1 ;; Scheduling description for IBM POWER5 processor.
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Sources: IBM Red Book and White Paper on POWER5
22 ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23 ;; Instructions that update more than one register get broken into two
24 ;; (split) or more internal ops. The chip can issue up to 5
25 ;; internal ops per cycle.
27 (define_automaton "power5iu,power5fpu,power5misc")
29 (define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
30 (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
31 (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
32 (define_cpu_unit "bpu_power5,cru_power5" "power5misc")
33 (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
36 (define_reservation "lsq_power5"
37 "(du1_power5,lsu1_power5)\
38 |(du2_power5,lsu2_power5)\
39 |(du3_power5,lsu2_power5)\
40 |(du4_power5,lsu1_power5)")
42 (define_reservation "iq_power5"
43 "(du1_power5|du2_power5|du3_power5|du4_power5),\
44 (iu1_power5|iu2_power5)")
46 (define_reservation "fpq_power5"
47 "(du1_power5|du2_power5|du3_power5|du4_power5),\
48 (fpu1_power5|fpu2_power5)")
50 ; Dispatch slots are allocated in order conforming to program order.
51 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
52 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
53 (absence_set "du3_power5" "du4_power5,du5_power5")
54 (absence_set "du4_power5" "du5_power5")
58 (define_insn_reservation "power5-load" 4 ; 3
59 (and (eq_attr "type" "load")
60 (eq_attr "sign_extend" "no")
61 (eq_attr "update" "no")
62 (eq_attr "cpu" "power5"))
65 (define_insn_reservation "power5-load-ext" 5
66 (and (eq_attr "type" "load")
67 (eq_attr "sign_extend" "yes")
68 (eq_attr "update" "no")
69 (eq_attr "cpu" "power5"))
70 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
72 (define_insn_reservation "power5-load-ext-update" 5
73 (and (eq_attr "type" "load")
74 (eq_attr "sign_extend" "yes")
75 (eq_attr "update" "yes")
76 (eq_attr "indexed" "no")
77 (eq_attr "cpu" "power5"))
78 "du1_power5+du2_power5+du3_power5+du4_power5,\
79 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
81 (define_insn_reservation "power5-load-ext-update-indexed" 5
82 (and (eq_attr "type" "load")
83 (eq_attr "sign_extend" "yes")
84 (eq_attr "update" "yes")
85 (eq_attr "indexed" "yes")
86 (eq_attr "cpu" "power5"))
87 "du1_power5+du2_power5+du3_power5+du4_power5,\
88 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
90 (define_insn_reservation "power5-load-update-indexed" 3
91 (and (eq_attr "type" "load")
92 (eq_attr "sign_extend" "no")
93 (eq_attr "update" "yes")
94 (eq_attr "indexed" "yes")
95 (eq_attr "cpu" "power5"))
96 "du1_power5+du2_power5+du3_power5+du4_power5,\
97 iu1_power5,lsu2_power5+iu2_power5")
99 (define_insn_reservation "power5-load-update" 4 ; 3
100 (and (eq_attr "type" "load")
101 (eq_attr "sign_extend" "no")
102 (eq_attr "update" "yes")
103 (eq_attr "indexed" "no")
104 (eq_attr "cpu" "power5"))
105 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
107 (define_insn_reservation "power5-fpload" 6 ; 5
108 (and (eq_attr "type" "fpload")
109 (eq_attr "update" "no")
110 (eq_attr "cpu" "power5"))
113 (define_insn_reservation "power5-fpload-update" 6 ; 5
114 (and (eq_attr "type" "fpload")
115 (eq_attr "update" "yes")
116 (eq_attr "cpu" "power5"))
117 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
119 (define_insn_reservation "power5-store" 12
120 (and (eq_attr "type" "store")
121 (eq_attr "update" "no")
122 (eq_attr "cpu" "power5"))
123 "((du1_power5,lsu1_power5)\
124 |(du2_power5,lsu2_power5)\
125 |(du3_power5,lsu2_power5)\
126 |(du4_power5,lsu1_power5)),\
127 (iu1_power5|iu2_power5)")
129 (define_insn_reservation "power5-store-update" 12
130 (and (eq_attr "type" "store")
131 (eq_attr "update" "yes")
132 (eq_attr "indexed" "no")
133 (eq_attr "cpu" "power5"))
134 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
136 (define_insn_reservation "power5-store-update-indexed" 12
137 (and (eq_attr "type" "store")
138 (eq_attr "update" "yes")
139 (eq_attr "indexed" "yes")
140 (eq_attr "cpu" "power5"))
141 "du1_power5+du2_power5+du3_power5+du4_power5,\
142 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
144 (define_insn_reservation "power5-fpstore" 12
145 (and (eq_attr "type" "fpstore")
146 (eq_attr "update" "no")
147 (eq_attr "cpu" "power5"))
148 "((du1_power5,lsu1_power5)\
149 |(du2_power5,lsu2_power5)\
150 |(du3_power5,lsu2_power5)\
151 |(du4_power5,lsu1_power5)),\
152 (fpu1_power5|fpu2_power5)")
154 (define_insn_reservation "power5-fpstore-update" 12
155 (and (eq_attr "type" "fpstore")
156 (eq_attr "update" "yes")
157 (eq_attr "cpu" "power5"))
158 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
160 (define_insn_reservation "power5-llsc" 11
161 (and (eq_attr "type" "load_l,store_c,sync")
162 (eq_attr "cpu" "power5"))
163 "du1_power5+du2_power5+du3_power5+du4_power5,\
167 ; Integer latency is 2 cycles
168 (define_insn_reservation "power5-integer" 2
169 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
170 var_shift_rotate,cntlz,exts,isel,popcnt")
171 (eq_attr "cpu" "power5"))
174 (define_insn_reservation "power5-two" 2
175 (and (eq_attr "type" "two")
176 (eq_attr "cpu" "power5"))
177 "((du1_power5+du2_power5)\
178 |(du2_power5+du3_power5)\
179 |(du3_power5+du4_power5)\
180 |(du4_power5+du1_power5)),\
181 ((iu1_power5,nothing,iu2_power5)\
182 |(iu2_power5,nothing,iu2_power5)\
183 |(iu2_power5,nothing,iu1_power5)\
184 |(iu1_power5,nothing,iu1_power5))")
186 (define_insn_reservation "power5-three" 2
187 (and (eq_attr "type" "three")
188 (eq_attr "cpu" "power5"))
189 "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
190 |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
191 ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
192 |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
193 |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
194 |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
196 (define_insn_reservation "power5-insert" 4
197 (and (eq_attr "type" "insert_word")
198 (eq_attr "cpu" "power5"))
199 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
201 (define_insn_reservation "power5-cmp" 3
202 (and (eq_attr "type" "cmp,fast_compare")
203 (eq_attr "cpu" "power5"))
206 (define_insn_reservation "power5-compare" 2
207 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
208 (eq_attr "cpu" "power5"))
209 "du1_power5+du2_power5,iu1_power5,iu2_power5")
211 (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
213 (define_insn_reservation "power5-lmul-cmp" 7
214 (and (eq_attr "type" "lmul_compare")
215 (eq_attr "cpu" "power5"))
216 "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
218 (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
220 (define_insn_reservation "power5-imul-cmp" 5
221 (and (eq_attr "type" "imul_compare")
222 (eq_attr "cpu" "power5"))
223 "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
225 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
227 (define_insn_reservation "power5-lmul" 7
228 (and (eq_attr "type" "lmul")
229 (eq_attr "cpu" "power5"))
230 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
232 (define_insn_reservation "power5-imul" 5
233 (and (eq_attr "type" "imul")
234 (eq_attr "cpu" "power5"))
235 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
237 (define_insn_reservation "power5-imul3" 4
238 (and (eq_attr "type" "imul2,imul3")
239 (eq_attr "cpu" "power5"))
240 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
243 ; SPR move only executes in first IU.
244 ; Integer division only executes in second IU.
245 (define_insn_reservation "power5-idiv" 36
246 (and (eq_attr "type" "idiv")
247 (eq_attr "cpu" "power5"))
248 "du1_power5+du2_power5,iu2_power5*35")
250 (define_insn_reservation "power5-ldiv" 68
251 (and (eq_attr "type" "ldiv")
252 (eq_attr "cpu" "power5"))
253 "du1_power5+du2_power5,iu2_power5*67")
256 (define_insn_reservation "power5-mtjmpr" 3
257 (and (eq_attr "type" "mtjmpr,mfjmpr")
258 (eq_attr "cpu" "power5"))
259 "du1_power5,bpu_power5")
262 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
263 ; grabbing previous dispatch slots once this is assigned.
264 (define_insn_reservation "power5-branch" 2
265 (and (eq_attr "type" "jmpreg,branch")
266 (eq_attr "cpu" "power5"))
268 |du4_power5+du5_power5\
269 |du3_power5+du4_power5+du5_power5\
270 |du2_power5+du3_power5+du4_power5+du5_power5\
271 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
274 ; Condition Register logical ops are split if non-destructive (RT != RB)
275 (define_insn_reservation "power5-crlogical" 2
276 (and (eq_attr "type" "cr_logical")
277 (eq_attr "cpu" "power5"))
278 "du1_power5,cru_power5")
280 (define_insn_reservation "power5-delayedcr" 4
281 (and (eq_attr "type" "delayed_cr")
282 (eq_attr "cpu" "power5"))
283 "du1_power5+du2_power5,cru_power5,cru_power5")
285 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
286 (define_insn_reservation "power5-mfcr" 6
287 (and (eq_attr "type" "mfcr")
288 (eq_attr "cpu" "power5"))
289 "du1_power5+du2_power5+du3_power5+du4_power5,\
290 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
291 cru_power5,cru_power5,cru_power5")
294 (define_insn_reservation "power5-mfcrf" 3
295 (and (eq_attr "type" "mfcrf")
296 (eq_attr "cpu" "power5"))
297 "du1_power5,cru_power5")
300 (define_insn_reservation "power5-mtcr" 4
301 (and (eq_attr "type" "mtcr")
302 (eq_attr "cpu" "power5"))
303 "du1_power5,iu1_power5")
305 ; Basic FP latency is 6 cycles
306 (define_insn_reservation "power5-fp" 6
307 (and (eq_attr "type" "fp,dmul")
308 (eq_attr "cpu" "power5"))
311 (define_insn_reservation "power5-fpcompare" 5
312 (and (eq_attr "type" "fpcompare")
313 (eq_attr "cpu" "power5"))
316 (define_insn_reservation "power5-sdiv" 33
317 (and (eq_attr "type" "sdiv,ddiv")
318 (eq_attr "cpu" "power5"))
319 "(du1_power5|du2_power5|du3_power5|du4_power5),\
320 (fpu1_power5*28|fpu2_power5*28)")
322 (define_insn_reservation "power5-sqrt" 40
323 (and (eq_attr "type" "ssqrt,dsqrt")
324 (eq_attr "cpu" "power5"))
325 "(du1_power5|du2_power5|du3_power5|du4_power5),\
326 (fpu1_power5*35|fpu2_power5*35)")
328 (define_insn_reservation "power5-isync" 2
329 (and (eq_attr "type" "isync")
330 (eq_attr "cpu" "power5"))
331 "du1_power5+du2_power5+du3_power5+du4_power5,\