1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Sources: IBM Red Book and White Paper on POWER4
22 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23 ;; Instructions that update more than one register get broken into two
24 ;; (split) or more internal ops. The chip can issue up to 5
25 ;; internal ops per cycle.
27 (define_automaton "power4iu,power4fpu,power4vec,power4misc")
29 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
30 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
31 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
32 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
33 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
34 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
37 (define_reservation "lsq_power4"
38 "(du1_power4,lsu1_power4)\
39 |(du2_power4,lsu2_power4)\
40 |(du3_power4,lsu2_power4)\
41 |(du4_power4,lsu1_power4)")
43 (define_reservation "lsuq_power4"
44 "((du1_power4+du2_power4,lsu1_power4)\
45 |(du2_power4+du3_power4,lsu2_power4)\
46 |(du3_power4+du4_power4,lsu2_power4))\
47 +(nothing,iu2_power4|nothing,iu1_power4)")
49 (define_reservation "iq_power4"
50 "(du1_power4|du2_power4|du3_power4|du4_power4),\
51 (iu1_power4|iu2_power4)")
53 (define_reservation "fpq_power4"
54 "(du1_power4|du2_power4|du3_power4|du4_power4),\
55 (fpu1_power4|fpu2_power4)")
57 (define_reservation "vq_power4"
58 "(du1_power4,vec_power4)\
59 |(du2_power4,vec_power4)\
60 |(du3_power4,vec_power4)\
61 |(du4_power4,vec_power4)")
63 (define_reservation "vpq_power4"
64 "(du1_power4,vecperm_power4)\
65 |(du2_power4,vecperm_power4)\
66 |(du3_power4,vecperm_power4)\
67 |(du4_power4,vecperm_power4)")
70 ; Dispatch slots are allocated in order conforming to program order.
71 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
72 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
73 (absence_set "du3_power4" "du4_power4,du5_power4")
74 (absence_set "du4_power4" "du5_power4")
78 (define_insn_reservation "power4-load" 4 ; 3
79 (and (eq_attr "type" "load")
80 (eq_attr "sign_extend" "no")
81 (eq_attr "update" "no")
82 (eq_attr "cpu" "power4"))
85 (define_insn_reservation "power4-load-ext" 5
86 (and (eq_attr "type" "load")
87 (eq_attr "sign_extend" "yes")
88 (eq_attr "update" "no")
89 (eq_attr "cpu" "power4"))
90 "(du1_power4+du2_power4,lsu1_power4\
91 |du2_power4+du3_power4,lsu2_power4\
92 |du3_power4+du4_power4,lsu2_power4),\
94 (iu2_power4|iu1_power4)")
96 (define_insn_reservation "power4-load-ext-update" 5
97 (and (eq_attr "type" "load")
98 (eq_attr "sign_extend" "yes")
99 (eq_attr "update" "yes")
100 (eq_attr "indexed" "no")
101 (eq_attr "cpu" "power4"))
102 "du1_power4+du2_power4+du3_power4+du4_power4,\
103 lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
105 (define_insn_reservation "power4-load-ext-update-indexed" 5
106 (and (eq_attr "type" "load")
107 (eq_attr "sign_extend" "yes")
108 (eq_attr "update" "yes")
109 (eq_attr "indexed" "yes")
110 (eq_attr "cpu" "power4"))
111 "du1_power4+du2_power4+du3_power4+du4_power4,\
112 iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
114 (define_insn_reservation "power4-load-update-indexed" 3
115 (and (eq_attr "type" "load")
116 (eq_attr "sign_extend" "no")
117 (eq_attr "update" "yes")
118 (eq_attr "indexed" "yes")
119 (eq_attr "cpu" "power4"))
120 "du1_power4+du2_power4+du3_power4+du4_power4,\
121 iu1_power4,lsu2_power4+iu2_power4")
123 (define_insn_reservation "power4-load-update" 4 ; 3
124 (and (eq_attr "type" "load")
125 (eq_attr "sign_extend" "no")
126 (eq_attr "update" "yes")
127 (eq_attr "indexed" "no")
128 (eq_attr "cpu" "power4"))
131 (define_insn_reservation "power4-fpload" 6 ; 5
132 (and (eq_attr "type" "fpload")
133 (eq_attr "update" "no")
134 (eq_attr "cpu" "power4"))
137 (define_insn_reservation "power4-fpload-update" 6 ; 5
138 (and (eq_attr "type" "fpload")
139 (eq_attr "update" "yes")
140 (eq_attr "cpu" "power4"))
143 (define_insn_reservation "power4-vecload" 6 ; 5
144 (and (eq_attr "type" "vecload")
145 (eq_attr "cpu" "power4"))
148 (define_insn_reservation "power4-store" 12
149 (and (eq_attr "type" "store")
150 (eq_attr "update" "no")
151 (eq_attr "cpu" "power4"))
152 "((du1_power4,lsu1_power4)\
153 |(du2_power4,lsu2_power4)\
154 |(du3_power4,lsu2_power4)\
155 |(du4_power4,lsu1_power4)),\
156 (iu1_power4|iu2_power4)")
158 (define_insn_reservation "power4-store-update" 12
159 (and (eq_attr "type" "store")
160 (eq_attr "update" "yes")
161 (eq_attr "indexed" "no")
162 (eq_attr "cpu" "power4"))
163 "((du1_power4+du2_power4,lsu1_power4)\
164 |(du2_power4+du3_power4,lsu2_power4)\
165 |(du3_power4+du4_power4,lsu2_power4))+\
166 ((nothing,iu1_power4,iu2_power4)\
167 |(nothing,iu2_power4,iu2_power4)\
168 |(nothing,iu2_power4,iu1_power4))")
170 (define_insn_reservation "power4-store-update-indexed" 12
171 (and (eq_attr "type" "store")
172 (eq_attr "update" "yes")
173 (eq_attr "indexed" "yes")
174 (eq_attr "cpu" "power4"))
175 "du1_power4+du2_power4+du3_power4+du4_power4,\
176 iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
178 (define_insn_reservation "power4-fpstore" 12
179 (and (eq_attr "type" "fpstore")
180 (eq_attr "update" "no")
181 (eq_attr "cpu" "power4"))
182 "((du1_power4,lsu1_power4)\
183 |(du2_power4,lsu2_power4)\
184 |(du3_power4,lsu2_power4)\
185 |(du4_power4,lsu1_power4)),\
186 (fpu1_power4|fpu2_power4)")
188 (define_insn_reservation "power4-fpstore-update" 12
189 (and (eq_attr "type" "fpstore")
190 (eq_attr "update" "yes")
191 (eq_attr "cpu" "power4"))
192 "((du1_power4+du2_power4,lsu1_power4)\
193 |(du2_power4+du3_power4,lsu2_power4)\
194 |(du3_power4+du4_power4,lsu2_power4))\
195 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
197 (define_insn_reservation "power4-vecstore" 12
198 (and (eq_attr "type" "vecstore")
199 (eq_attr "cpu" "power4"))
200 "(du1_power4,lsu1_power4,vec_power4)\
201 |(du2_power4,lsu2_power4,vec_power4)\
202 |(du3_power4,lsu2_power4,vec_power4)\
203 |(du4_power4,lsu1_power4,vec_power4)")
205 (define_insn_reservation "power4-llsc" 11
206 (and (eq_attr "type" "load_l,store_c,sync")
207 (eq_attr "cpu" "power4"))
208 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
211 ; Integer latency is 2 cycles
212 (define_insn_reservation "power4-integer" 2
213 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
214 var_shift_rotate,cntlz,exts,isel")
215 (eq_attr "cpu" "power4"))
218 (define_insn_reservation "power4-two" 2
219 (and (eq_attr "type" "two")
220 (eq_attr "cpu" "power4"))
221 "((du1_power4+du2_power4)\
222 |(du2_power4+du3_power4)\
223 |(du3_power4+du4_power4)\
224 |(du4_power4+du1_power4)),\
225 ((iu1_power4,nothing,iu2_power4)\
226 |(iu2_power4,nothing,iu2_power4)\
227 |(iu2_power4,nothing,iu1_power4)\
228 |(iu1_power4,nothing,iu1_power4))")
230 (define_insn_reservation "power4-three" 2
231 (and (eq_attr "type" "three")
232 (eq_attr "cpu" "power4"))
233 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
234 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
235 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
236 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
237 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
238 |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
240 (define_insn_reservation "power4-insert" 4
241 (and (eq_attr "type" "insert_word")
242 (eq_attr "cpu" "power4"))
243 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
244 ((iu1_power4,nothing,iu2_power4)\
245 |(iu2_power4,nothing,iu2_power4)\
246 |(iu2_power4,nothing,iu1_power4))")
248 (define_insn_reservation "power4-cmp" 3
249 (and (eq_attr "type" "cmp,fast_compare")
250 (eq_attr "cpu" "power4"))
253 (define_insn_reservation "power4-compare" 2
254 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
255 (eq_attr "cpu" "power4"))
256 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
257 ((iu1_power4,iu2_power4)\
258 |(iu2_power4,iu2_power4)\
259 |(iu2_power4,iu1_power4))")
261 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
263 (define_insn_reservation "power4-lmul-cmp" 7
264 (and (eq_attr "type" "lmul_compare")
265 (eq_attr "cpu" "power4"))
266 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
267 ((iu1_power4*6,iu2_power4)\
268 |(iu2_power4*6,iu2_power4)\
269 |(iu2_power4*6,iu1_power4))")
271 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
273 (define_insn_reservation "power4-imul-cmp" 5
274 (and (eq_attr "type" "imul_compare")
275 (eq_attr "cpu" "power4"))
276 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
277 ((iu1_power4*4,iu2_power4)\
278 |(iu2_power4*4,iu2_power4)\
279 |(iu2_power4*4,iu1_power4))")
281 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
283 (define_insn_reservation "power4-lmul" 7
284 (and (eq_attr "type" "lmul")
285 (eq_attr "cpu" "power4"))
286 "(du1_power4|du2_power4|du3_power4|du4_power4),\
287 (iu1_power4*6|iu2_power4*6)")
289 (define_insn_reservation "power4-imul" 5
290 (and (eq_attr "type" "imul")
291 (eq_attr "cpu" "power4"))
292 "(du1_power4|du2_power4|du3_power4|du4_power4),\
293 (iu1_power4*4|iu2_power4*4)")
295 (define_insn_reservation "power4-imul3" 4
296 (and (eq_attr "type" "imul2,imul3")
297 (eq_attr "cpu" "power4"))
298 "(du1_power4|du2_power4|du3_power4|du4_power4),\
299 (iu1_power4*3|iu2_power4*3)")
302 ; SPR move only executes in first IU.
303 ; Integer division only executes in second IU.
304 (define_insn_reservation "power4-idiv" 36
305 (and (eq_attr "type" "idiv")
306 (eq_attr "cpu" "power4"))
307 "du1_power4+du2_power4,iu2_power4*35")
309 (define_insn_reservation "power4-ldiv" 68
310 (and (eq_attr "type" "ldiv")
311 (eq_attr "cpu" "power4"))
312 "du1_power4+du2_power4,iu2_power4*67")
315 (define_insn_reservation "power4-mtjmpr" 3
316 (and (eq_attr "type" "mtjmpr,mfjmpr")
317 (eq_attr "cpu" "power4"))
318 "du1_power4,bpu_power4")
321 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
322 ; grabbing previous dispatch slots once this is assigned.
323 (define_insn_reservation "power4-branch" 2
324 (and (eq_attr "type" "jmpreg,branch")
325 (eq_attr "cpu" "power4"))
327 |du4_power4+du5_power4\
328 |du3_power4+du4_power4+du5_power4\
329 |du2_power4+du3_power4+du4_power4+du5_power4\
330 |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
333 ; Condition Register logical ops are split if non-destructive (RT != RB)
334 (define_insn_reservation "power4-crlogical" 2
335 (and (eq_attr "type" "cr_logical")
336 (eq_attr "cpu" "power4"))
337 "du1_power4,cru_power4")
339 (define_insn_reservation "power4-delayedcr" 4
340 (and (eq_attr "type" "delayed_cr")
341 (eq_attr "cpu" "power4"))
342 "du1_power4+du2_power4,cru_power4,cru_power4")
344 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
345 (define_insn_reservation "power4-mfcr" 6
346 (and (eq_attr "type" "mfcr")
347 (eq_attr "cpu" "power4"))
348 "du1_power4+du2_power4+du3_power4+du4_power4,\
349 du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
350 cru_power4,cru_power4,cru_power4")
353 (define_insn_reservation "power4-mfcrf" 3
354 (and (eq_attr "type" "mfcrf")
355 (eq_attr "cpu" "power4"))
356 "du1_power4,cru_power4")
359 (define_insn_reservation "power4-mtcr" 4
360 (and (eq_attr "type" "mtcr")
361 (eq_attr "cpu" "power4"))
362 "du1_power4,iu1_power4")
364 ; Basic FP latency is 6 cycles
365 (define_insn_reservation "power4-fp" 6
366 (and (eq_attr "type" "fp,dmul")
367 (eq_attr "cpu" "power4"))
370 (define_insn_reservation "power4-fpcompare" 5
371 (and (eq_attr "type" "fpcompare")
372 (eq_attr "cpu" "power4"))
375 (define_insn_reservation "power4-sdiv" 33
376 (and (eq_attr "type" "sdiv,ddiv")
377 (eq_attr "cpu" "power4"))
378 "(du1_power4|du2_power4|du3_power4|du4_power4),\
379 (fpu1_power4*28|fpu2_power4*28)")
381 (define_insn_reservation "power4-sqrt" 40
382 (and (eq_attr "type" "ssqrt,dsqrt")
383 (eq_attr "cpu" "power4"))
384 "(du1_power4|du2_power4|du3_power4|du4_power4),\
385 (fpu1_power4*35|fpu2_power4*35)")
387 (define_insn_reservation "power4-isync" 2
388 (and (eq_attr "type" "isync")
389 (eq_attr "cpu" "power4"))
390 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
394 (define_insn_reservation "power4-vecsimple" 2
395 (and (eq_attr "type" "vecsimple")
396 (eq_attr "cpu" "power4"))
399 (define_insn_reservation "power4-veccomplex" 5
400 (and (eq_attr "type" "veccomplex")
401 (eq_attr "cpu" "power4"))
405 (define_insn_reservation "power4-veccmp" 8
406 (and (eq_attr "type" "veccmp")
407 (eq_attr "cpu" "power4"))
410 (define_insn_reservation "power4-vecfloat" 8
411 (and (eq_attr "type" "vecfloat")
412 (eq_attr "cpu" "power4"))
415 (define_insn_reservation "power4-vecperm" 2
416 (and (eq_attr "type" "vecperm")
417 (eq_attr "cpu" "power4"))
420 (define_bypass 4 "power4-vecload" "power4-vecperm")
422 (define_bypass 3 "power4-vecsimple" "power4-vecperm")
423 (define_bypass 6 "power4-veccomplex" "power4-vecperm")
424 (define_bypass 3 "power4-vecperm"
425 "power4-vecsimple,power4-veccomplex,power4-vecfloat")
426 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
428 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
429 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
431 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
432 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
433 (define_bypass 10 "power4-vecfloat" "power4-vecstore")