1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
34 #include "stor-layout.h"
40 #include "diagnostic-core.h"
46 #include "tm-constrs.h"
48 #include "target-def.h"
55 /* Usable when we have an amount to add or subtract, and want the
56 optimal size of the insn. */
57 #define ADDITIVE_SIZE_MODIFIER(size) \
58 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
60 #define LOSE_AND_RETURN(msgid, x) \
63 cris_operand_lossage (msgid, x); \
67 enum cris_retinsn_type
68 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
70 /* Per-function machine data. */
71 struct GTY(()) machine_function
73 int needs_return_address_on_stack
;
75 /* This is the number of registers we save in the prologue due to
79 enum cris_retinsn_type return_type
;
82 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
84 static char cris_output_insn_is_bound
= 0;
86 /* In code for output macros, this is how we know whether e.g. constant
87 goes in code or in a static initializer. */
88 static int in_code
= 0;
90 /* Fix for reg_overlap_mentioned_p. */
91 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
93 static enum machine_mode
cris_promote_function_mode (const_tree
, enum machine_mode
,
94 int *, const_tree
, int);
96 static unsigned int cris_atomic_align_for_mode (enum machine_mode
);
98 static void cris_print_base (rtx
, FILE *);
100 static void cris_print_index (rtx
, FILE *);
102 static void cris_output_addr_const (FILE *, rtx
);
104 static struct machine_function
* cris_init_machine_status (void);
106 static rtx
cris_struct_value_rtx (tree
, int);
108 static void cris_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
109 tree type
, int *, int);
111 static int cris_initial_frame_pointer_offset (void);
113 static void cris_operand_lossage (const char *, rtx
);
115 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
117 static void cris_print_operand (FILE *, rtx
, int);
119 static void cris_print_operand_address (FILE *, rtx
);
121 static bool cris_print_operand_punct_valid_p (unsigned char code
);
123 static bool cris_output_addr_const_extra (FILE *, rtx
);
125 static void cris_conditional_register_usage (void);
127 static void cris_asm_output_mi_thunk
128 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
130 static void cris_file_start (void);
131 static void cris_init_libfuncs (void);
133 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
135 static int cris_register_move_cost (enum machine_mode
, reg_class_t
, reg_class_t
);
136 static int cris_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
137 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
138 static int cris_address_cost (rtx
, enum machine_mode
, addr_space_t
, bool);
139 static bool cris_pass_by_reference (cumulative_args_t
, enum machine_mode
,
141 static int cris_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
143 static rtx
cris_function_arg (cumulative_args_t
, enum machine_mode
,
145 static rtx
cris_function_incoming_arg (cumulative_args_t
,
146 enum machine_mode
, const_tree
, bool);
147 static void cris_function_arg_advance (cumulative_args_t
, enum machine_mode
,
149 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
151 static void cris_option_override (void);
153 static bool cris_frame_pointer_required (void);
155 static void cris_asm_trampoline_template (FILE *);
156 static void cris_trampoline_init (rtx
, tree
, rtx
);
158 static rtx
cris_function_value(const_tree
, const_tree
, bool);
159 static rtx
cris_libcall_value (enum machine_mode
, const_rtx
);
160 static bool cris_function_value_regno_p (const unsigned int);
161 static void cris_file_end (void);
163 /* This is the parsed result of the "-max-stack-stackframe=" option. If
164 it (still) is zero, then there was no such option given. */
165 int cris_max_stackframe
= 0;
167 /* This is the parsed result of the "-march=" option, if given. */
168 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
170 #undef TARGET_ASM_ALIGNED_HI_OP
171 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
172 #undef TARGET_ASM_ALIGNED_SI_OP
173 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
174 #undef TARGET_ASM_ALIGNED_DI_OP
175 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
177 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
178 available in ELF. These "normal" pseudos do not have any alignment
179 constraints or side-effects. */
180 #undef TARGET_ASM_UNALIGNED_HI_OP
181 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
183 #undef TARGET_ASM_UNALIGNED_SI_OP
184 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
186 #undef TARGET_ASM_UNALIGNED_DI_OP
187 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
189 #undef TARGET_PRINT_OPERAND
190 #define TARGET_PRINT_OPERAND cris_print_operand
191 #undef TARGET_PRINT_OPERAND_ADDRESS
192 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
193 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
194 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
195 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
196 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
198 #undef TARGET_CONDITIONAL_REGISTER_USAGE
199 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
201 #undef TARGET_ASM_OUTPUT_MI_THUNK
202 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
203 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
204 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
206 #undef TARGET_ASM_FILE_START
207 #define TARGET_ASM_FILE_START cris_file_start
208 #undef TARGET_ASM_FILE_END
209 #define TARGET_ASM_FILE_END cris_file_end
211 #undef TARGET_INIT_LIBFUNCS
212 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
214 #undef TARGET_LEGITIMATE_ADDRESS_P
215 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
217 #undef TARGET_PREFERRED_RELOAD_CLASS
218 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
220 #undef TARGET_REGISTER_MOVE_COST
221 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
222 #undef TARGET_MEMORY_MOVE_COST
223 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
224 #undef TARGET_RTX_COSTS
225 #define TARGET_RTX_COSTS cris_rtx_costs
226 #undef TARGET_ADDRESS_COST
227 #define TARGET_ADDRESS_COST cris_address_cost
229 #undef TARGET_PROMOTE_FUNCTION_MODE
230 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
232 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
233 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
235 #undef TARGET_STRUCT_VALUE_RTX
236 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
237 #undef TARGET_SETUP_INCOMING_VARARGS
238 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
239 #undef TARGET_PASS_BY_REFERENCE
240 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
241 #undef TARGET_ARG_PARTIAL_BYTES
242 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
243 #undef TARGET_FUNCTION_ARG
244 #define TARGET_FUNCTION_ARG cris_function_arg
245 #undef TARGET_FUNCTION_INCOMING_ARG
246 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
247 #undef TARGET_FUNCTION_ARG_ADVANCE
248 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
249 #undef TARGET_MD_ASM_CLOBBERS
250 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
251 #undef TARGET_FRAME_POINTER_REQUIRED
252 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
254 #undef TARGET_OPTION_OVERRIDE
255 #define TARGET_OPTION_OVERRIDE cris_option_override
257 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
258 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
259 #undef TARGET_TRAMPOLINE_INIT
260 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
262 #undef TARGET_FUNCTION_VALUE
263 #define TARGET_FUNCTION_VALUE cris_function_value
264 #undef TARGET_LIBCALL_VALUE
265 #define TARGET_LIBCALL_VALUE cris_libcall_value
266 #undef TARGET_FUNCTION_VALUE_REGNO_P
267 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
269 struct gcc_target targetm
= TARGET_INITIALIZER
;
271 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
274 cris_movem_load_rest_p (rtx op
, int offs
)
276 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
282 unsigned int regno
= 0;
284 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
285 other than (MEM reg). */
287 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
288 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
289 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
292 /* Check a possible post-inc indicator. */
293 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
295 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
296 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
302 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
303 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
304 || !CONST_INT_P (inc
)
305 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
315 regno
= reg_count
- 1;
318 elt
= XVECEXP (op
, 0, offs
);
319 src_addr
= XEXP (SET_SRC (elt
), 0);
321 if (GET_CODE (elt
) != SET
322 || !REG_P (SET_DEST (elt
))
323 || GET_MODE (SET_DEST (elt
)) != SImode
324 || REGNO (SET_DEST (elt
)) != regno
325 || !MEM_P (SET_SRC (elt
))
326 || GET_MODE (SET_SRC (elt
)) != SImode
327 || !memory_address_p (SImode
, src_addr
))
330 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
332 rtx elt
= XVECEXP (op
, 0, i
);
335 if (GET_CODE (elt
) != SET
336 || !REG_P (SET_DEST (elt
))
337 || GET_MODE (SET_DEST (elt
)) != SImode
338 || REGNO (SET_DEST (elt
)) != regno
339 || !MEM_P (SET_SRC (elt
))
340 || GET_MODE (SET_SRC (elt
)) != SImode
341 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
342 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
343 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
344 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
351 /* Worker function for predicate for the parallel contents in a movem
355 cris_store_multiple_op_p (rtx op
)
357 int reg_count
= XVECLEN (op
, 0);
368 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
369 other than (MEM reg) and (MEM (PLUS reg const)). */
373 elt
= XVECEXP (op
, 0, 0);
375 if (GET_CODE (elt
) != SET
)
378 dest
= SET_DEST (elt
);
380 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
383 dest_addr
= XEXP (dest
, 0);
385 /* Check a possible post-inc indicator. */
386 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
388 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
389 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
395 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
396 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
397 || !CONST_INT_P (inc
)
398 /* Support increment by number of registers, and by the offset
399 of the destination, if it has the form (MEM (PLUS reg
401 || !((REG_P (dest_addr
)
402 && REGNO (dest_addr
) == REGNO (reg
)
403 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
404 || (GET_CODE (dest_addr
) == PLUS
405 && REG_P (XEXP (dest_addr
, 0))
406 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
407 && CONST_INT_P (XEXP (dest_addr
, 1))
408 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
419 regno
= reg_count
- 1;
422 if (GET_CODE (elt
) != SET
423 || !REG_P (SET_SRC (elt
))
424 || GET_MODE (SET_SRC (elt
)) != SImode
425 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
426 || !MEM_P (SET_DEST (elt
))
427 || GET_MODE (SET_DEST (elt
)) != SImode
)
430 if (REG_P (dest_addr
))
432 dest_base
= dest_addr
;
435 else if (GET_CODE (dest_addr
) == PLUS
436 && REG_P (XEXP (dest_addr
, 0))
437 && CONST_INT_P (XEXP (dest_addr
, 1)))
439 dest_base
= XEXP (dest_addr
, 0);
440 offset
= INTVAL (XEXP (dest_addr
, 1));
445 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
447 rtx elt
= XVECEXP (op
, 0, i
);
450 if (GET_CODE (elt
) != SET
451 || !REG_P (SET_SRC (elt
))
452 || GET_MODE (SET_SRC (elt
)) != SImode
453 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
454 || !MEM_P (SET_DEST (elt
))
455 || GET_MODE (SET_DEST (elt
)) != SImode
456 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
457 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
458 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
459 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
466 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
469 cris_conditional_register_usage (void)
471 /* FIXME: This isn't nice. We should be able to use that register for
472 something else if the PIC table isn't needed. */
474 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
475 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
477 /* Allow use of ACR (PC in pre-V32) and tweak order. */
480 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
483 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
486 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
488 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
491 if (TARGET_HAS_MUL_INSNS
)
492 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
494 /* On early versions, we must use the 16-bit condition-code register,
495 which has another name. */
496 if (cris_cpu_version
< 8)
497 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
500 /* Return crtl->uses_pic_offset_table. For use in cris.md,
501 since some generated files do not include function.h. */
504 cris_cfun_uses_pic_table (void)
506 return crtl
->uses_pic_offset_table
;
509 /* Given an rtx, return the text string corresponding to the CODE of X.
510 Intended for use in the assembly language output section of a
516 cris_output_insn_is_bound
= 0;
517 switch (GET_CODE (x
))
528 /* This function is for retrieving a part of an instruction name for
529 an operator, for immediate output. If that ever happens for
530 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
532 internal_error ("MULT case in cris_op_str");
568 /* Used to control the sign/zero-extend character for the 'E' modifier.
570 cris_output_insn_is_bound
= 1;
575 return "Unknown operator";
580 /* Emit an error message when we're in an asm, and a fatal error for
581 "normal" insns. Formatted output isn't easily implemented, since we
582 use output_operand_lossage to output the actual message and handle the
583 categorization of the error. */
586 cris_operand_lossage (const char *msgid
, rtx op
)
589 output_operand_lossage ("%s", msgid
);
592 /* Print an index part of an address to file. */
595 cris_print_index (rtx index
, FILE *file
)
597 /* Make the index "additive" unless we'll output a negative number, in
598 which case the sign character is free (as in free beer). */
599 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
603 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
604 else if (CONSTANT_P (index
))
605 cris_output_addr_const (file
, index
);
606 else if (GET_CODE (index
) == MULT
)
608 fprintf (file
, "$%s.",
609 reg_names
[REGNO (XEXP (index
, 0))]);
611 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
613 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
615 rtx inner
= XEXP (index
, 0);
616 rtx inner_inner
= XEXP (inner
, 0);
618 if (GET_CODE (inner_inner
) == POST_INC
)
620 fprintf (file
, "[$%s+].",
621 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
622 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
626 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
628 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
631 else if (MEM_P (index
))
633 rtx inner
= XEXP (index
, 0);
634 if (GET_CODE (inner
) == POST_INC
)
635 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
637 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
640 cris_operand_lossage ("unexpected index-type in cris_print_index",
644 /* Print a base rtx of an address to file. */
647 cris_print_base (rtx base
, FILE *file
)
650 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
651 else if (GET_CODE (base
) == POST_INC
)
653 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
654 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
657 cris_operand_lossage ("unexpected base-type in cris_print_base",
661 /* Usable as a guard in expressions. */
664 cris_fatal (char *arg
)
666 internal_error (arg
);
668 /* We'll never get here; this is just to appease compilers. */
672 /* Return nonzero if REGNO is an ordinary register that *needs* to be
673 saved together with other registers, possibly by a MOVEM instruction,
674 or is saved for target-independent reasons. There may be
675 target-dependent reasons to save the register anyway; this is just a
676 wrapper for a complicated conditional. */
679 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
682 (((df_regs_ever_live_p (regno
)
683 && !call_used_regs
[regno
])
684 || (regno
== PIC_OFFSET_TABLE_REGNUM
686 /* It is saved anyway, if there would be a gap. */
688 && df_regs_ever_live_p (regno
+ 1)
689 && !call_used_regs
[regno
+ 1]))))
690 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
691 && regno
!= CRIS_SRP_REGNUM
)
692 || (crtl
->calls_eh_return
693 && (regno
== EH_RETURN_DATA_REGNO (0)
694 || regno
== EH_RETURN_DATA_REGNO (1)
695 || regno
== EH_RETURN_DATA_REGNO (2)
696 || regno
== EH_RETURN_DATA_REGNO (3)));
699 /* The PRINT_OPERAND worker. */
702 cris_print_operand (FILE *file
, rtx x
, int code
)
706 /* Size-strings corresponding to MULT expressions. */
707 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
709 /* New code entries should just be added to the switch below. If
710 handling is finished, just return. If handling was just a
711 modification of the operand, the modified operand should be put in
712 "operand", and then do a break to let default handling
713 (zero-modifier) output the operand. */
718 /* Print the unsigned supplied integer as if it were signed
719 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
720 if (!satisfies_constraint_O (x
))
721 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
722 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
723 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
727 /* Print assembler code for operator. */
728 fprintf (file
, "%s", cris_op_str (operand
));
733 /* A movem modifier working on a parallel; output the register
737 if (GET_CODE (x
) != PARALLEL
)
738 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
740 /* The second item can be (set reg (plus reg const)) to denote a
743 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
745 : XVECLEN (x
, 0) - 1);
747 fprintf (file
, "$%s", reg_names
[regno
]);
753 /* A similar movem modifier; output the memory operand. */
756 if (GET_CODE (x
) != PARALLEL
)
757 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
759 /* The lowest mem operand is in the first item, but perhaps it
760 needs to be output as postincremented. */
761 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
762 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
763 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
765 /* The second item can be a (set reg (plus reg const)) to denote
767 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
769 /* It's a post-increment, if the address is a naked (reg). */
771 addr
= gen_rtx_POST_INC (SImode
, addr
);
774 /* Otherwise, it's a side-effect; RN=RN+M. */
775 fprintf (file
, "[$%s=$%s%s%d]",
776 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
777 reg_names
[REGNO (XEXP (addr
, 0))],
778 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
779 (int) INTVAL (XEXP (addr
, 1)));
783 output_address (addr
);
788 /* Adjust a power of two to its log2. */
789 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
790 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
791 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
795 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
796 respectively. This modifier also terminates the inhibiting
797 effects of the 'x' modifier. */
798 cris_output_insn_is_bound
= 0;
799 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
803 if (INTVAL (x
) <= 255)
805 else if (INTVAL (x
) <= 65535)
815 /* For a non-integer, print the size of the operand. */
816 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
817 ? 'd' : GET_MODE (x
) == HImode
? 'w'
818 : GET_MODE (x
) == QImode
? 'b'
819 /* If none of the above, emit an erroneous size letter. */
825 /* Const_int: print b for -127 <= x <= 255,
826 w for -32768 <= x <= 65535, else die. */
828 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
829 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
830 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
834 /* If this is a GOT-symbol, print the size-letter corresponding to
835 -fpic/-fPIC. For everything else, print "d". */
837 && GET_CODE (x
) == CONST
838 && GET_CODE (XEXP (x
, 0)) == UNSPEC
839 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
844 /* Output a 'nop' if there's nothing for the delay slot.
845 This method stolen from the sparc files. */
846 if (dbr_sequence_length () == 0)
847 fputs ("\n\tnop", file
);
851 /* Output directive for alignment padded with "nop" insns.
852 Optimizing for size, it's plain 4-byte alignment, otherwise we
853 align the section to a cache-line (32 bytes) and skip at max 2
854 bytes, i.e. we skip if it's the last insn on a cache-line. The
855 latter is faster by a small amount (for two test-programs 99.6%
856 and 99.9%) and larger by a small amount (ditto 100.1% and
857 100.2%). This is supposed to be the simplest yet performance-
858 wise least intrusive way to make sure the immediately following
859 (supposed) muls/mulu insn isn't located at the end of a
863 ? ".p2alignw 2,0x050f\n\t"
864 : ".p2alignw 5,0x050f,2\n\t", file
);
868 /* The PIC register. */
870 internal_error ("invalid use of ':' modifier");
871 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
875 /* Print high (most significant) part of something. */
876 switch (GET_CODE (operand
))
879 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
880 value is kept here, and so may be other than 0 or -1. */
881 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
882 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
886 /* High part of a long long constant. */
887 if (GET_MODE (operand
) == VOIDmode
)
889 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
893 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
896 /* Print reg + 1. Check that there's not an attempt to print
897 high-parts of registers like stack-pointer or higher, except
898 for SRP (where the "high part" is MOF). */
899 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
900 && (REGNO (operand
) != CRIS_SRP_REGNUM
901 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
902 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
903 LOSE_AND_RETURN ("bad register", operand
);
904 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
908 /* Adjust memory address to high part. */
910 rtx adj_mem
= operand
;
912 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
914 /* Adjust so we can use two SImode in DImode.
915 Calling adj_offsettable_operand will make sure it is an
916 offsettable address. Don't do this for a postincrement
917 though; it should remain as it was. */
918 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
920 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
922 output_address (XEXP (adj_mem
, 0));
927 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
931 /* Strip the MEM expression. */
932 operand
= XEXP (operand
, 0);
936 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
937 iterators and attributes in cris.md to avoid the need for %x
938 and %E (and %e) and state passed between those modifiers. */
939 cris_output_insn_is_bound
= 0;
942 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
943 cris_output_insn_is_bound is nonzero. */
944 if (GET_CODE (operand
) != SIGN_EXTEND
945 && GET_CODE (operand
) != ZERO_EXTEND
946 && !CONST_INT_P (operand
))
947 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
949 if (cris_output_insn_is_bound
)
951 cris_output_insn_is_bound
= 0;
955 putc (GET_CODE (operand
) == SIGN_EXTEND
956 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
961 /* Print the size letter of the inner element. We can do it by
962 calling ourselves with the 's' modifier. */
963 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
964 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
965 cris_print_operand (file
, XEXP (operand
, 0), 's');
969 /* Print the least significant part of operand. */
970 if (GET_CODE (operand
) == CONST_DOUBLE
)
972 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
975 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
977 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
978 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
981 /* Otherwise the least significant part equals the normal part,
982 so handle it normally. */
986 /* When emitting an add for the high part of a DImode constant, we
987 want to use addq for 0 and adds.w for -1. */
988 if (!CONST_INT_P (operand
))
989 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
990 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
994 /* For const_int operands, print the additive mnemonic and the
995 modified operand (byte-sized operands don't save anything):
996 N=MIN_INT..-65536: add.d N
997 -65535..-64: subu.w -N
1001 65536..MAX_INT: add.d N.
1002 (Emitted mnemonics are capitalized to simplify testing.)
1003 For anything else (N.B: only register is valid), print "add.d". */
1004 if (REG_P (operand
))
1006 fprintf (file
, "Add.d ");
1008 /* Deal with printing the operand by dropping through to the
1015 gcc_assert (CONST_INT_P (operand
));
1017 val
= INTVAL (operand
);
1018 if (!IN_RANGE (val
, -65535, 65535))
1019 fprintf (file
, "Add.d %d", val
);
1020 else if (val
<= -64)
1021 fprintf (file
, "Subu.w %d", -val
);
1023 fprintf (file
, "Subq %d", -val
);
1025 fprintf (file
, "Addq %d", val
);
1026 else if (val
<= 65535)
1027 fprintf (file
, "Addu.w %d", val
);
1033 /* If the operand is an integer -31..31, print "q" else ".d". */
1034 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1035 fprintf (file
, "q");
1037 fprintf (file
, ".d");
1041 /* If this is a GOT symbol, force it to be emitted as :GOT and
1042 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1043 Avoid making this too much of a special case. */
1044 if (flag_pic
== 1 && CONSTANT_P (operand
))
1046 int flag_pic_save
= flag_pic
;
1049 cris_output_addr_const (file
, operand
);
1050 flag_pic
= flag_pic_save
;
1056 /* When emitting an sub for the high part of a DImode constant, we
1057 want to use subq for 0 and subs.w for -1. */
1058 if (!CONST_INT_P (operand
))
1059 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1060 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1064 /* Print the operand as the index-part of an address.
1065 Easiest way out is to use cris_print_index. */
1066 cris_print_index (operand
, file
);
1070 /* Print the size letter for an operand to a MULT, which must be a
1071 const_int with a suitable value. */
1072 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1073 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1074 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1078 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1080 && GET_CODE (operand
) == CONST
1081 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1082 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1083 fprintf (file
, "u.w");
1085 fprintf (file
, ".d");
1089 /* No code, print as usual. */
1093 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1096 /* Print an operand as without a modifier letter. */
1097 switch (GET_CODE (operand
))
1100 if (REGNO (operand
) > 15
1101 && REGNO (operand
) != CRIS_MOF_REGNUM
1102 && REGNO (operand
) != CRIS_SRP_REGNUM
1103 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1104 internal_error ("internal error: bad register: %d", REGNO (operand
));
1105 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1109 output_address (XEXP (operand
, 0));
1113 if (GET_MODE (operand
) == VOIDmode
)
1114 /* A long long constant. */
1115 output_addr_const (file
, operand
);
1118 /* Only single precision is allowed as plain operands the
1119 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1124 /* FIXME: Perhaps check overflow of the "single". */
1125 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1126 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1128 fprintf (file
, "0x%lx", l
);
1135 cris_output_addr_const (file
, operand
);
1141 /* For a (MULT (reg X) const_int) we output "rX.S". */
1142 int i
= CONST_INT_P (XEXP (operand
, 1))
1143 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1144 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1145 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1148 || (!CONST_INT_P (XEXP (operand
, 0))
1149 && !CONST_INT_P (XEXP (operand
, 1))))
1150 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1152 cris_print_base (reg
, file
);
1153 fprintf (file
, ".%c",
1154 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1156 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1162 /* No need to handle all strange variants, let output_addr_const
1164 if (CONSTANT_P (operand
))
1166 cris_output_addr_const (file
, operand
);
1170 LOSE_AND_RETURN ("unexpected operand", x
);
1175 cris_print_operand_punct_valid_p (unsigned char code
)
1177 return (code
== '#' || code
== '!' || code
== ':');
1180 /* The PRINT_OPERAND_ADDRESS worker. */
1183 cris_print_operand_address (FILE *file
, rtx x
)
1185 /* All these were inside MEM:s so output indirection characters. */
1188 if (CONSTANT_ADDRESS_P (x
))
1189 cris_output_addr_const (file
, x
);
1190 else if (cris_base_or_autoincr_p (x
, true))
1191 cris_print_base (x
, file
);
1192 else if (GET_CODE (x
) == PLUS
)
1198 if (cris_base_p (x1
, true))
1200 cris_print_base (x1
, file
);
1201 cris_print_index (x2
, file
);
1203 else if (cris_base_p (x2
, true))
1205 cris_print_base (x2
, file
);
1206 cris_print_index (x1
, file
);
1209 LOSE_AND_RETURN ("unrecognized address", x
);
1213 /* A DIP. Output more indirection characters. */
1215 cris_print_base (XEXP (x
, 0), file
);
1219 LOSE_AND_RETURN ("unrecognized address", x
);
1224 /* The RETURN_ADDR_RTX worker.
1225 We mark that the return address is used, either by EH or
1226 __builtin_return_address, for use by the function prologue and
1227 epilogue. FIXME: This isn't optimal; we just use the mark in the
1228 prologue and epilogue to say that the return address is to be stored
1229 in the stack frame. We could return SRP for leaf-functions and use the
1230 initial-value machinery. */
1233 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1235 cfun
->machine
->needs_return_address_on_stack
= 1;
1237 /* The return-address is stored just above the saved frame-pointer (if
1238 present). Apparently we can't eliminate from the frame-pointer in
1239 that direction, so use the incoming args (maybe pretended) pointer. */
1241 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1245 /* Accessor used in cris.md:return because cfun->machine isn't available
1249 cris_return_address_on_stack (void)
1251 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1252 || cfun
->machine
->needs_return_address_on_stack
;
1255 /* Accessor used in cris.md:return because cfun->machine isn't available
1259 cris_return_address_on_stack_for_return (void)
1261 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1262 : cris_return_address_on_stack ();
1265 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1266 handles FP -> SP elimination offset. */
1269 cris_initial_frame_pointer_offset (void)
1273 /* Initial offset is 0 if we don't have a frame pointer. */
1275 bool got_really_used
= false;
1277 if (crtl
->uses_pic_offset_table
)
1279 push_topmost_sequence ();
1281 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1283 pop_topmost_sequence ();
1286 /* And 4 for each register pushed. */
1287 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1288 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1291 /* And then, last, we add the locals allocated. */
1292 offs
+= get_frame_size ();
1294 /* And more; the accumulated args size. */
1295 offs
+= crtl
->outgoing_args_size
;
1297 /* Then round it off, in case we use aligned stack. */
1298 if (TARGET_STACK_ALIGN
)
1299 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1304 /* The INITIAL_ELIMINATION_OFFSET worker.
1305 Calculate the difference between imaginary registers such as frame
1306 pointer and the stack pointer. Used to eliminate the frame pointer
1307 and imaginary arg pointer. */
1310 cris_initial_elimination_offset (int fromreg
, int toreg
)
1313 = cris_initial_frame_pointer_offset ();
1315 /* We should be able to use regs_ever_live and related prologue
1316 information here, or alpha should not as well. */
1317 bool return_address_on_stack
= cris_return_address_on_stack ();
1319 /* Here we act as if the frame-pointer were needed. */
1320 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1322 if (fromreg
== ARG_POINTER_REGNUM
1323 && toreg
== FRAME_POINTER_REGNUM
)
1324 return ap_fp_offset
;
1326 /* Between the frame pointer and the stack are only "normal" stack
1327 variables and saved registers. */
1328 if (fromreg
== FRAME_POINTER_REGNUM
1329 && toreg
== STACK_POINTER_REGNUM
)
1330 return fp_sp_offset
;
1332 /* We need to balance out the frame pointer here. */
1333 if (fromreg
== ARG_POINTER_REGNUM
1334 && toreg
== STACK_POINTER_REGNUM
)
1335 return ap_fp_offset
+ fp_sp_offset
- 4;
1340 /* Nonzero if X is a hard reg that can be used as an index. */
1342 reg_ok_for_base_p (const_rtx x
, bool strict
)
1344 return ((! strict
&& ! HARD_REGISTER_P (x
))
1345 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1348 /* Nonzero if X is a hard reg that can be used as an index. */
1350 reg_ok_for_index_p (const_rtx x
, bool strict
)
1352 return reg_ok_for_base_p (x
, strict
);
1355 /* No symbol can be used as an index (or more correct, as a base) together
1356 with a register with PIC; the PIC register must be there. */
1359 cris_constant_index_p (const_rtx x
)
1361 return (CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1364 /* True if X is a valid base register. */
1367 cris_base_p (const_rtx x
, bool strict
)
1369 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1372 /* True if X is a valid index register. */
1375 cris_index_p (const_rtx x
, bool strict
)
1377 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1380 /* True if X is a valid base register with or without autoincrement. */
1383 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1385 return (cris_base_p (x
, strict
)
1386 || (GET_CODE (x
) == POST_INC
1387 && cris_base_p (XEXP (x
, 0), strict
)
1388 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1391 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1394 cris_bdap_index_p (const_rtx x
, bool strict
)
1397 && GET_MODE (x
) == SImode
1398 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1399 || (GET_CODE (x
) == SIGN_EXTEND
1400 && MEM_P (XEXP (x
, 0))
1401 && (GET_MODE (XEXP (x
, 0)) == HImode
1402 || GET_MODE (XEXP (x
, 0)) == QImode
)
1403 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1406 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1409 cris_biap_index_p (const_rtx x
, bool strict
)
1411 return (cris_index_p (x
, strict
)
1412 || (GET_CODE (x
) == MULT
1413 && cris_index_p (XEXP (x
, 0), strict
)
1414 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1417 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1419 A PIC operand looks like a normal symbol here. At output we dress it
1420 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1421 symbol) so we exclude all addressing modes where we can't replace a
1422 plain "symbol" with that. A global PIC symbol does not fit anywhere
1423 here (but is thankfully a general_operand in itself). A local PIC
1424 symbol is valid for the plain "symbol + offset" case. */
1427 cris_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1431 if (cris_base_or_autoincr_p (x
, strict
))
1433 else if (TARGET_V32
)
1434 /* Nothing else is valid then. */
1436 else if (cris_constant_index_p (x
))
1439 else if (GET_CODE (x
) == PLUS
)
1444 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1445 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1446 /* BDAP Rs[+], Rd. */
1447 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1448 && ((cris_base_p (x1
, strict
)
1449 && cris_bdap_index_p (x2
, strict
))
1450 || (cris_base_p (x2
, strict
)
1451 && cris_bdap_index_p (x1
, strict
))
1453 || (cris_base_p (x1
, strict
)
1454 && cris_biap_index_p (x2
, strict
))
1455 || (cris_base_p (x2
, strict
)
1456 && cris_biap_index_p (x1
, strict
)))))
1461 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1462 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1463 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1470 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1473 cris_reload_address_legitimized (rtx x
,
1474 enum machine_mode mode ATTRIBUTE_UNUSED
,
1475 int opnum ATTRIBUTE_UNUSED
,
1477 int ind_levels ATTRIBUTE_UNUSED
)
1479 enum reload_type type
= (enum reload_type
) itype
;
1483 if (GET_CODE (x
) != PLUS
)
1491 op1p
= &XEXP (x
, 1);
1496 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1498 rtx op00
= XEXP (op0
, 0);
1499 rtx op000
= XEXP (op00
, 0);
1500 rtx
*op000p
= &XEXP (op00
, 0);
1502 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1504 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1506 bool something_reloaded
= false;
1508 if (GET_CODE (op000
) == POST_INC
1509 && REG_P (XEXP (op000
, 0))
1510 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1511 /* No, this gets too complicated and is too rare to care
1512 about trying to improve on the general code Here.
1513 As the return-value is an all-or-nothing indicator, we
1514 punt on the other register too. */
1518 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1520 /* The address of the inner mem is a pseudo or wrong
1521 reg: reload that. */
1522 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1523 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1524 something_reloaded
= true;
1527 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1529 /* Base register is a pseudo or wrong reg: reload it. */
1530 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1531 GET_MODE (x
), VOIDmode
, 0, 0,
1533 something_reloaded
= true;
1536 gcc_assert (something_reloaded
);
1546 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1548 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1549 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1550 out a constant into the constant pool, we will trap this case and
1551 return something a bit more sane. FIXME: Check if this is a bug.
1552 Beware that we must not "override" classes that can be specified as
1553 constraint letters, or else asm operands using them will fail when
1554 they need to be reloaded. FIXME: Investigate whether that constitutes
1558 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1560 if (rclass
!= ACR_REGS
1561 && rclass
!= MOF_REGS
1562 && rclass
!= MOF_SRP_REGS
1563 && rclass
!= SRP_REGS
1564 && rclass
!= CC0_REGS
1565 && rclass
!= SPECIAL_REGS
)
1566 return GENERAL_REGS
;
1571 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1574 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1575 reg_class_t from
, reg_class_t to
)
1577 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1578 their move cost within that class is higher. How about 7? That's 3
1579 for a move to a GENERAL_REGS register, 3 for the move from the
1580 GENERAL_REGS register, and 1 for the increased register pressure.
1581 Also, it's higher than the memory move cost, as it should.
1582 We also do this for ALL_REGS, since we don't want that class to be
1583 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1584 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1585 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1586 used when a GENERAL_REGS should be used, even if there are call-saved
1587 GENERAL_REGS left to allocate. This is because the fall-back when
1588 the most preferred register class isn't available, isn't the next
1589 (or next good) wider register class, but the *most widest* register
1590 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1592 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1593 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1594 || from
== ALL_REGS
|| to
== ALL_REGS
)
1597 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1598 generally prefer GENERAL_REGS. */
1599 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1600 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1606 /* Worker function for TARGET_MEMORY_MOVE_COST.
1608 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1612 cris_memory_move_cost (enum machine_mode mode
,
1613 reg_class_t rclass ATTRIBUTE_UNUSED
,
1614 bool in ATTRIBUTE_UNUSED
)
1623 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1624 FIXME: this code is historical; its functionality should be
1625 refactored to look at insn attributes and moved to
1626 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1629 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1631 /* "Normal" means, for:
1636 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1637 register or (v32 and (...) is -32..-1), then CC does not change.
1638 CC_NO_OVERFLOW unless (...) is reg or mem.
1647 (set (reg1) (mem (bdap/biap)))
1648 (set (reg2) (bdap/biap))):
1649 CC is (reg1) and (mem (reg2))
1652 (set (mem (bdap/biap)) (reg1)) [or 0]
1653 (set (reg2) (bdap/biap))):
1656 (where reg and mem includes strict_low_parts variants thereof)
1658 For all others, assume CC is clobbered.
1659 Note that we do not have to care about setting CC_NO_OVERFLOW,
1660 since the overflow flag is set to 0 (i.e. right) for
1661 instructions where it does not have any sane sense, but where
1662 other flags have meanings. (This includes shifts; the carry is
1665 Note that there are other parallel constructs we could match,
1666 but we don't do that yet. */
1668 if (GET_CODE (exp
) == SET
)
1670 /* FIXME: Check when this happens. It looks like we should
1671 actually do a CC_STATUS_INIT here to be safe. */
1672 if (SET_DEST (exp
) == pc_rtx
)
1675 /* Record CC0 changes, so we do not have to output multiple
1677 if (SET_DEST (exp
) == cc0_rtx
)
1681 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1682 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1683 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1685 cc_status
.value1
= SET_SRC (exp
);
1687 /* Handle flags for the special btstq on one bit. */
1688 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1689 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1691 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1693 cc_status
.flags
= CC_INVERTED
;
1695 /* A one-bit btstq. */
1696 cc_status
.flags
= CC_Z_IN_NOT_N
;
1699 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1701 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1702 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1703 /* For some reason gcc will not canonicalize compare
1704 operations, reversing the sign by itself if
1705 operands are in wrong order. */
1706 /* (But NOT inverted; eq is still eq.) */
1707 cc_status
.flags
= CC_REVERSED
;
1709 /* This seems to be overlooked by gcc. FIXME: Check again.
1710 FIXME: Is it really safe? */
1712 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1713 XEXP (SET_SRC (exp
), 0),
1714 XEXP (SET_SRC (exp
), 1));
1718 else if (REG_P (SET_DEST (exp
))
1719 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1720 && REG_P (XEXP (SET_DEST (exp
), 0))))
1722 /* A register is set; normally CC is set to show that no
1723 test insn is needed. Catch the exceptions. */
1725 /* If not to cc0, then no "set"s in non-natural mode give
1727 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1728 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1730 /* ... except add:s and sub:s in DImode. */
1731 if (GET_MODE (SET_DEST (exp
)) == DImode
1732 && (GET_CODE (SET_SRC (exp
)) == PLUS
1733 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1736 cc_status
.value1
= SET_DEST (exp
);
1737 cc_status
.value2
= SET_SRC (exp
);
1739 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1741 cc_status
.value2
= 0;
1743 /* Add and sub may set V, which gets us
1744 unoptimizable results in "gt" and "le" condition
1746 cc_status
.flags
|= CC_NO_OVERFLOW
;
1751 else if (SET_SRC (exp
) == const0_rtx
1752 || (REG_P (SET_SRC (exp
))
1753 && (REGNO (SET_SRC (exp
))
1754 > CRIS_LAST_GENERAL_REGISTER
))
1756 && REG_P (SET_DEST (exp
))
1757 && satisfies_constraint_I (SET_SRC (exp
))))
1759 /* There's no CC0 change for this case. Just check
1761 if (cc_status
.value1
1762 && modified_in_p (cc_status
.value1
, insn
))
1763 cc_status
.value1
= 0;
1765 if (cc_status
.value2
1766 && modified_in_p (cc_status
.value2
, insn
))
1767 cc_status
.value2
= 0;
1774 cc_status
.value1
= SET_DEST (exp
);
1775 cc_status
.value2
= SET_SRC (exp
);
1777 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1779 cc_status
.value2
= 0;
1781 /* Some operations may set V, which gets us
1782 unoptimizable results in "gt" and "le" condition
1784 if (GET_CODE (SET_SRC (exp
)) == PLUS
1785 || GET_CODE (SET_SRC (exp
)) == MINUS
1786 || GET_CODE (SET_SRC (exp
)) == NEG
)
1787 cc_status
.flags
|= CC_NO_OVERFLOW
;
1789 /* For V32, nothing with a register destination sets
1790 C and V usefully. */
1792 cc_status
.flags
|= CC_NO_OVERFLOW
;
1797 else if (MEM_P (SET_DEST (exp
))
1798 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1799 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1801 /* When SET to MEM, then CC is not changed (except for
1803 if (cc_status
.value1
1804 && modified_in_p (cc_status
.value1
, insn
))
1805 cc_status
.value1
= 0;
1807 if (cc_status
.value2
1808 && modified_in_p (cc_status
.value2
, insn
))
1809 cc_status
.value2
= 0;
1814 else if (GET_CODE (exp
) == PARALLEL
)
1816 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1817 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1818 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1820 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1821 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1825 /* For "move.S [rx=ry+o],rz", say CC reflects
1826 value1=rz and value2=[rx] */
1827 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1829 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1830 XEXP (XVECEXP (exp
, 0, 1), 0));
1832 /* Huh? A side-effect cannot change the destination
1834 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1836 internal_error ("internal error: sideeffect-insn affecting main effect");
1838 /* For V32, moves to registers don't set C and V. */
1840 cc_status
.flags
|= CC_NO_OVERFLOW
;
1843 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1844 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1845 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1847 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1848 say flags are not changed, except for overlap. */
1849 if (cc_status
.value1
1850 && modified_in_p (cc_status
.value1
, insn
))
1851 cc_status
.value1
= 0;
1853 if (cc_status
.value2
1854 && modified_in_p (cc_status
.value2
, insn
))
1855 cc_status
.value2
= 0;
1862 /* If we got here, the case wasn't covered by the code above. */
1866 /* This function looks into the pattern to see how this insn affects
1869 Used when to eliminate test insns before a condition-code user,
1870 such as a "scc" insn or a conditional branch. This includes
1871 checking if the entities that cc was updated by, are changed by the
1874 Currently a jumble of the old peek-inside-the-insn and the newer
1875 check-cc-attribute methods. */
1878 cris_notice_update_cc (rtx exp
, rtx insn
)
1880 enum attr_cc attrval
= get_attr_cc (insn
);
1882 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1883 to still set CC_REVERSED as below, since that's required by some
1884 compare insn alternatives. (FIXME: GCC should do this virtual
1885 operand swap by itself.) A test-case that may otherwise fail is
1886 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1891 if (attrval
== CC_REV
)
1892 cc_status
.flags
= CC_REVERSED
;
1896 /* Slowly, we're converting to using attributes to control the setting
1897 of condition-code status. */
1901 /* Even if it is "none", a setting may clobber a previous
1902 cc-value, so check. */
1903 if (GET_CODE (exp
) == SET
)
1905 if (cc_status
.value1
1906 && modified_in_p (cc_status
.value1
, insn
))
1907 cc_status
.value1
= 0;
1909 if (cc_status
.value2
1910 && modified_in_p (cc_status
.value2
, insn
))
1911 cc_status
.value2
= 0;
1922 cris_normal_notice_update_cc (exp
, insn
);
1924 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1925 can change bge => bpl and blt => bmi by passing on to the cc0
1926 user that V should not be considered; bgt and ble are taken
1927 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1928 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1929 cc_status
.flags
|= CC_NO_OVERFLOW
;
1933 internal_error ("unknown cc_attr value");
1939 /* Return != 0 if the return sequence for the current function is short,
1940 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1941 registers must be saved, so return 0 then. */
1944 cris_simple_epilogue (void)
1947 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1948 bool got_really_used
= false;
1950 if (! reload_completed
1951 || frame_pointer_needed
1952 || get_frame_size () != 0
1953 || crtl
->args
.pretend_args_size
1955 || crtl
->outgoing_args_size
1956 || crtl
->calls_eh_return
1958 /* If we're not supposed to emit prologue and epilogue, we must
1959 not emit return-type instructions. */
1960 || !TARGET_PROLOGUE_EPILOGUE
)
1963 /* Can't return from stacked return address with v32. */
1964 if (TARGET_V32
&& cris_return_address_on_stack ())
1967 if (crtl
->uses_pic_offset_table
)
1969 push_topmost_sequence ();
1971 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
1972 pop_topmost_sequence ();
1975 /* No simple epilogue if there are saved registers. */
1976 for (regno
= 0; regno
< reglimit
; regno
++)
1977 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1983 /* Emit checking that MEM is aligned for an access in MODE, failing
1984 that, executing a "break 8" (or call to abort, if "break 8" is
1988 cris_emit_trap_for_misalignment (rtx mem
)
1990 rtx addr
, reg
, ok_label
, andop
, jmp
;
1991 int natural_alignment
;
1992 gcc_assert (MEM_P (mem
));
1994 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
1995 addr
= XEXP (mem
, 0);
1996 reg
= force_reg (Pmode
, addr
);
1997 ok_label
= gen_label_rtx ();
1999 /* This will yield a btstq without a separate register used, usually -
2000 with the exception for PRE hoisting the "and" but not the branch
2001 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2002 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2003 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2004 NULL_RTX
, Pmode
, 1, ok_label
);
2005 jmp
= get_last_insn ();
2006 gcc_assert (JUMP_P (jmp
));
2008 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2009 expand_builtin_trap ();
2010 emit_label (ok_label
);
2013 /* Expand a return insn (just one insn) marked as using SRP or stack
2014 slot depending on parameter ON_STACK. */
2017 cris_expand_return (bool on_stack
)
2019 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2020 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2021 GCC expect just (return) to do the right thing when optimizing, so
2022 we do that until they're fixed. Currently, all return insns in a
2023 function must be the same (not really a limiting factor) so we need
2024 to check that it doesn't change half-way through. */
2025 emit_jump_insn (ret_rtx
);
2027 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2028 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2030 cfun
->machine
->return_type
2031 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2034 /* Compute a (partial) cost for rtx X. Return true if the complete
2035 cost has been computed, and false if subexpressions should be
2036 scanned. In either case, *TOTAL contains the cost result. */
2039 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2046 HOST_WIDE_INT val
= INTVAL (x
);
2049 else if (val
< 32 && val
>= -32)
2051 /* Eight or 16 bits are a word and cycle more expensive. */
2052 else if (val
<= 32767 && val
>= -32768)
2054 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2055 another word. FIXME: This isn't linear to 16 bits. */
2071 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2074 /* Make 0.0 cheap, else test-insns will not be used. */
2079 /* If we have one arm of an ADDI, make sure it gets the cost of
2080 one insn, i.e. zero cost for this operand, and just the cost
2081 of the PLUS, as the insn is created by combine from a PLUS
2082 and an ASHIFT, and the MULT cost below would make the
2083 combined value be larger than the separate insns. The insn
2084 validity is checked elsewhere by combine.
2086 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2087 function should be rewritten. */
2088 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2094 /* Identify values that are no powers of two. Powers of 2 are
2095 taken care of already and those values should not be changed. */
2096 if (!CONST_INT_P (XEXP (x
, 1))
2097 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2099 /* If we have a multiply insn, then the cost is between
2100 1 and 2 "fast" instructions. */
2101 if (TARGET_HAS_MUL_INSNS
)
2103 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2107 /* Estimate as 4 + 4 * #ofbits. */
2108 *total
= COSTS_N_INSNS (132);
2117 if (!CONST_INT_P (XEXP (x
, 1))
2118 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2120 /* Estimate this as 4 + 8 * #of bits. */
2121 *total
= COSTS_N_INSNS (260);
2127 if (CONST_INT_P (XEXP (x
, 1))
2128 /* Two constants may actually happen before optimization. */
2129 && !CONST_INT_P (XEXP (x
, 0))
2130 && !satisfies_constraint_I (XEXP (x
, 1)))
2133 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2135 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2141 if (outer_code
!= COMPARE
)
2145 case ZERO_EXTEND
: case SIGN_EXTEND
:
2146 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2154 /* The ADDRESS_COST worker. */
2157 cris_address_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2158 addr_space_t as ATTRIBUTE_UNUSED
,
2159 bool speed ATTRIBUTE_UNUSED
)
2161 /* The metric to use for the cost-macros is unclear.
2162 The metric used here is (the number of cycles needed) / 2,
2163 where we consider equal a cycle for a word of code and a cycle to
2164 read memory. FIXME: Adding "+ 1" to all values would avoid
2165 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2166 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2167 Unfortunately(?) such a hack would expose other pessimizations,
2168 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2169 loop there, without apparent reason. */
2171 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2172 if (cris_base_or_autoincr_p (x
, false))
2175 /* An indirect mem must be a DIP. This means two bytes extra for code,
2176 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2180 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2181 an extra DIP prefix and 4 bytes of constant in most cases. */
2185 /* Handle BIAP and BDAP prefixes. */
2186 if (GET_CODE (x
) == PLUS
)
2188 rtx tem1
= XEXP (x
, 0);
2189 rtx tem2
= XEXP (x
, 1);
2191 /* Local extended canonicalization rule: the first operand must
2192 be REG, unless it's an operation (MULT). */
2193 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2194 tem1
= tem2
, tem2
= XEXP (x
, 0);
2196 /* We'll "assume" we have canonical RTX now. */
2197 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2199 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2200 recognize the typical MULT which is always in tem1 because of
2201 insn canonicalization. */
2202 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2206 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2207 PLUS is always found in tem2. */
2208 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2211 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2213 if (satisfies_constraint_L (tem2
))
2216 /* A BDAP with some other constant is 2 bytes extra. */
2217 if (CONSTANT_P (tem2
))
2218 return (2 + 2 + 2) / 2;
2220 /* BDAP with something indirect should have a higher cost than
2221 BIAP with register. FIXME: Should it cost like a MEM or more? */
2222 return (2 + 2 + 2) / 2;
2225 /* What else? Return a high cost. It matters only for valid
2226 addressing modes. */
2230 /* Check various objections to the side-effect. Used in the test-part
2231 of an anonymous insn describing an insn with a possible side-effect.
2232 Returns nonzero if the implied side-effect is ok.
2235 ops : An array of rtx:es. lreg, rreg, rval,
2236 The variables multop and other_op are indexes into this,
2237 or -1 if they are not applicable.
2238 lreg : The register that gets assigned in the side-effect.
2239 rreg : One register in the side-effect expression
2240 rval : The other register, or an int.
2241 multop : An integer to multiply rval with.
2242 other_op : One of the entities of the main effect,
2243 whose mode we must consider. */
2246 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2247 int lreg
, int rreg
, int rval
,
2248 int multop
, int other_op
)
2250 /* Find what value to multiply with, for rx =ry + rz * n. */
2251 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2253 rtx reg_rtx
= ops
[rreg
];
2254 rtx val_rtx
= ops
[rval
];
2256 /* The operands may be swapped. Canonicalize them in reg_rtx and
2257 val_rtx, where reg_rtx always is a reg (for this constraint to
2259 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2260 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2262 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2263 we have no business. */
2264 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2267 /* Don't do this when -mno-split. */
2268 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2271 /* The mult expression may be hidden in lreg. FIXME: Add more
2272 commentary about that. */
2273 if (GET_CODE (val_rtx
) == MULT
)
2275 mult
= INTVAL (XEXP (val_rtx
, 1));
2276 val_rtx
= XEXP (val_rtx
, 0);
2280 /* First check the "other operand". */
2283 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2286 /* Check if the lvalue register is the same as the "other
2287 operand". If so, the result is undefined and we shouldn't do
2288 this. FIXME: Check again. */
2289 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2290 && cris_base_p (ops
[other_op
],
2291 reload_in_progress
|| reload_completed
)
2292 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2293 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2297 /* Do not accept frame_pointer_rtx as any operand. */
2298 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2299 || ops
[rval
] == frame_pointer_rtx
2300 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2304 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2307 /* Do not allow rx = rx + n if a normal add or sub with same size
2309 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2310 && CONST_INT_P (val_rtx
)
2311 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2314 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2315 if (CONSTANT_P (val_rtx
))
2319 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2320 reload_in_progress
|| reload_completed
))
2323 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2324 && MEM_P (XEXP (val_rtx
, 0))
2325 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2326 reload_in_progress
|| reload_completed
))
2329 /* If we got here, it's not a valid addressing mode. */
2332 else if (code
== MULT
2334 && cris_base_p (val_rtx
,
2335 reload_in_progress
|| reload_completed
)))
2337 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2338 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2339 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2342 /* Do not allow bad multiply-values. */
2343 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2346 /* Only allow r + ... */
2347 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2350 /* If we got here, all seems ok.
2351 (All checks need to be done above). */
2355 /* If we get here, the caller got its initial tests wrong. */
2356 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2359 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2360 insn for other reasons. */
2363 cris_cc0_user_requires_cmp (rtx insn
)
2365 rtx cc0_user
= NULL
;
2369 gcc_assert (insn
!= NULL
);
2374 cc0_user
= next_cc0_user (insn
);
2375 if (cc0_user
== NULL
)
2378 body
= PATTERN (cc0_user
);
2379 set
= single_set (cc0_user
);
2381 /* Users can be sCC and bCC. */
2382 if (JUMP_P (cc0_user
)
2383 && GET_CODE (body
) == SET
2384 && SET_DEST (body
) == pc_rtx
2385 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2386 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2389 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2390 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2395 GET_CODE (SET_SRC (body
)) == GT
2396 || GET_CODE (SET_SRC (body
)) == LE
;
2402 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2403 does not handle the case where the IN operand is strict_low_part; it
2404 does handle it for X. Test-case in Axis-20010516. This function takes
2405 care of that for THIS port. FIXME: strict_low_part is going away
2409 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2411 /* The function reg_overlap_mentioned now handles when X is
2412 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2413 if (GET_CODE (in
) == STRICT_LOW_PART
)
2416 return reg_overlap_mentioned_p (x
, in
);
2419 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2420 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2424 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2426 gcc_assert (flag_pic
);
2428 switch (GET_CODE (x
))
2437 if (GET_CODE (x
) != CONST
)
2442 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2443 if (GET_CODE (x
) == PLUS
2444 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2445 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2446 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2447 && CONST_INT_P (XEXP (x
, 1)))
2450 if (GET_CODE (x
) == UNSPEC
)
2451 switch (XINT (x
, 1))
2453 /* A PCREL operand is only valid for call and movsi. */
2454 case CRIS_UNSPEC_PLT_PCREL
:
2455 case CRIS_UNSPEC_PCREL
:
2456 return !any_operand
;
2458 case CRIS_UNSPEC_PLT_GOTREL
:
2459 case CRIS_UNSPEC_PLTGOTREAD
:
2460 case CRIS_UNSPEC_GOTREAD
:
2461 case CRIS_UNSPEC_GOTREL
:
2467 return cris_pic_symbol_type_of (x
) == cris_no_symbol
;
2470 /* Helper function to find the right PIC-type symbol to generate,
2471 given the original (non-PIC) representation. */
2473 enum cris_pic_symbol_type
2474 cris_pic_symbol_type_of (const_rtx x
)
2476 switch (GET_CODE (x
))
2479 return SYMBOL_REF_LOCAL_P (x
)
2480 ? cris_rel_symbol
: cris_got_symbol
;
2483 return cris_rel_symbol
;
2486 return cris_pic_symbol_type_of (XEXP (x
, 0));
2491 enum cris_pic_symbol_type t1
= cris_pic_symbol_type_of (XEXP (x
, 0));
2492 enum cris_pic_symbol_type t2
= cris_pic_symbol_type_of (XEXP (x
, 1));
2494 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2496 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2497 return cris_got_symbol_needing_fixup
;
2499 return t1
!= cris_no_symbol
? t1
: t2
;
2504 return cris_no_symbol
;
2507 /* Likely an offsettability-test attempting to add a constant to
2508 a GOTREAD symbol, which can't be handled. */
2509 return cris_invalid_pic_symbol
;
2512 fatal_insn ("unrecognized supposed constant", x
);
2518 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2521 cris_legitimate_pic_operand (rtx x
)
2523 /* Symbols are not valid PIC operands as-is; just constants. */
2524 return cris_valid_pic_const (x
, true);
2527 /* Queue an .ident string in the queue of top-level asm statements.
2528 If the front-end is done, we must be being called from toplev.c.
2529 In that case, do nothing. */
2531 cris_asm_output_ident (const char *string
)
2533 if (cgraph_state
!= CGRAPH_STATE_PARSING
)
2536 default_asm_output_ident_directive (string
);
2539 /* The ASM_OUTPUT_CASE_END worker. */
2542 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2544 /* Step back, over the label for the table, to the actual casejump and
2545 assert that we find only what's expected. */
2546 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2547 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2548 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2549 gcc_assert (whole_jump_insn
!= NULL_RTX
2550 && (JUMP_P (whole_jump_insn
)
2551 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2552 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2553 /* Get the pattern of the casejump, so we can extract the default label. */
2554 whole_jump_insn
= PATTERN (whole_jump_insn
);
2558 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2559 filled. We also output the offset word a little differently. */
2561 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2562 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2564 asm_fprintf (stream
,
2565 "\t.word %LL%d-.%s\n",
2566 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2567 (parallel_jump
, 0, 0),
2569 (TARGET_PDEBUG
? "; default" : ""));
2573 asm_fprintf (stream
,
2574 "\t.word %LL%d-%LL%d%s\n",
2575 CODE_LABEL_NUMBER (XEXP
2577 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2580 (TARGET_PDEBUG
? "; default" : ""));
2583 /* The TARGET_OPTION_OVERRIDE worker.
2584 As is the norm, this also parses -mfoo=bar type parameters. */
2587 cris_option_override (void)
2589 if (cris_max_stackframe_str
)
2591 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2593 /* Do some sanity checking. */
2594 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2595 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2596 cris_max_stackframe
, 0x20000000);
2599 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2600 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2601 cris_cpu_version
= CRIS_CPU_SVINTO
;
2602 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2603 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2605 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2609 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2611 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2612 cris_cpu_version
= 3;
2614 if (strcmp ("svinto", cris_cpu_str
) == 0
2615 || strcmp ("etrax100", cris_cpu_str
) == 0)
2616 cris_cpu_version
= 8;
2618 if (strcmp ("ng", cris_cpu_str
) == 0
2619 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2620 cris_cpu_version
= 10;
2622 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2623 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2626 /* Set the target flags. */
2627 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2628 target_flags
|= MASK_ETRAX4_ADD
;
2630 /* If this is Svinto or higher, align for 32 bit accesses. */
2631 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2633 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2634 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2637 /* Note that we do not add new flags when it can be completely
2638 described with a macro that uses -mcpu=X. So
2639 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2645 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2647 if (strcmp ("etrax4", cris_tune_str
) == 0)
2650 if (strcmp ("svinto", cris_tune_str
) == 0
2651 || strcmp ("etrax100", cris_tune_str
) == 0)
2654 if (strcmp ("ng", cris_tune_str
) == 0
2655 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2658 if (cris_tune
< 0 || cris_tune
> 32)
2659 error ("unknown CRIS cpu version specification in -mtune= : %s",
2662 if (cris_tune
>= CRIS_CPU_SVINTO
)
2663 /* We have currently nothing more to tune than alignment for
2666 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2667 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2670 if (cris_cpu_version
>= CRIS_CPU_V32
)
2671 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2675 /* Use error rather than warning, so invalid use is easily
2676 detectable. Still change to the values we expect, to avoid
2680 error ("-fPIC and -fpic are not supported in this configuration");
2684 /* Turn off function CSE. We need to have the addresses reach the
2685 call expanders to get PLT-marked, as they could otherwise be
2686 compared against zero directly or indirectly. After visiting the
2687 call expanders they will then be cse:ed, as the call expanders
2688 force_reg the addresses, effectively forcing flag_no_function_cse
2690 flag_no_function_cse
= 1;
2693 /* Set the per-function-data initializer. */
2694 init_machine_status
= cris_init_machine_status
;
2697 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2700 cris_asm_output_mi_thunk (FILE *stream
,
2701 tree thunkdecl ATTRIBUTE_UNUSED
,
2702 HOST_WIDE_INT delta
,
2703 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2706 /* Make sure unwind info is emitted for the thunk if needed. */
2707 final_start_function (emit_barrier (), stream
, 1);
2710 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2711 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2712 reg_names
[CRIS_FIRST_ARG_REG
]);
2714 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2715 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2716 reg_names
[CRIS_FIRST_ARG_REG
]);
2720 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2722 name
= (* targetm
.strip_name_encoding
) (name
);
2726 fprintf (stream
, "\tba ");
2727 assemble_name (stream
, name
);
2728 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2732 fprintf (stream
, "add.d ");
2733 assemble_name (stream
, name
);
2734 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2739 fprintf (stream
, "jump ");
2740 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2741 fprintf (stream
, "\n");
2744 fprintf (stream
, "\tnop\n");
2747 final_end_function ();
2750 /* Boilerplate emitted at start of file.
2752 NO_APP *only at file start* means faster assembly. It also means
2753 comments are not allowed. In some cases comments will be output
2754 for debugging purposes. Make sure they are allowed then. */
2756 cris_file_start (void)
2758 /* These expressions can vary at run time, so we cannot put
2759 them into TARGET_INITIALIZER. */
2760 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2762 default_file_start ();
2765 /* Output that goes at the end of the file, similarly. */
2768 cris_file_end (void)
2770 /* For CRIS, the default is to assume *no* executable stack, so output
2771 an executable-stack-note only when needed. */
2772 if (TARGET_LINUX
&& trampolines_created
)
2773 file_end_indicate_exec_stack ();
2776 /* Rename the function calls for integer multiply and divide. */
2778 cris_init_libfuncs (void)
2780 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2781 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2782 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2783 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2784 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2786 /* Atomic data being unaligned is unfortunately a reality.
2788 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2790 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2791 "__cris_atcmpxchgr32");
2792 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2793 "__cris_atcmpxchgr16");
2797 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2801 cris_init_expanders (void)
2803 /* Nothing here at the moment. */
2806 /* Zero initialization is OK for all current fields. */
2808 static struct machine_function
*
2809 cris_init_machine_status (void)
2811 return ggc_alloc_cleared_machine_function ();
2814 /* Split a 2 word move (DI or presumably DF) into component parts.
2815 Originally a copy of gen_split_move_double in m32r.c. */
2818 cris_split_movdx (rtx
*operands
)
2820 enum machine_mode mode
= GET_MODE (operands
[0]);
2821 rtx dest
= operands
[0];
2822 rtx src
= operands
[1];
2825 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2826 longer happen; after reload there are no SUBREGs any more, and we're
2827 only called after reload. */
2828 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2833 int dregno
= REGNO (dest
);
2835 /* Reg-to-reg copy. */
2838 int sregno
= REGNO (src
);
2840 int reverse
= (dregno
== sregno
+ 1);
2842 /* We normally copy the low-numbered register first. However, if
2843 the first register operand 0 is the same as the second register of
2844 operand 1, we must copy in the opposite order. */
2845 emit_insn (gen_rtx_SET (VOIDmode
,
2846 operand_subword (dest
, reverse
, TRUE
, mode
),
2847 operand_subword (src
, reverse
, TRUE
, mode
)));
2849 emit_insn (gen_rtx_SET (VOIDmode
,
2850 operand_subword (dest
, !reverse
, TRUE
, mode
),
2851 operand_subword (src
, !reverse
, TRUE
, mode
)));
2853 /* Constant-to-reg copy. */
2854 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2857 split_double (src
, &words
[0], &words
[1]);
2858 emit_insn (gen_rtx_SET (VOIDmode
,
2859 operand_subword (dest
, 0, TRUE
, mode
),
2862 emit_insn (gen_rtx_SET (VOIDmode
,
2863 operand_subword (dest
, 1, TRUE
, mode
),
2866 /* Mem-to-reg copy. */
2867 else if (MEM_P (src
))
2869 /* If the high-address word is used in the address, we must load it
2870 last. Otherwise, load it first. */
2871 rtx addr
= XEXP (src
, 0);
2873 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2875 /* The original code implies that we can't do
2876 move.x [rN+],rM move.x [rN],rM+1
2877 when rN is dead, because of REG_NOTES damage. That is
2878 consistent with what I've seen, so don't try it.
2880 We have two different cases here; if the addr is POST_INC,
2881 just pass it through, otherwise add constants. */
2883 if (GET_CODE (addr
) == POST_INC
)
2888 /* Whenever we emit insns with post-incremented
2889 addresses ourselves, we must add a post-inc note
2891 mem
= change_address (src
, SImode
, addr
);
2893 = gen_rtx_SET (VOIDmode
,
2894 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2895 insn
= emit_insn (insn
);
2896 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2898 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2901 mem
= copy_rtx (mem
);
2903 = gen_rtx_SET (VOIDmode
,
2904 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2905 insn
= emit_insn (insn
);
2906 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2908 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2913 /* Make sure we don't get any other addresses with
2914 embedded postincrements. They should be stopped in
2915 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2917 if (side_effects_p (addr
))
2918 fatal_insn ("unexpected side-effects in address", addr
);
2920 emit_insn (gen_rtx_SET
2922 operand_subword (dest
, reverse
, TRUE
, mode
),
2925 plus_constant (Pmode
, addr
,
2926 reverse
* UNITS_PER_WORD
))));
2927 emit_insn (gen_rtx_SET
2929 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2932 plus_constant (Pmode
, addr
,
2938 internal_error ("unknown src");
2940 /* Reg-to-mem copy or clear mem. */
2941 else if (MEM_P (dest
)
2943 || src
== const0_rtx
2944 || src
== CONST0_RTX (DFmode
)))
2946 rtx addr
= XEXP (dest
, 0);
2948 if (GET_CODE (addr
) == POST_INC
)
2953 /* Whenever we emit insns with post-incremented addresses
2954 ourselves, we must add a post-inc note manually. */
2955 mem
= change_address (dest
, SImode
, addr
);
2957 = gen_rtx_SET (VOIDmode
,
2958 mem
, operand_subword (src
, 0, TRUE
, mode
));
2959 insn
= emit_insn (insn
);
2960 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2962 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2965 mem
= copy_rtx (mem
);
2967 = gen_rtx_SET (VOIDmode
,
2969 operand_subword (src
, 1, TRUE
, mode
));
2970 insn
= emit_insn (insn
);
2971 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2973 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2978 /* Make sure we don't get any other addresses with embedded
2979 postincrements. They should be stopped in
2980 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2981 if (side_effects_p (addr
))
2982 fatal_insn ("unexpected side-effects in address", addr
);
2984 emit_insn (gen_rtx_SET
2986 change_address (dest
, SImode
, addr
),
2987 operand_subword (src
, 0, TRUE
, mode
)));
2989 emit_insn (gen_rtx_SET
2991 change_address (dest
, SImode
,
2992 plus_constant (Pmode
, addr
,
2994 operand_subword (src
, 1, TRUE
, mode
)));
2999 internal_error ("unknown dest");
3006 /* The expander for the prologue pattern name. */
3009 cris_expand_prologue (void)
3012 int size
= get_frame_size ();
3013 /* Shorten the used name for readability. */
3014 int cfoa_size
= crtl
->outgoing_args_size
;
3015 int last_movem_reg
= -1;
3018 int return_address_on_stack
= cris_return_address_on_stack ();
3019 int got_really_used
= false;
3020 int n_movem_regs
= 0;
3021 int pretend
= crtl
->args
.pretend_args_size
;
3023 /* Don't do anything if no prologues or epilogues are wanted. */
3024 if (!TARGET_PROLOGUE_EPILOGUE
)
3027 CRIS_ASSERT (size
>= 0);
3029 if (crtl
->uses_pic_offset_table
)
3031 /* A reference may have been optimized out (like the abort () in
3032 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3034 push_topmost_sequence ();
3036 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
3037 pop_topmost_sequence ();
3040 /* Align the size to what's best for the CPU model. */
3041 if (TARGET_STACK_ALIGN
)
3042 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3046 /* See also cris_setup_incoming_varargs where
3047 cfun->machine->stdarg_regs is set. There are other setters of
3048 crtl->args.pretend_args_size than stdarg handling, like
3049 for an argument passed with parts in R13 and stack. We must
3050 not store R13 into the pretend-area for that case, as GCC does
3051 that itself. "Our" store would be marked as redundant and GCC
3052 will attempt to remove it, which will then be flagged as an
3053 internal error; trying to remove a frame-related insn. */
3054 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3056 framesize
+= pretend
;
3058 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3060 regno
--, pretend
-= 4, stdarg_regs
--)
3062 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3064 plus_constant (Pmode
,
3067 /* FIXME: When dwarf2 frame output and unless asynchronous
3068 exceptions, make dwarf2 bundle together all stack
3069 adjustments like it does for registers between stack
3071 RTX_FRAME_RELATED_P (insn
) = 1;
3073 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3074 set_mem_alias_set (mem
, get_varargs_alias_set ());
3075 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3077 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3078 the value isn't restored, so we don't want to tell dwarf2
3079 that it's been stored to stack, else EH handling info would
3083 /* For other setters of crtl->args.pretend_args_size, we
3084 just adjust the stack by leaving the remaining size in
3085 "pretend", handled below. */
3088 /* Save SRP if not a leaf function. */
3089 if (return_address_on_stack
)
3091 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3093 plus_constant (Pmode
, stack_pointer_rtx
,
3096 RTX_FRAME_RELATED_P (insn
) = 1;
3098 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3099 set_mem_alias_set (mem
, get_frame_alias_set ());
3100 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3101 RTX_FRAME_RELATED_P (insn
) = 1;
3105 /* Set up the frame pointer, if needed. */
3106 if (frame_pointer_needed
)
3108 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3110 plus_constant (Pmode
, stack_pointer_rtx
,
3113 RTX_FRAME_RELATED_P (insn
) = 1;
3115 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3116 set_mem_alias_set (mem
, get_frame_alias_set ());
3117 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3118 RTX_FRAME_RELATED_P (insn
) = 1;
3120 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3121 RTX_FRAME_RELATED_P (insn
) = 1;
3126 /* Between frame-pointer and saved registers lie the area for local
3127 variables. If we get here with "pretended" size remaining, count
3128 it into the general stack size. */
3131 /* Get a contiguous sequence of registers, starting with R0, that need
3133 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3135 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3139 /* Check if movem may be used for registers so far. */
3140 if (regno
== last_movem_reg
+ 1)
3141 /* Yes, update next expected register. */
3142 last_movem_reg
= regno
;
3145 /* We cannot use movem for all registers. We have to flush
3146 any movem:ed registers we got so far. */
3147 if (last_movem_reg
!= -1)
3150 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3152 /* It is a win to use a side-effect assignment for
3153 64 <= size <= 128. But side-effect on movem was
3154 not usable for CRIS v0..3. Also only do it if
3155 side-effects insns are allowed. */
3156 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3157 && (last_movem_reg
+ 1) * 4 + size
<= 128
3158 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3159 && TARGET_SIDE_EFFECT_PREFIXES
)
3162 = gen_rtx_MEM (SImode
,
3163 plus_constant (Pmode
, stack_pointer_rtx
,
3164 -(n_saved
* 4 + size
)));
3165 set_mem_alias_set (mem
, get_frame_alias_set ());
3167 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3168 -(n_saved
* 4 + size
),
3174 = gen_rtx_SET (VOIDmode
,
3176 plus_constant (Pmode
, stack_pointer_rtx
,
3177 -(n_saved
* 4 + size
)));
3178 insn
= emit_insn (insn
);
3179 RTX_FRAME_RELATED_P (insn
) = 1;
3181 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3182 set_mem_alias_set (mem
, get_frame_alias_set ());
3183 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3187 framesize
+= n_saved
* 4 + size
;
3188 last_movem_reg
= -1;
3192 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3194 plus_constant (Pmode
,
3197 RTX_FRAME_RELATED_P (insn
) = 1;
3199 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3200 set_mem_alias_set (mem
, get_frame_alias_set ());
3201 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3202 RTX_FRAME_RELATED_P (insn
) = 1;
3204 framesize
+= 4 + size
;
3210 /* Check after, if we could movem all registers. This is the normal case. */
3211 if (last_movem_reg
!= -1)
3214 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3216 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3217 do it if side-effects insns are allowed. */
3218 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3219 && (last_movem_reg
+ 1) * 4 + size
<= 128
3220 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3221 && TARGET_SIDE_EFFECT_PREFIXES
)
3224 = gen_rtx_MEM (SImode
,
3225 plus_constant (Pmode
, stack_pointer_rtx
,
3226 -(n_saved
* 4 + size
)));
3227 set_mem_alias_set (mem
, get_frame_alias_set ());
3228 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3229 -(n_saved
* 4 + size
), true);
3234 = gen_rtx_SET (VOIDmode
,
3236 plus_constant (Pmode
, stack_pointer_rtx
,
3237 -(n_saved
* 4 + size
)));
3238 insn
= emit_insn (insn
);
3239 RTX_FRAME_RELATED_P (insn
) = 1;
3241 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3242 set_mem_alias_set (mem
, get_frame_alias_set ());
3243 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3246 framesize
+= n_saved
* 4 + size
;
3247 /* We have to put outgoing argument space after regs. */
3250 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3252 plus_constant (Pmode
,
3255 RTX_FRAME_RELATED_P (insn
) = 1;
3256 framesize
+= cfoa_size
;
3259 else if ((size
+ cfoa_size
) > 0)
3261 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3263 plus_constant (Pmode
,
3265 -(cfoa_size
+ size
))));
3266 RTX_FRAME_RELATED_P (insn
) = 1;
3267 framesize
+= size
+ cfoa_size
;
3270 /* Set up the PIC register, if it is used. */
3271 if (got_really_used
)
3274 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3275 emit_move_insn (pic_offset_table_rtx
, got
);
3277 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3278 follow exceptional paths and tries to delete the GOT load as
3279 unused, if it isn't used on the non-exceptional paths. Other
3280 ports have similar or other cover-ups, or plain bugs marking
3281 the GOT register load as maybe-dead. To see this, remove the
3282 line below and try libsupc++/vec.cc or a trivial
3283 "static void y (); void x () {try {y ();} catch (...) {}}". */
3284 emit_use (pic_offset_table_rtx
);
3287 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3288 warning (0, "stackframe too big: %d bytes", framesize
);
3291 /* The expander for the epilogue pattern. */
3294 cris_expand_epilogue (void)
3297 int size
= get_frame_size ();
3298 int last_movem_reg
= -1;
3299 int argspace_offset
= crtl
->outgoing_args_size
;
3300 int pretend
= crtl
->args
.pretend_args_size
;
3302 bool return_address_on_stack
= cris_return_address_on_stack ();
3303 /* A reference may have been optimized out
3304 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3305 so check that it's still used. */
3306 int got_really_used
= false;
3307 int n_movem_regs
= 0;
3309 if (!TARGET_PROLOGUE_EPILOGUE
)
3312 if (crtl
->uses_pic_offset_table
)
3314 /* A reference may have been optimized out (like the abort () in
3315 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3317 push_topmost_sequence ();
3319 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
3320 pop_topmost_sequence ();
3323 /* Align byte count of stack frame. */
3324 if (TARGET_STACK_ALIGN
)
3325 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3327 /* Check how many saved regs we can movem. They start at r0 and must
3330 regno
< FIRST_PSEUDO_REGISTER
;
3332 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3336 if (regno
== last_movem_reg
+ 1)
3337 last_movem_reg
= regno
;
3342 /* If there was only one register that really needed to be saved
3343 through movem, don't use movem. */
3344 if (n_movem_regs
== 1)
3345 last_movem_reg
= -1;
3347 /* Now emit "normal" move insns for all regs higher than the movem
3349 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3350 regno
> last_movem_reg
;
3352 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3356 if (argspace_offset
)
3358 /* There is an area for outgoing parameters located before
3359 the saved registers. We have to adjust for that. */
3360 emit_insn (gen_rtx_SET (VOIDmode
,
3362 plus_constant (Pmode
, stack_pointer_rtx
,
3364 /* Make sure we only do this once. */
3365 argspace_offset
= 0;
3368 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3369 stack_pointer_rtx
));
3370 set_mem_alias_set (mem
, get_frame_alias_set ());
3371 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3373 /* Whenever we emit insns with post-incremented addresses
3374 ourselves, we must add a post-inc note manually. */
3376 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3379 /* If we have any movem-restore, do it now. */
3380 if (last_movem_reg
!= -1)
3384 if (argspace_offset
)
3386 emit_insn (gen_rtx_SET (VOIDmode
,
3388 plus_constant (Pmode
, stack_pointer_rtx
,
3390 argspace_offset
= 0;
3393 mem
= gen_rtx_MEM (SImode
,
3394 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3395 set_mem_alias_set (mem
, get_frame_alias_set ());
3397 = emit_insn (cris_gen_movem_load (mem
,
3398 GEN_INT (last_movem_reg
+ 1), 0));
3399 /* Whenever we emit insns with post-incremented addresses
3400 ourselves, we must add a post-inc note manually. */
3401 if (side_effects_p (PATTERN (insn
)))
3403 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3406 /* If we don't clobber all of the allocated stack area (we've already
3407 deallocated saved registers), GCC might want to schedule loads from
3408 the stack to *after* the stack-pointer restore, which introduces an
3409 interrupt race condition. This happened for the initial-value
3410 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3411 other failure for that test). It also happened for the stack slot
3412 for the return value in (one version of)
3413 linux/fs/dcache.c:__d_lookup, at least with "-O2
3414 -fno-omit-frame-pointer". */
3416 /* Restore frame pointer if necessary. */
3417 if (frame_pointer_needed
)
3421 emit_insn (gen_cris_frame_deallocated_barrier ());
3423 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3424 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3425 stack_pointer_rtx
));
3426 set_mem_alias_set (mem
, get_frame_alias_set ());
3427 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3429 /* Whenever we emit insns with post-incremented addresses
3430 ourselves, we must add a post-inc note manually. */
3432 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3434 else if ((size
+ argspace_offset
) != 0)
3436 emit_insn (gen_cris_frame_deallocated_barrier ());
3438 /* If there was no frame-pointer to restore sp from, we must
3439 explicitly deallocate local variables. */
3441 /* Handle space for outgoing parameters that hasn't been handled
3443 size
+= argspace_offset
;
3445 emit_insn (gen_rtx_SET (VOIDmode
,
3447 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3450 /* If this function has no pushed register parameters
3451 (stdargs/varargs), and if it is not a leaf function, then we have
3452 the return address on the stack. */
3453 if (return_address_on_stack
&& pretend
== 0)
3455 if (TARGET_V32
|| crtl
->calls_eh_return
)
3459 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3460 mem
= gen_rtx_MEM (SImode
,
3461 gen_rtx_POST_INC (SImode
,
3462 stack_pointer_rtx
));
3463 set_mem_alias_set (mem
, get_frame_alias_set ());
3464 insn
= emit_move_insn (srpreg
, mem
);
3466 /* Whenever we emit insns with post-incremented addresses
3467 ourselves, we must add a post-inc note manually. */
3469 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3471 if (crtl
->calls_eh_return
)
3472 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3474 gen_rtx_raw_REG (SImode
,
3475 CRIS_STACKADJ_REG
)));
3476 cris_expand_return (false);
3479 cris_expand_return (true);
3484 /* If we pushed some register parameters, then adjust the stack for
3488 /* If SRP is stored on the way, we need to restore it first. */
3489 if (return_address_on_stack
)
3492 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3495 mem
= gen_rtx_MEM (SImode
,
3496 gen_rtx_POST_INC (SImode
,
3497 stack_pointer_rtx
));
3498 set_mem_alias_set (mem
, get_frame_alias_set ());
3499 insn
= emit_move_insn (srpreg
, mem
);
3501 /* Whenever we emit insns with post-incremented addresses
3502 ourselves, we must add a post-inc note manually. */
3504 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3507 emit_insn (gen_rtx_SET (VOIDmode
,
3509 plus_constant (Pmode
, stack_pointer_rtx
,
3513 /* Perform the "physical" unwinding that the EH machinery calculated. */
3514 if (crtl
->calls_eh_return
)
3515 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3517 gen_rtx_raw_REG (SImode
,
3518 CRIS_STACKADJ_REG
)));
3519 cris_expand_return (false);
3522 /* Worker function for generating movem from mem for load_multiple. */
3525 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3527 int nregs
= INTVAL (nregs_rtx
);
3531 rtx srcreg
= XEXP (src
, 0);
3532 unsigned int regno
= nregs
- 1;
3541 if (GET_CODE (srcreg
) == POST_INC
)
3542 srcreg
= XEXP (srcreg
, 0);
3544 CRIS_ASSERT (REG_P (srcreg
));
3546 /* Don't use movem for just one insn. The insns are equivalent except
3547 for the pipeline hazard (on v32); movem does not forward the loaded
3548 registers so there's a three cycles penalty for their use. */
3550 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3552 vec
= rtvec_alloc (nprefix
+ nregs
3553 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3555 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3557 RTVEC_ELT (vec
, nprefix
+ 1)
3558 = gen_rtx_SET (VOIDmode
, srcreg
,
3559 plus_constant (Pmode
, srcreg
, nregs
* 4));
3563 src
= replace_equiv_address (src
, srcreg
);
3564 RTVEC_ELT (vec
, nprefix
)
3565 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3568 for (i
= 1; i
< nregs
; i
++, eltno
++)
3570 RTVEC_ELT (vec
, nprefix
+ eltno
)
3571 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3572 adjust_address_nv (src
, SImode
, i
* 4));
3576 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3579 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3580 are added that the dwarf2 machinery understands. */
3583 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3586 int nregs
= INTVAL (nregs_rtx
);
3591 rtx destreg
= XEXP (dest
, 0);
3592 unsigned int regno
= nregs
- 1;
3601 if (GET_CODE (destreg
) == POST_INC
)
3602 increment
+= nregs
* 4;
3604 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3605 destreg
= XEXP (destreg
, 0);
3607 CRIS_ASSERT (REG_P (destreg
));
3609 /* Don't use movem for just one insn. The insns are equivalent except
3610 for the pipeline hazard (on v32); movem does not forward the loaded
3611 registers so there's a three cycles penalty for use. */
3614 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3618 insn
= emit_insn (mov
);
3620 RTX_FRAME_RELATED_P (insn
) = 1;
3624 /* If there was a request for a side-effect, create the ordinary
3626 vec
= rtvec_alloc (2);
3628 RTVEC_ELT (vec
, 0) = mov
;
3629 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3630 plus_constant (Pmode
, destreg
,
3634 RTX_FRAME_RELATED_P (mov
) = 1;
3635 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3640 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3642 = gen_rtx_SET (VOIDmode
,
3643 replace_equiv_address (dest
,
3644 plus_constant (Pmode
, destreg
,
3646 gen_rtx_REG (SImode
, regno
));
3649 /* The dwarf2 info wants this mark on each component in a parallel
3650 that's part of the prologue (though it's optional on the first
3653 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3658 = gen_rtx_SET (VOIDmode
, destreg
,
3659 plus_constant (Pmode
, destreg
,
3661 ? increment
: nregs
* 4));
3665 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3667 /* Don't call adjust_address_nv on a post-incremented address if
3669 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3670 dest
= replace_equiv_address (dest
, destreg
);
3673 for (i
= 1; i
< nregs
; i
++, eltno
++)
3675 RTVEC_ELT (vec
, eltno
)
3676 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3677 gen_rtx_REG (SImode
, regno
));
3679 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3684 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3686 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3687 we need to keep the stack adjustment separate, after the
3688 MEM-setters. Else the stack-adjustment in the second component of
3689 the parallel would be mishandled; the offsets for the SETs that
3690 follow it would be wrong. We prepare for this by adding a
3691 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3692 followed by the increment. Note that we have FRAME_RELATED_P on
3693 all the SETs, including the original stack adjustment SET in the
3699 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3700 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3701 for (i
= 1; i
< nregs
; i
++)
3703 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3704 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3705 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3708 RTX_FRAME_RELATED_P (insn
) = 1;
3714 /* Worker function for expanding the address for PIC function calls. */
3717 cris_expand_pic_call_address (rtx
*opp
)
3721 gcc_assert (MEM_P (op
));
3724 /* It might be that code can be generated that jumps to 0 (or to a
3725 specific address). Don't die on that. (There is a
3727 if (CONSTANT_ADDRESS_P (op
) && !CONST_INT_P (op
))
3729 enum cris_pic_symbol_type t
= cris_pic_symbol_type_of (op
);
3731 CRIS_ASSERT (can_create_pseudo_p ());
3733 /* For local symbols (non-PLT), just get the plain symbol
3734 reference into a register. For symbols that can be PLT, make
3736 if (t
== cris_rel_symbol
)
3738 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3739 into a register caused performance regression for 3.2.1,
3740 observable in __floatdidf and elsewhere in libgcc. */
3743 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3744 HOST_WIDE_INT offs
= get_integer_term (op
);
3746 /* We can't get calls to sym+N, N integer, can we? */
3747 gcc_assert (offs
== 0);
3749 op
= gen_rtx_CONST (Pmode
,
3750 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3751 CRIS_UNSPEC_PCREL
));
3754 op
= force_reg (Pmode
, op
);
3756 else if (t
== cris_got_symbol
)
3758 if (TARGET_AVOID_GOTPLT
)
3760 /* Change a "jsr sym" into (allocate register rM, rO)
3761 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3762 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3763 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3766 gcc_assert (can_create_pseudo_p ());
3767 crtl
->uses_pic_offset_table
= 1;
3768 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3770 ? CRIS_UNSPEC_PLT_PCREL
3771 : CRIS_UNSPEC_PLT_GOTREL
);
3772 tem
= gen_rtx_CONST (Pmode
, tem
);
3777 rm
= gen_reg_rtx (Pmode
);
3778 emit_move_insn (rm
, tem
);
3779 ro
= gen_reg_rtx (Pmode
);
3780 if (expand_binop (Pmode
, add_optab
, rm
,
3781 pic_offset_table_rtx
,
3782 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3783 internal_error ("expand_binop failed in movsi got");
3789 /* Change a "jsr sym" into (allocate register rM, rO)
3790 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3791 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3792 marked as not trapping and not aliasing. No "move.d
3793 [rO],rP" as that would invite to re-use of a value
3794 that should not be reused. FIXME: Need a peephole2
3795 for cases when this is cse:d from the call, to change
3796 back to just get the PLT entry address, so we don't
3797 resolve the same symbol over and over (the memory
3798 access of the PLTGOT isn't constant). */
3799 rtx tem
, mem
, rm
, ro
;
3801 gcc_assert (can_create_pseudo_p ());
3802 crtl
->uses_pic_offset_table
= 1;
3803 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3804 CRIS_UNSPEC_PLTGOTREAD
);
3805 rm
= gen_reg_rtx (Pmode
);
3806 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3807 ro
= gen_reg_rtx (Pmode
);
3808 if (expand_binop (Pmode
, add_optab
, rm
,
3809 pic_offset_table_rtx
,
3810 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3811 internal_error ("expand_binop failed in movsi got");
3812 mem
= gen_rtx_MEM (Pmode
, ro
);
3814 /* This MEM doesn't alias anything. Whether it aliases
3815 other same symbols is unimportant. */
3816 set_mem_alias_set (mem
, new_alias_set ());
3817 MEM_NOTRAP_P (mem
) = 1;
3822 /* Can't possibly get a GOT-needing-fixup for a function-call,
3824 fatal_insn ("unidentifiable call op", op
);
3826 *opp
= replace_equiv_address (*opp
, op
);
3830 /* Make sure operands are in the right order for an addsi3 insn as
3831 generated by a define_split. Nothing but REG_P as the first
3832 operand is recognized by addsi3 after reload. OPERANDS contains
3833 the operands, with the first at OPERANDS[N] and the second at
3837 cris_order_for_addsi3 (rtx
*operands
, int n
)
3839 if (!REG_P (operands
[n
]))
3841 rtx tem
= operands
[n
];
3842 operands
[n
] = operands
[n
+ 1];
3843 operands
[n
+ 1] = tem
;
3847 /* Use from within code, from e.g. PRINT_OPERAND and
3848 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3849 different things depending on whether code operand or constant is
3853 cris_output_addr_const (FILE *file
, rtx x
)
3856 output_addr_const (file
, x
);
3860 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3863 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3865 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3867 if (flag_pic
&& in_code
> 0)
3869 const char *origstr
= XSTR (x
, 0);
3871 str
= (* targetm
.strip_name_encoding
) (origstr
);
3872 assemble_name (file
, str
);
3875 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3876 output_operand_lossage ("PIC register isn't set up");
3879 assemble_name (file
, XSTR (x
, 0));
3882 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3885 cris_asm_output_label_ref (FILE *file
, char *buf
)
3887 if (flag_pic
&& in_code
> 0)
3889 assemble_name (file
, buf
);
3892 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3893 internal_error ("emitting PIC operand, but PIC register "
3897 assemble_name (file
, buf
);
3900 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3903 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3905 switch (GET_CODE (xconst
))
3910 x
= XVECEXP (xconst
, 0, 0);
3911 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3912 || GET_CODE (x
) == LABEL_REF
3913 || GET_CODE (x
) == CONST
);
3914 output_addr_const (file
, x
);
3915 switch (XINT (xconst
, 1))
3917 case CRIS_UNSPEC_PCREL
:
3918 /* We only get this with -fpic/PIC to tell it apart from an
3919 invalid symbol. We can't tell here, but it should only
3920 be the operand of a call or movsi. */
3921 gcc_assert (TARGET_V32
&& flag_pic
);
3924 case CRIS_UNSPEC_PLT_PCREL
:
3925 gcc_assert (TARGET_V32
);
3926 fprintf (file
, ":PLT");
3929 case CRIS_UNSPEC_PLT_GOTREL
:
3930 gcc_assert (!TARGET_V32
);
3931 fprintf (file
, ":PLTG");
3934 case CRIS_UNSPEC_GOTREL
:
3935 gcc_assert (!TARGET_V32
);
3936 fprintf (file
, ":GOTOFF");
3939 case CRIS_UNSPEC_GOTREAD
:
3941 fprintf (file
, ":GOT16");
3943 fprintf (file
, ":GOT");
3946 case CRIS_UNSPEC_PLTGOTREAD
:
3948 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3950 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3963 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3966 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3967 int incoming ATTRIBUTE_UNUSED
)
3969 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3972 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3975 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
3976 enum machine_mode mode ATTRIBUTE_UNUSED
,
3977 tree type ATTRIBUTE_UNUSED
,
3978 int *pretend_arg_size
,
3981 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3983 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3985 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3986 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3987 *pretend_arg_size
= stdarg_regs
* 4;
3991 fprintf (asm_out_file
,
3992 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3993 ca
->regs
, *pretend_arg_size
, second_time
);
3996 /* Return true if TYPE must be passed by invisible reference.
3997 For cris, we pass <= 8 bytes by value, others by reference. */
4000 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4001 enum machine_mode mode
, const_tree type
,
4002 bool named ATTRIBUTE_UNUSED
)
4004 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4005 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4008 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4009 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4010 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4013 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4014 enum machine_mode mode
,
4015 int *punsignedp ATTRIBUTE_UNUSED
,
4016 const_tree fntype ATTRIBUTE_UNUSED
,
4019 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4020 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4021 Maybe pointless as of now, but let's keep the old behavior. */
4022 if (for_return
== 1)
4024 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4027 /* Atomic types require alignment to be at least their "natural" size. */
4030 cris_atomic_align_for_mode (enum machine_mode mode
)
4032 return GET_MODE_BITSIZE (mode
);
4035 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4039 cris_function_value(const_tree type
,
4040 const_tree func ATTRIBUTE_UNUSED
,
4041 bool outgoing ATTRIBUTE_UNUSED
)
4043 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4046 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4050 cris_libcall_value (enum machine_mode mode
,
4051 const_rtx fun ATTRIBUTE_UNUSED
)
4053 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4056 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4060 cris_function_value_regno_p (const unsigned int regno
)
4062 return (regno
== CRIS_FIRST_ARG_REG
);
4066 cris_arg_partial_bytes (cumulative_args_t ca
, enum machine_mode mode
,
4067 tree type
, bool named ATTRIBUTE_UNUSED
)
4069 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4070 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4071 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4072 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4073 return UNITS_PER_WORD
;
4079 cris_function_arg_1 (cumulative_args_t ca_v
,
4080 enum machine_mode mode ATTRIBUTE_UNUSED
,
4081 const_tree type ATTRIBUTE_UNUSED
,
4082 bool named
, bool incoming
)
4084 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4086 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4087 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4092 /* Worker function for TARGET_FUNCTION_ARG.
4093 The void_type_node is sent as a "closing" call. */
4096 cris_function_arg (cumulative_args_t ca
, enum machine_mode mode
,
4097 const_tree type
, bool named
)
4099 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4102 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4104 The differences between this and the previous, is that this one checks
4105 that an argument is named, since incoming stdarg/varargs arguments are
4106 pushed onto the stack, and we don't have to check against the "closing"
4107 void_type_node TYPE parameter. */
4110 cris_function_incoming_arg (cumulative_args_t ca
, enum machine_mode mode
,
4111 const_tree type
, bool named
)
4113 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4116 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4119 cris_function_arg_advance (cumulative_args_t ca_v
, enum machine_mode mode
,
4120 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4122 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4124 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4127 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4130 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
4132 HARD_REG_SET mof_set
;
4136 CLEAR_HARD_REG_SET (mof_set
);
4137 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
4139 /* For the time being, all asms clobber condition codes. Revisit when
4140 there's a reasonable use for inputs/outputs that mention condition
4143 = tree_cons (NULL_TREE
,
4144 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
4145 reg_names
[CRIS_CC0_REGNUM
]),
4148 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4150 tree val
= TREE_VALUE (t
);
4152 /* The constraint letter for the singleton register class of MOF
4153 is 'h'. If it's mentioned in the constraints, the asm is
4154 MOF-aware and adding it to the clobbers would cause it to have
4155 impossible constraints. */
4156 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4158 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4162 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4164 tree val
= TREE_VALUE (t
);
4166 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4168 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4172 return tree_cons (NULL_TREE
,
4173 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
4174 reg_names
[CRIS_MOF_REGNUM
]),
4178 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4180 Really only needed if the stack frame has variable length (alloca
4181 or variable sized local arguments (GNU C extension). See PR39499 and
4182 PR38609 for the reason this isn't just 0. */
4185 cris_frame_pointer_required (void)
4187 return !crtl
->sp_is_unchanging
;
4190 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4192 This looks too complicated, and it is. I assigned r7 to be the
4193 static chain register, but it is call-saved, so we have to save it,
4194 and come back to restore it after the call, so we have to save srp...
4195 Anyway, trampolines are rare enough that we can cope with this
4196 somewhat lack of elegance.
4197 (Do not be tempted to "straighten up" whitespace in the asms; the
4198 assembler #NO_APP state mandates strict spacing). */
4199 /* ??? See the i386 regparm=3 implementation that pushes the static
4200 chain value to the stack in the trampoline, and uses a call-saved
4201 register when called directly. */
4204 cris_asm_trampoline_template (FILE *f
)
4208 /* This normally-unused nop insn acts as an instruction to
4209 the simulator to flush its instruction cache. None of
4210 the other instructions in the trampoline template suits
4211 as a trigger for V32. The pc-relative addressing mode
4212 works nicely as a trigger for V10.
4213 FIXME: Have specific V32 template (possibly avoiding the
4214 use of a special instruction). */
4215 fprintf (f
, "\tclearf x\n");
4216 /* We have to use a register as an intermediate, choosing
4217 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4218 so we can use it for address indirection and jsr target. */
4219 fprintf (f
, "\tmove $r1,$mof\n");
4221 fprintf (f
, "\tmove.d 0,$r1\n");
4222 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4223 fprintf (f
, "\taddq 6,$r1\n");
4224 fprintf (f
, "\tmove $mof,[$r1]\n");
4225 fprintf (f
, "\taddq 6,$r1\n");
4226 fprintf (f
, "\tmove $srp,[$r1]\n");
4228 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4230 fprintf (f
, "\tmove.d 0,$r1\n");
4231 fprintf (f
, "\tjsr $r1\n");
4232 fprintf (f
, "\tsetf\n");
4234 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4236 fprintf (f
, "\tmove.d 0,$r1\n");
4238 fprintf (f
, "\tmove.d 0,$r9\n");
4239 fprintf (f
, "\tjump $r9\n");
4240 fprintf (f
, "\tsetf\n");
4244 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4245 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4246 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4247 fprintf (f
, "\tjsr 0\n");
4248 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4249 fprintf (f
, "\tjump 0\n");
4253 /* Implement TARGET_TRAMPOLINE_INIT. */
4256 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4258 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4259 rtx tramp
= XEXP (m_tramp
, 0);
4262 emit_block_move (m_tramp
, assemble_trampoline_template (),
4263 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4267 mem
= adjust_address (m_tramp
, SImode
, 6);
4268 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4269 mem
= adjust_address (m_tramp
, SImode
, 22);
4270 emit_move_insn (mem
, chain_value
);
4271 mem
= adjust_address (m_tramp
, SImode
, 28);
4272 emit_move_insn (mem
, fnaddr
);
4276 mem
= adjust_address (m_tramp
, SImode
, 10);
4277 emit_move_insn (mem
, chain_value
);
4278 mem
= adjust_address (m_tramp
, SImode
, 16);
4279 emit_move_insn (mem
, fnaddr
);
4282 /* Note that there is no need to do anything with the cache for
4283 sake of a trampoline. */
4288 /* Various small functions to replace macros. Only called from a
4289 debugger. They might collide with gcc functions or system functions,
4290 so only emit them when '#if 1' above. */
4292 enum rtx_code
Get_code (rtx
);
4297 return GET_CODE (x
);
4300 const char *Get_mode (rtx
);
4305 return GET_MODE_NAME (GET_MODE (x
));
4308 rtx
Xexp (rtx
, int);
4316 rtx
Xvecexp (rtx
, int, int);
4319 Xvecexp (rtx x
, int n
, int m
)
4321 return XVECEXP (x
, n
, m
);
4324 int Get_rtx_len (rtx
);
4329 return GET_RTX_LENGTH (GET_CODE (x
));
4332 /* Use upper-case to distinguish from local variables that are sometimes
4333 called next_insn and prev_insn. */
4335 rtx
Next_insn (rtx
);
4338 Next_insn (rtx insn
)
4340 return NEXT_INSN (insn
);
4343 rtx
Prev_insn (rtx
);
4346 Prev_insn (rtx insn
)
4348 return PREV_INSN (insn
);
4352 #include "gt-cris.h"
4356 * eval: (c-set-style "gnu")
4357 * indent-tabs-mode: t