| blob | 8826acd004b736219ecfaa2ba7946ce45b73b5b0 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2024 m_ATOM,
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2418 };
2421 {
2432 /* Core 2 */
2434 /* Core i7 */
2436 /* Core avx2 */
2447 };
2450 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3242 else
3244 }
3246 {
3249 }
3256 {
3259 /* Default cpu tuning to the architecture. */
3384 }
3399 {
3403 {
3405 {
3407 {
3415 }
3416 else
3419 }
3420 }
3421 else
3422 {
3423 /* Adjust tuning when compiling for 32-bit ABI. */
3425 {
3433 }
3434 }
3435 /* Intel CPUs have always interpreted SSE prefetch instructions as
3436 NOPs; so, we can enable SSE prefetch instructions even when
3437 -mtune (rather than -march) points us to a processor that has them.
3438 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3439 higher processors. */
3444 }
3454 #ifndef USE_IX86_FRAME_POINTER
3455 #define USE_IX86_FRAME_POINTER 0
3456 #endif
3458 #ifndef USE_X86_64_FRAME_POINTER
3459 #define USE_X86_64_FRAME_POINTER 0
3460 #endif
3462 /* Set the default values for switches whose default depends on TARGET_64BIT
3463 in case they weren't overwritten by command line options. */
3465 {
3472 }
3473 else
3474 {
3481 }
3486 else
3489 /* Arrange to set up i386_stack_locals for all functions. */
3492 /* Validate -mregparm= value. */
3494 {
3498 {
3502 }
3503 }
3507 /* Default align_* from the processor table. */
3509 {
3512 }
3514 {
3517 }
3519 {
3521 }
3523 /* Provide default for -mbranch-cost= value. */
3528 {
3531 /* Enable by default the SSE and MMX builtins. Do allow the user to
3532 explicitly disable any of these. In particular, disabling SSE and
3533 MMX for kernel code is extremely useful. */
3535 ix86_isa_flags
3541 }
3542 else
3543 {
3547 ix86_isa_flags
3550 /* i386 ABI does not specify red zone. It still makes sense to use it
3551 when programmer takes care to stack from being destroyed. */
3554 }
3556 /* Keep nonleaf frame pointers. */
3562 /* If we're doing fast math, we don't care about comparison order
3563 wrt NaNs. This lets us use a shorter comparison sequence. */
3567 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3568 since the insns won't need emulation. */
3572 /* Likewise, if the target doesn't have a 387, or we've specified
3573 software floating point, don't use 387 inline intrinsics. */
3577 /* Turn on MMX builtins for -msse. */
3581 /* Enable SSE prefetch. */
3585 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3589 /* Turn on lzcnt instruction for -mabm. */
3593 /* Validate -mpreferred-stack-boundary= value or default it to
3594 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3597 {
3603 {
3607 else
3610 }
3611 else
3612 ix86_preferred_stack_boundary
3614 }
3616 /* Set the default value for -mstackrealign. */
3622 /* Validate -mincoming-stack-boundary= value or default it to
3623 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3626 {
3631 else
3632 {
3633 ix86_user_incoming_stack_boundary
3635 ix86_incoming_stack_boundary
3637 }
3638 }
3640 /* Accept -msseregparm only if at least SSE support is enabled. */
3646 {
3648 {
3650 {
3653 }
3655 {
3658 }
3659 }
3660 }
3661 else
3664 /* If the i387 is disabled, then do not return values in it. */
3668 /* Use external vectorized library in vectorizing intrinsics. */
3671 {
3682 }
3690 /* ??? Unwind info is not correct around the CFG unless either a frame
3691 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3692 unwind info generation to be aware of the CFG and propagating states
3693 around edges. */
3696 && flag_omit_frame_pointer
3698 {
3704 }
3706 /* If stack probes are required, the space used for large function
3707 arguments on the stack must also be probed, so enable
3708 -maccumulate-outgoing-args so this happens in the prologue. */
3711 {
3716 }
3718 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3719 {
3725 }
3727 /* When scheduling description is not available, disable scheduler pass
3728 so it won't slow down the compilation and make x87 code slower. */
3749 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3751 && HAVE_prefetch
3756 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3757 can be optimized to ap = __builtin_next_arg (0). */
3762 {
3765 {
3768 ix86_gen_tls_local_dynamic_base_64
3770 }
3771 else
3772 {
3775 ix86_gen_tls_local_dynamic_base_64
3777 }
3778 }
3779 else
3780 {
3783 }
3786 {
3795 }
3796 else
3797 {
3806 }
3808 #ifdef USE_IX86_CLD
3809 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3812 #endif
3815 {
3820 }
3822 {
3826 }
3828 {
3829 #if defined(PROFILE_BEFORE_PROLOGUE)
3831 #else
3833 #endif
3834 }
3837 {
3838 /* When not optimize for size, enable vzeroupper optimization for
3839 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3840 AVX unaligned load/store. */
3842 {
3852 /* Enable 128-bit AVX instruction generation
3853 for the auto-vectorizer. */
3857 }
3858 }
3859 else
3860 {
3861 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3863 }
3866 {
3873 {
3876 {
3878 q++;
3879 }
3880 else
3885 else
3886 {
3889 {
3892 }
3895 {
3899 }
3900 }
3905 else
3907 }
3908 }
3915 /* Default long double to 64-bit for Bionic. */
3920 /* Save the initial options in case the user does function specific
3921 options. */
3923 target_option_default_node = target_option_current_node
3925 }
3927 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3929 static void
3931 {
3932 static struct register_pass_info insert_vzeroupper_info
3935 };
3940 /* This needs to be done at start up. It's convenient to do it here. */
3942 }
3944 /* Update register usage after having seen the compiler flags. */
3946 static void
3948 {
3952 /* The PIC register, if it exists, is fixed. */
3957 /* For 32-bit targets, squash the REX registers. */
3959 {
3964 }
3966 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3974 {
3975 /* Set/reset conditionally defined registers from
3976 CALL_USED_REGISTERS initializer. */
3980 /* Calculate registers of CLOBBERED_REGS register set
3981 as call used registers from GENERAL_REGS register set. */
3985 }
3987 /* If MMX is disabled, squash the registers. */
3993 /* If SSE is disabled, squash the registers. */
3999 /* If the FPU is disabled, squash the registers. */
4004 }
4006 \f
4007 /* Save the current options */
4009 static void
4011 {
4022 /* The fields are char but the variables are not; make sure the
4023 values fit in the fields. */
4028 }
4030 /* Restore the current options */
4032 static void
4034 {
4050 /* Recreate the arch feature tests if the arch changed */
4052 {
4057 }
4059 /* Recreate the tune optimization tests */
4061 {
4066 }
4067 }
4069 /* Print the current options */
4071 static void
4074 {
4096 {
4099 }
4100 }
4102 \f
4103 /* Inner function to process the attribute((target(...))), take an argument and
4104 set the current options from the argument. If we have a list, recursively go
4105 over the list. */
4107 static bool
4110 {
4114 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4115 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4116 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4117 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4118 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4120 enum ix86_opt_type
4121 {
4122 ix86_opt_unknown,
4123 ix86_opt_yes,
4124 ix86_opt_no,
4125 ix86_opt_str,
4126 ix86_opt_enum,
4127 ix86_opt_isa
4128 };
4130 static const struct
4131 {
4138 /* isa options */
4175 /* enum options */
4178 /* string options */
4182 /* flag options */
4184 OPT_mcld,
4185 MASK_CLD),
4188 OPT_mfancy_math_387,
4189 MASK_NO_FANCY_MATH_387),
4192 OPT_mieee_fp,
4193 MASK_IEEE_FP),
4196 OPT_minline_all_stringops,
4197 MASK_INLINE_ALL_STRINGOPS),
4200 OPT_minline_stringops_dynamically,
4201 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4204 OPT_mno_align_stringops,
4205 MASK_NO_ALIGN_STRINGOPS),
4208 OPT_mrecip,
4209 MASK_RECIP),
4211 };
4213 /* If this is a list, recurse to get the options. */
4215 {
4225 }
4228 {
4231 }
4233 /* Handle multiple arguments separated by commas. */
4237 {
4251 {
4255 }
4256 else
4257 {
4260 }
4262 /* Recognize no-xxx. */
4264 {
4268 }
4269 else
4272 /* Find the option. */
4276 {
4284 {
4289 }
4290 }
4292 /* Process the option. */
4294 {
4297 }
4300 {
4306 }
4309 {
4315 else
4317 }
4320 {
4322 {
4325 }
4326 else
4328 }
4331 {
4339 global_dc);
4340 else
4341 {
4344 }
4345 }
4347 else
4349 }
4352 }
4354 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4356 tree
4358 {
4373 /* Process each of the options on the chain. */
4378 /* If the changed options are different from the default, rerun
4379 ix86_option_override_internal, and then save the options away.
4380 The string options are are attribute options, and will be undone
4381 when we copy the save structure. */
4387 {
4388 /* If we are using the default tune= or arch=, undo the string assigned,
4389 and use the default. */
4400 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4404 {
4407 }
4409 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4412 /* Add any builtin functions with the new isa if any. */
4415 /* Save the current options unless we are validating options for
4416 #pragma. */
4423 /* Free up memory allocated to hold the strings */
4426 }
4429 }
4431 /* Hook to validate attribute((target("string"))). */
4433 static bool
4436 tree args,
4438 {
4442 /* attribute((target("default"))) does nothing, beyond
4443 affecting multi-versioning. */
4454 /* If the function changed the optimization levels as well as setting target
4455 options, start with the optimizations specified. */
4460 /* The target attributes may also change some optimization flags, so update
4461 the optimization options if necessary. */
4470 {
4475 }
4484 }
4486 \f
4487 /* Hook to determine if one function can safely inline another. */
4489 static bool
4491 {
4496 /* If callee has no option attributes, then it is ok to inline. */
4500 /* If caller has no option attributes, but callee does then it is not ok to
4501 inline. */
4505 else
4506 {
4510 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4511 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4512 function. */
4517 /* See if we have the same non-isa options. */
4521 /* See if arch, tune, etc. are the same. */
4534 else
4536 }
4539 }
4541 \f
4542 /* Remember the last target of ix86_set_current_function. */
4545 /* Establish appropriate back-end context for processing the function
4546 FNDECL. The argument might be NULL to indicate processing at top
4547 level, outside of any function scope. */
4548 static void
4550 {
4551 /* Only change the context if the function changes. This hook is called
4552 several times in the course of compiling a function, and we don't want to
4553 slow things down too much or call target_reinit when it isn't safe. */
4555 {
4556 tree old_tree = (ix86_previous_fndecl
4560 tree new_tree = (fndecl
4566 ;
4569 {
4573 }
4576 {
4582 }
4583 }
4584 }
4586 \f
4587 /* Return true if this goes in large data/bss. */
4589 static bool
4591 {
4595 /* Functions are never large data. */
4600 {
4606 }
4607 else
4608 {
4611 /* If this is an incomplete type with size 0, then we can't put it
4612 in data because it might be too big when completed. */
4615 }
4618 }
4620 /* Switch to the appropriate section for output of DECL.
4621 DECL is either a `VAR_DECL' node or a constant of some sort.
4622 RELOC indicates whether forming the initial value of DECL requires
4623 link-time relocations. */
4626 ATTRIBUTE_UNUSED;
4631 {
4634 {
4638 {
4672 /* We don't split these for medium model. Place them into
4673 default sections and hope for best. */
4675 }
4677 {
4678 /* We might get called with string constants, but get_named_section
4679 doesn't like them as they are not DECLs. Also, we need to set
4680 flags in that case. */
4684 }
4685 }
4687 }
4689 /* Build up a unique section name, expressed as a
4690 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4691 RELOC indicates whether the initial value of EXP requires
4692 link-time relocations. */
4694 static void ATTRIBUTE_UNUSED
4696 {
4699 {
4701 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4705 {
4729 /* We don't split these for medium model. Place them into
4730 default sections and hope for best. */
4732 }
4734 {
4741 /* If we're using one_only, then there needs to be a .gnu.linkonce
4742 prefix to the section name. */
4749 }
4750 }
4752 }
4754 #ifdef COMMON_ASM_OP
4755 /* This says how to output assembler code to declare an
4756 uninitialized external linkage data object.
4758 For medium model x86-64 we need to use .largecomm opcode for
4759 large objects. */
4760 void
4764 {
4768 else
4773 }
4774 #endif
4776 /* Utility function for targets to use in implementing
4777 ASM_OUTPUT_ALIGNED_BSS. */
4779 void
4783 {
4787 else
4790 #ifdef ASM_DECLARE_OBJECT_NAME
4793 #else
4794 /* Standard thing is just output label for the object. */
4798 }
4799 \f
4800 /* Decide whether we must probe the stack before any space allocation
4801 on this target. It's essentially TARGET_STACK_PROBE except when
4802 -fstack-check causes the stack to be already probed differently. */
4804 bool
4806 {
4807 /* Do not probe the stack twice if static stack checking is enabled. */
4812 }
4813 \f
4814 /* Decide whether we can make a sibling call to a function. DECL is the
4815 declaration of the function being targeted by the call and EXP is the
4816 CALL_EXPR representing the call. */
4818 static bool
4820 {
4824 /* If we are generating position-independent code, we cannot sibcall
4825 optimize any indirect call, or a direct call to a global function,
4826 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4828 && !TARGET_64BIT
4829 && flag_pic
4833 /* If we need to align the outgoing stack, then sibcalling would
4834 unalign the stack, which may break the called function. */
4840 {
4843 }
4844 else
4845 {
4846 /* We're looking at the CALL_EXPR, we need the type of the function. */
4851 }
4853 /* Check that the return value locations are the same. Like
4854 if we are returning floats on the 80387 register stack, we cannot
4855 make a sibcall from a function that doesn't return a float to a
4856 function that does or, conversely, from a function that does return
4857 a float to a function that doesn't; the necessary stack adjustment
4858 would not be executed. This is also the place we notice
4859 differences in the return value ABI. Note that it is ok for one
4860 of the functions to have void return type as long as the return
4861 value of the other is passed in a register. */
4866 {
4869 }
4871 ;
4876 {
4877 /* The SYSV ABI has more call-clobbered registers;
4878 disallow sibcalls from MS to SYSV. */
4882 }
4883 else
4884 {
4885 /* If this call is indirect, we'll need to be able to use a
4886 call-clobbered register for the address of the target function.
4887 Make sure that all such registers are not used for passing
4888 parameters. Note that DLLIMPORT functions are indirect. */
4891 {
4893 {
4894 /* ??? Need to count the actual number of registers to be used,
4895 not the possible number of registers. Fix later. */
4897 }
4898 }
4899 }
4901 /* Otherwise okay. That also includes certain types of indirect calls. */
4903 }
4905 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4906 and "sseregparm" calling convention attributes;
4907 arguments as in struct attribute_spec.handler. */
4909 static tree
4911 tree args,
4914 {
4919 {
4921 name);
4924 }
4926 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4928 {
4929 tree cst;
4932 {
4934 }
4937 {
4939 }
4943 {
4946 name);
4948 }
4950 {
4954 }
4957 }
4960 {
4961 /* Do not warn when emulating the MS ABI. */
4966 name);
4969 }
4971 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4973 {
4975 {
4977 }
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine stdcall with fastcall (redundant), regparm and
4993 sseregparm. */
4995 {
4997 {
4999 }
5001 {
5003 }
5005 {
5007 }
5008 }
5010 /* Can combine cdecl with regparm and sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 {
5030 name);
5032 {
5034 }
5036 {
5038 }
5040 {
5042 }
5043 }
5045 /* Can combine sseregparm with all attributes. */
5048 }
5050 /* The transactional memory builtins are implicitly regparm or fastcall
5051 depending on the ABI. Override the generic do-nothing attribute that
5052 these builtins were declared with, and replace it with one of the two
5053 attributes that we expect elsewhere. */
5055 static tree
5057 tree args ATTRIBUTE_UNUSED,
5060 {
5061 tree alt;
5063 /* In no case do we want to add the placeholder attribute. */
5066 /* The 64-bit ABI is unchanged for transactional memory. */
5070 /* ??? Is there a better way to validate 32-bit windows? We have
5071 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5074 else
5075 {
5078 }
5082 }
5084 /* This function determines from TYPE the calling-convention. */
5086 unsigned int
5088 {
5091 tree attrs;
5098 {
5108 /* Regparam isn't allowed for thiscall and fastcall. */
5110 {
5115 }
5119 }
5126 || is_stdarg
5132 }
5134 /* Return 0 if the attributes for two types are incompatible, 1 if they
5135 are compatible, and 2 if they are nearly compatible (which causes a
5136 warning to be generated). */
5138 static int
5140 {
5156 }
5157 \f
5158 /* Return the regparm value for a function with the indicated TYPE and DECL.
5159 DECL may be NULL when calling function indirectly
5160 or considering a libcall. */
5162 static int
5164 {
5165 tree attr;
5176 {
5179 {
5182 }
5183 }
5189 /* Use register calling convention for local functions when possible. */
5192 && optimize
5194 {
5195 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5198 {
5201 /* Make sure no regparm register is taken by a
5202 fixed register variable. */
5207 /* We don't want to use regparm(3) for nested functions as
5208 these use a static chain pointer in the third argument. */
5212 /* In 32-bit mode save a register for the split stack. */
5216 /* Each fixed register usage increases register pressure,
5217 so less registers should be used for argument passing.
5218 This functionality can be overriden by an explicit
5219 regparm value. */
5222 globals++;
5224 local_regparm
5229 }
5230 }
5233 }
5235 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5236 DFmode (2) arguments in SSE registers for a function with the
5237 indicated TYPE and DECL. DECL may be NULL when calling function
5238 indirectly or considering a libcall. Otherwise return 0. */
5240 static int
5242 {
5245 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5246 by the sseregparm attribute. */
5249 {
5251 {
5253 {
5257 else
5260 }
5262 }
5265 }
5267 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5268 (and DFmode for SSE2) arguments in SSE registers. */
5271 {
5272 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5276 }
5279 }
5281 /* Return true if EAX is live at the start of the function. Used by
5282 ix86_expand_prologue to determine if we need special help before
5283 calling allocate_stack_worker. */
5285 static bool
5287 {
5288 /* Cheat. Don't bother working forward from ix86_function_regparm
5289 to the function type to whether an actual argument is located in
5290 eax. Instead just look at cfg info, which is still close enough
5291 to correct at this point. This gives false positives for broken
5292 functions that might use uninitialized data that happens to be
5293 allocated in eax, but who cares? */
5295 }
5297 static bool
5299 {
5300 tree attr;
5303 {
5309 /* For 32-bit MS-ABI the default is to keep aggregate
5310 return pointer. */
5313 }
5315 }
5317 /* Value is the number of bytes of arguments automatically
5318 popped when returning from a subroutine call.
5319 FUNDECL is the declaration node of the function (as a tree),
5320 FUNTYPE is the data type of the function (as a tree),
5321 or for a library call it is an identifier node for the subroutine name.
5322 SIZE is the number of bytes of arguments passed on the stack.
5324 On the 80386, the RTD insn may be used to pop them if the number
5325 of args is fixed, but if the number is variable then the caller
5326 must pop them all. RTD can't be used for library calls now
5327 because the library is compiled with the Unix compiler.
5328 Use of RTD is a selectable option, since it is incompatible with
5329 standard Unix calling sequences. If the option is not selected,
5330 the caller must always pop the args.
5332 The attribute stdcall is equivalent to RTD on a per module basis. */
5334 static int
5336 {
5339 /* None of the 64-bit ABIs pop arguments. */
5350 /* Lose any fake structure return argument if it is passed on the stack. */
5353 {
5357 }
5360 }
5362 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5364 static bool
5366 {
5367 /* Check operand constraints in case hard registers were propagated
5368 into insn pattern. This check prevents combine pass from
5369 generating insn patterns with invalid hard register operands.
5370 These invalid insns can eventually confuse reload to error out
5371 with a spill failure. See also PRs 46829 and 46843. */
5373 {
5380 {
5388 /* A unary operator may be accepted by the predicate, but it
5389 is irrelevant for matching constraints. */
5394 {
5402 }
5409 /* Operand has no constraints, anything is OK. */
5413 {
5416 && operands_match_p
5420 {
5423 }
5424 }
5428 }
5429 }
5432 }
5433 \f
5434 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5436 static unsigned HOST_WIDE_INT
5438 {
5440 }
5441 \f
5442 /* Argument support functions. */
5444 /* Return true when register may be used to pass function parameters. */
5445 bool
5447 {
5452 {
5456 else
5462 }
5465 {
5468 }
5469 else
5470 {
5474 }
5476 /* TODO: The function should depend on current function ABI but
5477 builtins.c would need updating then. Therefore we use the
5478 default ABI. */
5480 /* RAX is used as hidden argument to va_arg functions. */
5486 else
5493 }
5495 /* Return if we do not know how to pass TYPE solely in registers. */
5497 static bool
5499 {
5503 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5504 The layout_type routine is crafty and tries to trick us into passing
5505 currently unsupported vector types on the stack by using TImode. */
5508 }
5510 /* It returns the size, in bytes, of the area reserved for arguments passed
5511 in registers for the function represented by fndecl dependent to the used
5512 abi format. */
5513 int
5515 {
5519 else
5524 }
5526 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5527 call abi used. */
5528 enum calling_abi
5530 {
5532 {
5535 {
5538 }
5542 }
5544 }
5546 static bool
5548 {
5550 {
5554 else
5556 }
5558 }
5560 static enum calling_abi
5562 {
5566 }
5568 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5569 call abi used. */
5570 enum calling_abi
5572 {
5576 }
5578 /* Write the extra assembler code needed to declare a function properly. */
5580 void
5582 tree decl)
5583 {
5587 {
5593 }
5595 #ifdef SUBTARGET_ASM_UNWIND_INIT
5597 #endif
5601 /* Output magic byte marker, if hot-patch attribute is set. */
5603 {
5605 {
5606 /* leaq [%rsp + 0], %rsp */
5609 }
5610 else
5611 {
5612 /* movl.s %edi, %edi
5613 push %ebp
5614 movl.s %esp, %ebp */
5617 }
5618 }
5619 }
5621 /* regclass.c */
5624 /* Implementation of call abi switching target hook. Specific to FNDECL
5625 the specific call register sets are set. See also
5626 ix86_conditional_register_usage for more details. */
5627 void
5629 {
5632 else
5634 }
5636 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5637 expensive re-initialization of init_regs each time we switch function context
5638 since this is needed only during RTL expansion. */
5639 static void
5641 {
5645 }
5647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5648 for a call to a function whose data type is FNTYPE.
5649 For a library call, FNTYPE is 0. */
5651 void
5655 tree fndecl,
5657 {
5663 {
5666 }
5667 else
5668 {
5671 }
5675 /* Set up the number of registers to use for passing arguments. */
5682 {
5684 ? X86_64_REGPARM_MAX
5686 }
5688 {
5691 {
5693 ? X86_64_SSE_REGPARM_MAX
5695 }
5696 }
5703 /* Because type might mismatch in between caller and callee, we need to
5704 use actual type of function for local calls.
5705 FIXME: cgraph_analyze can be told to actually record if function uses
5706 va_start so for local functions maybe_vaarg can be made aggressive
5707 helping K&R code.
5708 FIXME: once typesytem is fixed, we won't need this code anymore. */
5716 {
5717 /* If there are variable arguments, then we won't pass anything
5718 in registers in 32-bit mode. */
5720 {
5728 }
5730 /* Use ecx and edx registers if function has fastcall attribute,
5731 else look for regparm information. */
5733 {
5736 {
5739 }
5741 {
5744 }
5745 else
5747 }
5749 /* Set up the number of SSE registers used for passing SFmode
5750 and DFmode arguments. Warn for mismatching ABI. */
5752 }
5753 }
5755 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5756 But in the case of vector types, it is some vector mode.
5758 When we have only some of our vector isa extensions enabled, then there
5759 are some modes for which vector_mode_supported_p is false. For these
5760 modes, the generic vector support in gcc will choose some non-vector mode
5761 in order to implement the type. By computing the natural mode, we'll
5762 select the proper ABI location for the operand and not depend on whatever
5763 the middle-end decides to do with these vector types.
5765 The midde-end can't deal with the vector types > 16 bytes. In this
5766 case, we return the original mode and warn ABI change if CUM isn't
5767 NULL. */
5769 static enum machine_mode
5771 {
5775 {
5778 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5780 {
5785 else
5788 /* Get the mode which has this inner mode and number of units. */
5792 {
5794 {
5798 && !warnedavx
5800 {
5804 }
5806 }
5808 {
5812 && !warnedsse
5814 {
5818 }
5820 }
5821 else
5823 }
5826 }
5827 }
5830 }
5832 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5833 this may not agree with the mode that the type system has chosen for the
5834 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5835 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5837 static rtx
5840 {
5841 rtx tmp;
5845 else
5846 {
5850 }
5853 }
5855 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5856 of this code is to classify each 8bytes of incoming argument by the register
5857 class and assign registers accordingly. */
5859 /* Return the union class of CLASS1 and CLASS2.
5860 See the x86-64 PS ABI for details. */
5862 static enum x86_64_reg_class
5864 {
5865 /* Rule #1: If both classes are equal, this is the resulting class. */
5869 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5870 the other class. */
5876 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5880 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5888 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5889 MEMORY is used. */
5898 /* Rule #6: Otherwise class SSE is used. */
5900 }
5902 /* Classify the argument of type TYPE and mode MODE.
5903 CLASSES will be filled by the register class used to pass each word
5904 of the operand. The number of words is returned. In case the parameter
5905 should be passed in memory, 0 is returned. As a special case for zero
5906 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5908 BIT_OFFSET is used internally for handling records and specifies offset
5909 of the offset in bits modulo 256 to avoid overflow cases.
5911 See the x86-64 PS ABI for details.
5912 */
5914 static int
5917 {
5918 HOST_WIDE_INT bytes =
5920 int words
5923 /* Variable sized entities are always passed/returned in memory. */
5932 {
5934 tree field;
5937 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5944 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5945 signalize memory class, so handle it as special case. */
5947 {
5950 }
5952 /* Classify each field of record and merge classes. */
5954 {
5956 /* And now merge the fields of structure. */
5958 {
5960 {
5966 /* Bitfields are always classified as integer. Handle them
5967 early, since later code would consider them to be
5968 misaligned integers. */
5970 {
5979 }
5980 else
5981 {
5986 /* Flexible array member is ignored. */
5993 {
5997 {
6000 "the ABI of passing struct with"
6001 " a flexible array member has"
6003 }
6005 }
6007 subclasses,
6017 }
6018 }
6019 }
6023 /* Arrays are handled as small records. */
6024 {
6031 /* The partial classes are now full classes. */
6042 }
6045 /* Unions are similar to RECORD_TYPE but offset is always 0.
6046 */
6048 {
6050 {
6058 bit_offset);
6063 }
6064 }
6069 }
6072 {
6073 /* When size > 16 bytes, if the first one isn't
6074 X86_64_SSE_CLASS or any other ones aren't
6075 X86_64_SSEUP_CLASS, everything should be passed in
6076 memory. */
6083 }
6085 /* Final merger cleanup. */
6087 {
6088 /* If one class is MEMORY, everything should be passed in
6089 memory. */
6093 /* The X86_64_SSEUP_CLASS should be always preceded by
6094 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6098 {
6099 /* The first one should never be X86_64_SSEUP_CLASS. */
6102 }
6104 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6105 everything should be passed in memory. */
6108 {
6111 /* The first one should never be X86_64_X87UP_CLASS. */
6114 {
6117 "the ABI of passing union with long double"
6119 }
6121 }
6122 }
6124 }
6126 /* Compute alignment needed. We align all types to natural boundaries with
6127 exception of XFmode that is aligned to 64bits. */
6129 {
6138 /* Misaligned fields are always returned in memory. */
6141 }
6143 /* for V1xx modes, just use the base mode */
6148 /* Classification of atomic types. */
6150 {
6166 {
6170 {
6173 }
6175 {
6178 }
6180 {
6184 }
6186 {
6189 }
6190 else
6192 }
6199 /* OImode shouldn't be used directly. */
6206 else
6224 else
6225 {
6229 {
6232 "the ABI of passing structure with complex float"
6234 }
6237 }
6246 /* This modes is larger than 16 bytes. */
6289 else
6293 }
6294 }
6296 /* Examine the argument and return set number of register required in each
6297 class. Return 0 iff parameter should be passed in memory. */
6298 static int
6301 {
6311 {
6333 }
6335 }
6337 /* Construct container for the argument used by GCC interface. See
6338 FUNCTION_ARG for the detailed description. */
6340 static rtx
6344 {
6345 /* The following variables hold the static issued_error state. */
6359 rtx ret;
6370 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6371 some less clueful developer tries to use floating-point anyway. */
6373 {
6375 {
6377 {
6380 }
6381 }
6383 {
6386 }
6388 }
6390 /* Likewise, error if the ABI requires us to return values in the
6391 x87 registers and the user specified -mno-80387. */
6397 {
6399 {
6402 }
6404 }
6406 /* First construct simple cases. Avoid SCmode, since we want to use
6407 single register to pass this type. */
6410 {
6425 /* Zero sized array, struct or class. */
6429 }
6456 /* Otherwise figure out the entries of the PARALLEL. */
6458 {
6462 {
6467 /* Merge TImodes on aligned occasions here too. */
6469 tmpmode
6473 else
6475 /* We've requested 24 bytes we
6476 don't have mode for. Use DImode. */
6483 intreg++;
6491 sse_regno++;
6499 sse_regno++;
6504 {
6510 {
6512 i++;
6513 }
6514 else
6527 }
6533 sse_regno++;
6537 }
6538 }
6540 /* Empty aligned struct, union or class. */
6548 }
6550 /* Update the data in CUM to advance over an argument of mode MODE
6551 and data type TYPE. (TYPE is null for libcalls where that information
6552 may not be available.) */
6554 static void
6557 HOST_WIDE_INT words)
6558 {
6560 {
6567 /* FALLTHRU */
6578 {
6581 }
6585 /* OImode shouldn't be used directly. */
6594 /* FALLTHRU */
6610 {
6615 {
6618 }
6619 }
6629 {
6634 {
6637 }
6638 }
6640 }
6641 }
6643 static void
6646 {
6649 /* Unnamed 256bit vector mode parameters are passed on stack. */
6655 {
6660 }
6661 else
6662 {
6666 }
6667 }
6669 static void
6671 HOST_WIDE_INT words)
6672 {
6673 /* Otherwise, this should be passed indirect. */
6678 {
6681 }
6682 }
6684 /* Update the data in CUM to advance over an argument of mode MODE and
6685 data type TYPE. (TYPE is null for libcalls where that information
6686 may not be available.) */
6688 static void
6691 {
6697 else
6708 else
6710 }
6712 /* Define where to put the arguments to a function.
6713 Value is zero to push the argument on the stack,
6714 or a hard register in which to store the argument.
6716 MODE is the argument's machine mode.
6717 TYPE is the data type of the argument (as a tree).
6718 This is null for libcalls where that information may
6719 not be available.
6720 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6721 the preceding args and about the function being called.
6722 NAMED is nonzero if this argument is a named parameter
6723 (otherwise it is an extra parameter matching an ellipsis). */
6725 static rtx
6729 {
6732 /* Avoid the AL settings for the Unix64 ABI. */
6737 {
6744 /* FALLTHRU */
6750 {
6753 /* Fastcall allocates the first two DWORD (SImode) or
6754 smaller arguments to ECX and EDX if it isn't an
6755 aggregate type . */
6757 {
6763 /* ECX not EAX is the first allocated register. */
6766 }
6768 }
6777 /* FALLTHRU */
6779 /* In 32bit, we pass TImode in xmm registers. */
6787 {
6789 {
6793 }
6797 }
6801 /* OImode shouldn't be used directly. */
6811 {
6815 }
6825 {
6827 {
6831 }
6835 }
6837 }
6840 }
6842 static rtx
6845 {
6846 /* Handle a hidden AL argument containing number of registers
6847 for varargs x86-64 functions. */
6851 ? X86_64_SSE_REGPARM_MAX
6856 {
6866 /* Unnamed 256bit vector mode parameters are passed on stack. */
6870 }
6876 }
6878 static rtx
6881 HOST_WIDE_INT bytes)
6882 {
6885 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6886 We use value of -2 to specify that current function call is MSABI. */
6890 /* If we've run out of registers, it goes on the stack. */
6896 /* Only floating point modes are passed in anything but integer regs. */
6898 {
6901 else
6902 {
6905 /* Unnamed floating parameters are passed in both the
6906 SSE and integer registers. */
6912 }
6913 }
6914 /* Handle aggregated types passed in register. */
6916 {
6921 }
6924 }
6926 /* Return where to put the arguments to a function.
6927 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6929 MODE is the argument's machine mode. TYPE is the data type of the
6930 argument. It is null for libcalls where that information may not be
6931 available. CUM gives information about the preceding args and about
6932 the function being called. NAMED is nonzero if this argument is a
6933 named parameter (otherwise it is an extra parameter matching an
6934 ellipsis). */
6936 static rtx
6939 {
6943 rtx arg;
6947 else
6951 /* To simplify the code below, represent vector types with a vector mode
6952 even if MMX/SSE are not active. */
6960 else
6964 }
6966 /* A C expression that indicates when an argument must be passed by
6967 reference. If nonzero for an argument, a copy of that argument is
6968 made in memory and a pointer to the argument is passed instead of
6969 the argument itself. The pointer is passed in whatever way is
6970 appropriate for passing a pointer to that type. */
6972 static bool
6976 {
6979 /* See Windows x64 Software Convention. */
6981 {
6984 {
6985 /* Arrays are passed by reference. */
6990 {
6991 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6992 are passed by reference. */
6994 }
6995 }
6997 /* __m128 is passed by reference. */
7003 }
7004 }
7009 }
7011 /* Return true when TYPE should be 128bit aligned for 32bit argument
7012 passing ABI. XXX: This function is obsolete and is only used for
7013 checking psABI compatibility with previous versions of GCC. */
7015 static bool
7017 {
7029 {
7030 /* Walk the aggregates recursively. */
7032 {
7036 {
7037 tree field;
7039 /* Walk all the structure fields. */
7041 {
7045 }
7047 }
7050 /* Just for use if some languages passes arrays by value. */
7057 }
7058 }
7060 }
7062 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7063 XXX: This function is obsolete and is only used for checking psABI
7064 compatibility with previous versions of GCC. */
7066 static unsigned int
7069 {
7070 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7071 natural boundaries. */
7073 {
7074 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7075 make an exception for SSE modes since these require 128bit
7076 alignment.
7078 The handling here differs from field_alignment. ICC aligns MMX
7079 arguments to 4 byte boundaries, while structure fields are aligned
7080 to 8 byte boundaries. */
7082 {
7085 }
7086 else
7087 {
7090 }
7091 }
7095 }
7097 /* Return true when TYPE should be 128bit aligned for 32bit argument
7098 passing ABI. */
7100 static bool
7102 {
7112 {
7113 /* Walk the aggregates recursively. */
7115 {
7119 {
7120 tree field;
7122 /* Walk all the structure fields. */
7124 field;
7126 {
7130 }
7132 }
7135 /* Just for use if some languages passes arrays by value. */
7142 }
7143 }
7144 else
7148 }
7150 /* Gives the alignment boundary, in bits, of an argument with the
7151 specified mode and type. */
7153 static unsigned int
7155 {
7158 {
7159 /* Since the main variant type is used for call, we convert it to
7160 the main variant type. */
7163 }
7164 else
7168 else
7169 {
7174 {
7175 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7177 {
7180 }
7186 }
7189 && !warned
7191 saved_align))
7192 {
7195 "The ABI for passing parameters with %d-byte"
7198 }
7199 }
7202 }
7204 /* Return true if N is a possible register number of function value. */
7206 static bool
7208 {
7210 {
7215 /* TODO: The function should depend on current function ABI but
7216 builtins.c would need updating then. Therefore we use the
7217 default ABI. */
7229 }
7232 }
7234 /* Define how to find the value returned by a function.
7235 VALTYPE is the data type of the value (as a tree).
7236 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7237 otherwise, FUNC is 0. */
7239 static rtx
7242 {
7245 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7246 we normally prevent this case when mmx is not available. However
7247 some ABIs may require the result to be returned like DImode. */
7251 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7252 we prevent this case when sse is not available. However some ABIs
7253 may require the result to be returned like integer TImode. */
7258 /* 32-byte vector modes in %ymm0. */
7262 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7265 else
7266 /* Most things go in %eax. */
7269 /* Override FP return register with %xmm0 for local functions when
7270 SSE math is enabled or for functions with sseregparm attribute. */
7272 {
7277 }
7279 /* OImode shouldn't be used directly. */
7283 }
7285 static rtx
7287 const_tree valtype)
7288 {
7289 rtx ret;
7291 /* Handle libcalls, which don't provide a type node. */
7293 {
7297 {
7316 }
7319 }
7321 {
7322 /* Pointers are always returned in word_mode. */
7324 }
7330 /* For zero sized structures, construct_container returns NULL, but we
7331 need to keep rest of compiler happy by returning meaningful value. */
7336 }
7338 static rtx
7340 const_tree valtype)
7341 {
7345 {
7347 {
7366 }
7367 }
7369 }
7371 static rtx
7374 {
7386 else
7388 }
7390 static rtx
7393 {
7399 }
7401 /* Pointer function arguments and return values are promoted to
7402 word_mode. */
7404 static enum machine_mode
7408 {
7410 {
7413 }
7415 for_return);
7416 }
7418 /* Return true if a structure, union or array with MODE containing FIELD
7419 should be accessed using BLKmode. */
7421 static bool
7423 {
7424 /* Union with XFmode must be in BLKmode. */
7428 }
7430 rtx
7432 {
7434 }
7436 /* Return true iff type is returned in memory. */
7438 static bool ATTRIBUTE_UNUSED
7440 {
7441 HOST_WIDE_INT size;
7452 {
7453 /* User-created vectors small enough to fit in EAX. */
7457 /* MMX/3dNow values are returned in MM0,
7458 except when it doesn't exits or the ABI prescribes otherwise. */
7462 /* SSE values are returned in XMM0, except when it doesn't exist. */
7466 /* AVX values are returned in YMM0, except when it doesn't exist. */
7469 }
7477 /* OImode shouldn't be used directly. */
7481 }
7483 static bool ATTRIBUTE_UNUSED
7485 {
7488 }
7490 static bool ATTRIBUTE_UNUSED
7492 {
7495 /* __m128 is returned in xmm0. */
7502 /* Otherwise, the size must be exactly in [1248]. */
7504 }
7506 static bool
7508 {
7509 #ifdef SUBTARGET_RETURN_IN_MEMORY
7511 #else
7515 {
7518 else
7520 }
7521 else
7523 #endif
7524 }
7526 /* When returning SSE vector types, we have a choice of either
7527 (1) being abi incompatible with a -march switch, or
7528 (2) generating an error.
7529 Given no good solution, I think the safest thing is one warning.
7530 The user won't be able to use -Werror, but....
7532 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7533 called in response to actually generating a caller or callee that
7534 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7535 via aggregate_value_p for general type probing from tree-ssa. */
7537 static rtx
7539 {
7543 {
7544 /* Look at the return type of the function, not the function type. */
7548 {
7551 {
7555 }
7556 }
7559 {
7561 {
7565 }
7566 }
7567 }
7570 }
7572 \f
7573 /* Create the va_list data type. */
7575 /* Returns the calling convention specific va_list date type.
7576 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7578 static tree
7580 {
7583 /* For i386 we use plain pointer to argument area. */
7593 unsigned_type_node);
7596 unsigned_type_node);
7599 ptr_type_node);
7602 ptr_type_node);
7621 /* The correct type is an array type of one element. */
7623 }
7625 /* Setup the builtin va_list data type and for 64-bit the additional
7626 calling convention specific va_list data types. */
7628 static tree
7630 {
7633 /* Initialize abi specific va_list builtin types. */
7635 {
7636 tree t;
7638 {
7643 }
7644 else
7645 {
7650 }
7652 {
7657 }
7658 else
7659 {
7664 }
7665 }
7668 }
7670 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7672 static void
7674 {
7676 alias_set_type set;
7679 /* GPR size of varargs save area. */
7682 else
7685 /* FPR size of varargs save area. We don't need it if we don't pass
7686 anything in SSE registers. */
7689 else
7703 {
7711 }
7714 {
7718 /* Now emit code to save SSE registers. The AX parameter contains number
7719 of SSE parameter registers used to call this function, though all we
7720 actually check here is the zero/non-zero status. */
7725 label));
7727 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7728 we used movdqa (i.e. TImode) instead? Perhaps even better would
7729 be if we could determine the real mode of the data, via a hook
7730 into pass_stdarg. Ignore all that for now. */
7740 {
7749 }
7752 }
7753 }
7755 static void
7757 {
7761 /* Reset to zero, as there might be a sysv vaarg used
7762 before. */
7767 {
7778 }
7779 }
7781 static void
7785 {
7787 CUMULATIVE_ARGS next_cum;
7788 tree fntype;
7790 /* This argument doesn't appear to be used anymore. Which is good,
7791 because the old code here didn't suppress rtl generation. */
7799 /* For varargs, we do not want to skip the dummy va_dcl argument.
7800 For stdargs, we do want to skip the last named argument. */
7808 else
7810 }
7812 /* Checks if TYPE is of kind va_list char *. */
7814 static bool
7816 {
7817 tree canonic;
7819 /* For 32-bit it is always true. */
7825 }
7827 /* Implement va_start. */
7829 static void
7831 {
7835 tree type;
7836 rtx ovf_rtx;
7840 {
7843 /* When we are splitting the stack, we can't refer to the stack
7844 arguments using internal_arg_pointer, because they may be on
7845 the old stack. The split stack prologue will arrange to
7846 leave a pointer to the old stack arguments in a scratch
7847 register, which we here copy to a pseudo-register. The split
7848 stack prologue can't set the pseudo-register directly because
7849 it (the prologue) runs before any registers have been saved. */
7853 {
7867 }
7868 }
7870 /* Only 64bit target needs something special. */
7872 {
7875 else
7876 {
7885 }
7887 }
7896 /* The following should be folded into the MEM_REF offset. */
7906 /* Count number of gp and fp argument registers used. */
7912 {
7918 }
7921 {
7927 }
7929 /* Find the overflow area. */
7933 else
7943 {
7944 /* Find the register save area.
7945 Prologue of the function save it right above stack frame. */
7953 }
7954 }
7956 /* Implement va_arg. */
7958 static tree
7961 {
7968 rtx container;
7970 tree ptrtype;
7974 /* Only 64bit target needs something special. */
7998 {
8005 /* Unnamed 256bit vector mode parameters are passed on stack. */
8007 {
8010 }
8018 }
8020 /* Pull the value out of the saved registers. */
8025 {
8039 /* In case we are passing structure, verify that it is consecutive block
8040 on the register save area. If not we need to do moves. */
8042 {
8043 /* Verify that all registers are strictly consecutive */
8045 {
8049 {
8054 }
8055 }
8056 else
8057 {
8061 {
8066 }
8067 }
8068 }
8070 {
8073 }
8074 else
8075 {
8078 }
8080 /* First ensure that we fit completely in registers. */
8082 {
8089 }
8091 {
8099 }
8101 /* Compute index to start of area used for integer regs. */
8103 {
8104 /* int_addr = gpr + sav; */
8107 }
8109 {
8110 /* sse_addr = fpr + sav; */
8113 }
8115 {
8119 /* addr = &temp; */
8124 {
8128 tree piece_type;
8129 tree addr_type;
8130 tree daddr_type;
8139 {
8144 }
8148 else
8155 {
8158 }
8159 else
8160 {
8163 }
8170 {
8175 }
8176 else
8177 {
8178 tree copy
8183 }
8185 }
8186 }
8189 {
8193 }
8196 {
8200 }
8205 }
8207 /* ... otherwise out of the overflow area. */
8209 /* When we align parameter on stack for caller, if the parameter
8210 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8211 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8212 here with caller. */
8217 /* Care for on-stack alignment if needed. */
8220 else
8221 {
8226 }
8243 }
8244 \f
8245 /* Return true if OPNUM's MEM should be matched
8246 in movabs* patterns. */
8248 bool
8250 {
8262 }
8263 \f
8264 /* Initialize the table of extra 80387 mathematical constants. */
8266 static void
8268 {
8270 {
8276 };
8280 {
8282 /* Ensure each constant is rounded to XFmode precision. */
8285 }
8288 }
8290 /* Return non-zero if the constant is something that
8291 can be loaded with a special instruction. */
8293 int
8295 {
8298 REAL_VALUE_TYPE r;
8310 /* For XFmode constants, try to find a special 80387 instruction when
8311 optimizing for size or on those CPUs that benefit from them. */
8314 {
8323 }
8325 /* Load of the constant -0.0 or -1.0 will be split as
8326 fldz;fchs or fld1;fchs sequence. */
8333 }
8335 /* Return the opcode of the special instruction to be used to load
8336 the constant X. */
8340 {
8342 {
8362 }
8363 }
8365 /* Return the CONST_DOUBLE representing the 80387 constant that is
8366 loaded by the specified special instruction. The argument IDX
8367 matches the return value from standard_80387_constant_p. */
8369 rtx
8371 {
8378 {
8389 }
8392 XFmode);
8393 }
8395 /* Return 1 if X is all 0s and 2 if x is all 1s
8396 in supported SSE/AVX vector mode. */
8398 int
8400 {
8407 {
8422 }
8425 }
8427 /* Return the opcode of the special instruction to be used to load
8428 the constant X. */
8432 {
8434 {
8437 {
8454 }
8459 else
8464 }
8466 }
8468 /* Returns true if OP contains a symbol reference */
8470 bool
8472 {
8481 {
8483 {
8489 }
8493 }
8496 }
8498 /* Return true if it is appropriate to emit `ret' instructions in the
8499 body of a function. Do this only if the epilogue is simple, needing a
8500 couple of insns. Prior to reloading, we can't tell how many registers
8501 must be saved, so return false then. Return false if there is no frame
8502 marker to de-allocate. */
8504 bool
8506 {
8512 /* Don't allow more than 32k pop, since that's all we can do
8513 with one instruction. */
8520 }
8521 \f
8522 /* Value should be nonzero if functions must have frame pointers.
8523 Zero means the frame pointer need not be set up (and parms may
8524 be accessed via the stack pointer) in functions that seem suitable. */
8526 static bool
8528 {
8529 /* If we accessed previous frames, then the generated code expects
8530 to be able to access the saved ebp value in our frame. */
8534 /* Several x86 os'es need a frame pointer for other reasons,
8535 usually pertaining to setjmp. */
8539 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8543 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8544 allocation is 4GB. */
8548 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8549 turns off the frame pointer by default. Turn it back on now if
8550 we've not got a leaf function. */
8560 }
8562 /* Record that the current function accesses previous call frames. */
8564 void
8566 {
8568 }
8569 \f
8570 #ifndef USE_HIDDEN_LINKONCE
8571 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8572 # define USE_HIDDEN_LINKONCE 1
8573 # else
8574 # define USE_HIDDEN_LINKONCE 0
8575 # endif
8576 #endif
8580 /* Fills in the label name that should be used for a pc thunk for
8581 the given register. */
8583 static void
8585 {
8590 else
8592 }
8595 /* This function generates code for -fpic that loads %ebx with
8596 the return address of the caller and then returns. */
8598 static void
8600 {
8605 {
8607 tree decl;
8623 #if TARGET_MACHO
8625 {
8634 }
8635 else
8636 #endif
8638 {
8649 }
8650 else
8651 {
8654 }
8660 /* Make sure unwind info is emitted for the thunk if needed. */
8663 /* Pad stack IP move with 4 instructions (two NOPs count
8664 as one instruction). */
8666 {
8671 }
8682 }
8686 }
8688 /* Emit code for the SET_GOT patterns. */
8692 {
8698 {
8699 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8704 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8705 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8706 an unadorned address. */
8711 }
8716 {
8721 #if TARGET_MACHO
8722 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8723 is what will be referenced by the Mach-O PIC subsystem. */
8726 #endif
8730 }
8731 else
8732 {
8740 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8741 is what will be referenced by the Mach-O PIC subsystem. */
8742 #if TARGET_MACHO
8745 else
8748 #endif
8749 }
8755 }
8757 /* Generate an "push" pattern for input ARG. */
8759 static rtx
8761 {
8774 stack_pointer_rtx)),
8775 arg);
8776 }
8778 /* Generate an "pop" pattern for input ARG. */
8780 static rtx
8782 {
8787 arg,
8790 stack_pointer_rtx)));
8791 }
8793 /* Return >= 0 if there is an unused call-clobbered register available
8794 for the entire function. */
8796 static unsigned int
8798 {
8802 {
8804 /* Can't use the same register for both PIC and DRAP. */
8807 else
8812 }
8815 }
8817 /* Return TRUE if we need to save REGNO. */
8819 static bool
8821 {
8831 {
8834 {
8840 }
8841 }
8850 }
8852 /* Return number of saved general prupose registers. */
8854 static int
8856 {
8862 nregs ++;
8864 }
8866 /* Return number of saved SSE registrers. */
8868 static int
8870 {
8878 nregs ++;
8880 }
8882 /* Given FROM and TO register numbers, say whether this elimination is
8883 allowed. If stack alignment is needed, we can only replace argument
8884 pointer with hard frame pointer, or replace frame pointer with stack
8885 pointer. Otherwise, frame pointer elimination is automatically
8886 handled and all other eliminations are valid. */
8888 static bool
8890 {
8896 else
8898 }
8900 /* Return the offset between two registers, one to be eliminated, and the other
8901 its replacement, at the start of a routine. */
8903 HOST_WIDE_INT
8905 {
8914 else
8915 {
8923 }
8924 }
8926 /* In a dynamically-aligned function, we can't know the offset from
8927 stack pointer to frame pointer, so we must ensure that setjmp
8928 eliminates fp against the hard fp (%ebp) rather than trying to
8929 index from %esp up to the top of the frame across a gap that is
8930 of unknown (at compile-time) size. */
8931 static rtx
8933 {
8935 }
8937 /* When using -fsplit-stack, the allocation routines set a field in
8938 the TCB to the bottom of the stack plus this much space, measured
8939 in bytes. */
8941 #define SPLIT_STACK_AVAILABLE 256
8943 /* Fill structure ix86_frame about frame of currently computed function. */
8945 static void
8947 {
8949 HOST_WIDE_INT offset;
8952 HOST_WIDE_INT to_allocate;
8960 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8961 function prologues and leaf. */
8965 {
8970 }
8976 /* For SEH we have to limit the amount of code movement into the prologue.
8977 At present we do this via a BLOCKAGE, at which point there's very little
8978 scheduling that can be done, which means that there's very little point
8979 in doing anything except PUSHs. */
8983 /* During reload iteration the amount of registers saved can change.
8984 Recompute the value as needed. Do not recompute when amount of registers
8985 didn't change as reload does multiple calls to the function and does not
8986 expect the decision to change within single iteration. */
8989 {
8995 /* The fast prologue uses move instead of push to save registers. This
8996 is significantly longer, but also executes faster as modern hardware
8997 can execute the moves in parallel, but can't do that for push/pop.
8999 Be careful about choosing what prologue to emit: When function takes
9000 many instructions to execute we may use slow version as well as in
9001 case function is known to be outside hot spot (this is known with
9002 feedback only). Weight the size of function by number of registers
9003 to save as it is cheap to use one or two push instructions but very
9004 slow to use many of them. */
9008 || (flag_branch_probabilities
9011 else
9014 }
9016 frame->save_regs_using_mov
9018 /* If static stack checking is enabled and done with probes,
9019 the registers need to be saved before allocating the frame. */
9022 /* Skip return address. */
9025 /* Skip pushed static chain. */
9029 /* Skip saved base pointer. */
9034 /* The traditional frame pointer location is at the top of the frame. */
9037 /* Register save area */
9041 /* On SEH target, registers are pushed just before the frame pointer
9042 location. */
9046 /* Align and set SSE register save area. */
9048 {
9049 /* The only ABI that has saved SSE registers (Win64) also has a
9050 16-byte aligned default stack, and thus we don't need to be
9051 within the re-aligned local stack frame to save them. */
9055 }
9058 /* The re-aligned stack starts here. Values before this point are not
9059 directly comparable with values below this point. In order to make
9060 sure that no value happens to be the same before and after, force
9061 the alignment computation below to add a non-zero value. */
9065 /* Va-arg area */
9069 /* Align start of frame for local function. */
9078 /* Frame pointer points here. */
9083 /* Add outgoing arguments area. Can be skipped if we eliminated
9084 all the function calls as dead code.
9085 Skipping is however impossible when function calls alloca. Alloca
9086 expander assumes that last crtl->outgoing_args_size
9087 of stack frame are unused. */
9091 {
9094 }
9095 else
9098 /* Align stack boundary. Only needed if we're calling another function
9099 or using alloca. */
9104 /* We've reached end of stack frame. */
9107 /* Size prologue needs to allocate. */
9118 {
9124 }
9125 else
9129 /* The SEH frame pointer location is near the bottom of the frame.
9130 This is enforced by the fact that the difference between the
9131 stack pointer and the frame pointer is limited to 240 bytes in
9132 the unwind data structure. */
9134 {
9135 HOST_WIDE_INT diff;
9137 /* If we can leave the frame pointer where it is, do so. Also, returns
9138 the establisher frame for __builtin_frame_address (0). */
9143 {
9144 /* Ideally we'd determine what portion of the local stack frame
9145 (within the constraint of the lowest 240) is most heavily used.
9146 But without that complication, simply bias the frame pointer
9147 by 128 bytes so as to maximize the amount of the local stack
9148 frame that is addressable with 8-bit offsets. */
9150 }
9151 }
9152 }
9154 /* This is semi-inlined memory_address_length, but simplified
9155 since we know that we're always dealing with reg+offset, and
9156 to avoid having to create and discard all that rtl. */
9160 {
9164 {
9165 /* EBP and R13 cannot be encoded without an offset. */
9167 }
9171 /* ESP and R12 must be encoded with a SIB byte. */
9173 len++;
9176 }
9178 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9179 The valid base registers are taken from CFUN->MACHINE->FS. */
9181 static rtx
9183 {
9189 {
9190 /* Choose the base register most likely to allow the most scheduling
9191 opportunities. Generally FP is valid throughout the function,
9192 while DRAP must be reloaded within the epilogue. But choose either
9193 over the SP due to increased encoding size. */
9196 {
9199 }
9201 {
9204 }
9206 {
9209 }
9210 }
9211 else
9212 {
9213 HOST_WIDE_INT toffset;
9216 /* Choose the base register with the smallest address encoding.
9217 With a tie, choose FP > DRAP > SP. */
9219 {
9223 }
9225 {
9229 {
9233 }
9234 }
9236 {
9240 {
9244 }
9245 }
9246 }
9250 }
9252 /* Emit code to save registers in the prologue. */
9254 static void
9256 {
9258 rtx insn;
9262 {
9265 }
9266 }
9268 /* Emit a single register save at CFA - CFA_OFFSET. */
9270 static void
9272 HOST_WIDE_INT cfa_offset)
9273 {
9281 /* For SSE saves, we need to indicate the 128-bit alignment. */
9292 /* When saving registers into a re-aligned local stack frame, avoid
9293 any tricky guessing by dwarf2out. */
9295 {
9299 {
9300 /* A bit of a hack. We force the DRAP register to be saved in
9301 the re-aligned stack frame, which provides us with a copy
9302 of the CFA that will last past the prologue. Install it. */
9308 }
9309 else
9310 {
9311 /* The frame pointer is a stable reference within the
9312 aligned frame. Use it. */
9319 }
9320 }
9322 /* The memory may not be relative to the current CFA register,
9323 which means that we may need to generate a new pattern for
9324 use by the unwind info. */
9326 {
9331 }
9332 }
9334 /* Emit code to save registers using MOV insns.
9335 First register is stored at CFA - CFA_OFFSET. */
9336 static void
9338 {
9343 {
9346 }
9347 }
9349 /* Emit code to save SSE registers using MOV insns.
9350 First register is stored at CFA - CFA_OFFSET. */
9351 static void
9353 {
9358 {
9361 }
9362 }
9366 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9367 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9368 Don't add the note if the previously saved value will be left untouched
9369 within stack red-zone till return, as unwinders can find the same value
9370 in the register and on the stack. */
9372 static void
9374 {
9380 {
9383 }
9384 else
9385 queued_cfa_restores
9387 }
9389 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9391 static void
9393 {
9394 rtx last;
9398 ;
9403 }
9405 /* Expand prologue or epilogue stack adjustment.
9406 The pattern exist to put a dependency on all ebp-based memory accesses.
9407 STYLE should be negative if instructions should be marked as frame related,
9408 zero if %r11 register is live and cannot be freely used and positive
9409 otherwise. */
9411 static void
9414 {
9416 rtx insn;
9423 else
9424 {
9425 rtx tmp;
9426 /* r11 is used by indirect sibcall return as well, set before the
9427 epilogue and used after the epilogue. */
9430 else
9431 {
9435 }
9441 }
9448 {
9449 rtx r;
9459 }
9461 {
9464 {
9468 }
9469 }
9472 {
9477 {
9480 }
9482 {
9485 }
9486 else
9487 {
9488 /* Else there are two possibilities: SP itself, which we set
9489 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9490 taken care of this by hand along the eh_return path. */
9493 }
9497 }
9498 }
9500 /* Find an available register to be used as dynamic realign argument
9501 pointer regsiter. Such a register will be written in prologue and
9502 used in begin of body, so it must not be
9503 1. parameter passing register.
9504 2. GOT pointer.
9505 We reuse static-chain register if it is available. Otherwise, we
9506 use DI for i386 and R13 for x86-64. We chose R13 since it has
9507 shorter encoding.
9509 Return: the regno of chosen register. */
9511 static unsigned int
9513 {
9517 {
9518 /* Use R13 for nested function or function need static chain.
9519 Since function with tail call may use any caller-saved
9520 registers in epilogue, DRAP must not use caller-saved
9521 register in such case. */
9526 }
9527 else
9528 {
9529 /* Use DI for nested function or function need static chain.
9530 Since function with tail call may use any caller-saved
9531 registers in epilogue, DRAP must not use caller-saved
9532 register in such case. */
9536 /* Reuse static chain register if it isn't used for parameter
9537 passing. */
9539 {
9543 }
9545 }
9546 }
9548 /* Return minimum incoming stack alignment. */
9550 static unsigned int
9552 {
9555 /* Prefer the one specified at command line. */
9558 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9559 if -mstackrealign is used, it isn't used for sibcall check and
9560 estimated stack alignment is 128bit. */
9562 && !TARGET_64BIT
9563 && ix86_force_align_arg_pointer
9566 else
9569 /* Incoming stack alignment can be changed on individual functions
9570 via force_align_arg_pointer attribute. We use the smallest
9571 incoming stack boundary. */
9577 /* The incoming stack frame has to be aligned at least at
9578 parm_stack_boundary. */
9582 /* Stack at entrance of main is aligned by runtime. We use the
9583 smallest incoming stack boundary. */
9591 }
9593 /* Update incoming stack boundary and estimated stack alignment. */
9595 static void
9597 {
9598 ix86_incoming_stack_boundary
9601 /* x86_64 vararg needs 16byte stack alignment for register save
9602 area. */
9607 }
9609 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9610 needed or an rtx for DRAP otherwise. */
9612 static rtx
9614 {
9619 {
9620 /* Assign DRAP to vDRAP and returns vDRAP */
9622 rtx drap_vreg;
9623 rtx arg_ptr;
9636 {
9639 }
9641 }
9642 else
9644 }
9646 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9648 static rtx
9650 {
9652 }
9655 rtx reg;
9657 };
9659 /* Return a short-lived scratch register for use on function entry.
9660 In 32-bit mode, it is valid only after the registers are saved
9661 in the prologue. This register must be released by means of
9662 release_scratch_register_on_entry once it is dead. */
9664 static void
9666 {
9672 {
9673 /* We always use R11 in 64-bit mode. */
9675 }
9676 else
9677 {
9679 bool fastcall_p
9681 bool thiscall_p
9685 int drap_regno
9688 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9689 for the static chain register. */
9693 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9694 for the static chain register. */
9699 /* ecx is the static chain register. */
9701 && !static_chain_p
9706 /* esi is the static chain register. */
9712 else
9713 {
9716 }
9717 }
9721 {
9724 }
9725 }
9727 /* Release a scratch register obtained from the preceding function. */
9729 static void
9731 {
9733 {
9737 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9743 }
9744 }
9746 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9748 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9750 static void
9752 {
9753 /* We skip the probe for the first interval + a small dope of 4 words and
9754 probe that many bytes past the specified size to maintain a protection
9755 area at the botton of the stack. */
9759 /* See if we have a constant small number of probes to generate. If so,
9760 that's the easy case. The run-time loop is made up of 11 insns in the
9761 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9762 for n # of intervals. */
9764 {
9768 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9769 values of N from 1 until it exceeds SIZE. If only one probe is
9770 needed, this will not generate any code. Then adjust and probe
9771 to PROBE_INTERVAL + SIZE. */
9773 {
9775 {
9778 }
9779 else
9786 }
9790 else
9798 /* Adjust back to account for the additional first interval. */
9802 }
9804 /* Otherwise, do the same as above, but in a loop. Note that we must be
9805 extra careful with variables wrapping around because we might be at
9806 the very top (or the very bottom) of the address space and we have
9807 to be able to handle this case properly; in particular, we use an
9808 equality test for the loop condition. */
9809 else
9810 {
9811 HOST_WIDE_INT rounded_size;
9817 /* Step 1: round SIZE to the previous multiple of the interval. */
9822 /* Step 2: compute initial and final value of the loop counter. */
9824 /* SP = SP_0 + PROBE_INTERVAL. */
9829 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9833 stack_pointer_rtx)));
9836 /* Step 3: the loop
9838 while (SP != LAST_ADDR)
9839 {
9840 SP = SP + PROBE_INTERVAL
9841 probe at SP
9842 }
9844 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9845 values of N from 1 until it is equal to ROUNDED_SIZE. */
9850 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9851 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9854 {
9859 }
9861 /* Adjust back to account for the additional first interval. */
9867 }
9871 /* Even if the stack pointer isn't the CFA register, we need to correctly
9872 describe the adjustments made to it, in particular differentiate the
9873 frame-related ones from the frame-unrelated ones. */
9875 {
9888 }
9890 /* Make sure nothing is scheduled before we are done. */
9892 }
9894 /* Adjust the stack pointer up to REG while probing it. */
9898 {
9908 /* Jump to END_LAB if SP == LAST_ADDR. */
9916 /* SP = SP + PROBE_INTERVAL. */
9920 /* Probe at SP. */
9931 }
9933 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9934 inclusive. These are offsets from the current stack pointer. */
9936 static void
9938 {
9939 /* See if we have a constant small number of probes to generate. If so,
9940 that's the easy case. The run-time loop is made up of 7 insns in the
9941 generic case while the compile-time loop is made up of n insns for n #
9942 of intervals. */
9944 {
9945 HOST_WIDE_INT i;
9947 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9948 it exceeds SIZE. If only one probe is needed, this will not
9949 generate any code. Then probe at FIRST + SIZE. */
9956 }
9958 /* Otherwise, do the same as above, but in a loop. Note that we must be
9959 extra careful with variables wrapping around because we might be at
9960 the very top (or the very bottom) of the address space and we have
9961 to be able to handle this case properly; in particular, we use an
9962 equality test for the loop condition. */
9963 else
9964 {
9971 /* Step 1: round SIZE to the previous multiple of the interval. */
9976 /* Step 2: compute initial and final value of the loop counter. */
9978 /* TEST_OFFSET = FIRST. */
9981 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9985 /* Step 3: the loop
9987 while (TEST_ADDR != LAST_ADDR)
9988 {
9989 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9990 probe at TEST_ADDR
9991 }
9993 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9994 until it is equal to ROUNDED_SIZE. */
9999 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10000 that SIZE is equal to ROUNDED_SIZE. */
10005 stack_pointer_rtx,
10010 }
10012 /* Make sure nothing is scheduled before we are done. */
10014 }
10016 /* Probe a range of stack addresses from REG to END, inclusive. These are
10017 offsets from the current stack pointer. */
10021 {
10031 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10039 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10043 /* Probe at TEST_ADDR. */
10056 }
10058 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10059 to be generated in correct form. */
10060 static void
10062 {
10063 /* Check if stack realign is really needed after reload, and
10064 stores result in cfun */
10065 unsigned int incoming_stack_boundary
10074 {
10075 /* After stack_realign_needed is finalized, we can't no longer
10076 change it. */
10079 }
10081 /* If the only reason for frame_pointer_needed is that we conservatively
10082 assumed stack realignment might be needed, but in the end nothing that
10083 needed the stack alignment had been spilled, clear frame_pointer_needed
10084 and say we don't need stack realignment. */
10087 && frame_pointer_needed
10089 && flag_omit_frame_pointer
10091 && !ix86_current_function_calls_tls_descriptor
10100 {
10102 basic_block bb;
10109 HARD_FRAME_POINTER_REGNUM);
10111 {
10112 rtx insn;
10116 set_up_by_prologue))
10117 {
10121 }
10122 }
10136 }
10140 }
10142 /* Expand the prologue into a bunch of separate insns. */
10144 void
10146 {
10151 HOST_WIDE_INT allocate;
10157 /* DRAP should not coexist with stack_realign_fp */
10162 /* Initialize CFA state for before the prologue. */
10166 /* Track SP offset to the CFA. We continue tracking this after we've
10167 swapped the CFA register away from SP. In the case of re-alignment
10168 this is fudged; we're interested to offsets within the local frame. */
10175 {
10176 /* We should have already generated an error for any use of
10177 ms_hook on a nested function. */
10180 /* Check if profiling is active and we shall use profiling before
10181 prologue variant. If so sorry. */
10186 /* In ix86_asm_output_function_label we emitted:
10187 8b ff movl.s %edi,%edi
10188 55 push %ebp
10189 8b ec movl.s %esp,%ebp
10191 This matches the hookable function prologue in Win32 API
10192 functions in Microsoft Windows XP Service Pack 2 and newer.
10193 Wine uses this to enable Windows apps to hook the Win32 API
10194 functions provided by Wine.
10196 What that means is that we've already set up the frame pointer. */
10200 {
10203 /* We've decided to use the frame pointer already set up.
10204 Describe this to the unwinder by pretending that both
10205 push and mov insns happen right here.
10207 Putting the unwind info here at the end of the ms_hook
10208 is done so that we can make absolutely certain we get
10209 the required byte sequence at the start of the function,
10210 rather than relying on an assembler that can produce
10211 the exact encoding required.
10213 However it does mean (in the unpatched case) that we have
10214 a 1 insn window where the asynchronous unwind info is
10215 incorrect. However, if we placed the unwind info at
10216 its correct location we would have incorrect unwind info
10217 in the patched case. Which is probably all moot since
10218 I don't expect Wine generates dwarf2 unwind info for the
10219 system libraries that use this feature. */
10225 stack_pointer_rtx);
10233 /* Note that gen_push incremented m->fs.cfa_offset, even
10234 though we didn't emit the push insn here. */
10238 }
10239 else
10240 {
10241 /* The frame pointer is not needed so pop %ebp again.
10242 This leaves us with a pristine state. */
10244 }
10245 }
10247 /* The first insn of a function that accepts its static chain on the
10248 stack is to push the register that would be filled in by a direct
10249 call. This insn will be skipped by the trampoline. */
10251 {
10255 /* We don't want to interpret this push insn as a register save,
10256 only as a stack adjustment. The real copy of the register as
10257 a save will be done later, if needed. */
10262 }
10264 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10265 of DRAP is needed and stack realignment is really needed after reload */
10267 {
10270 /* Only need to push parameter pointer reg if it is caller saved. */
10272 {
10273 /* Push arg pointer reg */
10276 }
10278 /* Grab the argument pointer. */
10285 /* Align the stack. */
10287 stack_pointer_rtx,
10291 /* Replicate the return address on the stack so that return
10292 address can be reached via (argp - 1) slot. This is needed
10293 to implement macro RETURN_ADDR_RTX and intrinsic function
10294 expand_builtin_return_addr etc. */
10300 /* For the purposes of frame and register save area addressing,
10301 we've started over with a new frame. */
10304 }
10310 {
10311 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10312 slower on all targets. Also sdb doesn't like it. */
10316 /* Push registers now, before setting the frame pointer
10317 on SEH target. */
10319 && TARGET_SEH
10321 {
10325 }
10328 {
10336 }
10337 }
10340 {
10341 /* If saving registers via PUSH, do so now. */
10343 {
10347 }
10349 /* When using red zone we may start register saving before allocating
10350 the stack frame saving one cycle of the prologue. However, avoid
10351 doing this if we have to probe the stack; at least on x86_64 the
10352 stack probe can turn into a call that clobbers a red zone location. */
10354 && (! TARGET_STACK_PROBE
10356 {
10359 }
10360 }
10363 {
10367 /* The computation of the size of the re-aligned stack frame means
10368 that we must allocate the size of the register save area before
10369 performing the actual alignment. Otherwise we cannot guarantee
10370 that there's enough storage above the realignment point. */
10377 /* Align the stack. */
10379 stack_pointer_rtx,
10382 /* For the purposes of register save area addressing, the stack
10383 pointer is no longer valid. As for the value of sp_offset,
10384 see ix86_compute_frame_layout, which we need to match in order
10385 to pass verification of stack_pointer_offset at the end. */
10388 }
10393 {
10394 /* We start to count from ARG_POINTER. */
10397 /* If it was realigned, take into account the fake frame. */
10399 {
10406 /* This over-estimates by 1 minimal-stack-alignment-unit but
10407 mitigates that by counting in the new return address slot. */
10408 current_function_dynamic_stack_size
10410 }
10413 }
10415 /* On SEH target with very large frame size, allocate an area to save
10416 SSE registers (as the very large allocation won't be described). */
10420 {
10421 HOST_WIDE_INT sse_size =
10426 /* No need to do stack checking as the area will be immediately
10427 written. */
10434 }
10436 /* The stack has already been decremented by the instruction calling us
10437 so probe if the size is non-negative to preserve the protection area. */
10439 {
10440 /* We expect the registers to be saved when probes are used. */
10444 {
10447 }
10448 else
10449 {
10457 else
10459 }
10460 }
10463 ;
10466 {
10470 }
10471 else
10472 {
10485 /* Note that SEH directives need to continue tracking the stack
10486 pointer even after the frame pointer has been set up. */
10488 {
10492 {
10496 }
10497 }
10500 {
10505 {
10509 }
10510 }
10515 /* Use the fact that AX still contains ALLOCATE. */
10517 ? gen_pro_epilogue_adjust_stack_di_sub
10524 {
10532 }
10536 {
10543 }
10545 {
10550 }
10551 }
10554 /* If we havn't already set up the frame pointer, do so now. */
10556 {
10568 }
10579 {
10586 }
10589 {
10591 {
10593 {
10603 label));
10607 }
10608 else
10610 }
10611 else
10612 {
10616 }
10617 }
10619 /* In the pic_reg_used case, make sure that the got load isn't deleted
10620 when mcount needs it. Blockage to avoid call movement across mcount
10621 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10622 note. */
10627 {
10628 /* vDRAP is setup but after reload it turns out stack realign
10629 isn't necessary, here we will emit prologue to setup DRAP
10630 without stack realign adjustment */
10633 }
10635 /* Prevent instructions from being scheduled into register save push
10636 sequence when access to the redzone area is done through frame pointer.
10637 The offset between the frame pointer and the stack pointer is calculated
10638 relative to the value of the stack pointer at the end of the function
10639 prologue, and moving instructions that access redzone area via frame
10640 pointer inside push sequence violates this assumption. */
10644 /* Emit cld instruction if stringops are used in the function. */
10648 /* SEH requires that the prologue end within 256 bytes of the start of
10649 the function. Prevent instruction schedules that would extend that.
10650 Further, prevent alloca modifications to the stack pointer from being
10651 combined with prologue modifications. */
10654 }
10656 /* Emit code to restore REG using a POP insn. */
10658 static void
10660 {
10669 {
10670 /* Previously we'd represented the CFA as an expression
10671 like *(%ebp - 8). We've just popped that value from
10672 the stack, which means we need to reset the CFA to
10673 the drap register. This will remain until we restore
10674 the stack pointer. */
10678 /* This means that the DRAP register is valid for addressing too. */
10681 }
10684 {
10691 }
10693 /* When the frame pointer is the CFA, and we pop it, we are
10694 swapping back to the stack pointer as the CFA. This happens
10695 for stack frames that don't allocate other data, so we assume
10696 the stack pointer is now pointing at the return address, i.e.
10697 the function entry state, which makes the offset be 1 word. */
10699 {
10702 {
10710 }
10711 }
10712 }
10714 /* Emit code to restore saved registers using POP insns. */
10716 static void
10718 {
10724 }
10726 /* Emit code and notes for the LEAVE instruction. */
10728 static void
10730 {
10742 {
10750 }
10753 }
10755 /* Emit code to restore saved registers using MOV insns.
10756 First register is restored from CFA - CFA_OFFSET. */
10757 static void
10760 {
10766 {
10775 {
10776 /* Previously we'd represented the CFA as an expression
10777 like *(%ebp - 8). We've just popped that value from
10778 the stack, which means we need to reset the CFA to
10779 the drap register. This will remain until we restore
10780 the stack pointer. */
10784 /* This means that the DRAP register is valid for addressing. */
10786 }
10787 else
10791 }
10792 }
10794 /* Emit code to restore saved registers using MOV insns.
10795 First register is restored from CFA - CFA_OFFSET. */
10796 static void
10799 {
10804 {
10806 rtx mem;
10816 }
10817 }
10819 /* Restore function stack, frame, and registers. */
10821 void
10823 {
10839 /* The FP must be valid if the frame pointer is present. */
10844 /* We must have *some* valid pointer to the stack frame. */
10847 /* The DRAP is never valid at this point. */
10850 /* See the comment about red zone and frame
10851 pointer usage in ix86_expand_prologue. */
10858 /* Determine the CFA offset of the end of the red-zone. */
10861 {
10862 /* The red-zone begins below the return address. */
10865 /* When the register save area is in the aligned portion of
10866 the stack, determine the maximum runtime displacement that
10867 matches up with the aligned frame. */
10871 }
10873 /* Special care must be taken for the normal return case of a function
10874 using eh_return: the eax and edx registers are marked as saved, but
10875 not restored along this path. Adjust the save location to match. */
10879 /* EH_RETURN requires the use of moves to function properly. */
10882 /* SEH requires the use of pops to identify the epilogue. */
10885 /* If we're only restoring one register and sp is not valid then
10886 using a move instruction to restore the register since it's
10887 less work than reloading sp and popping the register. */
10900 && TARGET_USE_LEAVE
10904 else
10908 {
10909 /* Ensure that the entire register save area is addressable via
10910 the stack pointer, if we will restore via sp. */
10915 {
10919 style,
10921 }
10922 }
10924 /* If there are any SSE registers to restore, then we have to do it
10925 via moves, since there's obviously no pop for SSE regs. */
10931 {
10932 rtx t;
10937 /* eh_return epilogues need %ecx added to the stack pointer. */
10939 {
10942 /* Stack align doesn't work with eh_return. */
10944 /* Neither does regparm nested functions. */
10948 {
10956 /* Note that we use SA as a temporary CFA, as the return
10957 address is at the proper place relative to it. We
10958 pretend this happens at the FP restore insn because
10959 prior to this insn the FP would be stored at the wrong
10960 offset relative to SA, and after this insn we have no
10961 other reasonable register to use for the CFA. We don't
10962 bother resetting the CFA to the SP for the duration of
10963 the return insn. */
10976 }
10977 else
10978 {
10986 {
10990 UNITS_PER_WORD));
10992 }
10993 }
10996 }
10997 }
10998 else
10999 {
11000 /* SEH requires that the function end with (1) a stack adjustment
11001 if necessary, (2) a sequence of pops, and (3) a return or
11002 jump instruction. Prevent insns from the function body from
11003 being scheduled into this sequence. */
11005 {
11006 /* Prevent a catch region from being adjacent to the standard
11007 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11008 several other flags that would be interesting to test are
11009 not yet set up. */
11012 else
11014 }
11016 /* First step is to deallocate the stack frame so that we can
11017 pop the registers. Also do it on SEH target for very large
11018 frame as the emitted instructions aren't allowed by the ABI in
11019 epilogues. */
11021 || (TARGET_SEH
11024 {
11029 }
11031 {
11035 style,
11037 }
11040 }
11042 /* If we used a stack pointer and haven't already got rid of it,
11043 then do so now. */
11045 {
11046 /* If the stack pointer is valid and pointing at the frame
11047 pointer store address, then we only need a pop. */
11050 /* Leave results in shorter dependency chains on CPUs that are
11051 able to grok it fast. */
11056 else
11057 {
11059 hard_frame_pointer_rtx,
11062 }
11063 }
11066 {
11068 rtx insn;
11094 }
11096 /* At this point the stack pointer must be valid, and we must have
11097 restored all of the registers. We may not have deallocated the
11098 entire stack frame. We've delayed this until now because it may
11099 be possible to merge the local stack deallocation with the
11100 deallocation forced by ix86_static_chain_on_stack. */
11105 {
11109 }
11110 else
11113 /* Sibcall epilogues don't want a return instruction. */
11115 {
11118 }
11121 {
11124 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11125 address, do explicit add, and jump indirectly to the caller. */
11128 {
11130 rtx insn;
11132 /* There is no "pascal" calling convention in any 64bit ABI. */
11148 }
11149 else
11151 }
11152 else
11155 /* Restore the state back to the state from the prologue,
11156 so that it's correct for the next epilogue. */
11158 }
11160 /* Reset from the function's potential modifications. */
11162 static void
11164 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11165 {
11168 #if TARGET_MACHO
11169 /* Mach-O doesn't support labels at the end of objects, so if
11170 it looks like we might want one, insert a NOP. */
11171 {
11177 {
11178 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11179 notes only, instead set their CODE_LABEL_NUMBER to -1,
11180 otherwise there would be code generation differences
11181 in between -g and -g0. */
11185 }
11195 }
11196 #endif
11198 }
11200 /* Return a scratch register to use in the split stack prologue. The
11201 split stack prologue is used for -fsplit-stack. It is the first
11202 instructions in the function, even before the regular prologue.
11203 The scratch register can be any caller-saved register which is not
11204 used for parameters or for the static chain. */
11206 static unsigned int
11208 {
11211 else
11212 {
11225 {
11227 {
11231 }
11233 }
11235 {
11239 }
11241 {
11244 else
11245 {
11247 {
11251 }
11253 }
11254 }
11255 else
11256 {
11257 /* FIXME: We could make this work by pushing a register
11258 around the addition and comparison. */
11261 }
11262 }
11263 }
11265 /* A SYMBOL_REF for the function which allocates new stackspace for
11266 -fsplit-stack. */
11270 /* A SYMBOL_REF for the more stack function when using the large
11271 model. */
11275 /* Handle -fsplit-stack. These are the first instructions in the
11276 function, even before the regular prologue. */
11278 void
11280 {
11282 HOST_WIDE_INT allocate;
11287 rtx fn;
11295 /* This is the label we will branch to if we have enough stack
11296 space. We expect the basic block reordering pass to reverse this
11297 branch if optimizing, so that we branch in the unlikely case. */
11300 /* We need to compare the stack pointer minus the frame size with
11301 the stack boundary in the TCB. The stack boundary always gives
11302 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11303 can compare directly. Otherwise we need to do an addition. */
11306 UNSPEC_STACK_CHECK);
11311 else
11312 {
11314 rtx offset;
11316 /* We need a scratch register to hold the stack pointer minus
11317 the required frame size. Since this is the very start of the
11318 function, the scratch register can be any caller-saved
11319 register which is not used for parameters. */
11326 {
11327 /* We don't use ix86_gen_add3 in this case because it will
11328 want to split to lea, but when not optimizing the insn
11329 will not be split after this point. */
11332 offset)));
11333 }
11334 else
11335 {
11338 stack_pointer_rtx));
11339 }
11341 }
11347 /* Mark the jump as very likely to be taken. */
11355 /* Get more stack space. We pass in the desired stack space and the
11356 size of the arguments to copy to the new stack. In 32-bit mode
11357 we push the parameters; __morestack will return on a new stack
11358 anyhow. In 64-bit mode we pass the parameters in r10 and
11359 r11. */
11364 {
11370 /* If this function uses a static chain, it will be in %r10.
11371 Preserve it across the call to __morestack. */
11373 {
11374 rtx rax;
11379 }
11382 {
11383 HOST_WIDE_INT argval;
11386 /* When using the large model we need to load the address
11387 into a register, and we've run out of registers. So we
11388 switch to a different calling convention, and we call a
11389 different function: __morestack_large. We pass the
11390 argument size in the upper 32 bits of r10 and pass the
11391 frame size in the lower 32 bits. */
11396 split_stack_fn_large =
11400 {
11410 UNSPEC_GOT);
11416 }
11417 else
11424 }
11425 else
11426 {
11430 }
11433 }
11434 else
11435 {
11438 }
11444 /* In order to make call/return prediction work right, we now need
11445 to execute a return instruction. See
11446 libgcc/config/i386/morestack.S for the details on how this works.
11448 For flow purposes gcc must not see this as a return
11449 instruction--we need control flow to continue at the subsequent
11450 label. Therefore, we use an unspec. */
11454 /* If we are in 64-bit mode and this function uses a static chain,
11455 we saved %r10 in %rax before calling _morestack. */
11460 /* If this function calls va_start, we need to store a pointer to
11461 the arguments on the old stack, because they may not have been
11462 all copied to the new stack. At this point the old stack can be
11463 found at the frame pointer value used by __morestack, because
11464 __morestack has set that up before calling back to us. Here we
11465 store that pointer in a scratch register, and in
11466 ix86_expand_prologue we store the scratch register in a stack
11467 slot. */
11469 {
11471 rtx frame_reg;
11478 /* 64-bit:
11479 fp -> old fp value
11480 return address within this function
11481 return address of caller of this function
11482 stack arguments
11483 So we add three words to get to the stack arguments.
11485 32-bit:
11486 fp -> old fp value
11487 return address within this function
11488 first argument to __morestack
11489 second argument to __morestack
11490 return address of caller of this function
11491 stack arguments
11492 So we add five words to get to the stack arguments.
11493 */
11504 }
11509 /* If this function calls va_start, we now have to set the scratch
11510 register for the case where we do not call __morestack. In this
11511 case we need to set it based on the stack pointer. */
11513 {
11520 }
11521 }
11523 /* We may have to tell the dataflow pass that the split stack prologue
11524 is initializing a scratch register. */
11526 static void
11528 {
11530 {
11533 }
11534 }
11535 \f
11536 /* Determine if op is suitable SUBREG RTX for address. */
11538 static bool
11540 {
11551 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11552 failures when the register is one word out of a two word structure. */
11556 /* Allow only SUBREGs of non-eliminable hard registers. */
11558 }
11560 /* Extract the parts of an RTL expression that is a valid memory address
11561 for an instruction. Return 0 if the structure of the address is
11562 grossly off. Return -1 if the address contains ASHIFT, so it is not
11563 strictly valid, but still used for computing length of lea instruction. */
11565 int
11567 {
11572 rtx tmp;
11576 /* Allow zero-extended SImode addresses,
11577 they will be emitted with addr32 prefix. */
11579 {
11582 {
11586 }
11589 {
11596 }
11597 }
11599 /* Allow SImode subregs of DImode addresses,
11600 they will be emitted with addr32 prefix. */
11602 {
11605 {
11609 }
11610 }
11615 {
11618 else
11620 }
11622 {
11627 do
11628 {
11633 }
11640 {
11643 {
11668 /* FALLTHRU */
11672 && TARGET_TLS_DIRECT_SEG_REFS
11675 else
11682 /* FALLTHRU */
11689 else
11704 }
11705 }
11706 }
11708 {
11711 }
11713 {
11714 /* We're called for lea too, which implements ashift on occasion. */
11724 }
11726 {
11730 /* Constant addresses are sign extended to 64bit, we have to
11731 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11737 }
11738 else
11742 {
11744 ;
11747 ;
11748 else
11750 }
11752 /* Address override works only on the (%reg) part of %fs:(%reg). */
11758 /* Extract the integral value of scale. */
11760 {
11764 }
11769 /* Avoid useless 0 displacement. */
11773 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11778 {
11779 rtx tmp;
11782 }
11784 /* Special case: %ebp cannot be encoded as a base without a displacement.
11785 Similarly %r13. */
11787 && base_reg
11796 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11797 Avoid this by transforming to [%esi+0].
11798 Reload calls address legitimization without cfun defined, so we need
11799 to test cfun for being non-NULL. */
11805 /* Special case: encode reg+reg instead of reg*2. */
11809 /* Special case: scaling cannot be encoded without base or displacement. */
11820 }
11821 \f
11822 /* Return cost of the memory address x.
11823 For i386, it is better to use a complex address than let gcc copy
11824 the address into a reg and make a new pseudo. But not if the address
11825 requires to two regs - that would mean more pseudos with longer
11826 lifetimes. */
11827 static int
11829 addr_space_t as ATTRIBUTE_UNUSED,
11831 {
11843 /* Attempt to minimize number of registers in the address. */
11849 cost++;
11856 cost++;
11858 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11859 since it's predecode logic can't detect the length of instructions
11860 and it degenerates to vector decoded. Increase cost of such
11861 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11862 to split such addresses or even refuse such addresses at all.
11864 Following addressing modes are affected:
11865 [base+scale*index]
11866 [scale*index+disp]
11867 [base+index]
11869 The first and last case may be avoidable by explicitly coding the zero in
11870 memory address, but I don't have AMD-K6 machine handy to check this
11871 theory. */
11880 }
11881 \f
11882 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11883 this is used for to form addresses to local data when -fPIC is in
11884 use. */
11886 static bool
11888 {
11891 }
11893 /* Determine if a given RTX is a valid constant. We already know this
11894 satisfies CONSTANT_P. */
11896 static bool
11898 {
11900 {
11905 {
11909 }
11914 /* Only some unspecs are valid as "constants". */
11917 {
11933 }
11935 /* We must have drilled down to a symbol. */
11940 /* FALLTHRU */
11943 /* TLS symbols are never valid. */
11947 /* DLLIMPORT symbols are never valid. */
11952 #if TARGET_MACHO
11953 /* mdynamic-no-pic */
11956 #endif
11972 }
11974 /* Otherwise we handle everything else in the move patterns. */
11976 }
11978 /* Determine if it's legal to put X into the constant pool. This
11979 is not possible for the address of thread-local symbols, which
11980 is checked above. */
11982 static bool
11984 {
11985 /* We can always put integral constants and vectors in memory. */
11987 {
11995 }
11997 }
12000 /* Nonzero if the constant value X is a legitimate general operand
12001 when generating PIC code. It is given that flag_pic is on and
12002 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12004 bool
12006 {
12007 rtx inner;
12010 {
12017 /* Only some unspecs are valid as "constants". */
12020 {
12033 }
12034 /* FALLTHRU */
12042 }
12043 }
12045 /* Determine if a given CONST RTX is a valid memory displacement
12046 in PIC mode. */
12048 bool
12050 {
12053 /* In 64bit mode we can allow direct addresses of symbols and labels
12054 when they are not dynamic symbols. */
12056 {
12060 {
12084 /* FALLTHRU */
12087 /* TLS references should always be enclosed in UNSPEC. */
12097 }
12098 }
12104 {
12105 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12106 of GOT tables. We should not need these anyway. */
12118 }
12122 {
12127 }
12136 {
12140 /* We need to check for both symbols and labels because VxWorks loads
12141 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12142 details. */
12146 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12147 While ABI specify also 32bit relocation but we don't produce it in
12148 small PIC model at all. */
12170 }
12173 }
12175 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12176 replace the input X, or the original X if no replacement is called for.
12177 The output parameter *WIN is 1 if the calling macro should goto WIN,
12178 0 if it should not. */
12180 bool
12185 {
12186 /* Reload can generate:
12188 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12189 (reg:DI 97))
12190 (reg:DI 2 cx))
12192 This RTX is rejected from ix86_legitimate_address_p due to
12193 non-strictness of base register 97. Following this rejection,
12194 reload pushes all three components into separate registers,
12195 creating invalid memory address RTX.
12197 Following code reloads only the invalid part of the
12198 memory address RTX. */
12204 {
12210 {
12215 }
12219 {
12224 }
12228 }
12231 }
12233 /* Recognizes RTL expressions that are valid memory addresses for an
12234 instruction. The MODE argument is the machine mode for the MEM
12235 expression that wants to use this address.
12237 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12238 convert common non-canonical forms to canonical form so that they will
12239 be recognized. */
12241 static bool
12244 {
12247 HOST_WIDE_INT scale;
12250 /* Decomposition failed. */
12258 /* Validate base register. */
12260 {
12261 rtx reg;
12267 else
12268 /* Base is not a register. */
12276 /* Base is not valid. */
12278 }
12280 /* Validate index register. */
12282 {
12283 rtx reg;
12289 else
12290 /* Index is not a register. */
12298 /* Index is not valid. */
12300 }
12302 /* Index and base should have the same mode. */
12307 /* Validate scale factor. */
12309 {
12311 /* Scale without index. */
12315 /* Scale is not a valid multiplier. */
12317 }
12319 /* Validate displacement. */
12321 {
12326 {
12327 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12328 used. While ABI specify also 32bit relocations, we don't produce
12329 them at all and use IP relative instead. */
12336 /* 64bit address unspec. */
12356 /* Invalid address unspec. */
12358 }
12361 && (flag_pic
12362 || (TARGET_MACHO
12363 #if TARGET_MACHO
12364 && MACHOPIC_INDIRECT
12366 #endif
12367 )))
12368 {
12370 is_legitimate_pic:
12372 {
12373 /* foo@dtpoff(%rX) is ok. */
12380 /* Non-constant pic memory reference. */
12382 }
12385 /* Displacement is an invalid pic construct. */
12387 #if TARGET_MACHO
12390 /* displacment must be referenced via non_lazy_pointer */
12392 #endif
12394 /* This code used to verify that a symbolic pic displacement
12395 includes the pic_offset_table_rtx register.
12397 While this is good idea, unfortunately these constructs may
12398 be created by "adds using lea" optimization for incorrect
12399 code like:
12401 int a;
12402 int foo(int i)
12403 {
12404 return *(&a+i);
12405 }
12407 This code is nonsensical, but results in addressing
12408 GOT table with pic_offset_table_rtx base. We can't
12409 just refuse it easily, since it gets matched by
12410 "addsi3" pattern, that later gets split to lea in the
12411 case output register differs from input. While this
12412 can be handled by separate addsi pattern for this case
12413 that never results in lea, this seems to be easier and
12414 correct fix for crash to disable this test. */
12415 }
12422 /* Displacement is not constant. */
12426 /* Displacement is out of range. */
12428 }
12430 /* Everything looks valid. */
12432 }
12434 /* Determine if a given RTX is a valid constant address. */
12436 bool
12438 {
12440 }
12441 \f
12442 /* Return a unique alias set for the GOT. */
12444 static alias_set_type
12446 {
12451 }
12453 /* Return a legitimate reference for ORIG (an address) using the
12454 register REG. If REG is 0, a new pseudo is generated.
12456 There are two types of references that must be handled:
12458 1. Global data references must load the address from the GOT, via
12459 the PIC reg. An insn is emitted to do this load, and the reg is
12460 returned.
12462 2. Static data references, constant pool addresses, and code labels
12463 compute the address as an offset from the GOT, whose base is in
12464 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12465 differentiate them from global data objects. The returned
12466 address is the PIC reg + an unspec constant.
12468 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12469 reg also appears in the address. */
12471 static rtx
12473 {
12477 #if TARGET_MACHO
12479 {
12482 /* Use the generic Mach-O PIC machinery. */
12484 }
12485 #endif
12492 {
12493 rtx tmpreg;
12494 /* This symbol may be referenced via a displacement from the PIC
12495 base address (@GOTOFF). */
12502 {
12504 UNSPEC_GOTOFF);
12506 }
12507 else
12512 else
12517 {
12521 }
12523 }
12525 {
12526 /* This symbol may be referenced via a displacement from the PIC
12527 base address (@GOTOFF). */
12534 {
12536 UNSPEC_GOTOFF);
12538 }
12539 else
12545 {
12548 }
12549 }
12551 /* We can't use @GOTOFF for text labels on VxWorks;
12552 see gotoff_operand. */
12554 {
12556 {
12562 {
12565 }
12566 }
12568 /* For x64 PE-COFF there is no GOT table. So we use address
12569 directly. */
12571 {
12579 }
12581 {
12589 /* Use directly gen_movsi, otherwise the address is loaded
12590 into register for CSE. We don't want to CSE this addresses,
12591 instead we CSE addresses from the GOT table, so skip this. */
12594 }
12595 else
12596 {
12597 /* This symbol must be referenced via a load from the
12598 Global Offset Table (@GOT). */
12614 }
12615 }
12616 else
12617 {
12620 {
12622 {
12625 }
12626 else
12628 }
12630 {
12633 /* We must match stuff we generate before. Assume the only
12634 unspecs that can get here are ours. Not that we could do
12635 anything with them anyway.... */
12641 }
12643 {
12646 /* Check first to see if this is a constant offset from a @GOTOFF
12647 symbol reference. */
12650 {
12652 {
12656 UNSPEC_GOTOFF);
12662 {
12665 }
12666 }
12667 else
12668 {
12671 {
12675 }
12676 }
12677 }
12678 else
12679 {
12682 new_rtx
12686 {
12689 {
12692 new_rtx
12694 }
12695 else
12697 }
12698 else
12699 {
12702 {
12705 }
12707 }
12708 }
12709 }
12710 }
12712 }
12713 \f
12714 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12716 static rtx
12718 {
12722 {
12727 }
12733 }
12735 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12739 static rtx
12741 {
12743 {
12749 }
12752 }
12754 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12758 rtx
12760 {
12762 {
12763 ix86_tls_module_base_symbol
12768 }
12771 }
12773 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12774 false if we expect this to be used for a memory address and true if
12775 we expect to load the address into a register. */
12777 static rtx
12779 {
12786 {
12791 {
12794 else
12795 {
12798 }
12799 }
12802 {
12805 else
12815 }
12816 else
12817 {
12821 {
12823 rtx insns;
12826 emit_call_insn
12836 }
12837 else
12839 }
12846 {
12849 else
12850 {
12853 }
12854 }
12857 {
12862 else
12868 }
12869 else
12870 {
12874 {
12879 emit_call_insn
12884 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12885 share the LD_BASE result with other LD model accesses. */
12887 UNSPEC_TLS_LD_BASE);
12891 }
12892 else
12894 }
12902 {
12909 }
12914 {
12916 {
12917 /* The Sun linker took the AMD64 TLS spec literally
12918 and can only handle %rax as destination of the
12919 initial executable code sequence. */
12924 }
12926 /* Generate DImode references to avoid %fs:(%reg32)
12927 problems and linker IE->LE relaxation bug. */
12931 }
12933 {
12938 }
12940 {
12944 }
12945 else
12946 {
12949 }
12959 {
12964 }
12965 else
12966 {
12970 }
12980 {
12984 }
12985 else
12986 {
12990 }
12995 }
12998 }
13000 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13001 to symbol DECL. */
13004 htab_t dllimport_map;
13006 static tree
13008 {
13015 tree to;
13016 rtx rtl;
13060 }
13062 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13063 true if we require the result be a register. */
13065 static rtx
13067 {
13068 tree imp_decl;
13069 rtx x;
13078 }
13080 /* Try machine-dependent ways of modifying an illegitimate address
13081 to be legitimate. If we find one, return the new, valid address.
13082 This macro is used in only one place: `memory_address' in explow.c.
13084 OLDX is the address as it was before break_out_memory_refs was called.
13085 In some cases it is useful to look at this to decide what needs to be done.
13087 It is always safe for this macro to do nothing. It exists to recognize
13088 opportunities to optimize the output.
13090 For the 80386, we handle X+REG by loading X into a register R and
13091 using R+REG. R will go in a general reg and indexing will be used.
13092 However, if REG is a broken-out memory address or multiplication,
13093 nothing needs to be done because REG can certainly go in a general reg.
13095 When -fpic is used, special handling is needed for symbolic references.
13096 See comments by legitimize_pic_address in i386.c for details. */
13098 static rtx
13101 {
13112 {
13116 }
13119 {
13126 {
13129 }
13130 }
13135 #if TARGET_MACHO
13138 #endif
13140 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13144 {
13149 }
13152 {
13153 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13158 {
13164 }
13169 {
13175 }
13177 /* Put multiply first if it isn't already. */
13179 {
13184 }
13186 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13187 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13188 created by virtual register instantiation, register elimination, and
13189 similar optimizations. */
13191 {
13197 }
13199 /* Canonicalize
13200 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13201 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13206 {
13207 rtx constant;
13211 {
13214 }
13216 {
13219 }
13220 else
13224 {
13231 }
13232 }
13238 {
13241 }
13244 {
13247 }
13255 {
13258 }
13264 {
13268 {
13271 }
13275 }
13278 {
13282 {
13285 }
13289 }
13290 }
13293 }
13294 \f
13295 /* Print an integer constant expression in assembler syntax. Addition
13296 and subtraction are the only arithmetic that may appear in these
13297 expressions. FILE is the stdio stream to write to, X is the rtx, and
13298 CODE is the operand print code from the output string. */
13300 static void
13302 {
13306 {
13315 else
13316 {
13319 /* Mark the decl as referenced so that cgraph will
13320 output the function. */
13324 #if TARGET_MACHO
13328 #endif
13330 }
13338 /* FALLTHRU */
13349 /* This used to output parentheses around the expression,
13350 but that does not work on the 386 (either ATT or BSD assembler). */
13356 {
13357 /* We can use %d if the number is <32 bits and positive. */
13362 else
13364 }
13365 else
13366 /* We can't handle floating point constants;
13367 TARGET_PRINT_OPERAND must handle them. */
13372 /* Some assemblers need integer constants to appear first. */
13374 {
13378 }
13379 else
13380 {
13385 }
13400 {
13404 }
13409 {
13428 /* FIXME: This might be @TPOFF in Sun ld too. */
13437 else
13447 else
13453 #if TARGET_MACHO
13458 #endif
13462 }
13467 }
13468 }
13470 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13471 We need to emit DTP-relative relocations. */
13473 static void ATTRIBUTE_UNUSED
13475 {
13480 {
13488 }
13489 }
13491 /* Return true if X is a representation of the PIC register. This copes
13492 with calls from ix86_find_base_term, where the register might have
13493 been replaced by a cselib value. */
13495 static bool
13497 {
13501 else
13503 }
13505 /* Helper function for ix86_delegitimize_address.
13506 Attempt to delegitimize TLS local-exec accesses. */
13508 static rtx
13510 {
13535 {
13540 }
13546 }
13548 /* In the name of slightly smaller debug output, and to cater to
13549 general assembler lossage, recognize PIC+GOTOFF and turn it back
13550 into a direct symbol reference.
13552 On Darwin, this is necessary to avoid a crash, because Darwin
13553 has a different PIC label for each routine but the DWARF debugging
13554 information is not associated with any particular routine, so it's
13555 necessary to remove references to the PIC label from RTL stored by
13556 the DWARF output code. */
13558 static rtx
13560 {
13562 /* addend is NULL or some rtx if x is something+GOTOFF where
13563 something doesn't include the PIC register. */
13565 /* reg_addend is NULL or a multiple of some register. */
13567 /* const_addend is NULL or a const_int. */
13569 /* This is the result, or NULL. */
13578 {
13585 {
13591 }
13600 {
13605 }
13607 }
13614 /* %ebx + GOT/GOTOFF */
13615 ;
13617 {
13618 /* %ebx + %reg * scale + GOT/GOTOFF */
13624 else
13625 {
13628 }
13629 }
13630 else
13636 {
13639 }
13658 {
13659 /* If the rest of original X doesn't involve the PIC register, add
13660 addend and subtract pic_offset_table_rtx. This can happen e.g.
13661 for code like:
13662 leal (%ebx, %ecx, 4), %ecx
13663 ...
13664 movl foo@GOTOFF(%ecx), %edx
13665 in which case we return (%ecx - %ebx) + foo. */
13668 pic_offset_table_rtx),
13669 result);
13670 else
13672 }
13674 {
13678 }
13680 }
13682 /* If X is a machine specific address (i.e. a symbol or label being
13683 referenced as a displacement from the GOT implemented using an
13684 UNSPEC), then return the base term. Otherwise return X. */
13686 rtx
13688 {
13689 rtx term;
13692 {
13706 }
13709 }
13710 \f
13711 static void
13714 {
13718 {
13721 }
13726 {
13729 {
13748 }
13752 {
13771 }
13778 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13779 Those same assemblers have the same but opposite lossage on cmov. */
13784 else
13789 {
13802 }
13810 {
13823 }
13826 /* ??? As above. */
13835 /* ??? As above. */
13840 else
13851 }
13853 }
13855 /* Print the name of register X to FILE based on its machine mode and number.
13856 If CODE is 'w', pretend the mode is HImode.
13857 If CODE is 'b', pretend the mode is QImode.
13858 If CODE is 'k', pretend the mode is SImode.
13859 If CODE is 'q', pretend the mode is DImode.
13860 If CODE is 'x', pretend the mode is V4SFmode.
13861 If CODE is 't', pretend the mode is V8SFmode.
13862 If CODE is 'h', pretend the reg is the 'high' byte register.
13863 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13864 If CODE is 'd', duplicate the operand for AVX instruction.
13865 */
13867 void
13869 {
13878 {
13882 }
13907 else
13910 /* Irritatingly, AMD extended registers use different naming convention
13911 from the normal registers: "r%d[bwd]" */
13913 {
13918 {
13932 /* no suffix */
13937 }
13939 }
13943 {
13946 {
13949 }
13950 /* FALLTHRU */
13956 /* FALLTHRU */
13959 normal:
13974 {
13979 }
13983 }
13987 {
13990 else
13992 }
13993 }
13995 /* Locate some local-dynamic symbol still in use by this function
13996 so that we can print its name in some tls_local_dynamic_base
13997 pattern. */
13999 static int
14001 {
14006 {
14009 }
14012 }
14016 {
14017 rtx insn;
14028 }
14030 /* Meaning of CODE:
14031 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14032 C -- print opcode suffix for set/cmov insn.
14033 c -- like C, but print reversed condition
14034 F,f -- likewise, but for floating-point.
14035 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14036 otherwise nothing
14037 R -- print the prefix for register names.
14038 z -- print the opcode suffix for the size of the current operand.
14039 Z -- likewise, with special suffixes for x87 instructions.
14040 * -- print a star (in certain assembler syntax)
14041 A -- print an absolute memory reference.
14042 E -- print address with DImode register names if TARGET_64BIT.
14043 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14044 s -- print a shift double count, followed by the assemblers argument
14045 delimiter.
14046 b -- print the QImode name of the register for the indicated operand.
14047 %b0 would print %al if operands[0] is reg 0.
14048 w -- likewise, print the HImode name of the register.
14049 k -- likewise, print the SImode name of the register.
14050 q -- likewise, print the DImode name of the register.
14051 x -- likewise, print the V4SFmode name of the register.
14052 t -- likewise, print the V8SFmode name of the register.
14053 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14054 y -- print "st(0)" instead of "st" as a register.
14055 d -- print duplicated register operand for AVX instruction.
14056 D -- print condition for SSE cmp instruction.
14057 P -- if PIC, print an @PLT suffix.
14058 p -- print raw symbol name.
14059 X -- don't print any sort of PIC '@' suffix for a symbol.
14060 & -- print some in-use local-dynamic symbol name.
14061 H -- print a memory address offset by 8; used for sse high-parts
14062 Y -- print condition for XOP pcom* instruction.
14063 + -- print a branch hint as 'cs' or 'ds' prefix
14064 ; -- print a semicolon (after prefixes due to bug in older gas).
14065 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14066 @ -- print a segment register of thread base pointer load
14067 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14068 */
14070 void
14072 {
14074 {
14076 {
14079 {
14085 /* Intel syntax. For absolute addresses, registers should not
14086 be surrounded by braces. */
14088 {
14093 }
14098 }
14104 /* Wrap address in an UNSPEC to declare special handling. */
14142 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14147 {
14161 output_operand_lossage
14164 }
14167 #endif
14172 {
14173 /* Opcodes don't get size suffixes if using Intel opcodes. */
14178 {
14196 output_operand_lossage
14199 }
14200 }
14203 warning
14205 /* FALLTHRU */
14208 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14213 {
14215 {
14217 #ifdef HAVE_AS_IX86_FILDS
14219 #endif
14227 #ifdef HAVE_AS_IX86_FILDQ
14229 #else
14231 #endif
14236 }
14237 }
14239 {
14240 /* 387 opcodes don't get size suffixes
14241 if the operands are registers. */
14246 {
14262 }
14263 }
14264 else
14265 {
14266 output_operand_lossage
14269 }
14271 output_operand_lossage
14291 {
14294 }
14299 {
14350 }
14354 /* Little bit of braindamage here. The SSE compare instructions
14355 does use completely different names for the comparisons that the
14356 fp conditional moves. */
14358 {
14361 {
14364 }
14370 {
14373 }
14379 {
14382 }
14391 {
14394 }
14400 {
14403 }
14409 {
14412 }
14423 }
14428 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14431 #endif
14436 {
14440 }
14444 file);
14449 {
14453 }
14454 /* It doesn't actually matter what mode we use here, as we're
14455 only going to use this for printing. */
14463 #ifdef HAVE_AS_IX86_HLE
14465 #else
14467 #endif
14469 #ifdef HAVE_AS_IX86_HLE
14471 #else
14473 #endif
14474 /* We do not want to print value of the operand. */
14483 {
14488 else
14491 }
14494 {
14495 rtx x;
14504 {
14509 {
14511 bool cputaken
14514 /* Emit hints only in the case default branch prediction
14515 heuristics would fail. */
14517 {
14518 /* We use 3e (DS) prefix for taken branches and
14519 2e (CS) prefix for not taken branches. */
14522 else
14524 }
14525 }
14526 }
14528 }
14531 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14533 #endif
14540 /* The kernel uses a different segment register for performance
14541 reasons; a system call would not have to trash the userspace
14542 segment register, which would be expensive. */
14545 else
14560 }
14561 }
14567 {
14568 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14571 {
14574 {
14583 else
14589 }
14591 /* Check for explicit size override (codes 'b', 'w', 'k',
14592 'q' and 'x') */
14606 }
14609 /* Avoid (%rip) for call operands. */
14615 else
14617 }
14620 {
14621 REAL_VALUE_TYPE r;
14629 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14633 else
14635 }
14638 {
14639 REAL_VALUE_TYPE r;
14648 }
14650 /* These float cases don't actually occur as immediate operands. */
14652 {
14657 }
14659 else
14660 {
14661 /* We have patterns that allow zero sets of memory, for instance.
14662 In 64-bit mode, we should probably support all 8-byte vectors,
14663 since we can in fact encode that into an immediate. */
14665 {
14668 }
14671 {
14673 {
14676 }
14679 {
14682 else
14684 }
14685 }
14690 else
14692 }
14693 }
14695 static bool
14697 {
14700 }
14701 \f
14702 /* Print a memory operand whose address is ADDR. */
14704 static void
14706 {
14715 {
14722 }
14724 {
14728 }
14729 else
14740 {
14751 }
14753 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14755 {
14767 }
14769 {
14770 /* Displacement only requires special attention. */
14773 {
14777 }
14780 else
14782 }
14783 else
14784 {
14785 /* Print SImode register names to force addr32 prefix. */
14787 {
14788 #ifdef ENABLE_CHECKING
14791 {
14802 }
14803 #endif
14806 }
14808 && TARGET_X32
14809 && disp
14812 {
14813 /* X32 runs in 64-bit mode, where displacement, DISP, in
14814 address DISP(%r64), is encoded as 32-bit immediate sign-
14815 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14816 address is %r64 + 0xffffffffbffffd00. When %r64 <
14817 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14818 which is invalid for x32. The correct address is %r64
14819 - 0x40000300 == 0xf7ffdd64. To properly encode
14820 -0x40000300(%r64) for x32, we zero-extend negative
14821 displacement by forcing addr32 prefix which truncates
14822 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14823 zero-extend all negative displacements, including -1(%rsp).
14824 However, for small negative displacements, sign-extension
14825 won't cause overflow. We only zero-extend negative
14826 displacements if they < -16*1024*1024, which is also used
14827 to check legitimate address displacements for PIC. */
14829 }
14832 {
14834 {
14839 else
14841 }
14847 {
14852 }
14854 }
14855 else
14856 {
14860 {
14861 /* Pull out the offset of a symbol; print any symbol itself. */
14865 {
14869 }
14877 else
14879 }
14883 {
14886 {
14890 }
14891 }
14894 else
14898 {
14903 }
14905 }
14906 }
14907 }
14909 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14911 static bool
14913 {
14914 rtx op;
14921 {
14924 /* FIXME: This might be @TPOFF in Sun ld. */
14935 else
14947 else
14954 #if TARGET_MACHO
14960 #endif
14963 {
14968 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14970 #else
14972 #endif
14975 }
14980 }
14983 }
14984 \f
14985 /* Split one or more double-mode RTL references into pairs of half-mode
14986 references. The RTL can be REG, offsettable MEM, integer constant, or
14987 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14988 split and "num" is its length. lo_half and hi_half are output arrays
14989 that parallel "operands". */
14991 void
14994 {
14999 {
15008 }
15013 {
15016 /* simplify_subreg refuse to split volatile memory addresses,
15017 but we still have to handle it. */
15019 {
15022 }
15023 else
15024 {
15031 }
15032 }
15033 }
15034 \f
15035 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15036 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15037 is the expression of the binary operation. The output may either be
15038 emitted here, or returned to the caller, like all output_* functions.
15040 There is no guarantee that the operands are the same mode, as they
15041 might be within FLOAT or FLOAT_EXTEND expressions. */
15043 #ifndef SYSV386_COMPAT
15044 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15045 wants to fix the assemblers because that causes incompatibility
15046 with gcc. No-one wants to fix gcc because that causes
15047 incompatibility with assemblers... You can use the option of
15048 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15049 #define SYSV386_COMPAT 1
15050 #endif
15054 {
15060 #ifdef ENABLE_CHECKING
15061 /* Even if we do not want to check the inputs, this documents input
15062 constraints. Which helps in understanding the following code. */
15072 else
15074 #endif
15077 {
15082 else
15091 else
15100 else
15109 else
15116 }
15119 {
15121 {
15125 else
15127 }
15128 else
15129 {
15133 else
15135 }
15137 }
15141 {
15145 {
15149 }
15151 /* know operands[0] == operands[1]. */
15154 {
15157 }
15160 {
15162 /* How is it that we are storing to a dead operand[2]?
15163 Well, presumably operands[1] is dead too. We can't
15164 store the result to st(0) as st(0) gets popped on this
15165 instruction. Instead store to operands[2] (which I
15166 think has to be st(1)). st(1) will be popped later.
15167 gcc <= 2.8.1 didn't have this check and generated
15168 assembly code that the Unixware assembler rejected. */
15170 else
15173 }
15177 else
15184 {
15187 }
15190 {
15193 }
15196 {
15197 #if SYSV386_COMPAT
15198 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15199 derived assemblers, confusingly reverse the direction of
15200 the operation for fsub{r} and fdiv{r} when the
15201 destination register is not st(0). The Intel assembler
15202 doesn't have this brain damage. Read !SYSV386_COMPAT to
15203 figure out what the hardware really does. */
15206 else
15208 #else
15210 /* As above for fmul/fadd, we can't store to st(0). */
15212 else
15214 #endif
15216 }
15219 {
15220 #if SYSV386_COMPAT
15223 else
15225 #else
15228 else
15230 #endif
15232 }
15235 {
15238 else
15241 }
15243 {
15244 #if SYSV386_COMPAT
15246 #else
15248 #endif
15249 }
15250 else
15251 {
15252 #if SYSV386_COMPAT
15254 #else
15256 #endif
15257 }
15262 }
15266 }
15268 /* Check if a 256bit AVX register is referenced inside of EXP. */
15270 static int
15272 {
15283 }
15285 /* Return needed mode for entity in optimize_mode_switching pass. */
15287 static int
15289 {
15291 {
15292 rtx link;
15294 /* Needed mode is set to AVX_U128_CLEAN if there are
15295 no 256bit modes used in function arguments. */
15297 link;
15299 {
15301 {
15306 }
15307 }
15310 }
15312 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15313 changes state only when a 256bit register is written to, but we need
15314 to prevent the compiler from moving optimal insertion point above
15315 eventual read from 256bit register. */
15320 }
15322 /* Return mode that i387 must be switched into
15323 prior to the execution of insn. */
15325 static int
15327 {
15330 /* The mode UNINITIALIZED is used to store control word after a
15331 function call or ASM pattern. The mode ANY specify that function
15332 has no requirements on the control word and make no changes in the
15333 bits we are interested in. */
15347 {
15370 }
15373 }
15375 /* Return mode that entity must be switched into
15376 prior to the execution of insn. */
15378 int
15380 {
15382 {
15392 }
15394 }
15396 /* Check if a 256bit AVX register is referenced in stores. */
15398 static void
15400 {
15402 {
15405 }
15406 }
15408 /* Calculate mode of upper 128bit AVX registers after the insn. */
15410 static int
15412 {
15419 /* We know that state is clean after CALL insn if there are no
15420 256bit registers used in the function return register. */
15422 {
15427 }
15429 /* Otherwise, return current mode. Remember that if insn
15430 references AVX 256bit registers, the mode was already changed
15431 to DIRTY from MODE_NEEDED. */
15433 }
15435 /* Return the mode that an insn results in. */
15437 int
15439 {
15441 {
15451 }
15452 }
15454 static int
15456 {
15457 tree arg;
15459 /* Entry mode is set to AVX_U128_DIRTY if there are
15460 256bit modes used in function arguments. */
15463 {
15468 }
15471 }
15473 /* Return a mode that ENTITY is assumed to be
15474 switched to at function entry. */
15476 int
15478 {
15480 {
15490 }
15491 }
15493 static int
15495 {
15498 /* Exit mode is set to AVX_U128_DIRTY if there are
15499 256bit modes used in the function return register. */
15504 }
15506 /* Return a mode that ENTITY is assumed to be
15507 switched to at function exit. */
15509 int
15511 {
15513 {
15523 }
15524 }
15526 /* Output code to initialize control word copies used by trunc?f?i and
15527 rounding patterns. CURRENT_MODE is set to current control word,
15528 while NEW_MODE is set to new control word. */
15530 static void
15532 {
15534 rtx new_mode;
15545 {
15547 {
15549 /* round toward zero (truncate) */
15555 /* round down toward -oo */
15562 /* round up toward +oo */
15569 /* mask precision exception for nearbyint() */
15576 }
15577 }
15578 else
15579 {
15581 {
15583 /* round toward zero (truncate) */
15589 /* round down toward -oo */
15595 /* round up toward +oo */
15601 /* mask precision exception for nearbyint() */
15608 }
15609 }
15615 }
15617 /* Emit vzeroupper. */
15619 void
15621 {
15624 /* Cancel automatic vzeroupper insertion if there are
15625 live call-saved SSE registers at the insertion point. */
15637 }
15639 /* Generate one or more insns to set ENTITY to MODE. */
15641 void
15643 {
15645 {
15660 }
15661 }
15663 /* Output code for INSN to convert a float to a signed int. OPERANDS
15664 are the insn operands. The output may be [HSD]Imode and the input
15665 operand may be [SDX]Fmode. */
15669 {
15674 /* Jump through a hoop or two for DImode, since the hardware has no
15675 non-popping instruction. We used to do this a different way, but
15676 that was somewhat fragile and broke with post-reload splitters. */
15686 else
15687 {
15692 else
15696 }
15699 }
15701 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15702 have the values zero or one, indicates the ffreep insn's operand
15703 from the OPERANDS array. */
15707 {
15709 #ifdef HAVE_AS_IX86_FFREEP
15711 #else
15712 {
15722 }
15723 #endif
15726 }
15729 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15730 should be used. UNORDERED_P is true when fucom should be used. */
15734 {
15740 {
15743 }
15744 else
15745 {
15748 }
15751 {
15755 else
15757 else
15760 else
15762 }
15769 {
15771 {
15774 }
15775 else
15777 }
15780 && stack_top_dies
15783 {
15784 /* If both the top of the 387 stack dies, and the other operand
15785 is also a stack register that dies, then this must be a
15786 `fcompp' float compare */
15789 {
15790 /* There is no double popping fcomi variant. Fortunately,
15791 eflags is immune from the fstp's cc clobbering. */
15794 else
15797 }
15798 else
15799 {
15802 else
15804 }
15805 }
15806 else
15807 {
15808 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15811 {
15819 NULL,
15820 NULL,
15827 NULL,
15828 NULL,
15829 NULL,
15830 NULL
15831 };
15846 }
15847 }
15849 void
15851 {
15854 #ifdef ASM_QUAD
15857 #else
15859 #endif
15862 }
15864 void
15866 {
15869 #ifdef ASM_QUAD
15872 #else
15874 #endif
15875 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15881 #if TARGET_MACHO
15883 {
15887 }
15888 #endif
15889 else
15892 }
15893 \f
15894 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15895 for the target. */
15897 void
15899 {
15900 rtx tmp;
15902 /* We play register width games, which are only valid after reload. */
15905 /* Avoid HImode and its attendant prefix byte. */
15910 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15912 {
15915 }
15918 }
15920 /* X is an unchanging MEM. If it is a constant pool reference, return
15921 the constant pool rtx, else NULL. */
15923 rtx
15925 {
15932 }
15934 void
15936 {
15944 {
15947 {
15953 }
15957 }
15961 {
15974 {
15981 }
15982 }
15986 {
15988 {
15989 #if TARGET_MACHO
15990 /* dynamic-no-pic */
15992 {
15993 rtx temp = ((reload_in_progress
16001 }
16003 {
16007 }
16010 else
16011 {
16019 }
16020 /* dynamic-no-pic */
16021 #endif
16022 }
16023 else
16024 {
16028 {
16034 }
16035 }
16036 }
16037 else
16038 {
16049 /* Force large constants in 64bit compilation into register
16050 to get them CSEed. */
16062 {
16063 /* If we are loading a floating point constant to a register,
16064 force the value to memory now, since we'll get better code
16065 out the back end. */
16069 {
16074 }
16075 }
16076 }
16079 }
16081 void
16083 {
16087 /* Force constants other than zero into memory. We do not know how
16088 the instructions used to build constants modify the upper 64 bits
16089 of the register, once we have that information we may be able
16090 to handle some of them more efficiently. */
16099 /* We need to check memory alignment for SSE mode since attribute
16100 can make operands unaligned. */
16105 {
16108 /* ix86_expand_vector_move_misalign() does not like constants ... */
16114 /* ... nor both arguments in memory. */
16122 }
16124 /* Make operand1 a register if it isn't already. */
16128 {
16131 }
16134 }
16136 /* Split 32-byte AVX unaligned load and store if needed. */
16138 static void
16140 {
16141 rtx m;
16148 {
16169 }
16172 {
16174 {
16181 }
16182 else
16184 }
16186 {
16188 {
16193 }
16194 else
16196 }
16197 else
16199 }
16201 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16202 straight to ix86_expand_vector_move. */
16203 /* Code generation for scalar reg-reg moves of single and double precision data:
16204 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16205 movaps reg, reg
16206 else
16207 movss reg, reg
16208 if (x86_sse_partial_reg_dependency == true)
16209 movapd reg, reg
16210 else
16211 movsd reg, reg
16213 Code generation for scalar loads of double precision data:
16214 if (x86_sse_split_regs == true)
16215 movlpd mem, reg (gas syntax)
16216 else
16217 movsd mem, reg
16219 Code generation for unaligned packed loads of single precision data
16220 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16221 if (x86_sse_unaligned_move_optimal)
16222 movups mem, reg
16224 if (x86_sse_partial_reg_dependency == true)
16225 {
16226 xorps reg, reg
16227 movlps mem, reg
16228 movhps mem+8, reg
16229 }
16230 else
16231 {
16232 movlps mem, reg
16233 movhps mem+8, reg
16234 }
16236 Code generation for unaligned packed loads of double precision data
16237 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16238 if (x86_sse_unaligned_move_optimal)
16239 movupd mem, reg
16241 if (x86_sse_split_regs == true)
16242 {
16243 movlpd mem, reg
16244 movhpd mem+8, reg
16245 }
16246 else
16247 {
16248 movsd mem, reg
16249 movhpd mem+8, reg
16250 }
16251 */
16253 void
16255 {
16263 {
16265 {
16270 /* FALLTHRU */
16278 }
16281 }
16284 {
16285 /* ??? If we have typed data, then it would appear that using
16286 movdqu is the only way to get unaligned data loaded with
16287 integer type. */
16289 {
16292 /* We will eventually emit movups based on insn attributes. */
16294 }
16296 {
16297 rtx zero;
16300 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16301 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16303 {
16304 /* We will eventually emit movups based on insn attributes. */
16307 }
16309 /* When SSE registers are split into halves, we can avoid
16310 writing to the top half twice. */
16312 {
16315 }
16316 else
16317 {
16318 /* ??? Not sure about the best option for the Intel chips.
16319 The following would seem to satisfy; the register is
16320 entirely cleared, breaking the dependency chain. We
16321 then store to the upper half, with a dependency depth
16322 of one. A rumor has it that Intel recommends two movsd
16323 followed by an unpacklpd, but this is unconfirmed. And
16324 given that the dependency depth of the unpacklpd would
16325 still be one, I'm not sure why this would be better. */
16327 }
16333 }
16334 else
16335 {
16337 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16338 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16340 {
16345 }
16349 else
16359 }
16360 }
16362 {
16364 {
16367 /* We will eventually emit movups based on insn attributes. */
16369 }
16371 {
16373 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16374 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16376 /* We will eventually emit movups based on insn attributes. */
16378 else
16379 {
16384 }
16385 }
16386 else
16387 {
16392 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16393 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16395 {
16398 }
16399 else
16400 {
16405 }
16406 }
16407 }
16408 else
16410 }
16412 /* Expand a push in MODE. This is some mode for which we do not support
16413 proper push instructions, at least from the registers that we expect
16414 the value to live in. */
16416 void
16418 {
16419 rtx tmp;
16429 /* When we push an operand onto stack, it has to be aligned at least
16430 at the function argument boundary. However since we don't have
16431 the argument type, we can't determine the actual argument
16432 boundary. */
16434 }
16436 /* Helper function of ix86_fixup_binary_operands to canonicalize
16437 operand order. Returns true if the operands should be swapped. */
16439 static bool
16441 rtx operands[])
16442 {
16447 /* If the operation is not commutative, we can't do anything. */
16451 /* Highest priority is that src1 should match dst. */
16457 /* Next highest priority is that immediate constants come second. */
16463 /* Lowest priority is that memory references should come second. */
16470 }
16473 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16474 destination to use for the operation. If different from the true
16475 destination in operands[0], a copy operation will be required. */
16477 rtx
16479 rtx operands[])
16480 {
16485 /* Canonicalize operand order. */
16487 {
16488 rtx temp;
16490 /* It is invalid to swap operands of different modes. */
16496 }
16498 /* Both source operands cannot be in memory. */
16500 {
16501 /* Optimization: Only read from memory once. */
16503 {
16506 }
16507 else
16509 }
16511 /* If the destination is memory, and we do not have matching source
16512 operands, do things in registers. */
16516 /* Source 1 cannot be a constant. */
16520 /* Source 1 cannot be a non-matching memory. */
16524 /* Improve address combine. */
16533 }
16535 /* Similarly, but assume that the destination has already been
16536 set up properly. */
16538 void
16541 {
16544 }
16546 /* Attempt to expand a binary operator. Make the expansion closer to the
16547 actual machine, then just general_operand, which will allow 3 separate
16548 memory references (one output, two input) in a single insn. */
16550 void
16552 rtx operands[])
16553 {
16560 /* Emit the instruction. */
16564 {
16565 /* Reload doesn't know about the flags register, and doesn't know that
16566 it doesn't want to clobber it. We can only do this with PLUS. */
16569 }
16573 {
16574 /* This is going to be an LEA; avoid splitting it later. */
16576 }
16577 else
16578 {
16581 }
16583 /* Fix up the destination if needed. */
16586 }
16588 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16589 the given OPERANDS. */
16591 void
16593 rtx operands[])
16594 {
16597 {
16600 }
16602 {
16605 }
16606 /* Optimize (__m128i) d | (__m128i) e and similar code
16607 when d and e are float vectors into float vector logical
16608 insn. In C/C++ without using intrinsics there is no other way
16609 to express vector logical operation on float vectors than
16610 to cast them temporarily to integer vectors. */
16612 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16621 {
16622 rtx dst;
16624 {
16631 {
16634 }
16635 else
16636 {
16641 }
16652 }
16653 }
16662 }
16664 /* Return TRUE or FALSE depending on whether the binary operator meets the
16665 appropriate constraints. */
16667 bool
16670 {
16675 /* Both source operands cannot be in memory. */
16679 /* Canonicalize operand order for commutative operators. */
16681 {
16685 }
16687 /* If the destination is memory, we must have a matching source operand. */
16691 /* Source 1 cannot be a constant. */
16695 /* Source 1 cannot be a non-matching memory. */
16697 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16705 }
16707 /* Attempt to expand a unary operator. Make the expansion closer to the
16708 actual machine, then just general_operand, which will allow 2 separate
16709 memory references (one output, one input) in a single insn. */
16711 void
16713 rtx operands[])
16714 {
16721 /* If the destination is memory, and we do not have matching source
16722 operands, do things in registers. */
16725 {
16728 else
16730 }
16732 /* When source operand is memory, destination must match. */
16736 /* Emit the instruction. */
16740 {
16741 /* Reload doesn't know about the flags register, and doesn't know that
16742 it doesn't want to clobber it. */
16745 }
16746 else
16747 {
16750 }
16752 /* Fix up the destination if needed. */
16755 }
16757 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16758 divisor are within the range [0-255]. */
16760 void
16763 {
16772 {
16785 }
16792 /* Use 8bit unsigned divimod if dividend and divisor are within
16793 the range [0-255]. */
16802 pc_rtx);
16807 /* Generate original signed/unsigned divimod. */
16812 /* Branch to the end. */
16816 /* Generate 8bit unsigned divide. */
16818 /* Don't use operands[0] for result of 8bit divide since not all
16819 registers support QImode ZERO_EXTRACT. */
16826 {
16829 }
16830 else
16831 {
16834 }
16836 /* Extract remainder from AH. */
16840 else
16841 {
16842 /* Need a new scratch register since the old one has result
16843 of 8bit divide. */
16847 }
16850 /* Zero extend quotient from AL. */
16856 }
16858 #define LEA_MAX_STALL (3)
16859 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16861 /* Increase given DISTANCE in half-cycles according to
16862 dependencies between PREV and NEXT instructions.
16863 Add 1 half-cycle if there is no dependency and
16864 go to next cycle if there is some dependecy. */
16866 static unsigned int
16868 {
16885 }
16887 /* Function checks if instruction INSN defines register number
16888 REGNO1 or REGNO2. */
16890 static bool
16892 rtx insn)
16893 {
16901 {
16903 }
16906 }
16908 /* Function checks if instruction INSN uses register number
16909 REGNO as a part of address expression. */
16911 static bool
16913 {
16921 }
16923 /* Search backward for non-agu definition of register number REGNO1
16924 or register number REGNO2 in basic block starting from instruction
16925 START up to head of basic block or instruction INSN.
16927 Function puts true value into *FOUND var if definition was found
16928 and false otherwise.
16930 Distance in half-cycles between START and found instruction or head
16931 of BB is added to DISTANCE and returned. */
16933 static int
16937 {
16947 {
16949 {
16952 {
16955 {
16958 }
16959 }
16962 }
16967 }
16970 }
16972 /* Search backward for non-agu definition of register number REGNO1
16973 or register number REGNO2 in INSN's basic block until
16974 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16975 2. Reach neighbour BBs boundary, or
16976 3. Reach agu definition.
16977 Returns the distance between the non-agu definition point and INSN.
16978 If no definition point, returns -1. */
16980 static int
16982 rtx insn)
16983 {
16994 {
16995 edge e;
16996 edge_iterator ei;
17001 {
17004 }
17010 else
17011 {
17016 {
17017 int bb_dist
17023 {
17030 }
17031 }
17034 }
17035 }
17037 /* get_attr_type may modify recog data. We want to make sure
17038 that recog data is valid for instruction INSN, on which
17039 distance_non_agu_define is called. INSN is unchanged here. */
17046 }
17048 /* Return the distance in half-cycles between INSN and the next
17049 insn that uses register number REGNO in memory address added
17050 to DISTANCE. Return -1 if REGNO0 is set.
17052 Put true value into *FOUND if register usage was found and
17053 false otherwise.
17054 Put true value into *REDEFINED if register redefinition was
17055 found and false otherwise. */
17057 static int
17061 {
17072 {
17074 {
17077 {
17078 /* Return DISTANCE if OP0 is used in memory
17079 address in NEXT. */
17082 }
17085 {
17086 /* Return -1 if OP0 is set in NEXT. */
17089 }
17092 }
17098 }
17101 }
17103 /* Return the distance between INSN and the next insn that uses
17104 register number REGNO0 in memory address. Return -1 if no such
17105 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17107 static int
17109 {
17121 {
17122 edge e;
17123 edge_iterator ei;
17128 {
17131 }
17137 else
17138 {
17144 {
17145 int bb_dist
17150 {
17157 }
17158 }
17161 }
17162 }
17168 }
17170 /* Define this macro to tune LEA priority vs ADD, it take effect when
17171 there is a dilemma of choicing LEA or ADD
17172 Negative value: ADD is more preferred than LEA
17173 Zero: Netrual
17174 Positive value: LEA is more preferred than ADD*/
17175 #define IX86_LEA_PRIORITY 0
17177 /* Return true if usage of lea INSN has performance advantage
17178 over a sequence of instructions. Instructions sequence has
17179 SPLIT_COST cycles higher latency than lea latency. */
17181 static bool
17184 {
17191 {
17192 /* If there is no non AGU operand definition, no AGU
17193 operand usage and split cost is 0 then both lea
17194 and non lea variants have same priority. Currently
17195 we prefer lea for 64 bit code and non lea on 32 bit
17196 code. */
17199 else
17201 }
17203 /* With longer definitions distance lea is more preferable.
17204 Here we change it to take into account splitting cost and
17205 lea priority. */
17208 /* If there is no use in memory addess then we just check
17209 that split cost exceeds AGU stall. */
17213 /* If this insn has both backward non-agu dependence and forward
17214 agu dependence, the one with short distance takes effect. */
17216 }
17218 /* Return true if it is legal to clobber flags by INSN and
17219 false otherwise. */
17221 static bool
17223 {
17226 bitmap live;
17229 {
17231 {
17238 }
17244 }
17248 }
17250 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17251 move and add to avoid AGU stalls. */
17253 bool
17255 {
17258 /* Check if we need to optimize. */
17262 /* Check it is correct to split here. */
17270 /* We need to split only adds with non destructive
17271 destination operand. */
17274 else
17276 }
17278 /* Return true if we should emit lea instruction instead of mov
17279 instruction. */
17281 bool
17283 {
17286 /* Check if we need to optimize. */
17290 /* Use lea for reg to reg moves only. */
17298 }
17300 /* Return true if we need to split lea into a sequence of
17301 instructions to avoid AGU stalls. */
17303 bool
17305 {
17311 /* Check we need to optimize. */
17315 /* Check it is correct to split here. */
17322 /* There should be at least two components in the address. */
17327 /* We should not split into add if non legitimate pic
17328 operand is used as displacement. */
17343 /* Compute how many cycles we will add to execution time
17344 if split lea into a sequence of instructions. */
17346 {
17347 /* Have to use mov instruction if non desctructive
17348 destination form is used. */
17352 /* Have to add index to base if both exist. */
17356 /* Have to use shift and adds if scale is 2 or greater. */
17358 {
17363 else
17365 }
17367 /* Have to use add instruction with immediate if
17368 disp is non zero. */
17372 /* Subtract the price of lea. */
17374 }
17377 }
17379 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17380 matches destination. RTX includes clobber of FLAGS_REG. */
17382 static void
17385 {
17392 }
17394 /* Return true if regno1 def is nearest to the insn. */
17396 static bool
17398 {
17405 {
17407 {
17410 }
17416 }
17418 /* None of the regs is defined in the bb. */
17420 }
17422 /* Split lea instructions into a sequence of instructions
17423 which are executed on ALU to avoid AGU stalls.
17424 It is assumed that it is allowed to clobber flags register
17425 at lea position. */
17427 void
17429 {
17445 {
17448 }
17451 {
17454 }
17460 {
17461 /* Case r1 = r1 + ... */
17463 {
17464 /* If we have a case r1 = r1 + C * r1 then we
17465 should use multiplication which is very
17466 expensive. Assume cost model is wrong if we
17467 have such case here. */
17472 }
17473 else
17474 {
17475 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17479 /* Use shift for scaling. */
17488 }
17489 }
17491 {
17494 }
17495 else
17496 {
17498 {
17501 }
17503 {
17506 }
17507 else
17508 {
17513 else
17514 {
17515 rtx tmp1;
17517 /* Find better operand for SET instruction, depending
17518 on which definition is farther from the insn. */
17521 else
17531 }
17534 }
17538 }
17539 }
17541 /* Return true if it is ok to optimize an ADD operation to LEA
17542 operation to avoid flag register consumation. For most processors,
17543 ADD is faster than LEA. For the processors like ATOM, if the
17544 destination register of LEA holds an actual address which will be
17545 used soon, LEA is better and otherwise ADD is better. */
17547 bool
17549 {
17554 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17562 }
17564 /* Return true if destination reg of SET_BODY is shift count of
17565 USE_BODY. */
17567 static bool
17569 {
17570 rtx set_dest;
17571 rtx shift_rtx;
17574 /* Retrieve destination of SET_BODY. */
17576 {
17585 use_body))
17590 }
17592 /* Retrieve shift count of USE_BODY. */
17594 {
17606 }
17614 {
17617 /* Return true if shift count is dest of SET_BODY. */
17619 {
17620 /* Add check since it can be invoked before register
17621 allocation in pre-reload schedule. */
17627 }
17628 }
17631 }
17633 /* Return true if destination reg of SET_INSN is shift count of
17634 USE_INSN. */
17636 bool
17638 {
17641 }
17643 /* Return TRUE or FALSE depending on whether the unary operator meets the
17644 appropriate constraints. */
17646 bool
17650 {
17651 /* If one of operands is memory, source and destination must match. */
17657 }
17659 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17660 are ok, keeping in mind the possible movddup alternative. */
17662 bool
17664 {
17670 }
17672 /* Post-reload splitter for converting an SF or DFmode value in an
17673 SSE register into an unsigned SImode. */
17675 void
17677 {
17688 /* Load up the value into the low element. We must ensure that the other
17689 elements are valid floats -- zero is the easiest such value. */
17691 {
17694 else
17696 }
17697 else
17698 {
17703 else
17705 }
17725 else
17730 }
17732 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17733 Expects the 64-bit DImode to be supplied in a pair of integral
17734 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17735 -mfpmath=sse, !optimize_size only. */
17737 void
17739 {
17743 rtx x;
17749 {
17752 }
17753 else
17754 {
17758 }
17766 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17769 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17770 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17771 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17772 (0x1.0p84 + double(fp_value_hi_xmm)).
17773 Note these exponents differ by 32. */
17777 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17778 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17787 /* Add the upper and lower DFmode values together. */
17790 else
17791 {
17795 }
17798 }
17800 /* Not used, but eases macroization of patterns. */
17801 void
17803 rtx input ATTRIBUTE_UNUSED)
17804 {
17806 }
17808 /* Convert an unsigned SImode value into a DFmode. Only currently used
17809 for SSE, but applicable anywhere. */
17811 void
17813 {
17814 REAL_VALUE_TYPE TWO31r;
17829 }
17831 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17832 32-bit mode; otherwise we have a direct convert instruction. */
17834 void
17836 {
17837 REAL_VALUE_TYPE TWO32r;
17855 }
17857 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17858 For x86_32, -mfpmath=sse, !optimize_size only. */
17859 void
17861 {
17862 REAL_VALUE_TYPE ONE16r;
17881 }
17883 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17884 a vector of unsigned ints VAL to vector of floats TARGET. */
17886 void
17888 {
17890 REAL_VALUE_TYPE TWO16r;
17897 else
17902 OPTAB_DIRECT);
17913 OPTAB_DIRECT);
17915 OPTAB_DIRECT);
17918 }
17920 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17921 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17922 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17923 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17925 rtx
17927 {
17928 REAL_VALUE_TYPE TWO31r;
17943 {
17949 }
17958 OPTAB_DIRECT);
17959 else
17960 {
17966 OPTAB_DIRECT);
17967 }
17970 }
17972 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17973 then replicate the value for all elements of the vector
17974 register. */
17976 rtx
17978 {
17980 rtvec v;
17984 {
18011 }
18012 }
18014 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18015 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18016 for an SSE register. If VECT is true, then replicate the mask for
18017 all elements of the vector register. If INVERT is true, then create
18018 a mask excluding the sign bit. */
18020 rtx
18022 {
18026 rtx v;
18027 rtx mask;
18029 /* Find the sign bit, sign extended to 2*HWI. */
18031 {
18051 else
18059 {
18062 }
18063 else
18064 {
18065 rtvec vec;
18071 {
18074 }
18075 else
18085 }
18090 }
18095 /* Force this value into the low part of a fp vector constant. */
18104 }
18106 /* Generate code for floating point ABS or NEG. */
18108 void
18110 rtx operands[])
18111 {
18122 {
18128 }
18130 /* NEG and ABS performed with SSE use bitwise mask operations.
18131 Create the appropriate mask now. */
18134 else
18144 {
18146 rtvec par;
18151 else
18152 {
18155 }
18157 }
18158 else
18160 }
18162 /* Expand a copysign operation. Special case operand 0 being a constant. */
18164 void
18166 {
18180 else
18184 {
18191 {
18194 else
18195 {
18199 }
18200 }
18210 else
18214 }
18215 else
18216 {
18226 else
18230 }
18231 }
18233 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18234 be a constant, and so has already been expanded into a vector constant. */
18236 void
18238 {
18254 {
18257 }
18258 }
18260 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18261 so we have to do two masks. */
18263 void
18265 {
18280 {
18281 /* Shouldn't happen often (it's useless, obviously), but when it does
18282 we'd generate incorrect code if we continue below. */
18285 }
18288 {
18299 }
18300 else
18301 {
18303 {
18305 }
18307 {
18311 }
18315 {
18318 }
18320 {
18325 }
18327 }
18331 }
18333 /* Return TRUE or FALSE depending on whether the first SET in INSN
18334 has source and destination with matching CC modes, and that the
18335 CC mode is at least as constrained as REQ_MODE. */
18337 bool
18339 {
18340 rtx set;
18351 {
18361 /* FALLTHRU */
18365 /* FALLTHRU */
18369 /* FALLTHRU */
18383 }
18386 }
18388 /* Generate insn patterns to do an integer compare of OPERANDS. */
18390 static rtx
18392 {
18399 /* This is very simple, but making the interface the same as in the
18400 FP case makes the rest of the code easier. */
18404 /* Return the test that should be put into the flags user, i.e.
18405 the bcc, scc, or cmov instruction. */
18407 }
18409 /* Figure out whether to use ordered or unordered fp comparisons.
18410 Return the appropriate mode to use. */
18412 enum machine_mode
18414 {
18415 /* ??? In order to make all comparisons reversible, we do all comparisons
18416 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18417 all forms trapping and nontrapping comparisons, we can make inequality
18418 comparisons trapping again, since it results in better code when using
18419 FCOM based compares. */
18421 }
18423 enum machine_mode
18425 {
18429 {
18432 }
18435 {
18436 /* Only zero flag is needed. */
18440 /* Codes needing carry flag. */
18443 /* Detect overflow checks. They need just the carry flag. */
18447 else
18451 /* Detect overflow checks. They need just the carry flag. */
18455 else
18457 /* Codes possibly doable only with sign flag when
18458 comparing against zero. */
18463 else
18464 /* For other cases Carry flag is not required. */
18466 /* Codes doable only with sign flag when comparing
18467 against zero, but we miss jump instruction for it
18468 so we need to use relational tests against overflow
18469 that thus needs to be zero. */
18474 else
18476 /* strcmp pattern do (use flags) and combine may ask us for proper
18477 mode. */
18482 }
18483 }
18485 /* Return the fixed registers used for condition codes. */
18487 static bool
18489 {
18493 }
18495 /* If two condition code modes are compatible, return a condition code
18496 mode which is compatible with both. Otherwise, return
18497 VOIDmode. */
18499 static enum machine_mode
18501 {
18518 {
18532 {
18546 }
18550 /* These are only compatible with themselves, which we already
18551 checked above. */
18553 }
18554 }
18557 /* Return a comparison we can do and that it is equivalent to
18558 swap_condition (code) apart possibly from orderedness.
18559 But, never change orderedness if TARGET_IEEE_FP, returning
18560 UNKNOWN in that case if necessary. */
18562 static enum rtx_code
18564 {
18566 {
18577 }
18578 }
18580 /* Return cost of comparison CODE using the best strategy for performance.
18581 All following functions do use number of instructions as a cost metrics.
18582 In future this should be tweaked to compute bytes for optimize_size and
18583 take into account performance of various instructions on various CPUs. */
18585 static int
18587 {
18590 /* The cost of code using bit-twiddling on %ah. */
18592 {
18615 }
18618 {
18625 }
18626 }
18628 /* Return strategy to use for floating-point. We assume that fcomi is always
18629 preferrable where available, since that is also true when looking at size
18630 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18632 enum ix86_fpcmp_strategy
18634 {
18635 /* Do fcomi/sahf based test when profitable. */
18644 }
18646 /* Swap, force into registers, or otherwise massage the two operands
18647 to a fp comparison. The operands are updated in place; the new
18648 comparison code is returned. */
18650 static enum rtx_code
18652 {
18658 /* All of the unordered compare instructions only work on registers.
18659 The same is true of the fcomi compare instructions. The XFmode
18660 compare instructions require registers except when comparing
18661 against zero or when converting operand 1 from fixed point to
18662 floating point. */
18671 {
18674 }
18675 else
18676 {
18677 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18678 things around if they appear profitable, otherwise force op0
18679 into a register. */
18685 {
18688 {
18689 rtx tmp;
18692 }
18693 }
18699 {
18704 {
18707 }
18708 else
18710 }
18711 }
18713 /* Try to rearrange the comparison to make it cheaper. */
18717 {
18718 rtx tmp;
18723 }
18728 }
18730 /* Convert comparison codes we use to represent FP comparison to integer
18731 code that will result in proper branch. Return UNKNOWN if no such code
18732 is available. */
18734 enum rtx_code
18736 {
18738 {
18761 }
18762 }
18764 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18766 static rtx
18768 {
18775 /* Do fcomi/sahf based test when profitable. */
18777 {
18782 tmp);
18790 tmp);
18799 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18806 /* In the unordered case, we have to check C2 for NaN's, which
18807 doesn't happen to work out to anything nice combination-wise.
18808 So do some bit twiddling on the value we've got in AH to come
18809 up with an appropriate set of condition codes. */
18813 {
18817 {
18820 }
18821 else
18822 {
18828 }
18833 {
18838 }
18839 else
18840 {
18843 }
18848 {
18851 }
18852 else
18853 {
18857 }
18862 {
18868 }
18869 else
18870 {
18873 }
18878 {
18883 }
18884 else
18885 {
18888 }
18893 {
18898 }
18899 else
18900 {
18903 }
18917 }
18922 }
18924 /* Return the test that should be put into the flags user, i.e.
18925 the bcc, scc, or cmov instruction. */
18928 const0_rtx);
18929 }
18931 static rtx
18933 {
18934 rtx ret;
18940 {
18943 }
18944 else
18948 }
18950 void
18952 {
18954 rtx tmp;
18957 {
18964 simple:
18968 pc_rtx);
18976 /* Expand DImode branch into multiple compare+branch. */
18977 {
18983 {
18986 }
18993 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18994 avoid two branches. This costs one extra insn, so disable when
18995 optimizing for size. */
19000 {
19018 }
19020 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19021 op1 is a constant and the low word is zero, then we can just
19022 examine the high word. Similarly for low word -1 and
19023 less-or-equal-than or greater-than. */
19027 {
19030 {
19033 }
19037 {
19040 }
19044 }
19046 /* Otherwise, we need two or three jumps. */
19055 {
19069 }
19071 /*
19072 * a < b =>
19073 * if (hi(a) < hi(b)) goto true;
19074 * if (hi(a) > hi(b)) goto false;
19075 * if (lo(a) < lo(b)) goto true;
19076 * false:
19077 */
19089 }
19094 }
19095 }
19097 /* Split branch based on floating point condition. */
19098 void
19101 {
19102 rtx condition;
19103 rtx i;
19106 {
19111 }
19114 tmp);
19116 /* Remove pushed operand from stack. */
19126 }
19128 void
19130 {
19131 rtx ret;
19138 }
19140 /* Expand comparison setting or clearing carry flag. Return true when
19141 successful and set pop for the operation. */
19142 static bool
19144 {
19148 /* Do not handle double-mode compares that go through special path. */
19153 {
19158 /* Shortcut: following common codes never translate
19159 into carry flag compares. */
19164 /* These comparisons require zero flag; swap operands so they won't. */
19167 {
19172 }
19174 /* Try to expand the comparison and verify that we end up with
19175 carry flag based comparison. This fails to be true only when
19176 we decide to expand comparison using arithmetic that is not
19177 too common scenario. */
19186 else
19195 }
19201 {
19206 /* Convert a==0 into (unsigned)a<1. */
19215 /* Convert a>b into b<a or a>=b-1. */
19219 {
19221 /* Bail out on overflow. We still can swap operands but that
19222 would force loading of the constant into register. */
19227 }
19228 else
19229 {
19234 }
19237 /* Convert a>=0 into (unsigned)a<0x80000000. */
19255 }
19256 /* Swapping operands may cause constant to appear as first operand. */
19258 {
19262 }
19266 }
19268 bool
19270 {
19294 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19295 HImode insns, we'd be swallowed in word prefix ops. */
19301 {
19305 HOST_WIDE_INT diff;
19308 /* Sign bit compares are better done using shifts than we do by using
19309 sbb. */
19312 {
19313 /* Detect overlap between destination and compare sources. */
19317 {
19318 rtx flags;
19327 {
19329 compare_code
19331 }
19333 /* To simplify rest of code, restrict to the GEU case. */
19335 {
19341 }
19342 else
19343 {
19346 reverse_condition_maybe_unordered
19348 else
19351 }
19360 else
19363 }
19364 else
19365 {
19368 else
19369 {
19374 }
19376 }
19379 {
19380 /*
19381 * cmpl op0,op1
19382 * sbbl dest,dest
19383 * [addl dest, ct]
19384 *
19385 * Size 5 - 8.
19386 */
19391 }
19393 {
19394 /*
19395 * cmpl op0,op1
19396 * sbbl dest,dest
19397 * orl $ct, dest
19398 *
19399 * Size 8.
19400 */
19404 }
19406 {
19407 /*
19408 * cmpl op0,op1
19409 * sbbl dest,dest
19410 * notl dest
19411 * [addl dest, cf]
19412 *
19413 * Size 8 - 11.
19414 */
19420 }
19421 else
19422 {
19423 /*
19424 * cmpl op0,op1
19425 * sbbl dest,dest
19426 * [notl dest]
19427 * andl cf - ct, dest
19428 * [addl dest, ct]
19429 *
19430 * Size 8 - 11.
19431 */
19434 {
19438 }
19448 }
19454 }
19457 {
19460 HOST_WIDE_INT tmp;
19465 {
19468 /* We may be reversing unordered compare to normal compare, that
19469 is not valid in general (we may convert non-trapping condition
19470 to trapping one), however on i386 we currently emit all
19471 comparisons unordered. */
19474 }
19475 else
19476 {
19479 }
19480 }
19485 {
19490 {
19495 }
19496 }
19498 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19502 {
19503 /* If lea code below could be used, only optimize
19504 if it results in a 2 insn sequence. */
19510 {
19511 /*
19512 * notl op1 (if necessary)
19513 * sarl $31, op1
19514 * orl cf, op1
19515 */
19517 {
19521 }
19532 }
19533 }
19541 {
19542 /*
19543 * xorl dest,dest
19544 * cmpl op1,op2
19545 * setcc dest
19546 * lea cf(dest*(ct-cf)),dest
19547 *
19548 * Size 14.
19549 *
19550 * This also catches the degenerate setcc-only case.
19551 */
19553 rtx tmp;
19559 /* On x86_64 the lea instruction operates on Pmode, so we need
19560 to get arithmetics done in proper mode to match. */
19563 else
19564 {
19565 rtx out1;
19568 nops++;
19570 {
19572 nops++;
19573 }
19574 }
19576 {
19578 nops++;
19579 }
19581 {
19584 else
19586 }
19591 }
19593 /*
19594 * General case: Jumpful:
19595 * xorl dest,dest cmpl op1, op2
19596 * cmpl op1, op2 movl ct, dest
19597 * setcc dest jcc 1f
19598 * decl dest movl cf, dest
19599 * andl (cf-ct),dest 1:
19600 * addl ct,dest
19601 *
19602 * Size 20. Size 14.
19603 *
19604 * This is reasonably steep, but branch mispredict costs are
19605 * high on modern cpus, so consider failing only if optimizing
19606 * for space.
19607 */
19612 {
19614 {
19621 {
19624 /* We may be reversing unordered compare to normal compare,
19625 that is not valid in general (we may convert non-trapping
19626 condition to trapping one), however on i386 we currently
19627 emit all comparisons unordered. */
19629 }
19630 else
19631 {
19635 }
19636 }
19639 {
19640 /* notl op1 (if needed)
19641 sarl $31, op1
19642 andl (cf-ct), op1
19643 addl ct, op1
19645 For x < 0 (resp. x <= -1) there will be no notl,
19646 so if possible swap the constants to get rid of the
19647 complement.
19648 True/false will be -1/0 while code below (store flag
19649 followed by decrement) is 0/-1, so the constants need
19650 to be exchanged once more. */
19653 {
19656 }
19657 else
19658 {
19662 }
19665 }
19666 else
19667 {
19671 constm1_rtx,
19673 }
19685 }
19686 }
19689 {
19690 /* Try a few things more with specific constants and a variable. */
19692 optab op;
19698 /* If one of the two operands is an interesting constant, load a
19699 constant with the above and mask it in with a logical operation. */
19702 {
19708 else
19710 }
19712 {
19718 else
19720 }
19721 else
19728 /* Recurse to get the constant loaded. */
19732 /* Mask in the interesting variable. */
19734 OPTAB_WIDEN);
19739 }
19741 /*
19742 * For comparison with above,
19743 *
19744 * movl cf,dest
19745 * movl ct,tmp
19746 * cmpl op1,op2
19747 * cmovcc tmp,dest
19748 *
19749 * Size 15.
19750 */
19772 }
19774 /* Swap, force into registers, or otherwise massage the two operands
19775 to an sse comparison with a mask result. Thus we differ a bit from
19776 ix86_prepare_fp_compare_args which expects to produce a flags result.
19778 The DEST operand exists to help determine whether to commute commutative
19779 operators. The POP0/POP1 operands are updated in place. The new
19780 comparison code is returned, or UNKNOWN if not implementable. */
19782 static enum rtx_code
19785 {
19786 rtx tmp;
19789 {
19792 /* AVX supports all the needed comparisons. */
19795 /* We have no LTGT as an operator. We could implement it with
19796 NE & ORDERED, but this requires an extra temporary. It's
19797 not clear that it's worth it. */
19804 /* These are supported directly. */
19811 /* AVX has 3 operand comparisons, no need to swap anything. */
19814 /* For commutative operators, try to canonicalize the destination
19815 operand to be first in the comparison - this helps reload to
19816 avoid extra moves. */
19819 /* FALLTHRU */
19825 /* These are not supported directly before AVX, and furthermore
19826 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19827 comparison operands to transform into something that is
19828 supported. */
19837 }
19840 }
19842 /* Detect conditional moves that exactly match min/max operational
19843 semantics. Note that this is IEEE safe, as long as we don't
19844 interchange the operands.
19846 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19847 and TRUE if the operation is successful and instructions are emitted. */
19849 static bool
19852 {
19855 rtx tmp;
19858 ;
19860 {
19864 }
19865 else
19872 else
19877 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19878 but MODE may be a vector mode and thus not appropriate. */
19880 {
19882 rtvec v;
19887 }
19888 else
19889 {
19892 }
19896 }
19898 /* Expand an sse vector comparison. Return the register with the result. */
19900 static rtx
19903 {
19906 rtx x;
19919 {
19922 }
19923 else
19927 }
19929 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19930 operations. This is used for both scalar and vector conditional moves. */
19932 static void
19934 {
19940 {
19942 }
19944 {
19948 }
19950 {
19955 }
19957 {
19961 }
19963 {
19971 op_true,
19972 op_false)));
19973 }
19974 else
19975 {
19984 {
19998 {
20004 }
20019 {
20025 }
20029 }
20033 else
20034 {
20040 else
20052 }
20053 }
20054 }
20056 /* Expand a floating-point conditional move. Return true if successful. */
20058 bool
20060 {
20068 {
20071 /* Since we've no cmove for sse registers, don't force bad register
20072 allocation just to gain access to it. Deny movcc when the
20073 comparison mode doesn't match the move mode. */
20092 }
20099 /* The floating point conditional move instructions don't directly
20100 support conditions resulting from a signed integer comparison. */
20104 {
20109 }
20116 }
20118 /* Expand a floating-point vector conditional move; a vcond operation
20119 rather than a movcc operation. */
20121 bool
20123 {
20125 rtx cmp;
20130 {
20131 rtx temp;
20133 {
20150 }
20152 OPTAB_DIRECT);
20155 }
20165 }
20167 /* Expand a signed/unsigned integral vector conditional move. */
20169 bool
20171 {
20181 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20182 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20191 {
20195 {
20201 }
20204 {
20210 }
20211 }
20220 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20224 ;
20225 else
20226 {
20227 /* Canonicalize the comparison to EQ, GT, GTU. */
20229 {
20246 /* FALLTHRU */
20256 }
20258 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20260 {
20262 {
20264 /* SSE4.1 supports EQ. */
20271 /* SSE4.2 supports GT/GTU. */
20278 }
20279 }
20281 /* Unsigned parallel compare is not supported by the hardware.
20282 Play some tricks to turn this into a signed comparison
20283 against 0. */
20285 {
20289 {
20294 {
20299 {
20306 }
20307 /* Subtract (-(INT MAX) - 1) from both operands to make
20308 them signed. */
20319 }
20326 /* Perform a parallel unsigned saturating subtraction. */
20339 }
20340 }
20341 }
20343 /* Allow the comparison to be done in one mode, but the movcc to
20344 happen in another mode. */
20346 {
20349 }
20350 else
20351 {
20357 }
20362 }
20364 /* Expand a variable vector permutation. */
20366 void
20368 {
20379 /* Number of elements in the vector. */
20385 {
20387 {
20388 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20389 an constant shuffle operand. With a tiny bit of effort we can
20390 use VPERMD instead. A re-interpretation stall for V4DFmode is
20391 unfortunate but there's no avoiding it.
20392 Similarly for V16HImode we don't have instructions for variable
20393 shuffling, while for V32QImode we can use after preparing suitable
20394 masks vpshufb; vpshufb; vpermq; vpor. */
20397 {
20401 }
20402 else
20403 {
20407 }
20410 /* Replicate the low bits of the V4DImode mask into V8SImode:
20411 mask = { A B C D }
20412 t1 = { A A B B C C D D }. */
20420 else
20423 /* Multiply the shuffle indicies by two. */
20425 OPTAB_DIRECT);
20427 /* Add one to the odd shuffle indicies:
20428 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20430 {
20433 }
20437 OPTAB_DIRECT);
20439 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20444 }
20447 {
20449 /* The VPERMD and VPERMPS instructions already properly ignore
20450 the high bits of the shuffle elements. No need for us to
20451 perform an AND ourselves. */
20454 else
20455 {
20461 }
20468 else
20469 {
20475 }
20479 /* By combining the two 128-bit input vectors into one 256-bit
20480 input vector, we can use VPERMD and VPERMPS for the full
20481 two-operand shuffle. */
20513 /* From mask create two adjusted masks, which contain the same
20514 bits as mask in the low 7 bits of each vector element.
20515 The first mask will have the most significant bit clear
20516 if it requests element from the same 128-bit lane
20517 and MSB set if it requests element from the other 128-bit lane.
20518 The second mask will have the opposite values of the MSB,
20519 and additionally will have its 128-bit lanes swapped.
20520 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20521 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20522 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20523 stands for other 12 bytes. */
20524 /* The bit whether element is from the same lane or the other
20525 lane is bit 4, so shift it up by 3 to the MSB position. */
20529 /* Clear MSB bits from the mask just in case it had them set. */
20531 /* After this t1 will have MSB set for elements from other lane. */
20533 /* Clear bits other than MSB. */
20535 /* Or in the lower bits from mask into t3. */
20537 /* And invert MSB bits in t1, so MSB is set for elements from the same
20538 lane. */
20540 /* Swap 128-bit lanes in t3. */
20545 /* And or in the lower bits from mask into t1. */
20548 {
20549 /* Each of these shuffles will put 0s in places where
20550 element from the other 128-bit lane is needed, otherwise
20551 will shuffle in the requested value. */
20554 /* For t3 the 128-bit lanes are swapped again. */
20559 /* And oring both together leads to the result. */
20562 }
20565 /* Similarly to the above one_operand_shuffle code,
20566 just for repeated twice for each operand. merge_two:
20567 code will merge the two results together. */
20589 }
20590 }
20593 {
20594 /* The XOP VPPERM insn supports three inputs. By ignoring the
20595 one_operand_shuffle special case, we avoid creating another
20596 set of constant vectors in memory. */
20599 /* mask = mask & {2*w-1, ...} */
20601 }
20602 else
20603 {
20604 /* mask = mask & {w-1, ...} */
20606 }
20614 /* For non-QImode operations, convert the word permutation control
20615 into a byte permutation control. */
20617 {
20622 /* Convert mask to vector of chars. */
20625 /* Replicate each of the input bytes into byte positions:
20626 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20627 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20628 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20635 else
20638 /* Convert it into the byte positions by doing
20639 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20645 }
20647 /* The actual shuffle operations all operate on V16QImode. */
20653 {
20655 }
20657 {
20659 }
20660 else
20661 {
20665 /* Shuffle the two input vectors independently. */
20671 merge_two:
20672 /* Then merge them together. The key is whether any given control
20673 element contained a bit set that indicates the second word. */
20677 {
20678 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20679 more shuffle to convert the V2DI input mask into a V4SI
20680 input mask. At which point the masking that expand_int_vcond
20681 will work as desired. */
20689 }
20706 }
20707 }
20709 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20710 true if we should do zero extension, else sign extension. HIGH_P is
20711 true if we want the N/2 high elements, else the low elements. */
20713 void
20715 {
20717 rtx tmp;
20720 {
20726 {
20730 else
20733 extract
20739 else
20742 extract
20748 else
20751 extract
20757 else
20763 else
20769 else
20774 }
20777 {
20780 }
20782 {
20783 /* Shift higher 8 bytes to lower 8 bytes. */
20788 }
20789 else
20793 }
20794 else
20795 {
20799 {
20803 else
20809 else
20815 else
20820 }
20824 else
20829 }
20830 }
20832 /* Expand conditional increment or decrement using adb/sbb instructions.
20833 The default case using setcc followed by the conditional move can be
20834 done by generic code. */
20835 bool
20837 {
20839 rtx flags;
20841 rtx compare_op;
20859 {
20862 }
20865 {
20869 reverse_condition_maybe_unordered
20871 else
20873 }
20877 /* Construct either adc or sbb insn. */
20879 {
20881 {
20896 }
20897 }
20898 else
20899 {
20901 {
20916 }
20917 }
20921 }
20924 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20925 but works for floating pointer parameters and nonoffsetable memories.
20926 For pushes, it returns just stack offsets; the values will be saved
20927 in the right order. Maximally three parts are generated. */
20929 static int
20931 {
20936 else
20942 /* Optimize constant pool reference to immediates. This is used by fp
20943 moves, that force all constants to memory to allow combining. */
20945 {
20949 }
20952 {
20953 /* The only non-offsetable memories we handle are pushes. */
20962 }
20965 {
20967 /* Caution: if we looked through a constant pool memory above,
20968 the operand may actually have a different mode now. That's
20969 ok, since we want to pun this all the way back to an integer. */
20973 }
20976 {
20979 else
20980 {
20984 {
20988 }
20990 {
20995 }
20997 {
20998 REAL_VALUE_TYPE r;
21003 {
21010 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21011 long double may not be 80-bit. */
21020 }
21023 }
21024 else
21026 }
21027 }
21028 else
21029 {
21033 {
21036 {
21040 }
21042 {
21046 }
21048 {
21049 REAL_VALUE_TYPE r;
21055 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21058 = gen_int_mode
21061 DImode);
21062 else
21069 = gen_int_mode
21072 DImode);
21073 else
21075 }
21076 else
21078 }
21079 }
21082 }
21084 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21085 Return false when normal moves are needed; true when all required
21086 insns have been emitted. Operands 2-4 contain the input values
21087 int the correct order; operands 5-7 contain the output values. */
21089 void
21091 {
21099 /* The DFmode expanders may ask us to move double.
21100 For 64bit target this is single move. By hiding the fact
21101 here we simplify i386.md splitters. */
21103 {
21104 /* Optimize constant pool reference to immediates. This is used by
21105 fp moves, that force all constants to memory to allow combining. */
21112 {
21115 }
21116 else
21121 }
21123 /* The only non-offsettable memory we handle is push. */
21126 else
21133 /* When emitting push, take care for source operands on the stack. */
21136 {
21139 /* Compensate for the stack decrement by 4. */
21144 /* src_base refers to the stack pointer and is
21145 automatically decreased by emitted push. */
21149 }
21151 /* We need to do copy in the right order in case an address register
21152 of the source overlaps the destination. */
21154 {
21155 rtx tmp;
21158 {
21162 collisions++;
21163 }
21165 /* Collision in the middle part can be handled by reordering. */
21167 {
21170 }
21174 {
21176 {
21179 }
21180 else
21181 {
21184 }
21185 }
21187 /* If there are more collisions, we can't handle it by reordering.
21188 Do an lea to the last part and use only one colliding move. */
21190 {
21191 rtx base;
21197 /* Handle the case when the last part isn't valid for lea.
21198 Happens in 64-bit mode storing the 12-byte XFmode. */
21205 {
21208 }
21209 }
21210 }
21213 {
21215 {
21217 {
21222 }
21224 {
21227 }
21228 }
21229 else
21230 {
21231 /* In 64bit mode we don't have 32bit push available. In case this is
21232 register, it is OK - we will just use larger counterpart. We also
21233 retype memory - these comes from attempt to avoid REX prefix on
21234 moving of second half of TFmode value. */
21236 {
21238 {
21249 }
21253 }
21254 }
21258 }
21260 /* Choose correct order to not overwrite the source before it is copied. */
21270 {
21272 {
21275 }
21276 }
21277 else
21278 {
21280 {
21283 }
21284 }
21286 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21288 {
21297 }
21303 }
21305 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21306 left shift by a constant, either using a single shift or
21307 a sequence of add instructions. */
21309 static void
21311 {
21317 {
21321 }
21322 else
21323 {
21326 }
21327 }
21329 void
21331 {
21340 {
21345 {
21351 }
21352 else
21353 {
21361 }
21363 }
21370 {
21371 /* Assuming we've chosen a QImode capable registers, then 1 << N
21372 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21374 {
21390 }
21392 /* Otherwise, we can get the same results by manually performing
21393 a bit extract operation on bit 5/6, and then performing the two
21394 shifts. The two methods of getting 0/1 into low/high are exactly
21395 the same size. Avoiding the shift in the bit extract case helps
21396 pentium4 a bit; no one else seems to care much either way. */
21397 else
21398 {
21403 HOST_WIDE_INT bits;
21404 rtx x;
21407 {
21413 }
21414 else
21415 {
21421 }
21425 else
21433 }
21438 }
21441 {
21442 /* For -1 << N, we can avoid the shld instruction, because we
21443 know that we're shifting 0...31/63 ones into a -1. */
21447 else
21449 }
21450 else
21451 {
21459 }
21464 {
21470 }
21471 else
21472 {
21477 }
21478 }
21480 void
21482 {
21492 {
21497 {
21503 }
21505 {
21514 }
21515 else
21516 {
21524 }
21525 }
21526 else
21527 {
21539 {
21547 scratch));
21548 }
21549 else
21550 {
21555 }
21556 }
21557 }
21559 void
21561 {
21571 {
21576 {
21583 }
21584 else
21585 {
21593 }
21594 }
21595 else
21596 {
21608 {
21614 scratch));
21615 }
21616 else
21617 {
21622 }
21623 }
21624 }
21626 /* Predict just emitted jump instruction to be taken with probability PROB. */
21627 static void
21629 {
21633 }
21635 /* Helper function for the string operations below. Dest VARIABLE whether
21636 it is aligned to VALUE bytes. If true, jump to the label. */
21637 static rtx
21639 {
21644 else
21650 else
21653 }
21655 /* Adjust COUNTER by the VALUE. */
21656 static void
21658 {
21663 }
21665 /* Zero extend possibly SImode EXP to Pmode register. */
21666 rtx
21668 {
21670 }
21672 /* Divide COUNTREG by SCALE. */
21673 static rtx
21675 {
21676 rtx sc;
21688 }
21690 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21691 DImode for constant loop counts. */
21693 static enum machine_mode
21695 {
21703 }
21705 /* When SRCPTR is non-NULL, output simple loop to move memory
21706 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21707 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21708 equivalent loop to set memory by VALUE (supposed to be in MODE).
21710 The size is rounded down to whole number of chunk size moved at once.
21711 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21714 static void
21719 {
21724 rtx size;
21725 rtx x_addr;
21726 rtx y_addr;
21735 /* Those two should combine. */
21737 {
21741 }
21751 {
21755 /* When unrolling for chips that reorder memory reads and writes,
21756 we can save registers by using single temporary.
21757 Also using 4 temporaries is overkill in 32bit mode. */
21759 {
21761 {
21763 {
21764 destmem =
21766 srcmem =
21768 }
21770 }
21771 }
21772 else
21773 {
21777 {
21780 {
21781 srcmem =
21783 }
21785 }
21787 {
21789 {
21790 destmem =
21792 }
21794 }
21795 }
21796 }
21797 else
21799 {
21801 destmem =
21804 }
21814 {
21820 else
21822 }
21823 else
21831 {
21836 }
21838 }
21840 /* Output "rep; mov" instruction.
21841 Arguments have same meaning as for previous function */
21842 static void
21845 rtx count,
21847 {
21848 rtx destexp;
21849 rtx srcexp;
21850 rtx countreg;
21851 HOST_WIDE_INT rounded_count;
21853 /* If the size is known, it is shorter to use rep movs. */
21864 {
21871 }
21872 else
21873 {
21876 }
21878 {
21885 }
21886 else
21887 {
21892 }
21895 }
21897 /* Output "rep; stos" instruction.
21898 Arguments have same meaning as for previous function */
21899 static void
21902 rtx orig_value)
21903 {
21904 rtx destexp;
21905 rtx countreg;
21906 HOST_WIDE_INT rounded_count;
21913 {
21917 }
21918 else
21921 {
21926 }
21930 }
21932 static void
21935 {
21939 }
21941 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21942 static void
21945 {
21948 {
21953 {
21955 {
21958 }
21959 else
21962 }
21964 {
21967 else
21968 {
21971 }
21973 }
21975 {
21978 }
21980 {
21983 }
21985 {
21988 }
21990 }
21992 {
21998 }
22000 /* When there are stringops, we can cheaply increase dest and src pointers.
22001 Otherwise we save code size by maintaining offset (zero is readily
22002 available from preceding rep operation) and using x86 addressing modes.
22003 */
22005 {
22007 {
22014 }
22016 {
22023 }
22025 {
22032 }
22033 }
22034 else
22035 {
22037 rtx tmp;
22040 {
22051 }
22053 {
22066 }
22068 {
22077 }
22078 }
22079 }
22081 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22082 static void
22085 {
22086 count =
22092 }
22094 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22095 static void
22097 {
22098 rtx dest;
22101 {
22106 {
22108 {
22113 }
22114 else
22117 }
22119 {
22121 {
22124 }
22125 else
22126 {
22131 }
22133 }
22135 {
22139 }
22141 {
22145 }
22147 {
22151 }
22153 }
22155 {
22158 }
22160 {
22163 {
22167 }
22168 else
22169 {
22175 }
22178 }
22180 {
22183 {
22186 }
22187 else
22188 {
22192 }
22195 }
22197 {
22203 }
22205 {
22211 }
22213 {
22219 }
22220 }
22222 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22223 DESIRED_ALIGNMENT. */
22224 static void
22228 {
22230 {
22238 }
22240 {
22248 }
22250 {
22258 }
22260 }
22262 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22263 ALIGN_BYTES is how many bytes need to be copied. */
22264 static rtx
22267 {
22276 {
22281 }
22283 {
22294 }
22296 {
22302 {
22310 }
22313 }
22319 {
22331 }
22338 }
22340 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22341 DESIRED_ALIGNMENT. */
22342 static void
22345 {
22347 {
22354 }
22356 {
22363 }
22365 {
22372 }
22374 }
22376 /* Set enough from DST to align DST known to by aligned by ALIGN to
22377 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22378 static rtx
22381 {
22385 {
22390 }
22392 {
22399 }
22401 {
22408 }
22415 }
22417 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22418 static enum stringop_alg
22421 {
22424 /* Algorithms using the rep prefix want at least edi and ecx;
22425 additionally, memset wants eax and memcpy wants esi. Don't
22426 consider such algorithms if the user has appropriated those
22427 registers for their own purposes. */
22429 || (memset
22433 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22434 || (alg != rep_prefix_1_byte \
22435 && alg != rep_prefix_4_byte \
22436 && alg != rep_prefix_8_byte))
22439 /* Even if the string operation call is cold, we still might spend a lot
22440 of time processing large blocks. */
22445 else
22453 else
22457 /* rep; movq or rep; movl is the smallest variant. */
22459 {
22462 else
22464 }
22465 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22466 */
22470 {
22474 {
22475 /* We get here if the algorithms that were not libcall-based
22476 were rep-prefix based and we are unable to use rep prefixes
22477 based on global register usage. Break out of the loop and
22478 use the heuristic below. */
22482 {
22487 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22488 last non-libcall inline algorithm. */
22490 {
22491 /* When the current size is best to be copied by a libcall,
22492 but we are still forced to inline, run the heuristic below
22493 that will pick code for medium sized blocks. */
22497 }
22499 {
22502 }
22503 }
22504 }
22506 }
22507 /* When asked to inline the call anyway, try to pick meaningful choice.
22508 We look for maximal size of block that is faster to copy by hand and
22509 take blocks of at most of that size guessing that average size will
22510 be roughly half of the block.
22512 If this turns out to be bad, we might simply specify the preferred
22513 choice in ix86_costs. */
22516 {
22523 {
22530 }
22531 /* If there aren't any usable algorithms, then recursing on
22532 smaller sizes isn't going to find anything. Just return the
22533 simple byte-at-a-time copy loop. */
22535 {
22536 /* Pick something reasonable. */
22540 }
22549 }
22551 #undef ALG_USABLE_P
22552 }
22554 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22555 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22556 static int
22560 {
22563 {
22574 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22575 copying whole cacheline at once. */
22578 else
22582 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22583 copying whole cacheline at once. */
22586 else
22594 }
22603 }
22605 /* Return the smallest power of 2 greater than VAL. */
22606 static int
22608 {
22613 }
22615 /* Expand string move (memcpy) operation. Use i386 string operations
22616 when profitable. expand_setmem contains similar code. The code
22617 depends upon architecture, block size and alignment, but always has
22618 the same overall structure:
22620 1) Prologue guard: Conditional that jumps up to epilogues for small
22621 blocks that can be handled by epilogue alone. This is faster
22622 but also needed for correctness, since prologue assume the block
22623 is larger than the desired alignment.
22625 Optional dynamic check for size and libcall for large
22626 blocks is emitted here too, with -minline-stringops-dynamically.
22628 2) Prologue: copy first few bytes in order to get destination
22629 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22630 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22631 copied. We emit either a jump tree on power of two sized
22632 blocks, or a byte loop.
22634 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22635 with specified algorithm.
22637 4) Epilogue: code copying tail of the block that is too small to be
22638 handled by main body (or up to size guarded by prologue guard). */
22640 bool
22643 {
22644 rtx destreg;
22645 rtx srcreg;
22647 rtx tmp;
22661 /* i386 can do misaligned access on reasonably increased cost. */
22665 /* ALIGN is the minimum of destination and source alignment, but we care here
22666 just about destination alignment. */
22675 /* Make sure we don't need to care about overflow later on. */
22679 /* Step 0: Decide on preferred algorithm, desired alignment and
22680 size of chunks to be copied by main loop. */
22696 {
22721 }
22725 /* Step 1: Prologue guard. */
22727 /* Alignment code needs count to be in register. */
22729 {
22732 {
22733 align_bytes
22737 else
22739 }
22742 }
22745 /* Ensure that alignment prologue won't copy past end of block. */
22747 {
22749 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22750 Make sure it is power of 2. */
22754 {
22756 {
22757 /* If main algorithm works on QImode, no epilogue is needed.
22758 For small sizes just don't align anything. */
22761 else
22763 }
22764 }
22765 else
22766 {
22773 else
22775 }
22776 }
22778 /* Emit code to decide on runtime whether library call or inline should be
22779 used. */
22781 {
22783 {
22785 {
22789 }
22790 }
22791 else
22792 {
22801 }
22802 }
22804 /* Step 2: Alignment prologue. */
22807 {
22809 {
22810 /* Except for the first move in epilogue, we no longer know
22811 constant offset in aliasing info. It don't seems to worth
22812 the pain to maintain it for the first move, so throw away
22813 the info early. */
22817 desired_align);
22818 }
22819 else
22820 {
22821 /* If we know how many bytes need to be stored before dst is
22822 sufficiently aligned, maintain aliasing info accurately. */
22828 }
22834 {
22835 /* It is possible that we copied enough so the main loop will not
22836 execute. */
22846 else
22848 }
22849 }
22851 {
22856 }
22860 /* Step 3: Main loop. */
22863 {
22876 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22877 registers for 4 temporaries anyway. */
22880 expected_size);
22884 DImode);
22888 SImode);
22892 QImode);
22894 }
22895 /* Adjust properly the offset of src and dest memory for aliasing. */
22897 {
22902 }
22903 else
22904 {
22907 }
22909 /* Step 4: Epilogue to copy the remaining bytes. */
22910 epilogue:
22912 {
22913 /* When the main loop is done, COUNT_EXP might hold original count,
22914 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22915 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22916 bytes. Compensate if needed. */
22919 {
22920 tmp =
22923 OPTAB_DIRECT);
22926 }
22929 }
22933 epilogue_size_needed);
22937 }
22939 /* Helper function for memcpy. For QImode value 0xXY produce
22940 0xXYXYXYXY of wide specified by MODE. This is essentially
22941 a * 0x10101010, but we can do slightly better than
22942 synth_mult by unwinding the sequence by hand on CPUs with
22943 slow multiply. */
22944 static rtx
22946 {
22948 rtx tmp;
22955 {
22963 }
22972 nops--;
22977 {
22981 OPTAB_DIRECT);
22982 }
22983 else
22984 {
22990 else
22992 else
22993 {
22996 reg =
22998 }
23008 }
23009 }
23011 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23012 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23013 alignment from ALIGN to DESIRED_ALIGN. */
23014 static rtx
23016 {
23017 rtx promoted_val;
23026 else
23030 }
23032 /* Expand string clear operation (bzero). Use i386 string operations when
23033 profitable. See expand_movmem comment for explanation of individual
23034 steps performed. */
23035 bool
23038 {
23039 rtx destreg;
23041 rtx tmp;
23057 /* i386 can do misaligned access on reasonably increased cost. */
23066 /* Make sure we don't need to care about overflow later on. */
23070 /* Step 0: Decide on preferred algorithm, desired alignment and
23071 size of chunks to be copied by main loop. */
23086 {
23111 }
23114 /* Step 1: Prologue guard. */
23116 /* Alignment code needs count to be in register. */
23118 {
23121 {
23122 align_bytes
23126 else
23128 }
23130 {
23135 }
23136 }
23137 /* Do the cheap promotion to allow better CSE across the
23138 main loop and epilogue (ie one load of the big constant in the
23139 front of all code. */
23143 /* Ensure that alignment prologue won't copy past end of block. */
23145 {
23147 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23148 Make sure it is power of 2. */
23151 /* To improve performance of small blocks, we jump around the VAL
23152 promoting mode. This mean that if the promoted VAL is not constant,
23153 we might not use it in the epilogue and have to use byte
23154 loop variant. */
23158 {
23160 {
23161 /* If main algorithm works on QImode, no epilogue is needed.
23162 For small sizes just don't align anything. */
23165 else
23167 }
23168 }
23169 else
23170 {
23177 else
23179 }
23180 }
23182 {
23191 }
23193 /* Step 2: Alignment prologue. */
23195 /* Do the expensive promotion once we branched off the small blocks. */
23202 {
23204 {
23205 /* Except for the first move in epilogue, we no longer know
23206 constant offset in aliasing info. It don't seems to worth
23207 the pain to maintain it for the first move, so throw away
23208 the info early. */
23211 desired_align);
23212 }
23213 else
23214 {
23215 /* If we know how many bytes need to be stored before dst is
23216 sufficiently aligned, maintain aliasing info accurately. */
23222 }
23228 {
23229 /* It is possible that we copied enough so the main loop will not
23230 execute. */
23240 else
23242 }
23243 }
23245 {
23251 }
23255 /* Step 3: Main loop. */
23258 {
23286 }
23287 /* Adjust properly the offset of src and dest memory for aliasing. */
23291 else
23294 /* Step 4: Epilogue to copy the remaining bytes. */
23297 {
23298 /* When the main loop is done, COUNT_EXP might hold original count,
23299 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23300 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23301 bytes. Compensate if needed. */
23304 {
23305 tmp =
23308 OPTAB_DIRECT);
23311 }
23314 }
23315 epilogue:
23317 {
23320 epilogue_size_needed);
23321 else
23323 epilogue_size_needed);
23324 }
23328 }
23330 /* Expand the appropriate insns for doing strlen if not just doing
23331 repnz; scasb
23333 out = result, initialized with the start address
23334 align_rtx = alignment of the address.
23335 scratch = scratch register, initialized with the startaddress when
23336 not aligned, otherwise undefined
23338 This is just the body. It needs the initializations mentioned above and
23339 some address computing at the end. These things are done in i386.md. */
23341 static void
23343 {
23345 rtx tmp;
23350 rtx mem;
23353 rtx cmp;
23359 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23361 /* Is there a known alignment and is it less than 4? */
23363 {
23366 /* Is there a known alignment and is it not 2? */
23368 {
23372 /* Leave just the 3 lower bits. */
23382 }
23383 else
23384 {
23385 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23386 check if is aligned to 4 - byte. */
23393 }
23397 /* Now compare the bytes. */
23399 /* Compare the first n unaligned byte on a byte per byte basis. */
23403 /* Increment the address. */
23406 /* Not needed with an alignment of 2 */
23408 {
23412 end_0_label);
23417 }
23420 end_0_label);
23423 }
23425 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23426 align this loop. It gives only huge programs, but does not help to
23427 speed up. */
23434 /* This formula yields a nonzero result iff one of the bytes is zero.
23435 This saves three branches inside loop and many cycles. */
23443 align_4_label);
23446 {
23452 /* If zero is not in the first two bytes, move two bytes forward. */
23458 reg,
23459 tmpreg)));
23460 /* Emit lea manually to avoid clobbering of flags. */
23468 reg2,
23469 out)));
23470 }
23471 else
23472 {
23474 /* Is zero in the first two bytes? */
23481 pc_rtx);
23485 /* Not in the first two. Move two bytes forward. */
23491 }
23493 /* Avoid branch in fixing the byte. */
23501 }
23503 /* Expand strlen. */
23505 bool
23507 {
23510 /* The generic case of strlen expander is long. Avoid it's
23511 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23514 && !TARGET_INLINE_ALL_STRINGOPS
23524 {
23525 /* Well it seems that some optimizer does not combine a call like
23526 foo(strlen(bar), strlen(bar));
23527 when the move and the subtraction is done here. It does calculate
23528 the length just once when these instructions are done inside of
23529 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23530 often used and I use one fewer register for the lifetime of
23531 output_strlen_unroll() this is better. */
23537 /* strlensi_unroll_1 returns the address of the zero at the end of
23538 the string, like memchr(), so compute the length by subtracting
23539 the start address. */
23541 }
23542 else
23543 {
23544 rtx unspec;
23546 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23559 /* If .md starts supporting :P, this can be done in .md. */
23565 }
23567 }
23569 /* For given symbol (function) construct code to compute address of it's PLT
23570 entry in large x86-64 PIC model. */
23571 static rtx
23573 {
23586 }
23588 rtx
23590 rtx callarg2,
23592 {
23593 /* We need to represent that SI and DI registers are clobbered
23594 by SYSV calls. */
23600 };
23610 {
23611 #if TARGET_MACHO
23614 #endif
23615 }
23616 else
23617 {
23618 /* Static functions and indirect calls don't need the pic register. */
23623 }
23626 {
23630 }
23640 {
23643 }
23652 {
23656 }
23660 {
23664 UNSPEC_MS_TO_SYSV_CALL);
23672 }
23681 }
23683 /* Output the assembly for a call instruction. */
23687 {
23693 {
23696 /* SEH epilogue detection requires the indirect branch case
23697 to include REX.W. */
23700 else
23705 }
23707 /* SEH unwinding can require an extra nop to be emitted in several
23708 circumstances. Determine if we have one of those. */
23710 {
23711 rtx i;
23714 {
23715 /* If we get to another real insn, we don't need the nop. */
23719 /* If we get to the epilogue note, prevent a catch region from
23720 being adjacent to the standard epilogue sequence. If non-
23721 call-exceptions, we'll have done this during epilogue emission. */
23723 && !flag_non_call_exceptions
23725 {
23728 }
23729 }
23731 /* If we didn't find a real insn following the call, prevent the
23732 unwinder from looking into the next function. */
23735 }
23739 else
23748 }
23749 \f
23750 /* Clear stack slot assignments remembered from previous functions.
23751 This is called from INIT_EXPANDERS once before RTL is emitted for each
23752 function. */
23756 {
23764 }
23766 /* Return a MEM corresponding to a stack slot with mode MODE.
23767 Allocate a new slot if necessary.
23769 The RTL for a function can have several slots available: N is
23770 which slot to use. */
23772 rtx
23774 {
23791 }
23793 static void
23795 {
23801 }
23802 \f
23803 /* Calculate the length of the memory address in the instruction encoding.
23804 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23805 or other prefixes. We never generate addr32 prefix for LEA insn. */
23807 int
23809 {
23826 /* If this is not LEA instruction, add the length of addr32 prefix. */
23831 len++;
23845 /* Rule of thumb:
23846 - esp as the base always wants an index,
23847 - ebp as the base always wants a displacement,
23848 - r12 as the base always wants an index,
23849 - r13 as the base always wants a displacement. */
23851 /* Register Indirect. */
23853 {
23854 /* esp (for its index) and ebp (for its displacement) need
23855 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23856 code. */
23863 len++;
23864 }
23866 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23867 is not disp32, but disp32(%rip), so for disp32
23868 SIB byte is needed, unless print_operand_address
23869 optimizes it into disp32(%rip) or (%rip) is implied
23870 by UNSPEC. */
23872 {
23875 {
23891 len++;
23892 }
23893 }
23894 else
23895 {
23896 /* Find the length of the displacement constant. */
23898 {
23901 else
23903 }
23904 /* ebp always wants a displacement. Similarly r13. */
23906 len++;
23908 /* An index requires the two-byte modrm form.... */
23910 /* ...like esp (or r12), which always wants an index. */
23914 len++;
23915 }
23918 }
23920 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23921 is set, expect that insn have 8bit immediate alternative. */
23922 int
23924 {
23930 {
23935 {
23938 {
23950 }
23952 {
23955 }
23956 }
23958 {
23968 /* Immediates for DImode instructions are encoded
23969 as 32bit sign extended values. */
23975 }
23976 }
23978 }
23980 /* Compute default value for "length_address" attribute. */
23981 int
23983 {
23987 {
23998 }
24003 {
24006 {
24011 constraints++;
24014 ;
24015 /* Skip ignored operands. */
24018 }
24020 }
24022 }
24024 /* Compute default value for "length_vex" attribute. It includes
24025 2 or 3 byte VEX prefix and 1 opcode byte. */
24027 int
24029 {
24032 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24033 byte VEX prefix. */
24037 /* We can always use 2 byte VEX prefix in 32bit. */
24045 {
24046 /* REX.W bit uses 3 byte VEX prefix. */
24050 }
24051 else
24052 {
24053 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24057 }
24060 }
24061 \f
24062 /* Return the maximum number of instructions a cpu can issue. */
24064 static int
24066 {
24068 {
24094 }
24095 }
24097 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24098 by DEP_INSN and nothing set by DEP_INSN. */
24100 static bool
24102 {
24105 /* Simplify the test for uninteresting insns. */
24113 {
24116 }
24121 {
24124 }
24125 else
24131 /* This test is true if the dependent insn reads the flags but
24132 not any other potentially set register. */
24140 }
24142 /* Return true iff USE_INSN has a memory address with operands set by
24143 SET_INSN. */
24145 bool
24147 {
24152 {
24155 }
24157 }
24159 static int
24161 {
24167 /* Anti and output dependencies have zero cost on all CPUs. */
24173 /* If we can't recognize the insns, we can't really do anything. */
24181 {
24183 /* Address Generation Interlock adds a cycle of latency. */
24185 {
24196 }
24200 /* ??? Compares pair with jump/setcc. */
24204 /* Floating point stores require value to be ready one cycle earlier. */
24214 /* INT->FP conversion is expensive. */
24218 /* There is one cycle extra latency between an FP op and a store. */
24226 /* Show ability of reorder buffer to hide latency of load by executing
24227 in parallel with previous instruction in case
24228 previous instruction is not needed to compute the address. */
24231 {
24232 /* Claim moves to take one cycle, as core can issue one load
24233 at time and the next load can start cycle later. */
24238 cost--;
24239 }
24245 /* The esp dependency is resolved before the instruction is really
24246 finished. */
24251 /* INT->FP conversion is expensive. */
24255 /* Show ability of reorder buffer to hide latency of load by executing
24256 in parallel with previous instruction in case
24257 previous instruction is not needed to compute the address. */
24260 {
24261 /* Claim moves to take one cycle, as core can issue one load
24262 at time and the next load can start cycle later. */
24268 else
24270 }
24286 /* Show ability of reorder buffer to hide latency of load by executing
24287 in parallel with previous instruction in case
24288 previous instruction is not needed to compute the address. */
24291 {
24295 /* Because of the difference between the length of integer and
24296 floating unit pipeline preparation stages, the memory operands
24297 for floating point are cheaper.
24299 ??? For Athlon it the difference is most probably 2. */
24302 else
24307 else
24309 }
24313 }
24316 }
24318 /* How many alternative schedules to try. This should be as wide as the
24319 scheduling freedom in the DFA, but no wider. Making this value too
24320 large results extra work for the scheduler. */
24322 static int
24324 {
24326 {
24338 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24339 as many instructions can be executed on a cycle, i.e.,
24340 issue_rate. I wonder why tuning for many CPUs does not do this. */
24343 /* Don't use lookahead for pre-reload schedule to save compile time. */
24348 }
24349 }
24351 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24352 execution. It is applied if
24353 (1) IMUL instruction is on the top of list;
24354 (2) There exists the only producer of independent IMUL instruction in
24355 ready list;
24356 (3) Put found producer on the top of ready list.
24357 Returns issue rate. */
24359 static int
24362 {
24367 sd_iterator_def sd_it;
24368 dep_t dep;
24371 /* Set up issue rate. */
24374 /* Do reodering for Atom only. */
24377 /* Do not perform ready list reodering for pre-reload schedule pass. */
24380 /* Nothing to do if ready list contains only 1 instruction. */
24384 /* Check that IMUL instruction is on the top of ready list. */
24397 /* Search for producer of independent IMUL instruction. */
24399 {
24403 /* Skip IMUL instruction. */
24413 {
24414 rtx con;
24425 {
24426 sd_iterator_def sd_it1;
24427 dep_t dep1;
24428 /* Check if there is no other dependee for IMUL. */
24431 {
24432 rtx pro;
24438 }
24441 }
24442 }
24445 }
24453 /* Put IMUL producer (ready[index]) at the top of ready list. */
24460 }
24462 static bool
24465 /* Returns true if lhs of insn is HW function argument register and set up
24466 is_spilled to true if it is likely spilled HW register. */
24467 static bool
24469 {
24470 rtx dst;
24474 /* Call instructions are not movable, ignore it. */
24485 {
24486 /* Is it likely spilled HW register? */
24491 }
24493 }
24495 /* Add output dependencies for chain of function adjacent arguments if only
24496 there is a move to likely spilled HW register. Return first argument
24497 if at least one dependence was added or NULL otherwise. */
24498 static rtx
24500 {
24501 rtx insn;
24508 /* Find nearest to call argument passing instruction. */
24510 {
24519 }
24523 {
24530 {
24533 }
24535 {
24536 /* Add output depdendence between two function arguments if chain
24537 of output arguments contains likely spilled HW registers. */
24541 }
24542 else
24544 }
24548 }
24550 /* Add output or anti dependency from insn to first_arg to restrict its code
24551 motion. */
24552 static void
24554 {
24555 rtx set;
24556 rtx tmp;
24563 {
24564 /* Add output dependency to the first function argument. */
24567 }
24568 /* Add anti dependency. */
24570 }
24572 /* Avoid cross block motion of function argument through adding dependency
24573 from the first non-jump instruction in bb. */
24574 static void
24576 {
24580 {
24582 {
24585 {
24588 }
24589 }
24593 }
24594 }
24596 /* Hook for pre-reload schedule - avoid motion of function arguments
24597 passed in likely spilled HW registers. */
24598 static void
24600 {
24601 rtx insn;
24609 {
24612 {
24613 /* Add dependee for first argument to predecessors if only
24614 region contains more than one block. */
24618 /* Skip trivial regions and region head blocks that can have
24619 predecessors outside of region. */
24621 {
24622 edge e;
24623 edge_iterator ei;
24624 /* Assume that region is SCC, i.e. all immediate predecessors
24625 of non-head block are in the same region. */
24627 {
24628 /* Avoid creating of loop-carried dependencies through
24629 using topological odering in region. */
24632 }
24633 }
24637 }
24638 }
24641 }
24643 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24644 HW registers to maximum, to schedule them at soon as possible. These are
24645 moves from function argument registers at the top of the function entry
24646 and moves from function return value registers after call. */
24647 static int
24649 {
24650 rtx set;
24660 {
24667 }
24670 }
24672 /* Model decoder of Core 2/i7.
24673 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24674 track the instruction fetch block boundaries and make sure that long
24675 (9+ bytes) instructions are assigned to D0. */
24677 /* Maximum length of an insn that can be handled by
24678 a secondary decoder unit. '8' for Core 2/i7. */
24681 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24682 '16' for Core 2/i7. */
24685 /* Maximum number of instructions decoder can handle per cycle.
24686 '6' for Core 2/i7. */
24690 ix86_first_cycle_multipass_data_t;
24692 const_ix86_first_cycle_multipass_data_t;
24694 /* A variable to store target state across calls to max_issue within
24695 one cycle. */
24699 /* Initialize DATA. */
24700 static void
24702 {
24703 ix86_first_cycle_multipass_data_t data
24710 }
24712 /* Advancing the cycle; reset ifetch block counts. */
24713 static void
24715 {
24722 }
24726 /* Filter out insns from ready_try that the core will not be able to issue
24727 on current cycle due to decoder. */
24728 static void
24729 core2i7_first_cycle_multipass_filter_ready_try
24732 {
24734 {
24735 rtx insn;
24745 (!first_cycle_insn_p
24747 /* ... or it would not fit into the ifetch block ... */
24749 /* ... or the decoder is full already ... */
24751 /* ... mask the insn out. */
24752 {
24757 }
24758 }
24759 }
24761 /* Prepare for a new round of multipass lookahead scheduling. */
24762 static void
24765 {
24766 ix86_first_cycle_multipass_data_t data
24768 const_ix86_first_cycle_multipass_data_t prev_data
24771 /* Restore the state from the end of the previous round. */
24775 /* Filter instructions that cannot be issued on current cycle due to
24776 decoder restrictions. */
24778 first_cycle_insn_p);
24779 }
24781 /* INSN is being issued in current solution. Account for its impact on
24782 the decoder model. */
24783 static void
24786 {
24787 ix86_first_cycle_multipass_data_t data
24789 const_ix86_first_cycle_multipass_data_t prev_data
24799 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24801 {
24804 }
24806 {
24810 }
24813 /* Filter out insns from ready_try that the core will not be able to issue
24814 on current cycle due to decoder. */
24817 }
24819 /* Revert the effect on ready_try. */
24820 static void
24824 {
24825 const_ix86_first_cycle_multipass_data_t data
24828 sbitmap_iterator sbi;
24832 {
24834 }
24835 }
24837 /* Save the result of multipass lookahead scheduling for the next round. */
24838 static void
24840 {
24841 const_ix86_first_cycle_multipass_data_t data
24843 ix86_first_cycle_multipass_data_t next_data
24847 {
24850 }
24851 }
24853 /* Deallocate target data. */
24854 static void
24856 {
24857 ix86_first_cycle_multipass_data_t data
24861 {
24865 }
24866 }
24868 /* Prepare for scheduling pass. */
24869 static void
24873 {
24874 /* Install scheduling hooks for current CPU. Some of these hooks are used
24875 in time-critical parts of the scheduler, so we only set them up when
24876 they are actually used. */
24878 {
24882 /* Do not perform multipass scheduling for pre-reload schedule
24883 to save compile time. */
24885 {
24901 /* Set decoder parameters. */
24906 }
24907 /* ... Fall through ... */
24917 }
24918 }
24920 \f
24921 /* Compute the alignment given to a constant that is being placed in memory.
24922 EXP is the constant and ALIGN is the alignment that the object would
24923 ordinarily have.
24924 The value of this function is used instead of that alignment to align
24925 the object. */
24927 int
24929 {
24932 {
24937 }
24943 }
24945 /* Compute the alignment for a static variable.
24946 TYPE is the data type, and ALIGN is the alignment that
24947 the object would ordinarily have. The value of this function is used
24948 instead of that alignment to align the object. */
24950 int
24952 {
24963 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24964 to 16byte boundary. */
24966 {
24973 }
24976 {
24981 }
24983 {
24990 }
24995 {
25000 }
25003 {
25008 }
25011 }
25013 /* Compute the alignment for a local variable or a stack slot. EXP is
25014 the data type or decl itself, MODE is the widest mode available and
25015 ALIGN is the alignment that the object would ordinarily have. The
25016 value of this macro is used instead of that alignment to align the
25017 object. */
25019 unsigned int
25022 {
25026 {
25029 }
25030 else
25031 {
25034 }
25036 /* Don't do dynamic stack realignment for long long objects with
25037 -mpreferred-stack-boundary=2. */
25046 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25047 register in MODE. We will return the largest alignment of XF
25048 and DF. */
25050 {
25054 }
25056 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25057 to 16byte boundary. Exact wording is:
25059 An array uses the same alignment as its elements, except that a local or
25060 global array variable of length at least 16 bytes or
25061 a C99 variable-length array variable always has alignment of at least 16 bytes.
25063 This was added to allow use of aligned SSE instructions at arrays. This
25064 rule is meant for static storage (where compiler can not do the analysis
25065 by itself). We follow it for automatic variables only when convenient.
25066 We fully control everything in the function compiled and functions from
25067 other unit can not rely on the alignment.
25069 Exclude va_list type. It is the common case of local array where
25070 we can not benefit from the alignment. */
25073 {
25083 }
25085 {
25090 }
25092 {
25098 }
25103 {
25108 }
25111 {
25117 }
25119 }
25121 /* Compute the minimum required alignment for dynamic stack realignment
25122 purposes for a local variable, parameter or a stack slot. EXP is
25123 the data type or decl itself, MODE is its mode and ALIGN is the
25124 alignment that the object would ordinarily have. */
25126 unsigned int
25129 {
25133 {
25136 }
25137 else
25138 {
25141 }
25146 /* Don't do dynamic stack realignment for long long objects with
25147 -mpreferred-stack-boundary=2. */
25154 }
25155 \f
25156 /* Find a location for the static chain incoming to a nested function.
25157 This is a register, unless all free registers are used by arguments. */
25159 static rtx
25161 {
25168 {
25169 /* We always use R10 in 64-bit mode. */
25171 }
25172 else
25173 {
25174 tree fntype;
25177 /* By default in 32-bit mode we use ECX to pass the static chain. */
25183 {
25184 /* Fastcall functions use ecx/edx for arguments, which leaves
25185 us with EAX for the static chain.
25186 Thiscall functions use ecx for arguments, which also
25187 leaves us with EAX for the static chain. */
25189 }
25191 {
25192 /* Thiscall functions use ecx for arguments, which leaves
25193 us with EAX and EDX for the static chain.
25194 We are using for abi-compatibility EAX. */
25196 }
25198 {
25199 /* For regparm 3, we have no free call-clobbered registers in
25200 which to store the static chain. In order to implement this,
25201 we have the trampoline push the static chain to the stack.
25202 However, we can't push a value below the return address when
25203 we call the nested function directly, so we have to use an
25204 alternate entry point. For this we use ESI, and have the
25205 alternate entry point push ESI, so that things appear the
25206 same once we're executing the nested function. */
25208 {
25214 }
25216 }
25217 }
25220 }
25222 /* Emit RTL insns to initialize the variable parts of a trampoline.
25223 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25224 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25225 to be passed to the target function. */
25227 static void
25229 {
25237 {
25240 /* Load the function address to r11. Try to load address using
25241 the shorter movl instead of movabs. We may want to support
25242 movq for kernel mode, but kernel does not use trampolines at
25243 the moment. FNADDR is a 32bit address and may not be in
25244 DImode when ptr_mode == SImode. Always use movl in this
25245 case. */
25248 {
25257 }
25258 else
25259 {
25266 }
25268 /* Load static chain using movabs to r10. Use the shorter movl
25269 instead of movabs when ptr_mode == SImode. */
25271 {
25274 }
25275 else
25276 {
25279 }
25288 /* Jump to r11; the last (unused) byte is a nop, only there to
25289 pad the write out to a single 32-bit store. */
25293 }
25294 else
25295 {
25298 /* Depending on the static chain location, either load a register
25299 with a constant, or push the constant to the stack. All of the
25300 instructions are the same size. */
25303 {
25305 {
25312 }
25313 }
25314 else
25329 /* Compute offset from the end of the jmp to the target function.
25330 In the case in which the trampoline stores the static chain on
25331 the stack, we need to skip the first insn which pushes the
25332 (call-saved) register static chain; this push is 1 byte. */
25339 }
25343 #ifdef HAVE_ENABLE_EXECUTE_STACK
25344 #ifdef CHECK_EXECUTE_STACK_ENABLED
25346 #endif
25349 #endif
25350 }
25351 \f
25352 /* The following file contains several enumerations and data structures
25353 built from the definitions in i386-builtin-types.def. */
25357 /* Table for the ix86 builtin non-function types. */
25360 /* Retrieve an element from the above table, building some of
25361 the types lazily. */
25363 static tree
25365 {
25377 {
25385 }
25386 else
25387 {
25393 else
25401 }
25405 }
25407 /* Table for the ix86 builtin function types. */
25410 /* Retrieve an element from the above table, building some of
25411 the types lazily. */
25413 static tree
25415 {
25416 tree type;
25425 {
25433 {
25436 }
25439 }
25440 else
25441 {
25447 }
25451 }
25454 /* Codes for all the SSE/MMX builtins. */
25455 enum ix86_builtins
25456 {
25457 IX86_BUILTIN_ADDPS,
25458 IX86_BUILTIN_ADDSS,
25459 IX86_BUILTIN_DIVPS,
25460 IX86_BUILTIN_DIVSS,
25461 IX86_BUILTIN_MULPS,
25462 IX86_BUILTIN_MULSS,
25463 IX86_BUILTIN_SUBPS,
25464 IX86_BUILTIN_SUBSS,
25466 IX86_BUILTIN_CMPEQPS,
25467 IX86_BUILTIN_CMPLTPS,
25468 IX86_BUILTIN_CMPLEPS,
25469 IX86_BUILTIN_CMPGTPS,
25470 IX86_BUILTIN_CMPGEPS,
25471 IX86_BUILTIN_CMPNEQPS,
25472 IX86_BUILTIN_CMPNLTPS,
25473 IX86_BUILTIN_CMPNLEPS,
25474 IX86_BUILTIN_CMPNGTPS,
25475 IX86_BUILTIN_CMPNGEPS,
25476 IX86_BUILTIN_CMPORDPS,
25477 IX86_BUILTIN_CMPUNORDPS,
25478 IX86_BUILTIN_CMPEQSS,
25479 IX86_BUILTIN_CMPLTSS,
25480 IX86_BUILTIN_CMPLESS,
25481 IX86_BUILTIN_CMPNEQSS,
25482 IX86_BUILTIN_CMPNLTSS,
25483 IX86_BUILTIN_CMPNLESS,
25484 IX86_BUILTIN_CMPNGTSS,
25485 IX86_BUILTIN_CMPNGESS,
25486 IX86_BUILTIN_CMPORDSS,
25487 IX86_BUILTIN_CMPUNORDSS,
25489 IX86_BUILTIN_COMIEQSS,
25490 IX86_BUILTIN_COMILTSS,
25491 IX86_BUILTIN_COMILESS,
25492 IX86_BUILTIN_COMIGTSS,
25493 IX86_BUILTIN_COMIGESS,
25494 IX86_BUILTIN_COMINEQSS,
25495 IX86_BUILTIN_UCOMIEQSS,
25496 IX86_BUILTIN_UCOMILTSS,
25497 IX86_BUILTIN_UCOMILESS,
25498 IX86_BUILTIN_UCOMIGTSS,
25499 IX86_BUILTIN_UCOMIGESS,
25500 IX86_BUILTIN_UCOMINEQSS,
25502 IX86_BUILTIN_CVTPI2PS,
25503 IX86_BUILTIN_CVTPS2PI,
25504 IX86_BUILTIN_CVTSI2SS,
25505 IX86_BUILTIN_CVTSI642SS,
25506 IX86_BUILTIN_CVTSS2SI,
25507 IX86_BUILTIN_CVTSS2SI64,
25508 IX86_BUILTIN_CVTTPS2PI,
25509 IX86_BUILTIN_CVTTSS2SI,
25510 IX86_BUILTIN_CVTTSS2SI64,
25512 IX86_BUILTIN_MAXPS,
25513 IX86_BUILTIN_MAXSS,
25514 IX86_BUILTIN_MINPS,
25515 IX86_BUILTIN_MINSS,
25517 IX86_BUILTIN_LOADUPS,
25518 IX86_BUILTIN_STOREUPS,
25519 IX86_BUILTIN_MOVSS,
25521 IX86_BUILTIN_MOVHLPS,
25522 IX86_BUILTIN_MOVLHPS,
25523 IX86_BUILTIN_LOADHPS,
25524 IX86_BUILTIN_LOADLPS,
25525 IX86_BUILTIN_STOREHPS,
25526 IX86_BUILTIN_STORELPS,
25528 IX86_BUILTIN_MASKMOVQ,
25529 IX86_BUILTIN_MOVMSKPS,
25530 IX86_BUILTIN_PMOVMSKB,
25532 IX86_BUILTIN_MOVNTPS,
25533 IX86_BUILTIN_MOVNTQ,
25535 IX86_BUILTIN_LOADDQU,
25536 IX86_BUILTIN_STOREDQU,
25538 IX86_BUILTIN_PACKSSWB,
25539 IX86_BUILTIN_PACKSSDW,
25540 IX86_BUILTIN_PACKUSWB,
25542 IX86_BUILTIN_PADDB,
25543 IX86_BUILTIN_PADDW,
25544 IX86_BUILTIN_PADDD,
25545 IX86_BUILTIN_PADDQ,
25546 IX86_BUILTIN_PADDSB,
25547 IX86_BUILTIN_PADDSW,
25548 IX86_BUILTIN_PADDUSB,
25549 IX86_BUILTIN_PADDUSW,
25550 IX86_BUILTIN_PSUBB,
25551 IX86_BUILTIN_PSUBW,
25552 IX86_BUILTIN_PSUBD,
25553 IX86_BUILTIN_PSUBQ,
25554 IX86_BUILTIN_PSUBSB,
25555 IX86_BUILTIN_PSUBSW,
25556 IX86_BUILTIN_PSUBUSB,
25557 IX86_BUILTIN_PSUBUSW,
25559 IX86_BUILTIN_PAND,
25560 IX86_BUILTIN_PANDN,
25561 IX86_BUILTIN_POR,
25562 IX86_BUILTIN_PXOR,
25564 IX86_BUILTIN_PAVGB,
25565 IX86_BUILTIN_PAVGW,
25567 IX86_BUILTIN_PCMPEQB,
25568 IX86_BUILTIN_PCMPEQW,
25569 IX86_BUILTIN_PCMPEQD,
25570 IX86_BUILTIN_PCMPGTB,
25571 IX86_BUILTIN_PCMPGTW,
25572 IX86_BUILTIN_PCMPGTD,
25574 IX86_BUILTIN_PMADDWD,
25576 IX86_BUILTIN_PMAXSW,
25577 IX86_BUILTIN_PMAXUB,
25578 IX86_BUILTIN_PMINSW,
25579 IX86_BUILTIN_PMINUB,
25581 IX86_BUILTIN_PMULHUW,
25582 IX86_BUILTIN_PMULHW,
25583 IX86_BUILTIN_PMULLW,
25585 IX86_BUILTIN_PSADBW,
25586 IX86_BUILTIN_PSHUFW,
25588 IX86_BUILTIN_PSLLW,
25589 IX86_BUILTIN_PSLLD,
25590 IX86_BUILTIN_PSLLQ,
25591 IX86_BUILTIN_PSRAW,
25592 IX86_BUILTIN_PSRAD,
25593 IX86_BUILTIN_PSRLW,
25594 IX86_BUILTIN_PSRLD,
25595 IX86_BUILTIN_PSRLQ,
25596 IX86_BUILTIN_PSLLWI,
25597 IX86_BUILTIN_PSLLDI,
25598 IX86_BUILTIN_PSLLQI,
25599 IX86_BUILTIN_PSRAWI,
25600 IX86_BUILTIN_PSRADI,
25601 IX86_BUILTIN_PSRLWI,
25602 IX86_BUILTIN_PSRLDI,
25603 IX86_BUILTIN_PSRLQI,
25605 IX86_BUILTIN_PUNPCKHBW,
25606 IX86_BUILTIN_PUNPCKHWD,
25607 IX86_BUILTIN_PUNPCKHDQ,
25608 IX86_BUILTIN_PUNPCKLBW,
25609 IX86_BUILTIN_PUNPCKLWD,
25610 IX86_BUILTIN_PUNPCKLDQ,
25612 IX86_BUILTIN_SHUFPS,
25614 IX86_BUILTIN_RCPPS,
25615 IX86_BUILTIN_RCPSS,
25616 IX86_BUILTIN_RSQRTPS,
25617 IX86_BUILTIN_RSQRTPS_NR,
25618 IX86_BUILTIN_RSQRTSS,
25619 IX86_BUILTIN_RSQRTF,
25620 IX86_BUILTIN_SQRTPS,
25621 IX86_BUILTIN_SQRTPS_NR,
25622 IX86_BUILTIN_SQRTSS,
25624 IX86_BUILTIN_UNPCKHPS,
25625 IX86_BUILTIN_UNPCKLPS,
25627 IX86_BUILTIN_ANDPS,
25628 IX86_BUILTIN_ANDNPS,
25629 IX86_BUILTIN_ORPS,
25630 IX86_BUILTIN_XORPS,
25632 IX86_BUILTIN_EMMS,
25633 IX86_BUILTIN_LDMXCSR,
25634 IX86_BUILTIN_STMXCSR,
25635 IX86_BUILTIN_SFENCE,
25637 IX86_BUILTIN_FXSAVE,
25638 IX86_BUILTIN_FXRSTOR,
25639 IX86_BUILTIN_FXSAVE64,
25640 IX86_BUILTIN_FXRSTOR64,
25642 IX86_BUILTIN_XSAVE,
25643 IX86_BUILTIN_XRSTOR,
25644 IX86_BUILTIN_XSAVE64,
25645 IX86_BUILTIN_XRSTOR64,
25647 IX86_BUILTIN_XSAVEOPT,
25648 IX86_BUILTIN_XSAVEOPT64,
25650 /* 3DNow! Original */
25651 IX86_BUILTIN_FEMMS,
25652 IX86_BUILTIN_PAVGUSB,
25653 IX86_BUILTIN_PF2ID,
25654 IX86_BUILTIN_PFACC,
25655 IX86_BUILTIN_PFADD,
25656 IX86_BUILTIN_PFCMPEQ,
25657 IX86_BUILTIN_PFCMPGE,
25658 IX86_BUILTIN_PFCMPGT,
25659 IX86_BUILTIN_PFMAX,
25660 IX86_BUILTIN_PFMIN,
25661 IX86_BUILTIN_PFMUL,
25662 IX86_BUILTIN_PFRCP,
25663 IX86_BUILTIN_PFRCPIT1,
25664 IX86_BUILTIN_PFRCPIT2,
25665 IX86_BUILTIN_PFRSQIT1,
25666 IX86_BUILTIN_PFRSQRT,
25667 IX86_BUILTIN_PFSUB,
25668 IX86_BUILTIN_PFSUBR,
25669 IX86_BUILTIN_PI2FD,
25670 IX86_BUILTIN_PMULHRW,
25672 /* 3DNow! Athlon Extensions */
25673 IX86_BUILTIN_PF2IW,
25674 IX86_BUILTIN_PFNACC,
25675 IX86_BUILTIN_PFPNACC,
25676 IX86_BUILTIN_PI2FW,
25677 IX86_BUILTIN_PSWAPDSI,
25678 IX86_BUILTIN_PSWAPDSF,
25680 /* SSE2 */
25681 IX86_BUILTIN_ADDPD,
25682 IX86_BUILTIN_ADDSD,
25683 IX86_BUILTIN_DIVPD,
25684 IX86_BUILTIN_DIVSD,
25685 IX86_BUILTIN_MULPD,
25686 IX86_BUILTIN_MULSD,
25687 IX86_BUILTIN_SUBPD,
25688 IX86_BUILTIN_SUBSD,
25690 IX86_BUILTIN_CMPEQPD,
25691 IX86_BUILTIN_CMPLTPD,
25692 IX86_BUILTIN_CMPLEPD,
25693 IX86_BUILTIN_CMPGTPD,
25694 IX86_BUILTIN_CMPGEPD,
25695 IX86_BUILTIN_CMPNEQPD,
25696 IX86_BUILTIN_CMPNLTPD,
25697 IX86_BUILTIN_CMPNLEPD,
25698 IX86_BUILTIN_CMPNGTPD,
25699 IX86_BUILTIN_CMPNGEPD,
25700 IX86_BUILTIN_CMPORDPD,
25701 IX86_BUILTIN_CMPUNORDPD,
25702 IX86_BUILTIN_CMPEQSD,
25703 IX86_BUILTIN_CMPLTSD,
25704 IX86_BUILTIN_CMPLESD,
25705 IX86_BUILTIN_CMPNEQSD,
25706 IX86_BUILTIN_CMPNLTSD,
25707 IX86_BUILTIN_CMPNLESD,
25708 IX86_BUILTIN_CMPORDSD,
25709 IX86_BUILTIN_CMPUNORDSD,
25711 IX86_BUILTIN_COMIEQSD,
25712 IX86_BUILTIN_COMILTSD,
25713 IX86_BUILTIN_COMILESD,
25714 IX86_BUILTIN_COMIGTSD,
25715 IX86_BUILTIN_COMIGESD,
25716 IX86_BUILTIN_COMINEQSD,
25717 IX86_BUILTIN_UCOMIEQSD,
25718 IX86_BUILTIN_UCOMILTSD,
25719 IX86_BUILTIN_UCOMILESD,
25720 IX86_BUILTIN_UCOMIGTSD,
25721 IX86_BUILTIN_UCOMIGESD,
25722 IX86_BUILTIN_UCOMINEQSD,
25724 IX86_BUILTIN_MAXPD,
25725 IX86_BUILTIN_MAXSD,
25726 IX86_BUILTIN_MINPD,
25727 IX86_BUILTIN_MINSD,
25729 IX86_BUILTIN_ANDPD,
25730 IX86_BUILTIN_ANDNPD,
25731 IX86_BUILTIN_ORPD,
25732 IX86_BUILTIN_XORPD,
25734 IX86_BUILTIN_SQRTPD,
25735 IX86_BUILTIN_SQRTSD,
25737 IX86_BUILTIN_UNPCKHPD,
25738 IX86_BUILTIN_UNPCKLPD,
25740 IX86_BUILTIN_SHUFPD,
25742 IX86_BUILTIN_LOADUPD,
25743 IX86_BUILTIN_STOREUPD,
25744 IX86_BUILTIN_MOVSD,
25746 IX86_BUILTIN_LOADHPD,
25747 IX86_BUILTIN_LOADLPD,
25749 IX86_BUILTIN_CVTDQ2PD,
25750 IX86_BUILTIN_CVTDQ2PS,
25752 IX86_BUILTIN_CVTPD2DQ,
25753 IX86_BUILTIN_CVTPD2PI,
25754 IX86_BUILTIN_CVTPD2PS,
25755 IX86_BUILTIN_CVTTPD2DQ,
25756 IX86_BUILTIN_CVTTPD2PI,
25758 IX86_BUILTIN_CVTPI2PD,
25759 IX86_BUILTIN_CVTSI2SD,
25760 IX86_BUILTIN_CVTSI642SD,
25762 IX86_BUILTIN_CVTSD2SI,
25763 IX86_BUILTIN_CVTSD2SI64,
25764 IX86_BUILTIN_CVTSD2SS,
25765 IX86_BUILTIN_CVTSS2SD,
25766 IX86_BUILTIN_CVTTSD2SI,
25767 IX86_BUILTIN_CVTTSD2SI64,
25769 IX86_BUILTIN_CVTPS2DQ,
25770 IX86_BUILTIN_CVTPS2PD,
25771 IX86_BUILTIN_CVTTPS2DQ,
25773 IX86_BUILTIN_MOVNTI,
25774 IX86_BUILTIN_MOVNTI64,
25775 IX86_BUILTIN_MOVNTPD,
25776 IX86_BUILTIN_MOVNTDQ,
25778 IX86_BUILTIN_MOVQ128,
25780 /* SSE2 MMX */
25781 IX86_BUILTIN_MASKMOVDQU,
25782 IX86_BUILTIN_MOVMSKPD,
25783 IX86_BUILTIN_PMOVMSKB128,
25785 IX86_BUILTIN_PACKSSWB128,
25786 IX86_BUILTIN_PACKSSDW128,
25787 IX86_BUILTIN_PACKUSWB128,
25789 IX86_BUILTIN_PADDB128,
25790 IX86_BUILTIN_PADDW128,
25791 IX86_BUILTIN_PADDD128,
25792 IX86_BUILTIN_PADDQ128,
25793 IX86_BUILTIN_PADDSB128,
25794 IX86_BUILTIN_PADDSW128,
25795 IX86_BUILTIN_PADDUSB128,
25796 IX86_BUILTIN_PADDUSW128,
25797 IX86_BUILTIN_PSUBB128,
25798 IX86_BUILTIN_PSUBW128,
25799 IX86_BUILTIN_PSUBD128,
25800 IX86_BUILTIN_PSUBQ128,
25801 IX86_BUILTIN_PSUBSB128,
25802 IX86_BUILTIN_PSUBSW128,
25803 IX86_BUILTIN_PSUBUSB128,
25804 IX86_BUILTIN_PSUBUSW128,
25806 IX86_BUILTIN_PAND128,
25807 IX86_BUILTIN_PANDN128,
25808 IX86_BUILTIN_POR128,
25809 IX86_BUILTIN_PXOR128,
25811 IX86_BUILTIN_PAVGB128,
25812 IX86_BUILTIN_PAVGW128,
25814 IX86_BUILTIN_PCMPEQB128,
25815 IX86_BUILTIN_PCMPEQW128,
25816 IX86_BUILTIN_PCMPEQD128,
25817 IX86_BUILTIN_PCMPGTB128,
25818 IX86_BUILTIN_PCMPGTW128,
25819 IX86_BUILTIN_PCMPGTD128,
25821 IX86_BUILTIN_PMADDWD128,
25823 IX86_BUILTIN_PMAXSW128,
25824 IX86_BUILTIN_PMAXUB128,
25825 IX86_BUILTIN_PMINSW128,
25826 IX86_BUILTIN_PMINUB128,
25828 IX86_BUILTIN_PMULUDQ,
25829 IX86_BUILTIN_PMULUDQ128,
25830 IX86_BUILTIN_PMULHUW128,
25831 IX86_BUILTIN_PMULHW128,
25832 IX86_BUILTIN_PMULLW128,
25834 IX86_BUILTIN_PSADBW128,
25835 IX86_BUILTIN_PSHUFHW,
25836 IX86_BUILTIN_PSHUFLW,
25837 IX86_BUILTIN_PSHUFD,
25839 IX86_BUILTIN_PSLLDQI128,
25840 IX86_BUILTIN_PSLLWI128,
25841 IX86_BUILTIN_PSLLDI128,
25842 IX86_BUILTIN_PSLLQI128,
25843 IX86_BUILTIN_PSRAWI128,
25844 IX86_BUILTIN_PSRADI128,
25845 IX86_BUILTIN_PSRLDQI128,
25846 IX86_BUILTIN_PSRLWI128,
25847 IX86_BUILTIN_PSRLDI128,
25848 IX86_BUILTIN_PSRLQI128,
25850 IX86_BUILTIN_PSLLDQ128,
25851 IX86_BUILTIN_PSLLW128,
25852 IX86_BUILTIN_PSLLD128,
25853 IX86_BUILTIN_PSLLQ128,
25854 IX86_BUILTIN_PSRAW128,
25855 IX86_BUILTIN_PSRAD128,
25856 IX86_BUILTIN_PSRLW128,
25857 IX86_BUILTIN_PSRLD128,
25858 IX86_BUILTIN_PSRLQ128,
25860 IX86_BUILTIN_PUNPCKHBW128,
25861 IX86_BUILTIN_PUNPCKHWD128,
25862 IX86_BUILTIN_PUNPCKHDQ128,
25863 IX86_BUILTIN_PUNPCKHQDQ128,
25864 IX86_BUILTIN_PUNPCKLBW128,
25865 IX86_BUILTIN_PUNPCKLWD128,
25866 IX86_BUILTIN_PUNPCKLDQ128,
25867 IX86_BUILTIN_PUNPCKLQDQ128,
25869 IX86_BUILTIN_CLFLUSH,
25870 IX86_BUILTIN_MFENCE,
25871 IX86_BUILTIN_LFENCE,
25872 IX86_BUILTIN_PAUSE,
25874 IX86_BUILTIN_BSRSI,
25875 IX86_BUILTIN_BSRDI,
25876 IX86_BUILTIN_RDPMC,
25877 IX86_BUILTIN_RDTSC,
25878 IX86_BUILTIN_RDTSCP,
25879 IX86_BUILTIN_ROLQI,
25880 IX86_BUILTIN_ROLHI,
25881 IX86_BUILTIN_RORQI,
25882 IX86_BUILTIN_RORHI,
25884 /* SSE3. */
25885 IX86_BUILTIN_ADDSUBPS,
25886 IX86_BUILTIN_HADDPS,
25887 IX86_BUILTIN_HSUBPS,
25888 IX86_BUILTIN_MOVSHDUP,
25889 IX86_BUILTIN_MOVSLDUP,
25890 IX86_BUILTIN_ADDSUBPD,
25891 IX86_BUILTIN_HADDPD,
25892 IX86_BUILTIN_HSUBPD,
25893 IX86_BUILTIN_LDDQU,
25895 IX86_BUILTIN_MONITOR,
25896 IX86_BUILTIN_MWAIT,
25898 /* SSSE3. */
25899 IX86_BUILTIN_PHADDW,
25900 IX86_BUILTIN_PHADDD,
25901 IX86_BUILTIN_PHADDSW,
25902 IX86_BUILTIN_PHSUBW,
25903 IX86_BUILTIN_PHSUBD,
25904 IX86_BUILTIN_PHSUBSW,
25905 IX86_BUILTIN_PMADDUBSW,
25906 IX86_BUILTIN_PMULHRSW,
25907 IX86_BUILTIN_PSHUFB,
25908 IX86_BUILTIN_PSIGNB,
25909 IX86_BUILTIN_PSIGNW,
25910 IX86_BUILTIN_PSIGND,
25911 IX86_BUILTIN_PALIGNR,
25912 IX86_BUILTIN_PABSB,
25913 IX86_BUILTIN_PABSW,
25914 IX86_BUILTIN_PABSD,
25916 IX86_BUILTIN_PHADDW128,
25917 IX86_BUILTIN_PHADDD128,
25918 IX86_BUILTIN_PHADDSW128,
25919 IX86_BUILTIN_PHSUBW128,
25920 IX86_BUILTIN_PHSUBD128,
25921 IX86_BUILTIN_PHSUBSW128,
25922 IX86_BUILTIN_PMADDUBSW128,
25923 IX86_BUILTIN_PMULHRSW128,
25924 IX86_BUILTIN_PSHUFB128,
25925 IX86_BUILTIN_PSIGNB128,
25926 IX86_BUILTIN_PSIGNW128,
25927 IX86_BUILTIN_PSIGND128,
25928 IX86_BUILTIN_PALIGNR128,
25929 IX86_BUILTIN_PABSB128,
25930 IX86_BUILTIN_PABSW128,
25931 IX86_BUILTIN_PABSD128,
25933 /* AMDFAM10 - SSE4A New Instructions. */
25934 IX86_BUILTIN_MOVNTSD,
25935 IX86_BUILTIN_MOVNTSS,
25936 IX86_BUILTIN_EXTRQI,
25937 IX86_BUILTIN_EXTRQ,
25938 IX86_BUILTIN_INSERTQI,
25939 IX86_BUILTIN_INSERTQ,
25941 /* SSE4.1. */
25942 IX86_BUILTIN_BLENDPD,
25943 IX86_BUILTIN_BLENDPS,
25944 IX86_BUILTIN_BLENDVPD,
25945 IX86_BUILTIN_BLENDVPS,
25946 IX86_BUILTIN_PBLENDVB128,
25947 IX86_BUILTIN_PBLENDW128,
25949 IX86_BUILTIN_DPPD,
25950 IX86_BUILTIN_DPPS,
25952 IX86_BUILTIN_INSERTPS128,
25954 IX86_BUILTIN_MOVNTDQA,
25955 IX86_BUILTIN_MPSADBW128,
25956 IX86_BUILTIN_PACKUSDW128,
25957 IX86_BUILTIN_PCMPEQQ,
25958 IX86_BUILTIN_PHMINPOSUW128,
25960 IX86_BUILTIN_PMAXSB128,
25961 IX86_BUILTIN_PMAXSD128,
25962 IX86_BUILTIN_PMAXUD128,
25963 IX86_BUILTIN_PMAXUW128,
25965 IX86_BUILTIN_PMINSB128,
25966 IX86_BUILTIN_PMINSD128,
25967 IX86_BUILTIN_PMINUD128,
25968 IX86_BUILTIN_PMINUW128,
25970 IX86_BUILTIN_PMOVSXBW128,
25971 IX86_BUILTIN_PMOVSXBD128,
25972 IX86_BUILTIN_PMOVSXBQ128,
25973 IX86_BUILTIN_PMOVSXWD128,
25974 IX86_BUILTIN_PMOVSXWQ128,
25975 IX86_BUILTIN_PMOVSXDQ128,
25977 IX86_BUILTIN_PMOVZXBW128,
25978 IX86_BUILTIN_PMOVZXBD128,
25979 IX86_BUILTIN_PMOVZXBQ128,
25980 IX86_BUILTIN_PMOVZXWD128,
25981 IX86_BUILTIN_PMOVZXWQ128,
25982 IX86_BUILTIN_PMOVZXDQ128,
25984 IX86_BUILTIN_PMULDQ128,
25985 IX86_BUILTIN_PMULLD128,
25987 IX86_BUILTIN_ROUNDSD,
25988 IX86_BUILTIN_ROUNDSS,
25990 IX86_BUILTIN_ROUNDPD,
25991 IX86_BUILTIN_ROUNDPS,
25993 IX86_BUILTIN_FLOORPD,
25994 IX86_BUILTIN_CEILPD,
25995 IX86_BUILTIN_TRUNCPD,
25996 IX86_BUILTIN_RINTPD,
25997 IX86_BUILTIN_ROUNDPD_AZ,
25999 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26000 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26001 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26003 IX86_BUILTIN_FLOORPS,
26004 IX86_BUILTIN_CEILPS,
26005 IX86_BUILTIN_TRUNCPS,
26006 IX86_BUILTIN_RINTPS,
26007 IX86_BUILTIN_ROUNDPS_AZ,
26009 IX86_BUILTIN_FLOORPS_SFIX,
26010 IX86_BUILTIN_CEILPS_SFIX,
26011 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26013 IX86_BUILTIN_PTESTZ,
26014 IX86_BUILTIN_PTESTC,
26015 IX86_BUILTIN_PTESTNZC,
26017 IX86_BUILTIN_VEC_INIT_V2SI,
26018 IX86_BUILTIN_VEC_INIT_V4HI,
26019 IX86_BUILTIN_VEC_INIT_V8QI,
26020 IX86_BUILTIN_VEC_EXT_V2DF,
26021 IX86_BUILTIN_VEC_EXT_V2DI,
26022 IX86_BUILTIN_VEC_EXT_V4SF,
26023 IX86_BUILTIN_VEC_EXT_V4SI,
26024 IX86_BUILTIN_VEC_EXT_V8HI,
26025 IX86_BUILTIN_VEC_EXT_V2SI,
26026 IX86_BUILTIN_VEC_EXT_V4HI,
26027 IX86_BUILTIN_VEC_EXT_V16QI,
26028 IX86_BUILTIN_VEC_SET_V2DI,
26029 IX86_BUILTIN_VEC_SET_V4SF,
26030 IX86_BUILTIN_VEC_SET_V4SI,
26031 IX86_BUILTIN_VEC_SET_V8HI,
26032 IX86_BUILTIN_VEC_SET_V4HI,
26033 IX86_BUILTIN_VEC_SET_V16QI,
26035 IX86_BUILTIN_VEC_PACK_SFIX,
26036 IX86_BUILTIN_VEC_PACK_SFIX256,
26038 /* SSE4.2. */
26039 IX86_BUILTIN_CRC32QI,
26040 IX86_BUILTIN_CRC32HI,
26041 IX86_BUILTIN_CRC32SI,
26042 IX86_BUILTIN_CRC32DI,
26044 IX86_BUILTIN_PCMPESTRI128,
26045 IX86_BUILTIN_PCMPESTRM128,
26046 IX86_BUILTIN_PCMPESTRA128,
26047 IX86_BUILTIN_PCMPESTRC128,
26048 IX86_BUILTIN_PCMPESTRO128,
26049 IX86_BUILTIN_PCMPESTRS128,
26050 IX86_BUILTIN_PCMPESTRZ128,
26051 IX86_BUILTIN_PCMPISTRI128,
26052 IX86_BUILTIN_PCMPISTRM128,
26053 IX86_BUILTIN_PCMPISTRA128,
26054 IX86_BUILTIN_PCMPISTRC128,
26055 IX86_BUILTIN_PCMPISTRO128,
26056 IX86_BUILTIN_PCMPISTRS128,
26057 IX86_BUILTIN_PCMPISTRZ128,
26059 IX86_BUILTIN_PCMPGTQ,
26061 /* AES instructions */
26062 IX86_BUILTIN_AESENC128,
26063 IX86_BUILTIN_AESENCLAST128,
26064 IX86_BUILTIN_AESDEC128,
26065 IX86_BUILTIN_AESDECLAST128,
26066 IX86_BUILTIN_AESIMC128,
26067 IX86_BUILTIN_AESKEYGENASSIST128,
26069 /* PCLMUL instruction */
26070 IX86_BUILTIN_PCLMULQDQ128,
26072 /* AVX */
26073 IX86_BUILTIN_ADDPD256,
26074 IX86_BUILTIN_ADDPS256,
26075 IX86_BUILTIN_ADDSUBPD256,
26076 IX86_BUILTIN_ADDSUBPS256,
26077 IX86_BUILTIN_ANDPD256,
26078 IX86_BUILTIN_ANDPS256,
26079 IX86_BUILTIN_ANDNPD256,
26080 IX86_BUILTIN_ANDNPS256,
26081 IX86_BUILTIN_BLENDPD256,
26082 IX86_BUILTIN_BLENDPS256,
26083 IX86_BUILTIN_BLENDVPD256,
26084 IX86_BUILTIN_BLENDVPS256,
26085 IX86_BUILTIN_DIVPD256,
26086 IX86_BUILTIN_DIVPS256,
26087 IX86_BUILTIN_DPPS256,
26088 IX86_BUILTIN_HADDPD256,
26089 IX86_BUILTIN_HADDPS256,
26090 IX86_BUILTIN_HSUBPD256,
26091 IX86_BUILTIN_HSUBPS256,
26092 IX86_BUILTIN_MAXPD256,
26093 IX86_BUILTIN_MAXPS256,
26094 IX86_BUILTIN_MINPD256,
26095 IX86_BUILTIN_MINPS256,
26096 IX86_BUILTIN_MULPD256,
26097 IX86_BUILTIN_MULPS256,
26098 IX86_BUILTIN_ORPD256,
26099 IX86_BUILTIN_ORPS256,
26100 IX86_BUILTIN_SHUFPD256,
26101 IX86_BUILTIN_SHUFPS256,
26102 IX86_BUILTIN_SUBPD256,
26103 IX86_BUILTIN_SUBPS256,
26104 IX86_BUILTIN_XORPD256,
26105 IX86_BUILTIN_XORPS256,
26106 IX86_BUILTIN_CMPSD,
26107 IX86_BUILTIN_CMPSS,
26108 IX86_BUILTIN_CMPPD,
26109 IX86_BUILTIN_CMPPS,
26110 IX86_BUILTIN_CMPPD256,
26111 IX86_BUILTIN_CMPPS256,
26112 IX86_BUILTIN_CVTDQ2PD256,
26113 IX86_BUILTIN_CVTDQ2PS256,
26114 IX86_BUILTIN_CVTPD2PS256,
26115 IX86_BUILTIN_CVTPS2DQ256,
26116 IX86_BUILTIN_CVTPS2PD256,
26117 IX86_BUILTIN_CVTTPD2DQ256,
26118 IX86_BUILTIN_CVTPD2DQ256,
26119 IX86_BUILTIN_CVTTPS2DQ256,
26120 IX86_BUILTIN_EXTRACTF128PD256,
26121 IX86_BUILTIN_EXTRACTF128PS256,
26122 IX86_BUILTIN_EXTRACTF128SI256,
26123 IX86_BUILTIN_VZEROALL,
26124 IX86_BUILTIN_VZEROUPPER,
26125 IX86_BUILTIN_VPERMILVARPD,
26126 IX86_BUILTIN_VPERMILVARPS,
26127 IX86_BUILTIN_VPERMILVARPD256,
26128 IX86_BUILTIN_VPERMILVARPS256,
26129 IX86_BUILTIN_VPERMILPD,
26130 IX86_BUILTIN_VPERMILPS,
26131 IX86_BUILTIN_VPERMILPD256,
26132 IX86_BUILTIN_VPERMILPS256,
26133 IX86_BUILTIN_VPERMIL2PD,
26134 IX86_BUILTIN_VPERMIL2PS,
26135 IX86_BUILTIN_VPERMIL2PD256,
26136 IX86_BUILTIN_VPERMIL2PS256,
26137 IX86_BUILTIN_VPERM2F128PD256,
26138 IX86_BUILTIN_VPERM2F128PS256,
26139 IX86_BUILTIN_VPERM2F128SI256,
26140 IX86_BUILTIN_VBROADCASTSS,
26141 IX86_BUILTIN_VBROADCASTSD256,
26142 IX86_BUILTIN_VBROADCASTSS256,
26143 IX86_BUILTIN_VBROADCASTPD256,
26144 IX86_BUILTIN_VBROADCASTPS256,
26145 IX86_BUILTIN_VINSERTF128PD256,
26146 IX86_BUILTIN_VINSERTF128PS256,
26147 IX86_BUILTIN_VINSERTF128SI256,
26148 IX86_BUILTIN_LOADUPD256,
26149 IX86_BUILTIN_LOADUPS256,
26150 IX86_BUILTIN_STOREUPD256,
26151 IX86_BUILTIN_STOREUPS256,
26152 IX86_BUILTIN_LDDQU256,
26153 IX86_BUILTIN_MOVNTDQ256,
26154 IX86_BUILTIN_MOVNTPD256,
26155 IX86_BUILTIN_MOVNTPS256,
26156 IX86_BUILTIN_LOADDQU256,
26157 IX86_BUILTIN_STOREDQU256,
26158 IX86_BUILTIN_MASKLOADPD,
26159 IX86_BUILTIN_MASKLOADPS,
26160 IX86_BUILTIN_MASKSTOREPD,
26161 IX86_BUILTIN_MASKSTOREPS,
26162 IX86_BUILTIN_MASKLOADPD256,
26163 IX86_BUILTIN_MASKLOADPS256,
26164 IX86_BUILTIN_MASKSTOREPD256,
26165 IX86_BUILTIN_MASKSTOREPS256,
26166 IX86_BUILTIN_MOVSHDUP256,
26167 IX86_BUILTIN_MOVSLDUP256,
26168 IX86_BUILTIN_MOVDDUP256,
26170 IX86_BUILTIN_SQRTPD256,
26171 IX86_BUILTIN_SQRTPS256,
26172 IX86_BUILTIN_SQRTPS_NR256,
26173 IX86_BUILTIN_RSQRTPS256,
26174 IX86_BUILTIN_RSQRTPS_NR256,
26176 IX86_BUILTIN_RCPPS256,
26178 IX86_BUILTIN_ROUNDPD256,
26179 IX86_BUILTIN_ROUNDPS256,
26181 IX86_BUILTIN_FLOORPD256,
26182 IX86_BUILTIN_CEILPD256,
26183 IX86_BUILTIN_TRUNCPD256,
26184 IX86_BUILTIN_RINTPD256,
26185 IX86_BUILTIN_ROUNDPD_AZ256,
26187 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26188 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26189 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26191 IX86_BUILTIN_FLOORPS256,
26192 IX86_BUILTIN_CEILPS256,
26193 IX86_BUILTIN_TRUNCPS256,
26194 IX86_BUILTIN_RINTPS256,
26195 IX86_BUILTIN_ROUNDPS_AZ256,
26197 IX86_BUILTIN_FLOORPS_SFIX256,
26198 IX86_BUILTIN_CEILPS_SFIX256,
26199 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26201 IX86_BUILTIN_UNPCKHPD256,
26202 IX86_BUILTIN_UNPCKLPD256,
26203 IX86_BUILTIN_UNPCKHPS256,
26204 IX86_BUILTIN_UNPCKLPS256,
26206 IX86_BUILTIN_SI256_SI,
26207 IX86_BUILTIN_PS256_PS,
26208 IX86_BUILTIN_PD256_PD,
26209 IX86_BUILTIN_SI_SI256,
26210 IX86_BUILTIN_PS_PS256,
26211 IX86_BUILTIN_PD_PD256,
26213 IX86_BUILTIN_VTESTZPD,
26214 IX86_BUILTIN_VTESTCPD,
26215 IX86_BUILTIN_VTESTNZCPD,
26216 IX86_BUILTIN_VTESTZPS,
26217 IX86_BUILTIN_VTESTCPS,
26218 IX86_BUILTIN_VTESTNZCPS,
26219 IX86_BUILTIN_VTESTZPD256,
26220 IX86_BUILTIN_VTESTCPD256,
26221 IX86_BUILTIN_VTESTNZCPD256,
26222 IX86_BUILTIN_VTESTZPS256,
26223 IX86_BUILTIN_VTESTCPS256,
26224 IX86_BUILTIN_VTESTNZCPS256,
26225 IX86_BUILTIN_PTESTZ256,
26226 IX86_BUILTIN_PTESTC256,
26227 IX86_BUILTIN_PTESTNZC256,
26229 IX86_BUILTIN_MOVMSKPD256,
26230 IX86_BUILTIN_MOVMSKPS256,
26232 /* AVX2 */
26233 IX86_BUILTIN_MPSADBW256,
26234 IX86_BUILTIN_PABSB256,
26235 IX86_BUILTIN_PABSW256,
26236 IX86_BUILTIN_PABSD256,
26237 IX86_BUILTIN_PACKSSDW256,
26238 IX86_BUILTIN_PACKSSWB256,
26239 IX86_BUILTIN_PACKUSDW256,
26240 IX86_BUILTIN_PACKUSWB256,
26241 IX86_BUILTIN_PADDB256,
26242 IX86_BUILTIN_PADDW256,
26243 IX86_BUILTIN_PADDD256,
26244 IX86_BUILTIN_PADDQ256,
26245 IX86_BUILTIN_PADDSB256,
26246 IX86_BUILTIN_PADDSW256,
26247 IX86_BUILTIN_PADDUSB256,
26248 IX86_BUILTIN_PADDUSW256,
26249 IX86_BUILTIN_PALIGNR256,
26250 IX86_BUILTIN_AND256I,
26251 IX86_BUILTIN_ANDNOT256I,
26252 IX86_BUILTIN_PAVGB256,
26253 IX86_BUILTIN_PAVGW256,
26254 IX86_BUILTIN_PBLENDVB256,
26255 IX86_BUILTIN_PBLENDVW256,
26256 IX86_BUILTIN_PCMPEQB256,
26257 IX86_BUILTIN_PCMPEQW256,
26258 IX86_BUILTIN_PCMPEQD256,
26259 IX86_BUILTIN_PCMPEQQ256,
26260 IX86_BUILTIN_PCMPGTB256,
26261 IX86_BUILTIN_PCMPGTW256,
26262 IX86_BUILTIN_PCMPGTD256,
26263 IX86_BUILTIN_PCMPGTQ256,
26264 IX86_BUILTIN_PHADDW256,
26265 IX86_BUILTIN_PHADDD256,
26266 IX86_BUILTIN_PHADDSW256,
26267 IX86_BUILTIN_PHSUBW256,
26268 IX86_BUILTIN_PHSUBD256,
26269 IX86_BUILTIN_PHSUBSW256,
26270 IX86_BUILTIN_PMADDUBSW256,
26271 IX86_BUILTIN_PMADDWD256,
26272 IX86_BUILTIN_PMAXSB256,
26273 IX86_BUILTIN_PMAXSW256,
26274 IX86_BUILTIN_PMAXSD256,
26275 IX86_BUILTIN_PMAXUB256,
26276 IX86_BUILTIN_PMAXUW256,
26277 IX86_BUILTIN_PMAXUD256,
26278 IX86_BUILTIN_PMINSB256,
26279 IX86_BUILTIN_PMINSW256,
26280 IX86_BUILTIN_PMINSD256,
26281 IX86_BUILTIN_PMINUB256,
26282 IX86_BUILTIN_PMINUW256,
26283 IX86_BUILTIN_PMINUD256,
26284 IX86_BUILTIN_PMOVMSKB256,
26285 IX86_BUILTIN_PMOVSXBW256,
26286 IX86_BUILTIN_PMOVSXBD256,
26287 IX86_BUILTIN_PMOVSXBQ256,
26288 IX86_BUILTIN_PMOVSXWD256,
26289 IX86_BUILTIN_PMOVSXWQ256,
26290 IX86_BUILTIN_PMOVSXDQ256,
26291 IX86_BUILTIN_PMOVZXBW256,
26292 IX86_BUILTIN_PMOVZXBD256,
26293 IX86_BUILTIN_PMOVZXBQ256,
26294 IX86_BUILTIN_PMOVZXWD256,
26295 IX86_BUILTIN_PMOVZXWQ256,
26296 IX86_BUILTIN_PMOVZXDQ256,
26297 IX86_BUILTIN_PMULDQ256,
26298 IX86_BUILTIN_PMULHRSW256,
26299 IX86_BUILTIN_PMULHUW256,
26300 IX86_BUILTIN_PMULHW256,
26301 IX86_BUILTIN_PMULLW256,
26302 IX86_BUILTIN_PMULLD256,
26303 IX86_BUILTIN_PMULUDQ256,
26304 IX86_BUILTIN_POR256,
26305 IX86_BUILTIN_PSADBW256,
26306 IX86_BUILTIN_PSHUFB256,
26307 IX86_BUILTIN_PSHUFD256,
26308 IX86_BUILTIN_PSHUFHW256,
26309 IX86_BUILTIN_PSHUFLW256,
26310 IX86_BUILTIN_PSIGNB256,
26311 IX86_BUILTIN_PSIGNW256,
26312 IX86_BUILTIN_PSIGND256,
26313 IX86_BUILTIN_PSLLDQI256,
26314 IX86_BUILTIN_PSLLWI256,
26315 IX86_BUILTIN_PSLLW256,
26316 IX86_BUILTIN_PSLLDI256,
26317 IX86_BUILTIN_PSLLD256,
26318 IX86_BUILTIN_PSLLQI256,
26319 IX86_BUILTIN_PSLLQ256,
26320 IX86_BUILTIN_PSRAWI256,
26321 IX86_BUILTIN_PSRAW256,
26322 IX86_BUILTIN_PSRADI256,
26323 IX86_BUILTIN_PSRAD256,
26324 IX86_BUILTIN_PSRLDQI256,
26325 IX86_BUILTIN_PSRLWI256,
26326 IX86_BUILTIN_PSRLW256,
26327 IX86_BUILTIN_PSRLDI256,
26328 IX86_BUILTIN_PSRLD256,
26329 IX86_BUILTIN_PSRLQI256,
26330 IX86_BUILTIN_PSRLQ256,
26331 IX86_BUILTIN_PSUBB256,
26332 IX86_BUILTIN_PSUBW256,
26333 IX86_BUILTIN_PSUBD256,
26334 IX86_BUILTIN_PSUBQ256,
26335 IX86_BUILTIN_PSUBSB256,
26336 IX86_BUILTIN_PSUBSW256,
26337 IX86_BUILTIN_PSUBUSB256,
26338 IX86_BUILTIN_PSUBUSW256,
26339 IX86_BUILTIN_PUNPCKHBW256,
26340 IX86_BUILTIN_PUNPCKHWD256,
26341 IX86_BUILTIN_PUNPCKHDQ256,
26342 IX86_BUILTIN_PUNPCKHQDQ256,
26343 IX86_BUILTIN_PUNPCKLBW256,
26344 IX86_BUILTIN_PUNPCKLWD256,
26345 IX86_BUILTIN_PUNPCKLDQ256,
26346 IX86_BUILTIN_PUNPCKLQDQ256,
26347 IX86_BUILTIN_PXOR256,
26348 IX86_BUILTIN_MOVNTDQA256,
26349 IX86_BUILTIN_VBROADCASTSS_PS,
26350 IX86_BUILTIN_VBROADCASTSS_PS256,
26351 IX86_BUILTIN_VBROADCASTSD_PD256,
26352 IX86_BUILTIN_VBROADCASTSI256,
26353 IX86_BUILTIN_PBLENDD256,
26354 IX86_BUILTIN_PBLENDD128,
26355 IX86_BUILTIN_PBROADCASTB256,
26356 IX86_BUILTIN_PBROADCASTW256,
26357 IX86_BUILTIN_PBROADCASTD256,
26358 IX86_BUILTIN_PBROADCASTQ256,
26359 IX86_BUILTIN_PBROADCASTB128,
26360 IX86_BUILTIN_PBROADCASTW128,
26361 IX86_BUILTIN_PBROADCASTD128,
26362 IX86_BUILTIN_PBROADCASTQ128,
26363 IX86_BUILTIN_VPERMVARSI256,
26364 IX86_BUILTIN_VPERMDF256,
26365 IX86_BUILTIN_VPERMVARSF256,
26366 IX86_BUILTIN_VPERMDI256,
26367 IX86_BUILTIN_VPERMTI256,
26368 IX86_BUILTIN_VEXTRACT128I256,
26369 IX86_BUILTIN_VINSERT128I256,
26370 IX86_BUILTIN_MASKLOADD,
26371 IX86_BUILTIN_MASKLOADQ,
26372 IX86_BUILTIN_MASKLOADD256,
26373 IX86_BUILTIN_MASKLOADQ256,
26374 IX86_BUILTIN_MASKSTORED,
26375 IX86_BUILTIN_MASKSTOREQ,
26376 IX86_BUILTIN_MASKSTORED256,
26377 IX86_BUILTIN_MASKSTOREQ256,
26378 IX86_BUILTIN_PSLLVV4DI,
26379 IX86_BUILTIN_PSLLVV2DI,
26380 IX86_BUILTIN_PSLLVV8SI,
26381 IX86_BUILTIN_PSLLVV4SI,
26382 IX86_BUILTIN_PSRAVV8SI,
26383 IX86_BUILTIN_PSRAVV4SI,
26384 IX86_BUILTIN_PSRLVV4DI,
26385 IX86_BUILTIN_PSRLVV2DI,
26386 IX86_BUILTIN_PSRLVV8SI,
26387 IX86_BUILTIN_PSRLVV4SI,
26389 IX86_BUILTIN_GATHERSIV2DF,
26390 IX86_BUILTIN_GATHERSIV4DF,
26391 IX86_BUILTIN_GATHERDIV2DF,
26392 IX86_BUILTIN_GATHERDIV4DF,
26393 IX86_BUILTIN_GATHERSIV4SF,
26394 IX86_BUILTIN_GATHERSIV8SF,
26395 IX86_BUILTIN_GATHERDIV4SF,
26396 IX86_BUILTIN_GATHERDIV8SF,
26397 IX86_BUILTIN_GATHERSIV2DI,
26398 IX86_BUILTIN_GATHERSIV4DI,
26399 IX86_BUILTIN_GATHERDIV2DI,
26400 IX86_BUILTIN_GATHERDIV4DI,
26401 IX86_BUILTIN_GATHERSIV4SI,
26402 IX86_BUILTIN_GATHERSIV8SI,
26403 IX86_BUILTIN_GATHERDIV4SI,
26404 IX86_BUILTIN_GATHERDIV8SI,
26406 /* Alternate 4 element gather for the vectorizer where
26407 all operands are 32-byte wide. */
26408 IX86_BUILTIN_GATHERALTSIV4DF,
26409 IX86_BUILTIN_GATHERALTDIV8SF,
26410 IX86_BUILTIN_GATHERALTSIV4DI,
26411 IX86_BUILTIN_GATHERALTDIV8SI,
26413 /* TFmode support builtins. */
26414 IX86_BUILTIN_INFQ,
26415 IX86_BUILTIN_HUGE_VALQ,
26416 IX86_BUILTIN_FABSQ,
26417 IX86_BUILTIN_COPYSIGNQ,
26419 /* Vectorizer support builtins. */
26420 IX86_BUILTIN_CPYSGNPS,
26421 IX86_BUILTIN_CPYSGNPD,
26422 IX86_BUILTIN_CPYSGNPS256,
26423 IX86_BUILTIN_CPYSGNPD256,
26425 /* FMA4 instructions. */
26426 IX86_BUILTIN_VFMADDSS,
26427 IX86_BUILTIN_VFMADDSD,
26428 IX86_BUILTIN_VFMADDPS,
26429 IX86_BUILTIN_VFMADDPD,
26430 IX86_BUILTIN_VFMADDPS256,
26431 IX86_BUILTIN_VFMADDPD256,
26432 IX86_BUILTIN_VFMADDSUBPS,
26433 IX86_BUILTIN_VFMADDSUBPD,
26434 IX86_BUILTIN_VFMADDSUBPS256,
26435 IX86_BUILTIN_VFMADDSUBPD256,
26437 /* FMA3 instructions. */
26438 IX86_BUILTIN_VFMADDSS3,
26439 IX86_BUILTIN_VFMADDSD3,
26441 /* XOP instructions. */
26442 IX86_BUILTIN_VPCMOV,
26443 IX86_BUILTIN_VPCMOV_V2DI,
26444 IX86_BUILTIN_VPCMOV_V4SI,
26445 IX86_BUILTIN_VPCMOV_V8HI,
26446 IX86_BUILTIN_VPCMOV_V16QI,
26447 IX86_BUILTIN_VPCMOV_V4SF,
26448 IX86_BUILTIN_VPCMOV_V2DF,
26449 IX86_BUILTIN_VPCMOV256,
26450 IX86_BUILTIN_VPCMOV_V4DI256,
26451 IX86_BUILTIN_VPCMOV_V8SI256,
26452 IX86_BUILTIN_VPCMOV_V16HI256,
26453 IX86_BUILTIN_VPCMOV_V32QI256,
26454 IX86_BUILTIN_VPCMOV_V8SF256,
26455 IX86_BUILTIN_VPCMOV_V4DF256,
26457 IX86_BUILTIN_VPPERM,
26459 IX86_BUILTIN_VPMACSSWW,
26460 IX86_BUILTIN_VPMACSWW,
26461 IX86_BUILTIN_VPMACSSWD,
26462 IX86_BUILTIN_VPMACSWD,
26463 IX86_BUILTIN_VPMACSSDD,
26464 IX86_BUILTIN_VPMACSDD,
26465 IX86_BUILTIN_VPMACSSDQL,
26466 IX86_BUILTIN_VPMACSSDQH,
26467 IX86_BUILTIN_VPMACSDQL,
26468 IX86_BUILTIN_VPMACSDQH,
26469 IX86_BUILTIN_VPMADCSSWD,
26470 IX86_BUILTIN_VPMADCSWD,
26472 IX86_BUILTIN_VPHADDBW,
26473 IX86_BUILTIN_VPHADDBD,
26474 IX86_BUILTIN_VPHADDBQ,
26475 IX86_BUILTIN_VPHADDWD,
26476 IX86_BUILTIN_VPHADDWQ,
26477 IX86_BUILTIN_VPHADDDQ,
26478 IX86_BUILTIN_VPHADDUBW,
26479 IX86_BUILTIN_VPHADDUBD,
26480 IX86_BUILTIN_VPHADDUBQ,
26481 IX86_BUILTIN_VPHADDUWD,
26482 IX86_BUILTIN_VPHADDUWQ,
26483 IX86_BUILTIN_VPHADDUDQ,
26484 IX86_BUILTIN_VPHSUBBW,
26485 IX86_BUILTIN_VPHSUBWD,
26486 IX86_BUILTIN_VPHSUBDQ,
26488 IX86_BUILTIN_VPROTB,
26489 IX86_BUILTIN_VPROTW,
26490 IX86_BUILTIN_VPROTD,
26491 IX86_BUILTIN_VPROTQ,
26492 IX86_BUILTIN_VPROTB_IMM,
26493 IX86_BUILTIN_VPROTW_IMM,
26494 IX86_BUILTIN_VPROTD_IMM,
26495 IX86_BUILTIN_VPROTQ_IMM,
26497 IX86_BUILTIN_VPSHLB,
26498 IX86_BUILTIN_VPSHLW,
26499 IX86_BUILTIN_VPSHLD,
26500 IX86_BUILTIN_VPSHLQ,
26501 IX86_BUILTIN_VPSHAB,
26502 IX86_BUILTIN_VPSHAW,
26503 IX86_BUILTIN_VPSHAD,
26504 IX86_BUILTIN_VPSHAQ,
26506 IX86_BUILTIN_VFRCZSS,
26507 IX86_BUILTIN_VFRCZSD,
26508 IX86_BUILTIN_VFRCZPS,
26509 IX86_BUILTIN_VFRCZPD,
26510 IX86_BUILTIN_VFRCZPS256,
26511 IX86_BUILTIN_VFRCZPD256,
26513 IX86_BUILTIN_VPCOMEQUB,
26514 IX86_BUILTIN_VPCOMNEUB,
26515 IX86_BUILTIN_VPCOMLTUB,
26516 IX86_BUILTIN_VPCOMLEUB,
26517 IX86_BUILTIN_VPCOMGTUB,
26518 IX86_BUILTIN_VPCOMGEUB,
26519 IX86_BUILTIN_VPCOMFALSEUB,
26520 IX86_BUILTIN_VPCOMTRUEUB,
26522 IX86_BUILTIN_VPCOMEQUW,
26523 IX86_BUILTIN_VPCOMNEUW,
26524 IX86_BUILTIN_VPCOMLTUW,
26525 IX86_BUILTIN_VPCOMLEUW,
26526 IX86_BUILTIN_VPCOMGTUW,
26527 IX86_BUILTIN_VPCOMGEUW,
26528 IX86_BUILTIN_VPCOMFALSEUW,
26529 IX86_BUILTIN_VPCOMTRUEUW,
26531 IX86_BUILTIN_VPCOMEQUD,
26532 IX86_BUILTIN_VPCOMNEUD,
26533 IX86_BUILTIN_VPCOMLTUD,
26534 IX86_BUILTIN_VPCOMLEUD,
26535 IX86_BUILTIN_VPCOMGTUD,
26536 IX86_BUILTIN_VPCOMGEUD,
26537 IX86_BUILTIN_VPCOMFALSEUD,
26538 IX86_BUILTIN_VPCOMTRUEUD,
26540 IX86_BUILTIN_VPCOMEQUQ,
26541 IX86_BUILTIN_VPCOMNEUQ,
26542 IX86_BUILTIN_VPCOMLTUQ,
26543 IX86_BUILTIN_VPCOMLEUQ,
26544 IX86_BUILTIN_VPCOMGTUQ,
26545 IX86_BUILTIN_VPCOMGEUQ,
26546 IX86_BUILTIN_VPCOMFALSEUQ,
26547 IX86_BUILTIN_VPCOMTRUEUQ,
26549 IX86_BUILTIN_VPCOMEQB,
26550 IX86_BUILTIN_VPCOMNEB,
26551 IX86_BUILTIN_VPCOMLTB,
26552 IX86_BUILTIN_VPCOMLEB,
26553 IX86_BUILTIN_VPCOMGTB,
26554 IX86_BUILTIN_VPCOMGEB,
26555 IX86_BUILTIN_VPCOMFALSEB,
26556 IX86_BUILTIN_VPCOMTRUEB,
26558 IX86_BUILTIN_VPCOMEQW,
26559 IX86_BUILTIN_VPCOMNEW,
26560 IX86_BUILTIN_VPCOMLTW,
26561 IX86_BUILTIN_VPCOMLEW,
26562 IX86_BUILTIN_VPCOMGTW,
26563 IX86_BUILTIN_VPCOMGEW,
26564 IX86_BUILTIN_VPCOMFALSEW,
26565 IX86_BUILTIN_VPCOMTRUEW,
26567 IX86_BUILTIN_VPCOMEQD,
26568 IX86_BUILTIN_VPCOMNED,
26569 IX86_BUILTIN_VPCOMLTD,
26570 IX86_BUILTIN_VPCOMLED,
26571 IX86_BUILTIN_VPCOMGTD,
26572 IX86_BUILTIN_VPCOMGED,
26573 IX86_BUILTIN_VPCOMFALSED,
26574 IX86_BUILTIN_VPCOMTRUED,
26576 IX86_BUILTIN_VPCOMEQQ,
26577 IX86_BUILTIN_VPCOMNEQ,
26578 IX86_BUILTIN_VPCOMLTQ,
26579 IX86_BUILTIN_VPCOMLEQ,
26580 IX86_BUILTIN_VPCOMGTQ,
26581 IX86_BUILTIN_VPCOMGEQ,
26582 IX86_BUILTIN_VPCOMFALSEQ,
26583 IX86_BUILTIN_VPCOMTRUEQ,
26585 /* LWP instructions. */
26586 IX86_BUILTIN_LLWPCB,
26587 IX86_BUILTIN_SLWPCB,
26588 IX86_BUILTIN_LWPVAL32,
26589 IX86_BUILTIN_LWPVAL64,
26590 IX86_BUILTIN_LWPINS32,
26591 IX86_BUILTIN_LWPINS64,
26593 IX86_BUILTIN_CLZS,
26595 /* RTM */
26596 IX86_BUILTIN_XBEGIN,
26597 IX86_BUILTIN_XEND,
26598 IX86_BUILTIN_XABORT,
26599 IX86_BUILTIN_XTEST,
26601 /* BMI instructions. */
26602 IX86_BUILTIN_BEXTR32,
26603 IX86_BUILTIN_BEXTR64,
26604 IX86_BUILTIN_CTZS,
26606 /* TBM instructions. */
26607 IX86_BUILTIN_BEXTRI32,
26608 IX86_BUILTIN_BEXTRI64,
26610 /* BMI2 instructions. */
26611 IX86_BUILTIN_BZHI32,
26612 IX86_BUILTIN_BZHI64,
26613 IX86_BUILTIN_PDEP32,
26614 IX86_BUILTIN_PDEP64,
26615 IX86_BUILTIN_PEXT32,
26616 IX86_BUILTIN_PEXT64,
26618 /* ADX instructions. */
26619 IX86_BUILTIN_ADDCARRYX32,
26620 IX86_BUILTIN_ADDCARRYX64,
26622 /* FSGSBASE instructions. */
26623 IX86_BUILTIN_RDFSBASE32,
26624 IX86_BUILTIN_RDFSBASE64,
26625 IX86_BUILTIN_RDGSBASE32,
26626 IX86_BUILTIN_RDGSBASE64,
26627 IX86_BUILTIN_WRFSBASE32,
26628 IX86_BUILTIN_WRFSBASE64,
26629 IX86_BUILTIN_WRGSBASE32,
26630 IX86_BUILTIN_WRGSBASE64,
26632 /* RDRND instructions. */
26633 IX86_BUILTIN_RDRAND16_STEP,
26634 IX86_BUILTIN_RDRAND32_STEP,
26635 IX86_BUILTIN_RDRAND64_STEP,
26637 /* RDSEED instructions. */
26638 IX86_BUILTIN_RDSEED16_STEP,
26639 IX86_BUILTIN_RDSEED32_STEP,
26640 IX86_BUILTIN_RDSEED64_STEP,
26642 /* F16C instructions. */
26643 IX86_BUILTIN_CVTPH2PS,
26644 IX86_BUILTIN_CVTPH2PS256,
26645 IX86_BUILTIN_CVTPS2PH,
26646 IX86_BUILTIN_CVTPS2PH256,
26648 /* CFString built-in for darwin */
26649 IX86_BUILTIN_CFSTRING,
26651 /* Builtins to get CPU type and supported features. */
26652 IX86_BUILTIN_CPU_INIT,
26653 IX86_BUILTIN_CPU_IS,
26654 IX86_BUILTIN_CPU_SUPPORTS,
26656 IX86_BUILTIN_MAX
26657 };
26659 /* Table for the ix86 builtin decls. */
26662 /* Table of all of the builtin functions that are possible with different ISA's
26663 but are waiting to be built until a function is declared to use that
26664 ISA. */
26671 };
26676 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26677 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26678 function decl in the ix86_builtins array. Returns the function decl or
26679 NULL_TREE, if the builtin was not added.
26681 If the front end has a special hook for builtin functions, delay adding
26682 builtin functions that aren't in the current ISA until the ISA is changed
26683 with function specific optimization. Doing so, can save about 300K for the
26684 default compiler. When the builtin is expanded, check at that time whether
26685 it is valid.
26687 If the front end doesn't have a special hook, record all builtins, even if
26688 it isn't an instruction set in the current ISA in case the user uses
26689 function specific options for a different ISA, so that we don't get scope
26690 errors if a builtin is added in the middle of a function scope. */
26696 {
26700 {
26709 {
26715 }
26716 else
26717 {
26723 }
26724 }
26727 }
26729 /* Like def_builtin, but also marks the function decl "const". */
26734 {
26738 else
26742 }
26744 /* Add any new builtin functions for a given ISA that may not have been
26745 declared. This saves a bit of space compared to adding all of the
26746 declarations to the tree, even if we didn't use them. */
26748 static void
26750 {
26754 {
26757 {
26760 /* Don't define the builtin again. */
26766 NULL_TREE);
26771 }
26772 }
26773 }
26775 /* Bits for builtin_description.flag. */
26777 /* Set when we don't support the comparison natively, and should
26778 swap_comparison in order to support it. */
26779 #define BUILTIN_DESC_SWAP_OPERANDS 1
26781 struct builtin_description
26782 {
26789 };
26792 {
26793 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26817 };
26820 {
26821 /* SSE4.2 */
26822 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26823 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26824 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26825 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26826 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26827 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26828 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26829 };
26832 {
26833 /* SSE4.2 */
26834 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26835 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26836 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26837 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26838 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26839 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26840 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26841 };
26843 /* Special builtins with variable number of arguments. */
26845 {
26846 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26847 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26848 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26850 /* MMX */
26851 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26853 /* 3DNow! */
26854 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26856 /* FXSR, XSAVE and XSAVEOPT */
26857 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26858 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26859 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26860 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26861 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26863 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26864 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26865 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26866 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26867 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26869 /* SSE */
26870 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26879 /* SSE or 3DNow!A */
26880 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26881 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26883 /* SSE2 */
26884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26891 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26898 /* SSE3 */
26899 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26901 /* SSE4.1 */
26902 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26904 /* SSE4A */
26905 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26906 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26908 /* AVX */
26909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26912 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26913 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26922 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26923 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26926 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26927 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26932 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26934 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26939 /* AVX2 */
26940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26950 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26951 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26952 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26953 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26954 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26955 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26957 /* FSGSBASE */
26958 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26959 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26960 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26961 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26962 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26963 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26964 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26965 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26967 /* RTM */
26968 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26969 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26970 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26971 };
26973 /* Builtins with variable number of arguments. */
26975 {
26976 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26977 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26978 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26979 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26980 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26981 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26982 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26984 /* MMX */
26985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27048 /* 3DNow! */
27049 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27050 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27051 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27052 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27054 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27055 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27056 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27057 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27058 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27059 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27060 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27061 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27070 /* 3DNow!A */
27071 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27072 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27073 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27074 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27075 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27076 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27078 /* SSE */
27079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27081 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27083 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27087 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27090 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27095 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27131 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27142 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27145 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27146 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27148 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27151 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27154 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27155 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27157 /* SSE MMX or 3Dnow!A */
27158 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27159 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27160 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27162 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27163 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27164 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27165 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27167 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27168 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27170 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27172 /* SSE2 */
27173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27179 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27191 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27192 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27247 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27265 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27283 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27289 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27291 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27309 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27314 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27332 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27342 /* SSE2 MMX */
27343 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27344 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27346 /* SSE3 */
27347 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27348 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27350 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27351 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27352 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27353 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27354 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27355 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27357 /* SSSE3 */
27358 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27359 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27361 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27362 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27365 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27366 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27390 /* SSSE3. */
27391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27394 /* SSE4.1 */
27395 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27396 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27433 /* SSE4.1 */
27434 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27435 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27436 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27437 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27439 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27440 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27441 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27442 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27444 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27447 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27448 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27450 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27451 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27452 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27453 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27458 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27459 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27463 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27465 /* SSE4.2 */
27466 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27467 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27468 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27469 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27470 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27472 /* SSE4A */
27473 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27474 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27475 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27476 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27478 /* AES */
27479 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27480 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27482 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27483 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27484 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27485 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27487 /* PCLMUL */
27488 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27490 /* AVX */
27491 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27492 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27493 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27494 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27495 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27499 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27501 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27592 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27626 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27627 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27631 /* AVX2 */
27632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27633 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27634 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27635 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27636 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27779 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27781 /* BMI */
27782 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27783 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27784 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27786 /* TBM */
27787 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27788 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27790 /* F16C */
27791 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27792 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27793 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27794 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27796 /* BMI2 */
27797 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27798 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27799 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27800 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27801 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27802 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27803 };
27805 /* FMA4 and XOP. */
27806 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27807 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27808 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27809 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27810 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27811 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27812 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27813 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27814 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27815 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27816 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27817 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27818 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27819 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27820 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27821 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27822 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27823 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27824 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27825 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27826 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27827 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27828 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27829 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27830 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27831 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27832 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27833 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27834 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27835 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27836 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27837 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27838 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27839 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27840 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27841 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27842 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27843 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27844 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27845 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27846 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27847 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27848 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27849 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27850 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27851 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27852 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27853 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27854 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27855 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27856 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27857 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27860 {
27901 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27902 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27913 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28059 };
28060 \f
28061 /* TM vector builtins. */
28063 /* Reuse the existing x86-specific `struct builtin_description' cause
28064 we're lazy. Add casts to make them fit. */
28066 {
28067 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28068 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28069 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28070 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28071 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28072 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28073 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28075 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28076 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28077 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28078 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28079 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28080 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28081 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28083 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28084 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28085 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28086 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28087 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28088 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28089 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28091 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28092 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28093 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28094 };
28096 /* TM callbacks. */
28098 /* Return the builtin decl needed to load a vector of TYPE. */
28100 static tree
28102 {
28104 {
28106 {
28113 }
28114 }
28116 }
28118 /* Return the builtin decl needed to store a vector of TYPE. */
28120 static tree
28122 {
28124 {
28126 {
28133 }
28134 }
28136 }
28137 \f
28138 /* Initialize the transactional memory vector load/store builtins. */
28140 static void
28142 {
28146 tree decl;
28153 /* If there are no builtins defined, we must be compiling in a
28154 language without trans-mem support. */
28158 /* Use whatever attributes a normal TM load has. */
28162 /* Use whatever attributes a normal TM store has. */
28166 /* Use whatever attributes a normal TM log has. */
28174 {
28178 {
28186 {
28189 }
28191 {
28194 }
28195 else
28196 {
28199 }
28201 /* The builtin without the prefix for
28202 calling it directly. */
28204 attrs);
28205 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28206 set the TYPE_ATTRIBUTES. */
28210 }
28211 }
28212 }
28214 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28215 in the current target ISA to allow the user to compile particular modules
28216 with different target specific options that differ from the command line
28217 options. */
28218 static void
28220 {
28225 /* Add all special builtins with variable number of operands. */
28229 {
28235 }
28237 /* Add all builtins with variable number of operands. */
28241 {
28247 }
28249 /* pcmpestr[im] insns. */
28253 {
28256 else
28259 }
28261 /* pcmpistr[im] insns. */
28265 {
28268 else
28271 }
28273 /* comi/ucomi insns. */
28275 {
28278 else
28281 }
28283 /* SSE */
28289 /* SSE or 3DNow!A */
28292 IX86_BUILTIN_MASKMOVQ);
28294 /* SSE2 */
28303 /* SSE3. */
28309 /* AES */
28323 /* PCLMUL */
28327 /* RDRND */
28334 IX86_BUILTIN_RDRAND64_STEP);
28336 /* AVX2 */
28338 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28339 IX86_BUILTIN_GATHERSIV2DF);
28342 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28343 IX86_BUILTIN_GATHERSIV4DF);
28346 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28347 IX86_BUILTIN_GATHERDIV2DF);
28350 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28351 IX86_BUILTIN_GATHERDIV4DF);
28354 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28355 IX86_BUILTIN_GATHERSIV4SF);
28358 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28359 IX86_BUILTIN_GATHERSIV8SF);
28362 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28363 IX86_BUILTIN_GATHERDIV4SF);
28366 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28367 IX86_BUILTIN_GATHERDIV8SF);
28370 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28371 IX86_BUILTIN_GATHERSIV2DI);
28374 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28375 IX86_BUILTIN_GATHERSIV4DI);
28378 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28379 IX86_BUILTIN_GATHERDIV2DI);
28382 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28383 IX86_BUILTIN_GATHERDIV4DI);
28386 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28387 IX86_BUILTIN_GATHERSIV4SI);
28390 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28391 IX86_BUILTIN_GATHERSIV8SI);
28394 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28395 IX86_BUILTIN_GATHERDIV4SI);
28398 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28399 IX86_BUILTIN_GATHERDIV8SI);
28402 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28403 IX86_BUILTIN_GATHERALTSIV4DF);
28406 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28407 IX86_BUILTIN_GATHERALTDIV8SF);
28410 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28411 IX86_BUILTIN_GATHERALTSIV4DI);
28414 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28415 IX86_BUILTIN_GATHERALTDIV8SI);
28417 /* RTM. */
28421 /* MMX access to the vec_init patterns. */
28426 V4HI_FTYPE_HI_HI_HI_HI,
28427 IX86_BUILTIN_VEC_INIT_V4HI);
28430 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28431 IX86_BUILTIN_VEC_INIT_V8QI);
28433 /* Access to the vec_extract patterns. */
28455 /* Access to the vec_set patterns. */
28476 /* RDSEED */
28485 /* ADCX */
28490 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28491 IX86_BUILTIN_ADDCARRYX64);
28493 /* Add FMA4 multi-arg argument instructions */
28495 {
28501 }
28502 }
28504 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28505 to return a pointer to VERSION_DECL if the outcome of the expression
28506 formed by PREDICATE_CHAIN is true. This function will be called during
28507 version dispatch to decide which function version to execute. It returns
28508 the basic block at the end, to which more conditions can be added. */
28510 static basic_block
28513 {
28514 gimple return_stmt;
28516 gimple convert_stmt;
28517 gimple call_cond_stmt;
28518 gimple if_else_stmt;
28524 gimple_seq gseq;
28541 {
28549 }
28552 {
28567 else
28568 {
28569 gimple assign_stmt;
28570 /* Use MIN_EXPR to check if any integer is zero?.
28571 and_expr_var = min_expr <cond_var, and_expr_var> */
28579 }
28580 }
28583 integer_zero_node,
28613 }
28615 /* This parses the attribute arguments to target in DECL and determines
28616 the right builtin to use to match the platform specification.
28617 It returns the priority value for this version decl. If PREDICATE_LIST
28618 is not NULL, it stores the list of cpu features that need to be checked
28619 before dispatching this function. */
28621 static unsigned int
28623 {
28624 tree attrs;
28626 tree target_node;
28633 /* Priority of i386 features, greater value is higher priority. This is
28634 used to decide the order in which function dispatch must happen. For
28635 instance, a version specialized for SSE4.2 should be checked for dispatch
28636 before a version for SSE3, as SSE4.2 implies SSE3. */
28637 enum feature_priority
28638 {
28640 P_MMX,
28641 P_SSE,
28642 P_SSE2,
28643 P_SSE3,
28644 P_SSSE3,
28645 P_PROC_SSSE3,
28646 P_SSE4_a,
28647 P_PROC_SSE4_a,
28648 P_SSE4_1,
28649 P_SSE4_2,
28650 P_PROC_SSE4_2,
28651 P_POPCNT,
28652 P_AVX,
28653 P_AVX2,
28654 P_FMA,
28655 P_PROC_FMA
28656 };
28660 /* These are the target attribute strings for which a dispatcher is
28661 available, from fold_builtin_cpu. */
28663 static struct _feature_list
28664 {
28667 }
28669 {
28680 };
28683 static unsigned int NUM_FEATURES
28700 /* Handle arch= if specified. For priority, set it to be 1 more than
28701 the best instruction set the processor can handle. For instance, if
28702 there is a version for atom and a version for ssse3 (the highest ISA
28703 priority for atom), the atom version must be checked for dispatch
28704 before the ssse3 version. */
28706 {
28715 {
28717 {
28742 }
28743 }
28748 {
28752 }
28755 {
28757 /* For a C string literal the length includes the trailing NULL. */
28760 predicate_chain);
28761 }
28762 }
28764 /* Process feature name. */
28771 {
28772 /* Do not process "arch=" */
28774 {
28777 }
28779 {
28781 {
28783 {
28788 predicate_chain);
28789 }
28790 /* Find the maximum priority feature. */
28795 }
28796 }
28798 {
28802 }
28804 }
28808 {
28811 attrs_str);
28813 }
28815 {
28818 }
28821 }
28823 /* This compares the priority of target features in function DECL1
28824 and DECL2. It returns positive value if DECL1 is higher priority,
28825 negative value if DECL2 is higher priority and 0 if they are the
28826 same. */
28828 static int
28830 {
28841 }
28843 /* V1 and V2 point to function versions with different priorities
28844 based on the target ISA. This function compares their priorities. */
28846 static int
28848 {
28850 {
28851 tree version_decl;
28852 tree predicate_chain;
28859 }
28861 /* This function generates the dispatch function for
28862 multi-versioned functions. DISPATCH_DECL is the function which will
28863 contain the dispatch logic. FNDECLS are the function choices for
28864 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28865 in DISPATCH_DECL in which the dispatch code is generated. */
28867 static int
28871 {
28872 tree default_decl;
28873 gimple ifunc_cpu_init_stmt;
28874 gimple_seq gseq;
28876 tree ele;
28882 struct _function_version_info
28883 {
28884 tree version_decl;
28885 tree predicate_chain;
28893 /*fndecls_p is actually a vector. */
28896 /* At least one more version other than the default. */
28903 /* The first version in the vector is the default decl. */
28909 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28910 constructors, so explicity call __builtin_cpu_init here. */
28921 {
28925 /* Get attribute string, parse it and find the right predicate decl.
28926 The predicate function could be a lengthy combination of many
28927 features, like arch-type and various isa-variants. */
28934 actual_versions++;
28938 }
28940 /* Sort the versions according to descending order of dispatch priority. The
28941 priority is based on the ISA. This is not a perfect solution. There
28942 could still be ambiguity. If more than one function version is suitable
28943 to execute, which one should be dispatched? In future, allow the user
28944 to specify a dispatch priority next to the version. */
28954 /* dispatch default version at the end. */
28960 }
28962 /* Comparator function to be used in qsort routine to sort attribute
28963 specification strings to "target". */
28965 static int
28967 {
28971 }
28973 /* ARGLIST is the argument to target attribute. This function tokenizes
28974 the comma separated arguments, sorts them and returns a string which
28975 is a unique identifier for the comma separated arguments. It also
28976 replaces non-identifier characters "=,-" with "_". */
28980 {
28981 tree arg;
28990 {
28995 argnum++;
28998 argnum++;
28999 }
29004 {
29010 }
29012 /* Replace "=,-" with "_". */
29025 {
29027 i++;
29029 }
29036 {
29041 }
29046 }
29048 /* This function changes the assembler name for functions that are
29049 versions. If DECL is a function version and has a "target"
29050 attribute, it appends the attribute string to its assembler name. */
29052 static tree
29054 {
29055 tree version_attr;
29063 "Function versions cannot be marked as gnu_inline,"
29073 /* target attribute string is NULL for default functions. */
29078 version_string
29089 /* Allow assembler name to be modified if already set. */
29097 }
29099 /* This function returns true if FN1 and FN2 are versions of the same function,
29100 that is, the target strings of the function decls are different. This assumes
29101 that FN1 and FN2 have the same signature. */
29103 static bool
29105 {
29117 /* At least one function decl should have the target attribute specified. */
29121 /* Diagnose missing target attribute if one of the decls is already
29122 multi-versioned. */
29124 {
29126 {
29128 {
29133 }
29136 fn2);
29139 /* Prevent diagnosing of the same error multiple times. */
29144 }
29146 }
29151 /* The sorted target strings must be different for fn1 and fn2
29152 to be versions. */
29155 else
29162 }
29164 static tree
29166 {
29167 /* For function version, add the target suffix to the assembler name. */
29171 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29173 #endif
29176 }
29178 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29179 is true, append the full path name of the source file. */
29183 {
29191 /* Get a unique name that can be used globally without any chances
29192 of collision at link time. */
29202 /* Use '.' to concatenate names as it is demangler friendly. */
29205 suffix);
29206 else
29210 }
29212 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29214 /* Make a dispatcher declaration for the multi-versioned function DECL.
29215 Calls to DECL function will be replaced with calls to the dispatcher
29216 by the front-end. Return the decl created. */
29218 static tree
29220 {
29221 tree func_decl;
29241 /* Mark this func as external, the resolver will flip it again if
29242 it gets generated. */
29244 /* This will be of type IFUNCs have to be externally visible. */
29248 }
29250 #endif
29252 /* Returns true if decl is multi-versioned and DECL is the default function,
29253 that is it is not tagged with target specific optimization. */
29255 static bool
29257 {
29266 }
29268 /* Make a dispatcher declaration for the multi-versioned function DECL.
29269 Calls to DECL function will be replaced with calls to the dispatcher
29270 by the front-end. Returns the decl of the dispatcher function. */
29272 static tree
29274 {
29283 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29287 #endif
29302 /* Find the default version and make it the first node. */
29304 /* Go to the beginnig of the chain. */
29309 {
29314 }
29316 /* If there is no default node, just return NULL. */
29320 /* Make default info the first node. */
29322 {
29329 }
29333 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29334 /* Right now, the dispatching is done via ifunc. */
29340 dispatcher_version_info
29345 /* Set the dispatcher for all the versions. */
29348 {
29351 }
29352 #else
29354 "multiversioning needs ifunc which is not supported "
29356 #endif
29358 }
29360 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29361 it to CHAIN. */
29363 static tree
29365 {
29366 tree attr_name;
29367 tree attr_arg_name;
29368 tree attr_args;
29369 tree attr;
29376 }
29378 /* Make the resolver function decl to dispatch the versions of
29379 a multi-versioned function, DEFAULT_DECL. Create an
29380 empty basic block in the resolver and store the pointer in
29381 EMPTY_BB. Return the decl of the resolver function. */
29383 static tree
29387 {
29392 /* IFUNC's have to be globally visible. So, if the default_decl is
29393 not, then the name of the IFUNC should be made unique. */
29397 /* Append the filename to the resolver function if the versions are
29398 not externally visible. This is because the resolver function has
29399 to be externally visible for the loader to find it. So, appending
29400 the filename will prevent conflicts with a resolver function from
29401 another module which is based on the same version name. */
29404 /* The resolver function should return a (void *). */
29415 /* IFUNC resolvers have to be externally visible. */
29419 /* Resolver is not external, body is generated. */
29429 {
29430 /* In this case, each translation unit with a call to this
29431 versioned function will put out a resolver. Ensure it
29432 is comdat to keep just one copy. */
29435 }
29436 /* Build result decl and add to function_decl. */
29452 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29456 /* Create the alias for dispatch to resolver here. */
29457 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29461 }
29463 /* Generate the dispatching code body to dispatch multi-versioned function
29464 DECL. The target hook is called to process the "target" attributes and
29465 provide the code to dispatch the right function at run-time. NODE points
29466 to the dispatcher decl whose body will be created. */
29468 static tree
29470 {
29471 tree resolver_decl;
29472 basic_block empty_bb;
29474 tree default_ver_decl;
29490 /* The first version in the chain corresponds to the default version. */
29493 /* node is going to be an alias, so remove the finalized bit. */
29507 {
29509 /* Check for virtual functions here again, as by this time it should
29510 have been determined if this function needs a vtable index or
29511 not. This happens for methods in derived classes that override
29512 virtual methods in base classes but are not explicitly marked as
29513 virtual. */
29518 }
29525 }
29526 /* This builds the processor_model struct type defined in
29527 libgcc/config/i386/cpuinfo.c */
29529 static tree
29531 {
29538 /* The first 3 fields are unsigned int. */
29540 {
29546 }
29548 /* The last field is an array of unsigned integers of size one. */
29559 }
29561 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29563 static tree
29565 {
29566 tree new_decl;
29569 VAR_DECL,
29571 type);
29584 }
29586 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29587 into an integer defined in libgcc/config/i386/cpuinfo.c */
29589 static tree
29591 {
29597 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29598 enum processor_features
29599 {
29601 F_MMX,
29602 F_POPCNT,
29603 F_SSE,
29604 F_SSE2,
29605 F_SSE3,
29606 F_SSSE3,
29607 F_SSE4_1,
29608 F_SSE4_2,
29609 F_AVX,
29610 F_AVX2,
29611 F_MAX
29612 };
29614 /* These are the values for vendor types and cpu types and subtypes
29615 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29616 the corresponding start value. */
29617 enum processor_model
29618 {
29620 M_AMD,
29621 M_CPU_TYPE_START,
29622 M_INTEL_ATOM,
29623 M_INTEL_CORE2,
29624 M_INTEL_COREI7,
29625 M_AMDFAM10H,
29626 M_AMDFAM15H,
29627 M_CPU_SUBTYPE_START,
29628 M_INTEL_COREI7_NEHALEM,
29629 M_INTEL_COREI7_WESTMERE,
29630 M_INTEL_COREI7_SANDYBRIDGE,
29631 M_AMDFAM10H_BARCELONA,
29632 M_AMDFAM10H_SHANGHAI,
29633 M_AMDFAM10H_ISTANBUL,
29634 M_AMDFAM15H_BDVER1,
29635 M_AMDFAM15H_BDVER2,
29636 M_AMDFAM15H_BDVER3
29637 };
29639 static struct _arch_names_table
29640 {
29643 }
29645 {
29662 };
29664 static struct _isa_names_table
29665 {
29668 }
29670 {
29682 };
29693 {
29694 /* *args must be a expr that can contain other EXPRS leading to a
29695 STRING_CST. */
29697 {
29700 }
29702 }
29707 {
29708 tree ref;
29709 tree field;
29710 tree final;
29713 unsigned int NUM_ARCH_NAMES
29722 {
29726 }
29731 /* CPU types are stored in the next field. */
29734 {
29737 }
29739 /* CPU subtypes are stored in the next field. */
29741 {
29744 }
29746 /* Get the appropriate field in __cpu_model. */
29750 /* Check the value. */
29754 }
29756 {
29757 tree ref;
29758 tree array_elt;
29759 tree field;
29760 tree final;
29763 unsigned int NUM_ISA_NAMES
29772 {
29776 }
29779 /* Get the last field, which is __cpu_features. */
29783 /* Get the appropriate field: __cpu_model.__cpu_features */
29787 /* Access the 0th element of __cpu_features array. */
29792 /* Return __cpu_model.__cpu_features[0] & field_val */
29796 }
29798 }
29800 static tree
29803 {
29805 {
29810 {
29813 }
29814 }
29816 #ifdef SUBTARGET_FOLD_BUILTIN
29818 #endif
29821 }
29823 /* Make builtins to detect cpu type and features supported. NAME is
29824 the builtin name, CODE is the builtin code, and FTYPE is the function
29825 type of the builtin. */
29827 static void
29830 {
29831 tree decl;
29832 tree type;
29840 }
29842 /* Make builtins to get CPU type and features supported. The created
29843 builtins are :
29845 __builtin_cpu_init (), to detect cpu type and features,
29846 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29847 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29848 */
29850 static void
29852 {
29859 }
29861 /* Internal method for ix86_init_builtins. */
29863 static void
29865 {
29877 sysv_va_ref =
29880 fnvoid_va_end_ms =
29882 fnvoid_va_start_ms =
29884 fnvoid_va_end_sysv =
29886 fnvoid_va_start_sysv =
29888 NULL_TREE);
29889 fnvoid_va_copy_ms =
29891 NULL_TREE);
29892 fnvoid_va_copy_sysv =
29908 }
29910 static void
29912 {
29915 /* The __float80 type. */
29918 {
29919 /* The __float80 type. */
29924 }
29927 /* The __float128 type. */
29933 /* This macro is built by i386-builtin-types.awk. */
29934 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29935 }
29937 static void
29939 {
29940 tree t;
29944 /* Builtins to get CPU type and features. */
29947 /* TFmode support builtins. */
29953 /* We will expand them to normal call if SSE isn't available since
29954 they are used by libgcc. */
29973 #ifdef SUBTARGET_INIT_BUILTINS
29974 SUBTARGET_INIT_BUILTINS;
29975 #endif
29976 }
29978 /* Return the ix86 builtin for CODE. */
29980 static tree
29982 {
29987 }
29989 /* Errors in the source file can cause expand_expr to return const0_rtx
29990 where we expect a vector. To avoid crashing, use one of the vector
29991 clear instructions. */
29992 static rtx
29994 {
29998 }
30000 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30002 static rtx
30004 {
30005 rtx pat;
30025 {
30029 }
30043 }
30045 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30047 static rtx
30051 {
30052 rtx pat;
30060 rtx op;
30067 {
30147 }
30157 {
30164 {
30166 {
30169 {
30187 xop_rotl:
30189 {
30192 gcc_checking_assert
30194 }
30195 else
30196 {
30197 gcc_checking_assert
30208 }
30212 }
30213 }
30214 }
30215 else
30216 {
30217 non_constant:
30221 /* If we aren't optimizing, only allow one memory operand to be
30222 generated. */
30224 num_memory++;
30232 }
30236 }
30239 {
30250 else
30251 {
30257 }
30270 }
30277 }
30279 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30280 insns with vec_merge. */
30282 static rtx
30284 rtx target)
30285 {
30286 rtx pat;
30313 }
30315 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30317 static rtx
30320 {
30321 rtx pat;
30326 rtx op2;
30337 /* Swap operands if we have a comparison that isn't available in
30338 hardware. */
30340 {
30345 }
30365 }
30367 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30369 static rtx
30371 rtx target)
30372 {
30373 rtx pat;
30387 /* Swap operands if we have a comparison that isn't available in
30388 hardware. */
30390 {
30394 }
30415 const0_rtx)));
30418 }
30420 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30422 static rtx
30424 rtx target)
30425 {
30426 rtx pat;
30451 }
30453 static rtx
30456 {
30457 rtx pat;
30462 rtx op2;
30489 }
30491 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30493 static rtx
30495 rtx target)
30496 {
30497 rtx pat;
30530 const0_rtx)));
30533 }
30535 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30537 static rtx
30540 {
30541 rtx pat;
30579 {
30582 }
30585 {
30594 }
30596 {
30605 }
30606 else
30607 {
30614 }
30622 {
30627 emit_insn
30631 FLAGS_REG),
30632 const0_rtx)));
30634 }
30635 else
30637 }
30640 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30642 static rtx
30645 {
30646 rtx pat;
30674 {
30677 }
30680 {
30689 }
30691 {
30700 }
30701 else
30702 {
30709 }
30717 {
30722 emit_insn
30726 FLAGS_REG),
30727 const0_rtx)));
30729 }
30730 else
30732 }
30734 /* Subroutine of ix86_expand_builtin to take care of insns with
30735 variable number of operands. */
30737 static rtx
30740 {
30745 struct
30746 {
30747 rtx op;
30759 {
31038 }
31043 {
31046 }
31049 {
31056 }
31057 else
31058 {
31061 }
31064 {
31071 {
31072 /* SIMD shift insns take either an 8-bit immediate or
31073 register as count. But builtin functions take int as
31074 count. If count doesn't match, we put it in register. */
31076 {
31080 }
31081 }
31083 {
31086 {
31140 {
31143 {
31146 }
31152 }
31154 }
31155 }
31156 else
31157 {
31161 /* If we aren't optimizing, only allow one memory operand to
31162 be generated. */
31164 num_memory++;
31167 {
31170 }
31171 else
31172 {
31175 }
31176 }
31180 }
31183 {
31200 }
31207 }
31209 /* Subroutine of ix86_expand_builtin to take care of special insns
31210 with variable number of operands. */
31212 static rtx
31215 {
31216 tree arg;
31219 struct
31220 {
31221 rtx op;
31231 {
31279 /* Reserve memory operand for target. */
31310 /* Reserve memory operand for target. */
31324 }
31329 {
31334 {
31337 }
31338 else
31341 }
31342 else
31343 {
31350 }
31353 {
31362 {
31364 {
31370 else
31373 }
31374 }
31375 else
31376 {
31378 {
31379 /* This must be the memory operand. */
31384 }
31385 else
31386 {
31387 /* This must be register. */
31394 }
31395 }
31399 }
31402 {
31417 }
31423 }
31425 /* Return the integer constant in ARG. Constrain it to be in the range
31426 of the subparts of VEC_TYPE; issue an error if not. */
31428 static int
31430 {
31435 {
31438 }
31441 }
31443 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31444 ix86_expand_vector_init. We DO have language-level syntax for this, in
31445 the form of (type){ init-list }. Except that since we can't place emms
31446 instructions from inside the compiler, we can't allow the use of MMX
31447 registers unless the user explicitly asks for it. So we do *not* define
31448 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31449 we have builtins invoked by mmintrin.h that gives us license to emit
31450 these sorts of instructions. */
31452 static rtx
31454 {
31464 {
31467 }
31474 }
31476 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31477 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31478 had a language-level syntax for referencing vector elements. */
31480 static rtx
31482 {
31486 rtx op0;
31506 }
31508 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31509 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31510 a language-level syntax for referencing vector elements. */
31512 static rtx
31514 {
31538 /* OP0 is the source of these builtin functions and shouldn't be
31539 modified. Create a copy, use it and return it as target. */
31545 }
31547 /* Expand an expression EXP that calls a built-in function,
31548 with result going to TARGET if that's convenient
31549 (and in mode MODE if that's convenient).
31550 SUBTARGET may be used as the target for computing one of EXP's operands.
31551 IGNORE is nonzero if the value is to be ignored. */
31553 static rtx
31557 {
31567 /* For CPU builtins that can be folded, fold first and expand the fold. */
31569 {
31571 {
31572 /* Make it call __cpu_indicator_init in libgcc. */
31578 }
31581 {
31586 }
31587 }
31589 /* Determine whether the builtin function is available under the current ISA.
31590 Originally the builtin was not created if it wasn't applicable to the
31591 current ISA based on the command line switches. With function specific
31592 options, we need to check in the context of the function making the call
31593 whether it is supported. */
31596 {
31602 else
31603 {
31607 }
31609 }
31612 {
31616 ? CODE_FOR_mmx_maskmovq
31618 /* Note the arg order is different from the operand order. */
31719 {
31720 REAL_VALUE_TYPE inf;
31721 rtx tmp;
31733 }
31743 {
31749 insn = (TARGET_64BIT
31753 }
31755 {
31756 insn = (TARGET_64BIT
31760 }
31761 else
31762 {
31765 insn = (TARGET_64BIT
31773 {
31776 }
31778 }
31784 {
31789 }
31799 {
31814 }
31820 {
31823 }
31843 {
31846 }
31852 {
31856 {
31877 }
31882 }
31883 else
31884 {
31886 {
31898 }
31900 }
31930 ? CODE_FOR_tbm_bextri_si
31933 {
31936 }
31937 else
31938 {
31947 }
31963 rdrand_step:
31970 {
31973 }
31979 /* Emit SImode conditional move. */
31981 {
31984 }
31987 else
31994 const0_rtx);
32013 rdseed_step:
32020 {
32023 }
32029 const0_rtx);
32047 addcarryx:
32055 /* Generate CF from input operand. */
32060 /* Gen ADCX instruction to compute X+Y+CF. */
32075 /* Store the result. */
32078 {
32081 }
32084 /* Return current CF value. */
32153 gather_gen:
32164 /* Note the arg order is different from the operand order. */
32173 else
32178 {
32184 }
32187 {
32192 else
32202 }
32204 /* Force memory operand only with base register here. But we
32205 don't want to do it on memory operand for other builtin
32206 functions. */
32218 {
32221 }
32223 /* Optimize. If mask is known to have all high bits set,
32224 replace op0 with pc_rtx to signal that the instruction
32225 overwrites the whole destination and doesn't use its
32226 previous contents. */
32228 {
32230 {
32233 {
32237 negative++;
32240 negative++;
32241 }
32244 }
32246 {
32247 /* Recognize also when mask is like:
32248 __v2df src = _mm_setzero_pd ();
32249 __v2df mask = _mm_cmpeq_pd (src, src);
32250 or
32251 __v8sf src = _mm256_setzero_ps ();
32252 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32253 as that is a cheaper way to load all ones into
32254 a register than having to load a constant from
32255 memory. */
32258 {
32263 {
32270 /* FALLTHRU */
32280 }
32281 }
32282 }
32283 }
32292 {
32299 else
32301 }
32302 else
32313 {
32316 }
32322 }
32335 {
32339 /* Emit a normal call if SSE isn't available. */
32343 }
32368 }
32370 /* Returns a function decl for a vectorized version of the builtin function
32371 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32372 if it is not available. */
32374 static tree
32376 tree type_in)
32377 {
32393 {
32396 {
32401 }
32406 {
32411 }
32417 /* The round insn does not trap on denormals. */
32422 {
32427 }
32433 /* The round insn does not trap on denormals. */
32438 {
32443 }
32449 /* The round insn does not trap on denormals. */
32454 {
32459 }
32465 /* The round insn does not trap on denormals. */
32470 {
32475 }
32482 {
32487 }
32494 {
32499 }
32505 /* The round insn does not trap on denormals. */
32510 {
32515 }
32521 /* The round insn does not trap on denormals. */
32526 {
32531 }
32536 {
32541 }
32546 {
32551 }
32555 /* The round insn does not trap on denormals. */
32560 {
32565 }
32569 /* The round insn does not trap on denormals. */
32574 {
32579 }
32583 /* The round insn does not trap on denormals. */
32588 {
32593 }
32597 /* The round insn does not trap on denormals. */
32602 {
32607 }
32611 /* The round insn does not trap on denormals. */
32616 {
32621 }
32625 /* The round insn does not trap on denormals. */
32630 {
32635 }
32639 /* The round insn does not trap on denormals. */
32644 {
32649 }
32653 /* The round insn does not trap on denormals. */
32658 {
32663 }
32667 /* The round insn does not trap on denormals. */
32672 {
32677 }
32681 /* The round insn does not trap on denormals. */
32686 {
32691 }
32696 {
32701 }
32706 {
32711 }
32716 }
32718 /* Dispatch to a handler for a vectorization library. */
32721 type_in);
32724 }
32726 /* Handler for an SVML-style interface to
32727 a library with vectorized intrinsics. */
32729 static tree
32731 {
32739 /* The SVML is suitable for unsafe math only. */
32752 {
32799 }
32808 {
32811 }
32812 else
32815 /* Convert to uppercase. */
32820 args;
32822 arity++;
32826 else
32829 /* Build a function declaration for the vectorized function. */
32838 }
32840 /* Handler for an ACML-style interface to
32841 a library with vectorized intrinsics. */
32843 static tree
32845 {
32853 /* The ACML is 64bits only and suitable for unsafe math only as
32854 it does not correctly support parts of IEEE with the required
32855 precision such as denormals. */
32869 {
32899 }
32906 args;
32908 arity++;
32912 else
32915 /* Build a function declaration for the vectorized function. */
32924 }
32926 /* Returns a decl of a function that implements gather load with
32927 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32928 Return NULL_TREE if it is not available. */
32930 static tree
32933 {
32949 /* v*gather* insn sign extends index to pointer mode. */
32961 {
32988 }
32991 }
32993 /* Returns a code for a target-specific builtin that implements
32994 reciprocal of the function, or NULL_TREE if not available. */
32996 static tree
32999 {
33006 /* Machine dependent builtins. */
33008 {
33009 /* Vectorized version of sqrt to rsqrt conversion. */
33018 }
33019 else
33020 /* Normal builtins. */
33022 {
33023 /* Sqrt to rsqrt conversion. */
33029 }
33030 }
33031 \f
33032 /* Helper for avx_vpermilps256_operand et al. This is also used by
33033 the expansion functions to turn the parallel back into a mask.
33034 The return value is 0 for no match and the imm8+1 for a match. */
33036 int
33038 {
33046 /* Validate that all of the elements are constants, and not totally
33047 out of range. Copy the data into an integral array to make the
33048 subsequent checks easier. */
33050 {
33060 }
33063 {
33065 /* In the 256-bit DFmode case, we can only move elements within
33066 a 128-bit lane. */
33068 {
33072 }
33074 {
33078 }
33082 /* In the 256-bit SFmode case, we have full freedom of movement
33083 within the low 128-bit lane, but the high 128-bit lane must
33084 mirror the exact same pattern. */
33089 /* FALLTHRU */
33093 /* In the 128-bit case, we've full freedom in the placement of
33094 the elements from the source operand. */
33101 }
33103 /* Make sure success has a non-zero value by adding one. */
33105 }
33107 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33108 the expansion functions to turn the parallel back into a mask.
33109 The return value is 0 for no match and the imm8+1 for a match. */
33111 int
33113 {
33121 /* Validate that all of the elements are constants, and not totally
33122 out of range. Copy the data into an integral array to make the
33123 subsequent checks easier. */
33125 {
33135 }
33137 /* Validate that the halves of the permute are halves. */
33145 /* Reconstruct the mask. */
33147 {
33153 }
33155 /* Make sure success has a non-zero value by adding one. */
33157 }
33158 \f
33159 /* Store OPERAND to the memory after reload is completed. This means
33160 that we can't easily use assign_stack_local. */
33161 rtx
33163 {
33164 rtx result;
33168 {
33171 stack_pointer_rtx,
33174 }
33176 {
33178 {
33182 /* FALLTHRU */
33188 stack_pointer_rtx)),
33189 operand));
33193 }
33195 }
33196 else
33197 {
33199 {
33201 {
33208 stack_pointer_rtx)),
33214 stack_pointer_rtx)),
33216 }
33219 /* Store HImodes as SImodes. */
33221 /* FALLTHRU */
33227 stack_pointer_rtx)),
33228 operand));
33232 }
33234 }
33236 }
33238 /* Free operand from the memory. */
33239 void
33241 {
33243 {
33248 else
33250 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33251 to pop or add instruction if registers are available. */
33255 }
33256 }
33258 /* Return a register priority for hard reg REGNO. */
33259 static int
33261 {
33262 /* ebp and r13 as the base always wants a displacement, r12 as the
33263 base always wants an index. So discourage their usage in an
33264 address. */
33269 /* New x86-64 int registers result in bigger code size. Discourage
33270 them. */
33273 /* New x86-64 SSE registers result in bigger code size. Discourage
33274 them. */
33277 /* Usage of AX register results in smaller code. Prefer it. */
33281 }
33283 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33285 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33286 QImode must go into class Q_REGS.
33287 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33288 movdf to do mem-to-mem moves through integer regs. */
33290 static reg_class_t
33292 {
33295 /* We're only allowed to return a subclass of CLASS. Many of the
33296 following checks fail for NO_REGS, so eliminate that early. */
33300 /* All classes can load zeros. */
33304 /* Force constants into memory if we are loading a (nonzero) constant into
33305 an MMX or SSE register. This is because there are no MMX/SSE instructions
33306 to load from a constant. */
33311 /* Prefer SSE regs only, if we can use them for math. */
33315 /* Floating-point constants need more complex checks. */
33317 {
33318 /* General regs can load everything. */
33322 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33323 zero above. We only want to wind up preferring 80387 registers if
33324 we plan on doing computation with them. */
33327 {
33328 /* Limit class to non-sse. */
33337 }
33340 }
33342 /* Generally when we see PLUS here, it's the function invariant
33343 (plus soft-fp const_int). Which can only be computed into general
33344 regs. */
33348 /* QImode constants are easy to load, but non-constant QImode data
33349 must go into Q_REGS. */
33351 {
33357 }
33360 }
33362 /* Discourage putting floating-point values in SSE registers unless
33363 SSE math is being used, and likewise for the 387 registers. */
33364 static reg_class_t
33366 {
33369 /* Restrict the output reload class to the register bank that we are doing
33370 math on. If we would like not to return a subset of CLASS, reject this
33371 alternative: if reload cannot do this, it will still use its choice. */
33377 {
33382 else
33384 }
33387 }
33389 static reg_class_t
33392 {
33393 /* Double-word spills from general registers to non-offsettable memory
33394 references (zero-extended addresses) require special handling. */
33400 {
33402 ? CODE_FOR_reload_noff_load
33404 /* Add the cost of moving address to a temporary. */
33408 }
33410 /* QImode spills from non-QI registers require
33411 intermediate register on 32bit targets. */
33420 {
33425 else
33431 /* Return Q_REGS if the operand is in memory. */
33434 }
33436 /* This condition handles corner case where an expression involving
33437 pointers gets vectorized. We're trying to use the address of a
33438 stack slot as a vector initializer.
33440 (set (reg:V2DI 74 [ vect_cst_.2 ])
33441 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33443 Eventually frame gets turned into sp+offset like this:
33445 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33446 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33447 (const_int 392 [0x188]))))
33449 That later gets turned into:
33451 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33452 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33453 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33455 We'll have the following reload recorded:
33457 Reload 0: reload_in (DI) =
33458 (plus:DI (reg/f:DI 7 sp)
33459 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33460 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33461 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33462 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33463 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33464 reload_reg_rtx: (reg:V2DI 22 xmm1)
33466 Which isn't going to work since SSE instructions can't handle scalar
33467 additions. Returning GENERAL_REGS forces the addition into integer
33468 register and reload can handle subsequent reloads without problems. */
33476 }
33478 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33480 static bool
33482 {
33484 {
33499 }
33502 }
33504 /* If we are copying between general and FP registers, we need a memory
33505 location. The same is true for SSE and MMX registers.
33507 To optimize register_move_cost performance, allow inline variant.
33509 The macro can't work reliably when one of the CLASSES is class containing
33510 registers from multiple units (SSE, MMX, integer). We avoid this by never
33511 combining those units in single alternative in the machine description.
33512 Ensure that this constraint holds to avoid unexpected surprises.
33514 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33515 enforce these sanity checks. */
33520 {
33527 {
33530 }
33535 /* ??? This is a lie. We do have moves between mmx/general, and for
33536 mmx/sse2. But by saying we need secondary memory we discourage the
33537 register allocator from using the mmx registers unless needed. */
33542 {
33543 /* SSE1 doesn't have any direct moves from other classes. */
33547 /* If the target says that inter-unit moves are more expensive
33548 than moving through memory, then don't generate them. */
33552 /* Between SSE and general, we have moves no larger than word size. */
33555 }
33558 }
33560 bool
33563 {
33565 }
33567 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33569 On the 80386, this is the size of MODE in words,
33570 except in the FP regs, where a single reg is always enough. */
33572 static unsigned char
33574 {
33576 {
33581 else
33583 }
33584 else
33585 {
33588 else
33590 }
33591 }
33593 /* Return true if the registers in CLASS cannot represent the change from
33594 modes FROM to TO. */
33596 bool
33599 {
33603 /* x87 registers can't do subreg at all, as all values are reformatted
33604 to extended precision. */
33609 {
33610 /* Vector registers do not support QI or HImode loads. If we don't
33611 disallow a change to these modes, reload will assume it's ok to
33612 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33613 the vec_dupv4hi pattern. */
33617 /* Vector registers do not support subreg with nonzero offsets, which
33618 are otherwise valid for integer registers. Since we can't see
33619 whether we have a nonzero offset from here, prohibit all
33620 nonparadoxical subregs changing size. */
33623 }
33626 }
33628 /* Return the cost of moving data of mode M between a
33629 register and memory. A value of 2 is the default; this cost is
33630 relative to those in `REGISTER_MOVE_COST'.
33632 This function is used extensively by register_move_cost that is used to
33633 build tables at startup. Make it inline in this case.
33634 When IN is 2, return maximum of in and out move cost.
33636 If moving between registers and memory is more expensive than
33637 between two registers, you should define this macro to express the
33638 relative cost.
33640 Model also increased moving costs of QImode registers in non
33641 Q_REGS classes.
33642 */
33646 {
33649 {
33652 {
33664 }
33668 }
33670 {
33673 {
33685 }
33689 }
33691 {
33694 {
33703 }
33707 }
33709 {
33712 {
33718 else
33723 }
33724 else
33725 {
33730 else
33732 }
33739 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33746 else
33750 }
33751 }
33753 static int
33756 {
33758 }
33761 /* Return the cost of moving data from a register in class CLASS1 to
33762 one in class CLASS2.
33764 It is not required that the cost always equal 2 when FROM is the same as TO;
33765 on some machines it is expensive to move between registers if they are not
33766 general registers. */
33768 static int
33770 reg_class_t class2_i)
33771 {
33775 /* In case we require secondary memory, compute cost of the store followed
33776 by load. In order to avoid bad register allocation choices, we need
33777 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33780 {
33786 /* In case of copying from general_purpose_register we may emit multiple
33787 stores followed by single load causing memory size mismatch stall.
33788 Count this as arbitrarily high cost of 20. */
33793 /* In the case of FP/MMX moves, the registers actually overlap, and we
33794 have to switch modes in order to treat them differently. */
33800 }
33802 /* Moves between SSE/MMX and integer unit are expensive. */
33806 /* ??? By keeping returned value relatively high, we limit the number
33807 of moves between integer and MMX/SSE registers for all targets.
33808 Additionally, high value prevents problem with x86_modes_tieable_p(),
33809 where integer modes in MMX/SSE registers are not tieable
33810 because of missing QImode and HImode moves to, from or between
33811 MMX/SSE registers. */
33821 }
33823 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33824 MODE. */
33826 bool
33828 {
33829 /* Flags and only flags can only hold CCmode values. */
33839 {
33840 /* We implement the move patterns for all vector modes into and
33841 out of SSE registers, even when no operation instructions
33842 are available. OImode move is available only when AVX is
33843 enabled. */
33850 }
33852 {
33853 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33854 so if the register is available at all, then we can move data of
33855 the given mode into or out of it. */
33858 }
33861 {
33862 /* Take care for QImode values - they can be in non-QI regs,
33863 but then they do cause partial register stalls. */
33869 }
33870 /* We handle both integer and floats in the general purpose registers. */
33877 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33878 on to use that value in smaller contexts, this can easily force a
33879 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33880 supporting DImode, allow it. */
33885 }
33887 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33888 tieable integer mode. */
33890 static bool
33892 {
33894 {
33907 }
33908 }
33910 /* Return true if MODE1 is accessible in a register that can hold MODE2
33911 without copying. That is, all register classes that can hold MODE2
33912 can also hold MODE1. */
33914 bool
33916 {
33924 /* MODE2 being XFmode implies fp stack or general regs, which means we
33925 can tie any smaller floating point modes to it. Note that we do not
33926 tie this with TFmode. */
33930 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33931 that we can tie it with SFmode. */
33935 /* If MODE2 is only appropriate for an SSE register, then tie with
33936 any other mode acceptable to SSE registers. */
33946 /* If MODE2 is appropriate for an MMX register, then tie
33947 with any other mode acceptable to MMX registers. */
33954 }
33956 /* Return the cost of moving between two registers of mode MODE. */
33958 static int
33960 {
33964 {
33995 }
33997 /* Return the cost of moving between two registers of mode MODE,
33998 assuming that the move will be in pieces of at most UNITS bytes. */
34000 }
34002 /* Compute a (partial) cost for rtx X. Return true if the complete
34003 cost has been computed, and false if subexpressions should be
34004 scanned. In either case, *TOTAL contains the cost result. */
34006 static bool
34009 {
34016 {
34020 {
34023 }
34035 && (!TARGET_64BIT
34040 else
34046 {
34049 }
34051 {
34061 }
34063 {
34066 {
34075 }
34076 }
34077 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34078 it'll probably end up. Add a penalty for size. */
34085 /* The zero extensions is often completely free on x86_64, so make
34086 it as cheap as possible. */
34092 else
34104 {
34107 {
34110 }
34113 {
34116 }
34117 }
34118 /* FALLTHRU */
34125 {
34126 /* ??? Should be SSE vector operation cost. */
34127 /* At least for published AMD latencies, this really is the same
34128 as the latency for a simple fpu operation like fabs. */
34129 /* V*QImode is emulated with 1-11 insns. */
34131 {
34134 {
34135 /* For XOP we use vpshab, which requires a broadcast of the
34136 value to the variable shift insn. For constants this
34137 means a V16Q const in mem; even when we can perform the
34138 shift with one insn set the cost to prefer paddb. */
34140 {
34145 }
34147 }
34151 }
34152 else
34154 }
34156 {
34158 {
34161 else
34163 }
34164 else
34165 {
34168 else
34170 }
34171 }
34172 else
34173 {
34176 else
34178 }
34182 {
34183 rtx sub;
34188 /* ??? SSE scalar/vector cost should be used here. */
34189 /* ??? Bald assumption that fma has the same cost as fmul. */
34193 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34204 }
34208 {
34209 /* ??? SSE scalar cost should be used here. */
34212 }
34214 {
34217 }
34219 {
34220 /* ??? SSE vector cost should be used here. */
34223 }
34225 {
34226 /* V*QImode is emulated with 7-13 insns. */
34228 {
34235 }
34236 /* V*DImode is emulated with 5-8 insns. */
34238 {
34241 else
34243 }
34244 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34245 insns, including two PMULUDQ. */
34248 else
34251 }
34252 else
34253 {
34258 {
34261 nbits++;
34262 }
34263 else
34264 /* This is arbitrary. */
34267 /* Compute costs correctly for widening multiplication. */
34271 {
34278 {
34282 else
34284 }
34288 }
34296 }
34303 /* ??? SSE cost should be used here. */
34308 /* ??? SSE vector cost should be used here. */
34310 else
34317 {
34322 {
34325 {
34333 }
34334 }
34337 {
34340 {
34346 }
34347 }
34349 {
34357 }
34358 }
34359 /* FALLTHRU */
34363 {
34364 /* ??? SSE cost should be used here. */
34367 }
34369 {
34372 }
34374 {
34375 /* ??? SSE vector cost should be used here. */
34378 }
34379 /* FALLTHRU */
34386 {
34393 }
34394 /* FALLTHRU */
34398 {
34399 /* ??? SSE cost should be used here. */
34402 }
34404 {
34407 }
34409 {
34410 /* ??? SSE vector cost should be used here. */
34413 }
34414 /* FALLTHRU */
34418 {
34419 /* ??? Should be SSE vector operation cost. */
34420 /* At least for published AMD latencies, this really is the same
34421 as the latency for a simple fpu operation like fabs. */
34423 }
34426 else
34435 {
34436 /* This kind of construct is implemented using test[bwl].
34437 Treat it as if we had an AND. */
34442 }
34452 /* ??? SSE cost should be used here. */
34457 /* ??? SSE vector cost should be used here. */
34463 /* ??? SSE cost should be used here. */
34468 /* ??? SSE vector cost should be used here. */
34481 /* ??? Assume all of these vector manipulation patterns are
34482 recognizable. In which case they all pretty much have the
34483 same cost. */
34489 }
34490 }
34492 #if TARGET_MACHO
34496 /* Given a symbol name and its associated stub, write out the
34497 definition of the stub. */
34499 void
34501 {
34506 /* For 64-bit we shouldn't get here. */
34509 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34526 else
34533 {
34535 }
34537 {
34538 /* PIC stub. */
34539 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34545 }
34546 else
34549 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34550 it needs no stub-binding-helper. */
34557 {
34560 }
34561 else
34566 /* N.B. Keep the correspondence of these
34567 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34568 old-pic/new-pic/non-pic stubs; altering this will break
34569 compatibility with existing dylibs. */
34571 {
34572 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34574 }
34575 else
34576 /* 16-byte -mdynamic-no-pic stub. */
34582 }
34585 /* Order the registers for register allocator. */
34587 void
34589 {
34593 /* First allocate the local general purpose registers. */
34598 /* Global general purpose registers. */
34603 /* x87 registers come first in case we are doing FP math
34604 using them. */
34609 /* SSE registers. */
34615 /* x87 registers. */
34623 /* Initialize the rest of array as we do not allocate some registers
34624 at all. */
34627 }
34629 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34630 in struct attribute_spec handler. */
34631 static tree
34633 tree args,
34636 {
34641 {
34643 name);
34646 }
34648 {
34650 name);
34653 }
34655 {
34656 tree cst;
34660 {
34663 name);
34665 }
34668 {
34671 name);
34673 }
34676 }
34679 }
34681 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34682 struct attribute_spec.handler. */
34683 static tree
34685 tree args ATTRIBUTE_UNUSED,
34687 {
34692 {
34694 name);
34697 }
34699 /* Can combine regparm with all attributes but fastcall. */
34701 {
34703 {
34705 }
34708 }
34710 {
34712 {
34714 }
34717 }
34720 }
34722 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34723 struct attribute_spec.handler. */
34724 static tree
34726 tree args ATTRIBUTE_UNUSED,
34728 {
34731 {
34734 }
34735 else
34739 {
34741 name);
34743 }
34749 {
34751 name);
34753 }
34756 }
34758 static tree
34760 tree args ATTRIBUTE_UNUSED,
34762 {
34764 {
34766 name);
34768 }
34770 }
34772 static bool
34774 {
34778 }
34780 /* Returns an expression indicating where the this parameter is
34781 located on entry to the FUNCTION. */
34783 static rtx
34785 {
34791 {
34796 else
34799 }
34804 {
34811 {
34816 }
34817 else
34818 {
34821 {
34827 }
34828 }
34830 }
34834 }
34836 /* Determine whether x86_output_mi_thunk can succeed. */
34838 static bool
34840 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34842 {
34843 /* 64-bit can handle anything. */
34847 /* For 32-bit, everything's fine if we have one free register. */
34851 /* Need a free register for vcall_offset. */
34855 /* Need a free register for GOT references. */
34859 /* Otherwise ok. */
34861 }
34863 /* Output the assembler code for a thunk function. THUNK_DECL is the
34864 declaration for the thunk function itself, FUNCTION is the decl for
34865 the target function. DELTA is an immediate constant offset to be
34866 added to THIS. If VCALL_OFFSET is nonzero, the word at
34867 *(*this + vcall_offset) should be added to THIS. */
34869 static void
34873 {
34880 else
34881 {
34887 else
34889 }
34893 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34894 pull it in now and let DELTA benefit. */
34898 {
34899 /* Put the this parameter into %eax. */
34902 }
34903 else
34906 /* Adjust the this parameter by a fixed constant. */
34908 {
34913 {
34915 {
34919 }
34920 }
34923 }
34925 /* Adjust the this parameter by a value stored in the vtable. */
34927 {
34937 /* Adjust the this parameter. */
34941 {
34945 }
34952 vcall_mem));
34953 else
34955 }
34957 /* If necessary, drop THIS back to its stack slot. */
34963 {
34966 ;
34967 else
34968 {
34972 }
34973 }
34974 else
34975 {
34977 ;
34978 #if TARGET_MACHO
34980 {
34983 }
34985 else
34986 {
34993 }
34994 }
34996 /* Our sibling call patterns do not allow memories, because we have no
34997 predicate that can distinguish between frame and non-frame memory.
34998 For our purposes here, we can get away with (ab)using a jump pattern,
34999 because we're going to do no optimization. */
35002 else
35003 {
35009 {
35015 }
35021 }
35024 /* Emit just enough of rest_of_compilation to get the insns emitted.
35025 Note that use_thunk calls assemble_start_function et al. */
35031 }
35033 static void
35035 {
35037 #if TARGET_MACHO
35039 #endif
35046 }
35048 int
35050 {
35062 }
35064 /* Output assembler code to FILE to increment profiler label # LABELNO
35065 for profiling a function entry. */
35066 void
35068 {
35073 {
35074 #ifndef NO_PROFILE_COUNTERS
35076 #endif
35080 else
35082 }
35084 {
35085 #ifndef NO_PROFILE_COUNTERS
35088 #endif
35090 }
35091 else
35092 {
35093 #ifndef NO_PROFILE_COUNTERS
35096 #endif
35098 }
35099 }
35101 /* We don't have exact information about the insn sizes, but we may assume
35102 quite safely that we are informed about all 1 byte insns and memory
35103 address sizes. This is enough to eliminate unnecessary padding in
35104 99% of cases. */
35106 static int
35108 {
35114 /* Discard alignments we've emit and jump instructions. */
35121 /* Important case - calls are always 5 bytes.
35122 It is common to have many calls in the row. */
35131 /* For normal instructions we rely on get_attr_length being exact,
35132 with a few exceptions. */
35134 {
35138 {
35148 /* Otherwise trust get_attr_length. */
35150 }
35155 }
35158 else
35160 }
35162 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35164 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35165 window. */
35167 static void
35169 {
35174 /* Look for all minimal intervals of instructions containing 4 jumps.
35175 The intervals are bounded by START and INSN. NBYTES is the total
35176 size of instructions in the interval including INSN and not including
35177 START. When the NBYTES is smaller than 16 bytes, it is possible
35178 that the end of START and INSN ends up in the same 16byte page.
35180 The smallest offset in the page INSN can start is the case where START
35181 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35182 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35183 */
35185 {
35189 {
35195 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35196 already in the current 16 byte page, because otherwise
35197 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35198 bytes to reach 16 byte boundary. */
35206 {
35208 {
35215 else
35218 }
35219 }
35221 }
35232 njumps++;
35233 else
35237 {
35244 else
35247 }
35254 {
35261 }
35262 }
35263 }
35264 #endif
35266 /* AMD Athlon works faster
35267 when RET is not destination of conditional jump or directly preceded
35268 by other jump instruction. We avoid the penalty by inserting NOP just
35269 before the RET instructions in such cases. */
35270 static void
35272 {
35273 edge e;
35274 edge_iterator ei;
35277 {
35280 rtx prev;
35290 {
35291 edge e;
35292 edge_iterator ei;
35298 }
35300 {
35306 /* Empty functions get branch mispredict even when
35307 the jump destination is not visible to us. */
35310 }
35312 {
35315 }
35316 }
35317 }
35319 /* Count the minimum number of instructions in BB. Return 4 if the
35320 number of instructions >= 4. */
35322 static int
35324 {
35325 rtx insn;
35328 /* Count number of instructions in this block. Return 4 if the number
35329 of instructions >= 4. */
35331 {
35332 /* Only happen in exit blocks. */
35340 {
35341 insn_count++;
35344 }
35345 }
35348 }
35351 /* Count the minimum number of instructions in code path in BB.
35352 Return 4 if the number of instructions >= 4. */
35354 static int
35356 {
35357 edge e;
35358 edge_iterator ei;
35361 /* Only bother counting instructions along paths with no
35362 more than 2 basic blocks between entry and exit. Given
35363 that BB has an edge to exit, determine if a predecessor
35364 of BB has an edge from entry. If so, compute the number
35365 of instructions in the predecessor block. If there
35366 happen to be multiple such blocks, compute the minimum. */
35369 {
35370 edge prev_e;
35371 edge_iterator prev_ei;
35374 {
35377 }
35379 {
35381 {
35386 }
35387 }
35388 }
35394 }
35396 /* Pad short function to 4 instructions. */
35398 static void
35400 {
35401 edge e;
35402 edge_iterator ei;
35405 {
35408 {
35411 /* Pad short function. */
35413 {
35416 /* Find epilogue. */
35425 /* Two NOPs count as one instruction. */
35428 }
35429 }
35430 }
35431 }
35433 /* Implement machine specific optimizations. We implement padding of returns
35434 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35435 static void
35437 {
35438 /* We are freeing block_for_insn in the toplev to keep compatibility
35439 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35443 {
35448 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35451 #endif
35452 }
35453 }
35455 /* Return nonzero when QImode register that must be represented via REX prefix
35456 is used. */
35457 bool
35459 {
35467 }
35469 /* Return nonzero when P points to register encoded via REX prefix.
35470 Called via for_each_rtx. */
35471 static int
35473 {
35479 }
35481 /* Return true when INSN mentions register that must be encoded using REX
35482 prefix. */
35483 bool
35485 {
35488 }
35490 /* If profitable, negate (without causing overflow) integer constant
35491 of mode MODE at location LOC. Return true in this case. */
35492 bool
35494 {
35495 HOST_WIDE_INT val;
35501 {
35503 /* DImode x86_64 constants must fit in 32 bits. */
35516 }
35518 /* Avoid overflows. */
35524 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35525 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35528 {
35531 }
35534 }
35536 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35537 optabs would emit if we didn't have TFmode patterns. */
35539 void
35541 {
35575 }
35576 \f
35577 /* AVX2 does support 32-byte integer vector operations,
35578 thus the longest vector we are faced with is V32QImode. */
35579 #define MAX_VECT_LEN 32
35581 struct expand_vec_perm_d
35582 {
35589 };
35595 /* Get a vector mode of the same size as the original but with elements
35596 twice as wide. This is only guaranteed to apply to integral vectors. */
35600 {
35601 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35606 }
35608 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35609 with all elements equal to VAR. Return true if successful. */
35611 static bool
35614 {
35618 {
35623 /* FALLTHRU */
35633 {
35636 /* First attempt to recognize VAL as-is. */
35640 {
35641 rtx seq;
35642 /* If that fails, force VAL into a register. */
35653 }
35654 }
35661 {
35662 rtx x;
35669 }
35679 {
35683 permute:
35691 /* Extend to SImode using a paradoxical SUBREG. */
35695 /* Insert the SImode value as low element of a V4SImode vector. */
35703 }
35711 widen:
35712 /* Replicate the value once into the next wider mode and recurse. */
35713 {
35715 rtx x;
35731 }
35735 {
35744 }
35749 }
35750 }
35752 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35753 whose ONE_VAR element is VAR, and other elements are zero. Return true
35754 if successful. */
35756 static bool
35759 {
35761 rtx new_target;
35766 {
35768 /* For SSE4.1, we normally use vector set. But if the second
35769 element is zero and inter-unit moves are OK, we use movq
35770 instead. */
35771 use_vector_set = (TARGET_64BIT
35772 && TARGET_SSE4_1
35773 && !(TARGET_INTER_UNIT_MOVES
35795 /* Use ix86_expand_vector_set in 64bit mode only. */
35800 }
35803 {
35808 }
35811 {
35816 /* FALLTHRU */
35831 else
35838 {
35839 /* We need to shuffle the value to the correct position, so
35840 create a new pseudo to store the intermediate result. */
35842 /* With SSE2, we can use the integer shuffle insns. */
35844 {
35846 const1_rtx,
35853 }
35855 /* Otherwise convert the intermediate result to V4SFmode and
35856 use the SSE1 shuffle instructions. */
35858 {
35861 }
35862 else
35866 const1_rtx,
35875 }
35890 widen:
35894 /* Zero extend the variable element to SImode and recurse. */
35907 }
35908 }
35910 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35911 consisting of the values in VALS. It is known that all elements
35912 except ONE_VAR are constants. Return true if successful. */
35914 static bool
35917 {
35927 {
35932 /* For the two element vectors, it's just as easy to use
35933 the general case. */
35937 /* Use ix86_expand_vector_set in 64bit mode only. */
35959 widen:
35960 /* There's no way to set one QImode entry easily. Combine
35961 the variable value with its adjacent constant value, and
35962 promote to an HImode set. */
35965 {
35970 }
35971 else
35972 {
35975 }
35989 }
35994 }
35996 /* A subroutine of ix86_expand_vector_init_general. Use vector
35997 concatenate to handle the most general case: all values variable,
35998 and none identical. */
36000 static void
36003 {
36006 rtvec v;
36010 {
36013 {
36046 }
36059 {
36074 }
36079 {
36090 }
36093 half:
36094 /* FIXME: We process inputs backward to help RA. PR 36222. */
36098 {
36103 }
36107 {
36110 {
36114 }
36117 }
36118 else
36124 }
36125 }
36127 /* A subroutine of ix86_expand_vector_init_general. Use vector
36128 interleave to handle the most general case: all values variable,
36129 and none identical. */
36131 static void
36134 {
36143 {
36164 }
36167 {
36168 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36172 /* Insert the SImode value as low element of V4SImode vector. */
36176 op0),
36178 const1_rtx);
36181 /* Cast the V4SImode vector back to a vector in orignal mode. */
36185 /* Load even elements into the second positon. */
36189 const1_rtx));
36191 /* Cast vector to FIRST_IMODE vector. */
36194 }
36196 /* Interleave low FIRST_IMODE vectors. */
36198 {
36202 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36205 }
36207 /* Interleave low SECOND_IMODE vectors. */
36209 {
36212 {
36217 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36218 vector. */
36221 }
36224 /* FALLTHRU */
36231 /* Cast the SECOND_IMODE vector back to a vector on original
36232 mode. */
36239 }
36240 }
36242 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36243 all values variable, and none identical. */
36245 static void
36248 {
36254 {
36259 /* FALLTHRU */
36283 half:
36300 /* FALLTHRU */
36306 /* Don't use ix86_expand_vector_init_interleave if we can't
36307 move from GPR to SSE register directly. */
36323 }
36325 {
36337 {
36341 {
36347 else
36348 {
36353 }
36354 }
36357 }
36362 {
36368 }
36370 {
36376 }
36377 else
36379 }
36380 }
36382 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36383 instructions unless MMX_OK is true. */
36385 void
36387 {
36394 rtx x;
36397 {
36407 }
36409 /* Constants are best loaded from the constant pool. */
36411 {
36414 }
36416 /* If all values are identical, broadcast the value. */
36422 /* Values where only one field is non-constant are best loaded from
36423 the pool and overwritten via move later. */
36425 {
36429 one_var))
36434 }
36437 }
36439 void
36441 {
36446 rtx tmp;
36448 = {
36455 };
36457 = {
36464 };
36468 {
36472 {
36477 else
36481 }
36493 else
36499 {
36502 /* For the two element vectors, we implement a VEC_CONCAT with
36503 the extraction of the other element. */
36510 else
36515 }
36524 {
36530 /* tmp = target = A B C D */
36532 /* target = A A B B */
36534 /* target = X A B B */
36536 /* target = A X C D */
36543 /* tmp = target = A B C D */
36545 /* tmp = X B C D */
36547 /* target = A B X D */
36554 /* tmp = target = A B C D */
36556 /* tmp = X B C D */
36558 /* target = A B X D */
36566 }
36574 /* Element 0 handled by vec_merge below. */
36576 {
36579 }
36582 {
36583 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36584 store into element 0, then shuffle them back. */
36601 }
36602 else
36603 {
36604 /* For SSE1, we have to reuse the V4SF code. */
36607 }
36660 half:
36661 /* Compute offset. */
36667 /* Extract the half. */
36671 /* Put val in tmp at elt. */
36674 /* Put it back. */
36680 }
36683 {
36687 }
36688 else
36689 {
36698 }
36699 }
36701 void
36703 {
36707 rtx tmp;
36710 {
36715 /* FALLTHRU */
36728 {
36748 }
36760 {
36762 {
36782 }
36786 }
36787 else
36788 {
36789 /* For SSE1, we have to reuse the V4SF code. */
36793 }
36809 {
36813 else
36817 }
36822 {
36826 else
36830 }
36835 {
36839 else
36843 }
36848 {
36852 else
36856 }
36861 {
36865 else
36869 }
36874 {
36878 else
36882 }
36886 /* ??? Could extract the appropriate HImode element and shift. */
36889 }
36892 {
36896 /* Let the rtl optimizers know about the zero extension performed. */
36898 {
36901 }
36904 }
36905 else
36906 {
36913 }
36914 }
36916 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36917 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36918 The upper bits of DEST are undefined, though they shouldn't cause
36919 exceptions (some bits from src or all zeros are ok). */
36921 static void
36923 {
36924 rtx tem;
36926 {
36930 else
36948 else
36955 else
36966 const1_rtx);
36967 else
36974 }
36976 }
36978 /* Expand a vector reduction. FN is the binary pattern to reduce;
36979 DEST is the destination; IN is the input vector. */
36981 void
36983 {
36988 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36992 {
36995 }
37000 {
37005 else
37009 }
37010 }
37011 \f
37012 /* Target hook for scalar_mode_supported_p. */
37013 static bool
37015 {
37020 else
37022 }
37024 /* Implements target hook vector_mode_supported_p. */
37025 static bool
37027 {
37039 }
37041 /* Target hook for c_mode_for_suffix. */
37042 static enum machine_mode
37044 {
37051 }
37053 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37055 We do this in the new i386 backend to maintain source compatibility
37056 with the old cc0-based compiler. */
37058 static tree
37060 tree inputs ATTRIBUTE_UNUSED,
37061 tree clobbers)
37062 {
37064 clobbers);
37066 clobbers);
37068 }
37070 /* Implements target vector targetm.asm.encode_section_info. */
37072 static void ATTRIBUTE_UNUSED
37074 {
37081 }
37083 /* Worker function for REVERSE_CONDITION. */
37085 enum rtx_code
37087 {
37091 }
37093 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37094 to OPERANDS[0]. */
37098 {
37100 {
37103 {
37107 }
37111 }
37113 {
37117 else
37118 {
37119 /* There is no non-popping store to memory for XFmode.
37120 So if we need one, follow the store with a load. */
37123 else
37125 }
37126 }
37127 else
37129 }
37131 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37132 FP status register is set. */
37134 void
37136 {
37138 rtx temp;
37143 {
37148 }
37149 else
37150 {
37155 }
37159 pc_rtx);
37164 }
37166 /* Output code to perform a log1p XFmode calculation. */
37169 {
37175 rtx test;
37181 XFmode));
37195 }
37197 /* Emit code for round calculation. */
37199 {
37206 rtx insn;
37211 {
37223 }
37226 {
37247 }
37255 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37257 /* scratch = fxam(op1) */
37260 UNSPEC_FXAM)));
37261 /* e1 = fabs(op1) */
37264 /* e2 = e1 + 0.5 */
37269 /* res = floor(e2) */
37271 {
37276 }
37277 else
37281 {
37284 {
37291 UNSPEC_TRUNC_NOOP)));
37292 }
37308 }
37310 /* flags = signbit(a) */
37313 /* if (flags) then res = -res */
37317 pc_rtx);
37328 }
37330 /* Output code to perform a Newton-Rhapson approximation of a single precision
37331 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37334 {
37342 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37346 /* x0 = rcp(b) estimate */
37349 UNSPEC_RCP)));
37350 /* e0 = x0 * b */
37354 /* e0 = x0 * e0 */
37358 /* e1 = x0 + x0 */
37362 /* x1 = e1 - e0 */
37366 /* res = a * x1 */
37369 }
37371 /* Output code to perform a Newton-Rhapson approximation of a
37372 single precision floating point [reciprocal] square root. */
37376 {
37378 REAL_VALUE_TYPE r;
37393 {
37396 }
37398 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37399 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37403 /* x0 = rsqrt(a) estimate */
37406 UNSPEC_RSQRT)));
37408 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37410 {
37422 }
37424 /* e0 = x0 * a */
37427 /* e1 = e0 * x0 */
37431 /* e2 = e1 - 3. */
37438 /* e3 = -.5 * x0 */
37441 else
37442 /* e3 = -.5 * e0 */
37445 /* ret = e2 * e3 */
37448 }
37450 #ifdef TARGET_SOLARIS
37451 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37453 static void
37455 tree decl)
37456 {
37457 /* With Binutils 2.15, the "@unwind" marker must be specified on
37458 every occurrence of the ".eh_frame" section, not just the first
37459 one. */
37462 {
37466 }
37468 #ifndef USE_GAS
37470 {
37473 }
37474 #endif
37477 }
37480 /* Return the mangling of TYPE if it is an extended fundamental type. */
37484 {
37492 {
37494 /* __float128 is "g". */
37497 /* "long double" or __float80 is "e". */
37501 }
37502 }
37504 /* For 32-bit code we can save PIC register setup by using
37505 __stack_chk_fail_local hidden function instead of calling
37506 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37507 register, so it is better to call __stack_chk_fail directly. */
37509 static tree ATTRIBUTE_UNUSED
37511 {
37512 return TARGET_64BIT
37515 }
37517 /* Select a format to encode pointers in exception handling data. CODE
37518 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37519 true if the symbol may be affected by dynamic relocations.
37521 ??? All x86 object file formats are capable of representing this.
37522 After all, the relocation needed is the same as for the call insn.
37523 Whether or not a particular assembler allows us to enter such, I
37524 guess we'll have to see. */
37525 int
37527 {
37529 {
37536 }
37541 }
37542 \f
37543 /* Expand copysign from SIGN to the positive value ABS_VALUE
37544 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37545 the sign-bit. */
37546 static void
37548 {
37552 {
37559 else
37564 {
37565 /* We need to generate a scalar mode mask in this case. */
37570 }
37571 }
37572 else
37578 }
37580 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37581 mask for masking out the sign-bit is stored in *SMASK, if that is
37582 non-null. */
37583 static rtx
37585 {
37594 else
37598 {
37599 /* We need to generate a scalar mode mask in this case. */
37604 }
37612 }
37614 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37615 swapping the operands if SWAP_OPERANDS is true. The expanded
37616 code is a forward jump to a newly created label in case the
37617 comparison is true. The generated label rtx is returned. */
37618 static rtx
37621 {
37625 {
37629 }
37642 }
37644 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37645 using comparison code CODE. Operands are swapped for the comparison if
37646 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37647 static rtx
37650 {
37656 {
37660 }
37667 }
37669 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37670 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37671 static rtx
37673 {
37674 REAL_VALUE_TYPE TWO52r;
37675 rtx TWO52;
37682 }
37684 /* Expand SSE sequence for computing lround from OP1 storing
37685 into OP0. */
37686 void
37688 {
37689 /* C code for the stuff we're doing below:
37690 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37691 return (long)tmp;
37692 */
37696 rtx adj;
37698 /* load nextafter (0.5, 0.0) */
37703 /* adj = copysign (0.5, op1) */
37707 /* adj = op1 + adj */
37710 /* op0 = (imode)adj */
37712 }
37714 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37715 into OPERAND0. */
37716 void
37718 {
37719 /* C code for the stuff we're doing below (for do_floor):
37720 xi = (long)op1;
37721 xi -= (double)xi > op1 ? 1 : 0;
37722 return xi;
37723 */
37728 /* reg = (long)op1 */
37732 /* freg = (double)reg */
37736 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37747 }
37749 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37750 result in OPERAND0. */
37751 void
37753 {
37754 /* C code for the stuff we're doing below:
37755 xa = fabs (operand1);
37756 if (!isless (xa, 2**52))
37757 return operand1;
37758 xa = xa + 2**52 - 2**52;
37759 return copysign (xa, operand1);
37760 */
37767 /* xa = abs (operand1) */
37770 /* if (!isless (xa, TWO52)) goto label; */
37783 }
37785 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37786 into OPERAND0. */
37787 void
37789 {
37790 /* C code for the stuff we expand below.
37791 double xa = fabs (x), x2;
37792 if (!isless (xa, TWO52))
37793 return x;
37794 xa = xa + TWO52 - TWO52;
37795 x2 = copysign (xa, x);
37796 Compensate. Floor:
37797 if (x2 > x)
37798 x2 -= 1;
37799 Compensate. Ceil:
37800 if (x2 < x)
37801 x2 -= -1;
37802 return x2;
37803 */
37809 /* Temporary for holding the result, initialized to the input
37810 operand to ease control flow. */
37814 /* xa = abs (operand1) */
37817 /* if (!isless (xa, TWO52)) goto label; */
37820 /* xa = xa + TWO52 - TWO52; */
37824 /* xa = copysign (xa, operand1) */
37827 /* generate 1.0 or -1.0 */
37832 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37836 /* We always need to subtract here to preserve signed zero. */
37845 }
37847 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37848 into OPERAND0. */
37849 void
37851 {
37852 /* C code for the stuff we expand below.
37853 double xa = fabs (x), x2;
37854 if (!isless (xa, TWO52))
37855 return x;
37856 x2 = (double)(long)x;
37857 Compensate. Floor:
37858 if (x2 > x)
37859 x2 -= 1;
37860 Compensate. Ceil:
37861 if (x2 < x)
37862 x2 += 1;
37863 if (HONOR_SIGNED_ZEROS (mode))
37864 return copysign (x2, x);
37865 return x2;
37866 */
37872 /* Temporary for holding the result, initialized to the input
37873 operand to ease control flow. */
37877 /* xa = abs (operand1) */
37880 /* if (!isless (xa, TWO52)) goto label; */
37883 /* xa = (double)(long)x */
37888 /* generate 1.0 */
37891 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37906 }
37908 /* Expand SSE sequence for computing round from OPERAND1 storing
37909 into OPERAND0. Sequence that works without relying on DImode truncation
37910 via cvttsd2siq that is only available on 64bit targets. */
37911 void
37913 {
37914 /* C code for the stuff we expand below.
37915 double xa = fabs (x), xa2, x2;
37916 if (!isless (xa, TWO52))
37917 return x;
37918 Using the absolute value and copying back sign makes
37919 -0.0 -> -0.0 correct.
37920 xa2 = xa + TWO52 - TWO52;
37921 Compensate.
37922 dxa = xa2 - xa;
37923 if (dxa <= -0.5)
37924 xa2 += 1;
37925 else if (dxa > 0.5)
37926 xa2 -= 1;
37927 x2 = copysign (xa2, x);
37928 return x2;
37929 */
37935 /* Temporary for holding the result, initialized to the input
37936 operand to ease control flow. */
37940 /* xa = abs (operand1) */
37943 /* if (!isless (xa, TWO52)) goto label; */
37946 /* xa2 = xa + TWO52 - TWO52; */
37950 /* dxa = xa2 - xa; */
37953 /* generate 0.5, 1.0 and -0.5 */
37959 /* Compensate. */
37961 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37966 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37972 /* res = copysign (xa2, operand1) */
37979 }
37981 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37982 into OPERAND0. */
37983 void
37985 {
37986 /* C code for SSE variant we expand below.
37987 double xa = fabs (x), x2;
37988 if (!isless (xa, TWO52))
37989 return x;
37990 x2 = (double)(long)x;
37991 if (HONOR_SIGNED_ZEROS (mode))
37992 return copysign (x2, x);
37993 return x2;
37994 */
38000 /* Temporary for holding the result, initialized to the input
38001 operand to ease control flow. */
38005 /* xa = abs (operand1) */
38008 /* if (!isless (xa, TWO52)) goto label; */
38011 /* x = (double)(long)x */
38023 }
38025 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38026 into OPERAND0. */
38027 void
38029 {
38033 /* C code for SSE variant we expand below.
38034 double xa = fabs (x), x2;
38035 if (!isless (xa, TWO52))
38036 return x;
38037 xa2 = xa + TWO52 - TWO52;
38038 Compensate:
38039 if (xa2 > xa)
38040 xa2 -= 1.0;
38041 x2 = copysign (xa2, x);
38042 return x2;
38043 */
38047 /* Temporary for holding the result, initialized to the input
38048 operand to ease control flow. */
38052 /* xa = abs (operand1) */
38055 /* if (!isless (xa, TWO52)) goto label; */
38058 /* res = xa + TWO52 - TWO52; */
38063 /* generate 1.0 */
38066 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38074 /* res = copysign (res, operand1) */
38081 }
38083 /* Expand SSE sequence for computing round from OPERAND1 storing
38084 into OPERAND0. */
38085 void
38087 {
38088 /* C code for the stuff we're doing below:
38089 double xa = fabs (x);
38090 if (!isless (xa, TWO52))
38091 return x;
38092 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38093 return copysign (xa, x);
38094 */
38100 /* Temporary for holding the result, initialized to the input
38101 operand to ease control flow. */
38109 /* load nextafter (0.5, 0.0) */
38114 /* xa = xa + 0.5 */
38118 /* xa = (double)(int64_t)xa */
38123 /* res = copysign (xa, operand1) */
38130 }
38132 /* Expand SSE sequence for computing round
38133 from OP1 storing into OP0 using sse4 round insn. */
38134 void
38136 {
38145 {
38156 }
38158 /* round (a) = trunc (a + copysign (0.5, a)) */
38160 /* load nextafter (0.5, 0.0) */
38166 /* e1 = copysign (0.5, op1) */
38170 /* e2 = op1 + e1 */
38173 /* res = trunc (e2) */
38178 }
38179 \f
38181 /* Table of valid machine attributes. */
38183 {
38184 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38185 affects_type_identity } */
38186 /* Stdcall attribute says callee is responsible for popping arguments
38187 if they are not variable. */
38190 /* Fastcall attribute says callee is responsible for popping arguments
38191 if they are not variable. */
38194 /* Thiscall attribute says callee is responsible for popping arguments
38195 if they are not variable. */
38198 /* Cdecl attribute says the callee is a normal C declaration */
38201 /* Regparm attribute specifies how many integer arguments are to be
38202 passed in registers. */
38205 /* Sseregparm attribute says we are using x86_64 calling conventions
38206 for FP arguments. */
38209 /* The transactional memory builtins are implicitly regparm or fastcall
38210 depending on the ABI. Override the generic do-nothing attribute that
38211 these builtins were declared with. */
38214 /* force_align_arg_pointer says this function realigns the stack at entry. */
38217 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38222 #endif
38227 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38228 SUBTARGET_ATTRIBUTE_TABLE,
38229 #endif
38230 /* ms_abi and sysv_abi calling convention function attributes. */
38237 /* End element. */
38239 };
38241 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38242 static int
38244 tree vectype,
38246 {
38250 {
38295 }
38296 }
38298 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38299 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38300 insn every time. */
38304 /* Initialize vselect_insn. */
38306 static void
38308 {
38310 rtx x;
38321 }
38323 /* Construct (set target (vec_select op0 (parallel perm))) and
38324 return true if that's a valid instruction in the active ISA. */
38326 static bool
38329 {
38355 }
38357 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38359 static bool
38363 {
38365 rtx x;
38380 }
38382 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38383 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38385 static bool
38387 {
38396 ;
38398 ;
38400 ;
38401 else
38404 /* This is a blend, not a permute. Elements must stay in their
38405 respective lanes. */
38407 {
38411 }
38416 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38417 decision should be extracted elsewhere, so that we only try that
38418 sequence once all budget==3 options have been tried. */
38425 {
38449 /* See if bytes move in pairs so we can use pblendw with
38450 an immediate argument, rather than pblendvb with a vector
38451 argument. */
38454 {
38455 use_pblendvb:
38459 finish_pblendvb:
38465 else
38468 }
38473 /* FALLTHRU */
38475 do_subreg:
38482 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38486 /* See if bytes move in quadruplets. If yes, vpblendd
38487 with immediate can be used. */
38492 {
38493 /* See if bytes move the same in both lanes. If yes,
38494 vpblendw with immediate can be used. */
38499 /* Use vpblendw. */
38504 }
38506 /* Use vpblendd. */
38513 /* See if words move in pairs. If yes, vpblendd can be used. */
38518 {
38519 /* See if words move the same in both lanes. If not,
38520 vpblendvb must be used. */
38523 {
38524 /* Use vpblendvb. */
38534 }
38536 /* Use vpblendw. */
38540 }
38542 /* Use vpblendd. */
38549 /* Use vpblendd. */
38557 }
38559 /* This matches five different patterns with the different modes. */
38565 }
38567 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38568 in terms of the variable form of vpermilps.
38570 Note that we will have already failed the immediate input vpermilps,
38571 which requires that the high and low part shuffle be identical; the
38572 variable form doesn't require that. */
38574 static bool
38576 {
38583 /* We can only permute within the 128-bit lane. */
38585 {
38589 }
38595 {
38598 /* Within each 128-bit lane, the elements of op0 are numbered
38599 from 0 and the elements of op1 are numbered from 4. */
38606 }
38613 }
38615 /* Return true if permutation D can be performed as VMODE permutation
38616 instead. */
38618 static bool
38620 {
38635 else
38641 }
38643 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38644 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38646 static bool
38648 {
38657 {
38659 {
38662 {
38666 /* Use vperm2i128 insn. The pattern uses
38667 V4DImode instead of V2TImode. */
38676 }
38678 }
38679 }
38680 else
38681 {
38683 {
38686 }
38688 {
38692 /* V4DImode should be already handled through
38693 expand_vselect by vpermq instruction. */
38700 {
38701 /* First see if vpermq can be used for
38702 V8SImode/V16HImode/V32QImode. */
38704 {
38712 }
38714 /* Next see if vpermd can be used. */
38717 }
38718 /* Or if vpermps can be used. */
38723 {
38724 /* vpshufb only works intra lanes, it is not
38725 possible to shuffle bytes in between the lanes. */
38729 }
38730 }
38731 else
38733 }
38741 else
38742 {
38748 else
38752 {
38756 }
38757 }
38766 {
38773 else
38775 }
38776 else
38777 {
38780 }
38783 }
38785 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38786 in a single instruction. */
38788 static bool
38790 {
38794 /* Check plain VEC_SELECT first, because AVX has instructions that could
38795 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38796 input where SEL+CONCAT may not. */
38798 {
38804 {
38810 }
38813 {
38817 }
38819 {
38820 /* Use vpbroadcast{b,w,d}. */
38823 {
38842 /* For other modes prefer other shuffles this function creates. */
38844 }
38846 {
38850 }
38851 }
38856 /* There are plenty of patterns in sse.md that are written for
38857 SEL+CONCAT and are not replicated for a single op. Perhaps
38858 that should be changed, to avoid the nastiness here. */
38860 /* Recognize interleave style patterns, which means incrementing
38861 every other permutation operand. */
38863 {
38866 }
38871 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38873 {
38875 {
38880 }
38885 }
38886 }
38888 /* Finally, try the fully general two operand permute. */
38893 /* Recognize interleave style patterns with reversed operands. */
38895 {
38897 {
38901 else
38904 }
38909 }
38911 /* Try the SSE4.1 blend variable merge instructions. */
38915 /* Try one of the AVX vpermil variable permutations. */
38919 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38920 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38925 }
38927 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38928 in terms of a pair of pshuflw + pshufhw instructions. */
38930 static bool
38932 {
38940 /* The two permutations only operate in 64-bit lanes. */
38951 /* Emit the pshuflw. */
38958 /* Emit the pshufhw. */
38966 }
38968 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38969 the permutation using the SSSE3 palignr instruction. This succeeds
38970 when all of the elements in PERM fit within one vector and we merely
38971 need to shift them down so that a single vector permutation has a
38972 chance to succeed. */
38974 static bool
38976 {
38980 rtx shift;
38982 /* Even with AVX, palignr only operates on 128-bit vectors. */
38988 {
38994 }
38998 /* Given that we have SSSE3, we know we'll be able to implement the
38999 single operand permutation after the palignr with pshufb. */
39013 {
39018 }
39020 /* Test for the degenerate case where the alignment by itself
39021 produces the desired permutation. */
39029 }
39033 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39034 a two vector permutation into a single vector permutation by using
39035 an interleave operation to merge the vectors. */
39037 static bool
39039 {
39044 rtx seq;
39048 {
39051 }
39053 {
39056 /* For 32-byte modes allow even d->one_operand_p.
39057 The lack of cross-lane shuffling in some instructions
39058 might prevent a single insn shuffle. */
39061 /* If expand_vec_perm_interleave3 can expand this into
39062 a 3 insn sequence, give up and let it be expanded as
39063 3 insn sequence. While that is one insn longer,
39064 it doesn't need a memory operand and in the common
39065 case that both interleave low and high permutations
39066 with the same operands are adjacent needs 4 insns
39067 for both after CSE. */
39070 }
39071 else
39074 /* Examine from whence the elements come. */
39083 {
39086 /* Split the two input vectors into 4 halves. */
39092 /* If the elements from the low halves use interleave low, and similarly
39093 for interleave high. If the elements are from mis-matched halves, we
39094 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39096 {
39097 /* punpckl* */
39099 {
39104 }
39107 }
39109 {
39110 /* punpckh* */
39112 {
39117 }
39120 }
39122 {
39123 /* shufps */
39125 {
39130 }
39132 {
39133 /* shufpd */
39138 }
39139 }
39141 {
39142 /* shufps */
39144 {
39149 }
39151 {
39152 /* shufpd */
39157 }
39158 }
39159 else
39161 }
39162 else
39163 {
39168 /* Split the two input vectors into 8 quarters. */
39174 {
39177 }
39180 {
39184 }
39186 {
39189 }
39192 {
39194 {
39195 /* Attempt to increase the likelihood that dfinal
39196 shuffle will be intra-lane. */
39200 }
39202 /* vperm2f128 or vperm2i128. */
39204 {
39209 }
39214 {
39218 {
39221 }
39222 }
39223 }
39228 {
39229 /* vpunpckl* */
39231 {
39240 }
39241 }
39244 {
39245 /* vpunpckh* */
39247 {
39256 }
39257 }
39258 else
39260 }
39262 /* Use the remapping array set up above to move the elements from their
39263 swizzled locations into their final destinations. */
39266 {
39269 /* If same_halves is true, both halves of the remapped vector are the
39270 same. Avoid cross-lane accesses if possible. */
39272 {
39275 }
39276 else
39278 }
39284 /* Test if the final remap can be done with a single insn. For V4SFmode or
39285 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39298 {
39302 }
39309 }
39311 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39312 a single vector cross-lane permutation into vpermq followed
39313 by any of the single insn permutations. */
39315 static bool
39317 {
39331 {
39334 }
39337 {
39342 }
39355 {
39362 }
39369 {
39374 ;
39377 else
39379 }
39388 }
39390 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39391 a vector permutation using two instructions, vperm2f128 resp.
39392 vperm2i128 followed by any single in-lane permutation. */
39394 static bool
39396 {
39410 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39411 immediate. For perm < 16 the second permutation uses
39412 d->op0 as first operand, for perm >= 16 it uses d->op1
39413 as first operand. The second operand is the result of
39414 vperm2[fi]128. */
39416 {
39417 /* Ignore permutations which do not move anything cross-lane. */
39419 {
39420 /* The second shuffle for e.g. V4DFmode has
39421 0123 and ABCD operands.
39422 Ignore AB23, as 23 is already in the second lane
39423 of the first operand. */
39425 /* And 01CD, as 01 is in the first lane of the first
39426 operand. */
39428 /* And 4567, as then the vperm2[fi]128 doesn't change
39429 anything on the original 4567 second operand. */
39431 }
39432 else
39433 {
39434 /* The second shuffle for e.g. V4DFmode has
39435 4567 and ABCD operands.
39436 Ignore AB67, as 67 is already in the second lane
39437 of the first operand. */
39439 /* And 45CD, as 45 is in the first lane of the first
39440 operand. */
39442 /* And 0123, as then the vperm2[fi]128 doesn't change
39443 anything on the original 0123 first operand. */
39445 }
39448 {
39454 else
39456 }
39459 {
39463 }
39464 else
39468 {
39472 /* Found a usable second shuffle. dfirst will be
39473 vperm2f128 on d->op0 and d->op1. */
39484 /* And dsecond is some single insn shuffle, taking
39485 d->op0 and result of vperm2f128 (if perm < 16) or
39486 d->op1 and result of vperm2f128 (otherwise). */
39495 }
39497 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39500 }
39503 }
39505 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39506 a two vector permutation using 2 intra-lane interleave insns
39507 and cross-lane shuffle for 32-byte vectors. */
39509 static bool
39511 {
39518 ;
39520 ;
39521 else
39536 {
39540 else
39546 else
39552 else
39558 else
39564 else
39570 else
39575 }
39579 }
39581 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39582 a single vector permutation using a single intra-lane vector
39583 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39584 the non-swapped and swapped vectors together. */
39586 static bool
39588 {
39591 rtx seq;
39596 || TARGET_AVX2
39605 {
39612 }
39647 }
39649 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39650 permutation using two vperm2f128, followed by a vshufpd insn blending
39651 the two vectors together. */
39653 static bool
39655 {
39698 }
39700 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39701 permutation with two pshufb insns and an ior. We should have already
39702 failed all two instruction sequences. */
39704 static bool
39706 {
39717 /* Generate two permutation masks. If the required element is within
39718 the given vector it is shuffled into the proper lane. If the required
39719 element is in the other vector, force a zero into the lane by setting
39720 bit 7 in the permutation mask. */
39723 {
39730 {
39733 }
39734 }
39754 }
39756 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39757 with two vpshufb insns, vpermq and vpor. We should have already failed
39758 all two or three instruction sequences. */
39760 static bool
39762 {
39777 /* Generate two permutation masks. If the required element is within
39778 the same lane, it is shuffled in. If the required element from the
39779 other lane, force a zero by setting bit 7 in the permutation mask.
39780 In the other mask the mask has non-negative elements if element
39781 is requested from the other lane, but also moved to the other lane,
39782 so that the result of vpshufb can have the two V2TImode halves
39783 swapped. */
39786 {
39791 {
39794 }
39795 }
39804 /* Swap the 128-byte lanes of h into hp. */
39808 const1_rtx));
39821 }
39823 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39824 and extract-odd permutations of two V32QImode and V16QImode operand
39825 with two vpshufb insns, vpor and vpermq. We should have already
39826 failed all two or three instruction sequences. */
39828 static bool
39830 {
39849 /* Generate two permutation masks. In the first permutation mask
39850 the first quarter will contain indexes for the first half
39851 of the op0, the second quarter will contain bit 7 set, third quarter
39852 will contain indexes for the second half of the op0 and the
39853 last quarter bit 7 set. In the second permutation mask
39854 the first quarter will contain bit 7 set, the second quarter
39855 indexes for the first half of the op1, the third quarter bit 7 set
39856 and last quarter indexes for the second half of the op1.
39857 I.e. the first mask e.g. for V32QImode extract even will be:
39858 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39859 (all values masked with 0xf except for -128) and second mask
39860 for extract even will be
39861 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39864 {
39870 {
39873 }
39874 }
39893 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39900 }
39902 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39903 and extract-odd permutations. */
39905 static bool
39907 {
39911 {
39916 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39920 /* Now an unpck[lh]pd will produce the result required. */
39923 else
39929 {
39936 /* Shuffle within the 128-bit lanes to produce:
39937 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39941 /* Shuffle the lanes around to produce:
39942 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39946 /* Shuffle within the 128-bit lanes to produce:
39947 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39950 /* Shuffle within the 128-bit lanes to produce:
39951 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39954 /* Shuffle the lanes around to produce:
39955 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39958 }
39965 /* These are always directly implementable by expand_vec_perm_1. */
39971 else
39972 {
39973 /* We need 2*log2(N)-1 operations to achieve odd/even
39974 with interleave. */
39983 else
39986 }
39992 else
39993 {
40005 else
40008 }
40017 {
40024 }
40029 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40033 /* Now an vpunpck[lh]qdq will produce the result required. */
40036 else
40043 {
40050 }
40055 /* Shuffle the lanes around into
40056 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40066 /* Swap the 2nd and 3rd position in each lane into
40067 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40073 /* Now an vpunpck[lh]qdq will produce
40074 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40079 else
40088 }
40091 }
40093 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40094 extract-even and extract-odd permutations. */
40096 static bool
40098 {
40110 }
40112 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40113 permutations. We assume that expand_vec_perm_1 has already failed. */
40115 static bool
40117 {
40125 {
40128 /* These are special-cased in sse.md so that we can optionally
40129 use the vbroadcast instruction. They expand to two insns
40130 if the input happens to be in a register. */
40137 /* These are always implementable using standard shuffle patterns. */
40142 /* These can be implemented via interleave. We save one insn by
40143 stopping once we have promoted to V4SImode and then use pshufd. */
40144 do
40145 {
40146 rtx dest;
40152 {
40156 }
40163 }
40176 /* For AVX2 broadcasts of the first element vpbroadcast* or
40177 vpermq should be used by expand_vec_perm_1. */
40183 }
40184 }
40186 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40187 broadcast permutations. */
40189 static bool
40191 {
40203 }
40205 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40206 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40207 all the shorter instruction sequences. */
40209 static bool
40211 {
40227 /* Generate 4 permutation masks. If the required element is within
40228 the same lane, it is shuffled in. If the required element from the
40229 other lane, force a zero by setting bit 7 in the permutation mask.
40230 In the other mask the mask has non-negative elements if element
40231 is requested from the other lane, but also moved to the other lane,
40232 so that the result of vpshufb can have the two V2TImode halves
40233 swapped. */
40236 {
40241 }
40247 {
40255 }
40258 {
40260 {
40263 }
40270 }
40272 /* Swap the 128-byte lanes of h[X]. */
40274 {
40280 const1_rtx));
40282 }
40285 {
40287 {
40290 }
40296 }
40299 {
40301 {
40305 }
40308 }
40314 }
40316 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40317 With all of the interface bits taken care of, perform the expansion
40318 in D and return true on success. */
40320 static bool
40322 {
40323 /* Try a single instruction expansion. */
40327 /* Try sequences of two instructions. */
40347 /* Try sequences of three instructions. */
40361 /* Try sequences of four instructions. */
40369 /* ??? Look for narrow permutations whose element orderings would
40370 allow the promotion to a wider mode. */
40372 /* ??? Look for sequences of interleave or a wider permute that place
40373 the data into the correct lanes for a half-vector shuffle like
40374 pshuf[lh]w or vpermilps. */
40376 /* ??? Look for sequences of interleave that produce the desired results.
40377 The combinatorics of punpck[lh] get pretty ugly... */
40382 /* Even longer sequences. */
40387 }
40389 /* If a permutation only uses one operand, make it clear. Returns true
40390 if the permutation references both operands. */
40392 static bool
40394 {
40402 {
40408 {
40411 }
40412 /* The elements of PERM do not suggest that only the first operand
40413 is used, but both operands are identical. Allow easier matching
40414 of the permutation by folding the permutation into the single
40415 input vector. */
40416 /* FALLTHRU */
40427 }
40430 }
40432 bool
40434 {
40439 rtx sel;
40456 {
40461 }
40468 /* If the selector says both arguments are needed, but the operands are the
40469 same, the above tried to expand with one_operand_p and flattened selector.
40470 If that didn't work, retry without one_operand_p; we succeeded with that
40471 during testing. */
40473 {
40477 }
40480 }
40482 /* Implement targetm.vectorize.vec_perm_const_ok. */
40484 static bool
40487 {
40496 /* Given sufficient ISA support we can just return true here
40497 for selected vector modes. */
40499 {
40500 /* All implementable with a single vpperm insn. */
40503 /* All implementable with 2 pshufb + 1 ior. */
40506 /* All implementable with shufpd or unpck[lh]pd. */
40509 }
40511 /* Extract the values from the vector CST into the permutation
40512 array in D. */
40515 {
40519 }
40521 /* For all elements from second vector, fold the elements to first. */
40526 /* Check whether the mask can be applied to the vector type. */
40529 /* Implementable with shufps or pshufd. */
40533 /* Otherwise we have to go through the motions and see if we can
40534 figure out how to generate the requested permutation. */
40545 }
40547 void
40549 {
40564 /* We'll either be able to implement the permutation directly... */
40568 /* ... or we use the special-case patterns. */
40570 }
40572 static void
40574 {
40589 {
40592 }
40594 /* Note that for AVX this isn't one instruction. */
40597 }
40600 /* Expand a vector operation CODE for a V*QImode in terms of the
40601 same operation on V*HImode. */
40603 void
40605 {
40617 {
40630 }
40634 {
40636 /* Unpack data such that we've got a source byte in each low byte of
40637 each word. We don't care what goes into the high byte of each word.
40638 Rather than trying to get zero in there, most convenient is to let
40639 it be a copy of the low byte. */
40644 /* FALLTHRU */
40656 /* FALLTHRU */
40666 }
40668 /* Perform the operation. */
40675 /* Merge the data back into the right place. */
40685 {
40686 /* For SSE2, we used an full interleave, so the desired
40687 results are in the even elements. */
40690 }
40691 else
40692 {
40693 /* For AVX, the interleave used above was not cross-lane. So the
40694 extraction is evens but with the second and third quarter swapped.
40695 Happily, that is even one insn shorter than even extraction. */
40698 }
40705 }
40707 void
40710 {
40713 rtx x;
40715 /* We only play even/odd games with vectors of SImode. */
40718 /* If we're looking for the odd results, shift those members down to
40719 the even slots. For some cpus this is faster than a PSHUFD. */
40721 {
40723 {
40727 }
40736 }
40739 {
40742 else
40744 }
40749 else
40750 {
40753 /* The easiest way to implement this without PMULDQ is to go through
40754 the motions as if we are performing a full 64-bit multiply. With
40755 the exception that we need to do less shuffling of the elements. */
40757 /* Compute the sign-extension, aka highparts, of the two operands. */
40763 /* Multiply LO(A) * HI(B), and vice-versa. */
40769 /* Multiply LO(A) * LO(B). */
40773 /* Combine and shift the highparts into place. */
40778 /* Combine high and low parts. */
40781 }
40783 }
40785 void
40788 {
40794 {
40799 {
40800 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40801 shuffle the elements once so that all elements are in the right
40802 place for immediate use: { A C B D }. */
40807 }
40808 else
40809 {
40810 /* Put the elements into place for the multiply. */
40814 }
40819 /* Shuffle the elements between the lanes. After this we
40820 have { A B E F | C D G H } for each operand. */
40830 /* Shuffle the elements within the lanes. After this we
40831 have { A A B B | C C D D } or { E E F F | G G H H }. */
40867 }
40868 }
40870 void
40872 {
40882 /* Move the results in element 2 down to element 1; we don't care
40883 what goes in elements 2 and 3. Then we can merge the parts
40884 back together with an interleave.
40886 Note that two other sequences were tried:
40887 (1) Use interleaves at the start instead of psrldq, which allows
40888 us to use a single shufps to merge things back at the end.
40889 (2) Use shufps here to combine the two vectors, then pshufd to
40890 put the elements in the correct order.
40891 In both cases the cost of the reformatting stall was too high
40892 and the overall sequence slower. */
40901 }
40903 void
40905 {
40910 {
40911 /* op1: A,B,C,D, op2: E,F,G,H */
40920 /* t1: B,A,D,C */
40927 /* t2: (B*E),(A*F),(D*G),(C*H) */
40930 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40933 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40936 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40938 }
40939 else
40940 {
40945 {
40948 }
40950 {
40953 }
40954 else
40958 /* Multiply low parts. */
40962 /* Shift input vectors right 32 bits so we can multiply high parts. */
40967 /* Multiply high parts by low parts. */
40973 /* Combine and shift the highparts back. */
40977 /* Combine high and low parts. */
40979 }
40983 }
40985 /* Expand an insert into a vector register through pinsr insn.
40986 Return true if successful. */
40988 bool
40990 {
40998 {
41001 }
41007 {
41012 {
41019 {
41051 }
41060 }
41064 }
41065 }
41066 \f
41067 /* This function returns the calling abi specific va_list type node.
41068 It returns the FNDECL specific va_list type. */
41070 static tree
41072 {
41079 else
41081 }
41083 /* Returns the canonical va_list type specified by TYPE. If there
41084 is no valid TYPE provided, it return NULL_TREE. */
41086 static tree
41088 {
41091 /* Resolve references and pointers to va_list type. */
41100 {
41105 {
41106 /* If va_list is an array type, the argument may have decayed
41107 to a pointer type, e.g. by being passed to another function.
41108 In that case, unwrap both types so that we can compare the
41109 underlying records. */
41112 {
41115 }
41116 }
41123 {
41124 /* If va_list is an array type, the argument may have decayed
41125 to a pointer type, e.g. by being passed to another function.
41126 In that case, unwrap both types so that we can compare the
41127 underlying records. */
41130 {
41133 }
41134 }
41141 {
41142 /* If va_list is an array type, the argument may have decayed
41143 to a pointer type, e.g. by being passed to another function.
41144 In that case, unwrap both types so that we can compare the
41145 underlying records. */
41148 {
41151 }
41152 }
41156 }
41158 }
41160 /* Iterate through the target-specific builtin types for va_list.
41161 IDX denotes the iterator, *PTREE is set to the result type of
41162 the va_list builtin, and *PNAME to its internal type.
41163 Returns zero if there is no element for this index, otherwise
41164 IDX should be increased upon the next call.
41165 Note, do not iterate a base builtin's name like __builtin_va_list.
41166 Used from c_common_nodes_and_builtins. */
41168 static int
41170 {
41172 {
41174 {
41187 }
41188 }
41191 }
41193 #undef TARGET_SCHED_DISPATCH
41194 #define TARGET_SCHED_DISPATCH has_dispatch
41195 #undef TARGET_SCHED_DISPATCH_DO
41196 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41197 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41198 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41199 #undef TARGET_SCHED_REORDER
41200 #define TARGET_SCHED_REORDER ix86_sched_reorder
41201 #undef TARGET_SCHED_ADJUST_PRIORITY
41202 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41203 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41204 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41206 /* The size of the dispatch window is the total number of bytes of
41207 object code allowed in a window. */
41208 #define DISPATCH_WINDOW_SIZE 16
41210 /* Number of dispatch windows considered for scheduling. */
41211 #define MAX_DISPATCH_WINDOWS 3
41213 /* Maximum number of instructions in a window. */
41214 #define MAX_INSN 4
41216 /* Maximum number of immediate operands in a window. */
41217 #define MAX_IMM 4
41219 /* Maximum number of immediate bits allowed in a window. */
41220 #define MAX_IMM_SIZE 128
41222 /* Maximum number of 32 bit immediates allowed in a window. */
41223 #define MAX_IMM_32 4
41225 /* Maximum number of 64 bit immediates allowed in a window. */
41226 #define MAX_IMM_64 2
41228 /* Maximum total of loads or prefetches allowed in a window. */
41229 #define MAX_LOAD 2
41231 /* Maximum total of stores allowed in a window. */
41232 #define MAX_STORE 1
41234 #undef BIG
41235 #define BIG 100
41238 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41241 disp_load,
41242 disp_store,
41243 disp_load_store,
41244 disp_prefetch,
41245 disp_imm,
41246 disp_imm_32,
41247 disp_imm_64,
41248 disp_branch,
41249 disp_cmp,
41250 disp_jcc,
41251 disp_last
41252 };
41254 /* Number of allowable groups in a dispatch window. It is an array
41255 indexed by dispatch_group enum. 100 is used as a big number,
41256 because the number of these kind of operations does not have any
41257 effect in dispatch window, but we need them for other reasons in
41258 the table. */
41261 };
41267 };
41269 /* Instruction path. */
41275 last_path
41276 };
41278 /* sched_insn_info defines a window to the instructions scheduled in
41279 the basic block. It contains a pointer to the insn_info table and
41280 the instruction scheduled.
41282 Windows are allocated for each basic block and are linked
41283 together. */
41285 rtx insn;
41292 /* Linked list of dispatch windows. This is a two way list of
41293 dispatch windows of a basic block. It contains information about
41294 the number of uops in the window and the total number of
41295 instructions and of bytes in the object code for this dispatch
41296 window. */
41314 /* Immediate valuse used in an insn. */
41316 {
41325 /* Get dispatch group of insn. */
41327 static enum dispatch_group
41329 {
41345 }
41347 /* Return true if insn is a compare instruction. */
41349 static bool
41351 {
41359 }
41361 /* Return true if a dispatch violation encountered. */
41363 static bool
41365 {
41369 }
41371 /* Return true if insn is a branch instruction. */
41373 static bool
41375 {
41377 }
41379 /* Return true if insn is a prefetch instruction. */
41381 static bool
41383 {
41385 }
41387 /* This function initializes a dispatch window and the list container holding a
41388 pointer to the window. */
41390 static void
41392 {
41398 else
41416 {
41422 }
41424 }
41426 /* This function allocates and initializes a dispatch window and the
41427 list container holding a pointer to the window. */
41431 {
41436 }
41438 /* This routine initializes the dispatch scheduling information. It
41439 initiates building dispatch scheduler tables and constructs the
41440 first dispatch window. */
41442 static void
41444 {
41445 /* Allocate a dispatch list and a window. */
41450 }
41452 /* This function returns true if a branch is detected. End of a basic block
41453 does not have to be a branch, but here we assume only branches end a
41454 window. */
41456 static bool
41458 {
41460 }
41462 /* This function is called when the end of a window processing is reached. */
41464 static void
41466 {
41469 {
41474 }
41476 }
41478 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41479 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41480 for 48 bytes of instructions. Note that these windows are not dispatch
41481 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41485 {
41487 {
41492 }
41498 }
41500 /* Increment the number of immediate operands of an instruction. */
41502 static int
41504 {
41509 {
41516 else
41527 {
41530 }
41535 }
41538 }
41540 /* Compute number of immediate operands of an instruction. */
41542 static void
41544 {
41547 }
41549 /* Return total size of immediate operands of an instruction along with number
41550 of corresponding immediate-operands. It initializes its parameters to zero
41551 befor calling FIND_CONSTANT.
41552 INSN is the input instruction. IMM is the total of immediates.
41553 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41554 bit immediates. */
41556 static int
41558 {
41566 }
41568 /* This function indicates if an operand of an instruction is an
41569 immediate. */
41571 static bool
41573 {
41582 }
41584 /* Return single or double path for instructions. */
41586 static enum insn_path
41588 {
41598 }
41600 /* Return insn dispatch group. */
41602 static enum dispatch_group
41604 {
41622 }
41624 /* Count number of GROUP restricted instructions in a dispatch
41625 window WINDOW_LIST. */
41627 static int
41629 {
41640 {
41659 }
41672 }
41674 /* This function returns true if insn satisfies dispatch rules on the
41675 last window scheduled. */
41677 static bool
41679 {
41687 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41688 instructions should be given the lowest priority in the
41689 scheduling process in Haifa scheduler to make sure they will be
41690 scheduled in the same dispatch window as the reference to them. */
41694 /* Check nonrestricted. */
41698 /* Get last dispatch window. */
41703 {
41708 /* Window 1 is full. Go for next window. */
41710 }
41717 /* See if it fits in the first window. */
41719 {
41720 /* The first widow should have only single and double path
41721 uops. */
41727 }
41729 }
41731 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41732 dispatch window WINDOW_LIST. */
41734 static void
41736 {
41754 /* Initialize window with new instruction. */
41775 {
41778 }
41779 }
41781 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41782 If the total bytes of instructions or the number of instructions in
41783 the window exceed allowable, it allocates a new window. */
41785 static void
41787 {
41810 /* Get the last dispatch window. */
41818 else
41821 /* If current window is full, get a new window.
41822 Window number zero is full, if MAX_INSN uops are scheduled in it.
41823 Window number one is full, if window zero's bytes plus window
41824 one's bytes is 32, or if the bytes of the new instruction added
41825 to the total makes it greater than 48, or it has already MAX_INSN
41826 instructions in it. */
41835 {
41838 }
41841 {
41845 {
41848 }
41849 }
41851 {
41856 {
41859 }
41862 }
41863 else
41867 {
41868 /* End of basic block is reached do end-basic-block process. */
41871 }
41872 }
41874 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41876 DEBUG_FUNCTION static void
41878 {
41884 else
41898 {
41901 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41907 }
41908 }
41910 /* Print to stdout a dispatch window. */
41912 DEBUG_FUNCTION void
41914 {
41916 }
41918 /* Print INSN dispatch information to FILE. */
41920 DEBUG_FUNCTION static void
41922 {
41945 }
41947 /* Print to STDERR the status of the ready list with respect to
41948 dispatch windows. */
41950 DEBUG_FUNCTION void
41952 {
41960 }
41962 /* This routine is the driver of the dispatch scheduler. */
41964 static void
41966 {
41971 }
41973 /* Return TRUE if Dispatch Scheduling is supported. */
41975 static bool
41977 {
41981 {
41997 }
42000 }
42002 /* Implementation of reassociation_width target hook used by
42003 reassoc phase to identify parallelism level in reassociated
42004 tree. Statements tree_code is passed in OPC. Arguments type
42005 is passed in MODE.
42007 Currently parallel reassociation is enabled for Atom
42008 processors only and we set reassociation width to be 2
42009 because Atom may issue up to 2 instructions per cycle.
42011 Return value should be fixed if parallel reassociation is
42012 enabled for other processors. */
42014 static int
42017 {
42026 }
42028 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42029 place emms and femms instructions. */
42031 static enum machine_mode
42033 {
42038 {
42051 else
42061 /* FALLTHRU */
42065 }
42066 }
42068 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42069 vectors. */
42071 static unsigned int
42073 {
42075 }
42077 \f
42079 /* Return class of registers which could be used for pseudo of MODE
42080 and of class RCLASS for spilling instead of memory. Return NO_REGS
42081 if it is not possible or non-profitable. */
42082 static reg_class_t
42084 {
42090 }
42092 /* Implement targetm.vectorize.init_cost. */
42096 {
42100 }
42102 /* Implement targetm.vectorize.add_stmt_cost. */
42104 static unsigned
42108 {
42113 {
42117 /* Statements in an inner loop relative to the loop being
42118 vectorized are weighted more heavily. The value here is
42119 arbitrary and could potentially be improved with analysis. */
42125 }
42128 }
42130 /* Implement targetm.vectorize.finish_cost. */
42132 static void
42135 {
42140 }
42142 /* Implement targetm.vectorize.destroy_cost_data. */
42144 static void
42146 {
42148 }
42150 /* Validate target specific memory model bits in VAL. */
42152 static unsigned HOST_WIDE_INT
42154 {
42161 {
42165 }
42168 {
42172 }
42174 {
42178 }
42180 }
42182 /* Initialize the GCC target structure. */
42183 #undef TARGET_RETURN_IN_MEMORY
42184 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42186 #undef TARGET_LEGITIMIZE_ADDRESS
42187 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42189 #undef TARGET_ATTRIBUTE_TABLE
42190 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42191 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42192 # undef TARGET_MERGE_DECL_ATTRIBUTES
42193 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42194 #endif
42196 #undef TARGET_COMP_TYPE_ATTRIBUTES
42197 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42199 #undef TARGET_INIT_BUILTINS
42200 #define TARGET_INIT_BUILTINS ix86_init_builtins
42201 #undef TARGET_BUILTIN_DECL
42202 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42203 #undef TARGET_EXPAND_BUILTIN
42204 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42206 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42207 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42208 ix86_builtin_vectorized_function
42210 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42211 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42213 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42214 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42216 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42217 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42219 #undef TARGET_BUILTIN_RECIPROCAL
42220 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42222 #undef TARGET_ASM_FUNCTION_EPILOGUE
42223 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42225 #undef TARGET_ENCODE_SECTION_INFO
42226 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42227 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42228 #else
42229 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42230 #endif
42232 #undef TARGET_ASM_OPEN_PAREN
42234 #undef TARGET_ASM_CLOSE_PAREN
42237 #undef TARGET_ASM_BYTE_OP
42238 #define TARGET_ASM_BYTE_OP ASM_BYTE
42240 #undef TARGET_ASM_ALIGNED_HI_OP
42241 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42242 #undef TARGET_ASM_ALIGNED_SI_OP
42243 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42244 #ifdef ASM_QUAD
42245 #undef TARGET_ASM_ALIGNED_DI_OP
42246 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42247 #endif
42249 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42250 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42252 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42253 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42255 #undef TARGET_ASM_UNALIGNED_HI_OP
42256 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42257 #undef TARGET_ASM_UNALIGNED_SI_OP
42258 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42259 #undef TARGET_ASM_UNALIGNED_DI_OP
42260 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42262 #undef TARGET_PRINT_OPERAND
42263 #define TARGET_PRINT_OPERAND ix86_print_operand
42264 #undef TARGET_PRINT_OPERAND_ADDRESS
42265 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42266 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42267 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42268 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42269 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42271 #undef TARGET_SCHED_INIT_GLOBAL
42272 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42273 #undef TARGET_SCHED_ADJUST_COST
42274 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42275 #undef TARGET_SCHED_ISSUE_RATE
42276 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42277 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42278 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42279 ia32_multipass_dfa_lookahead
42281 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42282 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42284 #undef TARGET_MEMMODEL_CHECK
42285 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42287 #ifdef HAVE_AS_TLS
42288 #undef TARGET_HAVE_TLS
42289 #define TARGET_HAVE_TLS true
42290 #endif
42291 #undef TARGET_CANNOT_FORCE_CONST_MEM
42292 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42293 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42294 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42296 #undef TARGET_DELEGITIMIZE_ADDRESS
42297 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42299 #undef TARGET_MS_BITFIELD_LAYOUT_P
42300 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42302 #if TARGET_MACHO
42303 #undef TARGET_BINDS_LOCAL_P
42304 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42305 #endif
42306 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42307 #undef TARGET_BINDS_LOCAL_P
42308 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42309 #endif
42311 #undef TARGET_ASM_OUTPUT_MI_THUNK
42312 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42313 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42314 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42316 #undef TARGET_ASM_FILE_START
42317 #define TARGET_ASM_FILE_START x86_file_start
42319 #undef TARGET_OPTION_OVERRIDE
42320 #define TARGET_OPTION_OVERRIDE ix86_option_override
42322 #undef TARGET_REGISTER_MOVE_COST
42323 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42324 #undef TARGET_MEMORY_MOVE_COST
42325 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42326 #undef TARGET_RTX_COSTS
42327 #define TARGET_RTX_COSTS ix86_rtx_costs
42328 #undef TARGET_ADDRESS_COST
42329 #define TARGET_ADDRESS_COST ix86_address_cost
42331 #undef TARGET_FIXED_CONDITION_CODE_REGS
42332 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42333 #undef TARGET_CC_MODES_COMPATIBLE
42334 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42336 #undef TARGET_MACHINE_DEPENDENT_REORG
42337 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42339 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42340 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42342 #undef TARGET_BUILD_BUILTIN_VA_LIST
42343 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42345 #undef TARGET_FOLD_BUILTIN
42346 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42348 #undef TARGET_COMPARE_VERSION_PRIORITY
42349 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42351 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42352 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42353 ix86_generate_version_dispatcher_body
42355 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42356 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42357 ix86_get_function_versions_dispatcher
42359 #undef TARGET_ENUM_VA_LIST_P
42360 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42362 #undef TARGET_FN_ABI_VA_LIST
42363 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42365 #undef TARGET_CANONICAL_VA_LIST_TYPE
42366 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42368 #undef TARGET_EXPAND_BUILTIN_VA_START
42369 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42371 #undef TARGET_MD_ASM_CLOBBERS
42372 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42374 #undef TARGET_PROMOTE_PROTOTYPES
42375 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42376 #undef TARGET_STRUCT_VALUE_RTX
42377 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42378 #undef TARGET_SETUP_INCOMING_VARARGS
42379 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42380 #undef TARGET_MUST_PASS_IN_STACK
42381 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42382 #undef TARGET_FUNCTION_ARG_ADVANCE
42383 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42384 #undef TARGET_FUNCTION_ARG
42385 #define TARGET_FUNCTION_ARG ix86_function_arg
42386 #undef TARGET_FUNCTION_ARG_BOUNDARY
42387 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42388 #undef TARGET_PASS_BY_REFERENCE
42389 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42390 #undef TARGET_INTERNAL_ARG_POINTER
42391 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42392 #undef TARGET_UPDATE_STACK_BOUNDARY
42393 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42394 #undef TARGET_GET_DRAP_RTX
42395 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42396 #undef TARGET_STRICT_ARGUMENT_NAMING
42397 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42398 #undef TARGET_STATIC_CHAIN
42399 #define TARGET_STATIC_CHAIN ix86_static_chain
42400 #undef TARGET_TRAMPOLINE_INIT
42401 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42402 #undef TARGET_RETURN_POPS_ARGS
42403 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42405 #undef TARGET_LEGITIMATE_COMBINED_INSN
42406 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42408 #undef TARGET_ASAN_SHADOW_OFFSET
42409 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42411 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42412 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42414 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42415 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42417 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42418 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42420 #undef TARGET_C_MODE_FOR_SUFFIX
42421 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42423 #ifdef HAVE_AS_TLS
42424 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42425 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42426 #endif
42428 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42429 #undef TARGET_INSERT_ATTRIBUTES
42430 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42431 #endif
42433 #undef TARGET_MANGLE_TYPE
42434 #define TARGET_MANGLE_TYPE ix86_mangle_type
42436 #if !TARGET_MACHO
42437 #undef TARGET_STACK_PROTECT_FAIL
42438 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42439 #endif
42441 #undef TARGET_FUNCTION_VALUE
42442 #define TARGET_FUNCTION_VALUE ix86_function_value
42444 #undef TARGET_FUNCTION_VALUE_REGNO_P
42445 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42447 #undef TARGET_PROMOTE_FUNCTION_MODE
42448 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42450 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42451 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42453 #undef TARGET_INSTANTIATE_DECLS
42454 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42456 #undef TARGET_SECONDARY_RELOAD
42457 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42459 #undef TARGET_CLASS_MAX_NREGS
42460 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42462 #undef TARGET_PREFERRED_RELOAD_CLASS
42463 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42464 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42465 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42466 #undef TARGET_CLASS_LIKELY_SPILLED_P
42467 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42469 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42470 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42471 ix86_builtin_vectorization_cost
42472 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42473 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42474 ix86_vectorize_vec_perm_const_ok
42475 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42476 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42477 ix86_preferred_simd_mode
42478 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42479 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42480 ix86_autovectorize_vector_sizes
42481 #undef TARGET_VECTORIZE_INIT_COST
42482 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42483 #undef TARGET_VECTORIZE_ADD_STMT_COST
42484 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42485 #undef TARGET_VECTORIZE_FINISH_COST
42486 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42487 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42488 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42490 #undef TARGET_SET_CURRENT_FUNCTION
42491 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42493 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42494 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42496 #undef TARGET_OPTION_SAVE
42497 #define TARGET_OPTION_SAVE ix86_function_specific_save
42499 #undef TARGET_OPTION_RESTORE
42500 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42502 #undef TARGET_OPTION_PRINT
42503 #define TARGET_OPTION_PRINT ix86_function_specific_print
42505 #undef TARGET_OPTION_FUNCTION_VERSIONS
42506 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42508 #undef TARGET_CAN_INLINE_P
42509 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42511 #undef TARGET_EXPAND_TO_RTL_HOOK
42512 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42514 #undef TARGET_LEGITIMATE_ADDRESS_P
42515 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42517 #undef TARGET_LRA_P
42518 #define TARGET_LRA_P hook_bool_void_true
42520 #undef TARGET_REGISTER_PRIORITY
42521 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42523 #undef TARGET_LEGITIMATE_CONSTANT_P
42524 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42526 #undef TARGET_FRAME_POINTER_REQUIRED
42527 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42529 #undef TARGET_CAN_ELIMINATE
42530 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42532 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42533 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42535 #undef TARGET_ASM_CODE_END
42536 #define TARGET_ASM_CODE_END ix86_code_end
42538 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42539 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42541 #if TARGET_MACHO
42542 #undef TARGET_INIT_LIBFUNCS
42543 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42544 #endif
42546 #undef TARGET_SPILL_CLASS
42547 #define TARGET_SPILL_CLASS ix86_spill_class
42550 \f