| blob | c56ce3e98627a964dc891133a9591907fe7d8aee |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2419 };
2421 /* This table must be in sync with enum processor_type in i386.h. */
2423 {
2446 };
2447 \f
2448 static bool
2450 {
2452 }
2454 static unsigned int
2456 {
2459 /* vzeroupper instructions are inserted immediately after reload to
2460 account for possible spills from 256bit registers. The pass
2461 reuses mode switching infrastructure by re-running mode insertion
2462 pass, so disable entities that have already been processed. */
2468 /* Call optimize_mode_switching. */
2471 }
2474 {
2475 {
2476 RTL_PASS,
2491 }
2492 };
2494 /* Return true if a red-zone is in use. */
2498 {
2500 }
2501 \f
2502 /* Return a string that documents the current -m options. The caller is
2503 responsible for freeing the string. */
2509 {
2510 struct ix86_target_opts
2511 {
2514 };
2516 /* This table is ordered so that options like -msse4.2 that imply
2517 preceding options while match those first. */
2519 {
2555 };
2557 /* Flag options. */
2559 {
2587 };
2604 /* Add -march= option. */
2606 {
2609 }
2611 /* Add -mtune= option. */
2613 {
2616 }
2618 /* Add -m32/-m64/-mx32. */
2620 {
2623 else
2625 isa &= ~ (OPTION_MASK_ISA_64BIT
2626 | OPTION_MASK_ABI_64
2628 }
2629 else
2633 /* Pick out the options in isa options. */
2635 {
2637 {
2640 }
2641 }
2644 {
2647 isa);
2648 }
2650 /* Add flag options. */
2652 {
2654 {
2657 }
2658 }
2661 {
2664 }
2666 /* Add -fpmath= option. */
2668 {
2671 {
2686 }
2687 }
2689 /* Any options? */
2695 /* Size the string. */
2699 {
2704 }
2706 /* Build the string. */
2711 {
2718 {
2720 line_len++;
2723 {
2727 }
2728 }
2732 {
2736 }
2737 }
2743 }
2745 /* Return true, if profiling code should be emitted before
2746 prologue. Otherwise it returns false.
2747 Note: For x86 with "hotfix" it is sorried. */
2748 static bool
2750 {
2752 }
2754 /* Function that is callable from the debugger to print the current
2755 options. */
2756 void
2758 {
2764 {
2767 }
2768 else
2772 }
2773 \f
2774 /* Override various settings based on options. If MAIN_ARGS_P, the
2775 options are from the command line, otherwise they are from
2776 attributes. */
2778 static void
2780 {
2788 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2789 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2790 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2791 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2792 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2793 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2794 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2795 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2796 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2797 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2798 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2799 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2800 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2801 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2802 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2803 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2804 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2805 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2806 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2807 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2808 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2809 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2810 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2811 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2812 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2813 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2814 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2815 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2816 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2817 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2818 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2819 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2820 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2821 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2822 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2823 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2824 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2825 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2826 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2827 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2829 /* if this reaches 64, need to widen struct pta flags below */
2831 static struct pta
2832 {
2837 }
2839 {
2970 PTA_64BIT
2972 };
2974 /* -mrecip options. */
2975 static struct
2976 {
2979 }
2981 {
2988 };
2992 /* Set up prefix/suffix so the error messages refer to either the command
2993 line argument, or the attribute(target). */
2995 {
2999 }
3000 else
3001 {
3005 }
3007 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3008 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3011 #ifdef TARGET_BI_ARCH
3012 else
3013 {
3014 #if TARGET_BI_ARCH == 1
3015 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3016 is on and OPTION_MASK_ABI_X32 is off. We turn off
3017 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3018 -mx32. */
3021 #else
3022 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3023 on and OPTION_MASK_ABI_64 is off. We turn off
3024 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3025 -m64. */
3028 #endif
3029 }
3030 #endif
3033 {
3034 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3035 OPTION_MASK_ABI_64 for TARGET_X32. */
3038 }
3040 {
3041 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3042 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3045 }
3047 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3048 SUBTARGET_OVERRIDE_OPTIONS;
3049 #endif
3051 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3052 SUBSUBTARGET_OVERRIDE_OPTIONS;
3053 #endif
3055 /* -fPIC is the default for x86_64. */
3059 /* Need to check -mtune=generic first. */
3061 {
3064 /* As special support for cross compilers we read -mtune=native
3065 as -mtune=generic. With native compilers we won't see the
3066 -mtune=native, as it was changed by the driver. */
3068 {
3071 else
3073 }
3074 /* If this call is for setting the option attribute, allow the
3075 generic32/generic64 that was previously set. */
3079 ;
3087 }
3088 else
3089 {
3093 {
3094 ix86_tune_string
3097 }
3099 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3100 need to use a sensible tune option. */
3104 {
3107 else
3109 }
3110 }
3113 {
3114 /* rep; movq isn't available in 32-bit code. */
3117 }
3121 else
3125 {
3131 }
3132 else
3139 {
3141 {
3185 {
3188 }
3196 }
3197 }
3198 else
3199 {
3200 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3201 use of rip-relative addressing. This eliminates fixups that
3202 would otherwise be needed if this object is to be placed in a
3203 DLL, and is essentially just as efficient as direct addressing. */
3210 else
3212 }
3214 {
3217 }
3224 {
3227 /* Default cpu tuning to the architecture. */
3352 }
3367 {
3371 {
3373 {
3375 {
3383 }
3384 else
3387 }
3388 }
3389 else
3390 {
3391 /* Adjust tuning when compiling for 32-bit ABI. */
3393 {
3401 }
3402 }
3403 /* Intel CPUs have always interpreted SSE prefetch instructions as
3404 NOPs; so, we can enable SSE prefetch instructions even when
3405 -mtune (rather than -march) points us to a processor that has them.
3406 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3407 higher processors. */
3412 }
3422 #ifndef USE_IX86_FRAME_POINTER
3423 #define USE_IX86_FRAME_POINTER 0
3424 #endif
3426 #ifndef USE_X86_64_FRAME_POINTER
3427 #define USE_X86_64_FRAME_POINTER 0
3428 #endif
3430 /* Set the default values for switches whose default depends on TARGET_64BIT
3431 in case they weren't overwritten by command line options. */
3433 {
3440 }
3441 else
3442 {
3449 }
3454 else
3457 /* Arrange to set up i386_stack_locals for all functions. */
3460 /* Validate -mregparm= value. */
3462 {
3466 {
3470 }
3471 }
3475 /* Default align_* from the processor table. */
3477 {
3480 }
3482 {
3485 }
3487 {
3489 }
3491 /* Provide default for -mbranch-cost= value. */
3496 {
3499 /* Enable by default the SSE and MMX builtins. Do allow the user to
3500 explicitly disable any of these. In particular, disabling SSE and
3501 MMX for kernel code is extremely useful. */
3503 ix86_isa_flags
3509 }
3510 else
3511 {
3515 ix86_isa_flags
3518 /* i386 ABI does not specify red zone. It still makes sense to use it
3519 when programmer takes care to stack from being destroyed. */
3522 }
3524 /* Keep nonleaf frame pointers. */
3530 /* If we're doing fast math, we don't care about comparison order
3531 wrt NaNs. This lets us use a shorter comparison sequence. */
3535 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3536 since the insns won't need emulation. */
3540 /* Likewise, if the target doesn't have a 387, or we've specified
3541 software floating point, don't use 387 inline intrinsics. */
3545 /* Turn on MMX builtins for -msse. */
3549 /* Enable SSE prefetch. */
3553 /* Enable prefetch{,w} instructions for -m3dnow. */
3557 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3561 /* Enable lzcnt instruction for -mabm. */
3565 /* Validate -mpreferred-stack-boundary= value or default it to
3566 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3569 {
3575 {
3579 else
3582 }
3583 else
3584 ix86_preferred_stack_boundary
3586 }
3588 /* Set the default value for -mstackrealign. */
3594 /* Validate -mincoming-stack-boundary= value or default it to
3595 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3598 {
3603 else
3604 {
3605 ix86_user_incoming_stack_boundary
3607 ix86_incoming_stack_boundary
3609 }
3610 }
3612 /* Accept -msseregparm only if at least SSE support is enabled. */
3618 {
3620 {
3622 {
3625 }
3627 {
3630 }
3631 }
3632 }
3633 else
3636 /* If the i387 is disabled, then do not return values in it. */
3640 /* Use external vectorized library in vectorizing intrinsics. */
3643 {
3654 }
3662 /* ??? Unwind info is not correct around the CFG unless either a frame
3663 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3664 unwind info generation to be aware of the CFG and propagating states
3665 around edges. */
3668 && flag_omit_frame_pointer
3670 {
3676 }
3678 /* If stack probes are required, the space used for large function
3679 arguments on the stack must also be probed, so enable
3680 -maccumulate-outgoing-args so this happens in the prologue. */
3683 {
3688 }
3690 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3691 {
3697 }
3699 /* When scheduling description is not available, disable scheduler pass
3700 so it won't slow down the compilation and make x87 code slower. */
3721 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3723 && HAVE_prefetch
3728 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3729 can be optimized to ap = __builtin_next_arg (0). */
3734 {
3737 {
3739 ix86_gen_tls_local_dynamic_base_64
3741 }
3742 else
3743 {
3745 ix86_gen_tls_local_dynamic_base_64
3747 }
3748 }
3749 else
3753 {
3763 }
3764 else
3765 {
3775 }
3777 #ifdef USE_IX86_CLD
3778 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3781 #endif
3784 {
3789 }
3791 {
3795 }
3797 {
3798 #if defined(PROFILE_BEFORE_PROLOGUE)
3800 #else
3802 #endif
3803 }
3806 {
3807 /* When not optimize for size, enable vzeroupper optimization for
3808 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3809 AVX unaligned load/store. */
3811 {
3821 /* Enable 128-bit AVX instruction generation
3822 for the auto-vectorizer. */
3826 }
3827 }
3828 else
3829 {
3830 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3832 }
3835 {
3842 {
3845 {
3847 q++;
3848 }
3849 else
3854 else
3855 {
3858 {
3861 }
3864 {
3868 }
3869 }
3874 else
3876 }
3877 }
3884 /* Default long double to 64-bit for Bionic. */
3889 /* Save the initial options in case the user does function specific
3890 options. */
3892 target_option_default_node = target_option_current_node
3894 }
3896 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3898 static void
3900 {
3901 static struct register_pass_info insert_vzeroupper_info
3904 };
3909 /* This needs to be done at start up. It's convenient to do it here. */
3911 }
3913 /* Update register usage after having seen the compiler flags. */
3915 static void
3917 {
3921 /* The PIC register, if it exists, is fixed. */
3926 /* For 32-bit targets, squash the REX registers. */
3928 {
3933 }
3935 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3943 {
3944 /* Set/reset conditionally defined registers from
3945 CALL_USED_REGISTERS initializer. */
3949 /* Calculate registers of CLOBBERED_REGS register set
3950 as call used registers from GENERAL_REGS register set. */
3954 }
3956 /* If MMX is disabled, squash the registers. */
3962 /* If SSE is disabled, squash the registers. */
3968 /* If the FPU is disabled, squash the registers. */
3973 }
3975 \f
3976 /* Save the current options */
3978 static void
3980 {
3991 /* The fields are char but the variables are not; make sure the
3992 values fit in the fields. */
3997 }
3999 /* Restore the current options */
4001 static void
4003 {
4019 /* Recreate the arch feature tests if the arch changed */
4021 {
4026 }
4028 /* Recreate the tune optimization tests */
4030 {
4035 }
4036 }
4038 /* Print the current options */
4040 static void
4043 {
4061 {
4064 }
4065 }
4067 \f
4068 /* Inner function to process the attribute((target(...))), take an argument and
4069 set the current options from the argument. If we have a list, recursively go
4070 over the list. */
4072 static bool
4075 {
4079 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4080 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4081 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4082 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4083 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4085 enum ix86_opt_type
4086 {
4087 ix86_opt_unknown,
4088 ix86_opt_yes,
4089 ix86_opt_no,
4090 ix86_opt_str,
4091 ix86_opt_enum,
4092 ix86_opt_isa
4093 };
4095 static const struct
4096 {
4103 /* isa options */
4140 /* enum options */
4143 /* string options */
4147 /* flag options */
4149 OPT_mcld,
4150 MASK_CLD),
4153 OPT_mfancy_math_387,
4154 MASK_NO_FANCY_MATH_387),
4157 OPT_mieee_fp,
4158 MASK_IEEE_FP),
4161 OPT_minline_all_stringops,
4162 MASK_INLINE_ALL_STRINGOPS),
4165 OPT_minline_stringops_dynamically,
4166 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4169 OPT_mno_align_stringops,
4170 MASK_NO_ALIGN_STRINGOPS),
4173 OPT_mrecip,
4174 MASK_RECIP),
4176 };
4178 /* If this is a list, recurse to get the options. */
4180 {
4190 }
4193 {
4196 }
4198 /* Handle multiple arguments separated by commas. */
4202 {
4216 {
4220 }
4221 else
4222 {
4225 }
4227 /* Recognize no-xxx. */
4229 {
4233 }
4234 else
4237 /* Find the option. */
4241 {
4249 {
4254 }
4255 }
4257 /* Process the option. */
4259 {
4262 }
4265 {
4271 }
4274 {
4280 else
4282 }
4285 {
4287 {
4290 }
4291 else
4293 }
4296 {
4304 global_dc);
4305 else
4306 {
4309 }
4310 }
4312 else
4314 }
4317 }
4319 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4321 tree
4323 {
4338 /* Process each of the options on the chain. */
4343 /* If the changed options are different from the default, rerun
4344 ix86_option_override_internal, and then save the options away.
4345 The string options are are attribute options, and will be undone
4346 when we copy the save structure. */
4352 {
4353 /* If we are using the default tune= or arch=, undo the string assigned,
4354 and use the default. */
4365 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4369 {
4372 }
4374 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4377 /* Add any builtin functions with the new isa if any. */
4380 /* Save the current options unless we are validating options for
4381 #pragma. */
4388 /* Free up memory allocated to hold the strings */
4391 }
4394 }
4396 /* Hook to validate attribute((target("string"))). */
4398 static bool
4401 tree args,
4403 {
4407 /* attribute((target("default"))) does nothing, beyond
4408 affecting multi-versioning. */
4419 /* If the function changed the optimization levels as well as setting target
4420 options, start with the optimizations specified. */
4425 /* The target attributes may also change some optimization flags, so update
4426 the optimization options if necessary. */
4435 {
4440 }
4449 }
4451 \f
4452 /* Hook to determine if one function can safely inline another. */
4454 static bool
4456 {
4461 /* If callee has no option attributes, then it is ok to inline. */
4465 /* If caller has no option attributes, but callee does then it is not ok to
4466 inline. */
4470 else
4471 {
4475 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4476 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4477 function. */
4482 /* See if we have the same non-isa options. */
4486 /* See if arch, tune, etc. are the same. */
4499 else
4501 }
4504 }
4506 \f
4507 /* Remember the last target of ix86_set_current_function. */
4510 /* Establish appropriate back-end context for processing the function
4511 FNDECL. The argument might be NULL to indicate processing at top
4512 level, outside of any function scope. */
4513 static void
4515 {
4516 /* Only change the context if the function changes. This hook is called
4517 several times in the course of compiling a function, and we don't want to
4518 slow things down too much or call target_reinit when it isn't safe. */
4520 {
4521 tree old_tree = (ix86_previous_fndecl
4525 tree new_tree = (fndecl
4531 ;
4534 {
4538 }
4541 {
4547 }
4548 }
4549 }
4551 \f
4552 /* Return true if this goes in large data/bss. */
4554 static bool
4556 {
4560 /* Functions are never large data. */
4565 {
4571 }
4572 else
4573 {
4576 /* If this is an incomplete type with size 0, then we can't put it
4577 in data because it might be too big when completed. */
4580 }
4583 }
4585 /* Switch to the appropriate section for output of DECL.
4586 DECL is either a `VAR_DECL' node or a constant of some sort.
4587 RELOC indicates whether forming the initial value of DECL requires
4588 link-time relocations. */
4591 ATTRIBUTE_UNUSED;
4596 {
4599 {
4603 {
4637 /* We don't split these for medium model. Place them into
4638 default sections and hope for best. */
4640 }
4642 {
4643 /* We might get called with string constants, but get_named_section
4644 doesn't like them as they are not DECLs. Also, we need to set
4645 flags in that case. */
4649 }
4650 }
4652 }
4654 /* Select a set of attributes for section NAME based on the properties
4655 of DECL and whether or not RELOC indicates that DECL's initializer
4656 might contain runtime relocations. */
4658 static unsigned int ATTRIBUTE_UNUSED
4660 {
4674 }
4676 /* Build up a unique section name, expressed as a
4677 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4678 RELOC indicates whether the initial value of EXP requires
4679 link-time relocations. */
4681 static void ATTRIBUTE_UNUSED
4683 {
4686 {
4688 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4692 {
4716 /* We don't split these for medium model. Place them into
4717 default sections and hope for best. */
4719 }
4721 {
4728 /* If we're using one_only, then there needs to be a .gnu.linkonce
4729 prefix to the section name. */
4736 }
4737 }
4739 }
4741 #ifdef COMMON_ASM_OP
4742 /* This says how to output assembler code to declare an
4743 uninitialized external linkage data object.
4745 For medium model x86-64 we need to use .largecomm opcode for
4746 large objects. */
4747 void
4751 {
4755 else
4760 }
4761 #endif
4763 /* Utility function for targets to use in implementing
4764 ASM_OUTPUT_ALIGNED_BSS. */
4766 void
4770 {
4774 else
4777 #ifdef ASM_DECLARE_OBJECT_NAME
4780 #else
4781 /* Standard thing is just output label for the object. */
4785 }
4786 \f
4787 /* Decide whether we must probe the stack before any space allocation
4788 on this target. It's essentially TARGET_STACK_PROBE except when
4789 -fstack-check causes the stack to be already probed differently. */
4791 bool
4793 {
4794 /* Do not probe the stack twice if static stack checking is enabled. */
4799 }
4800 \f
4801 /* Decide whether we can make a sibling call to a function. DECL is the
4802 declaration of the function being targeted by the call and EXP is the
4803 CALL_EXPR representing the call. */
4805 static bool
4807 {
4811 /* If we are generating position-independent code, we cannot sibcall
4812 optimize any indirect call, or a direct call to a global function,
4813 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4815 && !TARGET_64BIT
4816 && flag_pic
4820 /* If we need to align the outgoing stack, then sibcalling would
4821 unalign the stack, which may break the called function. */
4827 {
4830 }
4831 else
4832 {
4833 /* We're looking at the CALL_EXPR, we need the type of the function. */
4838 }
4840 /* Check that the return value locations are the same. Like
4841 if we are returning floats on the 80387 register stack, we cannot
4842 make a sibcall from a function that doesn't return a float to a
4843 function that does or, conversely, from a function that does return
4844 a float to a function that doesn't; the necessary stack adjustment
4845 would not be executed. This is also the place we notice
4846 differences in the return value ABI. Note that it is ok for one
4847 of the functions to have void return type as long as the return
4848 value of the other is passed in a register. */
4853 {
4856 }
4858 ;
4863 {
4864 /* The SYSV ABI has more call-clobbered registers;
4865 disallow sibcalls from MS to SYSV. */
4869 }
4870 else
4871 {
4872 /* If this call is indirect, we'll need to be able to use a
4873 call-clobbered register for the address of the target function.
4874 Make sure that all such registers are not used for passing
4875 parameters. Note that DLLIMPORT functions are indirect. */
4878 {
4880 {
4881 /* ??? Need to count the actual number of registers to be used,
4882 not the possible number of registers. Fix later. */
4884 }
4885 }
4886 }
4888 /* Otherwise okay. That also includes certain types of indirect calls. */
4890 }
4892 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4893 and "sseregparm" calling convention attributes;
4894 arguments as in struct attribute_spec.handler. */
4896 static tree
4898 tree args,
4901 {
4906 {
4908 name);
4911 }
4913 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4915 {
4916 tree cst;
4919 {
4921 }
4924 {
4926 }
4930 {
4933 name);
4935 }
4937 {
4941 }
4944 }
4947 {
4948 /* Do not warn when emulating the MS ABI. */
4953 name);
4956 }
4958 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4960 {
4962 {
4964 }
4966 {
4968 }
4970 {
4972 }
4974 {
4976 }
4977 }
4979 /* Can combine stdcall with fastcall (redundant), regparm and
4980 sseregparm. */
4982 {
4984 {
4986 }
4988 {
4990 }
4992 {
4994 }
4995 }
4997 /* Can combine cdecl with regparm and sseregparm. */
4999 {
5001 {
5003 }
5005 {
5007 }
5009 {
5011 }
5012 }
5014 {
5017 name);
5019 {
5021 }
5023 {
5025 }
5027 {
5029 }
5030 }
5032 /* Can combine sseregparm with all attributes. */
5035 }
5037 /* The transactional memory builtins are implicitly regparm or fastcall
5038 depending on the ABI. Override the generic do-nothing attribute that
5039 these builtins were declared with, and replace it with one of the two
5040 attributes that we expect elsewhere. */
5042 static tree
5044 tree args ATTRIBUTE_UNUSED,
5047 {
5048 tree alt;
5050 /* In no case do we want to add the placeholder attribute. */
5053 /* The 64-bit ABI is unchanged for transactional memory. */
5057 /* ??? Is there a better way to validate 32-bit windows? We have
5058 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5061 else
5062 {
5065 }
5069 }
5071 /* This function determines from TYPE the calling-convention. */
5073 unsigned int
5075 {
5078 tree attrs;
5085 {
5095 /* Regparam isn't allowed for thiscall and fastcall. */
5097 {
5102 }
5106 }
5113 || is_stdarg
5119 }
5121 /* Return 0 if the attributes for two types are incompatible, 1 if they
5122 are compatible, and 2 if they are nearly compatible (which causes a
5123 warning to be generated). */
5125 static int
5127 {
5143 }
5144 \f
5145 /* Return the regparm value for a function with the indicated TYPE and DECL.
5146 DECL may be NULL when calling function indirectly
5147 or considering a libcall. */
5149 static int
5151 {
5152 tree attr;
5163 {
5166 {
5169 }
5170 }
5176 /* Use register calling convention for local functions when possible. */
5179 && optimize
5181 {
5182 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5185 {
5188 /* Make sure no regparm register is taken by a
5189 fixed register variable. */
5194 /* We don't want to use regparm(3) for nested functions as
5195 these use a static chain pointer in the third argument. */
5199 /* In 32-bit mode save a register for the split stack. */
5203 /* Each fixed register usage increases register pressure,
5204 so less registers should be used for argument passing.
5205 This functionality can be overriden by an explicit
5206 regparm value. */
5209 globals++;
5211 local_regparm
5216 }
5217 }
5220 }
5222 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5223 DFmode (2) arguments in SSE registers for a function with the
5224 indicated TYPE and DECL. DECL may be NULL when calling function
5225 indirectly or considering a libcall. Otherwise return 0. */
5227 static int
5229 {
5232 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5233 by the sseregparm attribute. */
5236 {
5238 {
5240 {
5244 else
5247 }
5249 }
5252 }
5254 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5255 (and DFmode for SSE2) arguments in SSE registers. */
5258 {
5259 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5263 }
5266 }
5268 /* Return true if EAX is live at the start of the function. Used by
5269 ix86_expand_prologue to determine if we need special help before
5270 calling allocate_stack_worker. */
5272 static bool
5274 {
5275 /* Cheat. Don't bother working forward from ix86_function_regparm
5276 to the function type to whether an actual argument is located in
5277 eax. Instead just look at cfg info, which is still close enough
5278 to correct at this point. This gives false positives for broken
5279 functions that might use uninitialized data that happens to be
5280 allocated in eax, but who cares? */
5282 }
5284 static bool
5286 {
5287 tree attr;
5290 {
5296 /* For 32-bit MS-ABI the default is to keep aggregate
5297 return pointer. */
5300 }
5302 }
5304 /* Value is the number of bytes of arguments automatically
5305 popped when returning from a subroutine call.
5306 FUNDECL is the declaration node of the function (as a tree),
5307 FUNTYPE is the data type of the function (as a tree),
5308 or for a library call it is an identifier node for the subroutine name.
5309 SIZE is the number of bytes of arguments passed on the stack.
5311 On the 80386, the RTD insn may be used to pop them if the number
5312 of args is fixed, but if the number is variable then the caller
5313 must pop them all. RTD can't be used for library calls now
5314 because the library is compiled with the Unix compiler.
5315 Use of RTD is a selectable option, since it is incompatible with
5316 standard Unix calling sequences. If the option is not selected,
5317 the caller must always pop the args.
5319 The attribute stdcall is equivalent to RTD on a per module basis. */
5321 static int
5323 {
5326 /* None of the 64-bit ABIs pop arguments. */
5337 /* Lose any fake structure return argument if it is passed on the stack. */
5340 {
5344 }
5347 }
5349 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5351 static bool
5353 {
5354 /* Check operand constraints in case hard registers were propagated
5355 into insn pattern. This check prevents combine pass from
5356 generating insn patterns with invalid hard register operands.
5357 These invalid insns can eventually confuse reload to error out
5358 with a spill failure. See also PRs 46829 and 46843. */
5360 {
5367 {
5375 /* For pre-AVX disallow unaligned loads/stores where the
5376 instructions don't support it. */
5380 {
5384 }
5386 /* A unary operator may be accepted by the predicate, but it
5387 is irrelevant for matching constraints. */
5392 {
5400 }
5407 /* Operand has no constraints, anything is OK. */
5411 {
5414 && operands_match_p
5418 {
5421 }
5422 }
5426 }
5427 }
5430 }
5431 \f
5432 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5434 static unsigned HOST_WIDE_INT
5436 {
5440 }
5441 \f
5442 /* Argument support functions. */
5444 /* Return true when register may be used to pass function parameters. */
5445 bool
5447 {
5452 {
5456 else
5462 }
5465 {
5468 }
5469 else
5470 {
5474 }
5476 /* TODO: The function should depend on current function ABI but
5477 builtins.c would need updating then. Therefore we use the
5478 default ABI. */
5480 /* RAX is used as hidden argument to va_arg functions. */
5486 else
5493 }
5495 /* Return if we do not know how to pass TYPE solely in registers. */
5497 static bool
5499 {
5503 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5504 The layout_type routine is crafty and tries to trick us into passing
5505 currently unsupported vector types on the stack by using TImode. */
5508 }
5510 /* It returns the size, in bytes, of the area reserved for arguments passed
5511 in registers for the function represented by fndecl dependent to the used
5512 abi format. */
5513 int
5515 {
5519 else
5524 }
5526 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5527 call abi used. */
5528 enum calling_abi
5530 {
5532 {
5535 {
5538 }
5542 }
5544 }
5546 static bool
5548 {
5550 {
5554 else
5556 }
5558 }
5560 static enum calling_abi
5562 {
5566 }
5568 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5569 call abi used. */
5570 enum calling_abi
5572 {
5576 }
5578 /* Write the extra assembler code needed to declare a function properly. */
5580 void
5582 tree decl)
5583 {
5587 {
5593 }
5595 #ifdef SUBTARGET_ASM_UNWIND_INIT
5597 #endif
5601 /* Output magic byte marker, if hot-patch attribute is set. */
5603 {
5605 {
5606 /* leaq [%rsp + 0], %rsp */
5609 }
5610 else
5611 {
5612 /* movl.s %edi, %edi
5613 push %ebp
5614 movl.s %esp, %ebp */
5617 }
5618 }
5619 }
5621 /* regclass.c */
5624 /* Implementation of call abi switching target hook. Specific to FNDECL
5625 the specific call register sets are set. See also
5626 ix86_conditional_register_usage for more details. */
5627 void
5629 {
5632 else
5634 }
5636 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5637 expensive re-initialization of init_regs each time we switch function context
5638 since this is needed only during RTL expansion. */
5639 static void
5641 {
5645 }
5647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5648 for a call to a function whose data type is FNTYPE.
5649 For a library call, FNTYPE is 0. */
5651 void
5655 tree fndecl,
5657 {
5663 {
5666 }
5667 else
5668 {
5671 }
5675 /* Set up the number of registers to use for passing arguments. */
5682 {
5684 ? X86_64_REGPARM_MAX
5686 }
5688 {
5691 {
5693 ? X86_64_SSE_REGPARM_MAX
5695 }
5696 }
5703 /* Because type might mismatch in between caller and callee, we need to
5704 use actual type of function for local calls.
5705 FIXME: cgraph_analyze can be told to actually record if function uses
5706 va_start so for local functions maybe_vaarg can be made aggressive
5707 helping K&R code.
5708 FIXME: once typesytem is fixed, we won't need this code anymore. */
5716 {
5717 /* If there are variable arguments, then we won't pass anything
5718 in registers in 32-bit mode. */
5720 {
5728 }
5730 /* Use ecx and edx registers if function has fastcall attribute,
5731 else look for regparm information. */
5733 {
5736 {
5739 }
5741 {
5744 }
5745 else
5747 }
5749 /* Set up the number of SSE registers used for passing SFmode
5750 and DFmode arguments. Warn for mismatching ABI. */
5752 }
5753 }
5755 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5756 But in the case of vector types, it is some vector mode.
5758 When we have only some of our vector isa extensions enabled, then there
5759 are some modes for which vector_mode_supported_p is false. For these
5760 modes, the generic vector support in gcc will choose some non-vector mode
5761 in order to implement the type. By computing the natural mode, we'll
5762 select the proper ABI location for the operand and not depend on whatever
5763 the middle-end decides to do with these vector types.
5765 The midde-end can't deal with the vector types > 16 bytes. In this
5766 case, we return the original mode and warn ABI change if CUM isn't
5767 NULL.
5769 If INT_RETURN is true, warn ABI change if the vector mode isn't
5770 available for function return value. */
5772 static enum machine_mode
5775 {
5779 {
5782 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5784 {
5789 else
5792 /* Get the mode which has this inner mode and number of units. */
5796 {
5798 {
5803 && !warnedavx
5805 {
5809 }
5811 {
5815 }
5818 }
5821 {
5826 && !warnedsse
5828 {
5832 }
5834 && in_return
5836 {
5840 }
5841 }
5843 {
5848 && !warnedmmx
5850 {
5854 }
5856 {
5860 }
5861 }
5863 }
5866 }
5867 }
5870 }
5872 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5873 this may not agree with the mode that the type system has chosen for the
5874 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5875 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5877 static rtx
5880 {
5881 rtx tmp;
5885 else
5886 {
5890 }
5893 }
5895 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5896 of this code is to classify each 8bytes of incoming argument by the register
5897 class and assign registers accordingly. */
5899 /* Return the union class of CLASS1 and CLASS2.
5900 See the x86-64 PS ABI for details. */
5902 static enum x86_64_reg_class
5904 {
5905 /* Rule #1: If both classes are equal, this is the resulting class. */
5909 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5910 the other class. */
5916 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5920 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5928 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5929 MEMORY is used. */
5938 /* Rule #6: Otherwise class SSE is used. */
5940 }
5942 /* Classify the argument of type TYPE and mode MODE.
5943 CLASSES will be filled by the register class used to pass each word
5944 of the operand. The number of words is returned. In case the parameter
5945 should be passed in memory, 0 is returned. As a special case for zero
5946 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5948 BIT_OFFSET is used internally for handling records and specifies offset
5949 of the offset in bits modulo 256 to avoid overflow cases.
5951 See the x86-64 PS ABI for details.
5952 */
5954 static int
5957 {
5958 HOST_WIDE_INT bytes =
5960 int words
5963 /* Variable sized entities are always passed/returned in memory. */
5972 {
5974 tree field;
5977 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5984 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5985 signalize memory class, so handle it as special case. */
5987 {
5990 }
5992 /* Classify each field of record and merge classes. */
5994 {
5996 /* And now merge the fields of structure. */
5998 {
6000 {
6006 /* Bitfields are always classified as integer. Handle them
6007 early, since later code would consider them to be
6008 misaligned integers. */
6010 {
6019 }
6020 else
6021 {
6026 /* Flexible array member is ignored. */
6033 {
6037 {
6040 "the ABI of passing struct with"
6041 " a flexible array member has"
6043 }
6045 }
6047 subclasses,
6057 }
6058 }
6059 }
6063 /* Arrays are handled as small records. */
6064 {
6071 /* The partial classes are now full classes. */
6082 }
6085 /* Unions are similar to RECORD_TYPE but offset is always 0.
6086 */
6088 {
6090 {
6098 bit_offset);
6103 }
6104 }
6109 }
6112 {
6113 /* When size > 16 bytes, if the first one isn't
6114 X86_64_SSE_CLASS or any other ones aren't
6115 X86_64_SSEUP_CLASS, everything should be passed in
6116 memory. */
6123 }
6125 /* Final merger cleanup. */
6127 {
6128 /* If one class is MEMORY, everything should be passed in
6129 memory. */
6133 /* The X86_64_SSEUP_CLASS should be always preceded by
6134 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6138 {
6139 /* The first one should never be X86_64_SSEUP_CLASS. */
6142 }
6144 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6145 everything should be passed in memory. */
6148 {
6151 /* The first one should never be X86_64_X87UP_CLASS. */
6154 {
6157 "the ABI of passing union with long double"
6159 }
6161 }
6162 }
6164 }
6166 /* Compute alignment needed. We align all types to natural boundaries with
6167 exception of XFmode that is aligned to 64bits. */
6169 {
6178 /* Misaligned fields are always returned in memory. */
6181 }
6183 /* for V1xx modes, just use the base mode */
6188 /* Classification of atomic types. */
6190 {
6206 {
6210 {
6213 }
6215 {
6218 }
6220 {
6224 }
6226 {
6229 }
6230 else
6232 }
6239 /* OImode shouldn't be used directly. */
6246 else
6264 else
6265 {
6269 {
6272 "the ABI of passing structure with complex float"
6274 }
6277 }
6286 /* This modes is larger than 16 bytes. */
6329 else
6333 }
6334 }
6336 /* Examine the argument and return set number of register required in each
6337 class. Return 0 iff parameter should be passed in memory. */
6338 static int
6341 {
6351 {
6373 }
6375 }
6377 /* Construct container for the argument used by GCC interface. See
6378 FUNCTION_ARG for the detailed description. */
6380 static rtx
6384 {
6385 /* The following variables hold the static issued_error state. */
6399 rtx ret;
6410 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6411 some less clueful developer tries to use floating-point anyway. */
6413 {
6415 {
6417 {
6420 }
6421 }
6423 {
6426 }
6428 }
6430 /* Likewise, error if the ABI requires us to return values in the
6431 x87 registers and the user specified -mno-80387. */
6437 {
6439 {
6442 }
6444 }
6446 /* First construct simple cases. Avoid SCmode, since we want to use
6447 single register to pass this type. */
6450 {
6465 /* Zero sized array, struct or class. */
6469 }
6496 /* Otherwise figure out the entries of the PARALLEL. */
6498 {
6502 {
6507 /* Merge TImodes on aligned occasions here too. */
6509 tmpmode
6513 else
6515 /* We've requested 24 bytes we
6516 don't have mode for. Use DImode. */
6523 intreg++;
6531 sse_regno++;
6539 sse_regno++;
6544 {
6550 {
6552 i++;
6553 }
6554 else
6567 }
6573 sse_regno++;
6577 }
6578 }
6580 /* Empty aligned struct, union or class. */
6588 }
6590 /* Update the data in CUM to advance over an argument of mode MODE
6591 and data type TYPE. (TYPE is null for libcalls where that information
6592 may not be available.) */
6594 static void
6597 HOST_WIDE_INT words)
6598 {
6600 {
6607 /* FALLTHRU */
6618 {
6621 }
6625 /* OImode shouldn't be used directly. */
6634 /* FALLTHRU */
6650 {
6655 {
6658 }
6659 }
6669 {
6674 {
6677 }
6678 }
6680 }
6681 }
6683 static void
6686 {
6689 /* Unnamed 256bit vector mode parameters are passed on stack. */
6695 {
6700 }
6701 else
6702 {
6706 }
6707 }
6709 static void
6711 HOST_WIDE_INT words)
6712 {
6713 /* Otherwise, this should be passed indirect. */
6718 {
6721 }
6722 }
6724 /* Update the data in CUM to advance over an argument of mode MODE and
6725 data type TYPE. (TYPE is null for libcalls where that information
6726 may not be available.) */
6728 static void
6731 {
6737 else
6748 else
6750 }
6752 /* Define where to put the arguments to a function.
6753 Value is zero to push the argument on the stack,
6754 or a hard register in which to store the argument.
6756 MODE is the argument's machine mode.
6757 TYPE is the data type of the argument (as a tree).
6758 This is null for libcalls where that information may
6759 not be available.
6760 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6761 the preceding args and about the function being called.
6762 NAMED is nonzero if this argument is a named parameter
6763 (otherwise it is an extra parameter matching an ellipsis). */
6765 static rtx
6769 {
6770 /* Avoid the AL settings for the Unix64 ABI. */
6775 {
6782 /* FALLTHRU */
6788 {
6791 /* Fastcall allocates the first two DWORD (SImode) or
6792 smaller arguments to ECX and EDX if it isn't an
6793 aggregate type . */
6795 {
6801 /* ECX not EAX is the first allocated register. */
6804 }
6806 }
6815 /* FALLTHRU */
6817 /* In 32bit, we pass TImode in xmm registers. */
6825 {
6829 }
6833 /* OImode shouldn't be used directly. */
6843 {
6847 }
6857 {
6861 }
6863 }
6866 }
6868 static rtx
6871 {
6872 /* Handle a hidden AL argument containing number of registers
6873 for varargs x86-64 functions. */
6877 ? X86_64_SSE_REGPARM_MAX
6882 {
6892 /* Unnamed 256bit vector mode parameters are passed on stack. */
6896 }
6902 }
6904 static rtx
6907 HOST_WIDE_INT bytes)
6908 {
6911 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6912 We use value of -2 to specify that current function call is MSABI. */
6916 /* If we've run out of registers, it goes on the stack. */
6922 /* Only floating point modes are passed in anything but integer regs. */
6924 {
6927 else
6928 {
6931 /* Unnamed floating parameters are passed in both the
6932 SSE and integer registers. */
6938 }
6939 }
6940 /* Handle aggregated types passed in register. */
6942 {
6947 }
6950 }
6952 /* Return where to put the arguments to a function.
6953 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6955 MODE is the argument's machine mode. TYPE is the data type of the
6956 argument. It is null for libcalls where that information may not be
6957 available. CUM gives information about the preceding args and about
6958 the function being called. NAMED is nonzero if this argument is a
6959 named parameter (otherwise it is an extra parameter matching an
6960 ellipsis). */
6962 static rtx
6965 {
6969 rtx arg;
6973 else
6977 /* To simplify the code below, represent vector types with a vector mode
6978 even if MMX/SSE are not active. */
6986 else
6990 }
6992 /* A C expression that indicates when an argument must be passed by
6993 reference. If nonzero for an argument, a copy of that argument is
6994 made in memory and a pointer to the argument is passed instead of
6995 the argument itself. The pointer is passed in whatever way is
6996 appropriate for passing a pointer to that type. */
6998 static bool
7002 {
7005 /* See Windows x64 Software Convention. */
7007 {
7010 {
7011 /* Arrays are passed by reference. */
7016 {
7017 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7018 are passed by reference. */
7020 }
7021 }
7023 /* __m128 is passed by reference. */
7029 }
7030 }
7035 }
7037 /* Return true when TYPE should be 128bit aligned for 32bit argument
7038 passing ABI. XXX: This function is obsolete and is only used for
7039 checking psABI compatibility with previous versions of GCC. */
7041 static bool
7043 {
7055 {
7056 /* Walk the aggregates recursively. */
7058 {
7062 {
7063 tree field;
7065 /* Walk all the structure fields. */
7067 {
7071 }
7073 }
7076 /* Just for use if some languages passes arrays by value. */
7083 }
7084 }
7086 }
7088 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7089 XXX: This function is obsolete and is only used for checking psABI
7090 compatibility with previous versions of GCC. */
7092 static unsigned int
7095 {
7096 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7097 natural boundaries. */
7099 {
7100 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7101 make an exception for SSE modes since these require 128bit
7102 alignment.
7104 The handling here differs from field_alignment. ICC aligns MMX
7105 arguments to 4 byte boundaries, while structure fields are aligned
7106 to 8 byte boundaries. */
7108 {
7111 }
7112 else
7113 {
7116 }
7117 }
7121 }
7123 /* Return true when TYPE should be 128bit aligned for 32bit argument
7124 passing ABI. */
7126 static bool
7128 {
7138 {
7139 /* Walk the aggregates recursively. */
7141 {
7145 {
7146 tree field;
7148 /* Walk all the structure fields. */
7150 field;
7152 {
7156 }
7158 }
7161 /* Just for use if some languages passes arrays by value. */
7168 }
7169 }
7170 else
7174 }
7176 /* Gives the alignment boundary, in bits, of an argument with the
7177 specified mode and type. */
7179 static unsigned int
7181 {
7184 {
7185 /* Since the main variant type is used for call, we convert it to
7186 the main variant type. */
7189 }
7190 else
7194 else
7195 {
7200 {
7201 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7203 {
7206 }
7212 }
7215 && !warned
7217 saved_align))
7218 {
7221 "The ABI for passing parameters with %d-byte"
7224 }
7225 }
7228 }
7230 /* Return true if N is a possible register number of function value. */
7232 static bool
7234 {
7236 {
7244 /* Complex values are returned in %st(0)/%st(1) pair. */
7247 /* TODO: The function should depend on current function ABI but
7248 builtins.c would need updating then. Therefore we use the
7249 default ABI. */
7254 /* Complex values are returned in %xmm0/%xmm1 pair. */
7263 }
7266 }
7268 /* Define how to find the value returned by a function.
7269 VALTYPE is the data type of the value (as a tree).
7270 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7271 otherwise, FUNC is 0. */
7273 static rtx
7276 {
7279 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7280 we normally prevent this case when mmx is not available. However
7281 some ABIs may require the result to be returned like DImode. */
7285 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7286 we prevent this case when sse is not available. However some ABIs
7287 may require the result to be returned like integer TImode. */
7292 /* 32-byte vector modes in %ymm0. */
7296 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7299 else
7300 /* Most things go in %eax. */
7303 /* Override FP return register with %xmm0 for local functions when
7304 SSE math is enabled or for functions with sseregparm attribute. */
7306 {
7311 }
7313 /* OImode shouldn't be used directly. */
7317 }
7319 static rtx
7321 const_tree valtype)
7322 {
7323 rtx ret;
7325 /* Handle libcalls, which don't provide a type node. */
7327 {
7331 {
7350 }
7353 }
7355 {
7356 /* Pointers are always returned in word_mode. */
7358 }
7364 /* For zero sized structures, construct_container returns NULL, but we
7365 need to keep rest of compiler happy by returning meaningful value. */
7370 }
7372 static rtx
7374 const_tree valtype)
7375 {
7379 {
7381 {
7400 }
7401 }
7403 }
7405 static rtx
7408 {
7420 else
7422 }
7424 static rtx
7427 {
7433 }
7435 /* Pointer function arguments and return values are promoted to
7436 word_mode. */
7438 static enum machine_mode
7442 {
7444 {
7447 }
7449 for_return);
7450 }
7452 /* Return true if a structure, union or array with MODE containing FIELD
7453 should be accessed using BLKmode. */
7455 static bool
7457 {
7458 /* Union with XFmode must be in BLKmode. */
7462 }
7464 rtx
7466 {
7468 }
7470 /* Return true iff type is returned in memory. */
7472 static bool ATTRIBUTE_UNUSED
7474 {
7475 HOST_WIDE_INT size;
7486 {
7487 /* User-created vectors small enough to fit in EAX. */
7491 /* MMX/3dNow values are returned in MM0,
7492 except when it doesn't exits or the ABI prescribes otherwise. */
7496 /* SSE values are returned in XMM0, except when it doesn't exist. */
7500 /* AVX values are returned in YMM0, except when it doesn't exist. */
7503 }
7511 /* OImode shouldn't be used directly. */
7515 }
7517 static bool ATTRIBUTE_UNUSED
7519 {
7522 }
7524 static bool ATTRIBUTE_UNUSED
7526 {
7529 /* __m128 is returned in xmm0. */
7536 /* Otherwise, the size must be exactly in [1248]. */
7538 }
7540 static bool
7542 {
7543 #ifdef SUBTARGET_RETURN_IN_MEMORY
7545 #else
7549 {
7552 else
7554 }
7555 else
7557 #endif
7558 }
7560 \f
7561 /* Create the va_list data type. */
7563 /* Returns the calling convention specific va_list date type.
7564 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7566 static tree
7568 {
7571 /* For i386 we use plain pointer to argument area. */
7581 unsigned_type_node);
7584 unsigned_type_node);
7587 ptr_type_node);
7590 ptr_type_node);
7609 /* The correct type is an array type of one element. */
7611 }
7613 /* Setup the builtin va_list data type and for 64-bit the additional
7614 calling convention specific va_list data types. */
7616 static tree
7618 {
7621 /* Initialize abi specific va_list builtin types. */
7623 {
7624 tree t;
7626 {
7631 }
7632 else
7633 {
7638 }
7640 {
7645 }
7646 else
7647 {
7652 }
7653 }
7656 }
7658 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7660 static void
7662 {
7664 alias_set_type set;
7667 /* GPR size of varargs save area. */
7670 else
7673 /* FPR size of varargs save area. We don't need it if we don't pass
7674 anything in SSE registers. */
7677 else
7691 {
7699 }
7702 {
7706 /* Now emit code to save SSE registers. The AX parameter contains number
7707 of SSE parameter registers used to call this function, though all we
7708 actually check here is the zero/non-zero status. */
7713 label));
7715 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7716 we used movdqa (i.e. TImode) instead? Perhaps even better would
7717 be if we could determine the real mode of the data, via a hook
7718 into pass_stdarg. Ignore all that for now. */
7728 {
7737 }
7740 }
7741 }
7743 static void
7745 {
7749 /* Reset to zero, as there might be a sysv vaarg used
7750 before. */
7755 {
7766 }
7767 }
7769 static void
7773 {
7775 CUMULATIVE_ARGS next_cum;
7776 tree fntype;
7778 /* This argument doesn't appear to be used anymore. Which is good,
7779 because the old code here didn't suppress rtl generation. */
7787 /* For varargs, we do not want to skip the dummy va_dcl argument.
7788 For stdargs, we do want to skip the last named argument. */
7796 else
7798 }
7800 /* Checks if TYPE is of kind va_list char *. */
7802 static bool
7804 {
7805 tree canonic;
7807 /* For 32-bit it is always true. */
7813 }
7815 /* Implement va_start. */
7817 static void
7819 {
7823 tree type;
7824 rtx ovf_rtx;
7828 {
7831 /* When we are splitting the stack, we can't refer to the stack
7832 arguments using internal_arg_pointer, because they may be on
7833 the old stack. The split stack prologue will arrange to
7834 leave a pointer to the old stack arguments in a scratch
7835 register, which we here copy to a pseudo-register. The split
7836 stack prologue can't set the pseudo-register directly because
7837 it (the prologue) runs before any registers have been saved. */
7841 {
7855 }
7856 }
7858 /* Only 64bit target needs something special. */
7860 {
7863 else
7864 {
7873 }
7875 }
7884 /* The following should be folded into the MEM_REF offset. */
7894 /* Count number of gp and fp argument registers used. */
7900 {
7906 }
7909 {
7915 }
7917 /* Find the overflow area. */
7921 else
7931 {
7932 /* Find the register save area.
7933 Prologue of the function save it right above stack frame. */
7941 }
7942 }
7944 /* Implement va_arg. */
7946 static tree
7949 {
7956 rtx container;
7958 tree ptrtype;
7962 /* Only 64bit target needs something special. */
7986 {
7993 /* Unnamed 256bit vector mode parameters are passed on stack. */
7995 {
7998 }
8006 }
8008 /* Pull the value out of the saved registers. */
8013 {
8027 /* In case we are passing structure, verify that it is consecutive block
8028 on the register save area. If not we need to do moves. */
8030 {
8031 /* Verify that all registers are strictly consecutive */
8033 {
8037 {
8042 }
8043 }
8044 else
8045 {
8049 {
8054 }
8055 }
8056 }
8058 {
8061 }
8062 else
8063 {
8066 }
8068 /* First ensure that we fit completely in registers. */
8070 {
8077 }
8079 {
8087 }
8089 /* Compute index to start of area used for integer regs. */
8091 {
8092 /* int_addr = gpr + sav; */
8095 }
8097 {
8098 /* sse_addr = fpr + sav; */
8101 }
8103 {
8107 /* addr = &temp; */
8112 {
8116 tree piece_type;
8117 tree addr_type;
8118 tree daddr_type;
8127 {
8132 }
8136 else
8143 {
8146 }
8147 else
8148 {
8151 }
8158 {
8163 }
8164 else
8165 {
8166 tree copy
8171 }
8173 }
8174 }
8177 {
8181 }
8184 {
8188 }
8193 }
8195 /* ... otherwise out of the overflow area. */
8197 /* When we align parameter on stack for caller, if the parameter
8198 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8199 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8200 here with caller. */
8205 /* Care for on-stack alignment if needed. */
8208 else
8209 {
8214 }
8231 }
8232 \f
8233 /* Return true if OPNUM's MEM should be matched
8234 in movabs* patterns. */
8236 bool
8238 {
8250 }
8251 \f
8252 /* Initialize the table of extra 80387 mathematical constants. */
8254 static void
8256 {
8258 {
8264 };
8268 {
8270 /* Ensure each constant is rounded to XFmode precision. */
8273 }
8276 }
8278 /* Return non-zero if the constant is something that
8279 can be loaded with a special instruction. */
8281 int
8283 {
8286 REAL_VALUE_TYPE r;
8298 /* For XFmode constants, try to find a special 80387 instruction when
8299 optimizing for size or on those CPUs that benefit from them. */
8302 {
8311 }
8313 /* Load of the constant -0.0 or -1.0 will be split as
8314 fldz;fchs or fld1;fchs sequence. */
8321 }
8323 /* Return the opcode of the special instruction to be used to load
8324 the constant X. */
8328 {
8330 {
8350 }
8351 }
8353 /* Return the CONST_DOUBLE representing the 80387 constant that is
8354 loaded by the specified special instruction. The argument IDX
8355 matches the return value from standard_80387_constant_p. */
8357 rtx
8359 {
8366 {
8377 }
8380 XFmode);
8381 }
8383 /* Return 1 if X is all 0s and 2 if x is all 1s
8384 in supported SSE/AVX vector mode. */
8386 int
8388 {
8395 {
8410 }
8413 }
8415 /* Return the opcode of the special instruction to be used to load
8416 the constant X. */
8420 {
8422 {
8425 {
8442 }
8447 else
8452 }
8454 }
8456 /* Returns true if OP contains a symbol reference */
8458 bool
8460 {
8469 {
8471 {
8477 }
8481 }
8484 }
8486 /* Return true if it is appropriate to emit `ret' instructions in the
8487 body of a function. Do this only if the epilogue is simple, needing a
8488 couple of insns. Prior to reloading, we can't tell how many registers
8489 must be saved, so return false then. Return false if there is no frame
8490 marker to de-allocate. */
8492 bool
8494 {
8500 /* Don't allow more than 32k pop, since that's all we can do
8501 with one instruction. */
8508 }
8509 \f
8510 /* Value should be nonzero if functions must have frame pointers.
8511 Zero means the frame pointer need not be set up (and parms may
8512 be accessed via the stack pointer) in functions that seem suitable. */
8514 static bool
8516 {
8517 /* If we accessed previous frames, then the generated code expects
8518 to be able to access the saved ebp value in our frame. */
8522 /* Several x86 os'es need a frame pointer for other reasons,
8523 usually pertaining to setjmp. */
8527 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8531 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8532 allocation is 4GB. */
8536 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8537 turns off the frame pointer by default. Turn it back on now if
8538 we've not got a leaf function. */
8548 }
8550 /* Record that the current function accesses previous call frames. */
8552 void
8554 {
8556 }
8557 \f
8558 #ifndef USE_HIDDEN_LINKONCE
8559 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8560 # define USE_HIDDEN_LINKONCE 1
8561 # else
8562 # define USE_HIDDEN_LINKONCE 0
8563 # endif
8564 #endif
8568 /* Fills in the label name that should be used for a pc thunk for
8569 the given register. */
8571 static void
8573 {
8578 else
8580 }
8583 /* This function generates code for -fpic that loads %ebx with
8584 the return address of the caller and then returns. */
8586 static void
8588 {
8593 {
8595 tree decl;
8611 #if TARGET_MACHO
8613 {
8622 }
8623 else
8624 #endif
8626 {
8637 }
8638 else
8639 {
8642 }
8648 /* Make sure unwind info is emitted for the thunk if needed. */
8651 /* Pad stack IP move with 4 instructions (two NOPs count
8652 as one instruction). */
8654 {
8659 }
8670 }
8674 }
8676 /* Emit code for the SET_GOT patterns. */
8680 {
8686 {
8687 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8692 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8693 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8694 an unadorned address. */
8699 }
8704 {
8706 /* We don't need a pic base, we're not producing pic. */
8713 }
8714 else
8715 {
8724 #if TARGET_MACHO
8725 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
8726 This is what will be referenced by the Mach-O PIC subsystem. */
8730 /* When we are restoring the pic base at the site of a nonlocal label,
8731 and we decided to emit the pic base above, we will still output a
8732 local label used for calculating the correction offset (even though
8733 the offset will be 0 in that case). */
8737 #endif
8738 }
8744 }
8746 /* Generate an "push" pattern for input ARG. */
8748 static rtx
8750 {
8763 stack_pointer_rtx)),
8764 arg);
8765 }
8767 /* Generate an "pop" pattern for input ARG. */
8769 static rtx
8771 {
8776 arg,
8779 stack_pointer_rtx)));
8780 }
8782 /* Return >= 0 if there is an unused call-clobbered register available
8783 for the entire function. */
8785 static unsigned int
8787 {
8791 {
8793 /* Can't use the same register for both PIC and DRAP. */
8796 else
8801 }
8804 }
8806 /* Return TRUE if we need to save REGNO. */
8808 static bool
8810 {
8821 {
8824 {
8830 }
8831 }
8840 }
8842 /* Return number of saved general prupose registers. */
8844 static int
8846 {
8852 nregs ++;
8854 }
8856 /* Return number of saved SSE registrers. */
8858 static int
8860 {
8868 nregs ++;
8870 }
8872 /* Given FROM and TO register numbers, say whether this elimination is
8873 allowed. If stack alignment is needed, we can only replace argument
8874 pointer with hard frame pointer, or replace frame pointer with stack
8875 pointer. Otherwise, frame pointer elimination is automatically
8876 handled and all other eliminations are valid. */
8878 static bool
8880 {
8886 else
8888 }
8890 /* Return the offset between two registers, one to be eliminated, and the other
8891 its replacement, at the start of a routine. */
8893 HOST_WIDE_INT
8895 {
8904 else
8905 {
8913 }
8914 }
8916 /* In a dynamically-aligned function, we can't know the offset from
8917 stack pointer to frame pointer, so we must ensure that setjmp
8918 eliminates fp against the hard fp (%ebp) rather than trying to
8919 index from %esp up to the top of the frame across a gap that is
8920 of unknown (at compile-time) size. */
8921 static rtx
8923 {
8925 }
8927 /* When using -fsplit-stack, the allocation routines set a field in
8928 the TCB to the bottom of the stack plus this much space, measured
8929 in bytes. */
8931 #define SPLIT_STACK_AVAILABLE 256
8933 /* Fill structure ix86_frame about frame of currently computed function. */
8935 static void
8937 {
8939 HOST_WIDE_INT offset;
8942 HOST_WIDE_INT to_allocate;
8950 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8951 function prologues and leaf. */
8955 {
8960 }
8966 /* For SEH we have to limit the amount of code movement into the prologue.
8967 At present we do this via a BLOCKAGE, at which point there's very little
8968 scheduling that can be done, which means that there's very little point
8969 in doing anything except PUSHs. */
8973 /* During reload iteration the amount of registers saved can change.
8974 Recompute the value as needed. Do not recompute when amount of registers
8975 didn't change as reload does multiple calls to the function and does not
8976 expect the decision to change within single iteration. */
8979 {
8985 /* The fast prologue uses move instead of push to save registers. This
8986 is significantly longer, but also executes faster as modern hardware
8987 can execute the moves in parallel, but can't do that for push/pop.
8989 Be careful about choosing what prologue to emit: When function takes
8990 many instructions to execute we may use slow version as well as in
8991 case function is known to be outside hot spot (this is known with
8992 feedback only). Weight the size of function by number of registers
8993 to save as it is cheap to use one or two push instructions but very
8994 slow to use many of them. */
8998 || (flag_branch_probabilities
9001 else
9004 }
9006 frame->save_regs_using_mov
9008 /* If static stack checking is enabled and done with probes,
9009 the registers need to be saved before allocating the frame. */
9012 /* Skip return address. */
9015 /* Skip pushed static chain. */
9019 /* Skip saved base pointer. */
9024 /* The traditional frame pointer location is at the top of the frame. */
9027 /* Register save area */
9031 /* On SEH target, registers are pushed just before the frame pointer
9032 location. */
9036 /* Align and set SSE register save area. */
9038 {
9039 /* The only ABI that has saved SSE registers (Win64) also has a
9040 16-byte aligned default stack, and thus we don't need to be
9041 within the re-aligned local stack frame to save them. */
9045 }
9048 /* The re-aligned stack starts here. Values before this point are not
9049 directly comparable with values below this point. In order to make
9050 sure that no value happens to be the same before and after, force
9051 the alignment computation below to add a non-zero value. */
9055 /* Va-arg area */
9059 /* Align start of frame for local function. */
9068 /* Frame pointer points here. */
9073 /* Add outgoing arguments area. Can be skipped if we eliminated
9074 all the function calls as dead code.
9075 Skipping is however impossible when function calls alloca. Alloca
9076 expander assumes that last crtl->outgoing_args_size
9077 of stack frame are unused. */
9081 {
9084 }
9085 else
9088 /* Align stack boundary. Only needed if we're calling another function
9089 or using alloca. */
9094 /* We've reached end of stack frame. */
9097 /* Size prologue needs to allocate. */
9108 {
9114 }
9115 else
9119 /* The SEH frame pointer location is near the bottom of the frame.
9120 This is enforced by the fact that the difference between the
9121 stack pointer and the frame pointer is limited to 240 bytes in
9122 the unwind data structure. */
9124 {
9125 HOST_WIDE_INT diff;
9127 /* If we can leave the frame pointer where it is, do so. Also, returns
9128 the establisher frame for __builtin_frame_address (0). */
9133 {
9134 /* Ideally we'd determine what portion of the local stack frame
9135 (within the constraint of the lowest 240) is most heavily used.
9136 But without that complication, simply bias the frame pointer
9137 by 128 bytes so as to maximize the amount of the local stack
9138 frame that is addressable with 8-bit offsets. */
9140 }
9141 }
9142 }
9144 /* This is semi-inlined memory_address_length, but simplified
9145 since we know that we're always dealing with reg+offset, and
9146 to avoid having to create and discard all that rtl. */
9150 {
9154 {
9155 /* EBP and R13 cannot be encoded without an offset. */
9157 }
9161 /* ESP and R12 must be encoded with a SIB byte. */
9163 len++;
9166 }
9168 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9169 The valid base registers are taken from CFUN->MACHINE->FS. */
9171 static rtx
9173 {
9179 {
9180 /* Choose the base register most likely to allow the most scheduling
9181 opportunities. Generally FP is valid throughout the function,
9182 while DRAP must be reloaded within the epilogue. But choose either
9183 over the SP due to increased encoding size. */
9186 {
9189 }
9191 {
9194 }
9196 {
9199 }
9200 }
9201 else
9202 {
9203 HOST_WIDE_INT toffset;
9206 /* Choose the base register with the smallest address encoding.
9207 With a tie, choose FP > DRAP > SP. */
9209 {
9213 }
9215 {
9219 {
9223 }
9224 }
9226 {
9230 {
9234 }
9235 }
9236 }
9240 }
9242 /* Emit code to save registers in the prologue. */
9244 static void
9246 {
9248 rtx insn;
9252 {
9255 }
9256 }
9258 /* Emit a single register save at CFA - CFA_OFFSET. */
9260 static void
9262 HOST_WIDE_INT cfa_offset)
9263 {
9271 /* For SSE saves, we need to indicate the 128-bit alignment. */
9282 /* When saving registers into a re-aligned local stack frame, avoid
9283 any tricky guessing by dwarf2out. */
9285 {
9289 {
9290 /* A bit of a hack. We force the DRAP register to be saved in
9291 the re-aligned stack frame, which provides us with a copy
9292 of the CFA that will last past the prologue. Install it. */
9298 }
9299 else
9300 {
9301 /* The frame pointer is a stable reference within the
9302 aligned frame. Use it. */
9309 }
9310 }
9312 /* The memory may not be relative to the current CFA register,
9313 which means that we may need to generate a new pattern for
9314 use by the unwind info. */
9316 {
9321 }
9322 }
9324 /* Emit code to save registers using MOV insns.
9325 First register is stored at CFA - CFA_OFFSET. */
9326 static void
9328 {
9333 {
9336 }
9337 }
9339 /* Emit code to save SSE registers using MOV insns.
9340 First register is stored at CFA - CFA_OFFSET. */
9341 static void
9343 {
9348 {
9351 }
9352 }
9356 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9357 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9358 Don't add the note if the previously saved value will be left untouched
9359 within stack red-zone till return, as unwinders can find the same value
9360 in the register and on the stack. */
9362 static void
9364 {
9370 {
9373 }
9374 else
9375 queued_cfa_restores
9377 }
9379 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9381 static void
9383 {
9384 rtx last;
9388 ;
9393 }
9395 /* Expand prologue or epilogue stack adjustment.
9396 The pattern exist to put a dependency on all ebp-based memory accesses.
9397 STYLE should be negative if instructions should be marked as frame related,
9398 zero if %r11 register is live and cannot be freely used and positive
9399 otherwise. */
9401 static void
9404 {
9406 rtx insn;
9413 else
9414 {
9415 rtx tmp;
9416 /* r11 is used by indirect sibcall return as well, set before the
9417 epilogue and used after the epilogue. */
9420 else
9421 {
9425 }
9431 }
9438 {
9439 rtx r;
9449 }
9451 {
9454 {
9458 }
9459 }
9462 {
9467 {
9470 }
9472 {
9475 }
9476 else
9477 {
9478 /* Else there are two possibilities: SP itself, which we set
9479 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9480 taken care of this by hand along the eh_return path. */
9483 }
9487 }
9488 }
9490 /* Find an available register to be used as dynamic realign argument
9491 pointer regsiter. Such a register will be written in prologue and
9492 used in begin of body, so it must not be
9493 1. parameter passing register.
9494 2. GOT pointer.
9495 We reuse static-chain register if it is available. Otherwise, we
9496 use DI for i386 and R13 for x86-64. We chose R13 since it has
9497 shorter encoding.
9499 Return: the regno of chosen register. */
9501 static unsigned int
9503 {
9507 {
9508 /* Use R13 for nested function or function need static chain.
9509 Since function with tail call may use any caller-saved
9510 registers in epilogue, DRAP must not use caller-saved
9511 register in such case. */
9516 }
9517 else
9518 {
9519 /* Use DI for nested function or function need static chain.
9520 Since function with tail call may use any caller-saved
9521 registers in epilogue, DRAP must not use caller-saved
9522 register in such case. */
9526 /* Reuse static chain register if it isn't used for parameter
9527 passing. */
9529 {
9533 }
9535 }
9536 }
9538 /* Return minimum incoming stack alignment. */
9540 static unsigned int
9542 {
9545 /* Prefer the one specified at command line. */
9548 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9549 if -mstackrealign is used, it isn't used for sibcall check and
9550 estimated stack alignment is 128bit. */
9552 && !TARGET_64BIT
9553 && ix86_force_align_arg_pointer
9556 else
9559 /* Incoming stack alignment can be changed on individual functions
9560 via force_align_arg_pointer attribute. We use the smallest
9561 incoming stack boundary. */
9567 /* The incoming stack frame has to be aligned at least at
9568 parm_stack_boundary. */
9572 /* Stack at entrance of main is aligned by runtime. We use the
9573 smallest incoming stack boundary. */
9581 }
9583 /* Update incoming stack boundary and estimated stack alignment. */
9585 static void
9587 {
9588 ix86_incoming_stack_boundary
9591 /* x86_64 vararg needs 16byte stack alignment for register save
9592 area. */
9597 }
9599 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9600 needed or an rtx for DRAP otherwise. */
9602 static rtx
9604 {
9609 {
9610 /* Assign DRAP to vDRAP and returns vDRAP */
9612 rtx drap_vreg;
9613 rtx arg_ptr;
9626 {
9629 }
9631 }
9632 else
9634 }
9636 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9638 static rtx
9640 {
9642 }
9645 rtx reg;
9647 };
9649 /* Return a short-lived scratch register for use on function entry.
9650 In 32-bit mode, it is valid only after the registers are saved
9651 in the prologue. This register must be released by means of
9652 release_scratch_register_on_entry once it is dead. */
9654 static void
9656 {
9662 {
9663 /* We always use R11 in 64-bit mode. */
9665 }
9666 else
9667 {
9669 bool fastcall_p
9671 bool thiscall_p
9675 int drap_regno
9678 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9679 for the static chain register. */
9683 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9684 for the static chain register. */
9689 /* ecx is the static chain register. */
9691 && !static_chain_p
9696 /* esi is the static chain register. */
9702 else
9703 {
9706 }
9707 }
9711 {
9714 }
9715 }
9717 /* Release a scratch register obtained from the preceding function. */
9719 static void
9721 {
9723 {
9727 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9733 }
9734 }
9736 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9738 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9740 static void
9742 {
9743 /* We skip the probe for the first interval + a small dope of 4 words and
9744 probe that many bytes past the specified size to maintain a protection
9745 area at the botton of the stack. */
9749 /* See if we have a constant small number of probes to generate. If so,
9750 that's the easy case. The run-time loop is made up of 11 insns in the
9751 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9752 for n # of intervals. */
9754 {
9758 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9759 values of N from 1 until it exceeds SIZE. If only one probe is
9760 needed, this will not generate any code. Then adjust and probe
9761 to PROBE_INTERVAL + SIZE. */
9763 {
9765 {
9768 }
9769 else
9776 }
9780 else
9788 /* Adjust back to account for the additional first interval. */
9792 }
9794 /* Otherwise, do the same as above, but in a loop. Note that we must be
9795 extra careful with variables wrapping around because we might be at
9796 the very top (or the very bottom) of the address space and we have
9797 to be able to handle this case properly; in particular, we use an
9798 equality test for the loop condition. */
9799 else
9800 {
9801 HOST_WIDE_INT rounded_size;
9807 /* Step 1: round SIZE to the previous multiple of the interval. */
9812 /* Step 2: compute initial and final value of the loop counter. */
9814 /* SP = SP_0 + PROBE_INTERVAL. */
9819 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9823 stack_pointer_rtx)));
9826 /* Step 3: the loop
9828 while (SP != LAST_ADDR)
9829 {
9830 SP = SP + PROBE_INTERVAL
9831 probe at SP
9832 }
9834 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9835 values of N from 1 until it is equal to ROUNDED_SIZE. */
9840 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9841 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9844 {
9849 }
9851 /* Adjust back to account for the additional first interval. */
9857 }
9861 /* Even if the stack pointer isn't the CFA register, we need to correctly
9862 describe the adjustments made to it, in particular differentiate the
9863 frame-related ones from the frame-unrelated ones. */
9865 {
9878 }
9880 /* Make sure nothing is scheduled before we are done. */
9882 }
9884 /* Adjust the stack pointer up to REG while probing it. */
9888 {
9898 /* Jump to END_LAB if SP == LAST_ADDR. */
9906 /* SP = SP + PROBE_INTERVAL. */
9910 /* Probe at SP. */
9921 }
9923 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9924 inclusive. These are offsets from the current stack pointer. */
9926 static void
9928 {
9929 /* See if we have a constant small number of probes to generate. If so,
9930 that's the easy case. The run-time loop is made up of 7 insns in the
9931 generic case while the compile-time loop is made up of n insns for n #
9932 of intervals. */
9934 {
9935 HOST_WIDE_INT i;
9937 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9938 it exceeds SIZE. If only one probe is needed, this will not
9939 generate any code. Then probe at FIRST + SIZE. */
9946 }
9948 /* Otherwise, do the same as above, but in a loop. Note that we must be
9949 extra careful with variables wrapping around because we might be at
9950 the very top (or the very bottom) of the address space and we have
9951 to be able to handle this case properly; in particular, we use an
9952 equality test for the loop condition. */
9953 else
9954 {
9961 /* Step 1: round SIZE to the previous multiple of the interval. */
9966 /* Step 2: compute initial and final value of the loop counter. */
9968 /* TEST_OFFSET = FIRST. */
9971 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9975 /* Step 3: the loop
9977 while (TEST_ADDR != LAST_ADDR)
9978 {
9979 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9980 probe at TEST_ADDR
9981 }
9983 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9984 until it is equal to ROUNDED_SIZE. */
9989 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9990 that SIZE is equal to ROUNDED_SIZE. */
9995 stack_pointer_rtx,
10000 }
10002 /* Make sure nothing is scheduled before we are done. */
10004 }
10006 /* Probe a range of stack addresses from REG to END, inclusive. These are
10007 offsets from the current stack pointer. */
10011 {
10021 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10029 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10033 /* Probe at TEST_ADDR. */
10046 }
10048 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10049 to be generated in correct form. */
10050 static void
10052 {
10053 /* Check if stack realign is really needed after reload, and
10054 stores result in cfun */
10055 unsigned int incoming_stack_boundary
10064 {
10065 /* After stack_realign_needed is finalized, we can't no longer
10066 change it. */
10069 }
10071 /* If the only reason for frame_pointer_needed is that we conservatively
10072 assumed stack realignment might be needed, but in the end nothing that
10073 needed the stack alignment had been spilled, clear frame_pointer_needed
10074 and say we don't need stack realignment. */
10077 && frame_pointer_needed
10079 && flag_omit_frame_pointer
10081 && !ix86_current_function_calls_tls_descriptor
10090 {
10092 basic_block bb;
10099 HARD_FRAME_POINTER_REGNUM);
10101 {
10102 rtx insn;
10106 set_up_by_prologue))
10107 {
10111 }
10112 }
10126 }
10130 }
10132 /* Expand the prologue into a bunch of separate insns. */
10134 void
10136 {
10141 HOST_WIDE_INT allocate;
10147 /* DRAP should not coexist with stack_realign_fp */
10152 /* Initialize CFA state for before the prologue. */
10156 /* Track SP offset to the CFA. We continue tracking this after we've
10157 swapped the CFA register away from SP. In the case of re-alignment
10158 this is fudged; we're interested to offsets within the local frame. */
10165 {
10166 /* We should have already generated an error for any use of
10167 ms_hook on a nested function. */
10170 /* Check if profiling is active and we shall use profiling before
10171 prologue variant. If so sorry. */
10176 /* In ix86_asm_output_function_label we emitted:
10177 8b ff movl.s %edi,%edi
10178 55 push %ebp
10179 8b ec movl.s %esp,%ebp
10181 This matches the hookable function prologue in Win32 API
10182 functions in Microsoft Windows XP Service Pack 2 and newer.
10183 Wine uses this to enable Windows apps to hook the Win32 API
10184 functions provided by Wine.
10186 What that means is that we've already set up the frame pointer. */
10190 {
10193 /* We've decided to use the frame pointer already set up.
10194 Describe this to the unwinder by pretending that both
10195 push and mov insns happen right here.
10197 Putting the unwind info here at the end of the ms_hook
10198 is done so that we can make absolutely certain we get
10199 the required byte sequence at the start of the function,
10200 rather than relying on an assembler that can produce
10201 the exact encoding required.
10203 However it does mean (in the unpatched case) that we have
10204 a 1 insn window where the asynchronous unwind info is
10205 incorrect. However, if we placed the unwind info at
10206 its correct location we would have incorrect unwind info
10207 in the patched case. Which is probably all moot since
10208 I don't expect Wine generates dwarf2 unwind info for the
10209 system libraries that use this feature. */
10215 stack_pointer_rtx);
10223 /* Note that gen_push incremented m->fs.cfa_offset, even
10224 though we didn't emit the push insn here. */
10228 }
10229 else
10230 {
10231 /* The frame pointer is not needed so pop %ebp again.
10232 This leaves us with a pristine state. */
10234 }
10235 }
10237 /* The first insn of a function that accepts its static chain on the
10238 stack is to push the register that would be filled in by a direct
10239 call. This insn will be skipped by the trampoline. */
10241 {
10245 /* We don't want to interpret this push insn as a register save,
10246 only as a stack adjustment. The real copy of the register as
10247 a save will be done later, if needed. */
10252 }
10254 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10255 of DRAP is needed and stack realignment is really needed after reload */
10257 {
10260 /* Only need to push parameter pointer reg if it is caller saved. */
10262 {
10263 /* Push arg pointer reg */
10266 }
10268 /* Grab the argument pointer. */
10275 /* Align the stack. */
10277 stack_pointer_rtx,
10281 /* Replicate the return address on the stack so that return
10282 address can be reached via (argp - 1) slot. This is needed
10283 to implement macro RETURN_ADDR_RTX and intrinsic function
10284 expand_builtin_return_addr etc. */
10290 /* For the purposes of frame and register save area addressing,
10291 we've started over with a new frame. */
10294 }
10300 {
10301 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10302 slower on all targets. Also sdb doesn't like it. */
10306 /* Push registers now, before setting the frame pointer
10307 on SEH target. */
10309 && TARGET_SEH
10311 {
10315 }
10318 {
10326 }
10327 }
10330 {
10331 /* If saving registers via PUSH, do so now. */
10333 {
10337 }
10339 /* When using red zone we may start register saving before allocating
10340 the stack frame saving one cycle of the prologue. However, avoid
10341 doing this if we have to probe the stack; at least on x86_64 the
10342 stack probe can turn into a call that clobbers a red zone location. */
10344 && (! TARGET_STACK_PROBE
10346 {
10349 }
10350 }
10353 {
10357 /* The computation of the size of the re-aligned stack frame means
10358 that we must allocate the size of the register save area before
10359 performing the actual alignment. Otherwise we cannot guarantee
10360 that there's enough storage above the realignment point. */
10367 /* Align the stack. */
10369 stack_pointer_rtx,
10372 /* For the purposes of register save area addressing, the stack
10373 pointer is no longer valid. As for the value of sp_offset,
10374 see ix86_compute_frame_layout, which we need to match in order
10375 to pass verification of stack_pointer_offset at the end. */
10378 }
10383 {
10384 /* We start to count from ARG_POINTER. */
10387 /* If it was realigned, take into account the fake frame. */
10389 {
10396 /* This over-estimates by 1 minimal-stack-alignment-unit but
10397 mitigates that by counting in the new return address slot. */
10398 current_function_dynamic_stack_size
10400 }
10403 }
10405 /* On SEH target with very large frame size, allocate an area to save
10406 SSE registers (as the very large allocation won't be described). */
10410 {
10411 HOST_WIDE_INT sse_size =
10416 /* No need to do stack checking as the area will be immediately
10417 written. */
10424 }
10426 /* The stack has already been decremented by the instruction calling us
10427 so probe if the size is non-negative to preserve the protection area. */
10429 {
10430 /* We expect the registers to be saved when probes are used. */
10434 {
10437 }
10438 else
10439 {
10447 else
10449 }
10450 }
10453 ;
10456 {
10460 }
10461 else
10462 {
10475 /* Note that SEH directives need to continue tracking the stack
10476 pointer even after the frame pointer has been set up. */
10478 {
10482 {
10486 }
10487 }
10490 {
10495 {
10499 }
10500 }
10505 /* Use the fact that AX still contains ALLOCATE. */
10507 ? gen_pro_epilogue_adjust_stack_di_sub
10514 {
10522 }
10525 /* Use stack_pointer_rtx for relative addressing so that code
10526 works for realigned stack, too. */
10528 {
10536 }
10538 {
10543 }
10544 }
10547 /* If we havn't already set up the frame pointer, do so now. */
10549 {
10561 }
10572 {
10579 }
10582 {
10584 {
10586 {
10596 label));
10600 }
10601 else
10603 }
10604 else
10605 {
10609 }
10610 }
10612 /* In the pic_reg_used case, make sure that the got load isn't deleted
10613 when mcount needs it. Blockage to avoid call movement across mcount
10614 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10615 note. */
10620 {
10621 /* vDRAP is setup but after reload it turns out stack realign
10622 isn't necessary, here we will emit prologue to setup DRAP
10623 without stack realign adjustment */
10626 }
10628 /* Prevent instructions from being scheduled into register save push
10629 sequence when access to the redzone area is done through frame pointer.
10630 The offset between the frame pointer and the stack pointer is calculated
10631 relative to the value of the stack pointer at the end of the function
10632 prologue, and moving instructions that access redzone area via frame
10633 pointer inside push sequence violates this assumption. */
10637 /* Emit cld instruction if stringops are used in the function. */
10641 /* SEH requires that the prologue end within 256 bytes of the start of
10642 the function. Prevent instruction schedules that would extend that.
10643 Further, prevent alloca modifications to the stack pointer from being
10644 combined with prologue modifications. */
10647 }
10649 /* Emit code to restore REG using a POP insn. */
10651 static void
10653 {
10662 {
10663 /* Previously we'd represented the CFA as an expression
10664 like *(%ebp - 8). We've just popped that value from
10665 the stack, which means we need to reset the CFA to
10666 the drap register. This will remain until we restore
10667 the stack pointer. */
10671 /* This means that the DRAP register is valid for addressing too. */
10674 }
10677 {
10684 }
10686 /* When the frame pointer is the CFA, and we pop it, we are
10687 swapping back to the stack pointer as the CFA. This happens
10688 for stack frames that don't allocate other data, so we assume
10689 the stack pointer is now pointing at the return address, i.e.
10690 the function entry state, which makes the offset be 1 word. */
10692 {
10695 {
10703 }
10704 }
10705 }
10707 /* Emit code to restore saved registers using POP insns. */
10709 static void
10711 {
10717 }
10719 /* Emit code and notes for the LEAVE instruction. */
10721 static void
10723 {
10735 {
10743 }
10746 }
10748 /* Emit code to restore saved registers using MOV insns.
10749 First register is restored from CFA - CFA_OFFSET. */
10750 static void
10753 {
10759 {
10768 {
10769 /* Previously we'd represented the CFA as an expression
10770 like *(%ebp - 8). We've just popped that value from
10771 the stack, which means we need to reset the CFA to
10772 the drap register. This will remain until we restore
10773 the stack pointer. */
10777 /* This means that the DRAP register is valid for addressing. */
10779 }
10780 else
10784 }
10785 }
10787 /* Emit code to restore saved registers using MOV insns.
10788 First register is restored from CFA - CFA_OFFSET. */
10789 static void
10792 {
10797 {
10799 rtx mem;
10809 }
10810 }
10812 /* Restore function stack, frame, and registers. */
10814 void
10816 {
10832 /* The FP must be valid if the frame pointer is present. */
10837 /* We must have *some* valid pointer to the stack frame. */
10840 /* The DRAP is never valid at this point. */
10843 /* See the comment about red zone and frame
10844 pointer usage in ix86_expand_prologue. */
10851 /* Determine the CFA offset of the end of the red-zone. */
10854 {
10855 /* The red-zone begins below the return address. */
10858 /* When the register save area is in the aligned portion of
10859 the stack, determine the maximum runtime displacement that
10860 matches up with the aligned frame. */
10864 }
10866 /* Special care must be taken for the normal return case of a function
10867 using eh_return: the eax and edx registers are marked as saved, but
10868 not restored along this path. Adjust the save location to match. */
10872 /* EH_RETURN requires the use of moves to function properly. */
10875 /* SEH requires the use of pops to identify the epilogue. */
10878 /* If we're only restoring one register and sp is not valid then
10879 using a move instruction to restore the register since it's
10880 less work than reloading sp and popping the register. */
10893 && TARGET_USE_LEAVE
10897 else
10901 {
10902 /* Ensure that the entire register save area is addressable via
10903 the stack pointer, if we will restore via sp. */
10908 {
10912 style,
10914 }
10915 }
10917 /* If there are any SSE registers to restore, then we have to do it
10918 via moves, since there's obviously no pop for SSE regs. */
10924 {
10925 rtx t;
10930 /* eh_return epilogues need %ecx added to the stack pointer. */
10932 {
10935 /* Stack align doesn't work with eh_return. */
10937 /* Neither does regparm nested functions. */
10941 {
10949 /* Note that we use SA as a temporary CFA, as the return
10950 address is at the proper place relative to it. We
10951 pretend this happens at the FP restore insn because
10952 prior to this insn the FP would be stored at the wrong
10953 offset relative to SA, and after this insn we have no
10954 other reasonable register to use for the CFA. We don't
10955 bother resetting the CFA to the SP for the duration of
10956 the return insn. */
10969 }
10970 else
10971 {
10979 {
10983 UNITS_PER_WORD));
10985 }
10986 }
10989 }
10990 }
10991 else
10992 {
10993 /* SEH requires that the function end with (1) a stack adjustment
10994 if necessary, (2) a sequence of pops, and (3) a return or
10995 jump instruction. Prevent insns from the function body from
10996 being scheduled into this sequence. */
10998 {
10999 /* Prevent a catch region from being adjacent to the standard
11000 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11001 several other flags that would be interesting to test are
11002 not yet set up. */
11005 else
11007 }
11009 /* First step is to deallocate the stack frame so that we can
11010 pop the registers. Also do it on SEH target for very large
11011 frame as the emitted instructions aren't allowed by the ABI in
11012 epilogues. */
11014 || (TARGET_SEH
11017 {
11022 }
11024 {
11028 style,
11030 }
11033 }
11035 /* If we used a stack pointer and haven't already got rid of it,
11036 then do so now. */
11038 {
11039 /* If the stack pointer is valid and pointing at the frame
11040 pointer store address, then we only need a pop. */
11043 /* Leave results in shorter dependency chains on CPUs that are
11044 able to grok it fast. */
11049 else
11050 {
11052 hard_frame_pointer_rtx,
11055 }
11056 }
11059 {
11061 rtx insn;
11087 }
11089 /* At this point the stack pointer must be valid, and we must have
11090 restored all of the registers. We may not have deallocated the
11091 entire stack frame. We've delayed this until now because it may
11092 be possible to merge the local stack deallocation with the
11093 deallocation forced by ix86_static_chain_on_stack. */
11098 {
11102 }
11103 else
11106 /* Sibcall epilogues don't want a return instruction. */
11108 {
11111 }
11114 {
11117 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11118 address, do explicit add, and jump indirectly to the caller. */
11121 {
11123 rtx insn;
11125 /* There is no "pascal" calling convention in any 64bit ABI. */
11141 }
11142 else
11144 }
11145 else
11148 /* Restore the state back to the state from the prologue,
11149 so that it's correct for the next epilogue. */
11151 }
11153 /* Reset from the function's potential modifications. */
11155 static void
11157 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11158 {
11161 #if TARGET_MACHO
11162 /* Mach-O doesn't support labels at the end of objects, so if
11163 it looks like we might want one, insert a NOP. */
11164 {
11170 {
11171 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11172 notes only, instead set their CODE_LABEL_NUMBER to -1,
11173 otherwise there would be code generation differences
11174 in between -g and -g0. */
11178 }
11188 }
11189 #endif
11191 }
11193 /* Return a scratch register to use in the split stack prologue. The
11194 split stack prologue is used for -fsplit-stack. It is the first
11195 instructions in the function, even before the regular prologue.
11196 The scratch register can be any caller-saved register which is not
11197 used for parameters or for the static chain. */
11199 static unsigned int
11201 {
11204 else
11205 {
11218 {
11220 {
11224 }
11226 }
11228 {
11232 }
11234 {
11237 else
11238 {
11240 {
11244 }
11246 }
11247 }
11248 else
11249 {
11250 /* FIXME: We could make this work by pushing a register
11251 around the addition and comparison. */
11254 }
11255 }
11256 }
11258 /* A SYMBOL_REF for the function which allocates new stackspace for
11259 -fsplit-stack. */
11263 /* A SYMBOL_REF for the more stack function when using the large
11264 model. */
11268 /* Handle -fsplit-stack. These are the first instructions in the
11269 function, even before the regular prologue. */
11271 void
11273 {
11275 HOST_WIDE_INT allocate;
11280 rtx fn;
11288 /* This is the label we will branch to if we have enough stack
11289 space. We expect the basic block reordering pass to reverse this
11290 branch if optimizing, so that we branch in the unlikely case. */
11293 /* We need to compare the stack pointer minus the frame size with
11294 the stack boundary in the TCB. The stack boundary always gives
11295 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11296 can compare directly. Otherwise we need to do an addition. */
11299 UNSPEC_STACK_CHECK);
11304 else
11305 {
11307 rtx offset;
11309 /* We need a scratch register to hold the stack pointer minus
11310 the required frame size. Since this is the very start of the
11311 function, the scratch register can be any caller-saved
11312 register which is not used for parameters. */
11319 {
11320 /* We don't use ix86_gen_add3 in this case because it will
11321 want to split to lea, but when not optimizing the insn
11322 will not be split after this point. */
11325 offset)));
11326 }
11327 else
11328 {
11331 stack_pointer_rtx));
11332 }
11334 }
11340 /* Mark the jump as very likely to be taken. */
11348 /* Get more stack space. We pass in the desired stack space and the
11349 size of the arguments to copy to the new stack. In 32-bit mode
11350 we push the parameters; __morestack will return on a new stack
11351 anyhow. In 64-bit mode we pass the parameters in r10 and
11352 r11. */
11357 {
11363 /* If this function uses a static chain, it will be in %r10.
11364 Preserve it across the call to __morestack. */
11366 {
11367 rtx rax;
11372 }
11375 {
11376 HOST_WIDE_INT argval;
11379 /* When using the large model we need to load the address
11380 into a register, and we've run out of registers. So we
11381 switch to a different calling convention, and we call a
11382 different function: __morestack_large. We pass the
11383 argument size in the upper 32 bits of r10 and pass the
11384 frame size in the lower 32 bits. */
11389 split_stack_fn_large =
11393 {
11403 UNSPEC_GOT);
11409 }
11410 else
11417 }
11418 else
11419 {
11423 }
11426 }
11427 else
11428 {
11431 }
11437 /* In order to make call/return prediction work right, we now need
11438 to execute a return instruction. See
11439 libgcc/config/i386/morestack.S for the details on how this works.
11441 For flow purposes gcc must not see this as a return
11442 instruction--we need control flow to continue at the subsequent
11443 label. Therefore, we use an unspec. */
11447 /* If we are in 64-bit mode and this function uses a static chain,
11448 we saved %r10 in %rax before calling _morestack. */
11453 /* If this function calls va_start, we need to store a pointer to
11454 the arguments on the old stack, because they may not have been
11455 all copied to the new stack. At this point the old stack can be
11456 found at the frame pointer value used by __morestack, because
11457 __morestack has set that up before calling back to us. Here we
11458 store that pointer in a scratch register, and in
11459 ix86_expand_prologue we store the scratch register in a stack
11460 slot. */
11462 {
11464 rtx frame_reg;
11471 /* 64-bit:
11472 fp -> old fp value
11473 return address within this function
11474 return address of caller of this function
11475 stack arguments
11476 So we add three words to get to the stack arguments.
11478 32-bit:
11479 fp -> old fp value
11480 return address within this function
11481 first argument to __morestack
11482 second argument to __morestack
11483 return address of caller of this function
11484 stack arguments
11485 So we add five words to get to the stack arguments.
11486 */
11497 }
11502 /* If this function calls va_start, we now have to set the scratch
11503 register for the case where we do not call __morestack. In this
11504 case we need to set it based on the stack pointer. */
11506 {
11513 }
11514 }
11516 /* We may have to tell the dataflow pass that the split stack prologue
11517 is initializing a scratch register. */
11519 static void
11521 {
11523 {
11526 }
11527 }
11528 \f
11529 /* Extract the parts of an RTL expression that is a valid memory address
11530 for an instruction. Return 0 if the structure of the address is
11531 grossly off. Return -1 if the address contains ASHIFT, so it is not
11532 strictly valid, but still used for computing length of lea instruction. */
11534 int
11536 {
11541 rtx tmp;
11545 /* Allow zero-extended SImode addresses,
11546 they will be emitted with addr32 prefix. */
11548 {
11551 {
11555 }
11558 {
11565 }
11566 }
11568 /* Allow SImode subregs of DImode addresses,
11569 they will be emitted with addr32 prefix. */
11571 {
11574 {
11578 }
11579 }
11584 {
11587 else
11589 }
11591 {
11596 do
11597 {
11602 }
11609 {
11612 {
11637 /* FALLTHRU */
11641 && TARGET_TLS_DIRECT_SEG_REFS
11644 else
11651 /* FALLTHRU */
11658 else
11673 }
11674 }
11675 }
11677 {
11680 }
11682 {
11683 /* We're called for lea too, which implements ashift on occasion. */
11693 }
11694 else
11698 {
11700 ;
11703 ;
11704 else
11706 }
11708 /* Extract the integral value of scale. */
11710 {
11714 }
11719 /* Avoid useless 0 displacement. */
11723 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11728 {
11729 rtx tmp;
11732 }
11734 /* Special case: %ebp cannot be encoded as a base without a displacement.
11735 Similarly %r13. */
11737 && base_reg
11746 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11747 Avoid this by transforming to [%esi+0].
11748 Reload calls address legitimization without cfun defined, so we need
11749 to test cfun for being non-NULL. */
11755 /* Special case: encode reg+reg instead of reg*2. */
11759 /* Special case: scaling cannot be encoded without base or displacement. */
11770 }
11771 \f
11772 /* Return cost of the memory address x.
11773 For i386, it is better to use a complex address than let gcc copy
11774 the address into a reg and make a new pseudo. But not if the address
11775 requires to two regs - that would mean more pseudos with longer
11776 lifetimes. */
11777 static int
11779 addr_space_t as ATTRIBUTE_UNUSED,
11781 {
11793 /* Attempt to minimize number of registers in the address. */
11799 cost++;
11806 cost++;
11808 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11809 since it's predecode logic can't detect the length of instructions
11810 and it degenerates to vector decoded. Increase cost of such
11811 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11812 to split such addresses or even refuse such addresses at all.
11814 Following addressing modes are affected:
11815 [base+scale*index]
11816 [scale*index+disp]
11817 [base+index]
11819 The first and last case may be avoidable by explicitly coding the zero in
11820 memory address, but I don't have AMD-K6 machine handy to check this
11821 theory. */
11830 }
11831 \f
11832 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11833 this is used for to form addresses to local data when -fPIC is in
11834 use. */
11836 static bool
11838 {
11841 }
11843 /* Determine if a given RTX is a valid constant. We already know this
11844 satisfies CONSTANT_P. */
11846 static bool
11848 {
11850 {
11855 {
11859 }
11864 /* Only some unspecs are valid as "constants". */
11867 {
11883 }
11885 /* We must have drilled down to a symbol. */
11890 /* FALLTHRU */
11893 /* TLS symbols are never valid. */
11897 /* DLLIMPORT symbols are never valid. */
11902 #if TARGET_MACHO
11903 /* mdynamic-no-pic */
11906 #endif
11922 }
11924 /* Otherwise we handle everything else in the move patterns. */
11926 }
11928 /* Determine if it's legal to put X into the constant pool. This
11929 is not possible for the address of thread-local symbols, which
11930 is checked above. */
11932 static bool
11934 {
11935 /* We can always put integral constants and vectors in memory. */
11937 {
11945 }
11947 }
11950 /* Nonzero if the constant value X is a legitimate general operand
11951 when generating PIC code. It is given that flag_pic is on and
11952 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11954 bool
11956 {
11957 rtx inner;
11960 {
11967 /* Only some unspecs are valid as "constants". */
11970 {
11983 }
11984 /* FALLTHRU */
11992 }
11993 }
11995 /* Determine if a given CONST RTX is a valid memory displacement
11996 in PIC mode. */
11998 bool
12000 {
12003 /* In 64bit mode we can allow direct addresses of symbols and labels
12004 when they are not dynamic symbols. */
12006 {
12010 {
12034 /* FALLTHRU */
12037 /* TLS references should always be enclosed in UNSPEC. */
12047 }
12048 }
12054 {
12055 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12056 of GOT tables. We should not need these anyway. */
12068 }
12072 {
12077 }
12086 {
12090 /* We need to check for both symbols and labels because VxWorks loads
12091 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12092 details. */
12096 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12097 While ABI specify also 32bit relocation but we don't produce it in
12098 small PIC model at all. */
12120 }
12123 }
12125 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12126 replace the input X, or the original X if no replacement is called for.
12127 The output parameter *WIN is 1 if the calling macro should goto WIN,
12128 0 if it should not. */
12130 bool
12135 {
12136 /* Reload can generate:
12138 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12139 (reg:DI 97))
12140 (reg:DI 2 cx))
12142 This RTX is rejected from ix86_legitimate_address_p due to
12143 non-strictness of base register 97. Following this rejection,
12144 reload pushes all three components into separate registers,
12145 creating invalid memory address RTX.
12147 Following code reloads only the invalid part of the
12148 memory address RTX. */
12154 {
12160 {
12165 }
12169 {
12174 }
12178 }
12181 }
12183 /* Determine if op is suitable RTX for an address register.
12184 Return naked register if a register or a register subreg is
12185 found, otherwise return NULL_RTX. */
12187 static rtx
12189 {
12192 /* Only SImode or DImode registers can form the address. */
12199 {
12207 /* Don't allow SUBREGs that span more than a word. It can
12208 lead to spill failures when the register is one word out
12209 of a two word structure. */
12213 /* Allow only SUBREGs of non-eliminable hard registers. */
12216 }
12218 /* Op is not a register. */
12220 }
12222 /* Recognizes RTL expressions that are valid memory addresses for an
12223 instruction. The MODE argument is the machine mode for the MEM
12224 expression that wants to use this address.
12226 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12227 convert common non-canonical forms to canonical form so that they will
12228 be recognized. */
12230 static bool
12233 {
12236 HOST_WIDE_INT scale;
12240 /* Decomposition failed. */
12249 /* Validate base register. */
12251 {
12259 /* Base is not valid. */
12261 }
12263 /* Validate index register. */
12265 {
12273 /* Index is not valid. */
12275 }
12277 /* Index and base should have the same mode. */
12282 /* Address override works only on the (%reg) part of %fs:(%reg). */
12288 /* Validate scale factor. */
12290 {
12292 /* Scale without index. */
12296 /* Scale is not a valid multiplier. */
12298 }
12300 /* Validate displacement. */
12302 {
12307 {
12308 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12309 used. While ABI specify also 32bit relocations, we don't produce
12310 them at all and use IP relative instead. */
12317 /* 64bit address unspec. */
12337 /* Invalid address unspec. */
12339 }
12342 && (flag_pic
12343 || (TARGET_MACHO
12344 #if TARGET_MACHO
12345 && MACHOPIC_INDIRECT
12347 #endif
12348 )))
12349 {
12351 is_legitimate_pic:
12353 {
12354 /* foo@dtpoff(%rX) is ok. */
12361 /* Non-constant pic memory reference. */
12363 }
12366 /* Displacement is an invalid pic construct. */
12368 #if TARGET_MACHO
12371 /* displacment must be referenced via non_lazy_pointer */
12373 #endif
12375 /* This code used to verify that a symbolic pic displacement
12376 includes the pic_offset_table_rtx register.
12378 While this is good idea, unfortunately these constructs may
12379 be created by "adds using lea" optimization for incorrect
12380 code like:
12382 int a;
12383 int foo(int i)
12384 {
12385 return *(&a+i);
12386 }
12388 This code is nonsensical, but results in addressing
12389 GOT table with pic_offset_table_rtx base. We can't
12390 just refuse it easily, since it gets matched by
12391 "addsi3" pattern, that later gets split to lea in the
12392 case output register differs from input. While this
12393 can be handled by separate addsi pattern for this case
12394 that never results in lea, this seems to be easier and
12395 correct fix for crash to disable this test. */
12396 }
12403 /* Displacement is not constant. */
12407 /* Displacement is out of range. */
12409 /* In x32 mode, constant addresses are sign extended to 64bit, so
12410 we have to prevent addresses from 0x80000000 to 0xffffffff. */
12415 }
12417 /* Everything looks valid. */
12419 }
12421 /* Determine if a given RTX is a valid constant address. */
12423 bool
12425 {
12427 }
12428 \f
12429 /* Return a unique alias set for the GOT. */
12431 static alias_set_type
12433 {
12438 }
12440 /* Return a legitimate reference for ORIG (an address) using the
12441 register REG. If REG is 0, a new pseudo is generated.
12443 There are two types of references that must be handled:
12445 1. Global data references must load the address from the GOT, via
12446 the PIC reg. An insn is emitted to do this load, and the reg is
12447 returned.
12449 2. Static data references, constant pool addresses, and code labels
12450 compute the address as an offset from the GOT, whose base is in
12451 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12452 differentiate them from global data objects. The returned
12453 address is the PIC reg + an unspec constant.
12455 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12456 reg also appears in the address. */
12458 static rtx
12460 {
12464 #if TARGET_MACHO
12466 {
12469 /* Use the generic Mach-O PIC machinery. */
12471 }
12472 #endif
12479 {
12480 rtx tmpreg;
12481 /* This symbol may be referenced via a displacement from the PIC
12482 base address (@GOTOFF). */
12489 {
12491 UNSPEC_GOTOFF);
12493 }
12494 else
12499 else
12504 {
12508 }
12510 }
12512 {
12513 /* This symbol may be referenced via a displacement from the PIC
12514 base address (@GOTOFF). */
12521 {
12523 UNSPEC_GOTOFF);
12525 }
12526 else
12532 {
12535 }
12536 }
12538 /* We can't use @GOTOFF for text labels on VxWorks;
12539 see gotoff_operand. */
12541 {
12543 {
12549 {
12552 }
12553 }
12555 /* For x64 PE-COFF there is no GOT table. So we use address
12556 directly. */
12558 {
12566 }
12568 {
12576 /* Use directly gen_movsi, otherwise the address is loaded
12577 into register for CSE. We don't want to CSE this addresses,
12578 instead we CSE addresses from the GOT table, so skip this. */
12581 }
12582 else
12583 {
12584 /* This symbol must be referenced via a load from the
12585 Global Offset Table (@GOT). */
12601 }
12602 }
12603 else
12604 {
12607 {
12609 {
12612 }
12613 else
12615 }
12617 {
12620 /* We must match stuff we generate before. Assume the only
12621 unspecs that can get here are ours. Not that we could do
12622 anything with them anyway.... */
12628 }
12630 {
12633 /* Check first to see if this is a constant offset from a @GOTOFF
12634 symbol reference. */
12637 {
12639 {
12643 UNSPEC_GOTOFF);
12649 {
12652 }
12653 }
12654 else
12655 {
12658 {
12662 }
12663 }
12664 }
12665 else
12666 {
12669 new_rtx
12673 {
12676 {
12679 new_rtx
12681 }
12682 else
12684 }
12685 else
12686 {
12689 {
12692 }
12694 }
12695 }
12696 }
12697 }
12699 }
12700 \f
12701 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12703 static rtx
12705 {
12709 {
12714 }
12720 }
12722 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12726 static rtx
12728 {
12730 {
12736 }
12739 }
12741 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12745 rtx
12747 {
12749 {
12750 ix86_tls_module_base_symbol
12755 }
12758 }
12760 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12761 false if we expect this to be used for a memory address and true if
12762 we expect to load the address into a register. */
12764 static rtx
12766 {
12773 {
12778 {
12781 else
12782 {
12785 }
12786 }
12789 {
12792 else
12802 }
12803 else
12804 {
12808 {
12810 rtx insns;
12813 emit_call_insn
12823 }
12824 else
12826 }
12833 {
12836 else
12837 {
12840 }
12841 }
12844 {
12849 else
12855 }
12856 else
12857 {
12861 {
12866 emit_call_insn
12871 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12872 share the LD_BASE result with other LD model accesses. */
12874 UNSPEC_TLS_LD_BASE);
12878 }
12879 else
12881 }
12889 {
12896 }
12901 {
12903 {
12904 /* The Sun linker took the AMD64 TLS spec literally
12905 and can only handle %rax as destination of the
12906 initial executable code sequence. */
12911 }
12913 /* Generate DImode references to avoid %fs:(%reg32)
12914 problems and linker IE->LE relaxation bug. */
12918 }
12920 {
12925 }
12927 {
12931 }
12932 else
12933 {
12936 }
12946 {
12951 }
12952 else
12953 {
12957 }
12967 {
12971 }
12972 else
12973 {
12977 }
12982 }
12985 }
12987 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12988 to symbol DECL. */
12991 htab_t dllimport_map;
12993 static tree
12995 {
13002 tree to;
13003 rtx rtl;
13047 }
13049 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13050 true if we require the result be a register. */
13052 static rtx
13054 {
13055 tree imp_decl;
13056 rtx x;
13065 }
13067 /* Try machine-dependent ways of modifying an illegitimate address
13068 to be legitimate. If we find one, return the new, valid address.
13069 This macro is used in only one place: `memory_address' in explow.c.
13071 OLDX is the address as it was before break_out_memory_refs was called.
13072 In some cases it is useful to look at this to decide what needs to be done.
13074 It is always safe for this macro to do nothing. It exists to recognize
13075 opportunities to optimize the output.
13077 For the 80386, we handle X+REG by loading X into a register R and
13078 using R+REG. R will go in a general reg and indexing will be used.
13079 However, if REG is a broken-out memory address or multiplication,
13080 nothing needs to be done because REG can certainly go in a general reg.
13082 When -fpic is used, special handling is needed for symbolic references.
13083 See comments by legitimize_pic_address in i386.c for details. */
13085 static rtx
13088 {
13099 {
13103 }
13106 {
13113 {
13116 }
13117 }
13122 #if TARGET_MACHO
13125 #endif
13127 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13131 {
13136 }
13139 {
13140 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13145 {
13151 }
13156 {
13162 }
13164 /* Put multiply first if it isn't already. */
13166 {
13171 }
13173 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13174 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13175 created by virtual register instantiation, register elimination, and
13176 similar optimizations. */
13178 {
13184 }
13186 /* Canonicalize
13187 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13188 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13193 {
13194 rtx constant;
13198 {
13201 }
13203 {
13206 }
13207 else
13211 {
13218 }
13219 }
13225 {
13228 }
13231 {
13234 }
13242 {
13245 }
13251 {
13255 {
13258 }
13262 }
13265 {
13269 {
13272 }
13276 }
13277 }
13280 }
13281 \f
13282 /* Print an integer constant expression in assembler syntax. Addition
13283 and subtraction are the only arithmetic that may appear in these
13284 expressions. FILE is the stdio stream to write to, X is the rtx, and
13285 CODE is the operand print code from the output string. */
13287 static void
13289 {
13293 {
13302 else
13303 {
13306 /* Mark the decl as referenced so that cgraph will
13307 output the function. */
13311 #if TARGET_MACHO
13315 #endif
13317 }
13325 /* FALLTHRU */
13336 /* This used to output parentheses around the expression,
13337 but that does not work on the 386 (either ATT or BSD assembler). */
13343 {
13344 /* We can use %d if the number is <32 bits and positive. */
13349 else
13351 }
13352 else
13353 /* We can't handle floating point constants;
13354 TARGET_PRINT_OPERAND must handle them. */
13359 /* Some assemblers need integer constants to appear first. */
13361 {
13365 }
13366 else
13367 {
13372 }
13387 {
13391 }
13396 {
13415 /* FIXME: This might be @TPOFF in Sun ld too. */
13424 else
13434 else
13440 #if TARGET_MACHO
13445 #endif
13449 }
13454 }
13455 }
13457 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13458 We need to emit DTP-relative relocations. */
13460 static void ATTRIBUTE_UNUSED
13462 {
13467 {
13475 }
13476 }
13478 /* Return true if X is a representation of the PIC register. This copes
13479 with calls from ix86_find_base_term, where the register might have
13480 been replaced by a cselib value. */
13482 static bool
13484 {
13488 else
13490 }
13492 /* Helper function for ix86_delegitimize_address.
13493 Attempt to delegitimize TLS local-exec accesses. */
13495 static rtx
13497 {
13522 {
13527 }
13533 }
13535 /* In the name of slightly smaller debug output, and to cater to
13536 general assembler lossage, recognize PIC+GOTOFF and turn it back
13537 into a direct symbol reference.
13539 On Darwin, this is necessary to avoid a crash, because Darwin
13540 has a different PIC label for each routine but the DWARF debugging
13541 information is not associated with any particular routine, so it's
13542 necessary to remove references to the PIC label from RTL stored by
13543 the DWARF output code. */
13545 static rtx
13547 {
13549 /* addend is NULL or some rtx if x is something+GOTOFF where
13550 something doesn't include the PIC register. */
13552 /* reg_addend is NULL or a multiple of some register. */
13554 /* const_addend is NULL or a const_int. */
13556 /* This is the result, or NULL. */
13565 {
13572 {
13578 }
13585 {
13588 {
13593 }
13595 }
13600 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
13601 and -mcmodel=medium -fpic. */
13602 }
13609 /* %ebx + GOT/GOTOFF */
13610 ;
13612 {
13613 /* %ebx + %reg * scale + GOT/GOTOFF */
13619 else
13620 {
13623 }
13624 }
13625 else
13631 {
13634 }
13655 {
13656 /* If the rest of original X doesn't involve the PIC register, add
13657 addend and subtract pic_offset_table_rtx. This can happen e.g.
13658 for code like:
13659 leal (%ebx, %ecx, 4), %ecx
13660 ...
13661 movl foo@GOTOFF(%ecx), %edx
13662 in which case we return (%ecx - %ebx) + foo. */
13665 pic_offset_table_rtx),
13666 result);
13667 else
13669 }
13671 {
13675 }
13677 }
13679 /* If X is a machine specific address (i.e. a symbol or label being
13680 referenced as a displacement from the GOT implemented using an
13681 UNSPEC), then return the base term. Otherwise return X. */
13683 rtx
13685 {
13686 rtx term;
13689 {
13703 }
13706 }
13707 \f
13708 static void
13711 {
13715 {
13718 }
13723 {
13726 {
13745 }
13749 {
13768 }
13775 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13776 Those same assemblers have the same but opposite lossage on cmov. */
13779 else
13784 {
13797 }
13804 else
13809 {
13822 }
13829 else
13839 else
13850 }
13852 }
13854 /* Print the name of register X to FILE based on its machine mode and number.
13855 If CODE is 'w', pretend the mode is HImode.
13856 If CODE is 'b', pretend the mode is QImode.
13857 If CODE is 'k', pretend the mode is SImode.
13858 If CODE is 'q', pretend the mode is DImode.
13859 If CODE is 'x', pretend the mode is V4SFmode.
13860 If CODE is 't', pretend the mode is V8SFmode.
13861 If CODE is 'h', pretend the reg is the 'high' byte register.
13862 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13863 If CODE is 'd', duplicate the operand for AVX instruction.
13864 */
13866 void
13868 {
13877 {
13881 }
13906 else
13909 /* Irritatingly, AMD extended registers use different naming convention
13910 from the normal registers: "r%d[bwd]" */
13912 {
13917 {
13931 /* no suffix */
13936 }
13938 }
13942 {
13945 {
13948 }
13949 /* FALLTHRU */
13955 /* FALLTHRU */
13958 normal:
13973 {
13978 }
13982 }
13986 {
13989 else
13991 }
13992 }
13994 /* Locate some local-dynamic symbol still in use by this function
13995 so that we can print its name in some tls_local_dynamic_base
13996 pattern. */
13998 static int
14000 {
14005 {
14008 }
14011 }
14015 {
14016 rtx insn;
14027 }
14029 /* Meaning of CODE:
14030 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14031 C -- print opcode suffix for set/cmov insn.
14032 c -- like C, but print reversed condition
14033 F,f -- likewise, but for floating-point.
14034 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14035 otherwise nothing
14036 R -- print the prefix for register names.
14037 z -- print the opcode suffix for the size of the current operand.
14038 Z -- likewise, with special suffixes for x87 instructions.
14039 * -- print a star (in certain assembler syntax)
14040 A -- print an absolute memory reference.
14041 E -- print address with DImode register names if TARGET_64BIT.
14042 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14043 s -- print a shift double count, followed by the assemblers argument
14044 delimiter.
14045 b -- print the QImode name of the register for the indicated operand.
14046 %b0 would print %al if operands[0] is reg 0.
14047 w -- likewise, print the HImode name of the register.
14048 k -- likewise, print the SImode name of the register.
14049 q -- likewise, print the DImode name of the register.
14050 x -- likewise, print the V4SFmode name of the register.
14051 t -- likewise, print the V8SFmode name of the register.
14052 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14053 y -- print "st(0)" instead of "st" as a register.
14054 d -- print duplicated register operand for AVX instruction.
14055 D -- print condition for SSE cmp instruction.
14056 P -- if PIC, print an @PLT suffix.
14057 p -- print raw symbol name.
14058 X -- don't print any sort of PIC '@' suffix for a symbol.
14059 & -- print some in-use local-dynamic symbol name.
14060 H -- print a memory address offset by 8; used for sse high-parts
14061 Y -- print condition for XOP pcom* instruction.
14062 + -- print a branch hint as 'cs' or 'ds' prefix
14063 ; -- print a semicolon (after prefixes due to bug in older gas).
14064 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14065 @ -- print a segment register of thread base pointer load
14066 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14067 */
14069 void
14071 {
14073 {
14075 {
14078 {
14084 /* Intel syntax. For absolute addresses, registers should not
14085 be surrounded by braces. */
14087 {
14092 }
14097 }
14103 /* Wrap address in an UNSPEC to declare special handling. */
14141 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14146 {
14160 output_operand_lossage
14163 }
14166 #endif
14171 {
14172 /* Opcodes don't get size suffixes if using Intel opcodes. */
14177 {
14195 output_operand_lossage
14198 }
14199 }
14202 warning
14204 /* FALLTHRU */
14207 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14212 {
14214 {
14216 #ifdef HAVE_AS_IX86_FILDS
14218 #endif
14226 #ifdef HAVE_AS_IX86_FILDQ
14228 #else
14230 #endif
14235 }
14236 }
14238 {
14239 /* 387 opcodes don't get size suffixes
14240 if the operands are registers. */
14245 {
14261 }
14262 }
14263 else
14264 {
14265 output_operand_lossage
14268 }
14270 output_operand_lossage
14290 {
14293 }
14298 {
14349 }
14353 /* Little bit of braindamage here. The SSE compare instructions
14354 does use completely different names for the comparisons that the
14355 fp conditional moves. */
14357 {
14360 {
14363 }
14369 {
14372 }
14378 {
14381 }
14390 {
14393 }
14399 {
14402 }
14408 {
14411 }
14422 }
14427 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14430 #endif
14435 {
14439 }
14443 file);
14448 {
14452 }
14453 /* It doesn't actually matter what mode we use here, as we're
14454 only going to use this for printing. */
14462 #ifdef HAVE_AS_IX86_HLE
14464 #else
14466 #endif
14468 #ifdef HAVE_AS_IX86_HLE
14470 #else
14472 #endif
14473 /* We do not want to print value of the operand. */
14482 {
14487 else
14490 }
14493 {
14494 rtx x;
14503 {
14508 {
14510 bool cputaken
14513 /* Emit hints only in the case default branch prediction
14514 heuristics would fail. */
14516 {
14517 /* We use 3e (DS) prefix for taken branches and
14518 2e (CS) prefix for not taken branches. */
14521 else
14523 }
14524 }
14525 }
14527 }
14530 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14532 #endif
14539 /* The kernel uses a different segment register for performance
14540 reasons; a system call would not have to trash the userspace
14541 segment register, which would be expensive. */
14544 else
14559 }
14560 }
14566 {
14567 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14570 {
14573 {
14582 else
14588 }
14590 /* Check for explicit size override (codes 'b', 'w', 'k',
14591 'q' and 'x') */
14605 }
14608 /* Avoid (%rip) for call operands. */
14614 else
14616 }
14619 {
14620 REAL_VALUE_TYPE r;
14628 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14632 else
14634 }
14637 {
14638 REAL_VALUE_TYPE r;
14647 }
14649 /* These float cases don't actually occur as immediate operands. */
14651 {
14656 }
14658 else
14659 {
14660 /* We have patterns that allow zero sets of memory, for instance.
14661 In 64-bit mode, we should probably support all 8-byte vectors,
14662 since we can in fact encode that into an immediate. */
14664 {
14667 }
14670 {
14672 {
14675 }
14678 {
14681 else
14683 }
14684 }
14689 else
14691 }
14692 }
14694 static bool
14696 {
14699 }
14700 \f
14701 /* Print a memory operand whose address is ADDR. */
14703 static void
14705 {
14714 {
14721 }
14723 {
14727 }
14728 else
14739 {
14750 }
14752 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14754 {
14766 }
14768 {
14769 /* Displacement only requires special attention. */
14772 {
14776 }
14779 else
14781 }
14782 else
14783 {
14784 /* Print SImode register names to force addr32 prefix. */
14786 {
14787 #ifdef ENABLE_CHECKING
14790 {
14801 }
14802 #endif
14805 }
14807 && TARGET_X32
14808 && disp
14811 {
14812 /* X32 runs in 64-bit mode, where displacement, DISP, in
14813 address DISP(%r64), is encoded as 32-bit immediate sign-
14814 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14815 address is %r64 + 0xffffffffbffffd00. When %r64 <
14816 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14817 which is invalid for x32. The correct address is %r64
14818 - 0x40000300 == 0xf7ffdd64. To properly encode
14819 -0x40000300(%r64) for x32, we zero-extend negative
14820 displacement by forcing addr32 prefix which truncates
14821 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14822 zero-extend all negative displacements, including -1(%rsp).
14823 However, for small negative displacements, sign-extension
14824 won't cause overflow. We only zero-extend negative
14825 displacements if they < -16*1024*1024, which is also used
14826 to check legitimate address displacements for PIC. */
14828 }
14831 {
14833 {
14838 else
14840 }
14846 {
14851 }
14853 }
14854 else
14855 {
14859 {
14860 /* Pull out the offset of a symbol; print any symbol itself. */
14864 {
14868 }
14876 else
14878 }
14882 {
14885 {
14889 }
14890 }
14893 else
14897 {
14902 }
14904 }
14905 }
14906 }
14908 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14910 static bool
14912 {
14913 rtx op;
14920 {
14923 /* FIXME: This might be @TPOFF in Sun ld. */
14934 else
14946 else
14953 #if TARGET_MACHO
14959 #endif
14962 {
14967 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14969 #else
14971 #endif
14974 }
14979 }
14982 }
14983 \f
14984 /* Split one or more double-mode RTL references into pairs of half-mode
14985 references. The RTL can be REG, offsettable MEM, integer constant, or
14986 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14987 split and "num" is its length. lo_half and hi_half are output arrays
14988 that parallel "operands". */
14990 void
14993 {
14998 {
15007 }
15012 {
15015 /* simplify_subreg refuse to split volatile memory addresses,
15016 but we still have to handle it. */
15018 {
15021 }
15022 else
15023 {
15030 }
15031 }
15032 }
15033 \f
15034 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15035 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15036 is the expression of the binary operation. The output may either be
15037 emitted here, or returned to the caller, like all output_* functions.
15039 There is no guarantee that the operands are the same mode, as they
15040 might be within FLOAT or FLOAT_EXTEND expressions. */
15042 #ifndef SYSV386_COMPAT
15043 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15044 wants to fix the assemblers because that causes incompatibility
15045 with gcc. No-one wants to fix gcc because that causes
15046 incompatibility with assemblers... You can use the option of
15047 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15048 #define SYSV386_COMPAT 1
15049 #endif
15053 {
15059 #ifdef ENABLE_CHECKING
15060 /* Even if we do not want to check the inputs, this documents input
15061 constraints. Which helps in understanding the following code. */
15071 else
15073 #endif
15076 {
15081 else
15090 else
15099 else
15108 else
15115 }
15118 {
15120 {
15124 else
15126 }
15127 else
15128 {
15132 else
15134 }
15136 }
15140 {
15144 {
15148 }
15150 /* know operands[0] == operands[1]. */
15153 {
15156 }
15159 {
15161 /* How is it that we are storing to a dead operand[2]?
15162 Well, presumably operands[1] is dead too. We can't
15163 store the result to st(0) as st(0) gets popped on this
15164 instruction. Instead store to operands[2] (which I
15165 think has to be st(1)). st(1) will be popped later.
15166 gcc <= 2.8.1 didn't have this check and generated
15167 assembly code that the Unixware assembler rejected. */
15169 else
15172 }
15176 else
15183 {
15186 }
15189 {
15192 }
15195 {
15196 #if SYSV386_COMPAT
15197 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15198 derived assemblers, confusingly reverse the direction of
15199 the operation for fsub{r} and fdiv{r} when the
15200 destination register is not st(0). The Intel assembler
15201 doesn't have this brain damage. Read !SYSV386_COMPAT to
15202 figure out what the hardware really does. */
15205 else
15207 #else
15209 /* As above for fmul/fadd, we can't store to st(0). */
15211 else
15213 #endif
15215 }
15218 {
15219 #if SYSV386_COMPAT
15222 else
15224 #else
15227 else
15229 #endif
15231 }
15234 {
15237 else
15240 }
15242 {
15243 #if SYSV386_COMPAT
15245 #else
15247 #endif
15248 }
15249 else
15250 {
15251 #if SYSV386_COMPAT
15253 #else
15255 #endif
15256 }
15261 }
15265 }
15267 /* Check if a 256bit AVX register is referenced inside of EXP. */
15269 static int
15271 {
15282 }
15284 /* Return needed mode for entity in optimize_mode_switching pass. */
15286 static int
15288 {
15290 {
15291 rtx link;
15293 /* Needed mode is set to AVX_U128_CLEAN if there are
15294 no 256bit modes used in function arguments. */
15296 link;
15298 {
15300 {
15305 }
15306 }
15309 }
15311 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15312 changes state only when a 256bit register is written to, but we need
15313 to prevent the compiler from moving optimal insertion point above
15314 eventual read from 256bit register. */
15319 }
15321 /* Return mode that i387 must be switched into
15322 prior to the execution of insn. */
15324 static int
15326 {
15329 /* The mode UNINITIALIZED is used to store control word after a
15330 function call or ASM pattern. The mode ANY specify that function
15331 has no requirements on the control word and make no changes in the
15332 bits we are interested in. */
15346 {
15369 }
15372 }
15374 /* Return mode that entity must be switched into
15375 prior to the execution of insn. */
15377 int
15379 {
15381 {
15391 }
15393 }
15395 /* Check if a 256bit AVX register is referenced in stores. */
15397 static void
15399 {
15401 {
15404 }
15405 }
15407 /* Calculate mode of upper 128bit AVX registers after the insn. */
15409 static int
15411 {
15418 /* We know that state is clean after CALL insn if there are no
15419 256bit registers used in the function return register. */
15421 {
15426 }
15428 /* Otherwise, return current mode. Remember that if insn
15429 references AVX 256bit registers, the mode was already changed
15430 to DIRTY from MODE_NEEDED. */
15432 }
15434 /* Return the mode that an insn results in. */
15436 int
15438 {
15440 {
15450 }
15451 }
15453 static int
15455 {
15456 tree arg;
15458 /* Entry mode is set to AVX_U128_DIRTY if there are
15459 256bit modes used in function arguments. */
15462 {
15467 }
15470 }
15472 /* Return a mode that ENTITY is assumed to be
15473 switched to at function entry. */
15475 int
15477 {
15479 {
15489 }
15490 }
15492 static int
15494 {
15497 /* Exit mode is set to AVX_U128_DIRTY if there are
15498 256bit modes used in the function return register. */
15503 }
15505 /* Return a mode that ENTITY is assumed to be
15506 switched to at function exit. */
15508 int
15510 {
15512 {
15522 }
15523 }
15525 /* Output code to initialize control word copies used by trunc?f?i and
15526 rounding patterns. CURRENT_MODE is set to current control word,
15527 while NEW_MODE is set to new control word. */
15529 static void
15531 {
15533 rtx new_mode;
15544 {
15546 {
15548 /* round toward zero (truncate) */
15554 /* round down toward -oo */
15561 /* round up toward +oo */
15568 /* mask precision exception for nearbyint() */
15575 }
15576 }
15577 else
15578 {
15580 {
15582 /* round toward zero (truncate) */
15588 /* round down toward -oo */
15594 /* round up toward +oo */
15600 /* mask precision exception for nearbyint() */
15607 }
15608 }
15614 }
15616 /* Emit vzeroupper. */
15618 void
15620 {
15623 /* Cancel automatic vzeroupper insertion if there are
15624 live call-saved SSE registers at the insertion point. */
15636 }
15638 /* Generate one or more insns to set ENTITY to MODE. */
15640 void
15642 {
15644 {
15659 }
15660 }
15662 /* Output code for INSN to convert a float to a signed int. OPERANDS
15663 are the insn operands. The output may be [HSD]Imode and the input
15664 operand may be [SDX]Fmode. */
15668 {
15673 /* Jump through a hoop or two for DImode, since the hardware has no
15674 non-popping instruction. We used to do this a different way, but
15675 that was somewhat fragile and broke with post-reload splitters. */
15685 else
15686 {
15691 else
15695 }
15698 }
15700 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15701 have the values zero or one, indicates the ffreep insn's operand
15702 from the OPERANDS array. */
15706 {
15708 #ifdef HAVE_AS_IX86_FFREEP
15710 #else
15711 {
15721 }
15722 #endif
15725 }
15728 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15729 should be used. UNORDERED_P is true when fucom should be used. */
15733 {
15739 {
15742 }
15743 else
15744 {
15747 }
15750 {
15754 else
15756 else
15759 else
15761 }
15768 {
15770 {
15773 }
15774 else
15776 }
15779 && stack_top_dies
15782 {
15783 /* If both the top of the 387 stack dies, and the other operand
15784 is also a stack register that dies, then this must be a
15785 `fcompp' float compare */
15788 {
15789 /* There is no double popping fcomi variant. Fortunately,
15790 eflags is immune from the fstp's cc clobbering. */
15793 else
15796 }
15797 else
15798 {
15801 else
15803 }
15804 }
15805 else
15806 {
15807 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15810 {
15818 NULL,
15819 NULL,
15826 NULL,
15827 NULL,
15828 NULL,
15829 NULL
15830 };
15845 }
15846 }
15848 void
15850 {
15853 #ifdef ASM_QUAD
15856 #else
15858 #endif
15861 }
15863 void
15865 {
15868 #ifdef ASM_QUAD
15871 #else
15873 #endif
15874 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15880 #if TARGET_MACHO
15882 {
15886 }
15887 #endif
15888 else
15891 }
15892 \f
15893 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15894 for the target. */
15896 void
15898 {
15899 rtx tmp;
15901 /* We play register width games, which are only valid after reload. */
15904 /* Avoid HImode and its attendant prefix byte. */
15909 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15911 {
15914 }
15917 }
15919 /* X is an unchanging MEM. If it is a constant pool reference, return
15920 the constant pool rtx, else NULL. */
15922 rtx
15924 {
15931 }
15933 void
15935 {
15943 {
15946 {
15952 }
15956 }
15960 {
15973 {
15980 }
15981 }
15985 {
15987 {
15988 #if TARGET_MACHO
15989 /* dynamic-no-pic */
15991 {
15992 rtx temp = ((reload_in_progress
16000 }
16002 {
16006 }
16009 else
16010 {
16018 }
16019 /* dynamic-no-pic */
16020 #endif
16021 }
16022 else
16023 {
16027 {
16033 }
16034 }
16035 }
16036 else
16037 {
16048 /* Force large constants in 64bit compilation into register
16049 to get them CSEed. */
16061 {
16062 /* If we are loading a floating point constant to a register,
16063 force the value to memory now, since we'll get better code
16064 out the back end. */
16068 {
16073 }
16074 }
16075 }
16078 }
16080 void
16082 {
16086 /* Force constants other than zero into memory. We do not know how
16087 the instructions used to build constants modify the upper 64 bits
16088 of the register, once we have that information we may be able
16089 to handle some of them more efficiently. */
16098 /* We need to check memory alignment for SSE mode since attribute
16099 can make operands unaligned. */
16104 {
16107 /* ix86_expand_vector_move_misalign() does not like constants ... */
16113 /* ... nor both arguments in memory. */
16121 }
16123 /* Make operand1 a register if it isn't already. */
16127 {
16130 }
16133 }
16135 /* Split 32-byte AVX unaligned load and store if needed. */
16137 static void
16139 {
16140 rtx m;
16147 {
16168 }
16171 {
16173 {
16180 }
16181 else
16183 }
16185 {
16187 {
16192 }
16193 else
16195 }
16196 else
16198 }
16200 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16201 straight to ix86_expand_vector_move. */
16202 /* Code generation for scalar reg-reg moves of single and double precision data:
16203 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16204 movaps reg, reg
16205 else
16206 movss reg, reg
16207 if (x86_sse_partial_reg_dependency == true)
16208 movapd reg, reg
16209 else
16210 movsd reg, reg
16212 Code generation for scalar loads of double precision data:
16213 if (x86_sse_split_regs == true)
16214 movlpd mem, reg (gas syntax)
16215 else
16216 movsd mem, reg
16218 Code generation for unaligned packed loads of single precision data
16219 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16220 if (x86_sse_unaligned_move_optimal)
16221 movups mem, reg
16223 if (x86_sse_partial_reg_dependency == true)
16224 {
16225 xorps reg, reg
16226 movlps mem, reg
16227 movhps mem+8, reg
16228 }
16229 else
16230 {
16231 movlps mem, reg
16232 movhps mem+8, reg
16233 }
16235 Code generation for unaligned packed loads of double precision data
16236 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16237 if (x86_sse_unaligned_move_optimal)
16238 movupd mem, reg
16240 if (x86_sse_split_regs == true)
16241 {
16242 movlpd mem, reg
16243 movhpd mem+8, reg
16244 }
16245 else
16246 {
16247 movsd mem, reg
16248 movhpd mem+8, reg
16249 }
16250 */
16252 void
16254 {
16262 {
16264 {
16269 /* FALLTHRU */
16277 }
16280 }
16283 {
16284 /* ??? If we have typed data, then it would appear that using
16285 movdqu is the only way to get unaligned data loaded with
16286 integer type. */
16288 {
16291 /* We will eventually emit movups based on insn attributes. */
16293 }
16295 {
16296 rtx zero;
16299 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16300 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16302 {
16303 /* We will eventually emit movups based on insn attributes. */
16306 }
16308 /* When SSE registers are split into halves, we can avoid
16309 writing to the top half twice. */
16311 {
16314 }
16315 else
16316 {
16317 /* ??? Not sure about the best option for the Intel chips.
16318 The following would seem to satisfy; the register is
16319 entirely cleared, breaking the dependency chain. We
16320 then store to the upper half, with a dependency depth
16321 of one. A rumor has it that Intel recommends two movsd
16322 followed by an unpacklpd, but this is unconfirmed. And
16323 given that the dependency depth of the unpacklpd would
16324 still be one, I'm not sure why this would be better. */
16326 }
16332 }
16333 else
16334 {
16336 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16337 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16339 {
16344 }
16348 else
16358 }
16359 }
16361 {
16363 {
16366 /* We will eventually emit movups based on insn attributes. */
16368 }
16370 {
16372 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16373 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16375 /* We will eventually emit movups based on insn attributes. */
16377 else
16378 {
16383 }
16384 }
16385 else
16386 {
16391 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16392 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16394 {
16397 }
16398 else
16399 {
16404 }
16405 }
16406 }
16407 else
16409 }
16411 /* Expand a push in MODE. This is some mode for which we do not support
16412 proper push instructions, at least from the registers that we expect
16413 the value to live in. */
16415 void
16417 {
16418 rtx tmp;
16428 /* When we push an operand onto stack, it has to be aligned at least
16429 at the function argument boundary. However since we don't have
16430 the argument type, we can't determine the actual argument
16431 boundary. */
16433 }
16435 /* Helper function of ix86_fixup_binary_operands to canonicalize
16436 operand order. Returns true if the operands should be swapped. */
16438 static bool
16440 rtx operands[])
16441 {
16446 /* If the operation is not commutative, we can't do anything. */
16450 /* Highest priority is that src1 should match dst. */
16456 /* Next highest priority is that immediate constants come second. */
16462 /* Lowest priority is that memory references should come second. */
16469 }
16472 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16473 destination to use for the operation. If different from the true
16474 destination in operands[0], a copy operation will be required. */
16476 rtx
16478 rtx operands[])
16479 {
16484 /* Canonicalize operand order. */
16486 {
16487 rtx temp;
16489 /* It is invalid to swap operands of different modes. */
16495 }
16497 /* Both source operands cannot be in memory. */
16499 {
16500 /* Optimization: Only read from memory once. */
16502 {
16505 }
16506 else
16508 }
16510 /* If the destination is memory, and we do not have matching source
16511 operands, do things in registers. */
16515 /* Source 1 cannot be a constant. */
16519 /* Source 1 cannot be a non-matching memory. */
16523 /* Improve address combine. */
16532 }
16534 /* Similarly, but assume that the destination has already been
16535 set up properly. */
16537 void
16540 {
16543 }
16545 /* Attempt to expand a binary operator. Make the expansion closer to the
16546 actual machine, then just general_operand, which will allow 3 separate
16547 memory references (one output, two input) in a single insn. */
16549 void
16551 rtx operands[])
16552 {
16559 /* Emit the instruction. */
16563 {
16564 /* Reload doesn't know about the flags register, and doesn't know that
16565 it doesn't want to clobber it. We can only do this with PLUS. */
16568 }
16572 {
16573 /* This is going to be an LEA; avoid splitting it later. */
16575 }
16576 else
16577 {
16580 }
16582 /* Fix up the destination if needed. */
16585 }
16587 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16588 the given OPERANDS. */
16590 void
16592 rtx operands[])
16593 {
16596 {
16599 }
16601 {
16604 }
16605 /* Optimize (__m128i) d | (__m128i) e and similar code
16606 when d and e are float vectors into float vector logical
16607 insn. In C/C++ without using intrinsics there is no other way
16608 to express vector logical operation on float vectors than
16609 to cast them temporarily to integer vectors. */
16611 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16620 {
16621 rtx dst;
16623 {
16630 {
16633 }
16634 else
16635 {
16640 }
16651 }
16652 }
16661 }
16663 /* Return TRUE or FALSE depending on whether the binary operator meets the
16664 appropriate constraints. */
16666 bool
16669 {
16674 /* Both source operands cannot be in memory. */
16678 /* Canonicalize operand order for commutative operators. */
16680 {
16684 }
16686 /* If the destination is memory, we must have a matching source operand. */
16690 /* Source 1 cannot be a constant. */
16694 /* Source 1 cannot be a non-matching memory. */
16696 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16704 }
16706 /* Attempt to expand a unary operator. Make the expansion closer to the
16707 actual machine, then just general_operand, which will allow 2 separate
16708 memory references (one output, one input) in a single insn. */
16710 void
16712 rtx operands[])
16713 {
16720 /* If the destination is memory, and we do not have matching source
16721 operands, do things in registers. */
16724 {
16727 else
16729 }
16731 /* When source operand is memory, destination must match. */
16735 /* Emit the instruction. */
16739 {
16740 /* Reload doesn't know about the flags register, and doesn't know that
16741 it doesn't want to clobber it. */
16744 }
16745 else
16746 {
16749 }
16751 /* Fix up the destination if needed. */
16754 }
16756 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16757 divisor are within the range [0-255]. */
16759 void
16762 {
16771 {
16784 }
16791 /* Use 8bit unsigned divimod if dividend and divisor are within
16792 the range [0-255]. */
16801 pc_rtx);
16806 /* Generate original signed/unsigned divimod. */
16811 /* Branch to the end. */
16815 /* Generate 8bit unsigned divide. */
16817 /* Don't use operands[0] for result of 8bit divide since not all
16818 registers support QImode ZERO_EXTRACT. */
16825 {
16828 }
16829 else
16830 {
16833 }
16835 /* Extract remainder from AH. */
16839 else
16840 {
16841 /* Need a new scratch register since the old one has result
16842 of 8bit divide. */
16846 }
16849 /* Zero extend quotient from AL. */
16855 }
16857 #define LEA_MAX_STALL (3)
16858 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16860 /* Increase given DISTANCE in half-cycles according to
16861 dependencies between PREV and NEXT instructions.
16862 Add 1 half-cycle if there is no dependency and
16863 go to next cycle if there is some dependecy. */
16865 static unsigned int
16867 {
16884 }
16886 /* Function checks if instruction INSN defines register number
16887 REGNO1 or REGNO2. */
16889 static bool
16891 rtx insn)
16892 {
16900 {
16902 }
16905 }
16907 /* Function checks if instruction INSN uses register number
16908 REGNO as a part of address expression. */
16910 static bool
16912 {
16920 }
16922 /* Search backward for non-agu definition of register number REGNO1
16923 or register number REGNO2 in basic block starting from instruction
16924 START up to head of basic block or instruction INSN.
16926 Function puts true value into *FOUND var if definition was found
16927 and false otherwise.
16929 Distance in half-cycles between START and found instruction or head
16930 of BB is added to DISTANCE and returned. */
16932 static int
16936 {
16946 {
16948 {
16951 {
16954 {
16957 }
16958 }
16961 }
16966 }
16969 }
16971 /* Search backward for non-agu definition of register number REGNO1
16972 or register number REGNO2 in INSN's basic block until
16973 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16974 2. Reach neighbour BBs boundary, or
16975 3. Reach agu definition.
16976 Returns the distance between the non-agu definition point and INSN.
16977 If no definition point, returns -1. */
16979 static int
16981 rtx insn)
16982 {
16993 {
16994 edge e;
16995 edge_iterator ei;
17000 {
17003 }
17009 else
17010 {
17015 {
17016 int bb_dist
17022 {
17029 }
17030 }
17033 }
17034 }
17036 /* get_attr_type may modify recog data. We want to make sure
17037 that recog data is valid for instruction INSN, on which
17038 distance_non_agu_define is called. INSN is unchanged here. */
17045 }
17047 /* Return the distance in half-cycles between INSN and the next
17048 insn that uses register number REGNO in memory address added
17049 to DISTANCE. Return -1 if REGNO0 is set.
17051 Put true value into *FOUND if register usage was found and
17052 false otherwise.
17053 Put true value into *REDEFINED if register redefinition was
17054 found and false otherwise. */
17056 static int
17060 {
17071 {
17073 {
17076 {
17077 /* Return DISTANCE if OP0 is used in memory
17078 address in NEXT. */
17081 }
17084 {
17085 /* Return -1 if OP0 is set in NEXT. */
17088 }
17091 }
17097 }
17100 }
17102 /* Return the distance between INSN and the next insn that uses
17103 register number REGNO0 in memory address. Return -1 if no such
17104 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17106 static int
17108 {
17120 {
17121 edge e;
17122 edge_iterator ei;
17127 {
17130 }
17136 else
17137 {
17143 {
17144 int bb_dist
17149 {
17156 }
17157 }
17160 }
17161 }
17167 }
17169 /* Define this macro to tune LEA priority vs ADD, it take effect when
17170 there is a dilemma of choicing LEA or ADD
17171 Negative value: ADD is more preferred than LEA
17172 Zero: Netrual
17173 Positive value: LEA is more preferred than ADD*/
17174 #define IX86_LEA_PRIORITY 0
17176 /* Return true if usage of lea INSN has performance advantage
17177 over a sequence of instructions. Instructions sequence has
17178 SPLIT_COST cycles higher latency than lea latency. */
17180 static bool
17183 {
17190 {
17191 /* If there is no non AGU operand definition, no AGU
17192 operand usage and split cost is 0 then both lea
17193 and non lea variants have same priority. Currently
17194 we prefer lea for 64 bit code and non lea on 32 bit
17195 code. */
17198 else
17200 }
17202 /* With longer definitions distance lea is more preferable.
17203 Here we change it to take into account splitting cost and
17204 lea priority. */
17207 /* If there is no use in memory addess then we just check
17208 that split cost exceeds AGU stall. */
17212 /* If this insn has both backward non-agu dependence and forward
17213 agu dependence, the one with short distance takes effect. */
17215 }
17217 /* Return true if it is legal to clobber flags by INSN and
17218 false otherwise. */
17220 static bool
17222 {
17225 bitmap live;
17228 {
17230 {
17237 }
17243 }
17247 }
17249 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17250 move and add to avoid AGU stalls. */
17252 bool
17254 {
17257 /* Check if we need to optimize. */
17261 /* Check it is correct to split here. */
17269 /* We need to split only adds with non destructive
17270 destination operand. */
17273 else
17275 }
17277 /* Return true if we should emit lea instruction instead of mov
17278 instruction. */
17280 bool
17282 {
17285 /* Check if we need to optimize. */
17289 /* Use lea for reg to reg moves only. */
17297 }
17299 /* Return true if we need to split lea into a sequence of
17300 instructions to avoid AGU stalls. */
17302 bool
17304 {
17310 /* Check we need to optimize. */
17314 /* The "at least two components" test below might not catch simple
17315 move or zero extension insns if parts.base is non-NULL and parts.disp
17316 is const0_rtx as the only components in the address, e.g. if the
17317 register is %rbp or %r13. As this test is much cheaper and moves or
17318 zero extensions are the common case, do this check first. */
17324 /* Check if it is OK to split here. */
17331 /* There should be at least two components in the address. */
17336 /* We should not split into add if non legitimate pic
17337 operand is used as displacement. */
17352 /* Compute how many cycles we will add to execution time
17353 if split lea into a sequence of instructions. */
17355 {
17356 /* Have to use mov instruction if non desctructive
17357 destination form is used. */
17361 /* Have to add index to base if both exist. */
17365 /* Have to use shift and adds if scale is 2 or greater. */
17367 {
17372 else
17374 }
17376 /* Have to use add instruction with immediate if
17377 disp is non zero. */
17381 /* Subtract the price of lea. */
17383 }
17386 }
17388 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17389 matches destination. RTX includes clobber of FLAGS_REG. */
17391 static void
17394 {
17401 }
17403 /* Return true if regno1 def is nearest to the insn. */
17405 static bool
17407 {
17414 {
17416 {
17419 }
17425 }
17427 /* None of the regs is defined in the bb. */
17429 }
17431 /* Split lea instructions into a sequence of instructions
17432 which are executed on ALU to avoid AGU stalls.
17433 It is assumed that it is allowed to clobber flags register
17434 at lea position. */
17436 void
17438 {
17454 {
17457 }
17460 {
17463 }
17469 {
17470 /* Case r1 = r1 + ... */
17472 {
17473 /* If we have a case r1 = r1 + C * r1 then we
17474 should use multiplication which is very
17475 expensive. Assume cost model is wrong if we
17476 have such case here. */
17481 }
17482 else
17483 {
17484 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17488 /* Use shift for scaling. */
17497 }
17498 }
17500 {
17503 }
17504 else
17505 {
17507 {
17510 }
17512 {
17515 }
17516 else
17517 {
17522 else
17523 {
17524 rtx tmp1;
17526 /* Find better operand for SET instruction, depending
17527 on which definition is farther from the insn. */
17530 else
17540 }
17543 }
17547 }
17548 }
17550 /* Return true if it is ok to optimize an ADD operation to LEA
17551 operation to avoid flag register consumation. For most processors,
17552 ADD is faster than LEA. For the processors like ATOM, if the
17553 destination register of LEA holds an actual address which will be
17554 used soon, LEA is better and otherwise ADD is better. */
17556 bool
17558 {
17563 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17571 }
17573 /* Return true if destination reg of SET_BODY is shift count of
17574 USE_BODY. */
17576 static bool
17578 {
17579 rtx set_dest;
17580 rtx shift_rtx;
17583 /* Retrieve destination of SET_BODY. */
17585 {
17594 use_body))
17599 }
17601 /* Retrieve shift count of USE_BODY. */
17603 {
17615 }
17623 {
17626 /* Return true if shift count is dest of SET_BODY. */
17628 {
17629 /* Add check since it can be invoked before register
17630 allocation in pre-reload schedule. */
17636 }
17637 }
17640 }
17642 /* Return true if destination reg of SET_INSN is shift count of
17643 USE_INSN. */
17645 bool
17647 {
17650 }
17652 /* Return TRUE or FALSE depending on whether the unary operator meets the
17653 appropriate constraints. */
17655 bool
17659 {
17660 /* If one of operands is memory, source and destination must match. */
17666 }
17668 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17669 are ok, keeping in mind the possible movddup alternative. */
17671 bool
17673 {
17679 }
17681 /* Post-reload splitter for converting an SF or DFmode value in an
17682 SSE register into an unsigned SImode. */
17684 void
17686 {
17697 /* Load up the value into the low element. We must ensure that the other
17698 elements are valid floats -- zero is the easiest such value. */
17700 {
17703 else
17705 }
17706 else
17707 {
17712 else
17714 }
17734 else
17739 }
17741 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17742 Expects the 64-bit DImode to be supplied in a pair of integral
17743 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17744 -mfpmath=sse, !optimize_size only. */
17746 void
17748 {
17752 rtx x;
17758 {
17761 }
17762 else
17763 {
17767 }
17775 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17778 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17779 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17780 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17781 (0x1.0p84 + double(fp_value_hi_xmm)).
17782 Note these exponents differ by 32. */
17786 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17787 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17796 /* Add the upper and lower DFmode values together. */
17799 else
17800 {
17804 }
17807 }
17809 /* Not used, but eases macroization of patterns. */
17810 void
17812 rtx input ATTRIBUTE_UNUSED)
17813 {
17815 }
17817 /* Convert an unsigned SImode value into a DFmode. Only currently used
17818 for SSE, but applicable anywhere. */
17820 void
17822 {
17823 REAL_VALUE_TYPE TWO31r;
17838 }
17840 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17841 32-bit mode; otherwise we have a direct convert instruction. */
17843 void
17845 {
17846 REAL_VALUE_TYPE TWO32r;
17864 }
17866 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17867 For x86_32, -mfpmath=sse, !optimize_size only. */
17868 void
17870 {
17871 REAL_VALUE_TYPE ONE16r;
17890 }
17892 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17893 a vector of unsigned ints VAL to vector of floats TARGET. */
17895 void
17897 {
17899 REAL_VALUE_TYPE TWO16r;
17906 else
17911 OPTAB_DIRECT);
17922 OPTAB_DIRECT);
17924 OPTAB_DIRECT);
17927 }
17929 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17930 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17931 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17932 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17934 rtx
17936 {
17937 REAL_VALUE_TYPE TWO31r;
17952 {
17958 }
17967 OPTAB_DIRECT);
17968 else
17969 {
17975 OPTAB_DIRECT);
17976 }
17979 }
17981 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17982 then replicate the value for all elements of the vector
17983 register. */
17985 rtx
17987 {
17989 rtvec v;
17993 {
18020 }
18021 }
18023 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18024 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18025 for an SSE register. If VECT is true, then replicate the mask for
18026 all elements of the vector register. If INVERT is true, then create
18027 a mask excluding the sign bit. */
18029 rtx
18031 {
18035 rtx v;
18036 rtx mask;
18038 /* Find the sign bit, sign extended to 2*HWI. */
18040 {
18060 else
18068 {
18071 }
18072 else
18073 {
18074 rtvec vec;
18080 {
18083 }
18084 else
18094 }
18099 }
18104 /* Force this value into the low part of a fp vector constant. */
18113 }
18115 /* Generate code for floating point ABS or NEG. */
18117 void
18119 rtx operands[])
18120 {
18131 {
18137 }
18139 /* NEG and ABS performed with SSE use bitwise mask operations.
18140 Create the appropriate mask now. */
18143 else
18153 {
18155 rtvec par;
18160 else
18161 {
18164 }
18166 }
18167 else
18169 }
18171 /* Expand a copysign operation. Special case operand 0 being a constant. */
18173 void
18175 {
18189 else
18193 {
18200 {
18203 else
18204 {
18208 }
18209 }
18219 else
18223 }
18224 else
18225 {
18235 else
18239 }
18240 }
18242 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18243 be a constant, and so has already been expanded into a vector constant. */
18245 void
18247 {
18263 {
18266 }
18267 }
18269 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18270 so we have to do two masks. */
18272 void
18274 {
18289 {
18290 /* Shouldn't happen often (it's useless, obviously), but when it does
18291 we'd generate incorrect code if we continue below. */
18294 }
18297 {
18308 }
18309 else
18310 {
18312 {
18314 }
18316 {
18320 }
18324 {
18327 }
18329 {
18334 }
18336 }
18340 }
18342 /* Return TRUE or FALSE depending on whether the first SET in INSN
18343 has source and destination with matching CC modes, and that the
18344 CC mode is at least as constrained as REQ_MODE. */
18346 bool
18348 {
18349 rtx set;
18360 {
18370 /* FALLTHRU */
18374 /* FALLTHRU */
18378 /* FALLTHRU */
18392 }
18395 }
18397 /* Generate insn patterns to do an integer compare of OPERANDS. */
18399 static rtx
18401 {
18408 /* This is very simple, but making the interface the same as in the
18409 FP case makes the rest of the code easier. */
18413 /* Return the test that should be put into the flags user, i.e.
18414 the bcc, scc, or cmov instruction. */
18416 }
18418 /* Figure out whether to use ordered or unordered fp comparisons.
18419 Return the appropriate mode to use. */
18421 enum machine_mode
18423 {
18424 /* ??? In order to make all comparisons reversible, we do all comparisons
18425 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18426 all forms trapping and nontrapping comparisons, we can make inequality
18427 comparisons trapping again, since it results in better code when using
18428 FCOM based compares. */
18430 }
18432 enum machine_mode
18434 {
18438 {
18441 }
18444 {
18445 /* Only zero flag is needed. */
18449 /* Codes needing carry flag. */
18452 /* Detect overflow checks. They need just the carry flag. */
18456 else
18461 /* Codes possibly doable only with sign flag when
18462 comparing against zero. */
18467 else
18468 /* For other cases Carry flag is not required. */
18470 /* Codes doable only with sign flag when comparing
18471 against zero, but we miss jump instruction for it
18472 so we need to use relational tests against overflow
18473 that thus needs to be zero. */
18478 else
18480 /* strcmp pattern do (use flags) and combine may ask us for proper
18481 mode. */
18486 }
18487 }
18489 /* Return the fixed registers used for condition codes. */
18491 static bool
18493 {
18497 }
18499 /* If two condition code modes are compatible, return a condition code
18500 mode which is compatible with both. Otherwise, return
18501 VOIDmode. */
18503 static enum machine_mode
18505 {
18522 {
18536 {
18550 }
18554 /* These are only compatible with themselves, which we already
18555 checked above. */
18557 }
18558 }
18561 /* Return a comparison we can do and that it is equivalent to
18562 swap_condition (code) apart possibly from orderedness.
18563 But, never change orderedness if TARGET_IEEE_FP, returning
18564 UNKNOWN in that case if necessary. */
18566 static enum rtx_code
18568 {
18570 {
18581 }
18582 }
18584 /* Return cost of comparison CODE using the best strategy for performance.
18585 All following functions do use number of instructions as a cost metrics.
18586 In future this should be tweaked to compute bytes for optimize_size and
18587 take into account performance of various instructions on various CPUs. */
18589 static int
18591 {
18594 /* The cost of code using bit-twiddling on %ah. */
18596 {
18619 }
18622 {
18629 }
18630 }
18632 /* Return strategy to use for floating-point. We assume that fcomi is always
18633 preferrable where available, since that is also true when looking at size
18634 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18636 enum ix86_fpcmp_strategy
18638 {
18639 /* Do fcomi/sahf based test when profitable. */
18648 }
18650 /* Swap, force into registers, or otherwise massage the two operands
18651 to a fp comparison. The operands are updated in place; the new
18652 comparison code is returned. */
18654 static enum rtx_code
18656 {
18662 /* All of the unordered compare instructions only work on registers.
18663 The same is true of the fcomi compare instructions. The XFmode
18664 compare instructions require registers except when comparing
18665 against zero or when converting operand 1 from fixed point to
18666 floating point. */
18675 {
18678 }
18679 else
18680 {
18681 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18682 things around if they appear profitable, otherwise force op0
18683 into a register. */
18689 {
18692 {
18693 rtx tmp;
18696 }
18697 }
18703 {
18708 {
18711 }
18712 else
18714 }
18715 }
18717 /* Try to rearrange the comparison to make it cheaper. */
18721 {
18722 rtx tmp;
18727 }
18732 }
18734 /* Convert comparison codes we use to represent FP comparison to integer
18735 code that will result in proper branch. Return UNKNOWN if no such code
18736 is available. */
18738 enum rtx_code
18740 {
18742 {
18765 }
18766 }
18768 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18770 static rtx
18772 {
18779 /* Do fcomi/sahf based test when profitable. */
18781 {
18786 tmp);
18794 tmp);
18803 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18810 /* In the unordered case, we have to check C2 for NaN's, which
18811 doesn't happen to work out to anything nice combination-wise.
18812 So do some bit twiddling on the value we've got in AH to come
18813 up with an appropriate set of condition codes. */
18817 {
18821 {
18824 }
18825 else
18826 {
18832 }
18837 {
18842 }
18843 else
18844 {
18847 }
18852 {
18855 }
18856 else
18857 {
18861 }
18866 {
18872 }
18873 else
18874 {
18877 }
18882 {
18887 }
18888 else
18889 {
18892 }
18897 {
18902 }
18903 else
18904 {
18907 }
18921 }
18926 }
18928 /* Return the test that should be put into the flags user, i.e.
18929 the bcc, scc, or cmov instruction. */
18932 const0_rtx);
18933 }
18935 static rtx
18937 {
18938 rtx ret;
18944 {
18947 }
18948 else
18952 }
18954 void
18956 {
18958 rtx tmp;
18961 {
18968 simple:
18972 pc_rtx);
18980 /* Expand DImode branch into multiple compare+branch. */
18981 {
18987 {
18990 }
18997 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18998 avoid two branches. This costs one extra insn, so disable when
18999 optimizing for size. */
19004 {
19022 }
19024 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19025 op1 is a constant and the low word is zero, then we can just
19026 examine the high word. Similarly for low word -1 and
19027 less-or-equal-than or greater-than. */
19031 {
19034 {
19037 }
19041 {
19044 }
19048 }
19050 /* Otherwise, we need two or three jumps. */
19059 {
19073 }
19075 /*
19076 * a < b =>
19077 * if (hi(a) < hi(b)) goto true;
19078 * if (hi(a) > hi(b)) goto false;
19079 * if (lo(a) < lo(b)) goto true;
19080 * false:
19081 */
19093 }
19098 }
19099 }
19101 /* Split branch based on floating point condition. */
19102 void
19105 {
19106 rtx condition;
19107 rtx i;
19110 {
19115 }
19118 tmp);
19120 /* Remove pushed operand from stack. */
19130 }
19132 void
19134 {
19135 rtx ret;
19142 }
19144 /* Expand comparison setting or clearing carry flag. Return true when
19145 successful and set pop for the operation. */
19146 static bool
19148 {
19152 /* Do not handle double-mode compares that go through special path. */
19157 {
19162 /* Shortcut: following common codes never translate
19163 into carry flag compares. */
19168 /* These comparisons require zero flag; swap operands so they won't. */
19171 {
19176 }
19178 /* Try to expand the comparison and verify that we end up with
19179 carry flag based comparison. This fails to be true only when
19180 we decide to expand comparison using arithmetic that is not
19181 too common scenario. */
19190 else
19199 }
19205 {
19210 /* Convert a==0 into (unsigned)a<1. */
19219 /* Convert a>b into b<a or a>=b-1. */
19223 {
19225 /* Bail out on overflow. We still can swap operands but that
19226 would force loading of the constant into register. */
19231 }
19232 else
19233 {
19238 }
19241 /* Convert a>=0 into (unsigned)a<0x80000000. */
19259 }
19260 /* Swapping operands may cause constant to appear as first operand. */
19262 {
19266 }
19270 }
19272 bool
19274 {
19298 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19299 HImode insns, we'd be swallowed in word prefix ops. */
19305 {
19309 HOST_WIDE_INT diff;
19312 /* Sign bit compares are better done using shifts than we do by using
19313 sbb. */
19316 {
19317 /* Detect overlap between destination and compare sources. */
19321 {
19322 rtx flags;
19331 {
19333 compare_code
19335 }
19337 /* To simplify rest of code, restrict to the GEU case. */
19339 {
19345 }
19346 else
19347 {
19350 reverse_condition_maybe_unordered
19352 else
19355 }
19364 else
19367 }
19368 else
19369 {
19372 else
19373 {
19378 }
19380 }
19383 {
19384 /*
19385 * cmpl op0,op1
19386 * sbbl dest,dest
19387 * [addl dest, ct]
19388 *
19389 * Size 5 - 8.
19390 */
19395 }
19397 {
19398 /*
19399 * cmpl op0,op1
19400 * sbbl dest,dest
19401 * orl $ct, dest
19402 *
19403 * Size 8.
19404 */
19408 }
19410 {
19411 /*
19412 * cmpl op0,op1
19413 * sbbl dest,dest
19414 * notl dest
19415 * [addl dest, cf]
19416 *
19417 * Size 8 - 11.
19418 */
19424 }
19425 else
19426 {
19427 /*
19428 * cmpl op0,op1
19429 * sbbl dest,dest
19430 * [notl dest]
19431 * andl cf - ct, dest
19432 * [addl dest, ct]
19433 *
19434 * Size 8 - 11.
19435 */
19438 {
19442 }
19452 }
19458 }
19461 {
19464 HOST_WIDE_INT tmp;
19469 {
19472 /* We may be reversing unordered compare to normal compare, that
19473 is not valid in general (we may convert non-trapping condition
19474 to trapping one), however on i386 we currently emit all
19475 comparisons unordered. */
19478 }
19479 else
19480 {
19483 }
19484 }
19489 {
19494 {
19499 }
19500 }
19502 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19506 {
19507 /* If lea code below could be used, only optimize
19508 if it results in a 2 insn sequence. */
19514 {
19515 /*
19516 * notl op1 (if necessary)
19517 * sarl $31, op1
19518 * orl cf, op1
19519 */
19521 {
19525 }
19536 }
19537 }
19545 {
19546 /*
19547 * xorl dest,dest
19548 * cmpl op1,op2
19549 * setcc dest
19550 * lea cf(dest*(ct-cf)),dest
19551 *
19552 * Size 14.
19553 *
19554 * This also catches the degenerate setcc-only case.
19555 */
19557 rtx tmp;
19563 /* On x86_64 the lea instruction operates on Pmode, so we need
19564 to get arithmetics done in proper mode to match. */
19567 else
19568 {
19569 rtx out1;
19572 nops++;
19574 {
19576 nops++;
19577 }
19578 }
19580 {
19582 nops++;
19583 }
19585 {
19588 else
19590 }
19595 }
19597 /*
19598 * General case: Jumpful:
19599 * xorl dest,dest cmpl op1, op2
19600 * cmpl op1, op2 movl ct, dest
19601 * setcc dest jcc 1f
19602 * decl dest movl cf, dest
19603 * andl (cf-ct),dest 1:
19604 * addl ct,dest
19605 *
19606 * Size 20. Size 14.
19607 *
19608 * This is reasonably steep, but branch mispredict costs are
19609 * high on modern cpus, so consider failing only if optimizing
19610 * for space.
19611 */
19616 {
19618 {
19625 {
19628 /* We may be reversing unordered compare to normal compare,
19629 that is not valid in general (we may convert non-trapping
19630 condition to trapping one), however on i386 we currently
19631 emit all comparisons unordered. */
19633 }
19634 else
19635 {
19639 }
19640 }
19643 {
19644 /* notl op1 (if needed)
19645 sarl $31, op1
19646 andl (cf-ct), op1
19647 addl ct, op1
19649 For x < 0 (resp. x <= -1) there will be no notl,
19650 so if possible swap the constants to get rid of the
19651 complement.
19652 True/false will be -1/0 while code below (store flag
19653 followed by decrement) is 0/-1, so the constants need
19654 to be exchanged once more. */
19657 {
19660 }
19661 else
19662 {
19666 }
19669 }
19670 else
19671 {
19675 constm1_rtx,
19677 }
19689 }
19690 }
19693 {
19694 /* Try a few things more with specific constants and a variable. */
19696 optab op;
19702 /* If one of the two operands is an interesting constant, load a
19703 constant with the above and mask it in with a logical operation. */
19706 {
19712 else
19714 }
19716 {
19722 else
19724 }
19725 else
19732 /* Recurse to get the constant loaded. */
19736 /* Mask in the interesting variable. */
19738 OPTAB_WIDEN);
19743 }
19745 /*
19746 * For comparison with above,
19747 *
19748 * movl cf,dest
19749 * movl ct,tmp
19750 * cmpl op1,op2
19751 * cmovcc tmp,dest
19752 *
19753 * Size 15.
19754 */
19776 }
19778 /* Swap, force into registers, or otherwise massage the two operands
19779 to an sse comparison with a mask result. Thus we differ a bit from
19780 ix86_prepare_fp_compare_args which expects to produce a flags result.
19782 The DEST operand exists to help determine whether to commute commutative
19783 operators. The POP0/POP1 operands are updated in place. The new
19784 comparison code is returned, or UNKNOWN if not implementable. */
19786 static enum rtx_code
19789 {
19790 rtx tmp;
19793 {
19796 /* AVX supports all the needed comparisons. */
19799 /* We have no LTGT as an operator. We could implement it with
19800 NE & ORDERED, but this requires an extra temporary. It's
19801 not clear that it's worth it. */
19808 /* These are supported directly. */
19815 /* AVX has 3 operand comparisons, no need to swap anything. */
19818 /* For commutative operators, try to canonicalize the destination
19819 operand to be first in the comparison - this helps reload to
19820 avoid extra moves. */
19823 /* FALLTHRU */
19829 /* These are not supported directly before AVX, and furthermore
19830 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19831 comparison operands to transform into something that is
19832 supported. */
19841 }
19844 }
19846 /* Detect conditional moves that exactly match min/max operational
19847 semantics. Note that this is IEEE safe, as long as we don't
19848 interchange the operands.
19850 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19851 and TRUE if the operation is successful and instructions are emitted. */
19853 static bool
19856 {
19859 rtx tmp;
19862 ;
19864 {
19868 }
19869 else
19876 else
19881 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19882 but MODE may be a vector mode and thus not appropriate. */
19884 {
19886 rtvec v;
19891 }
19892 else
19893 {
19896 }
19900 }
19902 /* Expand an sse vector comparison. Return the register with the result. */
19904 static rtx
19907 {
19910 rtx x;
19923 {
19926 }
19927 else
19931 }
19933 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19934 operations. This is used for both scalar and vector conditional moves. */
19936 static void
19938 {
19944 {
19946 }
19948 {
19952 }
19954 {
19959 }
19961 {
19965 }
19967 {
19975 op_true,
19976 op_false)));
19977 }
19978 else
19979 {
19988 {
20002 {
20008 }
20023 {
20029 }
20033 }
20037 else
20038 {
20044 else
20056 }
20057 }
20058 }
20060 /* Expand a floating-point conditional move. Return true if successful. */
20062 bool
20064 {
20072 {
20075 /* Since we've no cmove for sse registers, don't force bad register
20076 allocation just to gain access to it. Deny movcc when the
20077 comparison mode doesn't match the move mode. */
20096 }
20103 /* The floating point conditional move instructions don't directly
20104 support conditions resulting from a signed integer comparison. */
20108 {
20113 }
20120 }
20122 /* Expand a floating-point vector conditional move; a vcond operation
20123 rather than a movcc operation. */
20125 bool
20127 {
20129 rtx cmp;
20134 {
20135 rtx temp;
20137 {
20154 }
20156 OPTAB_DIRECT);
20159 }
20169 }
20171 /* Expand a signed/unsigned integral vector conditional move. */
20173 bool
20175 {
20185 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20186 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20195 {
20199 {
20205 }
20208 {
20214 }
20215 }
20224 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20228 ;
20229 else
20230 {
20231 /* Canonicalize the comparison to EQ, GT, GTU. */
20233 {
20250 /* FALLTHRU */
20260 }
20262 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20264 {
20266 {
20268 /* SSE4.1 supports EQ. */
20275 /* SSE4.2 supports GT/GTU. */
20282 }
20283 }
20285 /* Unsigned parallel compare is not supported by the hardware.
20286 Play some tricks to turn this into a signed comparison
20287 against 0. */
20289 {
20293 {
20298 {
20303 {
20310 }
20311 /* Subtract (-(INT MAX) - 1) from both operands to make
20312 them signed. */
20323 }
20330 /* Perform a parallel unsigned saturating subtraction. */
20343 }
20344 }
20345 }
20347 /* Allow the comparison to be done in one mode, but the movcc to
20348 happen in another mode. */
20350 {
20353 }
20354 else
20355 {
20361 }
20366 }
20368 /* Expand a variable vector permutation. */
20370 void
20372 {
20383 /* Number of elements in the vector. */
20389 {
20391 {
20392 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20393 an constant shuffle operand. With a tiny bit of effort we can
20394 use VPERMD instead. A re-interpretation stall for V4DFmode is
20395 unfortunate but there's no avoiding it.
20396 Similarly for V16HImode we don't have instructions for variable
20397 shuffling, while for V32QImode we can use after preparing suitable
20398 masks vpshufb; vpshufb; vpermq; vpor. */
20401 {
20405 }
20406 else
20407 {
20411 }
20414 /* Replicate the low bits of the V4DImode mask into V8SImode:
20415 mask = { A B C D }
20416 t1 = { A A B B C C D D }. */
20424 else
20427 /* Multiply the shuffle indicies by two. */
20429 OPTAB_DIRECT);
20431 /* Add one to the odd shuffle indicies:
20432 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20434 {
20437 }
20441 OPTAB_DIRECT);
20443 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20448 }
20451 {
20453 /* The VPERMD and VPERMPS instructions already properly ignore
20454 the high bits of the shuffle elements. No need for us to
20455 perform an AND ourselves. */
20458 else
20459 {
20465 }
20472 else
20473 {
20479 }
20483 /* By combining the two 128-bit input vectors into one 256-bit
20484 input vector, we can use VPERMD and VPERMPS for the full
20485 two-operand shuffle. */
20517 /* From mask create two adjusted masks, which contain the same
20518 bits as mask in the low 7 bits of each vector element.
20519 The first mask will have the most significant bit clear
20520 if it requests element from the same 128-bit lane
20521 and MSB set if it requests element from the other 128-bit lane.
20522 The second mask will have the opposite values of the MSB,
20523 and additionally will have its 128-bit lanes swapped.
20524 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20525 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20526 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20527 stands for other 12 bytes. */
20528 /* The bit whether element is from the same lane or the other
20529 lane is bit 4, so shift it up by 3 to the MSB position. */
20533 /* Clear MSB bits from the mask just in case it had them set. */
20535 /* After this t1 will have MSB set for elements from other lane. */
20537 /* Clear bits other than MSB. */
20539 /* Or in the lower bits from mask into t3. */
20541 /* And invert MSB bits in t1, so MSB is set for elements from the same
20542 lane. */
20544 /* Swap 128-bit lanes in t3. */
20549 /* And or in the lower bits from mask into t1. */
20552 {
20553 /* Each of these shuffles will put 0s in places where
20554 element from the other 128-bit lane is needed, otherwise
20555 will shuffle in the requested value. */
20558 /* For t3 the 128-bit lanes are swapped again. */
20563 /* And oring both together leads to the result. */
20566 }
20569 /* Similarly to the above one_operand_shuffle code,
20570 just for repeated twice for each operand. merge_two:
20571 code will merge the two results together. */
20593 }
20594 }
20597 {
20598 /* The XOP VPPERM insn supports three inputs. By ignoring the
20599 one_operand_shuffle special case, we avoid creating another
20600 set of constant vectors in memory. */
20603 /* mask = mask & {2*w-1, ...} */
20605 }
20606 else
20607 {
20608 /* mask = mask & {w-1, ...} */
20610 }
20618 /* For non-QImode operations, convert the word permutation control
20619 into a byte permutation control. */
20621 {
20626 /* Convert mask to vector of chars. */
20629 /* Replicate each of the input bytes into byte positions:
20630 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20631 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20632 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20639 else
20642 /* Convert it into the byte positions by doing
20643 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20649 }
20651 /* The actual shuffle operations all operate on V16QImode. */
20657 {
20659 }
20661 {
20663 }
20664 else
20665 {
20669 /* Shuffle the two input vectors independently. */
20675 merge_two:
20676 /* Then merge them together. The key is whether any given control
20677 element contained a bit set that indicates the second word. */
20681 {
20682 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20683 more shuffle to convert the V2DI input mask into a V4SI
20684 input mask. At which point the masking that expand_int_vcond
20685 will work as desired. */
20693 }
20710 }
20711 }
20713 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20714 true if we should do zero extension, else sign extension. HIGH_P is
20715 true if we want the N/2 high elements, else the low elements. */
20717 void
20719 {
20721 rtx tmp;
20724 {
20730 {
20734 else
20737 extract
20743 else
20746 extract
20752 else
20755 extract
20761 else
20767 else
20773 else
20778 }
20781 {
20784 }
20786 {
20787 /* Shift higher 8 bytes to lower 8 bytes. */
20792 }
20793 else
20797 }
20798 else
20799 {
20803 {
20807 else
20813 else
20819 else
20824 }
20828 else
20833 }
20834 }
20836 /* Expand conditional increment or decrement using adb/sbb instructions.
20837 The default case using setcc followed by the conditional move can be
20838 done by generic code. */
20839 bool
20841 {
20843 rtx flags;
20845 rtx compare_op;
20863 {
20866 }
20869 {
20873 reverse_condition_maybe_unordered
20875 else
20877 }
20881 /* Construct either adc or sbb insn. */
20883 {
20885 {
20900 }
20901 }
20902 else
20903 {
20905 {
20920 }
20921 }
20925 }
20928 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20929 but works for floating pointer parameters and nonoffsetable memories.
20930 For pushes, it returns just stack offsets; the values will be saved
20931 in the right order. Maximally three parts are generated. */
20933 static int
20935 {
20940 else
20946 /* Optimize constant pool reference to immediates. This is used by fp
20947 moves, that force all constants to memory to allow combining. */
20949 {
20953 }
20956 {
20957 /* The only non-offsetable memories we handle are pushes. */
20966 }
20969 {
20971 /* Caution: if we looked through a constant pool memory above,
20972 the operand may actually have a different mode now. That's
20973 ok, since we want to pun this all the way back to an integer. */
20977 }
20980 {
20983 else
20984 {
20988 {
20992 }
20994 {
20999 }
21001 {
21002 REAL_VALUE_TYPE r;
21007 {
21014 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21015 long double may not be 80-bit. */
21024 }
21027 }
21028 else
21030 }
21031 }
21032 else
21033 {
21037 {
21040 {
21044 }
21046 {
21050 }
21052 {
21053 REAL_VALUE_TYPE r;
21059 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21062 = gen_int_mode
21065 DImode);
21066 else
21073 = gen_int_mode
21076 DImode);
21077 else
21079 }
21080 else
21082 }
21083 }
21086 }
21088 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21089 Return false when normal moves are needed; true when all required
21090 insns have been emitted. Operands 2-4 contain the input values
21091 int the correct order; operands 5-7 contain the output values. */
21093 void
21095 {
21103 /* The DFmode expanders may ask us to move double.
21104 For 64bit target this is single move. By hiding the fact
21105 here we simplify i386.md splitters. */
21107 {
21108 /* Optimize constant pool reference to immediates. This is used by
21109 fp moves, that force all constants to memory to allow combining. */
21116 {
21119 }
21120 else
21125 }
21127 /* The only non-offsettable memory we handle is push. */
21130 else
21137 /* When emitting push, take care for source operands on the stack. */
21140 {
21143 /* Compensate for the stack decrement by 4. */
21148 /* src_base refers to the stack pointer and is
21149 automatically decreased by emitted push. */
21153 }
21155 /* We need to do copy in the right order in case an address register
21156 of the source overlaps the destination. */
21158 {
21159 rtx tmp;
21162 {
21166 collisions++;
21167 }
21169 /* Collision in the middle part can be handled by reordering. */
21171 {
21174 }
21178 {
21180 {
21183 }
21184 else
21185 {
21188 }
21189 }
21191 /* If there are more collisions, we can't handle it by reordering.
21192 Do an lea to the last part and use only one colliding move. */
21194 {
21195 rtx base;
21201 /* Handle the case when the last part isn't valid for lea.
21202 Happens in 64-bit mode storing the 12-byte XFmode. */
21209 {
21212 }
21213 }
21214 }
21217 {
21219 {
21221 {
21226 }
21228 {
21231 }
21232 }
21233 else
21234 {
21235 /* In 64bit mode we don't have 32bit push available. In case this is
21236 register, it is OK - we will just use larger counterpart. We also
21237 retype memory - these comes from attempt to avoid REX prefix on
21238 moving of second half of TFmode value. */
21240 {
21242 {
21253 }
21257 }
21258 }
21262 }
21264 /* Choose correct order to not overwrite the source before it is copied. */
21274 {
21276 {
21279 }
21280 }
21281 else
21282 {
21284 {
21287 }
21288 }
21290 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21292 {
21301 }
21307 }
21309 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21310 left shift by a constant, either using a single shift or
21311 a sequence of add instructions. */
21313 static void
21315 {
21321 {
21325 }
21326 else
21327 {
21330 }
21331 }
21333 void
21335 {
21344 {
21349 {
21355 }
21356 else
21357 {
21365 }
21367 }
21374 {
21375 /* Assuming we've chosen a QImode capable registers, then 1 << N
21376 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21378 {
21394 }
21396 /* Otherwise, we can get the same results by manually performing
21397 a bit extract operation on bit 5/6, and then performing the two
21398 shifts. The two methods of getting 0/1 into low/high are exactly
21399 the same size. Avoiding the shift in the bit extract case helps
21400 pentium4 a bit; no one else seems to care much either way. */
21401 else
21402 {
21407 HOST_WIDE_INT bits;
21408 rtx x;
21411 {
21417 }
21418 else
21419 {
21425 }
21429 else
21437 }
21442 }
21445 {
21446 /* For -1 << N, we can avoid the shld instruction, because we
21447 know that we're shifting 0...31/63 ones into a -1. */
21451 else
21453 }
21454 else
21455 {
21463 }
21468 {
21474 }
21475 else
21476 {
21481 }
21482 }
21484 void
21486 {
21496 {
21501 {
21507 }
21509 {
21518 }
21519 else
21520 {
21528 }
21529 }
21530 else
21531 {
21543 {
21551 scratch));
21552 }
21553 else
21554 {
21559 }
21560 }
21561 }
21563 void
21565 {
21575 {
21580 {
21587 }
21588 else
21589 {
21597 }
21598 }
21599 else
21600 {
21612 {
21618 scratch));
21619 }
21620 else
21621 {
21626 }
21627 }
21628 }
21630 /* Predict just emitted jump instruction to be taken with probability PROB. */
21631 static void
21633 {
21637 }
21639 /* Helper function for the string operations below. Dest VARIABLE whether
21640 it is aligned to VALUE bytes. If true, jump to the label. */
21641 static rtx
21643 {
21648 else
21654 else
21657 }
21659 /* Adjust COUNTER by the VALUE. */
21660 static void
21662 {
21667 }
21669 /* Zero extend possibly SImode EXP to Pmode register. */
21670 rtx
21672 {
21674 }
21676 /* Divide COUNTREG by SCALE. */
21677 static rtx
21679 {
21680 rtx sc;
21692 }
21694 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21695 DImode for constant loop counts. */
21697 static enum machine_mode
21699 {
21707 }
21709 /* Copy the address to a Pmode register. This is used for x32 to
21710 truncate DImode TLS address to a SImode register. */
21712 static rtx
21714 {
21717 else
21718 {
21721 }
21722 }
21724 /* When SRCPTR is non-NULL, output simple loop to move memory
21725 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21726 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21727 equivalent loop to set memory by VALUE (supposed to be in MODE).
21729 The size is rounded down to whole number of chunk size moved at once.
21730 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21733 static void
21738 {
21743 rtx size;
21744 rtx x_addr;
21745 rtx y_addr;
21754 /* Those two should combine. */
21756 {
21760 }
21770 {
21774 /* When unrolling for chips that reorder memory reads and writes,
21775 we can save registers by using single temporary.
21776 Also using 4 temporaries is overkill in 32bit mode. */
21778 {
21780 {
21782 {
21783 destmem =
21785 srcmem =
21787 }
21789 }
21790 }
21791 else
21792 {
21796 {
21799 {
21800 srcmem =
21802 }
21804 }
21806 {
21808 {
21809 destmem =
21811 }
21813 }
21814 }
21815 }
21816 else
21818 {
21820 destmem =
21823 }
21833 {
21839 else
21841 }
21842 else
21850 {
21855 }
21857 }
21859 /* Output "rep; mov" instruction.
21860 Arguments have same meaning as for previous function */
21861 static void
21864 rtx count,
21866 {
21867 rtx destexp;
21868 rtx srcexp;
21869 rtx countreg;
21870 HOST_WIDE_INT rounded_count;
21872 /* If the size is known, it is shorter to use rep movs. */
21883 {
21890 }
21891 else
21892 {
21895 }
21897 {
21904 }
21905 else
21906 {
21911 }
21914 }
21916 /* Output "rep; stos" instruction.
21917 Arguments have same meaning as for previous function */
21918 static void
21921 rtx orig_value)
21922 {
21923 rtx destexp;
21924 rtx countreg;
21925 HOST_WIDE_INT rounded_count;
21932 {
21936 }
21937 else
21940 {
21945 }
21949 }
21951 static void
21954 {
21958 }
21960 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21961 static void
21964 {
21967 {
21972 {
21974 {
21977 }
21978 else
21981 }
21983 {
21986 else
21987 {
21990 }
21992 }
21994 {
21997 }
21999 {
22002 }
22004 {
22007 }
22009 }
22011 {
22017 }
22019 /* When there are stringops, we can cheaply increase dest and src pointers.
22020 Otherwise we save code size by maintaining offset (zero is readily
22021 available from preceding rep operation) and using x86 addressing modes.
22022 */
22024 {
22026 {
22033 }
22035 {
22042 }
22044 {
22051 }
22052 }
22053 else
22054 {
22056 rtx tmp;
22059 {
22070 }
22072 {
22085 }
22087 {
22096 }
22097 }
22098 }
22100 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22101 static void
22104 {
22105 count =
22111 }
22113 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22114 static void
22116 {
22117 rtx dest;
22120 {
22125 {
22127 {
22132 }
22133 else
22136 }
22138 {
22140 {
22143 }
22144 else
22145 {
22150 }
22152 }
22154 {
22158 }
22160 {
22164 }
22166 {
22170 }
22172 }
22174 {
22177 }
22179 {
22182 {
22186 }
22187 else
22188 {
22194 }
22197 }
22199 {
22202 {
22205 }
22206 else
22207 {
22211 }
22214 }
22216 {
22222 }
22224 {
22230 }
22232 {
22238 }
22239 }
22241 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22242 DESIRED_ALIGNMENT. */
22243 static void
22247 {
22249 {
22257 }
22259 {
22267 }
22269 {
22277 }
22279 }
22281 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22282 ALIGN_BYTES is how many bytes need to be copied. */
22283 static rtx
22286 {
22295 {
22300 }
22302 {
22313 }
22315 {
22321 {
22329 }
22332 }
22338 {
22350 }
22357 }
22359 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22360 DESIRED_ALIGNMENT. */
22361 static void
22364 {
22366 {
22373 }
22375 {
22382 }
22384 {
22391 }
22393 }
22395 /* Set enough from DST to align DST known to by aligned by ALIGN to
22396 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22397 static rtx
22400 {
22404 {
22409 }
22411 {
22418 }
22420 {
22427 }
22434 }
22436 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22437 static enum stringop_alg
22440 {
22443 /* Algorithms using the rep prefix want at least edi and ecx;
22444 additionally, memset wants eax and memcpy wants esi. Don't
22445 consider such algorithms if the user has appropriated those
22446 registers for their own purposes. */
22448 || (memset
22452 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22453 || (alg != rep_prefix_1_byte \
22454 && alg != rep_prefix_4_byte \
22455 && alg != rep_prefix_8_byte))
22458 /* Even if the string operation call is cold, we still might spend a lot
22459 of time processing large blocks. */
22464 else
22472 else
22476 /* rep; movq or rep; movl is the smallest variant. */
22478 {
22481 else
22483 }
22484 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22485 */
22489 {
22493 {
22494 /* We get here if the algorithms that were not libcall-based
22495 were rep-prefix based and we are unable to use rep prefixes
22496 based on global register usage. Break out of the loop and
22497 use the heuristic below. */
22501 {
22506 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22507 last non-libcall inline algorithm. */
22509 {
22510 /* When the current size is best to be copied by a libcall,
22511 but we are still forced to inline, run the heuristic below
22512 that will pick code for medium sized blocks. */
22516 }
22518 {
22521 }
22522 }
22523 }
22525 }
22526 /* When asked to inline the call anyway, try to pick meaningful choice.
22527 We look for maximal size of block that is faster to copy by hand and
22528 take blocks of at most of that size guessing that average size will
22529 be roughly half of the block.
22531 If this turns out to be bad, we might simply specify the preferred
22532 choice in ix86_costs. */
22535 {
22542 {
22549 }
22550 /* If there aren't any usable algorithms, then recursing on
22551 smaller sizes isn't going to find anything. Just return the
22552 simple byte-at-a-time copy loop. */
22554 {
22555 /* Pick something reasonable. */
22559 }
22568 }
22570 #undef ALG_USABLE_P
22571 }
22573 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22574 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22575 static int
22579 {
22582 {
22593 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22594 copying whole cacheline at once. */
22597 else
22601 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22602 copying whole cacheline at once. */
22605 else
22613 }
22622 }
22624 /* Return the smallest power of 2 greater than VAL. */
22625 static int
22627 {
22632 }
22634 /* Expand string move (memcpy) operation. Use i386 string operations
22635 when profitable. expand_setmem contains similar code. The code
22636 depends upon architecture, block size and alignment, but always has
22637 the same overall structure:
22639 1) Prologue guard: Conditional that jumps up to epilogues for small
22640 blocks that can be handled by epilogue alone. This is faster
22641 but also needed for correctness, since prologue assume the block
22642 is larger than the desired alignment.
22644 Optional dynamic check for size and libcall for large
22645 blocks is emitted here too, with -minline-stringops-dynamically.
22647 2) Prologue: copy first few bytes in order to get destination
22648 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22649 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22650 copied. We emit either a jump tree on power of two sized
22651 blocks, or a byte loop.
22653 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22654 with specified algorithm.
22656 4) Epilogue: code copying tail of the block that is too small to be
22657 handled by main body (or up to size guarded by prologue guard). */
22659 bool
22662 {
22663 rtx destreg;
22664 rtx srcreg;
22666 rtx tmp;
22680 /* i386 can do misaligned access on reasonably increased cost. */
22684 /* ALIGN is the minimum of destination and source alignment, but we care here
22685 just about destination alignment. */
22694 /* Make sure we don't need to care about overflow later on. */
22698 /* Step 0: Decide on preferred algorithm, desired alignment and
22699 size of chunks to be copied by main loop. */
22715 {
22740 }
22744 /* Step 1: Prologue guard. */
22746 /* Alignment code needs count to be in register. */
22748 {
22751 {
22752 align_bytes
22756 else
22758 }
22761 }
22764 /* Ensure that alignment prologue won't copy past end of block. */
22766 {
22768 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22769 Make sure it is power of 2. */
22773 {
22775 {
22776 /* If main algorithm works on QImode, no epilogue is needed.
22777 For small sizes just don't align anything. */
22780 else
22782 }
22783 }
22784 else
22785 {
22792 else
22794 }
22795 }
22797 /* Emit code to decide on runtime whether library call or inline should be
22798 used. */
22800 {
22802 {
22804 {
22808 }
22809 }
22810 else
22811 {
22820 }
22821 }
22823 /* Step 2: Alignment prologue. */
22826 {
22828 {
22829 /* Except for the first move in epilogue, we no longer know
22830 constant offset in aliasing info. It don't seems to worth
22831 the pain to maintain it for the first move, so throw away
22832 the info early. */
22836 desired_align);
22837 }
22838 else
22839 {
22840 /* If we know how many bytes need to be stored before dst is
22841 sufficiently aligned, maintain aliasing info accurately. */
22847 }
22853 {
22854 /* It is possible that we copied enough so the main loop will not
22855 execute. */
22865 else
22867 }
22868 }
22870 {
22875 }
22879 /* Step 3: Main loop. */
22882 {
22895 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22896 registers for 4 temporaries anyway. */
22899 expected_size);
22903 DImode);
22907 SImode);
22911 QImode);
22913 }
22914 /* Adjust properly the offset of src and dest memory for aliasing. */
22916 {
22921 }
22922 else
22923 {
22926 }
22928 /* Step 4: Epilogue to copy the remaining bytes. */
22929 epilogue:
22931 {
22932 /* When the main loop is done, COUNT_EXP might hold original count,
22933 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22934 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22935 bytes. Compensate if needed. */
22938 {
22939 tmp =
22942 OPTAB_DIRECT);
22945 }
22948 }
22952 epilogue_size_needed);
22956 }
22958 /* Helper function for memcpy. For QImode value 0xXY produce
22959 0xXYXYXYXY of wide specified by MODE. This is essentially
22960 a * 0x10101010, but we can do slightly better than
22961 synth_mult by unwinding the sequence by hand on CPUs with
22962 slow multiply. */
22963 static rtx
22965 {
22967 rtx tmp;
22974 {
22982 }
22991 nops--;
22996 {
23000 OPTAB_DIRECT);
23001 }
23002 else
23003 {
23009 else
23011 else
23012 {
23015 reg =
23017 }
23027 }
23028 }
23030 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23031 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23032 alignment from ALIGN to DESIRED_ALIGN. */
23033 static rtx
23035 {
23036 rtx promoted_val;
23045 else
23049 }
23051 /* Expand string clear operation (bzero). Use i386 string operations when
23052 profitable. See expand_movmem comment for explanation of individual
23053 steps performed. */
23054 bool
23057 {
23058 rtx destreg;
23060 rtx tmp;
23076 /* i386 can do misaligned access on reasonably increased cost. */
23085 /* Make sure we don't need to care about overflow later on. */
23089 /* Step 0: Decide on preferred algorithm, desired alignment and
23090 size of chunks to be copied by main loop. */
23105 {
23130 }
23133 /* Step 1: Prologue guard. */
23135 /* Alignment code needs count to be in register. */
23137 {
23140 {
23141 align_bytes
23145 else
23147 }
23149 {
23154 }
23155 }
23156 /* Do the cheap promotion to allow better CSE across the
23157 main loop and epilogue (ie one load of the big constant in the
23158 front of all code. */
23162 /* Ensure that alignment prologue won't copy past end of block. */
23164 {
23166 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23167 Make sure it is power of 2. */
23170 /* To improve performance of small blocks, we jump around the VAL
23171 promoting mode. This mean that if the promoted VAL is not constant,
23172 we might not use it in the epilogue and have to use byte
23173 loop variant. */
23177 {
23179 {
23180 /* If main algorithm works on QImode, no epilogue is needed.
23181 For small sizes just don't align anything. */
23184 else
23186 }
23187 }
23188 else
23189 {
23196 else
23198 }
23199 }
23201 {
23210 }
23212 /* Step 2: Alignment prologue. */
23214 /* Do the expensive promotion once we branched off the small blocks. */
23221 {
23223 {
23224 /* Except for the first move in epilogue, we no longer know
23225 constant offset in aliasing info. It don't seems to worth
23226 the pain to maintain it for the first move, so throw away
23227 the info early. */
23230 desired_align);
23231 }
23232 else
23233 {
23234 /* If we know how many bytes need to be stored before dst is
23235 sufficiently aligned, maintain aliasing info accurately. */
23241 }
23247 {
23248 /* It is possible that we copied enough so the main loop will not
23249 execute. */
23259 else
23261 }
23262 }
23264 {
23270 }
23274 /* Step 3: Main loop. */
23277 {
23305 }
23306 /* Adjust properly the offset of src and dest memory for aliasing. */
23310 else
23313 /* Step 4: Epilogue to copy the remaining bytes. */
23316 {
23317 /* When the main loop is done, COUNT_EXP might hold original count,
23318 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23319 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23320 bytes. Compensate if needed. */
23323 {
23324 tmp =
23327 OPTAB_DIRECT);
23330 }
23333 }
23334 epilogue:
23336 {
23339 epilogue_size_needed);
23340 else
23342 epilogue_size_needed);
23343 }
23347 }
23349 /* Expand the appropriate insns for doing strlen if not just doing
23350 repnz; scasb
23352 out = result, initialized with the start address
23353 align_rtx = alignment of the address.
23354 scratch = scratch register, initialized with the startaddress when
23355 not aligned, otherwise undefined
23357 This is just the body. It needs the initializations mentioned above and
23358 some address computing at the end. These things are done in i386.md. */
23360 static void
23362 {
23364 rtx tmp;
23369 rtx mem;
23372 rtx cmp;
23378 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23380 /* Is there a known alignment and is it less than 4? */
23382 {
23385 /* Is there a known alignment and is it not 2? */
23387 {
23391 /* Leave just the 3 lower bits. */
23401 }
23402 else
23403 {
23404 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23405 check if is aligned to 4 - byte. */
23412 }
23416 /* Now compare the bytes. */
23418 /* Compare the first n unaligned byte on a byte per byte basis. */
23422 /* Increment the address. */
23425 /* Not needed with an alignment of 2 */
23427 {
23431 end_0_label);
23436 }
23439 end_0_label);
23442 }
23444 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23445 align this loop. It gives only huge programs, but does not help to
23446 speed up. */
23453 /* This formula yields a nonzero result iff one of the bytes is zero.
23454 This saves three branches inside loop and many cycles. */
23462 align_4_label);
23465 {
23471 /* If zero is not in the first two bytes, move two bytes forward. */
23477 reg,
23478 tmpreg)));
23479 /* Emit lea manually to avoid clobbering of flags. */
23487 reg2,
23488 out)));
23489 }
23490 else
23491 {
23493 /* Is zero in the first two bytes? */
23500 pc_rtx);
23504 /* Not in the first two. Move two bytes forward. */
23510 }
23512 /* Avoid branch in fixing the byte. */
23520 }
23522 /* Expand strlen. */
23524 bool
23526 {
23529 /* The generic case of strlen expander is long. Avoid it's
23530 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23533 && !TARGET_INLINE_ALL_STRINGOPS
23543 {
23544 /* Well it seems that some optimizer does not combine a call like
23545 foo(strlen(bar), strlen(bar));
23546 when the move and the subtraction is done here. It does calculate
23547 the length just once when these instructions are done inside of
23548 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23549 often used and I use one fewer register for the lifetime of
23550 output_strlen_unroll() this is better. */
23556 /* strlensi_unroll_1 returns the address of the zero at the end of
23557 the string, like memchr(), so compute the length by subtracting
23558 the start address. */
23560 }
23561 else
23562 {
23563 rtx unspec;
23565 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23578 /* If .md starts supporting :P, this can be done in .md. */
23584 }
23586 }
23588 /* For given symbol (function) construct code to compute address of it's PLT
23589 entry in large x86-64 PIC model. */
23590 static rtx
23592 {
23605 }
23607 rtx
23609 rtx callarg2,
23611 {
23612 /* We need to represent that SI and DI registers are clobbered
23613 by SYSV calls. */
23619 };
23629 {
23630 #if TARGET_MACHO
23633 #endif
23634 }
23635 else
23636 {
23637 /* Static functions and indirect calls don't need the pic register. */
23642 }
23645 {
23649 }
23659 {
23662 }
23671 {
23675 }
23679 {
23683 UNSPEC_MS_TO_SYSV_CALL);
23691 }
23700 }
23702 /* Output the assembly for a call instruction. */
23706 {
23712 {
23715 /* SEH epilogue detection requires the indirect branch case
23716 to include REX.W. */
23719 else
23724 }
23726 /* SEH unwinding can require an extra nop to be emitted in several
23727 circumstances. Determine if we have one of those. */
23729 {
23730 rtx i;
23733 {
23734 /* If we get to another real insn, we don't need the nop. */
23738 /* If we get to the epilogue note, prevent a catch region from
23739 being adjacent to the standard epilogue sequence. If non-
23740 call-exceptions, we'll have done this during epilogue emission. */
23742 && !flag_non_call_exceptions
23744 {
23747 }
23748 }
23750 /* If we didn't find a real insn following the call, prevent the
23751 unwinder from looking into the next function. */
23754 }
23758 else
23767 }
23768 \f
23769 /* Clear stack slot assignments remembered from previous functions.
23770 This is called from INIT_EXPANDERS once before RTL is emitted for each
23771 function. */
23775 {
23783 }
23785 /* Return a MEM corresponding to a stack slot with mode MODE.
23786 Allocate a new slot if necessary.
23788 The RTL for a function can have several slots available: N is
23789 which slot to use. */
23791 rtx
23793 {
23810 }
23812 static void
23814 {
23820 }
23821 \f
23822 /* Calculate the length of the memory address in the instruction encoding.
23823 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23824 or other prefixes. We never generate addr32 prefix for LEA insn. */
23826 int
23828 {
23845 /* If this is not LEA instruction, add the length of addr32 prefix. */
23850 len++;
23864 /* Rule of thumb:
23865 - esp as the base always wants an index,
23866 - ebp as the base always wants a displacement,
23867 - r12 as the base always wants an index,
23868 - r13 as the base always wants a displacement. */
23870 /* Register Indirect. */
23872 {
23873 /* esp (for its index) and ebp (for its displacement) need
23874 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23875 code. */
23882 len++;
23883 }
23885 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23886 is not disp32, but disp32(%rip), so for disp32
23887 SIB byte is needed, unless print_operand_address
23888 optimizes it into disp32(%rip) or (%rip) is implied
23889 by UNSPEC. */
23891 {
23894 {
23910 len++;
23911 }
23912 }
23913 else
23914 {
23915 /* Find the length of the displacement constant. */
23917 {
23920 else
23922 }
23923 /* ebp always wants a displacement. Similarly r13. */
23925 len++;
23927 /* An index requires the two-byte modrm form.... */
23929 /* ...like esp (or r12), which always wants an index. */
23933 len++;
23934 }
23937 }
23939 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23940 is set, expect that insn have 8bit immediate alternative. */
23941 int
23943 {
23949 {
23954 {
23957 {
23969 }
23971 {
23974 }
23975 }
23977 {
23987 /* Immediates for DImode instructions are encoded
23988 as 32bit sign extended values. */
23994 }
23995 }
23997 }
23999 /* Compute default value for "length_address" attribute. */
24000 int
24002 {
24006 {
24017 }
24022 {
24025 {
24030 constraints++;
24033 ;
24034 /* Skip ignored operands. */
24037 }
24039 }
24041 }
24043 /* Compute default value for "length_vex" attribute. It includes
24044 2 or 3 byte VEX prefix and 1 opcode byte. */
24046 int
24048 {
24051 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24052 byte VEX prefix. */
24056 /* We can always use 2 byte VEX prefix in 32bit. */
24064 {
24065 /* REX.W bit uses 3 byte VEX prefix. */
24069 }
24070 else
24071 {
24072 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24076 }
24079 }
24080 \f
24081 /* Return the maximum number of instructions a cpu can issue. */
24083 static int
24085 {
24087 {
24113 }
24114 }
24116 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24117 by DEP_INSN and nothing set by DEP_INSN. */
24119 static bool
24121 {
24124 /* Simplify the test for uninteresting insns. */
24132 {
24135 }
24140 {
24143 }
24144 else
24150 /* This test is true if the dependent insn reads the flags but
24151 not any other potentially set register. */
24159 }
24161 /* Return true iff USE_INSN has a memory address with operands set by
24162 SET_INSN. */
24164 bool
24166 {
24171 {
24174 }
24176 }
24178 static int
24180 {
24186 /* Anti and output dependencies have zero cost on all CPUs. */
24192 /* If we can't recognize the insns, we can't really do anything. */
24200 {
24202 /* Address Generation Interlock adds a cycle of latency. */
24204 {
24215 }
24219 /* ??? Compares pair with jump/setcc. */
24223 /* Floating point stores require value to be ready one cycle earlier. */
24233 /* INT->FP conversion is expensive. */
24237 /* There is one cycle extra latency between an FP op and a store. */
24245 /* Show ability of reorder buffer to hide latency of load by executing
24246 in parallel with previous instruction in case
24247 previous instruction is not needed to compute the address. */
24250 {
24251 /* Claim moves to take one cycle, as core can issue one load
24252 at time and the next load can start cycle later. */
24257 cost--;
24258 }
24264 /* The esp dependency is resolved before the instruction is really
24265 finished. */
24270 /* INT->FP conversion is expensive. */
24274 /* Show ability of reorder buffer to hide latency of load by executing
24275 in parallel with previous instruction in case
24276 previous instruction is not needed to compute the address. */
24279 {
24280 /* Claim moves to take one cycle, as core can issue one load
24281 at time and the next load can start cycle later. */
24287 else
24289 }
24305 /* Show ability of reorder buffer to hide latency of load by executing
24306 in parallel with previous instruction in case
24307 previous instruction is not needed to compute the address. */
24310 {
24314 /* Because of the difference between the length of integer and
24315 floating unit pipeline preparation stages, the memory operands
24316 for floating point are cheaper.
24318 ??? For Athlon it the difference is most probably 2. */
24321 else
24326 else
24328 }
24332 }
24335 }
24337 /* How many alternative schedules to try. This should be as wide as the
24338 scheduling freedom in the DFA, but no wider. Making this value too
24339 large results extra work for the scheduler. */
24341 static int
24343 {
24345 {
24357 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24358 as many instructions can be executed on a cycle, i.e.,
24359 issue_rate. I wonder why tuning for many CPUs does not do this. */
24362 /* Don't use lookahead for pre-reload schedule to save compile time. */
24367 }
24368 }
24370 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24371 execution. It is applied if
24372 (1) IMUL instruction is on the top of list;
24373 (2) There exists the only producer of independent IMUL instruction in
24374 ready list;
24375 (3) Put found producer on the top of ready list.
24376 Returns issue rate. */
24378 static int
24381 {
24386 sd_iterator_def sd_it;
24387 dep_t dep;
24390 /* Set up issue rate. */
24393 /* Do reodering for Atom only. */
24396 /* Do not perform ready list reodering for pre-reload schedule pass. */
24399 /* Nothing to do if ready list contains only 1 instruction. */
24403 /* Check that IMUL instruction is on the top of ready list. */
24416 /* Search for producer of independent IMUL instruction. */
24418 {
24422 /* Skip IMUL instruction. */
24432 {
24433 rtx con;
24444 {
24445 sd_iterator_def sd_it1;
24446 dep_t dep1;
24447 /* Check if there is no other dependee for IMUL. */
24450 {
24451 rtx pro;
24457 }
24460 }
24461 }
24464 }
24472 /* Put IMUL producer (ready[index]) at the top of ready list. */
24479 }
24481 static bool
24484 /* Returns true if lhs of insn is HW function argument register and set up
24485 is_spilled to true if it is likely spilled HW register. */
24486 static bool
24488 {
24489 rtx dst;
24493 /* Call instructions are not movable, ignore it. */
24504 {
24505 /* Is it likely spilled HW register? */
24510 }
24512 }
24514 /* Add output dependencies for chain of function adjacent arguments if only
24515 there is a move to likely spilled HW register. Return first argument
24516 if at least one dependence was added or NULL otherwise. */
24517 static rtx
24519 {
24520 rtx insn;
24527 /* Find nearest to call argument passing instruction. */
24529 {
24538 }
24542 {
24549 {
24552 }
24554 {
24555 /* Add output depdendence between two function arguments if chain
24556 of output arguments contains likely spilled HW registers. */
24560 }
24561 else
24563 }
24567 }
24569 /* Add output or anti dependency from insn to first_arg to restrict its code
24570 motion. */
24571 static void
24573 {
24574 rtx set;
24575 rtx tmp;
24582 {
24583 /* Add output dependency to the first function argument. */
24586 }
24587 /* Add anti dependency. */
24589 }
24591 /* Avoid cross block motion of function argument through adding dependency
24592 from the first non-jump instruction in bb. */
24593 static void
24595 {
24599 {
24601 {
24604 {
24607 }
24608 }
24612 }
24613 }
24615 /* Hook for pre-reload schedule - avoid motion of function arguments
24616 passed in likely spilled HW registers. */
24617 static void
24619 {
24620 rtx insn;
24628 {
24631 {
24632 /* Add dependee for first argument to predecessors if only
24633 region contains more than one block. */
24637 /* Skip trivial regions and region head blocks that can have
24638 predecessors outside of region. */
24640 {
24641 edge e;
24642 edge_iterator ei;
24643 /* Assume that region is SCC, i.e. all immediate predecessors
24644 of non-head block are in the same region. */
24646 {
24647 /* Avoid creating of loop-carried dependencies through
24648 using topological odering in region. */
24651 }
24652 }
24656 }
24657 }
24660 }
24662 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24663 HW registers to maximum, to schedule them at soon as possible. These are
24664 moves from function argument registers at the top of the function entry
24665 and moves from function return value registers after call. */
24666 static int
24668 {
24669 rtx set;
24679 {
24686 }
24689 }
24691 /* Model decoder of Core 2/i7.
24692 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24693 track the instruction fetch block boundaries and make sure that long
24694 (9+ bytes) instructions are assigned to D0. */
24696 /* Maximum length of an insn that can be handled by
24697 a secondary decoder unit. '8' for Core 2/i7. */
24700 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24701 '16' for Core 2/i7. */
24704 /* Maximum number of instructions decoder can handle per cycle.
24705 '6' for Core 2/i7. */
24709 ix86_first_cycle_multipass_data_t;
24711 const_ix86_first_cycle_multipass_data_t;
24713 /* A variable to store target state across calls to max_issue within
24714 one cycle. */
24718 /* Initialize DATA. */
24719 static void
24721 {
24722 ix86_first_cycle_multipass_data_t data
24729 }
24731 /* Advancing the cycle; reset ifetch block counts. */
24732 static void
24734 {
24741 }
24745 /* Filter out insns from ready_try that the core will not be able to issue
24746 on current cycle due to decoder. */
24747 static void
24748 core2i7_first_cycle_multipass_filter_ready_try
24751 {
24753 {
24754 rtx insn;
24764 (!first_cycle_insn_p
24766 /* ... or it would not fit into the ifetch block ... */
24768 /* ... or the decoder is full already ... */
24770 /* ... mask the insn out. */
24771 {
24776 }
24777 }
24778 }
24780 /* Prepare for a new round of multipass lookahead scheduling. */
24781 static void
24784 {
24785 ix86_first_cycle_multipass_data_t data
24787 const_ix86_first_cycle_multipass_data_t prev_data
24790 /* Restore the state from the end of the previous round. */
24794 /* Filter instructions that cannot be issued on current cycle due to
24795 decoder restrictions. */
24797 first_cycle_insn_p);
24798 }
24800 /* INSN is being issued in current solution. Account for its impact on
24801 the decoder model. */
24802 static void
24805 {
24806 ix86_first_cycle_multipass_data_t data
24808 const_ix86_first_cycle_multipass_data_t prev_data
24818 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24820 {
24823 }
24825 {
24829 }
24832 /* Filter out insns from ready_try that the core will not be able to issue
24833 on current cycle due to decoder. */
24836 }
24838 /* Revert the effect on ready_try. */
24839 static void
24843 {
24844 const_ix86_first_cycle_multipass_data_t data
24847 sbitmap_iterator sbi;
24851 {
24853 }
24854 }
24856 /* Save the result of multipass lookahead scheduling for the next round. */
24857 static void
24859 {
24860 const_ix86_first_cycle_multipass_data_t data
24862 ix86_first_cycle_multipass_data_t next_data
24866 {
24869 }
24870 }
24872 /* Deallocate target data. */
24873 static void
24875 {
24876 ix86_first_cycle_multipass_data_t data
24880 {
24884 }
24885 }
24887 /* Prepare for scheduling pass. */
24888 static void
24892 {
24893 /* Install scheduling hooks for current CPU. Some of these hooks are used
24894 in time-critical parts of the scheduler, so we only set them up when
24895 they are actually used. */
24897 {
24901 /* Do not perform multipass scheduling for pre-reload schedule
24902 to save compile time. */
24904 {
24920 /* Set decoder parameters. */
24925 }
24926 /* ... Fall through ... */
24936 }
24937 }
24939 \f
24940 /* Compute the alignment given to a constant that is being placed in memory.
24941 EXP is the constant and ALIGN is the alignment that the object would
24942 ordinarily have.
24943 The value of this function is used instead of that alignment to align
24944 the object. */
24946 int
24948 {
24951 {
24956 }
24962 }
24964 /* Compute the alignment for a static variable.
24965 TYPE is the data type, and ALIGN is the alignment that
24966 the object would ordinarily have. The value of this function is used
24967 instead of that alignment to align the object. */
24969 int
24971 {
24972 int max_align
24983 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24984 to 16byte boundary. */
24986 {
24993 }
24996 {
25001 }
25003 {
25010 }
25015 {
25020 }
25023 {
25028 }
25031 }
25033 /* Compute the alignment for a local variable or a stack slot. EXP is
25034 the data type or decl itself, MODE is the widest mode available and
25035 ALIGN is the alignment that the object would ordinarily have. The
25036 value of this macro is used instead of that alignment to align the
25037 object. */
25039 unsigned int
25042 {
25046 {
25049 }
25050 else
25051 {
25054 }
25056 /* Don't do dynamic stack realignment for long long objects with
25057 -mpreferred-stack-boundary=2. */
25066 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25067 register in MODE. We will return the largest alignment of XF
25068 and DF. */
25070 {
25074 }
25076 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25077 to 16byte boundary. Exact wording is:
25079 An array uses the same alignment as its elements, except that a local or
25080 global array variable of length at least 16 bytes or
25081 a C99 variable-length array variable always has alignment of at least 16 bytes.
25083 This was added to allow use of aligned SSE instructions at arrays. This
25084 rule is meant for static storage (where compiler can not do the analysis
25085 by itself). We follow it for automatic variables only when convenient.
25086 We fully control everything in the function compiled and functions from
25087 other unit can not rely on the alignment.
25089 Exclude va_list type. It is the common case of local array where
25090 we can not benefit from the alignment. */
25093 {
25103 }
25105 {
25110 }
25112 {
25118 }
25123 {
25128 }
25131 {
25137 }
25139 }
25141 /* Compute the minimum required alignment for dynamic stack realignment
25142 purposes for a local variable, parameter or a stack slot. EXP is
25143 the data type or decl itself, MODE is its mode and ALIGN is the
25144 alignment that the object would ordinarily have. */
25146 unsigned int
25149 {
25153 {
25156 }
25157 else
25158 {
25161 }
25166 /* Don't do dynamic stack realignment for long long objects with
25167 -mpreferred-stack-boundary=2. */
25174 }
25175 \f
25176 /* Find a location for the static chain incoming to a nested function.
25177 This is a register, unless all free registers are used by arguments. */
25179 static rtx
25181 {
25188 {
25189 /* We always use R10 in 64-bit mode. */
25191 }
25192 else
25193 {
25194 tree fntype;
25197 /* By default in 32-bit mode we use ECX to pass the static chain. */
25203 {
25204 /* Fastcall functions use ecx/edx for arguments, which leaves
25205 us with EAX for the static chain.
25206 Thiscall functions use ecx for arguments, which also
25207 leaves us with EAX for the static chain. */
25209 }
25211 {
25212 /* Thiscall functions use ecx for arguments, which leaves
25213 us with EAX and EDX for the static chain.
25214 We are using for abi-compatibility EAX. */
25216 }
25218 {
25219 /* For regparm 3, we have no free call-clobbered registers in
25220 which to store the static chain. In order to implement this,
25221 we have the trampoline push the static chain to the stack.
25222 However, we can't push a value below the return address when
25223 we call the nested function directly, so we have to use an
25224 alternate entry point. For this we use ESI, and have the
25225 alternate entry point push ESI, so that things appear the
25226 same once we're executing the nested function. */
25228 {
25234 }
25236 }
25237 }
25240 }
25242 /* Emit RTL insns to initialize the variable parts of a trampoline.
25243 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25244 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25245 to be passed to the target function. */
25247 static void
25249 {
25257 {
25260 /* Load the function address to r11. Try to load address using
25261 the shorter movl instead of movabs. We may want to support
25262 movq for kernel mode, but kernel does not use trampolines at
25263 the moment. FNADDR is a 32bit address and may not be in
25264 DImode when ptr_mode == SImode. Always use movl in this
25265 case. */
25268 {
25277 }
25278 else
25279 {
25286 }
25288 /* Load static chain using movabs to r10. Use the shorter movl
25289 instead of movabs when ptr_mode == SImode. */
25291 {
25294 }
25295 else
25296 {
25299 }
25308 /* Jump to r11; the last (unused) byte is a nop, only there to
25309 pad the write out to a single 32-bit store. */
25313 }
25314 else
25315 {
25318 /* Depending on the static chain location, either load a register
25319 with a constant, or push the constant to the stack. All of the
25320 instructions are the same size. */
25323 {
25325 {
25332 }
25333 }
25334 else
25349 /* Compute offset from the end of the jmp to the target function.
25350 In the case in which the trampoline stores the static chain on
25351 the stack, we need to skip the first insn which pushes the
25352 (call-saved) register static chain; this push is 1 byte. */
25359 }
25363 #ifdef HAVE_ENABLE_EXECUTE_STACK
25364 #ifdef CHECK_EXECUTE_STACK_ENABLED
25366 #endif
25369 #endif
25370 }
25371 \f
25372 /* The following file contains several enumerations and data structures
25373 built from the definitions in i386-builtin-types.def. */
25377 /* Table for the ix86 builtin non-function types. */
25380 /* Retrieve an element from the above table, building some of
25381 the types lazily. */
25383 static tree
25385 {
25397 {
25405 }
25406 else
25407 {
25413 else
25421 }
25425 }
25427 /* Table for the ix86 builtin function types. */
25430 /* Retrieve an element from the above table, building some of
25431 the types lazily. */
25433 static tree
25435 {
25436 tree type;
25445 {
25453 {
25456 }
25459 }
25460 else
25461 {
25467 }
25471 }
25474 /* Codes for all the SSE/MMX builtins. */
25475 enum ix86_builtins
25476 {
25477 IX86_BUILTIN_ADDPS,
25478 IX86_BUILTIN_ADDSS,
25479 IX86_BUILTIN_DIVPS,
25480 IX86_BUILTIN_DIVSS,
25481 IX86_BUILTIN_MULPS,
25482 IX86_BUILTIN_MULSS,
25483 IX86_BUILTIN_SUBPS,
25484 IX86_BUILTIN_SUBSS,
25486 IX86_BUILTIN_CMPEQPS,
25487 IX86_BUILTIN_CMPLTPS,
25488 IX86_BUILTIN_CMPLEPS,
25489 IX86_BUILTIN_CMPGTPS,
25490 IX86_BUILTIN_CMPGEPS,
25491 IX86_BUILTIN_CMPNEQPS,
25492 IX86_BUILTIN_CMPNLTPS,
25493 IX86_BUILTIN_CMPNLEPS,
25494 IX86_BUILTIN_CMPNGTPS,
25495 IX86_BUILTIN_CMPNGEPS,
25496 IX86_BUILTIN_CMPORDPS,
25497 IX86_BUILTIN_CMPUNORDPS,
25498 IX86_BUILTIN_CMPEQSS,
25499 IX86_BUILTIN_CMPLTSS,
25500 IX86_BUILTIN_CMPLESS,
25501 IX86_BUILTIN_CMPNEQSS,
25502 IX86_BUILTIN_CMPNLTSS,
25503 IX86_BUILTIN_CMPNLESS,
25504 IX86_BUILTIN_CMPNGTSS,
25505 IX86_BUILTIN_CMPNGESS,
25506 IX86_BUILTIN_CMPORDSS,
25507 IX86_BUILTIN_CMPUNORDSS,
25509 IX86_BUILTIN_COMIEQSS,
25510 IX86_BUILTIN_COMILTSS,
25511 IX86_BUILTIN_COMILESS,
25512 IX86_BUILTIN_COMIGTSS,
25513 IX86_BUILTIN_COMIGESS,
25514 IX86_BUILTIN_COMINEQSS,
25515 IX86_BUILTIN_UCOMIEQSS,
25516 IX86_BUILTIN_UCOMILTSS,
25517 IX86_BUILTIN_UCOMILESS,
25518 IX86_BUILTIN_UCOMIGTSS,
25519 IX86_BUILTIN_UCOMIGESS,
25520 IX86_BUILTIN_UCOMINEQSS,
25522 IX86_BUILTIN_CVTPI2PS,
25523 IX86_BUILTIN_CVTPS2PI,
25524 IX86_BUILTIN_CVTSI2SS,
25525 IX86_BUILTIN_CVTSI642SS,
25526 IX86_BUILTIN_CVTSS2SI,
25527 IX86_BUILTIN_CVTSS2SI64,
25528 IX86_BUILTIN_CVTTPS2PI,
25529 IX86_BUILTIN_CVTTSS2SI,
25530 IX86_BUILTIN_CVTTSS2SI64,
25532 IX86_BUILTIN_MAXPS,
25533 IX86_BUILTIN_MAXSS,
25534 IX86_BUILTIN_MINPS,
25535 IX86_BUILTIN_MINSS,
25537 IX86_BUILTIN_LOADUPS,
25538 IX86_BUILTIN_STOREUPS,
25539 IX86_BUILTIN_MOVSS,
25541 IX86_BUILTIN_MOVHLPS,
25542 IX86_BUILTIN_MOVLHPS,
25543 IX86_BUILTIN_LOADHPS,
25544 IX86_BUILTIN_LOADLPS,
25545 IX86_BUILTIN_STOREHPS,
25546 IX86_BUILTIN_STORELPS,
25548 IX86_BUILTIN_MASKMOVQ,
25549 IX86_BUILTIN_MOVMSKPS,
25550 IX86_BUILTIN_PMOVMSKB,
25552 IX86_BUILTIN_MOVNTPS,
25553 IX86_BUILTIN_MOVNTQ,
25555 IX86_BUILTIN_LOADDQU,
25556 IX86_BUILTIN_STOREDQU,
25558 IX86_BUILTIN_PACKSSWB,
25559 IX86_BUILTIN_PACKSSDW,
25560 IX86_BUILTIN_PACKUSWB,
25562 IX86_BUILTIN_PADDB,
25563 IX86_BUILTIN_PADDW,
25564 IX86_BUILTIN_PADDD,
25565 IX86_BUILTIN_PADDQ,
25566 IX86_BUILTIN_PADDSB,
25567 IX86_BUILTIN_PADDSW,
25568 IX86_BUILTIN_PADDUSB,
25569 IX86_BUILTIN_PADDUSW,
25570 IX86_BUILTIN_PSUBB,
25571 IX86_BUILTIN_PSUBW,
25572 IX86_BUILTIN_PSUBD,
25573 IX86_BUILTIN_PSUBQ,
25574 IX86_BUILTIN_PSUBSB,
25575 IX86_BUILTIN_PSUBSW,
25576 IX86_BUILTIN_PSUBUSB,
25577 IX86_BUILTIN_PSUBUSW,
25579 IX86_BUILTIN_PAND,
25580 IX86_BUILTIN_PANDN,
25581 IX86_BUILTIN_POR,
25582 IX86_BUILTIN_PXOR,
25584 IX86_BUILTIN_PAVGB,
25585 IX86_BUILTIN_PAVGW,
25587 IX86_BUILTIN_PCMPEQB,
25588 IX86_BUILTIN_PCMPEQW,
25589 IX86_BUILTIN_PCMPEQD,
25590 IX86_BUILTIN_PCMPGTB,
25591 IX86_BUILTIN_PCMPGTW,
25592 IX86_BUILTIN_PCMPGTD,
25594 IX86_BUILTIN_PMADDWD,
25596 IX86_BUILTIN_PMAXSW,
25597 IX86_BUILTIN_PMAXUB,
25598 IX86_BUILTIN_PMINSW,
25599 IX86_BUILTIN_PMINUB,
25601 IX86_BUILTIN_PMULHUW,
25602 IX86_BUILTIN_PMULHW,
25603 IX86_BUILTIN_PMULLW,
25605 IX86_BUILTIN_PSADBW,
25606 IX86_BUILTIN_PSHUFW,
25608 IX86_BUILTIN_PSLLW,
25609 IX86_BUILTIN_PSLLD,
25610 IX86_BUILTIN_PSLLQ,
25611 IX86_BUILTIN_PSRAW,
25612 IX86_BUILTIN_PSRAD,
25613 IX86_BUILTIN_PSRLW,
25614 IX86_BUILTIN_PSRLD,
25615 IX86_BUILTIN_PSRLQ,
25616 IX86_BUILTIN_PSLLWI,
25617 IX86_BUILTIN_PSLLDI,
25618 IX86_BUILTIN_PSLLQI,
25619 IX86_BUILTIN_PSRAWI,
25620 IX86_BUILTIN_PSRADI,
25621 IX86_BUILTIN_PSRLWI,
25622 IX86_BUILTIN_PSRLDI,
25623 IX86_BUILTIN_PSRLQI,
25625 IX86_BUILTIN_PUNPCKHBW,
25626 IX86_BUILTIN_PUNPCKHWD,
25627 IX86_BUILTIN_PUNPCKHDQ,
25628 IX86_BUILTIN_PUNPCKLBW,
25629 IX86_BUILTIN_PUNPCKLWD,
25630 IX86_BUILTIN_PUNPCKLDQ,
25632 IX86_BUILTIN_SHUFPS,
25634 IX86_BUILTIN_RCPPS,
25635 IX86_BUILTIN_RCPSS,
25636 IX86_BUILTIN_RSQRTPS,
25637 IX86_BUILTIN_RSQRTPS_NR,
25638 IX86_BUILTIN_RSQRTSS,
25639 IX86_BUILTIN_RSQRTF,
25640 IX86_BUILTIN_SQRTPS,
25641 IX86_BUILTIN_SQRTPS_NR,
25642 IX86_BUILTIN_SQRTSS,
25644 IX86_BUILTIN_UNPCKHPS,
25645 IX86_BUILTIN_UNPCKLPS,
25647 IX86_BUILTIN_ANDPS,
25648 IX86_BUILTIN_ANDNPS,
25649 IX86_BUILTIN_ORPS,
25650 IX86_BUILTIN_XORPS,
25652 IX86_BUILTIN_EMMS,
25653 IX86_BUILTIN_LDMXCSR,
25654 IX86_BUILTIN_STMXCSR,
25655 IX86_BUILTIN_SFENCE,
25657 IX86_BUILTIN_FXSAVE,
25658 IX86_BUILTIN_FXRSTOR,
25659 IX86_BUILTIN_FXSAVE64,
25660 IX86_BUILTIN_FXRSTOR64,
25662 IX86_BUILTIN_XSAVE,
25663 IX86_BUILTIN_XRSTOR,
25664 IX86_BUILTIN_XSAVE64,
25665 IX86_BUILTIN_XRSTOR64,
25667 IX86_BUILTIN_XSAVEOPT,
25668 IX86_BUILTIN_XSAVEOPT64,
25670 /* 3DNow! Original */
25671 IX86_BUILTIN_FEMMS,
25672 IX86_BUILTIN_PAVGUSB,
25673 IX86_BUILTIN_PF2ID,
25674 IX86_BUILTIN_PFACC,
25675 IX86_BUILTIN_PFADD,
25676 IX86_BUILTIN_PFCMPEQ,
25677 IX86_BUILTIN_PFCMPGE,
25678 IX86_BUILTIN_PFCMPGT,
25679 IX86_BUILTIN_PFMAX,
25680 IX86_BUILTIN_PFMIN,
25681 IX86_BUILTIN_PFMUL,
25682 IX86_BUILTIN_PFRCP,
25683 IX86_BUILTIN_PFRCPIT1,
25684 IX86_BUILTIN_PFRCPIT2,
25685 IX86_BUILTIN_PFRSQIT1,
25686 IX86_BUILTIN_PFRSQRT,
25687 IX86_BUILTIN_PFSUB,
25688 IX86_BUILTIN_PFSUBR,
25689 IX86_BUILTIN_PI2FD,
25690 IX86_BUILTIN_PMULHRW,
25692 /* 3DNow! Athlon Extensions */
25693 IX86_BUILTIN_PF2IW,
25694 IX86_BUILTIN_PFNACC,
25695 IX86_BUILTIN_PFPNACC,
25696 IX86_BUILTIN_PI2FW,
25697 IX86_BUILTIN_PSWAPDSI,
25698 IX86_BUILTIN_PSWAPDSF,
25700 /* SSE2 */
25701 IX86_BUILTIN_ADDPD,
25702 IX86_BUILTIN_ADDSD,
25703 IX86_BUILTIN_DIVPD,
25704 IX86_BUILTIN_DIVSD,
25705 IX86_BUILTIN_MULPD,
25706 IX86_BUILTIN_MULSD,
25707 IX86_BUILTIN_SUBPD,
25708 IX86_BUILTIN_SUBSD,
25710 IX86_BUILTIN_CMPEQPD,
25711 IX86_BUILTIN_CMPLTPD,
25712 IX86_BUILTIN_CMPLEPD,
25713 IX86_BUILTIN_CMPGTPD,
25714 IX86_BUILTIN_CMPGEPD,
25715 IX86_BUILTIN_CMPNEQPD,
25716 IX86_BUILTIN_CMPNLTPD,
25717 IX86_BUILTIN_CMPNLEPD,
25718 IX86_BUILTIN_CMPNGTPD,
25719 IX86_BUILTIN_CMPNGEPD,
25720 IX86_BUILTIN_CMPORDPD,
25721 IX86_BUILTIN_CMPUNORDPD,
25722 IX86_BUILTIN_CMPEQSD,
25723 IX86_BUILTIN_CMPLTSD,
25724 IX86_BUILTIN_CMPLESD,
25725 IX86_BUILTIN_CMPNEQSD,
25726 IX86_BUILTIN_CMPNLTSD,
25727 IX86_BUILTIN_CMPNLESD,
25728 IX86_BUILTIN_CMPORDSD,
25729 IX86_BUILTIN_CMPUNORDSD,
25731 IX86_BUILTIN_COMIEQSD,
25732 IX86_BUILTIN_COMILTSD,
25733 IX86_BUILTIN_COMILESD,
25734 IX86_BUILTIN_COMIGTSD,
25735 IX86_BUILTIN_COMIGESD,
25736 IX86_BUILTIN_COMINEQSD,
25737 IX86_BUILTIN_UCOMIEQSD,
25738 IX86_BUILTIN_UCOMILTSD,
25739 IX86_BUILTIN_UCOMILESD,
25740 IX86_BUILTIN_UCOMIGTSD,
25741 IX86_BUILTIN_UCOMIGESD,
25742 IX86_BUILTIN_UCOMINEQSD,
25744 IX86_BUILTIN_MAXPD,
25745 IX86_BUILTIN_MAXSD,
25746 IX86_BUILTIN_MINPD,
25747 IX86_BUILTIN_MINSD,
25749 IX86_BUILTIN_ANDPD,
25750 IX86_BUILTIN_ANDNPD,
25751 IX86_BUILTIN_ORPD,
25752 IX86_BUILTIN_XORPD,
25754 IX86_BUILTIN_SQRTPD,
25755 IX86_BUILTIN_SQRTSD,
25757 IX86_BUILTIN_UNPCKHPD,
25758 IX86_BUILTIN_UNPCKLPD,
25760 IX86_BUILTIN_SHUFPD,
25762 IX86_BUILTIN_LOADUPD,
25763 IX86_BUILTIN_STOREUPD,
25764 IX86_BUILTIN_MOVSD,
25766 IX86_BUILTIN_LOADHPD,
25767 IX86_BUILTIN_LOADLPD,
25769 IX86_BUILTIN_CVTDQ2PD,
25770 IX86_BUILTIN_CVTDQ2PS,
25772 IX86_BUILTIN_CVTPD2DQ,
25773 IX86_BUILTIN_CVTPD2PI,
25774 IX86_BUILTIN_CVTPD2PS,
25775 IX86_BUILTIN_CVTTPD2DQ,
25776 IX86_BUILTIN_CVTTPD2PI,
25778 IX86_BUILTIN_CVTPI2PD,
25779 IX86_BUILTIN_CVTSI2SD,
25780 IX86_BUILTIN_CVTSI642SD,
25782 IX86_BUILTIN_CVTSD2SI,
25783 IX86_BUILTIN_CVTSD2SI64,
25784 IX86_BUILTIN_CVTSD2SS,
25785 IX86_BUILTIN_CVTSS2SD,
25786 IX86_BUILTIN_CVTTSD2SI,
25787 IX86_BUILTIN_CVTTSD2SI64,
25789 IX86_BUILTIN_CVTPS2DQ,
25790 IX86_BUILTIN_CVTPS2PD,
25791 IX86_BUILTIN_CVTTPS2DQ,
25793 IX86_BUILTIN_MOVNTI,
25794 IX86_BUILTIN_MOVNTI64,
25795 IX86_BUILTIN_MOVNTPD,
25796 IX86_BUILTIN_MOVNTDQ,
25798 IX86_BUILTIN_MOVQ128,
25800 /* SSE2 MMX */
25801 IX86_BUILTIN_MASKMOVDQU,
25802 IX86_BUILTIN_MOVMSKPD,
25803 IX86_BUILTIN_PMOVMSKB128,
25805 IX86_BUILTIN_PACKSSWB128,
25806 IX86_BUILTIN_PACKSSDW128,
25807 IX86_BUILTIN_PACKUSWB128,
25809 IX86_BUILTIN_PADDB128,
25810 IX86_BUILTIN_PADDW128,
25811 IX86_BUILTIN_PADDD128,
25812 IX86_BUILTIN_PADDQ128,
25813 IX86_BUILTIN_PADDSB128,
25814 IX86_BUILTIN_PADDSW128,
25815 IX86_BUILTIN_PADDUSB128,
25816 IX86_BUILTIN_PADDUSW128,
25817 IX86_BUILTIN_PSUBB128,
25818 IX86_BUILTIN_PSUBW128,
25819 IX86_BUILTIN_PSUBD128,
25820 IX86_BUILTIN_PSUBQ128,
25821 IX86_BUILTIN_PSUBSB128,
25822 IX86_BUILTIN_PSUBSW128,
25823 IX86_BUILTIN_PSUBUSB128,
25824 IX86_BUILTIN_PSUBUSW128,
25826 IX86_BUILTIN_PAND128,
25827 IX86_BUILTIN_PANDN128,
25828 IX86_BUILTIN_POR128,
25829 IX86_BUILTIN_PXOR128,
25831 IX86_BUILTIN_PAVGB128,
25832 IX86_BUILTIN_PAVGW128,
25834 IX86_BUILTIN_PCMPEQB128,
25835 IX86_BUILTIN_PCMPEQW128,
25836 IX86_BUILTIN_PCMPEQD128,
25837 IX86_BUILTIN_PCMPGTB128,
25838 IX86_BUILTIN_PCMPGTW128,
25839 IX86_BUILTIN_PCMPGTD128,
25841 IX86_BUILTIN_PMADDWD128,
25843 IX86_BUILTIN_PMAXSW128,
25844 IX86_BUILTIN_PMAXUB128,
25845 IX86_BUILTIN_PMINSW128,
25846 IX86_BUILTIN_PMINUB128,
25848 IX86_BUILTIN_PMULUDQ,
25849 IX86_BUILTIN_PMULUDQ128,
25850 IX86_BUILTIN_PMULHUW128,
25851 IX86_BUILTIN_PMULHW128,
25852 IX86_BUILTIN_PMULLW128,
25854 IX86_BUILTIN_PSADBW128,
25855 IX86_BUILTIN_PSHUFHW,
25856 IX86_BUILTIN_PSHUFLW,
25857 IX86_BUILTIN_PSHUFD,
25859 IX86_BUILTIN_PSLLDQI128,
25860 IX86_BUILTIN_PSLLWI128,
25861 IX86_BUILTIN_PSLLDI128,
25862 IX86_BUILTIN_PSLLQI128,
25863 IX86_BUILTIN_PSRAWI128,
25864 IX86_BUILTIN_PSRADI128,
25865 IX86_BUILTIN_PSRLDQI128,
25866 IX86_BUILTIN_PSRLWI128,
25867 IX86_BUILTIN_PSRLDI128,
25868 IX86_BUILTIN_PSRLQI128,
25870 IX86_BUILTIN_PSLLDQ128,
25871 IX86_BUILTIN_PSLLW128,
25872 IX86_BUILTIN_PSLLD128,
25873 IX86_BUILTIN_PSLLQ128,
25874 IX86_BUILTIN_PSRAW128,
25875 IX86_BUILTIN_PSRAD128,
25876 IX86_BUILTIN_PSRLW128,
25877 IX86_BUILTIN_PSRLD128,
25878 IX86_BUILTIN_PSRLQ128,
25880 IX86_BUILTIN_PUNPCKHBW128,
25881 IX86_BUILTIN_PUNPCKHWD128,
25882 IX86_BUILTIN_PUNPCKHDQ128,
25883 IX86_BUILTIN_PUNPCKHQDQ128,
25884 IX86_BUILTIN_PUNPCKLBW128,
25885 IX86_BUILTIN_PUNPCKLWD128,
25886 IX86_BUILTIN_PUNPCKLDQ128,
25887 IX86_BUILTIN_PUNPCKLQDQ128,
25889 IX86_BUILTIN_CLFLUSH,
25890 IX86_BUILTIN_MFENCE,
25891 IX86_BUILTIN_LFENCE,
25892 IX86_BUILTIN_PAUSE,
25894 IX86_BUILTIN_BSRSI,
25895 IX86_BUILTIN_BSRDI,
25896 IX86_BUILTIN_RDPMC,
25897 IX86_BUILTIN_RDTSC,
25898 IX86_BUILTIN_RDTSCP,
25899 IX86_BUILTIN_ROLQI,
25900 IX86_BUILTIN_ROLHI,
25901 IX86_BUILTIN_RORQI,
25902 IX86_BUILTIN_RORHI,
25904 /* SSE3. */
25905 IX86_BUILTIN_ADDSUBPS,
25906 IX86_BUILTIN_HADDPS,
25907 IX86_BUILTIN_HSUBPS,
25908 IX86_BUILTIN_MOVSHDUP,
25909 IX86_BUILTIN_MOVSLDUP,
25910 IX86_BUILTIN_ADDSUBPD,
25911 IX86_BUILTIN_HADDPD,
25912 IX86_BUILTIN_HSUBPD,
25913 IX86_BUILTIN_LDDQU,
25915 IX86_BUILTIN_MONITOR,
25916 IX86_BUILTIN_MWAIT,
25918 /* SSSE3. */
25919 IX86_BUILTIN_PHADDW,
25920 IX86_BUILTIN_PHADDD,
25921 IX86_BUILTIN_PHADDSW,
25922 IX86_BUILTIN_PHSUBW,
25923 IX86_BUILTIN_PHSUBD,
25924 IX86_BUILTIN_PHSUBSW,
25925 IX86_BUILTIN_PMADDUBSW,
25926 IX86_BUILTIN_PMULHRSW,
25927 IX86_BUILTIN_PSHUFB,
25928 IX86_BUILTIN_PSIGNB,
25929 IX86_BUILTIN_PSIGNW,
25930 IX86_BUILTIN_PSIGND,
25931 IX86_BUILTIN_PALIGNR,
25932 IX86_BUILTIN_PABSB,
25933 IX86_BUILTIN_PABSW,
25934 IX86_BUILTIN_PABSD,
25936 IX86_BUILTIN_PHADDW128,
25937 IX86_BUILTIN_PHADDD128,
25938 IX86_BUILTIN_PHADDSW128,
25939 IX86_BUILTIN_PHSUBW128,
25940 IX86_BUILTIN_PHSUBD128,
25941 IX86_BUILTIN_PHSUBSW128,
25942 IX86_BUILTIN_PMADDUBSW128,
25943 IX86_BUILTIN_PMULHRSW128,
25944 IX86_BUILTIN_PSHUFB128,
25945 IX86_BUILTIN_PSIGNB128,
25946 IX86_BUILTIN_PSIGNW128,
25947 IX86_BUILTIN_PSIGND128,
25948 IX86_BUILTIN_PALIGNR128,
25949 IX86_BUILTIN_PABSB128,
25950 IX86_BUILTIN_PABSW128,
25951 IX86_BUILTIN_PABSD128,
25953 /* AMDFAM10 - SSE4A New Instructions. */
25954 IX86_BUILTIN_MOVNTSD,
25955 IX86_BUILTIN_MOVNTSS,
25956 IX86_BUILTIN_EXTRQI,
25957 IX86_BUILTIN_EXTRQ,
25958 IX86_BUILTIN_INSERTQI,
25959 IX86_BUILTIN_INSERTQ,
25961 /* SSE4.1. */
25962 IX86_BUILTIN_BLENDPD,
25963 IX86_BUILTIN_BLENDPS,
25964 IX86_BUILTIN_BLENDVPD,
25965 IX86_BUILTIN_BLENDVPS,
25966 IX86_BUILTIN_PBLENDVB128,
25967 IX86_BUILTIN_PBLENDW128,
25969 IX86_BUILTIN_DPPD,
25970 IX86_BUILTIN_DPPS,
25972 IX86_BUILTIN_INSERTPS128,
25974 IX86_BUILTIN_MOVNTDQA,
25975 IX86_BUILTIN_MPSADBW128,
25976 IX86_BUILTIN_PACKUSDW128,
25977 IX86_BUILTIN_PCMPEQQ,
25978 IX86_BUILTIN_PHMINPOSUW128,
25980 IX86_BUILTIN_PMAXSB128,
25981 IX86_BUILTIN_PMAXSD128,
25982 IX86_BUILTIN_PMAXUD128,
25983 IX86_BUILTIN_PMAXUW128,
25985 IX86_BUILTIN_PMINSB128,
25986 IX86_BUILTIN_PMINSD128,
25987 IX86_BUILTIN_PMINUD128,
25988 IX86_BUILTIN_PMINUW128,
25990 IX86_BUILTIN_PMOVSXBW128,
25991 IX86_BUILTIN_PMOVSXBD128,
25992 IX86_BUILTIN_PMOVSXBQ128,
25993 IX86_BUILTIN_PMOVSXWD128,
25994 IX86_BUILTIN_PMOVSXWQ128,
25995 IX86_BUILTIN_PMOVSXDQ128,
25997 IX86_BUILTIN_PMOVZXBW128,
25998 IX86_BUILTIN_PMOVZXBD128,
25999 IX86_BUILTIN_PMOVZXBQ128,
26000 IX86_BUILTIN_PMOVZXWD128,
26001 IX86_BUILTIN_PMOVZXWQ128,
26002 IX86_BUILTIN_PMOVZXDQ128,
26004 IX86_BUILTIN_PMULDQ128,
26005 IX86_BUILTIN_PMULLD128,
26007 IX86_BUILTIN_ROUNDSD,
26008 IX86_BUILTIN_ROUNDSS,
26010 IX86_BUILTIN_ROUNDPD,
26011 IX86_BUILTIN_ROUNDPS,
26013 IX86_BUILTIN_FLOORPD,
26014 IX86_BUILTIN_CEILPD,
26015 IX86_BUILTIN_TRUNCPD,
26016 IX86_BUILTIN_RINTPD,
26017 IX86_BUILTIN_ROUNDPD_AZ,
26019 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26020 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26021 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26023 IX86_BUILTIN_FLOORPS,
26024 IX86_BUILTIN_CEILPS,
26025 IX86_BUILTIN_TRUNCPS,
26026 IX86_BUILTIN_RINTPS,
26027 IX86_BUILTIN_ROUNDPS_AZ,
26029 IX86_BUILTIN_FLOORPS_SFIX,
26030 IX86_BUILTIN_CEILPS_SFIX,
26031 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26033 IX86_BUILTIN_PTESTZ,
26034 IX86_BUILTIN_PTESTC,
26035 IX86_BUILTIN_PTESTNZC,
26037 IX86_BUILTIN_VEC_INIT_V2SI,
26038 IX86_BUILTIN_VEC_INIT_V4HI,
26039 IX86_BUILTIN_VEC_INIT_V8QI,
26040 IX86_BUILTIN_VEC_EXT_V2DF,
26041 IX86_BUILTIN_VEC_EXT_V2DI,
26042 IX86_BUILTIN_VEC_EXT_V4SF,
26043 IX86_BUILTIN_VEC_EXT_V4SI,
26044 IX86_BUILTIN_VEC_EXT_V8HI,
26045 IX86_BUILTIN_VEC_EXT_V2SI,
26046 IX86_BUILTIN_VEC_EXT_V4HI,
26047 IX86_BUILTIN_VEC_EXT_V16QI,
26048 IX86_BUILTIN_VEC_SET_V2DI,
26049 IX86_BUILTIN_VEC_SET_V4SF,
26050 IX86_BUILTIN_VEC_SET_V4SI,
26051 IX86_BUILTIN_VEC_SET_V8HI,
26052 IX86_BUILTIN_VEC_SET_V4HI,
26053 IX86_BUILTIN_VEC_SET_V16QI,
26055 IX86_BUILTIN_VEC_PACK_SFIX,
26056 IX86_BUILTIN_VEC_PACK_SFIX256,
26058 /* SSE4.2. */
26059 IX86_BUILTIN_CRC32QI,
26060 IX86_BUILTIN_CRC32HI,
26061 IX86_BUILTIN_CRC32SI,
26062 IX86_BUILTIN_CRC32DI,
26064 IX86_BUILTIN_PCMPESTRI128,
26065 IX86_BUILTIN_PCMPESTRM128,
26066 IX86_BUILTIN_PCMPESTRA128,
26067 IX86_BUILTIN_PCMPESTRC128,
26068 IX86_BUILTIN_PCMPESTRO128,
26069 IX86_BUILTIN_PCMPESTRS128,
26070 IX86_BUILTIN_PCMPESTRZ128,
26071 IX86_BUILTIN_PCMPISTRI128,
26072 IX86_BUILTIN_PCMPISTRM128,
26073 IX86_BUILTIN_PCMPISTRA128,
26074 IX86_BUILTIN_PCMPISTRC128,
26075 IX86_BUILTIN_PCMPISTRO128,
26076 IX86_BUILTIN_PCMPISTRS128,
26077 IX86_BUILTIN_PCMPISTRZ128,
26079 IX86_BUILTIN_PCMPGTQ,
26081 /* AES instructions */
26082 IX86_BUILTIN_AESENC128,
26083 IX86_BUILTIN_AESENCLAST128,
26084 IX86_BUILTIN_AESDEC128,
26085 IX86_BUILTIN_AESDECLAST128,
26086 IX86_BUILTIN_AESIMC128,
26087 IX86_BUILTIN_AESKEYGENASSIST128,
26089 /* PCLMUL instruction */
26090 IX86_BUILTIN_PCLMULQDQ128,
26092 /* AVX */
26093 IX86_BUILTIN_ADDPD256,
26094 IX86_BUILTIN_ADDPS256,
26095 IX86_BUILTIN_ADDSUBPD256,
26096 IX86_BUILTIN_ADDSUBPS256,
26097 IX86_BUILTIN_ANDPD256,
26098 IX86_BUILTIN_ANDPS256,
26099 IX86_BUILTIN_ANDNPD256,
26100 IX86_BUILTIN_ANDNPS256,
26101 IX86_BUILTIN_BLENDPD256,
26102 IX86_BUILTIN_BLENDPS256,
26103 IX86_BUILTIN_BLENDVPD256,
26104 IX86_BUILTIN_BLENDVPS256,
26105 IX86_BUILTIN_DIVPD256,
26106 IX86_BUILTIN_DIVPS256,
26107 IX86_BUILTIN_DPPS256,
26108 IX86_BUILTIN_HADDPD256,
26109 IX86_BUILTIN_HADDPS256,
26110 IX86_BUILTIN_HSUBPD256,
26111 IX86_BUILTIN_HSUBPS256,
26112 IX86_BUILTIN_MAXPD256,
26113 IX86_BUILTIN_MAXPS256,
26114 IX86_BUILTIN_MINPD256,
26115 IX86_BUILTIN_MINPS256,
26116 IX86_BUILTIN_MULPD256,
26117 IX86_BUILTIN_MULPS256,
26118 IX86_BUILTIN_ORPD256,
26119 IX86_BUILTIN_ORPS256,
26120 IX86_BUILTIN_SHUFPD256,
26121 IX86_BUILTIN_SHUFPS256,
26122 IX86_BUILTIN_SUBPD256,
26123 IX86_BUILTIN_SUBPS256,
26124 IX86_BUILTIN_XORPD256,
26125 IX86_BUILTIN_XORPS256,
26126 IX86_BUILTIN_CMPSD,
26127 IX86_BUILTIN_CMPSS,
26128 IX86_BUILTIN_CMPPD,
26129 IX86_BUILTIN_CMPPS,
26130 IX86_BUILTIN_CMPPD256,
26131 IX86_BUILTIN_CMPPS256,
26132 IX86_BUILTIN_CVTDQ2PD256,
26133 IX86_BUILTIN_CVTDQ2PS256,
26134 IX86_BUILTIN_CVTPD2PS256,
26135 IX86_BUILTIN_CVTPS2DQ256,
26136 IX86_BUILTIN_CVTPS2PD256,
26137 IX86_BUILTIN_CVTTPD2DQ256,
26138 IX86_BUILTIN_CVTPD2DQ256,
26139 IX86_BUILTIN_CVTTPS2DQ256,
26140 IX86_BUILTIN_EXTRACTF128PD256,
26141 IX86_BUILTIN_EXTRACTF128PS256,
26142 IX86_BUILTIN_EXTRACTF128SI256,
26143 IX86_BUILTIN_VZEROALL,
26144 IX86_BUILTIN_VZEROUPPER,
26145 IX86_BUILTIN_VPERMILVARPD,
26146 IX86_BUILTIN_VPERMILVARPS,
26147 IX86_BUILTIN_VPERMILVARPD256,
26148 IX86_BUILTIN_VPERMILVARPS256,
26149 IX86_BUILTIN_VPERMILPD,
26150 IX86_BUILTIN_VPERMILPS,
26151 IX86_BUILTIN_VPERMILPD256,
26152 IX86_BUILTIN_VPERMILPS256,
26153 IX86_BUILTIN_VPERMIL2PD,
26154 IX86_BUILTIN_VPERMIL2PS,
26155 IX86_BUILTIN_VPERMIL2PD256,
26156 IX86_BUILTIN_VPERMIL2PS256,
26157 IX86_BUILTIN_VPERM2F128PD256,
26158 IX86_BUILTIN_VPERM2F128PS256,
26159 IX86_BUILTIN_VPERM2F128SI256,
26160 IX86_BUILTIN_VBROADCASTSS,
26161 IX86_BUILTIN_VBROADCASTSD256,
26162 IX86_BUILTIN_VBROADCASTSS256,
26163 IX86_BUILTIN_VBROADCASTPD256,
26164 IX86_BUILTIN_VBROADCASTPS256,
26165 IX86_BUILTIN_VINSERTF128PD256,
26166 IX86_BUILTIN_VINSERTF128PS256,
26167 IX86_BUILTIN_VINSERTF128SI256,
26168 IX86_BUILTIN_LOADUPD256,
26169 IX86_BUILTIN_LOADUPS256,
26170 IX86_BUILTIN_STOREUPD256,
26171 IX86_BUILTIN_STOREUPS256,
26172 IX86_BUILTIN_LDDQU256,
26173 IX86_BUILTIN_MOVNTDQ256,
26174 IX86_BUILTIN_MOVNTPD256,
26175 IX86_BUILTIN_MOVNTPS256,
26176 IX86_BUILTIN_LOADDQU256,
26177 IX86_BUILTIN_STOREDQU256,
26178 IX86_BUILTIN_MASKLOADPD,
26179 IX86_BUILTIN_MASKLOADPS,
26180 IX86_BUILTIN_MASKSTOREPD,
26181 IX86_BUILTIN_MASKSTOREPS,
26182 IX86_BUILTIN_MASKLOADPD256,
26183 IX86_BUILTIN_MASKLOADPS256,
26184 IX86_BUILTIN_MASKSTOREPD256,
26185 IX86_BUILTIN_MASKSTOREPS256,
26186 IX86_BUILTIN_MOVSHDUP256,
26187 IX86_BUILTIN_MOVSLDUP256,
26188 IX86_BUILTIN_MOVDDUP256,
26190 IX86_BUILTIN_SQRTPD256,
26191 IX86_BUILTIN_SQRTPS256,
26192 IX86_BUILTIN_SQRTPS_NR256,
26193 IX86_BUILTIN_RSQRTPS256,
26194 IX86_BUILTIN_RSQRTPS_NR256,
26196 IX86_BUILTIN_RCPPS256,
26198 IX86_BUILTIN_ROUNDPD256,
26199 IX86_BUILTIN_ROUNDPS256,
26201 IX86_BUILTIN_FLOORPD256,
26202 IX86_BUILTIN_CEILPD256,
26203 IX86_BUILTIN_TRUNCPD256,
26204 IX86_BUILTIN_RINTPD256,
26205 IX86_BUILTIN_ROUNDPD_AZ256,
26207 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26208 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26209 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26211 IX86_BUILTIN_FLOORPS256,
26212 IX86_BUILTIN_CEILPS256,
26213 IX86_BUILTIN_TRUNCPS256,
26214 IX86_BUILTIN_RINTPS256,
26215 IX86_BUILTIN_ROUNDPS_AZ256,
26217 IX86_BUILTIN_FLOORPS_SFIX256,
26218 IX86_BUILTIN_CEILPS_SFIX256,
26219 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26221 IX86_BUILTIN_UNPCKHPD256,
26222 IX86_BUILTIN_UNPCKLPD256,
26223 IX86_BUILTIN_UNPCKHPS256,
26224 IX86_BUILTIN_UNPCKLPS256,
26226 IX86_BUILTIN_SI256_SI,
26227 IX86_BUILTIN_PS256_PS,
26228 IX86_BUILTIN_PD256_PD,
26229 IX86_BUILTIN_SI_SI256,
26230 IX86_BUILTIN_PS_PS256,
26231 IX86_BUILTIN_PD_PD256,
26233 IX86_BUILTIN_VTESTZPD,
26234 IX86_BUILTIN_VTESTCPD,
26235 IX86_BUILTIN_VTESTNZCPD,
26236 IX86_BUILTIN_VTESTZPS,
26237 IX86_BUILTIN_VTESTCPS,
26238 IX86_BUILTIN_VTESTNZCPS,
26239 IX86_BUILTIN_VTESTZPD256,
26240 IX86_BUILTIN_VTESTCPD256,
26241 IX86_BUILTIN_VTESTNZCPD256,
26242 IX86_BUILTIN_VTESTZPS256,
26243 IX86_BUILTIN_VTESTCPS256,
26244 IX86_BUILTIN_VTESTNZCPS256,
26245 IX86_BUILTIN_PTESTZ256,
26246 IX86_BUILTIN_PTESTC256,
26247 IX86_BUILTIN_PTESTNZC256,
26249 IX86_BUILTIN_MOVMSKPD256,
26250 IX86_BUILTIN_MOVMSKPS256,
26252 /* AVX2 */
26253 IX86_BUILTIN_MPSADBW256,
26254 IX86_BUILTIN_PABSB256,
26255 IX86_BUILTIN_PABSW256,
26256 IX86_BUILTIN_PABSD256,
26257 IX86_BUILTIN_PACKSSDW256,
26258 IX86_BUILTIN_PACKSSWB256,
26259 IX86_BUILTIN_PACKUSDW256,
26260 IX86_BUILTIN_PACKUSWB256,
26261 IX86_BUILTIN_PADDB256,
26262 IX86_BUILTIN_PADDW256,
26263 IX86_BUILTIN_PADDD256,
26264 IX86_BUILTIN_PADDQ256,
26265 IX86_BUILTIN_PADDSB256,
26266 IX86_BUILTIN_PADDSW256,
26267 IX86_BUILTIN_PADDUSB256,
26268 IX86_BUILTIN_PADDUSW256,
26269 IX86_BUILTIN_PALIGNR256,
26270 IX86_BUILTIN_AND256I,
26271 IX86_BUILTIN_ANDNOT256I,
26272 IX86_BUILTIN_PAVGB256,
26273 IX86_BUILTIN_PAVGW256,
26274 IX86_BUILTIN_PBLENDVB256,
26275 IX86_BUILTIN_PBLENDVW256,
26276 IX86_BUILTIN_PCMPEQB256,
26277 IX86_BUILTIN_PCMPEQW256,
26278 IX86_BUILTIN_PCMPEQD256,
26279 IX86_BUILTIN_PCMPEQQ256,
26280 IX86_BUILTIN_PCMPGTB256,
26281 IX86_BUILTIN_PCMPGTW256,
26282 IX86_BUILTIN_PCMPGTD256,
26283 IX86_BUILTIN_PCMPGTQ256,
26284 IX86_BUILTIN_PHADDW256,
26285 IX86_BUILTIN_PHADDD256,
26286 IX86_BUILTIN_PHADDSW256,
26287 IX86_BUILTIN_PHSUBW256,
26288 IX86_BUILTIN_PHSUBD256,
26289 IX86_BUILTIN_PHSUBSW256,
26290 IX86_BUILTIN_PMADDUBSW256,
26291 IX86_BUILTIN_PMADDWD256,
26292 IX86_BUILTIN_PMAXSB256,
26293 IX86_BUILTIN_PMAXSW256,
26294 IX86_BUILTIN_PMAXSD256,
26295 IX86_BUILTIN_PMAXUB256,
26296 IX86_BUILTIN_PMAXUW256,
26297 IX86_BUILTIN_PMAXUD256,
26298 IX86_BUILTIN_PMINSB256,
26299 IX86_BUILTIN_PMINSW256,
26300 IX86_BUILTIN_PMINSD256,
26301 IX86_BUILTIN_PMINUB256,
26302 IX86_BUILTIN_PMINUW256,
26303 IX86_BUILTIN_PMINUD256,
26304 IX86_BUILTIN_PMOVMSKB256,
26305 IX86_BUILTIN_PMOVSXBW256,
26306 IX86_BUILTIN_PMOVSXBD256,
26307 IX86_BUILTIN_PMOVSXBQ256,
26308 IX86_BUILTIN_PMOVSXWD256,
26309 IX86_BUILTIN_PMOVSXWQ256,
26310 IX86_BUILTIN_PMOVSXDQ256,
26311 IX86_BUILTIN_PMOVZXBW256,
26312 IX86_BUILTIN_PMOVZXBD256,
26313 IX86_BUILTIN_PMOVZXBQ256,
26314 IX86_BUILTIN_PMOVZXWD256,
26315 IX86_BUILTIN_PMOVZXWQ256,
26316 IX86_BUILTIN_PMOVZXDQ256,
26317 IX86_BUILTIN_PMULDQ256,
26318 IX86_BUILTIN_PMULHRSW256,
26319 IX86_BUILTIN_PMULHUW256,
26320 IX86_BUILTIN_PMULHW256,
26321 IX86_BUILTIN_PMULLW256,
26322 IX86_BUILTIN_PMULLD256,
26323 IX86_BUILTIN_PMULUDQ256,
26324 IX86_BUILTIN_POR256,
26325 IX86_BUILTIN_PSADBW256,
26326 IX86_BUILTIN_PSHUFB256,
26327 IX86_BUILTIN_PSHUFD256,
26328 IX86_BUILTIN_PSHUFHW256,
26329 IX86_BUILTIN_PSHUFLW256,
26330 IX86_BUILTIN_PSIGNB256,
26331 IX86_BUILTIN_PSIGNW256,
26332 IX86_BUILTIN_PSIGND256,
26333 IX86_BUILTIN_PSLLDQI256,
26334 IX86_BUILTIN_PSLLWI256,
26335 IX86_BUILTIN_PSLLW256,
26336 IX86_BUILTIN_PSLLDI256,
26337 IX86_BUILTIN_PSLLD256,
26338 IX86_BUILTIN_PSLLQI256,
26339 IX86_BUILTIN_PSLLQ256,
26340 IX86_BUILTIN_PSRAWI256,
26341 IX86_BUILTIN_PSRAW256,
26342 IX86_BUILTIN_PSRADI256,
26343 IX86_BUILTIN_PSRAD256,
26344 IX86_BUILTIN_PSRLDQI256,
26345 IX86_BUILTIN_PSRLWI256,
26346 IX86_BUILTIN_PSRLW256,
26347 IX86_BUILTIN_PSRLDI256,
26348 IX86_BUILTIN_PSRLD256,
26349 IX86_BUILTIN_PSRLQI256,
26350 IX86_BUILTIN_PSRLQ256,
26351 IX86_BUILTIN_PSUBB256,
26352 IX86_BUILTIN_PSUBW256,
26353 IX86_BUILTIN_PSUBD256,
26354 IX86_BUILTIN_PSUBQ256,
26355 IX86_BUILTIN_PSUBSB256,
26356 IX86_BUILTIN_PSUBSW256,
26357 IX86_BUILTIN_PSUBUSB256,
26358 IX86_BUILTIN_PSUBUSW256,
26359 IX86_BUILTIN_PUNPCKHBW256,
26360 IX86_BUILTIN_PUNPCKHWD256,
26361 IX86_BUILTIN_PUNPCKHDQ256,
26362 IX86_BUILTIN_PUNPCKHQDQ256,
26363 IX86_BUILTIN_PUNPCKLBW256,
26364 IX86_BUILTIN_PUNPCKLWD256,
26365 IX86_BUILTIN_PUNPCKLDQ256,
26366 IX86_BUILTIN_PUNPCKLQDQ256,
26367 IX86_BUILTIN_PXOR256,
26368 IX86_BUILTIN_MOVNTDQA256,
26369 IX86_BUILTIN_VBROADCASTSS_PS,
26370 IX86_BUILTIN_VBROADCASTSS_PS256,
26371 IX86_BUILTIN_VBROADCASTSD_PD256,
26372 IX86_BUILTIN_VBROADCASTSI256,
26373 IX86_BUILTIN_PBLENDD256,
26374 IX86_BUILTIN_PBLENDD128,
26375 IX86_BUILTIN_PBROADCASTB256,
26376 IX86_BUILTIN_PBROADCASTW256,
26377 IX86_BUILTIN_PBROADCASTD256,
26378 IX86_BUILTIN_PBROADCASTQ256,
26379 IX86_BUILTIN_PBROADCASTB128,
26380 IX86_BUILTIN_PBROADCASTW128,
26381 IX86_BUILTIN_PBROADCASTD128,
26382 IX86_BUILTIN_PBROADCASTQ128,
26383 IX86_BUILTIN_VPERMVARSI256,
26384 IX86_BUILTIN_VPERMDF256,
26385 IX86_BUILTIN_VPERMVARSF256,
26386 IX86_BUILTIN_VPERMDI256,
26387 IX86_BUILTIN_VPERMTI256,
26388 IX86_BUILTIN_VEXTRACT128I256,
26389 IX86_BUILTIN_VINSERT128I256,
26390 IX86_BUILTIN_MASKLOADD,
26391 IX86_BUILTIN_MASKLOADQ,
26392 IX86_BUILTIN_MASKLOADD256,
26393 IX86_BUILTIN_MASKLOADQ256,
26394 IX86_BUILTIN_MASKSTORED,
26395 IX86_BUILTIN_MASKSTOREQ,
26396 IX86_BUILTIN_MASKSTORED256,
26397 IX86_BUILTIN_MASKSTOREQ256,
26398 IX86_BUILTIN_PSLLVV4DI,
26399 IX86_BUILTIN_PSLLVV2DI,
26400 IX86_BUILTIN_PSLLVV8SI,
26401 IX86_BUILTIN_PSLLVV4SI,
26402 IX86_BUILTIN_PSRAVV8SI,
26403 IX86_BUILTIN_PSRAVV4SI,
26404 IX86_BUILTIN_PSRLVV4DI,
26405 IX86_BUILTIN_PSRLVV2DI,
26406 IX86_BUILTIN_PSRLVV8SI,
26407 IX86_BUILTIN_PSRLVV4SI,
26409 IX86_BUILTIN_GATHERSIV2DF,
26410 IX86_BUILTIN_GATHERSIV4DF,
26411 IX86_BUILTIN_GATHERDIV2DF,
26412 IX86_BUILTIN_GATHERDIV4DF,
26413 IX86_BUILTIN_GATHERSIV4SF,
26414 IX86_BUILTIN_GATHERSIV8SF,
26415 IX86_BUILTIN_GATHERDIV4SF,
26416 IX86_BUILTIN_GATHERDIV8SF,
26417 IX86_BUILTIN_GATHERSIV2DI,
26418 IX86_BUILTIN_GATHERSIV4DI,
26419 IX86_BUILTIN_GATHERDIV2DI,
26420 IX86_BUILTIN_GATHERDIV4DI,
26421 IX86_BUILTIN_GATHERSIV4SI,
26422 IX86_BUILTIN_GATHERSIV8SI,
26423 IX86_BUILTIN_GATHERDIV4SI,
26424 IX86_BUILTIN_GATHERDIV8SI,
26426 /* Alternate 4 element gather for the vectorizer where
26427 all operands are 32-byte wide. */
26428 IX86_BUILTIN_GATHERALTSIV4DF,
26429 IX86_BUILTIN_GATHERALTDIV8SF,
26430 IX86_BUILTIN_GATHERALTSIV4DI,
26431 IX86_BUILTIN_GATHERALTDIV8SI,
26433 /* TFmode support builtins. */
26434 IX86_BUILTIN_INFQ,
26435 IX86_BUILTIN_HUGE_VALQ,
26436 IX86_BUILTIN_FABSQ,
26437 IX86_BUILTIN_COPYSIGNQ,
26439 /* Vectorizer support builtins. */
26440 IX86_BUILTIN_CPYSGNPS,
26441 IX86_BUILTIN_CPYSGNPD,
26442 IX86_BUILTIN_CPYSGNPS256,
26443 IX86_BUILTIN_CPYSGNPD256,
26445 /* FMA4 instructions. */
26446 IX86_BUILTIN_VFMADDSS,
26447 IX86_BUILTIN_VFMADDSD,
26448 IX86_BUILTIN_VFMADDPS,
26449 IX86_BUILTIN_VFMADDPD,
26450 IX86_BUILTIN_VFMADDPS256,
26451 IX86_BUILTIN_VFMADDPD256,
26452 IX86_BUILTIN_VFMADDSUBPS,
26453 IX86_BUILTIN_VFMADDSUBPD,
26454 IX86_BUILTIN_VFMADDSUBPS256,
26455 IX86_BUILTIN_VFMADDSUBPD256,
26457 /* FMA3 instructions. */
26458 IX86_BUILTIN_VFMADDSS3,
26459 IX86_BUILTIN_VFMADDSD3,
26461 /* XOP instructions. */
26462 IX86_BUILTIN_VPCMOV,
26463 IX86_BUILTIN_VPCMOV_V2DI,
26464 IX86_BUILTIN_VPCMOV_V4SI,
26465 IX86_BUILTIN_VPCMOV_V8HI,
26466 IX86_BUILTIN_VPCMOV_V16QI,
26467 IX86_BUILTIN_VPCMOV_V4SF,
26468 IX86_BUILTIN_VPCMOV_V2DF,
26469 IX86_BUILTIN_VPCMOV256,
26470 IX86_BUILTIN_VPCMOV_V4DI256,
26471 IX86_BUILTIN_VPCMOV_V8SI256,
26472 IX86_BUILTIN_VPCMOV_V16HI256,
26473 IX86_BUILTIN_VPCMOV_V32QI256,
26474 IX86_BUILTIN_VPCMOV_V8SF256,
26475 IX86_BUILTIN_VPCMOV_V4DF256,
26477 IX86_BUILTIN_VPPERM,
26479 IX86_BUILTIN_VPMACSSWW,
26480 IX86_BUILTIN_VPMACSWW,
26481 IX86_BUILTIN_VPMACSSWD,
26482 IX86_BUILTIN_VPMACSWD,
26483 IX86_BUILTIN_VPMACSSDD,
26484 IX86_BUILTIN_VPMACSDD,
26485 IX86_BUILTIN_VPMACSSDQL,
26486 IX86_BUILTIN_VPMACSSDQH,
26487 IX86_BUILTIN_VPMACSDQL,
26488 IX86_BUILTIN_VPMACSDQH,
26489 IX86_BUILTIN_VPMADCSSWD,
26490 IX86_BUILTIN_VPMADCSWD,
26492 IX86_BUILTIN_VPHADDBW,
26493 IX86_BUILTIN_VPHADDBD,
26494 IX86_BUILTIN_VPHADDBQ,
26495 IX86_BUILTIN_VPHADDWD,
26496 IX86_BUILTIN_VPHADDWQ,
26497 IX86_BUILTIN_VPHADDDQ,
26498 IX86_BUILTIN_VPHADDUBW,
26499 IX86_BUILTIN_VPHADDUBD,
26500 IX86_BUILTIN_VPHADDUBQ,
26501 IX86_BUILTIN_VPHADDUWD,
26502 IX86_BUILTIN_VPHADDUWQ,
26503 IX86_BUILTIN_VPHADDUDQ,
26504 IX86_BUILTIN_VPHSUBBW,
26505 IX86_BUILTIN_VPHSUBWD,
26506 IX86_BUILTIN_VPHSUBDQ,
26508 IX86_BUILTIN_VPROTB,
26509 IX86_BUILTIN_VPROTW,
26510 IX86_BUILTIN_VPROTD,
26511 IX86_BUILTIN_VPROTQ,
26512 IX86_BUILTIN_VPROTB_IMM,
26513 IX86_BUILTIN_VPROTW_IMM,
26514 IX86_BUILTIN_VPROTD_IMM,
26515 IX86_BUILTIN_VPROTQ_IMM,
26517 IX86_BUILTIN_VPSHLB,
26518 IX86_BUILTIN_VPSHLW,
26519 IX86_BUILTIN_VPSHLD,
26520 IX86_BUILTIN_VPSHLQ,
26521 IX86_BUILTIN_VPSHAB,
26522 IX86_BUILTIN_VPSHAW,
26523 IX86_BUILTIN_VPSHAD,
26524 IX86_BUILTIN_VPSHAQ,
26526 IX86_BUILTIN_VFRCZSS,
26527 IX86_BUILTIN_VFRCZSD,
26528 IX86_BUILTIN_VFRCZPS,
26529 IX86_BUILTIN_VFRCZPD,
26530 IX86_BUILTIN_VFRCZPS256,
26531 IX86_BUILTIN_VFRCZPD256,
26533 IX86_BUILTIN_VPCOMEQUB,
26534 IX86_BUILTIN_VPCOMNEUB,
26535 IX86_BUILTIN_VPCOMLTUB,
26536 IX86_BUILTIN_VPCOMLEUB,
26537 IX86_BUILTIN_VPCOMGTUB,
26538 IX86_BUILTIN_VPCOMGEUB,
26539 IX86_BUILTIN_VPCOMFALSEUB,
26540 IX86_BUILTIN_VPCOMTRUEUB,
26542 IX86_BUILTIN_VPCOMEQUW,
26543 IX86_BUILTIN_VPCOMNEUW,
26544 IX86_BUILTIN_VPCOMLTUW,
26545 IX86_BUILTIN_VPCOMLEUW,
26546 IX86_BUILTIN_VPCOMGTUW,
26547 IX86_BUILTIN_VPCOMGEUW,
26548 IX86_BUILTIN_VPCOMFALSEUW,
26549 IX86_BUILTIN_VPCOMTRUEUW,
26551 IX86_BUILTIN_VPCOMEQUD,
26552 IX86_BUILTIN_VPCOMNEUD,
26553 IX86_BUILTIN_VPCOMLTUD,
26554 IX86_BUILTIN_VPCOMLEUD,
26555 IX86_BUILTIN_VPCOMGTUD,
26556 IX86_BUILTIN_VPCOMGEUD,
26557 IX86_BUILTIN_VPCOMFALSEUD,
26558 IX86_BUILTIN_VPCOMTRUEUD,
26560 IX86_BUILTIN_VPCOMEQUQ,
26561 IX86_BUILTIN_VPCOMNEUQ,
26562 IX86_BUILTIN_VPCOMLTUQ,
26563 IX86_BUILTIN_VPCOMLEUQ,
26564 IX86_BUILTIN_VPCOMGTUQ,
26565 IX86_BUILTIN_VPCOMGEUQ,
26566 IX86_BUILTIN_VPCOMFALSEUQ,
26567 IX86_BUILTIN_VPCOMTRUEUQ,
26569 IX86_BUILTIN_VPCOMEQB,
26570 IX86_BUILTIN_VPCOMNEB,
26571 IX86_BUILTIN_VPCOMLTB,
26572 IX86_BUILTIN_VPCOMLEB,
26573 IX86_BUILTIN_VPCOMGTB,
26574 IX86_BUILTIN_VPCOMGEB,
26575 IX86_BUILTIN_VPCOMFALSEB,
26576 IX86_BUILTIN_VPCOMTRUEB,
26578 IX86_BUILTIN_VPCOMEQW,
26579 IX86_BUILTIN_VPCOMNEW,
26580 IX86_BUILTIN_VPCOMLTW,
26581 IX86_BUILTIN_VPCOMLEW,
26582 IX86_BUILTIN_VPCOMGTW,
26583 IX86_BUILTIN_VPCOMGEW,
26584 IX86_BUILTIN_VPCOMFALSEW,
26585 IX86_BUILTIN_VPCOMTRUEW,
26587 IX86_BUILTIN_VPCOMEQD,
26588 IX86_BUILTIN_VPCOMNED,
26589 IX86_BUILTIN_VPCOMLTD,
26590 IX86_BUILTIN_VPCOMLED,
26591 IX86_BUILTIN_VPCOMGTD,
26592 IX86_BUILTIN_VPCOMGED,
26593 IX86_BUILTIN_VPCOMFALSED,
26594 IX86_BUILTIN_VPCOMTRUED,
26596 IX86_BUILTIN_VPCOMEQQ,
26597 IX86_BUILTIN_VPCOMNEQ,
26598 IX86_BUILTIN_VPCOMLTQ,
26599 IX86_BUILTIN_VPCOMLEQ,
26600 IX86_BUILTIN_VPCOMGTQ,
26601 IX86_BUILTIN_VPCOMGEQ,
26602 IX86_BUILTIN_VPCOMFALSEQ,
26603 IX86_BUILTIN_VPCOMTRUEQ,
26605 /* LWP instructions. */
26606 IX86_BUILTIN_LLWPCB,
26607 IX86_BUILTIN_SLWPCB,
26608 IX86_BUILTIN_LWPVAL32,
26609 IX86_BUILTIN_LWPVAL64,
26610 IX86_BUILTIN_LWPINS32,
26611 IX86_BUILTIN_LWPINS64,
26613 IX86_BUILTIN_CLZS,
26615 /* RTM */
26616 IX86_BUILTIN_XBEGIN,
26617 IX86_BUILTIN_XEND,
26618 IX86_BUILTIN_XABORT,
26619 IX86_BUILTIN_XTEST,
26621 /* BMI instructions. */
26622 IX86_BUILTIN_BEXTR32,
26623 IX86_BUILTIN_BEXTR64,
26624 IX86_BUILTIN_CTZS,
26626 /* TBM instructions. */
26627 IX86_BUILTIN_BEXTRI32,
26628 IX86_BUILTIN_BEXTRI64,
26630 /* BMI2 instructions. */
26631 IX86_BUILTIN_BZHI32,
26632 IX86_BUILTIN_BZHI64,
26633 IX86_BUILTIN_PDEP32,
26634 IX86_BUILTIN_PDEP64,
26635 IX86_BUILTIN_PEXT32,
26636 IX86_BUILTIN_PEXT64,
26638 /* ADX instructions. */
26639 IX86_BUILTIN_ADDCARRYX32,
26640 IX86_BUILTIN_ADDCARRYX64,
26642 /* FSGSBASE instructions. */
26643 IX86_BUILTIN_RDFSBASE32,
26644 IX86_BUILTIN_RDFSBASE64,
26645 IX86_BUILTIN_RDGSBASE32,
26646 IX86_BUILTIN_RDGSBASE64,
26647 IX86_BUILTIN_WRFSBASE32,
26648 IX86_BUILTIN_WRFSBASE64,
26649 IX86_BUILTIN_WRGSBASE32,
26650 IX86_BUILTIN_WRGSBASE64,
26652 /* RDRND instructions. */
26653 IX86_BUILTIN_RDRAND16_STEP,
26654 IX86_BUILTIN_RDRAND32_STEP,
26655 IX86_BUILTIN_RDRAND64_STEP,
26657 /* RDSEED instructions. */
26658 IX86_BUILTIN_RDSEED16_STEP,
26659 IX86_BUILTIN_RDSEED32_STEP,
26660 IX86_BUILTIN_RDSEED64_STEP,
26662 /* F16C instructions. */
26663 IX86_BUILTIN_CVTPH2PS,
26664 IX86_BUILTIN_CVTPH2PS256,
26665 IX86_BUILTIN_CVTPS2PH,
26666 IX86_BUILTIN_CVTPS2PH256,
26668 /* CFString built-in for darwin */
26669 IX86_BUILTIN_CFSTRING,
26671 /* Builtins to get CPU type and supported features. */
26672 IX86_BUILTIN_CPU_INIT,
26673 IX86_BUILTIN_CPU_IS,
26674 IX86_BUILTIN_CPU_SUPPORTS,
26676 IX86_BUILTIN_MAX
26677 };
26679 /* Table for the ix86 builtin decls. */
26682 /* Table of all of the builtin functions that are possible with different ISA's
26683 but are waiting to be built until a function is declared to use that
26684 ISA. */
26691 };
26696 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26697 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26698 function decl in the ix86_builtins array. Returns the function decl or
26699 NULL_TREE, if the builtin was not added.
26701 If the front end has a special hook for builtin functions, delay adding
26702 builtin functions that aren't in the current ISA until the ISA is changed
26703 with function specific optimization. Doing so, can save about 300K for the
26704 default compiler. When the builtin is expanded, check at that time whether
26705 it is valid.
26707 If the front end doesn't have a special hook, record all builtins, even if
26708 it isn't an instruction set in the current ISA in case the user uses
26709 function specific options for a different ISA, so that we don't get scope
26710 errors if a builtin is added in the middle of a function scope. */
26716 {
26720 {
26729 {
26735 }
26736 else
26737 {
26743 }
26744 }
26747 }
26749 /* Like def_builtin, but also marks the function decl "const". */
26754 {
26758 else
26762 }
26764 /* Add any new builtin functions for a given ISA that may not have been
26765 declared. This saves a bit of space compared to adding all of the
26766 declarations to the tree, even if we didn't use them. */
26768 static void
26770 {
26774 {
26777 {
26780 /* Don't define the builtin again. */
26786 NULL_TREE);
26791 }
26792 }
26793 }
26795 /* Bits for builtin_description.flag. */
26797 /* Set when we don't support the comparison natively, and should
26798 swap_comparison in order to support it. */
26799 #define BUILTIN_DESC_SWAP_OPERANDS 1
26801 struct builtin_description
26802 {
26809 };
26812 {
26813 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26814 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26815 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26816 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26817 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26818 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26819 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26820 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26821 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26822 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26823 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26824 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26830 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26837 };
26840 {
26841 /* SSE4.2 */
26842 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26843 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26844 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26845 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26846 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26847 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26848 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26849 };
26852 {
26853 /* SSE4.2 */
26854 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26855 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26856 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26857 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26858 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26859 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26860 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26861 };
26863 /* Special builtins with variable number of arguments. */
26865 {
26866 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26867 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26868 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26870 /* MMX */
26871 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26873 /* 3DNow! */
26874 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26876 /* FXSR, XSAVE and XSAVEOPT */
26877 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26878 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26879 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26880 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26881 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26883 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26884 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26885 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26886 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26887 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26889 /* SSE */
26890 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26891 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26892 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26894 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26895 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26896 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26897 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26899 /* SSE or 3DNow!A */
26900 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26901 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26903 /* SSE2 */
26904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26911 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26918 /* SSE3 */
26919 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26921 /* SSE4.1 */
26922 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26924 /* SSE4A */
26925 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26926 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26928 /* AVX */
26929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26932 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26934 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26938 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26939 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26940 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26941 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26942 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26943 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26944 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26946 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26947 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26948 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26950 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26951 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26952 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26953 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26954 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26955 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26956 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26957 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26959 /* AVX2 */
26960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26970 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26971 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26972 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26973 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26974 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26975 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26977 /* FSGSBASE */
26978 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26979 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26980 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26981 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26982 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26983 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26984 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26985 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26987 /* RTM */
26988 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26989 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26990 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26991 };
26993 /* Builtins with variable number of arguments. */
26995 {
26996 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26997 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26998 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26999 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27000 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27001 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27002 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27004 /* MMX */
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27063 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27064 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27066 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27068 /* 3DNow! */
27069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27074 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27075 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27076 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27077 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27079 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27080 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27081 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27082 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27083 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27084 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27085 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27086 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27087 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27088 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27090 /* 3DNow!A */
27091 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27092 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27093 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27094 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27095 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27096 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27098 /* SSE */
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27107 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27110 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27142 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27146 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27147 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27151 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27153 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27154 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27156 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27158 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27161 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27162 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27164 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27166 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27168 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27174 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27175 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27177 /* SSE MMX or 3Dnow!A */
27178 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27179 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27180 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27182 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27183 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27184 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27185 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27187 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27188 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27190 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27192 /* SSE2 */
27193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27211 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27212 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27221 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27268 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27289 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27310 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27312 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27314 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27329 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27335 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27338 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27339 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27342 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27343 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27344 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27345 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27346 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27347 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27349 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27350 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27351 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27352 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27360 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27362 /* SSE2 MMX */
27363 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27364 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27366 /* SSE3 */
27367 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27368 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27370 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27371 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27372 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27373 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27374 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27375 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27377 /* SSSE3 */
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27395 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27398 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27399 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27400 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27401 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27402 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27403 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27404 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27405 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27406 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27408 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27410 /* SSSE3. */
27411 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27412 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27414 /* SSE4.1 */
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27438 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27440 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27441 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27442 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27443 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27444 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27445 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27446 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27447 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27448 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27449 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27450 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27451 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27453 /* SSE4.1 */
27454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27459 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27460 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27465 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27467 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27468 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27470 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27471 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27472 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27473 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27475 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27476 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27478 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27479 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27481 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27482 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27483 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27485 /* SSE4.2 */
27486 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27487 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27488 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27489 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27490 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27492 /* SSE4A */
27493 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27494 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27495 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27496 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27498 /* AES */
27499 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27500 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27502 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27503 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27504 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27505 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27507 /* PCLMUL */
27508 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27510 /* AVX */
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27582 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27646 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27647 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27649 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27651 /* AVX2 */
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27799 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27801 /* BMI */
27802 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27803 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27804 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27806 /* TBM */
27807 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27808 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27810 /* F16C */
27811 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27812 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27813 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27814 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27816 /* BMI2 */
27817 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27818 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27819 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27820 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27821 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27822 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27823 };
27825 /* FMA4 and XOP. */
27826 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27827 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27828 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27829 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27830 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27831 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27832 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27833 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27834 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27835 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27836 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27837 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27838 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27839 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27840 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27841 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27842 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27843 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27844 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27845 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27846 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27847 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27848 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27849 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27850 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27851 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27852 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27853 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27854 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27855 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27856 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27857 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27858 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27859 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27860 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27861 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27862 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27863 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27864 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27865 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27866 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27867 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27868 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27869 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27870 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27871 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27872 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27873 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27874 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27875 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27876 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27877 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27880 {
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28065 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28068 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28071 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28074 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28075 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28076 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28077 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28079 };
28080 \f
28081 /* TM vector builtins. */
28083 /* Reuse the existing x86-specific `struct builtin_description' cause
28084 we're lazy. Add casts to make them fit. */
28086 {
28087 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28088 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28089 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28090 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28091 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28092 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28093 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28095 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28096 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28097 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28098 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28099 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28100 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28101 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28103 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28104 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28105 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28106 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28107 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28108 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28109 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28111 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28112 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28113 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28114 };
28116 /* TM callbacks. */
28118 /* Return the builtin decl needed to load a vector of TYPE. */
28120 static tree
28122 {
28124 {
28126 {
28133 }
28134 }
28136 }
28138 /* Return the builtin decl needed to store a vector of TYPE. */
28140 static tree
28142 {
28144 {
28146 {
28153 }
28154 }
28156 }
28157 \f
28158 /* Initialize the transactional memory vector load/store builtins. */
28160 static void
28162 {
28166 tree decl;
28173 /* If there are no builtins defined, we must be compiling in a
28174 language without trans-mem support. */
28178 /* Use whatever attributes a normal TM load has. */
28182 /* Use whatever attributes a normal TM store has. */
28186 /* Use whatever attributes a normal TM log has. */
28194 {
28198 {
28206 {
28209 }
28211 {
28214 }
28215 else
28216 {
28219 }
28221 /* The builtin without the prefix for
28222 calling it directly. */
28224 attrs);
28225 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28226 set the TYPE_ATTRIBUTES. */
28230 }
28231 }
28232 }
28234 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28235 in the current target ISA to allow the user to compile particular modules
28236 with different target specific options that differ from the command line
28237 options. */
28238 static void
28240 {
28245 /* Add all special builtins with variable number of operands. */
28249 {
28255 }
28257 /* Add all builtins with variable number of operands. */
28261 {
28267 }
28269 /* pcmpestr[im] insns. */
28273 {
28276 else
28279 }
28281 /* pcmpistr[im] insns. */
28285 {
28288 else
28291 }
28293 /* comi/ucomi insns. */
28295 {
28298 else
28301 }
28303 /* SSE */
28309 /* SSE or 3DNow!A */
28312 IX86_BUILTIN_MASKMOVQ);
28314 /* SSE2 */
28323 /* SSE3. */
28329 /* AES */
28343 /* PCLMUL */
28347 /* RDRND */
28354 IX86_BUILTIN_RDRAND64_STEP);
28356 /* AVX2 */
28358 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28359 IX86_BUILTIN_GATHERSIV2DF);
28362 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28363 IX86_BUILTIN_GATHERSIV4DF);
28366 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28367 IX86_BUILTIN_GATHERDIV2DF);
28370 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28371 IX86_BUILTIN_GATHERDIV4DF);
28374 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28375 IX86_BUILTIN_GATHERSIV4SF);
28378 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28379 IX86_BUILTIN_GATHERSIV8SF);
28382 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28383 IX86_BUILTIN_GATHERDIV4SF);
28386 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28387 IX86_BUILTIN_GATHERDIV8SF);
28390 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28391 IX86_BUILTIN_GATHERSIV2DI);
28394 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28395 IX86_BUILTIN_GATHERSIV4DI);
28398 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28399 IX86_BUILTIN_GATHERDIV2DI);
28402 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28403 IX86_BUILTIN_GATHERDIV4DI);
28406 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28407 IX86_BUILTIN_GATHERSIV4SI);
28410 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28411 IX86_BUILTIN_GATHERSIV8SI);
28414 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28415 IX86_BUILTIN_GATHERDIV4SI);
28418 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28419 IX86_BUILTIN_GATHERDIV8SI);
28422 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28423 IX86_BUILTIN_GATHERALTSIV4DF);
28426 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28427 IX86_BUILTIN_GATHERALTDIV8SF);
28430 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28431 IX86_BUILTIN_GATHERALTSIV4DI);
28434 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28435 IX86_BUILTIN_GATHERALTDIV8SI);
28437 /* RTM. */
28441 /* MMX access to the vec_init patterns. */
28446 V4HI_FTYPE_HI_HI_HI_HI,
28447 IX86_BUILTIN_VEC_INIT_V4HI);
28450 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28451 IX86_BUILTIN_VEC_INIT_V8QI);
28453 /* Access to the vec_extract patterns. */
28475 /* Access to the vec_set patterns. */
28496 /* RDSEED */
28505 /* ADCX */
28510 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28511 IX86_BUILTIN_ADDCARRYX64);
28513 /* Add FMA4 multi-arg argument instructions */
28515 {
28521 }
28522 }
28524 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28525 to return a pointer to VERSION_DECL if the outcome of the expression
28526 formed by PREDICATE_CHAIN is true. This function will be called during
28527 version dispatch to decide which function version to execute. It returns
28528 the basic block at the end, to which more conditions can be added. */
28530 static basic_block
28533 {
28534 gimple return_stmt;
28536 gimple convert_stmt;
28537 gimple call_cond_stmt;
28538 gimple if_else_stmt;
28544 gimple_seq gseq;
28561 {
28569 }
28572 {
28587 else
28588 {
28589 gimple assign_stmt;
28590 /* Use MIN_EXPR to check if any integer is zero?.
28591 and_expr_var = min_expr <cond_var, and_expr_var> */
28599 }
28600 }
28603 integer_zero_node,
28633 }
28635 /* This parses the attribute arguments to target in DECL and determines
28636 the right builtin to use to match the platform specification.
28637 It returns the priority value for this version decl. If PREDICATE_LIST
28638 is not NULL, it stores the list of cpu features that need to be checked
28639 before dispatching this function. */
28641 static unsigned int
28643 {
28644 tree attrs;
28646 tree target_node;
28653 /* Priority of i386 features, greater value is higher priority. This is
28654 used to decide the order in which function dispatch must happen. For
28655 instance, a version specialized for SSE4.2 should be checked for dispatch
28656 before a version for SSE3, as SSE4.2 implies SSE3. */
28657 enum feature_priority
28658 {
28660 P_MMX,
28661 P_SSE,
28662 P_SSE2,
28663 P_SSE3,
28664 P_SSSE3,
28665 P_PROC_SSSE3,
28666 P_SSE4_a,
28667 P_PROC_SSE4_a,
28668 P_SSE4_1,
28669 P_SSE4_2,
28670 P_PROC_SSE4_2,
28671 P_POPCNT,
28672 P_AVX,
28673 P_AVX2,
28674 P_FMA,
28675 P_PROC_FMA
28676 };
28680 /* These are the target attribute strings for which a dispatcher is
28681 available, from fold_builtin_cpu. */
28683 static struct _feature_list
28684 {
28687 }
28689 {
28700 };
28703 static unsigned int NUM_FEATURES
28719 /* Return priority zero for default function. */
28723 /* Handle arch= if specified. For priority, set it to be 1 more than
28724 the best instruction set the processor can handle. For instance, if
28725 there is a version for atom and a version for ssse3 (the highest ISA
28726 priority for atom), the atom version must be checked for dispatch
28727 before the ssse3 version. */
28729 {
28738 {
28740 {
28765 }
28766 }
28771 {
28775 }
28778 {
28780 /* For a C string literal the length includes the trailing NULL. */
28783 predicate_chain);
28784 }
28785 }
28787 /* Process feature name. */
28794 {
28795 /* Do not process "arch=" */
28797 {
28800 }
28802 {
28804 {
28806 {
28811 predicate_chain);
28812 }
28813 /* Find the maximum priority feature. */
28818 }
28819 }
28821 {
28825 }
28827 }
28831 {
28834 attrs_str);
28836 }
28838 {
28841 }
28844 }
28846 /* This compares the priority of target features in function DECL1
28847 and DECL2. It returns positive value if DECL1 is higher priority,
28848 negative value if DECL2 is higher priority and 0 if they are the
28849 same. */
28851 static int
28853 {
28858 }
28860 /* V1 and V2 point to function versions with different priorities
28861 based on the target ISA. This function compares their priorities. */
28863 static int
28865 {
28867 {
28868 tree version_decl;
28869 tree predicate_chain;
28876 }
28878 /* This function generates the dispatch function for
28879 multi-versioned functions. DISPATCH_DECL is the function which will
28880 contain the dispatch logic. FNDECLS are the function choices for
28881 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28882 in DISPATCH_DECL in which the dispatch code is generated. */
28884 static int
28888 {
28889 tree default_decl;
28890 gimple ifunc_cpu_init_stmt;
28891 gimple_seq gseq;
28893 tree ele;
28899 struct _function_version_info
28900 {
28901 tree version_decl;
28902 tree predicate_chain;
28910 /*fndecls_p is actually a vector. */
28913 /* At least one more version other than the default. */
28920 /* The first version in the vector is the default decl. */
28926 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28927 constructors, so explicity call __builtin_cpu_init here. */
28938 {
28942 /* Get attribute string, parse it and find the right predicate decl.
28943 The predicate function could be a lengthy combination of many
28944 features, like arch-type and various isa-variants. */
28955 actual_versions++;
28956 }
28958 /* Sort the versions according to descending order of dispatch priority. The
28959 priority is based on the ISA. This is not a perfect solution. There
28960 could still be ambiguity. If more than one function version is suitable
28961 to execute, which one should be dispatched? In future, allow the user
28962 to specify a dispatch priority next to the version. */
28972 /* dispatch default version at the end. */
28978 }
28980 /* Comparator function to be used in qsort routine to sort attribute
28981 specification strings to "target". */
28983 static int
28985 {
28989 }
28991 /* ARGLIST is the argument to target attribute. This function tokenizes
28992 the comma separated arguments, sorts them and returns a string which
28993 is a unique identifier for the comma separated arguments. It also
28994 replaces non-identifier characters "=,-" with "_". */
28998 {
28999 tree arg;
29008 {
29013 argnum++;
29016 argnum++;
29017 }
29022 {
29028 }
29030 /* Replace "=,-" with "_". */
29043 {
29045 i++;
29047 }
29054 {
29059 }
29064 }
29066 /* This function changes the assembler name for functions that are
29067 versions. If DECL is a function version and has a "target"
29068 attribute, it appends the attribute string to its assembler name. */
29070 static tree
29072 {
29073 tree version_attr;
29081 "Function versions cannot be marked as gnu_inline,"
29090 /* target attribute string cannot be NULL. */
29094 version_string
29105 /* Allow assembler name to be modified if already set. */
29113 }
29115 /* This function returns true if FN1 and FN2 are versions of the same function,
29116 that is, the target strings of the function decls are different. This assumes
29117 that FN1 and FN2 have the same signature. */
29119 static bool
29121 {
29133 /* At least one function decl should have the target attribute specified. */
29137 /* Diagnose missing target attribute if one of the decls is already
29138 multi-versioned. */
29140 {
29142 {
29144 {
29149 }
29152 fn2);
29155 /* Prevent diagnosing of the same error multiple times. */
29160 }
29162 }
29167 /* The sorted target strings must be different for fn1 and fn2
29168 to be versions. */
29171 else
29178 }
29180 static tree
29182 {
29183 /* For function version, add the target suffix to the assembler name. */
29187 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29189 #endif
29192 }
29194 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29195 is true, append the full path name of the source file. */
29199 {
29207 /* Get a unique name that can be used globally without any chances
29208 of collision at link time. */
29218 /* Use '.' to concatenate names as it is demangler friendly. */
29221 suffix);
29222 else
29226 }
29228 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29230 /* Make a dispatcher declaration for the multi-versioned function DECL.
29231 Calls to DECL function will be replaced with calls to the dispatcher
29232 by the front-end. Return the decl created. */
29234 static tree
29236 {
29237 tree func_decl;
29257 /* Mark this func as external, the resolver will flip it again if
29258 it gets generated. */
29260 /* This will be of type IFUNCs have to be externally visible. */
29264 }
29266 #endif
29268 /* Returns true if decl is multi-versioned and DECL is the default function,
29269 that is it is not tagged with target specific optimization. */
29271 static bool
29273 {
29282 }
29284 /* Make a dispatcher declaration for the multi-versioned function DECL.
29285 Calls to DECL function will be replaced with calls to the dispatcher
29286 by the front-end. Returns the decl of the dispatcher function. */
29288 static tree
29290 {
29299 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29303 #endif
29318 /* Find the default version and make it the first node. */
29320 /* Go to the beginnig of the chain. */
29325 {
29330 }
29332 /* If there is no default node, just return NULL. */
29336 /* Make default info the first node. */
29338 {
29345 }
29349 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29350 /* Right now, the dispatching is done via ifunc. */
29356 dispatcher_version_info
29361 /* Set the dispatcher for all the versions. */
29364 {
29367 }
29368 #else
29370 "multiversioning needs ifunc which is not supported "
29372 #endif
29374 }
29376 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29377 it to CHAIN. */
29379 static tree
29381 {
29382 tree attr_name;
29383 tree attr_arg_name;
29384 tree attr_args;
29385 tree attr;
29392 }
29394 /* Make the resolver function decl to dispatch the versions of
29395 a multi-versioned function, DEFAULT_DECL. Create an
29396 empty basic block in the resolver and store the pointer in
29397 EMPTY_BB. Return the decl of the resolver function. */
29399 static tree
29403 {
29408 /* IFUNC's have to be globally visible. So, if the default_decl is
29409 not, then the name of the IFUNC should be made unique. */
29413 /* Append the filename to the resolver function if the versions are
29414 not externally visible. This is because the resolver function has
29415 to be externally visible for the loader to find it. So, appending
29416 the filename will prevent conflicts with a resolver function from
29417 another module which is based on the same version name. */
29420 /* The resolver function should return a (void *). */
29431 /* IFUNC resolvers have to be externally visible. */
29435 /* Resolver is not external, body is generated. */
29445 {
29446 /* In this case, each translation unit with a call to this
29447 versioned function will put out a resolver. Ensure it
29448 is comdat to keep just one copy. */
29451 }
29452 /* Build result decl and add to function_decl. */
29468 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29472 /* Create the alias for dispatch to resolver here. */
29473 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29477 }
29479 /* Generate the dispatching code body to dispatch multi-versioned function
29480 DECL. The target hook is called to process the "target" attributes and
29481 provide the code to dispatch the right function at run-time. NODE points
29482 to the dispatcher decl whose body will be created. */
29484 static tree
29486 {
29487 tree resolver_decl;
29488 basic_block empty_bb;
29490 tree default_ver_decl;
29506 /* The first version in the chain corresponds to the default version. */
29509 /* node is going to be an alias, so remove the finalized bit. */
29523 {
29525 /* Check for virtual functions here again, as by this time it should
29526 have been determined if this function needs a vtable index or
29527 not. This happens for methods in derived classes that override
29528 virtual methods in base classes but are not explicitly marked as
29529 virtual. */
29534 }
29541 }
29542 /* This builds the processor_model struct type defined in
29543 libgcc/config/i386/cpuinfo.c */
29545 static tree
29547 {
29554 /* The first 3 fields are unsigned int. */
29556 {
29562 }
29564 /* The last field is an array of unsigned integers of size one. */
29575 }
29577 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29579 static tree
29581 {
29582 tree new_decl;
29585 VAR_DECL,
29587 type);
29600 }
29602 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29603 into an integer defined in libgcc/config/i386/cpuinfo.c */
29605 static tree
29607 {
29613 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29614 enum processor_features
29615 {
29617 F_MMX,
29618 F_POPCNT,
29619 F_SSE,
29620 F_SSE2,
29621 F_SSE3,
29622 F_SSSE3,
29623 F_SSE4_1,
29624 F_SSE4_2,
29625 F_AVX,
29626 F_AVX2,
29627 F_MAX
29628 };
29630 /* These are the values for vendor types and cpu types and subtypes
29631 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29632 the corresponding start value. */
29633 enum processor_model
29634 {
29636 M_AMD,
29637 M_CPU_TYPE_START,
29638 M_INTEL_ATOM,
29639 M_INTEL_CORE2,
29640 M_INTEL_COREI7,
29641 M_AMDFAM10H,
29642 M_AMDFAM15H,
29643 M_CPU_SUBTYPE_START,
29644 M_INTEL_COREI7_NEHALEM,
29645 M_INTEL_COREI7_WESTMERE,
29646 M_INTEL_COREI7_SANDYBRIDGE,
29647 M_AMDFAM10H_BARCELONA,
29648 M_AMDFAM10H_SHANGHAI,
29649 M_AMDFAM10H_ISTANBUL,
29650 M_AMDFAM15H_BDVER1,
29651 M_AMDFAM15H_BDVER2,
29652 M_AMDFAM15H_BDVER3
29653 };
29655 static struct _arch_names_table
29656 {
29659 }
29661 {
29678 };
29680 static struct _isa_names_table
29681 {
29684 }
29686 {
29698 };
29709 {
29710 /* *args must be a expr that can contain other EXPRS leading to a
29711 STRING_CST. */
29713 {
29716 }
29718 }
29723 {
29724 tree ref;
29725 tree field;
29726 tree final;
29729 unsigned int NUM_ARCH_NAMES
29738 {
29742 }
29747 /* CPU types are stored in the next field. */
29750 {
29753 }
29755 /* CPU subtypes are stored in the next field. */
29757 {
29760 }
29762 /* Get the appropriate field in __cpu_model. */
29766 /* Check the value. */
29770 }
29772 {
29773 tree ref;
29774 tree array_elt;
29775 tree field;
29776 tree final;
29779 unsigned int NUM_ISA_NAMES
29788 {
29792 }
29795 /* Get the last field, which is __cpu_features. */
29799 /* Get the appropriate field: __cpu_model.__cpu_features */
29803 /* Access the 0th element of __cpu_features array. */
29808 /* Return __cpu_model.__cpu_features[0] & field_val */
29812 }
29814 }
29816 static tree
29819 {
29821 {
29826 {
29829 }
29830 }
29832 #ifdef SUBTARGET_FOLD_BUILTIN
29834 #endif
29837 }
29839 /* Make builtins to detect cpu type and features supported. NAME is
29840 the builtin name, CODE is the builtin code, and FTYPE is the function
29841 type of the builtin. */
29843 static void
29846 {
29847 tree decl;
29848 tree type;
29856 }
29858 /* Make builtins to get CPU type and features supported. The created
29859 builtins are :
29861 __builtin_cpu_init (), to detect cpu type and features,
29862 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29863 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29864 */
29866 static void
29868 {
29875 }
29877 /* Internal method for ix86_init_builtins. */
29879 static void
29881 {
29893 sysv_va_ref =
29896 fnvoid_va_end_ms =
29898 fnvoid_va_start_ms =
29900 fnvoid_va_end_sysv =
29902 fnvoid_va_start_sysv =
29904 NULL_TREE);
29905 fnvoid_va_copy_ms =
29907 NULL_TREE);
29908 fnvoid_va_copy_sysv =
29924 }
29926 static void
29928 {
29931 /* The __float80 type. */
29934 {
29935 /* The __float80 type. */
29940 }
29943 /* The __float128 type. */
29949 /* This macro is built by i386-builtin-types.awk. */
29950 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29951 }
29953 static void
29955 {
29956 tree t;
29960 /* Builtins to get CPU type and features. */
29963 /* TFmode support builtins. */
29969 /* We will expand them to normal call if SSE isn't available since
29970 they are used by libgcc. */
29989 #ifdef SUBTARGET_INIT_BUILTINS
29990 SUBTARGET_INIT_BUILTINS;
29991 #endif
29992 }
29994 /* Return the ix86 builtin for CODE. */
29996 static tree
29998 {
30003 }
30005 /* Errors in the source file can cause expand_expr to return const0_rtx
30006 where we expect a vector. To avoid crashing, use one of the vector
30007 clear instructions. */
30008 static rtx
30010 {
30014 }
30016 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30018 static rtx
30020 {
30021 rtx pat;
30041 {
30045 }
30059 }
30061 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30063 static rtx
30067 {
30068 rtx pat;
30076 rtx op;
30083 {
30163 }
30173 {
30180 {
30182 {
30185 {
30203 xop_rotl:
30205 {
30208 gcc_checking_assert
30210 }
30211 else
30212 {
30213 gcc_checking_assert
30224 }
30228 }
30229 }
30230 }
30231 else
30232 {
30233 non_constant:
30237 /* If we aren't optimizing, only allow one memory operand to be
30238 generated. */
30240 num_memory++;
30248 }
30252 }
30255 {
30266 else
30267 {
30273 }
30286 }
30293 }
30295 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30296 insns with vec_merge. */
30298 static rtx
30300 rtx target)
30301 {
30302 rtx pat;
30329 }
30331 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30333 static rtx
30336 {
30337 rtx pat;
30342 rtx op2;
30353 /* Swap operands if we have a comparison that isn't available in
30354 hardware. */
30356 {
30361 }
30381 }
30383 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30385 static rtx
30387 rtx target)
30388 {
30389 rtx pat;
30403 /* Swap operands if we have a comparison that isn't available in
30404 hardware. */
30406 {
30410 }
30431 const0_rtx)));
30434 }
30436 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30438 static rtx
30440 rtx target)
30441 {
30442 rtx pat;
30467 }
30469 static rtx
30472 {
30473 rtx pat;
30478 rtx op2;
30505 }
30507 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30509 static rtx
30511 rtx target)
30512 {
30513 rtx pat;
30546 const0_rtx)));
30549 }
30551 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30553 static rtx
30556 {
30557 rtx pat;
30595 {
30598 }
30601 {
30610 }
30612 {
30621 }
30622 else
30623 {
30630 }
30638 {
30643 emit_insn
30647 FLAGS_REG),
30648 const0_rtx)));
30650 }
30651 else
30653 }
30656 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30658 static rtx
30661 {
30662 rtx pat;
30690 {
30693 }
30696 {
30705 }
30707 {
30716 }
30717 else
30718 {
30725 }
30733 {
30738 emit_insn
30742 FLAGS_REG),
30743 const0_rtx)));
30745 }
30746 else
30748 }
30750 /* Subroutine of ix86_expand_builtin to take care of insns with
30751 variable number of operands. */
30753 static rtx
30756 {
30761 struct
30762 {
30763 rtx op;
30775 {
31054 }
31059 {
31062 }
31065 {
31072 }
31073 else
31074 {
31077 }
31080 {
31087 {
31088 /* SIMD shift insns take either an 8-bit immediate or
31089 register as count. But builtin functions take int as
31090 count. If count doesn't match, we put it in register. */
31092 {
31096 }
31097 }
31099 {
31102 {
31156 {
31159 {
31162 }
31168 }
31170 }
31171 }
31172 else
31173 {
31177 /* If we aren't optimizing, only allow one memory operand to
31178 be generated. */
31180 num_memory++;
31183 {
31186 }
31187 else
31188 {
31191 }
31192 }
31196 }
31199 {
31216 }
31223 }
31225 /* Subroutine of ix86_expand_builtin to take care of special insns
31226 with variable number of operands. */
31228 static rtx
31231 {
31232 tree arg;
31236 struct
31237 {
31238 rtx op;
31248 {
31282 {
31289 }
31305 /* Reserve memory operand for target. */
31308 {
31309 /* These builtins and instructions require the memory
31310 to be properly aligned. */
31326 }
31356 /* Reserve memory operand for target. */
31370 }
31375 {
31380 {
31383 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
31384 on it. Try to improve it using get_pointer_alignment,
31385 and if the special builtin is one that requires strict
31386 mode alignment, also from it's GET_MODE_ALIGNMENT.
31387 Failure to do so could lead to ix86_legitimate_combined_insn
31388 rejecting all changes to such insns. */
31394 }
31395 else
31398 }
31399 else
31400 {
31407 }
31410 {
31419 {
31421 {
31427 else
31430 }
31431 }
31432 else
31433 {
31435 {
31436 /* This must be the memory operand. */
31439 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
31440 on it. Try to improve it using get_pointer_alignment,
31441 and if the special builtin is one that requires strict
31442 mode alignment, also from it's GET_MODE_ALIGNMENT.
31443 Failure to do so could lead to ix86_legitimate_combined_insn
31444 rejecting all changes to such insns. */
31450 }
31451 else
31452 {
31453 /* This must be register. */
31460 }
31461 }
31465 }
31468 {
31483 }
31489 }
31491 /* Return the integer constant in ARG. Constrain it to be in the range
31492 of the subparts of VEC_TYPE; issue an error if not. */
31494 static int
31496 {
31501 {
31504 }
31507 }
31509 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31510 ix86_expand_vector_init. We DO have language-level syntax for this, in
31511 the form of (type){ init-list }. Except that since we can't place emms
31512 instructions from inside the compiler, we can't allow the use of MMX
31513 registers unless the user explicitly asks for it. So we do *not* define
31514 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31515 we have builtins invoked by mmintrin.h that gives us license to emit
31516 these sorts of instructions. */
31518 static rtx
31520 {
31530 {
31533 }
31540 }
31542 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31543 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31544 had a language-level syntax for referencing vector elements. */
31546 static rtx
31548 {
31552 rtx op0;
31572 }
31574 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31575 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31576 a language-level syntax for referencing vector elements. */
31578 static rtx
31580 {
31604 /* OP0 is the source of these builtin functions and shouldn't be
31605 modified. Create a copy, use it and return it as target. */
31611 }
31613 /* Expand an expression EXP that calls a built-in function,
31614 with result going to TARGET if that's convenient
31615 (and in mode MODE if that's convenient).
31616 SUBTARGET may be used as the target for computing one of EXP's operands.
31617 IGNORE is nonzero if the value is to be ignored. */
31619 static rtx
31623 {
31633 /* For CPU builtins that can be folded, fold first and expand the fold. */
31635 {
31637 {
31638 /* Make it call __cpu_indicator_init in libgcc. */
31644 }
31647 {
31652 }
31653 }
31655 /* Determine whether the builtin function is available under the current ISA.
31656 Originally the builtin was not created if it wasn't applicable to the
31657 current ISA based on the command line switches. With function specific
31658 options, we need to check in the context of the function making the call
31659 whether it is supported. */
31662 {
31668 else
31669 {
31673 }
31675 }
31678 {
31682 ? CODE_FOR_mmx_maskmovq
31684 /* Note the arg order is different from the operand order. */
31785 {
31786 REAL_VALUE_TYPE inf;
31787 rtx tmp;
31799 }
31809 {
31815 insn = (TARGET_64BIT
31819 }
31821 {
31822 insn = (TARGET_64BIT
31826 }
31827 else
31828 {
31831 insn = (TARGET_64BIT
31839 {
31842 }
31844 }
31847 {
31848 /* mode is VOIDmode if __builtin_rd* has been called
31849 without lhs. */
31853 }
31856 {
31861 }
31871 {
31886 }
31892 {
31895 }
31915 {
31918 }
31924 {
31928 {
31949 }
31954 }
31955 else
31956 {
31958 {
31970 }
31972 }
32002 ? CODE_FOR_tbm_bextri_si
32005 {
32008 }
32009 else
32010 {
32019 }
32035 rdrand_step:
32042 {
32045 }
32051 /* Emit SImode conditional move. */
32053 {
32056 }
32059 else
32066 const0_rtx);
32085 rdseed_step:
32092 {
32095 }
32101 const0_rtx);
32119 addcarryx:
32127 /* Generate CF from input operand. */
32132 /* Gen ADCX instruction to compute X+Y+CF. */
32147 /* Store the result. */
32150 {
32153 }
32156 /* Return current CF value. */
32225 gather_gen:
32236 /* Note the arg order is different from the operand order. */
32247 else
32252 {
32258 }
32261 {
32266 else
32276 }
32278 /* Force memory operand only with base register here. But we
32279 don't want to do it on memory operand for other builtin
32280 functions. */
32292 {
32295 }
32297 /* Optimize. If mask is known to have all high bits set,
32298 replace op0 with pc_rtx to signal that the instruction
32299 overwrites the whole destination and doesn't use its
32300 previous contents. */
32302 {
32304 {
32307 {
32311 negative++;
32314 negative++;
32315 }
32318 }
32320 {
32321 /* Recognize also when mask is like:
32322 __v2df src = _mm_setzero_pd ();
32323 __v2df mask = _mm_cmpeq_pd (src, src);
32324 or
32325 __v8sf src = _mm256_setzero_ps ();
32326 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32327 as that is a cheaper way to load all ones into
32328 a register than having to load a constant from
32329 memory. */
32332 {
32337 {
32344 /* FALLTHRU */
32354 }
32355 }
32356 }
32357 }
32366 {
32373 else
32375 }
32376 else
32387 {
32390 }
32396 }
32409 {
32413 /* Emit a normal call if SSE isn't available. */
32417 }
32442 }
32444 /* Returns a function decl for a vectorized version of the builtin function
32445 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32446 if it is not available. */
32448 static tree
32450 tree type_in)
32451 {
32467 {
32470 {
32475 }
32480 {
32485 }
32491 /* The round insn does not trap on denormals. */
32496 {
32501 }
32507 /* The round insn does not trap on denormals. */
32512 {
32517 }
32523 /* The round insn does not trap on denormals. */
32528 {
32533 }
32539 /* The round insn does not trap on denormals. */
32544 {
32549 }
32556 {
32561 }
32568 {
32573 }
32579 /* The round insn does not trap on denormals. */
32584 {
32589 }
32595 /* The round insn does not trap on denormals. */
32600 {
32605 }
32610 {
32615 }
32620 {
32625 }
32629 /* The round insn does not trap on denormals. */
32634 {
32639 }
32643 /* The round insn does not trap on denormals. */
32648 {
32653 }
32657 /* The round insn does not trap on denormals. */
32662 {
32667 }
32671 /* The round insn does not trap on denormals. */
32676 {
32681 }
32685 /* The round insn does not trap on denormals. */
32690 {
32695 }
32699 /* The round insn does not trap on denormals. */
32704 {
32709 }
32713 /* The round insn does not trap on denormals. */
32718 {
32723 }
32727 /* The round insn does not trap on denormals. */
32732 {
32737 }
32741 /* The round insn does not trap on denormals. */
32746 {
32751 }
32755 /* The round insn does not trap on denormals. */
32760 {
32765 }
32770 {
32775 }
32780 {
32785 }
32790 }
32792 /* Dispatch to a handler for a vectorization library. */
32795 type_in);
32798 }
32800 /* Handler for an SVML-style interface to
32801 a library with vectorized intrinsics. */
32803 static tree
32805 {
32813 /* The SVML is suitable for unsafe math only. */
32826 {
32873 }
32882 {
32885 }
32886 else
32889 /* Convert to uppercase. */
32894 args;
32896 arity++;
32900 else
32903 /* Build a function declaration for the vectorized function. */
32912 }
32914 /* Handler for an ACML-style interface to
32915 a library with vectorized intrinsics. */
32917 static tree
32919 {
32927 /* The ACML is 64bits only and suitable for unsafe math only as
32928 it does not correctly support parts of IEEE with the required
32929 precision such as denormals. */
32943 {
32973 }
32980 args;
32982 arity++;
32986 else
32989 /* Build a function declaration for the vectorized function. */
32998 }
33000 /* Returns a decl of a function that implements gather load with
33001 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
33002 Return NULL_TREE if it is not available. */
33004 static tree
33007 {
33023 /* v*gather* insn sign extends index to pointer mode. */
33035 {
33062 }
33065 }
33067 /* Returns a code for a target-specific builtin that implements
33068 reciprocal of the function, or NULL_TREE if not available. */
33070 static tree
33073 {
33080 /* Machine dependent builtins. */
33082 {
33083 /* Vectorized version of sqrt to rsqrt conversion. */
33092 }
33093 else
33094 /* Normal builtins. */
33096 {
33097 /* Sqrt to rsqrt conversion. */
33103 }
33104 }
33105 \f
33106 /* Helper for avx_vpermilps256_operand et al. This is also used by
33107 the expansion functions to turn the parallel back into a mask.
33108 The return value is 0 for no match and the imm8+1 for a match. */
33110 int
33112 {
33120 /* Validate that all of the elements are constants, and not totally
33121 out of range. Copy the data into an integral array to make the
33122 subsequent checks easier. */
33124 {
33134 }
33137 {
33139 /* In the 256-bit DFmode case, we can only move elements within
33140 a 128-bit lane. */
33142 {
33146 }
33148 {
33152 }
33156 /* In the 256-bit SFmode case, we have full freedom of movement
33157 within the low 128-bit lane, but the high 128-bit lane must
33158 mirror the exact same pattern. */
33163 /* FALLTHRU */
33167 /* In the 128-bit case, we've full freedom in the placement of
33168 the elements from the source operand. */
33175 }
33177 /* Make sure success has a non-zero value by adding one. */
33179 }
33181 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33182 the expansion functions to turn the parallel back into a mask.
33183 The return value is 0 for no match and the imm8+1 for a match. */
33185 int
33187 {
33195 /* Validate that all of the elements are constants, and not totally
33196 out of range. Copy the data into an integral array to make the
33197 subsequent checks easier. */
33199 {
33209 }
33211 /* Validate that the halves of the permute are halves. */
33219 /* Reconstruct the mask. */
33221 {
33227 }
33229 /* Make sure success has a non-zero value by adding one. */
33231 }
33232 \f
33233 /* Store OPERAND to the memory after reload is completed. This means
33234 that we can't easily use assign_stack_local. */
33235 rtx
33237 {
33238 rtx result;
33242 {
33245 stack_pointer_rtx,
33248 }
33250 {
33252 {
33256 /* FALLTHRU */
33262 stack_pointer_rtx)),
33263 operand));
33267 }
33269 }
33270 else
33271 {
33273 {
33275 {
33282 stack_pointer_rtx)),
33288 stack_pointer_rtx)),
33290 }
33293 /* Store HImodes as SImodes. */
33295 /* FALLTHRU */
33301 stack_pointer_rtx)),
33302 operand));
33306 }
33308 }
33310 }
33312 /* Free operand from the memory. */
33313 void
33315 {
33317 {
33322 else
33324 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33325 to pop or add instruction if registers are available. */
33329 }
33330 }
33332 /* Return a register priority for hard reg REGNO. */
33333 static int
33335 {
33336 /* ebp and r13 as the base always wants a displacement, r12 as the
33337 base always wants an index. So discourage their usage in an
33338 address. */
33343 /* New x86-64 int registers result in bigger code size. Discourage
33344 them. */
33347 /* New x86-64 SSE registers result in bigger code size. Discourage
33348 them. */
33351 /* Usage of AX register results in smaller code. Prefer it. */
33355 }
33357 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33359 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33360 QImode must go into class Q_REGS.
33361 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33362 movdf to do mem-to-mem moves through integer regs. */
33364 static reg_class_t
33366 {
33369 /* We're only allowed to return a subclass of CLASS. Many of the
33370 following checks fail for NO_REGS, so eliminate that early. */
33374 /* All classes can load zeros. */
33378 /* Force constants into memory if we are loading a (nonzero) constant into
33379 an MMX or SSE register. This is because there are no MMX/SSE instructions
33380 to load from a constant. */
33385 /* Prefer SSE regs only, if we can use them for math. */
33389 /* Floating-point constants need more complex checks. */
33391 {
33392 /* General regs can load everything. */
33396 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33397 zero above. We only want to wind up preferring 80387 registers if
33398 we plan on doing computation with them. */
33401 {
33402 /* Limit class to non-sse. */
33411 }
33414 }
33416 /* Generally when we see PLUS here, it's the function invariant
33417 (plus soft-fp const_int). Which can only be computed into general
33418 regs. */
33422 /* QImode constants are easy to load, but non-constant QImode data
33423 must go into Q_REGS. */
33425 {
33431 }
33434 }
33436 /* Discourage putting floating-point values in SSE registers unless
33437 SSE math is being used, and likewise for the 387 registers. */
33438 static reg_class_t
33440 {
33443 /* Restrict the output reload class to the register bank that we are doing
33444 math on. If we would like not to return a subset of CLASS, reject this
33445 alternative: if reload cannot do this, it will still use its choice. */
33451 {
33456 else
33458 }
33461 }
33463 static reg_class_t
33466 {
33467 /* Double-word spills from general registers to non-offsettable memory
33468 references (zero-extended addresses) require special handling. */
33474 {
33476 ? CODE_FOR_reload_noff_load
33478 /* Add the cost of moving address to a temporary. */
33482 }
33484 /* QImode spills from non-QI registers require
33485 intermediate register on 32bit targets. */
33494 {
33499 else
33505 /* Return Q_REGS if the operand is in memory. */
33508 }
33510 /* This condition handles corner case where an expression involving
33511 pointers gets vectorized. We're trying to use the address of a
33512 stack slot as a vector initializer.
33514 (set (reg:V2DI 74 [ vect_cst_.2 ])
33515 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33517 Eventually frame gets turned into sp+offset like this:
33519 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33520 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33521 (const_int 392 [0x188]))))
33523 That later gets turned into:
33525 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33526 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33527 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33529 We'll have the following reload recorded:
33531 Reload 0: reload_in (DI) =
33532 (plus:DI (reg/f:DI 7 sp)
33533 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33534 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33535 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33536 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33537 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33538 reload_reg_rtx: (reg:V2DI 22 xmm1)
33540 Which isn't going to work since SSE instructions can't handle scalar
33541 additions. Returning GENERAL_REGS forces the addition into integer
33542 register and reload can handle subsequent reloads without problems. */
33550 }
33552 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33554 static bool
33556 {
33558 {
33573 }
33576 }
33578 /* If we are copying between general and FP registers, we need a memory
33579 location. The same is true for SSE and MMX registers.
33581 To optimize register_move_cost performance, allow inline variant.
33583 The macro can't work reliably when one of the CLASSES is class containing
33584 registers from multiple units (SSE, MMX, integer). We avoid this by never
33585 combining those units in single alternative in the machine description.
33586 Ensure that this constraint holds to avoid unexpected surprises.
33588 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33589 enforce these sanity checks. */
33594 {
33601 {
33604 }
33609 /* ??? This is a lie. We do have moves between mmx/general, and for
33610 mmx/sse2. But by saying we need secondary memory we discourage the
33611 register allocator from using the mmx registers unless needed. */
33616 {
33617 /* SSE1 doesn't have any direct moves from other classes. */
33621 /* If the target says that inter-unit moves are more expensive
33622 than moving through memory, then don't generate them. */
33626 /* Between SSE and general, we have moves no larger than word size. */
33629 }
33632 }
33634 bool
33637 {
33639 }
33641 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33643 On the 80386, this is the size of MODE in words,
33644 except in the FP regs, where a single reg is always enough. */
33646 static unsigned char
33648 {
33650 {
33655 else
33657 }
33658 else
33659 {
33662 else
33664 }
33665 }
33667 /* Return true if the registers in CLASS cannot represent the change from
33668 modes FROM to TO. */
33670 bool
33673 {
33677 /* x87 registers can't do subreg at all, as all values are reformatted
33678 to extended precision. */
33683 {
33684 /* Vector registers do not support QI or HImode loads. If we don't
33685 disallow a change to these modes, reload will assume it's ok to
33686 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33687 the vec_dupv4hi pattern. */
33691 /* Vector registers do not support subreg with nonzero offsets, which
33692 are otherwise valid for integer registers. Since we can't see
33693 whether we have a nonzero offset from here, prohibit all
33694 nonparadoxical subregs changing size. */
33697 }
33700 }
33702 /* Return the cost of moving data of mode M between a
33703 register and memory. A value of 2 is the default; this cost is
33704 relative to those in `REGISTER_MOVE_COST'.
33706 This function is used extensively by register_move_cost that is used to
33707 build tables at startup. Make it inline in this case.
33708 When IN is 2, return maximum of in and out move cost.
33710 If moving between registers and memory is more expensive than
33711 between two registers, you should define this macro to express the
33712 relative cost.
33714 Model also increased moving costs of QImode registers in non
33715 Q_REGS classes.
33716 */
33720 {
33723 {
33726 {
33738 }
33742 }
33744 {
33747 {
33759 }
33763 }
33765 {
33768 {
33777 }
33781 }
33783 {
33786 {
33792 else
33797 }
33798 else
33799 {
33804 else
33806 }
33813 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33820 else
33824 }
33825 }
33827 static int
33830 {
33832 }
33835 /* Return the cost of moving data from a register in class CLASS1 to
33836 one in class CLASS2.
33838 It is not required that the cost always equal 2 when FROM is the same as TO;
33839 on some machines it is expensive to move between registers if they are not
33840 general registers. */
33842 static int
33844 reg_class_t class2_i)
33845 {
33849 /* In case we require secondary memory, compute cost of the store followed
33850 by load. In order to avoid bad register allocation choices, we need
33851 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33854 {
33860 /* In case of copying from general_purpose_register we may emit multiple
33861 stores followed by single load causing memory size mismatch stall.
33862 Count this as arbitrarily high cost of 20. */
33867 /* In the case of FP/MMX moves, the registers actually overlap, and we
33868 have to switch modes in order to treat them differently. */
33874 }
33876 /* Moves between SSE/MMX and integer unit are expensive. */
33880 /* ??? By keeping returned value relatively high, we limit the number
33881 of moves between integer and MMX/SSE registers for all targets.
33882 Additionally, high value prevents problem with x86_modes_tieable_p(),
33883 where integer modes in MMX/SSE registers are not tieable
33884 because of missing QImode and HImode moves to, from or between
33885 MMX/SSE registers. */
33895 }
33897 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33898 MODE. */
33900 bool
33902 {
33903 /* Flags and only flags can only hold CCmode values. */
33913 {
33914 /* We implement the move patterns for all vector modes into and
33915 out of SSE registers, even when no operation instructions
33916 are available. OImode and AVX modes are available only when
33917 AVX is enabled. */
33924 }
33926 {
33927 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33928 so if the register is available at all, then we can move data of
33929 the given mode into or out of it. */
33932 }
33935 {
33936 /* Take care for QImode values - they can be in non-QI regs,
33937 but then they do cause partial register stalls. */
33942 /* LRA checks if the hard register is OK for the given mode.
33943 QImode values can live in non-QI regs, so we allow all
33944 registers here. */
33948 }
33949 /* We handle both integer and floats in the general purpose registers. */
33956 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33957 on to use that value in smaller contexts, this can easily force a
33958 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33959 supporting DImode, allow it. */
33964 }
33966 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33967 tieable integer mode. */
33969 static bool
33971 {
33973 {
33986 }
33987 }
33989 /* Return true if MODE1 is accessible in a register that can hold MODE2
33990 without copying. That is, all register classes that can hold MODE2
33991 can also hold MODE1. */
33993 bool
33995 {
34003 /* MODE2 being XFmode implies fp stack or general regs, which means we
34004 can tie any smaller floating point modes to it. Note that we do not
34005 tie this with TFmode. */
34009 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
34010 that we can tie it with SFmode. */
34014 /* If MODE2 is only appropriate for an SSE register, then tie with
34015 any other mode acceptable to SSE registers. */
34025 /* If MODE2 is appropriate for an MMX register, then tie
34026 with any other mode acceptable to MMX registers. */
34033 }
34035 /* Return the cost of moving between two registers of mode MODE. */
34037 static int
34039 {
34043 {
34074 }
34076 /* Return the cost of moving between two registers of mode MODE,
34077 assuming that the move will be in pieces of at most UNITS bytes. */
34079 }
34081 /* Compute a (partial) cost for rtx X. Return true if the complete
34082 cost has been computed, and false if subexpressions should be
34083 scanned. In either case, *TOTAL contains the cost result. */
34085 static bool
34088 {
34095 {
34099 {
34102 }
34114 && (!TARGET_64BIT
34119 else
34125 {
34128 }
34130 {
34140 }
34142 {
34145 {
34154 }
34155 }
34156 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34157 it'll probably end up. Add a penalty for size. */
34164 /* The zero extensions is often completely free on x86_64, so make
34165 it as cheap as possible. */
34171 else
34183 {
34186 {
34189 }
34192 {
34195 }
34196 }
34197 /* FALLTHRU */
34204 {
34205 /* ??? Should be SSE vector operation cost. */
34206 /* At least for published AMD latencies, this really is the same
34207 as the latency for a simple fpu operation like fabs. */
34208 /* V*QImode is emulated with 1-11 insns. */
34210 {
34213 {
34214 /* For XOP we use vpshab, which requires a broadcast of the
34215 value to the variable shift insn. For constants this
34216 means a V16Q const in mem; even when we can perform the
34217 shift with one insn set the cost to prefer paddb. */
34219 {
34224 }
34226 }
34230 }
34231 else
34233 }
34235 {
34237 {
34240 else
34242 }
34243 else
34244 {
34247 else
34249 }
34250 }
34251 else
34252 {
34257 {
34258 /* Return the cost after shift-and truncation. */
34261 }
34262 else
34264 }
34268 {
34269 rtx sub;
34274 /* ??? SSE scalar/vector cost should be used here. */
34275 /* ??? Bald assumption that fma has the same cost as fmul. */
34279 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34290 }
34294 {
34295 /* ??? SSE scalar cost should be used here. */
34298 }
34300 {
34303 }
34305 {
34306 /* ??? SSE vector cost should be used here. */
34309 }
34311 {
34312 /* V*QImode is emulated with 7-13 insns. */
34314 {
34321 }
34322 /* V*DImode is emulated with 5-8 insns. */
34324 {
34327 else
34329 }
34330 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34331 insns, including two PMULUDQ. */
34334 else
34337 }
34338 else
34339 {
34344 {
34347 nbits++;
34348 }
34349 else
34350 /* This is arbitrary. */
34353 /* Compute costs correctly for widening multiplication. */
34357 {
34364 {
34368 else
34370 }
34374 }
34382 }
34389 /* ??? SSE cost should be used here. */
34394 /* ??? SSE vector cost should be used here. */
34396 else
34403 {
34408 {
34411 {
34419 }
34420 }
34423 {
34426 {
34432 }
34433 }
34435 {
34443 }
34444 }
34445 /* FALLTHRU */
34449 {
34450 /* ??? SSE cost should be used here. */
34453 }
34455 {
34458 }
34460 {
34461 /* ??? SSE vector cost should be used here. */
34464 }
34465 /* FALLTHRU */
34472 {
34479 }
34480 /* FALLTHRU */
34484 {
34485 /* ??? SSE cost should be used here. */
34488 }
34490 {
34493 }
34495 {
34496 /* ??? SSE vector cost should be used here. */
34499 }
34500 /* FALLTHRU */
34504 {
34505 /* ??? Should be SSE vector operation cost. */
34506 /* At least for published AMD latencies, this really is the same
34507 as the latency for a simple fpu operation like fabs. */
34509 }
34512 else
34521 {
34522 /* This kind of construct is implemented using test[bwl].
34523 Treat it as if we had an AND. */
34528 }
34538 /* ??? SSE cost should be used here. */
34543 /* ??? SSE vector cost should be used here. */
34549 /* ??? SSE cost should be used here. */
34554 /* ??? SSE vector cost should be used here. */
34567 /* ??? Assume all of these vector manipulation patterns are
34568 recognizable. In which case they all pretty much have the
34569 same cost. */
34575 }
34576 }
34578 #if TARGET_MACHO
34582 /* Given a symbol name and its associated stub, write out the
34583 definition of the stub. */
34585 void
34587 {
34592 /* For 64-bit we shouldn't get here. */
34595 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34612 else
34619 {
34621 }
34623 {
34624 /* PIC stub. */
34625 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34631 }
34632 else
34635 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34636 it needs no stub-binding-helper. */
34643 {
34646 }
34647 else
34652 /* N.B. Keep the correspondence of these
34653 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34654 old-pic/new-pic/non-pic stubs; altering this will break
34655 compatibility with existing dylibs. */
34657 {
34658 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34660 }
34661 else
34662 /* 16-byte -mdynamic-no-pic stub. */
34668 }
34671 /* Order the registers for register allocator. */
34673 void
34675 {
34679 /* First allocate the local general purpose registers. */
34684 /* Global general purpose registers. */
34689 /* x87 registers come first in case we are doing FP math
34690 using them. */
34695 /* SSE registers. */
34701 /* x87 registers. */
34709 /* Initialize the rest of array as we do not allocate some registers
34710 at all. */
34713 }
34715 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34716 in struct attribute_spec handler. */
34717 static tree
34719 tree args,
34722 {
34727 {
34729 name);
34732 }
34734 {
34736 name);
34739 }
34741 {
34742 tree cst;
34746 {
34749 name);
34751 }
34754 {
34757 name);
34759 }
34762 }
34765 }
34767 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34768 struct attribute_spec.handler. */
34769 static tree
34771 tree args ATTRIBUTE_UNUSED,
34773 {
34778 {
34780 name);
34783 }
34785 /* Can combine regparm with all attributes but fastcall. */
34787 {
34789 {
34791 }
34794 }
34796 {
34798 {
34800 }
34803 }
34806 }
34808 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34809 struct attribute_spec.handler. */
34810 static tree
34812 tree args ATTRIBUTE_UNUSED,
34814 {
34817 {
34820 }
34821 else
34825 {
34827 name);
34829 }
34835 {
34837 name);
34839 }
34842 }
34844 static tree
34846 tree args ATTRIBUTE_UNUSED,
34848 {
34850 {
34852 name);
34854 }
34856 }
34858 static bool
34860 {
34864 }
34866 /* Returns an expression indicating where the this parameter is
34867 located on entry to the FUNCTION. */
34869 static rtx
34871 {
34877 {
34882 else
34885 }
34890 {
34897 {
34902 }
34903 else
34904 {
34907 {
34913 }
34914 }
34916 }
34920 }
34922 /* Determine whether x86_output_mi_thunk can succeed. */
34924 static bool
34926 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34928 {
34929 /* 64-bit can handle anything. */
34933 /* For 32-bit, everything's fine if we have one free register. */
34937 /* Need a free register for vcall_offset. */
34941 /* Need a free register for GOT references. */
34945 /* Otherwise ok. */
34947 }
34949 /* Output the assembler code for a thunk function. THUNK_DECL is the
34950 declaration for the thunk function itself, FUNCTION is the decl for
34951 the target function. DELTA is an immediate constant offset to be
34952 added to THIS. If VCALL_OFFSET is nonzero, the word at
34953 *(*this + vcall_offset) should be added to THIS. */
34955 static void
34959 {
34966 else
34967 {
34973 else
34975 }
34979 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34980 pull it in now and let DELTA benefit. */
34984 {
34985 /* Put the this parameter into %eax. */
34988 }
34989 else
34992 /* Adjust the this parameter by a fixed constant. */
34994 {
34999 {
35001 {
35005 }
35006 }
35009 }
35011 /* Adjust the this parameter by a value stored in the vtable. */
35013 {
35023 /* Adjust the this parameter. */
35027 {
35031 }
35038 vcall_mem));
35039 else
35041 }
35043 /* If necessary, drop THIS back to its stack slot. */
35049 {
35052 ;
35053 else
35054 {
35058 }
35059 }
35060 else
35061 {
35063 ;
35064 #if TARGET_MACHO
35066 {
35069 }
35071 else
35072 {
35079 }
35080 }
35082 /* Our sibling call patterns do not allow memories, because we have no
35083 predicate that can distinguish between frame and non-frame memory.
35084 For our purposes here, we can get away with (ab)using a jump pattern,
35085 because we're going to do no optimization. */
35088 else
35089 {
35095 {
35101 }
35107 }
35110 /* Emit just enough of rest_of_compilation to get the insns emitted.
35111 Note that use_thunk calls assemble_start_function et al. */
35117 }
35119 static void
35121 {
35123 #if TARGET_MACHO
35125 #endif
35132 }
35134 int
35136 {
35148 }
35150 /* Output assembler code to FILE to increment profiler label # LABELNO
35151 for profiling a function entry. */
35152 void
35154 {
35159 {
35160 #ifndef NO_PROFILE_COUNTERS
35162 #endif
35166 else
35168 }
35170 {
35171 #ifndef NO_PROFILE_COUNTERS
35174 #endif
35176 }
35177 else
35178 {
35179 #ifndef NO_PROFILE_COUNTERS
35182 #endif
35184 }
35185 }
35187 /* We don't have exact information about the insn sizes, but we may assume
35188 quite safely that we are informed about all 1 byte insns and memory
35189 address sizes. This is enough to eliminate unnecessary padding in
35190 99% of cases. */
35192 static int
35194 {
35200 /* Discard alignments we've emit and jump instructions. */
35207 /* Important case - calls are always 5 bytes.
35208 It is common to have many calls in the row. */
35217 /* For normal instructions we rely on get_attr_length being exact,
35218 with a few exceptions. */
35220 {
35224 {
35234 /* Otherwise trust get_attr_length. */
35236 }
35241 }
35244 else
35246 }
35248 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35250 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35251 window. */
35253 static void
35255 {
35260 /* Look for all minimal intervals of instructions containing 4 jumps.
35261 The intervals are bounded by START and INSN. NBYTES is the total
35262 size of instructions in the interval including INSN and not including
35263 START. When the NBYTES is smaller than 16 bytes, it is possible
35264 that the end of START and INSN ends up in the same 16byte page.
35266 The smallest offset in the page INSN can start is the case where START
35267 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35268 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35270 Don't consider asm goto as jump, while it can contain a jump, it doesn't
35271 have to, control transfer to label(s) can be performed through other
35272 means, and also we estimate minimum length of all asm stmts as 0. */
35274 {
35278 {
35284 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35285 already in the current 16 byte page, because otherwise
35286 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35287 bytes to reach 16 byte boundary. */
35295 {
35297 {
35305 else
35308 }
35309 }
35311 }
35323 njumps++;
35324 else
35328 {
35336 else
35339 }
35346 {
35353 }
35354 }
35355 }
35356 #endif
35358 /* AMD Athlon works faster
35359 when RET is not destination of conditional jump or directly preceded
35360 by other jump instruction. We avoid the penalty by inserting NOP just
35361 before the RET instructions in such cases. */
35362 static void
35364 {
35365 edge e;
35366 edge_iterator ei;
35369 {
35372 rtx prev;
35382 {
35383 edge e;
35384 edge_iterator ei;
35390 }
35392 {
35398 /* Empty functions get branch mispredict even when
35399 the jump destination is not visible to us. */
35402 }
35404 {
35407 }
35408 }
35409 }
35411 /* Count the minimum number of instructions in BB. Return 4 if the
35412 number of instructions >= 4. */
35414 static int
35416 {
35417 rtx insn;
35420 /* Count number of instructions in this block. Return 4 if the number
35421 of instructions >= 4. */
35423 {
35424 /* Only happen in exit blocks. */
35432 {
35433 insn_count++;
35436 }
35437 }
35440 }
35443 /* Count the minimum number of instructions in code path in BB.
35444 Return 4 if the number of instructions >= 4. */
35446 static int
35448 {
35449 edge e;
35450 edge_iterator ei;
35453 /* Only bother counting instructions along paths with no
35454 more than 2 basic blocks between entry and exit. Given
35455 that BB has an edge to exit, determine if a predecessor
35456 of BB has an edge from entry. If so, compute the number
35457 of instructions in the predecessor block. If there
35458 happen to be multiple such blocks, compute the minimum. */
35461 {
35462 edge prev_e;
35463 edge_iterator prev_ei;
35466 {
35469 }
35471 {
35473 {
35478 }
35479 }
35480 }
35486 }
35488 /* Pad short function to 4 instructions. */
35490 static void
35492 {
35493 edge e;
35494 edge_iterator ei;
35497 {
35500 {
35503 /* Pad short function. */
35505 {
35508 /* Find epilogue. */
35517 /* Two NOPs count as one instruction. */
35520 }
35521 }
35522 }
35523 }
35525 /* Fix up a Windows system unwinder issue. If an EH region falls thru into
35526 the epilogue, the Windows system unwinder will apply epilogue logic and
35527 produce incorrect offsets. This can be avoided by adding a nop between
35528 the last insn that can throw and the first insn of the epilogue. */
35530 static void
35532 {
35533 edge e;
35534 edge_iterator ei;
35537 {
35540 /* Find the beginning of the epilogue. */
35547 /* We only care about preceeding insns that can throw. */
35552 /* Do not separate calls from their debug information. */
35558 else
35562 }
35563 }
35565 /* Implement machine specific optimizations. We implement padding of returns
35566 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35567 static void
35569 {
35570 /* We are freeing block_for_insn in the toplev to keep compatibility
35571 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35578 {
35583 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35586 #endif
35587 }
35588 }
35590 /* Return nonzero when QImode register that must be represented via REX prefix
35591 is used. */
35592 bool
35594 {
35602 }
35604 /* Return nonzero when P points to register encoded via REX prefix.
35605 Called via for_each_rtx. */
35606 static int
35608 {
35614 }
35616 /* Return true when INSN mentions register that must be encoded using REX
35617 prefix. */
35618 bool
35620 {
35623 }
35625 /* If profitable, negate (without causing overflow) integer constant
35626 of mode MODE at location LOC. Return true in this case. */
35627 bool
35629 {
35630 HOST_WIDE_INT val;
35636 {
35638 /* DImode x86_64 constants must fit in 32 bits. */
35651 }
35653 /* Avoid overflows. */
35659 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35660 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35663 {
35666 }
35669 }
35671 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35672 optabs would emit if we didn't have TFmode patterns. */
35674 void
35676 {
35710 }
35711 \f
35712 /* AVX2 does support 32-byte integer vector operations,
35713 thus the longest vector we are faced with is V32QImode. */
35714 #define MAX_VECT_LEN 32
35716 struct expand_vec_perm_d
35717 {
35724 };
35730 /* Get a vector mode of the same size as the original but with elements
35731 twice as wide. This is only guaranteed to apply to integral vectors. */
35735 {
35736 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35741 }
35743 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35744 with all elements equal to VAR. Return true if successful. */
35746 static bool
35749 {
35753 {
35758 /* FALLTHRU */
35768 {
35771 /* First attempt to recognize VAL as-is. */
35775 {
35776 rtx seq;
35777 /* If that fails, force VAL into a register. */
35788 }
35789 }
35796 {
35797 rtx x;
35804 }
35814 {
35818 permute:
35826 /* Extend to SImode using a paradoxical SUBREG. */
35830 /* Insert the SImode value as low element of a V4SImode vector. */
35838 }
35846 widen:
35847 /* Replicate the value once into the next wider mode and recurse. */
35848 {
35850 rtx x;
35866 }
35870 {
35879 }
35884 }
35885 }
35887 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35888 whose ONE_VAR element is VAR, and other elements are zero. Return true
35889 if successful. */
35891 static bool
35894 {
35896 rtx new_target;
35901 {
35903 /* For SSE4.1, we normally use vector set. But if the second
35904 element is zero and inter-unit moves are OK, we use movq
35905 instead. */
35906 use_vector_set = (TARGET_64BIT
35907 && TARGET_SSE4_1
35908 && !(TARGET_INTER_UNIT_MOVES
35930 /* Use ix86_expand_vector_set in 64bit mode only. */
35935 }
35938 {
35943 }
35946 {
35951 /* FALLTHRU */
35966 else
35973 {
35974 /* We need to shuffle the value to the correct position, so
35975 create a new pseudo to store the intermediate result. */
35977 /* With SSE2, we can use the integer shuffle insns. */
35979 {
35981 const1_rtx,
35988 }
35990 /* Otherwise convert the intermediate result to V4SFmode and
35991 use the SSE1 shuffle instructions. */
35993 {
35996 }
35997 else
36001 const1_rtx,
36010 }
36025 widen:
36029 /* Zero extend the variable element to SImode and recurse. */
36042 }
36043 }
36045 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36046 consisting of the values in VALS. It is known that all elements
36047 except ONE_VAR are constants. Return true if successful. */
36049 static bool
36052 {
36062 {
36067 /* For the two element vectors, it's just as easy to use
36068 the general case. */
36072 /* Use ix86_expand_vector_set in 64bit mode only. */
36094 widen:
36095 /* There's no way to set one QImode entry easily. Combine
36096 the variable value with its adjacent constant value, and
36097 promote to an HImode set. */
36100 {
36105 }
36106 else
36107 {
36110 }
36124 }
36129 }
36131 /* A subroutine of ix86_expand_vector_init_general. Use vector
36132 concatenate to handle the most general case: all values variable,
36133 and none identical. */
36135 static void
36138 {
36141 rtvec v;
36145 {
36148 {
36181 }
36194 {
36209 }
36214 {
36225 }
36228 half:
36229 /* FIXME: We process inputs backward to help RA. PR 36222. */
36233 {
36238 }
36242 {
36245 {
36249 }
36252 }
36253 else
36259 }
36260 }
36262 /* A subroutine of ix86_expand_vector_init_general. Use vector
36263 interleave to handle the most general case: all values variable,
36264 and none identical. */
36266 static void
36269 {
36278 {
36299 }
36302 {
36303 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36307 /* Insert the SImode value as low element of V4SImode vector. */
36311 op0),
36313 const1_rtx);
36316 /* Cast the V4SImode vector back to a vector in orignal mode. */
36320 /* Load even elements into the second positon. */
36324 const1_rtx));
36326 /* Cast vector to FIRST_IMODE vector. */
36329 }
36331 /* Interleave low FIRST_IMODE vectors. */
36333 {
36337 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36340 }
36342 /* Interleave low SECOND_IMODE vectors. */
36344 {
36347 {
36352 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36353 vector. */
36356 }
36359 /* FALLTHRU */
36366 /* Cast the SECOND_IMODE vector back to a vector on original
36367 mode. */
36374 }
36375 }
36377 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36378 all values variable, and none identical. */
36380 static void
36383 {
36389 {
36394 /* FALLTHRU */
36418 half:
36435 /* FALLTHRU */
36441 /* Don't use ix86_expand_vector_init_interleave if we can't
36442 move from GPR to SSE register directly. */
36458 }
36460 {
36472 {
36476 {
36482 else
36483 {
36488 }
36489 }
36492 }
36497 {
36503 }
36505 {
36511 }
36512 else
36514 }
36515 }
36517 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36518 instructions unless MMX_OK is true. */
36520 void
36522 {
36529 rtx x;
36532 {
36542 }
36544 /* Constants are best loaded from the constant pool. */
36546 {
36549 }
36551 /* If all values are identical, broadcast the value. */
36557 /* Values where only one field is non-constant are best loaded from
36558 the pool and overwritten via move later. */
36560 {
36564 one_var))
36569 }
36572 }
36574 void
36576 {
36581 rtx tmp;
36583 = {
36590 };
36592 = {
36599 };
36603 {
36607 {
36612 else
36616 }
36628 else
36634 {
36637 /* For the two element vectors, we implement a VEC_CONCAT with
36638 the extraction of the other element. */
36645 else
36650 }
36659 {
36665 /* tmp = target = A B C D */
36667 /* target = A A B B */
36669 /* target = X A B B */
36671 /* target = A X C D */
36678 /* tmp = target = A B C D */
36680 /* tmp = X B C D */
36682 /* target = A B X D */
36689 /* tmp = target = A B C D */
36691 /* tmp = X B C D */
36693 /* target = A B X D */
36701 }
36709 /* Element 0 handled by vec_merge below. */
36711 {
36714 }
36717 {
36718 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36719 store into element 0, then shuffle them back. */
36736 }
36737 else
36738 {
36739 /* For SSE1, we have to reuse the V4SF code. */
36742 }
36795 half:
36796 /* Compute offset. */
36802 /* Extract the half. */
36806 /* Put val in tmp at elt. */
36809 /* Put it back. */
36815 }
36818 {
36822 }
36823 else
36824 {
36833 }
36834 }
36836 void
36838 {
36842 rtx tmp;
36845 {
36850 /* FALLTHRU */
36863 {
36883 }
36895 {
36897 {
36917 }
36921 }
36922 else
36923 {
36924 /* For SSE1, we have to reuse the V4SF code. */
36928 }
36944 {
36948 else
36952 }
36957 {
36961 else
36965 }
36970 {
36974 else
36978 }
36983 {
36987 else
36991 }
36996 {
37000 else
37004 }
37009 {
37013 else
37017 }
37021 /* ??? Could extract the appropriate HImode element and shift. */
37024 }
37027 {
37031 /* Let the rtl optimizers know about the zero extension performed. */
37033 {
37036 }
37039 }
37040 else
37041 {
37048 }
37049 }
37051 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
37052 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
37053 The upper bits of DEST are undefined, though they shouldn't cause
37054 exceptions (some bits from src or all zeros are ok). */
37056 static void
37058 {
37059 rtx tem;
37061 {
37065 else
37083 else
37090 else
37101 const1_rtx);
37102 else
37109 }
37111 }
37113 /* Expand a vector reduction. FN is the binary pattern to reduce;
37114 DEST is the destination; IN is the input vector. */
37116 void
37118 {
37123 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37127 {
37130 }
37135 {
37140 else
37144 }
37145 }
37146 \f
37147 /* Target hook for scalar_mode_supported_p. */
37148 static bool
37150 {
37155 else
37157 }
37159 /* Implements target hook vector_mode_supported_p. */
37160 static bool
37162 {
37174 }
37176 /* Target hook for c_mode_for_suffix. */
37177 static enum machine_mode
37179 {
37186 }
37188 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37190 We do this in the new i386 backend to maintain source compatibility
37191 with the old cc0-based compiler. */
37193 static tree
37195 tree inputs ATTRIBUTE_UNUSED,
37196 tree clobbers)
37197 {
37199 clobbers);
37201 clobbers);
37203 }
37205 /* Implements target vector targetm.asm.encode_section_info. */
37207 static void ATTRIBUTE_UNUSED
37209 {
37216 }
37218 /* Worker function for REVERSE_CONDITION. */
37220 enum rtx_code
37222 {
37226 }
37228 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37229 to OPERANDS[0]. */
37233 {
37235 {
37238 {
37242 }
37246 }
37248 {
37252 else
37253 {
37254 /* There is no non-popping store to memory for XFmode.
37255 So if we need one, follow the store with a load. */
37258 else
37260 }
37261 }
37262 else
37264 }
37266 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37267 FP status register is set. */
37269 void
37271 {
37273 rtx temp;
37278 {
37283 }
37284 else
37285 {
37290 }
37294 pc_rtx);
37299 }
37301 /* Output code to perform a log1p XFmode calculation. */
37304 {
37310 rtx test;
37316 XFmode));
37330 }
37332 /* Emit code for round calculation. */
37334 {
37341 rtx insn;
37346 {
37358 }
37361 {
37382 }
37390 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37392 /* scratch = fxam(op1) */
37395 UNSPEC_FXAM)));
37396 /* e1 = fabs(op1) */
37399 /* e2 = e1 + 0.5 */
37404 /* res = floor(e2) */
37406 {
37411 }
37412 else
37416 {
37419 {
37426 UNSPEC_TRUNC_NOOP)));
37427 }
37443 }
37445 /* flags = signbit(a) */
37448 /* if (flags) then res = -res */
37452 pc_rtx);
37463 }
37465 /* Output code to perform a Newton-Rhapson approximation of a single precision
37466 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37469 {
37477 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37481 /* x0 = rcp(b) estimate */
37484 UNSPEC_RCP)));
37485 /* e0 = x0 * b */
37489 /* e0 = x0 * e0 */
37493 /* e1 = x0 + x0 */
37497 /* x1 = e1 - e0 */
37501 /* res = a * x1 */
37504 }
37506 /* Output code to perform a Newton-Rhapson approximation of a
37507 single precision floating point [reciprocal] square root. */
37511 {
37513 REAL_VALUE_TYPE r;
37528 {
37531 }
37533 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37534 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37538 /* x0 = rsqrt(a) estimate */
37541 UNSPEC_RSQRT)));
37543 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37545 {
37557 }
37559 /* e0 = x0 * a */
37562 /* e1 = e0 * x0 */
37566 /* e2 = e1 - 3. */
37573 /* e3 = -.5 * x0 */
37576 else
37577 /* e3 = -.5 * e0 */
37580 /* ret = e2 * e3 */
37583 }
37585 #ifdef TARGET_SOLARIS
37586 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37588 static void
37590 tree decl)
37591 {
37592 /* With Binutils 2.15, the "@unwind" marker must be specified on
37593 every occurrence of the ".eh_frame" section, not just the first
37594 one. */
37597 {
37601 }
37603 #ifndef USE_GAS
37605 {
37608 }
37609 #endif
37612 }
37615 /* Return the mangling of TYPE if it is an extended fundamental type. */
37619 {
37627 {
37629 /* __float128 is "g". */
37632 /* "long double" or __float80 is "e". */
37636 }
37637 }
37639 /* For 32-bit code we can save PIC register setup by using
37640 __stack_chk_fail_local hidden function instead of calling
37641 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37642 register, so it is better to call __stack_chk_fail directly. */
37644 static tree ATTRIBUTE_UNUSED
37646 {
37647 return TARGET_64BIT
37650 }
37652 /* Select a format to encode pointers in exception handling data. CODE
37653 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37654 true if the symbol may be affected by dynamic relocations.
37656 ??? All x86 object file formats are capable of representing this.
37657 After all, the relocation needed is the same as for the call insn.
37658 Whether or not a particular assembler allows us to enter such, I
37659 guess we'll have to see. */
37660 int
37662 {
37664 {
37671 }
37676 }
37677 \f
37678 /* Expand copysign from SIGN to the positive value ABS_VALUE
37679 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37680 the sign-bit. */
37681 static void
37683 {
37687 {
37694 else
37699 {
37700 /* We need to generate a scalar mode mask in this case. */
37705 }
37706 }
37707 else
37713 }
37715 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37716 mask for masking out the sign-bit is stored in *SMASK, if that is
37717 non-null. */
37718 static rtx
37720 {
37729 else
37733 {
37734 /* We need to generate a scalar mode mask in this case. */
37739 }
37747 }
37749 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37750 swapping the operands if SWAP_OPERANDS is true. The expanded
37751 code is a forward jump to a newly created label in case the
37752 comparison is true. The generated label rtx is returned. */
37753 static rtx
37756 {
37760 {
37764 }
37777 }
37779 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37780 using comparison code CODE. Operands are swapped for the comparison if
37781 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37782 static rtx
37785 {
37791 {
37795 }
37802 }
37804 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37805 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37806 static rtx
37808 {
37809 REAL_VALUE_TYPE TWO52r;
37810 rtx TWO52;
37817 }
37819 /* Expand SSE sequence for computing lround from OP1 storing
37820 into OP0. */
37821 void
37823 {
37824 /* C code for the stuff we're doing below:
37825 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37826 return (long)tmp;
37827 */
37831 rtx adj;
37833 /* load nextafter (0.5, 0.0) */
37838 /* adj = copysign (0.5, op1) */
37842 /* adj = op1 + adj */
37845 /* op0 = (imode)adj */
37847 }
37849 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37850 into OPERAND0. */
37851 void
37853 {
37854 /* C code for the stuff we're doing below (for do_floor):
37855 xi = (long)op1;
37856 xi -= (double)xi > op1 ? 1 : 0;
37857 return xi;
37858 */
37863 /* reg = (long)op1 */
37867 /* freg = (double)reg */
37871 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37882 }
37884 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37885 result in OPERAND0. */
37886 void
37888 {
37889 /* C code for the stuff we're doing below:
37890 xa = fabs (operand1);
37891 if (!isless (xa, 2**52))
37892 return operand1;
37893 xa = xa + 2**52 - 2**52;
37894 return copysign (xa, operand1);
37895 */
37902 /* xa = abs (operand1) */
37905 /* if (!isless (xa, TWO52)) goto label; */
37918 }
37920 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37921 into OPERAND0. */
37922 void
37924 {
37925 /* C code for the stuff we expand below.
37926 double xa = fabs (x), x2;
37927 if (!isless (xa, TWO52))
37928 return x;
37929 xa = xa + TWO52 - TWO52;
37930 x2 = copysign (xa, x);
37931 Compensate. Floor:
37932 if (x2 > x)
37933 x2 -= 1;
37934 Compensate. Ceil:
37935 if (x2 < x)
37936 x2 -= -1;
37937 return x2;
37938 */
37944 /* Temporary for holding the result, initialized to the input
37945 operand to ease control flow. */
37949 /* xa = abs (operand1) */
37952 /* if (!isless (xa, TWO52)) goto label; */
37955 /* xa = xa + TWO52 - TWO52; */
37959 /* xa = copysign (xa, operand1) */
37962 /* generate 1.0 or -1.0 */
37967 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37971 /* We always need to subtract here to preserve signed zero. */
37980 }
37982 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37983 into OPERAND0. */
37984 void
37986 {
37987 /* C code for the stuff we expand below.
37988 double xa = fabs (x), x2;
37989 if (!isless (xa, TWO52))
37990 return x;
37991 x2 = (double)(long)x;
37992 Compensate. Floor:
37993 if (x2 > x)
37994 x2 -= 1;
37995 Compensate. Ceil:
37996 if (x2 < x)
37997 x2 += 1;
37998 if (HONOR_SIGNED_ZEROS (mode))
37999 return copysign (x2, x);
38000 return x2;
38001 */
38007 /* Temporary for holding the result, initialized to the input
38008 operand to ease control flow. */
38012 /* xa = abs (operand1) */
38015 /* if (!isless (xa, TWO52)) goto label; */
38018 /* xa = (double)(long)x */
38023 /* generate 1.0 */
38026 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38041 }
38043 /* Expand SSE sequence for computing round from OPERAND1 storing
38044 into OPERAND0. Sequence that works without relying on DImode truncation
38045 via cvttsd2siq that is only available on 64bit targets. */
38046 void
38048 {
38049 /* C code for the stuff we expand below.
38050 double xa = fabs (x), xa2, x2;
38051 if (!isless (xa, TWO52))
38052 return x;
38053 Using the absolute value and copying back sign makes
38054 -0.0 -> -0.0 correct.
38055 xa2 = xa + TWO52 - TWO52;
38056 Compensate.
38057 dxa = xa2 - xa;
38058 if (dxa <= -0.5)
38059 xa2 += 1;
38060 else if (dxa > 0.5)
38061 xa2 -= 1;
38062 x2 = copysign (xa2, x);
38063 return x2;
38064 */
38070 /* Temporary for holding the result, initialized to the input
38071 operand to ease control flow. */
38075 /* xa = abs (operand1) */
38078 /* if (!isless (xa, TWO52)) goto label; */
38081 /* xa2 = xa + TWO52 - TWO52; */
38085 /* dxa = xa2 - xa; */
38088 /* generate 0.5, 1.0 and -0.5 */
38094 /* Compensate. */
38096 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
38101 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
38107 /* res = copysign (xa2, operand1) */
38114 }
38116 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38117 into OPERAND0. */
38118 void
38120 {
38121 /* C code for SSE variant we expand below.
38122 double xa = fabs (x), x2;
38123 if (!isless (xa, TWO52))
38124 return x;
38125 x2 = (double)(long)x;
38126 if (HONOR_SIGNED_ZEROS (mode))
38127 return copysign (x2, x);
38128 return x2;
38129 */
38135 /* Temporary for holding the result, initialized to the input
38136 operand to ease control flow. */
38140 /* xa = abs (operand1) */
38143 /* if (!isless (xa, TWO52)) goto label; */
38146 /* x = (double)(long)x */
38158 }
38160 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38161 into OPERAND0. */
38162 void
38164 {
38168 /* C code for SSE variant we expand below.
38169 double xa = fabs (x), x2;
38170 if (!isless (xa, TWO52))
38171 return x;
38172 xa2 = xa + TWO52 - TWO52;
38173 Compensate:
38174 if (xa2 > xa)
38175 xa2 -= 1.0;
38176 x2 = copysign (xa2, x);
38177 return x2;
38178 */
38182 /* Temporary for holding the result, initialized to the input
38183 operand to ease control flow. */
38187 /* xa = abs (operand1) */
38190 /* if (!isless (xa, TWO52)) goto label; */
38193 /* res = xa + TWO52 - TWO52; */
38198 /* generate 1.0 */
38201 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38209 /* res = copysign (res, operand1) */
38216 }
38218 /* Expand SSE sequence for computing round from OPERAND1 storing
38219 into OPERAND0. */
38220 void
38222 {
38223 /* C code for the stuff we're doing below:
38224 double xa = fabs (x);
38225 if (!isless (xa, TWO52))
38226 return x;
38227 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38228 return copysign (xa, x);
38229 */
38235 /* Temporary for holding the result, initialized to the input
38236 operand to ease control flow. */
38244 /* load nextafter (0.5, 0.0) */
38249 /* xa = xa + 0.5 */
38253 /* xa = (double)(int64_t)xa */
38258 /* res = copysign (xa, operand1) */
38265 }
38267 /* Expand SSE sequence for computing round
38268 from OP1 storing into OP0 using sse4 round insn. */
38269 void
38271 {
38280 {
38291 }
38293 /* round (a) = trunc (a + copysign (0.5, a)) */
38295 /* load nextafter (0.5, 0.0) */
38301 /* e1 = copysign (0.5, op1) */
38305 /* e2 = op1 + e1 */
38308 /* res = trunc (e2) */
38313 }
38314 \f
38316 /* Table of valid machine attributes. */
38318 {
38319 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38320 affects_type_identity } */
38321 /* Stdcall attribute says callee is responsible for popping arguments
38322 if they are not variable. */
38325 /* Fastcall attribute says callee is responsible for popping arguments
38326 if they are not variable. */
38329 /* Thiscall attribute says callee is responsible for popping arguments
38330 if they are not variable. */
38333 /* Cdecl attribute says the callee is a normal C declaration */
38336 /* Regparm attribute specifies how many integer arguments are to be
38337 passed in registers. */
38340 /* Sseregparm attribute says we are using x86_64 calling conventions
38341 for FP arguments. */
38344 /* The transactional memory builtins are implicitly regparm or fastcall
38345 depending on the ABI. Override the generic do-nothing attribute that
38346 these builtins were declared with. */
38349 /* force_align_arg_pointer says this function realigns the stack at entry. */
38352 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38357 #endif
38362 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38363 SUBTARGET_ATTRIBUTE_TABLE,
38364 #endif
38365 /* ms_abi and sysv_abi calling convention function attributes. */
38372 /* End element. */
38374 };
38376 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38377 static int
38379 tree vectype,
38381 {
38385 {
38430 }
38431 }
38433 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38434 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38435 insn every time. */
38439 /* Initialize vselect_insn. */
38441 static void
38443 {
38445 rtx x;
38456 }
38458 /* Construct (set target (vec_select op0 (parallel perm))) and
38459 return true if that's a valid instruction in the active ISA. */
38461 static bool
38464 {
38490 }
38492 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38494 static bool
38498 {
38500 rtx x;
38515 }
38517 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38518 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38520 static bool
38522 {
38531 ;
38533 ;
38535 ;
38536 else
38539 /* This is a blend, not a permute. Elements must stay in their
38540 respective lanes. */
38542 {
38546 }
38551 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38552 decision should be extracted elsewhere, so that we only try that
38553 sequence once all budget==3 options have been tried. */
38560 {
38584 /* See if bytes move in pairs so we can use pblendw with
38585 an immediate argument, rather than pblendvb with a vector
38586 argument. */
38589 {
38590 use_pblendvb:
38594 finish_pblendvb:
38600 else
38603 }
38608 /* FALLTHRU */
38610 do_subreg:
38617 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38621 /* See if bytes move in quadruplets. If yes, vpblendd
38622 with immediate can be used. */
38627 {
38628 /* See if bytes move the same in both lanes. If yes,
38629 vpblendw with immediate can be used. */
38634 /* Use vpblendw. */
38639 }
38641 /* Use vpblendd. */
38648 /* See if words move in pairs. If yes, vpblendd can be used. */
38653 {
38654 /* See if words move the same in both lanes. If not,
38655 vpblendvb must be used. */
38658 {
38659 /* Use vpblendvb. */
38669 }
38671 /* Use vpblendw. */
38675 }
38677 /* Use vpblendd. */
38684 /* Use vpblendd. */
38692 }
38694 /* This matches five different patterns with the different modes. */
38700 }
38702 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38703 in terms of the variable form of vpermilps.
38705 Note that we will have already failed the immediate input vpermilps,
38706 which requires that the high and low part shuffle be identical; the
38707 variable form doesn't require that. */
38709 static bool
38711 {
38718 /* We can only permute within the 128-bit lane. */
38720 {
38724 }
38730 {
38733 /* Within each 128-bit lane, the elements of op0 are numbered
38734 from 0 and the elements of op1 are numbered from 4. */
38741 }
38748 }
38750 /* Return true if permutation D can be performed as VMODE permutation
38751 instead. */
38753 static bool
38755 {
38770 else
38776 }
38778 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38779 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38781 static bool
38783 {
38792 {
38794 {
38797 {
38801 /* Use vperm2i128 insn. The pattern uses
38802 V4DImode instead of V2TImode. */
38811 }
38813 }
38814 }
38815 else
38816 {
38818 {
38821 }
38823 {
38827 /* V4DImode should be already handled through
38828 expand_vselect by vpermq instruction. */
38835 {
38836 /* First see if vpermq can be used for
38837 V8SImode/V16HImode/V32QImode. */
38839 {
38847 }
38849 /* Next see if vpermd can be used. */
38852 }
38853 /* Or if vpermps can be used. */
38858 {
38859 /* vpshufb only works intra lanes, it is not
38860 possible to shuffle bytes in between the lanes. */
38864 }
38865 }
38866 else
38868 }
38876 else
38877 {
38883 else
38887 {
38891 }
38892 }
38901 {
38908 else
38910 }
38911 else
38912 {
38915 }
38918 }
38920 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38921 in a single instruction. */
38923 static bool
38925 {
38929 /* Check plain VEC_SELECT first, because AVX has instructions that could
38930 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38931 input where SEL+CONCAT may not. */
38933 {
38939 {
38945 }
38948 {
38952 }
38954 {
38955 /* Use vpbroadcast{b,w,d}. */
38958 {
38977 /* For other modes prefer other shuffles this function creates. */
38979 }
38981 {
38985 }
38986 }
38991 /* There are plenty of patterns in sse.md that are written for
38992 SEL+CONCAT and are not replicated for a single op. Perhaps
38993 that should be changed, to avoid the nastiness here. */
38995 /* Recognize interleave style patterns, which means incrementing
38996 every other permutation operand. */
38998 {
39001 }
39006 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
39008 {
39010 {
39015 }
39020 }
39021 }
39023 /* Finally, try the fully general two operand permute. */
39028 /* Recognize interleave style patterns with reversed operands. */
39030 {
39032 {
39036 else
39039 }
39044 }
39046 /* Try the SSE4.1 blend variable merge instructions. */
39050 /* Try one of the AVX vpermil variable permutations. */
39054 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
39055 vpshufb, vpermd, vpermps or vpermq variable permutation. */
39060 }
39062 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39063 in terms of a pair of pshuflw + pshufhw instructions. */
39065 static bool
39067 {
39075 /* The two permutations only operate in 64-bit lanes. */
39086 /* Emit the pshuflw. */
39093 /* Emit the pshufhw. */
39101 }
39103 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39104 the permutation using the SSSE3 palignr instruction. This succeeds
39105 when all of the elements in PERM fit within one vector and we merely
39106 need to shift them down so that a single vector permutation has a
39107 chance to succeed. */
39109 static bool
39111 {
39115 rtx shift;
39117 /* Even with AVX, palignr only operates on 128-bit vectors. */
39123 {
39129 }
39133 /* Given that we have SSSE3, we know we'll be able to implement the
39134 single operand permutation after the palignr with pshufb. */
39148 {
39153 }
39155 /* Test for the degenerate case where the alignment by itself
39156 produces the desired permutation. */
39164 }
39168 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39169 a two vector permutation into a single vector permutation by using
39170 an interleave operation to merge the vectors. */
39172 static bool
39174 {
39179 rtx seq;
39183 {
39186 }
39188 {
39191 /* For 32-byte modes allow even d->one_operand_p.
39192 The lack of cross-lane shuffling in some instructions
39193 might prevent a single insn shuffle. */
39196 /* If expand_vec_perm_interleave3 can expand this into
39197 a 3 insn sequence, give up and let it be expanded as
39198 3 insn sequence. While that is one insn longer,
39199 it doesn't need a memory operand and in the common
39200 case that both interleave low and high permutations
39201 with the same operands are adjacent needs 4 insns
39202 for both after CSE. */
39205 }
39206 else
39209 /* Examine from whence the elements come. */
39218 {
39221 /* Split the two input vectors into 4 halves. */
39227 /* If the elements from the low halves use interleave low, and similarly
39228 for interleave high. If the elements are from mis-matched halves, we
39229 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39231 {
39232 /* punpckl* */
39234 {
39239 }
39242 }
39244 {
39245 /* punpckh* */
39247 {
39252 }
39255 }
39257 {
39258 /* shufps */
39260 {
39265 }
39267 {
39268 /* shufpd */
39273 }
39274 }
39276 {
39277 /* shufps */
39279 {
39284 }
39286 {
39287 /* shufpd */
39292 }
39293 }
39294 else
39296 }
39297 else
39298 {
39303 /* Split the two input vectors into 8 quarters. */
39309 {
39312 }
39315 {
39319 }
39321 {
39324 }
39327 {
39329 {
39330 /* Attempt to increase the likelihood that dfinal
39331 shuffle will be intra-lane. */
39335 }
39337 /* vperm2f128 or vperm2i128. */
39339 {
39344 }
39349 {
39353 {
39356 }
39357 }
39358 }
39363 {
39364 /* vpunpckl* */
39366 {
39375 }
39376 }
39379 {
39380 /* vpunpckh* */
39382 {
39391 }
39392 }
39393 else
39395 }
39397 /* Use the remapping array set up above to move the elements from their
39398 swizzled locations into their final destinations. */
39401 {
39404 /* If same_halves is true, both halves of the remapped vector are the
39405 same. Avoid cross-lane accesses if possible. */
39407 {
39410 }
39411 else
39413 }
39419 /* Test if the final remap can be done with a single insn. For V4SFmode or
39420 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39433 {
39437 }
39444 }
39446 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39447 a single vector cross-lane permutation into vpermq followed
39448 by any of the single insn permutations. */
39450 static bool
39452 {
39466 {
39469 }
39472 {
39477 }
39490 {
39497 }
39504 {
39509 ;
39512 else
39514 }
39523 }
39525 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39526 a vector permutation using two instructions, vperm2f128 resp.
39527 vperm2i128 followed by any single in-lane permutation. */
39529 static bool
39531 {
39545 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39546 immediate. For perm < 16 the second permutation uses
39547 d->op0 as first operand, for perm >= 16 it uses d->op1
39548 as first operand. The second operand is the result of
39549 vperm2[fi]128. */
39551 {
39552 /* Ignore permutations which do not move anything cross-lane. */
39554 {
39555 /* The second shuffle for e.g. V4DFmode has
39556 0123 and ABCD operands.
39557 Ignore AB23, as 23 is already in the second lane
39558 of the first operand. */
39560 /* And 01CD, as 01 is in the first lane of the first
39561 operand. */
39563 /* And 4567, as then the vperm2[fi]128 doesn't change
39564 anything on the original 4567 second operand. */
39566 }
39567 else
39568 {
39569 /* The second shuffle for e.g. V4DFmode has
39570 4567 and ABCD operands.
39571 Ignore AB67, as 67 is already in the second lane
39572 of the first operand. */
39574 /* And 45CD, as 45 is in the first lane of the first
39575 operand. */
39577 /* And 0123, as then the vperm2[fi]128 doesn't change
39578 anything on the original 0123 first operand. */
39580 }
39583 {
39589 else
39591 }
39594 {
39598 }
39599 else
39603 {
39607 /* Found a usable second shuffle. dfirst will be
39608 vperm2f128 on d->op0 and d->op1. */
39619 /* And dsecond is some single insn shuffle, taking
39620 d->op0 and result of vperm2f128 (if perm < 16) or
39621 d->op1 and result of vperm2f128 (otherwise). */
39630 }
39632 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39635 }
39638 }
39640 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39641 a two vector permutation using 2 intra-lane interleave insns
39642 and cross-lane shuffle for 32-byte vectors. */
39644 static bool
39646 {
39653 ;
39655 ;
39656 else
39671 {
39675 else
39681 else
39687 else
39693 else
39699 else
39705 else
39710 }
39714 }
39716 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39717 a single vector permutation using a single intra-lane vector
39718 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39719 the non-swapped and swapped vectors together. */
39721 static bool
39723 {
39726 rtx seq;
39731 || TARGET_AVX2
39740 {
39747 }
39782 }
39784 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39785 permutation using two vperm2f128, followed by a vshufpd insn blending
39786 the two vectors together. */
39788 static bool
39790 {
39833 }
39835 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39836 permutation with two pshufb insns and an ior. We should have already
39837 failed all two instruction sequences. */
39839 static bool
39841 {
39852 /* Generate two permutation masks. If the required element is within
39853 the given vector it is shuffled into the proper lane. If the required
39854 element is in the other vector, force a zero into the lane by setting
39855 bit 7 in the permutation mask. */
39858 {
39865 {
39868 }
39869 }
39889 }
39891 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39892 with two vpshufb insns, vpermq and vpor. We should have already failed
39893 all two or three instruction sequences. */
39895 static bool
39897 {
39912 /* Generate two permutation masks. If the required element is within
39913 the same lane, it is shuffled in. If the required element from the
39914 other lane, force a zero by setting bit 7 in the permutation mask.
39915 In the other mask the mask has non-negative elements if element
39916 is requested from the other lane, but also moved to the other lane,
39917 so that the result of vpshufb can have the two V2TImode halves
39918 swapped. */
39921 {
39926 {
39929 }
39930 }
39939 /* Swap the 128-byte lanes of h into hp. */
39943 const1_rtx));
39956 }
39958 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39959 and extract-odd permutations of two V32QImode and V16QImode operand
39960 with two vpshufb insns, vpor and vpermq. We should have already
39961 failed all two or three instruction sequences. */
39963 static bool
39965 {
39984 /* Generate two permutation masks. In the first permutation mask
39985 the first quarter will contain indexes for the first half
39986 of the op0, the second quarter will contain bit 7 set, third quarter
39987 will contain indexes for the second half of the op0 and the
39988 last quarter bit 7 set. In the second permutation mask
39989 the first quarter will contain bit 7 set, the second quarter
39990 indexes for the first half of the op1, the third quarter bit 7 set
39991 and last quarter indexes for the second half of the op1.
39992 I.e. the first mask e.g. for V32QImode extract even will be:
39993 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39994 (all values masked with 0xf except for -128) and second mask
39995 for extract even will be
39996 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39999 {
40005 {
40008 }
40009 }
40028 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
40035 }
40037 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
40038 and extract-odd permutations. */
40040 static bool
40042 {
40046 {
40051 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40055 /* Now an unpck[lh]pd will produce the result required. */
40058 else
40064 {
40071 /* Shuffle within the 128-bit lanes to produce:
40072 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
40076 /* Shuffle the lanes around to produce:
40077 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
40081 /* Shuffle within the 128-bit lanes to produce:
40082 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
40085 /* Shuffle within the 128-bit lanes to produce:
40086 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
40089 /* Shuffle the lanes around to produce:
40090 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
40093 }
40100 /* These are always directly implementable by expand_vec_perm_1. */
40106 else
40107 {
40108 /* We need 2*log2(N)-1 operations to achieve odd/even
40109 with interleave. */
40118 else
40121 }
40127 else
40128 {
40140 else
40143 }
40152 {
40159 }
40164 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40168 /* Now an vpunpck[lh]qdq will produce the result required. */
40171 else
40178 {
40185 }
40190 /* Shuffle the lanes around into
40191 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40201 /* Swap the 2nd and 3rd position in each lane into
40202 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40208 /* Now an vpunpck[lh]qdq will produce
40209 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40214 else
40223 }
40226 }
40228 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40229 extract-even and extract-odd permutations. */
40231 static bool
40233 {
40245 }
40247 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40248 permutations. We assume that expand_vec_perm_1 has already failed. */
40250 static bool
40252 {
40260 {
40263 /* These are special-cased in sse.md so that we can optionally
40264 use the vbroadcast instruction. They expand to two insns
40265 if the input happens to be in a register. */
40272 /* These are always implementable using standard shuffle patterns. */
40277 /* These can be implemented via interleave. We save one insn by
40278 stopping once we have promoted to V4SImode and then use pshufd. */
40279 do
40280 {
40281 rtx dest;
40287 {
40291 }
40298 }
40311 /* For AVX2 broadcasts of the first element vpbroadcast* or
40312 vpermq should be used by expand_vec_perm_1. */
40318 }
40319 }
40321 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40322 broadcast permutations. */
40324 static bool
40326 {
40338 }
40340 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40341 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40342 all the shorter instruction sequences. */
40344 static bool
40346 {
40362 /* Generate 4 permutation masks. If the required element is within
40363 the same lane, it is shuffled in. If the required element from the
40364 other lane, force a zero by setting bit 7 in the permutation mask.
40365 In the other mask the mask has non-negative elements if element
40366 is requested from the other lane, but also moved to the other lane,
40367 so that the result of vpshufb can have the two V2TImode halves
40368 swapped. */
40371 {
40376 }
40382 {
40390 }
40393 {
40395 {
40398 }
40405 }
40407 /* Swap the 128-byte lanes of h[X]. */
40409 {
40415 const1_rtx));
40417 }
40420 {
40422 {
40425 }
40431 }
40434 {
40436 {
40440 }
40443 }
40449 }
40451 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40452 With all of the interface bits taken care of, perform the expansion
40453 in D and return true on success. */
40455 static bool
40457 {
40458 /* Try a single instruction expansion. */
40462 /* Try sequences of two instructions. */
40482 /* Try sequences of three instructions. */
40496 /* Try sequences of four instructions. */
40504 /* ??? Look for narrow permutations whose element orderings would
40505 allow the promotion to a wider mode. */
40507 /* ??? Look for sequences of interleave or a wider permute that place
40508 the data into the correct lanes for a half-vector shuffle like
40509 pshuf[lh]w or vpermilps. */
40511 /* ??? Look for sequences of interleave that produce the desired results.
40512 The combinatorics of punpck[lh] get pretty ugly... */
40517 /* Even longer sequences. */
40522 }
40524 /* If a permutation only uses one operand, make it clear. Returns true
40525 if the permutation references both operands. */
40527 static bool
40529 {
40537 {
40543 {
40546 }
40547 /* The elements of PERM do not suggest that only the first operand
40548 is used, but both operands are identical. Allow easier matching
40549 of the permutation by folding the permutation into the single
40550 input vector. */
40551 /* FALLTHRU */
40562 }
40565 }
40567 bool
40569 {
40574 rtx sel;
40591 {
40596 }
40603 /* If the selector says both arguments are needed, but the operands are the
40604 same, the above tried to expand with one_operand_p and flattened selector.
40605 If that didn't work, retry without one_operand_p; we succeeded with that
40606 during testing. */
40608 {
40612 }
40615 }
40617 /* Implement targetm.vectorize.vec_perm_const_ok. */
40619 static bool
40622 {
40631 /* Given sufficient ISA support we can just return true here
40632 for selected vector modes. */
40634 {
40635 /* All implementable with a single vpperm insn. */
40638 /* All implementable with 2 pshufb + 1 ior. */
40641 /* All implementable with shufpd or unpck[lh]pd. */
40644 }
40646 /* Extract the values from the vector CST into the permutation
40647 array in D. */
40650 {
40654 }
40656 /* For all elements from second vector, fold the elements to first. */
40661 /* Check whether the mask can be applied to the vector type. */
40664 /* Implementable with shufps or pshufd. */
40668 /* Otherwise we have to go through the motions and see if we can
40669 figure out how to generate the requested permutation. */
40680 }
40682 void
40684 {
40699 /* We'll either be able to implement the permutation directly... */
40703 /* ... or we use the special-case patterns. */
40705 }
40707 static void
40709 {
40724 {
40727 }
40729 /* Note that for AVX this isn't one instruction. */
40732 }
40735 /* Expand a vector operation CODE for a V*QImode in terms of the
40736 same operation on V*HImode. */
40738 void
40740 {
40752 {
40765 }
40769 {
40771 /* Unpack data such that we've got a source byte in each low byte of
40772 each word. We don't care what goes into the high byte of each word.
40773 Rather than trying to get zero in there, most convenient is to let
40774 it be a copy of the low byte. */
40779 /* FALLTHRU */
40791 /* FALLTHRU */
40801 }
40803 /* Perform the operation. */
40810 /* Merge the data back into the right place. */
40820 {
40821 /* For SSE2, we used an full interleave, so the desired
40822 results are in the even elements. */
40825 }
40826 else
40827 {
40828 /* For AVX, the interleave used above was not cross-lane. So the
40829 extraction is evens but with the second and third quarter swapped.
40830 Happily, that is even one insn shorter than even extraction. */
40833 }
40840 }
40842 void
40845 {
40848 rtx x;
40850 /* We only play even/odd games with vectors of SImode. */
40853 /* If we're looking for the odd results, shift those members down to
40854 the even slots. For some cpus this is faster than a PSHUFD. */
40856 {
40857 /* For XOP use vpmacsdqh, but only for smult, as it is only
40858 signed. */
40860 {
40864 }
40873 }
40876 {
40879 else
40881 }
40886 else
40887 {
40890 /* The easiest way to implement this without PMULDQ is to go through
40891 the motions as if we are performing a full 64-bit multiply. With
40892 the exception that we need to do less shuffling of the elements. */
40894 /* Compute the sign-extension, aka highparts, of the two operands. */
40900 /* Multiply LO(A) * HI(B), and vice-versa. */
40906 /* Multiply LO(A) * LO(B). */
40910 /* Combine and shift the highparts into place. */
40915 /* Combine high and low parts. */
40918 }
40920 }
40922 void
40925 {
40931 {
40936 {
40937 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40938 shuffle the elements once so that all elements are in the right
40939 place for immediate use: { A C B D }. */
40944 }
40945 else
40946 {
40947 /* Put the elements into place for the multiply. */
40951 }
40956 /* Shuffle the elements between the lanes. After this we
40957 have { A B E F | C D G H } for each operand. */
40967 /* Shuffle the elements within the lanes. After this we
40968 have { A A B B | C C D D } or { E E F F | G G H H }. */
41004 }
41005 }
41007 void
41009 {
41019 /* Move the results in element 2 down to element 1; we don't care
41020 what goes in elements 2 and 3. Then we can merge the parts
41021 back together with an interleave.
41023 Note that two other sequences were tried:
41024 (1) Use interleaves at the start instead of psrldq, which allows
41025 us to use a single shufps to merge things back at the end.
41026 (2) Use shufps here to combine the two vectors, then pshufd to
41027 put the elements in the correct order.
41028 In both cases the cost of the reformatting stall was too high
41029 and the overall sequence slower. */
41038 }
41040 void
41042 {
41047 {
41048 /* op1: A,B,C,D, op2: E,F,G,H */
41057 /* t1: B,A,D,C */
41064 /* t2: (B*E),(A*F),(D*G),(C*H) */
41067 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
41070 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
41073 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
41075 }
41076 else
41077 {
41082 {
41085 }
41087 {
41090 }
41091 else
41095 /* Multiply low parts. */
41099 /* Shift input vectors right 32 bits so we can multiply high parts. */
41104 /* Multiply high parts by low parts. */
41110 /* Combine and shift the highparts back. */
41114 /* Combine high and low parts. */
41116 }
41120 }
41122 /* Expand an insert into a vector register through pinsr insn.
41123 Return true if successful. */
41125 bool
41127 {
41135 {
41138 }
41144 {
41149 {
41156 {
41188 }
41197 }
41201 }
41202 }
41203 \f
41204 /* This function returns the calling abi specific va_list type node.
41205 It returns the FNDECL specific va_list type. */
41207 static tree
41209 {
41216 else
41218 }
41220 /* Returns the canonical va_list type specified by TYPE. If there
41221 is no valid TYPE provided, it return NULL_TREE. */
41223 static tree
41225 {
41228 /* Resolve references and pointers to va_list type. */
41237 {
41242 {
41243 /* If va_list is an array type, the argument may have decayed
41244 to a pointer type, e.g. by being passed to another function.
41245 In that case, unwrap both types so that we can compare the
41246 underlying records. */
41249 {
41252 }
41253 }
41260 {
41261 /* If va_list is an array type, the argument may have decayed
41262 to a pointer type, e.g. by being passed to another function.
41263 In that case, unwrap both types so that we can compare the
41264 underlying records. */
41267 {
41270 }
41271 }
41278 {
41279 /* If va_list is an array type, the argument may have decayed
41280 to a pointer type, e.g. by being passed to another function.
41281 In that case, unwrap both types so that we can compare the
41282 underlying records. */
41285 {
41288 }
41289 }
41293 }
41295 }
41297 /* Iterate through the target-specific builtin types for va_list.
41298 IDX denotes the iterator, *PTREE is set to the result type of
41299 the va_list builtin, and *PNAME to its internal type.
41300 Returns zero if there is no element for this index, otherwise
41301 IDX should be increased upon the next call.
41302 Note, do not iterate a base builtin's name like __builtin_va_list.
41303 Used from c_common_nodes_and_builtins. */
41305 static int
41307 {
41309 {
41311 {
41324 }
41325 }
41328 }
41330 #undef TARGET_SCHED_DISPATCH
41331 #define TARGET_SCHED_DISPATCH has_dispatch
41332 #undef TARGET_SCHED_DISPATCH_DO
41333 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41334 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41335 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41336 #undef TARGET_SCHED_REORDER
41337 #define TARGET_SCHED_REORDER ix86_sched_reorder
41338 #undef TARGET_SCHED_ADJUST_PRIORITY
41339 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41340 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41341 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
41342 ix86_dependencies_evaluation_hook
41344 /* The size of the dispatch window is the total number of bytes of
41345 object code allowed in a window. */
41346 #define DISPATCH_WINDOW_SIZE 16
41348 /* Number of dispatch windows considered for scheduling. */
41349 #define MAX_DISPATCH_WINDOWS 3
41351 /* Maximum number of instructions in a window. */
41352 #define MAX_INSN 4
41354 /* Maximum number of immediate operands in a window. */
41355 #define MAX_IMM 4
41357 /* Maximum number of immediate bits allowed in a window. */
41358 #define MAX_IMM_SIZE 128
41360 /* Maximum number of 32 bit immediates allowed in a window. */
41361 #define MAX_IMM_32 4
41363 /* Maximum number of 64 bit immediates allowed in a window. */
41364 #define MAX_IMM_64 2
41366 /* Maximum total of loads or prefetches allowed in a window. */
41367 #define MAX_LOAD 2
41369 /* Maximum total of stores allowed in a window. */
41370 #define MAX_STORE 1
41372 #undef BIG
41373 #define BIG 100
41376 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41379 disp_load,
41380 disp_store,
41381 disp_load_store,
41382 disp_prefetch,
41383 disp_imm,
41384 disp_imm_32,
41385 disp_imm_64,
41386 disp_branch,
41387 disp_cmp,
41388 disp_jcc,
41389 disp_last
41390 };
41392 /* Number of allowable groups in a dispatch window. It is an array
41393 indexed by dispatch_group enum. 100 is used as a big number,
41394 because the number of these kind of operations does not have any
41395 effect in dispatch window, but we need them for other reasons in
41396 the table. */
41399 };
41405 };
41407 /* Instruction path. */
41413 last_path
41414 };
41416 /* sched_insn_info defines a window to the instructions scheduled in
41417 the basic block. It contains a pointer to the insn_info table and
41418 the instruction scheduled.
41420 Windows are allocated for each basic block and are linked
41421 together. */
41423 rtx insn;
41430 /* Linked list of dispatch windows. This is a two way list of
41431 dispatch windows of a basic block. It contains information about
41432 the number of uops in the window and the total number of
41433 instructions and of bytes in the object code for this dispatch
41434 window. */
41452 /* Immediate valuse used in an insn. */
41454 {
41463 /* Get dispatch group of insn. */
41465 static enum dispatch_group
41467 {
41483 }
41485 /* Return true if insn is a compare instruction. */
41487 static bool
41489 {
41497 }
41499 /* Return true if a dispatch violation encountered. */
41501 static bool
41503 {
41507 }
41509 /* Return true if insn is a branch instruction. */
41511 static bool
41513 {
41515 }
41517 /* Return true if insn is a prefetch instruction. */
41519 static bool
41521 {
41523 }
41525 /* This function initializes a dispatch window and the list container holding a
41526 pointer to the window. */
41528 static void
41530 {
41536 else
41554 {
41560 }
41562 }
41564 /* This function allocates and initializes a dispatch window and the
41565 list container holding a pointer to the window. */
41569 {
41574 }
41576 /* This routine initializes the dispatch scheduling information. It
41577 initiates building dispatch scheduler tables and constructs the
41578 first dispatch window. */
41580 static void
41582 {
41583 /* Allocate a dispatch list and a window. */
41588 }
41590 /* This function returns true if a branch is detected. End of a basic block
41591 does not have to be a branch, but here we assume only branches end a
41592 window. */
41594 static bool
41596 {
41598 }
41600 /* This function is called when the end of a window processing is reached. */
41602 static void
41604 {
41607 {
41612 }
41614 }
41616 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41617 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41618 for 48 bytes of instructions. Note that these windows are not dispatch
41619 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41623 {
41625 {
41630 }
41636 }
41638 /* Increment the number of immediate operands of an instruction. */
41640 static int
41642 {
41647 {
41654 else
41665 {
41668 }
41673 }
41676 }
41678 /* Compute number of immediate operands of an instruction. */
41680 static void
41682 {
41685 }
41687 /* Return total size of immediate operands of an instruction along with number
41688 of corresponding immediate-operands. It initializes its parameters to zero
41689 befor calling FIND_CONSTANT.
41690 INSN is the input instruction. IMM is the total of immediates.
41691 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41692 bit immediates. */
41694 static int
41696 {
41704 }
41706 /* This function indicates if an operand of an instruction is an
41707 immediate. */
41709 static bool
41711 {
41720 }
41722 /* Return single or double path for instructions. */
41724 static enum insn_path
41726 {
41736 }
41738 /* Return insn dispatch group. */
41740 static enum dispatch_group
41742 {
41760 }
41762 /* Count number of GROUP restricted instructions in a dispatch
41763 window WINDOW_LIST. */
41765 static int
41767 {
41778 {
41797 }
41810 }
41812 /* This function returns true if insn satisfies dispatch rules on the
41813 last window scheduled. */
41815 static bool
41817 {
41825 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41826 instructions should be given the lowest priority in the
41827 scheduling process in Haifa scheduler to make sure they will be
41828 scheduled in the same dispatch window as the reference to them. */
41832 /* Check nonrestricted. */
41836 /* Get last dispatch window. */
41841 {
41846 /* Window 1 is full. Go for next window. */
41848 }
41855 /* See if it fits in the first window. */
41857 {
41858 /* The first widow should have only single and double path
41859 uops. */
41865 }
41867 }
41869 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41870 dispatch window WINDOW_LIST. */
41872 static void
41874 {
41892 /* Initialize window with new instruction. */
41913 {
41916 }
41917 }
41919 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41920 If the total bytes of instructions or the number of instructions in
41921 the window exceed allowable, it allocates a new window. */
41923 static void
41925 {
41948 /* Get the last dispatch window. */
41956 else
41959 /* If current window is full, get a new window.
41960 Window number zero is full, if MAX_INSN uops are scheduled in it.
41961 Window number one is full, if window zero's bytes plus window
41962 one's bytes is 32, or if the bytes of the new instruction added
41963 to the total makes it greater than 48, or it has already MAX_INSN
41964 instructions in it. */
41973 {
41976 }
41979 {
41983 {
41986 }
41987 }
41989 {
41994 {
41997 }
42000 }
42001 else
42005 {
42006 /* End of basic block is reached do end-basic-block process. */
42009 }
42010 }
42012 /* Print the dispatch window, WINDOW_NUM, to FILE. */
42014 DEBUG_FUNCTION static void
42016 {
42022 else
42036 {
42039 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
42045 }
42046 }
42048 /* Print to stdout a dispatch window. */
42050 DEBUG_FUNCTION void
42052 {
42054 }
42056 /* Print INSN dispatch information to FILE. */
42058 DEBUG_FUNCTION static void
42060 {
42083 }
42085 /* Print to STDERR the status of the ready list with respect to
42086 dispatch windows. */
42088 DEBUG_FUNCTION void
42090 {
42098 }
42100 /* This routine is the driver of the dispatch scheduler. */
42102 static void
42104 {
42109 }
42111 /* Return TRUE if Dispatch Scheduling is supported. */
42113 static bool
42115 {
42119 {
42135 }
42138 }
42140 /* Implementation of reassociation_width target hook used by
42141 reassoc phase to identify parallelism level in reassociated
42142 tree. Statements tree_code is passed in OPC. Arguments type
42143 is passed in MODE.
42145 Currently parallel reassociation is enabled for Atom
42146 processors only and we set reassociation width to be 2
42147 because Atom may issue up to 2 instructions per cycle.
42149 Return value should be fixed if parallel reassociation is
42150 enabled for other processors. */
42152 static int
42155 {
42164 }
42166 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42167 place emms and femms instructions. */
42169 static enum machine_mode
42171 {
42176 {
42189 else
42199 /* FALLTHRU */
42203 }
42204 }
42206 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42207 vectors. */
42209 static unsigned int
42211 {
42213 }
42215 \f
42217 /* Return class of registers which could be used for pseudo of MODE
42218 and of class RCLASS for spilling instead of memory. Return NO_REGS
42219 if it is not possible or non-profitable. */
42220 static reg_class_t
42222 {
42228 }
42230 /* Implement targetm.vectorize.init_cost. */
42234 {
42238 }
42240 /* Implement targetm.vectorize.add_stmt_cost. */
42242 static unsigned
42246 {
42253 /* Statements in an inner loop relative to the loop being
42254 vectorized are weighted more heavily. The value here is
42255 arbitrary and could potentially be improved with analysis. */
42263 }
42265 /* Implement targetm.vectorize.finish_cost. */
42267 static void
42270 {
42275 }
42277 /* Implement targetm.vectorize.destroy_cost_data. */
42279 static void
42281 {
42283 }
42285 /* Validate target specific memory model bits in VAL. */
42287 static unsigned HOST_WIDE_INT
42289 {
42296 {
42300 }
42303 {
42307 }
42309 {
42313 }
42315 }
42317 /* Initialize the GCC target structure. */
42318 #undef TARGET_RETURN_IN_MEMORY
42319 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42321 #undef TARGET_LEGITIMIZE_ADDRESS
42322 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42324 #undef TARGET_ATTRIBUTE_TABLE
42325 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42326 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
42327 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
42328 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42329 # undef TARGET_MERGE_DECL_ATTRIBUTES
42330 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42331 #endif
42333 #undef TARGET_COMP_TYPE_ATTRIBUTES
42334 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42336 #undef TARGET_INIT_BUILTINS
42337 #define TARGET_INIT_BUILTINS ix86_init_builtins
42338 #undef TARGET_BUILTIN_DECL
42339 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42340 #undef TARGET_EXPAND_BUILTIN
42341 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42343 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42344 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42345 ix86_builtin_vectorized_function
42347 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42348 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42350 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42351 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42353 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42354 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42356 #undef TARGET_BUILTIN_RECIPROCAL
42357 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42359 #undef TARGET_ASM_FUNCTION_EPILOGUE
42360 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42362 #undef TARGET_ENCODE_SECTION_INFO
42363 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42364 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42365 #else
42366 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42367 #endif
42369 #undef TARGET_ASM_OPEN_PAREN
42371 #undef TARGET_ASM_CLOSE_PAREN
42374 #undef TARGET_ASM_BYTE_OP
42375 #define TARGET_ASM_BYTE_OP ASM_BYTE
42377 #undef TARGET_ASM_ALIGNED_HI_OP
42378 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42379 #undef TARGET_ASM_ALIGNED_SI_OP
42380 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42381 #ifdef ASM_QUAD
42382 #undef TARGET_ASM_ALIGNED_DI_OP
42383 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42384 #endif
42386 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42387 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42389 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42390 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42392 #undef TARGET_ASM_UNALIGNED_HI_OP
42393 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42394 #undef TARGET_ASM_UNALIGNED_SI_OP
42395 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42396 #undef TARGET_ASM_UNALIGNED_DI_OP
42397 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42399 #undef TARGET_PRINT_OPERAND
42400 #define TARGET_PRINT_OPERAND ix86_print_operand
42401 #undef TARGET_PRINT_OPERAND_ADDRESS
42402 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42403 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42404 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42405 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42406 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42408 #undef TARGET_SCHED_INIT_GLOBAL
42409 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42410 #undef TARGET_SCHED_ADJUST_COST
42411 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42412 #undef TARGET_SCHED_ISSUE_RATE
42413 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42414 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42415 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42416 ia32_multipass_dfa_lookahead
42418 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42419 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42421 #undef TARGET_MEMMODEL_CHECK
42422 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42424 #ifdef HAVE_AS_TLS
42425 #undef TARGET_HAVE_TLS
42426 #define TARGET_HAVE_TLS true
42427 #endif
42428 #undef TARGET_CANNOT_FORCE_CONST_MEM
42429 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42430 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42431 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42433 #undef TARGET_DELEGITIMIZE_ADDRESS
42434 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42436 #undef TARGET_MS_BITFIELD_LAYOUT_P
42437 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42439 #if TARGET_MACHO
42440 #undef TARGET_BINDS_LOCAL_P
42441 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42442 #endif
42443 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42444 #undef TARGET_BINDS_LOCAL_P
42445 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42446 #endif
42448 #undef TARGET_ASM_OUTPUT_MI_THUNK
42449 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42450 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42451 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42453 #undef TARGET_ASM_FILE_START
42454 #define TARGET_ASM_FILE_START x86_file_start
42456 #undef TARGET_OPTION_OVERRIDE
42457 #define TARGET_OPTION_OVERRIDE ix86_option_override
42459 #undef TARGET_REGISTER_MOVE_COST
42460 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42461 #undef TARGET_MEMORY_MOVE_COST
42462 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42463 #undef TARGET_RTX_COSTS
42464 #define TARGET_RTX_COSTS ix86_rtx_costs
42465 #undef TARGET_ADDRESS_COST
42466 #define TARGET_ADDRESS_COST ix86_address_cost
42468 #undef TARGET_FIXED_CONDITION_CODE_REGS
42469 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42470 #undef TARGET_CC_MODES_COMPATIBLE
42471 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42473 #undef TARGET_MACHINE_DEPENDENT_REORG
42474 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42476 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42477 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42479 #undef TARGET_BUILD_BUILTIN_VA_LIST
42480 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42482 #undef TARGET_FOLD_BUILTIN
42483 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42485 #undef TARGET_COMPARE_VERSION_PRIORITY
42486 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42488 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42489 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42490 ix86_generate_version_dispatcher_body
42492 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42493 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42494 ix86_get_function_versions_dispatcher
42496 #undef TARGET_ENUM_VA_LIST_P
42497 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42499 #undef TARGET_FN_ABI_VA_LIST
42500 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42502 #undef TARGET_CANONICAL_VA_LIST_TYPE
42503 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42505 #undef TARGET_EXPAND_BUILTIN_VA_START
42506 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42508 #undef TARGET_MD_ASM_CLOBBERS
42509 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42511 #undef TARGET_PROMOTE_PROTOTYPES
42512 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42513 #undef TARGET_SETUP_INCOMING_VARARGS
42514 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42515 #undef TARGET_MUST_PASS_IN_STACK
42516 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42517 #undef TARGET_FUNCTION_ARG_ADVANCE
42518 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42519 #undef TARGET_FUNCTION_ARG
42520 #define TARGET_FUNCTION_ARG ix86_function_arg
42521 #undef TARGET_FUNCTION_ARG_BOUNDARY
42522 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42523 #undef TARGET_PASS_BY_REFERENCE
42524 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42525 #undef TARGET_INTERNAL_ARG_POINTER
42526 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42527 #undef TARGET_UPDATE_STACK_BOUNDARY
42528 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42529 #undef TARGET_GET_DRAP_RTX
42530 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42531 #undef TARGET_STRICT_ARGUMENT_NAMING
42532 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42533 #undef TARGET_STATIC_CHAIN
42534 #define TARGET_STATIC_CHAIN ix86_static_chain
42535 #undef TARGET_TRAMPOLINE_INIT
42536 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42537 #undef TARGET_RETURN_POPS_ARGS
42538 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42540 #undef TARGET_LEGITIMATE_COMBINED_INSN
42541 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42543 #undef TARGET_ASAN_SHADOW_OFFSET
42544 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42546 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42547 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42549 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42550 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42552 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42553 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42555 #undef TARGET_C_MODE_FOR_SUFFIX
42556 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42558 #ifdef HAVE_AS_TLS
42559 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42560 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42561 #endif
42563 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42564 #undef TARGET_INSERT_ATTRIBUTES
42565 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42566 #endif
42568 #undef TARGET_MANGLE_TYPE
42569 #define TARGET_MANGLE_TYPE ix86_mangle_type
42571 #if !TARGET_MACHO
42572 #undef TARGET_STACK_PROTECT_FAIL
42573 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42574 #endif
42576 #undef TARGET_FUNCTION_VALUE
42577 #define TARGET_FUNCTION_VALUE ix86_function_value
42579 #undef TARGET_FUNCTION_VALUE_REGNO_P
42580 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42582 #undef TARGET_PROMOTE_FUNCTION_MODE
42583 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42585 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42586 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42588 #undef TARGET_INSTANTIATE_DECLS
42589 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42591 #undef TARGET_SECONDARY_RELOAD
42592 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42594 #undef TARGET_CLASS_MAX_NREGS
42595 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42597 #undef TARGET_PREFERRED_RELOAD_CLASS
42598 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42599 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42600 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42601 #undef TARGET_CLASS_LIKELY_SPILLED_P
42602 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42604 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42605 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42606 ix86_builtin_vectorization_cost
42607 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42608 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42609 ix86_vectorize_vec_perm_const_ok
42610 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42611 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42612 ix86_preferred_simd_mode
42613 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42614 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42615 ix86_autovectorize_vector_sizes
42616 #undef TARGET_VECTORIZE_INIT_COST
42617 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42618 #undef TARGET_VECTORIZE_ADD_STMT_COST
42619 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42620 #undef TARGET_VECTORIZE_FINISH_COST
42621 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42622 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42623 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42625 #undef TARGET_SET_CURRENT_FUNCTION
42626 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42628 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42629 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42631 #undef TARGET_OPTION_SAVE
42632 #define TARGET_OPTION_SAVE ix86_function_specific_save
42634 #undef TARGET_OPTION_RESTORE
42635 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42637 #undef TARGET_OPTION_PRINT
42638 #define TARGET_OPTION_PRINT ix86_function_specific_print
42640 #undef TARGET_OPTION_FUNCTION_VERSIONS
42641 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42643 #undef TARGET_CAN_INLINE_P
42644 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42646 #undef TARGET_EXPAND_TO_RTL_HOOK
42647 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42649 #undef TARGET_LEGITIMATE_ADDRESS_P
42650 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42652 #undef TARGET_LRA_P
42653 #define TARGET_LRA_P hook_bool_void_true
42655 #undef TARGET_REGISTER_PRIORITY
42656 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42658 #undef TARGET_LEGITIMATE_CONSTANT_P
42659 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42661 #undef TARGET_FRAME_POINTER_REQUIRED
42662 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42664 #undef TARGET_CAN_ELIMINATE
42665 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42667 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42668 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42670 #undef TARGET_ASM_CODE_END
42671 #define TARGET_ASM_CODE_END ix86_code_end
42673 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42674 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42676 #if TARGET_MACHO
42677 #undef TARGET_INIT_LIBFUNCS
42678 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42679 #endif
42681 #undef TARGET_SPILL_CLASS
42682 #define TARGET_SPILL_CLASS ix86_spill_class
42685 \f