| blob | 22787e2f70e3f2a4c927330b508b59a0c696fc40 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2015 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_TOCSLOT ; offset from r1 of toc pointer save slot
73 UNSPEC_MOVSI_GOT
74 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
75 UNSPEC_FCTIWZ
76 UNSPEC_FRIM
77 UNSPEC_FRIN
78 UNSPEC_FRIP
79 UNSPEC_FRIZ
80 UNSPEC_LD_MPIC ; load_macho_picbase
81 UNSPEC_RELD_MPIC ; re-load_macho_picbase
82 UNSPEC_MPIC_CORRECT ; macho_correct_pic
83 UNSPEC_TLSGD
84 UNSPEC_TLSLD
85 UNSPEC_MOVESI_FROM_CR
86 UNSPEC_MOVESI_TO_CR
87 UNSPEC_TLSDTPREL
88 UNSPEC_TLSDTPRELHA
89 UNSPEC_TLSDTPRELLO
90 UNSPEC_TLSGOTDTPREL
91 UNSPEC_TLSTPREL
92 UNSPEC_TLSTPRELHA
93 UNSPEC_TLSTPRELLO
94 UNSPEC_TLSGOTTPREL
95 UNSPEC_TLSTLS
96 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
97 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
98 UNSPEC_STFIWX
99 UNSPEC_POPCNTB
100 UNSPEC_FRES
101 UNSPEC_SP_SET
102 UNSPEC_SP_TEST
103 UNSPEC_SYNC
104 UNSPEC_LWSYNC
105 UNSPEC_SYNC_OP
106 UNSPEC_ATOMIC
107 UNSPEC_CMPXCHG
108 UNSPEC_XCHG
109 UNSPEC_AND
110 UNSPEC_DLMZB
111 UNSPEC_DLMZB_CR
112 UNSPEC_DLMZB_STRLEN
113 UNSPEC_RSQRT
114 UNSPEC_TOCREL
115 UNSPEC_MACHOPIC_OFFSET
116 UNSPEC_BPERM
117 UNSPEC_COPYSIGN
118 UNSPEC_PARITY
119 UNSPEC_FCTIW
120 UNSPEC_FCTID
121 UNSPEC_LFIWAX
122 UNSPEC_LFIWZX
123 UNSPEC_FCTIWUZ
124 UNSPEC_GRP_END_NOP
125 UNSPEC_P8V_FMRGOW
126 UNSPEC_P8V_MTVSRWZ
127 UNSPEC_P8V_RELOAD_FROM_GPR
128 UNSPEC_P8V_MTVSRD
129 UNSPEC_P8V_XXPERMDI
130 UNSPEC_P8V_RELOAD_FROM_VSX
131 UNSPEC_ADDG6S
132 UNSPEC_CDTBCD
133 UNSPEC_CBCDTD
134 UNSPEC_DIVE
135 UNSPEC_DIVEO
136 UNSPEC_DIVEU
137 UNSPEC_DIVEUO
138 UNSPEC_UNPACK_128BIT
139 UNSPEC_PACK_128BIT
140 UNSPEC_LSQ
141 UNSPEC_FUSION_GPR
142 ])
144 ;;
145 ;; UNSPEC_VOLATILE usage
146 ;;
148 (define_c_enum "unspecv"
149 [UNSPECV_BLOCK
150 UNSPECV_LL ; load-locked
151 UNSPECV_SC ; store-conditional
152 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
153 UNSPECV_EH_RR ; eh_reg_restore
154 UNSPECV_ISYNC ; isync instruction
155 UNSPECV_MFTB ; move from time base
156 UNSPECV_NLGR ; non-local goto receiver
157 UNSPECV_MFFS ; Move from FPSCR
158 UNSPECV_MTFSF ; Move to FPSCR Fields
159 ])
161 \f
162 ;; Define an insn type attribute. This is used in function unit delay
163 ;; computations.
164 (define_attr "type"
165 "integer,two,three,
166 add,logical,shift,insert,
167 mul,halfmul,div,
168 exts,cntlz,popcnt,isel,
169 load,store,fpload,fpstore,vecload,vecstore,
170 cmp,
171 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 brinc,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 htm"
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
200 (const_string "yes")
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
208 (const_string "yes")
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; register?
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
222 (const_string "yes")
223 (const_string "no"))
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (const_int -32768))
236 (lt (minus (match_dup 0) (pc))
237 (const_int 32764)))
238 (const_int 4)
239 (const_int 8))
240 (const_int 4)))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
244 (define_attr "cpu"
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (and (eq_attr "type" "shift,exts,mul")
258 (eq_attr "dot" "yes"))
259 (and (eq_attr "type" "load")
260 (eq_attr "sign_extend" "yes"))
261 (and (eq_attr "type" "shift")
262 (eq_attr "var_shift" "yes")))
263 (const_string "always")
264 (const_string "not")))
266 (automata_option "ndfa")
268 (include "rs64.md")
269 (include "mpc.md")
270 (include "40x.md")
271 (include "440.md")
272 (include "476.md")
273 (include "601.md")
274 (include "603.md")
275 (include "6xx.md")
276 (include "7xx.md")
277 (include "7450.md")
278 (include "8540.md")
279 (include "e300c2c3.md")
280 (include "e500mc.md")
281 (include "e500mc64.md")
282 (include "e5500.md")
283 (include "e6500.md")
284 (include "power4.md")
285 (include "power5.md")
286 (include "power6.md")
287 (include "power7.md")
288 (include "power8.md")
289 (include "cell.md")
290 (include "xfpu.md")
291 (include "a2.md")
292 (include "titan.md")
294 (include "predicates.md")
295 (include "constraints.md")
297 (include "darwin.md")
299 \f
300 ;; Mode iterators
302 ; This mode iterator allows :GPR to be used to indicate the allowable size
303 ; of whole values in GPRs.
304 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
306 ; Any supported integer mode.
307 (define_mode_iterator INT [QI HI SI DI TI PTI])
309 ; Any supported integer mode that fits in one register.
310 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
312 ; Everything we can extend QImode to.
313 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
315 ; Everything we can extend HImode to.
316 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
318 ; Everything we can extend SImode to.
319 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
321 ; QImode or HImode for small atomic ops
322 (define_mode_iterator QHI [QI HI])
324 ; HImode or SImode for sign extended fusion ops
325 (define_mode_iterator HSI [HI SI])
327 ; SImode or DImode, even if DImode doesn't fit in GPRs.
328 (define_mode_iterator SDI [SI DI])
330 ; The size of a pointer. Also, the size of the value that a record-condition
331 ; (one with a '.') will compare; and the size used for arithmetic carries.
332 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
334 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
335 ; PTImode is GPR only)
336 (define_mode_iterator TI2 [TI PTI])
338 ; Any hardware-supported floating-point mode
339 (define_mode_iterator FP [
340 (SF "TARGET_HARD_FLOAT
341 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
342 (DF "TARGET_HARD_FLOAT
343 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
344 (TF "!TARGET_IEEEQUAD
345 && TARGET_HARD_FLOAT
346 && (TARGET_FPRS || TARGET_E500_DOUBLE)
347 && TARGET_LONG_DOUBLE_128")
348 (DD "TARGET_DFP")
349 (TD "TARGET_DFP")])
351 ; Any fma capable floating-point mode.
352 (define_mode_iterator FMA_F [
353 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
354 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
355 || VECTOR_UNIT_VSX_P (DFmode)")
356 (V2SF "TARGET_PAIRED_FLOAT")
357 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
358 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
359 ])
361 ; Floating point move iterators to combine binary and decimal moves
362 (define_mode_iterator FMOVE32 [SF SD])
363 (define_mode_iterator FMOVE64 [DF DD])
364 (define_mode_iterator FMOVE64X [DI DF DD])
365 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
366 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
368 ; Iterators for 128 bit types for direct move
369 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
370 (V16QI "")
371 (V8HI "")
372 (V4SI "")
373 (V4SF "")
374 (V2DI "")
375 (V2DF "")
376 (V1TI "")])
378 ; Whether a floating point move is ok, don't allow SD without hardware FP
379 (define_mode_attr fmove_ok [(SF "")
380 (DF "")
381 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
382 (DD "")])
384 ; Convert REAL_VALUE to the appropriate bits
385 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
386 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
387 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
388 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
390 ; Definitions for load to 32-bit fpr register
391 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
392 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
393 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
394 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
396 ; Definitions for store from 32-bit fpr register
397 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
398 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
399 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
400 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
402 ; Definitions for 32-bit fpr direct move
403 ; At present, the decimal modes are not allowed in the traditional altivec
404 ; registers, so restrict the constraints to just the traditional FPRs.
405 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
407 ; Definitions for 32-bit VSX
408 (define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
410 ; Definitions for 32-bit use of altivec registers
411 (define_mode_attr f32_av [(SF "wu") (SD "wn")])
413 ; Definitions for 64-bit VSX
414 (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
416 ; Definitions for 64-bit direct move
417 (define_mode_attr f64_dm [(DF "wk") (DD "wh")])
419 ; Definitions for 64-bit use of altivec registers
420 (define_mode_attr f64_av [(DF "wv") (DD "wn")])
422 ; These modes do not fit in integer registers in 32-bit mode.
423 ; but on e500v2, the gpr are 64 bit registers
424 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
426 ; Iterator for reciprocal estimate instructions
427 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
429 ; Iterator for just SF/DF
430 (define_mode_iterator SFDF [SF DF])
432 ; SF/DF suffix for traditional floating instructions
433 (define_mode_attr Ftrad [(SF "s") (DF "")])
435 ; SF/DF suffix for VSX instructions
436 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
438 ; SF/DF constraint for arithmetic on traditional floating point registers
439 (define_mode_attr Ff [(SF "f") (DF "d")])
441 ; SF/DF constraint for arithmetic on VSX registers
442 (define_mode_attr Fv [(SF "wy") (DF "ws")])
444 ; SF/DF constraint for arithmetic on altivec registers
445 (define_mode_attr Fa [(SF "wu") (DF "wv")])
447 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
448 (define_mode_attr Fs [(SF "s") (DF "d")])
450 ; FRE/FRES support
451 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
452 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
454 ; Conditional returns.
455 (define_code_iterator any_return [return simple_return])
456 (define_code_attr return_pred [(return "direct_return ()")
457 (simple_return "1")])
458 (define_code_attr return_str [(return "") (simple_return "simple_")])
460 ; Logical operators.
461 (define_code_iterator iorxor [ior xor])
463 ; Signed/unsigned variants of ops.
464 (define_code_iterator any_extend [sign_extend zero_extend])
465 (define_code_attr u [(sign_extend "") (zero_extend "u")])
466 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
468 ; Various instructions that come in SI and DI forms.
469 ; A generic w/d attribute, for things like cmpw/cmpd.
470 (define_mode_attr wd [(QI "b")
471 (HI "h")
472 (SI "w")
473 (DI "d")
474 (V16QI "b")
475 (V8HI "h")
476 (V4SI "w")
477 (V2DI "d")])
479 ;; How many bits in this mode?
480 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
482 ; DImode bits
483 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
485 ;; ISEL/ISEL64 target selection
486 (define_mode_attr sel [(SI "") (DI "64")])
488 ;; Bitmask for shift instructions
489 (define_mode_attr hH [(SI "h") (DI "H")])
491 ;; A mode twice the size of the given mode
492 (define_mode_attr dmode [(SI "di") (DI "ti")])
493 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
495 ;; Suffix for reload patterns
496 (define_mode_attr ptrsize [(SI "32bit")
497 (DI "64bit")])
499 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
500 (DI "TARGET_64BIT")])
502 (define_mode_attr mptrsize [(SI "si")
503 (DI "di")])
505 (define_mode_attr ptrload [(SI "lwz")
506 (DI "ld")])
508 (define_mode_attr ptrm [(SI "m")
509 (DI "Y")])
511 (define_mode_attr rreg [(SF "f")
512 (DF "ws")
513 (TF "f")
514 (TD "f")
515 (V4SF "wf")
516 (V2DF "wd")])
518 (define_mode_attr rreg2 [(SF "f")
519 (DF "d")])
521 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
522 (DF "TARGET_FCFID")])
524 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
525 (DF "TARGET_E500_DOUBLE")])
527 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
528 (DF "TARGET_DOUBLE_FLOAT")])
530 ;; Mode iterator for logical operations on 128-bit types
531 (define_mode_iterator BOOL_128 [TI
532 PTI
533 (V16QI "TARGET_ALTIVEC")
534 (V8HI "TARGET_ALTIVEC")
535 (V4SI "TARGET_ALTIVEC")
536 (V4SF "TARGET_ALTIVEC")
537 (V2DI "TARGET_ALTIVEC")
538 (V2DF "TARGET_ALTIVEC")
539 (V1TI "TARGET_ALTIVEC")])
541 ;; For the GPRs we use 3 constraints for register outputs, two that are the
542 ;; same as the output register, and a third where the output register is an
543 ;; early clobber, so we don't have to deal with register overlaps. For the
544 ;; vector types, we prefer to use the vector registers. For TI mode, allow
545 ;; either.
547 ;; Mode attribute for boolean operation register constraints for output
548 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
549 (PTI "&r,r,r")
550 (V16QI "wa,v,&?r,?r,?r")
551 (V8HI "wa,v,&?r,?r,?r")
552 (V4SI "wa,v,&?r,?r,?r")
553 (V4SF "wa,v,&?r,?r,?r")
554 (V2DI "wa,v,&?r,?r,?r")
555 (V2DF "wa,v,&?r,?r,?r")
556 (V1TI "wa,v,&?r,?r,?r")])
558 ;; Mode attribute for boolean operation register constraints for operand1
559 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
560 (PTI "r,0,r")
561 (V16QI "wa,v,r,0,r")
562 (V8HI "wa,v,r,0,r")
563 (V4SI "wa,v,r,0,r")
564 (V4SF "wa,v,r,0,r")
565 (V2DI "wa,v,r,0,r")
566 (V2DF "wa,v,r,0,r")
567 (V1TI "wa,v,r,0,r")])
569 ;; Mode attribute for boolean operation register constraints for operand2
570 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
571 (PTI "r,r,0")
572 (V16QI "wa,v,r,r,0")
573 (V8HI "wa,v,r,r,0")
574 (V4SI "wa,v,r,r,0")
575 (V4SF "wa,v,r,r,0")
576 (V2DI "wa,v,r,r,0")
577 (V2DF "wa,v,r,r,0")
578 (V1TI "wa,v,r,r,0")])
580 ;; Mode attribute for boolean operation register constraints for operand1
581 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
582 ;; is used for operand1 or operand2
583 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
584 (PTI "r,0,0")
585 (V16QI "wa,v,r,0,0")
586 (V8HI "wa,v,r,0,0")
587 (V4SI "wa,v,r,0,0")
588 (V4SF "wa,v,r,0,0")
589 (V2DI "wa,v,r,0,0")
590 (V2DF "wa,v,r,0,0")
591 (V1TI "wa,v,r,0,0")])
593 ;; Reload iterator for creating the function to allocate a base register to
594 ;; supplement addressing modes.
595 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
596 SF SD SI DF DD DI TI PTI])
598 \f
599 ;; Start with fixed-point load and store insns. Here we put only the more
600 ;; complex forms. Basic data transfer is done later.
602 (define_insn "zero_extendqi<mode>2"
603 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
604 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
605 ""
606 "@
607 lbz%U1%X1 %0,%1
608 rlwinm %0,%1,0,0xff"
609 [(set_attr "type" "load,shift")])
611 (define_insn_and_split "*zero_extendqi<mode>2_dot"
612 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
613 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
614 (const_int 0)))
615 (clobber (match_scratch:EXTQI 0 "=r,r"))]
616 "rs6000_gen_cell_microcode"
617 "@
618 andi. %0,%1,0xff
619 #"
620 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
621 [(set (match_dup 0)
622 (zero_extend:EXTQI (match_dup 1)))
623 (set (match_dup 2)
624 (compare:CC (match_dup 0)
625 (const_int 0)))]
626 ""
627 [(set_attr "type" "logical")
628 (set_attr "dot" "yes")
629 (set_attr "length" "4,8")])
631 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
632 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
633 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
634 (const_int 0)))
635 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
636 (zero_extend:EXTQI (match_dup 1)))]
637 "rs6000_gen_cell_microcode"
638 "@
639 andi. %0,%1,0xff
640 #"
641 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
642 [(set (match_dup 0)
643 (zero_extend:EXTQI (match_dup 1)))
644 (set (match_dup 2)
645 (compare:CC (match_dup 0)
646 (const_int 0)))]
647 ""
648 [(set_attr "type" "logical")
649 (set_attr "dot" "yes")
650 (set_attr "length" "4,8")])
653 (define_insn "zero_extendhi<mode>2"
654 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
655 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
656 ""
657 "@
658 lhz%U1%X1 %0,%1
659 rlwinm %0,%1,0,0xffff"
660 [(set_attr "type" "load,shift")])
662 (define_insn_and_split "*zero_extendhi<mode>2_dot"
663 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
664 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
665 (const_int 0)))
666 (clobber (match_scratch:EXTHI 0 "=r,r"))]
667 "rs6000_gen_cell_microcode"
668 "@
669 andi. %0,%1,0xffff
670 #"
671 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
672 [(set (match_dup 0)
673 (zero_extend:EXTHI (match_dup 1)))
674 (set (match_dup 2)
675 (compare:CC (match_dup 0)
676 (const_int 0)))]
677 ""
678 [(set_attr "type" "logical")
679 (set_attr "dot" "yes")
680 (set_attr "length" "4,8")])
682 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
683 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
684 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
685 (const_int 0)))
686 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
687 (zero_extend:EXTHI (match_dup 1)))]
688 "rs6000_gen_cell_microcode"
689 "@
690 andi. %0,%1,0xffff
691 #"
692 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
693 [(set (match_dup 0)
694 (zero_extend:EXTHI (match_dup 1)))
695 (set (match_dup 2)
696 (compare:CC (match_dup 0)
697 (const_int 0)))]
698 ""
699 [(set_attr "type" "logical")
700 (set_attr "dot" "yes")
701 (set_attr "length" "4,8")])
704 (define_insn "zero_extendsi<mode>2"
705 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
706 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
707 ""
708 "@
709 lwz%U1%X1 %0,%1
710 rldicl %0,%1,0,32
711 mtvsrwz %x0,%1
712 lfiwzx %0,%y1
713 lxsiwzx %x0,%y1"
714 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
716 (define_insn_and_split "*zero_extendsi<mode>2_dot"
717 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
718 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
719 (const_int 0)))
720 (clobber (match_scratch:EXTSI 0 "=r,r"))]
721 "rs6000_gen_cell_microcode"
722 "@
723 rldicl. %0,%1,0,32
724 #"
725 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
726 [(set (match_dup 0)
727 (zero_extend:DI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 ""
732 [(set_attr "type" "shift")
733 (set_attr "dot" "yes")
734 (set_attr "length" "4,8")])
736 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
737 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
738 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
739 (const_int 0)))
740 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
741 (zero_extend:EXTSI (match_dup 1)))]
742 "rs6000_gen_cell_microcode"
743 "@
744 rldicl. %0,%1,0,32
745 #"
746 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
747 [(set (match_dup 0)
748 (zero_extend:EXTSI (match_dup 1)))
749 (set (match_dup 2)
750 (compare:CC (match_dup 0)
751 (const_int 0)))]
752 ""
753 [(set_attr "type" "shift")
754 (set_attr "dot" "yes")
755 (set_attr "length" "4,8")])
758 (define_insn "extendqi<mode>2"
759 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
760 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
761 ""
762 "extsb %0,%1"
763 [(set_attr "type" "exts")])
765 (define_insn_and_split "*extendqi<mode>2_dot"
766 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
767 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
768 (const_int 0)))
769 (clobber (match_scratch:EXTQI 0 "=r,r"))]
770 "rs6000_gen_cell_microcode"
771 "@
772 extsb. %0,%1
773 #"
774 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
775 [(set (match_dup 0)
776 (sign_extend:EXTQI (match_dup 1)))
777 (set (match_dup 2)
778 (compare:CC (match_dup 0)
779 (const_int 0)))]
780 ""
781 [(set_attr "type" "exts")
782 (set_attr "dot" "yes")
783 (set_attr "length" "4,8")])
785 (define_insn_and_split "*extendqi<mode>2_dot2"
786 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
787 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
788 (const_int 0)))
789 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
790 (sign_extend:EXTQI (match_dup 1)))]
791 "rs6000_gen_cell_microcode"
792 "@
793 extsb. %0,%1
794 #"
795 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
796 [(set (match_dup 0)
797 (sign_extend:EXTQI (match_dup 1)))
798 (set (match_dup 2)
799 (compare:CC (match_dup 0)
800 (const_int 0)))]
801 ""
802 [(set_attr "type" "exts")
803 (set_attr "dot" "yes")
804 (set_attr "length" "4,8")])
807 (define_expand "extendhi<mode>2"
808 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
809 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
810 ""
811 "")
813 (define_insn "*extendhi<mode>2"
814 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
815 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
816 "rs6000_gen_cell_microcode"
817 "@
818 lha%U1%X1 %0,%1
819 extsh %0,%1"
820 [(set_attr "type" "load,exts")
821 (set_attr "sign_extend" "yes")])
823 (define_insn "*extendhi<mode>2_noload"
824 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
825 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
826 "!rs6000_gen_cell_microcode"
827 "extsh %0,%1"
828 [(set_attr "type" "exts")])
830 (define_insn_and_split "*extendhi<mode>2_dot"
831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
832 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
833 (const_int 0)))
834 (clobber (match_scratch:EXTHI 0 "=r,r"))]
835 "rs6000_gen_cell_microcode"
836 "@
837 extsh. %0,%1
838 #"
839 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
840 [(set (match_dup 0)
841 (sign_extend:EXTHI (match_dup 1)))
842 (set (match_dup 2)
843 (compare:CC (match_dup 0)
844 (const_int 0)))]
845 ""
846 [(set_attr "type" "exts")
847 (set_attr "dot" "yes")
848 (set_attr "length" "4,8")])
850 (define_insn_and_split "*extendhi<mode>2_dot2"
851 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
852 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
855 (sign_extend:EXTHI (match_dup 1)))]
856 "rs6000_gen_cell_microcode"
857 "@
858 extsh. %0,%1
859 #"
860 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
861 [(set (match_dup 0)
862 (sign_extend:EXTHI (match_dup 1)))
863 (set (match_dup 2)
864 (compare:CC (match_dup 0)
865 (const_int 0)))]
866 ""
867 [(set_attr "type" "exts")
868 (set_attr "dot" "yes")
869 (set_attr "length" "4,8")])
872 (define_insn "extendsi<mode>2"
873 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
874 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
875 ""
876 "@
877 lwa%U1%X1 %0,%1
878 extsw %0,%1
879 mtvsrwa %x0,%1
880 lfiwax %0,%y1
881 lxsiwax %x0,%y1"
882 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
883 (set_attr "sign_extend" "yes")])
885 (define_insn_and_split "*extendsi<mode>2_dot"
886 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
887 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
888 (const_int 0)))
889 (clobber (match_scratch:EXTSI 0 "=r,r"))]
890 "rs6000_gen_cell_microcode"
891 "@
892 extsw. %0,%1
893 #"
894 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
895 [(set (match_dup 0)
896 (sign_extend:EXTSI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 ""
901 [(set_attr "type" "exts")
902 (set_attr "dot" "yes")
903 (set_attr "length" "4,8")])
905 (define_insn_and_split "*extendsi<mode>2_dot2"
906 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
907 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
908 (const_int 0)))
909 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:EXTSI (match_dup 1)))]
911 "rs6000_gen_cell_microcode"
912 "@
913 extsw. %0,%1
914 #"
915 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
916 [(set (match_dup 0)
917 (sign_extend:EXTSI (match_dup 1)))
918 (set (match_dup 2)
919 (compare:CC (match_dup 0)
920 (const_int 0)))]
921 ""
922 [(set_attr "type" "exts")
923 (set_attr "dot" "yes")
924 (set_attr "length" "4,8")])
925 \f
926 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
928 (define_insn "*macchwc"
929 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
930 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
931 (match_operand:SI 2 "gpc_reg_operand" "r")
932 (const_int 16))
933 (sign_extend:SI
934 (match_operand:HI 1 "gpc_reg_operand" "r")))
935 (match_operand:SI 4 "gpc_reg_operand" "0"))
936 (const_int 0)))
937 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
938 (plus:SI (mult:SI (ashiftrt:SI
939 (match_dup 2)
940 (const_int 16))
941 (sign_extend:SI
942 (match_dup 1)))
943 (match_dup 4)))]
944 "TARGET_MULHW"
945 "macchw. %0,%1,%2"
946 [(set_attr "type" "halfmul")])
948 (define_insn "*macchw"
949 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
950 (plus:SI (mult:SI (ashiftrt:SI
951 (match_operand:SI 2 "gpc_reg_operand" "r")
952 (const_int 16))
953 (sign_extend:SI
954 (match_operand:HI 1 "gpc_reg_operand" "r")))
955 (match_operand:SI 3 "gpc_reg_operand" "0")))]
956 "TARGET_MULHW"
957 "macchw %0,%1,%2"
958 [(set_attr "type" "halfmul")])
960 (define_insn "*macchwuc"
961 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
962 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
963 (match_operand:SI 2 "gpc_reg_operand" "r")
964 (const_int 16))
965 (zero_extend:SI
966 (match_operand:HI 1 "gpc_reg_operand" "r")))
967 (match_operand:SI 4 "gpc_reg_operand" "0"))
968 (const_int 0)))
969 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
970 (plus:SI (mult:SI (lshiftrt:SI
971 (match_dup 2)
972 (const_int 16))
973 (zero_extend:SI
974 (match_dup 1)))
975 (match_dup 4)))]
976 "TARGET_MULHW"
977 "macchwu. %0,%1,%2"
978 [(set_attr "type" "halfmul")])
980 (define_insn "*macchwu"
981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
982 (plus:SI (mult:SI (lshiftrt:SI
983 (match_operand:SI 2 "gpc_reg_operand" "r")
984 (const_int 16))
985 (zero_extend:SI
986 (match_operand:HI 1 "gpc_reg_operand" "r")))
987 (match_operand:SI 3 "gpc_reg_operand" "0")))]
988 "TARGET_MULHW"
989 "macchwu %0,%1,%2"
990 [(set_attr "type" "halfmul")])
992 (define_insn "*machhwc"
993 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
994 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
995 (match_operand:SI 1 "gpc_reg_operand" "%r")
996 (const_int 16))
997 (ashiftrt:SI
998 (match_operand:SI 2 "gpc_reg_operand" "r")
999 (const_int 16)))
1000 (match_operand:SI 4 "gpc_reg_operand" "0"))
1001 (const_int 0)))
1002 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1003 (plus:SI (mult:SI (ashiftrt:SI
1004 (match_dup 1)
1005 (const_int 16))
1006 (ashiftrt:SI
1007 (match_dup 2)
1008 (const_int 16)))
1009 (match_dup 4)))]
1010 "TARGET_MULHW"
1011 "machhw. %0,%1,%2"
1012 [(set_attr "type" "halfmul")])
1014 (define_insn "*machhw"
1015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1016 (plus:SI (mult:SI (ashiftrt:SI
1017 (match_operand:SI 1 "gpc_reg_operand" "%r")
1018 (const_int 16))
1019 (ashiftrt:SI
1020 (match_operand:SI 2 "gpc_reg_operand" "r")
1021 (const_int 16)))
1022 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1023 "TARGET_MULHW"
1024 "machhw %0,%1,%2"
1025 [(set_attr "type" "halfmul")])
1027 (define_insn "*machhwuc"
1028 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1029 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1030 (match_operand:SI 1 "gpc_reg_operand" "%r")
1031 (const_int 16))
1032 (lshiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16)))
1035 (match_operand:SI 4 "gpc_reg_operand" "0"))
1036 (const_int 0)))
1037 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1038 (plus:SI (mult:SI (lshiftrt:SI
1039 (match_dup 1)
1040 (const_int 16))
1041 (lshiftrt:SI
1042 (match_dup 2)
1043 (const_int 16)))
1044 (match_dup 4)))]
1045 "TARGET_MULHW"
1046 "machhwu. %0,%1,%2"
1047 [(set_attr "type" "halfmul")])
1049 (define_insn "*machhwu"
1050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1051 (plus:SI (mult:SI (lshiftrt:SI
1052 (match_operand:SI 1 "gpc_reg_operand" "%r")
1053 (const_int 16))
1054 (lshiftrt:SI
1055 (match_operand:SI 2 "gpc_reg_operand" "r")
1056 (const_int 16)))
1057 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1058 "TARGET_MULHW"
1059 "machhwu %0,%1,%2"
1060 [(set_attr "type" "halfmul")])
1062 (define_insn "*maclhwc"
1063 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1064 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1065 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1066 (sign_extend:SI
1067 (match_operand:HI 2 "gpc_reg_operand" "r")))
1068 (match_operand:SI 4 "gpc_reg_operand" "0"))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (sign_extend:SI
1072 (match_dup 1))
1073 (sign_extend:SI
1074 (match_dup 2)))
1075 (match_dup 4)))]
1076 "TARGET_MULHW"
1077 "maclhw. %0,%1,%2"
1078 [(set_attr "type" "halfmul")])
1080 (define_insn "*maclhw"
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (sign_extend:SI
1083 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1084 (sign_extend:SI
1085 (match_operand:HI 2 "gpc_reg_operand" "r")))
1086 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1087 "TARGET_MULHW"
1088 "maclhw %0,%1,%2"
1089 [(set_attr "type" "halfmul")])
1091 (define_insn "*maclhwuc"
1092 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1093 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1094 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1095 (zero_extend:SI
1096 (match_operand:HI 2 "gpc_reg_operand" "r")))
1097 (match_operand:SI 4 "gpc_reg_operand" "0"))
1098 (const_int 0)))
1099 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (zero_extend:SI
1101 (match_dup 1))
1102 (zero_extend:SI
1103 (match_dup 2)))
1104 (match_dup 4)))]
1105 "TARGET_MULHW"
1106 "maclhwu. %0,%1,%2"
1107 [(set_attr "type" "halfmul")])
1109 (define_insn "*maclhwu"
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1111 (plus:SI (mult:SI (zero_extend:SI
1112 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1113 (zero_extend:SI
1114 (match_operand:HI 2 "gpc_reg_operand" "r")))
1115 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1116 "TARGET_MULHW"
1117 "maclhwu %0,%1,%2"
1118 [(set_attr "type" "halfmul")])
1120 (define_insn "*nmacchwc"
1121 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1122 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1123 (mult:SI (ashiftrt:SI
1124 (match_operand:SI 2 "gpc_reg_operand" "r")
1125 (const_int 16))
1126 (sign_extend:SI
1127 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1128 (const_int 0)))
1129 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1130 (minus:SI (match_dup 4)
1131 (mult:SI (ashiftrt:SI
1132 (match_dup 2)
1133 (const_int 16))
1134 (sign_extend:SI
1135 (match_dup 1)))))]
1136 "TARGET_MULHW"
1137 "nmacchw. %0,%1,%2"
1138 [(set_attr "type" "halfmul")])
1140 (define_insn "*nmacchw"
1141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1142 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1143 (mult:SI (ashiftrt:SI
1144 (match_operand:SI 2 "gpc_reg_operand" "r")
1145 (const_int 16))
1146 (sign_extend:SI
1147 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1148 "TARGET_MULHW"
1149 "nmacchw %0,%1,%2"
1150 [(set_attr "type" "halfmul")])
1152 (define_insn "*nmachhwc"
1153 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1154 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1155 (mult:SI (ashiftrt:SI
1156 (match_operand:SI 1 "gpc_reg_operand" "%r")
1157 (const_int 16))
1158 (ashiftrt:SI
1159 (match_operand:SI 2 "gpc_reg_operand" "r")
1160 (const_int 16))))
1161 (const_int 0)))
1162 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1163 (minus:SI (match_dup 4)
1164 (mult:SI (ashiftrt:SI
1165 (match_dup 1)
1166 (const_int 16))
1167 (ashiftrt:SI
1168 (match_dup 2)
1169 (const_int 16)))))]
1170 "TARGET_MULHW"
1171 "nmachhw. %0,%1,%2"
1172 [(set_attr "type" "halfmul")])
1174 (define_insn "*nmachhw"
1175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1176 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1177 (mult:SI (ashiftrt:SI
1178 (match_operand:SI 1 "gpc_reg_operand" "%r")
1179 (const_int 16))
1180 (ashiftrt:SI
1181 (match_operand:SI 2 "gpc_reg_operand" "r")
1182 (const_int 16)))))]
1183 "TARGET_MULHW"
1184 "nmachhw %0,%1,%2"
1185 [(set_attr "type" "halfmul")])
1187 (define_insn "*nmaclhwc"
1188 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1189 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1190 (mult:SI (sign_extend:SI
1191 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1192 (sign_extend:SI
1193 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1194 (const_int 0)))
1195 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (minus:SI (match_dup 4)
1197 (mult:SI (sign_extend:SI
1198 (match_dup 1))
1199 (sign_extend:SI
1200 (match_dup 2)))))]
1201 "TARGET_MULHW"
1202 "nmaclhw. %0,%1,%2"
1203 [(set_attr "type" "halfmul")])
1205 (define_insn "*nmaclhw"
1206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1207 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1208 (mult:SI (sign_extend:SI
1209 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1210 (sign_extend:SI
1211 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1212 "TARGET_MULHW"
1213 "nmaclhw %0,%1,%2"
1214 [(set_attr "type" "halfmul")])
1216 (define_insn "*mulchwc"
1217 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1218 (compare:CC (mult:SI (ashiftrt:SI
1219 (match_operand:SI 2 "gpc_reg_operand" "r")
1220 (const_int 16))
1221 (sign_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "r")))
1223 (const_int 0)))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (mult:SI (ashiftrt:SI
1226 (match_dup 2)
1227 (const_int 16))
1228 (sign_extend:SI
1229 (match_dup 1))))]
1230 "TARGET_MULHW"
1231 "mulchw. %0,%1,%2"
1232 [(set_attr "type" "halfmul")])
1234 (define_insn "*mulchw"
1235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1236 (mult:SI (ashiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1241 "TARGET_MULHW"
1242 "mulchw %0,%1,%2"
1243 [(set_attr "type" "halfmul")])
1245 (define_insn "*mulchwuc"
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (mult:SI (lshiftrt:SI
1248 (match_operand:SI 2 "gpc_reg_operand" "r")
1249 (const_int 16))
1250 (zero_extend:SI
1251 (match_operand:HI 1 "gpc_reg_operand" "r")))
1252 (const_int 0)))
1253 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1254 (mult:SI (lshiftrt:SI
1255 (match_dup 2)
1256 (const_int 16))
1257 (zero_extend:SI
1258 (match_dup 1))))]
1259 "TARGET_MULHW"
1260 "mulchwu. %0,%1,%2"
1261 [(set_attr "type" "halfmul")])
1263 (define_insn "*mulchwu"
1264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1265 (mult:SI (lshiftrt:SI
1266 (match_operand:SI 2 "gpc_reg_operand" "r")
1267 (const_int 16))
1268 (zero_extend:SI
1269 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1270 "TARGET_MULHW"
1271 "mulchwu %0,%1,%2"
1272 [(set_attr "type" "halfmul")])
1274 (define_insn "*mulhhwc"
1275 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1276 (compare:CC (mult:SI (ashiftrt:SI
1277 (match_operand:SI 1 "gpc_reg_operand" "%r")
1278 (const_int 16))
1279 (ashiftrt:SI
1280 (match_operand:SI 2 "gpc_reg_operand" "r")
1281 (const_int 16)))
1282 (const_int 0)))
1283 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1284 (mult:SI (ashiftrt:SI
1285 (match_dup 1)
1286 (const_int 16))
1287 (ashiftrt:SI
1288 (match_dup 2)
1289 (const_int 16))))]
1290 "TARGET_MULHW"
1291 "mulhhw. %0,%1,%2"
1292 [(set_attr "type" "halfmul")])
1294 (define_insn "*mulhhw"
1295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296 (mult:SI (ashiftrt:SI
1297 (match_operand:SI 1 "gpc_reg_operand" "%r")
1298 (const_int 16))
1299 (ashiftrt:SI
1300 (match_operand:SI 2 "gpc_reg_operand" "r")
1301 (const_int 16))))]
1302 "TARGET_MULHW"
1303 "mulhhw %0,%1,%2"
1304 [(set_attr "type" "halfmul")])
1306 (define_insn "*mulhhwuc"
1307 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1308 (compare:CC (mult:SI (lshiftrt:SI
1309 (match_operand:SI 1 "gpc_reg_operand" "%r")
1310 (const_int 16))
1311 (lshiftrt:SI
1312 (match_operand:SI 2 "gpc_reg_operand" "r")
1313 (const_int 16)))
1314 (const_int 0)))
1315 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (mult:SI (lshiftrt:SI
1317 (match_dup 1)
1318 (const_int 16))
1319 (lshiftrt:SI
1320 (match_dup 2)
1321 (const_int 16))))]
1322 "TARGET_MULHW"
1323 "mulhhwu. %0,%1,%2"
1324 [(set_attr "type" "halfmul")])
1326 (define_insn "*mulhhwu"
1327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (mult:SI (lshiftrt:SI
1329 (match_operand:SI 1 "gpc_reg_operand" "%r")
1330 (const_int 16))
1331 (lshiftrt:SI
1332 (match_operand:SI 2 "gpc_reg_operand" "r")
1333 (const_int 16))))]
1334 "TARGET_MULHW"
1335 "mulhhwu %0,%1,%2"
1336 [(set_attr "type" "halfmul")])
1338 (define_insn "*mullhwc"
1339 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1340 (compare:CC (mult:SI (sign_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1342 (sign_extend:SI
1343 (match_operand:HI 2 "gpc_reg_operand" "r")))
1344 (const_int 0)))
1345 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (sign_extend:SI
1347 (match_dup 1))
1348 (sign_extend:SI
1349 (match_dup 2))))]
1350 "TARGET_MULHW"
1351 "mullhw. %0,%1,%2"
1352 [(set_attr "type" "halfmul")])
1354 (define_insn "*mullhw"
1355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (sign_extend:SI
1357 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1358 (sign_extend:SI
1359 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1360 "TARGET_MULHW"
1361 "mullhw %0,%1,%2"
1362 [(set_attr "type" "halfmul")])
1364 (define_insn "*mullhwuc"
1365 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1366 (compare:CC (mult:SI (zero_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (zero_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r")))
1370 (const_int 0)))
1371 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1372 (mult:SI (zero_extend:SI
1373 (match_dup 1))
1374 (zero_extend:SI
1375 (match_dup 2))))]
1376 "TARGET_MULHW"
1377 "mullhwu. %0,%1,%2"
1378 [(set_attr "type" "halfmul")])
1380 (define_insn "*mullhwu"
1381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (zero_extend:SI
1383 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1384 (zero_extend:SI
1385 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1386 "TARGET_MULHW"
1387 "mullhwu %0,%1,%2"
1388 [(set_attr "type" "halfmul")])
1389 \f
1390 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1391 (define_insn "dlmzb"
1392 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1393 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1394 (match_operand:SI 2 "gpc_reg_operand" "r")]
1395 UNSPEC_DLMZB_CR))
1396 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (unspec:SI [(match_dup 1)
1398 (match_dup 2)]
1399 UNSPEC_DLMZB))]
1400 "TARGET_DLMZB"
1401 "dlmzb. %0,%1,%2")
1403 (define_expand "strlensi"
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1405 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1406 (match_operand:QI 2 "const_int_operand" "")
1407 (match_operand 3 "const_int_operand" "")]
1408 UNSPEC_DLMZB_STRLEN))
1409 (clobber (match_scratch:CC 4 "=x"))]
1410 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1411 {
1412 rtx result = operands[0];
1413 rtx src = operands[1];
1414 rtx search_char = operands[2];
1415 rtx align = operands[3];
1416 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1417 rtx loop_label, end_label, mem, cr0, cond;
1418 if (search_char != const0_rtx
1419 || GET_CODE (align) != CONST_INT
1420 || INTVAL (align) < 8)
1421 FAIL;
1422 word1 = gen_reg_rtx (SImode);
1423 word2 = gen_reg_rtx (SImode);
1424 scratch_dlmzb = gen_reg_rtx (SImode);
1425 scratch_string = gen_reg_rtx (Pmode);
1426 loop_label = gen_label_rtx ();
1427 end_label = gen_label_rtx ();
1428 addr = force_reg (Pmode, XEXP (src, 0));
1429 emit_move_insn (scratch_string, addr);
1430 emit_label (loop_label);
1431 mem = change_address (src, SImode, scratch_string);
1432 emit_move_insn (word1, mem);
1433 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1434 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1435 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1436 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1437 emit_jump_insn (gen_rtx_SET (VOIDmode,
1438 pc_rtx,
1439 gen_rtx_IF_THEN_ELSE (VOIDmode,
1440 cond,
1441 gen_rtx_LABEL_REF
1442 (VOIDmode,
1443 end_label),
1444 pc_rtx)));
1445 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1446 emit_jump_insn (gen_rtx_SET (VOIDmode,
1447 pc_rtx,
1448 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1449 emit_barrier ();
1450 emit_label (end_label);
1451 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1452 emit_insn (gen_subsi3 (result, scratch_string, addr));
1453 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1454 DONE;
1455 })
1456 \f
1457 ;; Fixed-point arithmetic insns.
1459 (define_expand "add<mode>3"
1460 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1461 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1462 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1463 ""
1464 {
1465 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1466 {
1467 rtx lo0 = gen_lowpart (SImode, operands[0]);
1468 rtx lo1 = gen_lowpart (SImode, operands[1]);
1469 rtx lo2 = gen_lowpart (SImode, operands[2]);
1470 rtx hi0 = gen_highpart (SImode, operands[0]);
1471 rtx hi1 = gen_highpart (SImode, operands[1]);
1472 rtx hi2 = gen_highpart_mode (SImode, DImode, operands[2]);
1474 if (!reg_or_short_operand (lo2, SImode))
1475 lo2 = force_reg (SImode, lo2);
1476 if (!adde_operand (hi2, SImode))
1477 hi2 = force_reg (SImode, hi2);
1479 emit_insn (gen_addsi3_carry (lo0, lo1, lo2));
1480 emit_insn (gen_addsi3_carry_in (hi0, hi1, hi2));
1481 DONE;
1482 }
1484 if (CONST_INT_P (operands[2]) && !add_operand (operands[2], <MODE>mode))
1485 {
1486 rtx tmp = ((!can_create_pseudo_p ()
1487 || rtx_equal_p (operands[0], operands[1]))
1488 ? operands[0] : gen_reg_rtx (<MODE>mode));
1490 HOST_WIDE_INT val = INTVAL (operands[2]);
1491 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1492 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1494 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1495 FAIL;
1497 /* The ordering here is important for the prolog expander.
1498 When space is allocated from the stack, adding 'low' first may
1499 produce a temporary deallocation (which would be bad). */
1500 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1501 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1502 DONE;
1503 }
1504 })
1506 (define_insn "*add<mode>3"
1507 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r")
1508 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b")
1509 (match_operand:GPR 2 "add_operand" "r,I,L")))]
1510 ""
1511 "@
1512 add %0,%1,%2
1513 addi %0,%1,%2
1514 addis %0,%1,%v2"
1515 [(set_attr "type" "add")])
1517 (define_insn "addsi3_high"
1518 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1519 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1520 (high:SI (match_operand 2 "" ""))))]
1521 "TARGET_MACHO && !TARGET_64BIT"
1522 "addis %0,%1,ha16(%2)"
1523 [(set_attr "type" "add")])
1525 (define_insn_and_split "*add<mode>3_dot"
1526 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1527 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
1528 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
1529 (const_int 0)))
1530 (clobber (match_scratch:GPR 0 "=r,r"))]
1531 "<MODE>mode == Pmode"
1532 "@
1533 add. %0,%1,%2
1534 #"
1535 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1536 [(set (match_dup 0)
1537 (plus:GPR (match_dup 1)
1538 (match_dup 2)))
1539 (set (match_dup 3)
1540 (compare:CC (match_dup 0)
1541 (const_int 0)))]
1542 ""
1543 [(set_attr "type" "add")
1544 (set_attr "dot" "yes")
1545 (set_attr "length" "4,8")])
1547 (define_insn_and_split "*add<mode>3_dot2"
1548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1549 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
1550 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
1551 (const_int 0)))
1552 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1553 (plus:GPR (match_dup 1)
1554 (match_dup 2)))]
1555 "<MODE>mode == Pmode"
1556 "@
1557 add. %0,%1,%2
1558 #"
1559 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1560 [(set (match_dup 0)
1561 (plus:GPR (match_dup 1)
1562 (match_dup 2)))
1563 (set (match_dup 3)
1564 (compare:CC (match_dup 0)
1565 (const_int 0)))]
1566 ""
1567 [(set_attr "type" "add")
1568 (set_attr "dot" "yes")
1569 (set_attr "length" "4,8")])
1571 (define_insn_and_split "*add<mode>3_imm_dot"
1572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1573 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b")
1574 (match_operand:GPR 2 "short_cint_operand" "I,I"))
1575 (const_int 0)))
1576 (clobber (match_scratch:GPR 0 "=r,r"))
1577 (clobber (reg:GPR CA_REGNO))]
1578 "<MODE>mode == Pmode"
1579 "@
1580 addic. %0,%1,%2
1581 #"
1582 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1583 [(set (match_dup 0)
1584 (plus:GPR (match_dup 1)
1585 (match_dup 2)))
1586 (set (match_dup 3)
1587 (compare:CC (match_dup 0)
1588 (const_int 0)))]
1589 ""
1590 [(set_attr "type" "add")
1591 (set_attr "dot" "yes")
1592 (set_attr "length" "4,8")])
1594 (define_insn_and_split "*add<mode>3_imm_dot2"
1595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1596 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b")
1597 (match_operand:GPR 2 "short_cint_operand" "I,I"))
1598 (const_int 0)))
1599 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1600 (plus:GPR (match_dup 1)
1601 (match_dup 2)))
1602 (clobber (reg:GPR CA_REGNO))]
1603 "<MODE>mode == Pmode"
1604 "@
1605 addic. %0,%1,%2
1606 #"
1607 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1608 [(set (match_dup 0)
1609 (plus:GPR (match_dup 1)
1610 (match_dup 2)))
1611 (set (match_dup 3)
1612 (compare:CC (match_dup 0)
1613 (const_int 0)))]
1614 ""
1615 [(set_attr "type" "add")
1616 (set_attr "dot" "yes")
1617 (set_attr "length" "4,8")])
1619 ;; Split an add that we can't do in one insn into two insns, each of which
1620 ;; does one 16-bit part. This is used by combine. Note that the low-order
1621 ;; add should be last in case the result gets used in an address.
1623 (define_split
1624 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1625 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1626 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1627 ""
1628 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1629 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1630 {
1631 HOST_WIDE_INT val = INTVAL (operands[2]);
1632 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1633 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1635 operands[4] = GEN_INT (low);
1636 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1637 operands[3] = GEN_INT (rest);
1638 else if (can_create_pseudo_p ())
1639 {
1640 operands[3] = gen_reg_rtx (DImode);
1641 emit_move_insn (operands[3], operands[2]);
1642 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1643 DONE;
1644 }
1645 else
1646 FAIL;
1647 })
1650 (define_insn "add<mode>3_carry"
1651 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1652 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1653 (match_operand:P 2 "reg_or_short_operand" "rI")))
1654 (set (reg:P CA_REGNO)
1655 (ltu:P (plus:P (match_dup 1)
1656 (match_dup 2))
1657 (match_dup 1)))]
1658 ""
1659 "add%I2c %0,%1,%2"
1660 [(set_attr "type" "add")])
1662 (define_insn "*add<mode>3_imm_carry_pos"
1663 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1664 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1665 (match_operand:P 2 "short_cint_operand" "n")))
1666 (set (reg:P CA_REGNO)
1667 (geu:P (match_dup 1)
1668 (match_operand:P 3 "const_int_operand" "n")))]
1669 "INTVAL (operands[2]) > 0
1670 && INTVAL (operands[2]) + INTVAL (operands[3]) == 0"
1671 "addic %0,%1,%2"
1672 [(set_attr "type" "add")])
1674 (define_insn "*add<mode>3_imm_carry_0"
1675 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1676 (match_operand:P 1 "gpc_reg_operand" "r"))
1677 (set (reg:P CA_REGNO)
1678 (const_int 0))]
1679 ""
1680 "addic %0,%1,0"
1681 [(set_attr "type" "add")])
1683 (define_insn "*add<mode>3_imm_carry_m1"
1684 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1685 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1686 (const_int -1)))
1687 (set (reg:P CA_REGNO)
1688 (ne:P (match_dup 1)
1689 (const_int 0)))]
1690 ""
1691 "addic %0,%1,-1"
1692 [(set_attr "type" "add")])
1694 (define_insn "*add<mode>3_imm_carry_neg"
1695 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1696 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1697 (match_operand:P 2 "short_cint_operand" "n")))
1698 (set (reg:P CA_REGNO)
1699 (gtu:P (match_dup 1)
1700 (match_operand:P 3 "const_int_operand" "n")))]
1701 "INTVAL (operands[2]) < 0
1702 && INTVAL (operands[2]) + INTVAL (operands[3]) == -1"
1703 "addic %0,%1,%2"
1704 [(set_attr "type" "add")])
1707 (define_expand "add<mode>3_carry_in"
1708 [(parallel [
1709 (set (match_operand:GPR 0 "gpc_reg_operand")
1710 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand")
1711 (match_operand:GPR 2 "adde_operand"))
1712 (reg:GPR CA_REGNO)))
1713 (clobber (reg:GPR CA_REGNO))])]
1714 ""
1715 {
1716 if (operands[2] == const0_rtx)
1717 {
1718 emit_insn (gen_add<mode>3_carry_in_0 (operands[0], operands[1]));
1719 DONE;
1720 }
1721 if (operands[2] == constm1_rtx)
1722 {
1723 emit_insn (gen_add<mode>3_carry_in_m1 (operands[0], operands[1]));
1724 DONE;
1725 }
1726 })
1728 (define_insn "*add<mode>3_carry_in_internal"
1729 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1730 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1731 (match_operand:GPR 2 "gpc_reg_operand" "r"))
1732 (reg:GPR CA_REGNO)))
1733 (clobber (reg:GPR CA_REGNO))]
1734 ""
1735 "adde %0,%1,%2"
1736 [(set_attr "type" "add")])
1738 (define_insn "add<mode>3_carry_in_0"
1739 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1740 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1741 (reg:GPR CA_REGNO)))
1742 (clobber (reg:GPR CA_REGNO))]
1743 ""
1744 "addze %0,%1"
1745 [(set_attr "type" "add")])
1747 (define_insn "add<mode>3_carry_in_m1"
1748 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1749 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1750 (reg:GPR CA_REGNO))
1751 (const_int -1)))
1752 (clobber (reg:GPR CA_REGNO))]
1753 ""
1754 "addme %0,%1"
1755 [(set_attr "type" "add")])
1758 (define_expand "one_cmpl<mode>2"
1759 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1760 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1761 ""
1762 {
1763 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1764 {
1765 rs6000_split_logical (operands, NOT, false, false, false);
1766 DONE;
1767 }
1768 })
1770 (define_insn "*one_cmpl<mode>2"
1771 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1772 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1773 ""
1774 "not %0,%1")
1776 (define_insn_and_split "*one_cmpl<mode>2_dot"
1777 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1778 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1779 (const_int 0)))
1780 (clobber (match_scratch:GPR 0 "=r,r"))]
1781 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1782 "@
1783 not. %0,%1
1784 #"
1785 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1786 [(set (match_dup 0)
1787 (not:GPR (match_dup 1)))
1788 (set (match_dup 2)
1789 (compare:CC (match_dup 0)
1790 (const_int 0)))]
1791 ""
1792 [(set_attr "type" "logical")
1793 (set_attr "dot" "yes")
1794 (set_attr "length" "4,8")])
1796 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1797 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1798 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1799 (const_int 0)))
1800 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1801 (not:GPR (match_dup 1)))]
1802 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1803 "@
1804 not. %0,%1
1805 #"
1806 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1807 [(set (match_dup 0)
1808 (not:GPR (match_dup 1)))
1809 (set (match_dup 2)
1810 (compare:CC (match_dup 0)
1811 (const_int 0)))]
1812 ""
1813 [(set_attr "type" "logical")
1814 (set_attr "dot" "yes")
1815 (set_attr "length" "4,8")])
1818 (define_expand "sub<mode>3"
1819 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1820 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1821 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1822 ""
1823 {
1824 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1825 {
1826 rtx lo0 = gen_lowpart (SImode, operands[0]);
1827 rtx lo1 = gen_lowpart (SImode, operands[1]);
1828 rtx lo2 = gen_lowpart (SImode, operands[2]);
1829 rtx hi0 = gen_highpart (SImode, operands[0]);
1830 rtx hi1 = gen_highpart_mode (SImode, DImode, operands[1]);
1831 rtx hi2 = gen_highpart (SImode, operands[2]);
1833 if (!reg_or_short_operand (lo1, SImode))
1834 lo1 = force_reg (SImode, lo1);
1835 if (!adde_operand (hi1, SImode))
1836 hi1 = force_reg (SImode, hi1);
1838 emit_insn (gen_subfsi3_carry (lo0, lo2, lo1));
1839 emit_insn (gen_subfsi3_carry_in (hi0, hi2, hi1));
1840 DONE;
1841 }
1843 if (short_cint_operand (operands[1], <MODE>mode))
1844 {
1845 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1846 DONE;
1847 }
1848 })
1850 (define_insn "*subf<mode>3"
1851 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1852 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1853 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1854 ""
1855 "subf %0,%1,%2"
1856 [(set_attr "type" "add")])
1858 (define_insn_and_split "*subf<mode>3_dot"
1859 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1860 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1861 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1862 (const_int 0)))
1863 (clobber (match_scratch:GPR 0 "=r,r"))]
1864 "<MODE>mode == Pmode"
1865 "@
1866 subf. %0,%1,%2
1867 #"
1868 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1869 [(set (match_dup 0)
1870 (minus:GPR (match_dup 2)
1871 (match_dup 1)))
1872 (set (match_dup 3)
1873 (compare:CC (match_dup 0)
1874 (const_int 0)))]
1875 ""
1876 [(set_attr "type" "add")
1877 (set_attr "dot" "yes")
1878 (set_attr "length" "4,8")])
1880 (define_insn_and_split "*subf<mode>3_dot2"
1881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1882 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1883 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1884 (const_int 0)))
1885 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1886 (minus:GPR (match_dup 2)
1887 (match_dup 1)))]
1888 "<MODE>mode == Pmode"
1889 "@
1890 subf. %0,%1,%2
1891 #"
1892 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1893 [(set (match_dup 0)
1894 (minus:GPR (match_dup 2)
1895 (match_dup 1)))
1896 (set (match_dup 3)
1897 (compare:CC (match_dup 0)
1898 (const_int 0)))]
1899 ""
1900 [(set_attr "type" "add")
1901 (set_attr "dot" "yes")
1902 (set_attr "length" "4,8")])
1904 (define_insn "subf<mode>3_imm"
1905 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1906 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
1907 (match_operand:GPR 1 "gpc_reg_operand" "r")))
1908 (clobber (reg:GPR CA_REGNO))]
1909 ""
1910 "subfic %0,%1,%2"
1911 [(set_attr "type" "add")])
1914 (define_insn "subf<mode>3_carry"
1915 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1916 (minus:P (match_operand:P 2 "reg_or_short_operand" "rI")
1917 (match_operand:P 1 "gpc_reg_operand" "r")))
1918 (set (reg:P CA_REGNO)
1919 (leu:P (match_dup 1)
1920 (match_dup 2)))]
1921 ""
1922 "subf%I2c %0,%1,%2"
1923 [(set_attr "type" "add")])
1925 (define_insn "*subf<mode>3_imm_carry_0"
1926 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1927 (neg:P (match_operand:P 1 "gpc_reg_operand" "r")))
1928 (set (reg:P CA_REGNO)
1929 (eq:P (match_dup 1)
1930 (const_int 0)))]
1931 ""
1932 "subfic %0,%1,0"
1933 [(set_attr "type" "add")])
1935 (define_insn "*subf<mode>3_imm_carry_m1"
1936 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1937 (not:P (match_operand:P 1 "gpc_reg_operand" "r")))
1938 (set (reg:P CA_REGNO)
1939 (const_int 1))]
1940 ""
1941 "subfic %0,%1,-1"
1942 [(set_attr "type" "add")])
1945 (define_expand "subf<mode>3_carry_in"
1946 [(parallel [
1947 (set (match_operand:GPR 0 "gpc_reg_operand")
1948 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand"))
1949 (reg:GPR CA_REGNO))
1950 (match_operand:GPR 2 "adde_operand")))
1951 (clobber (reg:GPR CA_REGNO))])]
1952 ""
1953 {
1954 if (operands[2] == const0_rtx)
1955 {
1956 emit_insn (gen_subf<mode>3_carry_in_0 (operands[0], operands[1]));
1957 DONE;
1958 }
1959 if (operands[2] == constm1_rtx)
1960 {
1961 emit_insn (gen_subf<mode>3_carry_in_m1 (operands[0], operands[1]));
1962 DONE;
1963 }
1964 })
1966 (define_insn "*subf<mode>3_carry_in_internal"
1967 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1968 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
1969 (reg:GPR CA_REGNO))
1970 (match_operand:GPR 2 "gpc_reg_operand" "r")))
1971 (clobber (reg:GPR CA_REGNO))]
1972 ""
1973 "subfe %0,%1,%2"
1974 [(set_attr "type" "add")])
1976 (define_insn "subf<mode>3_carry_in_0"
1977 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1978 (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
1979 (reg:GPR CA_REGNO)))
1980 (clobber (reg:GPR CA_REGNO))]
1981 ""
1982 "subfze %0,%1"
1983 [(set_attr "type" "add")])
1985 (define_insn "subf<mode>3_carry_in_m1"
1986 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1987 (plus:GPR (minus:GPR (reg:GPR CA_REGNO)
1988 (match_operand:GPR 1 "gpc_reg_operand" "r"))
1989 (const_int -2)))
1990 (clobber (reg:GPR CA_REGNO))]
1991 ""
1992 "subfme %0,%1"
1993 [(set_attr "type" "add")])
1995 (define_insn "subf<mode>3_carry_in_xx"
1996 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1997 (plus:GPR (reg:GPR CA_REGNO)
1998 (const_int -1)))
1999 (clobber (reg:GPR CA_REGNO))]
2000 ""
2001 "subfe %0,%0,%0"
2002 [(set_attr "type" "add")])
2005 (define_insn "neg<mode>2"
2006 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2007 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2008 ""
2009 "neg %0,%1"
2010 [(set_attr "type" "add")])
2012 (define_insn_and_split "*neg<mode>2_dot"
2013 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2014 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
2015 (const_int 0)))
2016 (clobber (match_scratch:GPR 0 "=r,r"))]
2017 "<MODE>mode == Pmode"
2018 "@
2019 neg. %0,%1
2020 #"
2021 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
2022 [(set (match_dup 0)
2023 (neg:GPR (match_dup 1)))
2024 (set (match_dup 2)
2025 (compare:CC (match_dup 0)
2026 (const_int 0)))]
2027 ""
2028 [(set_attr "type" "add")
2029 (set_attr "dot" "yes")
2030 (set_attr "length" "4,8")])
2032 (define_insn_and_split "*neg<mode>2_dot2"
2033 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2034 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
2035 (const_int 0)))
2036 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2037 (neg:GPR (match_dup 1)))]
2038 "<MODE>mode == Pmode"
2039 "@
2040 neg. %0,%1
2041 #"
2042 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
2043 [(set (match_dup 0)
2044 (neg:GPR (match_dup 1)))
2045 (set (match_dup 2)
2046 (compare:CC (match_dup 0)
2047 (const_int 0)))]
2048 ""
2049 [(set_attr "type" "add")
2050 (set_attr "dot" "yes")
2051 (set_attr "length" "4,8")])
2054 (define_insn "clz<mode>2"
2055 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2056 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2057 ""
2058 "cntlz<wd> %0,%1"
2059 [(set_attr "type" "cntlz")])
2061 (define_expand "ctz<mode>2"
2062 [(set (match_dup 2)
2063 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2064 (set (match_dup 3)
2065 (and:GPR (match_dup 1)
2066 (match_dup 2)))
2067 (set (match_dup 4)
2068 (clz:GPR (match_dup 3)))
2069 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2070 (minus:GPR (match_dup 5)
2071 (match_dup 4)))
2072 (clobber (reg:GPR CA_REGNO))])]
2073 ""
2074 {
2075 operands[2] = gen_reg_rtx (<MODE>mode);
2076 operands[3] = gen_reg_rtx (<MODE>mode);
2077 operands[4] = gen_reg_rtx (<MODE>mode);
2078 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2079 })
2081 (define_expand "ffs<mode>2"
2082 [(set (match_dup 2)
2083 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2084 (set (match_dup 3)
2085 (and:GPR (match_dup 1)
2086 (match_dup 2)))
2087 (set (match_dup 4)
2088 (clz:GPR (match_dup 3)))
2089 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2090 (minus:GPR (match_dup 5)
2091 (match_dup 4)))
2092 (clobber (reg:GPR CA_REGNO))])]
2093 ""
2094 {
2095 operands[2] = gen_reg_rtx (<MODE>mode);
2096 operands[3] = gen_reg_rtx (<MODE>mode);
2097 operands[4] = gen_reg_rtx (<MODE>mode);
2098 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2099 })
2102 (define_expand "popcount<mode>2"
2103 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2104 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2105 "TARGET_POPCNTB || TARGET_POPCNTD"
2106 {
2107 rs6000_emit_popcount (operands[0], operands[1]);
2108 DONE;
2109 })
2111 (define_insn "popcntb<mode>2"
2112 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2113 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2114 UNSPEC_POPCNTB))]
2115 "TARGET_POPCNTB"
2116 "popcntb %0,%1"
2117 [(set_attr "type" "popcnt")])
2119 (define_insn "popcntd<mode>2"
2120 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2121 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2122 "TARGET_POPCNTD"
2123 "popcnt<wd> %0,%1"
2124 [(set_attr "type" "popcnt")])
2127 (define_expand "parity<mode>2"
2128 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2129 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2130 "TARGET_POPCNTB"
2131 {
2132 rs6000_emit_parity (operands[0], operands[1]);
2133 DONE;
2134 })
2136 (define_insn "parity<mode>2_cmpb"
2137 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2138 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2139 "TARGET_CMPB && TARGET_POPCNTB"
2140 "prty<wd> %0,%1"
2141 [(set_attr "type" "popcnt")])
2144 ;; Since the hardware zeros the upper part of the register, save generating the
2145 ;; AND immediate if we are converting to unsigned
2146 (define_insn "*bswaphi2_extenddi"
2147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2148 (zero_extend:DI
2149 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2150 "TARGET_POWERPC64"
2151 "lhbrx %0,%y1"
2152 [(set_attr "length" "4")
2153 (set_attr "type" "load")])
2155 (define_insn "*bswaphi2_extendsi"
2156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2157 (zero_extend:SI
2158 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2159 ""
2160 "lhbrx %0,%y1"
2161 [(set_attr "length" "4")
2162 (set_attr "type" "load")])
2164 (define_expand "bswaphi2"
2165 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2166 (bswap:HI
2167 (match_operand:HI 1 "reg_or_mem_operand" "")))
2168 (clobber (match_scratch:SI 2 ""))])]
2169 ""
2170 {
2171 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2172 operands[1] = force_reg (HImode, operands[1]);
2173 })
2175 (define_insn "bswaphi2_internal"
2176 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2177 (bswap:HI
2178 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2179 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2180 ""
2181 "@
2182 lhbrx %0,%y1
2183 sthbrx %1,%y0
2184 #"
2185 [(set_attr "length" "4,4,12")
2186 (set_attr "type" "load,store,*")])
2188 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2189 ;; correct for -mlittle as well as -mbig.
2190 (define_split
2191 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2192 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2193 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2194 "reload_completed"
2195 [(set (match_dup 3)
2196 (zero_extract:SI (match_dup 4)
2197 (const_int 8)
2198 (const_int 16)))
2199 (set (match_dup 2)
2200 (and:SI (ashift:SI (match_dup 4)
2201 (const_int 8))
2202 (const_int 65280))) ;; 0xff00
2203 (set (match_dup 3)
2204 (ior:SI (match_dup 3)
2205 (match_dup 2)))]
2206 "
2207 {
2208 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2209 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2210 }")
2212 (define_insn "*bswapsi2_extenddi"
2213 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2214 (zero_extend:DI
2215 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2216 "TARGET_POWERPC64"
2217 "lwbrx %0,%y1"
2218 [(set_attr "length" "4")
2219 (set_attr "type" "load")])
2221 (define_expand "bswapsi2"
2222 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2223 (bswap:SI
2224 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2225 ""
2226 {
2227 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2228 operands[1] = force_reg (SImode, operands[1]);
2229 })
2231 (define_insn "*bswapsi2_internal"
2232 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2233 (bswap:SI
2234 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2235 ""
2236 "@
2237 lwbrx %0,%y1
2238 stwbrx %1,%y0
2239 #"
2240 [(set_attr "length" "4,4,12")
2241 (set_attr "type" "load,store,*")])
2243 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2244 ;; zero_extract insns do not change for -mlittle.
2245 (define_split
2246 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2247 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2248 "reload_completed"
2249 [(set (match_dup 0)
2250 (rotate:SI (match_dup 1) (const_int 8)))
2251 (set (zero_extract:SI (match_dup 0)
2252 (const_int 8)
2253 (const_int 0))
2254 (match_dup 1))
2255 (set (zero_extract:SI (match_dup 0)
2256 (const_int 8)
2257 (const_int 16))
2258 (rotate:SI (match_dup 1)
2259 (const_int 16)))]
2260 "")
2262 (define_expand "bswapdi2"
2263 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2264 (bswap:DI
2265 (match_operand:DI 1 "reg_or_mem_operand" "")))
2266 (clobber (match_scratch:DI 2 ""))
2267 (clobber (match_scratch:DI 3 ""))
2268 (clobber (match_scratch:DI 4 ""))])]
2269 ""
2270 {
2271 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2272 operands[1] = force_reg (DImode, operands[1]);
2274 if (!TARGET_POWERPC64)
2275 {
2276 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2277 that uses 64-bit registers needs the same scratch registers as 64-bit
2278 mode. */
2279 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2280 DONE;
2281 }
2282 })
2284 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2285 (define_insn "*bswapdi2_ldbrx"
2286 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2287 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2288 (clobber (match_scratch:DI 2 "=X,X,&r"))
2289 (clobber (match_scratch:DI 3 "=X,X,&r"))
2290 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2291 "TARGET_POWERPC64 && TARGET_LDBRX
2292 && (REG_P (operands[0]) || REG_P (operands[1]))"
2293 "@
2294 ldbrx %0,%y1
2295 stdbrx %1,%y0
2296 #"
2297 [(set_attr "length" "4,4,36")
2298 (set_attr "type" "load,store,*")])
2300 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2301 (define_insn "*bswapdi2_64bit"
2302 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2303 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2304 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2305 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2306 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2307 "TARGET_POWERPC64 && !TARGET_LDBRX
2308 && (REG_P (operands[0]) || REG_P (operands[1]))
2309 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2310 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2311 "#"
2312 [(set_attr "length" "16,12,36")])
2314 (define_split
2315 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2316 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2317 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2318 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2319 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2320 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2321 [(const_int 0)]
2322 "
2323 {
2324 rtx dest = operands[0];
2325 rtx src = operands[1];
2326 rtx op2 = operands[2];
2327 rtx op3 = operands[3];
2328 rtx op4 = operands[4];
2329 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2330 BYTES_BIG_ENDIAN ? 4 : 0);
2331 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2332 BYTES_BIG_ENDIAN ? 4 : 0);
2333 rtx addr1;
2334 rtx addr2;
2335 rtx word_high;
2336 rtx word_low;
2338 addr1 = XEXP (src, 0);
2339 if (GET_CODE (addr1) == PLUS)
2340 {
2341 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2342 if (TARGET_AVOID_XFORM)
2343 {
2344 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2345 addr2 = op2;
2346 }
2347 else
2348 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2349 }
2350 else if (TARGET_AVOID_XFORM)
2351 {
2352 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2353 addr2 = op2;
2354 }
2355 else
2356 {
2357 emit_move_insn (op2, GEN_INT (4));
2358 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2359 }
2361 if (BYTES_BIG_ENDIAN)
2362 {
2363 word_high = change_address (src, SImode, addr1);
2364 word_low = change_address (src, SImode, addr2);
2365 }
2366 else
2367 {
2368 word_high = change_address (src, SImode, addr2);
2369 word_low = change_address (src, SImode, addr1);
2370 }
2372 emit_insn (gen_bswapsi2 (op3_32, word_low));
2373 emit_insn (gen_bswapsi2 (op4_32, word_high));
2374 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2375 emit_insn (gen_iordi3 (dest, dest, op4));
2376 DONE;
2377 }")
2379 (define_split
2380 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2381 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2382 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2383 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2384 (clobber (match_operand:DI 4 "" ""))]
2385 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2386 [(const_int 0)]
2387 "
2388 {
2389 rtx dest = operands[0];
2390 rtx src = operands[1];
2391 rtx op2 = operands[2];
2392 rtx op3 = operands[3];
2393 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2394 BYTES_BIG_ENDIAN ? 4 : 0);
2395 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2396 BYTES_BIG_ENDIAN ? 4 : 0);
2397 rtx addr1;
2398 rtx addr2;
2399 rtx word_high;
2400 rtx word_low;
2402 addr1 = XEXP (dest, 0);
2403 if (GET_CODE (addr1) == PLUS)
2404 {
2405 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2406 if (TARGET_AVOID_XFORM)
2407 {
2408 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2409 addr2 = op2;
2410 }
2411 else
2412 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2413 }
2414 else if (TARGET_AVOID_XFORM)
2415 {
2416 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2417 addr2 = op2;
2418 }
2419 else
2420 {
2421 emit_move_insn (op2, GEN_INT (4));
2422 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2423 }
2425 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2426 if (BYTES_BIG_ENDIAN)
2427 {
2428 word_high = change_address (dest, SImode, addr1);
2429 word_low = change_address (dest, SImode, addr2);
2430 }
2431 else
2432 {
2433 word_high = change_address (dest, SImode, addr2);
2434 word_low = change_address (dest, SImode, addr1);
2435 }
2436 emit_insn (gen_bswapsi2 (word_high, src_si));
2437 emit_insn (gen_bswapsi2 (word_low, op3_si));
2438 DONE;
2439 }")
2441 (define_split
2442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2443 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2444 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2445 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2446 (clobber (match_operand:DI 4 "" ""))]
2447 "TARGET_POWERPC64 && reload_completed"
2448 [(const_int 0)]
2449 "
2450 {
2451 rtx dest = operands[0];
2452 rtx src = operands[1];
2453 rtx op2 = operands[2];
2454 rtx op3 = operands[3];
2455 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2456 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2457 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2458 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2459 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2461 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2462 emit_insn (gen_bswapsi2 (dest_si, src_si));
2463 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2464 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2465 emit_insn (gen_iordi3 (dest, dest, op3));
2466 DONE;
2467 }")
2469 (define_insn "bswapdi2_32bit"
2470 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2471 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2472 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2473 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2474 "#"
2475 [(set_attr "length" "16,12,36")])
2477 (define_split
2478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2479 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2480 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2481 "!TARGET_POWERPC64 && reload_completed"
2482 [(const_int 0)]
2483 "
2484 {
2485 rtx dest = operands[0];
2486 rtx src = operands[1];
2487 rtx op2 = operands[2];
2488 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2489 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2490 rtx addr1;
2491 rtx addr2;
2492 rtx word1;
2493 rtx word2;
2495 addr1 = XEXP (src, 0);
2496 if (GET_CODE (addr1) == PLUS)
2497 {
2498 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2499 if (TARGET_AVOID_XFORM)
2500 {
2501 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2502 addr2 = op2;
2503 }
2504 else
2505 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2506 }
2507 else if (TARGET_AVOID_XFORM)
2508 {
2509 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2510 addr2 = op2;
2511 }
2512 else
2513 {
2514 emit_move_insn (op2, GEN_INT (4));
2515 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2516 }
2518 word1 = change_address (src, SImode, addr1);
2519 word2 = change_address (src, SImode, addr2);
2521 emit_insn (gen_bswapsi2 (dest2, word1));
2522 emit_insn (gen_bswapsi2 (dest1, word2));
2523 DONE;
2524 }")
2526 (define_split
2527 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2528 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2529 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2530 "!TARGET_POWERPC64 && reload_completed"
2531 [(const_int 0)]
2532 "
2533 {
2534 rtx dest = operands[0];
2535 rtx src = operands[1];
2536 rtx op2 = operands[2];
2537 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2538 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2539 rtx addr1;
2540 rtx addr2;
2541 rtx word1;
2542 rtx word2;
2544 addr1 = XEXP (dest, 0);
2545 if (GET_CODE (addr1) == PLUS)
2546 {
2547 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2548 if (TARGET_AVOID_XFORM)
2549 {
2550 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2551 addr2 = op2;
2552 }
2553 else
2554 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2555 }
2556 else if (TARGET_AVOID_XFORM)
2557 {
2558 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2559 addr2 = op2;
2560 }
2561 else
2562 {
2563 emit_move_insn (op2, GEN_INT (4));
2564 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2565 }
2567 word1 = change_address (dest, SImode, addr1);
2568 word2 = change_address (dest, SImode, addr2);
2570 emit_insn (gen_bswapsi2 (word2, src1));
2571 emit_insn (gen_bswapsi2 (word1, src2));
2572 DONE;
2573 }")
2575 (define_split
2576 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2577 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2578 (clobber (match_operand:SI 2 "" ""))]
2579 "!TARGET_POWERPC64 && reload_completed"
2580 [(const_int 0)]
2581 "
2582 {
2583 rtx dest = operands[0];
2584 rtx src = operands[1];
2585 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2586 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2587 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2588 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2590 emit_insn (gen_bswapsi2 (dest1, src2));
2591 emit_insn (gen_bswapsi2 (dest2, src1));
2592 DONE;
2593 }")
2596 (define_insn "mul<mode>3"
2597 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2598 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2599 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2600 ""
2601 "@
2602 mull<wd> %0,%1,%2
2603 mulli %0,%1,%2"
2604 [(set_attr "type" "mul")
2605 (set (attr "size")
2606 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2607 (const_string "8")
2608 (match_operand:GPR 2 "short_cint_operand" "")
2609 (const_string "16")]
2610 (const_string "<bits>")))])
2612 (define_insn_and_split "*mul<mode>3_dot"
2613 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2614 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2615 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2616 (const_int 0)))
2617 (clobber (match_scratch:GPR 0 "=r,r"))]
2618 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2619 "@
2620 mull<wd>. %0,%1,%2
2621 #"
2622 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2623 [(set (match_dup 0)
2624 (mult:GPR (match_dup 1)
2625 (match_dup 2)))
2626 (set (match_dup 3)
2627 (compare:CC (match_dup 0)
2628 (const_int 0)))]
2629 ""
2630 [(set_attr "type" "mul")
2631 (set_attr "size" "<bits>")
2632 (set_attr "dot" "yes")
2633 (set_attr "length" "4,8")])
2635 (define_insn_and_split "*mul<mode>3_dot2"
2636 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2637 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2638 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2639 (const_int 0)))
2640 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2641 (mult:GPR (match_dup 1)
2642 (match_dup 2)))]
2643 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2644 "@
2645 mull<wd>. %0,%1,%2
2646 #"
2647 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2648 [(set (match_dup 0)
2649 (mult:GPR (match_dup 1)
2650 (match_dup 2)))
2651 (set (match_dup 3)
2652 (compare:CC (match_dup 0)
2653 (const_int 0)))]
2654 ""
2655 [(set_attr "type" "mul")
2656 (set_attr "size" "<bits>")
2657 (set_attr "dot" "yes")
2658 (set_attr "length" "4,8")])
2661 (define_expand "<su>mul<mode>3_highpart"
2662 [(set (match_operand:GPR 0 "gpc_reg_operand")
2663 (subreg:GPR
2664 (mult:<DMODE> (any_extend:<DMODE>
2665 (match_operand:GPR 1 "gpc_reg_operand"))
2666 (any_extend:<DMODE>
2667 (match_operand:GPR 2 "gpc_reg_operand")))
2668 0))]
2669 ""
2670 {
2671 if (<MODE>mode == SImode && TARGET_POWERPC64)
2672 {
2673 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2674 operands[2]));
2675 DONE;
2676 }
2678 if (!WORDS_BIG_ENDIAN)
2679 {
2680 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2681 operands[2]));
2682 DONE;
2683 }
2684 })
2686 (define_insn "*<su>mul<mode>3_highpart"
2687 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2688 (subreg:GPR
2689 (mult:<DMODE> (any_extend:<DMODE>
2690 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2691 (any_extend:<DMODE>
2692 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2693 0))]
2694 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2695 "mulh<wd><u> %0,%1,%2"
2696 [(set_attr "type" "mul")
2697 (set_attr "size" "<bits>")])
2699 (define_insn "<su>mulsi3_highpart_le"
2700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2701 (subreg:SI
2702 (mult:DI (any_extend:DI
2703 (match_operand:SI 1 "gpc_reg_operand" "r"))
2704 (any_extend:DI
2705 (match_operand:SI 2 "gpc_reg_operand" "r")))
2706 4))]
2707 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2708 "mulhw<u> %0,%1,%2"
2709 [(set_attr "type" "mul")])
2711 (define_insn "<su>muldi3_highpart_le"
2712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2713 (subreg:DI
2714 (mult:TI (any_extend:TI
2715 (match_operand:DI 1 "gpc_reg_operand" "r"))
2716 (any_extend:TI
2717 (match_operand:DI 2 "gpc_reg_operand" "r")))
2718 8))]
2719 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2720 "mulhd<u> %0,%1,%2"
2721 [(set_attr "type" "mul")
2722 (set_attr "size" "64")])
2724 (define_insn "<su>mulsi3_highpart_64"
2725 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2726 (truncate:SI
2727 (lshiftrt:DI
2728 (mult:DI (any_extend:DI
2729 (match_operand:SI 1 "gpc_reg_operand" "r"))
2730 (any_extend:DI
2731 (match_operand:SI 2 "gpc_reg_operand" "r")))
2732 (const_int 32))))]
2733 "TARGET_POWERPC64"
2734 "mulhw<u> %0,%1,%2"
2735 [(set_attr "type" "mul")])
2737 (define_expand "<u>mul<mode><dmode>3"
2738 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2739 (mult:<DMODE> (any_extend:<DMODE>
2740 (match_operand:GPR 1 "gpc_reg_operand"))
2741 (any_extend:<DMODE>
2742 (match_operand:GPR 2 "gpc_reg_operand"))))]
2743 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2744 {
2745 rtx l = gen_reg_rtx (<MODE>mode);
2746 rtx h = gen_reg_rtx (<MODE>mode);
2747 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2748 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2749 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2750 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2751 DONE;
2752 })
2755 (define_insn "udiv<mode>3"
2756 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2757 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2758 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2759 ""
2760 "div<wd>u %0,%1,%2"
2761 [(set_attr "type" "div")
2762 (set_attr "size" "<bits>")])
2765 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
2766 ;; modulus. If it isn't a power of two, force operands into register and do
2767 ;; a normal divide.
2768 (define_expand "div<mode>3"
2769 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2770 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2771 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2772 ""
2773 {
2774 if (CONST_INT_P (operands[2])
2775 && INTVAL (operands[2]) > 0
2776 && exact_log2 (INTVAL (operands[2])) >= 0)
2777 {
2778 emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
2779 DONE;
2780 }
2782 operands[2] = force_reg (<MODE>mode, operands[2]);
2783 })
2785 (define_insn "*div<mode>3"
2786 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2787 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2788 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2789 ""
2790 "div<wd> %0,%1,%2"
2791 [(set_attr "type" "div")
2792 (set_attr "size" "<bits>")])
2794 (define_insn "div<mode>3_sra"
2795 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2796 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2797 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))
2798 (clobber (reg:GPR CA_REGNO))]
2799 ""
2800 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2801 [(set_attr "type" "two")
2802 (set_attr "length" "8")])
2804 (define_insn_and_split "*div<mode>3_sra_dot"
2805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2806 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2807 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2808 (const_int 0)))
2809 (clobber (match_scratch:GPR 0 "=r,r"))
2810 (clobber (reg:GPR CA_REGNO))]
2811 "<MODE>mode == Pmode"
2812 "@
2813 sra<wd>i %0,%1,%p2\;addze. %0,%0
2814 #"
2815 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2816 [(parallel [(set (match_dup 0)
2817 (div:GPR (match_dup 1)
2818 (match_dup 2)))
2819 (clobber (reg:GPR CA_REGNO))])
2820 (set (match_dup 3)
2821 (compare:CC (match_dup 0)
2822 (const_int 0)))]
2823 ""
2824 [(set_attr "type" "two")
2825 (set_attr "length" "8,12")
2826 (set_attr "cell_micro" "not")])
2828 (define_insn_and_split "*div<mode>3_sra_dot2"
2829 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2830 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2831 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2832 (const_int 0)))
2833 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2834 (div:GPR (match_dup 1)
2835 (match_dup 2)))
2836 (clobber (reg:GPR CA_REGNO))]
2837 "<MODE>mode == Pmode"
2838 "@
2839 sra<wd>i %0,%1,%p2\;addze. %0,%0
2840 #"
2841 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2842 [(parallel [(set (match_dup 0)
2843 (div:GPR (match_dup 1)
2844 (match_dup 2)))
2845 (clobber (reg:GPR CA_REGNO))])
2846 (set (match_dup 3)
2847 (compare:CC (match_dup 0)
2848 (const_int 0)))]
2849 ""
2850 [(set_attr "type" "two")
2851 (set_attr "length" "8,12")
2852 (set_attr "cell_micro" "not")])
2854 (define_expand "mod<mode>3"
2855 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2856 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2857 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2858 ""
2859 {
2860 int i;
2861 rtx temp1;
2862 rtx temp2;
2864 if (GET_CODE (operands[2]) != CONST_INT
2865 || INTVAL (operands[2]) <= 0
2866 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2867 FAIL;
2869 temp1 = gen_reg_rtx (<MODE>mode);
2870 temp2 = gen_reg_rtx (<MODE>mode);
2872 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2873 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2874 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2875 DONE;
2876 })
2877 \f
2878 ;; Logical instructions
2879 ;; The logical instructions are mostly combined by using match_operator,
2880 ;; but the plain AND insns are somewhat different because there is no
2881 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2882 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2884 (define_expand "and<mode>3"
2885 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2886 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2887 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2888 ""
2889 {
2890 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2891 {
2892 rs6000_split_logical (operands, AND, false, false, false);
2893 DONE;
2894 }
2896 if (logical_const_operand (operands[2], <MODE>mode)
2897 && !any_mask_operand (operands[2], <MODE>mode))
2898 {
2899 if (rs6000_gen_cell_microcode)
2900 {
2901 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2902 DONE;
2903 }
2904 else
2905 operands[2] = force_reg (<MODE>mode, operands[2]);
2906 }
2908 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2909 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2910 operands[2] = force_reg (<MODE>mode, operands[2]);
2911 })
2914 (define_insn "and<mode>3_imm"
2915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2916 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2917 (match_operand:GPR 2 "logical_const_operand" "n")))
2918 (clobber (match_scratch:CC 3 "=x"))]
2919 "rs6000_gen_cell_microcode
2920 && !any_mask_operand (operands[2], <MODE>mode)"
2921 "andi%e2. %0,%1,%u2"
2922 [(set_attr "type" "logical")
2923 (set_attr "dot" "yes")])
2925 (define_insn_and_split "*and<mode>3_imm_dot"
2926 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2927 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2928 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2929 (const_int 0)))
2930 (clobber (match_scratch:GPR 0 "=r,r"))
2931 (clobber (match_scratch:CC 4 "=X,x"))]
2932 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2933 && rs6000_gen_cell_microcode
2934 && !any_mask_operand (operands[2], <MODE>mode)"
2935 "@
2936 andi%e2. %0,%1,%u2
2937 #"
2938 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2939 [(parallel [(set (match_dup 0)
2940 (and:GPR (match_dup 1)
2941 (match_dup 2)))
2942 (clobber (match_dup 4))])
2943 (set (match_dup 3)
2944 (compare:CC (match_dup 0)
2945 (const_int 0)))]
2946 ""
2947 [(set_attr "type" "logical")
2948 (set_attr "dot" "yes")
2949 (set_attr "length" "4,8")])
2951 (define_insn_and_split "*and<mode>3_imm_dot2"
2952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2953 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2954 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2955 (const_int 0)))
2956 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2957 (and:GPR (match_dup 1)
2958 (match_dup 2)))
2959 (clobber (match_scratch:CC 4 "=X,x"))]
2960 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2961 && rs6000_gen_cell_microcode
2962 && !any_mask_operand (operands[2], <MODE>mode)"
2963 "@
2964 andi%e2. %0,%1,%u2
2965 #"
2966 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2967 [(parallel [(set (match_dup 0)
2968 (and:GPR (match_dup 1)
2969 (match_dup 2)))
2970 (clobber (match_dup 4))])
2971 (set (match_dup 3)
2972 (compare:CC (match_dup 0)
2973 (const_int 0)))]
2974 ""
2975 [(set_attr "type" "logical")
2976 (set_attr "dot" "yes")
2977 (set_attr "length" "4,8")])
2979 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2981 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2982 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2983 (const_int 0)))
2984 (clobber (match_scratch:GPR 0 "=r,r"))]
2985 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2986 && rs6000_gen_cell_microcode
2987 && any_mask_operand (operands[2], <MODE>mode)"
2988 "@
2989 andi%e2. %0,%1,%u2
2990 #"
2991 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2992 [(set (match_dup 0)
2993 (and:GPR (match_dup 1)
2994 (match_dup 2)))
2995 (set (match_dup 3)
2996 (compare:CC (match_dup 0)
2997 (const_int 0)))]
2998 ""
2999 [(set_attr "type" "logical")
3000 (set_attr "dot" "yes")
3001 (set_attr "length" "4,8")])
3003 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
3004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3005 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3006 (match_operand:GPR 2 "logical_const_operand" "n,n"))
3007 (const_int 0)))
3008 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3009 (and:GPR (match_dup 1)
3010 (match_dup 2)))]
3011 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3012 && rs6000_gen_cell_microcode
3013 && any_mask_operand (operands[2], <MODE>mode)"
3014 "@
3015 andi%e2. %0,%1,%u2
3016 #"
3017 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3018 [(set (match_dup 0)
3019 (and:GPR (match_dup 1)
3020 (match_dup 2)))
3021 (set (match_dup 3)
3022 (compare:CC (match_dup 0)
3023 (const_int 0)))]
3024 ""
3025 [(set_attr "type" "logical")
3026 (set_attr "dot" "yes")
3027 (set_attr "length" "4,8")])
3030 (define_insn "*and<mode>3_mask"
3031 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3032 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3033 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
3034 ""
3035 "@
3036 rldic%B2 %0,%1,0,%S2
3037 rlwinm %0,%1,0,%m2,%M2"
3038 [(set_attr "type" "shift")])
3040 (define_insn_and_split "*and<mode>3_mask_dot"
3041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3042 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
3043 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
3044 (const_int 0)))
3045 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
3046 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3047 && rs6000_gen_cell_microcode
3048 && !logical_const_operand (operands[2], <MODE>mode)"
3049 "@
3050 rldic%B2. %0,%1,0,%S2
3051 rlwinm. %0,%1,0,%m2,%M2
3052 #
3053 #"
3054 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3055 [(set (match_dup 0)
3056 (and:GPR (match_dup 1)
3057 (match_dup 2)))
3058 (set (match_dup 3)
3059 (compare:CC (match_dup 0)
3060 (const_int 0)))]
3061 ""
3062 [(set_attr "type" "shift")
3063 (set_attr "dot" "yes")
3064 (set_attr "length" "4,4,8,8")])
3066 (define_insn_and_split "*and<mode>3_mask_dot2"
3067 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3068 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
3069 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
3070 (const_int 0)))
3071 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
3072 (and:GPR (match_dup 1)
3073 (match_dup 2)))]
3074 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3075 && rs6000_gen_cell_microcode
3076 && !logical_const_operand (operands[2], <MODE>mode)"
3077 "@
3078 rldic%B2. %0,%1,0,%S2
3079 rlwinm. %0,%1,0,%m2,%M2
3080 #
3081 #"
3082 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3083 [(set (match_dup 0)
3084 (and:GPR (match_dup 1)
3085 (match_dup 2)))
3086 (set (match_dup 3)
3087 (compare:CC (match_dup 0)
3088 (const_int 0)))]
3089 ""
3090 [(set_attr "type" "shift")
3091 (set_attr "dot" "yes")
3092 (set_attr "length" "4,4,8,8")])
3096 (define_insn "andsi3_internal0_nomc"
3097 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3098 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3099 (match_operand:SI 2 "and_operand" "?r,T")))]
3100 "!rs6000_gen_cell_microcode"
3101 "@
3102 and %0,%1,%2
3103 rlwinm %0,%1,0,%m2,%M2"
3104 [(set_attr "type" "logical,shift")])
3107 ;; Handle the PowerPC64 rlwinm corner case
3109 (define_insn_and_split "*andsi3_internal6"
3110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3111 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3112 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3113 "TARGET_POWERPC64"
3114 "#"
3115 "TARGET_POWERPC64"
3116 [(set (match_dup 0)
3117 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3118 (match_dup 4)))
3119 (set (match_dup 0)
3120 (rotate:SI (match_dup 0) (match_dup 5)))]
3121 "
3122 {
3123 int mb = extract_MB (operands[2]);
3124 int me = extract_ME (operands[2]);
3125 operands[3] = GEN_INT (me + 1);
3126 operands[5] = GEN_INT (32 - (me + 1));
3127 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3128 }"
3129 [(set_attr "length" "8")])
3132 (define_expand "<code><mode>3"
3133 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
3134 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
3135 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
3136 ""
3137 {
3138 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3139 {
3140 rs6000_split_logical (operands, <CODE>, false, false, false);
3141 DONE;
3142 }
3144 if (non_logical_cint_operand (operands[2], <MODE>mode))
3145 {
3146 rtx tmp = ((!can_create_pseudo_p ()
3147 || rtx_equal_p (operands[0], operands[1]))
3148 ? operands[0] : gen_reg_rtx (<MODE>mode));
3150 HOST_WIDE_INT value = INTVAL (operands[2]);
3151 HOST_WIDE_INT lo = value & 0xffff;
3152 HOST_WIDE_INT hi = value - lo;
3154 emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
3155 emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
3156 DONE;
3157 }
3159 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
3160 operands[2] = force_reg (<MODE>mode, operands[2]);
3161 })
3163 (define_split
3164 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3165 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3166 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
3167 ""
3168 [(set (match_dup 3)
3169 (iorxor:GPR (match_dup 1)
3170 (match_dup 4)))
3171 (set (match_dup 0)
3172 (iorxor:GPR (match_dup 3)
3173 (match_dup 5)))]
3174 {
3175 operands[3] = ((!can_create_pseudo_p ()
3176 || rtx_equal_p (operands[0], operands[1]))
3177 ? operands[0] : gen_reg_rtx (<MODE>mode));
3179 HOST_WIDE_INT value = INTVAL (operands[2]);
3180 HOST_WIDE_INT lo = value & 0xffff;
3181 HOST_WIDE_INT hi = value - lo;
3183 operands[4] = GEN_INT (hi);
3184 operands[5] = GEN_INT (lo);
3185 })
3187 (define_insn "*bool<mode>3_imm"
3188 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3189 (match_operator:GPR 3 "boolean_or_operator"
3190 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
3191 (match_operand:GPR 2 "logical_const_operand" "n")]))]
3192 ""
3193 "%q3i%e2 %0,%1,%u2"
3194 [(set_attr "type" "logical")])
3196 (define_insn "*bool<mode>3"
3197 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3198 (match_operator:GPR 3 "boolean_operator"
3199 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3200 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
3201 ""
3202 "%q3 %0,%1,%2"
3203 [(set_attr "type" "logical")])
3205 (define_insn_and_split "*bool<mode>3_dot"
3206 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3207 (compare:CC (match_operator:GPR 3 "boolean_operator"
3208 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3209 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3210 (const_int 0)))
3211 (clobber (match_scratch:GPR 0 "=r,r"))]
3212 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3213 "@
3214 %q3. %0,%1,%2
3215 #"
3216 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3217 [(set (match_dup 0)
3218 (match_dup 3))
3219 (set (match_dup 4)
3220 (compare:CC (match_dup 0)
3221 (const_int 0)))]
3222 ""
3223 [(set_attr "type" "logical")
3224 (set_attr "dot" "yes")
3225 (set_attr "length" "4,8")])
3227 (define_insn_and_split "*bool<mode>3_dot2"
3228 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3229 (compare:CC (match_operator:GPR 3 "boolean_operator"
3230 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3231 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3232 (const_int 0)))
3233 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3234 (match_dup 3))]
3235 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3236 "@
3237 %q3. %0,%1,%2
3238 #"
3239 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3240 [(set (match_dup 0)
3241 (match_dup 3))
3242 (set (match_dup 4)
3243 (compare:CC (match_dup 0)
3244 (const_int 0)))]
3245 ""
3246 [(set_attr "type" "logical")
3247 (set_attr "dot" "yes")
3248 (set_attr "length" "4,8")])
3251 (define_insn "*boolc<mode>3"
3252 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3253 (match_operator:GPR 3 "boolean_operator"
3254 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3255 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3256 ""
3257 "%q3 %0,%1,%2"
3258 [(set_attr "type" "logical")])
3260 (define_insn_and_split "*boolc<mode>3_dot"
3261 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3262 (compare:CC (match_operator:GPR 3 "boolean_operator"
3263 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3264 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3265 (const_int 0)))
3266 (clobber (match_scratch:GPR 0 "=r,r"))]
3267 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3268 "@
3269 %q3. %0,%1,%2
3270 #"
3271 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3272 [(set (match_dup 0)
3273 (match_dup 3))
3274 (set (match_dup 4)
3275 (compare:CC (match_dup 0)
3276 (const_int 0)))]
3277 ""
3278 [(set_attr "type" "logical")
3279 (set_attr "dot" "yes")
3280 (set_attr "length" "4,8")])
3282 (define_insn_and_split "*boolc<mode>3_dot2"
3283 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3284 (compare:CC (match_operator:GPR 3 "boolean_operator"
3285 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3286 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3287 (const_int 0)))
3288 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3289 (match_dup 3))]
3290 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3291 "@
3292 %q3. %0,%1,%2
3293 #"
3294 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3295 [(set (match_dup 0)
3296 (match_dup 3))
3297 (set (match_dup 4)
3298 (compare:CC (match_dup 0)
3299 (const_int 0)))]
3300 ""
3301 [(set_attr "type" "logical")
3302 (set_attr "dot" "yes")
3303 (set_attr "length" "4,8")])
3306 (define_insn "*boolcc<mode>3"
3307 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3308 (match_operator:GPR 3 "boolean_operator"
3309 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3310 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3311 ""
3312 "%q3 %0,%1,%2"
3313 [(set_attr "type" "logical")])
3315 (define_insn_and_split "*boolcc<mode>3_dot"
3316 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3317 (compare:CC (match_operator:GPR 3 "boolean_operator"
3318 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3319 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3320 (const_int 0)))
3321 (clobber (match_scratch:GPR 0 "=r,r"))]
3322 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3323 "@
3324 %q3. %0,%1,%2
3325 #"
3326 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3327 [(set (match_dup 0)
3328 (match_dup 3))
3329 (set (match_dup 4)
3330 (compare:CC (match_dup 0)
3331 (const_int 0)))]
3332 ""
3333 [(set_attr "type" "logical")
3334 (set_attr "dot" "yes")
3335 (set_attr "length" "4,8")])
3337 (define_insn_and_split "*boolcc<mode>3_dot2"
3338 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3339 (compare:CC (match_operator:GPR 3 "boolean_operator"
3340 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3341 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3342 (const_int 0)))
3343 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3344 (match_dup 3))]
3345 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3346 "@
3347 %q3. %0,%1,%2
3348 #"
3349 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3350 [(set (match_dup 0)
3351 (match_dup 3))
3352 (set (match_dup 4)
3353 (compare:CC (match_dup 0)
3354 (const_int 0)))]
3355 ""
3356 [(set_attr "type" "logical")
3357 (set_attr "dot" "yes")
3358 (set_attr "length" "4,8")])
3361 ;; TODO: Should have dots of this as well.
3362 (define_insn "*eqv<mode>3"
3363 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3364 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3365 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3366 ""
3367 "eqv %0,%1,%2"
3368 [(set_attr "type" "logical")])
3369 \f
3370 ;; Rotate and shift insns, in all their variants. These support shifts,
3371 ;; field inserts and extracts, and various combinations thereof.
3372 (define_expand "insv"
3373 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3374 (match_operand:SI 1 "const_int_operand" "")
3375 (match_operand:SI 2 "const_int_operand" ""))
3376 (match_operand 3 "gpc_reg_operand" ""))]
3377 ""
3378 "
3379 {
3380 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3381 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3382 compiler if the address of the structure is taken later. Likewise, do
3383 not handle invalid E500 subregs. */
3384 if (GET_CODE (operands[0]) == SUBREG
3385 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3386 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3387 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3388 FAIL;
3390 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3391 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3392 operands[3]));
3393 else
3394 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3395 operands[3]));
3396 DONE;
3397 }")
3399 (define_insn "insvsi_internal"
3400 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3401 (match_operand:SI 1 "const_int_operand" "i")
3402 (match_operand:SI 2 "const_int_operand" "i"))
3403 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3404 ""
3405 "*
3406 {
3407 int start = INTVAL (operands[2]) & 31;
3408 int size = INTVAL (operands[1]) & 31;
3410 operands[4] = GEN_INT (32 - start - size);
3411 operands[1] = GEN_INT (start + size - 1);
3412 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3413 }"
3414 [(set_attr "type" "insert")])
3416 (define_insn "*insvsi_internal1"
3417 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3418 (match_operand:SI 1 "const_int_operand" "i")
3419 (match_operand:SI 2 "const_int_operand" "i"))
3420 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3421 (match_operand:SI 4 "const_int_operand" "i")))]
3422 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3423 "*
3424 {
3425 int shift = INTVAL (operands[4]) & 31;
3426 int start = INTVAL (operands[2]) & 31;
3427 int size = INTVAL (operands[1]) & 31;
3429 operands[4] = GEN_INT (shift - start - size);
3430 operands[1] = GEN_INT (start + size - 1);
3431 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3432 }"
3433 [(set_attr "type" "insert")])
3435 (define_insn "*insvsi_internal2"
3436 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3437 (match_operand:SI 1 "const_int_operand" "i")
3438 (match_operand:SI 2 "const_int_operand" "i"))
3439 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3440 (match_operand:SI 4 "const_int_operand" "i")))]
3441 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3442 "*
3443 {
3444 int shift = INTVAL (operands[4]) & 31;
3445 int start = INTVAL (operands[2]) & 31;
3446 int size = INTVAL (operands[1]) & 31;
3448 operands[4] = GEN_INT (32 - shift - start - size);
3449 operands[1] = GEN_INT (start + size - 1);
3450 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3451 }"
3452 [(set_attr "type" "insert")])
3454 (define_insn "*insvsi_internal3"
3455 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3456 (match_operand:SI 1 "const_int_operand" "i")
3457 (match_operand:SI 2 "const_int_operand" "i"))
3458 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3459 (match_operand:SI 4 "const_int_operand" "i")))]
3460 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3461 "*
3462 {
3463 int shift = INTVAL (operands[4]) & 31;
3464 int start = INTVAL (operands[2]) & 31;
3465 int size = INTVAL (operands[1]) & 31;
3467 operands[4] = GEN_INT (32 - shift - start - size);
3468 operands[1] = GEN_INT (start + size - 1);
3469 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3470 }"
3471 [(set_attr "type" "insert")])
3473 (define_insn "*insvsi_internal4"
3474 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3475 (match_operand:SI 1 "const_int_operand" "i")
3476 (match_operand:SI 2 "const_int_operand" "i"))
3477 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3478 (match_operand:SI 4 "const_int_operand" "i")
3479 (match_operand:SI 5 "const_int_operand" "i")))]
3480 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3481 "*
3482 {
3483 int extract_start = INTVAL (operands[5]) & 31;
3484 int extract_size = INTVAL (operands[4]) & 31;
3485 int insert_start = INTVAL (operands[2]) & 31;
3486 int insert_size = INTVAL (operands[1]) & 31;
3488 /* Align extract field with insert field */
3489 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3490 operands[1] = GEN_INT (insert_start + insert_size - 1);
3491 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3492 }"
3493 [(set_attr "type" "insert")])
3495 ;; combine patterns for rlwimi
3496 (define_insn "*insvsi_internal5"
3497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3498 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3499 (match_operand:SI 1 "mask_operand" "i"))
3500 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3501 (match_operand:SI 2 "const_int_operand" "i"))
3502 (match_operand:SI 5 "mask_operand" "i"))))]
3503 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3504 "*
3505 {
3506 int me = extract_ME(operands[5]);
3507 int mb = extract_MB(operands[5]);
3508 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3509 operands[2] = GEN_INT(mb);
3510 operands[1] = GEN_INT(me);
3511 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3512 }"
3513 [(set_attr "type" "insert")])
3515 (define_insn "*insvsi_internal6"
3516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3517 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "const_int_operand" "i"))
3519 (match_operand:SI 5 "mask_operand" "i"))
3520 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3521 (match_operand:SI 1 "mask_operand" "i"))))]
3522 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3523 "*
3524 {
3525 int me = extract_ME(operands[5]);
3526 int mb = extract_MB(operands[5]);
3527 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3528 operands[2] = GEN_INT(mb);
3529 operands[1] = GEN_INT(me);
3530 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3531 }"
3532 [(set_attr "type" "insert")])
3534 (define_insn "insvdi_internal"
3535 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3536 (match_operand:SI 1 "const_int_operand" "i")
3537 (match_operand:SI 2 "const_int_operand" "i"))
3538 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3539 "TARGET_POWERPC64"
3540 "*
3541 {
3542 int start = INTVAL (operands[2]) & 63;
3543 int size = INTVAL (operands[1]) & 63;
3545 operands[1] = GEN_INT (64 - start - size);
3546 return \"rldimi %0,%3,%H1,%H2\";
3547 }"
3548 [(set_attr "type" "insert")
3549 (set_attr "size" "64")])
3551 (define_insn "*insvdi_internal2"
3552 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3553 (match_operand:SI 1 "const_int_operand" "i")
3554 (match_operand:SI 2 "const_int_operand" "i"))
3555 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 4 "const_int_operand" "i")))]
3557 "TARGET_POWERPC64
3558 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3559 "*
3560 {
3561 int shift = INTVAL (operands[4]) & 63;
3562 int start = (INTVAL (operands[2]) & 63) - 32;
3563 int size = INTVAL (operands[1]) & 63;
3565 operands[4] = GEN_INT (64 - shift - start - size);
3566 operands[2] = GEN_INT (start);
3567 operands[1] = GEN_INT (start + size - 1);
3568 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3569 }")
3571 (define_insn "*insvdi_internal3"
3572 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3573 (match_operand:SI 1 "const_int_operand" "i")
3574 (match_operand:SI 2 "const_int_operand" "i"))
3575 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3576 (match_operand:SI 4 "const_int_operand" "i")))]
3577 "TARGET_POWERPC64
3578 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3579 "*
3580 {
3581 int shift = INTVAL (operands[4]) & 63;
3582 int start = (INTVAL (operands[2]) & 63) - 32;
3583 int size = INTVAL (operands[1]) & 63;
3585 operands[4] = GEN_INT (64 - shift - start - size);
3586 operands[2] = GEN_INT (start);
3587 operands[1] = GEN_INT (start + size - 1);
3588 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3589 }")
3591 (define_expand "extzv"
3592 [(set (match_operand 0 "gpc_reg_operand" "")
3593 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3594 (match_operand:SI 2 "const_int_operand" "")
3595 (match_operand:SI 3 "const_int_operand" "")))]
3596 ""
3597 "
3598 {
3599 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3600 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3601 compiler if the address of the structure is taken later. */
3602 if (GET_CODE (operands[0]) == SUBREG
3603 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3604 FAIL;
3606 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3607 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3608 operands[3]));
3609 else
3610 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3611 operands[3]));
3612 DONE;
3613 }")
3615 (define_insn "extzvsi_internal"
3616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3617 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3618 (match_operand:SI 2 "const_int_operand" "i")
3619 (match_operand:SI 3 "const_int_operand" "i")))]
3620 ""
3621 "*
3622 {
3623 int start = INTVAL (operands[3]) & 31;
3624 int size = INTVAL (operands[2]) & 31;
3626 if (start + size >= 32)
3627 operands[3] = const0_rtx;
3628 else
3629 operands[3] = GEN_INT (start + size);
3630 return \"rlwinm %0,%1,%3,%s2,31\";
3631 }"
3632 [(set_attr "type" "shift")])
3634 (define_insn "*extzvsi_internal1"
3635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3636 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3637 (match_operand:SI 2 "const_int_operand" "i,i")
3638 (match_operand:SI 3 "const_int_operand" "i,i"))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 4 "=r,r"))]
3641 ""
3642 "*
3643 {
3644 int start = INTVAL (operands[3]) & 31;
3645 int size = INTVAL (operands[2]) & 31;
3647 /* Force split for non-cc0 compare. */
3648 if (which_alternative == 1)
3649 return \"#\";
3651 /* If the bit-field being tested fits in the upper or lower half of a
3652 word, it is possible to use andiu. or andil. to test it. This is
3653 useful because the condition register set-use delay is smaller for
3654 andi[ul]. than for rlinm. This doesn't work when the starting bit
3655 position is 0 because the LT and GT bits may be set wrong. */
3657 if ((start > 0 && start + size <= 16) || start >= 16)
3658 {
3659 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3660 - (1 << (16 - (start & 15) - size))));
3661 if (start < 16)
3662 return \"andis. %4,%1,%3\";
3663 else
3664 return \"andi. %4,%1,%3\";
3665 }
3667 if (start + size >= 32)
3668 operands[3] = const0_rtx;
3669 else
3670 operands[3] = GEN_INT (start + size);
3671 return \"rlwinm. %4,%1,%3,%s2,31\";
3672 }"
3673 [(set_attr "type" "shift")
3674 (set_attr "dot" "yes")
3675 (set_attr "length" "4,8")])
3677 (define_split
3678 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3679 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3680 (match_operand:SI 2 "const_int_operand" "")
3681 (match_operand:SI 3 "const_int_operand" ""))
3682 (const_int 0)))
3683 (clobber (match_scratch:SI 4 ""))]
3684 "reload_completed"
3685 [(set (match_dup 4)
3686 (zero_extract:SI (match_dup 1) (match_dup 2)
3687 (match_dup 3)))
3688 (set (match_dup 0)
3689 (compare:CC (match_dup 4)
3690 (const_int 0)))]
3691 "")
3693 (define_insn "*extzvsi_internal2"
3694 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3695 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3696 (match_operand:SI 2 "const_int_operand" "i,i")
3697 (match_operand:SI 3 "const_int_operand" "i,i"))
3698 (const_int 0)))
3699 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3700 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3701 ""
3702 "*
3703 {
3704 int start = INTVAL (operands[3]) & 31;
3705 int size = INTVAL (operands[2]) & 31;
3707 /* Force split for non-cc0 compare. */
3708 if (which_alternative == 1)
3709 return \"#\";
3711 /* Since we are using the output value, we can't ignore any need for
3712 a shift. The bit-field must end at the LSB. */
3713 if (start >= 16 && start + size == 32)
3714 {
3715 operands[3] = GEN_INT ((1 << size) - 1);
3716 return \"andi. %0,%1,%3\";
3717 }
3719 if (start + size >= 32)
3720 operands[3] = const0_rtx;
3721 else
3722 operands[3] = GEN_INT (start + size);
3723 return \"rlwinm. %0,%1,%3,%s2,31\";
3724 }"
3725 [(set_attr "type" "shift")
3726 (set_attr "dot" "yes")
3727 (set_attr "length" "4,8")])
3729 (define_split
3730 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3731 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3732 (match_operand:SI 2 "const_int_operand" "")
3733 (match_operand:SI 3 "const_int_operand" ""))
3734 (const_int 0)))
3735 (set (match_operand:SI 0 "gpc_reg_operand" "")
3736 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3737 "reload_completed"
3738 [(set (match_dup 0)
3739 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3740 (set (match_dup 4)
3741 (compare:CC (match_dup 0)
3742 (const_int 0)))]
3743 "")
3745 (define_insn "extzvdi_internal"
3746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3747 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3748 (match_operand:SI 2 "const_int_operand" "i")
3749 (match_operand:SI 3 "const_int_operand" "i")))]
3750 "TARGET_POWERPC64"
3751 "*
3752 {
3753 int start = INTVAL (operands[3]) & 63;
3754 int size = INTVAL (operands[2]) & 63;
3756 if (start + size >= 64)
3757 operands[3] = const0_rtx;
3758 else
3759 operands[3] = GEN_INT (start + size);
3760 operands[2] = GEN_INT (64 - size);
3761 return \"rldicl %0,%1,%3,%2\";
3762 }"
3763 [(set_attr "type" "shift")])
3765 (define_insn "*extzvdi_internal1"
3766 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3767 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3768 (match_operand:SI 2 "const_int_operand" "i")
3769 (match_operand:SI 3 "const_int_operand" "i"))
3770 (const_int 0)))
3771 (clobber (match_scratch:DI 4 "=r"))]
3772 "TARGET_64BIT && rs6000_gen_cell_microcode"
3773 "*
3774 {
3775 int start = INTVAL (operands[3]) & 63;
3776 int size = INTVAL (operands[2]) & 63;
3778 if (start + size >= 64)
3779 operands[3] = const0_rtx;
3780 else
3781 operands[3] = GEN_INT (start + size);
3782 operands[2] = GEN_INT (64 - size);
3783 return \"rldicl. %4,%1,%3,%2\";
3784 }"
3785 [(set_attr "type" "shift")
3786 (set_attr "dot" "yes")])
3788 (define_insn "*extzvdi_internal2"
3789 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3790 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3791 (match_operand:SI 2 "const_int_operand" "i")
3792 (match_operand:SI 3 "const_int_operand" "i"))
3793 (const_int 0)))
3794 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3795 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3796 "TARGET_64BIT && rs6000_gen_cell_microcode"
3797 "*
3798 {
3799 int start = INTVAL (operands[3]) & 63;
3800 int size = INTVAL (operands[2]) & 63;
3802 if (start + size >= 64)
3803 operands[3] = const0_rtx;
3804 else
3805 operands[3] = GEN_INT (start + size);
3806 operands[2] = GEN_INT (64 - size);
3807 return \"rldicl. %0,%1,%3,%2\";
3808 }"
3809 [(set_attr "type" "shift")
3810 (set_attr "dot" "yes")])
3813 (define_insn "rotl<mode>3"
3814 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3815 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3816 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3817 ""
3818 "rotl<wd>%I2 %0,%1,%<hH>2"
3819 [(set_attr "type" "shift")
3820 (set_attr "maybe_var_shift" "yes")])
3822 (define_insn "*rotlsi3_64"
3823 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3824 (zero_extend:DI
3825 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3826 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3827 "TARGET_POWERPC64"
3828 "rotlw%I2 %0,%1,%h2"
3829 [(set_attr "type" "shift")
3830 (set_attr "maybe_var_shift" "yes")])
3832 (define_insn_and_split "*rotl<mode>3_dot"
3833 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3834 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3835 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3836 (const_int 0)))
3837 (clobber (match_scratch:GPR 0 "=r,r"))]
3838 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3839 "@
3840 rotl<wd>%I2. %0,%1,%<hH>2
3841 #"
3842 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3843 [(set (match_dup 0)
3844 (rotate:GPR (match_dup 1)
3845 (match_dup 2)))
3846 (set (match_dup 3)
3847 (compare:CC (match_dup 0)
3848 (const_int 0)))]
3849 ""
3850 [(set_attr "type" "shift")
3851 (set_attr "maybe_var_shift" "yes")
3852 (set_attr "dot" "yes")
3853 (set_attr "length" "4,8")])
3855 (define_insn_and_split "*rotl<mode>3_dot2"
3856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3857 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3859 (const_int 0)))
3860 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3861 (rotate:GPR (match_dup 1)
3862 (match_dup 2)))]
3863 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3864 "@
3865 rotl<wd>%I2. %0,%1,%<hH>2
3866 #"
3867 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3868 [(set (match_dup 0)
3869 (rotate:GPR (match_dup 1)
3870 (match_dup 2)))
3871 (set (match_dup 3)
3872 (compare:CC (match_dup 0)
3873 (const_int 0)))]
3874 ""
3875 [(set_attr "type" "shift")
3876 (set_attr "maybe_var_shift" "yes")
3877 (set_attr "dot" "yes")
3878 (set_attr "length" "4,8")])
3881 (define_insn "*rotlsi3_internal4"
3882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3883 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3884 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3885 (match_operand:SI 3 "mask_operand" "n")))]
3886 ""
3887 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3888 [(set_attr "type" "shift")
3889 (set_attr "maybe_var_shift" "yes")])
3891 (define_insn "*rotlsi3_internal5"
3892 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3893 (compare:CC (and:SI
3894 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3896 (match_operand:SI 3 "mask_operand" "n,n"))
3897 (const_int 0)))
3898 (clobber (match_scratch:SI 4 "=r,r"))]
3899 ""
3900 "@
3901 rlw%I2nm. %4,%1,%h2,%m3,%M3
3902 #"
3903 [(set_attr "type" "shift")
3904 (set_attr "maybe_var_shift" "yes")
3905 (set_attr "dot" "yes")
3906 (set_attr "length" "4,8")])
3908 (define_split
3909 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3910 (compare:CC (and:SI
3911 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3912 (match_operand:SI 2 "reg_or_cint_operand" ""))
3913 (match_operand:SI 3 "mask_operand" ""))
3914 (const_int 0)))
3915 (clobber (match_scratch:SI 4 ""))]
3916 "reload_completed"
3917 [(set (match_dup 4)
3918 (and:SI (rotate:SI (match_dup 1)
3919 (match_dup 2))
3920 (match_dup 3)))
3921 (set (match_dup 0)
3922 (compare:CC (match_dup 4)
3923 (const_int 0)))]
3924 "")
3926 (define_insn "*rotlsi3_internal6"
3927 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3928 (compare:CC (and:SI
3929 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3930 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3931 (match_operand:SI 3 "mask_operand" "n,n"))
3932 (const_int 0)))
3933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3934 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3935 ""
3936 "@
3937 rlw%I2nm. %0,%1,%h2,%m3,%M3
3938 #"
3939 [(set_attr "type" "shift")
3940 (set_attr "maybe_var_shift" "yes")
3941 (set_attr "dot" "yes")
3942 (set_attr "length" "4,8")])
3944 (define_split
3945 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3946 (compare:CC (and:SI
3947 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3948 (match_operand:SI 2 "reg_or_cint_operand" ""))
3949 (match_operand:SI 3 "mask_operand" ""))
3950 (const_int 0)))
3951 (set (match_operand:SI 0 "gpc_reg_operand" "")
3952 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3953 "reload_completed"
3954 [(set (match_dup 0)
3955 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3956 (set (match_dup 4)
3957 (compare:CC (match_dup 0)
3958 (const_int 0)))]
3959 "")
3961 (define_insn "*rotlsi3_internal7le"
3962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3963 (zero_extend:SI
3964 (subreg:QI
3965 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3966 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3967 "!BYTES_BIG_ENDIAN"
3968 "rlw%I2nm %0,%1,%h2,0xff"
3969 [(set (attr "cell_micro")
3970 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3971 (const_string "not")
3972 (const_string "always")))
3973 (set_attr "type" "shift")])
3975 (define_insn "*rotlsi3_internal7be"
3976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3977 (zero_extend:SI
3978 (subreg:QI
3979 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3980 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3981 "BYTES_BIG_ENDIAN"
3982 "rlw%I2nm %0,%1,%h2,0xff"
3983 [(set (attr "cell_micro")
3984 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3985 (const_string "not")
3986 (const_string "always")))
3987 (set_attr "type" "shift")])
3989 (define_insn "*rotlsi3_internal8le"
3990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3991 (compare:CC (zero_extend:SI
3992 (subreg:QI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3995 (const_int 0)))
3996 (clobber (match_scratch:SI 3 "=r,r"))]
3997 "!BYTES_BIG_ENDIAN"
3998 "@
3999 rlw%I2nm. %3,%1,%h2,0xff
4000 #"
4001 [(set_attr "type" "shift")
4002 (set_attr "maybe_var_shift" "yes")
4003 (set_attr "dot" "yes")
4004 (set_attr "length" "4,8")])
4006 (define_insn "*rotlsi3_internal8be"
4007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4008 (compare:CC (zero_extend:SI
4009 (subreg:QI
4010 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4011 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4012 (const_int 0)))
4013 (clobber (match_scratch:SI 3 "=r,r"))]
4014 "BYTES_BIG_ENDIAN"
4015 "@
4016 rlw%I2nm. %3,%1,%h2,0xff
4017 #"
4018 [(set_attr "type" "shift")
4019 (set_attr "maybe_var_shift" "yes")
4020 (set_attr "dot" "yes")
4021 (set_attr "length" "4,8")])
4023 (define_split
4024 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4025 (compare:CC (zero_extend:SI
4026 (subreg:QI
4027 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4028 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4029 (const_int 0)))
4030 (clobber (match_scratch:SI 3 ""))]
4031 "!BYTES_BIG_ENDIAN && reload_completed"
4032 [(set (match_dup 3)
4033 (zero_extend:SI (subreg:QI
4034 (rotate:SI (match_dup 1)
4035 (match_dup 2)) 0)))
4036 (set (match_dup 0)
4037 (compare:CC (match_dup 3)
4038 (const_int 0)))]
4039 "")
4041 (define_split
4042 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4043 (compare:CC (zero_extend:SI
4044 (subreg:QI
4045 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4046 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4047 (const_int 0)))
4048 (clobber (match_scratch:SI 3 ""))]
4049 "BYTES_BIG_ENDIAN && reload_completed"
4050 [(set (match_dup 3)
4051 (zero_extend:SI (subreg:QI
4052 (rotate:SI (match_dup 1)
4053 (match_dup 2)) 3)))
4054 (set (match_dup 0)
4055 (compare:CC (match_dup 3)
4056 (const_int 0)))]
4057 "")
4059 (define_insn "*rotlsi3_internal9le"
4060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4061 (compare:CC (zero_extend:SI
4062 (subreg:QI
4063 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4064 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4065 (const_int 0)))
4066 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4067 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4068 "!BYTES_BIG_ENDIAN"
4069 "@
4070 rlw%I2nm. %0,%1,%h2,0xff
4071 #"
4072 [(set_attr "type" "shift")
4073 (set_attr "maybe_var_shift" "yes")
4074 (set_attr "dot" "yes")
4075 (set_attr "length" "4,8")])
4077 (define_insn "*rotlsi3_internal9be"
4078 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4079 (compare:CC (zero_extend:SI
4080 (subreg:QI
4081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4082 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4083 (const_int 0)))
4084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4085 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4086 "BYTES_BIG_ENDIAN"
4087 "@
4088 rlw%I2nm. %0,%1,%h2,0xff
4089 #"
4090 [(set_attr "type" "shift")
4091 (set_attr "maybe_var_shift" "yes")
4092 (set_attr "dot" "yes")
4093 (set_attr "length" "4,8")])
4095 (define_split
4096 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4097 (compare:CC (zero_extend:SI
4098 (subreg:QI
4099 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4100 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4101 (const_int 0)))
4102 (set (match_operand:SI 0 "gpc_reg_operand" "")
4103 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4104 "!BYTES_BIG_ENDIAN && reload_completed"
4105 [(set (match_dup 0)
4106 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4107 (set (match_dup 3)
4108 (compare:CC (match_dup 0)
4109 (const_int 0)))]
4110 "")
4112 (define_split
4113 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4114 (compare:CC (zero_extend:SI
4115 (subreg:QI
4116 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4117 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "")
4120 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4121 "BYTES_BIG_ENDIAN && reload_completed"
4122 [(set (match_dup 0)
4123 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4124 (set (match_dup 3)
4125 (compare:CC (match_dup 0)
4126 (const_int 0)))]
4127 "")
4129 (define_insn "*rotlsi3_internal10le"
4130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4131 (zero_extend:SI
4132 (subreg:HI
4133 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4134 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
4135 "!BYTES_BIG_ENDIAN"
4136 "rlw%I2nm %0,%1,%h2,0xffff"
4137 [(set_attr "type" "shift")
4138 (set_attr "maybe_var_shift" "yes")])
4140 (define_insn "*rotlsi3_internal10be"
4141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4142 (zero_extend:SI
4143 (subreg:HI
4144 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4145 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
4146 "BYTES_BIG_ENDIAN"
4147 "rlw%I2nm %0,%1,%h2,0xffff"
4148 [(set_attr "type" "shift")
4149 (set_attr "maybe_var_shift" "yes")])
4151 (define_insn "*rotlsi3_internal11le"
4152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4153 (compare:CC (zero_extend:SI
4154 (subreg:HI
4155 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4156 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4157 (const_int 0)))
4158 (clobber (match_scratch:SI 3 "=r,r"))]
4159 "!BYTES_BIG_ENDIAN"
4160 "@
4161 rlw%I2nm. %3,%1,%h2,0xffff
4162 #"
4163 [(set_attr "type" "shift")
4164 (set_attr "maybe_var_shift" "yes")
4165 (set_attr "dot" "yes")
4166 (set_attr "length" "4,8")])
4168 (define_insn "*rotlsi3_internal11be"
4169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4170 (compare:CC (zero_extend:SI
4171 (subreg:HI
4172 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4173 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4174 (const_int 0)))
4175 (clobber (match_scratch:SI 3 "=r,r"))]
4176 "BYTES_BIG_ENDIAN"
4177 "@
4178 rlw%I2nm. %3,%1,%h2,0xffff
4179 #"
4180 [(set_attr "type" "shift")
4181 (set_attr "maybe_var_shift" "yes")
4182 (set_attr "dot" "yes")
4183 (set_attr "length" "4,8")])
4185 (define_split
4186 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4187 (compare:CC (zero_extend:SI
4188 (subreg:HI
4189 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4190 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4191 (const_int 0)))
4192 (clobber (match_scratch:SI 3 ""))]
4193 "!BYTES_BIG_ENDIAN && reload_completed"
4194 [(set (match_dup 3)
4195 (zero_extend:SI (subreg:HI
4196 (rotate:SI (match_dup 1)
4197 (match_dup 2)) 0)))
4198 (set (match_dup 0)
4199 (compare:CC (match_dup 3)
4200 (const_int 0)))]
4201 "")
4203 (define_split
4204 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4205 (compare:CC (zero_extend:SI
4206 (subreg:HI
4207 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4208 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4209 (const_int 0)))
4210 (clobber (match_scratch:SI 3 ""))]
4211 "BYTES_BIG_ENDIAN && reload_completed"
4212 [(set (match_dup 3)
4213 (zero_extend:SI (subreg:HI
4214 (rotate:SI (match_dup 1)
4215 (match_dup 2)) 2)))
4216 (set (match_dup 0)
4217 (compare:CC (match_dup 3)
4218 (const_int 0)))]
4219 "")
4221 (define_insn "*rotlsi3_internal12le"
4222 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4223 (compare:CC (zero_extend:SI
4224 (subreg:HI
4225 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4226 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4227 (const_int 0)))
4228 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4229 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4230 "!BYTES_BIG_ENDIAN"
4231 "@
4232 rlw%I2nm. %0,%1,%h2,0xffff
4233 #"
4234 [(set_attr "type" "shift")
4235 (set_attr "maybe_var_shift" "yes")
4236 (set_attr "dot" "yes")
4237 (set_attr "length" "4,8")])
4239 (define_insn "*rotlsi3_internal12be"
4240 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4241 (compare:CC (zero_extend:SI
4242 (subreg:HI
4243 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4245 (const_int 0)))
4246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4247 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4248 "BYTES_BIG_ENDIAN"
4249 "@
4250 rlw%I2nm. %0,%1,%h2,0xffff
4251 #"
4252 [(set_attr "type" "shift")
4253 (set_attr "maybe_var_shift" "yes")
4254 (set_attr "dot" "yes")
4255 (set_attr "length" "4,8")])
4257 (define_split
4258 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4259 (compare:CC (zero_extend:SI
4260 (subreg:HI
4261 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4262 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4263 (const_int 0)))
4264 (set (match_operand:SI 0 "gpc_reg_operand" "")
4265 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4266 "!BYTES_BIG_ENDIAN && reload_completed"
4267 [(set (match_dup 0)
4268 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4269 (set (match_dup 3)
4270 (compare:CC (match_dup 0)
4271 (const_int 0)))]
4272 "")
4274 (define_split
4275 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4276 (compare:CC (zero_extend:SI
4277 (subreg:HI
4278 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4279 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4280 (const_int 0)))
4281 (set (match_operand:SI 0 "gpc_reg_operand" "")
4282 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4283 "BYTES_BIG_ENDIAN && reload_completed"
4284 [(set (match_dup 0)
4285 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4286 (set (match_dup 3)
4287 (compare:CC (match_dup 0)
4288 (const_int 0)))]
4289 "")
4292 (define_insn "ashl<mode>3"
4293 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4294 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4295 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4296 ""
4297 "sl<wd>%I2 %0,%1,%<hH>2"
4298 [(set_attr "type" "shift")
4299 (set_attr "maybe_var_shift" "yes")])
4301 (define_insn "*ashlsi3_64"
4302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4303 (zero_extend:DI
4304 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4305 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4306 "TARGET_POWERPC64"
4307 "slw%I2 %0,%1,%h2"
4308 [(set_attr "type" "shift")
4309 (set_attr "maybe_var_shift" "yes")])
4311 (define_insn_and_split "*ashl<mode>3_dot"
4312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4313 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4314 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4315 (const_int 0)))
4316 (clobber (match_scratch:GPR 0 "=r,r"))]
4317 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4318 "@
4319 sl<wd>%I2. %0,%1,%<hH>2
4320 #"
4321 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4322 [(set (match_dup 0)
4323 (ashift:GPR (match_dup 1)
4324 (match_dup 2)))
4325 (set (match_dup 3)
4326 (compare:CC (match_dup 0)
4327 (const_int 0)))]
4328 ""
4329 [(set_attr "type" "shift")
4330 (set_attr "maybe_var_shift" "yes")
4331 (set_attr "dot" "yes")
4332 (set_attr "length" "4,8")])
4334 (define_insn_and_split "*ashl<mode>3_dot2"
4335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4336 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4337 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4338 (const_int 0)))
4339 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4340 (ashift:GPR (match_dup 1)
4341 (match_dup 2)))]
4342 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4343 "@
4344 sl<wd>%I2. %0,%1,%<hH>2
4345 #"
4346 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4347 [(set (match_dup 0)
4348 (ashift:GPR (match_dup 1)
4349 (match_dup 2)))
4350 (set (match_dup 3)
4351 (compare:CC (match_dup 0)
4352 (const_int 0)))]
4353 ""
4354 [(set_attr "type" "shift")
4355 (set_attr "maybe_var_shift" "yes")
4356 (set_attr "dot" "yes")
4357 (set_attr "length" "4,8")])
4360 (define_insn "rlwinm"
4361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4362 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4363 (match_operand:SI 2 "const_int_operand" "i"))
4364 (match_operand:SI 3 "mask_operand" "n")))]
4365 "includes_lshift_p (operands[2], operands[3])"
4366 "rlwinm %0,%1,%h2,%m3,%M3"
4367 [(set_attr "type" "shift")])
4369 (define_insn ""
4370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4371 (compare:CC
4372 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4373 (match_operand:SI 2 "const_int_operand" "i,i"))
4374 (match_operand:SI 3 "mask_operand" "n,n"))
4375 (const_int 0)))
4376 (clobber (match_scratch:SI 4 "=r,r"))]
4377 "includes_lshift_p (operands[2], operands[3])"
4378 "@
4379 rlwinm. %4,%1,%h2,%m3,%M3
4380 #"
4381 [(set_attr "type" "shift")
4382 (set_attr "dot" "yes")
4383 (set_attr "length" "4,8")])
4385 (define_split
4386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4387 (compare:CC
4388 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4389 (match_operand:SI 2 "const_int_operand" ""))
4390 (match_operand:SI 3 "mask_operand" ""))
4391 (const_int 0)))
4392 (clobber (match_scratch:SI 4 ""))]
4393 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4394 [(set (match_dup 4)
4395 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4396 (match_dup 3)))
4397 (set (match_dup 0)
4398 (compare:CC (match_dup 4)
4399 (const_int 0)))]
4400 "")
4402 (define_insn ""
4403 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4404 (compare:CC
4405 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4406 (match_operand:SI 2 "const_int_operand" "i,i"))
4407 (match_operand:SI 3 "mask_operand" "n,n"))
4408 (const_int 0)))
4409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4410 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4411 "includes_lshift_p (operands[2], operands[3])"
4412 "@
4413 rlwinm. %0,%1,%h2,%m3,%M3
4414 #"
4415 [(set_attr "type" "shift")
4416 (set_attr "dot" "yes")
4417 (set_attr "length" "4,8")])
4419 (define_split
4420 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4421 (compare:CC
4422 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4423 (match_operand:SI 2 "const_int_operand" ""))
4424 (match_operand:SI 3 "mask_operand" ""))
4425 (const_int 0)))
4426 (set (match_operand:SI 0 "gpc_reg_operand" "")
4427 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4428 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4429 [(set (match_dup 0)
4430 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4431 (set (match_dup 4)
4432 (compare:CC (match_dup 0)
4433 (const_int 0)))]
4434 "")
4437 (define_insn "lshr<mode>3"
4438 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4439 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4440 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4441 ""
4442 "sr<wd>%I2 %0,%1,%<hH>2"
4443 [(set_attr "type" "shift")
4444 (set_attr "maybe_var_shift" "yes")])
4446 (define_insn "*lshrsi3_64"
4447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4448 (zero_extend:DI
4449 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4450 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4451 "TARGET_POWERPC64"
4452 "srw%I2 %0,%1,%h2"
4453 [(set_attr "type" "shift")
4454 (set_attr "maybe_var_shift" "yes")])
4456 (define_insn_and_split "*lshr<mode>3_dot"
4457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4458 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4459 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4460 (const_int 0)))
4461 (clobber (match_scratch:GPR 0 "=r,r"))]
4462 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4463 "@
4464 sr<wd>%I2. %0,%1,%<hH>2
4465 #"
4466 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4467 [(set (match_dup 0)
4468 (lshiftrt:GPR (match_dup 1)
4469 (match_dup 2)))
4470 (set (match_dup 3)
4471 (compare:CC (match_dup 0)
4472 (const_int 0)))]
4473 ""
4474 [(set_attr "type" "shift")
4475 (set_attr "maybe_var_shift" "yes")
4476 (set_attr "dot" "yes")
4477 (set_attr "length" "4,8")])
4479 (define_insn_and_split "*lshr<mode>3_dot2"
4480 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4481 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4482 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4483 (const_int 0)))
4484 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4485 (lshiftrt:GPR (match_dup 1)
4486 (match_dup 2)))]
4487 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4488 "@
4489 sr<wd>%I2. %0,%1,%<hH>2
4490 #"
4491 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4492 [(set (match_dup 0)
4493 (lshiftrt:GPR (match_dup 1)
4494 (match_dup 2)))
4495 (set (match_dup 3)
4496 (compare:CC (match_dup 0)
4497 (const_int 0)))]
4498 ""
4499 [(set_attr "type" "shift")
4500 (set_attr "maybe_var_shift" "yes")
4501 (set_attr "dot" "yes")
4502 (set_attr "length" "4,8")])
4505 (define_insn ""
4506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4507 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4508 (match_operand:SI 2 "const_int_operand" "i"))
4509 (match_operand:SI 3 "mask_operand" "n")))]
4510 "includes_rshift_p (operands[2], operands[3])"
4511 "rlwinm %0,%1,%s2,%m3,%M3"
4512 [(set_attr "type" "shift")])
4514 (define_insn ""
4515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4516 (compare:CC
4517 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4518 (match_operand:SI 2 "const_int_operand" "i,i"))
4519 (match_operand:SI 3 "mask_operand" "n,n"))
4520 (const_int 0)))
4521 (clobber (match_scratch:SI 4 "=r,r"))]
4522 "includes_rshift_p (operands[2], operands[3])"
4523 "@
4524 rlwinm. %4,%1,%s2,%m3,%M3
4525 #"
4526 [(set_attr "type" "shift")
4527 (set_attr "dot" "yes")
4528 (set_attr "length" "4,8")])
4530 (define_split
4531 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4532 (compare:CC
4533 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4534 (match_operand:SI 2 "const_int_operand" ""))
4535 (match_operand:SI 3 "mask_operand" ""))
4536 (const_int 0)))
4537 (clobber (match_scratch:SI 4 ""))]
4538 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4539 [(set (match_dup 4)
4540 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4541 (match_dup 3)))
4542 (set (match_dup 0)
4543 (compare:CC (match_dup 4)
4544 (const_int 0)))]
4545 "")
4547 (define_insn ""
4548 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4549 (compare:CC
4550 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4551 (match_operand:SI 2 "const_int_operand" "i,i"))
4552 (match_operand:SI 3 "mask_operand" "n,n"))
4553 (const_int 0)))
4554 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4555 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4556 "includes_rshift_p (operands[2], operands[3])"
4557 "@
4558 rlwinm. %0,%1,%s2,%m3,%M3
4559 #"
4560 [(set_attr "type" "shift")
4561 (set_attr "dot" "yes")
4562 (set_attr "length" "4,8")])
4564 (define_split
4565 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4566 (compare:CC
4567 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4568 (match_operand:SI 2 "const_int_operand" ""))
4569 (match_operand:SI 3 "mask_operand" ""))
4570 (const_int 0)))
4571 (set (match_operand:SI 0 "gpc_reg_operand" "")
4572 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4573 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4574 [(set (match_dup 0)
4575 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4576 (set (match_dup 4)
4577 (compare:CC (match_dup 0)
4578 (const_int 0)))]
4579 "")
4581 (define_insn "*lshiftrt_internal1le"
4582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4583 (zero_extend:SI
4584 (subreg:QI
4585 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4586 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4587 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4588 "rlwinm %0,%1,%s2,0xff"
4589 [(set_attr "type" "shift")])
4591 (define_insn "*lshiftrt_internal1be"
4592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4593 (zero_extend:SI
4594 (subreg:QI
4595 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4596 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4597 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4598 "rlwinm %0,%1,%s2,0xff"
4599 [(set_attr "type" "shift")])
4601 (define_insn "*lshiftrt_internal2le"
4602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4603 (compare:CC
4604 (zero_extend:SI
4605 (subreg:QI
4606 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4607 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4608 (const_int 0)))
4609 (clobber (match_scratch:SI 3 "=r,r"))]
4610 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4611 "@
4612 rlwinm. %3,%1,%s2,0xff
4613 #"
4614 [(set_attr "type" "shift")
4615 (set_attr "dot" "yes")
4616 (set_attr "length" "4,8")])
4618 (define_insn "*lshiftrt_internal2be"
4619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4620 (compare:CC
4621 (zero_extend:SI
4622 (subreg:QI
4623 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4624 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4625 (const_int 0)))
4626 (clobber (match_scratch:SI 3 "=r,r"))]
4627 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4628 "@
4629 rlwinm. %3,%1,%s2,0xff
4630 #"
4631 [(set_attr "type" "shift")
4632 (set_attr "dot" "yes")
4633 (set_attr "length" "4,8")])
4635 (define_split
4636 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4637 (compare:CC
4638 (zero_extend:SI
4639 (subreg:QI
4640 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4641 (match_operand:SI 2 "const_int_operand" "")) 0))
4642 (const_int 0)))
4643 (clobber (match_scratch:SI 3 ""))]
4644 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4645 [(set (match_dup 3)
4646 (zero_extend:SI (subreg:QI
4647 (lshiftrt:SI (match_dup 1)
4648 (match_dup 2)) 0)))
4649 (set (match_dup 0)
4650 (compare:CC (match_dup 3)
4651 (const_int 0)))]
4652 "")
4654 (define_split
4655 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4656 (compare:CC
4657 (zero_extend:SI
4658 (subreg:QI
4659 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4660 (match_operand:SI 2 "const_int_operand" "")) 3))
4661 (const_int 0)))
4662 (clobber (match_scratch:SI 3 ""))]
4663 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4664 [(set (match_dup 3)
4665 (zero_extend:SI (subreg:QI
4666 (lshiftrt:SI (match_dup 1)
4667 (match_dup 2)) 3)))
4668 (set (match_dup 0)
4669 (compare:CC (match_dup 3)
4670 (const_int 0)))]
4671 "")
4673 (define_insn "*lshiftrt_internal3le"
4674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4675 (compare:CC
4676 (zero_extend:SI
4677 (subreg:QI
4678 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4679 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4680 (const_int 0)))
4681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4682 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4683 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4684 "@
4685 rlwinm. %0,%1,%s2,0xff
4686 #"
4687 [(set_attr "type" "shift")
4688 (set_attr "dot" "yes")
4689 (set_attr "length" "4,8")])
4691 (define_insn "*lshiftrt_internal3be"
4692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4693 (compare:CC
4694 (zero_extend:SI
4695 (subreg:QI
4696 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4697 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4698 (const_int 0)))
4699 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4700 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4701 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4702 "@
4703 rlwinm. %0,%1,%s2,0xff
4704 #"
4705 [(set_attr "type" "shift")
4706 (set_attr "dot" "yes")
4707 (set_attr "length" "4,8")])
4709 (define_split
4710 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4711 (compare:CC
4712 (zero_extend:SI
4713 (subreg:QI
4714 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4715 (match_operand:SI 2 "const_int_operand" "")) 0))
4716 (const_int 0)))
4717 (set (match_operand:SI 0 "gpc_reg_operand" "")
4718 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4719 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4720 [(set (match_dup 0)
4721 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4722 (set (match_dup 3)
4723 (compare:CC (match_dup 0)
4724 (const_int 0)))]
4725 "")
4727 (define_split
4728 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4729 (compare:CC
4730 (zero_extend:SI
4731 (subreg:QI
4732 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4733 (match_operand:SI 2 "const_int_operand" "")) 3))
4734 (const_int 0)))
4735 (set (match_operand:SI 0 "gpc_reg_operand" "")
4736 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4737 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4738 [(set (match_dup 0)
4739 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4740 (set (match_dup 3)
4741 (compare:CC (match_dup 0)
4742 (const_int 0)))]
4743 "")
4745 (define_insn "*lshiftrt_internal4le"
4746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4747 (zero_extend:SI
4748 (subreg:HI
4749 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4750 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4751 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4752 "rlwinm %0,%1,%s2,0xffff"
4753 [(set_attr "type" "shift")])
4755 (define_insn "*lshiftrt_internal4be"
4756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4757 (zero_extend:SI
4758 (subreg:HI
4759 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4760 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4761 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4762 "rlwinm %0,%1,%s2,0xffff"
4763 [(set_attr "type" "shift")])
4765 (define_insn "*lshiftrt_internal5le"
4766 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4767 (compare:CC
4768 (zero_extend:SI
4769 (subreg:HI
4770 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4771 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4772 (const_int 0)))
4773 (clobber (match_scratch:SI 3 "=r,r"))]
4774 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4775 "@
4776 rlwinm. %3,%1,%s2,0xffff
4777 #"
4778 [(set_attr "type" "shift")
4779 (set_attr "dot" "yes")
4780 (set_attr "length" "4,8")])
4782 (define_insn "*lshiftrt_internal5be"
4783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4784 (compare:CC
4785 (zero_extend:SI
4786 (subreg:HI
4787 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4788 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4789 (const_int 0)))
4790 (clobber (match_scratch:SI 3 "=r,r"))]
4791 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4792 "@
4793 rlwinm. %3,%1,%s2,0xffff
4794 #"
4795 [(set_attr "type" "shift")
4796 (set_attr "dot" "yes")
4797 (set_attr "length" "4,8")])
4799 (define_split
4800 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4801 (compare:CC
4802 (zero_extend:SI
4803 (subreg:HI
4804 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4805 (match_operand:SI 2 "const_int_operand" "")) 0))
4806 (const_int 0)))
4807 (clobber (match_scratch:SI 3 ""))]
4808 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4809 [(set (match_dup 3)
4810 (zero_extend:SI (subreg:HI
4811 (lshiftrt:SI (match_dup 1)
4812 (match_dup 2)) 0)))
4813 (set (match_dup 0)
4814 (compare:CC (match_dup 3)
4815 (const_int 0)))]
4816 "")
4818 (define_split
4819 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4820 (compare:CC
4821 (zero_extend:SI
4822 (subreg:HI
4823 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4824 (match_operand:SI 2 "const_int_operand" "")) 2))
4825 (const_int 0)))
4826 (clobber (match_scratch:SI 3 ""))]
4827 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4828 [(set (match_dup 3)
4829 (zero_extend:SI (subreg:HI
4830 (lshiftrt:SI (match_dup 1)
4831 (match_dup 2)) 2)))
4832 (set (match_dup 0)
4833 (compare:CC (match_dup 3)
4834 (const_int 0)))]
4835 "")
4837 (define_insn "*lshiftrt_internal5le"
4838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4839 (compare:CC
4840 (zero_extend:SI
4841 (subreg:HI
4842 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4843 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4844 (const_int 0)))
4845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4846 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4847 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4848 "@
4849 rlwinm. %0,%1,%s2,0xffff
4850 #"
4851 [(set_attr "type" "shift")
4852 (set_attr "dot" "yes")
4853 (set_attr "length" "4,8")])
4855 (define_insn "*lshiftrt_internal5be"
4856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4857 (compare:CC
4858 (zero_extend:SI
4859 (subreg:HI
4860 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4861 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4862 (const_int 0)))
4863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4864 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4865 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4866 "@
4867 rlwinm. %0,%1,%s2,0xffff
4868 #"
4869 [(set_attr "type" "shift")
4870 (set_attr "dot" "yes")
4871 (set_attr "length" "4,8")])
4873 (define_split
4874 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4875 (compare:CC
4876 (zero_extend:SI
4877 (subreg:HI
4878 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4879 (match_operand:SI 2 "const_int_operand" "")) 0))
4880 (const_int 0)))
4881 (set (match_operand:SI 0 "gpc_reg_operand" "")
4882 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4883 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4884 [(set (match_dup 0)
4885 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4886 (set (match_dup 3)
4887 (compare:CC (match_dup 0)
4888 (const_int 0)))]
4889 "")
4891 (define_split
4892 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4893 (compare:CC
4894 (zero_extend:SI
4895 (subreg:HI
4896 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4897 (match_operand:SI 2 "const_int_operand" "")) 2))
4898 (const_int 0)))
4899 (set (match_operand:SI 0 "gpc_reg_operand" "")
4900 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4901 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4902 [(set (match_dup 0)
4903 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4904 (set (match_dup 3)
4905 (compare:CC (match_dup 0)
4906 (const_int 0)))]
4907 "")
4910 (define_expand "ashr<mode>3"
4911 [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4912 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4913 (match_operand:SI 2 "reg_or_cint_operand" "")))
4914 (clobber (reg:GPR CA_REGNO))])]
4915 ""
4916 {
4917 /* The generic code does not generate optimal code for the low word
4918 (it should be a rlwimi and a rot). Until we have target code to
4919 solve this generically, keep this expander. */
4921 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4922 {
4923 if (CONST_INT_P (operands[2]))
4924 {
4925 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4926 DONE;
4927 }
4928 else
4929 FAIL;
4930 }
4931 })
4933 (define_insn "*ashr<mode>3"
4934 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4935 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4936 (match_operand:SI 2 "reg_or_cint_operand" "rn")))
4937 (clobber (reg:GPR CA_REGNO))]
4938 ""
4939 "sra<wd>%I2 %0,%1,%<hH>2"
4940 [(set_attr "type" "shift")
4941 (set_attr "maybe_var_shift" "yes")])
4943 (define_insn "*ashrsi3_64"
4944 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4945 (sign_extend:DI
4946 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4947 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
4948 (clobber (reg:SI CA_REGNO))]
4949 "TARGET_POWERPC64"
4950 "sraw%I2 %0,%1,%h2"
4951 [(set_attr "type" "shift")
4952 (set_attr "maybe_var_shift" "yes")])
4954 (define_insn_and_split "*ashr<mode>3_dot"
4955 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4956 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4957 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4958 (const_int 0)))
4959 (clobber (match_scratch:GPR 0 "=r,r"))
4960 (clobber (reg:GPR CA_REGNO))]
4961 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4962 "@
4963 sra<wd>%I2. %0,%1,%<hH>2
4964 #"
4965 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4966 [(parallel [(set (match_dup 0)
4967 (ashiftrt:GPR (match_dup 1)
4968 (match_dup 2)))
4969 (clobber (reg:GPR CA_REGNO))])
4970 (set (match_dup 3)
4971 (compare:CC (match_dup 0)
4972 (const_int 0)))]
4973 ""
4974 [(set_attr "type" "shift")
4975 (set_attr "maybe_var_shift" "yes")
4976 (set_attr "dot" "yes")
4977 (set_attr "length" "4,8")])
4979 (define_insn_and_split "*ashr<mode>3_dot2"
4980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4981 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4982 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4983 (const_int 0)))
4984 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4985 (ashiftrt:GPR (match_dup 1)
4986 (match_dup 2)))
4987 (clobber (reg:GPR CA_REGNO))]
4988 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4989 "@
4990 sra<wd>%I2. %0,%1,%<hH>2
4991 #"
4992 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4993 [(parallel [(set (match_dup 0)
4994 (ashiftrt:GPR (match_dup 1)
4995 (match_dup 2)))
4996 (clobber (reg:GPR CA_REGNO))])
4997 (set (match_dup 3)
4998 (compare:CC (match_dup 0)
4999 (const_int 0)))]
5000 ""
5001 [(set_attr "type" "shift")
5002 (set_attr "maybe_var_shift" "yes")
5003 (set_attr "dot" "yes")
5004 (set_attr "length" "4,8")])
5005 \f
5006 ;; Builtins to replace a division to generate FRE reciprocal estimate
5007 ;; instructions and the necessary fixup instructions
5008 (define_expand "recip<mode>3"
5009 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5010 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5011 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5012 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5013 {
5014 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5015 DONE;
5016 })
5018 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5019 ;; hardware division. This is only done before register allocation and with
5020 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5021 (define_split
5022 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5023 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5024 (match_operand 2 "gpc_reg_operand" "")))]
5025 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5026 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5027 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5028 [(const_int 0)]
5029 {
5030 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5031 DONE;
5032 })
5034 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5035 ;; appropriate fixup.
5036 (define_expand "rsqrt<mode>2"
5037 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5038 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5039 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5040 {
5041 rs6000_emit_swrsqrt (operands[0], operands[1]);
5042 DONE;
5043 })
5044 \f
5045 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5046 ;; modes here, and also add in conditional vsx/power8-vector support to access
5047 ;; values in the traditional Altivec registers if the appropriate
5048 ;; -mupper-regs-{df,sf} option is enabled.
5050 (define_expand "abs<mode>2"
5051 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5052 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5053 "TARGET_<MODE>_INSN"
5054 "")
5056 (define_insn "*abs<mode>2_fpr"
5057 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5058 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5059 "TARGET_<MODE>_FPR"
5060 "@
5061 fabs %0,%1
5062 xsabsdp %x0,%x1"
5063 [(set_attr "type" "fp")
5064 (set_attr "fp_type" "fp_addsub_<Fs>")])
5066 (define_insn "*nabs<mode>2_fpr"
5067 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5068 (neg:SFDF
5069 (abs:SFDF
5070 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5071 "TARGET_<MODE>_FPR"
5072 "@
5073 fnabs %0,%1
5074 xsnabsdp %x0,%x1"
5075 [(set_attr "type" "fp")
5076 (set_attr "fp_type" "fp_addsub_<Fs>")])
5078 (define_expand "neg<mode>2"
5079 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5080 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5081 "TARGET_<MODE>_INSN"
5082 "")
5084 (define_insn "*neg<mode>2_fpr"
5085 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5086 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5087 "TARGET_<MODE>_FPR"
5088 "@
5089 fneg %0,%1
5090 xsnegdp %x0,%x1"
5091 [(set_attr "type" "fp")
5092 (set_attr "fp_type" "fp_addsub_<Fs>")])
5094 (define_expand "add<mode>3"
5095 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5096 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5097 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5098 "TARGET_<MODE>_INSN"
5099 "")
5101 (define_insn "*add<mode>3_fpr"
5102 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5103 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5104 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5105 "TARGET_<MODE>_FPR"
5106 "@
5107 fadd<Ftrad> %0,%1,%2
5108 xsadd<Fvsx> %x0,%x1,%x2"
5109 [(set_attr "type" "fp")
5110 (set_attr "fp_type" "fp_addsub_<Fs>")])
5112 (define_expand "sub<mode>3"
5113 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5114 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5115 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5116 "TARGET_<MODE>_INSN"
5117 "")
5119 (define_insn "*sub<mode>3_fpr"
5120 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5121 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5122 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5123 "TARGET_<MODE>_FPR"
5124 "@
5125 fsub<Ftrad> %0,%1,%2
5126 xssub<Fvsx> %x0,%x1,%x2"
5127 [(set_attr "type" "fp")
5128 (set_attr "fp_type" "fp_addsub_<Fs>")])
5130 (define_expand "mul<mode>3"
5131 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5132 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5133 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5134 "TARGET_<MODE>_INSN"
5135 "")
5137 (define_insn "*mul<mode>3_fpr"
5138 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5139 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5140 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5141 "TARGET_<MODE>_FPR"
5142 "@
5143 fmul<Ftrad> %0,%1,%2
5144 xsmul<Fvsx> %x0,%x1,%x2"
5145 [(set_attr "type" "dmul")
5146 (set_attr "fp_type" "fp_mul_<Fs>")])
5148 (define_expand "div<mode>3"
5149 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5150 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5151 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5152 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5153 "")
5155 (define_insn "*div<mode>3_fpr"
5156 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5157 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5158 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5159 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5160 "@
5161 fdiv<Ftrad> %0,%1,%2
5162 xsdiv<Fvsx> %x0,%x1,%x2"
5163 [(set_attr "type" "<Fs>div")
5164 (set_attr "fp_type" "fp_div_<Fs>")])
5166 (define_insn "sqrt<mode>2"
5167 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5168 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5169 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5170 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5171 "@
5172 fsqrt<Ftrad> %0,%1
5173 xssqrt<Fvsx> %x0,%x1"
5174 [(set_attr "type" "<Fs>sqrt")
5175 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5177 ;; Floating point reciprocal approximation
5178 (define_insn "fre<Fs>"
5179 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5180 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5181 UNSPEC_FRES))]
5182 "TARGET_<FFRE>"
5183 "@
5184 fre<Ftrad> %0,%1
5185 xsre<Fvsx> %x0,%x1"
5186 [(set_attr "type" "fp")])
5188 (define_insn "*rsqrt<mode>2"
5189 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5190 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5191 UNSPEC_RSQRT))]
5192 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5193 "@
5194 frsqrte<Ftrad> %0,%1
5195 xsrsqrte<Fvsx> %x0,%x1"
5196 [(set_attr "type" "fp")])
5198 ;; Floating point comparisons
5199 (define_insn "*cmp<mode>_fpr"
5200 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5201 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5202 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5203 "TARGET_<MODE>_FPR"
5204 "@
5205 fcmpu %0,%1,%2
5206 xscmpudp %0,%x1,%x2"
5207 [(set_attr "type" "fpcompare")])
5209 ;; Floating point conversions
5210 (define_expand "extendsfdf2"
5211 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5212 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5213 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5214 "")
5216 (define_insn_and_split "*extendsfdf2_fpr"
5217 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu")
5218 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5219 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5220 "@
5221 #
5222 fmr %0,%1
5223 lfs%U1%X1 %0,%1
5224 #
5225 xxlor %x0,%x1,%x1
5226 lxsspx %x0,%y1"
5227 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5228 [(const_int 0)]
5229 {
5230 emit_note (NOTE_INSN_DELETED);
5231 DONE;
5232 }
5233 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5235 (define_expand "truncdfsf2"
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5237 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5238 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5239 "")
5241 (define_insn "*truncdfsf2_fpr"
5242 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5243 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5244 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5245 "frsp %0,%1"
5246 [(set_attr "type" "fp")])
5248 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5249 ;; builtins.c and optabs.c that are not correct for IBM long double
5250 ;; when little-endian.
5251 (define_expand "signbittf2"
5252 [(set (match_dup 2)
5253 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5254 (set (match_dup 3)
5255 (subreg:DI (match_dup 2) 0))
5256 (set (match_dup 4)
5257 (match_dup 5))
5258 (set (match_operand:SI 0 "gpc_reg_operand" "")
5259 (match_dup 6))]
5260 "!TARGET_IEEEQUAD
5261 && TARGET_HARD_FLOAT
5262 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5263 && TARGET_LONG_DOUBLE_128"
5264 {
5265 operands[2] = gen_reg_rtx (DFmode);
5266 operands[3] = gen_reg_rtx (DImode);
5267 if (TARGET_POWERPC64)
5268 {
5269 operands[4] = gen_reg_rtx (DImode);
5270 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5271 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5272 WORDS_BIG_ENDIAN ? 4 : 0);
5273 }
5274 else
5275 {
5276 operands[4] = gen_reg_rtx (SImode);
5277 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5278 WORDS_BIG_ENDIAN ? 0 : 4);
5279 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5280 }
5281 })
5283 (define_expand "copysign<mode>3"
5284 [(set (match_dup 3)
5285 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5286 (set (match_dup 4)
5287 (neg:SFDF (abs:SFDF (match_dup 1))))
5288 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5289 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5290 (match_dup 5))
5291 (match_dup 3)
5292 (match_dup 4)))]
5293 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5294 && ((TARGET_PPC_GFXOPT
5295 && !HONOR_NANS (<MODE>mode)
5296 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5297 || TARGET_CMPB
5298 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5299 {
5300 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5301 {
5302 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5303 operands[2]));
5304 DONE;
5305 }
5307 operands[3] = gen_reg_rtx (<MODE>mode);
5308 operands[4] = gen_reg_rtx (<MODE>mode);
5309 operands[5] = CONST0_RTX (<MODE>mode);
5310 })
5312 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5313 ;; compiler from optimizing -0.0
5314 (define_insn "copysign<mode>3_fcpsgn"
5315 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5316 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5317 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5318 UNSPEC_COPYSIGN))]
5319 "TARGET_<MODE>_FPR && TARGET_CMPB"
5320 "@
5321 fcpsgn %0,%2,%1
5322 xscpsgndp %x0,%x2,%x1"
5323 [(set_attr "type" "fp")])
5325 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5326 ;; fsel instruction and some auxiliary computations. Then we just have a
5327 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5328 ;; combine.
5329 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5330 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5331 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5332 ;; define_splits to make them if made by combine. On VSX machines we have the
5333 ;; min/max instructions.
5334 ;;
5335 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5336 ;; to allow either DF/SF to use only traditional registers.
5338 (define_expand "smax<mode>3"
5339 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5340 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5341 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5342 (match_dup 1)
5343 (match_dup 2)))]
5344 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5345 {
5346 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5347 DONE;
5348 })
5350 (define_insn "*smax<mode>3_vsx"
5351 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5352 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5353 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5354 "TARGET_<MODE>_FPR && TARGET_VSX"
5355 "xsmaxdp %x0,%x1,%x2"
5356 [(set_attr "type" "fp")])
5358 (define_expand "smin<mode>3"
5359 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5360 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5361 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5362 (match_dup 2)
5363 (match_dup 1)))]
5364 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5365 {
5366 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5367 DONE;
5368 })
5370 (define_insn "*smin<mode>3_vsx"
5371 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5372 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5373 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5374 "TARGET_<MODE>_FPR && TARGET_VSX"
5375 "xsmindp %x0,%x1,%x2"
5376 [(set_attr "type" "fp")])
5378 (define_split
5379 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5380 (match_operator:SFDF 3 "min_max_operator"
5381 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5382 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5383 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5384 && !TARGET_VSX"
5385 [(const_int 0)]
5386 {
5387 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5388 operands[2]);
5389 DONE;
5390 })
5392 (define_split
5393 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5394 (match_operator:SF 3 "min_max_operator"
5395 [(match_operand:SF 1 "gpc_reg_operand" "")
5396 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5397 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5398 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5399 [(const_int 0)]
5400 "
5401 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5402 operands[1], operands[2]);
5403 DONE;
5404 }")
5406 (define_expand "mov<mode>cc"
5407 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5408 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5409 (match_operand:GPR 2 "gpc_reg_operand" "")
5410 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5411 "TARGET_ISEL<sel>"
5412 "
5413 {
5414 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5415 DONE;
5416 else
5417 FAIL;
5418 }")
5420 ;; We use the BASE_REGS for the isel input operands because, if rA is
5421 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5422 ;; because we may switch the operands and rB may end up being rA.
5423 ;;
5424 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5425 ;; leave out the mode in operand 4 and use one pattern, but reload can
5426 ;; change the mode underneath our feet and then gets confused trying
5427 ;; to reload the value.
5428 (define_insn "isel_signed_<mode>"
5429 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5430 (if_then_else:GPR
5431 (match_operator 1 "scc_comparison_operator"
5432 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5433 (const_int 0)])
5434 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5435 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5436 "TARGET_ISEL<sel>"
5437 "*
5438 { return output_isel (operands); }"
5439 [(set_attr "type" "isel")
5440 (set_attr "length" "4")])
5442 (define_insn "isel_unsigned_<mode>"
5443 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5444 (if_then_else:GPR
5445 (match_operator 1 "scc_comparison_operator"
5446 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5447 (const_int 0)])
5448 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5449 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5450 "TARGET_ISEL<sel>"
5451 "*
5452 { return output_isel (operands); }"
5453 [(set_attr "type" "isel")
5454 (set_attr "length" "4")])
5456 ;; These patterns can be useful for combine; they let combine know that
5457 ;; isel can handle reversed comparisons so long as the operands are
5458 ;; registers.
5460 (define_insn "*isel_reversed_signed_<mode>"
5461 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5462 (if_then_else:GPR
5463 (match_operator 1 "scc_rev_comparison_operator"
5464 [(match_operand:CC 4 "cc_reg_operand" "y")
5465 (const_int 0)])
5466 (match_operand:GPR 2 "gpc_reg_operand" "b")
5467 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5468 "TARGET_ISEL<sel>"
5469 "*
5470 { return output_isel (operands); }"
5471 [(set_attr "type" "isel")
5472 (set_attr "length" "4")])
5474 (define_insn "*isel_reversed_unsigned_<mode>"
5475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5476 (if_then_else:GPR
5477 (match_operator 1 "scc_rev_comparison_operator"
5478 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5479 (const_int 0)])
5480 (match_operand:GPR 2 "gpc_reg_operand" "b")
5481 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5482 "TARGET_ISEL<sel>"
5483 "*
5484 { return output_isel (operands); }"
5485 [(set_attr "type" "isel")
5486 (set_attr "length" "4")])
5488 (define_expand "movsfcc"
5489 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5490 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5491 (match_operand:SF 2 "gpc_reg_operand" "")
5492 (match_operand:SF 3 "gpc_reg_operand" "")))]
5493 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5494 "
5495 {
5496 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5497 DONE;
5498 else
5499 FAIL;
5500 }")
5502 (define_insn "*fselsfsf4"
5503 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5504 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5505 (match_operand:SF 4 "zero_fp_constant" "F"))
5506 (match_operand:SF 2 "gpc_reg_operand" "f")
5507 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5508 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5509 "fsel %0,%1,%2,%3"
5510 [(set_attr "type" "fp")])
5512 (define_insn "*fseldfsf4"
5513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5514 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5515 (match_operand:DF 4 "zero_fp_constant" "F"))
5516 (match_operand:SF 2 "gpc_reg_operand" "f")
5517 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5518 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5519 "fsel %0,%1,%2,%3"
5520 [(set_attr "type" "fp")])
5522 ;; The conditional move instructions allow us to perform max and min
5523 ;; operations even when
5525 (define_split
5526 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5527 (match_operator:DF 3 "min_max_operator"
5528 [(match_operand:DF 1 "gpc_reg_operand" "")
5529 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5530 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5531 && !flag_trapping_math"
5532 [(const_int 0)]
5533 "
5534 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5535 operands[1], operands[2]);
5536 DONE;
5537 }")
5539 (define_expand "movdfcc"
5540 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5541 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5542 (match_operand:DF 2 "gpc_reg_operand" "")
5543 (match_operand:DF 3 "gpc_reg_operand" "")))]
5544 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5545 "
5546 {
5547 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5548 DONE;
5549 else
5550 FAIL;
5551 }")
5553 (define_insn "*fseldfdf4"
5554 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5555 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5556 (match_operand:DF 4 "zero_fp_constant" "F"))
5557 (match_operand:DF 2 "gpc_reg_operand" "d")
5558 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5559 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5560 "fsel %0,%1,%2,%3"
5561 [(set_attr "type" "fp")])
5563 (define_insn "*fselsfdf4"
5564 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5565 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5566 (match_operand:SF 4 "zero_fp_constant" "F"))
5567 (match_operand:DF 2 "gpc_reg_operand" "d")
5568 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5569 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5570 "fsel %0,%1,%2,%3"
5571 [(set_attr "type" "fp")])
5572 \f
5573 ;; Conversions to and from floating-point.
5575 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5576 ; don't want to support putting SImode in FPR registers.
5577 (define_insn "lfiwax"
5578 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5579 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5580 UNSPEC_LFIWAX))]
5581 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5582 "@
5583 lfiwax %0,%y1
5584 lxsiwax %x0,%y1
5585 mtvsrwa %x0,%1"
5586 [(set_attr "type" "fpload,fpload,mffgpr")])
5588 ; This split must be run before register allocation because it allocates the
5589 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5590 ; it earlier to allow for the combiner to merge insns together where it might
5591 ; not be needed and also in case the insns are deleted as dead code.
5593 (define_insn_and_split "floatsi<mode>2_lfiwax"
5594 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5595 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5596 (clobber (match_scratch:DI 2 "=wj"))]
5597 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5598 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5599 "#"
5600 ""
5601 [(pc)]
5602 "
5603 {
5604 rtx dest = operands[0];
5605 rtx src = operands[1];
5606 rtx tmp;
5608 if (!MEM_P (src) && TARGET_POWERPC64
5609 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5610 tmp = convert_to_mode (DImode, src, false);
5611 else
5612 {
5613 tmp = operands[2];
5614 if (GET_CODE (tmp) == SCRATCH)
5615 tmp = gen_reg_rtx (DImode);
5616 if (MEM_P (src))
5617 {
5618 src = rs6000_address_for_fpconvert (src);
5619 emit_insn (gen_lfiwax (tmp, src));
5620 }
5621 else
5622 {
5623 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5624 emit_move_insn (stack, src);
5625 emit_insn (gen_lfiwax (tmp, stack));
5626 }
5627 }
5628 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5629 DONE;
5630 }"
5631 [(set_attr "length" "12")
5632 (set_attr "type" "fpload")])
5634 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5635 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5636 (float:SFDF
5637 (sign_extend:DI
5638 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5639 (clobber (match_scratch:DI 2 "=0,d"))]
5640 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5641 && <SI_CONVERT_FP>"
5642 "#"
5643 ""
5644 [(pc)]
5645 "
5646 {
5647 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5648 if (GET_CODE (operands[2]) == SCRATCH)
5649 operands[2] = gen_reg_rtx (DImode);
5650 emit_insn (gen_lfiwax (operands[2], operands[1]));
5651 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5652 DONE;
5653 }"
5654 [(set_attr "length" "8")
5655 (set_attr "type" "fpload")])
5657 (define_insn "lfiwzx"
5658 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5659 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5660 UNSPEC_LFIWZX))]
5661 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5662 "@
5663 lfiwzx %0,%y1
5664 lxsiwzx %x0,%y1
5665 mtvsrwz %x0,%1"
5666 [(set_attr "type" "fpload,fpload,mftgpr")])
5668 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5669 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5670 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5671 (clobber (match_scratch:DI 2 "=wj"))]
5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5673 && <SI_CONVERT_FP>"
5674 "#"
5675 ""
5676 [(pc)]
5677 "
5678 {
5679 rtx dest = operands[0];
5680 rtx src = operands[1];
5681 rtx tmp;
5683 if (!MEM_P (src) && TARGET_POWERPC64
5684 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5685 tmp = convert_to_mode (DImode, src, true);
5686 else
5687 {
5688 tmp = operands[2];
5689 if (GET_CODE (tmp) == SCRATCH)
5690 tmp = gen_reg_rtx (DImode);
5691 if (MEM_P (src))
5692 {
5693 src = rs6000_address_for_fpconvert (src);
5694 emit_insn (gen_lfiwzx (tmp, src));
5695 }
5696 else
5697 {
5698 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5699 emit_move_insn (stack, src);
5700 emit_insn (gen_lfiwzx (tmp, stack));
5701 }
5702 }
5703 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5704 DONE;
5705 }"
5706 [(set_attr "length" "12")
5707 (set_attr "type" "fpload")])
5709 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5710 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5711 (unsigned_float:SFDF
5712 (zero_extend:DI
5713 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5714 (clobber (match_scratch:DI 2 "=0,d"))]
5715 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5716 && <SI_CONVERT_FP>"
5717 "#"
5718 ""
5719 [(pc)]
5720 "
5721 {
5722 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5723 if (GET_CODE (operands[2]) == SCRATCH)
5724 operands[2] = gen_reg_rtx (DImode);
5725 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5726 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5727 DONE;
5728 }"
5729 [(set_attr "length" "8")
5730 (set_attr "type" "fpload")])
5732 ; For each of these conversions, there is a define_expand, a define_insn
5733 ; with a '#' template, and a define_split (with C code). The idea is
5734 ; to allow constant folding with the template of the define_insn,
5735 ; then to have the insns split later (between sched1 and final).
5737 (define_expand "floatsidf2"
5738 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5739 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5740 (use (match_dup 2))
5741 (use (match_dup 3))
5742 (clobber (match_dup 4))
5743 (clobber (match_dup 5))
5744 (clobber (match_dup 6))])]
5745 "TARGET_HARD_FLOAT
5746 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5747 "
5748 {
5749 if (TARGET_E500_DOUBLE)
5750 {
5751 if (!REG_P (operands[1]))
5752 operands[1] = force_reg (SImode, operands[1]);
5753 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5754 DONE;
5755 }
5756 else if (TARGET_LFIWAX && TARGET_FCFID)
5757 {
5758 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5759 DONE;
5760 }
5761 else if (TARGET_FCFID)
5762 {
5763 rtx dreg = operands[1];
5764 if (!REG_P (dreg))
5765 dreg = force_reg (SImode, dreg);
5766 dreg = convert_to_mode (DImode, dreg, false);
5767 emit_insn (gen_floatdidf2 (operands[0], dreg));
5768 DONE;
5769 }
5771 if (!REG_P (operands[1]))
5772 operands[1] = force_reg (SImode, operands[1]);
5773 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5774 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5775 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5776 operands[5] = gen_reg_rtx (DFmode);
5777 operands[6] = gen_reg_rtx (SImode);
5778 }")
5780 (define_insn_and_split "*floatsidf2_internal"
5781 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5782 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5783 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5784 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5785 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5786 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5787 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5788 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5789 "#"
5790 ""
5791 [(pc)]
5792 "
5793 {
5794 rtx lowword, highword;
5795 gcc_assert (MEM_P (operands[4]));
5796 highword = adjust_address (operands[4], SImode, 0);
5797 lowword = adjust_address (operands[4], SImode, 4);
5798 if (! WORDS_BIG_ENDIAN)
5799 std::swap (lowword, highword);
5801 emit_insn (gen_xorsi3 (operands[6], operands[1],
5802 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5803 emit_move_insn (lowword, operands[6]);
5804 emit_move_insn (highword, operands[2]);
5805 emit_move_insn (operands[5], operands[4]);
5806 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5807 DONE;
5808 }"
5809 [(set_attr "length" "24")
5810 (set_attr "type" "fp")])
5812 ;; If we don't have a direct conversion to single precision, don't enable this
5813 ;; conversion for 32-bit without fast math, because we don't have the insn to
5814 ;; generate the fixup swizzle to avoid double rounding problems.
5815 (define_expand "floatunssisf2"
5816 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5817 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5818 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5819 && (!TARGET_FPRS
5820 || (TARGET_FPRS
5821 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5822 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5823 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5824 "
5825 {
5826 if (!TARGET_FPRS)
5827 {
5828 if (!REG_P (operands[1]))
5829 operands[1] = force_reg (SImode, operands[1]);
5830 }
5831 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5832 {
5833 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5834 DONE;
5835 }
5836 else
5837 {
5838 rtx dreg = operands[1];
5839 if (!REG_P (dreg))
5840 dreg = force_reg (SImode, dreg);
5841 dreg = convert_to_mode (DImode, dreg, true);
5842 emit_insn (gen_floatdisf2 (operands[0], dreg));
5843 DONE;
5844 }
5845 }")
5847 (define_expand "floatunssidf2"
5848 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5849 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5850 (use (match_dup 2))
5851 (use (match_dup 3))
5852 (clobber (match_dup 4))
5853 (clobber (match_dup 5))])]
5854 "TARGET_HARD_FLOAT
5855 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5856 "
5857 {
5858 if (TARGET_E500_DOUBLE)
5859 {
5860 if (!REG_P (operands[1]))
5861 operands[1] = force_reg (SImode, operands[1]);
5862 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5863 DONE;
5864 }
5865 else if (TARGET_LFIWZX && TARGET_FCFID)
5866 {
5867 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5868 DONE;
5869 }
5870 else if (TARGET_FCFID)
5871 {
5872 rtx dreg = operands[1];
5873 if (!REG_P (dreg))
5874 dreg = force_reg (SImode, dreg);
5875 dreg = convert_to_mode (DImode, dreg, true);
5876 emit_insn (gen_floatdidf2 (operands[0], dreg));
5877 DONE;
5878 }
5880 if (!REG_P (operands[1]))
5881 operands[1] = force_reg (SImode, operands[1]);
5882 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5883 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5884 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5885 operands[5] = gen_reg_rtx (DFmode);
5886 }")
5888 (define_insn_and_split "*floatunssidf2_internal"
5889 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5890 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5891 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5892 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5893 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5894 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5895 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5896 && !(TARGET_FCFID && TARGET_POWERPC64)"
5897 "#"
5898 ""
5899 [(pc)]
5900 "
5901 {
5902 rtx lowword, highword;
5903 gcc_assert (MEM_P (operands[4]));
5904 highword = adjust_address (operands[4], SImode, 0);
5905 lowword = adjust_address (operands[4], SImode, 4);
5906 if (! WORDS_BIG_ENDIAN)
5907 std::swap (lowword, highword);
5909 emit_move_insn (lowword, operands[1]);
5910 emit_move_insn (highword, operands[2]);
5911 emit_move_insn (operands[5], operands[4]);
5912 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5913 DONE;
5914 }"
5915 [(set_attr "length" "20")
5916 (set_attr "type" "fp")])
5918 (define_expand "fix_trunc<mode>si2"
5919 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5920 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5921 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5922 "
5923 {
5924 if (!<E500_CONVERT>)
5925 {
5926 rtx tmp, stack;
5928 if (TARGET_STFIWX)
5929 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5930 else
5931 {
5932 tmp = gen_reg_rtx (DImode);
5933 stack = rs6000_allocate_stack_temp (DImode, true, false);
5934 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5935 tmp, stack));
5936 }
5937 DONE;
5938 }
5939 }")
5941 ; Like the convert to float patterns, this insn must be split before
5942 ; register allocation so that it can allocate the memory slot if it
5943 ; needed
5944 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5945 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5946 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5947 (clobber (match_scratch:DI 2 "=d"))]
5948 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5949 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5950 && TARGET_STFIWX && can_create_pseudo_p ()"
5951 "#"
5952 ""
5953 [(pc)]
5954 {
5955 rtx dest = operands[0];
5956 rtx src = operands[1];
5957 rtx tmp = operands[2];
5959 if (GET_CODE (tmp) == SCRATCH)
5960 tmp = gen_reg_rtx (DImode);
5962 emit_insn (gen_fctiwz_<mode> (tmp, src));
5963 if (MEM_P (dest))
5964 {
5965 dest = rs6000_address_for_fpconvert (dest);
5966 emit_insn (gen_stfiwx (dest, tmp));
5967 DONE;
5968 }
5969 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5970 {
5971 dest = gen_lowpart (DImode, dest);
5972 emit_move_insn (dest, tmp);
5973 DONE;
5974 }
5975 else
5976 {
5977 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5978 emit_insn (gen_stfiwx (stack, tmp));
5979 emit_move_insn (dest, stack);
5980 DONE;
5981 }
5982 }
5983 [(set_attr "length" "12")
5984 (set_attr "type" "fp")])
5986 (define_insn_and_split "fix_trunc<mode>si2_internal"
5987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5988 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5989 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5990 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5991 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5992 "#"
5993 ""
5994 [(pc)]
5995 "
5996 {
5997 rtx lowword;
5998 gcc_assert (MEM_P (operands[3]));
5999 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6001 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6002 emit_move_insn (operands[3], operands[2]);
6003 emit_move_insn (operands[0], lowword);
6004 DONE;
6005 }"
6006 [(set_attr "length" "16")
6007 (set_attr "type" "fp")])
6009 (define_expand "fix_trunc<mode>di2"
6010 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6011 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6012 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6013 && TARGET_FCFID"
6014 "")
6016 (define_insn "*fix_trunc<mode>di2_fctidz"
6017 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
6018 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
6019 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6020 && TARGET_FCFID"
6021 "@
6022 fctidz %0,%1
6023 xscvdpsxds %x0,%x1"
6024 [(set_attr "type" "fp")])
6026 (define_expand "fixuns_trunc<mode>si2"
6027 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6028 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6029 "TARGET_HARD_FLOAT
6030 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6031 || <E500_CONVERT>)"
6032 "
6033 {
6034 if (!<E500_CONVERT>)
6035 {
6036 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6037 DONE;
6038 }
6039 }")
6041 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6042 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6043 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6044 (clobber (match_scratch:DI 2 "=d"))]
6045 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6046 && TARGET_STFIWX && can_create_pseudo_p ()"
6047 "#"
6048 ""
6049 [(pc)]
6050 {
6051 rtx dest = operands[0];
6052 rtx src = operands[1];
6053 rtx tmp = operands[2];
6055 if (GET_CODE (tmp) == SCRATCH)
6056 tmp = gen_reg_rtx (DImode);
6058 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6059 if (MEM_P (dest))
6060 {
6061 dest = rs6000_address_for_fpconvert (dest);
6062 emit_insn (gen_stfiwx (dest, tmp));
6063 DONE;
6064 }
6065 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6066 {
6067 dest = gen_lowpart (DImode, dest);
6068 emit_move_insn (dest, tmp);
6069 DONE;
6070 }
6071 else
6072 {
6073 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6074 emit_insn (gen_stfiwx (stack, tmp));
6075 emit_move_insn (dest, stack);
6076 DONE;
6077 }
6078 }
6079 [(set_attr "length" "12")
6080 (set_attr "type" "fp")])
6082 (define_expand "fixuns_trunc<mode>di2"
6083 [(set (match_operand:DI 0 "register_operand" "")
6084 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6085 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6086 "")
6088 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6089 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
6090 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
6091 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6092 && TARGET_FCTIDUZ"
6093 "@
6094 fctiduz %0,%1
6095 xscvdpuxds %x0,%x1"
6096 [(set_attr "type" "fp")])
6098 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6099 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6100 ; because the first makes it clear that operand 0 is not live
6101 ; before the instruction.
6102 (define_insn "fctiwz_<mode>"
6103 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
6104 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
6105 UNSPEC_FCTIWZ))]
6106 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6107 "@
6108 fctiwz %0,%1
6109 xscvdpsxws %x0,%x1"
6110 [(set_attr "type" "fp")])
6112 (define_insn "fctiwuz_<mode>"
6113 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
6114 (unspec:DI [(unsigned_fix:SI
6115 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
6116 UNSPEC_FCTIWUZ))]
6117 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6118 "@
6119 fctiwuz %0,%1
6120 xscvdpuxws %x0,%x1"
6121 [(set_attr "type" "fp")])
6123 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6124 ;; since the friz instruction does not truncate the value if the floating
6125 ;; point value is < LONG_MIN or > LONG_MAX.
6126 (define_insn "*friz"
6127 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6128 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
6129 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6130 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
6131 "@
6132 friz %0,%1
6133 xsrdpiz %x0,%x1"
6134 [(set_attr "type" "fp")])
6136 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6137 ;; load to properly sign extend the value, but at least doing a store, load
6138 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6139 ;; if we have 32-bit memory ops
6140 (define_insn_and_split "*round32<mode>2_fprs"
6141 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6142 (float:SFDF
6143 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6144 (clobber (match_scratch:DI 2 "=d"))
6145 (clobber (match_scratch:DI 3 "=d"))]
6146 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6147 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6148 && can_create_pseudo_p ()"
6149 "#"
6150 ""
6151 [(pc)]
6152 {
6153 rtx dest = operands[0];
6154 rtx src = operands[1];
6155 rtx tmp1 = operands[2];
6156 rtx tmp2 = operands[3];
6157 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6159 if (GET_CODE (tmp1) == SCRATCH)
6160 tmp1 = gen_reg_rtx (DImode);
6161 if (GET_CODE (tmp2) == SCRATCH)
6162 tmp2 = gen_reg_rtx (DImode);
6164 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6165 emit_insn (gen_stfiwx (stack, tmp1));
6166 emit_insn (gen_lfiwax (tmp2, stack));
6167 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6168 DONE;
6169 }
6170 [(set_attr "type" "fpload")
6171 (set_attr "length" "16")])
6173 (define_insn_and_split "*roundu32<mode>2_fprs"
6174 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6175 (unsigned_float:SFDF
6176 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6177 (clobber (match_scratch:DI 2 "=d"))
6178 (clobber (match_scratch:DI 3 "=d"))]
6179 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6180 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6181 && can_create_pseudo_p ()"
6182 "#"
6183 ""
6184 [(pc)]
6185 {
6186 rtx dest = operands[0];
6187 rtx src = operands[1];
6188 rtx tmp1 = operands[2];
6189 rtx tmp2 = operands[3];
6190 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6192 if (GET_CODE (tmp1) == SCRATCH)
6193 tmp1 = gen_reg_rtx (DImode);
6194 if (GET_CODE (tmp2) == SCRATCH)
6195 tmp2 = gen_reg_rtx (DImode);
6197 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6198 emit_insn (gen_stfiwx (stack, tmp1));
6199 emit_insn (gen_lfiwzx (tmp2, stack));
6200 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6201 DONE;
6202 }
6203 [(set_attr "type" "fpload")
6204 (set_attr "length" "16")])
6206 ;; No VSX equivalent to fctid
6207 (define_insn "lrint<mode>di2"
6208 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6209 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6210 UNSPEC_FCTID))]
6211 "TARGET_<MODE>_FPR && TARGET_FPRND"
6212 "fctid %0,%1"
6213 [(set_attr "type" "fp")])
6215 (define_insn "btrunc<mode>2"
6216 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6217 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6218 UNSPEC_FRIZ))]
6219 "TARGET_<MODE>_FPR && TARGET_FPRND"
6220 "@
6221 friz %0,%1
6222 xsrdpiz %x0,%x1"
6223 [(set_attr "type" "fp")
6224 (set_attr "fp_type" "fp_addsub_<Fs>")])
6226 (define_insn "ceil<mode>2"
6227 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6228 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6229 UNSPEC_FRIP))]
6230 "TARGET_<MODE>_FPR && TARGET_FPRND"
6231 "@
6232 frip %0,%1
6233 xsrdpip %x0,%x1"
6234 [(set_attr "type" "fp")
6235 (set_attr "fp_type" "fp_addsub_<Fs>")])
6237 (define_insn "floor<mode>2"
6238 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6239 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6240 UNSPEC_FRIM))]
6241 "TARGET_<MODE>_FPR && TARGET_FPRND"
6242 "@
6243 frim %0,%1
6244 xsrdpim %x0,%x1"
6245 [(set_attr "type" "fp")
6246 (set_attr "fp_type" "fp_addsub_<Fs>")])
6248 ;; No VSX equivalent to frin
6249 (define_insn "round<mode>2"
6250 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6251 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6252 UNSPEC_FRIN))]
6253 "TARGET_<MODE>_FPR && TARGET_FPRND"
6254 "frin %0,%1"
6255 [(set_attr "type" "fp")
6256 (set_attr "fp_type" "fp_addsub_<Fs>")])
6258 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6259 (define_insn "stfiwx"
6260 [(set (match_operand:SI 0 "memory_operand" "=Z")
6261 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6262 UNSPEC_STFIWX))]
6263 "TARGET_PPC_GFXOPT"
6264 "stfiwx %1,%y0"
6265 [(set_attr "type" "fpstore")])
6267 ;; If we don't have a direct conversion to single precision, don't enable this
6268 ;; conversion for 32-bit without fast math, because we don't have the insn to
6269 ;; generate the fixup swizzle to avoid double rounding problems.
6270 (define_expand "floatsisf2"
6271 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6272 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6273 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6274 && (!TARGET_FPRS
6275 || (TARGET_FPRS
6276 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6277 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6278 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6279 "
6280 {
6281 if (!TARGET_FPRS)
6282 {
6283 if (!REG_P (operands[1]))
6284 operands[1] = force_reg (SImode, operands[1]);
6285 }
6286 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6287 {
6288 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6289 DONE;
6290 }
6291 else if (TARGET_FCFID && TARGET_LFIWAX)
6292 {
6293 rtx dfreg = gen_reg_rtx (DFmode);
6294 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6295 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6296 DONE;
6297 }
6298 else
6299 {
6300 rtx dreg = operands[1];
6301 if (!REG_P (dreg))
6302 dreg = force_reg (SImode, dreg);
6303 dreg = convert_to_mode (DImode, dreg, false);
6304 emit_insn (gen_floatdisf2 (operands[0], dreg));
6305 DONE;
6306 }
6307 }")
6309 (define_expand "floatdidf2"
6310 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6311 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6312 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6313 "")
6315 (define_insn "*floatdidf2_fpr"
6316 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6317 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6318 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6319 "@
6320 fcfid %0,%1
6321 xscvsxddp %x0,%x1"
6322 [(set_attr "type" "fp")])
6324 ; Allow the combiner to merge source memory operands to the conversion so that
6325 ; the optimizer/register allocator doesn't try to load the value too early in a
6326 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6327 ; hit. We will split after reload to avoid the trip through the GPRs
6329 (define_insn_and_split "*floatdidf2_mem"
6330 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6331 (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6332 (clobber (match_scratch:DI 2 "=d,wi"))]
6333 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6334 "#"
6335 "&& reload_completed"
6336 [(set (match_dup 2) (match_dup 1))
6337 (set (match_dup 0) (float:DF (match_dup 2)))]
6338 ""
6339 [(set_attr "length" "8")
6340 (set_attr "type" "fpload")])
6342 (define_expand "floatunsdidf2"
6343 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6344 (unsigned_float:DF
6345 (match_operand:DI 1 "gpc_reg_operand" "")))]
6346 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6347 "")
6349 (define_insn "*floatunsdidf2_fcfidu"
6350 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6351 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6352 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6353 "@
6354 fcfidu %0,%1
6355 xscvuxddp %x0,%x1"
6356 [(set_attr "type" "fp")
6357 (set_attr "length" "4")])
6359 (define_insn_and_split "*floatunsdidf2_mem"
6360 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6361 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6362 (clobber (match_scratch:DI 2 "=d,wi"))]
6363 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6364 "#"
6365 "&& reload_completed"
6366 [(set (match_dup 2) (match_dup 1))
6367 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6368 ""
6369 [(set_attr "length" "8")
6370 (set_attr "type" "fpload")])
6372 (define_expand "floatdisf2"
6373 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6374 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6375 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6376 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6377 "
6378 {
6379 if (!TARGET_FCFIDS)
6380 {
6381 rtx val = operands[1];
6382 if (!flag_unsafe_math_optimizations)
6383 {
6384 rtx label = gen_label_rtx ();
6385 val = gen_reg_rtx (DImode);
6386 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6387 emit_label (label);
6388 }
6389 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6390 DONE;
6391 }
6392 }")
6394 (define_insn "floatdisf2_fcfids"
6395 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
6396 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6397 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6398 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6399 "@
6400 fcfids %0,%1
6401 xscvsxdsp %x0,%x1"
6402 [(set_attr "type" "fp")])
6404 (define_insn_and_split "*floatdisf2_mem"
6405 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6406 (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6407 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6408 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6409 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6410 "#"
6411 "&& reload_completed"
6412 [(pc)]
6413 "
6414 {
6415 emit_move_insn (operands[2], operands[1]);
6416 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6417 DONE;
6418 }"
6419 [(set_attr "length" "8")])
6421 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6422 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6423 ;; from double rounding.
6424 ;; Instead of creating a new cpu type for two FP operations, just use fp
6425 (define_insn_and_split "floatdisf2_internal1"
6426 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6427 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6428 (clobber (match_scratch:DF 2 "=d"))]
6429 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6430 && !TARGET_FCFIDS"
6431 "#"
6432 "&& reload_completed"
6433 [(set (match_dup 2)
6434 (float:DF (match_dup 1)))
6435 (set (match_dup 0)
6436 (float_truncate:SF (match_dup 2)))]
6437 ""
6438 [(set_attr "length" "8")
6439 (set_attr "type" "fp")])
6441 ;; Twiddles bits to avoid double rounding.
6442 ;; Bits that might be truncated when converting to DFmode are replaced
6443 ;; by a bit that won't be lost at that stage, but is below the SFmode
6444 ;; rounding position.
6445 (define_expand "floatdisf2_internal2"
6446 [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6447 (const_int 53)))
6448 (clobber (reg:DI CA_REGNO))])
6449 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6450 (const_int 2047)))
6451 (set (match_dup 3) (plus:DI (match_dup 3)
6452 (const_int 1)))
6453 (set (match_dup 0) (plus:DI (match_dup 0)
6454 (const_int 2047)))
6455 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6456 (const_int 2)))
6457 (set (match_dup 0) (ior:DI (match_dup 0)
6458 (match_dup 1)))
6459 (set (match_dup 0) (and:DI (match_dup 0)
6460 (const_int -2048)))
6461 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6462 (label_ref (match_operand:DI 2 "" ""))
6463 (pc)))
6464 (set (match_dup 0) (match_dup 1))]
6465 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6466 && !TARGET_FCFIDS"
6467 "
6468 {
6469 operands[3] = gen_reg_rtx (DImode);
6470 operands[4] = gen_reg_rtx (CCUNSmode);
6471 }")
6473 (define_expand "floatunsdisf2"
6474 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6475 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6476 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6477 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6478 "")
6480 (define_insn "floatunsdisf2_fcfidus"
6481 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
6482 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6483 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6484 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6485 "@
6486 fcfidus %0,%1
6487 xscvuxdsp %x0,%x1"
6488 [(set_attr "type" "fp")])
6490 (define_insn_and_split "*floatunsdisf2_mem"
6491 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6492 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6493 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6494 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6495 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6496 "#"
6497 "&& reload_completed"
6498 [(pc)]
6499 "
6500 {
6501 emit_move_insn (operands[2], operands[1]);
6502 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6503 DONE;
6504 }"
6505 [(set_attr "length" "8")
6506 (set_attr "type" "fpload")])
6507 \f
6508 ;; Define the TImode operations that can be done in a small number
6509 ;; of instructions. The & constraints are to prevent the register
6510 ;; allocator from allocating registers that overlap with the inputs
6511 ;; (for example, having an input in 7,8 and an output in 6,7). We
6512 ;; also allow for the output being the same as one of the inputs.
6514 (define_expand "addti3"
6515 [(set (match_operand:TI 0 "gpc_reg_operand" "")
6516 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "")
6517 (match_operand:TI 2 "reg_or_short_operand" "")))]
6518 "TARGET_64BIT"
6519 {
6520 rtx lo0 = gen_lowpart (DImode, operands[0]);
6521 rtx lo1 = gen_lowpart (DImode, operands[1]);
6522 rtx lo2 = gen_lowpart (DImode, operands[2]);
6523 rtx hi0 = gen_highpart (DImode, operands[0]);
6524 rtx hi1 = gen_highpart (DImode, operands[1]);
6525 rtx hi2 = gen_highpart_mode (DImode, TImode, operands[2]);
6527 if (!reg_or_short_operand (lo2, DImode))
6528 lo2 = force_reg (DImode, lo2);
6529 if (!adde_operand (hi2, DImode))
6530 hi2 = force_reg (DImode, hi2);
6532 emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
6533 emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
6534 DONE;
6535 })
6537 (define_expand "subti3"
6538 [(set (match_operand:TI 0 "gpc_reg_operand" "")
6539 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "")
6540 (match_operand:TI 2 "gpc_reg_operand" "")))]
6541 "TARGET_64BIT"
6542 {
6543 rtx lo0 = gen_lowpart (DImode, operands[0]);
6544 rtx lo1 = gen_lowpart (DImode, operands[1]);
6545 rtx lo2 = gen_lowpart (DImode, operands[2]);
6546 rtx hi0 = gen_highpart (DImode, operands[0]);
6547 rtx hi1 = gen_highpart_mode (DImode, TImode, operands[1]);
6548 rtx hi2 = gen_highpart (DImode, operands[2]);
6550 if (!reg_or_short_operand (lo1, DImode))
6551 lo1 = force_reg (DImode, lo1);
6552 if (!adde_operand (hi1, DImode))
6553 hi1 = force_reg (DImode, hi1);
6555 emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
6556 emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
6557 DONE;
6558 })
6561 ;; Shift by a variable amount is too complex to be worth open-coding. We
6562 ;; just handle shifts by constants.
6563 (define_insn "ashrdi3_no_power"
6564 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6565 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6566 (match_operand:SI 2 "const_int_operand" "M,i")))
6567 (clobber (reg:SI CA_REGNO))]
6568 "!TARGET_POWERPC64"
6569 {
6570 switch (which_alternative)
6571 {
6572 default:
6573 gcc_unreachable ();
6574 case 0:
6575 if (WORDS_BIG_ENDIAN)
6576 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6577 else
6578 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6579 case 1:
6580 if (WORDS_BIG_ENDIAN)
6581 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6582 else
6583 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6584 }
6585 }
6586 [(set_attr "type" "two,three")
6587 (set_attr "length" "8,12")])
6589 (define_insn "*ashrdisi3_noppc64be"
6590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6591 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6592 (const_int 32)) 4))]
6593 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6594 "*
6595 {
6596 if (REGNO (operands[0]) == REGNO (operands[1]))
6597 return \"\";
6598 else
6599 return \"mr %0,%1\";
6600 }"
6601 [(set_attr "length" "4")])
6603 \f
6604 ;; PowerPC64 DImode operations.
6606 (define_insn "*rotldi3_internal4"
6607 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6608 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6609 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6610 (match_operand:DI 3 "mask64_operand" "n")))]
6611 "TARGET_POWERPC64"
6612 "rld%I2c%B3 %0,%1,%H2,%S3"
6613 [(set_attr "type" "shift")
6614 (set_attr "maybe_var_shift" "yes")])
6616 (define_insn "*rotldi3_internal5"
6617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6618 (compare:CC (and:DI
6619 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6620 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6621 (match_operand:DI 3 "mask64_operand" "n,n"))
6622 (const_int 0)))
6623 (clobber (match_scratch:DI 4 "=r,r"))]
6624 "TARGET_64BIT"
6625 "@
6626 rld%I2c%B3. %4,%1,%H2,%S3
6627 #"
6628 [(set_attr "type" "shift")
6629 (set_attr "maybe_var_shift" "yes")
6630 (set_attr "dot" "yes")
6631 (set_attr "length" "4,8")])
6633 (define_split
6634 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6635 (compare:CC (and:DI
6636 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6637 (match_operand:DI 2 "reg_or_cint_operand" ""))
6638 (match_operand:DI 3 "mask64_operand" ""))
6639 (const_int 0)))
6640 (clobber (match_scratch:DI 4 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6642 [(set (match_dup 4)
6643 (and:DI (rotate:DI (match_dup 1)
6644 (match_dup 2))
6645 (match_dup 3)))
6646 (set (match_dup 0)
6647 (compare:CC (match_dup 4)
6648 (const_int 0)))]
6649 "")
6651 (define_insn "*rotldi3_internal6"
6652 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6653 (compare:CC (and:DI
6654 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6655 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6656 (match_operand:DI 3 "mask64_operand" "n,n"))
6657 (const_int 0)))
6658 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6659 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6660 "TARGET_64BIT"
6661 "@
6662 rld%I2c%B3. %0,%1,%H2,%S3
6663 #"
6664 [(set_attr "type" "shift")
6665 (set_attr "maybe_var_shift" "yes")
6666 (set_attr "dot" "yes")
6667 (set_attr "length" "4,8")])
6669 (define_split
6670 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6671 (compare:CC (and:DI
6672 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6673 (match_operand:DI 2 "reg_or_cint_operand" ""))
6674 (match_operand:DI 3 "mask64_operand" ""))
6675 (const_int 0)))
6676 (set (match_operand:DI 0 "gpc_reg_operand" "")
6677 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6678 "TARGET_POWERPC64 && reload_completed"
6679 [(set (match_dup 0)
6680 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6681 (set (match_dup 4)
6682 (compare:CC (match_dup 0)
6683 (const_int 0)))]
6684 "")
6686 (define_insn "*rotldi3_internal7le"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6688 (zero_extend:DI
6689 (subreg:QI
6690 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6691 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6692 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6693 "rld%I2cl %0,%1,%H2,56"
6694 [(set_attr "type" "shift")
6695 (set_attr "maybe_var_shift" "yes")])
6697 (define_insn "*rotldi3_internal7be"
6698 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6699 (zero_extend:DI
6700 (subreg:QI
6701 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6702 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6703 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6704 "rld%I2cl %0,%1,%H2,56"
6705 [(set_attr "type" "shift")
6706 (set_attr "maybe_var_shift" "yes")])
6708 (define_insn "*rotldi3_internal8le"
6709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6710 (compare:CC (zero_extend:DI
6711 (subreg:QI
6712 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6713 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6714 (const_int 0)))
6715 (clobber (match_scratch:DI 3 "=r,r"))]
6716 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6717 "@
6718 rld%I2cl. %3,%1,%H2,56
6719 #"
6720 [(set_attr "type" "shift")
6721 (set_attr "maybe_var_shift" "yes")
6722 (set_attr "dot" "yes")
6723 (set_attr "length" "4,8")])
6725 (define_insn "*rotldi3_internal8be"
6726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6727 (compare:CC (zero_extend:DI
6728 (subreg:QI
6729 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6730 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6731 (const_int 0)))
6732 (clobber (match_scratch:DI 3 "=r,r"))]
6733 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6734 "@
6735 rld%I2cl. %3,%1,%H2,56
6736 #"
6737 [(set_attr "type" "shift")
6738 (set_attr "maybe_var_shift" "yes")
6739 (set_attr "dot" "yes")
6740 (set_attr "length" "4,8")])
6742 (define_split
6743 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6744 (compare:CC (zero_extend:DI
6745 (subreg:QI
6746 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6747 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6748 (const_int 0)))
6749 (clobber (match_scratch:DI 3 ""))]
6750 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6751 [(set (match_dup 3)
6752 (zero_extend:DI (subreg:QI
6753 (rotate:DI (match_dup 1)
6754 (match_dup 2)) 0)))
6755 (set (match_dup 0)
6756 (compare:CC (match_dup 3)
6757 (const_int 0)))]
6758 "")
6760 (define_split
6761 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6762 (compare:CC (zero_extend:DI
6763 (subreg:QI
6764 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6765 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6766 (const_int 0)))
6767 (clobber (match_scratch:DI 3 ""))]
6768 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6769 [(set (match_dup 3)
6770 (zero_extend:DI (subreg:QI
6771 (rotate:DI (match_dup 1)
6772 (match_dup 2)) 7)))
6773 (set (match_dup 0)
6774 (compare:CC (match_dup 3)
6775 (const_int 0)))]
6776 "")
6778 (define_insn "*rotldi3_internal9le"
6779 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6780 (compare:CC (zero_extend:DI
6781 (subreg:QI
6782 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6783 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6784 (const_int 0)))
6785 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6786 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6787 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6788 "@
6789 rld%I2cl. %0,%1,%H2,56
6790 #"
6791 [(set_attr "type" "shift")
6792 (set_attr "maybe_var_shift" "yes")
6793 (set_attr "dot" "yes")
6794 (set_attr "length" "4,8")])
6796 (define_insn "*rotldi3_internal9be"
6797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6798 (compare:CC (zero_extend:DI
6799 (subreg:QI
6800 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6801 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6802 (const_int 0)))
6803 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6804 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6805 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6806 "@
6807 rld%I2cl. %0,%1,%H2,56
6808 #"
6809 [(set_attr "type" "shift")
6810 (set_attr "maybe_var_shift" "yes")
6811 (set_attr "dot" "yes")
6812 (set_attr "length" "4,8")])
6814 (define_split
6815 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6816 (compare:CC (zero_extend:DI
6817 (subreg:QI
6818 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6819 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6820 (const_int 0)))
6821 (set (match_operand:DI 0 "gpc_reg_operand" "")
6822 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6823 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6824 [(set (match_dup 0)
6825 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6826 (set (match_dup 3)
6827 (compare:CC (match_dup 0)
6828 (const_int 0)))]
6829 "")
6831 (define_split
6832 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6833 (compare:CC (zero_extend:DI
6834 (subreg:QI
6835 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6836 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6837 (const_int 0)))
6838 (set (match_operand:DI 0 "gpc_reg_operand" "")
6839 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6840 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6841 [(set (match_dup 0)
6842 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6843 (set (match_dup 3)
6844 (compare:CC (match_dup 0)
6845 (const_int 0)))]
6846 "")
6848 (define_insn "*rotldi3_internal10le"
6849 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6850 (zero_extend:DI
6851 (subreg:HI
6852 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6853 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6854 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6855 "rld%I2cl %0,%1,%H2,48"
6856 [(set_attr "type" "shift")
6857 (set_attr "maybe_var_shift" "yes")])
6859 (define_insn "*rotldi3_internal10be"
6860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6861 (zero_extend:DI
6862 (subreg:HI
6863 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6864 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6865 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6866 "rld%I2cl %0,%1,%H2,48"
6867 [(set_attr "type" "shift")
6868 (set_attr "maybe_var_shift" "yes")])
6870 (define_insn "*rotldi3_internal11le"
6871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6872 (compare:CC (zero_extend:DI
6873 (subreg:HI
6874 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6876 (const_int 0)))
6877 (clobber (match_scratch:DI 3 "=r,r"))]
6878 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6879 "@
6880 rld%I2cl. %3,%1,%H2,48
6881 #"
6882 [(set_attr "type" "shift")
6883 (set_attr "maybe_var_shift" "yes")
6884 (set_attr "dot" "yes")
6885 (set_attr "length" "4,8")])
6887 (define_insn "*rotldi3_internal11be"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6889 (compare:CC (zero_extend:DI
6890 (subreg:HI
6891 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6892 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 3 "=r,r"))]
6895 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6896 "@
6897 rld%I2cl. %3,%1,%H2,48
6898 #"
6899 [(set_attr "type" "shift")
6900 (set_attr "maybe_var_shift" "yes")
6901 (set_attr "dot" "yes")
6902 (set_attr "length" "4,8")])
6904 (define_split
6905 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6906 (compare:CC (zero_extend:DI
6907 (subreg:HI
6908 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6910 (const_int 0)))
6911 (clobber (match_scratch:DI 3 ""))]
6912 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6913 [(set (match_dup 3)
6914 (zero_extend:DI (subreg:HI
6915 (rotate:DI (match_dup 1)
6916 (match_dup 2)) 0)))
6917 (set (match_dup 0)
6918 (compare:CC (match_dup 3)
6919 (const_int 0)))]
6920 "")
6922 (define_split
6923 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6924 (compare:CC (zero_extend:DI
6925 (subreg:HI
6926 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6927 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6928 (const_int 0)))
6929 (clobber (match_scratch:DI 3 ""))]
6930 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6931 [(set (match_dup 3)
6932 (zero_extend:DI (subreg:HI
6933 (rotate:DI (match_dup 1)
6934 (match_dup 2)) 6)))
6935 (set (match_dup 0)
6936 (compare:CC (match_dup 3)
6937 (const_int 0)))]
6938 "")
6940 (define_insn "*rotldi3_internal12le"
6941 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6942 (compare:CC (zero_extend:DI
6943 (subreg:HI
6944 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6945 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6946 (const_int 0)))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6948 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6949 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6950 "@
6951 rld%I2cl. %0,%1,%H2,48
6952 #"
6953 [(set_attr "type" "shift")
6954 (set_attr "maybe_var_shift" "yes")
6955 (set_attr "dot" "yes")
6956 (set_attr "length" "4,8")])
6958 (define_insn "*rotldi3_internal12be"
6959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6960 (compare:CC (zero_extend:DI
6961 (subreg:HI
6962 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6963 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6964 (const_int 0)))
6965 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6966 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6967 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6968 "@
6969 rld%I2cl. %0,%1,%H2,48
6970 #"
6971 [(set_attr "type" "shift")
6972 (set_attr "maybe_var_shift" "yes")
6973 (set_attr "dot" "yes")
6974 (set_attr "length" "4,8")])
6976 (define_split
6977 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6978 (compare:CC (zero_extend:DI
6979 (subreg:HI
6980 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6981 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6982 (const_int 0)))
6983 (set (match_operand:DI 0 "gpc_reg_operand" "")
6984 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6985 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6986 [(set (match_dup 0)
6987 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6988 (set (match_dup 3)
6989 (compare:CC (match_dup 0)
6990 (const_int 0)))]
6991 "")
6993 (define_split
6994 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6995 (compare:CC (zero_extend:DI
6996 (subreg:HI
6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6999 (const_int 0)))
7000 (set (match_operand:DI 0 "gpc_reg_operand" "")
7001 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7002 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7003 [(set (match_dup 0)
7004 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7005 (set (match_dup 3)
7006 (compare:CC (match_dup 0)
7007 (const_int 0)))]
7008 "")
7010 (define_insn "*rotldi3_internal13le"
7011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7012 (zero_extend:DI
7013 (subreg:SI
7014 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7015 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7016 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7017 "rld%I2cl %0,%1,%H2,32"
7018 [(set_attr "type" "shift")
7019 (set_attr "maybe_var_shift" "yes")])
7021 (define_insn "*rotldi3_internal13be"
7022 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7023 (zero_extend:DI
7024 (subreg:SI
7025 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7026 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
7027 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7028 "rld%I2cl %0,%1,%H2,32"
7029 [(set_attr "type" "shift")
7030 (set_attr "maybe_var_shift" "yes")])
7032 (define_insn "*rotldi3_internal14le"
7033 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7034 (compare:CC (zero_extend:DI
7035 (subreg:SI
7036 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7037 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7038 (const_int 0)))
7039 (clobber (match_scratch:DI 3 "=r,r"))]
7040 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7041 "@
7042 rld%I2cl. %3,%1,%H2,32
7043 #"
7044 [(set_attr "type" "shift")
7045 (set_attr "maybe_var_shift" "yes")
7046 (set_attr "dot" "yes")
7047 (set_attr "length" "4,8")])
7049 (define_insn "*rotldi3_internal14be"
7050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7051 (compare:CC (zero_extend:DI
7052 (subreg:SI
7053 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7054 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7055 (const_int 0)))
7056 (clobber (match_scratch:DI 3 "=r,r"))]
7057 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7058 "@
7059 rld%I2cl. %3,%1,%H2,32
7060 #"
7061 [(set_attr "type" "shift")
7062 (set_attr "maybe_var_shift" "yes")
7063 (set_attr "dot" "yes")
7064 (set_attr "length" "4,8")])
7066 (define_split
7067 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7068 (compare:CC (zero_extend:DI
7069 (subreg:SI
7070 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7071 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7072 (const_int 0)))
7073 (clobber (match_scratch:DI 3 ""))]
7074 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7075 [(set (match_dup 3)
7076 (zero_extend:DI (subreg:SI
7077 (rotate:DI (match_dup 1)
7078 (match_dup 2)) 0)))
7079 (set (match_dup 0)
7080 (compare:CC (match_dup 3)
7081 (const_int 0)))]
7082 "")
7084 (define_split
7085 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7086 (compare:CC (zero_extend:DI
7087 (subreg:SI
7088 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7089 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7090 (const_int 0)))
7091 (clobber (match_scratch:DI 3 ""))]
7092 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7093 [(set (match_dup 3)
7094 (zero_extend:DI (subreg:SI
7095 (rotate:DI (match_dup 1)
7096 (match_dup 2)) 4)))
7097 (set (match_dup 0)
7098 (compare:CC (match_dup 3)
7099 (const_int 0)))]
7100 "")
7102 (define_insn "*rotldi3_internal15le"
7103 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7104 (compare:CC (zero_extend:DI
7105 (subreg:SI
7106 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7107 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7108 (const_int 0)))
7109 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7110 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7111 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7112 "@
7113 rld%I2cl. %0,%1,%H2,32
7114 #"
7115 [(set_attr "type" "shift")
7116 (set_attr "maybe_var_shift" "yes")
7117 (set_attr "dot" "yes")
7118 (set_attr "length" "4,8")])
7120 (define_insn "*rotldi3_internal15be"
7121 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7122 (compare:CC (zero_extend:DI
7123 (subreg:SI
7124 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7125 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7126 (const_int 0)))
7127 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7128 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7129 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7130 "@
7131 rld%I2cl. %0,%1,%H2,32
7132 #"
7133 [(set_attr "type" "shift")
7134 (set_attr "maybe_var_shift" "yes")
7135 (set_attr "dot" "yes")
7136 (set_attr "length" "4,8")])
7138 (define_split
7139 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7140 (compare:CC (zero_extend:DI
7141 (subreg:SI
7142 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7143 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7144 (const_int 0)))
7145 (set (match_operand:DI 0 "gpc_reg_operand" "")
7146 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7147 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7148 [(set (match_dup 0)
7149 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7150 (set (match_dup 3)
7151 (compare:CC (match_dup 0)
7152 (const_int 0)))]
7153 "")
7155 (define_split
7156 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7157 (compare:CC (zero_extend:DI
7158 (subreg:SI
7159 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "")
7163 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7164 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7165 [(set (match_dup 0)
7166 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7167 (set (match_dup 3)
7168 (compare:CC (match_dup 0)
7169 (const_int 0)))]
7170 "")
7172 (define_insn "*ashldi3_internal4"
7173 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7174 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7175 (match_operand:SI 2 "const_int_operand" "i"))
7176 (match_operand:DI 3 "const_int_operand" "n")))]
7177 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7178 "rldic %0,%1,%H2,%W3"
7179 [(set_attr "type" "shift")])
7181 (define_insn "ashldi3_internal5"
7182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7183 (compare:CC
7184 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7185 (match_operand:SI 2 "const_int_operand" "i,i"))
7186 (match_operand:DI 3 "const_int_operand" "n,n"))
7187 (const_int 0)))
7188 (clobber (match_scratch:DI 4 "=r,r"))]
7189 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7190 "@
7191 rldic. %4,%1,%H2,%W3
7192 #"
7193 [(set_attr "type" "shift")
7194 (set_attr "dot" "yes")
7195 (set_attr "length" "4,8")])
7197 (define_split
7198 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7199 (compare:CC
7200 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7201 (match_operand:SI 2 "const_int_operand" ""))
7202 (match_operand:DI 3 "const_int_operand" ""))
7203 (const_int 0)))
7204 (clobber (match_scratch:DI 4 ""))]
7205 "TARGET_POWERPC64 && reload_completed
7206 && includes_rldic_lshift_p (operands[2], operands[3])"
7207 [(set (match_dup 4)
7208 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7209 (match_dup 3)))
7210 (set (match_dup 0)
7211 (compare:CC (match_dup 4)
7212 (const_int 0)))]
7213 "")
7215 (define_insn "*ashldi3_internal6"
7216 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7217 (compare:CC
7218 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7219 (match_operand:SI 2 "const_int_operand" "i,i"))
7220 (match_operand:DI 3 "const_int_operand" "n,n"))
7221 (const_int 0)))
7222 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7223 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7224 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7225 "@
7226 rldic. %0,%1,%H2,%W3
7227 #"
7228 [(set_attr "type" "shift")
7229 (set_attr "dot" "yes")
7230 (set_attr "length" "4,8")])
7232 (define_split
7233 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7234 (compare:CC
7235 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7236 (match_operand:SI 2 "const_int_operand" ""))
7237 (match_operand:DI 3 "const_int_operand" ""))
7238 (const_int 0)))
7239 (set (match_operand:DI 0 "gpc_reg_operand" "")
7240 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7241 "TARGET_POWERPC64 && reload_completed
7242 && includes_rldic_lshift_p (operands[2], operands[3])"
7243 [(set (match_dup 0)
7244 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7245 (match_dup 3)))
7246 (set (match_dup 4)
7247 (compare:CC (match_dup 0)
7248 (const_int 0)))]
7249 "")
7251 (define_insn "*ashldi3_internal7"
7252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7253 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7254 (match_operand:SI 2 "const_int_operand" "i"))
7255 (match_operand:DI 3 "mask64_operand" "n")))]
7256 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7257 "rldicr %0,%1,%H2,%S3"
7258 [(set_attr "type" "shift")])
7260 (define_insn "ashldi3_internal8"
7261 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7262 (compare:CC
7263 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7264 (match_operand:SI 2 "const_int_operand" "i,i"))
7265 (match_operand:DI 3 "mask64_operand" "n,n"))
7266 (const_int 0)))
7267 (clobber (match_scratch:DI 4 "=r,r"))]
7268 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7269 "@
7270 rldicr. %4,%1,%H2,%S3
7271 #"
7272 [(set_attr "type" "shift")
7273 (set_attr "dot" "yes")
7274 (set_attr "length" "4,8")])
7276 (define_split
7277 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7278 (compare:CC
7279 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7280 (match_operand:SI 2 "const_int_operand" ""))
7281 (match_operand:DI 3 "mask64_operand" ""))
7282 (const_int 0)))
7283 (clobber (match_scratch:DI 4 ""))]
7284 "TARGET_POWERPC64 && reload_completed
7285 && includes_rldicr_lshift_p (operands[2], operands[3])"
7286 [(set (match_dup 4)
7287 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7288 (match_dup 3)))
7289 (set (match_dup 0)
7290 (compare:CC (match_dup 4)
7291 (const_int 0)))]
7292 "")
7294 (define_insn "*ashldi3_internal9"
7295 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7296 (compare:CC
7297 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7298 (match_operand:SI 2 "const_int_operand" "i,i"))
7299 (match_operand:DI 3 "mask64_operand" "n,n"))
7300 (const_int 0)))
7301 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7302 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7303 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7304 "@
7305 rldicr. %0,%1,%H2,%S3
7306 #"
7307 [(set_attr "type" "shift")
7308 (set_attr "dot" "yes")
7309 (set_attr "length" "4,8")])
7311 (define_split
7312 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7313 (compare:CC
7314 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7315 (match_operand:SI 2 "const_int_operand" ""))
7316 (match_operand:DI 3 "mask64_operand" ""))
7317 (const_int 0)))
7318 (set (match_operand:DI 0 "gpc_reg_operand" "")
7319 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7320 "TARGET_POWERPC64 && reload_completed
7321 && includes_rldicr_lshift_p (operands[2], operands[3])"
7322 [(set (match_dup 0)
7323 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7324 (match_dup 3)))
7325 (set (match_dup 4)
7326 (compare:CC (match_dup 0)
7327 (const_int 0)))]
7328 "")
7331 (define_insn_and_split "*anddi3_2rld"
7332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7333 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7334 (match_operand:DI 2 "and_2rld_operand" "n")))]
7335 "TARGET_POWERPC64"
7336 "#"
7337 ""
7338 [(set (match_dup 0)
7339 (and:DI (rotate:DI (match_dup 1)
7340 (match_dup 4))
7341 (match_dup 5)))
7342 (set (match_dup 0)
7343 (and:DI (rotate:DI (match_dup 0)
7344 (match_dup 6))
7345 (match_dup 7)))]
7346 {
7347 build_mask64_2_operands (operands[2], &operands[4]);
7348 }
7349 [(set_attr "length" "8")])
7351 (define_insn_and_split "*anddi3_2rld_dot"
7352 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7353 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7354 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7355 (const_int 0)))
7356 (clobber (match_scratch:DI 0 "=r,r"))]
7357 "TARGET_64BIT && rs6000_gen_cell_microcode"
7358 "@
7359 #
7360 #"
7361 "&& reload_completed"
7362 [(set (match_dup 0)
7363 (and:DI (rotate:DI (match_dup 1)
7364 (match_dup 4))
7365 (match_dup 5)))
7366 (parallel [(set (match_dup 3)
7367 (compare:CC (and:DI (rotate:DI (match_dup 0)
7368 (match_dup 6))
7369 (match_dup 7))
7370 (const_int 0)))
7371 (clobber (match_dup 0))])]
7372 {
7373 build_mask64_2_operands (operands[2], &operands[4]);
7374 }
7375 [(set_attr "type" "two")
7376 (set_attr "dot" "yes")
7377 (set_attr "length" "8,12")])
7379 (define_insn_and_split "*anddi3_2rld_dot2"
7380 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7381 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7382 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7383 (const_int 0)))
7384 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7385 (and:DI (match_dup 1)
7386 (match_dup 2)))]
7387 "TARGET_64BIT && rs6000_gen_cell_microcode"
7388 "@
7389 #
7390 #"
7391 "&& reload_completed"
7392 [(set (match_dup 0)
7393 (and:DI (rotate:DI (match_dup 1)
7394 (match_dup 4))
7395 (match_dup 5)))
7396 (parallel [(set (match_dup 3)
7397 (compare:CC (and:DI (rotate:DI (match_dup 0)
7398 (match_dup 6))
7399 (match_dup 7))
7400 (const_int 0)))
7401 (set (match_dup 0)
7402 (and:DI (rotate:DI (match_dup 0)
7403 (match_dup 6))
7404 (match_dup 7)))])]
7405 {
7406 build_mask64_2_operands (operands[2], &operands[4]);
7407 }
7408 [(set_attr "type" "two")
7409 (set_attr "dot" "yes")
7410 (set_attr "length" "8,12")])
7411 \f
7412 ;; 128-bit logical operations expanders
7414 (define_expand "and<mode>3"
7415 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7416 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7417 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7418 ""
7419 "")
7421 (define_expand "ior<mode>3"
7422 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7423 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7424 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7425 ""
7426 "")
7428 (define_expand "xor<mode>3"
7429 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7430 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7431 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7432 ""
7433 "")
7435 (define_expand "one_cmpl<mode>2"
7436 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7437 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7438 ""
7439 "")
7441 (define_expand "nor<mode>3"
7442 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7443 (and:BOOL_128
7444 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7445 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7446 ""
7447 "")
7449 (define_expand "andc<mode>3"
7450 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7451 (and:BOOL_128
7452 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7453 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7454 ""
7455 "")
7457 ;; Power8 vector logical instructions.
7458 (define_expand "eqv<mode>3"
7459 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7460 (not:BOOL_128
7461 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7462 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7463 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7464 "")
7466 ;; Rewrite nand into canonical form
7467 (define_expand "nand<mode>3"
7468 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7469 (ior:BOOL_128
7470 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7471 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7472 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7473 "")
7475 ;; The canonical form is to have the negated element first, so we need to
7476 ;; reverse arguments.
7477 (define_expand "orc<mode>3"
7478 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7479 (ior:BOOL_128
7480 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7481 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7482 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7483 "")
7485 ;; 128-bit logical operations insns and split operations
7486 (define_insn_and_split "*and<mode>3_internal"
7487 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7488 (and:BOOL_128
7489 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7490 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7491 ""
7492 {
7493 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7494 return "xxland %x0,%x1,%x2";
7496 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7497 return "vand %0,%1,%2";
7499 return "#";
7500 }
7501 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7502 [(const_int 0)]
7503 {
7504 rs6000_split_logical (operands, AND, false, false, false);
7505 DONE;
7506 }
7507 [(set (attr "type")
7508 (if_then_else
7509 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7510 (const_string "vecsimple")
7511 (const_string "integer")))
7512 (set (attr "length")
7513 (if_then_else
7514 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7515 (const_string "4")
7516 (if_then_else
7517 (match_test "TARGET_POWERPC64")
7518 (const_string "8")
7519 (const_string "16"))))])
7521 ;; 128-bit IOR/XOR
7522 (define_insn_and_split "*bool<mode>3_internal"
7523 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7524 (match_operator:BOOL_128 3 "boolean_or_operator"
7525 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7526 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7527 ""
7528 {
7529 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7530 return "xxl%q3 %x0,%x1,%x2";
7532 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7533 return "v%q3 %0,%1,%2";
7535 return "#";
7536 }
7537 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7538 [(const_int 0)]
7539 {
7540 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7541 DONE;
7542 }
7543 [(set (attr "type")
7544 (if_then_else
7545 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7546 (const_string "vecsimple")
7547 (const_string "integer")))
7548 (set (attr "length")
7549 (if_then_else
7550 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7551 (const_string "4")
7552 (if_then_else
7553 (match_test "TARGET_POWERPC64")
7554 (const_string "8")
7555 (const_string "16"))))])
7557 ;; 128-bit ANDC/ORC
7558 (define_insn_and_split "*boolc<mode>3_internal1"
7559 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7560 (match_operator:BOOL_128 3 "boolean_operator"
7561 [(not:BOOL_128
7562 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
7563 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
7564 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7565 {
7566 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7567 return "xxl%q3 %x0,%x1,%x2";
7569 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7570 return "v%q3 %0,%1,%2";
7572 return "#";
7573 }
7574 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7575 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7576 [(const_int 0)]
7577 {
7578 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
7579 DONE;
7580 }
7581 [(set (attr "type")
7582 (if_then_else
7583 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7584 (const_string "vecsimple")
7585 (const_string "integer")))
7586 (set (attr "length")
7587 (if_then_else
7588 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7589 (const_string "4")
7590 (if_then_else
7591 (match_test "TARGET_POWERPC64")
7592 (const_string "8")
7593 (const_string "16"))))])
7595 (define_insn_and_split "*boolc<mode>3_internal2"
7596 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7597 (match_operator:TI2 3 "boolean_operator"
7598 [(not:TI2
7599 (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
7600 (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
7601 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7602 "#"
7603 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7604 [(const_int 0)]
7605 {
7606 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
7607 DONE;
7608 }
7609 [(set_attr "type" "integer")
7610 (set (attr "length")
7611 (if_then_else
7612 (match_test "TARGET_POWERPC64")
7613 (const_string "8")
7614 (const_string "16")))])
7616 ;; 128-bit NAND/NOR
7617 (define_insn_and_split "*boolcc<mode>3_internal1"
7618 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7619 (match_operator:BOOL_128 3 "boolean_operator"
7620 [(not:BOOL_128
7621 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7622 (not:BOOL_128
7623 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7624 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7625 {
7626 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7627 return "xxl%q3 %x0,%x1,%x2";
7629 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7630 return "v%q3 %0,%1,%2";
7632 return "#";
7633 }
7634 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7635 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7636 [(const_int 0)]
7637 {
7638 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7639 DONE;
7640 }
7641 [(set (attr "type")
7642 (if_then_else
7643 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7644 (const_string "vecsimple")
7645 (const_string "integer")))
7646 (set (attr "length")
7647 (if_then_else
7648 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7649 (const_string "4")
7650 (if_then_else
7651 (match_test "TARGET_POWERPC64")
7652 (const_string "8")
7653 (const_string "16"))))])
7655 (define_insn_and_split "*boolcc<mode>3_internal2"
7656 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7657 (match_operator:TI2 3 "boolean_operator"
7658 [(not:TI2
7659 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7660 (not:TI2
7661 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7662 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7663 "#"
7664 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7665 [(const_int 0)]
7666 {
7667 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7668 DONE;
7669 }
7670 [(set_attr "type" "integer")
7671 (set (attr "length")
7672 (if_then_else
7673 (match_test "TARGET_POWERPC64")
7674 (const_string "8")
7675 (const_string "16")))])
7678 ;; 128-bit EQV
7679 (define_insn_and_split "*eqv<mode>3_internal1"
7680 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7681 (not:BOOL_128
7682 (xor:BOOL_128
7683 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7684 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7685 "TARGET_P8_VECTOR"
7686 {
7687 if (vsx_register_operand (operands[0], <MODE>mode))
7688 return "xxleqv %x0,%x1,%x2";
7690 return "#";
7691 }
7692 "TARGET_P8_VECTOR && reload_completed
7693 && int_reg_operand (operands[0], <MODE>mode)"
7694 [(const_int 0)]
7695 {
7696 rs6000_split_logical (operands, XOR, true, false, false);
7697 DONE;
7698 }
7699 [(set (attr "type")
7700 (if_then_else
7701 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7702 (const_string "vecsimple")
7703 (const_string "integer")))
7704 (set (attr "length")
7705 (if_then_else
7706 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7707 (const_string "4")
7708 (if_then_else
7709 (match_test "TARGET_POWERPC64")
7710 (const_string "8")
7711 (const_string "16"))))])
7713 (define_insn_and_split "*eqv<mode>3_internal2"
7714 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7715 (not:TI2
7716 (xor:TI2
7717 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7718 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7719 "!TARGET_P8_VECTOR"
7720 "#"
7721 "reload_completed && !TARGET_P8_VECTOR"
7722 [(const_int 0)]
7723 {
7724 rs6000_split_logical (operands, XOR, true, false, false);
7725 DONE;
7726 }
7727 [(set_attr "type" "integer")
7728 (set (attr "length")
7729 (if_then_else
7730 (match_test "TARGET_POWERPC64")
7731 (const_string "8")
7732 (const_string "16")))])
7734 ;; 128-bit one's complement
7735 (define_insn_and_split "*one_cmpl<mode>3_internal"
7736 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7737 (not:BOOL_128
7738 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7739 ""
7740 {
7741 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7742 return "xxlnor %x0,%x1,%x1";
7744 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7745 return "vnor %0,%1,%1";
7747 return "#";
7748 }
7749 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7750 [(const_int 0)]
7751 {
7752 rs6000_split_logical (operands, NOT, false, false, false);
7753 DONE;
7754 }
7755 [(set (attr "type")
7756 (if_then_else
7757 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7758 (const_string "vecsimple")
7759 (const_string "integer")))
7760 (set (attr "length")
7761 (if_then_else
7762 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7763 (const_string "4")
7764 (if_then_else
7765 (match_test "TARGET_POWERPC64")
7766 (const_string "8")
7767 (const_string "16"))))])
7769 \f
7770 ;; Now define ways of moving data around.
7772 ;; Set up a register with a value from the GOT table
7774 (define_expand "movsi_got"
7775 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7776 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7777 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7778 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7779 "
7780 {
7781 if (GET_CODE (operands[1]) == CONST)
7782 {
7783 rtx offset = const0_rtx;
7784 HOST_WIDE_INT value;
7786 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7787 value = INTVAL (offset);
7788 if (value != 0)
7789 {
7790 rtx tmp = (!can_create_pseudo_p ()
7791 ? operands[0]
7792 : gen_reg_rtx (Pmode));
7793 emit_insn (gen_movsi_got (tmp, operands[1]));
7794 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7795 DONE;
7796 }
7797 }
7799 operands[2] = rs6000_got_register (operands[1]);
7800 }")
7802 (define_insn "*movsi_got_internal"
7803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7804 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7805 (match_operand:SI 2 "gpc_reg_operand" "b")]
7806 UNSPEC_MOVSI_GOT))]
7807 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7808 "lwz %0,%a1@got(%2)"
7809 [(set_attr "type" "load")])
7811 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7812 ;; didn't get allocated to a hard register.
7813 (define_split
7814 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7815 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7816 (match_operand:SI 2 "memory_operand" "")]
7817 UNSPEC_MOVSI_GOT))]
7818 "DEFAULT_ABI == ABI_V4
7819 && flag_pic == 1
7820 && (reload_in_progress || reload_completed)"
7821 [(set (match_dup 0) (match_dup 2))
7822 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7823 UNSPEC_MOVSI_GOT))]
7824 "")
7826 ;; For SI, we special-case integers that can't be loaded in one insn. We
7827 ;; do the load 16-bits at a time. We could do this by loading from memory,
7828 ;; and this is even supposed to be faster, but it is simpler not to get
7829 ;; integers in the TOC.
7830 (define_insn "movsi_low"
7831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7832 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7833 (match_operand 2 "" ""))))]
7834 "TARGET_MACHO && ! TARGET_64BIT"
7835 "lwz %0,lo16(%2)(%1)"
7836 [(set_attr "type" "load")
7837 (set_attr "length" "4")])
7839 (define_insn "*movsi_internal1"
7840 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7841 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7842 "!TARGET_SINGLE_FPU &&
7843 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7844 "@
7845 mr %0,%1
7846 la %0,%a1
7847 lwz%U1%X1 %0,%1
7848 stw%U0%X0 %1,%0
7849 li %0,%1
7850 lis %0,%v1
7851 #
7852 mf%1 %0
7853 mt%0 %1
7854 mt%0 %1
7855 nop"
7856 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7857 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7859 (define_insn "*movsi_internal1_single"
7860 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7861 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7862 "TARGET_SINGLE_FPU &&
7863 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7864 "@
7865 mr %0,%1
7866 la %0,%a1
7867 lwz%U1%X1 %0,%1
7868 stw%U0%X0 %1,%0
7869 li %0,%1
7870 lis %0,%v1
7871 #
7872 mf%1 %0
7873 mt%0 %1
7874 mt%0 %1
7875 nop
7876 stfs%U0%X0 %1,%0
7877 lfs%U1%X1 %0,%1"
7878 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7879 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7881 ;; Split a load of a large constant into the appropriate two-insn
7882 ;; sequence.
7884 (define_split
7885 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7886 (match_operand:SI 1 "const_int_operand" ""))]
7887 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7888 && (INTVAL (operands[1]) & 0xffff) != 0"
7889 [(set (match_dup 0)
7890 (match_dup 2))
7891 (set (match_dup 0)
7892 (ior:SI (match_dup 0)
7893 (match_dup 3)))]
7894 "
7895 {
7896 if (rs6000_emit_set_const (operands[0], operands[1]))
7897 DONE;
7898 else
7899 FAIL;
7900 }")
7902 (define_insn "*mov<mode>_internal2"
7903 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7904 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7905 (const_int 0)))
7906 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7907 ""
7908 "@
7909 cmp<wd>i %2,%0,0
7910 mr. %0,%1
7911 #"
7912 [(set_attr "type" "cmp,logical,cmp")
7913 (set_attr "dot" "yes")
7914 (set_attr "length" "4,4,8")])
7916 (define_split
7917 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7918 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7919 (const_int 0)))
7920 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7921 "reload_completed"
7922 [(set (match_dup 0) (match_dup 1))
7923 (set (match_dup 2)
7924 (compare:CC (match_dup 0)
7925 (const_int 0)))]
7926 "")
7927 \f
7928 (define_insn "*movhi_internal"
7929 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7930 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7931 "gpc_reg_operand (operands[0], HImode)
7932 || gpc_reg_operand (operands[1], HImode)"
7933 "@
7934 mr %0,%1
7935 lhz%U1%X1 %0,%1
7936 sth%U0%X0 %1,%0
7937 li %0,%w1
7938 mf%1 %0
7939 mt%0 %1
7940 nop"
7941 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7943 (define_expand "mov<mode>"
7944 [(set (match_operand:INT 0 "general_operand" "")
7945 (match_operand:INT 1 "any_operand" ""))]
7946 ""
7947 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7949 (define_insn "*movqi_internal"
7950 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7951 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7952 "gpc_reg_operand (operands[0], QImode)
7953 || gpc_reg_operand (operands[1], QImode)"
7954 "@
7955 mr %0,%1
7956 lbz%U1%X1 %0,%1
7957 stb%U0%X0 %1,%0
7958 li %0,%1
7959 mf%1 %0
7960 mt%0 %1
7961 nop"
7962 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7963 \f
7964 ;; Here is how to move condition codes around. When we store CC data in
7965 ;; an integer register or memory, we store just the high-order 4 bits.
7966 ;; This lets us not shift in the most common case of CR0.
7967 (define_expand "movcc"
7968 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7969 (match_operand:CC 1 "nonimmediate_operand" ""))]
7970 ""
7971 "")
7973 (define_insn "*movcc_internal1"
7974 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7975 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7976 "register_operand (operands[0], CCmode)
7977 || register_operand (operands[1], CCmode)"
7978 "@
7979 mcrf %0,%1
7980 mtcrf 128,%1
7981 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7982 crxor %0,%0,%0
7983 mfcr %0%Q1
7984 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7985 mr %0,%1
7986 li %0,%1
7987 mf%1 %0
7988 mt%0 %1
7989 lwz%U1%X1 %0,%1
7990 stw%U0%X0 %1,%0"
7991 [(set (attr "type")
7992 (cond [(eq_attr "alternative" "0,3")
7993 (const_string "cr_logical")
7994 (eq_attr "alternative" "1,2")
7995 (const_string "mtcr")
7996 (eq_attr "alternative" "6,7")
7997 (const_string "integer")
7998 (eq_attr "alternative" "8")
7999 (const_string "mfjmpr")
8000 (eq_attr "alternative" "9")
8001 (const_string "mtjmpr")
8002 (eq_attr "alternative" "10")
8003 (const_string "load")
8004 (eq_attr "alternative" "11")
8005 (const_string "store")
8006 (match_test "TARGET_MFCRF")
8007 (const_string "mfcrf")
8008 ]
8009 (const_string "mfcr")))
8010 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8011 \f
8012 ;; For floating-point, we normally deal with the floating-point registers
8013 ;; unless -msoft-float is used. The sole exception is that parameter passing
8014 ;; can produce floating-point values in fixed-point registers. Unless the
8015 ;; value is a simple constant or already in memory, we deal with this by
8016 ;; allocating memory and copying the value explicitly via that memory location.
8018 ;; Move 32-bit binary/decimal floating point
8019 (define_expand "mov<mode>"
8020 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8021 (match_operand:FMOVE32 1 "any_operand" ""))]
8022 "<fmove_ok>"
8023 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8025 (define_split
8026 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8027 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8028 "reload_completed
8029 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8030 || (GET_CODE (operands[0]) == SUBREG
8031 && GET_CODE (SUBREG_REG (operands[0])) == REG
8032 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8033 [(set (match_dup 2) (match_dup 3))]
8034 "
8035 {
8036 long l;
8037 REAL_VALUE_TYPE rv;
8039 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8040 <real_value_to_target> (rv, l);
8042 if (! TARGET_POWERPC64)
8043 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8044 else
8045 operands[2] = gen_lowpart (SImode, operands[0]);
8047 operands[3] = gen_int_mode (l, SImode);
8048 }")
8050 (define_insn "mov<mode>_hardfloat"
8051 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
8052 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
8053 "(gpc_reg_operand (operands[0], <MODE>mode)
8054 || gpc_reg_operand (operands[1], <MODE>mode))
8055 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8056 "@
8057 mr %0,%1
8058 lwz%U1%X1 %0,%1
8059 stw%U0%X0 %1,%0
8060 fmr %0,%1
8061 xxlor %x0,%x1,%x1
8062 xxlxor %x0,%x0,%x0
8063 <f32_li>
8064 <f32_si>
8065 <f32_lv>
8066 <f32_sv>
8067 mtvsrwz %x0,%1
8068 mfvsrwz %0,%x1
8069 mt%0 %1
8070 mf%1 %0
8071 nop
8072 #
8073 #"
8074 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
8075 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
8077 (define_insn "*mov<mode>_softfloat"
8078 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8079 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
8080 "(gpc_reg_operand (operands[0], <MODE>mode)
8081 || gpc_reg_operand (operands[1], <MODE>mode))
8082 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8083 "@
8084 mr %0,%1
8085 mt%0 %1
8086 mf%1 %0
8087 lwz%U1%X1 %0,%1
8088 stw%U0%X0 %1,%0
8089 li %0,%1
8090 lis %0,%v1
8091 #
8092 #
8093 nop"
8094 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
8095 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8097 \f
8098 ;; Move 64-bit binary/decimal floating point
8099 (define_expand "mov<mode>"
8100 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8101 (match_operand:FMOVE64 1 "any_operand" ""))]
8102 ""
8103 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8105 (define_split
8106 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8107 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8108 "! TARGET_POWERPC64 && reload_completed
8109 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8110 || (GET_CODE (operands[0]) == SUBREG
8111 && GET_CODE (SUBREG_REG (operands[0])) == REG
8112 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8113 [(set (match_dup 2) (match_dup 4))
8114 (set (match_dup 3) (match_dup 1))]
8115 "
8116 {
8117 int endian = (WORDS_BIG_ENDIAN == 0);
8118 HOST_WIDE_INT value = INTVAL (operands[1]);
8120 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8121 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8122 operands[4] = GEN_INT (value >> 32);
8123 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8124 }")
8126 (define_split
8127 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8128 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8129 "! TARGET_POWERPC64 && reload_completed
8130 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8131 || (GET_CODE (operands[0]) == SUBREG
8132 && GET_CODE (SUBREG_REG (operands[0])) == REG
8133 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8134 [(set (match_dup 2) (match_dup 4))
8135 (set (match_dup 3) (match_dup 5))]
8136 "
8137 {
8138 int endian = (WORDS_BIG_ENDIAN == 0);
8139 long l[2];
8140 REAL_VALUE_TYPE rv;
8142 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8143 <real_value_to_target> (rv, l);
8145 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8146 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8147 operands[4] = gen_int_mode (l[endian], SImode);
8148 operands[5] = gen_int_mode (l[1 - endian], SImode);
8149 }")
8151 (define_split
8152 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8153 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8154 "TARGET_POWERPC64 && reload_completed
8155 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8156 || (GET_CODE (operands[0]) == SUBREG
8157 && GET_CODE (SUBREG_REG (operands[0])) == REG
8158 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8159 [(set (match_dup 2) (match_dup 3))]
8160 "
8161 {
8162 int endian = (WORDS_BIG_ENDIAN == 0);
8163 long l[2];
8164 REAL_VALUE_TYPE rv;
8165 HOST_WIDE_INT val;
8167 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8168 <real_value_to_target> (rv, l);
8170 operands[2] = gen_lowpart (DImode, operands[0]);
8171 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8172 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8173 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8175 operands[3] = gen_int_mode (val, DImode);
8176 }")
8178 ;; Don't have reload use general registers to load a constant. It is
8179 ;; less efficient than loading the constant into an FP register, since
8180 ;; it will probably be used there.
8182 ;; The move constraints are ordered to prefer floating point registers before
8183 ;; general purpose registers to avoid doing a store and a load to get the value
8184 ;; into a floating point register when it is needed for a floating point
8185 ;; operation. Prefer traditional floating point registers over VSX registers,
8186 ;; since the D-form version of the memory instructions does not need a GPR for
8187 ;; reloading.
8189 (define_insn "*mov<mode>_hardfloat32"
8190 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
8191 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
8192 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8193 && (gpc_reg_operand (operands[0], <MODE>mode)
8194 || gpc_reg_operand (operands[1], <MODE>mode))"
8195 "@
8196 stfd%U0%X0 %1,%0
8197 lfd%U1%X1 %0,%1
8198 fmr %0,%1
8199 lxsd%U1x %x0,%y1
8200 stxsd%U0x %x1,%y0
8201 xxlor %x0,%x1,%x1
8202 xxlxor %x0,%x0,%x0
8203 #
8204 #
8205 #
8206 #
8207 #
8208 #"
8209 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8210 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8212 (define_insn "*mov<mode>_softfloat32"
8213 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8214 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8215 "! TARGET_POWERPC64
8216 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8217 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8218 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8219 && (gpc_reg_operand (operands[0], <MODE>mode)
8220 || gpc_reg_operand (operands[1], <MODE>mode))"
8221 "#"
8222 [(set_attr "type" "store,load,two,*,*,*")
8223 (set_attr "length" "8,8,8,8,12,16")])
8225 ; ld/std require word-aligned displacements -> 'Y' constraint.
8226 ; List Y->r and r->Y before r->r for reload.
8227 (define_insn "*mov<mode>_hardfloat64"
8228 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
8229 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
8230 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8231 && (gpc_reg_operand (operands[0], <MODE>mode)
8232 || gpc_reg_operand (operands[1], <MODE>mode))"
8233 "@
8234 stfd%U0%X0 %1,%0
8235 lfd%U1%X1 %0,%1
8236 fmr %0,%1
8237 lxsd%U1x %x0,%y1
8238 stxsd%U0x %x1,%y0
8239 xxlor %x0,%x1,%x1
8240 xxlxor %x0,%x0,%x0
8241 std%U0%X0 %1,%0
8242 ld%U1%X1 %0,%1
8243 mr %0,%1
8244 mt%0 %1
8245 mf%1 %0
8246 nop
8247 #
8248 #
8249 #
8250 mftgpr %0,%1
8251 mffgpr %0,%1
8252 mfvsrd %0,%x1
8253 mtvsrd %x0,%1"
8254 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8255 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8257 (define_insn "*mov<mode>_softfloat64"
8258 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8259 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8260 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8261 && (gpc_reg_operand (operands[0], <MODE>mode)
8262 || gpc_reg_operand (operands[1], <MODE>mode))"
8263 "@
8264 std%U0%X0 %1,%0
8265 ld%U1%X1 %0,%1
8266 mr %0,%1
8267 mt%0 %1
8268 mf%1 %0
8269 #
8270 #
8271 #
8272 nop"
8273 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8274 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8275 \f
8276 (define_expand "mov<mode>"
8277 [(set (match_operand:FMOVE128 0 "general_operand" "")
8278 (match_operand:FMOVE128 1 "any_operand" ""))]
8279 ""
8280 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8282 ;; It's important to list Y->r and r->Y before r->r because otherwise
8283 ;; reload, given m->r, will try to pick r->r and reload it, which
8284 ;; doesn't make progress.
8286 ;; We can't split little endian direct moves of TDmode, because the words are
8287 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8288 ;; problematical. Don't allow direct move for this case.
8290 (define_insn_and_split "*mov<mode>_64bit_dm"
8291 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm")
8292 (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r,wm,r"))]
8293 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8294 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8295 && (gpc_reg_operand (operands[0], <MODE>mode)
8296 || gpc_reg_operand (operands[1], <MODE>mode))"
8297 "#"
8298 "&& reload_completed"
8299 [(pc)]
8300 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8301 [(set_attr "length" "8,8,8,8,12,12,8,8,8")])
8303 (define_insn_and_split "*movtd_64bit_nodm"
8304 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
8305 (match_operand:TD 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
8306 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8307 && (gpc_reg_operand (operands[0], TDmode)
8308 || gpc_reg_operand (operands[1], TDmode))"
8309 "#"
8310 "&& reload_completed"
8311 [(pc)]
8312 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8313 [(set_attr "length" "8,8,8,8,12,12,8")])
8315 (define_insn_and_split "*mov<mode>_32bit"
8316 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
8317 (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
8318 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8319 && (gpc_reg_operand (operands[0], <MODE>mode)
8320 || gpc_reg_operand (operands[1], <MODE>mode))"
8321 "#"
8322 "&& reload_completed"
8323 [(pc)]
8324 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8325 [(set_attr "length" "8,8,8,8,20,20,16")])
8327 (define_insn_and_split "*mov<mode>_softfloat"
8328 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8329 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8330 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8331 && (gpc_reg_operand (operands[0], <MODE>mode)
8332 || gpc_reg_operand (operands[1], <MODE>mode))"
8333 "#"
8334 "&& reload_completed"
8335 [(pc)]
8336 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8337 [(set_attr "length" "20,20,16")])
8339 ;; If we are using -ffast-math, easy_fp_constant assumes all constants are
8340 ;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
8341 ;; is in the constant pool before reload occurs. This simplifies accessing
8342 ;; scalars in the traditional Altivec registers.
8344 (define_split
8345 [(set (match_operand:SFDF 0 "register_operand" "")
8346 (match_operand:SFDF 1 "memory_fp_constant" ""))]
8347 "TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
8348 && !reload_in_progress && !reload_completed && !lra_in_progress"
8349 [(set (match_dup 0) (match_dup 2))]
8350 {
8351 operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
8352 })
8354 (define_expand "extenddftf2"
8355 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8356 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8357 "!TARGET_IEEEQUAD
8358 && TARGET_HARD_FLOAT
8359 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8360 && TARGET_LONG_DOUBLE_128"
8361 {
8362 if (TARGET_E500_DOUBLE)
8363 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8364 else
8365 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8366 DONE;
8367 })
8369 (define_expand "extenddftf2_fprs"
8370 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8371 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8372 (use (match_dup 2))])]
8373 "!TARGET_IEEEQUAD
8374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8375 && TARGET_LONG_DOUBLE_128"
8376 {
8377 operands[2] = CONST0_RTX (DFmode);
8378 /* Generate GOT reference early for SVR4 PIC. */
8379 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8380 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8381 })
8383 (define_insn_and_split "*extenddftf2_internal"
8384 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8385 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8386 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8387 "!TARGET_IEEEQUAD
8388 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8389 && TARGET_LONG_DOUBLE_128"
8390 "#"
8391 "&& reload_completed"
8392 [(pc)]
8393 {
8394 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8395 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8396 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8397 operands[1]);
8398 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8399 operands[2]);
8400 DONE;
8401 })
8403 (define_expand "extendsftf2"
8404 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8405 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8406 "!TARGET_IEEEQUAD
8407 && TARGET_HARD_FLOAT
8408 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8409 && TARGET_LONG_DOUBLE_128"
8410 {
8411 rtx tmp = gen_reg_rtx (DFmode);
8412 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8413 emit_insn (gen_extenddftf2 (operands[0], tmp));
8414 DONE;
8415 })
8417 (define_expand "trunctfdf2"
8418 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8419 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8420 "!TARGET_IEEEQUAD
8421 && TARGET_HARD_FLOAT
8422 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8423 && TARGET_LONG_DOUBLE_128"
8424 "")
8426 (define_insn_and_split "trunctfdf2_internal1"
8427 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8428 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8429 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8430 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8431 "@
8432 #
8433 fmr %0,%1"
8434 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8435 [(const_int 0)]
8436 {
8437 emit_note (NOTE_INSN_DELETED);
8438 DONE;
8439 }
8440 [(set_attr "type" "fp")])
8442 (define_insn "trunctfdf2_internal2"
8443 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8444 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8445 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8446 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8447 && TARGET_LONG_DOUBLE_128"
8448 "fadd %0,%1,%L1"
8449 [(set_attr "type" "fp")
8450 (set_attr "fp_type" "fp_addsub_d")])
8452 (define_expand "trunctfsf2"
8453 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8454 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8455 "!TARGET_IEEEQUAD
8456 && TARGET_HARD_FLOAT
8457 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8458 && TARGET_LONG_DOUBLE_128"
8459 {
8460 if (TARGET_E500_DOUBLE)
8461 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8462 else
8463 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8464 DONE;
8465 })
8467 (define_insn_and_split "trunctfsf2_fprs"
8468 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8469 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8470 (clobber (match_scratch:DF 2 "=d"))]
8471 "!TARGET_IEEEQUAD
8472 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8473 && TARGET_LONG_DOUBLE_128"
8474 "#"
8475 "&& reload_completed"
8476 [(set (match_dup 2)
8477 (float_truncate:DF (match_dup 1)))
8478 (set (match_dup 0)
8479 (float_truncate:SF (match_dup 2)))]
8480 "")
8482 (define_expand "floatsitf2"
8483 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8484 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8485 "!TARGET_IEEEQUAD
8486 && TARGET_HARD_FLOAT
8487 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8488 && TARGET_LONG_DOUBLE_128"
8489 {
8490 rtx tmp = gen_reg_rtx (DFmode);
8491 expand_float (tmp, operands[1], false);
8492 emit_insn (gen_extenddftf2 (operands[0], tmp));
8493 DONE;
8494 })
8496 ; fadd, but rounding towards zero.
8497 ; This is probably not the optimal code sequence.
8498 (define_insn "fix_trunc_helper"
8499 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8500 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8501 UNSPEC_FIX_TRUNC_TF))
8502 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8503 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8504 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8505 [(set_attr "type" "fp")
8506 (set_attr "length" "20")])
8508 (define_expand "fix_trunctfsi2"
8509 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8510 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8511 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8512 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8513 {
8514 if (TARGET_E500_DOUBLE)
8515 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8516 else
8517 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8518 DONE;
8519 })
8521 (define_expand "fix_trunctfsi2_fprs"
8522 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8523 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8524 (clobber (match_dup 2))
8525 (clobber (match_dup 3))
8526 (clobber (match_dup 4))
8527 (clobber (match_dup 5))])]
8528 "!TARGET_IEEEQUAD
8529 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8530 {
8531 operands[2] = gen_reg_rtx (DFmode);
8532 operands[3] = gen_reg_rtx (DFmode);
8533 operands[4] = gen_reg_rtx (DImode);
8534 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8535 })
8537 (define_insn_and_split "*fix_trunctfsi2_internal"
8538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8539 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8540 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8541 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8542 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8543 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8544 "!TARGET_IEEEQUAD
8545 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8546 "#"
8547 ""
8548 [(pc)]
8549 {
8550 rtx lowword;
8551 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8553 gcc_assert (MEM_P (operands[5]));
8554 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8556 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8557 emit_move_insn (operands[5], operands[4]);
8558 emit_move_insn (operands[0], lowword);
8559 DONE;
8560 })
8562 (define_expand "negtf2"
8563 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8564 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8565 "!TARGET_IEEEQUAD
8566 && TARGET_HARD_FLOAT
8567 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8568 && TARGET_LONG_DOUBLE_128"
8569 "")
8571 (define_insn "negtf2_internal"
8572 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8573 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8574 "!TARGET_IEEEQUAD
8575 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8576 "*
8577 {
8578 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8579 return \"fneg %L0,%L1\;fneg %0,%1\";
8580 else
8581 return \"fneg %0,%1\;fneg %L0,%L1\";
8582 }"
8583 [(set_attr "type" "fp")
8584 (set_attr "length" "8")])
8586 (define_expand "abstf2"
8587 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8588 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8589 "!TARGET_IEEEQUAD
8590 && TARGET_HARD_FLOAT
8591 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8592 && TARGET_LONG_DOUBLE_128"
8593 "
8594 {
8595 rtx label = gen_label_rtx ();
8596 if (TARGET_E500_DOUBLE)
8597 {
8598 if (flag_finite_math_only && !flag_trapping_math)
8599 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8600 else
8601 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8602 }
8603 else
8604 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8605 emit_label (label);
8606 DONE;
8607 }")
8609 (define_expand "abstf2_internal"
8610 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8611 (match_operand:TF 1 "gpc_reg_operand" ""))
8612 (set (match_dup 3) (match_dup 5))
8613 (set (match_dup 5) (abs:DF (match_dup 5)))
8614 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8615 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8616 (label_ref (match_operand 2 "" ""))
8617 (pc)))
8618 (set (match_dup 6) (neg:DF (match_dup 6)))]
8619 "!TARGET_IEEEQUAD
8620 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8621 && TARGET_LONG_DOUBLE_128"
8622 "
8623 {
8624 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8625 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8626 operands[3] = gen_reg_rtx (DFmode);
8627 operands[4] = gen_reg_rtx (CCFPmode);
8628 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8629 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8630 }")
8631 \f
8632 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8633 ;; must have 3 arguments, and scratch register constraint must be a single
8634 ;; constraint.
8636 ;; Reload patterns to support gpr load/store with misaligned mem.
8637 ;; and multiple gpr load/store at offset >= 0xfffc
8638 (define_expand "reload_<mode>_store"
8639 [(parallel [(match_operand 0 "memory_operand" "=m")
8640 (match_operand 1 "gpc_reg_operand" "r")
8641 (match_operand:GPR 2 "register_operand" "=&b")])]
8642 ""
8643 {
8644 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8645 DONE;
8646 })
8648 (define_expand "reload_<mode>_load"
8649 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8650 (match_operand 1 "memory_operand" "m")
8651 (match_operand:GPR 2 "register_operand" "=b")])]
8652 ""
8653 {
8654 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8655 DONE;
8656 })
8658 \f
8659 ;; Reload patterns for various types using the vector registers. We may need
8660 ;; an additional base register to convert the reg+offset addressing to reg+reg
8661 ;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
8662 ;; index register for gpr registers.
8663 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
8664 [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
8665 (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
8666 (match_operand:P 2 "register_operand" "=b")])]
8667 "<P:tptrsize>"
8668 {
8669 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
8670 DONE;
8671 })
8673 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
8674 [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
8675 (match_operand:RELOAD 1 "memory_operand" "m")
8676 (match_operand:P 2 "register_operand" "=b")])]
8677 "<P:tptrsize>"
8678 {
8679 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
8680 DONE;
8681 })
8684 ;; Reload sometimes tries to move the address to a GPR, and can generate
8685 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
8686 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
8688 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
8689 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
8690 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
8691 (match_operand:P 2 "reg_or_cint_operand" "rI"))
8692 (const_int -16)))]
8693 "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
8694 "#"
8695 "&& reload_completed"
8696 [(set (match_dup 0)
8697 (plus:P (match_dup 1)
8698 (match_dup 2)))
8699 (set (match_dup 0)
8700 (and:P (match_dup 0)
8701 (const_int -16)))])
8702 \f
8703 ;; Power8 merge instructions to allow direct move to/from floating point
8704 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8705 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8706 ;; value, since it is allocated in reload and not all of the flow information
8707 ;; is setup for it. We have two patterns to do the two moves between gprs and
8708 ;; fprs. There isn't a dependancy between the two, but we could potentially
8709 ;; schedule other instructions between the two instructions. TFmode is
8710 ;; currently limited to traditional FPR registers. If/when this is changed, we
8711 ;; will need to revist %L to make sure it works with VSX registers, or add an
8712 ;; %x version of %L.
8714 (define_insn "p8_fmrgow_<mode>"
8715 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8716 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8717 UNSPEC_P8V_FMRGOW))]
8718 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8719 "fmrgow %0,%1,%L1"
8720 [(set_attr "type" "vecperm")])
8722 (define_insn "p8_mtvsrwz_1"
8723 [(set (match_operand:TF 0 "register_operand" "=d")
8724 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8725 UNSPEC_P8V_MTVSRWZ))]
8726 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8727 "mtvsrwz %x0,%1"
8728 [(set_attr "type" "mftgpr")])
8730 (define_insn "p8_mtvsrwz_2"
8731 [(set (match_operand:TF 0 "register_operand" "+d")
8732 (unspec:TF [(match_dup 0)
8733 (match_operand:SI 1 "register_operand" "r")]
8734 UNSPEC_P8V_MTVSRWZ))]
8735 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8736 "mtvsrwz %L0,%1"
8737 [(set_attr "type" "mftgpr")])
8739 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8740 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8741 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8742 UNSPEC_P8V_RELOAD_FROM_GPR))
8743 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8744 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8745 "#"
8746 "&& reload_completed"
8747 [(const_int 0)]
8748 {
8749 rtx dest = operands[0];
8750 rtx src = operands[1];
8751 rtx tmp = operands[2];
8752 rtx gpr_hi_reg = gen_highpart (SImode, src);
8753 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8755 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8756 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8757 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8758 DONE;
8759 }
8760 [(set_attr "length" "12")
8761 (set_attr "type" "three")])
8763 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8764 (define_insn "p8_mtvsrd_1"
8765 [(set (match_operand:TF 0 "register_operand" "=ws")
8766 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8767 UNSPEC_P8V_MTVSRD))]
8768 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8769 "mtvsrd %0,%1"
8770 [(set_attr "type" "mftgpr")])
8772 (define_insn "p8_mtvsrd_2"
8773 [(set (match_operand:TF 0 "register_operand" "+ws")
8774 (unspec:TF [(match_dup 0)
8775 (match_operand:DI 1 "register_operand" "r")]
8776 UNSPEC_P8V_MTVSRD))]
8777 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8778 "mtvsrd %L0,%1"
8779 [(set_attr "type" "mftgpr")])
8781 (define_insn "p8_xxpermdi_<mode>"
8782 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8783 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8784 UNSPEC_P8V_XXPERMDI))]
8785 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8786 "xxpermdi %x0,%1,%L1,0"
8787 [(set_attr "type" "vecperm")])
8789 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8790 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8791 (unspec:FMOVE128_GPR
8792 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8793 UNSPEC_P8V_RELOAD_FROM_GPR))
8794 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8795 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8796 "#"
8797 "&& reload_completed"
8798 [(const_int 0)]
8799 {
8800 rtx dest = operands[0];
8801 rtx src = operands[1];
8802 rtx tmp = operands[2];
8803 rtx gpr_hi_reg = gen_highpart (DImode, src);
8804 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8806 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8807 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8808 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8809 }
8810 [(set_attr "length" "12")
8811 (set_attr "type" "three")])
8813 (define_split
8814 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8815 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8816 "reload_completed
8817 && (int_reg_operand (operands[0], <MODE>mode)
8818 || int_reg_operand (operands[1], <MODE>mode))"
8819 [(pc)]
8820 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8822 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8823 ;; type is stored internally as double precision in the VSX registers, we have
8824 ;; to convert it from the vector format.
8826 (define_insn_and_split "reload_vsx_from_gprsf"
8827 [(set (match_operand:SF 0 "register_operand" "=wa")
8828 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8829 UNSPEC_P8V_RELOAD_FROM_GPR))
8830 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8831 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8832 "#"
8833 "&& reload_completed"
8834 [(const_int 0)]
8835 {
8836 rtx op0 = operands[0];
8837 rtx op1 = operands[1];
8838 rtx op2 = operands[2];
8839 /* Also use the destination register to hold the unconverted DImode value.
8840 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8841 rather than simplify_gen_subreg. */
8842 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8843 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8845 /* Move SF value to upper 32-bits for xscvspdpn. */
8846 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8847 emit_move_insn (op0_di, op2);
8848 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8849 DONE;
8850 }
8851 [(set_attr "length" "8")
8852 (set_attr "type" "two")])
8854 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8855 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8856 ;; and then doing a move of that.
8857 (define_insn "p8_mfvsrd_3_<mode>"
8858 [(set (match_operand:DF 0 "register_operand" "=r")
8859 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8860 UNSPEC_P8V_RELOAD_FROM_VSX))]
8861 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8862 "mfvsrd %0,%x1"
8863 [(set_attr "type" "mftgpr")])
8865 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8866 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8867 (unspec:FMOVE128_GPR
8868 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8869 UNSPEC_P8V_RELOAD_FROM_VSX))
8870 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8871 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8872 "#"
8873 "&& reload_completed"
8874 [(const_int 0)]
8875 {
8876 rtx dest = operands[0];
8877 rtx src = operands[1];
8878 rtx tmp = operands[2];
8879 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8880 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8882 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8883 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8884 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8885 }
8886 [(set_attr "length" "12")
8887 (set_attr "type" "three")])
8889 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8890 ;; type is stored internally as double precision, we have to convert it to the
8891 ;; vector format.
8893 (define_insn_and_split "reload_gpr_from_vsxsf"
8894 [(set (match_operand:SF 0 "register_operand" "=r")
8895 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8896 UNSPEC_P8V_RELOAD_FROM_VSX))
8897 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8898 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8899 "#"
8900 "&& reload_completed"
8901 [(const_int 0)]
8902 {
8903 rtx op0 = operands[0];
8904 rtx op1 = operands[1];
8905 rtx op2 = operands[2];
8906 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8908 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8909 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8910 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8911 DONE;
8912 }
8913 [(set_attr "length" "12")
8914 (set_attr "type" "three")])
8916 (define_insn "p8_mfvsrd_4_disf"
8917 [(set (match_operand:DI 0 "register_operand" "=r")
8918 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8919 UNSPEC_P8V_RELOAD_FROM_VSX))]
8920 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8921 "mfvsrd %0,%x1"
8922 [(set_attr "type" "mftgpr")])
8924 \f
8925 ;; Next come the multi-word integer load and store and the load and store
8926 ;; multiple insns.
8928 ;; List r->r after r->Y, otherwise reload will try to reload a
8929 ;; non-offsettable address by using r->r which won't make progress.
8930 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8931 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8932 (define_insn "*movdi_internal32"
8933 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8934 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8935 "! TARGET_POWERPC64
8936 && (gpc_reg_operand (operands[0], DImode)
8937 || gpc_reg_operand (operands[1], DImode))"
8938 "@
8939 #
8940 #
8941 #
8942 stfd%U0%X0 %1,%0
8943 lfd%U1%X1 %0,%1
8944 fmr %0,%1
8945 #"
8946 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8948 (define_split
8949 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8950 (match_operand:DI 1 "const_int_operand" ""))]
8951 "! TARGET_POWERPC64 && reload_completed
8952 && gpr_or_gpr_p (operands[0], operands[1])
8953 && !direct_move_p (operands[0], operands[1])"
8954 [(set (match_dup 2) (match_dup 4))
8955 (set (match_dup 3) (match_dup 1))]
8956 "
8957 {
8958 HOST_WIDE_INT value = INTVAL (operands[1]);
8959 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8960 DImode);
8961 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8962 DImode);
8963 operands[4] = GEN_INT (value >> 32);
8964 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8965 }")
8967 (define_split
8968 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8969 (match_operand:DIFD 1 "input_operand" ""))]
8970 "reload_completed && !TARGET_POWERPC64
8971 && gpr_or_gpr_p (operands[0], operands[1])
8972 && !direct_move_p (operands[0], operands[1])"
8973 [(pc)]
8974 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8976 (define_insn "*movdi_internal64"
8977 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8978 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8979 "TARGET_POWERPC64
8980 && (gpc_reg_operand (operands[0], DImode)
8981 || gpc_reg_operand (operands[1], DImode))"
8982 "@
8983 std%U0%X0 %1,%0
8984 ld%U1%X1 %0,%1
8985 mr %0,%1
8986 li %0,%1
8987 lis %0,%v1
8988 #
8989 stfd%U0%X0 %1,%0
8990 lfd%U1%X1 %0,%1
8991 fmr %0,%1
8992 mf%1 %0
8993 mt%0 %1
8994 nop
8995 mftgpr %0,%1
8996 mffgpr %0,%1
8997 mfvsrd %0,%x1
8998 mtvsrd %x0,%1
8999 xxlxor %x0,%x0,%x0"
9000 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
9001 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
9003 ;; Generate all one-bits and clear left or right.
9004 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9005 (define_split
9006 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9007 (match_operand:DI 1 "mask64_operand" ""))]
9008 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9009 [(set (match_dup 0) (const_int -1))
9010 (set (match_dup 0)
9011 (and:DI (rotate:DI (match_dup 0)
9012 (const_int 0))
9013 (match_dup 1)))]
9014 "")
9016 ;; Split a load of a large constant into the appropriate five-instruction
9017 ;; sequence. Handle anything in a constant number of insns.
9018 ;; When non-easy constants can go in the TOC, this should use
9019 ;; easy_fp_constant predicate.
9020 (define_split
9021 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9022 (match_operand:DI 1 "const_int_operand" ""))]
9023 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9024 [(set (match_dup 0) (match_dup 2))
9025 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9026 "
9027 {
9028 if (rs6000_emit_set_const (operands[0], operands[1]))
9029 DONE;
9030 else
9031 FAIL;
9032 }")
9034 (define_split
9035 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9036 (match_operand:DI 1 "const_scalar_int_operand" ""))]
9037 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9038 [(set (match_dup 0) (match_dup 2))
9039 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9040 "
9041 {
9042 if (rs6000_emit_set_const (operands[0], operands[1]))
9043 DONE;
9044 else
9045 FAIL;
9046 }")
9047 \f
9048 ;; TImode/PTImode is similar, except that we usually want to compute the
9049 ;; address into a register and use lsi/stsi (the exception is during reload).
9051 (define_insn "*mov<mode>_string"
9052 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9053 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9054 "! TARGET_POWERPC64
9055 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9056 && (gpc_reg_operand (operands[0], <MODE>mode)
9057 || gpc_reg_operand (operands[1], <MODE>mode))"
9058 "*
9059 {
9060 switch (which_alternative)
9061 {
9062 default:
9063 gcc_unreachable ();
9064 case 0:
9065 if (TARGET_STRING)
9066 return \"stswi %1,%P0,16\";
9067 case 1:
9068 return \"#\";
9069 case 2:
9070 /* If the address is not used in the output, we can use lsi. Otherwise,
9071 fall through to generating four loads. */
9072 if (TARGET_STRING
9073 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9074 return \"lswi %0,%P1,16\";
9075 /* ... fall through ... */
9076 case 3:
9077 case 4:
9078 case 5:
9079 return \"#\";
9080 }
9081 }"
9082 [(set_attr "type" "store,store,load,load,*,*")
9083 (set_attr "update" "yes")
9084 (set_attr "indexed" "yes")
9085 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9086 (const_string "always")
9087 (const_string "conditional")))])
9089 (define_insn "*mov<mode>_ppc64"
9090 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
9091 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
9092 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
9093 && (gpc_reg_operand (operands[0], <MODE>mode)
9094 || gpc_reg_operand (operands[1], <MODE>mode)))"
9095 {
9096 return rs6000_output_move_128bit (operands);
9097 }
9098 [(set_attr "type" "store,store,load,load,*,*")
9099 (set_attr "length" "8")])
9101 (define_split
9102 [(set (match_operand:TI2 0 "int_reg_operand" "")
9103 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
9104 "TARGET_POWERPC64
9105 && (VECTOR_MEM_NONE_P (<MODE>mode)
9106 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
9107 [(set (match_dup 2) (match_dup 4))
9108 (set (match_dup 3) (match_dup 5))]
9109 "
9110 {
9111 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9112 <MODE>mode);
9113 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9114 <MODE>mode);
9115 if (CONST_WIDE_INT_P (operands[1]))
9116 {
9117 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
9118 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
9119 }
9120 else if (CONST_INT_P (operands[1]))
9121 {
9122 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9123 operands[5] = operands[1];
9124 }
9125 else
9126 FAIL;
9127 }")
9129 (define_split
9130 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
9131 (match_operand:TI2 1 "input_operand" ""))]
9132 "reload_completed
9133 && gpr_or_gpr_p (operands[0], operands[1])
9134 && !direct_move_p (operands[0], operands[1])
9135 && !quad_load_store_p (operands[0], operands[1])"
9136 [(pc)]
9137 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9138 \f
9139 (define_expand "load_multiple"
9140 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9141 (match_operand:SI 1 "" ""))
9142 (use (match_operand:SI 2 "" ""))])]
9143 "TARGET_STRING && !TARGET_POWERPC64"
9144 "
9145 {
9146 int regno;
9147 int count;
9148 rtx op1;
9149 int i;
9151 /* Support only loading a constant number of fixed-point registers from
9152 memory and only bother with this if more than two; the machine
9153 doesn't support more than eight. */
9154 if (GET_CODE (operands[2]) != CONST_INT
9155 || INTVAL (operands[2]) <= 2
9156 || INTVAL (operands[2]) > 8
9157 || GET_CODE (operands[1]) != MEM
9158 || GET_CODE (operands[0]) != REG
9159 || REGNO (operands[0]) >= 32)
9160 FAIL;
9162 count = INTVAL (operands[2]);
9163 regno = REGNO (operands[0]);
9165 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9166 op1 = replace_equiv_address (operands[1],
9167 force_reg (SImode, XEXP (operands[1], 0)));
9169 for (i = 0; i < count; i++)
9170 XVECEXP (operands[3], 0, i)
9171 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9172 adjust_address_nv (op1, SImode, i * 4));
9173 }")
9175 (define_insn "*ldmsi8"
9176 [(match_parallel 0 "load_multiple_operation"
9177 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9178 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9179 (set (match_operand:SI 3 "gpc_reg_operand" "")
9180 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9181 (set (match_operand:SI 4 "gpc_reg_operand" "")
9182 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9183 (set (match_operand:SI 5 "gpc_reg_operand" "")
9184 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9185 (set (match_operand:SI 6 "gpc_reg_operand" "")
9186 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9187 (set (match_operand:SI 7 "gpc_reg_operand" "")
9188 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9189 (set (match_operand:SI 8 "gpc_reg_operand" "")
9190 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9191 (set (match_operand:SI 9 "gpc_reg_operand" "")
9192 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9193 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9194 "*
9195 { return rs6000_output_load_multiple (operands); }"
9196 [(set_attr "type" "load")
9197 (set_attr "update" "yes")
9198 (set_attr "indexed" "yes")
9199 (set_attr "length" "32")])
9201 (define_insn "*ldmsi7"
9202 [(match_parallel 0 "load_multiple_operation"
9203 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9204 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9205 (set (match_operand:SI 3 "gpc_reg_operand" "")
9206 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9207 (set (match_operand:SI 4 "gpc_reg_operand" "")
9208 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9209 (set (match_operand:SI 5 "gpc_reg_operand" "")
9210 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9211 (set (match_operand:SI 6 "gpc_reg_operand" "")
9212 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9213 (set (match_operand:SI 7 "gpc_reg_operand" "")
9214 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9215 (set (match_operand:SI 8 "gpc_reg_operand" "")
9216 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9217 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9218 "*
9219 { return rs6000_output_load_multiple (operands); }"
9220 [(set_attr "type" "load")
9221 (set_attr "update" "yes")
9222 (set_attr "indexed" "yes")
9223 (set_attr "length" "32")])
9225 (define_insn "*ldmsi6"
9226 [(match_parallel 0 "load_multiple_operation"
9227 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9228 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9229 (set (match_operand:SI 3 "gpc_reg_operand" "")
9230 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9231 (set (match_operand:SI 4 "gpc_reg_operand" "")
9232 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9233 (set (match_operand:SI 5 "gpc_reg_operand" "")
9234 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9235 (set (match_operand:SI 6 "gpc_reg_operand" "")
9236 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9237 (set (match_operand:SI 7 "gpc_reg_operand" "")
9238 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9239 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9240 "*
9241 { return rs6000_output_load_multiple (operands); }"
9242 [(set_attr "type" "load")
9243 (set_attr "update" "yes")
9244 (set_attr "indexed" "yes")
9245 (set_attr "length" "32")])
9247 (define_insn "*ldmsi5"
9248 [(match_parallel 0 "load_multiple_operation"
9249 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9250 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9251 (set (match_operand:SI 3 "gpc_reg_operand" "")
9252 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9253 (set (match_operand:SI 4 "gpc_reg_operand" "")
9254 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9255 (set (match_operand:SI 5 "gpc_reg_operand" "")
9256 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9257 (set (match_operand:SI 6 "gpc_reg_operand" "")
9258 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9259 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9260 "*
9261 { return rs6000_output_load_multiple (operands); }"
9262 [(set_attr "type" "load")
9263 (set_attr "update" "yes")
9264 (set_attr "indexed" "yes")
9265 (set_attr "length" "32")])
9267 (define_insn "*ldmsi4"
9268 [(match_parallel 0 "load_multiple_operation"
9269 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9270 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9271 (set (match_operand:SI 3 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9273 (set (match_operand:SI 4 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9275 (set (match_operand:SI 5 "gpc_reg_operand" "")
9276 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9277 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9278 "*
9279 { return rs6000_output_load_multiple (operands); }"
9280 [(set_attr "type" "load")
9281 (set_attr "update" "yes")
9282 (set_attr "indexed" "yes")
9283 (set_attr "length" "32")])
9285 (define_insn "*ldmsi3"
9286 [(match_parallel 0 "load_multiple_operation"
9287 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9288 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9289 (set (match_operand:SI 3 "gpc_reg_operand" "")
9290 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9291 (set (match_operand:SI 4 "gpc_reg_operand" "")
9292 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9293 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9294 "*
9295 { return rs6000_output_load_multiple (operands); }"
9296 [(set_attr "type" "load")
9297 (set_attr "update" "yes")
9298 (set_attr "indexed" "yes")
9299 (set_attr "length" "32")])
9301 (define_expand "store_multiple"
9302 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9303 (match_operand:SI 1 "" ""))
9304 (clobber (scratch:SI))
9305 (use (match_operand:SI 2 "" ""))])]
9306 "TARGET_STRING && !TARGET_POWERPC64"
9307 "
9308 {
9309 int regno;
9310 int count;
9311 rtx to;
9312 rtx op0;
9313 int i;
9315 /* Support only storing a constant number of fixed-point registers to
9316 memory and only bother with this if more than two; the machine
9317 doesn't support more than eight. */
9318 if (GET_CODE (operands[2]) != CONST_INT
9319 || INTVAL (operands[2]) <= 2
9320 || INTVAL (operands[2]) > 8
9321 || GET_CODE (operands[0]) != MEM
9322 || GET_CODE (operands[1]) != REG
9323 || REGNO (operands[1]) >= 32)
9324 FAIL;
9326 count = INTVAL (operands[2]);
9327 regno = REGNO (operands[1]);
9329 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9330 to = force_reg (SImode, XEXP (operands[0], 0));
9331 op0 = replace_equiv_address (operands[0], to);
9333 XVECEXP (operands[3], 0, 0)
9334 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9335 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9336 gen_rtx_SCRATCH (SImode));
9338 for (i = 1; i < count; i++)
9339 XVECEXP (operands[3], 0, i + 1)
9340 = gen_rtx_SET (VOIDmode,
9341 adjust_address_nv (op0, SImode, i * 4),
9342 gen_rtx_REG (SImode, regno + i));
9343 }")
9345 (define_insn "*stmsi8"
9346 [(match_parallel 0 "store_multiple_operation"
9347 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9348 (match_operand:SI 2 "gpc_reg_operand" "r"))
9349 (clobber (match_scratch:SI 3 "=X"))
9350 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9351 (match_operand:SI 4 "gpc_reg_operand" "r"))
9352 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9353 (match_operand:SI 5 "gpc_reg_operand" "r"))
9354 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9355 (match_operand:SI 6 "gpc_reg_operand" "r"))
9356 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9357 (match_operand:SI 7 "gpc_reg_operand" "r"))
9358 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9359 (match_operand:SI 8 "gpc_reg_operand" "r"))
9360 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9361 (match_operand:SI 9 "gpc_reg_operand" "r"))
9362 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9363 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9364 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9365 "stswi %2,%1,%O0"
9366 [(set_attr "type" "store")
9367 (set_attr "update" "yes")
9368 (set_attr "indexed" "yes")
9369 (set_attr "cell_micro" "always")])
9371 (define_insn "*stmsi7"
9372 [(match_parallel 0 "store_multiple_operation"
9373 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9374 (match_operand:SI 2 "gpc_reg_operand" "r"))
9375 (clobber (match_scratch:SI 3 "=X"))
9376 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9377 (match_operand:SI 4 "gpc_reg_operand" "r"))
9378 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9379 (match_operand:SI 5 "gpc_reg_operand" "r"))
9380 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9381 (match_operand:SI 6 "gpc_reg_operand" "r"))
9382 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9383 (match_operand:SI 7 "gpc_reg_operand" "r"))
9384 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9385 (match_operand:SI 8 "gpc_reg_operand" "r"))
9386 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9387 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9388 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9389 "stswi %2,%1,%O0"
9390 [(set_attr "type" "store")
9391 (set_attr "update" "yes")
9392 (set_attr "indexed" "yes")
9393 (set_attr "cell_micro" "always")])
9395 (define_insn "*stmsi6"
9396 [(match_parallel 0 "store_multiple_operation"
9397 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9398 (match_operand:SI 2 "gpc_reg_operand" "r"))
9399 (clobber (match_scratch:SI 3 "=X"))
9400 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9401 (match_operand:SI 4 "gpc_reg_operand" "r"))
9402 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9403 (match_operand:SI 5 "gpc_reg_operand" "r"))
9404 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9405 (match_operand:SI 6 "gpc_reg_operand" "r"))
9406 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9407 (match_operand:SI 7 "gpc_reg_operand" "r"))
9408 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9409 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9410 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9411 "stswi %2,%1,%O0"
9412 [(set_attr "type" "store")
9413 (set_attr "update" "yes")
9414 (set_attr "indexed" "yes")
9415 (set_attr "cell_micro" "always")])
9417 (define_insn "*stmsi5"
9418 [(match_parallel 0 "store_multiple_operation"
9419 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9420 (match_operand:SI 2 "gpc_reg_operand" "r"))
9421 (clobber (match_scratch:SI 3 "=X"))
9422 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9423 (match_operand:SI 4 "gpc_reg_operand" "r"))
9424 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9425 (match_operand:SI 5 "gpc_reg_operand" "r"))
9426 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9427 (match_operand:SI 6 "gpc_reg_operand" "r"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9429 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9430 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9431 "stswi %2,%1,%O0"
9432 [(set_attr "type" "store")
9433 (set_attr "update" "yes")
9434 (set_attr "indexed" "yes")
9435 (set_attr "cell_micro" "always")])
9437 (define_insn "*stmsi4"
9438 [(match_parallel 0 "store_multiple_operation"
9439 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9440 (match_operand:SI 2 "gpc_reg_operand" "r"))
9441 (clobber (match_scratch:SI 3 "=X"))
9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9443 (match_operand:SI 4 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9445 (match_operand:SI 5 "gpc_reg_operand" "r"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9447 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9448 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9449 "stswi %2,%1,%O0"
9450 [(set_attr "type" "store")
9451 (set_attr "update" "yes")
9452 (set_attr "indexed" "yes")
9453 (set_attr "cell_micro" "always")])
9455 (define_insn "*stmsi3"
9456 [(match_parallel 0 "store_multiple_operation"
9457 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9458 (match_operand:SI 2 "gpc_reg_operand" "r"))
9459 (clobber (match_scratch:SI 3 "=X"))
9460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9461 (match_operand:SI 4 "gpc_reg_operand" "r"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9463 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9464 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9465 "stswi %2,%1,%O0"
9466 [(set_attr "type" "store")
9467 (set_attr "update" "yes")
9468 (set_attr "indexed" "yes")
9469 (set_attr "cell_micro" "always")])
9470 \f
9471 (define_expand "setmemsi"
9472 [(parallel [(set (match_operand:BLK 0 "" "")
9473 (match_operand 2 "const_int_operand" ""))
9474 (use (match_operand:SI 1 "" ""))
9475 (use (match_operand:SI 3 "" ""))])]
9476 ""
9477 "
9478 {
9479 /* If value to set is not zero, use the library routine. */
9480 if (operands[2] != const0_rtx)
9481 FAIL;
9483 if (expand_block_clear (operands))
9484 DONE;
9485 else
9486 FAIL;
9487 }")
9489 ;; String/block move insn.
9490 ;; Argument 0 is the destination
9491 ;; Argument 1 is the source
9492 ;; Argument 2 is the length
9493 ;; Argument 3 is the alignment
9495 (define_expand "movmemsi"
9496 [(parallel [(set (match_operand:BLK 0 "" "")
9497 (match_operand:BLK 1 "" ""))
9498 (use (match_operand:SI 2 "" ""))
9499 (use (match_operand:SI 3 "" ""))])]
9500 ""
9501 "
9502 {
9503 if (expand_block_move (operands))
9504 DONE;
9505 else
9506 FAIL;
9507 }")
9509 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9510 ;; register allocator doesn't have a clue about allocating 8 word registers.
9511 ;; rD/rS = r5 is preferred, efficient form.
9512 (define_expand "movmemsi_8reg"
9513 [(parallel [(set (match_operand 0 "" "")
9514 (match_operand 1 "" ""))
9515 (use (match_operand 2 "" ""))
9516 (use (match_operand 3 "" ""))
9517 (clobber (reg:SI 5))
9518 (clobber (reg:SI 6))
9519 (clobber (reg:SI 7))
9520 (clobber (reg:SI 8))
9521 (clobber (reg:SI 9))
9522 (clobber (reg:SI 10))
9523 (clobber (reg:SI 11))
9524 (clobber (reg:SI 12))
9525 (clobber (match_scratch:SI 4 ""))])]
9526 "TARGET_STRING"
9527 "")
9529 (define_insn ""
9530 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9531 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9532 (use (match_operand:SI 2 "immediate_operand" "i"))
9533 (use (match_operand:SI 3 "immediate_operand" "i"))
9534 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9535 (clobber (reg:SI 6))
9536 (clobber (reg:SI 7))
9537 (clobber (reg:SI 8))
9538 (clobber (reg:SI 9))
9539 (clobber (reg:SI 10))
9540 (clobber (reg:SI 11))
9541 (clobber (reg:SI 12))
9542 (clobber (match_scratch:SI 5 "=X"))]
9543 "TARGET_STRING
9544 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9545 || INTVAL (operands[2]) == 0)
9546 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9547 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9548 && REGNO (operands[4]) == 5"
9549 "lswi %4,%1,%2\;stswi %4,%0,%2"
9550 [(set_attr "type" "store")
9551 (set_attr "update" "yes")
9552 (set_attr "indexed" "yes")
9553 (set_attr "cell_micro" "always")
9554 (set_attr "length" "8")])
9556 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9557 ;; register allocator doesn't have a clue about allocating 6 word registers.
9558 ;; rD/rS = r5 is preferred, efficient form.
9559 (define_expand "movmemsi_6reg"
9560 [(parallel [(set (match_operand 0 "" "")
9561 (match_operand 1 "" ""))
9562 (use (match_operand 2 "" ""))
9563 (use (match_operand 3 "" ""))
9564 (clobber (reg:SI 5))
9565 (clobber (reg:SI 6))
9566 (clobber (reg:SI 7))
9567 (clobber (reg:SI 8))
9568 (clobber (reg:SI 9))
9569 (clobber (reg:SI 10))
9570 (clobber (match_scratch:SI 4 ""))])]
9571 "TARGET_STRING"
9572 "")
9574 (define_insn ""
9575 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9576 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9577 (use (match_operand:SI 2 "immediate_operand" "i"))
9578 (use (match_operand:SI 3 "immediate_operand" "i"))
9579 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9580 (clobber (reg:SI 6))
9581 (clobber (reg:SI 7))
9582 (clobber (reg:SI 8))
9583 (clobber (reg:SI 9))
9584 (clobber (reg:SI 10))
9585 (clobber (match_scratch:SI 5 "=X"))]
9586 "TARGET_STRING
9587 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9588 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9589 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9590 && REGNO (operands[4]) == 5"
9591 "lswi %4,%1,%2\;stswi %4,%0,%2"
9592 [(set_attr "type" "store")
9593 (set_attr "update" "yes")
9594 (set_attr "indexed" "yes")
9595 (set_attr "cell_micro" "always")
9596 (set_attr "length" "8")])
9598 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9599 ;; problems with TImode.
9600 ;; rD/rS = r5 is preferred, efficient form.
9601 (define_expand "movmemsi_4reg"
9602 [(parallel [(set (match_operand 0 "" "")
9603 (match_operand 1 "" ""))
9604 (use (match_operand 2 "" ""))
9605 (use (match_operand 3 "" ""))
9606 (clobber (reg:SI 5))
9607 (clobber (reg:SI 6))
9608 (clobber (reg:SI 7))
9609 (clobber (reg:SI 8))
9610 (clobber (match_scratch:SI 4 ""))])]
9611 "TARGET_STRING"
9612 "")
9614 (define_insn ""
9615 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9616 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9617 (use (match_operand:SI 2 "immediate_operand" "i"))
9618 (use (match_operand:SI 3 "immediate_operand" "i"))
9619 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9620 (clobber (reg:SI 6))
9621 (clobber (reg:SI 7))
9622 (clobber (reg:SI 8))
9623 (clobber (match_scratch:SI 5 "=X"))]
9624 "TARGET_STRING
9625 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9626 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9627 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9628 && REGNO (operands[4]) == 5"
9629 "lswi %4,%1,%2\;stswi %4,%0,%2"
9630 [(set_attr "type" "store")
9631 (set_attr "update" "yes")
9632 (set_attr "indexed" "yes")
9633 (set_attr "cell_micro" "always")
9634 (set_attr "length" "8")])
9636 ;; Move up to 8 bytes at a time.
9637 (define_expand "movmemsi_2reg"
9638 [(parallel [(set (match_operand 0 "" "")
9639 (match_operand 1 "" ""))
9640 (use (match_operand 2 "" ""))
9641 (use (match_operand 3 "" ""))
9642 (clobber (match_scratch:DI 4 ""))
9643 (clobber (match_scratch:SI 5 ""))])]
9644 "TARGET_STRING && ! TARGET_POWERPC64"
9645 "")
9647 (define_insn ""
9648 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9649 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9650 (use (match_operand:SI 2 "immediate_operand" "i"))
9651 (use (match_operand:SI 3 "immediate_operand" "i"))
9652 (clobber (match_scratch:DI 4 "=&r"))
9653 (clobber (match_scratch:SI 5 "=X"))]
9654 "TARGET_STRING && ! TARGET_POWERPC64
9655 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9656 "lswi %4,%1,%2\;stswi %4,%0,%2"
9657 [(set_attr "type" "store")
9658 (set_attr "update" "yes")
9659 (set_attr "indexed" "yes")
9660 (set_attr "cell_micro" "always")
9661 (set_attr "length" "8")])
9663 ;; Move up to 4 bytes at a time.
9664 (define_expand "movmemsi_1reg"
9665 [(parallel [(set (match_operand 0 "" "")
9666 (match_operand 1 "" ""))
9667 (use (match_operand 2 "" ""))
9668 (use (match_operand 3 "" ""))
9669 (clobber (match_scratch:SI 4 ""))
9670 (clobber (match_scratch:SI 5 ""))])]
9671 "TARGET_STRING"
9672 "")
9674 (define_insn ""
9675 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9676 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9677 (use (match_operand:SI 2 "immediate_operand" "i"))
9678 (use (match_operand:SI 3 "immediate_operand" "i"))
9679 (clobber (match_scratch:SI 4 "=&r"))
9680 (clobber (match_scratch:SI 5 "=X"))]
9681 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9682 "lswi %4,%1,%2\;stswi %4,%0,%2"
9683 [(set_attr "type" "store")
9684 (set_attr "update" "yes")
9685 (set_attr "indexed" "yes")
9686 (set_attr "cell_micro" "always")
9687 (set_attr "length" "8")])
9688 \f
9689 ;; Define insns that do load or store with update. Some of these we can
9690 ;; get by using pre-decrement or pre-increment, but the hardware can also
9691 ;; do cases where the increment is not the size of the object.
9692 ;;
9693 ;; In all these cases, we use operands 0 and 1 for the register being
9694 ;; incremented because those are the operands that local-alloc will
9695 ;; tie and these are the pair most likely to be tieable (and the ones
9696 ;; that will benefit the most).
9698 (define_insn "*movdi_update1"
9699 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9700 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9701 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9702 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9703 (plus:DI (match_dup 1) (match_dup 2)))]
9704 "TARGET_POWERPC64 && TARGET_UPDATE
9705 && (!avoiding_indexed_address_p (DImode)
9706 || !gpc_reg_operand (operands[2], DImode))"
9707 "@
9708 ldux %3,%0,%2
9709 ldu %3,%2(%0)"
9710 [(set_attr "type" "load")
9711 (set_attr "update" "yes")
9712 (set_attr "indexed" "yes,no")])
9714 (define_insn "movdi_<mode>_update"
9715 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9716 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9717 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9718 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9719 (plus:P (match_dup 1) (match_dup 2)))]
9720 "TARGET_POWERPC64 && TARGET_UPDATE
9721 && (!avoiding_indexed_address_p (Pmode)
9722 || !gpc_reg_operand (operands[2], Pmode)
9723 || (REG_P (operands[0])
9724 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9725 "@
9726 stdux %3,%0,%2
9727 stdu %3,%2(%0)"
9728 [(set_attr "type" "store")
9729 (set_attr "update" "yes")
9730 (set_attr "indexed" "yes,no")])
9732 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9733 ;; needed for stack allocation, even if the user passes -mno-update.
9734 (define_insn "movdi_<mode>_update_stack"
9735 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9736 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9737 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9738 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9739 (plus:P (match_dup 1) (match_dup 2)))]
9740 "TARGET_POWERPC64"
9741 "@
9742 stdux %3,%0,%2
9743 stdu %3,%2(%0)"
9744 [(set_attr "type" "store")
9745 (set_attr "update" "yes")
9746 (set_attr "indexed" "yes,no")])
9748 (define_insn "*movsi_update1"
9749 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9750 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9751 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9752 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9753 (plus:SI (match_dup 1) (match_dup 2)))]
9754 "TARGET_UPDATE
9755 && (!avoiding_indexed_address_p (SImode)
9756 || !gpc_reg_operand (operands[2], SImode))"
9757 "@
9758 lwzux %3,%0,%2
9759 lwzu %3,%2(%0)"
9760 [(set_attr "type" "load")
9761 (set_attr "update" "yes")
9762 (set_attr "indexed" "yes,no")])
9764 (define_insn "*movsi_update2"
9765 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9766 (sign_extend:DI
9767 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9768 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9769 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9770 (plus:DI (match_dup 1) (match_dup 2)))]
9771 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9772 && !avoiding_indexed_address_p (DImode)"
9773 "lwaux %3,%0,%2"
9774 [(set_attr "type" "load")
9775 (set_attr "sign_extend" "yes")
9776 (set_attr "update" "yes")
9777 (set_attr "indexed" "yes")])
9779 (define_insn "movsi_update"
9780 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9781 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9782 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9783 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9784 (plus:SI (match_dup 1) (match_dup 2)))]
9785 "TARGET_UPDATE
9786 && (!avoiding_indexed_address_p (SImode)
9787 || !gpc_reg_operand (operands[2], SImode)
9788 || (REG_P (operands[0])
9789 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9790 "@
9791 stwux %3,%0,%2
9792 stwu %3,%2(%0)"
9793 [(set_attr "type" "store")
9794 (set_attr "update" "yes")
9795 (set_attr "indexed" "yes,no")])
9797 ;; This is an unconditional pattern; needed for stack allocation, even
9798 ;; if the user passes -mno-update.
9799 (define_insn "movsi_update_stack"
9800 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9801 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9802 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9803 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9804 (plus:SI (match_dup 1) (match_dup 2)))]
9805 ""
9806 "@
9807 stwux %3,%0,%2
9808 stwu %3,%2(%0)"
9809 [(set_attr "type" "store")
9810 (set_attr "update" "yes")
9811 (set_attr "indexed" "yes,no")])
9813 (define_insn "*movhi_update1"
9814 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9815 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9816 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9817 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9818 (plus:SI (match_dup 1) (match_dup 2)))]
9819 "TARGET_UPDATE
9820 && (!avoiding_indexed_address_p (SImode)
9821 || !gpc_reg_operand (operands[2], SImode))"
9822 "@
9823 lhzux %3,%0,%2
9824 lhzu %3,%2(%0)"
9825 [(set_attr "type" "load")
9826 (set_attr "update" "yes")
9827 (set_attr "indexed" "yes,no")])
9829 (define_insn "*movhi_update2"
9830 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9831 (zero_extend:SI
9832 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9833 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9834 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9835 (plus:SI (match_dup 1) (match_dup 2)))]
9836 "TARGET_UPDATE
9837 && (!avoiding_indexed_address_p (SImode)
9838 || !gpc_reg_operand (operands[2], SImode))"
9839 "@
9840 lhzux %3,%0,%2
9841 lhzu %3,%2(%0)"
9842 [(set_attr "type" "load")
9843 (set_attr "update" "yes")
9844 (set_attr "indexed" "yes,no")])
9846 (define_insn "*movhi_update3"
9847 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9848 (sign_extend:SI
9849 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9850 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9852 (plus:SI (match_dup 1) (match_dup 2)))]
9853 "TARGET_UPDATE && rs6000_gen_cell_microcode
9854 && (!avoiding_indexed_address_p (SImode)
9855 || !gpc_reg_operand (operands[2], SImode))"
9856 "@
9857 lhaux %3,%0,%2
9858 lhau %3,%2(%0)"
9859 [(set_attr "type" "load")
9860 (set_attr "sign_extend" "yes")
9861 (set_attr "update" "yes")
9862 (set_attr "indexed" "yes,no")])
9864 (define_insn "*movhi_update4"
9865 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9866 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9867 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9868 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9869 (plus:SI (match_dup 1) (match_dup 2)))]
9870 "TARGET_UPDATE
9871 && (!avoiding_indexed_address_p (SImode)
9872 || !gpc_reg_operand (operands[2], SImode))"
9873 "@
9874 sthux %3,%0,%2
9875 sthu %3,%2(%0)"
9876 [(set_attr "type" "store")
9877 (set_attr "update" "yes")
9878 (set_attr "indexed" "yes,no")])
9880 (define_insn "*movqi_update1"
9881 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9882 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9883 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9884 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9885 (plus:SI (match_dup 1) (match_dup 2)))]
9886 "TARGET_UPDATE
9887 && (!avoiding_indexed_address_p (SImode)
9888 || !gpc_reg_operand (operands[2], SImode))"
9889 "@
9890 lbzux %3,%0,%2
9891 lbzu %3,%2(%0)"
9892 [(set_attr "type" "load")
9893 (set_attr "update" "yes")
9894 (set_attr "indexed" "yes,no")])
9896 (define_insn "*movqi_update2"
9897 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9898 (zero_extend:SI
9899 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9900 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9901 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9902 (plus:SI (match_dup 1) (match_dup 2)))]
9903 "TARGET_UPDATE
9904 && (!avoiding_indexed_address_p (SImode)
9905 || !gpc_reg_operand (operands[2], SImode))"
9906 "@
9907 lbzux %3,%0,%2
9908 lbzu %3,%2(%0)"
9909 [(set_attr "type" "load")
9910 (set_attr "update" "yes")
9911 (set_attr "indexed" "yes,no")])
9913 (define_insn "*movqi_update3"
9914 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9915 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9916 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9917 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9918 (plus:SI (match_dup 1) (match_dup 2)))]
9919 "TARGET_UPDATE
9920 && (!avoiding_indexed_address_p (SImode)
9921 || !gpc_reg_operand (operands[2], SImode))"
9922 "@
9923 stbux %3,%0,%2
9924 stbu %3,%2(%0)"
9925 [(set_attr "type" "store")
9926 (set_attr "update" "yes")
9927 (set_attr "indexed" "yes,no")])
9929 (define_insn "*movsf_update1"
9930 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9931 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9932 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9933 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9934 (plus:SI (match_dup 1) (match_dup 2)))]
9935 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9936 && (!avoiding_indexed_address_p (SImode)
9937 || !gpc_reg_operand (operands[2], SImode))"
9938 "@
9939 lfsux %3,%0,%2
9940 lfsu %3,%2(%0)"
9941 [(set_attr "type" "fpload")
9942 (set_attr "update" "yes")
9943 (set_attr "indexed" "yes,no")])
9945 (define_insn "*movsf_update2"
9946 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9947 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9948 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9949 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9950 (plus:SI (match_dup 1) (match_dup 2)))]
9951 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9952 && (!avoiding_indexed_address_p (SImode)
9953 || !gpc_reg_operand (operands[2], SImode))"
9954 "@
9955 stfsux %3,%0,%2
9956 stfsu %3,%2(%0)"
9957 [(set_attr "type" "fpstore")
9958 (set_attr "update" "yes")
9959 (set_attr "indexed" "yes,no")])
9961 (define_insn "*movsf_update3"
9962 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9963 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9964 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9965 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9966 (plus:SI (match_dup 1) (match_dup 2)))]
9967 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9968 && (!avoiding_indexed_address_p (SImode)
9969 || !gpc_reg_operand (operands[2], SImode))"
9970 "@
9971 lwzux %3,%0,%2
9972 lwzu %3,%2(%0)"
9973 [(set_attr "type" "load")
9974 (set_attr "update" "yes")
9975 (set_attr "indexed" "yes,no")])
9977 (define_insn "*movsf_update4"
9978 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9979 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9980 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9981 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9982 (plus:SI (match_dup 1) (match_dup 2)))]
9983 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9984 && (!avoiding_indexed_address_p (SImode)
9985 || !gpc_reg_operand (operands[2], SImode))"
9986 "@
9987 stwux %3,%0,%2
9988 stwu %3,%2(%0)"
9989 [(set_attr "type" "store")
9990 (set_attr "update" "yes")
9991 (set_attr "indexed" "yes,no")])
9993 (define_insn "*movdf_update1"
9994 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9995 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9996 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9997 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9998 (plus:SI (match_dup 1) (match_dup 2)))]
9999 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10000 && (!avoiding_indexed_address_p (SImode)
10001 || !gpc_reg_operand (operands[2], SImode))"
10002 "@
10003 lfdux %3,%0,%2
10004 lfdu %3,%2(%0)"
10005 [(set_attr "type" "fpload")
10006 (set_attr "update" "yes")
10007 (set_attr "indexed" "yes,no")])
10009 (define_insn "*movdf_update2"
10010 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10011 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10012 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10013 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10014 (plus:SI (match_dup 1) (match_dup 2)))]
10015 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10016 && (!avoiding_indexed_address_p (SImode)
10017 || !gpc_reg_operand (operands[2], SImode))"
10018 "@
10019 stfdux %3,%0,%2
10020 stfdu %3,%2(%0)"
10021 [(set_attr "type" "fpstore")
10022 (set_attr "update" "yes")
10023 (set_attr "indexed" "yes,no")])
10026 ;; After inserting conditional returns we can sometimes have
10027 ;; unnecessary register moves. Unfortunately we cannot have a
10028 ;; modeless peephole here, because some single SImode sets have early
10029 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10030 ;; sequences, using get_attr_length here will smash the operands
10031 ;; array. Neither is there an early_cobbler_p predicate.
10032 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10033 ;; Also this optimization interferes with scalars going into
10034 ;; altivec registers (the code does reloading through the FPRs).
10035 (define_peephole2
10036 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10037 (match_operand:DF 1 "any_operand" ""))
10038 (set (match_operand:DF 2 "gpc_reg_operand" "")
10039 (match_dup 0))]
10040 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10041 && !TARGET_UPPER_REGS_DF
10042 && peep2_reg_dead_p (2, operands[0])"
10043 [(set (match_dup 2) (match_dup 1))])
10045 (define_peephole2
10046 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10047 (match_operand:SF 1 "any_operand" ""))
10048 (set (match_operand:SF 2 "gpc_reg_operand" "")
10049 (match_dup 0))]
10050 "!TARGET_UPPER_REGS_SF
10051 && peep2_reg_dead_p (2, operands[0])"
10052 [(set (match_dup 2) (match_dup 1))])
10054 \f
10055 ;; TLS support.
10057 ;; Mode attributes for different ABIs.
10058 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10059 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10060 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10061 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10063 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10064 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10065 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10066 (match_operand 4 "" "g")))
10067 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10068 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10069 UNSPEC_TLSGD)
10070 (clobber (reg:SI LR_REGNO))]
10071 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10072 {
10073 if (TARGET_CMODEL != CMODEL_SMALL)
10074 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10075 "bl %z3\;nop";
10076 else
10077 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10078 }
10079 "&& TARGET_TLS_MARKERS"
10080 [(set (match_dup 0)
10081 (unspec:TLSmode [(match_dup 1)
10082 (match_dup 2)]
10083 UNSPEC_TLSGD))
10084 (parallel [(set (match_dup 0)
10085 (call (mem:TLSmode (match_dup 3))
10086 (match_dup 4)))
10087 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10088 (clobber (reg:SI LR_REGNO))])]
10089 ""
10090 [(set_attr "type" "two")
10091 (set (attr "length")
10092 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10093 (const_int 16)
10094 (const_int 12)))])
10096 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10097 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10098 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10099 (match_operand 4 "" "g")))
10100 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10101 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10102 UNSPEC_TLSGD)
10103 (clobber (reg:SI LR_REGNO))]
10104 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10105 {
10106 if (flag_pic)
10107 {
10108 if (TARGET_SECURE_PLT && flag_pic == 2)
10109 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10110 else
10111 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10112 }
10113 else
10114 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10115 }
10116 "&& TARGET_TLS_MARKERS"
10117 [(set (match_dup 0)
10118 (unspec:TLSmode [(match_dup 1)
10119 (match_dup 2)]
10120 UNSPEC_TLSGD))
10121 (parallel [(set (match_dup 0)
10122 (call (mem:TLSmode (match_dup 3))
10123 (match_dup 4)))
10124 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10125 (clobber (reg:SI LR_REGNO))])]
10126 ""
10127 [(set_attr "type" "two")
10128 (set_attr "length" "8")])
10130 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10131 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10132 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10133 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10134 UNSPEC_TLSGD))]
10135 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10136 "addi %0,%1,%2@got@tlsgd"
10137 "&& TARGET_CMODEL != CMODEL_SMALL"
10138 [(set (match_dup 3)
10139 (high:TLSmode
10140 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10141 (set (match_dup 0)
10142 (lo_sum:TLSmode (match_dup 3)
10143 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
10144 "
10145 {
10146 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10147 }"
10148 [(set (attr "length")
10149 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10150 (const_int 8)
10151 (const_int 4)))])
10153 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10154 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10155 (high:TLSmode
10156 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10157 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10158 UNSPEC_TLSGD)))]
10159 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10160 "addis %0,%1,%2@got@tlsgd@ha"
10161 [(set_attr "length" "4")])
10163 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10164 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10165 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10166 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10167 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10168 UNSPEC_TLSGD)))]
10169 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10170 "addi %0,%1,%2@got@tlsgd@l"
10171 [(set_attr "length" "4")])
10173 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10174 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10175 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10176 (match_operand 2 "" "g")))
10177 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10178 UNSPEC_TLSGD)
10179 (clobber (reg:SI LR_REGNO))]
10180 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10181 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10182 "bl %z1(%3@tlsgd)\;nop"
10183 [(set_attr "type" "branch")
10184 (set_attr "length" "8")])
10186 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10188 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10189 (match_operand 2 "" "g")))
10190 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10191 UNSPEC_TLSGD)
10192 (clobber (reg:SI LR_REGNO))]
10193 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10194 {
10195 if (flag_pic)
10196 {
10197 if (TARGET_SECURE_PLT && flag_pic == 2)
10198 return "bl %z1+32768(%3@tlsgd)@plt";
10199 return "bl %z1(%3@tlsgd)@plt";
10200 }
10201 return "bl %z1(%3@tlsgd)";
10202 }
10203 [(set_attr "type" "branch")
10204 (set_attr "length" "4")])
10206 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10208 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10209 (match_operand 3 "" "g")))
10210 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10211 UNSPEC_TLSLD)
10212 (clobber (reg:SI LR_REGNO))]
10213 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10214 {
10215 if (TARGET_CMODEL != CMODEL_SMALL)
10216 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10217 "bl %z2\;nop";
10218 else
10219 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10220 }
10221 "&& TARGET_TLS_MARKERS"
10222 [(set (match_dup 0)
10223 (unspec:TLSmode [(match_dup 1)]
10224 UNSPEC_TLSLD))
10225 (parallel [(set (match_dup 0)
10226 (call (mem:TLSmode (match_dup 2))
10227 (match_dup 3)))
10228 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10229 (clobber (reg:SI LR_REGNO))])]
10230 ""
10231 [(set_attr "type" "two")
10232 (set (attr "length")
10233 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10234 (const_int 16)
10235 (const_int 12)))])
10237 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10238 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10239 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10240 (match_operand 3 "" "g")))
10241 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10242 UNSPEC_TLSLD)
10243 (clobber (reg:SI LR_REGNO))]
10244 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10245 {
10246 if (flag_pic)
10247 {
10248 if (TARGET_SECURE_PLT && flag_pic == 2)
10249 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10250 else
10251 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10252 }
10253 else
10254 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10255 }
10256 "&& TARGET_TLS_MARKERS"
10257 [(set (match_dup 0)
10258 (unspec:TLSmode [(match_dup 1)]
10259 UNSPEC_TLSLD))
10260 (parallel [(set (match_dup 0)
10261 (call (mem:TLSmode (match_dup 2))
10262 (match_dup 3)))
10263 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10264 (clobber (reg:SI LR_REGNO))])]
10265 ""
10266 [(set_attr "length" "8")])
10268 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10269 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10270 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10271 UNSPEC_TLSLD))]
10272 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10273 "addi %0,%1,%&@got@tlsld"
10274 "&& TARGET_CMODEL != CMODEL_SMALL"
10275 [(set (match_dup 2)
10276 (high:TLSmode
10277 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10278 (set (match_dup 0)
10279 (lo_sum:TLSmode (match_dup 2)
10280 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10281 "
10282 {
10283 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10284 }"
10285 [(set (attr "length")
10286 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10287 (const_int 8)
10288 (const_int 4)))])
10290 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10291 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10292 (high:TLSmode
10293 (unspec:TLSmode [(const_int 0)
10294 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10295 UNSPEC_TLSLD)))]
10296 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10297 "addis %0,%1,%&@got@tlsld@ha"
10298 [(set_attr "length" "4")])
10300 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10301 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10302 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10303 (unspec:TLSmode [(const_int 0)
10304 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10305 UNSPEC_TLSLD)))]
10306 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10307 "addi %0,%1,%&@got@tlsld@l"
10308 [(set_attr "length" "4")])
10310 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10311 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10312 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10313 (match_operand 2 "" "g")))
10314 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10315 (clobber (reg:SI LR_REGNO))]
10316 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10317 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10318 "bl %z1(%&@tlsld)\;nop"
10319 [(set_attr "type" "branch")
10320 (set_attr "length" "8")])
10322 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10323 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10324 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10325 (match_operand 2 "" "g")))
10326 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10327 (clobber (reg:SI LR_REGNO))]
10328 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10329 {
10330 if (flag_pic)
10331 {
10332 if (TARGET_SECURE_PLT && flag_pic == 2)
10333 return "bl %z1+32768(%&@tlsld)@plt";
10334 return "bl %z1(%&@tlsld)@plt";
10335 }
10336 return "bl %z1(%&@tlsld)";
10337 }
10338 [(set_attr "type" "branch")
10339 (set_attr "length" "4")])
10341 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10342 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10343 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10344 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10345 UNSPEC_TLSDTPREL))]
10346 "HAVE_AS_TLS"
10347 "addi %0,%1,%2@dtprel")
10349 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10350 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10351 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10352 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10353 UNSPEC_TLSDTPRELHA))]
10354 "HAVE_AS_TLS"
10355 "addis %0,%1,%2@dtprel@ha")
10357 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10358 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10359 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10360 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10361 UNSPEC_TLSDTPRELLO))]
10362 "HAVE_AS_TLS"
10363 "addi %0,%1,%2@dtprel@l")
10365 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10366 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10367 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10368 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10369 UNSPEC_TLSGOTDTPREL))]
10370 "HAVE_AS_TLS"
10371 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10372 "&& TARGET_CMODEL != CMODEL_SMALL"
10373 [(set (match_dup 3)
10374 (high:TLSmode
10375 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10376 (set (match_dup 0)
10377 (lo_sum:TLSmode (match_dup 3)
10378 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10379 "
10380 {
10381 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10382 }"
10383 [(set (attr "length")
10384 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10385 (const_int 8)
10386 (const_int 4)))])
10388 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10389 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10390 (high:TLSmode
10391 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10392 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10393 UNSPEC_TLSGOTDTPREL)))]
10394 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10395 "addis %0,%1,%2@got@dtprel@ha"
10396 [(set_attr "length" "4")])
10398 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10399 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10400 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10401 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10402 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10403 UNSPEC_TLSGOTDTPREL)))]
10404 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10405 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10406 [(set_attr "length" "4")])
10408 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10409 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10410 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10411 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10412 UNSPEC_TLSTPREL))]
10413 "HAVE_AS_TLS"
10414 "addi %0,%1,%2@tprel")
10416 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10417 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10418 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10419 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10420 UNSPEC_TLSTPRELHA))]
10421 "HAVE_AS_TLS"
10422 "addis %0,%1,%2@tprel@ha")
10424 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10425 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10426 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10427 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10428 UNSPEC_TLSTPRELLO))]
10429 "HAVE_AS_TLS"
10430 "addi %0,%1,%2@tprel@l")
10432 ;; "b" output constraint here and on tls_tls input to support linker tls
10433 ;; optimization. The linker may edit the instructions emitted by a
10434 ;; tls_got_tprel/tls_tls pair to addis,addi.
10435 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10436 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10437 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10438 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10439 UNSPEC_TLSGOTTPREL))]
10440 "HAVE_AS_TLS"
10441 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10442 "&& TARGET_CMODEL != CMODEL_SMALL"
10443 [(set (match_dup 3)
10444 (high:TLSmode
10445 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10446 (set (match_dup 0)
10447 (lo_sum:TLSmode (match_dup 3)
10448 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10449 "
10450 {
10451 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10452 }"
10453 [(set (attr "length")
10454 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10455 (const_int 8)
10456 (const_int 4)))])
10458 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10459 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10460 (high:TLSmode
10461 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10462 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10463 UNSPEC_TLSGOTTPREL)))]
10464 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10465 "addis %0,%1,%2@got@tprel@ha"
10466 [(set_attr "length" "4")])
10468 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10469 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10470 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10471 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10472 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10473 UNSPEC_TLSGOTTPREL)))]
10474 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10475 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10476 [(set_attr "length" "4")])
10478 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10479 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10480 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10481 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10482 UNSPEC_TLSTLS))]
10483 "TARGET_ELF && HAVE_AS_TLS"
10484 "add %0,%1,%2@tls")
10486 (define_expand "tls_get_tpointer"
10487 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10488 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10489 "TARGET_XCOFF && HAVE_AS_TLS"
10490 "
10491 {
10492 emit_insn (gen_tls_get_tpointer_internal ());
10493 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10494 DONE;
10495 }")
10497 (define_insn "tls_get_tpointer_internal"
10498 [(set (reg:SI 3)
10499 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10500 (clobber (reg:SI LR_REGNO))]
10501 "TARGET_XCOFF && HAVE_AS_TLS"
10502 "bla __get_tpointer")
10504 (define_expand "tls_get_addr<mode>"
10505 [(set (match_operand:P 0 "gpc_reg_operand" "")
10506 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10507 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10508 "TARGET_XCOFF && HAVE_AS_TLS"
10509 "
10510 {
10511 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10512 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10513 emit_insn (gen_tls_get_addr_internal<mode> ());
10514 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10515 DONE;
10516 }")
10518 (define_insn "tls_get_addr_internal<mode>"
10519 [(set (reg:P 3)
10520 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10521 (clobber (reg:P 0))
10522 (clobber (reg:P 4))
10523 (clobber (reg:P 5))
10524 (clobber (reg:P 11))
10525 (clobber (reg:CC CR0_REGNO))
10526 (clobber (reg:P LR_REGNO))]
10527 "TARGET_XCOFF && HAVE_AS_TLS"
10528 "bla __tls_get_addr")
10529 \f
10530 ;; Next come insns related to the calling sequence.
10531 ;;
10532 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10533 ;; We move the back-chain and decrement the stack pointer.
10535 (define_expand "allocate_stack"
10536 [(set (match_operand 0 "gpc_reg_operand" "")
10537 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10538 (set (reg 1)
10539 (minus (reg 1) (match_dup 1)))]
10540 ""
10541 "
10542 { rtx chain = gen_reg_rtx (Pmode);
10543 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10544 rtx neg_op0;
10545 rtx insn, par, set, mem;
10547 emit_move_insn (chain, stack_bot);
10549 /* Check stack bounds if necessary. */
10550 if (crtl->limit_stack)
10551 {
10552 rtx available;
10553 available = expand_binop (Pmode, sub_optab,
10554 stack_pointer_rtx, stack_limit_rtx,
10555 NULL_RTX, 1, OPTAB_WIDEN);
10556 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10557 }
10559 if (GET_CODE (operands[1]) != CONST_INT
10560 || INTVAL (operands[1]) < -32767
10561 || INTVAL (operands[1]) > 32768)
10562 {
10563 neg_op0 = gen_reg_rtx (Pmode);
10564 if (TARGET_32BIT)
10565 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10566 else
10567 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10568 }
10569 else
10570 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10572 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10573 : gen_movdi_di_update_stack))
10574 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10575 chain));
10576 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10577 it now and set the alias set/attributes. The above gen_*_update
10578 calls will generate a PARALLEL with the MEM set being the first
10579 operation. */
10580 par = PATTERN (insn);
10581 gcc_assert (GET_CODE (par) == PARALLEL);
10582 set = XVECEXP (par, 0, 0);
10583 gcc_assert (GET_CODE (set) == SET);
10584 mem = SET_DEST (set);
10585 gcc_assert (MEM_P (mem));
10586 MEM_NOTRAP_P (mem) = 1;
10587 set_mem_alias_set (mem, get_frame_alias_set ());
10589 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10590 DONE;
10591 }")
10593 ;; These patterns say how to save and restore the stack pointer. We need not
10594 ;; save the stack pointer at function level since we are careful to
10595 ;; preserve the backchain. At block level, we have to restore the backchain
10596 ;; when we restore the stack pointer.
10597 ;;
10598 ;; For nonlocal gotos, we must save both the stack pointer and its
10599 ;; backchain and restore both. Note that in the nonlocal case, the
10600 ;; save area is a memory location.
10602 (define_expand "save_stack_function"
10603 [(match_operand 0 "any_operand" "")
10604 (match_operand 1 "any_operand" "")]
10605 ""
10606 "DONE;")
10608 (define_expand "restore_stack_function"
10609 [(match_operand 0 "any_operand" "")
10610 (match_operand 1 "any_operand" "")]
10611 ""
10612 "DONE;")
10614 ;; Adjust stack pointer (op0) to a new value (op1).
10615 ;; First copy old stack backchain to new location, and ensure that the
10616 ;; scheduler won't reorder the sp assignment before the backchain write.
10617 (define_expand "restore_stack_block"
10618 [(set (match_dup 2) (match_dup 3))
10619 (set (match_dup 4) (match_dup 2))
10620 (match_dup 5)
10621 (set (match_operand 0 "register_operand" "")
10622 (match_operand 1 "register_operand" ""))]
10623 ""
10624 "
10625 {
10626 rtvec p;
10628 operands[1] = force_reg (Pmode, operands[1]);
10629 operands[2] = gen_reg_rtx (Pmode);
10630 operands[3] = gen_frame_mem (Pmode, operands[0]);
10631 operands[4] = gen_frame_mem (Pmode, operands[1]);
10632 p = rtvec_alloc (1);
10633 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10634 gen_frame_mem (BLKmode, operands[0]),
10635 const0_rtx);
10636 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10637 }")
10639 (define_expand "save_stack_nonlocal"
10640 [(set (match_dup 3) (match_dup 4))
10641 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10642 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10643 ""
10644 "
10645 {
10646 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10648 /* Copy the backchain to the first word, sp to the second. */
10649 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10650 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10651 operands[3] = gen_reg_rtx (Pmode);
10652 operands[4] = gen_frame_mem (Pmode, operands[1]);
10653 }")
10655 (define_expand "restore_stack_nonlocal"
10656 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10657 (set (match_dup 3) (match_dup 4))
10658 (set (match_dup 5) (match_dup 2))
10659 (match_dup 6)
10660 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10661 ""
10662 "
10663 {
10664 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10665 rtvec p;
10667 /* Restore the backchain from the first word, sp from the second. */
10668 operands[2] = gen_reg_rtx (Pmode);
10669 operands[3] = gen_reg_rtx (Pmode);
10670 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10671 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10672 operands[5] = gen_frame_mem (Pmode, operands[3]);
10673 p = rtvec_alloc (1);
10674 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10675 gen_frame_mem (BLKmode, operands[0]),
10676 const0_rtx);
10677 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10678 }")
10679 \f
10680 ;; TOC register handling.
10682 ;; Code to initialize the TOC register...
10684 (define_insn "load_toc_aix_si"
10685 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10686 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10687 (use (reg:SI 2))])]
10688 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10689 "*
10690 {
10691 char buf[30];
10692 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10693 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10694 operands[2] = gen_rtx_REG (Pmode, 2);
10695 return \"lwz %0,%1(%2)\";
10696 }"
10697 [(set_attr "type" "load")
10698 (set_attr "update" "no")
10699 (set_attr "indexed" "no")])
10701 (define_insn "load_toc_aix_di"
10702 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10703 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10704 (use (reg:DI 2))])]
10705 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10706 "*
10707 {
10708 char buf[30];
10709 #ifdef TARGET_RELOCATABLE
10710 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10711 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10712 #else
10713 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10714 #endif
10715 if (TARGET_ELF)
10716 strcat (buf, \"@toc\");
10717 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10718 operands[2] = gen_rtx_REG (Pmode, 2);
10719 return \"ld %0,%1(%2)\";
10720 }"
10721 [(set_attr "type" "load")
10722 (set_attr "update" "no")
10723 (set_attr "indexed" "no")])
10725 (define_insn "load_toc_v4_pic_si"
10726 [(set (reg:SI LR_REGNO)
10727 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10728 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10729 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10730 [(set_attr "type" "branch")
10731 (set_attr "length" "4")])
10733 (define_expand "load_toc_v4_PIC_1"
10734 [(parallel [(set (reg:SI LR_REGNO)
10735 (match_operand:SI 0 "immediate_operand" "s"))
10736 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10737 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10738 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10739 "")
10741 (define_insn "load_toc_v4_PIC_1_normal"
10742 [(set (reg:SI LR_REGNO)
10743 (match_operand:SI 0 "immediate_operand" "s"))
10744 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10745 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10746 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10747 "bcl 20,31,%0\\n%0:"
10748 [(set_attr "type" "branch")
10749 (set_attr "length" "4")])
10751 (define_insn "load_toc_v4_PIC_1_476"
10752 [(set (reg:SI LR_REGNO)
10753 (match_operand:SI 0 "immediate_operand" "s"))
10754 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10755 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10756 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10757 "*
10758 {
10759 char name[32];
10760 static char templ[32];
10762 get_ppc476_thunk_name (name);
10763 sprintf (templ, \"bl %s\\n%%0:\", name);
10764 return templ;
10765 }"
10766 [(set_attr "type" "branch")
10767 (set_attr "length" "4")])
10769 (define_expand "load_toc_v4_PIC_1b"
10770 [(parallel [(set (reg:SI LR_REGNO)
10771 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10772 (label_ref (match_operand 1 "" ""))]
10773 UNSPEC_TOCPTR))
10774 (match_dup 1)])]
10775 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10776 "")
10778 (define_insn "load_toc_v4_PIC_1b_normal"
10779 [(set (reg:SI LR_REGNO)
10780 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10781 (label_ref (match_operand 1 "" ""))]
10782 UNSPEC_TOCPTR))
10783 (match_dup 1)]
10784 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10785 "bcl 20,31,$+8\;.long %0-$"
10786 [(set_attr "type" "branch")
10787 (set_attr "length" "8")])
10789 (define_insn "load_toc_v4_PIC_1b_476"
10790 [(set (reg:SI LR_REGNO)
10791 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10792 (label_ref (match_operand 1 "" ""))]
10793 UNSPEC_TOCPTR))
10794 (match_dup 1)]
10795 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10796 "*
10797 {
10798 char name[32];
10799 static char templ[32];
10801 get_ppc476_thunk_name (name);
10802 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10803 return templ;
10804 }"
10805 [(set_attr "type" "branch")
10806 (set_attr "length" "16")])
10808 (define_insn "load_toc_v4_PIC_2"
10809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10810 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10811 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10812 (match_operand:SI 3 "immediate_operand" "s")))))]
10813 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10814 "lwz %0,%2-%3(%1)"
10815 [(set_attr "type" "load")])
10817 (define_insn "load_toc_v4_PIC_3b"
10818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10819 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10820 (high:SI
10821 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10822 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10823 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10824 "addis %0,%1,%2-%3@ha")
10826 (define_insn "load_toc_v4_PIC_3c"
10827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10828 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10829 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10830 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10831 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10832 "addi %0,%1,%2-%3@l")
10834 ;; If the TOC is shared over a translation unit, as happens with all
10835 ;; the kinds of PIC that we support, we need to restore the TOC
10836 ;; pointer only when jumping over units of translation.
10837 ;; On Darwin, we need to reload the picbase.
10839 (define_expand "builtin_setjmp_receiver"
10840 [(use (label_ref (match_operand 0 "" "")))]
10841 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10842 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10843 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10844 "
10845 {
10846 #if TARGET_MACHO
10847 if (DEFAULT_ABI == ABI_DARWIN)
10848 {
10849 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10850 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10851 rtx tmplabrtx;
10852 char tmplab[20];
10854 crtl->uses_pic_offset_table = 1;
10855 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10856 CODE_LABEL_NUMBER (operands[0]));
10857 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10859 emit_insn (gen_load_macho_picbase (tmplabrtx));
10860 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10861 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10862 }
10863 else
10864 #endif
10865 rs6000_emit_load_toc_table (FALSE);
10866 DONE;
10867 }")
10869 ;; Largetoc support
10870 (define_insn "*largetoc_high"
10871 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10872 (high:DI
10873 (unspec [(match_operand:DI 1 "" "")
10874 (match_operand:DI 2 "gpc_reg_operand" "b")]
10875 UNSPEC_TOCREL)))]
10876 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10877 "addis %0,%2,%1@toc@ha")
10879 (define_insn "*largetoc_high_aix<mode>"
10880 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10881 (high:P
10882 (unspec [(match_operand:P 1 "" "")
10883 (match_operand:P 2 "gpc_reg_operand" "b")]
10884 UNSPEC_TOCREL)))]
10885 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10886 "addis %0,%1@u(%2)")
10888 (define_insn "*largetoc_high_plus"
10889 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10890 (high:DI
10891 (plus:DI
10892 (unspec [(match_operand:DI 1 "" "")
10893 (match_operand:DI 2 "gpc_reg_operand" "b")]
10894 UNSPEC_TOCREL)
10895 (match_operand:DI 3 "add_cint_operand" "n"))))]
10896 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10897 "addis %0,%2,%1+%3@toc@ha")
10899 (define_insn "*largetoc_high_plus_aix<mode>"
10900 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10901 (high:P
10902 (plus:P
10903 (unspec [(match_operand:P 1 "" "")
10904 (match_operand:P 2 "gpc_reg_operand" "b")]
10905 UNSPEC_TOCREL)
10906 (match_operand:P 3 "add_cint_operand" "n"))))]
10907 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10908 "addis %0,%1+%3@u(%2)")
10910 (define_insn "*largetoc_low"
10911 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10912 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
10913 (match_operand:DI 2 "" "")))]
10914 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10915 "addi %0,%1,%2@l")
10917 (define_insn "*largetoc_low_aix<mode>"
10918 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10919 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10920 (match_operand:P 2 "" "")))]
10921 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10922 "la %0,%2@l(%1)")
10924 (define_insn_and_split "*tocref<mode>"
10925 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
10926 (match_operand:P 1 "small_toc_ref" "R"))]
10927 "TARGET_TOC"
10928 "la %0,%a1"
10929 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10930 [(set (match_dup 0) (high:P (match_dup 1)))
10931 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10933 ;; Elf specific ways of loading addresses for non-PIC code.
10934 ;; The output of this could be r0, but we make a very strong
10935 ;; preference for a base register because it will usually
10936 ;; be needed there.
10937 (define_insn "elf_high"
10938 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10939 (high:SI (match_operand 1 "" "")))]
10940 "TARGET_ELF && ! TARGET_64BIT"
10941 "lis %0,%1@ha")
10943 (define_insn "elf_low"
10944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10945 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10946 (match_operand 2 "" "")))]
10947 "TARGET_ELF && ! TARGET_64BIT"
10948 "la %0,%2@l(%1)")
10949 \f
10950 ;; Call and call_value insns
10951 (define_expand "call"
10952 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10953 (match_operand 1 "" ""))
10954 (use (match_operand 2 "" ""))
10955 (clobber (reg:SI LR_REGNO))])]
10956 ""
10957 "
10958 {
10959 #if TARGET_MACHO
10960 if (MACHOPIC_INDIRECT)
10961 operands[0] = machopic_indirect_call_target (operands[0]);
10962 #endif
10964 gcc_assert (GET_CODE (operands[0]) == MEM);
10965 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10967 operands[0] = XEXP (operands[0], 0);
10969 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10970 {
10971 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10972 DONE;
10973 }
10975 if (GET_CODE (operands[0]) != SYMBOL_REF
10976 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10977 {
10978 if (INTVAL (operands[2]) & CALL_LONG)
10979 operands[0] = rs6000_longcall_ref (operands[0]);
10981 switch (DEFAULT_ABI)
10982 {
10983 case ABI_V4:
10984 case ABI_DARWIN:
10985 operands[0] = force_reg (Pmode, operands[0]);
10986 break;
10988 default:
10989 gcc_unreachable ();
10990 }
10991 }
10992 }")
10994 (define_expand "call_value"
10995 [(parallel [(set (match_operand 0 "" "")
10996 (call (mem:SI (match_operand 1 "address_operand" ""))
10997 (match_operand 2 "" "")))
10998 (use (match_operand 3 "" ""))
10999 (clobber (reg:SI LR_REGNO))])]
11000 ""
11001 "
11002 {
11003 #if TARGET_MACHO
11004 if (MACHOPIC_INDIRECT)
11005 operands[1] = machopic_indirect_call_target (operands[1]);
11006 #endif
11008 gcc_assert (GET_CODE (operands[1]) == MEM);
11009 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11011 operands[1] = XEXP (operands[1], 0);
11013 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11014 {
11015 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
11016 DONE;
11017 }
11019 if (GET_CODE (operands[1]) != SYMBOL_REF
11020 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11021 {
11022 if (INTVAL (operands[3]) & CALL_LONG)
11023 operands[1] = rs6000_longcall_ref (operands[1]);
11025 switch (DEFAULT_ABI)
11026 {
11027 case ABI_V4:
11028 case ABI_DARWIN:
11029 operands[1] = force_reg (Pmode, operands[1]);
11030 break;
11032 default:
11033 gcc_unreachable ();
11034 }
11035 }
11036 }")
11038 ;; Call to function in current module. No TOC pointer reload needed.
11039 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11040 ;; either the function was not prototyped, or it was prototyped as a
11041 ;; variable argument function. It is > 0 if FP registers were passed
11042 ;; and < 0 if they were not.
11044 (define_insn "*call_local32"
11045 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11046 (match_operand 1 "" "g,g"))
11047 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11048 (clobber (reg:SI LR_REGNO))]
11049 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11050 "*
11051 {
11052 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11053 output_asm_insn (\"crxor 6,6,6\", operands);
11055 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11056 output_asm_insn (\"creqv 6,6,6\", operands);
11058 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11059 }"
11060 [(set_attr "type" "branch")
11061 (set_attr "length" "4,8")])
11063 (define_insn "*call_local64"
11064 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11065 (match_operand 1 "" "g,g"))
11066 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11067 (clobber (reg:SI LR_REGNO))]
11068 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11069 "*
11070 {
11071 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11072 output_asm_insn (\"crxor 6,6,6\", operands);
11074 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11075 output_asm_insn (\"creqv 6,6,6\", operands);
11077 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11078 }"
11079 [(set_attr "type" "branch")
11080 (set_attr "length" "4,8")])
11082 (define_insn "*call_value_local32"
11083 [(set (match_operand 0 "" "")
11084 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11085 (match_operand 2 "" "g,g")))
11086 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11087 (clobber (reg:SI LR_REGNO))]
11088 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11089 "*
11090 {
11091 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11092 output_asm_insn (\"crxor 6,6,6\", operands);
11094 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11095 output_asm_insn (\"creqv 6,6,6\", operands);
11097 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11098 }"
11099 [(set_attr "type" "branch")
11100 (set_attr "length" "4,8")])
11103 (define_insn "*call_value_local64"
11104 [(set (match_operand 0 "" "")
11105 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11106 (match_operand 2 "" "g,g")))
11107 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11108 (clobber (reg:SI LR_REGNO))]
11109 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11110 "*
11111 {
11112 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11113 output_asm_insn (\"crxor 6,6,6\", operands);
11115 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11116 output_asm_insn (\"creqv 6,6,6\", operands);
11118 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11119 }"
11120 [(set_attr "type" "branch")
11121 (set_attr "length" "4,8")])
11124 ;; A function pointer under System V is just a normal pointer
11125 ;; operands[0] is the function pointer
11126 ;; operands[1] is the stack size to clean up
11127 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11128 ;; which indicates how to set cr1
11130 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11131 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11132 (match_operand 1 "" "g,g,g,g"))
11133 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11134 (clobber (reg:SI LR_REGNO))]
11135 "DEFAULT_ABI == ABI_V4
11136 || DEFAULT_ABI == ABI_DARWIN"
11137 {
11138 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11139 output_asm_insn ("crxor 6,6,6", operands);
11141 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11142 output_asm_insn ("creqv 6,6,6", operands);
11144 return "b%T0l";
11145 }
11146 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11147 (set_attr "length" "4,4,8,8")])
11149 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11150 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11151 (match_operand 1 "" "g,g"))
11152 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11153 (clobber (reg:SI LR_REGNO))]
11154 "(DEFAULT_ABI == ABI_DARWIN
11155 || (DEFAULT_ABI == ABI_V4
11156 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11157 {
11158 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11159 output_asm_insn ("crxor 6,6,6", operands);
11161 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11162 output_asm_insn ("creqv 6,6,6", operands);
11164 #if TARGET_MACHO
11165 return output_call(insn, operands, 0, 2);
11166 #else
11167 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11168 {
11169 gcc_assert (!TARGET_SECURE_PLT);
11170 return "bl %z0@plt";
11171 }
11172 else
11173 return "bl %z0";
11174 #endif
11175 }
11176 "DEFAULT_ABI == ABI_V4
11177 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11178 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11179 [(parallel [(call (mem:SI (match_dup 0))
11180 (match_dup 1))
11181 (use (match_dup 2))
11182 (use (match_dup 3))
11183 (clobber (reg:SI LR_REGNO))])]
11184 {
11185 operands[3] = pic_offset_table_rtx;
11186 }
11187 [(set_attr "type" "branch,branch")
11188 (set_attr "length" "4,8")])
11190 (define_insn "*call_nonlocal_sysv_secure<mode>"
11191 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11192 (match_operand 1 "" "g,g"))
11193 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11194 (use (match_operand:SI 3 "register_operand" "r,r"))
11195 (clobber (reg:SI LR_REGNO))]
11196 "(DEFAULT_ABI == ABI_V4
11197 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11198 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11199 {
11200 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11201 output_asm_insn ("crxor 6,6,6", operands);
11203 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11204 output_asm_insn ("creqv 6,6,6", operands);
11206 if (flag_pic == 2)
11207 /* The magic 32768 offset here and in the other sysv call insns
11208 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11209 See sysv4.h:toc_section. */
11210 return "bl %z0+32768@plt";
11211 else
11212 return "bl %z0@plt";
11213 }
11214 [(set_attr "type" "branch,branch")
11215 (set_attr "length" "4,8")])
11217 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11218 [(set (match_operand 0 "" "")
11219 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11220 (match_operand 2 "" "g,g,g,g")))
11221 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11222 (clobber (reg:SI LR_REGNO))]
11223 "DEFAULT_ABI == ABI_V4
11224 || DEFAULT_ABI == ABI_DARWIN"
11225 {
11226 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11227 output_asm_insn ("crxor 6,6,6", operands);
11229 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11230 output_asm_insn ("creqv 6,6,6", operands);
11232 return "b%T1l";
11233 }
11234 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11235 (set_attr "length" "4,4,8,8")])
11237 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11238 [(set (match_operand 0 "" "")
11239 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11240 (match_operand 2 "" "g,g")))
11241 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11242 (clobber (reg:SI LR_REGNO))]
11243 "(DEFAULT_ABI == ABI_DARWIN
11244 || (DEFAULT_ABI == ABI_V4
11245 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11246 {
11247 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11248 output_asm_insn ("crxor 6,6,6", operands);
11250 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11251 output_asm_insn ("creqv 6,6,6", operands);
11253 #if TARGET_MACHO
11254 return output_call(insn, operands, 1, 3);
11255 #else
11256 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11257 {
11258 gcc_assert (!TARGET_SECURE_PLT);
11259 return "bl %z1@plt";
11260 }
11261 else
11262 return "bl %z1";
11263 #endif
11264 }
11265 "DEFAULT_ABI == ABI_V4
11266 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11267 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11268 [(parallel [(set (match_dup 0)
11269 (call (mem:SI (match_dup 1))
11270 (match_dup 2)))
11271 (use (match_dup 3))
11272 (use (match_dup 4))
11273 (clobber (reg:SI LR_REGNO))])]
11274 {
11275 operands[4] = pic_offset_table_rtx;
11276 }
11277 [(set_attr "type" "branch,branch")
11278 (set_attr "length" "4,8")])
11280 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11281 [(set (match_operand 0 "" "")
11282 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11283 (match_operand 2 "" "g,g")))
11284 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11285 (use (match_operand:SI 4 "register_operand" "r,r"))
11286 (clobber (reg:SI LR_REGNO))]
11287 "(DEFAULT_ABI == ABI_V4
11288 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11289 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11290 {
11291 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11292 output_asm_insn ("crxor 6,6,6", operands);
11294 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11295 output_asm_insn ("creqv 6,6,6", operands);
11297 if (flag_pic == 2)
11298 return "bl %z1+32768@plt";
11299 else
11300 return "bl %z1@plt";
11301 }
11302 [(set_attr "type" "branch,branch")
11303 (set_attr "length" "4,8")])
11306 ;; Call to AIX abi function in the same module.
11308 (define_insn "*call_local_aix<mode>"
11309 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11310 (match_operand 1 "" "g"))
11311 (clobber (reg:P LR_REGNO))]
11312 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11313 "bl %z0"
11314 [(set_attr "type" "branch")
11315 (set_attr "length" "4")])
11317 (define_insn "*call_value_local_aix<mode>"
11318 [(set (match_operand 0 "" "")
11319 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11320 (match_operand 2 "" "g")))
11321 (clobber (reg:P LR_REGNO))]
11322 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11323 "bl %z1"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4")])
11327 ;; Call to AIX abi function which may be in another module.
11328 ;; Restore the TOC pointer (r2) after the call.
11330 (define_insn "*call_nonlocal_aix<mode>"
11331 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11332 (match_operand 1 "" "g"))
11333 (clobber (reg:P LR_REGNO))]
11334 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11335 "bl %z0\;nop"
11336 [(set_attr "type" "branch")
11337 (set_attr "length" "8")])
11339 (define_insn "*call_value_nonlocal_aix<mode>"
11340 [(set (match_operand 0 "" "")
11341 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11342 (match_operand 2 "" "g")))
11343 (clobber (reg:P LR_REGNO))]
11344 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11345 "bl %z1\;nop"
11346 [(set_attr "type" "branch")
11347 (set_attr "length" "8")])
11349 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11350 ;; Operand0 is the addresss of the function to call
11351 ;; Operand2 is the location in the function descriptor to load r2 from
11352 ;; Operand3 is the offset of the stack location holding the current TOC pointer
11354 (define_insn "*call_indirect_aix<mode>"
11355 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11356 (match_operand 1 "" "g,g"))
11357 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11358 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 3 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
11359 (clobber (reg:P LR_REGNO))]
11360 "DEFAULT_ABI == ABI_AIX"
11361 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3(1)"
11362 [(set_attr "type" "jmpreg")
11363 (set_attr "length" "12")])
11365 (define_insn "*call_value_indirect_aix<mode>"
11366 [(set (match_operand 0 "" "")
11367 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11368 (match_operand 2 "" "g,g")))
11369 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11370 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 4 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
11371 (clobber (reg:P LR_REGNO))]
11372 "DEFAULT_ABI == ABI_AIX"
11373 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4(1)"
11374 [(set_attr "type" "jmpreg")
11375 (set_attr "length" "12")])
11377 ;; Call to indirect functions with the ELFv2 ABI.
11378 ;; Operand0 is the addresss of the function to call
11379 ;; Operand2 is the offset of the stack location holding the current TOC pointer
11381 (define_insn "*call_indirect_elfv2<mode>"
11382 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11383 (match_operand 1 "" "g,g"))
11384 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 2 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
11385 (clobber (reg:P LR_REGNO))]
11386 "DEFAULT_ABI == ABI_ELFv2"
11387 "b%T0l\;<ptrload> 2,%2(1)"
11388 [(set_attr "type" "jmpreg")
11389 (set_attr "length" "8")])
11391 (define_insn "*call_value_indirect_elfv2<mode>"
11392 [(set (match_operand 0 "" "")
11393 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11394 (match_operand 2 "" "g,g")))
11395 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 3 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
11396 (clobber (reg:P LR_REGNO))]
11397 "DEFAULT_ABI == ABI_ELFv2"
11398 "b%T1l\;<ptrload> 2,%3(1)"
11399 [(set_attr "type" "jmpreg")
11400 (set_attr "length" "8")])
11403 ;; Call subroutine returning any type.
11404 (define_expand "untyped_call"
11405 [(parallel [(call (match_operand 0 "" "")
11406 (const_int 0))
11407 (match_operand 1 "" "")
11408 (match_operand 2 "" "")])]
11409 ""
11410 "
11411 {
11412 int i;
11414 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11416 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11417 {
11418 rtx set = XVECEXP (operands[2], 0, i);
11419 emit_move_insn (SET_DEST (set), SET_SRC (set));
11420 }
11422 /* The optimizer does not know that the call sets the function value
11423 registers we stored in the result block. We avoid problems by
11424 claiming that all hard registers are used and clobbered at this
11425 point. */
11426 emit_insn (gen_blockage ());
11428 DONE;
11429 }")
11431 ;; sibling call patterns
11432 (define_expand "sibcall"
11433 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11434 (match_operand 1 "" ""))
11435 (use (match_operand 2 "" ""))
11436 (use (reg:SI LR_REGNO))
11437 (simple_return)])]
11438 ""
11439 "
11440 {
11441 #if TARGET_MACHO
11442 if (MACHOPIC_INDIRECT)
11443 operands[0] = machopic_indirect_call_target (operands[0]);
11444 #endif
11446 gcc_assert (GET_CODE (operands[0]) == MEM);
11447 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11449 operands[0] = XEXP (operands[0], 0);
11451 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11452 {
11453 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11454 DONE;
11455 }
11456 }")
11458 (define_expand "sibcall_value"
11459 [(parallel [(set (match_operand 0 "register_operand" "")
11460 (call (mem:SI (match_operand 1 "address_operand" ""))
11461 (match_operand 2 "" "")))
11462 (use (match_operand 3 "" ""))
11463 (use (reg:SI LR_REGNO))
11464 (simple_return)])]
11465 ""
11466 "
11467 {
11468 #if TARGET_MACHO
11469 if (MACHOPIC_INDIRECT)
11470 operands[1] = machopic_indirect_call_target (operands[1]);
11471 #endif
11473 gcc_assert (GET_CODE (operands[1]) == MEM);
11474 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11476 operands[1] = XEXP (operands[1], 0);
11478 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11479 {
11480 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11481 DONE;
11482 }
11483 }")
11485 ;; this and similar patterns must be marked as using LR, otherwise
11486 ;; dataflow will try to delete the store into it. This is true
11487 ;; even when the actual reg to jump to is in CTR, when LR was
11488 ;; saved and restored around the PIC-setting BCL.
11489 (define_insn "*sibcall_local32"
11490 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11491 (match_operand 1 "" "g,g"))
11492 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11493 (use (reg:SI LR_REGNO))
11494 (simple_return)]
11495 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11496 "*
11497 {
11498 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11499 output_asm_insn (\"crxor 6,6,6\", operands);
11501 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11502 output_asm_insn (\"creqv 6,6,6\", operands);
11504 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11505 }"
11506 [(set_attr "type" "branch")
11507 (set_attr "length" "4,8")])
11509 (define_insn "*sibcall_local64"
11510 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11511 (match_operand 1 "" "g,g"))
11512 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11513 (use (reg:SI LR_REGNO))
11514 (simple_return)]
11515 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11516 "*
11517 {
11518 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11519 output_asm_insn (\"crxor 6,6,6\", operands);
11521 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11522 output_asm_insn (\"creqv 6,6,6\", operands);
11524 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11525 }"
11526 [(set_attr "type" "branch")
11527 (set_attr "length" "4,8")])
11529 (define_insn "*sibcall_value_local32"
11530 [(set (match_operand 0 "" "")
11531 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11532 (match_operand 2 "" "g,g")))
11533 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11534 (use (reg:SI LR_REGNO))
11535 (simple_return)]
11536 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11537 "*
11538 {
11539 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11540 output_asm_insn (\"crxor 6,6,6\", operands);
11542 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11543 output_asm_insn (\"creqv 6,6,6\", operands);
11545 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11546 }"
11547 [(set_attr "type" "branch")
11548 (set_attr "length" "4,8")])
11550 (define_insn "*sibcall_value_local64"
11551 [(set (match_operand 0 "" "")
11552 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11553 (match_operand 2 "" "g,g")))
11554 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11555 (use (reg:SI LR_REGNO))
11556 (simple_return)]
11557 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11558 "*
11559 {
11560 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11561 output_asm_insn (\"crxor 6,6,6\", operands);
11563 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11564 output_asm_insn (\"creqv 6,6,6\", operands);
11566 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11567 }"
11568 [(set_attr "type" "branch")
11569 (set_attr "length" "4,8")])
11571 (define_insn "*sibcall_nonlocal_sysv<mode>"
11572 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11573 (match_operand 1 "" ""))
11574 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11575 (use (reg:SI LR_REGNO))
11576 (simple_return)]
11577 "(DEFAULT_ABI == ABI_DARWIN
11578 || DEFAULT_ABI == ABI_V4)
11579 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11580 "*
11581 {
11582 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11583 output_asm_insn (\"crxor 6,6,6\", operands);
11585 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11586 output_asm_insn (\"creqv 6,6,6\", operands);
11588 if (which_alternative >= 2)
11589 return \"b%T0\";
11590 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11591 {
11592 gcc_assert (!TARGET_SECURE_PLT);
11593 return \"b %z0@plt\";
11594 }
11595 else
11596 return \"b %z0\";
11597 }"
11598 [(set_attr "type" "branch")
11599 (set_attr "length" "4,8,4,8")])
11601 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11602 [(set (match_operand 0 "" "")
11603 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11604 (match_operand 2 "" "")))
11605 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11606 (use (reg:SI LR_REGNO))
11607 (simple_return)]
11608 "(DEFAULT_ABI == ABI_DARWIN
11609 || DEFAULT_ABI == ABI_V4)
11610 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11611 "*
11612 {
11613 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11614 output_asm_insn (\"crxor 6,6,6\", operands);
11616 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11617 output_asm_insn (\"creqv 6,6,6\", operands);
11619 if (which_alternative >= 2)
11620 return \"b%T1\";
11621 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11622 {
11623 gcc_assert (!TARGET_SECURE_PLT);
11624 return \"b %z1@plt\";
11625 }
11626 else
11627 return \"b %z1\";
11628 }"
11629 [(set_attr "type" "branch")
11630 (set_attr "length" "4,8,4,8")])
11632 ;; AIX ABI sibling call patterns.
11634 (define_insn "*sibcall_aix<mode>"
11635 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11636 (match_operand 1 "" "g,g"))
11637 (simple_return)]
11638 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11639 "@
11640 b %z0
11641 b%T0"
11642 [(set_attr "type" "branch")
11643 (set_attr "length" "4")])
11645 (define_insn "*sibcall_value_aix<mode>"
11646 [(set (match_operand 0 "" "")
11647 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11648 (match_operand 2 "" "g,g")))
11649 (simple_return)]
11650 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11651 "@
11652 b %z1
11653 b%T1"
11654 [(set_attr "type" "branch")
11655 (set_attr "length" "4")])
11657 (define_expand "sibcall_epilogue"
11658 [(use (const_int 0))]
11659 ""
11660 {
11661 if (!TARGET_SCHED_PROLOG)
11662 emit_insn (gen_blockage ());
11663 rs6000_emit_epilogue (TRUE);
11664 DONE;
11665 })
11667 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11668 ;; all of memory. This blocks insns from being moved across this point.
11670 (define_insn "blockage"
11671 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11672 ""
11673 "")
11675 (define_expand "probe_stack_address"
11676 [(use (match_operand 0 "address_operand"))]
11677 ""
11678 {
11679 operands[0] = gen_rtx_MEM (Pmode, operands[0]);
11680 MEM_VOLATILE_P (operands[0]) = 1;
11682 if (TARGET_64BIT)
11683 emit_insn (gen_probe_stack_di (operands[0]));
11684 else
11685 emit_insn (gen_probe_stack_si (operands[0]));
11686 DONE;
11687 })
11689 (define_insn "probe_stack_<mode>"
11690 [(set (match_operand:P 0 "memory_operand" "=m")
11691 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11692 ""
11693 {
11694 operands[1] = gen_rtx_REG (Pmode, 0);
11695 return "st<wd>%U0%X0 %1,%0";
11696 }
11697 [(set_attr "type" "store")
11698 (set (attr "update")
11699 (if_then_else (match_operand 0 "update_address_mem")
11700 (const_string "yes")
11701 (const_string "no")))
11702 (set (attr "indexed")
11703 (if_then_else (match_operand 0 "indexed_address_mem")
11704 (const_string "yes")
11705 (const_string "no")))
11706 (set_attr "length" "4")])
11708 (define_insn "probe_stack_range<P:mode>"
11709 [(set (match_operand:P 0 "register_operand" "=r")
11710 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11711 (match_operand:P 2 "register_operand" "r")]
11712 UNSPECV_PROBE_STACK_RANGE))]
11713 ""
11714 "* return output_probe_stack_range (operands[0], operands[2]);"
11715 [(set_attr "type" "three")])
11716 \f
11717 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11718 ;; signed & unsigned, and one type of branch.
11719 ;;
11720 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11721 ;; insns, and branches.
11723 (define_expand "cbranch<mode>4"
11724 [(use (match_operator 0 "rs6000_cbranch_operator"
11725 [(match_operand:GPR 1 "gpc_reg_operand" "")
11726 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11727 (use (match_operand 3 ""))]
11728 ""
11729 "
11730 {
11731 /* Take care of the possibility that operands[2] might be negative but
11732 this might be a logical operation. That insn doesn't exist. */
11733 if (GET_CODE (operands[2]) == CONST_INT
11734 && INTVAL (operands[2]) < 0)
11735 {
11736 operands[2] = force_reg (<MODE>mode, operands[2]);
11737 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11738 GET_MODE (operands[0]),
11739 operands[1], operands[2]);
11740 }
11742 rs6000_emit_cbranch (<MODE>mode, operands);
11743 DONE;
11744 }")
11746 (define_expand "cbranch<mode>4"
11747 [(use (match_operator 0 "rs6000_cbranch_operator"
11748 [(match_operand:FP 1 "gpc_reg_operand" "")
11749 (match_operand:FP 2 "gpc_reg_operand" "")]))
11750 (use (match_operand 3 ""))]
11751 ""
11752 "
11753 {
11754 rs6000_emit_cbranch (<MODE>mode, operands);
11755 DONE;
11756 }")
11758 (define_expand "cstore<mode>4_unsigned"
11759 [(use (match_operator 1 "unsigned_comparison_operator"
11760 [(match_operand:P 2 "gpc_reg_operand" "")
11761 (match_operand:P 3 "reg_or_short_operand" "")]))
11762 (clobber (match_operand:P 0 "register_operand"))]
11763 ""
11764 {
11765 enum rtx_code cond_code = GET_CODE (operands[1]);
11767 rtx op0 = operands[0];
11768 rtx op1 = operands[2];
11769 rtx op2 = operands[3];
11771 if (cond_code == GEU || cond_code == LTU)
11772 {
11773 cond_code = swap_condition (cond_code);
11774 op1 = operands[3];
11775 op2 = operands[2];
11776 }
11778 if (!gpc_reg_operand (op1, <MODE>mode))
11779 op1 = force_reg (<MODE>mode, op1);
11780 if (!reg_or_short_operand (op2, <MODE>mode))
11781 op2 = force_reg (<MODE>mode, op2);
11783 rtx tmp = gen_reg_rtx (<MODE>mode);
11784 rtx tmp2 = gen_reg_rtx (<MODE>mode);
11786 emit_insn (gen_subf<mode>3_carry (tmp, op1, op2));
11787 emit_insn (gen_subf<mode>3_carry_in_xx (tmp2));
11789 if (cond_code == LEU)
11790 emit_insn (gen_add<mode>3 (op0, tmp2, const1_rtx));
11791 else
11792 emit_insn (gen_neg<mode>2 (op0, tmp2));
11794 DONE;
11795 })
11797 (define_expand "cstore<mode>4"
11798 [(use (match_operator 1 "rs6000_cbranch_operator"
11799 [(match_operand:GPR 2 "gpc_reg_operand" "")
11800 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11801 (clobber (match_operand:GPR 0 "register_operand"))]
11802 ""
11803 {
11804 /* Use ISEL if the user asked for it. */
11805 if (TARGET_ISEL)
11806 rs6000_emit_sISEL (<MODE>mode, operands);
11808 /* Expanding EQ and NE directly to some machine instructions does not help
11809 but does hurt combine. So don't. */
11810 else if (GET_CODE (operands[1]) == EQ)
11811 emit_insn (gen_eq<mode>3 (operands[0], operands[2], operands[3]));
11812 else if (<MODE>mode == Pmode
11813 && GET_CODE (operands[1]) == NE)
11814 emit_insn (gen_ne<mode>3 (operands[0], operands[2], operands[3]));
11815 else if (GET_CODE (operands[1]) == NE)
11816 {
11817 rtx tmp = gen_reg_rtx (<MODE>mode);
11818 emit_insn (gen_eq<mode>3 (tmp, operands[2], operands[3]));
11819 emit_insn (gen_xor<mode>3 (operands[0], tmp, const1_rtx));
11820 }
11822 /* Expanding the unsigned comparisons however helps a lot: all the neg_ltu
11823 etc. combinations magically work out just right. */
11824 else if (<MODE>mode == Pmode
11825 && unsigned_comparison_operator (operands[1], VOIDmode))
11826 emit_insn (gen_cstore<mode>4_unsigned (operands[0], operands[1],
11827 operands[2], operands[3]));
11829 /* The generic code knows tricks to compute signed comparisons against
11830 zero. Let it do its thing. */
11831 else if (operands[3] == const0_rtx
11832 && signed_comparison_operator (operands[1], VOIDmode))
11833 FAIL;
11835 /* Everything else, use the mfcr brute force. */
11836 else
11837 rs6000_emit_sCOND (<MODE>mode, operands);
11839 DONE;
11840 })
11842 (define_expand "cstore<mode>4"
11843 [(use (match_operator 1 "rs6000_cbranch_operator"
11844 [(match_operand:FP 2 "gpc_reg_operand" "")
11845 (match_operand:FP 3 "gpc_reg_operand" "")]))
11846 (clobber (match_operand:SI 0 "register_operand"))]
11847 ""
11848 {
11849 rs6000_emit_sCOND (<MODE>mode, operands);
11850 DONE;
11851 })
11854 (define_expand "stack_protect_set"
11855 [(match_operand 0 "memory_operand" "")
11856 (match_operand 1 "memory_operand" "")]
11857 ""
11858 {
11859 #ifdef TARGET_THREAD_SSP_OFFSET
11860 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11861 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11862 operands[1] = gen_rtx_MEM (Pmode, addr);
11863 #endif
11864 if (TARGET_64BIT)
11865 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11866 else
11867 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11868 DONE;
11869 })
11871 (define_insn "stack_protect_setsi"
11872 [(set (match_operand:SI 0 "memory_operand" "=m")
11873 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11874 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11875 "TARGET_32BIT"
11876 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11877 [(set_attr "type" "three")
11878 (set_attr "length" "12")])
11880 (define_insn "stack_protect_setdi"
11881 [(set (match_operand:DI 0 "memory_operand" "=Y")
11882 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11883 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11884 "TARGET_64BIT"
11885 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11886 [(set_attr "type" "three")
11887 (set_attr "length" "12")])
11889 (define_expand "stack_protect_test"
11890 [(match_operand 0 "memory_operand" "")
11891 (match_operand 1 "memory_operand" "")
11892 (match_operand 2 "" "")]
11893 ""
11894 {
11895 rtx test, op0, op1;
11896 #ifdef TARGET_THREAD_SSP_OFFSET
11897 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11898 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11899 operands[1] = gen_rtx_MEM (Pmode, addr);
11900 #endif
11901 op0 = operands[0];
11902 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11903 test = gen_rtx_EQ (VOIDmode, op0, op1);
11904 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11905 DONE;
11906 })
11908 (define_insn "stack_protect_testsi"
11909 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11910 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11911 (match_operand:SI 2 "memory_operand" "m,m")]
11912 UNSPEC_SP_TEST))
11913 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11914 (clobber (match_scratch:SI 3 "=&r,&r"))]
11915 "TARGET_32BIT"
11916 "@
11917 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11918 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11919 [(set_attr "length" "16,20")])
11921 (define_insn "stack_protect_testdi"
11922 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11923 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11924 (match_operand:DI 2 "memory_operand" "Y,Y")]
11925 UNSPEC_SP_TEST))
11926 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11927 (clobber (match_scratch:DI 3 "=&r,&r"))]
11928 "TARGET_64BIT"
11929 "@
11930 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11931 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11932 [(set_attr "length" "16,20")])
11934 \f
11935 ;; Here are the actual compare insns.
11936 (define_insn "*cmp<mode>_internal1"
11937 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11938 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11939 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11940 ""
11941 "cmp<wd>%I2 %0,%1,%2"
11942 [(set_attr "type" "cmp")])
11944 ;; If we are comparing a register for equality with a large constant,
11945 ;; we can do this with an XOR followed by a compare. But this is profitable
11946 ;; only if the large constant is only used for the comparison (and in this
11947 ;; case we already have a register to reuse as scratch).
11948 ;;
11949 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11950 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11952 (define_peephole2
11953 [(set (match_operand:SI 0 "register_operand")
11954 (match_operand:SI 1 "logical_const_operand" ""))
11955 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11956 [(match_dup 0)
11957 (match_operand:SI 2 "logical_const_operand" "")]))
11958 (set (match_operand:CC 4 "cc_reg_operand" "")
11959 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11960 (match_dup 0)))
11961 (set (pc)
11962 (if_then_else (match_operator 6 "equality_operator"
11963 [(match_dup 4) (const_int 0)])
11964 (match_operand 7 "" "")
11965 (match_operand 8 "" "")))]
11966 "peep2_reg_dead_p (3, operands[0])
11967 && peep2_reg_dead_p (4, operands[4])"
11968 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11969 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11970 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11972 {
11973 /* Get the constant we are comparing against, and see what it looks like
11974 when sign-extended from 16 to 32 bits. Then see what constant we could
11975 XOR with SEXTC to get the sign-extended value. */
11976 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11977 SImode,
11978 operands[1], operands[2]);
11979 HOST_WIDE_INT c = INTVAL (cnst);
11980 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11981 HOST_WIDE_INT xorv = c ^ sextc;
11983 operands[9] = GEN_INT (xorv);
11984 operands[10] = GEN_INT (sextc);
11985 })
11987 (define_insn "*cmpsi_internal2"
11988 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11989 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11990 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11991 ""
11992 "cmplw%I2 %0,%1,%b2"
11993 [(set_attr "type" "cmp")])
11995 (define_insn "*cmpdi_internal2"
11996 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11997 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11998 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11999 ""
12000 "cmpld%I2 %0,%1,%b2"
12001 [(set_attr "type" "cmp")])
12003 ;; The following two insns don't exist as single insns, but if we provide
12004 ;; them, we can swap an add and compare, which will enable us to overlap more
12005 ;; of the required delay between a compare and branch. We generate code for
12006 ;; them by splitting.
12008 (define_insn ""
12009 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12010 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12011 (match_operand:SI 2 "short_cint_operand" "i")))
12012 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12013 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12014 ""
12015 "#"
12016 [(set_attr "length" "8")])
12018 (define_insn ""
12019 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12020 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12021 (match_operand:SI 2 "u_short_cint_operand" "i")))
12022 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12023 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12024 ""
12025 "#"
12026 [(set_attr "length" "8")])
12028 (define_split
12029 [(set (match_operand:CC 3 "cc_reg_operand" "")
12030 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12031 (match_operand:SI 2 "short_cint_operand" "")))
12032 (set (match_operand:SI 0 "gpc_reg_operand" "")
12033 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12034 ""
12035 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12036 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12038 (define_split
12039 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12040 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12041 (match_operand:SI 2 "u_short_cint_operand" "")))
12042 (set (match_operand:SI 0 "gpc_reg_operand" "")
12043 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12044 ""
12045 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12046 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12048 ;; Only need to compare second words if first words equal
12049 (define_insn "*cmptf_internal1"
12050 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12051 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12052 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12053 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12054 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12055 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12056 [(set_attr "type" "fpcompare")
12057 (set_attr "length" "12")])
12059 (define_insn_and_split "*cmptf_internal2"
12060 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12061 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12062 (match_operand:TF 2 "gpc_reg_operand" "d")))
12063 (clobber (match_scratch:DF 3 "=d"))
12064 (clobber (match_scratch:DF 4 "=d"))
12065 (clobber (match_scratch:DF 5 "=d"))
12066 (clobber (match_scratch:DF 6 "=d"))
12067 (clobber (match_scratch:DF 7 "=d"))
12068 (clobber (match_scratch:DF 8 "=d"))
12069 (clobber (match_scratch:DF 9 "=d"))
12070 (clobber (match_scratch:DF 10 "=d"))
12071 (clobber (match_scratch:GPR 11 "=b"))]
12072 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12073 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12074 "#"
12075 "&& reload_completed"
12076 [(set (match_dup 3) (match_dup 14))
12077 (set (match_dup 4) (match_dup 15))
12078 (set (match_dup 9) (abs:DF (match_dup 5)))
12079 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12080 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12081 (label_ref (match_dup 12))
12082 (pc)))
12083 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12084 (set (pc) (label_ref (match_dup 13)))
12085 (match_dup 12)
12086 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12087 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12088 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12089 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12090 (match_dup 13)]
12091 {
12092 REAL_VALUE_TYPE rv;
12093 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
12094 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
12096 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12097 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12098 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12099 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12100 operands[12] = gen_label_rtx ();
12101 operands[13] = gen_label_rtx ();
12102 real_inf (&rv);
12103 operands[14] = force_const_mem (DFmode,
12104 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12105 operands[15] = force_const_mem (DFmode,
12106 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12107 DFmode));
12108 if (TARGET_TOC)
12109 {
12110 rtx tocref;
12111 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12112 operands[14] = gen_const_mem (DFmode, tocref);
12113 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12114 operands[15] = gen_const_mem (DFmode, tocref);
12115 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12116 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12117 }
12118 })
12119 \f
12120 ;; Now we have the scc insns. We can do some combinations because of the
12121 ;; way the machine works.
12122 ;;
12123 ;; Note that this is probably faster if we can put an insn between the
12124 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12125 ;; cases the insns below which don't use an intermediate CR field will
12126 ;; be used instead.
12127 (define_insn ""
12128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12129 (match_operator:SI 1 "scc_comparison_operator"
12130 [(match_operand 2 "cc_reg_operand" "y")
12131 (const_int 0)]))]
12132 ""
12133 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12134 [(set (attr "type")
12135 (cond [(match_test "TARGET_MFCRF")
12136 (const_string "mfcrf")
12137 ]
12138 (const_string "mfcr")))
12139 (set_attr "length" "8")])
12141 ;; Same as above, but get the GT bit.
12142 (define_insn "move_from_CR_gt_bit"
12143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12144 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12145 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12146 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12147 [(set_attr "type" "mfcr")
12148 (set_attr "length" "8")])
12150 ;; Same as above, but get the OV/ORDERED bit.
12151 (define_insn "move_from_CR_ov_bit"
12152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12153 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12154 UNSPEC_MV_CR_OV))]
12155 "TARGET_ISEL"
12156 "mfcr %0\;rlwinm %0,%0,%t1,1"
12157 [(set_attr "type" "mfcr")
12158 (set_attr "length" "8")])
12160 (define_insn ""
12161 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12162 (match_operator:DI 1 "scc_comparison_operator"
12163 [(match_operand 2 "cc_reg_operand" "y")
12164 (const_int 0)]))]
12165 "TARGET_POWERPC64"
12166 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12167 [(set (attr "type")
12168 (cond [(match_test "TARGET_MFCRF")
12169 (const_string "mfcrf")
12170 ]
12171 (const_string "mfcr")))
12172 (set_attr "length" "8")])
12174 (define_insn ""
12175 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12176 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12177 [(match_operand 2 "cc_reg_operand" "y,y")
12178 (const_int 0)])
12179 (const_int 0)))
12180 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12181 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12182 "TARGET_32BIT"
12183 "@
12184 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12185 #"
12186 [(set_attr "type" "shift")
12187 (set_attr "dot" "yes")
12188 (set_attr "length" "8,16")])
12190 (define_split
12191 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12192 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12193 [(match_operand 2 "cc_reg_operand" "")
12194 (const_int 0)])
12195 (const_int 0)))
12196 (set (match_operand:SI 3 "gpc_reg_operand" "")
12197 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12198 "TARGET_32BIT && reload_completed"
12199 [(set (match_dup 3)
12200 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12201 (set (match_dup 0)
12202 (compare:CC (match_dup 3)
12203 (const_int 0)))]
12204 "")
12206 (define_insn ""
12207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12208 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12209 [(match_operand 2 "cc_reg_operand" "y")
12210 (const_int 0)])
12211 (match_operand:SI 3 "const_int_operand" "n")))]
12212 ""
12213 "*
12214 {
12215 int is_bit = ccr_bit (operands[1], 1);
12216 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12217 int count;
12219 if (is_bit >= put_bit)
12220 count = is_bit - put_bit;
12221 else
12222 count = 32 - (put_bit - is_bit);
12224 operands[4] = GEN_INT (count);
12225 operands[5] = GEN_INT (put_bit);
12227 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
12228 }"
12229 [(set (attr "type")
12230 (cond [(match_test "TARGET_MFCRF")
12231 (const_string "mfcrf")
12232 ]
12233 (const_string "mfcr")))
12234 (set_attr "length" "8")])
12236 (define_insn ""
12237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12238 (compare:CC
12239 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12240 [(match_operand 2 "cc_reg_operand" "y,y")
12241 (const_int 0)])
12242 (match_operand:SI 3 "const_int_operand" "n,n"))
12243 (const_int 0)))
12244 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12245 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12246 (match_dup 3)))]
12247 ""
12248 "*
12249 {
12250 int is_bit = ccr_bit (operands[1], 1);
12251 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12252 int count;
12254 /* Force split for non-cc0 compare. */
12255 if (which_alternative == 1)
12256 return \"#\";
12258 if (is_bit >= put_bit)
12259 count = is_bit - put_bit;
12260 else
12261 count = 32 - (put_bit - is_bit);
12263 operands[5] = GEN_INT (count);
12264 operands[6] = GEN_INT (put_bit);
12266 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12267 }"
12268 [(set_attr "type" "shift")
12269 (set_attr "dot" "yes")
12270 (set_attr "length" "8,16")])
12272 (define_split
12273 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12274 (compare:CC
12275 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12276 [(match_operand 2 "cc_reg_operand" "")
12277 (const_int 0)])
12278 (match_operand:SI 3 "const_int_operand" ""))
12279 (const_int 0)))
12280 (set (match_operand:SI 4 "gpc_reg_operand" "")
12281 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12282 (match_dup 3)))]
12283 "reload_completed"
12284 [(set (match_dup 4)
12285 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12286 (match_dup 3)))
12287 (set (match_dup 0)
12288 (compare:CC (match_dup 4)
12289 (const_int 0)))]
12290 "")
12292 ;; There is a 3 cycle delay between consecutive mfcr instructions
12293 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12295 (define_peephole
12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12297 (match_operator:SI 1 "scc_comparison_operator"
12298 [(match_operand 2 "cc_reg_operand" "y")
12299 (const_int 0)]))
12300 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12301 (match_operator:SI 4 "scc_comparison_operator"
12302 [(match_operand 5 "cc_reg_operand" "y")
12303 (const_int 0)]))]
12304 "REGNO (operands[2]) != REGNO (operands[5])"
12305 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12306 [(set_attr "type" "mfcr")
12307 (set_attr "length" "12")])
12309 (define_peephole
12310 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12311 (match_operator:DI 1 "scc_comparison_operator"
12312 [(match_operand 2 "cc_reg_operand" "y")
12313 (const_int 0)]))
12314 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12315 (match_operator:DI 4 "scc_comparison_operator"
12316 [(match_operand 5 "cc_reg_operand" "y")
12317 (const_int 0)]))]
12318 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12319 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12320 [(set_attr "type" "mfcr")
12321 (set_attr "length" "12")])
12324 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12325 (DI "rKJI")])
12327 (define_insn_and_split "eq<mode>3"
12328 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12329 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12330 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
12331 (clobber (match_scratch:GPR 3 "=r"))
12332 (clobber (match_scratch:GPR 4 "=r"))]
12333 ""
12334 "#"
12335 ""
12336 [(set (match_dup 4)
12337 (clz:GPR (match_dup 3)))
12338 (set (match_dup 0)
12339 (lshiftrt:GPR (match_dup 4)
12340 (match_dup 5)))]
12341 {
12342 operands[3] = rs6000_emit_eqne (<MODE>mode,
12343 operands[1], operands[2], operands[3]);
12345 if (GET_CODE (operands[4]) == SCRATCH)
12346 operands[4] = gen_reg_rtx (<MODE>mode);
12348 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12349 }
12350 [(set (attr "length")
12351 (if_then_else (match_test "operands[2] == const0_rtx")
12352 (const_string "8")
12353 (const_string "12")))])
12355 (define_insn_and_split "ne<mode>3"
12356 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12357 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12358 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")))
12359 (clobber (match_scratch:P 3 "=r"))
12360 (clobber (match_scratch:P 4 "=r"))
12361 (clobber (reg:P CA_REGNO))]
12362 "!TARGET_ISEL"
12363 "#"
12364 ""
12365 [(parallel [(set (match_dup 4)
12366 (plus:P (match_dup 3)
12367 (const_int -1)))
12368 (set (reg:P CA_REGNO)
12369 (ne:P (match_dup 3)
12370 (const_int 0)))])
12371 (parallel [(set (match_dup 0)
12372 (plus:P (plus:P (not:P (match_dup 4))
12373 (reg:P CA_REGNO))
12374 (match_dup 3)))
12375 (clobber (reg:P CA_REGNO))])]
12376 {
12377 operands[3] = rs6000_emit_eqne (<MODE>mode,
12378 operands[1], operands[2], operands[3]);
12380 if (GET_CODE (operands[4]) == SCRATCH)
12381 operands[4] = gen_reg_rtx (<MODE>mode);
12382 }
12383 [(set (attr "length")
12384 (if_then_else (match_test "operands[2] == const0_rtx")
12385 (const_string "8")
12386 (const_string "12")))])
12388 (define_insn_and_split "*neg_eq_<mode>"
12389 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12390 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12391 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
12392 (clobber (match_scratch:P 3 "=r"))
12393 (clobber (match_scratch:P 4 "=r"))
12394 (clobber (reg:P CA_REGNO))]
12395 ""
12396 "#"
12397 ""
12398 [(parallel [(set (match_dup 4)
12399 (plus:P (match_dup 3)
12400 (const_int -1)))
12401 (set (reg:P CA_REGNO)
12402 (ne:P (match_dup 3)
12403 (const_int 0)))])
12404 (parallel [(set (match_dup 0)
12405 (plus:P (reg:P CA_REGNO)
12406 (const_int -1)))
12407 (clobber (reg:P CA_REGNO))])]
12408 {
12409 operands[3] = rs6000_emit_eqne (<MODE>mode,
12410 operands[1], operands[2], operands[3]);
12412 if (GET_CODE (operands[4]) == SCRATCH)
12413 operands[4] = gen_reg_rtx (<MODE>mode);
12414 }
12415 [(set (attr "length")
12416 (if_then_else (match_test "operands[2] == const0_rtx")
12417 (const_string "8")
12418 (const_string "12")))])
12420 (define_insn_and_split "*neg_ne_<mode>"
12421 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12422 (neg:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12423 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
12424 (clobber (match_scratch:P 3 "=r"))
12425 (clobber (match_scratch:P 4 "=r"))
12426 (clobber (reg:P CA_REGNO))]
12427 ""
12428 "#"
12429 ""
12430 [(parallel [(set (match_dup 4)
12431 (neg:P (match_dup 3)))
12432 (set (reg:P CA_REGNO)
12433 (eq:P (match_dup 3)
12434 (const_int 0)))])
12435 (parallel [(set (match_dup 0)
12436 (plus:P (reg:P CA_REGNO)
12437 (const_int -1)))
12438 (clobber (reg:P CA_REGNO))])]
12439 {
12440 operands[3] = rs6000_emit_eqne (<MODE>mode,
12441 operands[1], operands[2], operands[3]);
12443 if (GET_CODE (operands[4]) == SCRATCH)
12444 operands[4] = gen_reg_rtx (<MODE>mode);
12445 }
12446 [(set (attr "length")
12447 (if_then_else (match_test "operands[2] == const0_rtx")
12448 (const_string "8")
12449 (const_string "12")))])
12451 (define_insn_and_split "*plus_eq_<mode>"
12452 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12453 (plus:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12454 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12455 (match_operand:P 3 "gpc_reg_operand" "r")))
12456 (clobber (match_scratch:P 4 "=r"))
12457 (clobber (match_scratch:P 5 "=r"))
12458 (clobber (reg:P CA_REGNO))]
12459 ""
12460 "#"
12461 ""
12462 [(parallel [(set (match_dup 5)
12463 (neg:P (match_dup 4)))
12464 (set (reg:P CA_REGNO)
12465 (eq:P (match_dup 4)
12466 (const_int 0)))])
12467 (parallel [(set (match_dup 0)
12468 (plus:P (match_dup 3)
12469 (reg:P CA_REGNO)))
12470 (clobber (reg:P CA_REGNO))])]
12471 {
12472 operands[4] = rs6000_emit_eqne (<MODE>mode,
12473 operands[1], operands[2], operands[4]);
12475 if (GET_CODE (operands[5]) == SCRATCH)
12476 operands[5] = gen_reg_rtx (<MODE>mode);
12477 }
12478 [(set (attr "length")
12479 (if_then_else (match_test "operands[2] == const0_rtx")
12480 (const_string "8")
12481 (const_string "12")))])
12483 (define_insn_and_split "*plus_ne_<mode>"
12484 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12485 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12486 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12487 (match_operand:P 3 "gpc_reg_operand" "r")))
12488 (clobber (match_scratch:P 4 "=r"))
12489 (clobber (match_scratch:P 5 "=r"))
12490 (clobber (reg:P CA_REGNO))]
12491 ""
12492 "#"
12493 ""
12494 [(parallel [(set (match_dup 5)
12495 (plus:P (match_dup 4)
12496 (const_int -1)))
12497 (set (reg:P CA_REGNO)
12498 (ne:P (match_dup 4)
12499 (const_int 0)))])
12500 (parallel [(set (match_dup 0)
12501 (plus:P (match_dup 3)
12502 (reg:P CA_REGNO)))
12503 (clobber (reg:P CA_REGNO))])]
12504 {
12505 operands[4] = rs6000_emit_eqne (<MODE>mode,
12506 operands[1], operands[2], operands[4]);
12508 if (GET_CODE (operands[5]) == SCRATCH)
12509 operands[5] = gen_reg_rtx (<MODE>mode);
12510 }
12511 [(set (attr "length")
12512 (if_then_else (match_test "operands[2] == const0_rtx")
12513 (const_string "8")
12514 (const_string "12")))])
12516 (define_insn_and_split "*minus_eq_<mode>"
12517 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12518 (minus:P (match_operand:P 3 "gpc_reg_operand" "r")
12519 (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12520 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
12521 (clobber (match_scratch:P 4 "=r"))
12522 (clobber (match_scratch:P 5 "=r"))
12523 (clobber (reg:P CA_REGNO))]
12524 ""
12525 "#"
12526 ""
12527 [(parallel [(set (match_dup 5)
12528 (plus:P (match_dup 4)
12529 (const_int -1)))
12530 (set (reg:P CA_REGNO)
12531 (ne:P (match_dup 4)
12532 (const_int 0)))])
12533 (parallel [(set (match_dup 0)
12534 (plus:P (plus:P (match_dup 3)
12535 (reg:P CA_REGNO))
12536 (const_int -1)))
12537 (clobber (reg:P CA_REGNO))])]
12538 {
12539 operands[4] = rs6000_emit_eqne (<MODE>mode,
12540 operands[1], operands[2], operands[4]);
12542 if (GET_CODE (operands[5]) == SCRATCH)
12543 operands[5] = gen_reg_rtx (<MODE>mode);
12544 }
12545 [(set (attr "length")
12546 (if_then_else (match_test "operands[2] == const0_rtx")
12547 (const_string "8")
12548 (const_string "12")))])
12550 (define_insn_and_split "*minus_ne_<mode>"
12551 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12552 (minus:P (match_operand:P 3 "gpc_reg_operand" "r")
12553 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12554 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
12555 (clobber (match_scratch:P 4 "=r"))
12556 (clobber (match_scratch:P 5 "=r"))
12557 (clobber (reg:P CA_REGNO))]
12558 ""
12559 "#"
12560 ""
12561 [(parallel [(set (match_dup 5)
12562 (neg:P (match_dup 4)))
12563 (set (reg:P CA_REGNO)
12564 (eq:P (match_dup 4)
12565 (const_int 0)))])
12566 (parallel [(set (match_dup 0)
12567 (plus:P (plus:P (match_dup 3)
12568 (reg:P CA_REGNO))
12569 (const_int -1)))
12570 (clobber (reg:P CA_REGNO))])]
12571 {
12572 operands[4] = rs6000_emit_eqne (<MODE>mode,
12573 operands[1], operands[2], operands[4]);
12575 if (GET_CODE (operands[5]) == SCRATCH)
12576 operands[5] = gen_reg_rtx (<MODE>mode);
12577 }
12578 [(set (attr "length")
12579 (if_then_else (match_test "operands[2] == const0_rtx")
12580 (const_string "8")
12581 (const_string "12")))])
12583 (define_insn_and_split "*eqsi3_ext<mode>"
12584 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r")
12585 (eq:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r")
12586 (match_operand:SI 2 "scc_eq_operand" "rKLI")))
12587 (clobber (match_scratch:SI 3 "=r"))
12588 (clobber (match_scratch:SI 4 "=r"))]
12589 ""
12590 "#"
12591 ""
12592 [(set (match_dup 4)
12593 (clz:SI (match_dup 3)))
12594 (set (match_dup 0)
12595 (zero_extend:EXTSI
12596 (lshiftrt:SI (match_dup 4)
12597 (const_int 5))))]
12598 {
12599 operands[3] = rs6000_emit_eqne (SImode,
12600 operands[1], operands[2], operands[3]);
12602 if (GET_CODE (operands[4]) == SCRATCH)
12603 operands[4] = gen_reg_rtx (SImode);
12604 }
12605 [(set (attr "length")
12606 (if_then_else (match_test "operands[2] == const0_rtx")
12607 (const_string "8")
12608 (const_string "12")))])
12610 (define_insn_and_split "*nesi3_ext<mode>"
12611 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r")
12612 (ne:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r")
12613 (match_operand:SI 2 "scc_eq_operand" "rKLI")))
12614 (clobber (match_scratch:SI 3 "=r"))
12615 (clobber (match_scratch:SI 4 "=r"))
12616 (clobber (match_scratch:EXTSI 5 "=r"))]
12617 ""
12618 "#"
12619 ""
12620 [(set (match_dup 4)
12621 (clz:SI (match_dup 3)))
12622 (set (match_dup 5)
12623 (zero_extend:EXTSI
12624 (lshiftrt:SI (match_dup 4)
12625 (const_int 5))))
12626 (set (match_dup 0)
12627 (xor:EXTSI (match_dup 5)
12628 (const_int 1)))]
12629 {
12630 operands[3] = rs6000_emit_eqne (SImode,
12631 operands[1], operands[2], operands[3]);
12633 if (GET_CODE (operands[4]) == SCRATCH)
12634 operands[4] = gen_reg_rtx (SImode);
12635 if (GET_CODE (operands[5]) == SCRATCH)
12636 operands[5] = gen_reg_rtx (<MODE>mode);
12637 }
12638 [(set (attr "length")
12639 (if_then_else (match_test "operands[2] == const0_rtx")
12640 (const_string "12")
12641 (const_string "16")))])
12642 \f
12643 ;; Define both directions of branch and return. If we need a reload
12644 ;; register, we'd rather use CR0 since it is much easier to copy a
12645 ;; register CC value to there.
12647 (define_insn ""
12648 [(set (pc)
12649 (if_then_else (match_operator 1 "branch_comparison_operator"
12650 [(match_operand 2
12651 "cc_reg_operand" "y")
12652 (const_int 0)])
12653 (label_ref (match_operand 0 "" ""))
12654 (pc)))]
12655 ""
12656 "*
12657 {
12658 return output_cbranch (operands[1], \"%l0\", 0, insn);
12659 }"
12660 [(set_attr "type" "branch")])
12662 (define_insn ""
12663 [(set (pc)
12664 (if_then_else (match_operator 0 "branch_comparison_operator"
12665 [(match_operand 1
12666 "cc_reg_operand" "y")
12667 (const_int 0)])
12668 (any_return)
12669 (pc)))]
12670 "<return_pred>"
12671 "*
12672 {
12673 return output_cbranch (operands[0], NULL, 0, insn);
12674 }"
12675 [(set_attr "type" "jmpreg")
12676 (set_attr "length" "4")])
12678 (define_insn ""
12679 [(set (pc)
12680 (if_then_else (match_operator 1 "branch_comparison_operator"
12681 [(match_operand 2
12682 "cc_reg_operand" "y")
12683 (const_int 0)])
12684 (pc)
12685 (label_ref (match_operand 0 "" ""))))]
12686 ""
12687 "*
12688 {
12689 return output_cbranch (operands[1], \"%l0\", 1, insn);
12690 }"
12691 [(set_attr "type" "branch")])
12693 (define_insn ""
12694 [(set (pc)
12695 (if_then_else (match_operator 0 "branch_comparison_operator"
12696 [(match_operand 1
12697 "cc_reg_operand" "y")
12698 (const_int 0)])
12699 (pc)
12700 (any_return)))]
12701 "<return_pred>"
12702 "*
12703 {
12704 return output_cbranch (operands[0], NULL, 1, insn);
12705 }"
12706 [(set_attr "type" "jmpreg")
12707 (set_attr "length" "4")])
12709 ;; Logic on condition register values.
12711 ; This pattern matches things like
12712 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12713 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12714 ; (const_int 1)))
12715 ; which are generated by the branch logic.
12716 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12718 (define_insn "*cceq_ior_compare"
12719 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12720 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12721 [(match_operator:SI 2
12722 "branch_positive_comparison_operator"
12723 [(match_operand 3
12724 "cc_reg_operand" "y,y")
12725 (const_int 0)])
12726 (match_operator:SI 4
12727 "branch_positive_comparison_operator"
12728 [(match_operand 5
12729 "cc_reg_operand" "0,y")
12730 (const_int 0)])])
12731 (const_int 1)))]
12732 ""
12733 "cr%q1 %E0,%j2,%j4"
12734 [(set_attr "type" "cr_logical,delayed_cr")])
12736 ; Why is the constant -1 here, but 1 in the previous pattern?
12737 ; Because ~1 has all but the low bit set.
12738 (define_insn ""
12739 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12740 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12741 [(not:SI (match_operator:SI 2
12742 "branch_positive_comparison_operator"
12743 [(match_operand 3
12744 "cc_reg_operand" "y,y")
12745 (const_int 0)]))
12746 (match_operator:SI 4
12747 "branch_positive_comparison_operator"
12748 [(match_operand 5
12749 "cc_reg_operand" "0,y")
12750 (const_int 0)])])
12751 (const_int -1)))]
12752 ""
12753 "cr%q1 %E0,%j2,%j4"
12754 [(set_attr "type" "cr_logical,delayed_cr")])
12756 (define_insn "*cceq_rev_compare"
12757 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12758 (compare:CCEQ (match_operator:SI 1
12759 "branch_positive_comparison_operator"
12760 [(match_operand 2
12761 "cc_reg_operand" "0,y")
12762 (const_int 0)])
12763 (const_int 0)))]
12764 ""
12765 "crnot %E0,%j1"
12766 [(set_attr "type" "cr_logical,delayed_cr")])
12768 ;; If we are comparing the result of two comparisons, this can be done
12769 ;; using creqv or crxor.
12771 (define_insn_and_split ""
12772 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12773 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12774 [(match_operand 2 "cc_reg_operand" "y")
12775 (const_int 0)])
12776 (match_operator 3 "branch_comparison_operator"
12777 [(match_operand 4 "cc_reg_operand" "y")
12778 (const_int 0)])))]
12779 ""
12780 "#"
12781 ""
12782 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12783 (match_dup 5)))]
12784 "
12785 {
12786 int positive_1, positive_2;
12788 positive_1 = branch_positive_comparison_operator (operands[1],
12789 GET_MODE (operands[1]));
12790 positive_2 = branch_positive_comparison_operator (operands[3],
12791 GET_MODE (operands[3]));
12793 if (! positive_1)
12794 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12795 GET_CODE (operands[1])),
12796 SImode,
12797 operands[2], const0_rtx);
12798 else if (GET_MODE (operands[1]) != SImode)
12799 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12800 operands[2], const0_rtx);
12802 if (! positive_2)
12803 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12804 GET_CODE (operands[3])),
12805 SImode,
12806 operands[4], const0_rtx);
12807 else if (GET_MODE (operands[3]) != SImode)
12808 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12809 operands[4], const0_rtx);
12811 if (positive_1 == positive_2)
12812 {
12813 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12814 operands[5] = constm1_rtx;
12815 }
12816 else
12817 {
12818 operands[5] = const1_rtx;
12819 }
12820 }")
12822 ;; Unconditional branch and return.
12824 (define_insn "jump"
12825 [(set (pc)
12826 (label_ref (match_operand 0 "" "")))]
12827 ""
12828 "b %l0"
12829 [(set_attr "type" "branch")])
12831 (define_insn "<return_str>return"
12832 [(any_return)]
12833 "<return_pred>"
12834 "blr"
12835 [(set_attr "type" "jmpreg")])
12837 (define_expand "indirect_jump"
12838 [(set (pc) (match_operand 0 "register_operand" ""))])
12840 (define_insn "*indirect_jump<mode>"
12841 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12842 ""
12843 "@
12844 bctr
12845 blr"
12846 [(set_attr "type" "jmpreg")])
12848 ;; Table jump for switch statements:
12849 (define_expand "tablejump"
12850 [(use (match_operand 0 "" ""))
12851 (use (label_ref (match_operand 1 "" "")))]
12852 ""
12853 "
12854 {
12855 if (TARGET_32BIT)
12856 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12857 else
12858 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12859 DONE;
12860 }")
12862 (define_expand "tablejumpsi"
12863 [(set (match_dup 3)
12864 (plus:SI (match_operand:SI 0 "" "")
12865 (match_dup 2)))
12866 (parallel [(set (pc) (match_dup 3))
12867 (use (label_ref (match_operand 1 "" "")))])]
12868 "TARGET_32BIT"
12869 "
12870 { operands[0] = force_reg (SImode, operands[0]);
12871 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12872 operands[3] = gen_reg_rtx (SImode);
12873 }")
12875 (define_expand "tablejumpdi"
12876 [(set (match_dup 4)
12877 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
12878 (set (match_dup 3)
12879 (plus:DI (match_dup 4)
12880 (match_dup 2)))
12881 (parallel [(set (pc) (match_dup 3))
12882 (use (label_ref (match_operand 1 "" "")))])]
12883 "TARGET_64BIT"
12884 "
12885 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
12886 operands[3] = gen_reg_rtx (DImode);
12887 operands[4] = gen_reg_rtx (DImode);
12888 }")
12890 (define_insn "*tablejump<mode>_internal1"
12891 [(set (pc)
12892 (match_operand:P 0 "register_operand" "c,*l"))
12893 (use (label_ref (match_operand 1 "" "")))]
12894 ""
12895 "@
12896 bctr
12897 blr"
12898 [(set_attr "type" "jmpreg")])
12900 (define_insn "nop"
12901 [(const_int 0)]
12902 ""
12903 "nop")
12905 (define_insn "group_ending_nop"
12906 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
12907 ""
12908 "*
12909 {
12910 if (rs6000_cpu_attr == CPU_POWER6)
12911 return \"ori 1,1,0\";
12912 return \"ori 2,2,0\";
12913 }")
12914 \f
12915 ;; Define the subtract-one-and-jump insns, starting with the template
12916 ;; so loop.c knows what to generate.
12918 (define_expand "doloop_end"
12919 [(use (match_operand 0 "" "")) ; loop pseudo
12920 (use (match_operand 1 "" ""))] ; label
12921 ""
12922 "
12923 {
12924 if (TARGET_64BIT)
12925 {
12926 if (GET_MODE (operands[0]) != DImode)
12927 FAIL;
12928 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
12929 }
12930 else
12931 {
12932 if (GET_MODE (operands[0]) != SImode)
12933 FAIL;
12934 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
12935 }
12936 DONE;
12937 }")
12939 (define_expand "ctr<mode>"
12940 [(parallel [(set (pc)
12941 (if_then_else (ne (match_operand:P 0 "register_operand" "")
12942 (const_int 1))
12943 (label_ref (match_operand 1 "" ""))
12944 (pc)))
12945 (set (match_dup 0)
12946 (plus:P (match_dup 0)
12947 (const_int -1)))
12948 (clobber (match_scratch:CC 2 ""))
12949 (clobber (match_scratch:P 3 ""))])]
12950 ""
12951 "")
12953 ;; We need to be able to do this for any operand, including MEM, or we
12954 ;; will cause reload to blow up since we don't allow output reloads on
12955 ;; JUMP_INSNs.
12956 ;; For the length attribute to be calculated correctly, the
12957 ;; label MUST be operand 0.
12959 (define_insn "*ctr<mode>_internal1"
12960 [(set (pc)
12961 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12962 (const_int 1))
12963 (label_ref (match_operand 0 "" ""))
12964 (pc)))
12965 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
12966 (plus:P (match_dup 1)
12967 (const_int -1)))
12968 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12969 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12970 ""
12971 "*
12972 {
12973 if (which_alternative != 0)
12974 return \"#\";
12975 else if (get_attr_length (insn) == 4)
12976 return \"bdnz %l0\";
12977 else
12978 return \"bdz $+8\;b %l0\";
12979 }"
12980 [(set_attr "type" "branch")
12981 (set_attr "length" "*,16,20,20")])
12983 (define_insn "*ctr<mode>_internal2"
12984 [(set (pc)
12985 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12986 (const_int 1))
12987 (pc)
12988 (label_ref (match_operand 0 "" ""))))
12989 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
12990 (plus:P (match_dup 1)
12991 (const_int -1)))
12992 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12993 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12994 ""
12995 "*
12996 {
12997 if (which_alternative != 0)
12998 return \"#\";
12999 else if (get_attr_length (insn) == 4)
13000 return \"bdz %l0\";
13001 else
13002 return \"bdnz $+8\;b %l0\";
13003 }"
13004 [(set_attr "type" "branch")
13005 (set_attr "length" "*,16,20,20")])
13007 ;; Similar but use EQ
13009 (define_insn "*ctr<mode>_internal5"
13010 [(set (pc)
13011 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*b,*b,*b")
13012 (const_int 1))
13013 (label_ref (match_operand 0 "" ""))
13014 (pc)))
13015 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13016 (plus:P (match_dup 1)
13017 (const_int -1)))
13018 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13019 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13020 ""
13021 "*
13022 {
13023 if (which_alternative != 0)
13024 return \"#\";
13025 else if (get_attr_length (insn) == 4)
13026 return \"bdz %l0\";
13027 else
13028 return \"bdnz $+8\;b %l0\";
13029 }"
13030 [(set_attr "type" "branch")
13031 (set_attr "length" "*,16,20,20")])
13033 (define_insn "*ctr<mode>_internal6"
13034 [(set (pc)
13035 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*b,*b,*b")
13036 (const_int 1))
13037 (pc)
13038 (label_ref (match_operand 0 "" ""))))
13039 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13040 (plus:P (match_dup 1)
13041 (const_int -1)))
13042 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13043 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13044 ""
13045 "*
13046 {
13047 if (which_alternative != 0)
13048 return \"#\";
13049 else if (get_attr_length (insn) == 4)
13050 return \"bdnz %l0\";
13051 else
13052 return \"bdz $+8\;b %l0\";
13053 }"
13054 [(set_attr "type" "branch")
13055 (set_attr "length" "*,16,20,20")])
13057 ;; Now the splitters if we could not allocate the CTR register
13059 (define_split
13060 [(set (pc)
13061 (if_then_else (match_operator 2 "comparison_operator"
13062 [(match_operand:P 1 "gpc_reg_operand" "")
13063 (const_int 1)])
13064 (match_operand 5 "" "")
13065 (match_operand 6 "" "")))
13066 (set (match_operand:P 0 "gpc_reg_operand" "")
13067 (plus:P (match_dup 1) (const_int -1)))
13068 (clobber (match_scratch:CC 3 ""))
13069 (clobber (match_scratch:P 4 ""))]
13070 "reload_completed"
13071 [(set (match_dup 3)
13072 (compare:CC (match_dup 1)
13073 (const_int 1)))
13074 (set (match_dup 0)
13075 (plus:P (match_dup 1)
13076 (const_int -1)))
13077 (set (pc) (if_then_else (match_dup 7)
13078 (match_dup 5)
13079 (match_dup 6)))]
13080 "
13081 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13082 operands[3], const0_rtx); }")
13084 (define_split
13085 [(set (pc)
13086 (if_then_else (match_operator 2 "comparison_operator"
13087 [(match_operand:P 1 "gpc_reg_operand" "")
13088 (const_int 1)])
13089 (match_operand 5 "" "")
13090 (match_operand 6 "" "")))
13091 (set (match_operand:P 0 "nonimmediate_operand" "")
13092 (plus:P (match_dup 1) (const_int -1)))
13093 (clobber (match_scratch:CC 3 ""))
13094 (clobber (match_scratch:P 4 ""))]
13095 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13096 [(set (match_dup 3)
13097 (compare:CC (match_dup 1)
13098 (const_int 1)))
13099 (set (match_dup 4)
13100 (plus:P (match_dup 1)
13101 (const_int -1)))
13102 (set (match_dup 0)
13103 (match_dup 4))
13104 (set (pc) (if_then_else (match_dup 7)
13105 (match_dup 5)
13106 (match_dup 6)))]
13107 "
13108 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13109 operands[3], const0_rtx); }")
13110 \f
13111 (define_insn "trap"
13112 [(trap_if (const_int 1) (const_int 0))]
13113 ""
13114 "trap"
13115 [(set_attr "type" "trap")])
13117 (define_expand "ctrap<mode>4"
13118 [(trap_if (match_operator 0 "ordered_comparison_operator"
13119 [(match_operand:GPR 1 "register_operand")
13120 (match_operand:GPR 2 "reg_or_short_operand")])
13121 (match_operand 3 "zero_constant" ""))]
13122 ""
13123 "")
13125 (define_insn ""
13126 [(trap_if (match_operator 0 "ordered_comparison_operator"
13127 [(match_operand:GPR 1 "register_operand" "r")
13128 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13129 (const_int 0))]
13130 ""
13131 "t<wd>%V0%I2 %1,%2"
13132 [(set_attr "type" "trap")])
13133 \f
13134 ;; Insns related to generating the function prologue and epilogue.
13136 (define_expand "prologue"
13137 [(use (const_int 0))]
13138 ""
13139 {
13140 rs6000_emit_prologue ();
13141 if (!TARGET_SCHED_PROLOG)
13142 emit_insn (gen_blockage ());
13143 DONE;
13144 })
13146 (define_insn "*movesi_from_cr_one"
13147 [(match_parallel 0 "mfcr_operation"
13148 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13149 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13150 (match_operand 3 "immediate_operand" "n")]
13151 UNSPEC_MOVESI_FROM_CR))])]
13152 "TARGET_MFCRF"
13153 "*
13154 {
13155 int mask = 0;
13156 int i;
13157 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13158 {
13159 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13160 operands[4] = GEN_INT (mask);
13161 output_asm_insn (\"mfcr %1,%4\", operands);
13162 }
13163 return \"\";
13164 }"
13165 [(set_attr "type" "mfcrf")])
13167 (define_insn "movesi_from_cr"
13168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13169 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13170 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13171 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13172 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13173 UNSPEC_MOVESI_FROM_CR))]
13174 ""
13175 "mfcr %0"
13176 [(set_attr "type" "mfcr")])
13178 (define_insn "*crsave"
13179 [(match_parallel 0 "crsave_operation"
13180 [(set (match_operand:SI 1 "memory_operand" "=m")
13181 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13182 ""
13183 "stw %2,%1"
13184 [(set_attr "type" "store")])
13186 (define_insn "*stmw"
13187 [(match_parallel 0 "stmw_operation"
13188 [(set (match_operand:SI 1 "memory_operand" "=m")
13189 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13190 "TARGET_MULTIPLE"
13191 "stmw %2,%1"
13192 [(set_attr "type" "store")
13193 (set_attr "update" "yes")
13194 (set_attr "indexed" "yes")])
13196 ; The following comment applies to:
13197 ; save_gpregs_*
13198 ; save_fpregs_*
13199 ; restore_gpregs*
13200 ; return_and_restore_gpregs*
13201 ; return_and_restore_fpregs*
13202 ; return_and_restore_fpregs_aix*
13203 ;
13204 ; The out-of-line save / restore functions expects one input argument.
13205 ; Since those are not standard call_insn's, we must avoid using
13206 ; MATCH_OPERAND for that argument. That way the register rename
13207 ; optimization will not try to rename this register.
13208 ; Each pattern is repeated for each possible register number used in
13209 ; various ABIs (r11, r1, and for some functions r12)
13211 (define_insn "*save_gpregs_<mode>_r11"
13212 [(match_parallel 0 "any_parallel_operand"
13213 [(clobber (reg:P 65))
13214 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13215 (use (reg:P 11))
13216 (set (match_operand:P 2 "memory_operand" "=m")
13217 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13218 ""
13219 "bl %1"
13220 [(set_attr "type" "branch")
13221 (set_attr "length" "4")])
13223 (define_insn "*save_gpregs_<mode>_r12"
13224 [(match_parallel 0 "any_parallel_operand"
13225 [(clobber (reg:P 65))
13226 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13227 (use (reg:P 12))
13228 (set (match_operand:P 2 "memory_operand" "=m")
13229 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13230 ""
13231 "bl %1"
13232 [(set_attr "type" "branch")
13233 (set_attr "length" "4")])
13235 (define_insn "*save_gpregs_<mode>_r1"
13236 [(match_parallel 0 "any_parallel_operand"
13237 [(clobber (reg:P 65))
13238 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13239 (use (reg:P 1))
13240 (set (match_operand:P 2 "memory_operand" "=m")
13241 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13242 ""
13243 "bl %1"
13244 [(set_attr "type" "branch")
13245 (set_attr "length" "4")])
13247 (define_insn "*save_fpregs_<mode>_r11"
13248 [(match_parallel 0 "any_parallel_operand"
13249 [(clobber (reg:P 65))
13250 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13251 (use (reg:P 11))
13252 (set (match_operand:DF 2 "memory_operand" "=m")
13253 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13254 ""
13255 "bl %1"
13256 [(set_attr "type" "branch")
13257 (set_attr "length" "4")])
13259 (define_insn "*save_fpregs_<mode>_r12"
13260 [(match_parallel 0 "any_parallel_operand"
13261 [(clobber (reg:P 65))
13262 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13263 (use (reg:P 12))
13264 (set (match_operand:DF 2 "memory_operand" "=m")
13265 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13266 ""
13267 "bl %1"
13268 [(set_attr "type" "branch")
13269 (set_attr "length" "4")])
13271 (define_insn "*save_fpregs_<mode>_r1"
13272 [(match_parallel 0 "any_parallel_operand"
13273 [(clobber (reg:P 65))
13274 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13275 (use (reg:P 1))
13276 (set (match_operand:DF 2 "memory_operand" "=m")
13277 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13278 ""
13279 "bl %1"
13280 [(set_attr "type" "branch")
13281 (set_attr "length" "4")])
13283 ; This is to explain that changes to the stack pointer should
13284 ; not be moved over loads from or stores to stack memory.
13285 (define_insn "stack_tie"
13286 [(match_parallel 0 "tie_operand"
13287 [(set (mem:BLK (reg 1)) (const_int 0))])]
13288 ""
13289 ""
13290 [(set_attr "length" "0")])
13292 (define_expand "epilogue"
13293 [(use (const_int 0))]
13294 ""
13295 {
13296 if (!TARGET_SCHED_PROLOG)
13297 emit_insn (gen_blockage ());
13298 rs6000_emit_epilogue (FALSE);
13299 DONE;
13300 })
13302 ; On some processors, doing the mtcrf one CC register at a time is
13303 ; faster (like on the 604e). On others, doing them all at once is
13304 ; faster; for instance, on the 601 and 750.
13306 (define_expand "movsi_to_cr_one"
13307 [(set (match_operand:CC 0 "cc_reg_operand" "")
13308 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13309 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13310 ""
13311 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13313 (define_insn "*movsi_to_cr"
13314 [(match_parallel 0 "mtcrf_operation"
13315 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13316 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13317 (match_operand 3 "immediate_operand" "n")]
13318 UNSPEC_MOVESI_TO_CR))])]
13319 ""
13320 "*
13321 {
13322 int mask = 0;
13323 int i;
13324 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13325 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13326 operands[4] = GEN_INT (mask);
13327 return \"mtcrf %4,%2\";
13328 }"
13329 [(set_attr "type" "mtcr")])
13331 (define_insn "*mtcrfsi"
13332 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13333 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13334 (match_operand 2 "immediate_operand" "n")]
13335 UNSPEC_MOVESI_TO_CR))]
13336 "GET_CODE (operands[0]) == REG
13337 && CR_REGNO_P (REGNO (operands[0]))
13338 && GET_CODE (operands[2]) == CONST_INT
13339 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13340 "mtcrf %R0,%1"
13341 [(set_attr "type" "mtcr")])
13343 ; The load-multiple instructions have similar properties.
13344 ; Note that "load_multiple" is a name known to the machine-independent
13345 ; code that actually corresponds to the PowerPC load-string.
13347 (define_insn "*lmw"
13348 [(match_parallel 0 "lmw_operation"
13349 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13350 (match_operand:SI 2 "memory_operand" "m"))])]
13351 "TARGET_MULTIPLE"
13352 "lmw %1,%2"
13353 [(set_attr "type" "load")
13354 (set_attr "update" "yes")
13355 (set_attr "indexed" "yes")
13356 (set_attr "cell_micro" "always")])
13358 (define_insn "*return_internal_<mode>"
13359 [(simple_return)
13360 (use (match_operand:P 0 "register_operand" "lc"))]
13361 ""
13362 "b%T0"
13363 [(set_attr "type" "jmpreg")])
13365 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13366 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13368 ; The following comment applies to:
13369 ; save_gpregs_*
13370 ; save_fpregs_*
13371 ; restore_gpregs*
13372 ; return_and_restore_gpregs*
13373 ; return_and_restore_fpregs*
13374 ; return_and_restore_fpregs_aix*
13375 ;
13376 ; The out-of-line save / restore functions expects one input argument.
13377 ; Since those are not standard call_insn's, we must avoid using
13378 ; MATCH_OPERAND for that argument. That way the register rename
13379 ; optimization will not try to rename this register.
13380 ; Each pattern is repeated for each possible register number used in
13381 ; various ABIs (r11, r1, and for some functions r12)
13383 (define_insn "*restore_gpregs_<mode>_r11"
13384 [(match_parallel 0 "any_parallel_operand"
13385 [(clobber (match_operand:P 1 "register_operand" "=l"))
13386 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13387 (use (reg:P 11))
13388 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13389 (match_operand:P 4 "memory_operand" "m"))])]
13390 ""
13391 "bl %2"
13392 [(set_attr "type" "branch")
13393 (set_attr "length" "4")])
13395 (define_insn "*restore_gpregs_<mode>_r12"
13396 [(match_parallel 0 "any_parallel_operand"
13397 [(clobber (match_operand:P 1 "register_operand" "=l"))
13398 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13399 (use (reg:P 12))
13400 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13401 (match_operand:P 4 "memory_operand" "m"))])]
13402 ""
13403 "bl %2"
13404 [(set_attr "type" "branch")
13405 (set_attr "length" "4")])
13407 (define_insn "*restore_gpregs_<mode>_r1"
13408 [(match_parallel 0 "any_parallel_operand"
13409 [(clobber (match_operand:P 1 "register_operand" "=l"))
13410 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13411 (use (reg:P 1))
13412 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13413 (match_operand:P 4 "memory_operand" "m"))])]
13414 ""
13415 "bl %2"
13416 [(set_attr "type" "branch")
13417 (set_attr "length" "4")])
13419 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13420 [(match_parallel 0 "any_parallel_operand"
13421 [(return)
13422 (clobber (match_operand:P 1 "register_operand" "=l"))
13423 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13424 (use (reg:P 11))
13425 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13426 (match_operand:P 4 "memory_operand" "m"))])]
13427 ""
13428 "b %2"
13429 [(set_attr "type" "branch")
13430 (set_attr "length" "4")])
13432 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13433 [(match_parallel 0 "any_parallel_operand"
13434 [(return)
13435 (clobber (match_operand:P 1 "register_operand" "=l"))
13436 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13437 (use (reg:P 12))
13438 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13439 (match_operand:P 4 "memory_operand" "m"))])]
13440 ""
13441 "b %2"
13442 [(set_attr "type" "branch")
13443 (set_attr "length" "4")])
13445 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13446 [(match_parallel 0 "any_parallel_operand"
13447 [(return)
13448 (clobber (match_operand:P 1 "register_operand" "=l"))
13449 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13450 (use (reg:P 1))
13451 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13452 (match_operand:P 4 "memory_operand" "m"))])]
13453 ""
13454 "b %2"
13455 [(set_attr "type" "branch")
13456 (set_attr "length" "4")])
13458 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13459 [(match_parallel 0 "any_parallel_operand"
13460 [(return)
13461 (clobber (match_operand:P 1 "register_operand" "=l"))
13462 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13463 (use (reg:P 11))
13464 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13465 (match_operand:DF 4 "memory_operand" "m"))])]
13466 ""
13467 "b %2"
13468 [(set_attr "type" "branch")
13469 (set_attr "length" "4")])
13471 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13472 [(match_parallel 0 "any_parallel_operand"
13473 [(return)
13474 (clobber (match_operand:P 1 "register_operand" "=l"))
13475 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13476 (use (reg:P 12))
13477 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13478 (match_operand:DF 4 "memory_operand" "m"))])]
13479 ""
13480 "b %2"
13481 [(set_attr "type" "branch")
13482 (set_attr "length" "4")])
13484 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13485 [(match_parallel 0 "any_parallel_operand"
13486 [(return)
13487 (clobber (match_operand:P 1 "register_operand" "=l"))
13488 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13489 (use (reg:P 1))
13490 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13491 (match_operand:DF 4 "memory_operand" "m"))])]
13492 ""
13493 "b %2"
13494 [(set_attr "type" "branch")
13495 (set_attr "length" "4")])
13497 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13498 [(match_parallel 0 "any_parallel_operand"
13499 [(return)
13500 (use (match_operand:P 1 "register_operand" "l"))
13501 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13502 (use (reg:P 11))
13503 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13504 (match_operand:DF 4 "memory_operand" "m"))])]
13505 ""
13506 "b %2"
13507 [(set_attr "type" "branch")
13508 (set_attr "length" "4")])
13510 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13511 [(match_parallel 0 "any_parallel_operand"
13512 [(return)
13513 (use (match_operand:P 1 "register_operand" "l"))
13514 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13515 (use (reg:P 1))
13516 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13517 (match_operand:DF 4 "memory_operand" "m"))])]
13518 ""
13519 "b %2"
13520 [(set_attr "type" "branch")
13521 (set_attr "length" "4")])
13523 ; This is used in compiling the unwind routines.
13524 (define_expand "eh_return"
13525 [(use (match_operand 0 "general_operand" ""))]
13526 ""
13527 "
13528 {
13529 if (TARGET_32BIT)
13530 emit_insn (gen_eh_set_lr_si (operands[0]));
13531 else
13532 emit_insn (gen_eh_set_lr_di (operands[0]));
13533 DONE;
13534 }")
13536 ; We can't expand this before we know where the link register is stored.
13537 (define_insn "eh_set_lr_<mode>"
13538 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13539 UNSPECV_EH_RR)
13540 (clobber (match_scratch:P 1 "=&b"))]
13541 ""
13542 "#")
13544 (define_split
13545 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13546 (clobber (match_scratch 1 ""))]
13547 "reload_completed"
13548 [(const_int 0)]
13549 "
13550 {
13551 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13552 DONE;
13553 }")
13555 (define_insn "prefetch"
13556 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13557 (match_operand:SI 1 "const_int_operand" "n")
13558 (match_operand:SI 2 "const_int_operand" "n"))]
13559 ""
13560 "*
13561 {
13562 if (GET_CODE (operands[0]) == REG)
13563 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13564 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13565 }"
13566 [(set_attr "type" "load")])
13567 \f
13568 (define_insn "bpermd_<mode>"
13569 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13570 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
13571 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
13572 "TARGET_POPCNTD"
13573 "bpermd %0,%1,%2"
13574 [(set_attr "type" "popcnt")])
13576 \f
13577 ;; Builtin fma support. Handle
13578 ;; Note that the conditions for expansion are in the FMA_F iterator.
13580 (define_expand "fma<mode>4"
13581 [(set (match_operand:FMA_F 0 "register_operand" "")
13582 (fma:FMA_F
13583 (match_operand:FMA_F 1 "register_operand" "")
13584 (match_operand:FMA_F 2 "register_operand" "")
13585 (match_operand:FMA_F 3 "register_operand" "")))]
13586 ""
13587 "")
13589 (define_insn "*fma<mode>4_fpr"
13590 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
13591 (fma:SFDF
13592 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
13593 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
13594 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
13595 "TARGET_<MODE>_FPR"
13596 "@
13597 fmadd<Ftrad> %0,%1,%2,%3
13598 xsmadda<Fvsx> %x0,%x1,%x2
13599 xsmaddm<Fvsx> %x0,%x1,%x3"
13600 [(set_attr "type" "fp")
13601 (set_attr "fp_type" "fp_maddsub_<Fs>")])
13603 ; Altivec only has fma and nfms.
13604 (define_expand "fms<mode>4"
13605 [(set (match_operand:FMA_F 0 "register_operand" "")
13606 (fma:FMA_F
13607 (match_operand:FMA_F 1 "register_operand" "")
13608 (match_operand:FMA_F 2 "register_operand" "")
13609 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
13610 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13611 "")
13613 (define_insn "*fms<mode>4_fpr"
13614 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
13615 (fma:SFDF
13616 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
13617 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
13618 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
13619 "TARGET_<MODE>_FPR"
13620 "@
13621 fmsub<Ftrad> %0,%1,%2,%3
13622 xsmsuba<Fvsx> %x0,%x1,%x2
13623 xsmsubm<Fvsx> %x0,%x1,%x3"
13624 [(set_attr "type" "fp")
13625 (set_attr "fp_type" "fp_maddsub_<Fs>")])
13627 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
13628 (define_expand "fnma<mode>4"
13629 [(set (match_operand:FMA_F 0 "register_operand" "")
13630 (neg:FMA_F
13631 (fma:FMA_F
13632 (match_operand:FMA_F 1 "register_operand" "")
13633 (match_operand:FMA_F 2 "register_operand" "")
13634 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13635 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
13636 "")
13638 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
13639 (define_expand "fnms<mode>4"
13640 [(set (match_operand:FMA_F 0 "register_operand" "")
13641 (neg:FMA_F
13642 (fma:FMA_F
13643 (match_operand:FMA_F 1 "register_operand" "")
13644 (match_operand:FMA_F 2 "register_operand" "")
13645 (match_operand:FMA_F 3 "register_operand" ""))))]
13646 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13647 "")
13649 ; Not an official optab name, but used from builtins.
13650 (define_expand "nfma<mode>4"
13651 [(set (match_operand:FMA_F 0 "register_operand" "")
13652 (neg:FMA_F
13653 (fma:FMA_F
13654 (match_operand:FMA_F 1 "register_operand" "")
13655 (match_operand:FMA_F 2 "register_operand" "")
13656 (match_operand:FMA_F 3 "register_operand" ""))))]
13657 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13658 "")
13660 (define_insn "*nfma<mode>4_fpr"
13661 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
13662 (neg:SFDF
13663 (fma:SFDF
13664 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
13665 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
13666 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
13667 "TARGET_<MODE>_FPR"
13668 "@
13669 fnmadd<Ftrad> %0,%1,%2,%3
13670 xsnmadda<Fvsx> %x0,%x1,%x2
13671 xsnmaddm<Fvsx> %x0,%x1,%x3"
13672 [(set_attr "type" "fp")
13673 (set_attr "fp_type" "fp_maddsub_<Fs>")])
13675 ; Not an official optab name, but used from builtins.
13676 (define_expand "nfms<mode>4"
13677 [(set (match_operand:FMA_F 0 "register_operand" "")
13678 (neg:FMA_F
13679 (fma:FMA_F
13680 (match_operand:FMA_F 1 "register_operand" "")
13681 (match_operand:FMA_F 2 "register_operand" "")
13682 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13683 ""
13684 "")
13686 (define_insn "*nfmssf4_fpr"
13687 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
13688 (neg:SFDF
13689 (fma:SFDF
13690 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
13691 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
13692 (neg:SFDF
13693 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
13694 "TARGET_<MODE>_FPR"
13695 "@
13696 fnmsub<Ftrad> %0,%1,%2,%3
13697 xsnmsuba<Fvsx> %x0,%x1,%x2
13698 xsnmsubm<Fvsx> %x0,%x1,%x3"
13699 [(set_attr "type" "fp")
13700 (set_attr "fp_type" "fp_maddsub_<Fs>")])
13702 \f
13703 (define_expand "rs6000_get_timebase"
13704 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13705 ""
13706 {
13707 if (TARGET_POWERPC64)
13708 emit_insn (gen_rs6000_mftb_di (operands[0]));
13709 else
13710 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13711 DONE;
13712 })
13714 (define_insn "rs6000_get_timebase_ppc32"
13715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13716 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13717 (clobber (match_scratch:SI 1 "=r"))
13718 (clobber (match_scratch:CC 2 "=y"))]
13719 "!TARGET_POWERPC64"
13720 {
13721 if (WORDS_BIG_ENDIAN)
13722 if (TARGET_MFCRF)
13723 {
13724 return "mfspr %0,269\;"
13725 "mfspr %L0,268\;"
13726 "mfspr %1,269\;"
13727 "cmpw %2,%0,%1\;"
13728 "bne- %2,$-16";
13729 }
13730 else
13731 {
13732 return "mftbu %0\;"
13733 "mftb %L0\;"
13734 "mftbu %1\;"
13735 "cmpw %2,%0,%1\;"
13736 "bne- %2,$-16";
13737 }
13738 else
13739 if (TARGET_MFCRF)
13740 {
13741 return "mfspr %L0,269\;"
13742 "mfspr %0,268\;"
13743 "mfspr %1,269\;"
13744 "cmpw %2,%L0,%1\;"
13745 "bne- %2,$-16";
13746 }
13747 else
13748 {
13749 return "mftbu %L0\;"
13750 "mftb %0\;"
13751 "mftbu %1\;"
13752 "cmpw %2,%L0,%1\;"
13753 "bne- %2,$-16";
13754 }
13755 }
13756 [(set_attr "length" "20")])
13758 (define_insn "rs6000_mftb_<mode>"
13759 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13760 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
13761 ""
13762 {
13763 if (TARGET_MFCRF)
13764 return "mfspr %0,268";
13765 else
13766 return "mftb %0";
13767 })
13769 \f
13770 (define_insn "rs6000_mffs"
13771 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
13772 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
13773 "TARGET_HARD_FLOAT && TARGET_FPRS"
13774 "mffs %0")
13776 (define_insn "rs6000_mtfsf"
13777 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
13778 (match_operand:DF 1 "gpc_reg_operand" "d")]
13779 UNSPECV_MTFSF)]
13780 "TARGET_HARD_FLOAT && TARGET_FPRS"
13781 "mtfsf %0,%1")
13783 \f
13784 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
13785 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
13786 ;; register that is being loaded. The fused ops must be physically adjacent.
13788 ;; Find cases where the addis that feeds into a load instruction is either used
13789 ;; once or is the same as the target register, and replace it with the fusion
13790 ;; insn
13792 (define_peephole2
13793 [(set (match_operand:P 0 "base_reg_operand" "")
13794 (match_operand:P 1 "fusion_gpr_addis" ""))
13795 (set (match_operand:INT1 2 "base_reg_operand" "")
13796 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
13797 "TARGET_P8_FUSION
13798 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
13799 operands[3])"
13800 [(const_int 0)]
13801 {
13802 expand_fusion_gpr_load (operands);
13803 DONE;
13804 })
13806 ;; Fusion insn, created by the define_peephole2 above (and eventually by
13807 ;; reload)
13809 (define_insn "fusion_gpr_load_<mode>"
13810 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
13811 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
13812 UNSPEC_FUSION_GPR))]
13813 "TARGET_P8_FUSION"
13814 {
13815 return emit_fusion_gpr_load (operands[0], operands[1]);
13816 }
13817 [(set_attr "type" "load")
13818 (set_attr "length" "8")])
13820 \f
13821 ;; Miscellaneous ISA 2.06 (power7) instructions
13822 (define_insn "addg6s"
13823 [(set (match_operand:SI 0 "register_operand" "=r")
13824 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
13825 (match_operand:SI 2 "register_operand" "r")]
13826 UNSPEC_ADDG6S))]
13827 "TARGET_POPCNTD"
13828 "addg6s %0,%1,%2"
13829 [(set_attr "type" "integer")
13830 (set_attr "length" "4")])
13832 (define_insn "cdtbcd"
13833 [(set (match_operand:SI 0 "register_operand" "=r")
13834 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
13835 UNSPEC_CDTBCD))]
13836 "TARGET_POPCNTD"
13837 "cdtbcd %0,%1"
13838 [(set_attr "type" "integer")
13839 (set_attr "length" "4")])
13841 (define_insn "cbcdtd"
13842 [(set (match_operand:SI 0 "register_operand" "=r")
13843 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
13844 UNSPEC_CBCDTD))]
13845 "TARGET_POPCNTD"
13846 "cbcdtd %0,%1"
13847 [(set_attr "type" "integer")
13848 (set_attr "length" "4")])
13850 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
13851 UNSPEC_DIVEO
13852 UNSPEC_DIVEU
13853 UNSPEC_DIVEUO])
13855 (define_int_attr div_extend [(UNSPEC_DIVE "e")
13856 (UNSPEC_DIVEO "eo")
13857 (UNSPEC_DIVEU "eu")
13858 (UNSPEC_DIVEUO "euo")])
13860 (define_insn "div<div_extend>_<mode>"
13861 [(set (match_operand:GPR 0 "register_operand" "=r")
13862 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
13863 (match_operand:GPR 2 "register_operand" "r")]
13864 UNSPEC_DIV_EXTEND))]
13865 "TARGET_POPCNTD"
13866 "div<wd><div_extend> %0,%1,%2"
13867 [(set_attr "type" "div")
13868 (set_attr "size" "<bits>")])
13870 \f
13871 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
13873 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
13874 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
13876 (define_expand "unpack<mode>"
13877 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
13878 (unspec:<FP128_64>
13879 [(match_operand:FMOVE128 1 "register_operand" "")
13880 (match_operand:QI 2 "const_0_to_1_operand" "")]
13881 UNSPEC_UNPACK_128BIT))]
13882 ""
13883 "")
13885 (define_insn_and_split "unpack<mode>_dm"
13886 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
13887 (unspec:<FP128_64>
13888 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
13889 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
13890 UNSPEC_UNPACK_128BIT))]
13891 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
13892 "#"
13893 "&& reload_completed"
13894 [(set (match_dup 0) (match_dup 3))]
13895 {
13896 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
13898 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
13899 {
13900 emit_note (NOTE_INSN_DELETED);
13901 DONE;
13902 }
13904 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
13905 }
13906 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
13907 (set_attr "length" "4")])
13909 (define_insn_and_split "unpack<mode>_nodm"
13910 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
13911 (unspec:<FP128_64>
13912 [(match_operand:FMOVE128 1 "register_operand" "d,d")
13913 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
13914 UNSPEC_UNPACK_128BIT))]
13915 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
13916 "#"
13917 "&& reload_completed"
13918 [(set (match_dup 0) (match_dup 3))]
13919 {
13920 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
13922 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
13923 {
13924 emit_note (NOTE_INSN_DELETED);
13925 DONE;
13926 }
13928 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
13929 }
13930 [(set_attr "type" "fp,fpstore")
13931 (set_attr "length" "4")])
13933 (define_insn_and_split "pack<mode>"
13934 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
13935 (unspec:FMOVE128
13936 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
13937 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
13938 UNSPEC_PACK_128BIT))]
13939 ""
13940 "@
13941 fmr %L0,%2
13942 #"
13943 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
13944 [(set (match_dup 3) (match_dup 1))
13945 (set (match_dup 4) (match_dup 2))]
13946 {
13947 unsigned dest_hi = REGNO (operands[0]);
13948 unsigned dest_lo = dest_hi + 1;
13950 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
13951 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
13953 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
13954 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
13955 }
13956 [(set_attr "type" "fp,fp")
13957 (set_attr "length" "4,8")])
13959 (define_insn "unpackv1ti"
13960 [(set (match_operand:DI 0 "register_operand" "=d,d")
13961 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
13962 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
13963 UNSPEC_UNPACK_128BIT))]
13964 "TARGET_VSX"
13965 {
13966 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
13967 return ASM_COMMENT_START " xxpermdi to same register";
13969 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
13970 return "xxpermdi %x0,%x1,%x1,%3";
13971 }
13972 [(set_attr "type" "vecperm")
13973 (set_attr "length" "4")])
13975 (define_insn "packv1ti"
13976 [(set (match_operand:V1TI 0 "register_operand" "=wa")
13977 (unspec:V1TI
13978 [(match_operand:DI 1 "register_operand" "d")
13979 (match_operand:DI 2 "register_operand" "d")]
13980 UNSPEC_PACK_128BIT))]
13981 "TARGET_VSX"
13982 "xxpermdi %x0,%x1,%x2,0"
13983 [(set_attr "type" "vecperm")
13984 (set_attr "length" "4")])
13986 \f
13988 (include "sync.md")
13989 (include "vector.md")
13990 (include "vsx.md")
13991 (include "altivec.md")
13992 (include "spe.md")
13993 (include "dfp.md")
13994 (include "paired.md")
13995 (include "crypto.md")
13996 (include "htm.md")