1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
2 ;; Copyright (C) 2003-2015 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_automaton "ppc40x,ppc40xiu")
21 (define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
22 (define_cpu_unit "iu_40x" "ppc40xiu")
24 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
25 ;; Embedded PowerPC controller
27 ;; Max issue two insns/cycle (includes one branch)
28 (define_insn_reservation "ppc403-load" 2
29 (and (eq_attr "type" "load,load_l,store_c,sync")
30 (eq_attr "cpu" "ppc403,ppc405"))
33 (define_insn_reservation "ppc403-store" 2
34 (and (eq_attr "type" "store")
35 (eq_attr "cpu" "ppc403,ppc405"))
38 (define_insn_reservation "ppc403-integer" 1
39 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
40 (and (eq_attr "type" "add,logical,shift,exts")
41 (eq_attr "dot" "no")))
42 (eq_attr "cpu" "ppc403,ppc405"))
45 (define_insn_reservation "ppc403-two" 1
46 (and (eq_attr "type" "two")
47 (eq_attr "cpu" "ppc403,ppc405"))
50 (define_insn_reservation "ppc403-three" 1
51 (and (eq_attr "type" "three")
52 (eq_attr "cpu" "ppc403,ppc405"))
53 "iu_40x,iu_40x,iu_40x")
55 (define_insn_reservation "ppc403-compare" 3
56 (and (ior (eq_attr "type" "cmp")
57 (and (eq_attr "type" "add,logical,shift,exts")
58 (eq_attr "dot" "yes")))
59 (eq_attr "cpu" "ppc403,ppc405"))
60 "iu_40x,nothing,bpu_40x")
62 (define_insn_reservation "ppc403-imul" 4
63 (and (eq_attr "type" "mul")
64 (eq_attr "cpu" "ppc403"))
67 (define_insn_reservation "ppc405-imul" 5
68 (and (eq_attr "type" "mul")
70 (eq_attr "cpu" "ppc405"))
73 (define_insn_reservation "ppc405-imul2" 3
74 (and (eq_attr "type" "mul")
76 (eq_attr "cpu" "ppc405"))
79 (define_insn_reservation "ppc405-imul3" 2
80 (and (ior (eq_attr "type" "halfmul")
81 (and (eq_attr "type" "mul")
82 (eq_attr "size" "8")))
83 (eq_attr "cpu" "ppc405"))
86 (define_insn_reservation "ppc403-idiv" 33
87 (and (eq_attr "type" "div")
88 (eq_attr "cpu" "ppc403,ppc405"))
91 (define_insn_reservation "ppc403-mfcr" 2
92 (and (eq_attr "type" "mfcr")
93 (eq_attr "cpu" "ppc403,ppc405"))
96 (define_insn_reservation "ppc403-mtcr" 3
97 (and (eq_attr "type" "mtcr")
98 (eq_attr "cpu" "ppc403,ppc405"))
101 (define_insn_reservation "ppc403-mtjmpr" 4
102 (and (eq_attr "type" "mtjmpr")
103 (eq_attr "cpu" "ppc403,ppc405"))
106 (define_insn_reservation "ppc403-mfjmpr" 2
107 (and (eq_attr "type" "mfjmpr")
108 (eq_attr "cpu" "ppc403,ppc405"))
111 (define_insn_reservation "ppc403-jmpreg" 1
112 (and (eq_attr "type" "jmpreg,branch,isync")
113 (eq_attr "cpu" "ppc403,ppc405"))
116 (define_insn_reservation "ppc403-cr" 2
117 (and (eq_attr "type" "cr_logical,delayed_cr")
118 (eq_attr "cpu" "ppc403,ppc405"))
121 (define_insn_reservation "ppc405-float" 11
122 (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
123 (eq_attr "cpu" "ppc405"))