1 ;; Machine Description for Renesas RL78 processors
2 ;; Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
50 (UNS_TRAMPOLINE_INIT 20)
51 (UNS_TRAMPOLINE_UNINIT 21)
52 (UNS_NONLOCAL_GOTO 22)
62 (define_mode_iterator QHI [QI HI])
64 (include "predicates.md")
65 (include "constraints.md")
66 (include "rl78-expand.md")
67 (include "rl78-virt.md")
68 (include "rl78-real.md")
71 ;; Function Prologue/Epilogue Instructions
73 (define_expand "prologue"
76 "rl78_expand_prologue (); DONE;"
79 (define_expand "epilogue"
82 "rl78_expand_epilogue (); DONE;"
85 (define_expand "sibcall_epilogue"
91 (define_insn "rl78_return"
97 (define_insn "interrupt_return"
98 [(unspec_volatile [(return)] UNS_RETI) ]
103 (define_insn "brk_interrupt_return"
104 [(unspec_volatile [(return)] UNS_RETB) ]
109 (define_expand "eh_return"
110 [(match_operand:HI 0 "" "")]
112 "rl78_expand_eh_epilogue (operands[0]);
117 ;; These are used only by prologue/epilogue so it's "safe" to pass
118 ;; virtual registers.
120 [(set (reg:HI SP_REG)
121 (plus:HI (reg:HI SP_REG)
123 (set (mem:HI (reg:HI SP_REG))
124 (match_operand:HI 0 "register_operand" "ABDT,vZint"))]
132 [(set (match_operand:HI 0 "register_operand" "=ABDT,vZint")
133 (mem:HI (reg:HI SP_REG)))
135 (plus:HI (reg:HI SP_REG)
143 (define_insn "sel_rb"
144 [(unspec_volatile [(match_operand 0 "immediate_operand" "")] UNS_SET_RB)]
149 (define_insn "trampoline_init"
150 [(set (match_operand 0 "register_operand" "=Z08W")
151 (unspec_volatile [(match_operand 1 "register_operand" "Z08W")
152 (match_operand 2 "register_operand" "Z10W")
153 ] UNS_TRAMPOLINE_INIT))
156 "call !!___trampoline_init ; %0 <= %1 %2"
159 (define_insn "trampoline_uninit"
160 [(unspec_volatile [(const_int 0)] UNS_TRAMPOLINE_UNINIT)
163 "call !!___trampoline_uninit"
166 ;; GCC restores $fp *before* using it to access values on the *old*
167 ;; frame. So, we do it ourselves, to ensure this is not the case.
168 ;; Note that while %1 is usually a label_ref, we allow for a
169 ;; non-immediate as well.
170 (define_expand "nonlocal_goto"
172 (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore)
173 (match_operand 1 "" "vi") ;; target
174 (match_operand 2 "" "vi") ;; sp
175 (match_operand 3 "" "vi") ;; ?
176 ] UNS_NONLOCAL_GOTO))
179 "emit_jump_insn (gen_nonlocal_goto_insn (operands[0], operands[1], operands[2], operands[3]));
184 (define_insn "nonlocal_goto_insn"
186 (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore)
187 (match_operand 1 "" "vi") ;; target
188 (match_operand 2 "" "vi") ;; sp
189 (match_operand 3 "" "vi") ;; ?
190 ] UNS_NONLOCAL_GOTO))
203 ;;======================================================================
205 ;; "macro" insns - cases where inline chunks of code are more
206 ;; efficient than anything else.
208 (define_expand "addsi3"
209 [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm")
210 (plus:SI (match_operand:SI 1 "general_operand" "vim")
211 (match_operand 2 "general_operand" "vim")))
214 "emit_insn (gen_addsi3_internal_virt (operands[0], operands[1], operands[2]));
218 (define_insn "addsi3_internal_virt"
219 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
220 (plus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
221 (match_operand 2 "general_operand" "vim,vim,vim")))
222 (clobber (reg:HI AX_REG))
223 (clobber (reg:HI BC_REG))
225 "rl78_virt_insns_ok ()"
227 [(set_attr "valloc" "macax")]
230 (define_insn "addsi3_internal_real"
231 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
232 (plus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
233 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
234 (clobber (reg:HI AX_REG))
235 (clobber (reg:HI BC_REG))
237 "rl78_real_insns_ok ()"
239 movw ax,%h1 \;addw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax
240 movw ax,%h1 \;addw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax
241 movw ax,%h1 \;addw ax,%h2 \;movw bc, ax \;movw ax,%H1 \;sknc \;incw ax \;addw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
242 [(set_attr "valloc" "macax")]
245 (define_expand "subsi3"
246 [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm")
247 (minus:SI (match_operand:SI 1 "general_operand" "vim")
248 (match_operand 2 "general_operand" "vim")))
251 "emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2]));
255 (define_insn "subsi3_internal_virt"
256 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
257 (minus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
258 (match_operand 2 "general_operand" "vim,vim,vim")))
259 (clobber (reg:HI AX_REG))
260 (clobber (reg:HI BC_REG))
262 "rl78_virt_insns_ok ()"
264 [(set_attr "valloc" "macax")]
267 (define_insn "subsi3_internal_real"
268 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
269 (minus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
270 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
271 (clobber (reg:HI AX_REG))
272 (clobber (reg:HI BC_REG))
274 "rl78_real_insns_ok ()"
276 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
277 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
278 movw ax,%h1 \;subw ax,%h2 \;movw bc, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
279 [(set_attr "valloc" "macax")]
282 (define_expand "mulqi3"
283 [(set (match_operand:QI 0 "register_operand" "")
284 (mult:QI (match_operand:QI 1 "general_operand" "")
285 (match_operand:QI 2 "nonmemory_operand" "")))
287 "" ; mulu supported by all targets
291 (define_expand "mulhi3"
292 [(set (match_operand:HI 0 "register_operand" "")
293 (mult:HI (match_operand:HI 1 "general_operand" "")
294 (match_operand:HI 2 "nonmemory_operand" "")))
300 (define_expand "mulsi3"
301 [(set (match_operand:SI 0 "register_operand" "=&v")
302 (mult:SI (match_operand:SI 1 "general_operand" "+vim")
303 (match_operand:SI 2 "nonmemory_operand" "vi")))
309 (define_insn "*mulqi3_rl78"
310 [(set (match_operand:QI 0 "register_operand" "=&v")
311 (mult:QI (match_operand:QI 1 "general_operand" "+viU")
312 (match_operand:QI 2 "general_operand" "vi")))
314 "" ; mulu supported by all targets
315 "; mulqi macro %0 = %1 * %2
322 ; end of mulqi macro"
323 ;; [(set_attr "valloc" "macax")]
326 (define_insn "*mulhi3_rl78"
327 [(set (match_operand:HI 0 "register_operand" "=&v")
328 (mult:HI (match_operand:HI 1 "general_operand" "+viU")
329 (match_operand:HI 2 "general_operand" "vi")))
332 "; mulhi macro %0 = %1 * %2
335 mulhu ; bcax = bc * ax
337 ; end of mulhi macro"
338 ;; [(set_attr "valloc" "macax")]
341 (define_insn "*mulhi3_g13"
342 [(set (match_operand:HI 0 "register_operand" "=&v")
343 (mult:HI (match_operand:HI 1 "general_operand" "+viU")
344 (match_operand:HI 2 "general_operand" "vi")))
347 "; mulhi macro %0 = %1 * %2
349 mov !0xf00e8, a ; MDUC
351 movw 0xffff0, ax ; MDAL
353 movw 0xffff2, ax ; MDAH
354 nop ; mdb = mdal * mdah
355 movw ax, 0xffff6 ; MDBL
357 ; end of mulhi macro"
358 ;; [(set_attr "valloc" "umul")]
361 ;; 0xFFFF0 is MACR(L). 0xFFFF2 is MACR(H) but we don't care about it
362 ;; because we're only using the lower 16 bits (which is the upper 16
363 ;; bits of the result).
364 (define_insn "mulsi3_rl78"
365 [(set (match_operand:SI 0 "register_operand" "=&v")
366 (mult:SI (match_operand:SI 1 "general_operand" "+viU")
367 (match_operand:SI 2 "general_operand" "vi")))
370 "; mulsi macro %0 = %1 * %2
373 MULHU ; bcax = bc * ax
379 MACHU ; MACR += bc * ax
382 MACHU ; MACR += bc * ax
385 ; end of mulsi macro"
386 [(set_attr "valloc" "macax")]
389 ;; 0xFFFF0 is MDAL. 0xFFFF2 is MDAH.
390 ;; 0xFFFF6 is MDBL. 0xFFFF4 is MDBH.
391 ;; 0xF00E0 is MDCL. 0xF00E2 is MDCH.
393 ;; Warning: this matches the silicon not the documentation.
394 (define_insn "mulsi3_g13"
395 [(set (match_operand:SI 0 "register_operand" "=&v")
396 (mult:SI (match_operand:SI 1 "general_operand" "viU")
397 (match_operand:SI 2 "general_operand" "viU")))
400 "; mulsi macro %0 = %1 * %2
402 mov !0xf00e8, a ; MDUC
404 movw 0xffff0, ax ; MDAL
406 movw 0xffff2, ax ; MDAH
407 nop ; mdb = mdal * mdah
408 movw ax, 0xffff6 ; MDBL
412 mov !0xf00e8, a ; MDUC
413 movw ax, 0xffff4 ; MDBH
414 movw !0xf00e0, ax ; MDCL
416 movw !0xf00e2, ax ; MDCL
418 movw 0xffff0, ax ; MDAL
420 movw 0xffff2, ax ; MDAH
421 nop ; mdc += mdal * mdah
424 mov !0xf00e8, a ; MDUC
426 movw 0xffff0, ax ; MDAL
428 movw 0xffff2, ax ; MDAH
429 nop ; mdc += mdal * mdah
430 nop ; Additional nop for MAC
431 movw ax, !0xf00e0 ; MDCL
433 ; end of mulsi macro"
434 [(set_attr "valloc" "macax")]
437 (define_expand "es_addr"
438 [(unspec:SI [(reg:QI ES_REG)
439 (match_operand:HI 0 "" "")