1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005-2012 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/rs6000/rs6000-opts.h
25 ;; ISA flag bits (on/off)
27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
30 HOST_WIDE_INT x_rs6000_isa_flags
32 ;; Miscellaneous flag bits that were set explicitly by the user
34 HOST_WIDE_INT x_rs6000_isa_flags_explicit
38 enum processor_type rs6000_cpu = PROCESSOR_PPC603
40 ;; Always emit branch hint bits.
42 unsigned char rs6000_always_hint
44 ;; Schedule instructions for group formation.
46 unsigned char rs6000_sched_groups
48 ;; Align branch targets.
50 unsigned char rs6000_align_branch_targets
52 ;; Support for -msched-costly-dep option.
54 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
56 ;; Support for -minsert-sched-nops option.
58 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
60 ;; Non-zero to allow overriding loop alignment.
62 unsigned char can_override_loop_align
64 ;; Which small data model to use (for System V targets only)
66 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
68 ;; Bit size of immediate TLS offsets and string from which it is decoded.
70 int rs6000_tls_size = 32
72 ;; ABI enumeration available for subtarget to use.
74 enum rs6000_abi rs6000_current_abi = ABI_NONE
76 ;; Type of traceback to use.
78 enum rs6000_traceback_type rs6000_traceback = traceback_default
80 ;; Control alignment for fields within structures.
82 unsigned char rs6000_alignment_flags
84 ;; Code model for 64-bit linux.
86 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
88 ;; What type of reciprocal estimation instructions to generate
90 unsigned int rs6000_recip_control
92 ;; Mask of what builtin functions are allowed
94 HOST_WIDE_INT rs6000_builtin_mask
98 unsigned int rs6000_debug
100 ;; This option existed in the past, but now is always on.
102 Target RejectNegative Undocumented Ignore
105 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
106 Use PowerPC-64 instruction set
109 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
110 Use PowerPC General Purpose group optional instructions
113 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
114 Use PowerPC Graphics group optional instructions
117 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
118 Use PowerPC V2.01 single field mfcr instruction
121 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
122 Use PowerPC V2.02 popcntb instruction
125 Target Report Mask(FPRND) Var(rs6000_isa_flags)
126 Use PowerPC V2.02 floating point rounding instructions
129 Target Report Mask(CMPB) Var(rs6000_isa_flags)
130 Use PowerPC V2.05 compare bytes instruction
133 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
134 Use extended PowerPC V2.05 move floating point to/from GPR instructions
137 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
138 Use AltiVec instructions
141 Target Report Mask(DFP) Var(rs6000_isa_flags)
142 Use decimal floating point instructions
145 Target Report Mask(MULHW) Var(rs6000_isa_flags)
146 Use 4xx half-word multiply instructions
149 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
150 Use 4xx string-search dlmzb instruction
153 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
154 Generate load/store multiple instructions
157 Target Report Mask(STRING) Var(rs6000_isa_flags)
158 Generate string instructions for block moves
161 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
162 Do not use hardware floating point
165 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
166 Use hardware floating point
169 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
170 Use PowerPC V2.06 popcntd instruction
173 Target Report Var(TARGET_FRIZ) Init(-1) Save
174 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions
177 Target RejectNegative Joined Var(rs6000_veclibabi_name)
178 Vector library ABI to use
181 Target Report Mask(VSX) Var(rs6000_isa_flags)
182 Use vector/scalar (VSX) instructions
185 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
186 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
189 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
190 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
193 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
194 ; If -mvsx, set alignment to 128 bits instead of 32/64
197 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
198 ; Allow/disallow the movmisalign in DF/DI vectors
201 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
202 ; Allow/disallow permutation of DF/DI vectors
205 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
206 ; Explicitly set/unset whether rs6000_sched_groups is set
209 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
210 ; Explicitly set/unset whether rs6000_always_hint is set
212 malign-branch-targets
213 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
214 ; Explicitly set/unset whether rs6000_align_branch_targets is set
217 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
218 ; Explicitly control whether we vectorize the builtins or not.
221 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
222 Do not generate load/store with update instructions
225 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
226 Generate load/store with update instructions
229 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
230 Do not load the PIC register in function prologues
232 mavoid-indexed-addresses
233 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
234 Avoid generation of indexed load/store instructions when possible
237 Target Report Var(tls_markers) Init(1) Save
238 Mark __tls_get_addr calls with argument info
241 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
244 Target Report Var(TARGET_SCHED_PROLOG) Save
245 Schedule the start and end of the procedure
248 Target Report RejectNegative Var(aix_struct_return) Save
249 Return all structures in memory (AIX default)
252 Target Report RejectNegative Var(aix_struct_return,0) Save
253 Return small structures in registers (SVR4 default)
256 Target Report Var(TARGET_XL_COMPAT) Save
257 Conform more closely to IBM XLC semantics
261 Generate software reciprocal divide and square root for better throughput.
264 Target Report RejectNegative Joined Var(rs6000_recip_name)
265 Generate software reciprocal divide and square root for better throughput.
268 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
269 Assume that the reciprocal estimate instructions provide more accuracy.
272 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
273 Do not place floating point constants in TOC
276 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
277 Place floating point constants in TOC
280 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
281 Do not place symbol+offset constants in TOC
284 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
285 Place symbol+offset constants in TOC
287 ; Output only one TOC entry per module. Normally linking fails if
288 ; there are more than 16K unique variables/constants in an executable. With
289 ; this option, linking fails only if there are more than 16K modules, or
290 ; if there are more than 16K unique variables/constant in a single module.
292 ; This is at the cost of having 2 extra loads and one extra store per
293 ; function, and one less allocable register.
295 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
296 Use only one TOC entry per procedure
300 Put everything in the regular TOC
303 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
304 Generate VRSAVE instructions when generating AltiVec code
307 Target RejectNegative Alias(mvrsave) NegativeAlias
308 Deprecated option. Use -mno-vrsave instead
311 Target RejectNegative Alias(mvrsave)
312 Deprecated option. Use -mvrsave instead
314 mblock-move-inline-limit=
315 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
316 Specify how many bytes should be moved inline before calling out to memcpy/memmove
319 Target Report Mask(ISEL) Var(rs6000_isa_flags)
320 Generate isel instructions
323 Target RejectNegative Alias(misel) NegativeAlias
324 Deprecated option. Use -mno-isel instead
327 Target RejectNegative Alias(misel)
328 Deprecated option. Use -misel instead
331 Target Var(rs6000_spe) Save
332 Generate SPE SIMD instructions on E500
335 Target Var(rs6000_paired_float) Save
336 Generate PPC750CL paired-single instructions
339 Target RejectNegative Alias(mspe) NegativeAlias
340 Deprecated option. Use -mno-spe instead
343 Target RejectNegative Alias(mspe)
344 Deprecated option. Use -mspe instead
347 Target RejectNegative Joined
348 -mdebug= Enable debug output
351 Target RejectNegative Var(rs6000_altivec_abi) Save
352 Use the AltiVec ABI extensions
355 Target RejectNegative Var(rs6000_altivec_abi, 0)
356 Do not use the AltiVec ABI extensions
359 Target RejectNegative Var(rs6000_spe_abi) Save
360 Use the SPE ABI extensions
363 Target RejectNegative Var(rs6000_spe_abi, 0)
364 Do not use the SPE ABI extensions
366 ; These are here for testing during development only, do not document
367 ; in the manual please.
369 ; If we want Darwin's struct-by-value-in-regs ABI.
371 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
374 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
377 Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save
380 Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)
383 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
384 -mcpu= Use features of and schedule code for given CPU
387 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
388 -mtune= Schedule code for given CPU
391 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
392 -mtraceback= Select full, part, or no traceback table
395 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
398 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
401 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
404 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
407 Target Report Var(rs6000_default_long_calls) Save
408 Avoid all range limits on call instructions
411 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
412 Generate Cell microcode
415 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
416 Warn when a Cell microcoded instruction is emitted
419 Target Var(rs6000_warn_altivec_long) Init(1) Save
420 Warn about deprecated 'vector long ...' AltiVec type usage
423 Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
424 -mfloat-gprs= Select GPR floating point method
427 Name(rs6000_float_gprs) Type(unsigned char)
428 Valid arguments to -mfloat-gprs=:
431 Enum(rs6000_float_gprs) String(yes) Value(1)
434 Enum(rs6000_float_gprs) String(single) Value(1)
437 Enum(rs6000_float_gprs) String(double) Value(2)
440 Enum(rs6000_float_gprs) String(no) Value(0)
443 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
444 -mlong-double-<n> Specify size of long double (64 or 128 bits)
447 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
448 Determine which dependences between insns are considered costly
451 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
452 Specify which post scheduling nop insertion scheme to apply
455 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
456 Specify alignment of structure fields default/natural
459 Name(rs6000_alignment_flags) Type(unsigned char)
460 Valid arguments to -malign-:
463 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
466 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
468 mprioritize-restricted-insns=
469 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
470 Specify scheduling priority for dispatch slot restricted insns
473 Target RejectNegative Var(rs6000_single_float) Save
474 Single-precision floating point unit
477 Target RejectNegative Var(rs6000_double_float) Save
478 Double-precision floating point unit
481 Target RejectNegative Var(rs6000_simple_fpu) Save
482 Floating point unit does not support divide & sqrt
485 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
486 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
489 Name(fpu_type_t) Type(enum fpu_type_t)
492 Enum(fpu_type_t) String(none) Value(FPU_NONE)
495 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
498 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
501 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
504 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
507 Target Var(rs6000_xilinx_fpu) Save
510 mpointers-to-nested-functions
511 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
512 Use/do not use r11 to hold the static link in calls to functions via pointers.
515 Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save
516 Control whether we save the TOC in the prologue for indirect calls or generate the save inline