gcc/config/rs6000/rs6000-cpus.def

   1 /* IBM RS/6000 CPU names..
   2    Copyright (C) 1991-2012 Free Software Foundation, Inc.
   3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* ISA masks.  */
  22 #ifndef ISA_2_1_MASKS
  23 #define ISA_2_1_MASKS           OPTION_MASK_MFCRF
  24 #define ISA_2_2_MASKS           (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
  25 #define ISA_2_4_MASKS           (ISA_2_2_MASKS | OPTION_MASK_FPRND)
  26
  27   /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
  28      ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
  29      fre, fsqrt, etc. were no longer documented as optional.  Group masks by
  30      server and embedded. */
  31 #define ISA_2_5_MASKS_EMBEDDED  (ISA_2_2_MASKS                          \
  32                                  | OPTION_MASK_CMPB                     \
  33                                  | OPTION_MASK_RECIP_PRECISION          \
  34                                  | OPTION_MASK_PPC_GFXOPT               \
  35                                  | OPTION_MASK_PPC_GPOPT)
  36
  37 #define ISA_2_5_MASKS_SERVER    (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
  38
  39   /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
  40      altivec is a win so enable it.  */
  41 #define ISA_2_6_MASKS_EMBEDDED  (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
  42 #define ISA_2_6_MASKS_SERVER    (ISA_2_5_MASKS_SERVER                   \
  43                                  | OPTION_MASK_POPCNTD                  \
  44                                  | OPTION_MASK_ALTIVEC                  \
  45                                  | OPTION_MASK_VSX)
  46
  47 #define POWERPC_7400_MASK       (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
  48
  49 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
  50 #define POWERPC_MASKS           (OPTION_MASK_ALTIVEC                    \
  51                                  | OPTION_MASK_CMPB                     \
  52                                  | OPTION_MASK_DFP                      \
  53                                  | OPTION_MASK_DLMZB                    \
  54                                  | OPTION_MASK_FPRND                    \
  55                                  | OPTION_MASK_ISEL                     \
  56                                  | OPTION_MASK_MFCRF                    \
  57                                  | OPTION_MASK_MFPGPR                   \
  58                                  | OPTION_MASK_MULHW                    \
  59                                  | OPTION_MASK_NO_UPDATE                \
  60                                  | OPTION_MASK_POPCNTB                  \
  61                                  | OPTION_MASK_POPCNTD                  \
  62                                  | OPTION_MASK_POWERPC64                \
  63                                  | OPTION_MASK_PPC_GFXOPT               \
  64                                  | OPTION_MASK_PPC_GPOPT                \
  65                                  | OPTION_MASK_RECIP_PRECISION          \
  66                                  | OPTION_MASK_SOFT_FLOAT               \
  67                                  | OPTION_MASK_STRICT_ALIGN             \
  68                                  | OPTION_MASK_VSX)
  69
  70 #endif
  71
  72 /* This table occasionally claims that a processor does not support a
  73    particular feature even though it does, but the feature is slower than the
  74    alternative.  Thus, it shouldn't be relied on as a complete description of
  75    the processor's support.
  76
  77    Please keep this list in order, and don't forget to update the documentation
  78    in invoke.texi when adding a new processor or flag.
  79
  80    Before including this file, define a macro:
  81
  82    RS6000_CPU (NAME, CPU, FLAGS)
  83
  84    where the arguments are the fields of struct rs6000_ptt.  */
  85
  86 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
  87 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
  88 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
  89 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
  90 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
  91 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
  92 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
  93 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
  94 RS6000_CPU ("476", PROCESSOR_PPC476,
  95             MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
  96             | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
  97 RS6000_CPU ("476fp", PROCESSOR_PPC476,
  98             MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
  99             | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 100 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 101 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
 102 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 103 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 104 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 105 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
 106 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
 107 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
 108 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 109 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 110 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
 111 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
 112 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 113 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 114 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 115 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 116 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
 117 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
 118 RS6000_CPU ("a2", PROCESSOR_PPCA2,
 119             MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
 120             | MASK_NO_UPDATE)
 121 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
 122 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
 123 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
 124 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
 125             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 126 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
 127             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 128 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
 129             | MASK_MFCRF | MASK_ISEL)
 130 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 131 RS6000_CPU ("970", PROCESSOR_POWER4,
 132             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 133 RS6000_CPU ("cell", PROCESSOR_CELL,
 134             POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 135 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
 136 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 137 RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
 138 RS6000_CPU ("G5", PROCESSOR_POWER4,
 139             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 140 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
 141 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 142 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
 143             | MASK_PPC_GFXOPT | MASK_MFCRF)
 144 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 145             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
 146 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 147             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
 148 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 149             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 150             | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 151 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 152             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 153             | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
 154 RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
 155             POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
 156             | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
 157             | MASK_VSX | MASK_RECIP_PRECISION)
 158 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 159 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
 160 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)