gcc/config/avr/avr.h

   1 /* Definitions of target machine for GNU compiler,
   2    for ATMEL AVR at90s8515, ATmega103/103L, ATmega603/603L microcontrollers.
   3    Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   4    2008, 2009, 2010, 2011
   5    Free Software Foundation, Inc.
   6    Contributed by Denis Chertykov (chertykov@gmail.com)
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 3, or (at your option)
  13 any later version.
  14
  15 GCC is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not see
  22 <http://www.gnu.org/licenses/>.  */
  23
  24 /* Names to predefine in the preprocessor for this target machine.  */
  25
  26 struct base_arch_s
  27 {
  28   /* Assembler only.  */
  29   int asm_only;
  30
  31   /* Core have 'MUL*' instructions.  */
  32   int have_mul;
  33
  34   /* Core have 'CALL' and 'JMP' instructions.  */
  35   int have_jmp_call;
  36
  37   /* Core have 'MOVW' and 'LPM Rx,Z' instructions.  */
  38   int have_movw_lpmx;
  39
  40   /* Core have 'ELPM' instructions.  */
  41   int have_elpm;
  42
  43   /* Core have 'ELPM Rx,Z' instructions.  */
  44   int have_elpmx;
  45
  46   /* Core have 'EICALL' and 'EIJMP' instructions.  */
  47   int have_eijmp_eicall;
  48
  49   /* Reserved for xmega architecture.  */
  50   int reserved;
  51
  52   /* Reserved for xmega architecture.  */
  53   int reserved2;
  54
  55   /* Default start of data section address for architecture.  */
  56   int default_data_section_start;
  57
  58   /* Offset between SFR address and RAM address:
  59      SFR-address = RAM-address - sfr_offset  */
  60   int sfr_offset;
  61
  62   /* Number of 64k segments in the flash.  */
  63   int n_segments;
  64
  65   const char *const macro;
  66
  67   /* Architecture name.  */
  68   const char *const arch_name;
  69 };
  70
  71 /* These names are used as the index into the avr_arch_types[] table
  72    above.  */
  73
  74 enum avr_arch
  75 {
  76   ARCH_UNKNOWN,
  77   ARCH_AVR1,
  78   ARCH_AVR2,
  79   ARCH_AVR25,
  80   ARCH_AVR3,
  81   ARCH_AVR31,
  82   ARCH_AVR35,
  83   ARCH_AVR4,
  84   ARCH_AVR5,
  85   ARCH_AVR51,
  86   ARCH_AVR6
  87 };
  88
  89 struct mcu_type_s {
  90   /* Device name.  */
  91   const char *const name;
  92
  93   /* Index in avr_arch_types[].  */
  94   int arch;
  95
  96   /* Must lie outside user's namespace.  NULL == no macro.  */
  97   const char *const macro;
  98
  99   /* Stack pointer have 8 bits width.  */
 100   int short_sp;
 101
 102   /* Some AVR devices have a core erratum when skipping a 2-word instruction.
 103      Skip instructions are:  SBRC, SBRS, SBIC, SBIS, CPSE.
 104      Problems will occur with return address is IRQ executes during the
 105      skip sequence.
 106
 107      A support ticket from Atmel returned the following information:
 108
 109          Subject: (ATTicket:644469) On AVR skip-bug core Erratum
 110          From: avr@atmel.com                    Date: 2011-07-27
 111          (Please keep the subject when replying to this mail)
 112
 113          This errata exists only in AT90S8515 and ATmega103 devices.
 114
 115          For information please refer the following respective errata links
 116             http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf
 117             http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf  */
 118
 119   /* Core Erratum:  Must not skip 2-word instruction.  */
 120   int errata_skip;
 121
 122   /* Start of data section.  */
 123   int data_section_start;
 124
 125   /* Name of device library.  */
 126   const char *const library_name;
 127 };
 128
 129 /* Preprocessor macros to define depending on MCU type.  */
 130 extern const char *avr_extra_arch_macro;
 131 extern const struct base_arch_s *avr_current_arch;
 132 extern const struct mcu_type_s *avr_current_device;
 133 extern const struct mcu_type_s avr_mcu_types[];
 134 extern const struct base_arch_s avr_arch_types[];
 135
 136 typedef struct
 137 {
 138   /* Id of the address space as used in c_register_addr_space */
 139   unsigned char id;
 140
 141   /* Flavour of memory: 0 = RAM, 1 = Flash */
 142   int memory_class;
 143
 144   /* Width of pointer (in bytes) */
 145   int pointer_size;
 146
 147   /* Name of the address space as visible to the user */
 148   const char *name;
 149
 150   /* Segment (i.e. 64k memory chunk) number.  */
 151   int segment;
 152 } avr_addrspace_t;
 153
 154 extern const avr_addrspace_t avr_addrspace[];
 155
 156 /* Known address spaces */
 157
 158 enum
 159   {
 160     ADDR_SPACE_RAM,
 161     ADDR_SPACE_PGM,
 162     ADDR_SPACE_PGM1,
 163     ADDR_SPACE_PGM2,
 164     ADDR_SPACE_PGM3,
 165     ADDR_SPACE_PGM4,
 166     ADDR_SPACE_PGM5,
 167     ADDR_SPACE_PGMX
 168   };
 169
 170 #define TARGET_CPU_CPP_BUILTINS()       avr_cpu_cpp_builtins (pfile)
 171
 172 #define AVR_HAVE_JMP_CALL (avr_current_arch->have_jmp_call && !TARGET_SHORT_CALLS)
 173 #define AVR_HAVE_MUL (avr_current_arch->have_mul)
 174 #define AVR_HAVE_MOVW (avr_current_arch->have_movw_lpmx)
 175 #define AVR_HAVE_LPMX (avr_current_arch->have_movw_lpmx)
 176 #define AVR_HAVE_ELPM (avr_current_arch->have_elpm)
 177 #define AVR_HAVE_ELPMX (avr_current_arch->have_elpmx)
 178 #define AVR_HAVE_RAMPZ (avr_current_arch->have_elpm)
 179 #define AVR_HAVE_EIJMP_EICALL (avr_current_arch->have_eijmp_eicall)
 180 #define AVR_HAVE_8BIT_SP (avr_current_device->short_sp || TARGET_TINY_STACK)
 181
 182 #define AVR_2_BYTE_PC (!AVR_HAVE_EIJMP_EICALL)
 183 #define AVR_3_BYTE_PC (AVR_HAVE_EIJMP_EICALL)
 184
 185 #define BITS_BIG_ENDIAN 0
 186 #define BYTES_BIG_ENDIAN 0
 187 #define WORDS_BIG_ENDIAN 0
 188
 189 #ifdef IN_LIBGCC2
 190 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits).  */
 191 #define UNITS_PER_WORD 4
 192 #else
 193 /* Width of a word, in units (bytes).  */
 194 #define UNITS_PER_WORD 1
 195 #endif
 196
 197 #define POINTER_SIZE 16
 198
 199
 200 /* Maximum sized of reasonable data type
 201    DImode or Dfmode ...  */
 202 #define MAX_FIXED_MODE_SIZE 32
 203
 204 #define PARM_BOUNDARY 8
 205
 206 #define FUNCTION_BOUNDARY 8
 207
 208 #define EMPTY_FIELD_BOUNDARY 8
 209
 210 /* No data type wants to be aligned rounder than this.  */
 211 #define BIGGEST_ALIGNMENT 8
 212
 213 #define TARGET_VTABLE_ENTRY_ALIGN 8
 214
 215 #define STRICT_ALIGNMENT 0
 216
 217 #define INT_TYPE_SIZE (TARGET_INT8 ? 8 : 16)
 218 #define SHORT_TYPE_SIZE (INT_TYPE_SIZE == 8 ? INT_TYPE_SIZE : 16)
 219 #define LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 16 : 32)
 220 #define LONG_LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 32 : 64)
 221 #define FLOAT_TYPE_SIZE 32
 222 #define DOUBLE_TYPE_SIZE 32
 223 #define LONG_DOUBLE_TYPE_SIZE 32
 224
 225 #define DEFAULT_SIGNED_CHAR 1
 226
 227 #define SIZE_TYPE (INT_TYPE_SIZE == 8 ? "long unsigned int" : "unsigned int")
 228 #define PTRDIFF_TYPE (INT_TYPE_SIZE == 8 ? "long int" :"int")
 229
 230 #define WCHAR_TYPE_SIZE 16
 231
 232 #define FIRST_PSEUDO_REGISTER 36
 233
 234 #define FIXED_REGISTERS {\
 235   1,1,/* r0 r1 */\
 236   0,0,/* r2 r3 */\
 237   0,0,/* r4 r5 */\
 238   0,0,/* r6 r7 */\
 239   0,0,/* r8 r9 */\
 240   0,0,/* r10 r11 */\
 241   0,0,/* r12 r13 */\
 242   0,0,/* r14 r15 */\
 243   0,0,/* r16 r17 */\
 244   0,0,/* r18 r19 */\
 245   0,0,/* r20 r21 */\
 246   0,0,/* r22 r23 */\
 247   0,0,/* r24 r25 */\
 248   0,0,/* r26 r27 */\
 249   0,0,/* r28 r29 */\
 250   0,0,/* r30 r31 */\
 251   1,1,/*  STACK */\
 252   1,1 /* arg pointer */  }
 253
 254 #define CALL_USED_REGISTERS {                   \
 255   1,1,/* r0 r1 */                               \
 256     0,0,/* r2 r3 */                             \
 257     0,0,/* r4 r5 */                             \
 258     0,0,/* r6 r7 */                             \
 259     0,0,/* r8 r9 */                             \
 260     0,0,/* r10 r11 */                           \
 261     0,0,/* r12 r13 */                           \
 262     0,0,/* r14 r15 */                           \
 263     0,0,/* r16 r17 */                           \
 264     1,1,/* r18 r19 */                           \
 265     1,1,/* r20 r21 */                           \
 266     1,1,/* r22 r23 */                           \
 267     1,1,/* r24 r25 */                           \
 268     1,1,/* r26 r27 */                           \
 269     0,0,/* r28 r29 */                           \
 270     1,1,/* r30 r31 */                           \
 271     1,1,/*  STACK */                            \
 272     1,1 /* arg pointer */  }
 273
 274 #define REG_ALLOC_ORDER {                       \
 275     24,25,                                      \
 276     18,19,                                      \
 277     20,21,                                      \
 278     22,23,                                      \
 279     30,31,                                      \
 280     26,27,                                      \
 281     28,29,                                      \
 282     17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,    \
 283     0,1,                                        \
 284     32,33,34,35                                 \
 285     }
 286
 287 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
 288
 289
 290 #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 291
 292 #define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
 293
 294 #define MODES_TIEABLE_P(MODE1, MODE2) 1
 295
 296 enum reg_class {
 297   NO_REGS,
 298   R0_REG,                       /* r0 */
 299   POINTER_X_REGS,               /* r26 - r27 */
 300   POINTER_Y_REGS,               /* r28 - r29 */
 301   POINTER_Z_REGS,               /* r30 - r31 */
 302   STACK_REG,                    /* STACK */
 303   BASE_POINTER_REGS,            /* r28 - r31 */
 304   POINTER_REGS,                 /* r26 - r31 */
 305   ADDW_REGS,                    /* r24 - r31 */
 306   SIMPLE_LD_REGS,               /* r16 - r23 */
 307   LD_REGS,                      /* r16 - r31 */
 308   NO_LD_REGS,                   /* r0 - r15 */
 309   GENERAL_REGS,                 /* r0 - r31 */
 310   ALL_REGS, LIM_REG_CLASSES
 311 };
 312
 313
 314 #define N_REG_CLASSES (int)LIM_REG_CLASSES
 315
 316 #define REG_CLASS_NAMES {                                       \
 317                  "NO_REGS",                                     \
 318                    "R0_REG",    /* r0 */                        \
 319                    "POINTER_X_REGS", /* r26 - r27 */            \
 320                    "POINTER_Y_REGS", /* r28 - r29 */            \
 321                    "POINTER_Z_REGS", /* r30 - r31 */            \
 322                    "STACK_REG", /* STACK */                     \
 323                    "BASE_POINTER_REGS", /* r28 - r31 */         \
 324                    "POINTER_REGS", /* r26 - r31 */              \
 325                    "ADDW_REGS", /* r24 - r31 */                 \
 326                    "SIMPLE_LD_REGS", /* r16 - r23 */            \
 327                    "LD_REGS",   /* r16 - r31 */                 \
 328                    "NO_LD_REGS", /* r0 - r15 */                 \
 329                    "GENERAL_REGS", /* r0 - r31 */               \
 330                    "ALL_REGS" }
 331
 332 #define REG_CLASS_CONTENTS {                                            \
 333   {0x00000000,0x00000000},      /* NO_REGS */                           \
 334   {0x00000001,0x00000000},      /* R0_REG */                            \
 335   {3 << REG_X,0x00000000},      /* POINTER_X_REGS, r26 - r27 */         \
 336   {3 << REG_Y,0x00000000},      /* POINTER_Y_REGS, r28 - r29 */         \
 337   {3 << REG_Z,0x00000000},      /* POINTER_Z_REGS, r30 - r31 */         \
 338   {0x00000000,0x00000003},      /* STACK_REG, STACK */                  \
 339   {(3 << REG_Y) | (3 << REG_Z),                                         \
 340      0x00000000},               /* BASE_POINTER_REGS, r28 - r31 */      \
 341   {(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z),                          \
 342      0x00000000},               /* POINTER_REGS, r26 - r31 */           \
 343   {(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z) | (3 << REG_W),           \
 344      0x00000000},               /* ADDW_REGS, r24 - r31 */              \
 345   {0x00ff0000,0x00000000},      /* SIMPLE_LD_REGS r16 - r23 */          \
 346   {(3 << REG_X)|(3 << REG_Y)|(3 << REG_Z)|(3 << REG_W)|(0xff << 16),    \
 347      0x00000000},       /* LD_REGS, r16 - r31 */                        \
 348   {0x0000ffff,0x00000000},      /* NO_LD_REGS  r0 - r15 */              \
 349   {0xffffffff,0x00000000},      /* GENERAL_REGS, r0 - r31 */            \
 350   {0xffffffff,0x00000003}       /* ALL_REGS */                          \
 351 }
 352
 353 #define REGNO_REG_CLASS(R) avr_regno_reg_class(R)
 354
 355 #define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code)   \
 356   avr_mode_code_base_reg_class (mode, as, outer_code, index_code)
 357
 358 #define INDEX_REG_CLASS NO_REGS
 359
 360 #define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, index_code) \
 361   avr_regno_mode_code_ok_for_base_p (num, mode, as, outer_code, index_code)
 362
 363 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 364
 365 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 366
 367 #define STACK_PUSH_CODE POST_DEC
 368
 369 #define STACK_GROWS_DOWNWARD
 370
 371 #define STARTING_FRAME_OFFSET avr_starting_frame_offset()
 372
 373 #define STACK_POINTER_OFFSET 1
 374
 375 #define FIRST_PARM_OFFSET(FUNDECL) 0
 376
 377 #define STACK_BOUNDARY 8
 378
 379 #define STACK_POINTER_REGNUM 32
 380
 381 #define FRAME_POINTER_REGNUM REG_Y
 382
 383 #define ARG_POINTER_REGNUM 34
 384
 385 #define STATIC_CHAIN_REGNUM 2
 386
 387 #define ELIMINABLE_REGS {                                       \
 388       {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},               \
 389         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}            \
 390        ,{FRAME_POINTER_REGNUM+1,STACK_POINTER_REGNUM+1}}
 391
 392 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                    \
 393   OFFSET = avr_initial_elimination_offset (FROM, TO)
 394
 395 #define RETURN_ADDR_RTX(count, tem) avr_return_addr_rtx (count, tem)
 396
 397 /* Don't use Push rounding. expr.c: emit_single_push_insn is broken
 398    for POST_DEC targets (PR27386).  */
 399 /*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
 400
 401 typedef struct avr_args {
 402   int nregs;                    /* # registers available for passing */
 403   int regno;                    /* next available register number */
 404 } CUMULATIVE_ARGS;
 405
 406 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 407   init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
 408
 409 #define FUNCTION_ARG_REGNO_P(r) function_arg_regno_p(r)
 410
 411 #define DEFAULT_PCC_STRUCT_RETURN 0
 412
 413 #define EPILOGUE_USES(REGNO) avr_epilogue_uses(REGNO)
 414
 415 #define HAVE_POST_INCREMENT 1
 416 #define HAVE_PRE_DECREMENT 1
 417
 418 #define MAX_REGS_PER_ADDRESS 1
 419
 420 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN)          \
 421   do {                                                                  \
 422     rtx new_x = avr_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \
 423                                                ADDR_TYPE (TYPE),        \
 424                                                IND_L, make_memloc);     \
 425     if (new_x)                                                          \
 426       {                                                                 \
 427         X = new_x;                                                      \
 428         goto WIN;                                                       \
 429       }                                                                 \
 430   } while (0)
 431
 432 #define BRANCH_COST(speed_p, predictable_p) avr_branch_cost
 433
 434 #define SLOW_BYTE_ACCESS 0
 435
 436 #define NO_FUNCTION_CSE
 437
 438 #define REGISTER_TARGET_PRAGMAS()                                       \
 439   do {                                                                  \
 440     avr_register_target_pragmas();                                      \
 441   } while (0)
 442
 443 #define TEXT_SECTION_ASM_OP "\t.text"
 444
 445 #define DATA_SECTION_ASM_OP "\t.data"
 446
 447 #define BSS_SECTION_ASM_OP "\t.section .bss"
 448
 449 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
 450    There are no shared libraries on this target, and these sections are
 451    placed in the read-only program memory, so they are not writable.  */
 452
 453 #undef CTORS_SECTION_ASM_OP
 454 #define CTORS_SECTION_ASM_OP "\t.section .ctors,\"a\",@progbits"
 455
 456 #undef DTORS_SECTION_ASM_OP
 457 #define DTORS_SECTION_ASM_OP "\t.section .dtors,\"a\",@progbits"
 458
 459 #define TARGET_ASM_CONSTRUCTOR avr_asm_out_ctor
 460
 461 #define TARGET_ASM_DESTRUCTOR avr_asm_out_dtor
 462
 463 #define SUPPORTS_INIT_PRIORITY 0
 464
 465 #define JUMP_TABLES_IN_TEXT_SECTION 0
 466
 467 #define ASM_COMMENT_START " ; "
 468
 469 #define ASM_APP_ON "/* #APP */\n"
 470
 471 #define ASM_APP_OFF "/* #NOAPP */\n"
 472
 473 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '\n' || ((C) == '$'))
 474
 475 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
 476   avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, false)
 477
 478 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
 479   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
 480
 481 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN)  \
 482   avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, true)
 483
 484 /* Globalizing directive for a label.  */
 485 #define GLOBAL_ASM_OP ".global\t"
 486
 487 #define SUPPORTS_WEAK 1
 488
 489 #define HAS_INIT_SECTION 1
 490
 491 #define REGISTER_NAMES {                                \
 492   "r0","r1","r2","r3","r4","r5","r6","r7",              \
 493     "r8","r9","r10","r11","r12","r13","r14","r15",      \
 494     "r16","r17","r18","r19","r20","r21","r22","r23",    \
 495     "r24","r25","r26","r27","r28","r29","r30","r31",    \
 496     "__SP_L__","__SP_H__","argL","argH"}
 497
 498 #define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
 499
 500 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO)      \
 501 {                                               \
 502   gcc_assert (REGNO < 32);                      \
 503   fprintf (STREAM, "\tpush\tr%d", REGNO);       \
 504 }
 505
 506 #define ASM_OUTPUT_REG_POP(STREAM, REGNO)       \
 507 {                                               \
 508   gcc_assert (REGNO < 32);                      \
 509   fprintf (STREAM, "\tpop\tr%d", REGNO);        \
 510 }
 511
 512 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)          \
 513   avr_output_addr_vec_elt(STREAM, VALUE)
 514
 515 #define ASM_OUTPUT_ALIGN(STREAM, POWER)                 \
 516   do {                                                  \
 517       if ((POWER) > 1)                                  \
 518           fprintf (STREAM, "\t.p2align\t%d\n", POWER);  \
 519   } while (0)
 520
 521 #define CASE_VECTOR_MODE HImode
 522
 523 #undef WORD_REGISTER_OPERATIONS
 524
 525 #define MOVE_MAX 4
 526
 527 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 528
 529 #define Pmode HImode
 530
 531 #define FUNCTION_MODE HImode
 532
 533 #define DOLLARS_IN_IDENTIFIERS 0
 534
 535 #define TRAMPOLINE_SIZE 4
 536
 537 /* Store in cc_status the expressions
 538    that the condition codes will describe
 539    after execution of an instruction whose pattern is EXP.
 540    Do not alter them if the instruction would not alter the cc's.  */
 541
 542 #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
 543
 544 /* The add insns don't set overflow in a usable way.  */
 545 #define CC_OVERFLOW_UNUSABLE 01000
 546 /* The mov,and,or,xor insns don't set carry.  That's ok though as the
 547    Z bit is all we need when doing unsigned comparisons on the result of
 548    these insns (since they're always with 0).  However, conditions.h has
 549    CC_NO_OVERFLOW defined for this purpose.  Rename it to something more
 550    understandable.  */
 551 #define CC_NO_CARRY CC_NO_OVERFLOW
 552
 553
 554 /* Output assembler code to FILE to increment profiler label # LABELNO
 555    for profiling a function entry.  */
 556
 557 #define FUNCTION_PROFILER(FILE, LABELNO)  \
 558   fprintf (FILE, "/* profiler %d */", (LABELNO))
 559
 560 #define ADJUST_INSN_LENGTH(INSN, LENGTH) (LENGTH =\
 561                                           adjust_insn_length (INSN, LENGTH))
 562
 563 extern const char *avr_device_to_arch (int argc, const char **argv);
 564 extern const char *avr_device_to_data_start (int argc, const char **argv);
 565 extern const char *avr_device_to_startfiles (int argc, const char **argv);
 566 extern const char *avr_device_to_devicelib (int argc, const char **argv);
 567
 568 #define EXTRA_SPEC_FUNCTIONS \
 569   { "device_to_arch", avr_device_to_arch }, \
 570   { "device_to_data_start", avr_device_to_data_start }, \
 571   { "device_to_startfile", avr_device_to_startfiles }, \
 572   { "device_to_devicelib", avr_device_to_devicelib },
 573
 574 #define CPP_SPEC ""
 575
 576 #define CC1_SPEC ""
 577
 578 #define CC1PLUS_SPEC "%{!frtti:-fno-rtti} \
 579     %{!fenforce-eh-specs:-fno-enforce-eh-specs} \
 580     %{!fexceptions:-fno-exceptions}"
 581 /* A C string constant that tells the GCC driver program options to
 582    pass to `cc1plus'.  */
 583
 584 #define ASM_SPEC "%{mmcu=avr25:-mmcu=avr2;mmcu=avr35:-mmcu=avr3;mmcu=avr31:-mmcu=avr3;mmcu=avr51:-mmcu=avr5;\
 585 mmcu=*:-mmcu=%*}"
 586
 587 #define LINK_SPEC "\
 588 %{mrelax:--relax\
 589          %{mpmem-wrap-around:%{mmcu=at90usb8*:--pmem-wrap-around=8k}\
 590                              %{mmcu=atmega16*:--pmem-wrap-around=16k}\
 591                              %{mmcu=atmega32*|\
 592                                mmcu=at90can32*:--pmem-wrap-around=32k}\
 593                              %{mmcu=atmega64*|\
 594                                mmcu=at90can64*|\
 595                                mmcu=at90usb64*:--pmem-wrap-around=64k}}}\
 596 %:device_to_arch(%{mmcu=*:%*})\
 597 %:device_to_data_start(%{mmcu=*:%*})"
 598
 599 #define LIB_SPEC \
 600   "%{!mmcu=at90s1*:%{!mmcu=attiny11:%{!mmcu=attiny12:%{!mmcu=attiny15:%{!mmcu=attiny28: -lc }}}}}"
 601
 602 #define LIBSTDCXX "gcc"
 603 /* No libstdc++ for now.  Empty string doesn't work.  */
 604
 605 #define LIBGCC_SPEC \
 606   "%{!mmcu=at90s1*:%{!mmcu=attiny11:%{!mmcu=attiny12:%{!mmcu=attiny15:%{!mmcu=attiny28: -lgcc }}}}}"
 607
 608 #define STARTFILE_SPEC "%:device_to_startfile(%{mmcu=*:%*})"
 609
 610 #define ENDFILE_SPEC ""
 611
 612 /* This is the default without any -mmcu=* option (AT90S*).  */
 613 #define MULTILIB_DEFAULTS { "mmcu=avr2" }
 614
 615 #define TEST_HARD_REG_CLASS(CLASS, REGNO) \
 616   TEST_HARD_REG_BIT (reg_class_contents[ (int) (CLASS)], REGNO)
 617
 618 /* Note that the other files fail to use these
 619    in some of the places where they should.  */
 620
 621 #if defined(__STDC__) || defined(ALMOST_STDC)
 622 #define AS2(a,b,c) #a " " #b "," #c
 623 #define AS2C(b,c) " " #b "," #c
 624 #define AS3(a,b,c,d) #a " " #b "," #c "," #d
 625 #define AS1(a,b) #a " " #b
 626 #else
 627 #define AS1(a,b) "a     b"
 628 #define AS2(a,b,c) "a   b,c"
 629 #define AS2C(b,c) " b,c"
 630 #define AS3(a,b,c,d) "a b,c,d"
 631 #endif
 632 #define OUT_AS1(a,b) output_asm_insn (AS1(a,b), operands)
 633 #define OUT_AS2(a,b,c) output_asm_insn (AS2(a,b,c), operands)
 634 #define CR_TAB "\n\t"
 635
 636 #define DWARF2_ADDR_SIZE 4
 637
 638 #define INCOMING_RETURN_ADDR_RTX   avr_incoming_return_addr_rtx ()
 639 #define INCOMING_FRAME_SP_OFFSET   (AVR_3_BYTE_PC ? 3 : 2)
 640
 641 /* The caller's stack pointer value immediately before the call
 642    is one byte below the first argument.  */
 643 #define ARG_POINTER_CFA_OFFSET(FNDECL)  -1
 644
 645 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
 646   avr_hard_regno_rename_ok (OLD_REG, NEW_REG)
 647
 648 /* A C structure for machine-specific, per-function data.
 649    This is added to the cfun structure.  */
 650 struct GTY(()) machine_function
 651 {
 652   /* 'true' - if current function is a naked function.  */
 653   int is_naked;
 654
 655   /* 'true' - if current function is an interrupt function
 656      as specified by the "interrupt" attribute.  */
 657   int is_interrupt;
 658
 659   /* 'true' - if current function is a signal function
 660      as specified by the "signal" attribute.  */
 661   int is_signal;
 662
 663   /* 'true' - if current function is a 'task' function
 664      as specified by the "OS_task" attribute.  */
 665   int is_OS_task;
 666
 667   /* 'true' - if current function is a 'main' function
 668      as specified by the "OS_main" attribute.  */
 669   int is_OS_main;
 670
 671   /* Current function stack size.  */
 672   int stack_usage;
 673
 674   /* 'true' if a callee might be tail called */
 675   int sibcall_fails;
 676 };
 677
 678 /* AVR does not round pushes, but the existance of this macro is
 679    required in order for pushes to be generated.  */
 680 #define PUSH_ROUNDING(X)        (X)
 681
 682 #define ACCUMULATE_OUTGOING_ARGS avr_accumulate_outgoing_args()
 683
 684 #define INIT_EXPANDERS avr_init_expanders()