1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94 #include "insn-attr.h"
96 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
104 #include "valtrack.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 typedef struct reg_stat_struct
{
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* Record the luid of the last insn that invalidated memory
258 (anything that writes memory, and subroutine calls, but not pushes). */
260 static int mem_last_set
;
262 /* Record the luid of the last CALL_INSN
263 so we can tell whether a potential combination crosses any calls. */
265 static int last_call_luid
;
267 /* When `subst' is called, this is the insn that is being modified
268 (by combining in a previous insn). The PATTERN of this insn
269 is still the old pattern partially modified and it should not be
270 looked at, but this may be used to examine the successors of the insn
271 to judge whether a simplification is valid. */
273 static rtx subst_insn
;
275 /* This is the lowest LUID that `subst' is currently dealing with.
276 get_last_value will not return a value if the register was set at or
277 after this LUID. If not for this mechanism, we could get confused if
278 I2 or I1 in try_combine were an insn that used the old value of a register
279 to obtain a new value. In that case, we might erroneously get the
280 new value of the register when we wanted the old one. */
282 static int subst_low_luid
;
284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
285 must consider all these registers to be always live. */
287 static HARD_REG_SET newpat_used_regs
;
289 /* This is an insn to which a LOG_LINKS entry has been added. If this
290 insn is the earlier than I2 or I3, combine should rescan starting at
293 static rtx added_links_insn
;
295 /* Basic block in which we are performing combines. */
296 static basic_block this_basic_block
;
297 static bool optimize_this_for_speed_p
;
300 /* Length of the currently allocated uid_insn_cost array. */
302 static int max_uid_known
;
304 /* The following array records the insn_rtx_cost for every insn
305 in the instruction stream. */
307 static int *uid_insn_cost
;
309 /* The following array records the LOG_LINKS for every insn in the
310 instruction stream as struct insn_link pointers. */
314 struct insn_link
*next
;
317 static struct insn_link
**uid_log_links
;
319 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
320 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
322 #define FOR_EACH_LOG_LINK(L, INSN) \
323 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
325 /* Links for LOG_LINKS are allocated from this obstack. */
327 static struct obstack insn_link_obstack
;
329 /* Allocate a link. */
331 static inline struct insn_link
*
332 alloc_insn_link (rtx insn
, struct insn_link
*next
)
335 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
336 sizeof (struct insn_link
));
342 /* Incremented for each basic block. */
344 static int label_tick
;
346 /* Reset to label_tick for each extended basic block in scanning order. */
348 static int label_tick_ebb_start
;
350 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
351 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
353 static enum machine_mode nonzero_bits_mode
;
355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
356 be safely used. It is zero while computing them and after combine has
357 completed. This former test prevents propagating values based on
358 previously set values, which can be incorrect if a variable is modified
361 static int nonzero_sign_valid
;
364 /* Record one modification to rtl structure
365 to be undone by storing old_contents into *where. */
367 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
373 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
374 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
378 num_undo says how many are currently recorded.
380 other_insn is nonzero if we have modified some other insn in the process
381 of working on subst_insn. It must be verified too. */
390 static struct undobuf undobuf
;
392 /* Number of times the pseudo being substituted for
393 was found and replaced. */
395 static int n_occurrences
;
397 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
399 unsigned HOST_WIDE_INT
,
400 unsigned HOST_WIDE_INT
*);
401 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
403 unsigned int, unsigned int *);
404 static void do_SUBST (rtx
*, rtx
);
405 static void do_SUBST_INT (int *, int);
406 static void init_reg_last (void);
407 static void setup_incoming_promotions (rtx
);
408 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
409 static int cant_combine_insn_p (rtx
);
410 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
411 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
412 static int contains_muldiv (rtx
);
413 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
414 static void undo_all (void);
415 static void undo_commit (void);
416 static rtx
*find_split_point (rtx
*, rtx
, bool);
417 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
418 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
419 static rtx
simplify_if_then_else (rtx
);
420 static rtx
simplify_set (rtx
);
421 static rtx
simplify_logical (rtx
);
422 static rtx
expand_compound_operation (rtx
);
423 static const_rtx
expand_field_assignment (const_rtx
);
424 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
425 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
426 static rtx
extract_left_shift (rtx
, int);
427 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
428 unsigned HOST_WIDE_INT
*);
429 static rtx
canon_reg_for_combine (rtx
, rtx
);
430 static rtx
force_to_mode (rtx
, enum machine_mode
,
431 unsigned HOST_WIDE_INT
, int);
432 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
433 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
434 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
435 static rtx
make_field_assignment (rtx
);
436 static rtx
apply_distributive_law (rtx
);
437 static rtx
distribute_and_simplify_rtx (rtx
, int);
438 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
439 unsigned HOST_WIDE_INT
);
440 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
441 unsigned HOST_WIDE_INT
);
442 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
443 HOST_WIDE_INT
, enum machine_mode
, int *);
444 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
445 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
447 static int recog_for_combine (rtx
*, rtx
, rtx
*);
448 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
449 static enum rtx_code
simplify_compare_const (enum rtx_code
, enum machine_mode
,
451 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
452 static void update_table_tick (rtx
);
453 static void record_value_for_reg (rtx
, rtx
, rtx
);
454 static void check_promoted_subreg (rtx
, rtx
);
455 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
456 static void record_dead_and_set_regs (rtx
);
457 static int get_last_value_validate (rtx
*, rtx
, int, int);
458 static rtx
get_last_value (const_rtx
);
459 static int use_crosses_set_p (const_rtx
, int);
460 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
461 static int reg_dead_at_p (rtx
, rtx
);
462 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
463 static int reg_bitfield_target_p (rtx
, rtx
);
464 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
465 static void distribute_links (struct insn_link
*);
466 static void mark_used_regs_combine (rtx
);
467 static void record_promoted_value (rtx
, rtx
);
468 static int unmentioned_reg_p_1 (rtx
*, void *);
469 static bool unmentioned_reg_p (rtx
, rtx
);
470 static int record_truncated_value (rtx
*, void *);
471 static void record_truncated_values (rtx
*, void *);
472 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
473 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
476 /* It is not safe to use ordinary gen_lowpart in combine.
477 See comments in gen_lowpart_for_combine. */
478 #undef RTL_HOOKS_GEN_LOWPART
479 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
481 /* Our implementation of gen_lowpart never emits a new pseudo. */
482 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
483 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
485 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
486 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
488 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
489 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
491 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
492 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
494 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
497 /* Convenience wrapper for the canonicalize_comparison target hook.
498 Target hooks cannot use enum rtx_code. */
500 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
501 bool op0_preserve_value
)
503 int code_int
= (int)*code
;
504 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
505 *code
= (enum rtx_code
)code_int
;
508 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
509 PATTERN can not be split. Otherwise, it returns an insn sequence.
510 This is a wrapper around split_insns which ensures that the
511 reg_stat vector is made larger if the splitter creates a new
515 combine_split_insns (rtx pattern
, rtx insn
)
520 ret
= split_insns (pattern
, insn
);
521 nregs
= max_reg_num ();
522 if (nregs
> reg_stat
.length ())
523 reg_stat
.safe_grow_cleared (nregs
);
527 /* This is used by find_single_use to locate an rtx in LOC that
528 contains exactly one use of DEST, which is typically either a REG
529 or CC0. It returns a pointer to the innermost rtx expression
530 containing DEST. Appearances of DEST that are being used to
531 totally replace it are not counted. */
534 find_single_use_1 (rtx dest
, rtx
*loc
)
537 enum rtx_code code
= GET_CODE (x
);
553 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
554 of a REG that occupies all of the REG, the insn uses DEST if
555 it is mentioned in the destination or the source. Otherwise, we
556 need just check the source. */
557 if (GET_CODE (SET_DEST (x
)) != CC0
558 && GET_CODE (SET_DEST (x
)) != PC
559 && !REG_P (SET_DEST (x
))
560 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
561 && REG_P (SUBREG_REG (SET_DEST (x
)))
562 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
563 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
564 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
565 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
568 return find_single_use_1 (dest
, &SET_SRC (x
));
572 return find_single_use_1 (dest
, &XEXP (x
, 0));
578 /* If it wasn't one of the common cases above, check each expression and
579 vector of this code. Look for a unique usage of DEST. */
581 fmt
= GET_RTX_FORMAT (code
);
582 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
586 if (dest
== XEXP (x
, i
)
587 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
588 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
591 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
594 result
= this_result
;
595 else if (this_result
)
596 /* Duplicate usage. */
599 else if (fmt
[i
] == 'E')
603 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
605 if (XVECEXP (x
, i
, j
) == dest
607 && REG_P (XVECEXP (x
, i
, j
))
608 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
611 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
614 result
= this_result
;
615 else if (this_result
)
625 /* See if DEST, produced in INSN, is used only a single time in the
626 sequel. If so, return a pointer to the innermost rtx expression in which
629 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
631 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
632 care about REG_DEAD notes or LOG_LINKS.
634 Otherwise, we find the single use by finding an insn that has a
635 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
636 only referenced once in that insn, we know that it must be the first
637 and last insn referencing DEST. */
640 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
645 struct insn_link
*link
;
650 next
= NEXT_INSN (insn
);
652 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
655 result
= find_single_use_1 (dest
, &PATTERN (next
));
665 bb
= BLOCK_FOR_INSN (insn
);
666 for (next
= NEXT_INSN (insn
);
667 next
&& BLOCK_FOR_INSN (next
) == bb
;
668 next
= NEXT_INSN (next
))
669 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
671 FOR_EACH_LOG_LINK (link
, next
)
672 if (link
->insn
== insn
)
677 result
= find_single_use_1 (dest
, &PATTERN (next
));
687 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
688 insn. The substitution can be undone by undo_all. If INTO is already
689 set to NEWVAL, do not record this change. Because computing NEWVAL might
690 also call SUBST, we have to compute it before we put anything into
694 do_SUBST (rtx
*into
, rtx newval
)
699 if (oldval
== newval
)
702 /* We'd like to catch as many invalid transformations here as
703 possible. Unfortunately, there are way too many mode changes
704 that are perfectly valid, so we'd waste too much effort for
705 little gain doing the checks here. Focus on catching invalid
706 transformations involving integer constants. */
707 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
708 && CONST_INT_P (newval
))
710 /* Sanity check that we're replacing oldval with a CONST_INT
711 that is a valid sign-extension for the original mode. */
712 gcc_assert (INTVAL (newval
)
713 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
715 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
716 CONST_INT is not valid, because after the replacement, the
717 original mode would be gone. Unfortunately, we can't tell
718 when do_SUBST is called to replace the operand thereof, so we
719 perform this test on oldval instead, checking whether an
720 invalid replacement took place before we got here. */
721 gcc_assert (!(GET_CODE (oldval
) == SUBREG
722 && CONST_INT_P (SUBREG_REG (oldval
))));
723 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
724 && CONST_INT_P (XEXP (oldval
, 0))));
728 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
730 buf
= XNEW (struct undo
);
732 buf
->kind
= UNDO_RTX
;
734 buf
->old_contents
.r
= oldval
;
737 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
740 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
742 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
743 for the value of a HOST_WIDE_INT value (including CONST_INT) is
747 do_SUBST_INT (int *into
, int newval
)
752 if (oldval
== newval
)
756 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
758 buf
= XNEW (struct undo
);
760 buf
->kind
= UNDO_INT
;
762 buf
->old_contents
.i
= oldval
;
765 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
768 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
770 /* Similar to SUBST, but just substitute the mode. This is used when
771 changing the mode of a pseudo-register, so that any other
772 references to the entry in the regno_reg_rtx array will change as
776 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
779 enum machine_mode oldval
= GET_MODE (*into
);
781 if (oldval
== newval
)
785 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
787 buf
= XNEW (struct undo
);
789 buf
->kind
= UNDO_MODE
;
791 buf
->old_contents
.m
= oldval
;
792 adjust_reg_mode (*into
, newval
);
794 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
797 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
800 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
803 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
806 struct insn_link
* oldval
= *into
;
808 if (oldval
== newval
)
812 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
814 buf
= XNEW (struct undo
);
816 buf
->kind
= UNDO_LINKS
;
818 buf
->old_contents
.l
= oldval
;
821 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
824 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
827 /* Subroutine of try_combine. Determine whether the replacement patterns
828 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
829 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
830 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
831 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
832 of all the instructions can be estimated and the replacements are more
833 expensive than the original sequence. */
836 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
837 rtx newi2pat
, rtx newotherpat
)
839 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
840 int new_i2_cost
, new_i3_cost
;
841 int old_cost
, new_cost
;
843 /* Lookup the original insn_rtx_costs. */
844 i2_cost
= INSN_COST (i2
);
845 i3_cost
= INSN_COST (i3
);
849 i1_cost
= INSN_COST (i1
);
852 i0_cost
= INSN_COST (i0
);
853 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
854 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
858 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
859 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
865 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
866 i1_cost
= i0_cost
= 0;
869 /* Calculate the replacement insn_rtx_costs. */
870 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
873 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
874 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
875 ? new_i2_cost
+ new_i3_cost
: 0;
879 new_cost
= new_i3_cost
;
883 if (undobuf
.other_insn
)
885 int old_other_cost
, new_other_cost
;
887 old_other_cost
= INSN_COST (undobuf
.other_insn
);
888 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
889 if (old_other_cost
> 0 && new_other_cost
> 0)
891 old_cost
+= old_other_cost
;
892 new_cost
+= new_other_cost
;
898 /* Disallow this combination if both new_cost and old_cost are greater than
899 zero, and new_cost is greater than old cost. */
900 if (old_cost
> 0 && new_cost
> old_cost
)
907 "rejecting combination of insns %d, %d, %d and %d\n",
908 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
910 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
911 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
916 "rejecting combination of insns %d, %d and %d\n",
917 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
918 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
919 i1_cost
, i2_cost
, i3_cost
, old_cost
);
924 "rejecting combination of insns %d and %d\n",
925 INSN_UID (i2
), INSN_UID (i3
));
926 fprintf (dump_file
, "original costs %d + %d = %d\n",
927 i2_cost
, i3_cost
, old_cost
);
932 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
933 new_i2_cost
, new_i3_cost
, new_cost
);
936 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
942 /* Update the uid_insn_cost array with the replacement costs. */
943 INSN_COST (i2
) = new_i2_cost
;
944 INSN_COST (i3
) = new_i3_cost
;
956 /* Delete any insns that copy a register to itself. */
959 delete_noop_moves (void)
964 FOR_EACH_BB_FN (bb
, cfun
)
966 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
968 next
= NEXT_INSN (insn
);
969 if (INSN_P (insn
) && noop_move_p (insn
))
972 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
974 delete_insn_and_edges (insn
);
981 /* Fill in log links field for all insns. */
984 create_log_links (void)
988 df_ref
*def_vec
, *use_vec
;
990 next_use
= XCNEWVEC (rtx
, max_reg_num ());
992 /* Pass through each block from the end, recording the uses of each
993 register and establishing log links when def is encountered.
994 Note that we do not clear next_use array in order to save time,
995 so we have to test whether the use is in the same basic block as def.
997 There are a few cases below when we do not consider the definition or
998 usage -- these are taken from original flow.c did. Don't ask me why it is
999 done this way; I don't know and if it works, I don't want to know. */
1001 FOR_EACH_BB_FN (bb
, cfun
)
1003 FOR_BB_INSNS_REVERSE (bb
, insn
)
1005 if (!NONDEBUG_INSN_P (insn
))
1008 /* Log links are created only once. */
1009 gcc_assert (!LOG_LINKS (insn
));
1011 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1013 df_ref def
= *def_vec
;
1014 int regno
= DF_REF_REGNO (def
);
1017 if (!next_use
[regno
])
1020 /* Do not consider if it is pre/post modification in MEM. */
1021 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1024 /* Do not make the log link for frame pointer. */
1025 if ((regno
== FRAME_POINTER_REGNUM
1026 && (! reload_completed
|| frame_pointer_needed
))
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1028 || (regno
== HARD_FRAME_POINTER_REGNUM
1029 && (! reload_completed
|| frame_pointer_needed
))
1031 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1032 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1037 use_insn
= next_use
[regno
];
1038 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1042 We don't build a LOG_LINK for hard registers contained
1043 in ASM_OPERANDs. If these registers get replaced,
1044 we might wind up changing the semantics of the insn,
1045 even if reload can make what appear to be valid
1046 assignments later. */
1047 if (regno
>= FIRST_PSEUDO_REGISTER
1048 || asm_noperands (PATTERN (use_insn
)) < 0)
1050 /* Don't add duplicate links between instructions. */
1051 struct insn_link
*links
;
1052 FOR_EACH_LOG_LINK (links
, use_insn
)
1053 if (insn
== links
->insn
)
1057 LOG_LINKS (use_insn
)
1058 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1061 next_use
[regno
] = NULL_RTX
;
1064 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1066 df_ref use
= *use_vec
;
1067 int regno
= DF_REF_REGNO (use
);
1069 /* Do not consider the usage of the stack pointer
1070 by function call. */
1071 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1074 next_use
[regno
] = insn
;
1082 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1083 true if we found a LOG_LINK that proves that A feeds B. This only works
1084 if there are no instructions between A and B which could have a link
1085 depending on A, since in that case we would not record a link for B.
1086 We also check the implicit dependency created by a cc0 setter/user
1090 insn_a_feeds_b (rtx a
, rtx b
)
1092 struct insn_link
*links
;
1093 FOR_EACH_LOG_LINK (links
, b
)
1094 if (links
->insn
== a
)
1103 /* Main entry point for combiner. F is the first insn of the function.
1104 NREGS is the first unused pseudo-reg number.
1106 Return nonzero if the combiner has turned an indirect jump
1107 instruction into a direct jump. */
1109 combine_instructions (rtx f
, unsigned int nregs
)
1115 struct insn_link
*links
, *nextlinks
;
1117 basic_block last_bb
;
1119 int new_direct_jump_p
= 0;
1121 for (first
= f
; first
&& !INSN_P (first
); )
1122 first
= NEXT_INSN (first
);
1126 combine_attempts
= 0;
1129 combine_successes
= 0;
1131 rtl_hooks
= combine_rtl_hooks
;
1133 reg_stat
.safe_grow_cleared (nregs
);
1135 init_recog_no_volatile ();
1137 /* Allocate array for insn info. */
1138 max_uid_known
= get_max_uid ();
1139 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1140 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1141 gcc_obstack_init (&insn_link_obstack
);
1143 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1145 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1146 problems when, for example, we have j <<= 1 in a loop. */
1148 nonzero_sign_valid
= 0;
1149 label_tick
= label_tick_ebb_start
= 1;
1151 /* Scan all SETs and see if we can deduce anything about what
1152 bits are known to be zero for some registers and how many copies
1153 of the sign bit are known to exist for those registers.
1155 Also set any known values so that we can use it while searching
1156 for what bits are known to be set. */
1158 setup_incoming_promotions (first
);
1159 /* Allow the entry block and the first block to fall into the same EBB.
1160 Conceptually the incoming promotions are assigned to the entry block. */
1161 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1163 create_log_links ();
1164 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1166 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1171 if (!single_pred_p (this_basic_block
)
1172 || single_pred (this_basic_block
) != last_bb
)
1173 label_tick_ebb_start
= label_tick
;
1174 last_bb
= this_basic_block
;
1176 FOR_BB_INSNS (this_basic_block
, insn
)
1177 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1183 subst_low_luid
= DF_INSN_LUID (insn
);
1186 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1188 record_dead_and_set_regs (insn
);
1191 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1192 if (REG_NOTE_KIND (links
) == REG_INC
)
1193 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1197 /* Record the current insn_rtx_cost of this instruction. */
1198 if (NONJUMP_INSN_P (insn
))
1199 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1200 optimize_this_for_speed_p
);
1202 fprintf (dump_file
, "insn_cost %d: %d\n",
1203 INSN_UID (insn
), INSN_COST (insn
));
1207 nonzero_sign_valid
= 1;
1209 /* Now scan all the insns in forward order. */
1210 label_tick
= label_tick_ebb_start
= 1;
1212 setup_incoming_promotions (first
);
1213 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1215 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1217 rtx last_combined_insn
= NULL_RTX
;
1218 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1223 if (!single_pred_p (this_basic_block
)
1224 || single_pred (this_basic_block
) != last_bb
)
1225 label_tick_ebb_start
= label_tick
;
1226 last_bb
= this_basic_block
;
1228 rtl_profile_for_bb (this_basic_block
);
1229 for (insn
= BB_HEAD (this_basic_block
);
1230 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1231 insn
= next
? next
: NEXT_INSN (insn
))
1234 if (NONDEBUG_INSN_P (insn
))
1236 while (last_combined_insn
1237 && INSN_DELETED_P (last_combined_insn
))
1238 last_combined_insn
= PREV_INSN (last_combined_insn
);
1239 if (last_combined_insn
== NULL_RTX
1240 || BARRIER_P (last_combined_insn
)
1241 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1242 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1243 last_combined_insn
= insn
;
1245 /* See if we know about function return values before this
1246 insn based upon SUBREG flags. */
1247 check_promoted_subreg (insn
, PATTERN (insn
));
1249 /* See if we can find hardregs and subreg of pseudos in
1250 narrower modes. This could help turning TRUNCATEs
1252 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1254 /* Try this insn with each insn it links back to. */
1256 FOR_EACH_LOG_LINK (links
, insn
)
1257 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1258 NULL_RTX
, &new_direct_jump_p
,
1259 last_combined_insn
)) != 0)
1262 /* Try each sequence of three linked insns ending with this one. */
1264 FOR_EACH_LOG_LINK (links
, insn
)
1266 rtx link
= links
->insn
;
1268 /* If the linked insn has been replaced by a note, then there
1269 is no point in pursuing this chain any further. */
1273 FOR_EACH_LOG_LINK (nextlinks
, link
)
1274 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1275 NULL_RTX
, &new_direct_jump_p
,
1276 last_combined_insn
)) != 0)
1281 /* Try to combine a jump insn that uses CC0
1282 with a preceding insn that sets CC0, and maybe with its
1283 logical predecessor as well.
1284 This is how we make decrement-and-branch insns.
1285 We need this special code because data flow connections
1286 via CC0 do not get entered in LOG_LINKS. */
1289 && (prev
= prev_nonnote_insn (insn
)) != 0
1290 && NONJUMP_INSN_P (prev
)
1291 && sets_cc0_p (PATTERN (prev
)))
1293 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1295 last_combined_insn
)) != 0)
1298 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1299 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1300 NULL_RTX
, &new_direct_jump_p
,
1301 last_combined_insn
)) != 0)
1305 /* Do the same for an insn that explicitly references CC0. */
1306 if (NONJUMP_INSN_P (insn
)
1307 && (prev
= prev_nonnote_insn (insn
)) != 0
1308 && NONJUMP_INSN_P (prev
)
1309 && sets_cc0_p (PATTERN (prev
))
1310 && GET_CODE (PATTERN (insn
)) == SET
1311 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1313 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1315 last_combined_insn
)) != 0)
1318 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1319 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1320 NULL_RTX
, &new_direct_jump_p
,
1321 last_combined_insn
)) != 0)
1325 /* Finally, see if any of the insns that this insn links to
1326 explicitly references CC0. If so, try this insn, that insn,
1327 and its predecessor if it sets CC0. */
1328 FOR_EACH_LOG_LINK (links
, insn
)
1329 if (NONJUMP_INSN_P (links
->insn
)
1330 && GET_CODE (PATTERN (links
->insn
)) == SET
1331 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1332 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1333 && NONJUMP_INSN_P (prev
)
1334 && sets_cc0_p (PATTERN (prev
))
1335 && (next
= try_combine (insn
, links
->insn
,
1336 prev
, NULL_RTX
, &new_direct_jump_p
,
1337 last_combined_insn
)) != 0)
1341 /* Try combining an insn with two different insns whose results it
1343 FOR_EACH_LOG_LINK (links
, insn
)
1344 for (nextlinks
= links
->next
; nextlinks
;
1345 nextlinks
= nextlinks
->next
)
1346 if ((next
= try_combine (insn
, links
->insn
,
1347 nextlinks
->insn
, NULL_RTX
,
1349 last_combined_insn
)) != 0)
1352 /* Try four-instruction combinations. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1355 struct insn_link
*next1
;
1356 rtx link
= links
->insn
;
1358 /* If the linked insn has been replaced by a note, then there
1359 is no point in pursuing this chain any further. */
1363 FOR_EACH_LOG_LINK (next1
, link
)
1365 rtx link1
= next1
->insn
;
1368 /* I0 -> I1 -> I2 -> I3. */
1369 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1370 if ((next
= try_combine (insn
, link
, link1
,
1373 last_combined_insn
)) != 0)
1375 /* I0, I1 -> I2, I2 -> I3. */
1376 for (nextlinks
= next1
->next
; nextlinks
;
1377 nextlinks
= nextlinks
->next
)
1378 if ((next
= try_combine (insn
, link
, link1
,
1381 last_combined_insn
)) != 0)
1385 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1387 rtx link1
= next1
->insn
;
1390 /* I0 -> I2; I1, I2 -> I3. */
1391 FOR_EACH_LOG_LINK (nextlinks
, link
)
1392 if ((next
= try_combine (insn
, link
, link1
,
1395 last_combined_insn
)) != 0)
1397 /* I0 -> I1; I1, I2 -> I3. */
1398 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1399 if ((next
= try_combine (insn
, link
, link1
,
1402 last_combined_insn
)) != 0)
1407 /* Try this insn with each REG_EQUAL note it links back to. */
1408 FOR_EACH_LOG_LINK (links
, insn
)
1411 rtx temp
= links
->insn
;
1412 if ((set
= single_set (temp
)) != 0
1413 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1414 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1415 /* Avoid using a register that may already been marked
1416 dead by an earlier instruction. */
1417 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1418 && (GET_MODE (note
) == VOIDmode
1419 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1420 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1422 /* Temporarily replace the set's source with the
1423 contents of the REG_EQUAL note. The insn will
1424 be deleted or recognized by try_combine. */
1425 rtx orig
= SET_SRC (set
);
1426 SET_SRC (set
) = note
;
1428 i2mod_old_rhs
= copy_rtx (orig
);
1429 i2mod_new_rhs
= copy_rtx (note
);
1430 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1432 last_combined_insn
);
1436 SET_SRC (set
) = orig
;
1441 record_dead_and_set_regs (insn
);
1449 default_rtl_profile ();
1451 new_direct_jump_p
|= purge_all_dead_edges ();
1452 delete_noop_moves ();
1455 obstack_free (&insn_link_obstack
, NULL
);
1456 free (uid_log_links
);
1457 free (uid_insn_cost
);
1458 reg_stat
.release ();
1461 struct undo
*undo
, *next
;
1462 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1470 total_attempts
+= combine_attempts
;
1471 total_merges
+= combine_merges
;
1472 total_extras
+= combine_extras
;
1473 total_successes
+= combine_successes
;
1475 nonzero_sign_valid
= 0;
1476 rtl_hooks
= general_rtl_hooks
;
1478 /* Make recognizer allow volatile MEMs again. */
1481 return new_direct_jump_p
;
1484 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1487 init_reg_last (void)
1492 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1493 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1496 /* Set up any promoted values for incoming argument registers. */
1499 setup_incoming_promotions (rtx first
)
1502 bool strictly_local
= false;
1504 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1505 arg
= DECL_CHAIN (arg
))
1507 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1509 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1511 /* Only continue if the incoming argument is in a register. */
1515 /* Determine, if possible, whether all call sites of the current
1516 function lie within the current compilation unit. (This does
1517 take into account the exporting of a function via taking its
1518 address, and so forth.) */
1519 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1521 /* The mode and signedness of the argument before any promotions happen
1522 (equal to the mode of the pseudo holding it at that stage). */
1523 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1524 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1526 /* The mode and signedness of the argument after any source language and
1527 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1528 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1529 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1531 /* The mode and signedness of the argument as it is actually passed,
1532 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1533 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1534 TREE_TYPE (cfun
->decl
), 0);
1536 /* The mode of the register in which the argument is being passed. */
1537 mode4
= GET_MODE (reg
);
1539 /* Eliminate sign extensions in the callee when:
1540 (a) A mode promotion has occurred; */
1543 /* (b) The mode of the register is the same as the mode of
1544 the argument as it is passed; */
1547 /* (c) There's no language level extension; */
1550 /* (c.1) All callers are from the current compilation unit. If that's
1551 the case we don't have to rely on an ABI, we only have to know
1552 what we're generating right now, and we know that we will do the
1553 mode1 to mode2 promotion with the given sign. */
1554 else if (!strictly_local
)
1556 /* (c.2) The combination of the two promotions is useful. This is
1557 true when the signs match, or if the first promotion is unsigned.
1558 In the later case, (sign_extend (zero_extend x)) is the same as
1559 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1565 /* Record that the value was promoted from mode1 to mode3,
1566 so that any sign extension at the head of the current
1567 function may be eliminated. */
1568 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1569 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1570 record_value_for_reg (reg
, first
, x
);
1574 /* Called via note_stores. If X is a pseudo that is narrower than
1575 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1577 If we are setting only a portion of X and we can't figure out what
1578 portion, assume all bits will be used since we don't know what will
1581 Similarly, set how many bits of X are known to be copies of the sign bit
1582 at all locations in the function. This is the smallest number implied
1586 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1588 rtx insn
= (rtx
) data
;
1592 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1593 /* If this register is undefined at the start of the file, we can't
1594 say what its contents were. */
1595 && ! REGNO_REG_SET_P
1596 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1597 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1599 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1601 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1603 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1604 rsp
->sign_bit_copies
= 1;
1608 /* If this register is being initialized using itself, and the
1609 register is uninitialized in this basic block, and there are
1610 no LOG_LINKS which set the register, then part of the
1611 register is uninitialized. In that case we can't assume
1612 anything about the number of nonzero bits.
1614 ??? We could do better if we checked this in
1615 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1616 could avoid making assumptions about the insn which initially
1617 sets the register, while still using the information in other
1618 insns. We would have to be careful to check every insn
1619 involved in the combination. */
1622 && reg_referenced_p (x
, PATTERN (insn
))
1623 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1626 struct insn_link
*link
;
1628 FOR_EACH_LOG_LINK (link
, insn
)
1629 if (dead_or_set_p (link
->insn
, x
))
1633 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1634 rsp
->sign_bit_copies
= 1;
1639 /* If this is a complex assignment, see if we can convert it into a
1640 simple assignment. */
1641 set
= expand_field_assignment (set
);
1643 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1644 set what we know about X. */
1646 if (SET_DEST (set
) == x
1647 || (paradoxical_subreg_p (SET_DEST (set
))
1648 && SUBREG_REG (SET_DEST (set
)) == x
))
1650 rtx src
= SET_SRC (set
);
1652 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1653 /* If X is narrower than a word and SRC is a non-negative
1654 constant that would appear negative in the mode of X,
1655 sign-extend it for use in reg_stat[].nonzero_bits because some
1656 machines (maybe most) will actually do the sign-extension
1657 and this is the conservative approach.
1659 ??? For 2.5, try to tighten up the MD files in this regard
1660 instead of this kludge. */
1662 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1663 && CONST_INT_P (src
)
1665 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1666 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1669 /* Don't call nonzero_bits if it cannot change anything. */
1670 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1671 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1672 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1673 if (rsp
->sign_bit_copies
== 0
1674 || rsp
->sign_bit_copies
> num
)
1675 rsp
->sign_bit_copies
= num
;
1679 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1680 rsp
->sign_bit_copies
= 1;
1685 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1686 optionally insns that were previously combined into I3 or that will be
1687 combined into the merger of INSN and I3. The order is PRED, PRED2,
1688 INSN, SUCC, SUCC2, I3.
1690 Return 0 if the combination is not allowed for any reason.
1692 If the combination is allowed, *PDEST will be set to the single
1693 destination of INSN and *PSRC to the single source, and this function
1697 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1698 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1699 rtx
*pdest
, rtx
*psrc
)
1708 bool all_adjacent
= true;
1709 int (*is_volatile_p
) (const_rtx
);
1715 if (next_active_insn (succ2
) != i3
)
1716 all_adjacent
= false;
1717 if (next_active_insn (succ
) != succ2
)
1718 all_adjacent
= false;
1720 else if (next_active_insn (succ
) != i3
)
1721 all_adjacent
= false;
1722 if (next_active_insn (insn
) != succ
)
1723 all_adjacent
= false;
1725 else if (next_active_insn (insn
) != i3
)
1726 all_adjacent
= false;
1728 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1729 or a PARALLEL consisting of such a SET and CLOBBERs.
1731 If INSN has CLOBBER parallel parts, ignore them for our processing.
1732 By definition, these happen during the execution of the insn. When it
1733 is merged with another insn, all bets are off. If they are, in fact,
1734 needed and aren't also supplied in I3, they may be added by
1735 recog_for_combine. Otherwise, it won't match.
1737 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1740 Get the source and destination of INSN. If more than one, can't
1743 if (GET_CODE (PATTERN (insn
)) == SET
)
1744 set
= PATTERN (insn
);
1745 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1746 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1748 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1750 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1752 switch (GET_CODE (elt
))
1754 /* This is important to combine floating point insns
1755 for the SH4 port. */
1757 /* Combining an isolated USE doesn't make sense.
1758 We depend here on combinable_i3pat to reject them. */
1759 /* The code below this loop only verifies that the inputs of
1760 the SET in INSN do not change. We call reg_set_between_p
1761 to verify that the REG in the USE does not change between
1763 If the USE in INSN was for a pseudo register, the matching
1764 insn pattern will likely match any register; combining this
1765 with any other USE would only be safe if we knew that the
1766 used registers have identical values, or if there was
1767 something to tell them apart, e.g. different modes. For
1768 now, we forgo such complicated tests and simply disallow
1769 combining of USES of pseudo registers with any other USE. */
1770 if (REG_P (XEXP (elt
, 0))
1771 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1773 rtx i3pat
= PATTERN (i3
);
1774 int i
= XVECLEN (i3pat
, 0) - 1;
1775 unsigned int regno
= REGNO (XEXP (elt
, 0));
1779 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1781 if (GET_CODE (i3elt
) == USE
1782 && REG_P (XEXP (i3elt
, 0))
1783 && (REGNO (XEXP (i3elt
, 0)) == regno
1784 ? reg_set_between_p (XEXP (elt
, 0),
1785 PREV_INSN (insn
), i3
)
1786 : regno
>= FIRST_PSEUDO_REGISTER
))
1793 /* We can ignore CLOBBERs. */
1798 /* Ignore SETs whose result isn't used but not those that
1799 have side-effects. */
1800 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1801 && insn_nothrow_p (insn
)
1802 && !side_effects_p (elt
))
1805 /* If we have already found a SET, this is a second one and
1806 so we cannot combine with this insn. */
1814 /* Anything else means we can't combine. */
1820 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1821 so don't do anything with it. */
1822 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1831 /* The simplification in expand_field_assignment may call back to
1832 get_last_value, so set safe guard here. */
1833 subst_low_luid
= DF_INSN_LUID (insn
);
1835 set
= expand_field_assignment (set
);
1836 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1838 /* Don't eliminate a store in the stack pointer. */
1839 if (dest
== stack_pointer_rtx
1840 /* Don't combine with an insn that sets a register to itself if it has
1841 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1842 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1843 /* Can't merge an ASM_OPERANDS. */
1844 || GET_CODE (src
) == ASM_OPERANDS
1845 /* Can't merge a function call. */
1846 || GET_CODE (src
) == CALL
1847 /* Don't eliminate a function call argument. */
1849 && (find_reg_fusage (i3
, USE
, dest
)
1851 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1852 && global_regs
[REGNO (dest
)])))
1853 /* Don't substitute into an incremented register. */
1854 || FIND_REG_INC_NOTE (i3
, dest
)
1855 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1856 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1857 /* Don't substitute into a non-local goto, this confuses CFG. */
1858 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1859 /* Make sure that DEST is not used after SUCC but before I3. */
1862 && (reg_used_between_p (dest
, succ2
, i3
)
1863 || reg_used_between_p (dest
, succ
, succ2
)))
1864 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1865 /* Make sure that the value that is to be substituted for the register
1866 does not use any registers whose values alter in between. However,
1867 If the insns are adjacent, a use can't cross a set even though we
1868 think it might (this can happen for a sequence of insns each setting
1869 the same destination; last_set of that register might point to
1870 a NOTE). If INSN has a REG_EQUIV note, the register is always
1871 equivalent to the memory so the substitution is valid even if there
1872 are intervening stores. Also, don't move a volatile asm or
1873 UNSPEC_VOLATILE across any other insns. */
1876 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1877 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1878 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1879 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1880 /* Don't combine across a CALL_INSN, because that would possibly
1881 change whether the life span of some REGs crosses calls or not,
1882 and it is a pain to update that information.
1883 Exception: if source is a constant, moving it later can't hurt.
1884 Accept that as a special case. */
1885 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1888 /* DEST must either be a REG or CC0. */
1891 /* If register alignment is being enforced for multi-word items in all
1892 cases except for parameters, it is possible to have a register copy
1893 insn referencing a hard register that is not allowed to contain the
1894 mode being copied and which would not be valid as an operand of most
1895 insns. Eliminate this problem by not combining with such an insn.
1897 Also, on some machines we don't want to extend the life of a hard
1901 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1902 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1903 /* Don't extend the life of a hard register unless it is
1904 user variable (if we have few registers) or it can't
1905 fit into the desired register (meaning something special
1907 Also avoid substituting a return register into I3, because
1908 reload can't handle a conflict with constraints of other
1910 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1911 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1914 else if (GET_CODE (dest
) != CC0
)
1918 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1919 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1920 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1922 /* Don't substitute for a register intended as a clobberable
1924 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1925 if (rtx_equal_p (reg
, dest
))
1928 /* If the clobber represents an earlyclobber operand, we must not
1929 substitute an expression containing the clobbered register.
1930 As we do not analyze the constraint strings here, we have to
1931 make the conservative assumption. However, if the register is
1932 a fixed hard reg, the clobber cannot represent any operand;
1933 we leave it up to the machine description to either accept or
1934 reject use-and-clobber patterns. */
1936 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1937 || !fixed_regs
[REGNO (reg
)])
1938 if (reg_overlap_mentioned_p (reg
, src
))
1942 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1943 or not), reject, unless nothing volatile comes between it and I3 */
1945 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1947 /* Make sure neither succ nor succ2 contains a volatile reference. */
1948 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1950 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1952 /* We'll check insns between INSN and I3 below. */
1955 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1956 to be an explicit register variable, and was chosen for a reason. */
1958 if (GET_CODE (src
) == ASM_OPERANDS
1959 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1962 /* If INSN contains volatile references (specifically volatile MEMs),
1963 we cannot combine across any other volatile references.
1964 Even if INSN doesn't contain volatile references, any intervening
1965 volatile insn might affect machine state. */
1967 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1971 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1972 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1975 /* If INSN contains an autoincrement or autodecrement, make sure that
1976 register is not used between there and I3, and not already used in
1977 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1978 Also insist that I3 not be a jump; if it were one
1979 and the incremented register were spilled, we would lose. */
1982 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1983 if (REG_NOTE_KIND (link
) == REG_INC
1985 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1986 || (pred
!= NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1988 || (pred2
!= NULL_RTX
1989 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1990 || (succ
!= NULL_RTX
1991 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1992 || (succ2
!= NULL_RTX
1993 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1994 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1999 /* Don't combine an insn that follows a CC0-setting insn.
2000 An insn that uses CC0 must not be separated from the one that sets it.
2001 We do, however, allow I2 to follow a CC0-setting insn if that insn
2002 is passed as I1; in that case it will be deleted also.
2003 We also allow combining in this case if all the insns are adjacent
2004 because that would leave the two CC0 insns adjacent as well.
2005 It would be more logical to test whether CC0 occurs inside I1 or I2,
2006 but that would be much slower, and this ought to be equivalent. */
2008 p
= prev_nonnote_insn (insn
);
2009 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2014 /* If we get here, we have passed all the tests and the combination is
2023 /* LOC is the location within I3 that contains its pattern or the component
2024 of a PARALLEL of the pattern. We validate that it is valid for combining.
2026 One problem is if I3 modifies its output, as opposed to replacing it
2027 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2028 doing so would produce an insn that is not equivalent to the original insns.
2032 (set (reg:DI 101) (reg:DI 100))
2033 (set (subreg:SI (reg:DI 101) 0) <foo>)
2035 This is NOT equivalent to:
2037 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2038 (set (reg:DI 101) (reg:DI 100))])
2040 Not only does this modify 100 (in which case it might still be valid
2041 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2043 We can also run into a problem if I2 sets a register that I1
2044 uses and I1 gets directly substituted into I3 (not via I2). In that
2045 case, we would be getting the wrong value of I2DEST into I3, so we
2046 must reject the combination. This case occurs when I2 and I1 both
2047 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2048 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2049 of a SET must prevent combination from occurring. The same situation
2050 can occur for I0, in which case I0_NOT_IN_SRC is set.
2052 Before doing the above check, we first try to expand a field assignment
2053 into a set of logical operations.
2055 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2056 we place a register that is both set and used within I3. If more than one
2057 such register is detected, we fail.
2059 Return 1 if the combination is valid, zero otherwise. */
2062 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2063 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2067 if (GET_CODE (x
) == SET
)
2070 rtx dest
= SET_DEST (set
);
2071 rtx src
= SET_SRC (set
);
2072 rtx inner_dest
= dest
;
2075 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2076 || GET_CODE (inner_dest
) == SUBREG
2077 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2078 inner_dest
= XEXP (inner_dest
, 0);
2080 /* Check for the case where I3 modifies its output, as discussed
2081 above. We don't want to prevent pseudos from being combined
2082 into the address of a MEM, so only prevent the combination if
2083 i1 or i2 set the same MEM. */
2084 if ((inner_dest
!= dest
&&
2085 (!MEM_P (inner_dest
)
2086 || rtx_equal_p (i2dest
, inner_dest
)
2087 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2088 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2089 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2090 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2091 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2093 /* This is the same test done in can_combine_p except we can't test
2094 all_adjacent; we don't have to, since this instruction will stay
2095 in place, thus we are not considering increasing the lifetime of
2098 Also, if this insn sets a function argument, combining it with
2099 something that might need a spill could clobber a previous
2100 function argument; the all_adjacent test in can_combine_p also
2101 checks this; here, we do a more specific test for this case. */
2103 || (REG_P (inner_dest
)
2104 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2105 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2106 GET_MODE (inner_dest
))))
2107 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2108 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2111 /* If DEST is used in I3, it is being killed in this insn, so
2112 record that for later. We have to consider paradoxical
2113 subregs here, since they kill the whole register, but we
2114 ignore partial subregs, STRICT_LOW_PART, etc.
2115 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2116 STACK_POINTER_REGNUM, since these are always considered to be
2117 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2119 if (GET_CODE (subdest
) == SUBREG
2120 && (GET_MODE_SIZE (GET_MODE (subdest
))
2121 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2122 subdest
= SUBREG_REG (subdest
);
2125 && reg_referenced_p (subdest
, PATTERN (i3
))
2126 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2127 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2128 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2130 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2131 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2132 || ! fixed_regs
[REGNO (subdest
)])
2134 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2136 if (*pi3dest_killed
)
2139 *pi3dest_killed
= subdest
;
2143 else if (GET_CODE (x
) == PARALLEL
)
2147 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2148 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2149 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2156 /* Return 1 if X is an arithmetic expression that contains a multiplication
2157 and division. We don't count multiplications by powers of two here. */
2160 contains_muldiv (rtx x
)
2162 switch (GET_CODE (x
))
2164 case MOD
: case DIV
: case UMOD
: case UDIV
:
2168 return ! (CONST_INT_P (XEXP (x
, 1))
2169 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2172 return contains_muldiv (XEXP (x
, 0))
2173 || contains_muldiv (XEXP (x
, 1));
2176 return contains_muldiv (XEXP (x
, 0));
2182 /* Determine whether INSN can be used in a combination. Return nonzero if
2183 not. This is used in try_combine to detect early some cases where we
2184 can't perform combinations. */
2187 cant_combine_insn_p (rtx insn
)
2192 /* If this isn't really an insn, we can't do anything.
2193 This can occur when flow deletes an insn that it has merged into an
2194 auto-increment address. */
2195 if (! INSN_P (insn
))
2198 /* Never combine loads and stores involving hard regs that are likely
2199 to be spilled. The register allocator can usually handle such
2200 reg-reg moves by tying. If we allow the combiner to make
2201 substitutions of likely-spilled regs, reload might die.
2202 As an exception, we allow combinations involving fixed regs; these are
2203 not available to the register allocator so there's no risk involved. */
2205 set
= single_set (insn
);
2208 src
= SET_SRC (set
);
2209 dest
= SET_DEST (set
);
2210 if (GET_CODE (src
) == SUBREG
)
2211 src
= SUBREG_REG (src
);
2212 if (GET_CODE (dest
) == SUBREG
)
2213 dest
= SUBREG_REG (dest
);
2214 if (REG_P (src
) && REG_P (dest
)
2215 && ((HARD_REGISTER_P (src
)
2216 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2217 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2218 || (HARD_REGISTER_P (dest
)
2219 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2220 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2226 struct likely_spilled_retval_info
2228 unsigned regno
, nregs
;
2232 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2233 hard registers that are known to be written to / clobbered in full. */
2235 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2237 struct likely_spilled_retval_info
*const info
=
2238 (struct likely_spilled_retval_info
*) data
;
2239 unsigned regno
, nregs
;
2242 if (!REG_P (XEXP (set
, 0)))
2245 if (regno
>= info
->regno
+ info
->nregs
)
2247 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2248 if (regno
+ nregs
<= info
->regno
)
2250 new_mask
= (2U << (nregs
- 1)) - 1;
2251 if (regno
< info
->regno
)
2252 new_mask
>>= info
->regno
- regno
;
2254 new_mask
<<= regno
- info
->regno
;
2255 info
->mask
&= ~new_mask
;
2258 /* Return nonzero iff part of the return value is live during INSN, and
2259 it is likely spilled. This can happen when more than one insn is needed
2260 to copy the return value, e.g. when we consider to combine into the
2261 second copy insn for a complex value. */
2264 likely_spilled_retval_p (rtx insn
)
2266 rtx use
= BB_END (this_basic_block
);
2268 unsigned regno
, nregs
;
2269 /* We assume here that no machine mode needs more than
2270 32 hard registers when the value overlaps with a register
2271 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2273 struct likely_spilled_retval_info info
;
2275 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2277 reg
= XEXP (PATTERN (use
), 0);
2278 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2280 regno
= REGNO (reg
);
2281 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2284 mask
= (2U << (nregs
- 1)) - 1;
2286 /* Disregard parts of the return value that are set later. */
2290 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2292 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2295 /* Check if any of the (probably) live return value registers is
2300 if ((mask
& 1 << nregs
)
2301 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2307 /* Adjust INSN after we made a change to its destination.
2309 Changing the destination can invalidate notes that say something about
2310 the results of the insn and a LOG_LINK pointing to the insn. */
2313 adjust_for_new_dest (rtx insn
)
2315 /* For notes, be conservative and simply remove them. */
2316 remove_reg_equal_equiv_notes (insn
);
2318 /* The new insn will have a destination that was previously the destination
2319 of an insn just above it. Call distribute_links to make a LOG_LINK from
2320 the next use of that destination. */
2321 distribute_links (alloc_insn_link (insn
, NULL
));
2323 df_insn_rescan (insn
);
2326 /* Return TRUE if combine can reuse reg X in mode MODE.
2327 ADDED_SETS is nonzero if the original set is still required. */
2329 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2337 /* Allow hard registers if the new mode is legal, and occupies no more
2338 registers than the old mode. */
2339 if (regno
< FIRST_PSEUDO_REGISTER
)
2340 return (HARD_REGNO_MODE_OK (regno
, mode
)
2341 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2342 >= hard_regno_nregs
[regno
][mode
]));
2344 /* Or a pseudo that is only used once. */
2345 return (REG_N_SETS (regno
) == 1 && !added_sets
2346 && !REG_USERVAR_P (x
));
2350 /* Check whether X, the destination of a set, refers to part of
2351 the register specified by REG. */
2354 reg_subword_p (rtx x
, rtx reg
)
2356 /* Check that reg is an integer mode register. */
2357 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2360 if (GET_CODE (x
) == STRICT_LOW_PART
2361 || GET_CODE (x
) == ZERO_EXTRACT
)
2364 return GET_CODE (x
) == SUBREG
2365 && SUBREG_REG (x
) == reg
2366 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2369 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2370 Note that the INSN should be deleted *after* removing dead edges, so
2371 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2372 but not for a (set (pc) (label_ref FOO)). */
2375 update_cfg_for_uncondjump (rtx insn
)
2377 basic_block bb
= BLOCK_FOR_INSN (insn
);
2378 gcc_assert (BB_END (bb
) == insn
);
2380 purge_dead_edges (bb
);
2383 if (EDGE_COUNT (bb
->succs
) == 1)
2387 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2389 /* Remove barriers from the footer if there are any. */
2390 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2391 if (BARRIER_P (insn
))
2393 if (PREV_INSN (insn
))
2394 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2396 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2397 if (NEXT_INSN (insn
))
2398 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2400 else if (LABEL_P (insn
))
2405 /* Try to combine the insns I0, I1 and I2 into I3.
2406 Here I0, I1 and I2 appear earlier than I3.
2407 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2410 If we are combining more than two insns and the resulting insn is not
2411 recognized, try splitting it into two insns. If that happens, I2 and I3
2412 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2413 Otherwise, I0, I1 and I2 are pseudo-deleted.
2415 Return 0 if the combination does not work. Then nothing is changed.
2416 If we did the combination, return the insn at which combine should
2419 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2420 new direct jump instruction.
2422 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2423 been I3 passed to an earlier try_combine within the same basic
2427 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2428 rtx last_combined_insn
)
2430 /* New patterns for I3 and I2, respectively. */
2431 rtx newpat
, newi2pat
= 0;
2432 rtvec newpat_vec_with_clobbers
= 0;
2433 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2434 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2436 int added_sets_0
, added_sets_1
, added_sets_2
;
2437 /* Total number of SETs to put into I3. */
2439 /* Nonzero if I2's or I1's body now appears in I3. */
2440 int i2_is_used
= 0, i1_is_used
= 0;
2441 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2442 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2443 /* Contains I3 if the destination of I3 is used in its source, which means
2444 that the old life of I3 is being killed. If that usage is placed into
2445 I2 and not in I3, a REG_DEAD note must be made. */
2446 rtx i3dest_killed
= 0;
2447 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2448 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2449 /* Copy of SET_SRC of I1 and I0, if needed. */
2450 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2451 /* Set if I2DEST was reused as a scratch register. */
2452 bool i2scratch
= false;
2453 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2454 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2455 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2456 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2457 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2458 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2459 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2460 /* Notes that must be added to REG_NOTES in I3 and I2. */
2461 rtx new_i3_notes
, new_i2_notes
;
2462 /* Notes that we substituted I3 into I2 instead of the normal case. */
2463 int i3_subst_into_i2
= 0;
2464 /* Notes that I1, I2 or I3 is a MULT operation. */
2467 int changed_i3_dest
= 0;
2471 struct insn_link
*link
;
2473 rtx new_other_notes
;
2476 /* Only try four-insn combinations when there's high likelihood of
2477 success. Look for simple insns, such as loads of constants or
2478 binary operations involving a constant. */
2485 if (!flag_expensive_optimizations
)
2488 for (i
= 0; i
< 4; i
++)
2490 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2491 rtx set
= single_set (insn
);
2495 src
= SET_SRC (set
);
2496 if (CONSTANT_P (src
))
2501 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2503 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2504 || GET_CODE (src
) == LSHIFTRT
)
2507 if (ngood
< 2 && nshift
< 2)
2511 /* Exit early if one of the insns involved can't be used for
2513 if (cant_combine_insn_p (i3
)
2514 || cant_combine_insn_p (i2
)
2515 || (i1
&& cant_combine_insn_p (i1
))
2516 || (i0
&& cant_combine_insn_p (i0
))
2517 || likely_spilled_retval_p (i3
))
2521 undobuf
.other_insn
= 0;
2523 /* Reset the hard register usage information. */
2524 CLEAR_HARD_REG_SET (newpat_used_regs
);
2526 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2529 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2530 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2532 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2533 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2535 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2536 INSN_UID (i2
), INSN_UID (i3
));
2539 /* If multiple insns feed into one of I2 or I3, they can be in any
2540 order. To simplify the code below, reorder them in sequence. */
2541 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2542 temp
= i2
, i2
= i0
, i0
= temp
;
2543 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2544 temp
= i1
, i1
= i0
, i0
= temp
;
2545 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2546 temp
= i1
, i1
= i2
, i2
= temp
;
2548 added_links_insn
= 0;
2550 /* First check for one important special case that the code below will
2551 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2553 we may be able to replace that destination with the destination of I3.
2554 This occurs in the common code where we compute both a quotient and
2555 remainder into a structure, in which case we want to do the computation
2556 directly into the structure to avoid register-register copies.
2558 Note that this case handles both multiple sets in I2 and also cases
2559 where I2 has a number of CLOBBERs inside the PARALLEL.
2561 We make very conservative checks below and only try to handle the
2562 most common cases of this. For example, we only handle the case
2563 where I2 and I3 are adjacent to avoid making difficult register
2566 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2567 && REG_P (SET_SRC (PATTERN (i3
)))
2568 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2569 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2570 && GET_CODE (PATTERN (i2
)) == PARALLEL
2571 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2572 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2573 below would need to check what is inside (and reg_overlap_mentioned_p
2574 doesn't support those codes anyway). Don't allow those destinations;
2575 the resulting insn isn't likely to be recognized anyway. */
2576 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2577 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2578 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2579 SET_DEST (PATTERN (i3
)))
2580 && next_active_insn (i2
) == i3
)
2582 rtx p2
= PATTERN (i2
);
2584 /* Make sure that the destination of I3,
2585 which we are going to substitute into one output of I2,
2586 is not used within another output of I2. We must avoid making this:
2587 (parallel [(set (mem (reg 69)) ...)
2588 (set (reg 69) ...)])
2589 which is not well-defined as to order of actions.
2590 (Besides, reload can't handle output reloads for this.)
2592 The problem can also happen if the dest of I3 is a memory ref,
2593 if another dest in I2 is an indirect memory ref. */
2594 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2595 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2596 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2597 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2598 SET_DEST (XVECEXP (p2
, 0, i
))))
2601 if (i
== XVECLEN (p2
, 0))
2602 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2603 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2604 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2609 subst_low_luid
= DF_INSN_LUID (i2
);
2611 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2612 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2613 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2614 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2616 /* Replace the dest in I2 with our dest and make the resulting
2617 insn the new pattern for I3. Then skip to where we validate
2618 the pattern. Everything was set up above. */
2619 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2621 i3_subst_into_i2
= 1;
2622 goto validate_replacement
;
2626 /* If I2 is setting a pseudo to a constant and I3 is setting some
2627 sub-part of it to another constant, merge them by making a new
2630 && (temp
= single_set (i2
)) != 0
2631 && CONST_SCALAR_INT_P (SET_SRC (temp
))
2632 && GET_CODE (PATTERN (i3
)) == SET
2633 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2634 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2636 rtx dest
= SET_DEST (PATTERN (i3
));
2640 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2642 if (CONST_INT_P (XEXP (dest
, 1))
2643 && CONST_INT_P (XEXP (dest
, 2)))
2645 width
= INTVAL (XEXP (dest
, 1));
2646 offset
= INTVAL (XEXP (dest
, 2));
2647 dest
= XEXP (dest
, 0);
2648 if (BITS_BIG_ENDIAN
)
2649 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2654 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2655 dest
= XEXP (dest
, 0);
2656 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2662 /* If this is the low part, we're done. */
2663 if (subreg_lowpart_p (dest
))
2665 /* Handle the case where inner is twice the size of outer. */
2666 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2667 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2668 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2669 /* Otherwise give up for now. */
2676 rtx inner
= SET_SRC (PATTERN (i3
));
2677 rtx outer
= SET_SRC (temp
);
2680 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp
))),
2681 std::make_pair (inner
, GET_MODE (dest
)),
2686 subst_low_luid
= DF_INSN_LUID (i2
);
2687 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2688 i2dest
= SET_DEST (temp
);
2689 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2691 /* Replace the source in I2 with the new constant and make the
2692 resulting insn the new pattern for I3. Then skip to where we
2693 validate the pattern. Everything was set up above. */
2694 SUBST (SET_SRC (temp
),
2695 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp
))));
2697 newpat
= PATTERN (i2
);
2699 /* The dest of I3 has been replaced with the dest of I2. */
2700 changed_i3_dest
= 1;
2701 goto validate_replacement
;
2706 /* If we have no I1 and I2 looks like:
2707 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2709 make up a dummy I1 that is
2712 (set (reg:CC X) (compare:CC Y (const_int 0)))
2714 (We can ignore any trailing CLOBBERs.)
2716 This undoes a previous combination and allows us to match a branch-and-
2719 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2720 && XVECLEN (PATTERN (i2
), 0) >= 2
2721 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2722 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2724 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2725 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2726 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2727 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2728 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2729 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2731 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2732 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2737 /* We make I1 with the same INSN_UID as I2. This gives it
2738 the same DF_INSN_LUID for value tracking. Our fake I1 will
2739 never appear in the insn stream so giving it the same INSN_UID
2740 as I2 will not cause a problem. */
2742 i1
= gen_rtx_INSN (VOIDmode
, NULL_RTX
, i2
, BLOCK_FOR_INSN (i2
),
2743 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2745 INSN_UID (i1
) = INSN_UID (i2
);
2747 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2748 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2749 SET_DEST (PATTERN (i1
)));
2750 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2755 /* Verify that I2 and I1 are valid for combining. */
2756 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2757 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2759 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2766 /* Record whether I2DEST is used in I2SRC and similarly for the other
2767 cases. Knowing this will help in register status updating below. */
2768 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2769 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2770 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2771 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2772 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2773 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2774 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2775 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2776 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2778 /* For the earlier insns, determine which of the subsequent ones they
2780 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2781 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2782 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2783 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2784 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2786 /* Ensure that I3's pattern can be the destination of combines. */
2787 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2788 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2789 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2790 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2797 /* See if any of the insns is a MULT operation. Unless one is, we will
2798 reject a combination that is, since it must be slower. Be conservative
2800 if (GET_CODE (i2src
) == MULT
2801 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2802 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2803 || (GET_CODE (PATTERN (i3
)) == SET
2804 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2807 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2808 We used to do this EXCEPT in one case: I3 has a post-inc in an
2809 output operand. However, that exception can give rise to insns like
2811 which is a famous insn on the PDP-11 where the value of r3 used as the
2812 source was model-dependent. Avoid this sort of thing. */
2815 if (!(GET_CODE (PATTERN (i3
)) == SET
2816 && REG_P (SET_SRC (PATTERN (i3
)))
2817 && MEM_P (SET_DEST (PATTERN (i3
)))
2818 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2819 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2820 /* It's not the exception. */
2825 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2826 if (REG_NOTE_KIND (link
) == REG_INC
2827 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2829 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2837 /* See if the SETs in I1 or I2 need to be kept around in the merged
2838 instruction: whenever the value set there is still needed past I3.
2839 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2841 For the SET in I1, we have two cases: if I1 and I2 independently feed
2842 into I3, the set in I1 needs to be kept around unless I1DEST dies
2843 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2844 in I1 needs to be kept around unless I1DEST dies or is set in either
2845 I2 or I3. The same considerations apply to I0. */
2847 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2850 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2851 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2856 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2857 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2858 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2859 && dead_or_set_p (i2
, i0dest
)));
2863 /* We are about to copy insns for the case where they need to be kept
2864 around. Check that they can be copied in the merged instruction. */
2866 if (targetm
.cannot_copy_insn_p
2867 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2868 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2869 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2875 /* If the set in I2 needs to be kept around, we must make a copy of
2876 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2877 PATTERN (I2), we are only substituting for the original I1DEST, not into
2878 an already-substituted copy. This also prevents making self-referential
2879 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2885 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2887 i2pat
= copy_rtx (PATTERN (i2
));
2892 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2893 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2895 i1pat
= copy_rtx (PATTERN (i1
));
2900 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2901 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2903 i0pat
= copy_rtx (PATTERN (i0
));
2908 /* Substitute in the latest insn for the regs set by the earlier ones. */
2910 maxreg
= max_reg_num ();
2915 /* Many machines that don't use CC0 have insns that can both perform an
2916 arithmetic operation and set the condition code. These operations will
2917 be represented as a PARALLEL with the first element of the vector
2918 being a COMPARE of an arithmetic operation with the constant zero.
2919 The second element of the vector will set some pseudo to the result
2920 of the same arithmetic operation. If we simplify the COMPARE, we won't
2921 match such a pattern and so will generate an extra insn. Here we test
2922 for this case, where both the comparison and the operation result are
2923 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2924 I2SRC. Later we will make the PARALLEL that contains I2. */
2926 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2927 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2928 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2929 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2932 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2933 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2934 enum machine_mode compare_mode
, orig_compare_mode
;
2935 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2937 newpat
= PATTERN (i3
);
2938 newpat_dest
= SET_DEST (newpat
);
2939 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2941 if (undobuf
.other_insn
== 0
2942 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2945 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2946 compare_code
= simplify_compare_const (compare_code
,
2947 GET_MODE (i2dest
), op0
, &op1
);
2948 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2951 /* Do the rest only if op1 is const0_rtx, which may be the
2952 result of simplification. */
2953 if (op1
== const0_rtx
)
2955 /* If a single use of the CC is found, prepare to modify it
2956 when SELECT_CC_MODE returns a new CC-class mode, or when
2957 the above simplify_compare_const() returned a new comparison
2958 operator. undobuf.other_insn is assigned the CC use insn
2959 when modifying it. */
2962 #ifdef SELECT_CC_MODE
2963 enum machine_mode new_mode
2964 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2965 if (new_mode
!= orig_compare_mode
2966 && can_change_dest_mode (SET_DEST (newpat
),
2967 added_sets_2
, new_mode
))
2969 unsigned int regno
= REGNO (newpat_dest
);
2970 compare_mode
= new_mode
;
2971 if (regno
< FIRST_PSEUDO_REGISTER
)
2972 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2975 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2976 newpat_dest
= regno_reg_rtx
[regno
];
2980 /* Cases for modifying the CC-using comparison. */
2981 if (compare_code
!= orig_compare_code
2982 /* ??? Do we need to verify the zero rtx? */
2983 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2985 /* Replace cc_use_loc with entire new RTX. */
2987 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2988 newpat_dest
, const0_rtx
));
2989 undobuf
.other_insn
= cc_use_insn
;
2991 else if (compare_mode
!= orig_compare_mode
)
2993 /* Just replace the CC reg with a new mode. */
2994 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
2995 undobuf
.other_insn
= cc_use_insn
;
2999 /* Now we modify the current newpat:
3000 First, SET_DEST(newpat) is updated if the CC mode has been
3001 altered. For targets without SELECT_CC_MODE, this should be
3003 if (compare_mode
!= orig_compare_mode
)
3004 SUBST (SET_DEST (newpat
), newpat_dest
);
3005 /* This is always done to propagate i2src into newpat. */
3006 SUBST (SET_SRC (newpat
),
3007 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3008 /* Create new version of i2pat if needed; the below PARALLEL
3009 creation needs this to work correctly. */
3010 if (! rtx_equal_p (i2src
, op0
))
3011 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3017 if (i2_is_used
== 0)
3019 /* It is possible that the source of I2 or I1 may be performing
3020 an unneeded operation, such as a ZERO_EXTEND of something
3021 that is known to have the high part zero. Handle that case
3022 by letting subst look at the inner insns.
3024 Another way to do this would be to have a function that tries
3025 to simplify a single insn instead of merging two or more
3026 insns. We don't do this because of the potential of infinite
3027 loops and because of the potential extra memory required.
3028 However, doing it the way we are is a bit of a kludge and
3029 doesn't catch all cases.
3031 But only do this if -fexpensive-optimizations since it slows
3032 things down and doesn't usually win.
3034 This is not done in the COMPARE case above because the
3035 unmodified I2PAT is used in the PARALLEL and so a pattern
3036 with a modified I2SRC would not match. */
3038 if (flag_expensive_optimizations
)
3040 /* Pass pc_rtx so no substitutions are done, just
3044 subst_low_luid
= DF_INSN_LUID (i1
);
3045 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3048 subst_low_luid
= DF_INSN_LUID (i2
);
3049 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3052 n_occurrences
= 0; /* `subst' counts here */
3053 subst_low_luid
= DF_INSN_LUID (i2
);
3055 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3056 copy of I2SRC each time we substitute it, in order to avoid creating
3057 self-referential RTL when we will be substituting I1SRC for I1DEST
3058 later. Likewise if I0 feeds into I2, either directly or indirectly
3059 through I1, and I0DEST is in I0SRC. */
3060 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3061 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3062 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3063 && i0dest_in_i0src
));
3066 /* Record whether I2's body now appears within I3's body. */
3067 i2_is_used
= n_occurrences
;
3070 /* If we already got a failure, don't try to do more. Otherwise, try to
3071 substitute I1 if we have it. */
3073 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3075 /* Check that an autoincrement side-effect on I1 has not been lost.
3076 This happens if I1DEST is mentioned in I2 and dies there, and
3077 has disappeared from the new pattern. */
3078 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3080 && dead_or_set_p (i2
, i1dest
)
3081 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3082 /* Before we can do this substitution, we must redo the test done
3083 above (see detailed comments there) that ensures I1DEST isn't
3084 mentioned in any SETs in NEWPAT that are field assignments. */
3085 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3093 subst_low_luid
= DF_INSN_LUID (i1
);
3095 /* If the following substitution will modify I1SRC, make a copy of it
3096 for the case where it is substituted for I1DEST in I2PAT later. */
3097 if (added_sets_2
&& i1_feeds_i2_n
)
3098 i1src_copy
= copy_rtx (i1src
);
3100 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3101 copy of I1SRC each time we substitute it, in order to avoid creating
3102 self-referential RTL when we will be substituting I0SRC for I0DEST
3104 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3105 i0_feeds_i1_n
&& i0dest_in_i0src
);
3108 /* Record whether I1's body now appears within I3's body. */
3109 i1_is_used
= n_occurrences
;
3112 /* Likewise for I0 if we have it. */
3114 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3116 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3117 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3118 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3119 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3120 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3127 /* If the following substitution will modify I0SRC, make a copy of it
3128 for the case where it is substituted for I0DEST in I1PAT later. */
3129 if (added_sets_1
&& i0_feeds_i1_n
)
3130 i0src_copy
= copy_rtx (i0src
);
3131 /* And a copy for I0DEST in I2PAT substitution. */
3132 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3133 || (i0_feeds_i2_n
)))
3134 i0src_copy2
= copy_rtx (i0src
);
3137 subst_low_luid
= DF_INSN_LUID (i0
);
3138 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3142 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3143 to count all the ways that I2SRC and I1SRC can be used. */
3144 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3145 && i2_is_used
+ added_sets_2
> 1)
3146 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3147 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3149 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3150 && (n_occurrences
+ added_sets_0
3151 + (added_sets_1
&& i0_feeds_i1_n
)
3152 + (added_sets_2
&& i0_feeds_i2_n
)
3154 /* Fail if we tried to make a new register. */
3155 || max_reg_num () != maxreg
3156 /* Fail if we couldn't do something and have a CLOBBER. */
3157 || GET_CODE (newpat
) == CLOBBER
3158 /* Fail if this new pattern is a MULT and we didn't have one before
3159 at the outer level. */
3160 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3167 /* If the actions of the earlier insns must be kept
3168 in addition to substituting them into the latest one,
3169 we must make a new PARALLEL for the latest insn
3170 to hold additional the SETs. */
3172 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3174 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3177 if (GET_CODE (newpat
) == PARALLEL
)
3179 rtvec old
= XVEC (newpat
, 0);
3180 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3181 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3182 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3183 sizeof (old
->elem
[0]) * old
->num_elem
);
3188 total_sets
= 1 + extra_sets
;
3189 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3190 XVECEXP (newpat
, 0, 0) = old
;
3194 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3200 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3202 XVECEXP (newpat
, 0, --total_sets
) = t
;
3208 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3209 i0_feeds_i1_n
&& i0dest_in_i0src
);
3210 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3211 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3213 XVECEXP (newpat
, 0, --total_sets
) = t
;
3217 validate_replacement
:
3219 /* Note which hard regs this insn has as inputs. */
3220 mark_used_regs_combine (newpat
);
3222 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3223 consider splitting this pattern, we might need these clobbers. */
3224 if (i1
&& GET_CODE (newpat
) == PARALLEL
3225 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3227 int len
= XVECLEN (newpat
, 0);
3229 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3230 for (i
= 0; i
< len
; i
++)
3231 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3234 /* Is the result of combination a valid instruction? */
3235 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3237 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3238 the second SET's destination is a register that is unused and isn't
3239 marked as an instruction that might trap in an EH region. In that case,
3240 we just need the first SET. This can occur when simplifying a divmod
3241 insn. We *must* test for this case here because the code below that
3242 splits two independent SETs doesn't handle this case correctly when it
3243 updates the register status.
3245 It's pointless doing this if we originally had two sets, one from
3246 i3, and one from i2. Combining then splitting the parallel results
3247 in the original i2 again plus an invalid insn (which we delete).
3248 The net effect is only to move instructions around, which makes
3249 debug info less accurate.
3251 Also check the case where the first SET's destination is unused.
3252 That would not cause incorrect code, but does cause an unneeded
3255 if (insn_code_number
< 0
3256 && !(added_sets_2
&& i1
== 0)
3257 && GET_CODE (newpat
) == PARALLEL
3258 && XVECLEN (newpat
, 0) == 2
3259 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3260 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3261 && asm_noperands (newpat
) < 0)
3263 rtx set0
= XVECEXP (newpat
, 0, 0);
3264 rtx set1
= XVECEXP (newpat
, 0, 1);
3266 if (((REG_P (SET_DEST (set1
))
3267 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3268 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3269 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3270 && insn_nothrow_p (i3
)
3271 && !side_effects_p (SET_SRC (set1
)))
3274 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3277 else if (((REG_P (SET_DEST (set0
))
3278 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3279 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3280 && find_reg_note (i3
, REG_UNUSED
,
3281 SUBREG_REG (SET_DEST (set0
)))))
3282 && insn_nothrow_p (i3
)
3283 && !side_effects_p (SET_SRC (set0
)))
3286 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3288 if (insn_code_number
>= 0)
3289 changed_i3_dest
= 1;
3293 /* If we were combining three insns and the result is a simple SET
3294 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3295 insns. There are two ways to do this. It can be split using a
3296 machine-specific method (like when you have an addition of a large
3297 constant) or by combine in the function find_split_point. */
3299 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3300 && asm_noperands (newpat
) < 0)
3302 rtx parallel
, m_split
, *split
;
3304 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3305 use I2DEST as a scratch register will help. In the latter case,
3306 convert I2DEST to the mode of the source of NEWPAT if we can. */
3308 m_split
= combine_split_insns (newpat
, i3
);
3310 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3311 inputs of NEWPAT. */
3313 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3314 possible to try that as a scratch reg. This would require adding
3315 more code to make it work though. */
3317 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3319 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3321 /* First try to split using the original register as a
3322 scratch register. */
3323 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3324 gen_rtvec (2, newpat
,
3325 gen_rtx_CLOBBER (VOIDmode
,
3327 m_split
= combine_split_insns (parallel
, i3
);
3329 /* If that didn't work, try changing the mode of I2DEST if
3332 && new_mode
!= GET_MODE (i2dest
)
3333 && new_mode
!= VOIDmode
3334 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3336 enum machine_mode old_mode
= GET_MODE (i2dest
);
3339 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3340 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3343 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3344 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3347 parallel
= (gen_rtx_PARALLEL
3349 gen_rtvec (2, newpat
,
3350 gen_rtx_CLOBBER (VOIDmode
,
3352 m_split
= combine_split_insns (parallel
, i3
);
3355 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3359 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3360 buf
= undobuf
.undos
;
3361 undobuf
.undos
= buf
->next
;
3362 buf
->next
= undobuf
.frees
;
3363 undobuf
.frees
= buf
;
3367 i2scratch
= m_split
!= 0;
3370 /* If recog_for_combine has discarded clobbers, try to use them
3371 again for the split. */
3372 if (m_split
== 0 && newpat_vec_with_clobbers
)
3374 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3375 m_split
= combine_split_insns (parallel
, i3
);
3378 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3380 m_split
= PATTERN (m_split
);
3381 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3382 if (insn_code_number
>= 0)
3385 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3386 && (next_nonnote_nondebug_insn (i2
) == i3
3387 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3390 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3391 newi2pat
= PATTERN (m_split
);
3393 i3set
= single_set (NEXT_INSN (m_split
));
3394 i2set
= single_set (m_split
);
3396 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3398 /* If I2 or I3 has multiple SETs, we won't know how to track
3399 register status, so don't use these insns. If I2's destination
3400 is used between I2 and I3, we also can't use these insns. */
3402 if (i2_code_number
>= 0 && i2set
&& i3set
3403 && (next_nonnote_nondebug_insn (i2
) == i3
3404 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3405 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3407 if (insn_code_number
>= 0)
3410 /* It is possible that both insns now set the destination of I3.
3411 If so, we must show an extra use of it. */
3413 if (insn_code_number
>= 0)
3415 rtx new_i3_dest
= SET_DEST (i3set
);
3416 rtx new_i2_dest
= SET_DEST (i2set
);
3418 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3419 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3420 || GET_CODE (new_i3_dest
) == SUBREG
)
3421 new_i3_dest
= XEXP (new_i3_dest
, 0);
3423 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3424 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3425 || GET_CODE (new_i2_dest
) == SUBREG
)
3426 new_i2_dest
= XEXP (new_i2_dest
, 0);
3428 if (REG_P (new_i3_dest
)
3429 && REG_P (new_i2_dest
)
3430 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3431 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3435 /* If we can split it and use I2DEST, go ahead and see if that
3436 helps things be recognized. Verify that none of the registers
3437 are set between I2 and I3. */
3438 if (insn_code_number
< 0
3439 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3443 /* We need I2DEST in the proper mode. If it is a hard register
3444 or the only use of a pseudo, we can change its mode.
3445 Make sure we don't change a hard register to have a mode that
3446 isn't valid for it, or change the number of registers. */
3447 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3448 || GET_MODE (*split
) == VOIDmode
3449 || can_change_dest_mode (i2dest
, added_sets_2
,
3451 && (next_nonnote_nondebug_insn (i2
) == i3
3452 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3453 /* We can't overwrite I2DEST if its value is still used by
3455 && ! reg_referenced_p (i2dest
, newpat
))
3457 rtx newdest
= i2dest
;
3458 enum rtx_code split_code
= GET_CODE (*split
);
3459 enum machine_mode split_mode
= GET_MODE (*split
);
3460 bool subst_done
= false;
3461 newi2pat
= NULL_RTX
;
3465 /* *SPLIT may be part of I2SRC, so make sure we have the
3466 original expression around for later debug processing.
3467 We should not need I2SRC any more in other cases. */
3468 if (MAY_HAVE_DEBUG_INSNS
)
3469 i2src
= copy_rtx (i2src
);
3473 /* Get NEWDEST as a register in the proper mode. We have already
3474 validated that we can do this. */
3475 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3477 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3478 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3481 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3482 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3486 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3487 an ASHIFT. This can occur if it was inside a PLUS and hence
3488 appeared to be a memory address. This is a kludge. */
3489 if (split_code
== MULT
3490 && CONST_INT_P (XEXP (*split
, 1))
3491 && INTVAL (XEXP (*split
, 1)) > 0
3492 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3494 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3495 XEXP (*split
, 0), GEN_INT (i
)));
3496 /* Update split_code because we may not have a multiply
3498 split_code
= GET_CODE (*split
);
3501 #ifdef INSN_SCHEDULING
3502 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3503 be written as a ZERO_EXTEND. */
3504 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3506 #ifdef LOAD_EXTEND_OP
3507 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3508 what it really is. */
3509 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3511 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3512 SUBREG_REG (*split
)));
3515 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3516 SUBREG_REG (*split
)));
3520 /* Attempt to split binary operators using arithmetic identities. */
3521 if (BINARY_P (SET_SRC (newpat
))
3522 && split_mode
== GET_MODE (SET_SRC (newpat
))
3523 && ! side_effects_p (SET_SRC (newpat
)))
3525 rtx setsrc
= SET_SRC (newpat
);
3526 enum machine_mode mode
= GET_MODE (setsrc
);
3527 enum rtx_code code
= GET_CODE (setsrc
);
3528 rtx src_op0
= XEXP (setsrc
, 0);
3529 rtx src_op1
= XEXP (setsrc
, 1);
3531 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3532 if (rtx_equal_p (src_op0
, src_op1
))
3534 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3535 SUBST (XEXP (setsrc
, 0), newdest
);
3536 SUBST (XEXP (setsrc
, 1), newdest
);
3539 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3540 else if ((code
== PLUS
|| code
== MULT
)
3541 && GET_CODE (src_op0
) == code
3542 && GET_CODE (XEXP (src_op0
, 0)) == code
3543 && (INTEGRAL_MODE_P (mode
)
3544 || (FLOAT_MODE_P (mode
)
3545 && flag_unsafe_math_optimizations
)))
3547 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3548 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3549 rtx r
= XEXP (src_op0
, 1);
3552 /* Split both "((X op Y) op X) op Y" and
3553 "((X op Y) op Y) op X" as "T op T" where T is
3555 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3556 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3558 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3560 SUBST (XEXP (setsrc
, 0), newdest
);
3561 SUBST (XEXP (setsrc
, 1), newdest
);
3564 /* Split "((X op X) op Y) op Y)" as "T op T" where
3566 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3568 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3569 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3570 SUBST (XEXP (setsrc
, 0), newdest
);
3571 SUBST (XEXP (setsrc
, 1), newdest
);
3579 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3580 SUBST (*split
, newdest
);
3583 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3585 /* recog_for_combine might have added CLOBBERs to newi2pat.
3586 Make sure NEWPAT does not depend on the clobbered regs. */
3587 if (GET_CODE (newi2pat
) == PARALLEL
)
3588 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3589 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3591 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3592 if (reg_overlap_mentioned_p (reg
, newpat
))
3599 /* If the split point was a MULT and we didn't have one before,
3600 don't use one now. */
3601 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3602 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3606 /* Check for a case where we loaded from memory in a narrow mode and
3607 then sign extended it, but we need both registers. In that case,
3608 we have a PARALLEL with both loads from the same memory location.
3609 We can split this into a load from memory followed by a register-register
3610 copy. This saves at least one insn, more if register allocation can
3613 We cannot do this if the destination of the first assignment is a
3614 condition code register or cc0. We eliminate this case by making sure
3615 the SET_DEST and SET_SRC have the same mode.
3617 We cannot do this if the destination of the second assignment is
3618 a register that we have already assumed is zero-extended. Similarly
3619 for a SUBREG of such a register. */
3621 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3622 && GET_CODE (newpat
) == PARALLEL
3623 && XVECLEN (newpat
, 0) == 2
3624 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3625 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3626 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3627 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3628 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3629 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3630 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3631 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3633 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3634 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3635 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3637 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3638 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3639 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3640 && (reg_stat
[REGNO (temp
)].nonzero_bits
3641 != GET_MODE_MASK (word_mode
))))
3642 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3643 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3645 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3646 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3647 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3648 && (reg_stat
[REGNO (temp
)].nonzero_bits
3649 != GET_MODE_MASK (word_mode
)))))
3650 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3651 SET_SRC (XVECEXP (newpat
, 0, 1)))
3652 && ! find_reg_note (i3
, REG_UNUSED
,
3653 SET_DEST (XVECEXP (newpat
, 0, 0))))
3657 newi2pat
= XVECEXP (newpat
, 0, 0);
3658 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3659 newpat
= XVECEXP (newpat
, 0, 1);
3660 SUBST (SET_SRC (newpat
),
3661 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3662 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3664 if (i2_code_number
>= 0)
3665 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3667 if (insn_code_number
>= 0)
3671 /* Similarly, check for a case where we have a PARALLEL of two independent
3672 SETs but we started with three insns. In this case, we can do the sets
3673 as two separate insns. This case occurs when some SET allows two
3674 other insns to combine, but the destination of that SET is still live. */
3676 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3677 && GET_CODE (newpat
) == PARALLEL
3678 && XVECLEN (newpat
, 0) == 2
3679 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3680 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3681 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3682 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3683 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3684 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3685 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3686 XVECEXP (newpat
, 0, 0))
3687 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3688 XVECEXP (newpat
, 0, 1))
3689 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3690 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3692 rtx set0
= XVECEXP (newpat
, 0, 0);
3693 rtx set1
= XVECEXP (newpat
, 0, 1);
3695 /* Normally, it doesn't matter which of the two is done first,
3696 but the one that references cc0 can't be the second, and
3697 one which uses any regs/memory set in between i2 and i3 can't
3698 be first. The PARALLEL might also have been pre-existing in i3,
3699 so we need to make sure that we won't wrongly hoist a SET to i2
3700 that would conflict with a death note present in there. */
3701 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3702 && !(REG_P (SET_DEST (set1
))
3703 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3704 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3705 && find_reg_note (i2
, REG_DEAD
,
3706 SUBREG_REG (SET_DEST (set1
))))
3708 && !reg_referenced_p (cc0_rtx
, set0
)
3710 /* If I3 is a jump, ensure that set0 is a jump so that
3711 we do not create invalid RTL. */
3712 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3718 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3719 && !(REG_P (SET_DEST (set0
))
3720 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3721 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3722 && find_reg_note (i2
, REG_DEAD
,
3723 SUBREG_REG (SET_DEST (set0
))))
3725 && !reg_referenced_p (cc0_rtx
, set1
)
3727 /* If I3 is a jump, ensure that set1 is a jump so that
3728 we do not create invalid RTL. */
3729 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3741 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3743 if (i2_code_number
>= 0)
3745 /* recog_for_combine might have added CLOBBERs to newi2pat.
3746 Make sure NEWPAT does not depend on the clobbered regs. */
3747 if (GET_CODE (newi2pat
) == PARALLEL
)
3749 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3750 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3752 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3753 if (reg_overlap_mentioned_p (reg
, newpat
))
3761 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3765 /* If it still isn't recognized, fail and change things back the way they
3767 if ((insn_code_number
< 0
3768 /* Is the result a reasonable ASM_OPERANDS? */
3769 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3775 /* If we had to change another insn, make sure it is valid also. */
3776 if (undobuf
.other_insn
)
3778 CLEAR_HARD_REG_SET (newpat_used_regs
);
3780 other_pat
= PATTERN (undobuf
.other_insn
);
3781 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3784 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3792 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3793 they are adjacent to each other or not. */
3795 rtx p
= prev_nonnote_insn (i3
);
3796 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3797 && sets_cc0_p (newi2pat
))
3805 /* Only allow this combination if insn_rtx_costs reports that the
3806 replacement instructions are cheaper than the originals. */
3807 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3813 if (MAY_HAVE_DEBUG_INSNS
)
3817 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3818 if (undo
->kind
== UNDO_MODE
)
3820 rtx reg
= *undo
->where
.r
;
3821 enum machine_mode new_mode
= GET_MODE (reg
);
3822 enum machine_mode old_mode
= undo
->old_contents
.m
;
3824 /* Temporarily revert mode back. */
3825 adjust_reg_mode (reg
, old_mode
);
3827 if (reg
== i2dest
&& i2scratch
)
3829 /* If we used i2dest as a scratch register with a
3830 different mode, substitute it for the original
3831 i2src while its original mode is temporarily
3832 restored, and then clear i2scratch so that we don't
3833 do it again later. */
3834 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3837 /* Put back the new mode. */
3838 adjust_reg_mode (reg
, new_mode
);
3842 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3848 last
= last_combined_insn
;
3853 last
= undobuf
.other_insn
;
3855 if (DF_INSN_LUID (last
)
3856 < DF_INSN_LUID (last_combined_insn
))
3857 last
= last_combined_insn
;
3860 /* We're dealing with a reg that changed mode but not
3861 meaning, so we want to turn it into a subreg for
3862 the new mode. However, because of REG sharing and
3863 because its mode had already changed, we have to do
3864 it in two steps. First, replace any debug uses of
3865 reg, with its original mode temporarily restored,
3866 with this copy we have created; then, replace the
3867 copy with the SUBREG of the original shared reg,
3868 once again changed to the new mode. */
3869 propagate_for_debug (first
, last
, reg
, tempreg
,
3871 adjust_reg_mode (reg
, new_mode
);
3872 propagate_for_debug (first
, last
, tempreg
,
3873 lowpart_subreg (old_mode
, reg
, new_mode
),
3879 /* If we will be able to accept this, we have made a
3880 change to the destination of I3. This requires us to
3881 do a few adjustments. */
3883 if (changed_i3_dest
)
3885 PATTERN (i3
) = newpat
;
3886 adjust_for_new_dest (i3
);
3889 /* We now know that we can do this combination. Merge the insns and
3890 update the status of registers and LOG_LINKS. */
3892 if (undobuf
.other_insn
)
3896 PATTERN (undobuf
.other_insn
) = other_pat
;
3898 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3899 ensure that they are still valid. Then add any non-duplicate
3900 notes added by recog_for_combine. */
3901 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3903 next
= XEXP (note
, 1);
3905 if ((REG_NOTE_KIND (note
) == REG_DEAD
3906 && !reg_referenced_p (XEXP (note
, 0),
3907 PATTERN (undobuf
.other_insn
)))
3908 ||(REG_NOTE_KIND (note
) == REG_UNUSED
3909 && !reg_set_p (XEXP (note
, 0),
3910 PATTERN (undobuf
.other_insn
))))
3911 remove_note (undobuf
.other_insn
, note
);
3914 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3915 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3922 struct insn_link
*link
;
3925 /* I3 now uses what used to be its destination and which is now
3926 I2's destination. This requires us to do a few adjustments. */
3927 PATTERN (i3
) = newpat
;
3928 adjust_for_new_dest (i3
);
3930 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3933 However, some later insn might be using I2's dest and have
3934 a LOG_LINK pointing at I3. We must remove this link.
3935 The simplest way to remove the link is to point it at I1,
3936 which we know will be a NOTE. */
3938 /* newi2pat is usually a SET here; however, recog_for_combine might
3939 have added some clobbers. */
3940 if (GET_CODE (newi2pat
) == PARALLEL
)
3941 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3943 ni2dest
= SET_DEST (newi2pat
);
3945 for (insn
= NEXT_INSN (i3
);
3946 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
3947 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3948 insn
= NEXT_INSN (insn
))
3950 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3952 FOR_EACH_LOG_LINK (link
, insn
)
3953 if (link
->insn
== i3
)
3962 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3963 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3966 /* Compute which registers we expect to eliminate. newi2pat may be setting
3967 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3968 same as i3dest, in which case newi2pat may be setting i1dest. */
3969 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3970 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3973 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3974 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3977 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3978 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3982 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3984 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3985 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3987 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3989 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3991 /* Ensure that we do not have something that should not be shared but
3992 occurs multiple times in the new insns. Check this by first
3993 resetting all the `used' flags and then copying anything is shared. */
3995 reset_used_flags (i3notes
);
3996 reset_used_flags (i2notes
);
3997 reset_used_flags (i1notes
);
3998 reset_used_flags (i0notes
);
3999 reset_used_flags (newpat
);
4000 reset_used_flags (newi2pat
);
4001 if (undobuf
.other_insn
)
4002 reset_used_flags (PATTERN (undobuf
.other_insn
));
4004 i3notes
= copy_rtx_if_shared (i3notes
);
4005 i2notes
= copy_rtx_if_shared (i2notes
);
4006 i1notes
= copy_rtx_if_shared (i1notes
);
4007 i0notes
= copy_rtx_if_shared (i0notes
);
4008 newpat
= copy_rtx_if_shared (newpat
);
4009 newi2pat
= copy_rtx_if_shared (newi2pat
);
4010 if (undobuf
.other_insn
)
4011 reset_used_flags (PATTERN (undobuf
.other_insn
));
4013 INSN_CODE (i3
) = insn_code_number
;
4014 PATTERN (i3
) = newpat
;
4016 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4018 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4020 reset_used_flags (call_usage
);
4021 call_usage
= copy_rtx (call_usage
);
4025 /* I2SRC must still be meaningful at this point. Some splitting
4026 operations can invalidate I2SRC, but those operations do not
4029 replace_rtx (call_usage
, i2dest
, i2src
);
4033 replace_rtx (call_usage
, i1dest
, i1src
);
4035 replace_rtx (call_usage
, i0dest
, i0src
);
4037 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4040 if (undobuf
.other_insn
)
4041 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4043 /* We had one special case above where I2 had more than one set and
4044 we replaced a destination of one of those sets with the destination
4045 of I3. In that case, we have to update LOG_LINKS of insns later
4046 in this basic block. Note that this (expensive) case is rare.
4048 Also, in this case, we must pretend that all REG_NOTEs for I2
4049 actually came from I3, so that REG_UNUSED notes from I2 will be
4050 properly handled. */
4052 if (i3_subst_into_i2
)
4054 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4055 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4056 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4057 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4058 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4059 && ! find_reg_note (i2
, REG_UNUSED
,
4060 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4061 for (temp
= NEXT_INSN (i2
);
4063 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4064 || BB_HEAD (this_basic_block
) != temp
);
4065 temp
= NEXT_INSN (temp
))
4066 if (temp
!= i3
&& INSN_P (temp
))
4067 FOR_EACH_LOG_LINK (link
, temp
)
4068 if (link
->insn
== i2
)
4074 while (XEXP (link
, 1))
4075 link
= XEXP (link
, 1);
4076 XEXP (link
, 1) = i2notes
;
4083 LOG_LINKS (i3
) = NULL
;
4085 LOG_LINKS (i2
) = NULL
;
4090 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4091 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4093 INSN_CODE (i2
) = i2_code_number
;
4094 PATTERN (i2
) = newi2pat
;
4098 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4099 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4101 SET_INSN_DELETED (i2
);
4106 LOG_LINKS (i1
) = NULL
;
4108 if (MAY_HAVE_DEBUG_INSNS
)
4109 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4111 SET_INSN_DELETED (i1
);
4116 LOG_LINKS (i0
) = NULL
;
4118 if (MAY_HAVE_DEBUG_INSNS
)
4119 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4121 SET_INSN_DELETED (i0
);
4124 /* Get death notes for everything that is now used in either I3 or
4125 I2 and used to die in a previous insn. If we built two new
4126 patterns, move from I1 to I2 then I2 to I3 so that we get the
4127 proper movement on registers that I2 modifies. */
4130 from_luid
= DF_INSN_LUID (i0
);
4132 from_luid
= DF_INSN_LUID (i1
);
4134 from_luid
= DF_INSN_LUID (i2
);
4136 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4137 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4139 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4141 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4142 elim_i2
, elim_i1
, elim_i0
);
4144 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4145 elim_i2
, elim_i1
, elim_i0
);
4147 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4148 elim_i2
, elim_i1
, elim_i0
);
4150 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4151 elim_i2
, elim_i1
, elim_i0
);
4153 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4154 elim_i2
, elim_i1
, elim_i0
);
4156 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4157 know these are REG_UNUSED and want them to go to the desired insn,
4158 so we always pass it as i3. */
4160 if (newi2pat
&& new_i2_notes
)
4161 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4165 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4168 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4169 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4170 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4171 in that case, it might delete I2. Similarly for I2 and I1.
4172 Show an additional death due to the REG_DEAD note we make here. If
4173 we discard it in distribute_notes, we will decrement it again. */
4177 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4178 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4179 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, elim_i2
,
4182 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4183 elim_i2
, elim_i1
, elim_i0
);
4186 if (i2dest_in_i2src
)
4188 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4189 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4190 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4191 NULL_RTX
, NULL_RTX
);
4193 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4194 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4197 if (i1dest_in_i1src
)
4199 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4200 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4201 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4202 NULL_RTX
, NULL_RTX
);
4204 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4205 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4208 if (i0dest_in_i0src
)
4210 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4211 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4212 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4213 NULL_RTX
, NULL_RTX
);
4215 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4216 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4219 distribute_links (i3links
);
4220 distribute_links (i2links
);
4221 distribute_links (i1links
);
4222 distribute_links (i0links
);
4226 struct insn_link
*link
;
4227 rtx i2_insn
= 0, i2_val
= 0, set
;
4229 /* The insn that used to set this register doesn't exist, and
4230 this life of the register may not exist either. See if one of
4231 I3's links points to an insn that sets I2DEST. If it does,
4232 that is now the last known value for I2DEST. If we don't update
4233 this and I2 set the register to a value that depended on its old
4234 contents, we will get confused. If this insn is used, thing
4235 will be set correctly in combine_instructions. */
4236 FOR_EACH_LOG_LINK (link
, i3
)
4237 if ((set
= single_set (link
->insn
)) != 0
4238 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4239 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4241 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4243 /* If the reg formerly set in I2 died only once and that was in I3,
4244 zero its use count so it won't make `reload' do any work. */
4246 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4247 && ! i2dest_in_i2src
)
4248 INC_REG_N_SETS (REGNO (i2dest
), -1);
4251 if (i1
&& REG_P (i1dest
))
4253 struct insn_link
*link
;
4254 rtx i1_insn
= 0, i1_val
= 0, set
;
4256 FOR_EACH_LOG_LINK (link
, i3
)
4257 if ((set
= single_set (link
->insn
)) != 0
4258 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4259 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4261 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4263 if (! added_sets_1
&& ! i1dest_in_i1src
)
4264 INC_REG_N_SETS (REGNO (i1dest
), -1);
4267 if (i0
&& REG_P (i0dest
))
4269 struct insn_link
*link
;
4270 rtx i0_insn
= 0, i0_val
= 0, set
;
4272 FOR_EACH_LOG_LINK (link
, i3
)
4273 if ((set
= single_set (link
->insn
)) != 0
4274 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4275 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4277 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4279 if (! added_sets_0
&& ! i0dest_in_i0src
)
4280 INC_REG_N_SETS (REGNO (i0dest
), -1);
4283 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4284 been made to this insn. The order is important, because newi2pat
4285 can affect nonzero_bits of newpat. */
4287 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4288 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4291 if (undobuf
.other_insn
!= NULL_RTX
)
4295 fprintf (dump_file
, "modifying other_insn ");
4296 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4298 df_insn_rescan (undobuf
.other_insn
);
4301 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4305 fprintf (dump_file
, "modifying insn i0 ");
4306 dump_insn_slim (dump_file
, i0
);
4308 df_insn_rescan (i0
);
4311 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4315 fprintf (dump_file
, "modifying insn i1 ");
4316 dump_insn_slim (dump_file
, i1
);
4318 df_insn_rescan (i1
);
4321 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4325 fprintf (dump_file
, "modifying insn i2 ");
4326 dump_insn_slim (dump_file
, i2
);
4328 df_insn_rescan (i2
);
4331 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4335 fprintf (dump_file
, "modifying insn i3 ");
4336 dump_insn_slim (dump_file
, i3
);
4338 df_insn_rescan (i3
);
4341 /* Set new_direct_jump_p if a new return or simple jump instruction
4342 has been created. Adjust the CFG accordingly. */
4343 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4345 *new_direct_jump_p
= 1;
4346 mark_jump_label (PATTERN (i3
), i3
, 0);
4347 update_cfg_for_uncondjump (i3
);
4350 if (undobuf
.other_insn
!= NULL_RTX
4351 && (returnjump_p (undobuf
.other_insn
)
4352 || any_uncondjump_p (undobuf
.other_insn
)))
4354 *new_direct_jump_p
= 1;
4355 update_cfg_for_uncondjump (undobuf
.other_insn
);
4358 /* A noop might also need cleaning up of CFG, if it comes from the
4359 simplification of a jump. */
4361 && GET_CODE (newpat
) == SET
4362 && SET_SRC (newpat
) == pc_rtx
4363 && SET_DEST (newpat
) == pc_rtx
)
4365 *new_direct_jump_p
= 1;
4366 update_cfg_for_uncondjump (i3
);
4369 if (undobuf
.other_insn
!= NULL_RTX
4370 && JUMP_P (undobuf
.other_insn
)
4371 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4372 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4373 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4375 *new_direct_jump_p
= 1;
4376 update_cfg_for_uncondjump (undobuf
.other_insn
);
4379 combine_successes
++;
4382 if (added_links_insn
4383 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4384 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4385 return added_links_insn
;
4387 return newi2pat
? i2
: i3
;
4390 /* Undo all the modifications recorded in undobuf. */
4395 struct undo
*undo
, *next
;
4397 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4403 *undo
->where
.r
= undo
->old_contents
.r
;
4406 *undo
->where
.i
= undo
->old_contents
.i
;
4409 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4412 *undo
->where
.l
= undo
->old_contents
.l
;
4418 undo
->next
= undobuf
.frees
;
4419 undobuf
.frees
= undo
;
4425 /* We've committed to accepting the changes we made. Move all
4426 of the undos to the free list. */
4431 struct undo
*undo
, *next
;
4433 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4436 undo
->next
= undobuf
.frees
;
4437 undobuf
.frees
= undo
;
4442 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4443 where we have an arithmetic expression and return that point. LOC will
4446 try_combine will call this function to see if an insn can be split into
4450 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4453 enum rtx_code code
= GET_CODE (x
);
4455 unsigned HOST_WIDE_INT len
= 0;
4456 HOST_WIDE_INT pos
= 0;
4458 rtx inner
= NULL_RTX
;
4460 /* First special-case some codes. */
4464 #ifdef INSN_SCHEDULING
4465 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4467 if (MEM_P (SUBREG_REG (x
)))
4470 return find_split_point (&SUBREG_REG (x
), insn
, false);
4474 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4475 using LO_SUM and HIGH. */
4476 if (GET_CODE (XEXP (x
, 0)) == CONST
4477 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4479 enum machine_mode address_mode
= get_address_mode (x
);
4482 gen_rtx_LO_SUM (address_mode
,
4483 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4485 return &XEXP (XEXP (x
, 0), 0);
4489 /* If we have a PLUS whose second operand is a constant and the
4490 address is not valid, perhaps will can split it up using
4491 the machine-specific way to split large constants. We use
4492 the first pseudo-reg (one of the virtual regs) as a placeholder;
4493 it will not remain in the result. */
4494 if (GET_CODE (XEXP (x
, 0)) == PLUS
4495 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4496 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4497 MEM_ADDR_SPACE (x
)))
4499 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4500 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4504 /* This should have produced two insns, each of which sets our
4505 placeholder. If the source of the second is a valid address,
4506 we can make put both sources together and make a split point
4510 && NEXT_INSN (seq
) != NULL_RTX
4511 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4512 && NONJUMP_INSN_P (seq
)
4513 && GET_CODE (PATTERN (seq
)) == SET
4514 && SET_DEST (PATTERN (seq
)) == reg
4515 && ! reg_mentioned_p (reg
,
4516 SET_SRC (PATTERN (seq
)))
4517 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4518 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4519 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4520 && memory_address_addr_space_p
4521 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4522 MEM_ADDR_SPACE (x
)))
4524 rtx src1
= SET_SRC (PATTERN (seq
));
4525 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4527 /* Replace the placeholder in SRC2 with SRC1. If we can
4528 find where in SRC2 it was placed, that can become our
4529 split point and we can replace this address with SRC2.
4530 Just try two obvious places. */
4532 src2
= replace_rtx (src2
, reg
, src1
);
4534 if (XEXP (src2
, 0) == src1
)
4535 split
= &XEXP (src2
, 0);
4536 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4537 && XEXP (XEXP (src2
, 0), 0) == src1
)
4538 split
= &XEXP (XEXP (src2
, 0), 0);
4542 SUBST (XEXP (x
, 0), src2
);
4547 /* If that didn't work, perhaps the first operand is complex and
4548 needs to be computed separately, so make a split point there.
4549 This will occur on machines that just support REG + CONST
4550 and have a constant moved through some previous computation. */
4552 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4553 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4554 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4555 return &XEXP (XEXP (x
, 0), 0);
4558 /* If we have a PLUS whose first operand is complex, try computing it
4559 separately by making a split there. */
4560 if (GET_CODE (XEXP (x
, 0)) == PLUS
4561 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4563 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4564 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4565 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4566 return &XEXP (XEXP (x
, 0), 0);
4571 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4572 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4573 we need to put the operand into a register. So split at that
4576 if (SET_DEST (x
) == cc0_rtx
4577 && GET_CODE (SET_SRC (x
)) != COMPARE
4578 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4579 && !OBJECT_P (SET_SRC (x
))
4580 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4581 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4582 return &SET_SRC (x
);
4585 /* See if we can split SET_SRC as it stands. */
4586 split
= find_split_point (&SET_SRC (x
), insn
, true);
4587 if (split
&& split
!= &SET_SRC (x
))
4590 /* See if we can split SET_DEST as it stands. */
4591 split
= find_split_point (&SET_DEST (x
), insn
, false);
4592 if (split
&& split
!= &SET_DEST (x
))
4595 /* See if this is a bitfield assignment with everything constant. If
4596 so, this is an IOR of an AND, so split it into that. */
4597 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4598 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4599 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4600 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4601 && CONST_INT_P (SET_SRC (x
))
4602 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4603 + INTVAL (XEXP (SET_DEST (x
), 2)))
4604 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4605 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4607 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4608 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4609 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4610 rtx dest
= XEXP (SET_DEST (x
), 0);
4611 enum machine_mode mode
= GET_MODE (dest
);
4612 unsigned HOST_WIDE_INT mask
4613 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4616 if (BITS_BIG_ENDIAN
)
4617 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4619 or_mask
= gen_int_mode (src
<< pos
, mode
);
4622 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4625 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4627 simplify_gen_binary (IOR
, mode
,
4628 simplify_gen_binary (AND
, mode
,
4633 SUBST (SET_DEST (x
), dest
);
4635 split
= find_split_point (&SET_SRC (x
), insn
, true);
4636 if (split
&& split
!= &SET_SRC (x
))
4640 /* Otherwise, see if this is an operation that we can split into two.
4641 If so, try to split that. */
4642 code
= GET_CODE (SET_SRC (x
));
4647 /* If we are AND'ing with a large constant that is only a single
4648 bit and the result is only being used in a context where we
4649 need to know if it is zero or nonzero, replace it with a bit
4650 extraction. This will avoid the large constant, which might
4651 have taken more than one insn to make. If the constant were
4652 not a valid argument to the AND but took only one insn to make,
4653 this is no worse, but if it took more than one insn, it will
4656 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4657 && REG_P (XEXP (SET_SRC (x
), 0))
4658 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4659 && REG_P (SET_DEST (x
))
4660 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4661 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4662 && XEXP (*split
, 0) == SET_DEST (x
)
4663 && XEXP (*split
, 1) == const0_rtx
)
4665 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4666 XEXP (SET_SRC (x
), 0),
4667 pos
, NULL_RTX
, 1, 1, 0, 0);
4668 if (extraction
!= 0)
4670 SUBST (SET_SRC (x
), extraction
);
4671 return find_split_point (loc
, insn
, false);
4677 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4678 is known to be on, this can be converted into a NEG of a shift. */
4679 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4680 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4681 && 1 <= (pos
= exact_log2
4682 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4683 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4685 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4689 gen_rtx_LSHIFTRT (mode
,
4690 XEXP (SET_SRC (x
), 0),
4693 split
= find_split_point (&SET_SRC (x
), insn
, true);
4694 if (split
&& split
!= &SET_SRC (x
))
4700 inner
= XEXP (SET_SRC (x
), 0);
4702 /* We can't optimize if either mode is a partial integer
4703 mode as we don't know how many bits are significant
4705 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4706 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4710 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4716 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4717 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4719 inner
= XEXP (SET_SRC (x
), 0);
4720 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4721 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4723 if (BITS_BIG_ENDIAN
)
4724 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4725 unsignedp
= (code
== ZERO_EXTRACT
);
4734 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4736 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4738 /* For unsigned, we have a choice of a shift followed by an
4739 AND or two shifts. Use two shifts for field sizes where the
4740 constant might be too large. We assume here that we can
4741 always at least get 8-bit constants in an AND insn, which is
4742 true for every current RISC. */
4744 if (unsignedp
&& len
<= 8)
4746 unsigned HOST_WIDE_INT mask
4747 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4751 (mode
, gen_lowpart (mode
, inner
),
4753 gen_int_mode (mask
, mode
)));
4755 split
= find_split_point (&SET_SRC (x
), insn
, true);
4756 if (split
&& split
!= &SET_SRC (x
))
4763 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4764 gen_rtx_ASHIFT (mode
,
4765 gen_lowpart (mode
, inner
),
4766 GEN_INT (GET_MODE_PRECISION (mode
)
4768 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4770 split
= find_split_point (&SET_SRC (x
), insn
, true);
4771 if (split
&& split
!= &SET_SRC (x
))
4776 /* See if this is a simple operation with a constant as the second
4777 operand. It might be that this constant is out of range and hence
4778 could be used as a split point. */
4779 if (BINARY_P (SET_SRC (x
))
4780 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4781 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4782 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4783 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4784 return &XEXP (SET_SRC (x
), 1);
4786 /* Finally, see if this is a simple operation with its first operand
4787 not in a register. The operation might require this operand in a
4788 register, so return it as a split point. We can always do this
4789 because if the first operand were another operation, we would have
4790 already found it as a split point. */
4791 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4792 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4793 return &XEXP (SET_SRC (x
), 0);
4799 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4800 it is better to write this as (not (ior A B)) so we can split it.
4801 Similarly for IOR. */
4802 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4805 gen_rtx_NOT (GET_MODE (x
),
4806 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4808 XEXP (XEXP (x
, 0), 0),
4809 XEXP (XEXP (x
, 1), 0))));
4810 return find_split_point (loc
, insn
, set_src
);
4813 /* Many RISC machines have a large set of logical insns. If the
4814 second operand is a NOT, put it first so we will try to split the
4815 other operand first. */
4816 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4818 rtx tem
= XEXP (x
, 0);
4819 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4820 SUBST (XEXP (x
, 1), tem
);
4826 /* Canonicalization can produce (minus A (mult B C)), where C is a
4827 constant. It may be better to try splitting (plus (mult B -C) A)
4828 instead if this isn't a multiply by a power of two. */
4829 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4830 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4831 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4833 enum machine_mode mode
= GET_MODE (x
);
4834 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4835 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4836 SUBST (*loc
, gen_rtx_PLUS (mode
,
4838 XEXP (XEXP (x
, 1), 0),
4839 gen_int_mode (other_int
,
4842 return find_split_point (loc
, insn
, set_src
);
4845 /* Split at a multiply-accumulate instruction. However if this is
4846 the SET_SRC, we likely do not have such an instruction and it's
4847 worthless to try this split. */
4848 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4855 /* Otherwise, select our actions depending on our rtx class. */
4856 switch (GET_RTX_CLASS (code
))
4858 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4860 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4863 /* ... fall through ... */
4865 case RTX_COMM_ARITH
:
4867 case RTX_COMM_COMPARE
:
4868 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4871 /* ... fall through ... */
4873 /* Some machines have (and (shift ...) ...) insns. If X is not
4874 an AND, but XEXP (X, 0) is, use it as our split point. */
4875 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4876 return &XEXP (x
, 0);
4878 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4884 /* Otherwise, we don't have a split point. */
4889 /* Throughout X, replace FROM with TO, and return the result.
4890 The result is TO if X is FROM;
4891 otherwise the result is X, but its contents may have been modified.
4892 If they were modified, a record was made in undobuf so that
4893 undo_all will (among other things) return X to its original state.
4895 If the number of changes necessary is too much to record to undo,
4896 the excess changes are not made, so the result is invalid.
4897 The changes already made can still be undone.
4898 undobuf.num_undo is incremented for such changes, so by testing that
4899 the caller can tell whether the result is valid.
4901 `n_occurrences' is incremented each time FROM is replaced.
4903 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4905 IN_COND is nonzero if we are at the top level of a condition.
4907 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4908 by copying if `n_occurrences' is nonzero. */
4911 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4913 enum rtx_code code
= GET_CODE (x
);
4914 enum machine_mode op0_mode
= VOIDmode
;
4919 /* Two expressions are equal if they are identical copies of a shared
4920 RTX or if they are both registers with the same register number
4923 #define COMBINE_RTX_EQUAL_P(X,Y) \
4925 || (REG_P (X) && REG_P (Y) \
4926 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4928 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4931 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4934 /* If X and FROM are the same register but different modes, they
4935 will not have been seen as equal above. However, the log links code
4936 will make a LOG_LINKS entry for that case. If we do nothing, we
4937 will try to rerecognize our original insn and, when it succeeds,
4938 we will delete the feeding insn, which is incorrect.
4940 So force this insn not to match in this (rare) case. */
4941 if (! in_dest
&& code
== REG
&& REG_P (from
)
4942 && reg_overlap_mentioned_p (x
, from
))
4943 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4945 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4946 of which may contain things that can be combined. */
4947 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4950 /* It is possible to have a subexpression appear twice in the insn.
4951 Suppose that FROM is a register that appears within TO.
4952 Then, after that subexpression has been scanned once by `subst',
4953 the second time it is scanned, TO may be found. If we were
4954 to scan TO here, we would find FROM within it and create a
4955 self-referent rtl structure which is completely wrong. */
4956 if (COMBINE_RTX_EQUAL_P (x
, to
))
4959 /* Parallel asm_operands need special attention because all of the
4960 inputs are shared across the arms. Furthermore, unsharing the
4961 rtl results in recognition failures. Failure to handle this case
4962 specially can result in circular rtl.
4964 Solve this by doing a normal pass across the first entry of the
4965 parallel, and only processing the SET_DESTs of the subsequent
4968 if (code
== PARALLEL
4969 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4970 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4972 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4974 /* If this substitution failed, this whole thing fails. */
4975 if (GET_CODE (new_rtx
) == CLOBBER
4976 && XEXP (new_rtx
, 0) == const0_rtx
)
4979 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4981 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4983 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4986 && GET_CODE (dest
) != CC0
4987 && GET_CODE (dest
) != PC
)
4989 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4991 /* If this substitution failed, this whole thing fails. */
4992 if (GET_CODE (new_rtx
) == CLOBBER
4993 && XEXP (new_rtx
, 0) == const0_rtx
)
4996 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5002 len
= GET_RTX_LENGTH (code
);
5003 fmt
= GET_RTX_FORMAT (code
);
5005 /* We don't need to process a SET_DEST that is a register, CC0,
5006 or PC, so set up to skip this common case. All other cases
5007 where we want to suppress replacing something inside a
5008 SET_SRC are handled via the IN_DEST operand. */
5010 && (REG_P (SET_DEST (x
))
5011 || GET_CODE (SET_DEST (x
)) == CC0
5012 || GET_CODE (SET_DEST (x
)) == PC
))
5015 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5018 op0_mode
= GET_MODE (XEXP (x
, 0));
5020 for (i
= 0; i
< len
; i
++)
5025 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5027 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5029 new_rtx
= (unique_copy
&& n_occurrences
5030 ? copy_rtx (to
) : to
);
5035 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5038 /* If this substitution failed, this whole thing
5040 if (GET_CODE (new_rtx
) == CLOBBER
5041 && XEXP (new_rtx
, 0) == const0_rtx
)
5045 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5048 else if (fmt
[i
] == 'e')
5050 /* If this is a register being set, ignore it. */
5051 new_rtx
= XEXP (x
, i
);
5054 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5056 || code
== STRICT_LOW_PART
))
5059 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5061 /* In general, don't install a subreg involving two
5062 modes not tieable. It can worsen register
5063 allocation, and can even make invalid reload
5064 insns, since the reg inside may need to be copied
5065 from in the outside mode, and that may be invalid
5066 if it is an fp reg copied in integer mode.
5068 We allow two exceptions to this: It is valid if
5069 it is inside another SUBREG and the mode of that
5070 SUBREG and the mode of the inside of TO is
5071 tieable and it is valid if X is a SET that copies
5074 if (GET_CODE (to
) == SUBREG
5075 && ! MODES_TIEABLE_P (GET_MODE (to
),
5076 GET_MODE (SUBREG_REG (to
)))
5077 && ! (code
== SUBREG
5078 && MODES_TIEABLE_P (GET_MODE (x
),
5079 GET_MODE (SUBREG_REG (to
))))
5081 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5084 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5086 #ifdef CANNOT_CHANGE_MODE_CLASS
5089 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5090 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5093 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5096 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5100 /* If we are in a SET_DEST, suppress most cases unless we
5101 have gone inside a MEM, in which case we want to
5102 simplify the address. We assume here that things that
5103 are actually part of the destination have their inner
5104 parts in the first expression. This is true for SUBREG,
5105 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5106 things aside from REG and MEM that should appear in a
5108 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5110 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5111 || code
== ZERO_EXTRACT
))
5114 code
== IF_THEN_ELSE
&& i
== 0,
5117 /* If we found that we will have to reject this combination,
5118 indicate that by returning the CLOBBER ourselves, rather than
5119 an expression containing it. This will speed things up as
5120 well as prevent accidents where two CLOBBERs are considered
5121 to be equal, thus producing an incorrect simplification. */
5123 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5126 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5128 enum machine_mode mode
= GET_MODE (x
);
5130 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5131 GET_MODE (SUBREG_REG (x
)),
5134 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5136 else if (CONST_SCALAR_INT_P (new_rtx
)
5137 && GET_CODE (x
) == ZERO_EXTEND
)
5139 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5140 new_rtx
, GET_MODE (XEXP (x
, 0)));
5144 SUBST (XEXP (x
, i
), new_rtx
);
5149 /* Check if we are loading something from the constant pool via float
5150 extension; in this case we would undo compress_float_constant
5151 optimization and degenerate constant load to an immediate value. */
5152 if (GET_CODE (x
) == FLOAT_EXTEND
5153 && MEM_P (XEXP (x
, 0))
5154 && MEM_READONLY_P (XEXP (x
, 0)))
5156 rtx tmp
= avoid_constant_pool_reference (x
);
5161 /* Try to simplify X. If the simplification changed the code, it is likely
5162 that further simplification will help, so loop, but limit the number
5163 of repetitions that will be performed. */
5165 for (i
= 0; i
< 4; i
++)
5167 /* If X is sufficiently simple, don't bother trying to do anything
5169 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5170 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5172 if (GET_CODE (x
) == code
)
5175 code
= GET_CODE (x
);
5177 /* We no longer know the original mode of operand 0 since we
5178 have changed the form of X) */
5179 op0_mode
= VOIDmode
;
5185 /* Simplify X, a piece of RTL. We just operate on the expression at the
5186 outer level; call `subst' to simplify recursively. Return the new
5189 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5190 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5194 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5197 enum rtx_code code
= GET_CODE (x
);
5198 enum machine_mode mode
= GET_MODE (x
);
5202 /* If this is a commutative operation, put a constant last and a complex
5203 expression first. We don't need to do this for comparisons here. */
5204 if (COMMUTATIVE_ARITH_P (x
)
5205 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5208 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5209 SUBST (XEXP (x
, 1), temp
);
5212 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5213 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5214 things. Check for cases where both arms are testing the same
5217 Don't do anything if all operands are very simple. */
5220 && ((!OBJECT_P (XEXP (x
, 0))
5221 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5222 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5223 || (!OBJECT_P (XEXP (x
, 1))
5224 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5225 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5227 && (!OBJECT_P (XEXP (x
, 0))
5228 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5229 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5231 rtx cond
, true_rtx
, false_rtx
;
5233 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5235 /* If everything is a comparison, what we have is highly unlikely
5236 to be simpler, so don't use it. */
5237 && ! (COMPARISON_P (x
)
5238 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5240 rtx cop1
= const0_rtx
;
5241 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5243 if (cond_code
== NE
&& COMPARISON_P (cond
))
5246 /* Simplify the alternative arms; this may collapse the true and
5247 false arms to store-flag values. Be careful to use copy_rtx
5248 here since true_rtx or false_rtx might share RTL with x as a
5249 result of the if_then_else_cond call above. */
5250 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5251 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5253 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5254 is unlikely to be simpler. */
5255 if (general_operand (true_rtx
, VOIDmode
)
5256 && general_operand (false_rtx
, VOIDmode
))
5258 enum rtx_code reversed
;
5260 /* Restarting if we generate a store-flag expression will cause
5261 us to loop. Just drop through in this case. */
5263 /* If the result values are STORE_FLAG_VALUE and zero, we can
5264 just make the comparison operation. */
5265 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5266 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5268 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5269 && ((reversed
= reversed_comparison_code_parts
5270 (cond_code
, cond
, cop1
, NULL
))
5272 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5275 /* Likewise, we can make the negate of a comparison operation
5276 if the result values are - STORE_FLAG_VALUE and zero. */
5277 else if (CONST_INT_P (true_rtx
)
5278 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5279 && false_rtx
== const0_rtx
)
5280 x
= simplify_gen_unary (NEG
, mode
,
5281 simplify_gen_relational (cond_code
,
5285 else if (CONST_INT_P (false_rtx
)
5286 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5287 && true_rtx
== const0_rtx
5288 && ((reversed
= reversed_comparison_code_parts
5289 (cond_code
, cond
, cop1
, NULL
))
5291 x
= simplify_gen_unary (NEG
, mode
,
5292 simplify_gen_relational (reversed
,
5297 return gen_rtx_IF_THEN_ELSE (mode
,
5298 simplify_gen_relational (cond_code
,
5303 true_rtx
, false_rtx
);
5305 code
= GET_CODE (x
);
5306 op0_mode
= VOIDmode
;
5311 /* Try to fold this expression in case we have constants that weren't
5314 switch (GET_RTX_CLASS (code
))
5317 if (op0_mode
== VOIDmode
)
5318 op0_mode
= GET_MODE (XEXP (x
, 0));
5319 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5322 case RTX_COMM_COMPARE
:
5324 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5325 if (cmp_mode
== VOIDmode
)
5327 cmp_mode
= GET_MODE (XEXP (x
, 1));
5328 if (cmp_mode
== VOIDmode
)
5329 cmp_mode
= op0_mode
;
5331 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5332 XEXP (x
, 0), XEXP (x
, 1));
5335 case RTX_COMM_ARITH
:
5337 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5339 case RTX_BITFIELD_OPS
:
5341 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5342 XEXP (x
, 1), XEXP (x
, 2));
5351 code
= GET_CODE (temp
);
5352 op0_mode
= VOIDmode
;
5353 mode
= GET_MODE (temp
);
5356 /* First see if we can apply the inverse distributive law. */
5357 if (code
== PLUS
|| code
== MINUS
5358 || code
== AND
|| code
== IOR
|| code
== XOR
)
5360 x
= apply_distributive_law (x
);
5361 code
= GET_CODE (x
);
5362 op0_mode
= VOIDmode
;
5365 /* If CODE is an associative operation not otherwise handled, see if we
5366 can associate some operands. This can win if they are constants or
5367 if they are logically related (i.e. (a & b) & a). */
5368 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5369 || code
== AND
|| code
== IOR
|| code
== XOR
5370 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5371 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5372 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5374 if (GET_CODE (XEXP (x
, 0)) == code
)
5376 rtx other
= XEXP (XEXP (x
, 0), 0);
5377 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5378 rtx inner_op1
= XEXP (x
, 1);
5381 /* Make sure we pass the constant operand if any as the second
5382 one if this is a commutative operation. */
5383 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5385 rtx tem
= inner_op0
;
5386 inner_op0
= inner_op1
;
5389 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5390 : code
== DIV
? MULT
5392 mode
, inner_op0
, inner_op1
);
5394 /* For commutative operations, try the other pair if that one
5396 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5398 other
= XEXP (XEXP (x
, 0), 1);
5399 inner
= simplify_binary_operation (code
, mode
,
5400 XEXP (XEXP (x
, 0), 0),
5405 return simplify_gen_binary (code
, mode
, other
, inner
);
5409 /* A little bit of algebraic simplification here. */
5413 /* Ensure that our address has any ASHIFTs converted to MULT in case
5414 address-recognizing predicates are called later. */
5415 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5416 SUBST (XEXP (x
, 0), temp
);
5420 if (op0_mode
== VOIDmode
)
5421 op0_mode
= GET_MODE (SUBREG_REG (x
));
5423 /* See if this can be moved to simplify_subreg. */
5424 if (CONSTANT_P (SUBREG_REG (x
))
5425 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5426 /* Don't call gen_lowpart if the inner mode
5427 is VOIDmode and we cannot simplify it, as SUBREG without
5428 inner mode is invalid. */
5429 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5430 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5431 return gen_lowpart (mode
, SUBREG_REG (x
));
5433 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5437 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5442 /* If op is known to have all lower bits zero, the result is zero. */
5444 && SCALAR_INT_MODE_P (mode
)
5445 && SCALAR_INT_MODE_P (op0_mode
)
5446 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5447 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5448 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5449 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5450 & GET_MODE_MASK (mode
)) == 0)
5451 return CONST0_RTX (mode
);
5454 /* Don't change the mode of the MEM if that would change the meaning
5456 if (MEM_P (SUBREG_REG (x
))
5457 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5458 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5459 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5460 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5462 /* Note that we cannot do any narrowing for non-constants since
5463 we might have been counting on using the fact that some bits were
5464 zero. We now do this in the SET. */
5469 temp
= expand_compound_operation (XEXP (x
, 0));
5471 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5472 replaced by (lshiftrt X C). This will convert
5473 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5475 if (GET_CODE (temp
) == ASHIFTRT
5476 && CONST_INT_P (XEXP (temp
, 1))
5477 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5478 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5479 INTVAL (XEXP (temp
, 1)));
5481 /* If X has only a single bit that might be nonzero, say, bit I, convert
5482 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5483 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5484 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5485 or a SUBREG of one since we'd be making the expression more
5486 complex if it was just a register. */
5489 && ! (GET_CODE (temp
) == SUBREG
5490 && REG_P (SUBREG_REG (temp
)))
5491 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5493 rtx temp1
= simplify_shift_const
5494 (NULL_RTX
, ASHIFTRT
, mode
,
5495 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5496 GET_MODE_PRECISION (mode
) - 1 - i
),
5497 GET_MODE_PRECISION (mode
) - 1 - i
);
5499 /* If all we did was surround TEMP with the two shifts, we
5500 haven't improved anything, so don't use it. Otherwise,
5501 we are better off with TEMP1. */
5502 if (GET_CODE (temp1
) != ASHIFTRT
5503 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5504 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5510 /* We can't handle truncation to a partial integer mode here
5511 because we don't know the real bitsize of the partial
5513 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5516 if (HWI_COMPUTABLE_MODE_P (mode
))
5518 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5519 GET_MODE_MASK (mode
), 0));
5521 /* We can truncate a constant value and return it. */
5522 if (CONST_INT_P (XEXP (x
, 0)))
5523 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5525 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5526 whose value is a comparison can be replaced with a subreg if
5527 STORE_FLAG_VALUE permits. */
5528 if (HWI_COMPUTABLE_MODE_P (mode
)
5529 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5530 && (temp
= get_last_value (XEXP (x
, 0)))
5531 && COMPARISON_P (temp
))
5532 return gen_lowpart (mode
, XEXP (x
, 0));
5536 /* (const (const X)) can become (const X). Do it this way rather than
5537 returning the inner CONST since CONST can be shared with a
5539 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5540 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5545 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5546 can add in an offset. find_split_point will split this address up
5547 again if it doesn't match. */
5548 if (GET_CODE (XEXP (x
, 0)) == HIGH
5549 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5555 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5556 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5557 bit-field and can be replaced by either a sign_extend or a
5558 sign_extract. The `and' may be a zero_extend and the two
5559 <c>, -<c> constants may be reversed. */
5560 if (GET_CODE (XEXP (x
, 0)) == XOR
5561 && CONST_INT_P (XEXP (x
, 1))
5562 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5563 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5564 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5565 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5566 && HWI_COMPUTABLE_MODE_P (mode
)
5567 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5568 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5569 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5570 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5571 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5572 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5573 == (unsigned int) i
+ 1))))
5574 return simplify_shift_const
5575 (NULL_RTX
, ASHIFTRT
, mode
,
5576 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5577 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5578 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5579 GET_MODE_PRECISION (mode
) - (i
+ 1));
5581 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5582 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5583 the bitsize of the mode - 1. This allows simplification of
5584 "a = (b & 8) == 0;" */
5585 if (XEXP (x
, 1) == constm1_rtx
5586 && !REG_P (XEXP (x
, 0))
5587 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5588 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5589 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5590 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5591 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5592 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5593 GET_MODE_PRECISION (mode
) - 1),
5594 GET_MODE_PRECISION (mode
) - 1);
5596 /* If we are adding two things that have no bits in common, convert
5597 the addition into an IOR. This will often be further simplified,
5598 for example in cases like ((a & 1) + (a & 2)), which can
5601 if (HWI_COMPUTABLE_MODE_P (mode
)
5602 && (nonzero_bits (XEXP (x
, 0), mode
)
5603 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5605 /* Try to simplify the expression further. */
5606 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5607 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5609 /* If we could, great. If not, do not go ahead with the IOR
5610 replacement, since PLUS appears in many special purpose
5611 address arithmetic instructions. */
5612 if (GET_CODE (temp
) != CLOBBER
5613 && (GET_CODE (temp
) != IOR
5614 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5615 || XEXP (temp
, 1) != XEXP (x
, 1))
5616 && (XEXP (temp
, 0) != XEXP (x
, 1)
5617 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5623 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5624 (and <foo> (const_int pow2-1)) */
5625 if (GET_CODE (XEXP (x
, 1)) == AND
5626 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5627 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5628 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5629 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5630 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5634 /* If we have (mult (plus A B) C), apply the distributive law and then
5635 the inverse distributive law to see if things simplify. This
5636 occurs mostly in addresses, often when unrolling loops. */
5638 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5640 rtx result
= distribute_and_simplify_rtx (x
, 0);
5645 /* Try simplify a*(b/c) as (a*b)/c. */
5646 if (FLOAT_MODE_P (mode
) && flag_associative_math
5647 && GET_CODE (XEXP (x
, 0)) == DIV
)
5649 rtx tem
= simplify_binary_operation (MULT
, mode
,
5650 XEXP (XEXP (x
, 0), 0),
5653 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5658 /* If this is a divide by a power of two, treat it as a shift if
5659 its first operand is a shift. */
5660 if (CONST_INT_P (XEXP (x
, 1))
5661 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5662 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5663 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5664 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5665 || GET_CODE (XEXP (x
, 0)) == ROTATE
5666 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5667 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5671 case GT
: case GTU
: case GE
: case GEU
:
5672 case LT
: case LTU
: case LE
: case LEU
:
5673 case UNEQ
: case LTGT
:
5674 case UNGT
: case UNGE
:
5675 case UNLT
: case UNLE
:
5676 case UNORDERED
: case ORDERED
:
5677 /* If the first operand is a condition code, we can't do anything
5679 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5680 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5681 && ! CC0_P (XEXP (x
, 0))))
5683 rtx op0
= XEXP (x
, 0);
5684 rtx op1
= XEXP (x
, 1);
5685 enum rtx_code new_code
;
5687 if (GET_CODE (op0
) == COMPARE
)
5688 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5690 /* Simplify our comparison, if possible. */
5691 new_code
= simplify_comparison (code
, &op0
, &op1
);
5693 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5694 if only the low-order bit is possibly nonzero in X (such as when
5695 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5696 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5697 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5700 Remove any ZERO_EXTRACT we made when thinking this was a
5701 comparison. It may now be simpler to use, e.g., an AND. If a
5702 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5703 the call to make_compound_operation in the SET case.
5705 Don't apply these optimizations if the caller would
5706 prefer a comparison rather than a value.
5707 E.g., for the condition in an IF_THEN_ELSE most targets need
5708 an explicit comparison. */
5713 else if (STORE_FLAG_VALUE
== 1
5714 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5715 && op1
== const0_rtx
5716 && mode
== GET_MODE (op0
)
5717 && nonzero_bits (op0
, mode
) == 1)
5718 return gen_lowpart (mode
,
5719 expand_compound_operation (op0
));
5721 else if (STORE_FLAG_VALUE
== 1
5722 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5723 && op1
== const0_rtx
5724 && mode
== GET_MODE (op0
)
5725 && (num_sign_bit_copies (op0
, mode
)
5726 == GET_MODE_PRECISION (mode
)))
5728 op0
= expand_compound_operation (op0
);
5729 return simplify_gen_unary (NEG
, mode
,
5730 gen_lowpart (mode
, op0
),
5734 else if (STORE_FLAG_VALUE
== 1
5735 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5736 && op1
== const0_rtx
5737 && mode
== GET_MODE (op0
)
5738 && nonzero_bits (op0
, mode
) == 1)
5740 op0
= expand_compound_operation (op0
);
5741 return simplify_gen_binary (XOR
, mode
,
5742 gen_lowpart (mode
, op0
),
5746 else if (STORE_FLAG_VALUE
== 1
5747 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5748 && op1
== const0_rtx
5749 && mode
== GET_MODE (op0
)
5750 && (num_sign_bit_copies (op0
, mode
)
5751 == GET_MODE_PRECISION (mode
)))
5753 op0
= expand_compound_operation (op0
);
5754 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5757 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5762 else if (STORE_FLAG_VALUE
== -1
5763 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5764 && op1
== const0_rtx
5765 && (num_sign_bit_copies (op0
, mode
)
5766 == GET_MODE_PRECISION (mode
)))
5767 return gen_lowpart (mode
,
5768 expand_compound_operation (op0
));
5770 else if (STORE_FLAG_VALUE
== -1
5771 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5772 && op1
== const0_rtx
5773 && mode
== GET_MODE (op0
)
5774 && nonzero_bits (op0
, mode
) == 1)
5776 op0
= expand_compound_operation (op0
);
5777 return simplify_gen_unary (NEG
, mode
,
5778 gen_lowpart (mode
, op0
),
5782 else if (STORE_FLAG_VALUE
== -1
5783 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5784 && op1
== const0_rtx
5785 && mode
== GET_MODE (op0
)
5786 && (num_sign_bit_copies (op0
, mode
)
5787 == GET_MODE_PRECISION (mode
)))
5789 op0
= expand_compound_operation (op0
);
5790 return simplify_gen_unary (NOT
, mode
,
5791 gen_lowpart (mode
, op0
),
5795 /* If X is 0/1, (eq X 0) is X-1. */
5796 else if (STORE_FLAG_VALUE
== -1
5797 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5798 && op1
== const0_rtx
5799 && mode
== GET_MODE (op0
)
5800 && nonzero_bits (op0
, mode
) == 1)
5802 op0
= expand_compound_operation (op0
);
5803 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5806 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5807 one bit that might be nonzero, we can convert (ne x 0) to
5808 (ashift x c) where C puts the bit in the sign bit. Remove any
5809 AND with STORE_FLAG_VALUE when we are done, since we are only
5810 going to test the sign bit. */
5811 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5812 && HWI_COMPUTABLE_MODE_P (mode
)
5813 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5814 && op1
== const0_rtx
5815 && mode
== GET_MODE (op0
)
5816 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5818 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5819 expand_compound_operation (op0
),
5820 GET_MODE_PRECISION (mode
) - 1 - i
);
5821 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5827 /* If the code changed, return a whole new comparison.
5828 We also need to avoid using SUBST in cases where
5829 simplify_comparison has widened a comparison with a CONST_INT,
5830 since in that case the wider CONST_INT may fail the sanity
5831 checks in do_SUBST. */
5832 if (new_code
!= code
5833 || (CONST_INT_P (op1
)
5834 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5835 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5836 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5838 /* Otherwise, keep this operation, but maybe change its operands.
5839 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5840 SUBST (XEXP (x
, 0), op0
);
5841 SUBST (XEXP (x
, 1), op1
);
5846 return simplify_if_then_else (x
);
5852 /* If we are processing SET_DEST, we are done. */
5856 return expand_compound_operation (x
);
5859 return simplify_set (x
);
5863 return simplify_logical (x
);
5870 /* If this is a shift by a constant amount, simplify it. */
5871 if (CONST_INT_P (XEXP (x
, 1)))
5872 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5873 INTVAL (XEXP (x
, 1)));
5875 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5877 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5878 ((unsigned HOST_WIDE_INT
) 1
5879 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5891 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5894 simplify_if_then_else (rtx x
)
5896 enum machine_mode mode
= GET_MODE (x
);
5897 rtx cond
= XEXP (x
, 0);
5898 rtx true_rtx
= XEXP (x
, 1);
5899 rtx false_rtx
= XEXP (x
, 2);
5900 enum rtx_code true_code
= GET_CODE (cond
);
5901 int comparison_p
= COMPARISON_P (cond
);
5904 enum rtx_code false_code
;
5907 /* Simplify storing of the truth value. */
5908 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5909 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5910 XEXP (cond
, 0), XEXP (cond
, 1));
5912 /* Also when the truth value has to be reversed. */
5914 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5915 && (reversed
= reversed_comparison (cond
, mode
)))
5918 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5919 in it is being compared against certain values. Get the true and false
5920 comparisons and see if that says anything about the value of each arm. */
5923 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5925 && REG_P (XEXP (cond
, 0)))
5928 rtx from
= XEXP (cond
, 0);
5929 rtx true_val
= XEXP (cond
, 1);
5930 rtx false_val
= true_val
;
5933 /* If FALSE_CODE is EQ, swap the codes and arms. */
5935 if (false_code
== EQ
)
5937 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5938 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5941 /* If we are comparing against zero and the expression being tested has
5942 only a single bit that might be nonzero, that is its value when it is
5943 not equal to zero. Similarly if it is known to be -1 or 0. */
5945 if (true_code
== EQ
&& true_val
== const0_rtx
5946 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5949 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5951 else if (true_code
== EQ
&& true_val
== const0_rtx
5952 && (num_sign_bit_copies (from
, GET_MODE (from
))
5953 == GET_MODE_PRECISION (GET_MODE (from
))))
5956 false_val
= constm1_rtx
;
5959 /* Now simplify an arm if we know the value of the register in the
5960 branch and it is used in the arm. Be careful due to the potential
5961 of locally-shared RTL. */
5963 if (reg_mentioned_p (from
, true_rtx
))
5964 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5966 pc_rtx
, pc_rtx
, 0, 0, 0);
5967 if (reg_mentioned_p (from
, false_rtx
))
5968 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5970 pc_rtx
, pc_rtx
, 0, 0, 0);
5972 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5973 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5975 true_rtx
= XEXP (x
, 1);
5976 false_rtx
= XEXP (x
, 2);
5977 true_code
= GET_CODE (cond
);
5980 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5981 reversed, do so to avoid needing two sets of patterns for
5982 subtract-and-branch insns. Similarly if we have a constant in the true
5983 arm, the false arm is the same as the first operand of the comparison, or
5984 the false arm is more complicated than the true arm. */
5987 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5988 && (true_rtx
== pc_rtx
5989 || (CONSTANT_P (true_rtx
)
5990 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5991 || true_rtx
== const0_rtx
5992 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5993 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5994 && !OBJECT_P (false_rtx
))
5995 || reg_mentioned_p (true_rtx
, false_rtx
)
5996 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5998 true_code
= reversed_comparison_code (cond
, NULL
);
5999 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6000 SUBST (XEXP (x
, 1), false_rtx
);
6001 SUBST (XEXP (x
, 2), true_rtx
);
6003 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6006 /* It is possible that the conditional has been simplified out. */
6007 true_code
= GET_CODE (cond
);
6008 comparison_p
= COMPARISON_P (cond
);
6011 /* If the two arms are identical, we don't need the comparison. */
6013 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6016 /* Convert a == b ? b : a to "a". */
6017 if (true_code
== EQ
&& ! side_effects_p (cond
)
6018 && !HONOR_NANS (mode
)
6019 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6020 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6022 else if (true_code
== NE
&& ! side_effects_p (cond
)
6023 && !HONOR_NANS (mode
)
6024 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6025 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6028 /* Look for cases where we have (abs x) or (neg (abs X)). */
6030 if (GET_MODE_CLASS (mode
) == MODE_INT
6032 && XEXP (cond
, 1) == const0_rtx
6033 && GET_CODE (false_rtx
) == NEG
6034 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6035 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6036 && ! side_effects_p (true_rtx
))
6041 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6045 simplify_gen_unary (NEG
, mode
,
6046 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6052 /* Look for MIN or MAX. */
6054 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6056 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6057 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6058 && ! side_effects_p (cond
))
6063 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6066 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6069 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6072 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6077 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6078 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6079 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6080 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6081 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6082 neither 1 or -1, but it isn't worth checking for. */
6084 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6086 && GET_MODE_CLASS (mode
) == MODE_INT
6087 && ! side_effects_p (x
))
6089 rtx t
= make_compound_operation (true_rtx
, SET
);
6090 rtx f
= make_compound_operation (false_rtx
, SET
);
6091 rtx cond_op0
= XEXP (cond
, 0);
6092 rtx cond_op1
= XEXP (cond
, 1);
6093 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6094 enum machine_mode m
= mode
;
6095 rtx z
= 0, c1
= NULL_RTX
;
6097 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6098 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6099 || GET_CODE (t
) == ASHIFT
6100 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6101 && rtx_equal_p (XEXP (t
, 0), f
))
6102 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6104 /* If an identity-zero op is commutative, check whether there
6105 would be a match if we swapped the operands. */
6106 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6107 || GET_CODE (t
) == XOR
)
6108 && rtx_equal_p (XEXP (t
, 1), f
))
6109 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6110 else if (GET_CODE (t
) == SIGN_EXTEND
6111 && (GET_CODE (XEXP (t
, 0)) == PLUS
6112 || GET_CODE (XEXP (t
, 0)) == MINUS
6113 || GET_CODE (XEXP (t
, 0)) == IOR
6114 || GET_CODE (XEXP (t
, 0)) == XOR
6115 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6116 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6117 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6118 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6119 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6120 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6121 && (num_sign_bit_copies (f
, GET_MODE (f
))
6123 (GET_MODE_PRECISION (mode
)
6124 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6126 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6127 extend_op
= SIGN_EXTEND
;
6128 m
= GET_MODE (XEXP (t
, 0));
6130 else if (GET_CODE (t
) == SIGN_EXTEND
6131 && (GET_CODE (XEXP (t
, 0)) == PLUS
6132 || GET_CODE (XEXP (t
, 0)) == IOR
6133 || GET_CODE (XEXP (t
, 0)) == XOR
)
6134 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6135 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6136 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6137 && (num_sign_bit_copies (f
, GET_MODE (f
))
6139 (GET_MODE_PRECISION (mode
)
6140 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6142 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6143 extend_op
= SIGN_EXTEND
;
6144 m
= GET_MODE (XEXP (t
, 0));
6146 else if (GET_CODE (t
) == ZERO_EXTEND
6147 && (GET_CODE (XEXP (t
, 0)) == PLUS
6148 || GET_CODE (XEXP (t
, 0)) == MINUS
6149 || GET_CODE (XEXP (t
, 0)) == IOR
6150 || GET_CODE (XEXP (t
, 0)) == XOR
6151 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6152 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6153 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6154 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6155 && HWI_COMPUTABLE_MODE_P (mode
)
6156 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6157 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6158 && ((nonzero_bits (f
, GET_MODE (f
))
6159 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6162 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6163 extend_op
= ZERO_EXTEND
;
6164 m
= GET_MODE (XEXP (t
, 0));
6166 else if (GET_CODE (t
) == ZERO_EXTEND
6167 && (GET_CODE (XEXP (t
, 0)) == PLUS
6168 || GET_CODE (XEXP (t
, 0)) == IOR
6169 || GET_CODE (XEXP (t
, 0)) == XOR
)
6170 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6171 && HWI_COMPUTABLE_MODE_P (mode
)
6172 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6173 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6174 && ((nonzero_bits (f
, GET_MODE (f
))
6175 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6178 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6179 extend_op
= ZERO_EXTEND
;
6180 m
= GET_MODE (XEXP (t
, 0));
6185 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6186 cond_op0
, cond_op1
),
6187 pc_rtx
, pc_rtx
, 0, 0, 0);
6188 temp
= simplify_gen_binary (MULT
, m
, temp
,
6189 simplify_gen_binary (MULT
, m
, c1
,
6191 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6192 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6194 if (extend_op
!= UNKNOWN
)
6195 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6201 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6202 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6203 negation of a single bit, we can convert this operation to a shift. We
6204 can actually do this more generally, but it doesn't seem worth it. */
6206 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6207 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6208 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6209 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6210 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6211 == GET_MODE_PRECISION (mode
))
6212 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6214 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6215 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6217 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6218 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6219 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6220 && GET_MODE (XEXP (cond
, 0)) == mode
6221 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6222 == nonzero_bits (XEXP (cond
, 0), mode
)
6223 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6224 return XEXP (cond
, 0);
6229 /* Simplify X, a SET expression. Return the new expression. */
6232 simplify_set (rtx x
)
6234 rtx src
= SET_SRC (x
);
6235 rtx dest
= SET_DEST (x
);
6236 enum machine_mode mode
6237 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6241 /* (set (pc) (return)) gets written as (return). */
6242 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6245 /* Now that we know for sure which bits of SRC we are using, see if we can
6246 simplify the expression for the object knowing that we only need the
6249 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6251 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6252 SUBST (SET_SRC (x
), src
);
6255 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6256 the comparison result and try to simplify it unless we already have used
6257 undobuf.other_insn. */
6258 if ((GET_MODE_CLASS (mode
) == MODE_CC
6259 || GET_CODE (src
) == COMPARE
6261 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6262 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6263 && COMPARISON_P (*cc_use
)
6264 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6266 enum rtx_code old_code
= GET_CODE (*cc_use
);
6267 enum rtx_code new_code
;
6269 int other_changed
= 0;
6270 rtx inner_compare
= NULL_RTX
;
6271 enum machine_mode compare_mode
= GET_MODE (dest
);
6273 if (GET_CODE (src
) == COMPARE
)
6275 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6276 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6278 inner_compare
= op0
;
6279 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6283 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6285 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6288 new_code
= old_code
;
6289 else if (!CONSTANT_P (tmp
))
6291 new_code
= GET_CODE (tmp
);
6292 op0
= XEXP (tmp
, 0);
6293 op1
= XEXP (tmp
, 1);
6297 rtx pat
= PATTERN (other_insn
);
6298 undobuf
.other_insn
= other_insn
;
6299 SUBST (*cc_use
, tmp
);
6301 /* Attempt to simplify CC user. */
6302 if (GET_CODE (pat
) == SET
)
6304 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6305 if (new_rtx
!= NULL_RTX
)
6306 SUBST (SET_SRC (pat
), new_rtx
);
6309 /* Convert X into a no-op move. */
6310 SUBST (SET_DEST (x
), pc_rtx
);
6311 SUBST (SET_SRC (x
), pc_rtx
);
6315 /* Simplify our comparison, if possible. */
6316 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6318 #ifdef SELECT_CC_MODE
6319 /* If this machine has CC modes other than CCmode, check to see if we
6320 need to use a different CC mode here. */
6321 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6322 compare_mode
= GET_MODE (op0
);
6323 else if (inner_compare
6324 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6325 && new_code
== old_code
6326 && op0
== XEXP (inner_compare
, 0)
6327 && op1
== XEXP (inner_compare
, 1))
6328 compare_mode
= GET_MODE (inner_compare
);
6330 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6333 /* If the mode changed, we have to change SET_DEST, the mode in the
6334 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6335 a hard register, just build new versions with the proper mode. If it
6336 is a pseudo, we lose unless it is only time we set the pseudo, in
6337 which case we can safely change its mode. */
6338 if (compare_mode
!= GET_MODE (dest
))
6340 if (can_change_dest_mode (dest
, 0, compare_mode
))
6342 unsigned int regno
= REGNO (dest
);
6345 if (regno
< FIRST_PSEUDO_REGISTER
)
6346 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6349 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6350 new_dest
= regno_reg_rtx
[regno
];
6353 SUBST (SET_DEST (x
), new_dest
);
6354 SUBST (XEXP (*cc_use
, 0), new_dest
);
6361 #endif /* SELECT_CC_MODE */
6363 /* If the code changed, we have to build a new comparison in
6364 undobuf.other_insn. */
6365 if (new_code
!= old_code
)
6367 int other_changed_previously
= other_changed
;
6368 unsigned HOST_WIDE_INT mask
;
6369 rtx old_cc_use
= *cc_use
;
6371 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6375 /* If the only change we made was to change an EQ into an NE or
6376 vice versa, OP0 has only one bit that might be nonzero, and OP1
6377 is zero, check if changing the user of the condition code will
6378 produce a valid insn. If it won't, we can keep the original code
6379 in that insn by surrounding our operation with an XOR. */
6381 if (((old_code
== NE
&& new_code
== EQ
)
6382 || (old_code
== EQ
&& new_code
== NE
))
6383 && ! other_changed_previously
&& op1
== const0_rtx
6384 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6385 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6387 rtx pat
= PATTERN (other_insn
), note
= 0;
6389 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6390 && ! check_asm_operands (pat
)))
6392 *cc_use
= old_cc_use
;
6395 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6403 undobuf
.other_insn
= other_insn
;
6405 /* Otherwise, if we didn't previously have a COMPARE in the
6406 correct mode, we need one. */
6407 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6409 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6412 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6414 SUBST (SET_SRC (x
), op0
);
6417 /* Otherwise, update the COMPARE if needed. */
6418 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6420 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6426 /* Get SET_SRC in a form where we have placed back any
6427 compound expressions. Then do the checks below. */
6428 src
= make_compound_operation (src
, SET
);
6429 SUBST (SET_SRC (x
), src
);
6432 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6433 and X being a REG or (subreg (reg)), we may be able to convert this to
6434 (set (subreg:m2 x) (op)).
6436 We can always do this if M1 is narrower than M2 because that means that
6437 we only care about the low bits of the result.
6439 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6440 perform a narrower operation than requested since the high-order bits will
6441 be undefined. On machine where it is defined, this transformation is safe
6442 as long as M1 and M2 have the same number of words. */
6444 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6445 && !OBJECT_P (SUBREG_REG (src
))
6446 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6448 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6449 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6450 #ifndef WORD_REGISTER_OPERATIONS
6451 && (GET_MODE_SIZE (GET_MODE (src
))
6452 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6454 #ifdef CANNOT_CHANGE_MODE_CLASS
6455 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6456 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6457 GET_MODE (SUBREG_REG (src
)),
6461 || (GET_CODE (dest
) == SUBREG
6462 && REG_P (SUBREG_REG (dest
)))))
6464 SUBST (SET_DEST (x
),
6465 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6467 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6469 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6473 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6476 && GET_CODE (src
) == SUBREG
6477 && subreg_lowpart_p (src
)
6478 && (GET_MODE_PRECISION (GET_MODE (src
))
6479 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6481 rtx inner
= SUBREG_REG (src
);
6482 enum machine_mode inner_mode
= GET_MODE (inner
);
6484 /* Here we make sure that we don't have a sign bit on. */
6485 if (val_signbit_known_clear_p (GET_MODE (src
),
6486 nonzero_bits (inner
, inner_mode
)))
6488 SUBST (SET_SRC (x
), inner
);
6494 #ifdef LOAD_EXTEND_OP
6495 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6496 would require a paradoxical subreg. Replace the subreg with a
6497 zero_extend to avoid the reload that would otherwise be required. */
6499 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6500 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6501 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6502 && SUBREG_BYTE (src
) == 0
6503 && paradoxical_subreg_p (src
)
6504 && MEM_P (SUBREG_REG (src
)))
6507 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6508 GET_MODE (src
), SUBREG_REG (src
)));
6514 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6515 are comparing an item known to be 0 or -1 against 0, use a logical
6516 operation instead. Check for one of the arms being an IOR of the other
6517 arm with some value. We compute three terms to be IOR'ed together. In
6518 practice, at most two will be nonzero. Then we do the IOR's. */
6520 if (GET_CODE (dest
) != PC
6521 && GET_CODE (src
) == IF_THEN_ELSE
6522 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6523 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6524 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6525 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6526 #ifdef HAVE_conditional_move
6527 && ! can_conditionally_move_p (GET_MODE (src
))
6529 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6530 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6531 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6532 && ! side_effects_p (src
))
6534 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6535 ? XEXP (src
, 1) : XEXP (src
, 2));
6536 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6537 ? XEXP (src
, 2) : XEXP (src
, 1));
6538 rtx term1
= const0_rtx
, term2
, term3
;
6540 if (GET_CODE (true_rtx
) == IOR
6541 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6542 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6543 else if (GET_CODE (true_rtx
) == IOR
6544 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6545 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6546 else if (GET_CODE (false_rtx
) == IOR
6547 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6548 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6549 else if (GET_CODE (false_rtx
) == IOR
6550 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6551 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6553 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6554 XEXP (XEXP (src
, 0), 0), true_rtx
);
6555 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6556 simplify_gen_unary (NOT
, GET_MODE (src
),
6557 XEXP (XEXP (src
, 0), 0),
6562 simplify_gen_binary (IOR
, GET_MODE (src
),
6563 simplify_gen_binary (IOR
, GET_MODE (src
),
6570 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6571 whole thing fail. */
6572 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6574 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6577 /* Convert this into a field assignment operation, if possible. */
6578 return make_field_assignment (x
);
6581 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6585 simplify_logical (rtx x
)
6587 enum machine_mode mode
= GET_MODE (x
);
6588 rtx op0
= XEXP (x
, 0);
6589 rtx op1
= XEXP (x
, 1);
6591 switch (GET_CODE (x
))
6594 /* We can call simplify_and_const_int only if we don't lose
6595 any (sign) bits when converting INTVAL (op1) to
6596 "unsigned HOST_WIDE_INT". */
6597 if (CONST_INT_P (op1
)
6598 && (HWI_COMPUTABLE_MODE_P (mode
)
6599 || INTVAL (op1
) > 0))
6601 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6602 if (GET_CODE (x
) != AND
)
6609 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6610 apply the distributive law and then the inverse distributive
6611 law to see if things simplify. */
6612 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6614 rtx result
= distribute_and_simplify_rtx (x
, 0);
6618 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6620 rtx result
= distribute_and_simplify_rtx (x
, 1);
6627 /* If we have (ior (and A B) C), apply the distributive law and then
6628 the inverse distributive law to see if things simplify. */
6630 if (GET_CODE (op0
) == AND
)
6632 rtx result
= distribute_and_simplify_rtx (x
, 0);
6637 if (GET_CODE (op1
) == AND
)
6639 rtx result
= distribute_and_simplify_rtx (x
, 1);
6652 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6653 operations" because they can be replaced with two more basic operations.
6654 ZERO_EXTEND is also considered "compound" because it can be replaced with
6655 an AND operation, which is simpler, though only one operation.
6657 The function expand_compound_operation is called with an rtx expression
6658 and will convert it to the appropriate shifts and AND operations,
6659 simplifying at each stage.
6661 The function make_compound_operation is called to convert an expression
6662 consisting of shifts and ANDs into the equivalent compound expression.
6663 It is the inverse of this function, loosely speaking. */
6666 expand_compound_operation (rtx x
)
6668 unsigned HOST_WIDE_INT pos
= 0, len
;
6670 unsigned int modewidth
;
6673 switch (GET_CODE (x
))
6678 /* We can't necessarily use a const_int for a multiword mode;
6679 it depends on implicitly extending the value.
6680 Since we don't know the right way to extend it,
6681 we can't tell whether the implicit way is right.
6683 Even for a mode that is no wider than a const_int,
6684 we can't win, because we need to sign extend one of its bits through
6685 the rest of it, and we don't know which bit. */
6686 if (CONST_INT_P (XEXP (x
, 0)))
6689 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6690 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6691 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6692 reloaded. If not for that, MEM's would very rarely be safe.
6694 Reject MODEs bigger than a word, because we might not be able
6695 to reference a two-register group starting with an arbitrary register
6696 (and currently gen_lowpart might crash for a SUBREG). */
6698 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6701 /* Reject MODEs that aren't scalar integers because turning vector
6702 or complex modes into shifts causes problems. */
6704 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6707 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6708 /* If the inner object has VOIDmode (the only way this can happen
6709 is if it is an ASM_OPERANDS), we can't do anything since we don't
6710 know how much masking to do. */
6719 /* ... fall through ... */
6722 /* If the operand is a CLOBBER, just return it. */
6723 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6726 if (!CONST_INT_P (XEXP (x
, 1))
6727 || !CONST_INT_P (XEXP (x
, 2))
6728 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6731 /* Reject MODEs that aren't scalar integers because turning vector
6732 or complex modes into shifts causes problems. */
6734 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6737 len
= INTVAL (XEXP (x
, 1));
6738 pos
= INTVAL (XEXP (x
, 2));
6740 /* This should stay within the object being extracted, fail otherwise. */
6741 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6744 if (BITS_BIG_ENDIAN
)
6745 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6752 /* Convert sign extension to zero extension, if we know that the high
6753 bit is not set, as this is easier to optimize. It will be converted
6754 back to cheaper alternative in make_extraction. */
6755 if (GET_CODE (x
) == SIGN_EXTEND
6756 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6757 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6758 & ~(((unsigned HOST_WIDE_INT
)
6759 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6763 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6764 rtx temp2
= expand_compound_operation (temp
);
6766 /* Make sure this is a profitable operation. */
6767 if (set_src_cost (x
, optimize_this_for_speed_p
)
6768 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6770 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6771 > set_src_cost (temp
, optimize_this_for_speed_p
))
6777 /* We can optimize some special cases of ZERO_EXTEND. */
6778 if (GET_CODE (x
) == ZERO_EXTEND
)
6780 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6781 know that the last value didn't have any inappropriate bits
6783 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6784 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6785 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6786 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6787 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6788 return XEXP (XEXP (x
, 0), 0);
6790 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6791 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6792 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6793 && subreg_lowpart_p (XEXP (x
, 0))
6794 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6795 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6796 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6797 return SUBREG_REG (XEXP (x
, 0));
6799 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6800 is a comparison and STORE_FLAG_VALUE permits. This is like
6801 the first case, but it works even when GET_MODE (x) is larger
6802 than HOST_WIDE_INT. */
6803 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6804 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6805 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6806 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6807 <= HOST_BITS_PER_WIDE_INT
)
6808 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6809 return XEXP (XEXP (x
, 0), 0);
6811 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6812 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6813 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6814 && subreg_lowpart_p (XEXP (x
, 0))
6815 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6816 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6817 <= HOST_BITS_PER_WIDE_INT
)
6818 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6819 return SUBREG_REG (XEXP (x
, 0));
6823 /* If we reach here, we want to return a pair of shifts. The inner
6824 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6825 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6826 logical depending on the value of UNSIGNEDP.
6828 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6829 converted into an AND of a shift.
6831 We must check for the case where the left shift would have a negative
6832 count. This can happen in a case like (x >> 31) & 255 on machines
6833 that can't shift by a constant. On those machines, we would first
6834 combine the shift with the AND to produce a variable-position
6835 extraction. Then the constant of 31 would be substituted in
6836 to produce such a position. */
6838 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6839 if (modewidth
>= pos
+ len
)
6841 enum machine_mode mode
= GET_MODE (x
);
6842 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6843 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6845 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6846 tem
, modewidth
- pos
- len
);
6847 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6848 mode
, tem
, modewidth
- len
);
6850 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6851 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6852 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6855 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6857 /* Any other cases we can't handle. */
6860 /* If we couldn't do this for some reason, return the original
6862 if (GET_CODE (tem
) == CLOBBER
)
6868 /* X is a SET which contains an assignment of one object into
6869 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6870 or certain SUBREGS). If possible, convert it into a series of
6873 We half-heartedly support variable positions, but do not at all
6874 support variable lengths. */
6877 expand_field_assignment (const_rtx x
)
6880 rtx pos
; /* Always counts from low bit. */
6882 rtx mask
, cleared
, masked
;
6883 enum machine_mode compute_mode
;
6885 /* Loop until we find something we can't simplify. */
6888 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6889 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6891 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6892 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6893 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6895 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6896 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6898 inner
= XEXP (SET_DEST (x
), 0);
6899 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6900 pos
= XEXP (SET_DEST (x
), 2);
6902 /* A constant position should stay within the width of INNER. */
6903 if (CONST_INT_P (pos
)
6904 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6907 if (BITS_BIG_ENDIAN
)
6909 if (CONST_INT_P (pos
))
6910 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6912 else if (GET_CODE (pos
) == MINUS
6913 && CONST_INT_P (XEXP (pos
, 1))
6914 && (INTVAL (XEXP (pos
, 1))
6915 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6916 /* If position is ADJUST - X, new position is X. */
6917 pos
= XEXP (pos
, 0);
6920 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6921 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6922 gen_int_mode (prec
- len
,
6929 /* A SUBREG between two modes that occupy the same numbers of words
6930 can be done by moving the SUBREG to the source. */
6931 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6932 /* We need SUBREGs to compute nonzero_bits properly. */
6933 && nonzero_sign_valid
6934 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6935 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6936 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6937 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6939 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6941 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6948 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6949 inner
= SUBREG_REG (inner
);
6951 compute_mode
= GET_MODE (inner
);
6953 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6954 if (! SCALAR_INT_MODE_P (compute_mode
))
6956 enum machine_mode imode
;
6958 /* Don't do anything for vector or complex integral types. */
6959 if (! FLOAT_MODE_P (compute_mode
))
6962 /* Try to find an integral mode to pun with. */
6963 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6964 if (imode
== BLKmode
)
6967 compute_mode
= imode
;
6968 inner
= gen_lowpart (imode
, inner
);
6971 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6972 if (len
>= HOST_BITS_PER_WIDE_INT
)
6975 /* Now compute the equivalent expression. Make a copy of INNER
6976 for the SET_DEST in case it is a MEM into which we will substitute;
6977 we don't want shared RTL in that case. */
6978 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6980 cleared
= simplify_gen_binary (AND
, compute_mode
,
6981 simplify_gen_unary (NOT
, compute_mode
,
6982 simplify_gen_binary (ASHIFT
,
6987 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6988 simplify_gen_binary (
6990 gen_lowpart (compute_mode
, SET_SRC (x
)),
6994 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6995 simplify_gen_binary (IOR
, compute_mode
,
7002 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7003 it is an RTX that represents the (variable) starting position; otherwise,
7004 POS is the (constant) starting bit position. Both are counted from the LSB.
7006 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7008 IN_DEST is nonzero if this is a reference in the destination of a SET.
7009 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7010 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7013 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7014 ZERO_EXTRACT should be built even for bits starting at bit 0.
7016 MODE is the desired mode of the result (if IN_DEST == 0).
7018 The result is an RTX for the extraction or NULL_RTX if the target
7022 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7023 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7024 int in_dest
, int in_compare
)
7026 /* This mode describes the size of the storage area
7027 to fetch the overall value from. Within that, we
7028 ignore the POS lowest bits, etc. */
7029 enum machine_mode is_mode
= GET_MODE (inner
);
7030 enum machine_mode inner_mode
;
7031 enum machine_mode wanted_inner_mode
;
7032 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7033 enum machine_mode pos_mode
= word_mode
;
7034 enum machine_mode extraction_mode
= word_mode
;
7035 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7037 rtx orig_pos_rtx
= pos_rtx
;
7038 HOST_WIDE_INT orig_pos
;
7040 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7041 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7043 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7045 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7046 consider just the QI as the memory to extract from.
7047 The subreg adds or removes high bits; its mode is
7048 irrelevant to the meaning of this extraction,
7049 since POS and LEN count from the lsb. */
7050 if (MEM_P (SUBREG_REG (inner
)))
7051 is_mode
= GET_MODE (SUBREG_REG (inner
));
7052 inner
= SUBREG_REG (inner
);
7054 else if (GET_CODE (inner
) == ASHIFT
7055 && CONST_INT_P (XEXP (inner
, 1))
7056 && pos_rtx
== 0 && pos
== 0
7057 && len
> UINTVAL (XEXP (inner
, 1)))
7059 /* We're extracting the least significant bits of an rtx
7060 (ashift X (const_int C)), where LEN > C. Extract the
7061 least significant (LEN - C) bits of X, giving an rtx
7062 whose mode is MODE, then shift it left C times. */
7063 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7064 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7065 unsignedp
, in_dest
, in_compare
);
7067 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7069 else if (GET_CODE (inner
) == TRUNCATE
)
7070 inner
= XEXP (inner
, 0);
7072 inner_mode
= GET_MODE (inner
);
7074 /* See if this can be done without an extraction. We never can if the
7075 width of the field is not the same as that of some integer mode. For
7076 registers, we can only avoid the extraction if the position is at the
7077 low-order bit and this is either not in the destination or we have the
7078 appropriate STRICT_LOW_PART operation available.
7080 For MEM, we can avoid an extract if the field starts on an appropriate
7081 boundary and we can change the mode of the memory reference. */
7083 if (tmode
!= BLKmode
7084 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7086 && (inner_mode
== tmode
7088 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7089 || reg_truncated_to_mode (tmode
, inner
))
7092 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7093 || (MEM_P (inner
) && pos_rtx
== 0
7095 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7096 : BITS_PER_UNIT
)) == 0
7097 /* We can't do this if we are widening INNER_MODE (it
7098 may not be aligned, for one thing). */
7099 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7100 && (inner_mode
== tmode
7101 || (! mode_dependent_address_p (XEXP (inner
, 0),
7102 MEM_ADDR_SPACE (inner
))
7103 && ! MEM_VOLATILE_P (inner
))))))
7105 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7106 field. If the original and current mode are the same, we need not
7107 adjust the offset. Otherwise, we do if bytes big endian.
7109 If INNER is not a MEM, get a piece consisting of just the field
7110 of interest (in this case POS % BITS_PER_WORD must be 0). */
7114 HOST_WIDE_INT offset
;
7116 /* POS counts from lsb, but make OFFSET count in memory order. */
7117 if (BYTES_BIG_ENDIAN
)
7118 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7120 offset
= pos
/ BITS_PER_UNIT
;
7122 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7124 else if (REG_P (inner
))
7126 if (tmode
!= inner_mode
)
7128 /* We can't call gen_lowpart in a DEST since we
7129 always want a SUBREG (see below) and it would sometimes
7130 return a new hard register. */
7133 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7135 if (WORDS_BIG_ENDIAN
7136 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7137 final_word
= ((GET_MODE_SIZE (inner_mode
)
7138 - GET_MODE_SIZE (tmode
))
7139 / UNITS_PER_WORD
) - final_word
;
7141 final_word
*= UNITS_PER_WORD
;
7142 if (BYTES_BIG_ENDIAN
&&
7143 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7144 final_word
+= (GET_MODE_SIZE (inner_mode
)
7145 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7147 /* Avoid creating invalid subregs, for example when
7148 simplifying (x>>32)&255. */
7149 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7152 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7155 new_rtx
= gen_lowpart (tmode
, inner
);
7161 new_rtx
= force_to_mode (inner
, tmode
,
7162 len
>= HOST_BITS_PER_WIDE_INT
7163 ? ~(unsigned HOST_WIDE_INT
) 0
7164 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7167 /* If this extraction is going into the destination of a SET,
7168 make a STRICT_LOW_PART unless we made a MEM. */
7171 return (MEM_P (new_rtx
) ? new_rtx
7172 : (GET_CODE (new_rtx
) != SUBREG
7173 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7174 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7179 if (CONST_SCALAR_INT_P (new_rtx
))
7180 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7181 mode
, new_rtx
, tmode
);
7183 /* If we know that no extraneous bits are set, and that the high
7184 bit is not set, convert the extraction to the cheaper of
7185 sign and zero extension, that are equivalent in these cases. */
7186 if (flag_expensive_optimizations
7187 && (HWI_COMPUTABLE_MODE_P (tmode
)
7188 && ((nonzero_bits (new_rtx
, tmode
)
7189 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7192 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7193 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7195 /* Prefer ZERO_EXTENSION, since it gives more information to
7197 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7198 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7203 /* Otherwise, sign- or zero-extend unless we already are in the
7206 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7210 /* Unless this is a COMPARE or we have a funny memory reference,
7211 don't do anything with zero-extending field extracts starting at
7212 the low-order bit since they are simple AND operations. */
7213 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7214 && ! in_compare
&& unsignedp
)
7217 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7218 if the position is not a constant and the length is not 1. In all
7219 other cases, we would only be going outside our object in cases when
7220 an original shift would have been undefined. */
7222 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7223 || (pos_rtx
!= 0 && len
!= 1)))
7226 enum extraction_pattern pattern
= (in_dest
? EP_insv
7227 : unsignedp
? EP_extzv
: EP_extv
);
7229 /* If INNER is not from memory, we want it to have the mode of a register
7230 extraction pattern's structure operand, or word_mode if there is no
7231 such pattern. The same applies to extraction_mode and pos_mode
7232 and their respective operands.
7234 For memory, assume that the desired extraction_mode and pos_mode
7235 are the same as for a register operation, since at present we don't
7236 have named patterns for aligned memory structures. */
7237 struct extraction_insn insn
;
7238 if (get_best_reg_extraction_insn (&insn
, pattern
,
7239 GET_MODE_BITSIZE (inner_mode
), mode
))
7241 wanted_inner_reg_mode
= insn
.struct_mode
;
7242 pos_mode
= insn
.pos_mode
;
7243 extraction_mode
= insn
.field_mode
;
7246 /* Never narrow an object, since that might not be safe. */
7248 if (mode
!= VOIDmode
7249 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7250 extraction_mode
= mode
;
7253 wanted_inner_mode
= wanted_inner_reg_mode
;
7256 /* Be careful not to go beyond the extracted object and maintain the
7257 natural alignment of the memory. */
7258 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7259 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7260 > GET_MODE_BITSIZE (wanted_inner_mode
))
7262 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7263 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7269 if (BITS_BIG_ENDIAN
)
7271 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7272 BITS_BIG_ENDIAN style. If position is constant, compute new
7273 position. Otherwise, build subtraction.
7274 Note that POS is relative to the mode of the original argument.
7275 If it's a MEM we need to recompute POS relative to that.
7276 However, if we're extracting from (or inserting into) a register,
7277 we want to recompute POS relative to wanted_inner_mode. */
7278 int width
= (MEM_P (inner
)
7279 ? GET_MODE_BITSIZE (is_mode
)
7280 : GET_MODE_BITSIZE (wanted_inner_mode
));
7283 pos
= width
- len
- pos
;
7286 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7287 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7289 /* POS may be less than 0 now, but we check for that below.
7290 Note that it can only be less than 0 if !MEM_P (inner). */
7293 /* If INNER has a wider mode, and this is a constant extraction, try to
7294 make it smaller and adjust the byte to point to the byte containing
7296 if (wanted_inner_mode
!= VOIDmode
7297 && inner_mode
!= wanted_inner_mode
7299 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7301 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7302 && ! MEM_VOLATILE_P (inner
))
7306 /* The computations below will be correct if the machine is big
7307 endian in both bits and bytes or little endian in bits and bytes.
7308 If it is mixed, we must adjust. */
7310 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7311 adjust OFFSET to compensate. */
7312 if (BYTES_BIG_ENDIAN
7313 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7314 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7316 /* We can now move to the desired byte. */
7317 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7318 * GET_MODE_SIZE (wanted_inner_mode
);
7319 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7321 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7322 && is_mode
!= wanted_inner_mode
)
7323 offset
= (GET_MODE_SIZE (is_mode
)
7324 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7326 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7329 /* If INNER is not memory, get it into the proper mode. If we are changing
7330 its mode, POS must be a constant and smaller than the size of the new
7332 else if (!MEM_P (inner
))
7334 /* On the LHS, don't create paradoxical subregs implicitely truncating
7335 the register unless TRULY_NOOP_TRUNCATION. */
7337 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7341 if (GET_MODE (inner
) != wanted_inner_mode
7343 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7349 inner
= force_to_mode (inner
, wanted_inner_mode
,
7351 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7352 ? ~(unsigned HOST_WIDE_INT
) 0
7353 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7358 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7359 have to zero extend. Otherwise, we can just use a SUBREG. */
7361 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7363 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7364 GET_MODE (pos_rtx
));
7366 /* If we know that no extraneous bits are set, and that the high
7367 bit is not set, convert extraction to cheaper one - either
7368 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7370 if (flag_expensive_optimizations
7371 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7372 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7373 & ~(((unsigned HOST_WIDE_INT
)
7374 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7378 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7379 GET_MODE (pos_rtx
));
7381 /* Prefer ZERO_EXTENSION, since it gives more information to
7383 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7384 < set_src_cost (temp
, optimize_this_for_speed_p
))
7390 /* Make POS_RTX unless we already have it and it is correct. If we don't
7391 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7393 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7394 pos_rtx
= orig_pos_rtx
;
7396 else if (pos_rtx
== 0)
7397 pos_rtx
= GEN_INT (pos
);
7399 /* Make the required operation. See if we can use existing rtx. */
7400 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7401 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7403 new_rtx
= gen_lowpart (mode
, new_rtx
);
7408 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7409 with any other operations in X. Return X without that shift if so. */
7412 extract_left_shift (rtx x
, int count
)
7414 enum rtx_code code
= GET_CODE (x
);
7415 enum machine_mode mode
= GET_MODE (x
);
7421 /* This is the shift itself. If it is wide enough, we will return
7422 either the value being shifted if the shift count is equal to
7423 COUNT or a shift for the difference. */
7424 if (CONST_INT_P (XEXP (x
, 1))
7425 && INTVAL (XEXP (x
, 1)) >= count
)
7426 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7427 INTVAL (XEXP (x
, 1)) - count
);
7431 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7432 return simplify_gen_unary (code
, mode
, tem
, mode
);
7436 case PLUS
: case IOR
: case XOR
: case AND
:
7437 /* If we can safely shift this constant and we find the inner shift,
7438 make a new operation. */
7439 if (CONST_INT_P (XEXP (x
, 1))
7440 && (UINTVAL (XEXP (x
, 1))
7441 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7442 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7444 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7445 return simplify_gen_binary (code
, mode
, tem
,
7446 gen_int_mode (val
, mode
));
7457 /* Look at the expression rooted at X. Look for expressions
7458 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7459 Form these expressions.
7461 Return the new rtx, usually just X.
7463 Also, for machines like the VAX that don't have logical shift insns,
7464 try to convert logical to arithmetic shift operations in cases where
7465 they are equivalent. This undoes the canonicalizations to logical
7466 shifts done elsewhere.
7468 We try, as much as possible, to re-use rtl expressions to save memory.
7470 IN_CODE says what kind of expression we are processing. Normally, it is
7471 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7472 being kludges), it is MEM. When processing the arguments of a comparison
7473 or a COMPARE against zero, it is COMPARE. */
7476 make_compound_operation (rtx x
, enum rtx_code in_code
)
7478 enum rtx_code code
= GET_CODE (x
);
7479 enum machine_mode mode
= GET_MODE (x
);
7480 int mode_width
= GET_MODE_PRECISION (mode
);
7482 enum rtx_code next_code
;
7488 /* Select the code to be used in recursive calls. Once we are inside an
7489 address, we stay there. If we have a comparison, set to COMPARE,
7490 but once inside, go back to our default of SET. */
7492 next_code
= (code
== MEM
? MEM
7493 : ((code
== PLUS
|| code
== MINUS
)
7494 && SCALAR_INT_MODE_P (mode
)) ? MEM
7495 : ((code
== COMPARE
|| COMPARISON_P (x
))
7496 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7497 : in_code
== COMPARE
? SET
: in_code
);
7499 /* Process depending on the code of this operation. If NEW is set
7500 nonzero, it will be returned. */
7505 /* Convert shifts by constants into multiplications if inside
7507 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7508 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7509 && INTVAL (XEXP (x
, 1)) >= 0
7510 && SCALAR_INT_MODE_P (mode
))
7512 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7513 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7515 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7516 if (GET_CODE (new_rtx
) == NEG
)
7518 new_rtx
= XEXP (new_rtx
, 0);
7521 multval
= trunc_int_for_mode (multval
, mode
);
7522 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7529 lhs
= make_compound_operation (lhs
, next_code
);
7530 rhs
= make_compound_operation (rhs
, next_code
);
7531 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7532 && SCALAR_INT_MODE_P (mode
))
7534 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7536 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7538 else if (GET_CODE (lhs
) == MULT
7539 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7541 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7542 simplify_gen_unary (NEG
, mode
,
7545 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7549 SUBST (XEXP (x
, 0), lhs
);
7550 SUBST (XEXP (x
, 1), rhs
);
7553 x
= gen_lowpart (mode
, new_rtx
);
7559 lhs
= make_compound_operation (lhs
, next_code
);
7560 rhs
= make_compound_operation (rhs
, next_code
);
7561 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7562 && SCALAR_INT_MODE_P (mode
))
7564 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7566 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7568 else if (GET_CODE (rhs
) == MULT
7569 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7571 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7572 simplify_gen_unary (NEG
, mode
,
7575 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7579 SUBST (XEXP (x
, 0), lhs
);
7580 SUBST (XEXP (x
, 1), rhs
);
7583 return gen_lowpart (mode
, new_rtx
);
7586 /* If the second operand is not a constant, we can't do anything
7588 if (!CONST_INT_P (XEXP (x
, 1)))
7591 /* If the constant is a power of two minus one and the first operand
7592 is a logical right shift, make an extraction. */
7593 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7594 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7596 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7597 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7598 0, in_code
== COMPARE
);
7601 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7602 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7603 && subreg_lowpart_p (XEXP (x
, 0))
7604 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7605 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7607 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7609 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7610 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7611 0, in_code
== COMPARE
);
7613 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7614 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7615 || GET_CODE (XEXP (x
, 0)) == IOR
)
7616 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7617 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7618 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7620 /* Apply the distributive law, and then try to make extractions. */
7621 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7622 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7624 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7626 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7629 /* If we are have (and (rotate X C) M) and C is larger than the number
7630 of bits in M, this is an extraction. */
7632 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7633 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7634 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7635 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7637 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7638 new_rtx
= make_extraction (mode
, new_rtx
,
7639 (GET_MODE_PRECISION (mode
)
7640 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7641 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7644 /* On machines without logical shifts, if the operand of the AND is
7645 a logical shift and our mask turns off all the propagated sign
7646 bits, we can replace the logical shift with an arithmetic shift. */
7647 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7648 && !have_insn_for (LSHIFTRT
, mode
)
7649 && have_insn_for (ASHIFTRT
, mode
)
7650 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7651 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7652 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7653 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7655 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7657 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7658 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7660 gen_rtx_ASHIFTRT (mode
,
7661 make_compound_operation
7662 (XEXP (XEXP (x
, 0), 0), next_code
),
7663 XEXP (XEXP (x
, 0), 1)));
7666 /* If the constant is one less than a power of two, this might be
7667 representable by an extraction even if no shift is present.
7668 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7669 we are in a COMPARE. */
7670 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7671 new_rtx
= make_extraction (mode
,
7672 make_compound_operation (XEXP (x
, 0),
7674 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7676 /* If we are in a comparison and this is an AND with a power of two,
7677 convert this into the appropriate bit extract. */
7678 else if (in_code
== COMPARE
7679 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7680 new_rtx
= make_extraction (mode
,
7681 make_compound_operation (XEXP (x
, 0),
7683 i
, NULL_RTX
, 1, 1, 0, 1);
7688 /* If the sign bit is known to be zero, replace this with an
7689 arithmetic shift. */
7690 if (have_insn_for (ASHIFTRT
, mode
)
7691 && ! have_insn_for (LSHIFTRT
, mode
)
7692 && mode_width
<= HOST_BITS_PER_WIDE_INT
7693 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7695 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7696 make_compound_operation (XEXP (x
, 0),
7702 /* ... fall through ... */
7708 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7709 this is a SIGN_EXTRACT. */
7710 if (CONST_INT_P (rhs
)
7711 && GET_CODE (lhs
) == ASHIFT
7712 && CONST_INT_P (XEXP (lhs
, 1))
7713 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7714 && INTVAL (XEXP (lhs
, 1)) >= 0
7715 && INTVAL (rhs
) < mode_width
)
7717 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7718 new_rtx
= make_extraction (mode
, new_rtx
,
7719 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7720 NULL_RTX
, mode_width
- INTVAL (rhs
),
7721 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7725 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7726 If so, try to merge the shifts into a SIGN_EXTEND. We could
7727 also do this for some cases of SIGN_EXTRACT, but it doesn't
7728 seem worth the effort; the case checked for occurs on Alpha. */
7731 && ! (GET_CODE (lhs
) == SUBREG
7732 && (OBJECT_P (SUBREG_REG (lhs
))))
7733 && CONST_INT_P (rhs
)
7734 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7735 && INTVAL (rhs
) < mode_width
7736 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7737 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7738 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7739 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7744 /* Call ourselves recursively on the inner expression. If we are
7745 narrowing the object and it has a different RTL code from
7746 what it originally did, do this SUBREG as a force_to_mode. */
7748 rtx inner
= SUBREG_REG (x
), simplified
;
7749 enum rtx_code subreg_code
= in_code
;
7751 /* If in_code is COMPARE, it isn't always safe to pass it through
7752 to the recursive make_compound_operation call. */
7753 if (subreg_code
== COMPARE
7754 && (!subreg_lowpart_p (x
)
7755 || GET_CODE (inner
) == SUBREG
7756 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7757 is (const_int 0), rather than
7758 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7759 || (GET_CODE (inner
) == AND
7760 && CONST_INT_P (XEXP (inner
, 1))
7761 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7762 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7763 >= GET_MODE_BITSIZE (mode
))))
7766 tem
= make_compound_operation (inner
, subreg_code
);
7769 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7773 if (GET_CODE (tem
) != GET_CODE (inner
)
7774 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7775 && subreg_lowpart_p (x
))
7778 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7780 /* If we have something other than a SUBREG, we might have
7781 done an expansion, so rerun ourselves. */
7782 if (GET_CODE (newer
) != SUBREG
)
7783 newer
= make_compound_operation (newer
, in_code
);
7785 /* force_to_mode can expand compounds. If it just re-expanded the
7786 compound, use gen_lowpart to convert to the desired mode. */
7787 if (rtx_equal_p (newer
, x
)
7788 /* Likewise if it re-expanded the compound only partially.
7789 This happens for SUBREG of ZERO_EXTRACT if they extract
7790 the same number of bits. */
7791 || (GET_CODE (newer
) == SUBREG
7792 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7793 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7794 && GET_CODE (inner
) == AND
7795 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7796 return gen_lowpart (GET_MODE (x
), tem
);
7812 x
= gen_lowpart (mode
, new_rtx
);
7813 code
= GET_CODE (x
);
7816 /* Now recursively process each operand of this operation. We need to
7817 handle ZERO_EXTEND specially so that we don't lose track of the
7819 if (GET_CODE (x
) == ZERO_EXTEND
)
7821 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7822 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7823 new_rtx
, GET_MODE (XEXP (x
, 0)));
7826 SUBST (XEXP (x
, 0), new_rtx
);
7830 fmt
= GET_RTX_FORMAT (code
);
7831 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7834 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7835 SUBST (XEXP (x
, i
), new_rtx
);
7837 else if (fmt
[i
] == 'E')
7838 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7840 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7841 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7845 /* If this is a commutative operation, the changes to the operands
7846 may have made it noncanonical. */
7847 if (COMMUTATIVE_ARITH_P (x
)
7848 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7851 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7852 SUBST (XEXP (x
, 1), tem
);
7858 /* Given M see if it is a value that would select a field of bits
7859 within an item, but not the entire word. Return -1 if not.
7860 Otherwise, return the starting position of the field, where 0 is the
7863 *PLEN is set to the length of the field. */
7866 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7868 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7869 int pos
= m
? ctz_hwi (m
) : -1;
7873 /* Now shift off the low-order zero bits and see if we have a
7874 power of two minus 1. */
7875 len
= exact_log2 ((m
>> pos
) + 1);
7884 /* If X refers to a register that equals REG in value, replace these
7885 references with REG. */
7887 canon_reg_for_combine (rtx x
, rtx reg
)
7894 enum rtx_code code
= GET_CODE (x
);
7895 switch (GET_RTX_CLASS (code
))
7898 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7899 if (op0
!= XEXP (x
, 0))
7900 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7905 case RTX_COMM_ARITH
:
7906 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7907 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7908 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7909 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7913 case RTX_COMM_COMPARE
:
7914 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7915 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7916 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7917 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7918 GET_MODE (op0
), op0
, op1
);
7922 case RTX_BITFIELD_OPS
:
7923 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7924 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7925 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7926 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7927 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7928 GET_MODE (op0
), op0
, op1
, op2
);
7933 if (rtx_equal_p (get_last_value (reg
), x
)
7934 || rtx_equal_p (reg
, get_last_value (x
)))
7943 fmt
= GET_RTX_FORMAT (code
);
7945 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7948 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7949 if (op
!= XEXP (x
, i
))
7959 else if (fmt
[i
] == 'E')
7962 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7964 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7965 if (op
!= XVECEXP (x
, i
, j
))
7972 XVECEXP (x
, i
, j
) = op
;
7983 /* Return X converted to MODE. If the value is already truncated to
7984 MODE we can just return a subreg even though in the general case we
7985 would need an explicit truncation. */
7988 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7990 if (!CONST_INT_P (x
)
7991 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7992 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7993 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7995 /* Bit-cast X into an integer mode. */
7996 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7997 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7998 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8002 return gen_lowpart (mode
, x
);
8005 /* See if X can be simplified knowing that we will only refer to it in
8006 MODE and will only refer to those bits that are nonzero in MASK.
8007 If other bits are being computed or if masking operations are done
8008 that select a superset of the bits in MASK, they can sometimes be
8011 Return a possibly simplified expression, but always convert X to
8012 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8014 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8015 are all off in X. This is used when X will be complemented, by either
8016 NOT, NEG, or XOR. */
8019 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8022 enum rtx_code code
= GET_CODE (x
);
8023 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8024 enum machine_mode op_mode
;
8025 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8028 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8029 code below will do the wrong thing since the mode of such an
8030 expression is VOIDmode.
8032 Also do nothing if X is a CLOBBER; this can happen if X was
8033 the return value from a call to gen_lowpart. */
8034 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8037 /* We want to perform the operation in its present mode unless we know
8038 that the operation is valid in MODE, in which case we do the operation
8040 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8041 && have_insn_for (code
, mode
))
8042 ? mode
: GET_MODE (x
));
8044 /* It is not valid to do a right-shift in a narrower mode
8045 than the one it came in with. */
8046 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8047 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8048 op_mode
= GET_MODE (x
);
8050 /* Truncate MASK to fit OP_MODE. */
8052 mask
&= GET_MODE_MASK (op_mode
);
8054 /* When we have an arithmetic operation, or a shift whose count we
8055 do not know, we need to assume that all bits up to the highest-order
8056 bit in MASK will be needed. This is how we form such a mask. */
8057 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8058 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8060 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8063 /* Determine what bits of X are guaranteed to be (non)zero. */
8064 nonzero
= nonzero_bits (x
, mode
);
8066 /* If none of the bits in X are needed, return a zero. */
8067 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8070 /* If X is a CONST_INT, return a new one. Do this here since the
8071 test below will fail. */
8072 if (CONST_INT_P (x
))
8074 if (SCALAR_INT_MODE_P (mode
))
8075 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8078 x
= GEN_INT (INTVAL (x
) & mask
);
8079 return gen_lowpart_common (mode
, x
);
8083 /* If X is narrower than MODE and we want all the bits in X's mode, just
8084 get X in the proper mode. */
8085 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8086 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8087 return gen_lowpart (mode
, x
);
8089 /* We can ignore the effect of a SUBREG if it narrows the mode or
8090 if the constant masks to zero all the bits the mode doesn't have. */
8091 if (GET_CODE (x
) == SUBREG
8092 && subreg_lowpart_p (x
)
8093 && ((GET_MODE_SIZE (GET_MODE (x
))
8094 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8096 & GET_MODE_MASK (GET_MODE (x
))
8097 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8098 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8100 /* The arithmetic simplifications here only work for scalar integer modes. */
8101 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8102 return gen_lowpart_or_truncate (mode
, x
);
8107 /* If X is a (clobber (const_int)), return it since we know we are
8108 generating something that won't match. */
8115 x
= expand_compound_operation (x
);
8116 if (GET_CODE (x
) != code
)
8117 return force_to_mode (x
, mode
, mask
, next_select
);
8121 /* Similarly for a truncate. */
8122 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8125 /* If this is an AND with a constant, convert it into an AND
8126 whose constant is the AND of that constant with MASK. If it
8127 remains an AND of MASK, delete it since it is redundant. */
8129 if (CONST_INT_P (XEXP (x
, 1)))
8131 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8132 mask
& INTVAL (XEXP (x
, 1)));
8134 /* If X is still an AND, see if it is an AND with a mask that
8135 is just some low-order bits. If so, and it is MASK, we don't
8138 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8139 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8143 /* If it remains an AND, try making another AND with the bits
8144 in the mode mask that aren't in MASK turned on. If the
8145 constant in the AND is wide enough, this might make a
8146 cheaper constant. */
8148 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8149 && GET_MODE_MASK (GET_MODE (x
)) != mask
8150 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8152 unsigned HOST_WIDE_INT cval
8153 = UINTVAL (XEXP (x
, 1))
8154 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8157 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8158 gen_int_mode (cval
, GET_MODE (x
)));
8159 if (set_src_cost (y
, optimize_this_for_speed_p
)
8160 < set_src_cost (x
, optimize_this_for_speed_p
))
8170 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8171 low-order bits (as in an alignment operation) and FOO is already
8172 aligned to that boundary, mask C1 to that boundary as well.
8173 This may eliminate that PLUS and, later, the AND. */
8176 unsigned int width
= GET_MODE_PRECISION (mode
);
8177 unsigned HOST_WIDE_INT smask
= mask
;
8179 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8180 number, sign extend it. */
8182 if (width
< HOST_BITS_PER_WIDE_INT
8183 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8184 smask
|= HOST_WIDE_INT_M1U
<< width
;
8186 if (CONST_INT_P (XEXP (x
, 1))
8187 && exact_log2 (- smask
) >= 0
8188 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8189 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8190 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8191 (INTVAL (XEXP (x
, 1)) & smask
)),
8192 mode
, smask
, next_select
);
8195 /* ... fall through ... */
8198 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8199 most significant bit in MASK since carries from those bits will
8200 affect the bits we are interested in. */
8205 /* If X is (minus C Y) where C's least set bit is larger than any bit
8206 in the mask, then we may replace with (neg Y). */
8207 if (CONST_INT_P (XEXP (x
, 0))
8208 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8210 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8212 return force_to_mode (x
, mode
, mask
, next_select
);
8215 /* Similarly, if C contains every bit in the fuller_mask, then we may
8216 replace with (not Y). */
8217 if (CONST_INT_P (XEXP (x
, 0))
8218 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8220 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8221 XEXP (x
, 1), GET_MODE (x
));
8222 return force_to_mode (x
, mode
, mask
, next_select
);
8230 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8231 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8232 operation which may be a bitfield extraction. Ensure that the
8233 constant we form is not wider than the mode of X. */
8235 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8236 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8237 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8238 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8239 && CONST_INT_P (XEXP (x
, 1))
8240 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8241 + floor_log2 (INTVAL (XEXP (x
, 1))))
8242 < GET_MODE_PRECISION (GET_MODE (x
)))
8243 && (UINTVAL (XEXP (x
, 1))
8244 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8246 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8247 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8249 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8250 XEXP (XEXP (x
, 0), 0), temp
);
8251 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8252 XEXP (XEXP (x
, 0), 1));
8253 return force_to_mode (x
, mode
, mask
, next_select
);
8257 /* For most binary operations, just propagate into the operation and
8258 change the mode if we have an operation of that mode. */
8260 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8261 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8263 /* If we ended up truncating both operands, truncate the result of the
8264 operation instead. */
8265 if (GET_CODE (op0
) == TRUNCATE
8266 && GET_CODE (op1
) == TRUNCATE
)
8268 op0
= XEXP (op0
, 0);
8269 op1
= XEXP (op1
, 0);
8272 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8273 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8275 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8276 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8280 /* For left shifts, do the same, but just for the first operand.
8281 However, we cannot do anything with shifts where we cannot
8282 guarantee that the counts are smaller than the size of the mode
8283 because such a count will have a different meaning in a
8286 if (! (CONST_INT_P (XEXP (x
, 1))
8287 && INTVAL (XEXP (x
, 1)) >= 0
8288 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8289 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8290 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8291 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8294 /* If the shift count is a constant and we can do arithmetic in
8295 the mode of the shift, refine which bits we need. Otherwise, use the
8296 conservative form of the mask. */
8297 if (CONST_INT_P (XEXP (x
, 1))
8298 && INTVAL (XEXP (x
, 1)) >= 0
8299 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8300 && HWI_COMPUTABLE_MODE_P (op_mode
))
8301 mask
>>= INTVAL (XEXP (x
, 1));
8305 op0
= gen_lowpart_or_truncate (op_mode
,
8306 force_to_mode (XEXP (x
, 0), op_mode
,
8307 mask
, next_select
));
8309 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8310 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8314 /* Here we can only do something if the shift count is a constant,
8315 this shift constant is valid for the host, and we can do arithmetic
8318 if (CONST_INT_P (XEXP (x
, 1))
8319 && INTVAL (XEXP (x
, 1)) >= 0
8320 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8321 && HWI_COMPUTABLE_MODE_P (op_mode
))
8323 rtx inner
= XEXP (x
, 0);
8324 unsigned HOST_WIDE_INT inner_mask
;
8326 /* Select the mask of the bits we need for the shift operand. */
8327 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8329 /* We can only change the mode of the shift if we can do arithmetic
8330 in the mode of the shift and INNER_MASK is no wider than the
8331 width of X's mode. */
8332 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8333 op_mode
= GET_MODE (x
);
8335 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8337 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8338 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8341 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8342 shift and AND produces only copies of the sign bit (C2 is one less
8343 than a power of two), we can do this with just a shift. */
8345 if (GET_CODE (x
) == LSHIFTRT
8346 && CONST_INT_P (XEXP (x
, 1))
8347 /* The shift puts one of the sign bit copies in the least significant
8349 && ((INTVAL (XEXP (x
, 1))
8350 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8351 >= GET_MODE_PRECISION (GET_MODE (x
)))
8352 && exact_log2 (mask
+ 1) >= 0
8353 /* Number of bits left after the shift must be more than the mask
8355 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8356 <= GET_MODE_PRECISION (GET_MODE (x
)))
8357 /* Must be more sign bit copies than the mask needs. */
8358 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8359 >= exact_log2 (mask
+ 1)))
8360 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8361 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8362 - exact_log2 (mask
+ 1)));
8367 /* If we are just looking for the sign bit, we don't need this shift at
8368 all, even if it has a variable count. */
8369 if (val_signbit_p (GET_MODE (x
), mask
))
8370 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8372 /* If this is a shift by a constant, get a mask that contains those bits
8373 that are not copies of the sign bit. We then have two cases: If
8374 MASK only includes those bits, this can be a logical shift, which may
8375 allow simplifications. If MASK is a single-bit field not within
8376 those bits, we are requesting a copy of the sign bit and hence can
8377 shift the sign bit to the appropriate location. */
8379 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8380 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8384 /* If the considered data is wider than HOST_WIDE_INT, we can't
8385 represent a mask for all its bits in a single scalar.
8386 But we only care about the lower bits, so calculate these. */
8388 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8390 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8392 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8393 is the number of bits a full-width mask would have set.
8394 We need only shift if these are fewer than nonzero can
8395 hold. If not, we must keep all bits set in nonzero. */
8397 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8398 < HOST_BITS_PER_WIDE_INT
)
8399 nonzero
>>= INTVAL (XEXP (x
, 1))
8400 + HOST_BITS_PER_WIDE_INT
8401 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8405 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8406 nonzero
>>= INTVAL (XEXP (x
, 1));
8409 if ((mask
& ~nonzero
) == 0)
8411 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8412 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8413 if (GET_CODE (x
) != ASHIFTRT
)
8414 return force_to_mode (x
, mode
, mask
, next_select
);
8417 else if ((i
= exact_log2 (mask
)) >= 0)
8419 x
= simplify_shift_const
8420 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8421 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8423 if (GET_CODE (x
) != ASHIFTRT
)
8424 return force_to_mode (x
, mode
, mask
, next_select
);
8428 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8429 even if the shift count isn't a constant. */
8431 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8432 XEXP (x
, 0), XEXP (x
, 1));
8436 /* If this is a zero- or sign-extension operation that just affects bits
8437 we don't care about, remove it. Be sure the call above returned
8438 something that is still a shift. */
8440 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8441 && CONST_INT_P (XEXP (x
, 1))
8442 && INTVAL (XEXP (x
, 1)) >= 0
8443 && (INTVAL (XEXP (x
, 1))
8444 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8445 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8446 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8447 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8454 /* If the shift count is constant and we can do computations
8455 in the mode of X, compute where the bits we care about are.
8456 Otherwise, we can't do anything. Don't change the mode of
8457 the shift or propagate MODE into the shift, though. */
8458 if (CONST_INT_P (XEXP (x
, 1))
8459 && INTVAL (XEXP (x
, 1)) >= 0)
8461 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8463 gen_int_mode (mask
, GET_MODE (x
)),
8465 if (temp
&& CONST_INT_P (temp
))
8466 x
= simplify_gen_binary (code
, GET_MODE (x
),
8467 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8468 INTVAL (temp
), next_select
),
8474 /* If we just want the low-order bit, the NEG isn't needed since it
8475 won't change the low-order bit. */
8477 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8479 /* We need any bits less significant than the most significant bit in
8480 MASK since carries from those bits will affect the bits we are
8486 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8487 same as the XOR case above. Ensure that the constant we form is not
8488 wider than the mode of X. */
8490 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8491 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8492 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8493 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8494 < GET_MODE_PRECISION (GET_MODE (x
)))
8495 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8497 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8499 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8500 XEXP (XEXP (x
, 0), 0), temp
);
8501 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8502 temp
, XEXP (XEXP (x
, 0), 1));
8504 return force_to_mode (x
, mode
, mask
, next_select
);
8507 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8508 use the full mask inside the NOT. */
8512 op0
= gen_lowpart_or_truncate (op_mode
,
8513 force_to_mode (XEXP (x
, 0), mode
, mask
,
8515 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8516 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8520 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8521 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8522 which is equal to STORE_FLAG_VALUE. */
8523 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8524 && XEXP (x
, 1) == const0_rtx
8525 && GET_MODE (XEXP (x
, 0)) == mode
8526 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8527 && (nonzero_bits (XEXP (x
, 0), mode
)
8528 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8529 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8534 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8535 written in a narrower mode. We play it safe and do not do so. */
8537 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8538 force_to_mode (XEXP (x
, 1), mode
,
8539 mask
, next_select
));
8540 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8541 force_to_mode (XEXP (x
, 2), mode
,
8542 mask
, next_select
));
8543 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8544 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8545 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8553 /* Ensure we return a value of the proper mode. */
8554 return gen_lowpart_or_truncate (mode
, x
);
8557 /* Return nonzero if X is an expression that has one of two values depending on
8558 whether some other value is zero or nonzero. In that case, we return the
8559 value that is being tested, *PTRUE is set to the value if the rtx being
8560 returned has a nonzero value, and *PFALSE is set to the other alternative.
8562 If we return zero, we set *PTRUE and *PFALSE to X. */
8565 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8567 enum machine_mode mode
= GET_MODE (x
);
8568 enum rtx_code code
= GET_CODE (x
);
8569 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8570 unsigned HOST_WIDE_INT nz
;
8572 /* If we are comparing a value against zero, we are done. */
8573 if ((code
== NE
|| code
== EQ
)
8574 && XEXP (x
, 1) == const0_rtx
)
8576 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8577 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8581 /* If this is a unary operation whose operand has one of two values, apply
8582 our opcode to compute those values. */
8583 else if (UNARY_P (x
)
8584 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8586 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8587 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8588 GET_MODE (XEXP (x
, 0)));
8592 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8593 make can't possibly match and would suppress other optimizations. */
8594 else if (code
== COMPARE
)
8597 /* If this is a binary operation, see if either side has only one of two
8598 values. If either one does or if both do and they are conditional on
8599 the same value, compute the new true and false values. */
8600 else if (BINARY_P (x
))
8602 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8603 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8605 if ((cond0
!= 0 || cond1
!= 0)
8606 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8608 /* If if_then_else_cond returned zero, then true/false are the
8609 same rtl. We must copy one of them to prevent invalid rtl
8612 true0
= copy_rtx (true0
);
8613 else if (cond1
== 0)
8614 true1
= copy_rtx (true1
);
8616 if (COMPARISON_P (x
))
8618 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8620 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8625 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8626 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8629 return cond0
? cond0
: cond1
;
8632 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8633 operands is zero when the other is nonzero, and vice-versa,
8634 and STORE_FLAG_VALUE is 1 or -1. */
8636 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8637 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8639 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8641 rtx op0
= XEXP (XEXP (x
, 0), 1);
8642 rtx op1
= XEXP (XEXP (x
, 1), 1);
8644 cond0
= XEXP (XEXP (x
, 0), 0);
8645 cond1
= XEXP (XEXP (x
, 1), 0);
8647 if (COMPARISON_P (cond0
)
8648 && COMPARISON_P (cond1
)
8649 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8650 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8651 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8652 || ((swap_condition (GET_CODE (cond0
))
8653 == reversed_comparison_code (cond1
, NULL
))
8654 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8655 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8656 && ! side_effects_p (x
))
8658 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8659 *pfalse
= simplify_gen_binary (MULT
, mode
,
8661 ? simplify_gen_unary (NEG
, mode
,
8669 /* Similarly for MULT, AND and UMIN, except that for these the result
8671 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8672 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8673 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8675 cond0
= XEXP (XEXP (x
, 0), 0);
8676 cond1
= XEXP (XEXP (x
, 1), 0);
8678 if (COMPARISON_P (cond0
)
8679 && COMPARISON_P (cond1
)
8680 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8681 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8682 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8683 || ((swap_condition (GET_CODE (cond0
))
8684 == reversed_comparison_code (cond1
, NULL
))
8685 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8686 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8687 && ! side_effects_p (x
))
8689 *ptrue
= *pfalse
= const0_rtx
;
8695 else if (code
== IF_THEN_ELSE
)
8697 /* If we have IF_THEN_ELSE already, extract the condition and
8698 canonicalize it if it is NE or EQ. */
8699 cond0
= XEXP (x
, 0);
8700 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8701 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8702 return XEXP (cond0
, 0);
8703 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8705 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8706 return XEXP (cond0
, 0);
8712 /* If X is a SUBREG, we can narrow both the true and false values
8713 if the inner expression, if there is a condition. */
8714 else if (code
== SUBREG
8715 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8718 true0
= simplify_gen_subreg (mode
, true0
,
8719 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8720 false0
= simplify_gen_subreg (mode
, false0
,
8721 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8722 if (true0
&& false0
)
8730 /* If X is a constant, this isn't special and will cause confusions
8731 if we treat it as such. Likewise if it is equivalent to a constant. */
8732 else if (CONSTANT_P (x
)
8733 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8736 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8737 will be least confusing to the rest of the compiler. */
8738 else if (mode
== BImode
)
8740 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8744 /* If X is known to be either 0 or -1, those are the true and
8745 false values when testing X. */
8746 else if (x
== constm1_rtx
|| x
== const0_rtx
8747 || (mode
!= VOIDmode
8748 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8750 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8754 /* Likewise for 0 or a single bit. */
8755 else if (HWI_COMPUTABLE_MODE_P (mode
)
8756 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8758 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8762 /* Otherwise fail; show no condition with true and false values the same. */
8763 *ptrue
= *pfalse
= x
;
8767 /* Return the value of expression X given the fact that condition COND
8768 is known to be true when applied to REG as its first operand and VAL
8769 as its second. X is known to not be shared and so can be modified in
8772 We only handle the simplest cases, and specifically those cases that
8773 arise with IF_THEN_ELSE expressions. */
8776 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8778 enum rtx_code code
= GET_CODE (x
);
8783 if (side_effects_p (x
))
8786 /* If either operand of the condition is a floating point value,
8787 then we have to avoid collapsing an EQ comparison. */
8789 && rtx_equal_p (x
, reg
)
8790 && ! FLOAT_MODE_P (GET_MODE (x
))
8791 && ! FLOAT_MODE_P (GET_MODE (val
)))
8794 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8797 /* If X is (abs REG) and we know something about REG's relationship
8798 with zero, we may be able to simplify this. */
8800 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8803 case GE
: case GT
: case EQ
:
8806 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8808 GET_MODE (XEXP (x
, 0)));
8813 /* The only other cases we handle are MIN, MAX, and comparisons if the
8814 operands are the same as REG and VAL. */
8816 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8818 if (rtx_equal_p (XEXP (x
, 0), val
))
8819 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8821 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8823 if (COMPARISON_P (x
))
8825 if (comparison_dominates_p (cond
, code
))
8826 return const_true_rtx
;
8828 code
= reversed_comparison_code (x
, NULL
);
8830 && comparison_dominates_p (cond
, code
))
8835 else if (code
== SMAX
|| code
== SMIN
8836 || code
== UMIN
|| code
== UMAX
)
8838 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8840 /* Do not reverse the condition when it is NE or EQ.
8841 This is because we cannot conclude anything about
8842 the value of 'SMAX (x, y)' when x is not equal to y,
8843 but we can when x equals y. */
8844 if ((code
== SMAX
|| code
== UMAX
)
8845 && ! (cond
== EQ
|| cond
== NE
))
8846 cond
= reverse_condition (cond
);
8851 return unsignedp
? x
: XEXP (x
, 1);
8853 return unsignedp
? x
: XEXP (x
, 0);
8855 return unsignedp
? XEXP (x
, 1) : x
;
8857 return unsignedp
? XEXP (x
, 0) : x
;
8864 else if (code
== SUBREG
)
8866 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8867 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8869 if (SUBREG_REG (x
) != r
)
8871 /* We must simplify subreg here, before we lose track of the
8872 original inner_mode. */
8873 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8874 inner_mode
, SUBREG_BYTE (x
));
8878 SUBST (SUBREG_REG (x
), r
);
8883 /* We don't have to handle SIGN_EXTEND here, because even in the
8884 case of replacing something with a modeless CONST_INT, a
8885 CONST_INT is already (supposed to be) a valid sign extension for
8886 its narrower mode, which implies it's already properly
8887 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8888 story is different. */
8889 else if (code
== ZERO_EXTEND
)
8891 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8892 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8894 if (XEXP (x
, 0) != r
)
8896 /* We must simplify the zero_extend here, before we lose
8897 track of the original inner_mode. */
8898 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8903 SUBST (XEXP (x
, 0), r
);
8909 fmt
= GET_RTX_FORMAT (code
);
8910 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8913 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8914 else if (fmt
[i
] == 'E')
8915 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8916 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8923 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8924 assignment as a field assignment. */
8927 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8929 if (x
== y
|| rtx_equal_p (x
, y
))
8932 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8935 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8936 Note that all SUBREGs of MEM are paradoxical; otherwise they
8937 would have been rewritten. */
8938 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8939 && MEM_P (SUBREG_REG (y
))
8940 && rtx_equal_p (SUBREG_REG (y
),
8941 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8944 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8945 && MEM_P (SUBREG_REG (x
))
8946 && rtx_equal_p (SUBREG_REG (x
),
8947 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8950 /* We used to see if get_last_value of X and Y were the same but that's
8951 not correct. In one direction, we'll cause the assignment to have
8952 the wrong destination and in the case, we'll import a register into this
8953 insn that might have already have been dead. So fail if none of the
8954 above cases are true. */
8958 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8959 Return that assignment if so.
8961 We only handle the most common cases. */
8964 make_field_assignment (rtx x
)
8966 rtx dest
= SET_DEST (x
);
8967 rtx src
= SET_SRC (x
);
8972 unsigned HOST_WIDE_INT len
;
8974 enum machine_mode mode
;
8976 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8977 a clear of a one-bit field. We will have changed it to
8978 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8981 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8982 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8983 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8984 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8986 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8989 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8993 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8994 && subreg_lowpart_p (XEXP (src
, 0))
8995 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8996 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8997 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8998 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8999 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9000 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9002 assign
= make_extraction (VOIDmode
, dest
, 0,
9003 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9006 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9010 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9012 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9013 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9014 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9016 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9019 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9023 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9024 SRC is an AND with all bits of that field set, then we can discard
9026 if (GET_CODE (dest
) == ZERO_EXTRACT
9027 && CONST_INT_P (XEXP (dest
, 1))
9028 && GET_CODE (src
) == AND
9029 && CONST_INT_P (XEXP (src
, 1)))
9031 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9032 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9033 unsigned HOST_WIDE_INT ze_mask
;
9035 if (width
>= HOST_BITS_PER_WIDE_INT
)
9038 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9040 /* Complete overlap. We can remove the source AND. */
9041 if ((and_mask
& ze_mask
) == ze_mask
)
9042 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9044 /* Partial overlap. We can reduce the source AND. */
9045 if ((and_mask
& ze_mask
) != and_mask
)
9047 mode
= GET_MODE (src
);
9048 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9049 gen_int_mode (and_mask
& ze_mask
, mode
));
9050 return gen_rtx_SET (VOIDmode
, dest
, src
);
9054 /* The other case we handle is assignments into a constant-position
9055 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9056 a mask that has all one bits except for a group of zero bits and
9057 OTHER is known to have zeros where C1 has ones, this is such an
9058 assignment. Compute the position and length from C1. Shift OTHER
9059 to the appropriate position, force it to the required mode, and
9060 make the extraction. Check for the AND in both operands. */
9062 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9065 rhs
= expand_compound_operation (XEXP (src
, 0));
9066 lhs
= expand_compound_operation (XEXP (src
, 1));
9068 if (GET_CODE (rhs
) == AND
9069 && CONST_INT_P (XEXP (rhs
, 1))
9070 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9071 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9072 else if (GET_CODE (lhs
) == AND
9073 && CONST_INT_P (XEXP (lhs
, 1))
9074 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9075 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9079 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9080 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9081 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9082 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9085 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9089 /* The mode to use for the source is the mode of the assignment, or of
9090 what is inside a possible STRICT_LOW_PART. */
9091 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9092 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9094 /* Shift OTHER right POS places and make it the source, restricting it
9095 to the proper length and mode. */
9097 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9101 src
= force_to_mode (src
, mode
,
9102 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9103 ? ~(unsigned HOST_WIDE_INT
) 0
9104 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9107 /* If SRC is masked by an AND that does not make a difference in
9108 the value being stored, strip it. */
9109 if (GET_CODE (assign
) == ZERO_EXTRACT
9110 && CONST_INT_P (XEXP (assign
, 1))
9111 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9112 && GET_CODE (src
) == AND
9113 && CONST_INT_P (XEXP (src
, 1))
9114 && UINTVAL (XEXP (src
, 1))
9115 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9116 src
= XEXP (src
, 0);
9118 return gen_rtx_SET (VOIDmode
, assign
, src
);
9121 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9125 apply_distributive_law (rtx x
)
9127 enum rtx_code code
= GET_CODE (x
);
9128 enum rtx_code inner_code
;
9129 rtx lhs
, rhs
, other
;
9132 /* Distributivity is not true for floating point as it can change the
9133 value. So we don't do it unless -funsafe-math-optimizations. */
9134 if (FLOAT_MODE_P (GET_MODE (x
))
9135 && ! flag_unsafe_math_optimizations
)
9138 /* The outer operation can only be one of the following: */
9139 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9140 && code
!= PLUS
&& code
!= MINUS
)
9146 /* If either operand is a primitive we can't do anything, so get out
9148 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9151 lhs
= expand_compound_operation (lhs
);
9152 rhs
= expand_compound_operation (rhs
);
9153 inner_code
= GET_CODE (lhs
);
9154 if (inner_code
!= GET_CODE (rhs
))
9157 /* See if the inner and outer operations distribute. */
9164 /* These all distribute except over PLUS. */
9165 if (code
== PLUS
|| code
== MINUS
)
9170 if (code
!= PLUS
&& code
!= MINUS
)
9175 /* This is also a multiply, so it distributes over everything. */
9178 /* This used to handle SUBREG, but this turned out to be counter-
9179 productive, since (subreg (op ...)) usually is not handled by
9180 insn patterns, and this "optimization" therefore transformed
9181 recognizable patterns into unrecognizable ones. Therefore the
9182 SUBREG case was removed from here.
9184 It is possible that distributing SUBREG over arithmetic operations
9185 leads to an intermediate result than can then be optimized further,
9186 e.g. by moving the outer SUBREG to the other side of a SET as done
9187 in simplify_set. This seems to have been the original intent of
9188 handling SUBREGs here.
9190 However, with current GCC this does not appear to actually happen,
9191 at least on major platforms. If some case is found where removing
9192 the SUBREG case here prevents follow-on optimizations, distributing
9193 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9199 /* Set LHS and RHS to the inner operands (A and B in the example
9200 above) and set OTHER to the common operand (C in the example).
9201 There is only one way to do this unless the inner operation is
9203 if (COMMUTATIVE_ARITH_P (lhs
)
9204 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9205 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9206 else if (COMMUTATIVE_ARITH_P (lhs
)
9207 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9208 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9209 else if (COMMUTATIVE_ARITH_P (lhs
)
9210 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9211 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9212 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9213 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9217 /* Form the new inner operation, seeing if it simplifies first. */
9218 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9220 /* There is one exception to the general way of distributing:
9221 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9222 if (code
== XOR
&& inner_code
== IOR
)
9225 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9228 /* We may be able to continuing distributing the result, so call
9229 ourselves recursively on the inner operation before forming the
9230 outer operation, which we return. */
9231 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9232 apply_distributive_law (tem
), other
);
9235 /* See if X is of the form (* (+ A B) C), and if so convert to
9236 (+ (* A C) (* B C)) and try to simplify.
9238 Most of the time, this results in no change. However, if some of
9239 the operands are the same or inverses of each other, simplifications
9242 For example, (and (ior A B) (not B)) can occur as the result of
9243 expanding a bit field assignment. When we apply the distributive
9244 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9245 which then simplifies to (and (A (not B))).
9247 Note that no checks happen on the validity of applying the inverse
9248 distributive law. This is pointless since we can do it in the
9249 few places where this routine is called.
9251 N is the index of the term that is decomposed (the arithmetic operation,
9252 i.e. (+ A B) in the first example above). !N is the index of the term that
9253 is distributed, i.e. of C in the first example above. */
9255 distribute_and_simplify_rtx (rtx x
, int n
)
9257 enum machine_mode mode
;
9258 enum rtx_code outer_code
, inner_code
;
9259 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9261 /* Distributivity is not true for floating point as it can change the
9262 value. So we don't do it unless -funsafe-math-optimizations. */
9263 if (FLOAT_MODE_P (GET_MODE (x
))
9264 && ! flag_unsafe_math_optimizations
)
9267 decomposed
= XEXP (x
, n
);
9268 if (!ARITHMETIC_P (decomposed
))
9271 mode
= GET_MODE (x
);
9272 outer_code
= GET_CODE (x
);
9273 distributed
= XEXP (x
, !n
);
9275 inner_code
= GET_CODE (decomposed
);
9276 inner_op0
= XEXP (decomposed
, 0);
9277 inner_op1
= XEXP (decomposed
, 1);
9279 /* Special case (and (xor B C) (not A)), which is equivalent to
9280 (xor (ior A B) (ior A C)) */
9281 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9283 distributed
= XEXP (distributed
, 0);
9289 /* Distribute the second term. */
9290 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9291 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9295 /* Distribute the first term. */
9296 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9297 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9300 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9302 if (GET_CODE (tmp
) != outer_code
9303 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9304 < set_src_cost (x
, optimize_this_for_speed_p
)))
9310 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9311 in MODE. Return an equivalent form, if different from (and VAROP
9312 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9315 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9316 unsigned HOST_WIDE_INT constop
)
9318 unsigned HOST_WIDE_INT nonzero
;
9319 unsigned HOST_WIDE_INT orig_constop
;
9324 orig_constop
= constop
;
9325 if (GET_CODE (varop
) == CLOBBER
)
9328 /* Simplify VAROP knowing that we will be only looking at some of the
9331 Note by passing in CONSTOP, we guarantee that the bits not set in
9332 CONSTOP are not significant and will never be examined. We must
9333 ensure that is the case by explicitly masking out those bits
9334 before returning. */
9335 varop
= force_to_mode (varop
, mode
, constop
, 0);
9337 /* If VAROP is a CLOBBER, we will fail so return it. */
9338 if (GET_CODE (varop
) == CLOBBER
)
9341 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9342 to VAROP and return the new constant. */
9343 if (CONST_INT_P (varop
))
9344 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9346 /* See what bits may be nonzero in VAROP. Unlike the general case of
9347 a call to nonzero_bits, here we don't care about bits outside
9350 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9352 /* Turn off all bits in the constant that are known to already be zero.
9353 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9354 which is tested below. */
9358 /* If we don't have any bits left, return zero. */
9362 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9363 a power of two, we can replace this with an ASHIFT. */
9364 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9365 && (i
= exact_log2 (constop
)) >= 0)
9366 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9368 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9369 or XOR, then try to apply the distributive law. This may eliminate
9370 operations if either branch can be simplified because of the AND.
9371 It may also make some cases more complex, but those cases probably
9372 won't match a pattern either with or without this. */
9374 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9378 apply_distributive_law
9379 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9380 simplify_and_const_int (NULL_RTX
,
9384 simplify_and_const_int (NULL_RTX
,
9389 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9390 the AND and see if one of the operands simplifies to zero. If so, we
9391 may eliminate it. */
9393 if (GET_CODE (varop
) == PLUS
9394 && exact_log2 (constop
+ 1) >= 0)
9398 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9399 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9400 if (o0
== const0_rtx
)
9402 if (o1
== const0_rtx
)
9406 /* Make a SUBREG if necessary. If we can't make it, fail. */
9407 varop
= gen_lowpart (mode
, varop
);
9408 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9411 /* If we are only masking insignificant bits, return VAROP. */
9412 if (constop
== nonzero
)
9415 if (varop
== orig_varop
&& constop
== orig_constop
)
9418 /* Otherwise, return an AND. */
9419 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9423 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9426 Return an equivalent form, if different from X. Otherwise, return X. If
9427 X is zero, we are to always construct the equivalent form. */
9430 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9431 unsigned HOST_WIDE_INT constop
)
9433 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9438 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9439 gen_int_mode (constop
, mode
));
9440 if (GET_MODE (x
) != mode
)
9441 x
= gen_lowpart (mode
, x
);
9445 /* Given a REG, X, compute which bits in X can be nonzero.
9446 We don't care about bits outside of those defined in MODE.
9448 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9449 a shift, AND, or zero_extract, we can do better. */
9452 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9453 const_rtx known_x ATTRIBUTE_UNUSED
,
9454 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9455 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9456 unsigned HOST_WIDE_INT
*nonzero
)
9461 /* If X is a register whose nonzero bits value is current, use it.
9462 Otherwise, if X is a register whose value we can find, use that
9463 value. Otherwise, use the previously-computed global nonzero bits
9464 for this register. */
9466 rsp
= ®_stat
[REGNO (x
)];
9467 if (rsp
->last_set_value
!= 0
9468 && (rsp
->last_set_mode
== mode
9469 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9470 && GET_MODE_CLASS (mode
) == MODE_INT
))
9471 && ((rsp
->last_set_label
>= label_tick_ebb_start
9472 && rsp
->last_set_label
< label_tick
)
9473 || (rsp
->last_set_label
== label_tick
9474 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9475 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9476 && REG_N_SETS (REGNO (x
)) == 1
9478 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9481 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9483 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9484 /* We don't know anything about the upper bits. */
9485 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9491 tem
= get_last_value (x
);
9495 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9496 /* If X is narrower than MODE and TEM is a non-negative
9497 constant that would appear negative in the mode of X,
9498 sign-extend it for use in reg_nonzero_bits because some
9499 machines (maybe most) will actually do the sign-extension
9500 and this is the conservative approach.
9502 ??? For 2.5, try to tighten up the MD files in this regard
9503 instead of this kludge. */
9505 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9506 && CONST_INT_P (tem
)
9508 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9509 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9513 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9515 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9517 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9518 /* We don't know anything about the upper bits. */
9519 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9527 /* Return the number of bits at the high-order end of X that are known to
9528 be equal to the sign bit. X will be used in mode MODE; if MODE is
9529 VOIDmode, X will be used in its own mode. The returned value will always
9530 be between 1 and the number of bits in MODE. */
9533 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9534 const_rtx known_x ATTRIBUTE_UNUSED
,
9535 enum machine_mode known_mode
9537 unsigned int known_ret ATTRIBUTE_UNUSED
,
9538 unsigned int *result
)
9543 rsp
= ®_stat
[REGNO (x
)];
9544 if (rsp
->last_set_value
!= 0
9545 && rsp
->last_set_mode
== mode
9546 && ((rsp
->last_set_label
>= label_tick_ebb_start
9547 && rsp
->last_set_label
< label_tick
)
9548 || (rsp
->last_set_label
== label_tick
9549 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9550 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9551 && REG_N_SETS (REGNO (x
)) == 1
9553 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9556 *result
= rsp
->last_set_sign_bit_copies
;
9560 tem
= get_last_value (x
);
9564 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9565 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9566 *result
= rsp
->sign_bit_copies
;
9571 /* Return the number of "extended" bits there are in X, when interpreted
9572 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9573 unsigned quantities, this is the number of high-order zero bits.
9574 For signed quantities, this is the number of copies of the sign bit
9575 minus 1. In both case, this function returns the number of "spare"
9576 bits. For example, if two quantities for which this function returns
9577 at least 1 are added, the addition is known not to overflow.
9579 This function will always return 0 unless called during combine, which
9580 implies that it must be called from a define_split. */
9583 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9585 if (nonzero_sign_valid
== 0)
9589 ? (HWI_COMPUTABLE_MODE_P (mode
)
9590 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9591 - floor_log2 (nonzero_bits (x
, mode
)))
9593 : num_sign_bit_copies (x
, mode
) - 1);
9596 /* This function is called from `simplify_shift_const' to merge two
9597 outer operations. Specifically, we have already found that we need
9598 to perform operation *POP0 with constant *PCONST0 at the outermost
9599 position. We would now like to also perform OP1 with constant CONST1
9600 (with *POP0 being done last).
9602 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9603 the resulting operation. *PCOMP_P is set to 1 if we would need to
9604 complement the innermost operand, otherwise it is unchanged.
9606 MODE is the mode in which the operation will be done. No bits outside
9607 the width of this mode matter. It is assumed that the width of this mode
9608 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9610 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9611 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9612 result is simply *PCONST0.
9614 If the resulting operation cannot be expressed as one operation, we
9615 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9618 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9620 enum rtx_code op0
= *pop0
;
9621 HOST_WIDE_INT const0
= *pconst0
;
9623 const0
&= GET_MODE_MASK (mode
);
9624 const1
&= GET_MODE_MASK (mode
);
9626 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9630 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9633 if (op1
== UNKNOWN
|| op0
== SET
)
9636 else if (op0
== UNKNOWN
)
9637 op0
= op1
, const0
= const1
;
9639 else if (op0
== op1
)
9663 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9664 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9667 /* If the two constants aren't the same, we can't do anything. The
9668 remaining six cases can all be done. */
9669 else if (const0
!= const1
)
9677 /* (a & b) | b == b */
9679 else /* op1 == XOR */
9680 /* (a ^ b) | b == a | b */
9686 /* (a & b) ^ b == (~a) & b */
9687 op0
= AND
, *pcomp_p
= 1;
9688 else /* op1 == IOR */
9689 /* (a | b) ^ b == a & ~b */
9690 op0
= AND
, const0
= ~const0
;
9695 /* (a | b) & b == b */
9697 else /* op1 == XOR */
9698 /* (a ^ b) & b) == (~a) & b */
9705 /* Check for NO-OP cases. */
9706 const0
&= GET_MODE_MASK (mode
);
9708 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9710 else if (const0
== 0 && op0
== AND
)
9712 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9718 /* ??? Slightly redundant with the above mask, but not entirely.
9719 Moving this above means we'd have to sign-extend the mode mask
9720 for the final test. */
9721 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9722 *pconst0
= trunc_int_for_mode (const0
, mode
);
9727 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9728 the shift in. The original shift operation CODE is performed on OP in
9729 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9730 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9731 result of the shift is subject to operation OUTER_CODE with operand
9734 static enum machine_mode
9735 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9736 enum machine_mode orig_mode
, enum machine_mode mode
,
9737 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9739 if (orig_mode
== mode
)
9741 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9743 /* In general we can't perform in wider mode for right shift and rotate. */
9747 /* We can still widen if the bits brought in from the left are identical
9748 to the sign bit of ORIG_MODE. */
9749 if (num_sign_bit_copies (op
, mode
)
9750 > (unsigned) (GET_MODE_PRECISION (mode
)
9751 - GET_MODE_PRECISION (orig_mode
)))
9756 /* Similarly here but with zero bits. */
9757 if (HWI_COMPUTABLE_MODE_P (mode
)
9758 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9761 /* We can also widen if the bits brought in will be masked off. This
9762 operation is performed in ORIG_MODE. */
9763 if (outer_code
== AND
)
9765 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9768 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9784 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9785 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9786 if we cannot simplify it. Otherwise, return a simplified value.
9788 The shift is normally computed in the widest mode we find in VAROP, as
9789 long as it isn't a different number of words than RESULT_MODE. Exceptions
9790 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9793 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9794 rtx varop
, int orig_count
)
9796 enum rtx_code orig_code
= code
;
9797 rtx orig_varop
= varop
;
9799 enum machine_mode mode
= result_mode
;
9800 enum machine_mode shift_mode
, tmode
;
9801 unsigned int mode_words
9802 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9803 /* We form (outer_op (code varop count) (outer_const)). */
9804 enum rtx_code outer_op
= UNKNOWN
;
9805 HOST_WIDE_INT outer_const
= 0;
9806 int complement_p
= 0;
9809 /* Make sure and truncate the "natural" shift on the way in. We don't
9810 want to do this inside the loop as it makes it more difficult to
9812 if (SHIFT_COUNT_TRUNCATED
)
9813 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9815 /* If we were given an invalid count, don't do anything except exactly
9816 what was requested. */
9818 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9823 /* Unless one of the branches of the `if' in this loop does a `continue',
9824 we will `break' the loop after the `if'. */
9828 /* If we have an operand of (clobber (const_int 0)), fail. */
9829 if (GET_CODE (varop
) == CLOBBER
)
9832 /* Convert ROTATERT to ROTATE. */
9833 if (code
== ROTATERT
)
9835 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9837 if (VECTOR_MODE_P (result_mode
))
9838 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9840 count
= bitsize
- count
;
9843 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9844 mode
, outer_op
, outer_const
);
9846 /* Handle cases where the count is greater than the size of the mode
9847 minus 1. For ASHIFT, use the size minus one as the count (this can
9848 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9849 take the count modulo the size. For other shifts, the result is
9852 Since these shifts are being produced by the compiler by combining
9853 multiple operations, each of which are defined, we know what the
9854 result is supposed to be. */
9856 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9858 if (code
== ASHIFTRT
)
9859 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9860 else if (code
== ROTATE
|| code
== ROTATERT
)
9861 count
%= GET_MODE_PRECISION (shift_mode
);
9864 /* We can't simply return zero because there may be an
9872 /* If we discovered we had to complement VAROP, leave. Making a NOT
9873 here would cause an infinite loop. */
9877 /* An arithmetic right shift of a quantity known to be -1 or 0
9879 if (code
== ASHIFTRT
9880 && (num_sign_bit_copies (varop
, shift_mode
)
9881 == GET_MODE_PRECISION (shift_mode
)))
9887 /* If we are doing an arithmetic right shift and discarding all but
9888 the sign bit copies, this is equivalent to doing a shift by the
9889 bitsize minus one. Convert it into that shift because it will often
9890 allow other simplifications. */
9892 if (code
== ASHIFTRT
9893 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9894 >= GET_MODE_PRECISION (shift_mode
)))
9895 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9897 /* We simplify the tests below and elsewhere by converting
9898 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9899 `make_compound_operation' will convert it to an ASHIFTRT for
9900 those machines (such as VAX) that don't have an LSHIFTRT. */
9901 if (code
== ASHIFTRT
9902 && val_signbit_known_clear_p (shift_mode
,
9903 nonzero_bits (varop
, shift_mode
)))
9906 if (((code
== LSHIFTRT
9907 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9908 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9910 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9911 && !((nonzero_bits (varop
, shift_mode
) << count
)
9912 & GET_MODE_MASK (shift_mode
))))
9913 && !side_effects_p (varop
))
9916 switch (GET_CODE (varop
))
9922 new_rtx
= expand_compound_operation (varop
);
9923 if (new_rtx
!= varop
)
9931 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9932 minus the width of a smaller mode, we can do this with a
9933 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9934 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9935 && ! mode_dependent_address_p (XEXP (varop
, 0),
9936 MEM_ADDR_SPACE (varop
))
9937 && ! MEM_VOLATILE_P (varop
)
9938 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9939 MODE_INT
, 1)) != BLKmode
)
9941 new_rtx
= adjust_address_nv (varop
, tmode
,
9942 BYTES_BIG_ENDIAN
? 0
9943 : count
/ BITS_PER_UNIT
);
9945 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9946 : ZERO_EXTEND
, mode
, new_rtx
);
9953 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9954 the same number of words as what we've seen so far. Then store
9955 the widest mode in MODE. */
9956 if (subreg_lowpart_p (varop
)
9957 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9958 > GET_MODE_SIZE (GET_MODE (varop
)))
9959 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9960 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9962 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9963 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9965 varop
= SUBREG_REG (varop
);
9966 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9967 mode
= GET_MODE (varop
);
9973 /* Some machines use MULT instead of ASHIFT because MULT
9974 is cheaper. But it is still better on those machines to
9975 merge two shifts into one. */
9976 if (CONST_INT_P (XEXP (varop
, 1))
9977 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9980 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9982 GEN_INT (exact_log2 (
9983 UINTVAL (XEXP (varop
, 1)))));
9989 /* Similar, for when divides are cheaper. */
9990 if (CONST_INT_P (XEXP (varop
, 1))
9991 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9994 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9996 GEN_INT (exact_log2 (
9997 UINTVAL (XEXP (varop
, 1)))));
10003 /* If we are extracting just the sign bit of an arithmetic
10004 right shift, that shift is not needed. However, the sign
10005 bit of a wider mode may be different from what would be
10006 interpreted as the sign bit in a narrower mode, so, if
10007 the result is narrower, don't discard the shift. */
10008 if (code
== LSHIFTRT
10009 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10010 && (GET_MODE_BITSIZE (result_mode
)
10011 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10013 varop
= XEXP (varop
, 0);
10017 /* ... fall through ... */
10022 /* Here we have two nested shifts. The result is usually the
10023 AND of a new shift with a mask. We compute the result below. */
10024 if (CONST_INT_P (XEXP (varop
, 1))
10025 && INTVAL (XEXP (varop
, 1)) >= 0
10026 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10027 && HWI_COMPUTABLE_MODE_P (result_mode
)
10028 && HWI_COMPUTABLE_MODE_P (mode
)
10029 && !VECTOR_MODE_P (result_mode
))
10031 enum rtx_code first_code
= GET_CODE (varop
);
10032 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10033 unsigned HOST_WIDE_INT mask
;
10036 /* We have one common special case. We can't do any merging if
10037 the inner code is an ASHIFTRT of a smaller mode. However, if
10038 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10039 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10040 we can convert it to
10041 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10042 This simplifies certain SIGN_EXTEND operations. */
10043 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10044 && count
== (GET_MODE_PRECISION (result_mode
)
10045 - GET_MODE_PRECISION (GET_MODE (varop
))))
10047 /* C3 has the low-order C1 bits zero. */
10049 mask
= GET_MODE_MASK (mode
)
10050 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10052 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10053 XEXP (varop
, 0), mask
);
10054 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10056 count
= first_count
;
10061 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10062 than C1 high-order bits equal to the sign bit, we can convert
10063 this to either an ASHIFT or an ASHIFTRT depending on the
10066 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10068 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10069 && GET_MODE (varop
) == shift_mode
10070 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10073 varop
= XEXP (varop
, 0);
10074 count
-= first_count
;
10084 /* There are some cases we can't do. If CODE is ASHIFTRT,
10085 we can only do this if FIRST_CODE is also ASHIFTRT.
10087 We can't do the case when CODE is ROTATE and FIRST_CODE is
10090 If the mode of this shift is not the mode of the outer shift,
10091 we can't do this if either shift is a right shift or ROTATE.
10093 Finally, we can't do any of these if the mode is too wide
10094 unless the codes are the same.
10096 Handle the case where the shift codes are the same
10099 if (code
== first_code
)
10101 if (GET_MODE (varop
) != result_mode
10102 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10103 || code
== ROTATE
))
10106 count
+= first_count
;
10107 varop
= XEXP (varop
, 0);
10111 if (code
== ASHIFTRT
10112 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10113 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10114 || (GET_MODE (varop
) != result_mode
10115 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10116 || first_code
== ROTATE
10117 || code
== ROTATE
)))
10120 /* To compute the mask to apply after the shift, shift the
10121 nonzero bits of the inner shift the same way the
10122 outer shift will. */
10124 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10128 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10131 /* Give up if we can't compute an outer operation to use. */
10133 || !CONST_INT_P (mask_rtx
)
10134 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10136 result_mode
, &complement_p
))
10139 /* If the shifts are in the same direction, we add the
10140 counts. Otherwise, we subtract them. */
10141 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10142 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10143 count
+= first_count
;
10145 count
-= first_count
;
10147 /* If COUNT is positive, the new shift is usually CODE,
10148 except for the two exceptions below, in which case it is
10149 FIRST_CODE. If the count is negative, FIRST_CODE should
10152 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10153 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10155 else if (count
< 0)
10156 code
= first_code
, count
= -count
;
10158 varop
= XEXP (varop
, 0);
10162 /* If we have (A << B << C) for any shift, we can convert this to
10163 (A << C << B). This wins if A is a constant. Only try this if
10164 B is not a constant. */
10166 else if (GET_CODE (varop
) == code
10167 && CONST_INT_P (XEXP (varop
, 0))
10168 && !CONST_INT_P (XEXP (varop
, 1)))
10170 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10173 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10180 if (VECTOR_MODE_P (mode
))
10183 /* Make this fit the case below. */
10184 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10190 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10191 with C the size of VAROP - 1 and the shift is logical if
10192 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10193 we have an (le X 0) operation. If we have an arithmetic shift
10194 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10195 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10197 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10198 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10199 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10200 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10201 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10202 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10205 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10208 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10209 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10214 /* If we have (shift (logical)), move the logical to the outside
10215 to allow it to possibly combine with another logical and the
10216 shift to combine with another shift. This also canonicalizes to
10217 what a ZERO_EXTRACT looks like. Also, some machines have
10218 (and (shift)) insns. */
10220 if (CONST_INT_P (XEXP (varop
, 1))
10221 /* We can't do this if we have (ashiftrt (xor)) and the
10222 constant has its sign bit set in shift_mode. */
10223 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10224 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10226 && (new_rtx
= simplify_const_binary_operation
10227 (code
, result_mode
,
10228 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10229 GEN_INT (count
))) != 0
10230 && CONST_INT_P (new_rtx
)
10231 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10232 INTVAL (new_rtx
), result_mode
, &complement_p
))
10234 varop
= XEXP (varop
, 0);
10238 /* If we can't do that, try to simplify the shift in each arm of the
10239 logical expression, make a new logical expression, and apply
10240 the inverse distributive law. This also can't be done
10241 for some (ashiftrt (xor)). */
10242 if (CONST_INT_P (XEXP (varop
, 1))
10243 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10244 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10247 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10248 XEXP (varop
, 0), count
);
10249 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10250 XEXP (varop
, 1), count
);
10252 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10254 varop
= apply_distributive_law (varop
);
10262 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10263 says that the sign bit can be tested, FOO has mode MODE, C is
10264 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10265 that may be nonzero. */
10266 if (code
== LSHIFTRT
10267 && XEXP (varop
, 1) == const0_rtx
10268 && GET_MODE (XEXP (varop
, 0)) == result_mode
10269 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10270 && HWI_COMPUTABLE_MODE_P (result_mode
)
10271 && STORE_FLAG_VALUE
== -1
10272 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10273 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10276 varop
= XEXP (varop
, 0);
10283 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10284 than the number of bits in the mode is equivalent to A. */
10285 if (code
== LSHIFTRT
10286 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10287 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10289 varop
= XEXP (varop
, 0);
10294 /* NEG commutes with ASHIFT since it is multiplication. Move the
10295 NEG outside to allow shifts to combine. */
10297 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10300 varop
= XEXP (varop
, 0);
10306 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10307 is one less than the number of bits in the mode is
10308 equivalent to (xor A 1). */
10309 if (code
== LSHIFTRT
10310 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10311 && XEXP (varop
, 1) == constm1_rtx
10312 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10313 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10317 varop
= XEXP (varop
, 0);
10321 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10322 that might be nonzero in BAR are those being shifted out and those
10323 bits are known zero in FOO, we can replace the PLUS with FOO.
10324 Similarly in the other operand order. This code occurs when
10325 we are computing the size of a variable-size array. */
10327 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10328 && count
< HOST_BITS_PER_WIDE_INT
10329 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10330 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10331 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10333 varop
= XEXP (varop
, 0);
10336 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10337 && count
< HOST_BITS_PER_WIDE_INT
10338 && HWI_COMPUTABLE_MODE_P (result_mode
)
10339 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10341 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10342 & nonzero_bits (XEXP (varop
, 1),
10345 varop
= XEXP (varop
, 1);
10349 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10351 && CONST_INT_P (XEXP (varop
, 1))
10352 && (new_rtx
= simplify_const_binary_operation
10353 (ASHIFT
, result_mode
,
10354 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10355 GEN_INT (count
))) != 0
10356 && CONST_INT_P (new_rtx
)
10357 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10358 INTVAL (new_rtx
), result_mode
, &complement_p
))
10360 varop
= XEXP (varop
, 0);
10364 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10365 signbit', and attempt to change the PLUS to an XOR and move it to
10366 the outer operation as is done above in the AND/IOR/XOR case
10367 leg for shift(logical). See details in logical handling above
10368 for reasoning in doing so. */
10369 if (code
== LSHIFTRT
10370 && CONST_INT_P (XEXP (varop
, 1))
10371 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10372 && (new_rtx
= simplify_const_binary_operation
10373 (code
, result_mode
,
10374 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10375 GEN_INT (count
))) != 0
10376 && CONST_INT_P (new_rtx
)
10377 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10378 INTVAL (new_rtx
), result_mode
, &complement_p
))
10380 varop
= XEXP (varop
, 0);
10387 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10388 with C the size of VAROP - 1 and the shift is logical if
10389 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10390 we have a (gt X 0) operation. If the shift is arithmetic with
10391 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10392 we have a (neg (gt X 0)) operation. */
10394 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10395 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10396 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10397 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10398 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10399 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10400 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10403 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10406 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10407 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10414 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10415 if the truncate does not affect the value. */
10416 if (code
== LSHIFTRT
10417 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10418 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10419 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10420 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10421 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10423 rtx varop_inner
= XEXP (varop
, 0);
10426 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10427 XEXP (varop_inner
, 0),
10429 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10430 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10443 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10444 outer_op
, outer_const
);
10446 /* We have now finished analyzing the shift. The result should be
10447 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10448 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10449 to the result of the shift. OUTER_CONST is the relevant constant,
10450 but we must turn off all bits turned off in the shift. */
10452 if (outer_op
== UNKNOWN
10453 && orig_code
== code
&& orig_count
== count
10454 && varop
== orig_varop
10455 && shift_mode
== GET_MODE (varop
))
10458 /* Make a SUBREG if necessary. If we can't make it, fail. */
10459 varop
= gen_lowpart (shift_mode
, varop
);
10460 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10463 /* If we have an outer operation and we just made a shift, it is
10464 possible that we could have simplified the shift were it not
10465 for the outer operation. So try to do the simplification
10468 if (outer_op
!= UNKNOWN
)
10469 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10474 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10476 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10477 turn off all the bits that the shift would have turned off. */
10478 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10479 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10480 GET_MODE_MASK (result_mode
) >> orig_count
);
10482 /* Do the remainder of the processing in RESULT_MODE. */
10483 x
= gen_lowpart_or_truncate (result_mode
, x
);
10485 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10488 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10490 if (outer_op
!= UNKNOWN
)
10492 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10493 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10494 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10496 if (outer_op
== AND
)
10497 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10498 else if (outer_op
== SET
)
10500 /* This means that we have determined that the result is
10501 equivalent to a constant. This should be rare. */
10502 if (!side_effects_p (x
))
10503 x
= GEN_INT (outer_const
);
10505 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10506 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10508 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10509 GEN_INT (outer_const
));
10515 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10516 The result of the shift is RESULT_MODE. If we cannot simplify it,
10517 return X or, if it is NULL, synthesize the expression with
10518 simplify_gen_binary. Otherwise, return a simplified value.
10520 The shift is normally computed in the widest mode we find in VAROP, as
10521 long as it isn't a different number of words than RESULT_MODE. Exceptions
10522 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10525 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10526 rtx varop
, int count
)
10528 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10533 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10534 if (GET_MODE (x
) != result_mode
)
10535 x
= gen_lowpart (result_mode
, x
);
10540 /* Like recog, but we receive the address of a pointer to a new pattern.
10541 We try to match the rtx that the pointer points to.
10542 If that fails, we may try to modify or replace the pattern,
10543 storing the replacement into the same pointer object.
10545 Modifications include deletion or addition of CLOBBERs.
10547 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10548 the CLOBBERs are placed.
10550 The value is the final insn code from the pattern ultimately matched,
10554 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10556 rtx pat
= *pnewpat
;
10557 rtx pat_without_clobbers
;
10558 int insn_code_number
;
10559 int num_clobbers_to_add
= 0;
10561 rtx notes
= NULL_RTX
;
10562 rtx old_notes
, old_pat
;
10565 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10566 we use to indicate that something didn't match. If we find such a
10567 thing, force rejection. */
10568 if (GET_CODE (pat
) == PARALLEL
)
10569 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10570 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10571 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10574 old_pat
= PATTERN (insn
);
10575 old_notes
= REG_NOTES (insn
);
10576 PATTERN (insn
) = pat
;
10577 REG_NOTES (insn
) = NULL_RTX
;
10579 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10580 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10582 if (insn_code_number
< 0)
10583 fputs ("Failed to match this instruction:\n", dump_file
);
10585 fputs ("Successfully matched this instruction:\n", dump_file
);
10586 print_rtl_single (dump_file
, pat
);
10589 /* If it isn't, there is the possibility that we previously had an insn
10590 that clobbered some register as a side effect, but the combined
10591 insn doesn't need to do that. So try once more without the clobbers
10592 unless this represents an ASM insn. */
10594 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10595 && GET_CODE (pat
) == PARALLEL
)
10599 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10600 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10603 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10607 SUBST_INT (XVECLEN (pat
, 0), pos
);
10610 pat
= XVECEXP (pat
, 0, 0);
10612 PATTERN (insn
) = pat
;
10613 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10614 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10616 if (insn_code_number
< 0)
10617 fputs ("Failed to match this instruction:\n", dump_file
);
10619 fputs ("Successfully matched this instruction:\n", dump_file
);
10620 print_rtl_single (dump_file
, pat
);
10624 pat_without_clobbers
= pat
;
10626 PATTERN (insn
) = old_pat
;
10627 REG_NOTES (insn
) = old_notes
;
10629 /* Recognize all noop sets, these will be killed by followup pass. */
10630 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10631 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10633 /* If we had any clobbers to add, make a new pattern than contains
10634 them. Then check to make sure that all of them are dead. */
10635 if (num_clobbers_to_add
)
10637 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10638 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10639 ? (XVECLEN (pat
, 0)
10640 + num_clobbers_to_add
)
10641 : num_clobbers_to_add
+ 1));
10643 if (GET_CODE (pat
) == PARALLEL
)
10644 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10645 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10647 XVECEXP (newpat
, 0, 0) = pat
;
10649 add_clobbers (newpat
, insn_code_number
);
10651 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10652 i
< XVECLEN (newpat
, 0); i
++)
10654 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10655 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10657 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10659 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10660 notes
= alloc_reg_note (REG_UNUSED
,
10661 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10667 if (insn_code_number
>= 0
10668 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10670 old_pat
= PATTERN (insn
);
10671 old_notes
= REG_NOTES (insn
);
10672 old_icode
= INSN_CODE (insn
);
10673 PATTERN (insn
) = pat
;
10674 REG_NOTES (insn
) = notes
;
10676 /* Allow targets to reject combined insn. */
10677 if (!targetm
.legitimate_combined_insn (insn
))
10679 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10680 fputs ("Instruction not appropriate for target.",
10683 /* Callers expect recog_for_combine to strip
10684 clobbers from the pattern on failure. */
10685 pat
= pat_without_clobbers
;
10688 insn_code_number
= -1;
10691 PATTERN (insn
) = old_pat
;
10692 REG_NOTES (insn
) = old_notes
;
10693 INSN_CODE (insn
) = old_icode
;
10699 return insn_code_number
;
10702 /* Like gen_lowpart_general but for use by combine. In combine it
10703 is not possible to create any new pseudoregs. However, it is
10704 safe to create invalid memory addresses, because combine will
10705 try to recognize them and all they will do is make the combine
10708 If for some reason this cannot do its job, an rtx
10709 (clobber (const_int 0)) is returned.
10710 An insn containing that will not be recognized. */
10713 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10715 enum machine_mode imode
= GET_MODE (x
);
10716 unsigned int osize
= GET_MODE_SIZE (omode
);
10717 unsigned int isize
= GET_MODE_SIZE (imode
);
10720 if (omode
== imode
)
10723 /* We can only support MODE being wider than a word if X is a
10724 constant integer or has a mode the same size. */
10725 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10726 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10729 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10730 won't know what to do. So we will strip off the SUBREG here and
10731 process normally. */
10732 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10734 x
= SUBREG_REG (x
);
10736 /* For use in case we fall down into the address adjustments
10737 further below, we need to adjust the known mode and size of
10738 x; imode and isize, since we just adjusted x. */
10739 imode
= GET_MODE (x
);
10741 if (imode
== omode
)
10744 isize
= GET_MODE_SIZE (imode
);
10747 result
= gen_lowpart_common (omode
, x
);
10756 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10758 if (MEM_VOLATILE_P (x
)
10759 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10762 /* If we want to refer to something bigger than the original memref,
10763 generate a paradoxical subreg instead. That will force a reload
10764 of the original memref X. */
10766 return gen_rtx_SUBREG (omode
, x
, 0);
10768 if (WORDS_BIG_ENDIAN
)
10769 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10771 /* Adjust the address so that the address-after-the-data is
10773 if (BYTES_BIG_ENDIAN
)
10774 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10776 return adjust_address_nv (x
, omode
, offset
);
10779 /* If X is a comparison operator, rewrite it in a new mode. This
10780 probably won't match, but may allow further simplifications. */
10781 else if (COMPARISON_P (x
))
10782 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10784 /* If we couldn't simplify X any other way, just enclose it in a
10785 SUBREG. Normally, this SUBREG won't match, but some patterns may
10786 include an explicit SUBREG or we may simplify it further in combine. */
10792 offset
= subreg_lowpart_offset (omode
, imode
);
10793 if (imode
== VOIDmode
)
10795 imode
= int_mode_for_mode (omode
);
10796 x
= gen_lowpart_common (imode
, x
);
10800 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10806 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10809 /* Try to simplify a comparison between OP0 and a constant OP1,
10810 where CODE is the comparison code that will be tested, into a
10811 (CODE OP0 const0_rtx) form.
10813 The result is a possibly different comparison code to use.
10814 *POP1 may be updated. */
10816 static enum rtx_code
10817 simplify_compare_const (enum rtx_code code
, enum machine_mode mode
,
10818 rtx op0
, rtx
*pop1
)
10820 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10821 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10823 /* Get the constant we are comparing against and turn off all bits
10824 not on in our mode. */
10825 if (mode
!= VOIDmode
)
10826 const_op
= trunc_int_for_mode (const_op
, mode
);
10828 /* If we are comparing against a constant power of two and the value
10829 being compared can only have that single bit nonzero (e.g., it was
10830 `and'ed with that bit), we can replace this with a comparison
10833 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10834 || code
== LT
|| code
== LTU
)
10835 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10836 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10837 && (nonzero_bits (op0
, mode
)
10838 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10840 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10844 /* Similarly, if we are comparing a value known to be either -1 or
10845 0 with -1, change it to the opposite comparison against zero. */
10847 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10848 || code
== GEU
|| code
== LTU
)
10849 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10851 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10855 /* Do some canonicalizations based on the comparison code. We prefer
10856 comparisons against zero and then prefer equality comparisons.
10857 If we can reduce the size of a constant, we will do that too. */
10861 /* < C is equivalent to <= (C - 1) */
10866 /* ... fall through to LE case below. */
10872 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10879 /* If we are doing a <= 0 comparison on a value known to have
10880 a zero sign bit, we can replace this with == 0. */
10881 else if (const_op
== 0
10882 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10883 && (nonzero_bits (op0
, mode
)
10884 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10890 /* >= C is equivalent to > (C - 1). */
10895 /* ... fall through to GT below. */
10901 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10908 /* If we are doing a > 0 comparison on a value known to have
10909 a zero sign bit, we can replace this with != 0. */
10910 else if (const_op
== 0
10911 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10912 && (nonzero_bits (op0
, mode
)
10913 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10919 /* < C is equivalent to <= (C - 1). */
10924 /* ... fall through ... */
10926 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10927 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10928 && (unsigned HOST_WIDE_INT
) const_op
10929 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10939 /* unsigned <= 0 is equivalent to == 0 */
10942 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10943 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10944 && (unsigned HOST_WIDE_INT
) const_op
10945 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10953 /* >= C is equivalent to > (C - 1). */
10958 /* ... fall through ... */
10961 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10962 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10963 && (unsigned HOST_WIDE_INT
) const_op
10964 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10974 /* unsigned > 0 is equivalent to != 0 */
10977 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10978 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10979 && (unsigned HOST_WIDE_INT
) const_op
10980 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10991 *pop1
= GEN_INT (const_op
);
10995 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10996 comparison code that will be tested.
10998 The result is a possibly different comparison code to use. *POP0 and
10999 *POP1 may be updated.
11001 It is possible that we might detect that a comparison is either always
11002 true or always false. However, we do not perform general constant
11003 folding in combine, so this knowledge isn't useful. Such tautologies
11004 should have been detected earlier. Hence we ignore all such cases. */
11006 static enum rtx_code
11007 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11013 enum machine_mode mode
, tmode
;
11015 /* Try a few ways of applying the same transformation to both operands. */
11018 #ifndef WORD_REGISTER_OPERATIONS
11019 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11020 so check specially. */
11021 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11022 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11023 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11024 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11025 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11026 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11027 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11028 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11029 && CONST_INT_P (XEXP (op0
, 1))
11030 && XEXP (op0
, 1) == XEXP (op1
, 1)
11031 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11032 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11033 && (INTVAL (XEXP (op0
, 1))
11034 == (GET_MODE_PRECISION (GET_MODE (op0
))
11035 - (GET_MODE_PRECISION
11036 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11038 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11039 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11043 /* If both operands are the same constant shift, see if we can ignore the
11044 shift. We can if the shift is a rotate or if the bits shifted out of
11045 this shift are known to be zero for both inputs and if the type of
11046 comparison is compatible with the shift. */
11047 if (GET_CODE (op0
) == GET_CODE (op1
)
11048 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11049 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11050 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11051 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11052 || (GET_CODE (op0
) == ASHIFTRT
11053 && (code
!= GTU
&& code
!= LTU
11054 && code
!= GEU
&& code
!= LEU
)))
11055 && CONST_INT_P (XEXP (op0
, 1))
11056 && INTVAL (XEXP (op0
, 1)) >= 0
11057 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11058 && XEXP (op0
, 1) == XEXP (op1
, 1))
11060 enum machine_mode mode
= GET_MODE (op0
);
11061 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11062 int shift_count
= INTVAL (XEXP (op0
, 1));
11064 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11065 mask
&= (mask
>> shift_count
) << shift_count
;
11066 else if (GET_CODE (op0
) == ASHIFT
)
11067 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11069 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11070 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11071 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11076 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11077 SUBREGs are of the same mode, and, in both cases, the AND would
11078 be redundant if the comparison was done in the narrower mode,
11079 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11080 and the operand's possibly nonzero bits are 0xffffff01; in that case
11081 if we only care about QImode, we don't need the AND). This case
11082 occurs if the output mode of an scc insn is not SImode and
11083 STORE_FLAG_VALUE == 1 (e.g., the 386).
11085 Similarly, check for a case where the AND's are ZERO_EXTEND
11086 operations from some narrower mode even though a SUBREG is not
11089 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11090 && CONST_INT_P (XEXP (op0
, 1))
11091 && CONST_INT_P (XEXP (op1
, 1)))
11093 rtx inner_op0
= XEXP (op0
, 0);
11094 rtx inner_op1
= XEXP (op1
, 0);
11095 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11096 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11099 if (paradoxical_subreg_p (inner_op0
)
11100 && GET_CODE (inner_op1
) == SUBREG
11101 && (GET_MODE (SUBREG_REG (inner_op0
))
11102 == GET_MODE (SUBREG_REG (inner_op1
)))
11103 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11104 <= HOST_BITS_PER_WIDE_INT
)
11105 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11106 GET_MODE (SUBREG_REG (inner_op0
)))))
11107 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11108 GET_MODE (SUBREG_REG (inner_op1
))))))
11110 op0
= SUBREG_REG (inner_op0
);
11111 op1
= SUBREG_REG (inner_op1
);
11113 /* The resulting comparison is always unsigned since we masked
11114 off the original sign bit. */
11115 code
= unsigned_condition (code
);
11121 for (tmode
= GET_CLASS_NARROWEST_MODE
11122 (GET_MODE_CLASS (GET_MODE (op0
)));
11123 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11124 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11126 op0
= gen_lowpart (tmode
, inner_op0
);
11127 op1
= gen_lowpart (tmode
, inner_op1
);
11128 code
= unsigned_condition (code
);
11137 /* If both operands are NOT, we can strip off the outer operation
11138 and adjust the comparison code for swapped operands; similarly for
11139 NEG, except that this must be an equality comparison. */
11140 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11141 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11142 && (code
== EQ
|| code
== NE
)))
11143 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11149 /* If the first operand is a constant, swap the operands and adjust the
11150 comparison code appropriately, but don't do this if the second operand
11151 is already a constant integer. */
11152 if (swap_commutative_operands_p (op0
, op1
))
11154 tem
= op0
, op0
= op1
, op1
= tem
;
11155 code
= swap_condition (code
);
11158 /* We now enter a loop during which we will try to simplify the comparison.
11159 For the most part, we only are concerned with comparisons with zero,
11160 but some things may really be comparisons with zero but not start
11161 out looking that way. */
11163 while (CONST_INT_P (op1
))
11165 enum machine_mode mode
= GET_MODE (op0
);
11166 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11167 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11168 int equality_comparison_p
;
11169 int sign_bit_comparison_p
;
11170 int unsigned_comparison_p
;
11171 HOST_WIDE_INT const_op
;
11173 /* We only want to handle integral modes. This catches VOIDmode,
11174 CCmode, and the floating-point modes. An exception is that we
11175 can handle VOIDmode if OP0 is a COMPARE or a comparison
11178 if (GET_MODE_CLASS (mode
) != MODE_INT
11179 && ! (mode
== VOIDmode
11180 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11183 /* Try to simplify the compare to constant, possibly changing the
11184 comparison op, and/or changing op1 to zero. */
11185 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11186 const_op
= INTVAL (op1
);
11188 /* Compute some predicates to simplify code below. */
11190 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11191 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11192 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11195 /* If this is a sign bit comparison and we can do arithmetic in
11196 MODE, say that we will only be needing the sign bit of OP0. */
11197 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11198 op0
= force_to_mode (op0
, mode
,
11199 (unsigned HOST_WIDE_INT
) 1
11200 << (GET_MODE_PRECISION (mode
) - 1),
11203 /* Now try cases based on the opcode of OP0. If none of the cases
11204 does a "continue", we exit this loop immediately after the
11207 switch (GET_CODE (op0
))
11210 /* If we are extracting a single bit from a variable position in
11211 a constant that has only a single bit set and are comparing it
11212 with zero, we can convert this into an equality comparison
11213 between the position and the location of the single bit. */
11214 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11215 have already reduced the shift count modulo the word size. */
11216 if (!SHIFT_COUNT_TRUNCATED
11217 && CONST_INT_P (XEXP (op0
, 0))
11218 && XEXP (op0
, 1) == const1_rtx
11219 && equality_comparison_p
&& const_op
== 0
11220 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11222 if (BITS_BIG_ENDIAN
)
11223 i
= BITS_PER_WORD
- 1 - i
;
11225 op0
= XEXP (op0
, 2);
11229 /* Result is nonzero iff shift count is equal to I. */
11230 code
= reverse_condition (code
);
11234 /* ... fall through ... */
11237 tem
= expand_compound_operation (op0
);
11246 /* If testing for equality, we can take the NOT of the constant. */
11247 if (equality_comparison_p
11248 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11250 op0
= XEXP (op0
, 0);
11255 /* If just looking at the sign bit, reverse the sense of the
11257 if (sign_bit_comparison_p
)
11259 op0
= XEXP (op0
, 0);
11260 code
= (code
== GE
? LT
: GE
);
11266 /* If testing for equality, we can take the NEG of the constant. */
11267 if (equality_comparison_p
11268 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11270 op0
= XEXP (op0
, 0);
11275 /* The remaining cases only apply to comparisons with zero. */
11279 /* When X is ABS or is known positive,
11280 (neg X) is < 0 if and only if X != 0. */
11282 if (sign_bit_comparison_p
11283 && (GET_CODE (XEXP (op0
, 0)) == ABS
11284 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11285 && (nonzero_bits (XEXP (op0
, 0), mode
)
11286 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11289 op0
= XEXP (op0
, 0);
11290 code
= (code
== LT
? NE
: EQ
);
11294 /* If we have NEG of something whose two high-order bits are the
11295 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11296 if (num_sign_bit_copies (op0
, mode
) >= 2)
11298 op0
= XEXP (op0
, 0);
11299 code
= swap_condition (code
);
11305 /* If we are testing equality and our count is a constant, we
11306 can perform the inverse operation on our RHS. */
11307 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11308 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11309 op1
, XEXP (op0
, 1))) != 0)
11311 op0
= XEXP (op0
, 0);
11316 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11317 a particular bit. Convert it to an AND of a constant of that
11318 bit. This will be converted into a ZERO_EXTRACT. */
11319 if (const_op
== 0 && sign_bit_comparison_p
11320 && CONST_INT_P (XEXP (op0
, 1))
11321 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11323 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11324 ((unsigned HOST_WIDE_INT
) 1
11326 - INTVAL (XEXP (op0
, 1)))));
11327 code
= (code
== LT
? NE
: EQ
);
11331 /* Fall through. */
11334 /* ABS is ignorable inside an equality comparison with zero. */
11335 if (const_op
== 0 && equality_comparison_p
)
11337 op0
= XEXP (op0
, 0);
11343 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11344 (compare FOO CONST) if CONST fits in FOO's mode and we
11345 are either testing inequality or have an unsigned
11346 comparison with ZERO_EXTEND or a signed comparison with
11347 SIGN_EXTEND. But don't do it if we don't have a compare
11348 insn of the given mode, since we'd have to revert it
11349 later on, and then we wouldn't know whether to sign- or
11351 mode
= GET_MODE (XEXP (op0
, 0));
11352 if (GET_MODE_CLASS (mode
) == MODE_INT
11353 && ! unsigned_comparison_p
11354 && HWI_COMPUTABLE_MODE_P (mode
)
11355 && trunc_int_for_mode (const_op
, mode
) == const_op
11356 && have_insn_for (COMPARE
, mode
))
11358 op0
= XEXP (op0
, 0);
11364 /* Check for the case where we are comparing A - C1 with C2, that is
11366 (subreg:MODE (plus (A) (-C1))) op (C2)
11368 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11369 comparison in the wider mode. One of the following two conditions
11370 must be true in order for this to be valid:
11372 1. The mode extension results in the same bit pattern being added
11373 on both sides and the comparison is equality or unsigned. As
11374 C2 has been truncated to fit in MODE, the pattern can only be
11377 2. The mode extension results in the sign bit being copied on
11380 The difficulty here is that we have predicates for A but not for
11381 (A - C1) so we need to check that C1 is within proper bounds so
11382 as to perturbate A as little as possible. */
11384 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11385 && subreg_lowpart_p (op0
)
11386 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11387 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11388 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11390 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11391 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11392 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11395 && (unsigned HOST_WIDE_INT
) c1
11396 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11397 && (equality_comparison_p
|| unsigned_comparison_p
)
11398 /* (A - C1) zero-extends if it is positive and sign-extends
11399 if it is negative, C2 both zero- and sign-extends. */
11400 && ((0 == (nonzero_bits (a
, inner_mode
)
11401 & ~GET_MODE_MASK (mode
))
11403 /* (A - C1) sign-extends if it is positive and 1-extends
11404 if it is negative, C2 both sign- and 1-extends. */
11405 || (num_sign_bit_copies (a
, inner_mode
)
11406 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11409 || ((unsigned HOST_WIDE_INT
) c1
11410 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11411 /* (A - C1) always sign-extends, like C2. */
11412 && num_sign_bit_copies (a
, inner_mode
)
11413 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11414 - (mode_width
- 1))))
11416 op0
= SUBREG_REG (op0
);
11421 /* If the inner mode is narrower and we are extracting the low part,
11422 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11423 if (subreg_lowpart_p (op0
)
11424 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11425 /* Fall through */ ;
11429 /* ... fall through ... */
11432 mode
= GET_MODE (XEXP (op0
, 0));
11433 if (GET_MODE_CLASS (mode
) == MODE_INT
11434 && (unsigned_comparison_p
|| equality_comparison_p
)
11435 && HWI_COMPUTABLE_MODE_P (mode
)
11436 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11438 && have_insn_for (COMPARE
, mode
))
11440 op0
= XEXP (op0
, 0);
11446 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11447 this for equality comparisons due to pathological cases involving
11449 if (equality_comparison_p
11450 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11451 op1
, XEXP (op0
, 1))))
11453 op0
= XEXP (op0
, 0);
11458 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11459 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11460 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11462 op0
= XEXP (XEXP (op0
, 0), 0);
11463 code
= (code
== LT
? EQ
: NE
);
11469 /* We used to optimize signed comparisons against zero, but that
11470 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11471 arrive here as equality comparisons, or (GEU, LTU) are
11472 optimized away. No need to special-case them. */
11474 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11475 (eq B (minus A C)), whichever simplifies. We can only do
11476 this for equality comparisons due to pathological cases involving
11478 if (equality_comparison_p
11479 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11480 XEXP (op0
, 1), op1
)))
11482 op0
= XEXP (op0
, 0);
11487 if (equality_comparison_p
11488 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11489 XEXP (op0
, 0), op1
)))
11491 op0
= XEXP (op0
, 1);
11496 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11497 of bits in X minus 1, is one iff X > 0. */
11498 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11499 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11500 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11501 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11503 op0
= XEXP (op0
, 1);
11504 code
= (code
== GE
? LE
: GT
);
11510 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11511 if C is zero or B is a constant. */
11512 if (equality_comparison_p
11513 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11514 XEXP (op0
, 1), op1
)))
11516 op0
= XEXP (op0
, 0);
11523 case UNEQ
: case LTGT
:
11524 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11525 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11526 case UNORDERED
: case ORDERED
:
11527 /* We can't do anything if OP0 is a condition code value, rather
11528 than an actual data value. */
11530 || CC0_P (XEXP (op0
, 0))
11531 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11534 /* Get the two operands being compared. */
11535 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11536 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11538 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11540 /* Check for the cases where we simply want the result of the
11541 earlier test or the opposite of that result. */
11542 if (code
== NE
|| code
== EQ
11543 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11544 && (code
== LT
|| code
== GE
)))
11546 enum rtx_code new_code
;
11547 if (code
== LT
|| code
== NE
)
11548 new_code
= GET_CODE (op0
);
11550 new_code
= reversed_comparison_code (op0
, NULL
);
11552 if (new_code
!= UNKNOWN
)
11563 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11565 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11566 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11567 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11569 op0
= XEXP (op0
, 1);
11570 code
= (code
== GE
? GT
: LE
);
11576 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11577 will be converted to a ZERO_EXTRACT later. */
11578 if (const_op
== 0 && equality_comparison_p
11579 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11580 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11582 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11583 XEXP (XEXP (op0
, 0), 1));
11584 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11588 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11589 zero and X is a comparison and C1 and C2 describe only bits set
11590 in STORE_FLAG_VALUE, we can compare with X. */
11591 if (const_op
== 0 && equality_comparison_p
11592 && mode_width
<= HOST_BITS_PER_WIDE_INT
11593 && CONST_INT_P (XEXP (op0
, 1))
11594 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11595 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11596 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11597 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11599 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11600 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11601 if ((~STORE_FLAG_VALUE
& mask
) == 0
11602 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11603 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11604 && COMPARISON_P (tem
))))
11606 op0
= XEXP (XEXP (op0
, 0), 0);
11611 /* If we are doing an equality comparison of an AND of a bit equal
11612 to the sign bit, replace this with a LT or GE comparison of
11613 the underlying value. */
11614 if (equality_comparison_p
11616 && CONST_INT_P (XEXP (op0
, 1))
11617 && mode_width
<= HOST_BITS_PER_WIDE_INT
11618 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11619 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11621 op0
= XEXP (op0
, 0);
11622 code
= (code
== EQ
? GE
: LT
);
11626 /* If this AND operation is really a ZERO_EXTEND from a narrower
11627 mode, the constant fits within that mode, and this is either an
11628 equality or unsigned comparison, try to do this comparison in
11633 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11634 -> (ne:DI (reg:SI 4) (const_int 0))
11636 unless TRULY_NOOP_TRUNCATION allows it or the register is
11637 known to hold a value of the required mode the
11638 transformation is invalid. */
11639 if ((equality_comparison_p
|| unsigned_comparison_p
)
11640 && CONST_INT_P (XEXP (op0
, 1))
11641 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11642 & GET_MODE_MASK (mode
))
11644 && const_op
>> i
== 0
11645 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11646 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11647 || (REG_P (XEXP (op0
, 0))
11648 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11650 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11654 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11655 fits in both M1 and M2 and the SUBREG is either paradoxical
11656 or represents the low part, permute the SUBREG and the AND
11658 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11660 unsigned HOST_WIDE_INT c1
;
11661 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11662 /* Require an integral mode, to avoid creating something like
11664 if (SCALAR_INT_MODE_P (tmode
)
11665 /* It is unsafe to commute the AND into the SUBREG if the
11666 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11667 not defined. As originally written the upper bits
11668 have a defined value due to the AND operation.
11669 However, if we commute the AND inside the SUBREG then
11670 they no longer have defined values and the meaning of
11671 the code has been changed. */
11673 #ifdef WORD_REGISTER_OPERATIONS
11674 || (mode_width
> GET_MODE_PRECISION (tmode
)
11675 && mode_width
<= BITS_PER_WORD
)
11677 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11678 && subreg_lowpart_p (XEXP (op0
, 0))))
11679 && CONST_INT_P (XEXP (op0
, 1))
11680 && mode_width
<= HOST_BITS_PER_WIDE_INT
11681 && HWI_COMPUTABLE_MODE_P (tmode
)
11682 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11683 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11685 && c1
!= GET_MODE_MASK (tmode
))
11687 op0
= simplify_gen_binary (AND
, tmode
,
11688 SUBREG_REG (XEXP (op0
, 0)),
11689 gen_int_mode (c1
, tmode
));
11690 op0
= gen_lowpart (mode
, op0
);
11695 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11696 if (const_op
== 0 && equality_comparison_p
11697 && XEXP (op0
, 1) == const1_rtx
11698 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11700 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11701 XEXP (XEXP (op0
, 0), 0), 1);
11702 code
= (code
== NE
? EQ
: NE
);
11706 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11707 (eq (and (lshiftrt X) 1) 0).
11708 Also handle the case where (not X) is expressed using xor. */
11709 if (const_op
== 0 && equality_comparison_p
11710 && XEXP (op0
, 1) == const1_rtx
11711 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11713 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11714 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11716 if (GET_CODE (shift_op
) == NOT
11717 || (GET_CODE (shift_op
) == XOR
11718 && CONST_INT_P (XEXP (shift_op
, 1))
11719 && CONST_INT_P (shift_count
)
11720 && HWI_COMPUTABLE_MODE_P (mode
)
11721 && (UINTVAL (XEXP (shift_op
, 1))
11722 == (unsigned HOST_WIDE_INT
) 1
11723 << INTVAL (shift_count
))))
11726 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11727 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11728 code
= (code
== NE
? EQ
: NE
);
11735 /* If we have (compare (ashift FOO N) (const_int C)) and
11736 the high order N bits of FOO (N+1 if an inequality comparison)
11737 are known to be zero, we can do this by comparing FOO with C
11738 shifted right N bits so long as the low-order N bits of C are
11740 if (CONST_INT_P (XEXP (op0
, 1))
11741 && INTVAL (XEXP (op0
, 1)) >= 0
11742 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11743 < HOST_BITS_PER_WIDE_INT
)
11744 && (((unsigned HOST_WIDE_INT
) const_op
11745 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11747 && mode_width
<= HOST_BITS_PER_WIDE_INT
11748 && (nonzero_bits (XEXP (op0
, 0), mode
)
11749 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11750 + ! equality_comparison_p
))) == 0)
11752 /* We must perform a logical shift, not an arithmetic one,
11753 as we want the top N bits of C to be zero. */
11754 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11756 temp
>>= INTVAL (XEXP (op0
, 1));
11757 op1
= gen_int_mode (temp
, mode
);
11758 op0
= XEXP (op0
, 0);
11762 /* If we are doing a sign bit comparison, it means we are testing
11763 a particular bit. Convert it to the appropriate AND. */
11764 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11765 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11767 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11768 ((unsigned HOST_WIDE_INT
) 1
11770 - INTVAL (XEXP (op0
, 1)))));
11771 code
= (code
== LT
? NE
: EQ
);
11775 /* If this an equality comparison with zero and we are shifting
11776 the low bit to the sign bit, we can convert this to an AND of the
11778 if (const_op
== 0 && equality_comparison_p
11779 && CONST_INT_P (XEXP (op0
, 1))
11780 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11782 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11788 /* If this is an equality comparison with zero, we can do this
11789 as a logical shift, which might be much simpler. */
11790 if (equality_comparison_p
&& const_op
== 0
11791 && CONST_INT_P (XEXP (op0
, 1)))
11793 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11795 INTVAL (XEXP (op0
, 1)));
11799 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11800 do the comparison in a narrower mode. */
11801 if (! unsigned_comparison_p
11802 && CONST_INT_P (XEXP (op0
, 1))
11803 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11804 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11805 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11806 MODE_INT
, 1)) != BLKmode
11807 && (((unsigned HOST_WIDE_INT
) const_op
11808 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11809 <= GET_MODE_MASK (tmode
)))
11811 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11815 /* Likewise if OP0 is a PLUS of a sign extension with a
11816 constant, which is usually represented with the PLUS
11817 between the shifts. */
11818 if (! unsigned_comparison_p
11819 && CONST_INT_P (XEXP (op0
, 1))
11820 && GET_CODE (XEXP (op0
, 0)) == PLUS
11821 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11822 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11823 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11824 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11825 MODE_INT
, 1)) != BLKmode
11826 && (((unsigned HOST_WIDE_INT
) const_op
11827 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11828 <= GET_MODE_MASK (tmode
)))
11830 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11831 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11832 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11833 add_const
, XEXP (op0
, 1));
11835 op0
= simplify_gen_binary (PLUS
, tmode
,
11836 gen_lowpart (tmode
, inner
),
11841 /* ... fall through ... */
11843 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11844 the low order N bits of FOO are known to be zero, we can do this
11845 by comparing FOO with C shifted left N bits so long as no
11846 overflow occurs. Even if the low order N bits of FOO aren't known
11847 to be zero, if the comparison is >= or < we can use the same
11848 optimization and for > or <= by setting all the low
11849 order N bits in the comparison constant. */
11850 if (CONST_INT_P (XEXP (op0
, 1))
11851 && INTVAL (XEXP (op0
, 1)) > 0
11852 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11853 && mode_width
<= HOST_BITS_PER_WIDE_INT
11854 && (((unsigned HOST_WIDE_INT
) const_op
11855 + (GET_CODE (op0
) != LSHIFTRT
11856 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11859 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11861 unsigned HOST_WIDE_INT low_bits
11862 = (nonzero_bits (XEXP (op0
, 0), mode
)
11863 & (((unsigned HOST_WIDE_INT
) 1
11864 << INTVAL (XEXP (op0
, 1))) - 1));
11865 if (low_bits
== 0 || !equality_comparison_p
)
11867 /* If the shift was logical, then we must make the condition
11869 if (GET_CODE (op0
) == LSHIFTRT
)
11870 code
= unsigned_condition (code
);
11872 const_op
<<= INTVAL (XEXP (op0
, 1));
11874 && (code
== GT
|| code
== GTU
11875 || code
== LE
|| code
== LEU
))
11877 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11878 op1
= GEN_INT (const_op
);
11879 op0
= XEXP (op0
, 0);
11884 /* If we are using this shift to extract just the sign bit, we
11885 can replace this with an LT or GE comparison. */
11887 && (equality_comparison_p
|| sign_bit_comparison_p
)
11888 && CONST_INT_P (XEXP (op0
, 1))
11889 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11891 op0
= XEXP (op0
, 0);
11892 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11904 /* Now make any compound operations involved in this comparison. Then,
11905 check for an outmost SUBREG on OP0 that is not doing anything or is
11906 paradoxical. The latter transformation must only be performed when
11907 it is known that the "extra" bits will be the same in op0 and op1 or
11908 that they don't matter. There are three cases to consider:
11910 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11911 care bits and we can assume they have any convenient value. So
11912 making the transformation is safe.
11914 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11915 In this case the upper bits of op0 are undefined. We should not make
11916 the simplification in that case as we do not know the contents of
11919 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11920 UNKNOWN. In that case we know those bits are zeros or ones. We must
11921 also be sure that they are the same as the upper bits of op1.
11923 We can never remove a SUBREG for a non-equality comparison because
11924 the sign bit is in a different place in the underlying object. */
11926 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11927 op1
= make_compound_operation (op1
, SET
);
11929 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11930 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11931 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11932 && (code
== NE
|| code
== EQ
))
11934 if (paradoxical_subreg_p (op0
))
11936 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11938 if (REG_P (SUBREG_REG (op0
)))
11940 op0
= SUBREG_REG (op0
);
11941 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11944 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11945 <= HOST_BITS_PER_WIDE_INT
)
11946 && (nonzero_bits (SUBREG_REG (op0
),
11947 GET_MODE (SUBREG_REG (op0
)))
11948 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11950 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11952 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11953 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11954 op0
= SUBREG_REG (op0
), op1
= tem
;
11958 /* We now do the opposite procedure: Some machines don't have compare
11959 insns in all modes. If OP0's mode is an integer mode smaller than a
11960 word and we can't do a compare in that mode, see if there is a larger
11961 mode for which we can do the compare. There are a number of cases in
11962 which we can use the wider mode. */
11964 mode
= GET_MODE (op0
);
11965 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11966 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11967 && ! have_insn_for (COMPARE
, mode
))
11968 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11969 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11970 tmode
= GET_MODE_WIDER_MODE (tmode
))
11971 if (have_insn_for (COMPARE
, tmode
))
11975 /* If this is a test for negative, we can make an explicit
11976 test of the sign bit. Test this first so we can use
11977 a paradoxical subreg to extend OP0. */
11979 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11980 && HWI_COMPUTABLE_MODE_P (mode
))
11982 unsigned HOST_WIDE_INT sign
11983 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
11984 op0
= simplify_gen_binary (AND
, tmode
,
11985 gen_lowpart (tmode
, op0
),
11986 gen_int_mode (sign
, mode
));
11987 code
= (code
== LT
) ? NE
: EQ
;
11991 /* If the only nonzero bits in OP0 and OP1 are those in the
11992 narrower mode and this is an equality or unsigned comparison,
11993 we can use the wider mode. Similarly for sign-extended
11994 values, in which case it is true for all comparisons. */
11995 zero_extended
= ((code
== EQ
|| code
== NE
11996 || code
== GEU
|| code
== GTU
11997 || code
== LEU
|| code
== LTU
)
11998 && (nonzero_bits (op0
, tmode
)
11999 & ~GET_MODE_MASK (mode
)) == 0
12000 && ((CONST_INT_P (op1
)
12001 || (nonzero_bits (op1
, tmode
)
12002 & ~GET_MODE_MASK (mode
)) == 0)));
12005 || ((num_sign_bit_copies (op0
, tmode
)
12006 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12007 - GET_MODE_PRECISION (mode
)))
12008 && (num_sign_bit_copies (op1
, tmode
)
12009 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12010 - GET_MODE_PRECISION (mode
)))))
12012 /* If OP0 is an AND and we don't have an AND in MODE either,
12013 make a new AND in the proper mode. */
12014 if (GET_CODE (op0
) == AND
12015 && !have_insn_for (AND
, mode
))
12016 op0
= simplify_gen_binary (AND
, tmode
,
12017 gen_lowpart (tmode
,
12019 gen_lowpart (tmode
,
12025 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12026 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12030 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12031 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12038 /* We may have changed the comparison operands. Re-canonicalize. */
12039 if (swap_commutative_operands_p (op0
, op1
))
12041 tem
= op0
, op0
= op1
, op1
= tem
;
12042 code
= swap_condition (code
);
12045 /* If this machine only supports a subset of valid comparisons, see if we
12046 can convert an unsupported one into a supported one. */
12047 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12055 /* Utility function for record_value_for_reg. Count number of
12060 enum rtx_code code
= GET_CODE (x
);
12064 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12065 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12067 rtx x0
= XEXP (x
, 0);
12068 rtx x1
= XEXP (x
, 1);
12071 return 1 + 2 * count_rtxs (x0
);
12073 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12074 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12075 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12076 return 2 + 2 * count_rtxs (x0
)
12077 + count_rtxs (x
== XEXP (x1
, 0)
12078 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12080 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12081 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12082 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12083 return 2 + 2 * count_rtxs (x1
)
12084 + count_rtxs (x
== XEXP (x0
, 0)
12085 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12088 fmt
= GET_RTX_FORMAT (code
);
12089 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12091 ret
+= count_rtxs (XEXP (x
, i
));
12092 else if (fmt
[i
] == 'E')
12093 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12094 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12099 /* Utility function for following routine. Called when X is part of a value
12100 being stored into last_set_value. Sets last_set_table_tick
12101 for each register mentioned. Similar to mention_regs in cse.c */
12104 update_table_tick (rtx x
)
12106 enum rtx_code code
= GET_CODE (x
);
12107 const char *fmt
= GET_RTX_FORMAT (code
);
12112 unsigned int regno
= REGNO (x
);
12113 unsigned int endregno
= END_REGNO (x
);
12116 for (r
= regno
; r
< endregno
; r
++)
12118 reg_stat_type
*rsp
= ®_stat
[r
];
12119 rsp
->last_set_table_tick
= label_tick
;
12125 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12128 /* Check for identical subexpressions. If x contains
12129 identical subexpression we only have to traverse one of
12131 if (i
== 0 && ARITHMETIC_P (x
))
12133 /* Note that at this point x1 has already been
12135 rtx x0
= XEXP (x
, 0);
12136 rtx x1
= XEXP (x
, 1);
12138 /* If x0 and x1 are identical then there is no need to
12143 /* If x0 is identical to a subexpression of x1 then while
12144 processing x1, x0 has already been processed. Thus we
12145 are done with x. */
12146 if (ARITHMETIC_P (x1
)
12147 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12150 /* If x1 is identical to a subexpression of x0 then we
12151 still have to process the rest of x0. */
12152 if (ARITHMETIC_P (x0
)
12153 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12155 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12160 update_table_tick (XEXP (x
, i
));
12162 else if (fmt
[i
] == 'E')
12163 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12164 update_table_tick (XVECEXP (x
, i
, j
));
12167 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12168 are saying that the register is clobbered and we no longer know its
12169 value. If INSN is zero, don't update reg_stat[].last_set; this is
12170 only permitted with VALUE also zero and is used to invalidate the
12174 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12176 unsigned int regno
= REGNO (reg
);
12177 unsigned int endregno
= END_REGNO (reg
);
12179 reg_stat_type
*rsp
;
12181 /* If VALUE contains REG and we have a previous value for REG, substitute
12182 the previous value. */
12183 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12187 /* Set things up so get_last_value is allowed to see anything set up to
12189 subst_low_luid
= DF_INSN_LUID (insn
);
12190 tem
= get_last_value (reg
);
12192 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12193 it isn't going to be useful and will take a lot of time to process,
12194 so just use the CLOBBER. */
12198 if (ARITHMETIC_P (tem
)
12199 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12200 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12201 tem
= XEXP (tem
, 0);
12202 else if (count_occurrences (value
, reg
, 1) >= 2)
12204 /* If there are two or more occurrences of REG in VALUE,
12205 prevent the value from growing too much. */
12206 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12207 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12210 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12214 /* For each register modified, show we don't know its value, that
12215 we don't know about its bitwise content, that its value has been
12216 updated, and that we don't know the location of the death of the
12218 for (i
= regno
; i
< endregno
; i
++)
12220 rsp
= ®_stat
[i
];
12223 rsp
->last_set
= insn
;
12225 rsp
->last_set_value
= 0;
12226 rsp
->last_set_mode
= VOIDmode
;
12227 rsp
->last_set_nonzero_bits
= 0;
12228 rsp
->last_set_sign_bit_copies
= 0;
12229 rsp
->last_death
= 0;
12230 rsp
->truncated_to_mode
= VOIDmode
;
12233 /* Mark registers that are being referenced in this value. */
12235 update_table_tick (value
);
12237 /* Now update the status of each register being set.
12238 If someone is using this register in this block, set this register
12239 to invalid since we will get confused between the two lives in this
12240 basic block. This makes using this register always invalid. In cse, we
12241 scan the table to invalidate all entries using this register, but this
12242 is too much work for us. */
12244 for (i
= regno
; i
< endregno
; i
++)
12246 rsp
= ®_stat
[i
];
12247 rsp
->last_set_label
= label_tick
;
12249 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12250 rsp
->last_set_invalid
= 1;
12252 rsp
->last_set_invalid
= 0;
12255 /* The value being assigned might refer to X (like in "x++;"). In that
12256 case, we must replace it with (clobber (const_int 0)) to prevent
12258 rsp
= ®_stat
[regno
];
12259 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12261 value
= copy_rtx (value
);
12262 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12266 /* For the main register being modified, update the value, the mode, the
12267 nonzero bits, and the number of sign bit copies. */
12269 rsp
->last_set_value
= value
;
12273 enum machine_mode mode
= GET_MODE (reg
);
12274 subst_low_luid
= DF_INSN_LUID (insn
);
12275 rsp
->last_set_mode
= mode
;
12276 if (GET_MODE_CLASS (mode
) == MODE_INT
12277 && HWI_COMPUTABLE_MODE_P (mode
))
12278 mode
= nonzero_bits_mode
;
12279 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12280 rsp
->last_set_sign_bit_copies
12281 = num_sign_bit_copies (value
, GET_MODE (reg
));
12285 /* Called via note_stores from record_dead_and_set_regs to handle one
12286 SET or CLOBBER in an insn. DATA is the instruction in which the
12287 set is occurring. */
12290 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12292 rtx record_dead_insn
= (rtx
) data
;
12294 if (GET_CODE (dest
) == SUBREG
)
12295 dest
= SUBREG_REG (dest
);
12297 if (!record_dead_insn
)
12300 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12306 /* If we are setting the whole register, we know its value. Otherwise
12307 show that we don't know the value. We can handle SUBREG in
12309 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12310 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12311 else if (GET_CODE (setter
) == SET
12312 && GET_CODE (SET_DEST (setter
)) == SUBREG
12313 && SUBREG_REG (SET_DEST (setter
)) == dest
12314 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12315 && subreg_lowpart_p (SET_DEST (setter
)))
12316 record_value_for_reg (dest
, record_dead_insn
,
12317 gen_lowpart (GET_MODE (dest
),
12318 SET_SRC (setter
)));
12320 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12322 else if (MEM_P (dest
)
12323 /* Ignore pushes, they clobber nothing. */
12324 && ! push_operand (dest
, GET_MODE (dest
)))
12325 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12328 /* Update the records of when each REG was most recently set or killed
12329 for the things done by INSN. This is the last thing done in processing
12330 INSN in the combiner loop.
12332 We update reg_stat[], in particular fields last_set, last_set_value,
12333 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12334 last_death, and also the similar information mem_last_set (which insn
12335 most recently modified memory) and last_call_luid (which insn was the
12336 most recent subroutine call). */
12339 record_dead_and_set_regs (rtx insn
)
12344 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12346 if (REG_NOTE_KIND (link
) == REG_DEAD
12347 && REG_P (XEXP (link
, 0)))
12349 unsigned int regno
= REGNO (XEXP (link
, 0));
12350 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12352 for (i
= regno
; i
< endregno
; i
++)
12354 reg_stat_type
*rsp
;
12356 rsp
= ®_stat
[i
];
12357 rsp
->last_death
= insn
;
12360 else if (REG_NOTE_KIND (link
) == REG_INC
)
12361 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12366 hard_reg_set_iterator hrsi
;
12367 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12369 reg_stat_type
*rsp
;
12371 rsp
= ®_stat
[i
];
12372 rsp
->last_set_invalid
= 1;
12373 rsp
->last_set
= insn
;
12374 rsp
->last_set_value
= 0;
12375 rsp
->last_set_mode
= VOIDmode
;
12376 rsp
->last_set_nonzero_bits
= 0;
12377 rsp
->last_set_sign_bit_copies
= 0;
12378 rsp
->last_death
= 0;
12379 rsp
->truncated_to_mode
= VOIDmode
;
12382 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12384 /* We can't combine into a call pattern. Remember, though, that
12385 the return value register is set at this LUID. We could
12386 still replace a register with the return value from the
12387 wrong subroutine call! */
12388 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12391 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12394 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12395 register present in the SUBREG, so for each such SUBREG go back and
12396 adjust nonzero and sign bit information of the registers that are
12397 known to have some zero/sign bits set.
12399 This is needed because when combine blows the SUBREGs away, the
12400 information on zero/sign bits is lost and further combines can be
12401 missed because of that. */
12404 record_promoted_value (rtx insn
, rtx subreg
)
12406 struct insn_link
*links
;
12408 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12409 enum machine_mode mode
= GET_MODE (subreg
);
12411 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12414 for (links
= LOG_LINKS (insn
); links
;)
12416 reg_stat_type
*rsp
;
12418 insn
= links
->insn
;
12419 set
= single_set (insn
);
12421 if (! set
|| !REG_P (SET_DEST (set
))
12422 || REGNO (SET_DEST (set
)) != regno
12423 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12425 links
= links
->next
;
12429 rsp
= ®_stat
[regno
];
12430 if (rsp
->last_set
== insn
)
12432 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12433 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12436 if (REG_P (SET_SRC (set
)))
12438 regno
= REGNO (SET_SRC (set
));
12439 links
= LOG_LINKS (insn
);
12446 /* Check if X, a register, is known to contain a value already
12447 truncated to MODE. In this case we can use a subreg to refer to
12448 the truncated value even though in the generic case we would need
12449 an explicit truncation. */
12452 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12454 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12455 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12458 || rsp
->truncation_label
< label_tick_ebb_start
)
12460 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12462 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12467 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12468 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12469 might be able to turn a truncate into a subreg using this information.
12470 Return -1 if traversing *P is complete or 0 otherwise. */
12473 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12476 enum machine_mode truncated_mode
;
12477 reg_stat_type
*rsp
;
12479 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12481 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12482 truncated_mode
= GET_MODE (x
);
12484 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12487 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12490 x
= SUBREG_REG (x
);
12492 /* ??? For hard-regs we now record everything. We might be able to
12493 optimize this using last_set_mode. */
12494 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12495 truncated_mode
= GET_MODE (x
);
12499 rsp
= ®_stat
[REGNO (x
)];
12500 if (rsp
->truncated_to_mode
== 0
12501 || rsp
->truncation_label
< label_tick_ebb_start
12502 || (GET_MODE_SIZE (truncated_mode
)
12503 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12505 rsp
->truncated_to_mode
= truncated_mode
;
12506 rsp
->truncation_label
= label_tick
;
12512 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12513 the modes they are used in. This can help truning TRUNCATEs into
12517 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12519 for_each_rtx (x
, record_truncated_value
, NULL
);
12522 /* Scan X for promoted SUBREGs. For each one found,
12523 note what it implies to the registers used in it. */
12526 check_promoted_subreg (rtx insn
, rtx x
)
12528 if (GET_CODE (x
) == SUBREG
12529 && SUBREG_PROMOTED_VAR_P (x
)
12530 && REG_P (SUBREG_REG (x
)))
12531 record_promoted_value (insn
, x
);
12534 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12537 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12541 check_promoted_subreg (insn
, XEXP (x
, i
));
12545 if (XVEC (x
, i
) != 0)
12546 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12547 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12553 /* Verify that all the registers and memory references mentioned in *LOC are
12554 still valid. *LOC was part of a value set in INSN when label_tick was
12555 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12556 the invalid references with (clobber (const_int 0)) and return 1. This
12557 replacement is useful because we often can get useful information about
12558 the form of a value (e.g., if it was produced by a shift that always
12559 produces -1 or 0) even though we don't know exactly what registers it
12560 was produced from. */
12563 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12566 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12567 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12572 unsigned int regno
= REGNO (x
);
12573 unsigned int endregno
= END_REGNO (x
);
12576 for (j
= regno
; j
< endregno
; j
++)
12578 reg_stat_type
*rsp
= ®_stat
[j
];
12579 if (rsp
->last_set_invalid
12580 /* If this is a pseudo-register that was only set once and not
12581 live at the beginning of the function, it is always valid. */
12582 || (! (regno
>= FIRST_PSEUDO_REGISTER
12583 && REG_N_SETS (regno
) == 1
12584 && (!REGNO_REG_SET_P
12585 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12587 && rsp
->last_set_label
> tick
))
12590 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12597 /* If this is a memory reference, make sure that there were no stores after
12598 it that might have clobbered the value. We don't have alias info, so we
12599 assume any store invalidates it. Moreover, we only have local UIDs, so
12600 we also assume that there were stores in the intervening basic blocks. */
12601 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12602 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12605 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12609 for (i
= 0; i
< len
; i
++)
12613 /* Check for identical subexpressions. If x contains
12614 identical subexpression we only have to traverse one of
12616 if (i
== 1 && ARITHMETIC_P (x
))
12618 /* Note that at this point x0 has already been checked
12619 and found valid. */
12620 rtx x0
= XEXP (x
, 0);
12621 rtx x1
= XEXP (x
, 1);
12623 /* If x0 and x1 are identical then x is also valid. */
12627 /* If x1 is identical to a subexpression of x0 then
12628 while checking x0, x1 has already been checked. Thus
12629 it is valid and so as x. */
12630 if (ARITHMETIC_P (x0
)
12631 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12634 /* If x0 is identical to a subexpression of x1 then x is
12635 valid iff the rest of x1 is valid. */
12636 if (ARITHMETIC_P (x1
)
12637 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12639 get_last_value_validate (&XEXP (x1
,
12640 x0
== XEXP (x1
, 0) ? 1 : 0),
12641 insn
, tick
, replace
);
12644 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12648 else if (fmt
[i
] == 'E')
12649 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12650 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12651 insn
, tick
, replace
) == 0)
12655 /* If we haven't found a reason for it to be invalid, it is valid. */
12659 /* Get the last value assigned to X, if known. Some registers
12660 in the value may be replaced with (clobber (const_int 0)) if their value
12661 is known longer known reliably. */
12664 get_last_value (const_rtx x
)
12666 unsigned int regno
;
12668 reg_stat_type
*rsp
;
12670 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12671 then convert it to the desired mode. If this is a paradoxical SUBREG,
12672 we cannot predict what values the "extra" bits might have. */
12673 if (GET_CODE (x
) == SUBREG
12674 && subreg_lowpart_p (x
)
12675 && !paradoxical_subreg_p (x
)
12676 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12677 return gen_lowpart (GET_MODE (x
), value
);
12683 rsp
= ®_stat
[regno
];
12684 value
= rsp
->last_set_value
;
12686 /* If we don't have a value, or if it isn't for this basic block and
12687 it's either a hard register, set more than once, or it's a live
12688 at the beginning of the function, return 0.
12690 Because if it's not live at the beginning of the function then the reg
12691 is always set before being used (is never used without being set).
12692 And, if it's set only once, and it's always set before use, then all
12693 uses must have the same last value, even if it's not from this basic
12697 || (rsp
->last_set_label
< label_tick_ebb_start
12698 && (regno
< FIRST_PSEUDO_REGISTER
12699 || REG_N_SETS (regno
) != 1
12701 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12704 /* If the value was set in a later insn than the ones we are processing,
12705 we can't use it even if the register was only set once. */
12706 if (rsp
->last_set_label
== label_tick
12707 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12710 /* If the value has all its registers valid, return it. */
12711 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12714 /* Otherwise, make a copy and replace any invalid register with
12715 (clobber (const_int 0)). If that fails for some reason, return 0. */
12717 value
= copy_rtx (value
);
12718 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12724 /* Return nonzero if expression X refers to a REG or to memory
12725 that is set in an instruction more recent than FROM_LUID. */
12728 use_crosses_set_p (const_rtx x
, int from_luid
)
12732 enum rtx_code code
= GET_CODE (x
);
12736 unsigned int regno
= REGNO (x
);
12737 unsigned endreg
= END_REGNO (x
);
12739 #ifdef PUSH_ROUNDING
12740 /* Don't allow uses of the stack pointer to be moved,
12741 because we don't know whether the move crosses a push insn. */
12742 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12745 for (; regno
< endreg
; regno
++)
12747 reg_stat_type
*rsp
= ®_stat
[regno
];
12749 && rsp
->last_set_label
== label_tick
12750 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12756 if (code
== MEM
&& mem_last_set
> from_luid
)
12759 fmt
= GET_RTX_FORMAT (code
);
12761 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12766 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12767 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12770 else if (fmt
[i
] == 'e'
12771 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12777 /* Define three variables used for communication between the following
12780 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12781 static int reg_dead_flag
;
12783 /* Function called via note_stores from reg_dead_at_p.
12785 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12786 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12789 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12791 unsigned int regno
, endregno
;
12796 regno
= REGNO (dest
);
12797 endregno
= END_REGNO (dest
);
12798 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12799 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12802 /* Return nonzero if REG is known to be dead at INSN.
12804 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12805 referencing REG, it is dead. If we hit a SET referencing REG, it is
12806 live. Otherwise, see if it is live or dead at the start of the basic
12807 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12808 must be assumed to be always live. */
12811 reg_dead_at_p (rtx reg
, rtx insn
)
12816 /* Set variables for reg_dead_at_p_1. */
12817 reg_dead_regno
= REGNO (reg
);
12818 reg_dead_endregno
= END_REGNO (reg
);
12822 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12823 we allow the machine description to decide whether use-and-clobber
12824 patterns are OK. */
12825 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12827 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12828 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12832 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12833 beginning of basic block. */
12834 block
= BLOCK_FOR_INSN (insn
);
12839 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12841 return reg_dead_flag
== 1 ? 1 : 0;
12843 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12847 if (insn
== BB_HEAD (block
))
12850 insn
= PREV_INSN (insn
);
12853 /* Look at live-in sets for the basic block that we were in. */
12854 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12855 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12861 /* Note hard registers in X that are used. */
12864 mark_used_regs_combine (rtx x
)
12866 RTX_CODE code
= GET_CODE (x
);
12867 unsigned int regno
;
12878 case ADDR_DIFF_VEC
:
12881 /* CC0 must die in the insn after it is set, so we don't need to take
12882 special note of it here. */
12888 /* If we are clobbering a MEM, mark any hard registers inside the
12889 address as used. */
12890 if (MEM_P (XEXP (x
, 0)))
12891 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12896 /* A hard reg in a wide mode may really be multiple registers.
12897 If so, mark all of them just like the first. */
12898 if (regno
< FIRST_PSEUDO_REGISTER
)
12900 /* None of this applies to the stack, frame or arg pointers. */
12901 if (regno
== STACK_POINTER_REGNUM
12902 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12903 || regno
== HARD_FRAME_POINTER_REGNUM
12905 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12906 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12908 || regno
== FRAME_POINTER_REGNUM
)
12911 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12917 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12919 rtx testreg
= SET_DEST (x
);
12921 while (GET_CODE (testreg
) == SUBREG
12922 || GET_CODE (testreg
) == ZERO_EXTRACT
12923 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12924 testreg
= XEXP (testreg
, 0);
12926 if (MEM_P (testreg
))
12927 mark_used_regs_combine (XEXP (testreg
, 0));
12929 mark_used_regs_combine (SET_SRC (x
));
12937 /* Recursively scan the operands of this expression. */
12940 const char *fmt
= GET_RTX_FORMAT (code
);
12942 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12945 mark_used_regs_combine (XEXP (x
, i
));
12946 else if (fmt
[i
] == 'E')
12950 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12951 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12957 /* Remove register number REGNO from the dead registers list of INSN.
12959 Return the note used to record the death, if there was one. */
12962 remove_death (unsigned int regno
, rtx insn
)
12964 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12967 remove_note (insn
, note
);
12972 /* For each register (hardware or pseudo) used within expression X, if its
12973 death is in an instruction with luid between FROM_LUID (inclusive) and
12974 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12975 list headed by PNOTES.
12977 That said, don't move registers killed by maybe_kill_insn.
12979 This is done when X is being merged by combination into TO_INSN. These
12980 notes will then be distributed as needed. */
12983 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12988 enum rtx_code code
= GET_CODE (x
);
12992 unsigned int regno
= REGNO (x
);
12993 rtx where_dead
= reg_stat
[regno
].last_death
;
12995 /* Don't move the register if it gets killed in between from and to. */
12996 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12997 && ! reg_referenced_p (x
, maybe_kill_insn
))
13001 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13002 && DF_INSN_LUID (where_dead
) >= from_luid
13003 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13005 rtx note
= remove_death (regno
, where_dead
);
13007 /* It is possible for the call above to return 0. This can occur
13008 when last_death points to I2 or I1 that we combined with.
13009 In that case make a new note.
13011 We must also check for the case where X is a hard register
13012 and NOTE is a death note for a range of hard registers
13013 including X. In that case, we must put REG_DEAD notes for
13014 the remaining registers in place of NOTE. */
13016 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13017 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13018 > GET_MODE_SIZE (GET_MODE (x
))))
13020 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13021 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13022 unsigned int ourend
= END_HARD_REGNO (x
);
13025 for (i
= deadregno
; i
< deadend
; i
++)
13026 if (i
< regno
|| i
>= ourend
)
13027 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13030 /* If we didn't find any note, or if we found a REG_DEAD note that
13031 covers only part of the given reg, and we have a multi-reg hard
13032 register, then to be safe we must check for REG_DEAD notes
13033 for each register other than the first. They could have
13034 their own REG_DEAD notes lying around. */
13035 else if ((note
== 0
13037 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13038 < GET_MODE_SIZE (GET_MODE (x
)))))
13039 && regno
< FIRST_PSEUDO_REGISTER
13040 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13042 unsigned int ourend
= END_HARD_REGNO (x
);
13043 unsigned int i
, offset
;
13047 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13051 for (i
= regno
+ offset
; i
< ourend
; i
++)
13052 move_deaths (regno_reg_rtx
[i
],
13053 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13056 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13058 XEXP (note
, 1) = *pnotes
;
13062 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13068 else if (GET_CODE (x
) == SET
)
13070 rtx dest
= SET_DEST (x
);
13072 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13074 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13075 that accesses one word of a multi-word item, some
13076 piece of everything register in the expression is used by
13077 this insn, so remove any old death. */
13078 /* ??? So why do we test for equality of the sizes? */
13080 if (GET_CODE (dest
) == ZERO_EXTRACT
13081 || GET_CODE (dest
) == STRICT_LOW_PART
13082 || (GET_CODE (dest
) == SUBREG
13083 && (((GET_MODE_SIZE (GET_MODE (dest
))
13084 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13085 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13086 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13088 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13092 /* If this is some other SUBREG, we know it replaces the entire
13093 value, so use that as the destination. */
13094 if (GET_CODE (dest
) == SUBREG
)
13095 dest
= SUBREG_REG (dest
);
13097 /* If this is a MEM, adjust deaths of anything used in the address.
13098 For a REG (the only other possibility), the entire value is
13099 being replaced so the old value is not used in this insn. */
13102 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13107 else if (GET_CODE (x
) == CLOBBER
)
13110 len
= GET_RTX_LENGTH (code
);
13111 fmt
= GET_RTX_FORMAT (code
);
13113 for (i
= 0; i
< len
; i
++)
13118 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13119 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13122 else if (fmt
[i
] == 'e')
13123 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13127 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13128 pattern of an insn. X must be a REG. */
13131 reg_bitfield_target_p (rtx x
, rtx body
)
13135 if (GET_CODE (body
) == SET
)
13137 rtx dest
= SET_DEST (body
);
13139 unsigned int regno
, tregno
, endregno
, endtregno
;
13141 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13142 target
= XEXP (dest
, 0);
13143 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13144 target
= SUBREG_REG (XEXP (dest
, 0));
13148 if (GET_CODE (target
) == SUBREG
)
13149 target
= SUBREG_REG (target
);
13151 if (!REG_P (target
))
13154 tregno
= REGNO (target
), regno
= REGNO (x
);
13155 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13156 return target
== x
;
13158 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13159 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13161 return endregno
> tregno
&& regno
< endtregno
;
13164 else if (GET_CODE (body
) == PARALLEL
)
13165 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13166 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13172 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13173 as appropriate. I3 and I2 are the insns resulting from the combination
13174 insns including FROM (I2 may be zero).
13176 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13177 not need REG_DEAD notes because they are being substituted for. This
13178 saves searching in the most common cases.
13180 Each note in the list is either ignored or placed on some insns, depending
13181 on the type of note. */
13184 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13185 rtx elim_i1
, rtx elim_i0
)
13187 rtx note
, next_note
;
13190 for (note
= notes
; note
; note
= next_note
)
13192 rtx place
= 0, place2
= 0;
13194 next_note
= XEXP (note
, 1);
13195 switch (REG_NOTE_KIND (note
))
13199 /* Doesn't matter much where we put this, as long as it's somewhere.
13200 It is preferable to keep these notes on branches, which is most
13201 likely to be i3. */
13205 case REG_NON_LOCAL_GOTO
:
13210 gcc_assert (i2
&& JUMP_P (i2
));
13215 case REG_EH_REGION
:
13216 /* These notes must remain with the call or trapping instruction. */
13219 else if (i2
&& CALL_P (i2
))
13223 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13224 if (may_trap_p (i3
))
13226 else if (i2
&& may_trap_p (i2
))
13228 /* ??? Otherwise assume we've combined things such that we
13229 can now prove that the instructions can't trap. Drop the
13230 note in this case. */
13234 case REG_ARGS_SIZE
:
13235 /* ??? How to distribute between i3-i1. Assume i3 contains the
13236 entire adjustment. Assert i3 contains at least some adjust. */
13237 if (!noop_move_p (i3
))
13239 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13240 /* fixup_args_size_notes looks at REG_NORETURN note,
13241 so ensure the note is placed there first. */
13245 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13246 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13250 XEXP (n
, 1) = REG_NOTES (i3
);
13251 REG_NOTES (i3
) = n
;
13255 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13256 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13257 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13258 gcc_assert (old_size
!= args_size
13260 && !ACCUMULATE_OUTGOING_ARGS
13261 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13268 case REG_CALL_DECL
:
13269 /* These notes must remain with the call. It should not be
13270 possible for both I2 and I3 to be a call. */
13275 gcc_assert (i2
&& CALL_P (i2
));
13281 /* Any clobbers for i3 may still exist, and so we must process
13282 REG_UNUSED notes from that insn.
13284 Any clobbers from i2 or i1 can only exist if they were added by
13285 recog_for_combine. In that case, recog_for_combine created the
13286 necessary REG_UNUSED notes. Trying to keep any original
13287 REG_UNUSED notes from these insns can cause incorrect output
13288 if it is for the same register as the original i3 dest.
13289 In that case, we will notice that the register is set in i3,
13290 and then add a REG_UNUSED note for the destination of i3, which
13291 is wrong. However, it is possible to have REG_UNUSED notes from
13292 i2 or i1 for register which were both used and clobbered, so
13293 we keep notes from i2 or i1 if they will turn into REG_DEAD
13296 /* If this register is set or clobbered in I3, put the note there
13297 unless there is one already. */
13298 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13300 if (from_insn
!= i3
)
13303 if (! (REG_P (XEXP (note
, 0))
13304 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13305 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13308 /* Otherwise, if this register is used by I3, then this register
13309 now dies here, so we must put a REG_DEAD note here unless there
13311 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13312 && ! (REG_P (XEXP (note
, 0))
13313 ? find_regno_note (i3
, REG_DEAD
,
13314 REGNO (XEXP (note
, 0)))
13315 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13317 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13325 /* These notes say something about results of an insn. We can
13326 only support them if they used to be on I3 in which case they
13327 remain on I3. Otherwise they are ignored.
13329 If the note refers to an expression that is not a constant, we
13330 must also ignore the note since we cannot tell whether the
13331 equivalence is still true. It might be possible to do
13332 slightly better than this (we only have a problem if I2DEST
13333 or I1DEST is present in the expression), but it doesn't
13334 seem worth the trouble. */
13336 if (from_insn
== i3
13337 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13342 /* These notes say something about how a register is used. They must
13343 be present on any use of the register in I2 or I3. */
13344 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13347 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13356 case REG_LABEL_TARGET
:
13357 case REG_LABEL_OPERAND
:
13358 /* This can show up in several ways -- either directly in the
13359 pattern, or hidden off in the constant pool with (or without?)
13360 a REG_EQUAL note. */
13361 /* ??? Ignore the without-reg_equal-note problem for now. */
13362 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13363 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13364 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13365 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13369 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13370 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13371 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13372 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13380 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13381 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13383 if (place
&& JUMP_P (place
)
13384 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13385 && (JUMP_LABEL (place
) == NULL
13386 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13388 rtx label
= JUMP_LABEL (place
);
13391 JUMP_LABEL (place
) = XEXP (note
, 0);
13392 else if (LABEL_P (label
))
13393 LABEL_NUSES (label
)--;
13396 if (place2
&& JUMP_P (place2
)
13397 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13398 && (JUMP_LABEL (place2
) == NULL
13399 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13401 rtx label
= JUMP_LABEL (place2
);
13404 JUMP_LABEL (place2
) = XEXP (note
, 0);
13405 else if (LABEL_P (label
))
13406 LABEL_NUSES (label
)--;
13412 /* This note says something about the value of a register prior
13413 to the execution of an insn. It is too much trouble to see
13414 if the note is still correct in all situations. It is better
13415 to simply delete it. */
13419 /* If we replaced the right hand side of FROM_INSN with a
13420 REG_EQUAL note, the original use of the dying register
13421 will not have been combined into I3 and I2. In such cases,
13422 FROM_INSN is guaranteed to be the first of the combined
13423 instructions, so we simply need to search back before
13424 FROM_INSN for the previous use or set of this register,
13425 then alter the notes there appropriately.
13427 If the register is used as an input in I3, it dies there.
13428 Similarly for I2, if it is nonzero and adjacent to I3.
13430 If the register is not used as an input in either I3 or I2
13431 and it is not one of the registers we were supposed to eliminate,
13432 there are two possibilities. We might have a non-adjacent I2
13433 or we might have somehow eliminated an additional register
13434 from a computation. For example, we might have had A & B where
13435 we discover that B will always be zero. In this case we will
13436 eliminate the reference to A.
13438 In both cases, we must search to see if we can find a previous
13439 use of A and put the death note there. */
13442 && from_insn
== i2mod
13443 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13448 && CALL_P (from_insn
)
13449 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13451 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13453 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13454 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13456 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13458 && reg_overlap_mentioned_p (XEXP (note
, 0),
13460 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13461 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13468 basic_block bb
= this_basic_block
;
13470 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13472 if (!NONDEBUG_INSN_P (tem
))
13474 if (tem
== BB_HEAD (bb
))
13479 /* If the register is being set at TEM, see if that is all
13480 TEM is doing. If so, delete TEM. Otherwise, make this
13481 into a REG_UNUSED note instead. Don't delete sets to
13482 global register vars. */
13483 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13484 || !global_regs
[REGNO (XEXP (note
, 0))])
13485 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13487 rtx set
= single_set (tem
);
13488 rtx inner_dest
= 0;
13490 rtx cc0_setter
= NULL_RTX
;
13494 for (inner_dest
= SET_DEST (set
);
13495 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13496 || GET_CODE (inner_dest
) == SUBREG
13497 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13498 inner_dest
= XEXP (inner_dest
, 0))
13501 /* Verify that it was the set, and not a clobber that
13502 modified the register.
13504 CC0 targets must be careful to maintain setter/user
13505 pairs. If we cannot delete the setter due to side
13506 effects, mark the user with an UNUSED note instead
13509 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13510 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13512 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13513 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13514 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13518 /* Move the notes and links of TEM elsewhere.
13519 This might delete other dead insns recursively.
13520 First set the pattern to something that won't use
13522 rtx old_notes
= REG_NOTES (tem
);
13524 PATTERN (tem
) = pc_rtx
;
13525 REG_NOTES (tem
) = NULL
;
13527 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13528 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13529 distribute_links (LOG_LINKS (tem
));
13531 SET_INSN_DELETED (tem
);
13536 /* Delete the setter too. */
13539 PATTERN (cc0_setter
) = pc_rtx
;
13540 old_notes
= REG_NOTES (cc0_setter
);
13541 REG_NOTES (cc0_setter
) = NULL
;
13543 distribute_notes (old_notes
, cc0_setter
,
13544 cc0_setter
, NULL_RTX
,
13545 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13546 distribute_links (LOG_LINKS (cc0_setter
));
13548 SET_INSN_DELETED (cc0_setter
);
13549 if (cc0_setter
== i2
)
13556 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13558 /* If there isn't already a REG_UNUSED note, put one
13559 here. Do not place a REG_DEAD note, even if
13560 the register is also used here; that would not
13561 match the algorithm used in lifetime analysis
13562 and can cause the consistency check in the
13563 scheduler to fail. */
13564 if (! find_regno_note (tem
, REG_UNUSED
,
13565 REGNO (XEXP (note
, 0))))
13570 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13572 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13576 /* If we are doing a 3->2 combination, and we have a
13577 register which formerly died in i3 and was not used
13578 by i2, which now no longer dies in i3 and is used in
13579 i2 but does not die in i2, and place is between i2
13580 and i3, then we may need to move a link from place to
13582 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13584 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13585 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13587 struct insn_link
*links
= LOG_LINKS (place
);
13588 LOG_LINKS (place
) = NULL
;
13589 distribute_links (links
);
13594 if (tem
== BB_HEAD (bb
))
13600 /* If the register is set or already dead at PLACE, we needn't do
13601 anything with this note if it is still a REG_DEAD note.
13602 We check here if it is set at all, not if is it totally replaced,
13603 which is what `dead_or_set_p' checks, so also check for it being
13606 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13608 unsigned int regno
= REGNO (XEXP (note
, 0));
13609 reg_stat_type
*rsp
= ®_stat
[regno
];
13611 if (dead_or_set_p (place
, XEXP (note
, 0))
13612 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13614 /* Unless the register previously died in PLACE, clear
13615 last_death. [I no longer understand why this is
13617 if (rsp
->last_death
!= place
)
13618 rsp
->last_death
= 0;
13622 rsp
->last_death
= place
;
13624 /* If this is a death note for a hard reg that is occupying
13625 multiple registers, ensure that we are still using all
13626 parts of the object. If we find a piece of the object
13627 that is unused, we must arrange for an appropriate REG_DEAD
13628 note to be added for it. However, we can't just emit a USE
13629 and tag the note to it, since the register might actually
13630 be dead; so we recourse, and the recursive call then finds
13631 the previous insn that used this register. */
13633 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13634 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13636 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13637 bool all_used
= true;
13640 for (i
= regno
; i
< endregno
; i
++)
13641 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13642 && ! find_regno_fusage (place
, USE
, i
))
13643 || dead_or_set_regno_p (place
, i
))
13651 /* Put only REG_DEAD notes for pieces that are
13652 not already dead or set. */
13654 for (i
= regno
; i
< endregno
;
13655 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13657 rtx piece
= regno_reg_rtx
[i
];
13658 basic_block bb
= this_basic_block
;
13660 if (! dead_or_set_p (place
, piece
)
13661 && ! reg_bitfield_target_p (piece
,
13664 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13667 distribute_notes (new_note
, place
, place
,
13668 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13671 else if (! refers_to_regno_p (i
, i
+ 1,
13672 PATTERN (place
), 0)
13673 && ! find_regno_fusage (place
, USE
, i
))
13674 for (tem
= PREV_INSN (place
); ;
13675 tem
= PREV_INSN (tem
))
13677 if (!NONDEBUG_INSN_P (tem
))
13679 if (tem
== BB_HEAD (bb
))
13683 if (dead_or_set_p (tem
, piece
)
13684 || reg_bitfield_target_p (piece
,
13687 add_reg_note (tem
, REG_UNUSED
, piece
);
13700 /* Any other notes should not be present at this point in the
13702 gcc_unreachable ();
13707 XEXP (note
, 1) = REG_NOTES (place
);
13708 REG_NOTES (place
) = note
;
13712 add_shallow_copy_of_reg_note (place2
, note
);
13716 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13717 I3, I2, and I1 to new locations. This is also called to add a link
13718 pointing at I3 when I3's destination is changed. */
13721 distribute_links (struct insn_link
*links
)
13723 struct insn_link
*link
, *next_link
;
13725 for (link
= links
; link
; link
= next_link
)
13731 next_link
= link
->next
;
13733 /* If the insn that this link points to is a NOTE or isn't a single
13734 set, ignore it. In the latter case, it isn't clear what we
13735 can do other than ignore the link, since we can't tell which
13736 register it was for. Such links wouldn't be used by combine
13739 It is not possible for the destination of the target of the link to
13740 have been changed by combine. The only potential of this is if we
13741 replace I3, I2, and I1 by I3 and I2. But in that case the
13742 destination of I2 also remains unchanged. */
13744 if (NOTE_P (link
->insn
)
13745 || (set
= single_set (link
->insn
)) == 0)
13748 reg
= SET_DEST (set
);
13749 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13750 || GET_CODE (reg
) == STRICT_LOW_PART
)
13751 reg
= XEXP (reg
, 0);
13753 /* A LOG_LINK is defined as being placed on the first insn that uses
13754 a register and points to the insn that sets the register. Start
13755 searching at the next insn after the target of the link and stop
13756 when we reach a set of the register or the end of the basic block.
13758 Note that this correctly handles the link that used to point from
13759 I3 to I2. Also note that not much searching is typically done here
13760 since most links don't point very far away. */
13762 for (insn
= NEXT_INSN (link
->insn
);
13763 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13764 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13765 insn
= NEXT_INSN (insn
))
13766 if (DEBUG_INSN_P (insn
))
13768 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13770 if (reg_referenced_p (reg
, PATTERN (insn
)))
13774 else if (CALL_P (insn
)
13775 && find_reg_fusage (insn
, USE
, reg
))
13780 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13783 /* If we found a place to put the link, place it there unless there
13784 is already a link to the same insn as LINK at that point. */
13788 struct insn_link
*link2
;
13790 FOR_EACH_LOG_LINK (link2
, place
)
13791 if (link2
->insn
== link
->insn
)
13796 link
->next
= LOG_LINKS (place
);
13797 LOG_LINKS (place
) = link
;
13799 /* Set added_links_insn to the earliest insn we added a
13801 if (added_links_insn
== 0
13802 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13803 added_links_insn
= place
;
13809 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13810 Check whether the expression pointer to by LOC is a register or
13811 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13812 Otherwise return zero. */
13815 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13820 && (REG_P (x
) || MEM_P (x
))
13821 && ! reg_mentioned_p (x
, (rtx
) expr
))
13826 /* Check for any register or memory mentioned in EQUIV that is not
13827 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13828 of EXPR where some registers may have been replaced by constants. */
13831 unmentioned_reg_p (rtx equiv
, rtx expr
)
13833 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13836 DEBUG_FUNCTION
void
13837 dump_combine_stats (FILE *file
)
13841 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13842 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13846 dump_combine_total_stats (FILE *file
)
13850 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13851 total_attempts
, total_merges
, total_extras
, total_successes
);
13854 /* Try combining insns through substitution. */
13855 static unsigned int
13856 rest_of_handle_combine (void)
13858 int rebuild_jump_labels_after_combine
;
13860 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13861 df_note_add_problem ();
13864 regstat_init_n_sets_and_refs ();
13866 rebuild_jump_labels_after_combine
13867 = combine_instructions (get_insns (), max_reg_num ());
13869 /* Combining insns may have turned an indirect jump into a
13870 direct jump. Rebuild the JUMP_LABEL fields of jumping
13872 if (rebuild_jump_labels_after_combine
)
13874 timevar_push (TV_JUMP
);
13875 rebuild_jump_labels (get_insns ());
13877 timevar_pop (TV_JUMP
);
13880 regstat_free_n_sets_and_refs ();
13886 const pass_data pass_data_combine
=
13888 RTL_PASS
, /* type */
13889 "combine", /* name */
13890 OPTGROUP_NONE
, /* optinfo_flags */
13891 true, /* has_execute */
13892 TV_COMBINE
, /* tv_id */
13893 PROP_cfglayout
, /* properties_required */
13894 0, /* properties_provided */
13895 0, /* properties_destroyed */
13896 0, /* todo_flags_start */
13897 TODO_df_finish
, /* todo_flags_finish */
13900 class pass_combine
: public rtl_opt_pass
13903 pass_combine (gcc::context
*ctxt
)
13904 : rtl_opt_pass (pass_data_combine
, ctxt
)
13907 /* opt_pass methods: */
13908 virtual bool gate (function
*) { return (optimize
> 0); }
13909 virtual unsigned int execute (function
*)
13911 return rest_of_handle_combine ();
13914 }; // class pass_combine
13916 } // anon namespace
13919 make_pass_combine (gcc::context
*ctxt
)
13921 return new pass_combine (ctxt
);