1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
113 /* Classifies an address.
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
124 A signed 16-bit constant address.
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type
{
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
138 MIPS_V2SF_FTYPE_V2SF
,
139 MIPS_V2SF_FTYPE_V2SF_V2SF
,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
,
142 MIPS_V2SF_FTYPE_SF_SF
,
143 MIPS_INT_FTYPE_V2SF_V2SF
,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
,
145 MIPS_INT_FTYPE_SF_SF
,
146 MIPS_INT_FTYPE_DF_DF
,
157 /* Specifies how a builtin function should be converted into rtl. */
158 enum mips_builtin_type
160 /* The builtin corresponds directly to an .md pattern. The return
161 value is mapped to operand 0 and the arguments are mapped to
162 operands 1 and above. */
165 /* The builtin corresponds to a comparison instruction followed by
166 a mips_cond_move_tf_ps pattern. The first two arguments are the
167 values to compare and the second two arguments are the vector
168 operands for the movt.ps or movf.ps instruction (in assembly order). */
172 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
173 of this instruction is the result of the comparison, which has mode
174 CCV2 or CCV4. The function arguments are mapped to operands 1 and
175 above. The function's return value is an SImode boolean that is
176 true under the following conditions:
178 MIPS_BUILTIN_CMP_ANY: one of the registers is true
179 MIPS_BUILTIN_CMP_ALL: all of the registers are true
180 MIPS_BUILTIN_CMP_LOWER: the first register is true
181 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
182 MIPS_BUILTIN_CMP_ANY
,
183 MIPS_BUILTIN_CMP_ALL
,
184 MIPS_BUILTIN_CMP_UPPER
,
185 MIPS_BUILTIN_CMP_LOWER
,
187 /* As above, but the instruction only sets a single $fcc register. */
188 MIPS_BUILTIN_CMP_SINGLE
191 /* A function to save or store a register. The first argument is the
192 register and the second is the stack slot. */
193 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
195 struct mips16_constant
;
196 struct mips_arg_info
;
197 struct mips_address_info
;
198 struct mips_integer_op
;
201 static enum mips_symbol_type
mips_classify_symbol (rtx
);
202 static void mips_split_const (rtx
, rtx
*, HOST_WIDE_INT
*);
203 static bool mips_offset_within_object_p (rtx
, HOST_WIDE_INT
);
204 static bool mips_valid_base_register_p (rtx
, enum machine_mode
, int);
205 static bool mips_symbolic_address_p (enum mips_symbol_type
, enum machine_mode
);
206 static bool mips_classify_address (struct mips_address_info
*, rtx
,
207 enum machine_mode
, int);
208 static int mips_symbol_insns (enum mips_symbol_type
);
209 static bool mips16_unextended_reference_p (enum machine_mode mode
, rtx
, rtx
);
210 static rtx
mips_force_temporary (rtx
, rtx
);
211 static rtx
mips_split_symbol (rtx
, rtx
);
212 static rtx
mips_unspec_offset_high (rtx
, rtx
, rtx
, enum mips_symbol_type
);
213 static rtx
mips_add_offset (rtx
, rtx
, HOST_WIDE_INT
);
214 static unsigned int mips_build_shift (struct mips_integer_op
*, HOST_WIDE_INT
);
215 static unsigned int mips_build_lower (struct mips_integer_op
*,
216 unsigned HOST_WIDE_INT
);
217 static unsigned int mips_build_integer (struct mips_integer_op
*,
218 unsigned HOST_WIDE_INT
);
219 static void mips_move_integer (rtx
, unsigned HOST_WIDE_INT
);
220 static void mips_legitimize_const_move (enum machine_mode
, rtx
, rtx
);
221 static int m16_check_op (rtx
, int, int, int);
222 static bool mips_rtx_costs (rtx
, int, int, int *);
223 static int mips_address_cost (rtx
);
224 static void mips_emit_compare (enum rtx_code
*, rtx
*, rtx
*, bool);
225 static void mips_load_call_address (rtx
, rtx
, int);
226 static bool mips_function_ok_for_sibcall (tree
, tree
);
227 static void mips_block_move_straight (rtx
, rtx
, HOST_WIDE_INT
);
228 static void mips_adjust_block_mem (rtx
, HOST_WIDE_INT
, rtx
*, rtx
*);
229 static void mips_block_move_loop (rtx
, rtx
, HOST_WIDE_INT
);
230 static void mips_arg_info (const CUMULATIVE_ARGS
*, enum machine_mode
,
231 tree
, int, struct mips_arg_info
*);
232 static bool mips_get_unaligned_mem (rtx
*, unsigned int, int, rtx
*, rtx
*);
233 static void mips_set_architecture (const struct mips_cpu_info
*);
234 static void mips_set_tune (const struct mips_cpu_info
*);
235 static struct machine_function
*mips_init_machine_status (void);
236 static void print_operand_reloc (FILE *, rtx
, const char **);
238 static void irix_output_external_libcall (rtx
);
240 static void mips_file_start (void);
241 static void mips_file_end (void);
242 static bool mips_rewrite_small_data_p (rtx
);
243 static int mips_small_data_pattern_1 (rtx
*, void *);
244 static int mips_rewrite_small_data_1 (rtx
*, void *);
245 static bool mips_function_has_gp_insn (void);
246 static unsigned int mips_global_pointer (void);
247 static bool mips_save_reg_p (unsigned int);
248 static void mips_save_restore_reg (enum machine_mode
, int, HOST_WIDE_INT
,
249 mips_save_restore_fn
);
250 static void mips_for_each_saved_reg (HOST_WIDE_INT
, mips_save_restore_fn
);
251 static void mips_output_cplocal (void);
252 static void mips_emit_loadgp (void);
253 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT
);
254 static void mips_set_frame_expr (rtx
);
255 static rtx
mips_frame_set (rtx
, rtx
);
256 static void mips_save_reg (rtx
, rtx
);
257 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT
);
258 static void mips_restore_reg (rtx
, rtx
);
259 static void mips_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
260 HOST_WIDE_INT
, tree
);
261 static int symbolic_expression_p (rtx
);
262 static void mips_select_rtx_section (enum machine_mode
, rtx
,
263 unsigned HOST_WIDE_INT
);
264 static bool mips_in_small_data_p (tree
);
265 static int mips_fpr_return_fields (tree
, tree
*);
266 static bool mips_return_in_msb (tree
);
267 static rtx
mips_return_fpr_pair (enum machine_mode mode
,
268 enum machine_mode mode1
, HOST_WIDE_INT
,
269 enum machine_mode mode2
, HOST_WIDE_INT
);
270 static rtx
mips16_gp_pseudo_reg (void);
271 static void mips16_fp_args (FILE *, int, int);
272 static void build_mips16_function_stub (FILE *);
273 static rtx
dump_constants_1 (enum machine_mode
, rtx
, rtx
);
274 static void dump_constants (struct mips16_constant
*, rtx
);
275 static int mips16_insn_length (rtx
);
276 static int mips16_rewrite_pool_refs (rtx
*, void *);
277 static void mips16_lay_out_constants (void);
278 static void mips_sim_reset (struct mips_sim
*);
279 static void mips_sim_init (struct mips_sim
*, state_t
);
280 static void mips_sim_next_cycle (struct mips_sim
*);
281 static void mips_sim_wait_reg (struct mips_sim
*, rtx
, rtx
);
282 static int mips_sim_wait_regs_2 (rtx
*, void *);
283 static void mips_sim_wait_regs_1 (rtx
*, void *);
284 static void mips_sim_wait_regs (struct mips_sim
*, rtx
);
285 static void mips_sim_wait_units (struct mips_sim
*, rtx
);
286 static void mips_sim_wait_insn (struct mips_sim
*, rtx
);
287 static void mips_sim_record_set (rtx
, rtx
, void *);
288 static void mips_sim_issue_insn (struct mips_sim
*, rtx
);
289 static void mips_sim_issue_nop (struct mips_sim
*);
290 static void mips_sim_finish_insn (struct mips_sim
*, rtx
);
291 static void vr4130_avoid_branch_rt_conflict (rtx
);
292 static void vr4130_align_insns (void);
293 static void mips_avoid_hazard (rtx
, rtx
, int *, rtx
*, rtx
);
294 static void mips_avoid_hazards (void);
295 static void mips_reorg (void);
296 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
297 static bool mips_matching_cpu_name_p (const char *, const char *);
298 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
299 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
300 static bool mips_return_in_memory (tree
, tree
);
301 static bool mips_strict_argument_naming (CUMULATIVE_ARGS
*);
302 static void mips_macc_chains_record (rtx
);
303 static void mips_macc_chains_reorder (rtx
*, int);
304 static void vr4130_true_reg_dependence_p_1 (rtx
, rtx
, void *);
305 static bool vr4130_true_reg_dependence_p (rtx
);
306 static bool vr4130_swap_insns_p (rtx
, rtx
);
307 static void vr4130_reorder (rtx
*, int);
308 static void mips_promote_ready (rtx
*, int, int);
309 static int mips_sched_reorder (FILE *, int, rtx
*, int *, int);
310 static int mips_variable_issue (FILE *, int, rtx
, int);
311 static int mips_adjust_cost (rtx
, rtx
, rtx
, int);
312 static int mips_issue_rate (void);
313 static int mips_multipass_dfa_lookahead (void);
314 static void mips_init_libfuncs (void);
315 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
317 static tree
mips_build_builtin_va_list (void);
318 static tree
mips_gimplify_va_arg_expr (tree
, tree
, tree
*, tree
*);
319 static bool mips_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode mode
,
321 static bool mips_vector_mode_supported_p (enum machine_mode
);
322 static rtx
mips_prepare_builtin_arg (enum insn_code
, unsigned int, tree
*);
323 static rtx
mips_prepare_builtin_target (enum insn_code
, unsigned int, rtx
);
324 static rtx
mips_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
325 static void mips_init_builtins (void);
326 static rtx
mips_expand_builtin_direct (enum insn_code
, rtx
, tree
);
327 static rtx
mips_expand_builtin_movtf (enum mips_builtin_type
,
328 enum insn_code
, rtx
, tree
);
329 static rtx
mips_expand_builtin_compare (enum mips_builtin_type
,
330 enum insn_code
, rtx
, tree
);
332 /* Structure to be filled in by compute_frame_size with register
333 save masks, and offsets for the current function. */
335 struct mips_frame_info
GTY(())
337 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
338 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
339 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
340 HOST_WIDE_INT cprestore_size
; /* # bytes that the .cprestore slot takes up */
341 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
342 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
343 unsigned int mask
; /* mask of saved gp registers */
344 unsigned int fmask
; /* mask of saved fp registers */
345 HOST_WIDE_INT gp_save_offset
; /* offset from vfp to store gp registers */
346 HOST_WIDE_INT fp_save_offset
; /* offset from vfp to store fp registers */
347 HOST_WIDE_INT gp_sp_offset
; /* offset from new sp to store gp registers */
348 HOST_WIDE_INT fp_sp_offset
; /* offset from new sp to store fp registers */
349 bool initialized
; /* true if frame size already calculated */
350 int num_gp
; /* number of gp registers saved */
351 int num_fp
; /* number of fp registers saved */
354 struct machine_function
GTY(()) {
355 /* Pseudo-reg holding the value of $28 in a mips16 function which
356 refers to GP relative global variables. */
357 rtx mips16_gp_pseudo_rtx
;
359 /* Current frame information, calculated by compute_frame_size. */
360 struct mips_frame_info frame
;
362 /* The register to use as the global pointer within this function. */
363 unsigned int global_pointer
;
365 /* True if mips_adjust_insn_length should ignore an instruction's
367 bool ignore_hazard_length_p
;
369 /* True if the whole function is suitable for .set noreorder and
371 bool all_noreorder_p
;
373 /* True if the function is known to have an instruction that needs $gp. */
377 /* Information about a single argument. */
380 /* True if the argument is passed in a floating-point register, or
381 would have been if we hadn't run out of registers. */
384 /* The number of words passed in registers, rounded up. */
385 unsigned int reg_words
;
387 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
388 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
390 unsigned int reg_offset
;
392 /* The number of words that must be passed on the stack, rounded up. */
393 unsigned int stack_words
;
395 /* The offset from the start of the stack overflow area of the argument's
396 first stack word. Only meaningful when STACK_WORDS is nonzero. */
397 unsigned int stack_offset
;
401 /* Information about an address described by mips_address_type.
407 REG is the base register and OFFSET is the constant offset.
410 REG is the register that contains the high part of the address,
411 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
412 is the type of OFFSET's symbol.
415 SYMBOL_TYPE is the type of symbol being referenced. */
417 struct mips_address_info
419 enum mips_address_type type
;
422 enum mips_symbol_type symbol_type
;
426 /* One stage in a constant building sequence. These sequences have
430 A = A CODE[1] VALUE[1]
431 A = A CODE[2] VALUE[2]
434 where A is an accumulator, each CODE[i] is a binary rtl operation
435 and each VALUE[i] is a constant integer. */
436 struct mips_integer_op
{
438 unsigned HOST_WIDE_INT value
;
442 /* The largest number of operations needed to load an integer constant.
443 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
444 When the lowest bit is clear, we can try, but reject a sequence with
445 an extra SLL at the end. */
446 #define MIPS_MAX_INTEGER_OPS 7
449 /* Global variables for machine-dependent things. */
451 /* Threshold for data being put into the small data/bss area, instead
452 of the normal data area. */
453 int mips_section_threshold
= -1;
455 /* Count the number of .file directives, so that .loc is up to date. */
456 int num_source_filenames
= 0;
458 /* Count the number of sdb related labels are generated (to find block
459 start and end boundaries). */
460 int sdb_label_count
= 0;
462 /* Next label # for each statement for Silicon Graphics IRIS systems. */
465 /* Linked list of all externals that are to be emitted when optimizing
466 for the global pointer if they haven't been declared by the end of
467 the program with an appropriate .comm or initialization. */
469 struct extern_list
GTY (())
471 struct extern_list
*next
; /* next external */
472 const char *name
; /* name of the external */
473 int size
; /* size in bytes */
476 static GTY (()) struct extern_list
*extern_head
= 0;
478 /* Name of the file containing the current function. */
479 const char *current_function_file
= "";
481 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
487 /* The next branch instruction is a branch likely, not branch normal. */
488 int mips_branch_likely
;
490 /* The operands passed to the last cmpMM expander. */
493 /* The target cpu for code generation. */
494 enum processor_type mips_arch
;
495 const struct mips_cpu_info
*mips_arch_info
;
497 /* The target cpu for optimization and scheduling. */
498 enum processor_type mips_tune
;
499 const struct mips_cpu_info
*mips_tune_info
;
501 /* Which instruction set architecture to use. */
504 /* Which ABI to use. */
507 /* Strings to hold which cpu and instruction set architecture to use. */
508 const char *mips_arch_string
; /* for -march=<xxx> */
509 const char *mips_tune_string
; /* for -mtune=<xxx> */
510 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
511 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
513 /* Whether we are generating mips16 hard float code. In mips16 mode
514 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
515 -msoft-float was not specified by the user, which means that we
516 should arrange to call mips32 hard floating point code. */
517 int mips16_hard_float
;
519 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
521 /* If TRUE, we split addresses into their high and low parts in the RTL. */
522 int mips_split_addresses
;
524 /* Mode used for saving/restoring general purpose registers. */
525 static enum machine_mode gpr_mode
;
527 /* Array giving truth value on whether or not a given hard register
528 can support a given mode. */
529 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
531 /* List of all MIPS punctuation characters used by print_operand. */
532 char mips_print_operand_punct
[256];
534 /* Map GCC register number to debugger register number. */
535 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
537 /* A copy of the original flag_delayed_branch: see override_options. */
538 static int mips_flag_delayed_branch
;
540 static GTY (()) int mips_output_filename_first_time
= 1;
542 /* mips_split_p[X] is true if symbols of type X can be split by
543 mips_split_symbol(). */
544 static bool mips_split_p
[NUM_SYMBOL_TYPES
];
546 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
547 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
548 if they are matched by a special .md file pattern. */
549 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
551 /* Likewise for HIGHs. */
552 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
554 /* Map hard register number to register class */
555 const enum reg_class mips_regno_to_class
[] =
557 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, M16_NA_REGS
,
558 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
559 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
560 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
561 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
562 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
563 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
564 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
565 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
566 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
567 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
568 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
569 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
570 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
571 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
572 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
573 HI_REG
, LO_REG
, NO_REGS
, ST_REGS
,
574 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
575 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
576 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
577 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
578 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
579 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
580 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
581 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
582 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
583 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
584 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
585 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
586 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
587 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
588 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
589 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
590 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
591 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
592 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
593 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
594 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
595 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
596 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
597 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
598 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
599 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
600 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
603 /* Map register constraint character to register class. */
604 enum reg_class mips_char_to_class
[256];
606 /* A table describing all the processors gcc knows about. Names are
607 matched in the order listed. The first mention of an ISA level is
608 taken as the canonical name for that ISA.
610 To ease comparison, please keep this table in the same order as
611 gas's mips_cpu_info_table[]. */
612 const struct mips_cpu_info mips_cpu_info_table
[] = {
613 /* Entries for generic ISAs */
614 { "mips1", PROCESSOR_R3000
, 1 },
615 { "mips2", PROCESSOR_R6000
, 2 },
616 { "mips3", PROCESSOR_R4000
, 3 },
617 { "mips4", PROCESSOR_R8000
, 4 },
618 { "mips32", PROCESSOR_4KC
, 32 },
619 { "mips32r2", PROCESSOR_M4K
, 33 },
620 { "mips64", PROCESSOR_5KC
, 64 },
623 { "r3000", PROCESSOR_R3000
, 1 },
624 { "r2000", PROCESSOR_R3000
, 1 }, /* = r3000 */
625 { "r3900", PROCESSOR_R3900
, 1 },
628 { "r6000", PROCESSOR_R6000
, 2 },
631 { "r4000", PROCESSOR_R4000
, 3 },
632 { "vr4100", PROCESSOR_R4100
, 3 },
633 { "vr4111", PROCESSOR_R4111
, 3 },
634 { "vr4120", PROCESSOR_R4120
, 3 },
635 { "vr4130", PROCESSOR_R4130
, 3 },
636 { "vr4300", PROCESSOR_R4300
, 3 },
637 { "r4400", PROCESSOR_R4000
, 3 }, /* = r4000 */
638 { "r4600", PROCESSOR_R4600
, 3 },
639 { "orion", PROCESSOR_R4600
, 3 }, /* = r4600 */
640 { "r4650", PROCESSOR_R4650
, 3 },
643 { "r8000", PROCESSOR_R8000
, 4 },
644 { "vr5000", PROCESSOR_R5000
, 4 },
645 { "vr5400", PROCESSOR_R5400
, 4 },
646 { "vr5500", PROCESSOR_R5500
, 4 },
647 { "rm7000", PROCESSOR_R7000
, 4 },
648 { "rm9000", PROCESSOR_R9000
, 4 },
651 { "4kc", PROCESSOR_4KC
, 32 },
652 { "4kp", PROCESSOR_4KC
, 32 }, /* = 4kc */
654 /* MIPS32 Release 2 */
655 { "m4k", PROCESSOR_M4K
, 33 },
658 { "5kc", PROCESSOR_5KC
, 64 },
659 { "20kc", PROCESSOR_20KC
, 64 },
660 { "sb1", PROCESSOR_SB1
, 64 },
661 { "sr71000", PROCESSOR_SR71000
, 64 },
667 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
668 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
669 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
672 /* Initialize the GCC target structure. */
673 #undef TARGET_ASM_ALIGNED_HI_OP
674 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
675 #undef TARGET_ASM_ALIGNED_SI_OP
676 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
677 #undef TARGET_ASM_ALIGNED_DI_OP
678 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
680 #undef TARGET_ASM_FUNCTION_PROLOGUE
681 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
682 #undef TARGET_ASM_FUNCTION_EPILOGUE
683 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
684 #undef TARGET_ASM_SELECT_RTX_SECTION
685 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
687 #undef TARGET_SCHED_REORDER
688 #define TARGET_SCHED_REORDER mips_sched_reorder
689 #undef TARGET_SCHED_VARIABLE_ISSUE
690 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
691 #undef TARGET_SCHED_ADJUST_COST
692 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
693 #undef TARGET_SCHED_ISSUE_RATE
694 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
695 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
696 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
697 mips_multipass_dfa_lookahead
699 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
700 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
702 #undef TARGET_VALID_POINTER_MODE
703 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
704 #undef TARGET_RTX_COSTS
705 #define TARGET_RTX_COSTS mips_rtx_costs
706 #undef TARGET_ADDRESS_COST
707 #define TARGET_ADDRESS_COST mips_address_cost
709 #undef TARGET_IN_SMALL_DATA_P
710 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
712 #undef TARGET_MACHINE_DEPENDENT_REORG
713 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
715 #undef TARGET_ASM_FILE_START
716 #undef TARGET_ASM_FILE_END
717 #define TARGET_ASM_FILE_START mips_file_start
718 #define TARGET_ASM_FILE_END mips_file_end
719 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
720 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
722 #undef TARGET_INIT_LIBFUNCS
723 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
725 #undef TARGET_BUILD_BUILTIN_VA_LIST
726 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
727 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
728 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
730 #undef TARGET_PROMOTE_FUNCTION_ARGS
731 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
732 #undef TARGET_PROMOTE_FUNCTION_RETURN
733 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
734 #undef TARGET_PROMOTE_PROTOTYPES
735 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
737 #undef TARGET_RETURN_IN_MEMORY
738 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
739 #undef TARGET_RETURN_IN_MSB
740 #define TARGET_RETURN_IN_MSB mips_return_in_msb
742 #undef TARGET_ASM_OUTPUT_MI_THUNK
743 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
744 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
745 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
747 #undef TARGET_SETUP_INCOMING_VARARGS
748 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
749 #undef TARGET_STRICT_ARGUMENT_NAMING
750 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
751 #undef TARGET_MUST_PASS_IN_STACK
752 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
753 #undef TARGET_PASS_BY_REFERENCE
754 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
756 #undef TARGET_VECTOR_MODE_SUPPORTED_P
757 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
759 #undef TARGET_INIT_BUILTINS
760 #define TARGET_INIT_BUILTINS mips_init_builtins
761 #undef TARGET_EXPAND_BUILTIN
762 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
764 struct gcc_target targetm
= TARGET_INITIALIZER
;
766 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
768 static enum mips_symbol_type
769 mips_classify_symbol (rtx x
)
771 if (GET_CODE (x
) == LABEL_REF
)
774 return SYMBOL_CONSTANT_POOL
;
776 return SYMBOL_GOT_LOCAL
;
777 return SYMBOL_GENERAL
;
780 if (GET_CODE (x
) != SYMBOL_REF
)
783 if (CONSTANT_POOL_ADDRESS_P (x
))
786 return SYMBOL_CONSTANT_POOL
;
789 return SYMBOL_GOT_LOCAL
;
791 if (GET_MODE_SIZE (get_pool_mode (x
)) <= mips_section_threshold
)
792 return SYMBOL_SMALL_DATA
;
794 return SYMBOL_GENERAL
;
797 if (SYMBOL_REF_SMALL_P (x
))
798 return SYMBOL_SMALL_DATA
;
802 if (SYMBOL_REF_DECL (x
) == 0)
803 return SYMBOL_REF_LOCAL_P (x
) ? SYMBOL_GOT_LOCAL
: SYMBOL_GOT_GLOBAL
;
805 /* There are three cases to consider:
807 - o32 PIC (either with or without explicit relocs)
808 - n32/n64 PIC without explicit relocs
809 - n32/n64 PIC with explicit relocs
811 In the first case, both local and global accesses will use an
812 R_MIPS_GOT16 relocation. We must correctly predict which of
813 the two semantics (local or global) the assembler and linker
814 will apply. The choice doesn't depend on the symbol's
815 visibility, so we deliberately ignore decl_visibility and
818 In the second case, the assembler will not use R_MIPS_GOT16
819 relocations, but it chooses between local and global accesses
820 in the same way as for o32 PIC.
822 In the third case we have more freedom since both forms of
823 access will work for any kind of symbol. However, there seems
824 little point in doing things differently. */
825 if (DECL_P (SYMBOL_REF_DECL (x
)) && TREE_PUBLIC (SYMBOL_REF_DECL (x
)))
826 return SYMBOL_GOT_GLOBAL
;
828 return SYMBOL_GOT_LOCAL
;
831 return SYMBOL_GENERAL
;
835 /* Split X into a base and a constant offset, storing them in *BASE
836 and *OFFSET respectively. */
839 mips_split_const (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
843 if (GET_CODE (x
) == CONST
)
846 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
848 *offset
+= INTVAL (XEXP (x
, 1));
855 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
856 to the same object as SYMBOL. */
859 mips_offset_within_object_p (rtx symbol
, HOST_WIDE_INT offset
)
861 if (GET_CODE (symbol
) != SYMBOL_REF
)
864 if (CONSTANT_POOL_ADDRESS_P (symbol
)
866 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
869 if (SYMBOL_REF_DECL (symbol
) != 0
871 && offset
< int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol
))))
878 /* Return true if X is a symbolic constant that can be calculated in
879 the same way as a bare symbol. If it is, store the type of the
880 symbol in *SYMBOL_TYPE. */
883 mips_symbolic_constant_p (rtx x
, enum mips_symbol_type
*symbol_type
)
885 HOST_WIDE_INT offset
;
887 mips_split_const (x
, &x
, &offset
);
888 if (UNSPEC_ADDRESS_P (x
))
889 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
890 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
891 *symbol_type
= mips_classify_symbol (x
);
898 /* Check whether a nonzero offset is valid for the underlying
900 switch (*symbol_type
)
906 /* If the target has 64-bit pointers and the object file only
907 supports 32-bit symbols, the values of those symbols will be
908 sign-extended. In this case we can't allow an arbitrary offset
909 in case the 32-bit value X + OFFSET has a different sign from X. */
910 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
911 return mips_offset_within_object_p (x
, offset
);
913 /* In other cases the relocations can handle any offset. */
916 case SYMBOL_CONSTANT_POOL
:
917 /* Allow constant pool references to be converted to LABEL+CONSTANT.
918 In this case, we no longer have access to the underlying constant,
919 but the original symbol-based access was known to be valid. */
920 if (GET_CODE (x
) == LABEL_REF
)
925 case SYMBOL_SMALL_DATA
:
926 /* Make sure that the offset refers to something within the
927 underlying object. This should guarantee that the final
928 PC- or GP-relative offset is within the 16-bit limit. */
929 return mips_offset_within_object_p (x
, offset
);
931 case SYMBOL_GOT_LOCAL
:
932 case SYMBOL_GOTOFF_PAGE
:
933 /* The linker should provide enough local GOT entries for a
934 16-bit offset. Larger offsets may lead to GOT overflow. */
935 return SMALL_OPERAND (offset
);
937 case SYMBOL_GOT_GLOBAL
:
938 case SYMBOL_GOTOFF_GLOBAL
:
939 case SYMBOL_GOTOFF_CALL
:
940 case SYMBOL_GOTOFF_LOADGP
:
947 /* Return true if X is a symbolic constant whose value is not split
948 into separate relocations. */
951 mips_atomic_symbolic_constant_p (rtx x
)
953 enum mips_symbol_type type
;
954 return mips_symbolic_constant_p (x
, &type
) && !mips_split_p
[type
];
958 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
961 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
, int strict
)
963 if (regno
>= FIRST_PSEUDO_REGISTER
)
967 regno
= reg_renumber
[regno
];
970 /* These fake registers will be eliminated to either the stack or
971 hard frame pointer, both of which are usually valid base registers.
972 Reload deals with the cases where the eliminated form isn't valid. */
973 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
976 /* In mips16 mode, the stack pointer can only address word and doubleword
977 values, nothing smaller. There are two problems here:
979 (a) Instantiating virtual registers can introduce new uses of the
980 stack pointer. If these virtual registers are valid addresses,
981 the stack pointer should be too.
983 (b) Most uses of the stack pointer are not made explicit until
984 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
985 We don't know until that stage whether we'll be eliminating to the
986 stack pointer (which needs the restriction) or the hard frame
987 pointer (which doesn't).
989 All in all, it seems more consistent to only enforce this restriction
990 during and after reload. */
991 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
992 return !strict
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
994 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
998 /* Return true if X is a valid base register for the given mode.
999 Allow only hard registers if STRICT. */
1002 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, int strict
)
1004 if (!strict
&& GET_CODE (x
) == SUBREG
)
1007 return (GET_CODE (x
) == REG
1008 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict
));
1012 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1013 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1016 mips_symbolic_address_p (enum mips_symbol_type symbol_type
,
1017 enum machine_mode mode
)
1019 switch (symbol_type
)
1021 case SYMBOL_GENERAL
:
1022 return !TARGET_MIPS16
;
1024 case SYMBOL_SMALL_DATA
:
1027 case SYMBOL_CONSTANT_POOL
:
1028 /* PC-relative addressing is only available for lw and ld. */
1029 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1031 case SYMBOL_GOT_LOCAL
:
1034 case SYMBOL_GOT_GLOBAL
:
1035 /* The address will have to be loaded from the GOT first. */
1038 case SYMBOL_GOTOFF_PAGE
:
1039 case SYMBOL_GOTOFF_GLOBAL
:
1040 case SYMBOL_GOTOFF_CALL
:
1041 case SYMBOL_GOTOFF_LOADGP
:
1042 case SYMBOL_64_HIGH
:
1051 /* Return true if X is a valid address for machine mode MODE. If it is,
1052 fill in INFO appropriately. STRICT is true if we should only accept
1053 hard base registers. */
1056 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1057 enum machine_mode mode
, int strict
)
1059 switch (GET_CODE (x
))
1063 info
->type
= ADDRESS_REG
;
1065 info
->offset
= const0_rtx
;
1066 return mips_valid_base_register_p (info
->reg
, mode
, strict
);
1069 info
->type
= ADDRESS_REG
;
1070 info
->reg
= XEXP (x
, 0);
1071 info
->offset
= XEXP (x
, 1);
1072 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1073 && const_arith_operand (info
->offset
, VOIDmode
));
1076 info
->type
= ADDRESS_LO_SUM
;
1077 info
->reg
= XEXP (x
, 0);
1078 info
->offset
= XEXP (x
, 1);
1079 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1080 && mips_symbolic_constant_p (info
->offset
, &info
->symbol_type
)
1081 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1082 && mips_lo_relocs
[info
->symbol_type
] != 0);
1085 /* Small-integer addresses don't occur very often, but they
1086 are legitimate if $0 is a valid base register. */
1087 info
->type
= ADDRESS_CONST_INT
;
1088 return !TARGET_MIPS16
&& SMALL_INT (x
);
1093 info
->type
= ADDRESS_SYMBOLIC
;
1094 return (mips_symbolic_constant_p (x
, &info
->symbol_type
)
1095 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1096 && !mips_split_p
[info
->symbol_type
]);
1103 /* Return the number of instructions needed to load a symbol of the
1104 given type into a register. If valid in an address, the same number
1105 of instructions are needed for loads and stores. Treat extended
1106 mips16 instructions as two instructions. */
1109 mips_symbol_insns (enum mips_symbol_type type
)
1113 case SYMBOL_GENERAL
:
1114 /* In mips16 code, general symbols must be fetched from the
1119 /* When using 64-bit symbols, we need 5 preparatory instructions,
1122 lui $at,%highest(symbol)
1123 daddiu $at,$at,%higher(symbol)
1125 daddiu $at,$at,%hi(symbol)
1128 The final address is then $at + %lo(symbol). With 32-bit
1129 symbols we just need a preparatory lui. */
1130 return (ABI_HAS_64BIT_SYMBOLS
? 6 : 2);
1132 case SYMBOL_SMALL_DATA
:
1135 case SYMBOL_CONSTANT_POOL
:
1136 /* This case is for mips16 only. Assume we'll need an
1137 extended instruction. */
1140 case SYMBOL_GOT_LOCAL
:
1141 case SYMBOL_GOT_GLOBAL
:
1142 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1143 the local/global classification is accurate. See override_options
1146 The worst cases are:
1148 (1) For local symbols when generating o32 or o64 code. The assembler
1154 ...and the final address will be $at + %lo(symbol).
1156 (2) For global symbols when -mxgot. The assembler will use:
1158 lui $at,%got_hi(symbol)
1161 ...and the final address will be $at + %got_lo(symbol). */
1164 case SYMBOL_GOTOFF_PAGE
:
1165 case SYMBOL_GOTOFF_GLOBAL
:
1166 case SYMBOL_GOTOFF_CALL
:
1167 case SYMBOL_GOTOFF_LOADGP
:
1168 case SYMBOL_64_HIGH
:
1171 /* Check whether the offset is a 16- or 32-bit value. */
1172 return mips_split_p
[type
] ? 2 : 1;
1177 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1180 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1182 struct mips_address_info addr
;
1184 return (mips_classify_address (&addr
, x
, mode
, false)
1185 && addr
.type
== ADDRESS_REG
1186 && addr
.reg
== stack_pointer_rtx
);
1189 /* Return true if a value at OFFSET bytes from BASE can be accessed
1190 using an unextended mips16 instruction. MODE is the mode of the
1193 Usually the offset in an unextended instruction is a 5-bit field.
1194 The offset is unsigned and shifted left once for HIs, twice
1195 for SIs, and so on. An exception is SImode accesses off the
1196 stack pointer, which have an 8-bit immediate field. */
1199 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
, rtx offset
)
1202 && GET_CODE (offset
) == CONST_INT
1203 && INTVAL (offset
) >= 0
1204 && (INTVAL (offset
) & (GET_MODE_SIZE (mode
) - 1)) == 0)
1206 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1207 return INTVAL (offset
) < 256 * GET_MODE_SIZE (mode
);
1208 return INTVAL (offset
) < 32 * GET_MODE_SIZE (mode
);
1214 /* Return the number of instructions needed to load or store a value
1215 of mode MODE at X. Return 0 if X isn't valid for MODE.
1217 For mips16 code, count extended instructions as two instructions. */
1220 mips_address_insns (rtx x
, enum machine_mode mode
)
1222 struct mips_address_info addr
;
1225 if (mode
== BLKmode
)
1226 /* BLKmode is used for single unaligned loads and stores. */
1229 /* Each word of a multi-word value will be accessed individually. */
1230 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1232 if (mips_classify_address (&addr
, x
, mode
, false))
1237 && !mips16_unextended_reference_p (mode
, addr
.reg
, addr
.offset
))
1241 case ADDRESS_LO_SUM
:
1242 return (TARGET_MIPS16
? factor
* 2 : factor
);
1244 case ADDRESS_CONST_INT
:
1247 case ADDRESS_SYMBOLIC
:
1248 return factor
* mips_symbol_insns (addr
.symbol_type
);
1254 /* Likewise for constant X. */
1257 mips_const_insns (rtx x
)
1259 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
1260 enum mips_symbol_type symbol_type
;
1261 HOST_WIDE_INT offset
;
1263 switch (GET_CODE (x
))
1267 || !mips_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
1268 || !mips_split_p
[symbol_type
])
1275 /* Unsigned 8-bit constants can be loaded using an unextended
1276 LI instruction. Unsigned 16-bit constants can be loaded
1277 using an extended LI. Negative constants must be loaded
1278 using LI and then negated. */
1279 return (INTVAL (x
) >= 0 && INTVAL (x
) < 256 ? 1
1280 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
1281 : INTVAL (x
) > -256 && INTVAL (x
) < 0 ? 2
1282 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
1285 return mips_build_integer (codes
, INTVAL (x
));
1289 return (!TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0);
1295 /* See if we can refer to X directly. */
1296 if (mips_symbolic_constant_p (x
, &symbol_type
))
1297 return mips_symbol_insns (symbol_type
);
1299 /* Otherwise try splitting the constant into a base and offset.
1300 16-bit offsets can be added using an extra addiu. Larger offsets
1301 must be calculated separately and then added to the base. */
1302 mips_split_const (x
, &x
, &offset
);
1305 int n
= mips_const_insns (x
);
1308 if (SMALL_OPERAND (offset
))
1311 return n
+ 1 + mips_build_integer (codes
, offset
);
1318 return mips_symbol_insns (mips_classify_symbol (x
));
1326 /* Return the number of instructions needed for memory reference X.
1327 Count extended mips16 instructions as two instructions. */
1330 mips_fetch_insns (rtx x
)
1332 if (GET_CODE (x
) != MEM
)
1335 return mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
1339 /* Return the number of instructions needed for an integer division. */
1342 mips_idiv_insns (void)
1347 if (TARGET_CHECK_ZERO_DIV
)
1349 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
1354 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1355 returns a nonzero value if X is a legitimate address for a memory
1356 operand of the indicated MODE. STRICT is nonzero if this function
1357 is called during reload. */
1360 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1362 struct mips_address_info addr
;
1364 return mips_classify_address (&addr
, x
, mode
, strict
);
1368 /* Copy VALUE to a register and return that register. If new psuedos
1369 are allowed, copy it into a new register, otherwise use DEST. */
1372 mips_force_temporary (rtx dest
, rtx value
)
1374 if (!no_new_pseudos
)
1375 return force_reg (Pmode
, value
);
1378 emit_move_insn (copy_rtx (dest
), value
);
1384 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1385 and is used to load the high part into a register. */
1388 mips_split_symbol (rtx temp
, rtx addr
)
1393 high
= mips16_gp_pseudo_reg ();
1395 high
= mips_force_temporary (temp
, gen_rtx_HIGH (Pmode
, copy_rtx (addr
)));
1396 return gen_rtx_LO_SUM (Pmode
, high
, addr
);
1400 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1401 type SYMBOL_TYPE. */
1404 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
1407 HOST_WIDE_INT offset
;
1409 mips_split_const (address
, &base
, &offset
);
1410 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1411 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1412 return plus_constant (gen_rtx_CONST (Pmode
, base
), offset
);
1416 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1417 high part to BASE and return the result. Just return BASE otherwise.
1418 TEMP is available as a temporary register if needed.
1420 The returned expression can be used as the first operand to a LO_SUM. */
1423 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
1424 enum mips_symbol_type symbol_type
)
1426 if (mips_split_p
[symbol_type
])
1428 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
1429 addr
= mips_force_temporary (temp
, addr
);
1430 return mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
1436 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1437 mips_force_temporary; it is only needed when OFFSET is not a
1441 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1443 if (!SMALL_OPERAND (offset
))
1448 /* Load the full offset into a register so that we can use
1449 an unextended instruction for the address itself. */
1450 high
= GEN_INT (offset
);
1455 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1456 high
= GEN_INT (CONST_HIGH_PART (offset
));
1457 offset
= CONST_LOW_PART (offset
);
1459 high
= mips_force_temporary (temp
, high
);
1460 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1462 return plus_constant (reg
, offset
);
1466 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1467 be legitimized in a way that the generic machinery might not expect,
1468 put the new address in *XLOC and return true. MODE is the mode of
1469 the memory being accessed. */
1472 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
1474 enum mips_symbol_type symbol_type
;
1476 /* See if the address can split into a high part and a LO_SUM. */
1477 if (mips_symbolic_constant_p (*xloc
, &symbol_type
)
1478 && mips_symbolic_address_p (symbol_type
, mode
)
1479 && mips_split_p
[symbol_type
])
1481 *xloc
= mips_split_symbol (0, *xloc
);
1485 if (GET_CODE (*xloc
) == PLUS
&& GET_CODE (XEXP (*xloc
, 1)) == CONST_INT
)
1487 /* Handle REG + CONSTANT using mips_add_offset. */
1490 reg
= XEXP (*xloc
, 0);
1491 if (!mips_valid_base_register_p (reg
, mode
, 0))
1492 reg
= copy_to_mode_reg (Pmode
, reg
);
1493 *xloc
= mips_add_offset (0, reg
, INTVAL (XEXP (*xloc
, 1)));
1501 /* Subroutine of mips_build_integer (with the same interface).
1502 Assume that the final action in the sequence should be a left shift. */
1505 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1507 unsigned int i
, shift
;
1509 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1510 since signed numbers are easier to load than unsigned ones. */
1512 while ((value
& 1) == 0)
1513 value
/= 2, shift
++;
1515 i
= mips_build_integer (codes
, value
);
1516 codes
[i
].code
= ASHIFT
;
1517 codes
[i
].value
= shift
;
1522 /* As for mips_build_shift, but assume that the final action will be
1523 an IOR or PLUS operation. */
1526 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1528 unsigned HOST_WIDE_INT high
;
1531 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1532 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1534 /* The constant is too complex to load with a simple lui/ori pair
1535 so our goal is to clear as many trailing zeros as possible.
1536 In this case, we know bit 16 is set and that the low 16 bits
1537 form a negative number. If we subtract that number from VALUE,
1538 we will clear at least the lowest 17 bits, maybe more. */
1539 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1540 codes
[i
].code
= PLUS
;
1541 codes
[i
].value
= CONST_LOW_PART (value
);
1545 i
= mips_build_integer (codes
, high
);
1546 codes
[i
].code
= IOR
;
1547 codes
[i
].value
= value
& 0xffff;
1553 /* Fill CODES with a sequence of rtl operations to load VALUE.
1554 Return the number of operations needed. */
1557 mips_build_integer (struct mips_integer_op
*codes
,
1558 unsigned HOST_WIDE_INT value
)
1560 if (SMALL_OPERAND (value
)
1561 || SMALL_OPERAND_UNSIGNED (value
)
1562 || LUI_OPERAND (value
))
1564 /* The value can be loaded with a single instruction. */
1565 codes
[0].code
= UNKNOWN
;
1566 codes
[0].value
= value
;
1569 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1571 /* Either the constant is a simple LUI/ORI combination or its
1572 lowest bit is set. We don't want to shift in this case. */
1573 return mips_build_lower (codes
, value
);
1575 else if ((value
& 0xffff) == 0)
1577 /* The constant will need at least three actions. The lowest
1578 16 bits are clear, so the final action will be a shift. */
1579 return mips_build_shift (codes
, value
);
1583 /* The final action could be a shift, add or inclusive OR.
1584 Rather than use a complex condition to select the best
1585 approach, try both mips_build_shift and mips_build_lower
1586 and pick the one that gives the shortest sequence.
1587 Note that this case is only used once per constant. */
1588 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1589 unsigned int cost
, alt_cost
;
1591 cost
= mips_build_shift (codes
, value
);
1592 alt_cost
= mips_build_lower (alt_codes
, value
);
1593 if (alt_cost
< cost
)
1595 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1603 /* Move VALUE into register DEST. */
1606 mips_move_integer (rtx dest
, unsigned HOST_WIDE_INT value
)
1608 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
1609 enum machine_mode mode
;
1610 unsigned int i
, cost
;
1613 mode
= GET_MODE (dest
);
1614 cost
= mips_build_integer (codes
, value
);
1616 /* Apply each binary operation to X. Invariant: X is a legitimate
1617 source operand for a SET pattern. */
1618 x
= GEN_INT (codes
[0].value
);
1619 for (i
= 1; i
< cost
; i
++)
1622 emit_move_insn (dest
, x
), x
= dest
;
1624 x
= force_reg (mode
, x
);
1625 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1628 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1632 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1633 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1637 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
1640 HOST_WIDE_INT offset
;
1641 enum mips_symbol_type symbol_type
;
1643 /* Split moves of big integers into smaller pieces. In mips16 code,
1644 it's better to force the constant into memory instead. */
1645 if (GET_CODE (src
) == CONST_INT
&& !TARGET_MIPS16
)
1647 mips_move_integer (dest
, INTVAL (src
));
1651 /* See if the symbol can be split. For mips16, this is often worse than
1652 forcing it in the constant pool since it needs the single-register form
1653 of addiu or daddiu. */
1655 && mips_symbolic_constant_p (src
, &symbol_type
)
1656 && mips_split_p
[symbol_type
])
1658 emit_move_insn (dest
, mips_split_symbol (dest
, src
));
1662 /* If we have (const (plus symbol offset)), load the symbol first
1663 and then add in the offset. This is usually better than forcing
1664 the constant into memory, at least in non-mips16 code. */
1665 mips_split_const (src
, &base
, &offset
);
1668 && (!no_new_pseudos
|| SMALL_OPERAND (offset
)))
1670 base
= mips_force_temporary (dest
, base
);
1671 emit_move_insn (dest
, mips_add_offset (0, base
, offset
));
1675 src
= force_const_mem (mode
, src
);
1677 /* When using explicit relocs, constant pool references are sometimes
1678 not legitimate addresses. */
1679 if (!memory_operand (src
, VOIDmode
))
1680 src
= replace_equiv_address (src
, mips_split_symbol (dest
, XEXP (src
, 0)));
1681 emit_move_insn (dest
, src
);
1685 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1686 sequence that is valid. */
1689 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
1691 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1693 emit_move_insn (dest
, force_reg (mode
, src
));
1697 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
1698 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1699 && REG_P (src
) && MD_REG_P (REGNO (src
))
1700 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
1702 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
1703 if (GET_MODE_SIZE (mode
) <= 4)
1704 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode
, REGNO (dest
)),
1705 gen_rtx_REG (SImode
, REGNO (src
)),
1706 gen_rtx_REG (SImode
, other_regno
)));
1708 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode
, REGNO (dest
)),
1709 gen_rtx_REG (DImode
, REGNO (src
)),
1710 gen_rtx_REG (DImode
, other_regno
)));
1714 /* We need to deal with constants that would be legitimate
1715 immediate_operands but not legitimate move_operands. */
1716 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1718 mips_legitimize_const_move (mode
, dest
, src
);
1719 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1725 /* We need a lot of little routines to check constant values on the
1726 mips16. These are used to figure out how long the instruction will
1727 be. It would be much better to do this using constraints, but
1728 there aren't nearly enough letters available. */
1731 m16_check_op (rtx op
, int low
, int high
, int mask
)
1733 return (GET_CODE (op
) == CONST_INT
1734 && INTVAL (op
) >= low
1735 && INTVAL (op
) <= high
1736 && (INTVAL (op
) & mask
) == 0);
1740 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1742 return m16_check_op (op
, 0x1, 0x8, 0);
1746 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1748 return m16_check_op (op
, - 0x8, 0x7, 0);
1752 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1754 return m16_check_op (op
, - 0x7, 0x8, 0);
1758 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1760 return m16_check_op (op
, - 0x10, 0xf, 0);
1764 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1766 return m16_check_op (op
, - 0xf, 0x10, 0);
1770 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1772 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1776 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1778 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1782 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1784 return m16_check_op (op
, - 0x80, 0x7f, 0);
1788 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1790 return m16_check_op (op
, - 0x7f, 0x80, 0);
1794 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1796 return m16_check_op (op
, 0x0, 0xff, 0);
1800 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1802 return m16_check_op (op
, - 0xff, 0x0, 0);
1806 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1808 return m16_check_op (op
, - 0x1, 0xfe, 0);
1812 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1814 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1818 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1820 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1824 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1826 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1830 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1832 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1836 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1838 enum machine_mode mode
= GET_MODE (x
);
1845 /* Always return 0, since we don't have different sized
1846 instructions, hence different costs according to Richard
1852 /* A number between 1 and 8 inclusive is efficient for a shift.
1853 Otherwise, we will need an extended instruction. */
1854 if ((outer_code
) == ASHIFT
|| (outer_code
) == ASHIFTRT
1855 || (outer_code
) == LSHIFTRT
)
1857 if (INTVAL (x
) >= 1 && INTVAL (x
) <= 8)
1860 *total
= COSTS_N_INSNS (1);
1864 /* We can use cmpi for an xor with an unsigned 16 bit value. */
1865 if ((outer_code
) == XOR
1866 && INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
1872 /* We may be able to use slt or sltu for a comparison with a
1873 signed 16 bit value. (The boundary conditions aren't quite
1874 right, but this is just a heuristic anyhow.) */
1875 if (((outer_code
) == LT
|| (outer_code
) == LE
1876 || (outer_code
) == GE
|| (outer_code
) == GT
1877 || (outer_code
) == LTU
|| (outer_code
) == LEU
1878 || (outer_code
) == GEU
|| (outer_code
) == GTU
)
1879 && INTVAL (x
) >= -0x8000 && INTVAL (x
) < 0x8000)
1885 /* Equality comparisons with 0 are cheap. */
1886 if (((outer_code
) == EQ
|| (outer_code
) == NE
)
1893 /* Constants in the range 0...255 can be loaded with an unextended
1894 instruction. They are therefore as cheap as a register move.
1896 Given the choice between "li R1,0...255" and "move R1,R2"
1897 (where R2 is a known constant), it is usually better to use "li",
1898 since we do not want to unnessarily extend the lifetime of R2. */
1899 if (outer_code
== SET
1901 && INTVAL (x
) < 256)
1907 /* Otherwise fall through to the handling below. */
1913 if (LEGITIMATE_CONSTANT_P (x
))
1915 *total
= COSTS_N_INSNS (1);
1920 /* The value will need to be fetched from the constant pool. */
1921 *total
= CONSTANT_POOL_COST
;
1927 /* If the address is legitimate, return the number of
1928 instructions it needs, otherwise use the default handling. */
1929 int n
= mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
1932 *total
= COSTS_N_INSNS (1 + n
);
1939 *total
= COSTS_N_INSNS (6);
1943 *total
= COSTS_N_INSNS ((mode
== DImode
&& !TARGET_64BIT
) ? 2 : 1);
1949 if (mode
== DImode
&& !TARGET_64BIT
)
1951 *total
= COSTS_N_INSNS (2);
1959 if (mode
== DImode
&& !TARGET_64BIT
)
1961 *total
= COSTS_N_INSNS ((GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1968 if (mode
== SFmode
|| mode
== DFmode
)
1969 *total
= COSTS_N_INSNS (1);
1971 *total
= COSTS_N_INSNS (4);
1975 *total
= COSTS_N_INSNS (1);
1980 if (mode
== SFmode
|| mode
== DFmode
)
1982 if (TUNE_MIPS3000
|| TUNE_MIPS3900
)
1983 *total
= COSTS_N_INSNS (2);
1984 else if (TUNE_MIPS6000
)
1985 *total
= COSTS_N_INSNS (3);
1987 *total
= COSTS_N_INSNS (4);
1989 *total
= COSTS_N_INSNS (6);
1992 if (mode
== DImode
&& !TARGET_64BIT
)
1994 *total
= COSTS_N_INSNS (4);
2000 if (mode
== DImode
&& !TARGET_64BIT
)
2014 *total
= COSTS_N_INSNS (4);
2015 else if (TUNE_MIPS6000
2018 *total
= COSTS_N_INSNS (5);
2020 *total
= COSTS_N_INSNS (7);
2027 *total
= COSTS_N_INSNS (4);
2028 else if (TUNE_MIPS3000
2031 *total
= COSTS_N_INSNS (5);
2032 else if (TUNE_MIPS6000
2035 *total
= COSTS_N_INSNS (6);
2037 *total
= COSTS_N_INSNS (8);
2042 *total
= COSTS_N_INSNS (12);
2043 else if (TUNE_MIPS3900
)
2044 *total
= COSTS_N_INSNS (2);
2045 else if (TUNE_MIPS4130
)
2046 *total
= COSTS_N_INSNS (mode
== DImode
? 6 : 4);
2047 else if (TUNE_MIPS5400
|| TUNE_SB1
)
2048 *total
= COSTS_N_INSNS (mode
== DImode
? 4 : 3);
2049 else if (TUNE_MIPS5500
|| TUNE_MIPS7000
)
2050 *total
= COSTS_N_INSNS (mode
== DImode
? 9 : 5);
2051 else if (TUNE_MIPS9000
)
2052 *total
= COSTS_N_INSNS (mode
== DImode
? 8 : 3);
2053 else if (TUNE_MIPS6000
)
2054 *total
= COSTS_N_INSNS (17);
2055 else if (TUNE_MIPS5000
)
2056 *total
= COSTS_N_INSNS (5);
2058 *total
= COSTS_N_INSNS (10);
2067 *total
= COSTS_N_INSNS (12);
2068 else if (TUNE_MIPS6000
)
2069 *total
= COSTS_N_INSNS (15);
2071 *total
= COSTS_N_INSNS (24);
2072 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
2073 *total
= COSTS_N_INSNS (30);
2075 *total
= COSTS_N_INSNS (23);
2083 *total
= COSTS_N_INSNS (19);
2084 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
2085 *total
= COSTS_N_INSNS (59);
2086 else if (TUNE_MIPS6000
)
2087 *total
= COSTS_N_INSNS (16);
2089 *total
= COSTS_N_INSNS (32);
2091 *total
= COSTS_N_INSNS (36);
2100 *total
= COSTS_N_INSNS (35);
2101 else if (TUNE_MIPS6000
)
2102 *total
= COSTS_N_INSNS (38);
2103 else if (TUNE_MIPS5000
)
2104 *total
= COSTS_N_INSNS (36);
2106 *total
= COSTS_N_INSNS ((mode
== SImode
) ? 36 : 68);
2107 else if (TUNE_MIPS5400
|| TUNE_MIPS5500
)
2108 *total
= COSTS_N_INSNS ((mode
== SImode
) ? 42 : 74);
2110 *total
= COSTS_N_INSNS (69);
2114 /* A sign extend from SImode to DImode in 64 bit mode is often
2115 zero instructions, because the result can often be used
2116 directly by another instruction; we'll call it one. */
2117 if (TARGET_64BIT
&& mode
== DImode
2118 && GET_MODE (XEXP (x
, 0)) == SImode
)
2119 *total
= COSTS_N_INSNS (1);
2121 *total
= COSTS_N_INSNS (2);
2125 if (TARGET_64BIT
&& mode
== DImode
2126 && GET_MODE (XEXP (x
, 0)) == SImode
)
2127 *total
= COSTS_N_INSNS (2);
2129 *total
= COSTS_N_INSNS (1);
2137 /* Provide the costs of an addressing mode that contains ADDR.
2138 If ADDR is not a valid address, its cost is irrelevant. */
2141 mips_address_cost (rtx addr
)
2143 return mips_address_insns (addr
, SImode
);
2146 /* Return one word of double-word value OP, taking into account the fixed
2147 endianness of certain registers. HIGH_P is true to select the high part,
2148 false to select the low part. */
2151 mips_subword (rtx op
, int high_p
)
2154 enum machine_mode mode
;
2156 mode
= GET_MODE (op
);
2157 if (mode
== VOIDmode
)
2160 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
2161 byte
= UNITS_PER_WORD
;
2165 if (GET_CODE (op
) == REG
)
2167 if (FP_REG_P (REGNO (op
)))
2168 return gen_rtx_REG (word_mode
, high_p
? REGNO (op
) + 1 : REGNO (op
));
2169 if (REGNO (op
) == HI_REGNUM
)
2170 return gen_rtx_REG (word_mode
, high_p
? HI_REGNUM
: LO_REGNUM
);
2173 if (GET_CODE (op
) == MEM
)
2174 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2176 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2180 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2183 mips_split_64bit_move_p (rtx dest
, rtx src
)
2188 /* FP->FP moves can be done in a single instruction. */
2189 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
2192 /* Check for floating-point loads and stores. They can be done using
2193 ldc1 and sdc1 on MIPS II and above. */
2196 if (FP_REG_RTX_P (dest
) && GET_CODE (src
) == MEM
)
2198 if (FP_REG_RTX_P (src
) && GET_CODE (dest
) == MEM
)
2205 /* Split a 64-bit move from SRC to DEST assuming that
2206 mips_split_64bit_move_p holds.
2208 Moves into and out of FPRs cause some difficulty here. Such moves
2209 will always be DFmode, since paired FPRs are not allowed to store
2210 DImode values. The most natural representation would be two separate
2211 32-bit moves, such as:
2213 (set (reg:SI $f0) (mem:SI ...))
2214 (set (reg:SI $f1) (mem:SI ...))
2216 However, the second insn is invalid because odd-numbered FPRs are
2217 not allowed to store independent values. Use the patterns load_df_low,
2218 load_df_high and store_df_high instead. */
2221 mips_split_64bit_move (rtx dest
, rtx src
)
2223 if (FP_REG_RTX_P (dest
))
2225 /* Loading an FPR from memory or from GPRs. */
2226 emit_insn (gen_load_df_low (copy_rtx (dest
), mips_subword (src
, 0)));
2227 emit_insn (gen_load_df_high (dest
, mips_subword (src
, 1),
2230 else if (FP_REG_RTX_P (src
))
2232 /* Storing an FPR into memory or GPRs. */
2233 emit_move_insn (mips_subword (dest
, 0), mips_subword (src
, 0));
2234 emit_insn (gen_store_df_high (mips_subword (dest
, 1), src
));
2238 /* The operation can be split into two normal moves. Decide in
2239 which order to do them. */
2242 low_dest
= mips_subword (dest
, 0);
2243 if (GET_CODE (low_dest
) == REG
2244 && reg_overlap_mentioned_p (low_dest
, src
))
2246 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2247 emit_move_insn (low_dest
, mips_subword (src
, 0));
2251 emit_move_insn (low_dest
, mips_subword (src
, 0));
2252 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2257 /* Return the appropriate instructions to move SRC into DEST. Assume
2258 that SRC is operand 1 and DEST is operand 0. */
2261 mips_output_move (rtx dest
, rtx src
)
2263 enum rtx_code dest_code
, src_code
;
2266 dest_code
= GET_CODE (dest
);
2267 src_code
= GET_CODE (src
);
2268 dbl_p
= (GET_MODE_SIZE (GET_MODE (dest
)) == 8);
2270 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
2273 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2274 || (!TARGET_MIPS16
&& src
== CONST0_RTX (GET_MODE (dest
))))
2276 if (dest_code
== REG
)
2278 if (GP_REG_P (REGNO (dest
)))
2279 return "move\t%0,%z1";
2281 if (MD_REG_P (REGNO (dest
)))
2284 if (FP_REG_P (REGNO (dest
)))
2285 return (dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2287 if (ALL_COP_REG_P (REGNO (dest
)))
2289 static char retval
[] = "dmtc_\t%z1,%0";
2291 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2292 return (dbl_p
? retval
: retval
+ 1);
2295 if (dest_code
== MEM
)
2296 return (dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0");
2298 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2300 if (src_code
== REG
)
2302 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
2303 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2305 if (FP_REG_P (REGNO (src
)))
2306 return (dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2308 if (ALL_COP_REG_P (REGNO (src
)))
2310 static char retval
[] = "dmfc_\t%0,%1";
2312 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2313 return (dbl_p
? retval
: retval
+ 1);
2317 if (src_code
== MEM
)
2318 return (dbl_p
? "ld\t%0,%1" : "lw\t%0,%1");
2320 if (src_code
== CONST_INT
)
2322 /* Don't use the X format, because that will give out of
2323 range numbers for 64 bit hosts and 32 bit targets. */
2325 return "li\t%0,%1\t\t\t# %X1";
2327 if (INTVAL (src
) >= 0 && INTVAL (src
) <= 0xffff)
2330 if (INTVAL (src
) < 0 && INTVAL (src
) >= -0xffff)
2334 if (src_code
== HIGH
)
2335 return "lui\t%0,%h1";
2337 if (CONST_GP_P (src
))
2338 return "move\t%0,%1";
2340 if (symbolic_operand (src
, VOIDmode
))
2341 return (dbl_p
? "dla\t%0,%1" : "la\t%0,%1");
2343 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2345 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2347 if (GET_MODE (dest
) == V2SFmode
)
2348 return "mov.ps\t%0,%1";
2350 return (dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2353 if (dest_code
== MEM
)
2354 return (dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0");
2356 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2358 if (src_code
== MEM
)
2359 return (dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2361 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
2363 static char retval
[] = "l_c_\t%0,%1";
2365 retval
[1] = (dbl_p
? 'd' : 'w');
2366 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2369 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
2371 static char retval
[] = "s_c_\t%1,%0";
2373 retval
[1] = (dbl_p
? 'd' : 'w');
2374 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2380 /* Restore $gp from its save slot. Valid only when using o32 or
2384 mips_restore_gp (void)
2388 if (!TARGET_ABICALLS
|| !TARGET_OLDABI
)
2391 address
= mips_add_offset (pic_offset_table_rtx
,
2392 frame_pointer_needed
2393 ? hard_frame_pointer_rtx
2394 : stack_pointer_rtx
,
2395 current_function_outgoing_args_size
);
2396 slot
= gen_rtx_MEM (Pmode
, address
);
2398 emit_move_insn (pic_offset_table_rtx
, slot
);
2399 if (!TARGET_EXPLICIT_RELOCS
)
2400 emit_insn (gen_blockage ());
2403 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2406 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2408 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2409 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2412 /* Return true if CMP1 is a suitable second operand for relational
2413 operator CODE. See also the *sCC patterns in mips.md. */
2416 mips_relational_operand_ok_p (enum rtx_code code
, rtx cmp1
)
2422 return reg_or_0_operand (cmp1
, VOIDmode
);
2426 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
2430 return arith_operand (cmp1
, VOIDmode
);
2433 return sle_operand (cmp1
, VOIDmode
);
2436 return sleu_operand (cmp1
, VOIDmode
);
2443 /* Compare CMP0 and CMP1 using relational operator CODE and store the
2444 result in TARGET. CMP0 and TARGET are register_operands that have
2445 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
2446 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
2449 mips_emit_int_relational (enum rtx_code code
, bool *invert_ptr
,
2450 rtx target
, rtx cmp0
, rtx cmp1
)
2452 /* First see if there is a MIPS instruction that can do this operation
2453 with CMP1 in its current form. If not, try doing the same for the
2454 inverse operation. If that also fails, force CMP1 into a register
2456 if (mips_relational_operand_ok_p (code
, cmp1
))
2457 mips_emit_binary (code
, target
, cmp0
, cmp1
);
2460 enum rtx_code inv_code
= reverse_condition (code
);
2461 if (!mips_relational_operand_ok_p (inv_code
, cmp1
))
2463 cmp1
= force_reg (GET_MODE (cmp0
), cmp1
);
2464 mips_emit_int_relational (code
, invert_ptr
, target
, cmp0
, cmp1
);
2466 else if (invert_ptr
== 0)
2468 rtx inv_target
= gen_reg_rtx (GET_MODE (target
));
2469 mips_emit_binary (inv_code
, inv_target
, cmp0
, cmp1
);
2470 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2474 *invert_ptr
= !*invert_ptr
;
2475 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2480 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2481 The register will have the same mode as CMP0. */
2484 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
2486 if (cmp1
== const0_rtx
)
2489 if (uns_arith_operand (cmp1
, VOIDmode
))
2490 return expand_binop (GET_MODE (cmp0
), xor_optab
,
2491 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2493 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2494 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2497 /* Convert a comparison into something that can be used in a branch or
2498 conditional move. cmp_operands[0] and cmp_operands[1] are the values
2499 being compared and *CODE is the code used to compare them.
2501 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
2502 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
2503 otherwise any standard branch condition can be used. The standard branch
2506 - EQ/NE between two registers.
2507 - any comparison between a register and zero. */
2510 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
2512 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
2514 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
2516 *op0
= cmp_operands
[0];
2517 *op1
= cmp_operands
[1];
2519 else if (*code
== EQ
|| *code
== NE
)
2523 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
2528 *op0
= cmp_operands
[0];
2529 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
2534 /* The comparison needs a separate scc instruction. Store the
2535 result of the scc in *OP0 and compare it against zero. */
2536 bool invert
= false;
2537 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
2539 mips_emit_int_relational (*code
, &invert
, *op0
,
2540 cmp_operands
[0], cmp_operands
[1]);
2541 *code
= (invert
? EQ
: NE
);
2546 enum rtx_code cmp_code
;
2548 /* Floating-point tests use a separate c.cond.fmt comparison to
2549 set a condition code register. The branch or conditional move
2550 will then compare that register against zero.
2552 Set CMP_CODE to the code of the comparison instruction and
2553 *CODE to the code that the branch or move should use. */
2561 cmp_code
= reverse_condition_maybe_unordered (*code
);
2571 ? gen_reg_rtx (CCmode
)
2572 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
2574 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
2578 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
2579 Store the result in TARGET and return true if successful.
2581 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
2584 mips_emit_scc (enum rtx_code code
, rtx target
)
2586 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
2589 target
= gen_lowpart (GET_MODE (cmp_operands
[0]), target
);
2590 if (code
== EQ
|| code
== NE
)
2592 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
2593 mips_emit_binary (code
, target
, zie
, const0_rtx
);
2596 mips_emit_int_relational (code
, 0, target
,
2597 cmp_operands
[0], cmp_operands
[1]);
2601 /* Emit the common code for doing conditional branches.
2602 operand[0] is the label to jump to.
2603 The comparison operands are saved away by cmp{si,di,sf,df}. */
2606 gen_conditional_branch (rtx
*operands
, enum rtx_code code
)
2608 rtx op0
, op1
, target
;
2610 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
2611 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
2612 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2614 gen_rtx_LABEL_REF (VOIDmode
, operands
[0]),
2616 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, target
));
2619 /* Emit the common code for conditional moves. OPERANDS is the array
2620 of operands passed to the conditional move define_expand. */
2623 gen_conditional_move (rtx
*operands
)
2628 code
= GET_CODE (operands
[1]);
2629 mips_emit_compare (&code
, &op0
, &op1
, true);
2630 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2631 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2632 gen_rtx_fmt_ee (code
,
2635 operands
[2], operands
[3])));
2638 /* Emit a conditional trap. OPERANDS is the array of operands passed to
2639 the conditional_trap expander. */
2642 mips_gen_conditional_trap (rtx
*operands
)
2645 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
2646 enum machine_mode mode
= GET_MODE (cmp_operands
[0]);
2648 /* MIPS conditional trap machine instructions don't have GT or LE
2649 flavors, so we must invert the comparison and convert to LT and
2650 GE, respectively. */
2653 case GT
: cmp_code
= LT
; break;
2654 case LE
: cmp_code
= GE
; break;
2655 case GTU
: cmp_code
= LTU
; break;
2656 case LEU
: cmp_code
= GEU
; break;
2659 if (cmp_code
== GET_CODE (operands
[0]))
2661 op0
= cmp_operands
[0];
2662 op1
= cmp_operands
[1];
2666 op0
= cmp_operands
[1];
2667 op1
= cmp_operands
[0];
2669 op0
= force_reg (mode
, op0
);
2670 if (!arith_operand (op1
, mode
))
2671 op1
= force_reg (mode
, op1
);
2673 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
2674 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
),
2678 /* Load function address ADDR into register DEST. SIBCALL_P is true
2679 if the address is needed for a sibling call. */
2682 mips_load_call_address (rtx dest
, rtx addr
, int sibcall_p
)
2684 /* If we're generating PIC, and this call is to a global function,
2685 try to allow its address to be resolved lazily. This isn't
2686 possible for NewABI sibcalls since the value of $gp on entry
2687 to the stub would be our caller's gp, not ours. */
2688 if (TARGET_EXPLICIT_RELOCS
2689 && !(sibcall_p
&& TARGET_NEWABI
)
2690 && global_got_operand (addr
, VOIDmode
))
2692 rtx high
, lo_sum_symbol
;
2694 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
2695 addr
, SYMBOL_GOTOFF_CALL
);
2696 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
2697 if (Pmode
== SImode
)
2698 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
2700 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
2703 emit_move_insn (dest
, addr
);
2707 /* Expand a call or call_value instruction. RESULT is where the
2708 result will go (null for calls), ADDR is the address of the
2709 function, ARGS_SIZE is the size of the arguments and AUX is
2710 the value passed to us by mips_function_arg. SIBCALL_P is true
2711 if we are expanding a sibling call, false if we're expanding
2715 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, int sibcall_p
)
2717 rtx orig_addr
, pattern
, insn
;
2720 if (!call_insn_operand (addr
, VOIDmode
))
2722 addr
= gen_reg_rtx (Pmode
);
2723 mips_load_call_address (addr
, orig_addr
, sibcall_p
);
2727 && mips16_hard_float
2728 && build_mips16_call_stub (result
, addr
, args_size
,
2729 aux
== 0 ? 0 : (int) GET_MODE (aux
)))
2733 pattern
= (sibcall_p
2734 ? gen_sibcall_internal (addr
, args_size
)
2735 : gen_call_internal (addr
, args_size
));
2736 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
2740 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
2741 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
2744 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
2745 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
2748 pattern
= (sibcall_p
2749 ? gen_sibcall_value_internal (result
, addr
, args_size
)
2750 : gen_call_value_internal (result
, addr
, args_size
));
2752 insn
= emit_call_insn (pattern
);
2754 /* Lazy-binding stubs require $gp to be valid on entry. */
2755 if (global_got_operand (orig_addr
, VOIDmode
))
2756 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2760 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
2763 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
2764 tree exp ATTRIBUTE_UNUSED
)
2766 return TARGET_SIBCALLS
;
2769 /* Emit code to move general operand SRC into condition-code
2770 register DEST. SCRATCH is a scratch TFmode float register.
2777 where FP1 and FP2 are single-precision float registers
2778 taken from SCRATCH. */
2781 mips_emit_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
2785 /* Change the source to SFmode. */
2786 if (GET_CODE (src
) == MEM
)
2787 src
= adjust_address (src
, SFmode
, 0);
2788 else if (GET_CODE (src
) == REG
|| GET_CODE (src
) == SUBREG
)
2789 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
2791 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
2792 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + FP_INC
);
2794 emit_move_insn (copy_rtx (fp1
), src
);
2795 emit_move_insn (copy_rtx (fp2
), CONST0_RTX (SFmode
));
2796 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
2799 /* Emit code to change the current function's return address to
2800 ADDRESS. SCRATCH is available as a scratch register, if needed.
2801 ADDRESS and SCRATCH are both word-mode GPRs. */
2804 mips_set_return_address (rtx address
, rtx scratch
)
2808 compute_frame_size (get_frame_size ());
2809 if (((cfun
->machine
->frame
.mask
>> 31) & 1) == 0)
2811 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
2812 cfun
->machine
->frame
.gp_sp_offset
);
2814 emit_move_insn (gen_rtx_MEM (GET_MODE (address
), slot_address
), address
);
2817 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2818 Assume that the areas do not overlap. */
2821 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
2823 HOST_WIDE_INT offset
, delta
;
2824 unsigned HOST_WIDE_INT bits
;
2826 enum machine_mode mode
;
2829 /* Work out how many bits to move at a time. If both operands have
2830 half-word alignment, it is usually better to move in half words.
2831 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
2832 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
2833 Otherwise move word-sized chunks. */
2834 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
2835 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
2836 bits
= BITS_PER_WORD
/ 2;
2838 bits
= BITS_PER_WORD
;
2840 mode
= mode_for_size (bits
, MODE_INT
, 0);
2841 delta
= bits
/ BITS_PER_UNIT
;
2843 /* Allocate a buffer for the temporary registers. */
2844 regs
= alloca (sizeof (rtx
) * length
/ delta
);
2846 /* Load as many BITS-sized chunks as possible. Use a normal load if
2847 the source has enough alignment, otherwise use left/right pairs. */
2848 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2850 regs
[i
] = gen_reg_rtx (mode
);
2851 if (MEM_ALIGN (src
) >= bits
)
2852 emit_move_insn (regs
[i
], adjust_address (src
, mode
, offset
));
2855 rtx part
= adjust_address (src
, BLKmode
, offset
);
2856 if (!mips_expand_unaligned_load (regs
[i
], part
, bits
, 0))
2861 /* Copy the chunks to the destination. */
2862 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2863 if (MEM_ALIGN (dest
) >= bits
)
2864 emit_move_insn (adjust_address (dest
, mode
, offset
), regs
[i
]);
2867 rtx part
= adjust_address (dest
, BLKmode
, offset
);
2868 if (!mips_expand_unaligned_store (part
, regs
[i
], bits
, 0))
2872 /* Mop up any left-over bytes. */
2873 if (offset
< length
)
2875 src
= adjust_address (src
, BLKmode
, offset
);
2876 dest
= adjust_address (dest
, BLKmode
, offset
);
2877 move_by_pieces (dest
, src
, length
- offset
,
2878 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
2882 #define MAX_MOVE_REGS 4
2883 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2886 /* Helper function for doing a loop-based block operation on memory
2887 reference MEM. Each iteration of the loop will operate on LENGTH
2890 Create a new base register for use within the loop and point it to
2891 the start of MEM. Create a new memory reference that uses this
2892 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
2895 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
2896 rtx
*loop_reg
, rtx
*loop_mem
)
2898 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
2900 /* Although the new mem does not refer to a known location,
2901 it does keep up to LENGTH bytes of alignment. */
2902 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
2903 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
2907 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
2908 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
2909 memory regions do not overlap. */
2912 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
)
2914 rtx label
, src_reg
, dest_reg
, final_src
;
2915 HOST_WIDE_INT leftover
;
2917 leftover
= length
% MAX_MOVE_BYTES
;
2920 /* Create registers and memory references for use within the loop. */
2921 mips_adjust_block_mem (src
, MAX_MOVE_BYTES
, &src_reg
, &src
);
2922 mips_adjust_block_mem (dest
, MAX_MOVE_BYTES
, &dest_reg
, &dest
);
2924 /* Calculate the value that SRC_REG should have after the last iteration
2926 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
2929 /* Emit the start of the loop. */
2930 label
= gen_label_rtx ();
2933 /* Emit the loop body. */
2934 mips_block_move_straight (dest
, src
, MAX_MOVE_BYTES
);
2936 /* Move on to the next block. */
2937 emit_move_insn (src_reg
, plus_constant (src_reg
, MAX_MOVE_BYTES
));
2938 emit_move_insn (dest_reg
, plus_constant (dest_reg
, MAX_MOVE_BYTES
));
2940 /* Emit the loop condition. */
2941 if (Pmode
== DImode
)
2942 emit_insn (gen_cmpdi (src_reg
, final_src
));
2944 emit_insn (gen_cmpsi (src_reg
, final_src
));
2945 emit_jump_insn (gen_bne (label
));
2947 /* Mop up any left-over bytes. */
2949 mips_block_move_straight (dest
, src
, leftover
);
2952 /* Expand a movmemsi instruction. */
2955 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
2957 if (GET_CODE (length
) == CONST_INT
)
2959 if (INTVAL (length
) <= 2 * MAX_MOVE_BYTES
)
2961 mips_block_move_straight (dest
, src
, INTVAL (length
));
2966 mips_block_move_loop (dest
, src
, INTVAL (length
));
2973 /* Argument support functions. */
2975 /* Initialize CUMULATIVE_ARGS for a function. */
2978 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
2979 rtx libname ATTRIBUTE_UNUSED
)
2981 static CUMULATIVE_ARGS zero_cum
;
2982 tree param
, next_param
;
2985 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
2987 /* Determine if this function has variable arguments. This is
2988 indicated by the last argument being 'void_type_mode' if there
2989 are no variable arguments. The standard MIPS calling sequence
2990 passes all arguments in the general purpose registers in this case. */
2992 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
2993 param
!= 0; param
= next_param
)
2995 next_param
= TREE_CHAIN (param
);
2996 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
2997 cum
->gp_reg_found
= 1;
3002 /* Fill INFO with information about a single argument. CUM is the
3003 cumulative state for earlier arguments. MODE is the mode of this
3004 argument and TYPE is its type (if known). NAMED is true if this
3005 is a named (fixed) argument rather than a variable one. */
3008 mips_arg_info (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3009 tree type
, int named
, struct mips_arg_info
*info
)
3012 unsigned int num_bytes
, num_words
, max_regs
;
3014 /* Work out the size of the argument. */
3015 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
3016 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3018 /* Decide whether it should go in a floating-point register, assuming
3019 one is free. Later code checks for availability.
3021 The checks against UNITS_PER_FPVALUE handle the soft-float and
3022 single-float cases. */
3026 /* The EABI conventions have traditionally been defined in terms
3027 of TYPE_MODE, regardless of the actual type. */
3028 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3029 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3030 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3035 /* Only leading floating-point scalars are passed in
3036 floating-point registers. We also handle vector floats the same
3037 say, which is OK because they are not covered by the standard ABI. */
3038 info
->fpr_p
= (!cum
->gp_reg_found
3039 && cum
->arg_number
< 2
3040 && (type
== 0 || SCALAR_FLOAT_TYPE_P (type
)
3041 || VECTOR_FLOAT_TYPE_P (type
))
3042 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3043 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3044 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3049 /* Scalar and complex floating-point types are passed in
3050 floating-point registers. */
3051 info
->fpr_p
= (named
3052 && (type
== 0 || FLOAT_TYPE_P (type
))
3053 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3054 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3055 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3056 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3058 /* ??? According to the ABI documentation, the real and imaginary
3059 parts of complex floats should be passed in individual registers.
3060 The real and imaginary parts of stack arguments are supposed
3061 to be contiguous and there should be an extra word of padding
3064 This has two problems. First, it makes it impossible to use a
3065 single "void *" va_list type, since register and stack arguments
3066 are passed differently. (At the time of writing, MIPSpro cannot
3067 handle complex float varargs correctly.) Second, it's unclear
3068 what should happen when there is only one register free.
3070 For now, we assume that named complex floats should go into FPRs
3071 if there are two FPRs free, otherwise they should be passed in the
3072 same way as a struct containing two floats. */
3074 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3075 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
3077 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
3078 info
->fpr_p
= false;
3088 /* Now decide whether the argument must go in an even-numbered register.
3089 Usually this is determined by type alignment, but there are two
3092 - Under the O64 ABI, the second float argument goes in $f14 if it
3093 is single precision (doubles go in $f13 as expected).
3095 - Floats passed in FPRs must be in an even-numbered register if
3096 we're using paired FPRs. */
3098 even_reg_p
= TYPE_ALIGN (type
) > BITS_PER_WORD
;
3100 even_reg_p
= GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_WORD
;
3104 if (mips_abi
== ABI_O64
&& mode
== SFmode
)
3110 /* Set REG_OFFSET to the register count we're interested in.
3111 The EABI allocates the floating-point registers separately,
3112 but the other ABIs allocate them like integer registers. */
3113 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
3118 info
->reg_offset
+= info
->reg_offset
& 1;
3120 /* The alignment applied to registers is also applied to stack arguments. */
3121 info
->stack_offset
= cum
->stack_words
;
3123 info
->stack_offset
+= info
->stack_offset
& 1;
3125 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
3127 /* Partition the argument between registers and stack. */
3128 info
->reg_words
= MIN (num_words
, max_regs
);
3129 info
->stack_words
= num_words
- info
->reg_words
;
3133 /* Implement FUNCTION_ARG_ADVANCE. */
3136 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3137 tree type
, int named
)
3139 struct mips_arg_info info
;
3141 mips_arg_info (cum
, mode
, type
, named
, &info
);
3144 cum
->gp_reg_found
= true;
3146 /* See the comment above the cumulative args structure in mips.h
3147 for an explanation of what this code does. It assumes the O32
3148 ABI, which passes at most 2 arguments in float registers. */
3149 if (cum
->arg_number
< 2 && info
.fpr_p
)
3150 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
3152 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
3153 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
3154 else if (info
.reg_words
> 0)
3155 cum
->num_fprs
+= FP_INC
;
3157 if (info
.stack_words
> 0)
3158 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
3163 /* Implement FUNCTION_ARG. */
3166 function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3167 tree type
, int named
)
3169 struct mips_arg_info info
;
3171 /* We will be called with a mode of VOIDmode after the last argument
3172 has been seen. Whatever we return will be passed to the call
3173 insn. If we need a mips16 fp_code, return a REG with the code
3174 stored as the mode. */
3175 if (mode
== VOIDmode
)
3177 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
3178 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
3184 mips_arg_info (cum
, mode
, type
, named
, &info
);
3186 /* Return straight away if the whole argument is passed on the stack. */
3187 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
3191 && TREE_CODE (type
) == RECORD_TYPE
3193 && TYPE_SIZE_UNIT (type
)
3194 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
3197 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3198 structure contains a double in its entirety, then that 64 bit
3199 chunk is passed in a floating point register. */
3202 /* First check to see if there is any such field. */
3203 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3204 if (TREE_CODE (field
) == FIELD_DECL
3205 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3206 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3207 && host_integerp (bit_position (field
), 0)
3208 && int_bit_position (field
) % BITS_PER_WORD
== 0)
3213 /* Now handle the special case by returning a PARALLEL
3214 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3215 chunks are passed in registers. */
3217 HOST_WIDE_INT bitpos
;
3220 /* assign_parms checks the mode of ENTRY_PARM, so we must
3221 use the actual mode here. */
3222 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
3225 field
= TYPE_FIELDS (type
);
3226 for (i
= 0; i
< info
.reg_words
; i
++)
3230 for (; field
; field
= TREE_CHAIN (field
))
3231 if (TREE_CODE (field
) == FIELD_DECL
3232 && int_bit_position (field
) >= bitpos
)
3236 && int_bit_position (field
) == bitpos
3237 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3238 && !TARGET_SOFT_FLOAT
3239 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3240 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
3242 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
3245 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3246 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3248 bitpos
+= BITS_PER_WORD
;
3254 /* Handle the n32/n64 conventions for passing complex floating-point
3255 arguments in FPR pairs. The real part goes in the lower register
3256 and the imaginary part goes in the upper register. */
3259 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3262 enum machine_mode inner
;
3265 inner
= GET_MODE_INNER (mode
);
3266 reg
= FP_ARG_FIRST
+ info
.reg_offset
;
3267 real
= gen_rtx_EXPR_LIST (VOIDmode
,
3268 gen_rtx_REG (inner
, reg
),
3270 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
3271 gen_rtx_REG (inner
, reg
+ info
.reg_words
/ 2),
3272 GEN_INT (GET_MODE_SIZE (inner
)));
3273 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
3277 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
3279 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
3283 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3286 function_arg_partial_nregs (const CUMULATIVE_ARGS
*cum
,
3287 enum machine_mode mode
, tree type
, int named
)
3289 struct mips_arg_info info
;
3291 mips_arg_info (cum
, mode
, type
, named
, &info
);
3292 return info
.stack_words
> 0 ? info
.reg_words
: 0;
3296 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3297 upward rather than downward. In other words, return true if the
3298 first byte of the stack slot has useful data, false if the last
3302 mips_pad_arg_upward (enum machine_mode mode
, tree type
)
3304 /* On little-endian targets, the first byte of every stack argument
3305 is passed in the first byte of the stack slot. */
3306 if (!BYTES_BIG_ENDIAN
)
3309 /* Otherwise, integral types are padded downward: the last byte of a
3310 stack argument is passed in the last byte of the stack slot. */
3312 ? INTEGRAL_TYPE_P (type
) || POINTER_TYPE_P (type
)
3313 : GET_MODE_CLASS (mode
) == MODE_INT
)
3316 /* Big-endian o64 pads floating-point arguments downward. */
3317 if (mips_abi
== ABI_O64
)
3318 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3321 /* Other types are padded upward for o32, o64, n32 and n64. */
3322 if (mips_abi
!= ABI_EABI
)
3325 /* Arguments smaller than a stack slot are padded downward. */
3326 if (mode
!= BLKmode
)
3327 return (GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
);
3329 return (int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
));
3333 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3334 if the least significant byte of the register has useful data. Return
3335 the opposite if the most significant byte does. */
3338 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
3340 /* No shifting is required for floating-point arguments. */
3341 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3342 return !BYTES_BIG_ENDIAN
;
3344 /* Otherwise, apply the same padding to register arguments as we do
3345 to stack arguments. */
3346 return mips_pad_arg_upward (mode
, type
);
3350 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3351 tree type
, int *pretend_size
, int no_rtl
)
3353 CUMULATIVE_ARGS local_cum
;
3354 int gp_saved
, fp_saved
;
3356 /* The caller has advanced CUM up to, but not beyond, the last named
3357 argument. Advance a local copy of CUM past the last "real" named
3358 argument, to find out how many registers are left over. */
3361 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
3363 /* Found out how many registers we need to save. */
3364 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
3365 fp_saved
= (EABI_FLOAT_VARARGS_P
3366 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
3375 ptr
= virtual_incoming_args_rtx
;
3380 ptr
= plus_constant (ptr
, local_cum
.num_gprs
* UNITS_PER_WORD
);
3384 ptr
= plus_constant (ptr
, -gp_saved
* UNITS_PER_WORD
);
3387 mem
= gen_rtx_MEM (BLKmode
, ptr
);
3388 set_mem_alias_set (mem
, get_varargs_alias_set ());
3390 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
3395 /* We can't use move_block_from_reg, because it will use
3397 enum machine_mode mode
;
3400 /* Set OFF to the offset from virtual_incoming_args_rtx of
3401 the first float register. The FP save area lies below
3402 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3403 off
= -gp_saved
* UNITS_PER_WORD
;
3404 off
&= ~(UNITS_PER_FPVALUE
- 1);
3405 off
-= fp_saved
* UNITS_PER_FPREG
;
3407 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
3409 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
3413 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
3414 mem
= gen_rtx_MEM (mode
, ptr
);
3415 set_mem_alias_set (mem
, get_varargs_alias_set ());
3416 emit_move_insn (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
3417 off
+= UNITS_PER_HWFPVALUE
;
3423 /* No need for pretend arguments: the register parameter area was
3424 allocated by the caller. */
3428 *pretend_size
= (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_FPREG
);
3431 /* Create the va_list data type.
3432 We keep 3 pointers, and two offsets.
3433 Two pointers are to the overflow area, which starts at the CFA.
3434 One of these is constant, for addressing into the GPR save area below it.
3435 The other is advanced up the stack through the overflow region.
3436 The third pointer is to the GPR save area. Since the FPR save area
3437 is just below it, we can address FPR slots off this pointer.
3438 We also keep two one-byte offsets, which are to be subtracted from the
3439 constant pointers to yield addresses in the GPR and FPR save areas.
3440 These are downcounted as float or non-float arguments are used,
3441 and when they get to zero, the argument must be obtained from the
3443 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3444 pointer is enough. It's started at the GPR save area, and is
3446 Note that the GPR save area is not constant size, due to optimization
3447 in the prologue. Hence, we can't use a design with two pointers
3448 and two offsets, although we could have designed this with two pointers
3449 and three offsets. */
3452 mips_build_builtin_va_list (void)
3454 if (EABI_FLOAT_VARARGS_P
)
3456 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
3459 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
3461 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
3463 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
3465 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
3467 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
3468 unsigned_char_type_node
);
3469 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
3470 unsigned_char_type_node
);
3471 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3472 warn on every user file. */
3473 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
3474 array
= build_array_type (unsigned_char_type_node
,
3475 build_index_type (index
));
3476 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
3478 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
3479 DECL_FIELD_CONTEXT (f_gtop
) = record
;
3480 DECL_FIELD_CONTEXT (f_ftop
) = record
;
3481 DECL_FIELD_CONTEXT (f_goff
) = record
;
3482 DECL_FIELD_CONTEXT (f_foff
) = record
;
3483 DECL_FIELD_CONTEXT (f_res
) = record
;
3485 TYPE_FIELDS (record
) = f_ovfl
;
3486 TREE_CHAIN (f_ovfl
) = f_gtop
;
3487 TREE_CHAIN (f_gtop
) = f_ftop
;
3488 TREE_CHAIN (f_ftop
) = f_goff
;
3489 TREE_CHAIN (f_goff
) = f_foff
;
3490 TREE_CHAIN (f_foff
) = f_res
;
3492 layout_type (record
);
3495 else if (TARGET_IRIX
&& TARGET_IRIX6
)
3496 /* On IRIX 6, this type is 'char *'. */
3497 return build_pointer_type (char_type_node
);
3499 /* Otherwise, we use 'void *'. */
3500 return ptr_type_node
;
3503 /* Implement va_start. */
3506 mips_va_start (tree valist
, rtx nextarg
)
3508 const CUMULATIVE_ARGS
*cum
= ¤t_function_args_info
;
3510 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3511 since the stack is aligned for a pair of argument-passing slots,
3512 and the beginning of a variable argument list may be an odd slot,
3513 we have to decrease its alignment. */
3514 if (cfun
&& cfun
->emit
->regno_pointer_align
)
3515 while (((current_function_pretend_args_size
* BITS_PER_UNIT
)
3516 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) - 1)) != 0)
3517 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) /= 2;
3519 if (mips_abi
== ABI_EABI
)
3521 int gpr_save_area_size
;
3524 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
3526 if (EABI_FLOAT_VARARGS_P
)
3528 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
3529 tree ovfl
, gtop
, ftop
, goff
, foff
;
3532 int fpr_save_area_size
;
3534 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
3535 f_gtop
= TREE_CHAIN (f_ovfl
);
3536 f_ftop
= TREE_CHAIN (f_gtop
);
3537 f_goff
= TREE_CHAIN (f_ftop
);
3538 f_foff
= TREE_CHAIN (f_goff
);
3540 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
3542 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
3544 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
3546 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
3548 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
3551 /* Emit code to initialize OVFL, which points to the next varargs
3552 stack argument. CUM->STACK_WORDS gives the number of stack
3553 words used by named arguments. */
3554 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
3555 if (cum
->stack_words
> 0)
3556 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
3557 build_int_cst (NULL_TREE
,
3558 cum
->stack_words
* UNITS_PER_WORD
));
3559 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
3560 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3562 /* Emit code to initialize GTOP, the top of the GPR save area. */
3563 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
3564 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
3565 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3567 /* Emit code to initialize FTOP, the top of the FPR save area.
3568 This address is gpr_save_area_bytes below GTOP, rounded
3569 down to the next fp-aligned boundary. */
3570 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
3571 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
3572 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
3574 t
= build (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
3575 build_int_cst (NULL_TREE
, -fpr_offset
));
3576 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
3577 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3579 /* Emit code to initialize GOFF, the offset from GTOP of the
3580 next GPR argument. */
3581 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
3582 build_int_cst (NULL_TREE
, gpr_save_area_size
));
3583 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3585 /* Likewise emit code to initialize FOFF, the offset from FTOP
3586 of the next FPR argument. */
3588 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
3589 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
3590 build_int_cst (NULL_TREE
, fpr_save_area_size
));
3591 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3595 /* Everything is in the GPR save area, or in the overflow
3596 area which is contiguous with it. */
3597 nextarg
= plus_constant (nextarg
, -gpr_save_area_size
);
3598 std_expand_builtin_va_start (valist
, nextarg
);
3602 std_expand_builtin_va_start (valist
, nextarg
);
3605 /* Implement va_arg. */
3608 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
3610 HOST_WIDE_INT size
, rsize
;
3614 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
3617 type
= build_pointer_type (type
);
3619 size
= int_size_in_bytes (type
);
3620 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
3622 if (mips_abi
!= ABI_EABI
|| !EABI_FLOAT_VARARGS_P
)
3623 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
3626 /* Not a simple merged stack. */
3628 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
3629 tree ovfl
, top
, off
, align
;
3630 HOST_WIDE_INT osize
;
3633 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
3634 f_gtop
= TREE_CHAIN (f_ovfl
);
3635 f_ftop
= TREE_CHAIN (f_gtop
);
3636 f_goff
= TREE_CHAIN (f_ftop
);
3637 f_foff
= TREE_CHAIN (f_goff
);
3639 /* We maintain separate pointers and offsets for floating-point
3640 and integer arguments, but we need similar code in both cases.
3643 TOP be the top of the register save area;
3644 OFF be the offset from TOP of the next register;
3645 ADDR_RTX be the address of the argument;
3646 RSIZE be the number of bytes used to store the argument
3647 when it's in the register save area;
3648 OSIZE be the number of bytes used to store it when it's
3649 in the stack overflow area; and
3650 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
3652 The code we want is:
3654 1: off &= -rsize; // round down
3657 4: addr_rtx = top - off;
3662 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
3663 10: addr_rtx = ovfl + PADDING;
3667 [1] and [9] can sometimes be optimized away. */
3669 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
3672 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
3673 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
3675 top
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
3677 off
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
3680 /* When floating-point registers are saved to the stack,
3681 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
3682 of the float's precision. */
3683 rsize
= UNITS_PER_HWFPVALUE
;
3685 /* Overflow arguments are padded to UNITS_PER_WORD bytes
3686 (= PARM_BOUNDARY bits). This can be different from RSIZE
3689 (1) On 32-bit targets when TYPE is a structure such as:
3691 struct s { float f; };
3693 Such structures are passed in paired FPRs, so RSIZE
3694 will be 8 bytes. However, the structure only takes
3695 up 4 bytes of memory, so OSIZE will only be 4.
3697 (2) In combinations such as -mgp64 -msingle-float
3698 -fshort-double. Doubles passed in registers
3699 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
3700 but those passed on the stack take up
3701 UNITS_PER_WORD bytes. */
3702 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
3706 top
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
3708 off
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
3710 if (rsize
> UNITS_PER_WORD
)
3712 /* [1] Emit code for: off &= -rsize. */
3713 t
= build (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
3714 build_int_cst (NULL_TREE
, -rsize
));
3715 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
3716 gimplify_and_add (t
, pre_p
);
3721 /* [2] Emit code to branch if off == 0. */
3722 t
= lang_hooks
.truthvalue_conversion (off
);
3723 addr
= build (COND_EXPR
, ptr_type_node
, t
, NULL
, NULL
);
3725 /* [5] Emit code for: off -= rsize. We do this as a form of
3726 post-increment not available to C. Also widen for the
3727 coming pointer arithmetic. */
3728 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
3729 t
= build (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
3730 t
= fold_convert (sizetype
, t
);
3731 t
= fold_convert (TREE_TYPE (top
), t
);
3733 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
3734 the argument has RSIZE - SIZE bytes of leading padding. */
3735 t
= build (MINUS_EXPR
, TREE_TYPE (top
), top
, t
);
3736 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
3738 u
= fold_convert (TREE_TYPE (t
), build_int_cst (NULL_TREE
,
3740 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
3742 COND_EXPR_THEN (addr
) = t
;
3744 if (osize
> UNITS_PER_WORD
)
3746 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
3747 u
= fold_convert (TREE_TYPE (ovfl
),
3748 build_int_cst (NULL_TREE
, osize
- 1));
3749 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
3750 u
= fold_convert (TREE_TYPE (ovfl
),
3751 build_int_cst (NULL_TREE
, -osize
));
3752 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
, u
);
3753 align
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
3758 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
3759 post-increment ovfl by osize. On big-endian machines,
3760 the argument has OSIZE - SIZE bytes of leading padding. */
3761 u
= fold_convert (TREE_TYPE (ovfl
),
3762 build_int_cst (NULL_TREE
, osize
));
3763 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
3764 if (BYTES_BIG_ENDIAN
&& osize
> size
)
3766 u
= fold_convert (TREE_TYPE (t
),
3767 build_int_cst (NULL_TREE
, osize
- size
));
3768 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
3771 /* String [9] and [10,11] together. */
3773 t
= build (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
3774 COND_EXPR_ELSE (addr
) = t
;
3776 addr
= fold_convert (build_pointer_type (type
), addr
);
3777 addr
= build_fold_indirect_ref (addr
);
3781 addr
= build_fold_indirect_ref (addr
);
3786 /* Return true if it is possible to use left/right accesses for a
3787 bitfield of WIDTH bits starting BITPOS bits into *OP. When
3788 returning true, update *OP, *LEFT and *RIGHT as follows:
3790 *OP is a BLKmode reference to the whole field.
3792 *LEFT is a QImode reference to the first byte if big endian or
3793 the last byte if little endian. This address can be used in the
3794 left-side instructions (lwl, swl, ldl, sdl).
3796 *RIGHT is a QImode reference to the opposite end of the field and
3797 can be used in the parterning right-side instruction. */
3800 mips_get_unaligned_mem (rtx
*op
, unsigned int width
, int bitpos
,
3801 rtx
*left
, rtx
*right
)
3805 /* Check that the operand really is a MEM. Not all the extv and
3806 extzv predicates are checked. */
3807 if (GET_CODE (*op
) != MEM
)
3810 /* Check that the size is valid. */
3811 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
3814 /* We can only access byte-aligned values. Since we are always passed
3815 a reference to the first byte of the field, it is not necessary to
3816 do anything with BITPOS after this check. */
3817 if (bitpos
% BITS_PER_UNIT
!= 0)
3820 /* Reject aligned bitfields: we want to use a normal load or store
3821 instead of a left/right pair. */
3822 if (MEM_ALIGN (*op
) >= width
)
3825 /* Adjust *OP to refer to the whole field. This also has the effect
3826 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
3827 *op
= adjust_address (*op
, BLKmode
, 0);
3828 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
3830 /* Get references to both ends of the field. We deliberately don't
3831 use the original QImode *OP for FIRST since the new BLKmode one
3832 might have a simpler address. */
3833 first
= adjust_address (*op
, QImode
, 0);
3834 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
3836 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
3837 be the upper word and RIGHT the lower word. */
3838 if (TARGET_BIG_ENDIAN
)
3839 *left
= first
, *right
= last
;
3841 *left
= last
, *right
= first
;
3847 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
3848 Return true on success. We only handle cases where zero_extract is
3849 equivalent to sign_extract. */
3852 mips_expand_unaligned_load (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
3854 rtx left
, right
, temp
;
3856 /* If TARGET_64BIT, the destination of a 32-bit load will be a
3857 paradoxical word_mode subreg. This is the only case in which
3858 we allow the destination to be larger than the source. */
3859 if (GET_CODE (dest
) == SUBREG
3860 && GET_MODE (dest
) == DImode
3861 && SUBREG_BYTE (dest
) == 0
3862 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
3863 dest
= SUBREG_REG (dest
);
3865 /* After the above adjustment, the destination must be the same
3866 width as the source. */
3867 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
3870 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
3873 temp
= gen_reg_rtx (GET_MODE (dest
));
3874 if (GET_MODE (dest
) == DImode
)
3876 emit_insn (gen_mov_ldl (temp
, src
, left
));
3877 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
3881 emit_insn (gen_mov_lwl (temp
, src
, left
));
3882 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
3888 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
3892 mips_expand_unaligned_store (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
3896 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
3899 src
= gen_lowpart (mode_for_size (width
, MODE_INT
, 0), src
);
3901 if (GET_MODE (src
) == DImode
)
3903 emit_insn (gen_mov_sdl (dest
, src
, left
));
3904 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
3908 emit_insn (gen_mov_swl (dest
, src
, left
));
3909 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
3914 /* Set up globals to generate code for the ISA or processor
3915 described by INFO. */
3918 mips_set_architecture (const struct mips_cpu_info
*info
)
3922 mips_arch_info
= info
;
3923 mips_arch
= info
->cpu
;
3924 mips_isa
= info
->isa
;
3929 /* Likewise for tuning. */
3932 mips_set_tune (const struct mips_cpu_info
*info
)
3936 mips_tune_info
= info
;
3937 mips_tune
= info
->cpu
;
3942 /* Set up the threshold for data to go into the small data area, instead
3943 of the normal data area, and detect any conflicts in the switches. */
3946 override_options (void)
3948 int i
, start
, regno
;
3949 enum machine_mode mode
;
3951 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3953 /* Interpret -mabi. */
3954 mips_abi
= MIPS_ABI_DEFAULT
;
3955 if (mips_abi_string
!= 0)
3957 if (strcmp (mips_abi_string
, "32") == 0)
3959 else if (strcmp (mips_abi_string
, "o64") == 0)
3961 else if (strcmp (mips_abi_string
, "n32") == 0)
3963 else if (strcmp (mips_abi_string
, "64") == 0)
3965 else if (strcmp (mips_abi_string
, "eabi") == 0)
3966 mips_abi
= ABI_EABI
;
3968 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3971 /* The following code determines the architecture and register size.
3972 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
3973 The GAS and GCC code should be kept in sync as much as possible. */
3975 if (mips_arch_string
!= 0)
3976 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
3978 if (mips_isa_string
!= 0)
3980 /* Handle -mipsN. */
3981 char *whole_isa_str
= concat ("mips", mips_isa_string
, NULL
);
3982 const struct mips_cpu_info
*isa_info
;
3984 isa_info
= mips_parse_cpu ("-mips option", whole_isa_str
);
3985 free (whole_isa_str
);
3987 /* -march takes precedence over -mipsN, since it is more descriptive.
3988 There's no harm in specifying both as long as the ISA levels
3990 if (mips_arch_info
!= 0 && mips_isa
!= isa_info
->isa
)
3991 error ("-mips%s conflicts with the other architecture options, "
3992 "which specify a MIPS%d processor",
3993 mips_isa_string
, mips_isa
);
3995 /* Set architecture based on the given option. */
3996 mips_set_architecture (isa_info
);
3999 if (mips_arch_info
== 0)
4001 #ifdef MIPS_CPU_STRING_DEFAULT
4002 mips_set_architecture (mips_parse_cpu ("default CPU",
4003 MIPS_CPU_STRING_DEFAULT
));
4005 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
4009 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
4010 error ("-march=%s is not compatible with the selected ABI",
4011 mips_arch_info
->name
);
4013 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4014 if (mips_tune_string
!= 0)
4015 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
4017 if (mips_tune_info
== 0)
4018 mips_set_tune (mips_arch_info
);
4020 if ((target_flags_explicit
& MASK_64BIT
) != 0)
4022 /* The user specified the size of the integer registers. Make sure
4023 it agrees with the ABI and ISA. */
4024 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
4025 error ("-mgp64 used with a 32-bit processor");
4026 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
4027 error ("-mgp32 used with a 64-bit ABI");
4028 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
4029 error ("-mgp64 used with a 32-bit ABI");
4033 /* Infer the integer register size from the ABI and processor.
4034 Restrict ourselves to 32-bit registers if that's all the
4035 processor has, or if the ABI cannot handle 64-bit registers. */
4036 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
4037 target_flags
&= ~MASK_64BIT
;
4039 target_flags
|= MASK_64BIT
;
4042 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
4044 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4045 only one right answer here. */
4046 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
4047 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4048 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
4049 error ("unsupported combination: %s", "-mgp32 -mfp64");
4050 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
4051 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4055 /* -msingle-float selects 32-bit float registers. Otherwise the
4056 float registers should be the same size as the integer ones. */
4057 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
4058 target_flags
|= MASK_FLOAT64
;
4060 target_flags
&= ~MASK_FLOAT64
;
4063 /* End of code shared with GAS. */
4065 if ((target_flags_explicit
& MASK_LONG64
) == 0)
4067 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4068 were used, then set the type sizes. In the EABI in 64 bit mode,
4069 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4071 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
4072 target_flags
|= MASK_LONG64
;
4074 target_flags
&= ~MASK_LONG64
;
4077 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4078 && (target_flags_explicit
& MASK_SOFT_FLOAT
) == 0)
4080 /* For some configurations, it is useful to have -march control
4081 the default setting of MASK_SOFT_FLOAT. */
4082 switch ((int) mips_arch
)
4084 case PROCESSOR_R4100
:
4085 case PROCESSOR_R4111
:
4086 case PROCESSOR_R4120
:
4087 case PROCESSOR_R4130
:
4088 target_flags
|= MASK_SOFT_FLOAT
;
4092 target_flags
&= ~MASK_SOFT_FLOAT
;
4098 flag_pcc_struct_return
= 0;
4100 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
4102 /* If neither -mbranch-likely nor -mno-branch-likely was given
4103 on the command line, set MASK_BRANCHLIKELY based on the target
4106 By default, we enable use of Branch Likely instructions on
4107 all architectures which support them with the following
4108 exceptions: when creating MIPS32 or MIPS64 code, and when
4109 tuning for architectures where their use tends to hurt
4112 The MIPS32 and MIPS64 architecture specifications say "Software
4113 is strongly encouraged to avoid use of Branch Likely
4114 instructions, as they will be removed from a future revision
4115 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4116 issue those instructions unless instructed to do so by
4118 if (ISA_HAS_BRANCHLIKELY
4119 && !(ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64
)
4120 && !(TUNE_MIPS5500
|| TUNE_SB1
))
4121 target_flags
|= MASK_BRANCHLIKELY
;
4123 target_flags
&= ~MASK_BRANCHLIKELY
;
4125 if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
4126 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4128 /* The effect of -mabicalls isn't defined for the EABI. */
4129 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
4131 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4132 target_flags
&= ~MASK_ABICALLS
;
4135 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4136 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4137 /* ??? -non_shared turns off pic code generation, but this is not
4139 if (TARGET_ABICALLS
)
4142 if (mips_section_threshold
> 0)
4143 warning ("-G is incompatible with PIC code which is the default");
4146 /* mips_split_addresses is a half-way house between explicit
4147 relocations and the traditional assembler macros. It can
4148 split absolute 32-bit symbolic constants into a high/lo_sum
4149 pair but uses macros for other sorts of access.
4151 Like explicit relocation support for REL targets, it relies
4152 on GNU extensions in the assembler and the linker.
4154 Although this code should work for -O0, it has traditionally
4155 been treated as an optimization. */
4156 if (!TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
4157 && optimize
&& !flag_pic
4158 && !ABI_HAS_64BIT_SYMBOLS
)
4159 mips_split_addresses
= 1;
4161 mips_split_addresses
= 0;
4163 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4164 faster code, but at the expense of more nops. Enable it at -O3 and
4166 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
4167 target_flags
|= MASK_VR4130_ALIGN
;
4169 /* When compiling for the mips16, we cannot use floating point. We
4170 record the original hard float value in mips16_hard_float. */
4173 if (TARGET_SOFT_FLOAT
)
4174 mips16_hard_float
= 0;
4176 mips16_hard_float
= 1;
4177 target_flags
|= MASK_SOFT_FLOAT
;
4179 /* Don't run the scheduler before reload, since it tends to
4180 increase register pressure. */
4181 flag_schedule_insns
= 0;
4183 /* Don't do hot/cold partitioning. The constant layout code expects
4184 the whole function to be in a single section. */
4185 flag_reorder_blocks_and_partition
= 0;
4187 /* Silently disable -mexplicit-relocs since it doesn't apply
4188 to mips16 code. Even so, it would overly pedantic to warn
4189 about "-mips16 -mexplicit-relocs", especially given that
4190 we use a %gprel() operator. */
4191 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
4194 /* When using explicit relocs, we call dbr_schedule from within
4196 if (TARGET_EXPLICIT_RELOCS
)
4198 mips_flag_delayed_branch
= flag_delayed_branch
;
4199 flag_delayed_branch
= 0;
4202 #ifdef MIPS_TFMODE_FORMAT
4203 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
4206 /* Make sure that the user didn't turn off paired single support when
4207 MIPS-3D support is requested. */
4208 if (TARGET_MIPS3D
&& (target_flags_explicit
& MASK_PAIRED_SINGLE
)
4209 && !TARGET_PAIRED_SINGLE_FLOAT
)
4210 error ("-mips3d requires -mpaired-single");
4212 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE. */
4214 target_flags
|= MASK_PAIRED_SINGLE
;
4216 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4217 and TARGET_HARD_FLOAT are both true. */
4218 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT
))
4219 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4221 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4223 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_MIPS64
)
4224 error ("-mips3d/-mpaired-single must be used with -mips64");
4226 mips_print_operand_punct
['?'] = 1;
4227 mips_print_operand_punct
['#'] = 1;
4228 mips_print_operand_punct
['/'] = 1;
4229 mips_print_operand_punct
['&'] = 1;
4230 mips_print_operand_punct
['!'] = 1;
4231 mips_print_operand_punct
['*'] = 1;
4232 mips_print_operand_punct
['@'] = 1;
4233 mips_print_operand_punct
['.'] = 1;
4234 mips_print_operand_punct
['('] = 1;
4235 mips_print_operand_punct
[')'] = 1;
4236 mips_print_operand_punct
['['] = 1;
4237 mips_print_operand_punct
[']'] = 1;
4238 mips_print_operand_punct
['<'] = 1;
4239 mips_print_operand_punct
['>'] = 1;
4240 mips_print_operand_punct
['{'] = 1;
4241 mips_print_operand_punct
['}'] = 1;
4242 mips_print_operand_punct
['^'] = 1;
4243 mips_print_operand_punct
['$'] = 1;
4244 mips_print_operand_punct
['+'] = 1;
4245 mips_print_operand_punct
['~'] = 1;
4247 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
4248 mips_char_to_class
['t'] = T_REG
;
4249 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
4250 mips_char_to_class
['h'] = HI_REG
;
4251 mips_char_to_class
['l'] = LO_REG
;
4252 mips_char_to_class
['x'] = MD_REGS
;
4253 mips_char_to_class
['b'] = ALL_REGS
;
4254 mips_char_to_class
['c'] = (TARGET_ABICALLS
? PIC_FN_ADDR_REG
:
4255 TARGET_MIPS16
? M16_NA_REGS
:
4257 mips_char_to_class
['e'] = LEA_REGS
;
4258 mips_char_to_class
['j'] = PIC_FN_ADDR_REG
;
4259 mips_char_to_class
['y'] = GR_REGS
;
4260 mips_char_to_class
['z'] = ST_REGS
;
4261 mips_char_to_class
['B'] = COP0_REGS
;
4262 mips_char_to_class
['C'] = COP2_REGS
;
4263 mips_char_to_class
['D'] = COP3_REGS
;
4265 /* Set up array to map GCC register number to debug register number.
4266 Ignore the special purpose register numbers. */
4268 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4269 mips_dbx_regno
[i
] = -1;
4271 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
4272 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
4273 mips_dbx_regno
[i
] = i
+ start
;
4275 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
4276 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
4277 mips_dbx_regno
[i
] = i
+ start
;
4279 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
4280 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
4282 /* Set up array giving whether a given register can hold a given mode. */
4284 for (mode
= VOIDmode
;
4285 mode
!= MAX_MACHINE_MODE
;
4286 mode
= (enum machine_mode
) ((int)mode
+ 1))
4288 register int size
= GET_MODE_SIZE (mode
);
4289 register enum mode_class
class = GET_MODE_CLASS (mode
);
4291 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4295 if (mode
== CCV2mode
)
4298 && (regno
- ST_REG_FIRST
) % 2 == 0);
4300 else if (mode
== CCV4mode
)
4303 && (regno
- ST_REG_FIRST
) % 4 == 0);
4305 else if (mode
== CCmode
)
4308 temp
= (regno
== FPSW_REGNUM
);
4310 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
4311 || FP_REG_P (regno
));
4314 else if (GP_REG_P (regno
))
4315 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
4317 else if (FP_REG_P (regno
))
4318 temp
= ((regno
% FP_INC
) == 0)
4319 && (((class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
4320 || class == MODE_VECTOR_FLOAT
)
4321 && size
<= UNITS_PER_FPVALUE
)
4322 /* Allow integer modes that fit into a single
4323 register. We need to put integers into FPRs
4324 when using instructions like cvt and trunc. */
4325 || (class == MODE_INT
&& size
<= UNITS_PER_FPREG
)
4326 /* Allow TFmode for CCmode reloads. */
4327 || (ISA_HAS_8CC
&& mode
== TFmode
));
4329 else if (MD_REG_P (regno
))
4330 temp
= (INTEGRAL_MODE_P (mode
)
4331 && (size
<= UNITS_PER_WORD
4332 || (regno
== MD_REG_FIRST
4333 && size
== 2 * UNITS_PER_WORD
)));
4335 else if (ALL_COP_REG_P (regno
))
4336 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
4340 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
4344 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4345 initialized yet, so we can't use that here. */
4346 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
4348 /* Provide default values for align_* for 64-bit targets. */
4349 if (TARGET_64BIT
&& !TARGET_MIPS16
)
4351 if (align_loops
== 0)
4353 if (align_jumps
== 0)
4355 if (align_functions
== 0)
4356 align_functions
= 8;
4359 /* Function to allocate machine-dependent function status. */
4360 init_machine_status
= &mips_init_machine_status
;
4362 if (ABI_HAS_64BIT_SYMBOLS
)
4364 if (TARGET_EXPLICIT_RELOCS
)
4366 mips_split_p
[SYMBOL_64_HIGH
] = true;
4367 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
4368 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
4370 mips_split_p
[SYMBOL_64_MID
] = true;
4371 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
4372 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
4374 mips_split_p
[SYMBOL_64_LOW
] = true;
4375 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
4376 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
4378 mips_split_p
[SYMBOL_GENERAL
] = true;
4379 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
4384 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses
)
4386 mips_split_p
[SYMBOL_GENERAL
] = true;
4387 mips_hi_relocs
[SYMBOL_GENERAL
] = "%hi(";
4388 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
4394 /* The high part is provided by a pseudo copy of $gp. */
4395 mips_split_p
[SYMBOL_SMALL_DATA
] = true;
4396 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gprel(";
4399 if (TARGET_EXPLICIT_RELOCS
)
4401 /* Small data constants are kept whole until after reload,
4402 then lowered by mips_rewrite_small_data. */
4403 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gp_rel(";
4405 mips_split_p
[SYMBOL_GOT_LOCAL
] = true;
4408 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
4409 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%got_ofst(";
4413 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
4414 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%lo(";
4419 /* The HIGH and LO_SUM are matched by special .md patterns. */
4420 mips_split_p
[SYMBOL_GOT_GLOBAL
] = true;
4422 mips_split_p
[SYMBOL_GOTOFF_GLOBAL
] = true;
4423 mips_hi_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_hi(";
4424 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_lo(";
4426 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
4427 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
4428 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
4433 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_disp(";
4435 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got(";
4436 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
4442 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
4443 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
4444 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
4447 /* Default to working around R4000 errata only if the processor
4448 was selected explicitly. */
4449 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
4450 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
4451 target_flags
|= MASK_FIX_R4000
;
4453 /* Default to working around R4400 errata only if the processor
4454 was selected explicitly. */
4455 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
4456 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
4457 target_flags
|= MASK_FIX_R4400
;
4460 /* Implement CONDITIONAL_REGISTER_USAGE. */
4463 mips_conditional_register_usage (void)
4465 if (!TARGET_HARD_FLOAT
)
4469 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4470 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4471 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
4472 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4474 else if (! ISA_HAS_8CC
)
4478 /* We only have a single condition code register. We
4479 implement this by hiding all the condition code registers,
4480 and generating RTL that refers directly to ST_REG_FIRST. */
4481 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
4482 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4484 /* In mips16 mode, we permit the $t temporary registers to be used
4485 for reload. We prohibit the unused $s registers, since they
4486 are caller saved, and saving them via a mips16 register would
4487 probably waste more time than just reloading the value. */
4490 fixed_regs
[18] = call_used_regs
[18] = 1;
4491 fixed_regs
[19] = call_used_regs
[19] = 1;
4492 fixed_regs
[20] = call_used_regs
[20] = 1;
4493 fixed_regs
[21] = call_used_regs
[21] = 1;
4494 fixed_regs
[22] = call_used_regs
[22] = 1;
4495 fixed_regs
[23] = call_used_regs
[23] = 1;
4496 fixed_regs
[26] = call_used_regs
[26] = 1;
4497 fixed_regs
[27] = call_used_regs
[27] = 1;
4498 fixed_regs
[30] = call_used_regs
[30] = 1;
4500 /* fp20-23 are now caller saved. */
4501 if (mips_abi
== ABI_64
)
4504 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
4505 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
4507 /* Odd registers from fp21 to fp31 are now caller saved. */
4508 if (mips_abi
== ABI_N32
)
4511 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
4512 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
4516 /* Allocate a chunk of memory for per-function machine-dependent data. */
4517 static struct machine_function
*
4518 mips_init_machine_status (void)
4520 return ((struct machine_function
*)
4521 ggc_alloc_cleared (sizeof (struct machine_function
)));
4524 /* On the mips16, we want to allocate $24 (T_REG) before other
4525 registers for instructions for which it is possible. This helps
4526 avoid shuffling registers around in order to set up for an xor,
4527 encouraging the compiler to use a cmp instead. */
4530 mips_order_regs_for_local_alloc (void)
4534 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4535 reg_alloc_order
[i
] = i
;
4539 /* It really doesn't matter where we put register 0, since it is
4540 a fixed register anyhow. */
4541 reg_alloc_order
[0] = 24;
4542 reg_alloc_order
[24] = 0;
4547 /* The MIPS debug format wants all automatic variables and arguments
4548 to be in terms of the virtual frame pointer (stack pointer before
4549 any adjustment in the function), while the MIPS 3.0 linker wants
4550 the frame pointer to be the stack pointer after the initial
4551 adjustment. So, we do the adjustment here. The arg pointer (which
4552 is eliminated) points to the virtual frame pointer, while the frame
4553 pointer (which may be eliminated) points to the stack pointer after
4554 the initial adjustments. */
4557 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
4559 rtx offset2
= const0_rtx
;
4560 rtx reg
= eliminate_constant_term (addr
, &offset2
);
4563 offset
= INTVAL (offset2
);
4565 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
4566 || reg
== hard_frame_pointer_rtx
)
4568 HOST_WIDE_INT frame_size
= (!cfun
->machine
->frame
.initialized
)
4569 ? compute_frame_size (get_frame_size ())
4570 : cfun
->machine
->frame
.total_size
;
4572 /* MIPS16 frame is smaller */
4573 if (frame_pointer_needed
&& TARGET_MIPS16
)
4574 frame_size
-= cfun
->machine
->frame
.args_size
;
4576 offset
= offset
- frame_size
;
4579 /* sdbout_parms does not want this to crash for unrecognized cases. */
4581 else if (reg
!= arg_pointer_rtx
)
4582 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
4589 /* A helper function for print_operand. This prints out a floating point
4590 condition code register. OP is the operand we are printing. CODE is the
4591 rtx code of OP. ALIGN is the required register alignment for OP. OFFSET
4592 is the index into operand for multiple register operands. If IGNORE is
4593 true, then we only print the register name if it isn't fcc0, and we
4594 follow it with a comma. */
4597 print_fcc_operand (FILE *file
, rtx op
, enum rtx_code code
,
4598 int align
, int offset
, int ignore
)
4605 regnum
= REGNO (op
);
4606 if (!ST_REG_P (regnum
)
4607 || (regnum
- ST_REG_FIRST
) % align
!= 0)
4610 if (!ignore
|| regnum
!= ST_REG_FIRST
)
4611 fprintf (file
, "%s%s", reg_names
[regnum
+offset
], (ignore
? "," : ""));
4614 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
4616 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4617 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4618 'h' OP is HIGH, prints %hi(X),
4619 'd' output integer constant in decimal,
4620 'z' if the operand is 0, use $0 instead of normal operand.
4621 'D' print second part of double-word register or memory operand.
4622 'L' print low-order register of double-word register operand.
4623 'M' print high-order register of double-word register operand.
4624 'C' print part of opcode for a branch condition.
4625 'F' print part of opcode for a floating-point branch condition.
4626 'N' print part of opcode for a branch condition, inverted.
4627 'W' print part of opcode for a floating-point branch condition, inverted.
4628 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
4629 'z' for (eq:?I ...), 'n' for (ne:?I ...).
4630 't' like 'T', but with the EQ/NE cases reversed
4631 'Z' print register and a comma, but print nothing for $fcc0
4632 'R' print the reloc associated with LO_SUM
4633 'V' Check if the fcc register number divided by 4 is zero. Then print
4634 the fcc register plus 2.
4635 'v' Check if the fcc register number divided by 4 is zero. Then print
4637 'Q' print the fcc register.
4639 The punctuation characters are:
4641 '(' Turn on .set noreorder
4642 ')' Turn on .set reorder
4643 '[' Turn on .set noat
4645 '<' Turn on .set nomacro
4646 '>' Turn on .set macro
4647 '{' Turn on .set volatile (not GAS)
4648 '}' Turn on .set novolatile (not GAS)
4649 '&' Turn on .set noreorder if filling delay slots
4650 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4651 '!' Turn on .set nomacro if filling delay slots
4652 '#' Print nop if in a .set noreorder section.
4653 '/' Like '#', but does nothing within a delayed branch sequence
4654 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4655 '@' Print the name of the assembler temporary register (at or $1).
4656 '.' Print the name of the register with a hard-wired zero (zero or $0).
4657 '^' Print the name of the pic call-through register (t9 or $25).
4658 '$' Print the name of the stack pointer register (sp or $29).
4659 '+' Print the name of the gp register (usually gp or $28).
4660 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
4663 print_operand (FILE *file
, rtx op
, int letter
)
4665 register enum rtx_code code
;
4667 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
4672 if (mips_branch_likely
)
4677 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
4681 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
4685 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
4689 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
4693 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
4697 if (final_sequence
!= 0 && set_noreorder
++ == 0)
4698 fputs (".set\tnoreorder\n\t", file
);
4702 if (final_sequence
!= 0)
4704 if (set_noreorder
++ == 0)
4705 fputs (".set\tnoreorder\n\t", file
);
4707 if (set_nomacro
++ == 0)
4708 fputs (".set\tnomacro\n\t", file
);
4713 if (final_sequence
!= 0 && set_nomacro
++ == 0)
4714 fputs ("\n\t.set\tnomacro", file
);
4718 if (set_noreorder
!= 0)
4719 fputs ("\n\tnop", file
);
4723 /* Print an extra newline so that the delayed insn is separated
4724 from the following ones. This looks neater and is consistent
4725 with non-nop delayed sequences. */
4726 if (set_noreorder
!= 0 && final_sequence
== 0)
4727 fputs ("\n\tnop\n", file
);
4731 if (set_noreorder
++ == 0)
4732 fputs (".set\tnoreorder\n\t", file
);
4736 if (set_noreorder
== 0)
4737 error ("internal error: %%) found without a %%( in assembler pattern");
4739 else if (--set_noreorder
== 0)
4740 fputs ("\n\t.set\treorder", file
);
4745 if (set_noat
++ == 0)
4746 fputs (".set\tnoat\n\t", file
);
4751 error ("internal error: %%] found without a %%[ in assembler pattern");
4752 else if (--set_noat
== 0)
4753 fputs ("\n\t.set\tat", file
);
4758 if (set_nomacro
++ == 0)
4759 fputs (".set\tnomacro\n\t", file
);
4763 if (set_nomacro
== 0)
4764 error ("internal error: %%> found without a %%< in assembler pattern");
4765 else if (--set_nomacro
== 0)
4766 fputs ("\n\t.set\tmacro", file
);
4771 if (set_volatile
++ == 0)
4772 fputs ("#.set\tvolatile\n\t", file
);
4776 if (set_volatile
== 0)
4777 error ("internal error: %%} found without a %%{ in assembler pattern");
4778 else if (--set_volatile
== 0)
4779 fputs ("\n\t#.set\tnovolatile", file
);
4785 if (align_labels_log
> 0)
4786 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
4791 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
4800 error ("PRINT_OPERAND null pointer");
4804 code
= GET_CODE (op
);
4809 case EQ
: fputs ("eq", file
); break;
4810 case NE
: fputs ("ne", file
); break;
4811 case GT
: fputs ("gt", file
); break;
4812 case GE
: fputs ("ge", file
); break;
4813 case LT
: fputs ("lt", file
); break;
4814 case LE
: fputs ("le", file
); break;
4815 case GTU
: fputs ("gtu", file
); break;
4816 case GEU
: fputs ("geu", file
); break;
4817 case LTU
: fputs ("ltu", file
); break;
4818 case LEU
: fputs ("leu", file
); break;
4820 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op
);
4823 else if (letter
== 'N')
4826 case EQ
: fputs ("ne", file
); break;
4827 case NE
: fputs ("eq", file
); break;
4828 case GT
: fputs ("le", file
); break;
4829 case GE
: fputs ("lt", file
); break;
4830 case LT
: fputs ("ge", file
); break;
4831 case LE
: fputs ("gt", file
); break;
4832 case GTU
: fputs ("leu", file
); break;
4833 case GEU
: fputs ("ltu", file
); break;
4834 case LTU
: fputs ("geu", file
); break;
4835 case LEU
: fputs ("gtu", file
); break;
4837 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op
);
4840 else if (letter
== 'F')
4843 case EQ
: fputs ("c1f", file
); break;
4844 case NE
: fputs ("c1t", file
); break;
4846 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op
);
4849 else if (letter
== 'W')
4852 case EQ
: fputs ("c1t", file
); break;
4853 case NE
: fputs ("c1f", file
); break;
4855 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op
);
4858 else if (letter
== 'h')
4860 if (GET_CODE (op
) == HIGH
)
4863 print_operand_reloc (file
, op
, mips_hi_relocs
);
4866 else if (letter
== 'R')
4867 print_operand_reloc (file
, op
, mips_lo_relocs
);
4869 else if (letter
== 'Z')
4870 print_fcc_operand (file
, op
, code
, 1, 0, 1);
4872 else if (letter
== 'V')
4873 print_fcc_operand (file
, op
, code
, 4, 2, 0);
4875 else if (letter
== 'v')
4876 print_fcc_operand (file
, op
, code
, 4, 0, 0);
4878 else if (letter
== 'Q')
4879 print_fcc_operand (file
, op
, code
, 1, 0, 0);
4881 else if (code
== REG
|| code
== SUBREG
)
4883 register int regnum
;
4886 regnum
= REGNO (op
);
4888 regnum
= true_regnum (op
);
4890 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4891 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4895 fprintf (file
, "%s", reg_names
[regnum
]);
4898 else if (code
== MEM
)
4901 output_address (plus_constant (XEXP (op
, 0), 4));
4903 output_address (XEXP (op
, 0));
4906 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
4907 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
4909 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
4910 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
4912 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
4913 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
4915 else if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
4916 fputs (reg_names
[GP_REG_FIRST
], file
);
4918 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4919 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
4921 else if (letter
== 'T' || letter
== 't')
4923 int truth
= (code
== NE
) == (letter
== 'T');
4924 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
4927 else if (CONST_GP_P (op
))
4928 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
4931 output_addr_const (file
, op
);
4935 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
4936 RELOCS is the array of relocations to use. */
4939 print_operand_reloc (FILE *file
, rtx op
, const char **relocs
)
4941 enum mips_symbol_type symbol_type
;
4944 HOST_WIDE_INT offset
;
4946 if (!mips_symbolic_constant_p (op
, &symbol_type
) || relocs
[symbol_type
] == 0)
4947 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op
);
4949 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
4950 mips_split_const (op
, &base
, &offset
);
4951 if (UNSPEC_ADDRESS_P (base
))
4952 op
= plus_constant (UNSPEC_ADDRESS (base
), offset
);
4954 fputs (relocs
[symbol_type
], file
);
4955 output_addr_const (file
, op
);
4956 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
4961 /* Output address operand X to FILE. */
4964 print_operand_address (FILE *file
, rtx x
)
4966 struct mips_address_info addr
;
4968 if (mips_classify_address (&addr
, x
, word_mode
, true))
4972 print_operand (file
, addr
.offset
, 0);
4973 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
4976 case ADDRESS_LO_SUM
:
4977 print_operand (file
, addr
.offset
, 'R');
4978 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
4981 case ADDRESS_CONST_INT
:
4982 output_addr_const (file
, x
);
4983 fprintf (file
, "(%s)", reg_names
[0]);
4986 case ADDRESS_SYMBOLIC
:
4987 output_addr_const (file
, x
);
4993 /* When using assembler macros, keep track of all of small-data externs
4994 so that mips_file_end can emit the appropriate declarations for them.
4996 In most cases it would be safe (though pointless) to emit .externs
4997 for other symbols too. One exception is when an object is within
4998 the -G limit but declared by the user to be in a section other
4999 than .sbss or .sdata. */
5002 mips_output_external (FILE *file ATTRIBUTE_UNUSED
, tree decl
, const char *name
)
5004 register struct extern_list
*p
;
5006 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
5008 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5009 p
->next
= extern_head
;
5011 p
->size
= int_size_in_bytes (TREE_TYPE (decl
));
5015 if (TARGET_IRIX
&& mips_abi
== ABI_32
&& TREE_CODE (decl
) == FUNCTION_DECL
)
5017 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5018 p
->next
= extern_head
;
5029 irix_output_external_libcall (rtx fun
)
5031 register struct extern_list
*p
;
5033 if (mips_abi
== ABI_32
)
5035 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5036 p
->next
= extern_head
;
5037 p
->name
= XSTR (fun
, 0);
5044 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5045 put out a MIPS ECOFF file and a stab. */
5048 mips_output_filename (FILE *stream
, const char *name
)
5050 char ltext_label_name
[100];
5052 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5054 if (write_symbols
== DWARF2_DEBUG
)
5056 else if (mips_output_filename_first_time
)
5058 mips_output_filename_first_time
= 0;
5059 num_source_filenames
+= 1;
5060 current_function_file
= name
;
5061 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5064 else if (write_symbols
== DBX_DEBUG
)
5066 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
5067 fputs ("\t.stabs\t", stream
);
5068 output_quoted_string (stream
, name
);
5069 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
5072 else if (name
!= current_function_file
5073 && strcmp (name
, current_function_file
) != 0)
5075 num_source_filenames
+= 1;
5076 current_function_file
= name
;
5077 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5081 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5082 as well as a .loc, since it is possible that MIPS ECOFF might not be
5083 able to represent the location for inlines that come from a different
5087 mips_output_lineno (FILE *stream
, int line
)
5089 if (write_symbols
== DBX_DEBUG
)
5092 fprintf (stream
, "%sLM%d:\n\t.stabn\t%d,0,%d,%sLM%d\n",
5093 LOCAL_LABEL_PREFIX
, sym_lineno
, N_SLINE
, line
,
5094 LOCAL_LABEL_PREFIX
, sym_lineno
);
5098 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
5102 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5103 that should be written before the opening quote, such as "\t.ascii\t"
5104 for real string data or "\t# " for a comment. */
5107 mips_output_ascii (FILE *stream
, const char *string_param
, size_t len
,
5112 register const unsigned char *string
=
5113 (const unsigned char *)string_param
;
5115 fprintf (stream
, "%s\"", prefix
);
5116 for (i
= 0; i
< len
; i
++)
5118 register int c
= string
[i
];
5124 putc ('\\', stream
);
5129 case TARGET_NEWLINE
:
5130 fputs ("\\n", stream
);
5132 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
5133 || c
== TARGET_TAB
))
5134 cur_pos
= 32767; /* break right here */
5140 fputs ("\\t", stream
);
5145 fputs ("\\f", stream
);
5150 fputs ("\\b", stream
);
5155 fputs ("\\r", stream
);
5160 if (c
>= ' ' && c
< 0177)
5167 fprintf (stream
, "\\%03o", c
);
5172 if (cur_pos
> 72 && i
+1 < len
)
5175 fprintf (stream
, "\"\n%s\"", prefix
);
5178 fprintf (stream
, "\"\n");
5181 /* Implement TARGET_ASM_FILE_START. */
5184 mips_file_start (void)
5186 default_file_start ();
5190 /* Generate a special section to describe the ABI switches used to
5191 produce the resultant binary. This used to be done by the assembler
5192 setting bits in the ELF header's flags field, but we have run out of
5193 bits. GDB needs this information in order to be able to correctly
5194 debug these binaries. See the function mips_gdbarch_init() in
5195 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5196 causes unnecessary IRIX 6 ld warnings. */
5197 const char * abi_string
= NULL
;
5201 case ABI_32
: abi_string
= "abi32"; break;
5202 case ABI_N32
: abi_string
= "abiN32"; break;
5203 case ABI_64
: abi_string
= "abi64"; break;
5204 case ABI_O64
: abi_string
= "abiO64"; break;
5205 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
5209 /* Note - we use fprintf directly rather than called named_section()
5210 because in this way we can avoid creating an allocated section. We
5211 do not want this section to take up any space in the running
5213 fprintf (asm_out_file
, "\t.section .mdebug.%s\n", abi_string
);
5215 /* There is no ELF header flag to distinguish long32 forms of the
5216 EABI from long64 forms. Emit a special section to help tools
5218 if (mips_abi
== ABI_EABI
)
5219 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n",
5220 TARGET_LONG64
? 64 : 32);
5222 /* Restore the default section. */
5223 fprintf (asm_out_file
, "\t.previous\n");
5226 /* Generate the pseudo ops that System V.4 wants. */
5227 if (TARGET_ABICALLS
)
5228 /* ??? but do not want this (or want pic0) if -non-shared? */
5229 fprintf (asm_out_file
, "\t.abicalls\n");
5232 fprintf (asm_out_file
, "\t.set\tmips16\n");
5234 if (flag_verbose_asm
)
5235 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5237 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
5240 #ifdef BSS_SECTION_ASM_OP
5241 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5242 in the use of sbss. */
5245 mips_output_aligned_bss (FILE *stream
, tree decl
, const char *name
,
5246 unsigned HOST_WIDE_INT size
, int align
)
5248 extern tree last_assemble_variable_decl
;
5250 if (mips_in_small_data_p (decl
))
5251 named_section (0, ".sbss", 0);
5254 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5255 last_assemble_variable_decl
= decl
;
5256 ASM_DECLARE_OBJECT_NAME (stream
, name
, decl
);
5257 ASM_OUTPUT_SKIP (stream
, size
!= 0 ? size
: 1);
5261 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5262 .externs for any small-data variables that turned out to be external. */
5265 mips_file_end (void)
5268 struct extern_list
*p
;
5272 fputs ("\n", asm_out_file
);
5274 for (p
= extern_head
; p
!= 0; p
= p
->next
)
5276 name_tree
= get_identifier (p
->name
);
5278 /* Positively ensure only one .extern for any given symbol. */
5279 if (!TREE_ASM_WRITTEN (name_tree
)
5280 && TREE_SYMBOL_REFERENCED (name_tree
))
5282 TREE_ASM_WRITTEN (name_tree
) = 1;
5283 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5284 `.global name .text' directive for every used but
5285 undefined function. If we don't, the linker may perform
5286 an optimization (skipping over the insns that set $gp)
5287 when it is unsafe. */
5288 if (TARGET_IRIX
&& mips_abi
== ABI_32
&& p
->size
== -1)
5290 fputs ("\t.globl ", asm_out_file
);
5291 assemble_name (asm_out_file
, p
->name
);
5292 fputs (" .text\n", asm_out_file
);
5296 fputs ("\t.extern\t", asm_out_file
);
5297 assemble_name (asm_out_file
, p
->name
);
5298 fprintf (asm_out_file
, ", %d\n", p
->size
);
5305 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5306 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5309 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
5310 unsigned HOST_WIDE_INT size
,
5313 /* If the target wants uninitialized const declarations in
5314 .rdata then don't put them in .comm. */
5315 if (TARGET_EMBEDDED_DATA
&& TARGET_UNINIT_CONST_IN_RODATA
5316 && TREE_CODE (decl
) == VAR_DECL
&& TREE_READONLY (decl
)
5317 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
5319 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
5320 targetm
.asm_out
.globalize_label (stream
, name
);
5322 readonly_data_section ();
5323 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5324 mips_declare_object (stream
, name
, "",
5325 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
5329 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
5333 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5334 NAME is the name of the object and ALIGN is the required alignment
5335 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5336 alignment argument. */
5339 mips_declare_common_object (FILE *stream
, const char *name
,
5340 const char *init_string
,
5341 unsigned HOST_WIDE_INT size
,
5342 unsigned int align
, bool takes_alignment_p
)
5344 if (!takes_alignment_p
)
5346 size
+= (align
/ BITS_PER_UNIT
) - 1;
5347 size
-= size
% (align
/ BITS_PER_UNIT
);
5348 mips_declare_object (stream
, name
, init_string
,
5349 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
5352 mips_declare_object (stream
, name
, init_string
,
5353 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
5354 size
, align
/ BITS_PER_UNIT
);
5357 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5358 macros, mark the symbol as written so that mips_file_end won't emit an
5359 .extern for it. STREAM is the output file, NAME is the name of the
5360 symbol, INIT_STRING is the string that should be written before the
5361 symbol and FINAL_STRING is the string that should be written after it.
5362 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5365 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
5366 const char *final_string
, ...)
5370 fputs (init_string
, stream
);
5371 assemble_name (stream
, name
);
5372 va_start (ap
, final_string
);
5373 vfprintf (stream
, final_string
, ap
);
5376 if (!TARGET_EXPLICIT_RELOCS
)
5378 tree name_tree
= get_identifier (name
);
5379 TREE_ASM_WRITTEN (name_tree
) = 1;
5383 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5384 extern int size_directive_output
;
5386 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5387 definitions except that it uses mips_declare_object() to emit the label. */
5390 mips_declare_object_name (FILE *stream
, const char *name
,
5391 tree decl ATTRIBUTE_UNUSED
)
5393 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5394 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
5397 size_directive_output
= 0;
5398 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
5402 size_directive_output
= 1;
5403 size
= int_size_in_bytes (TREE_TYPE (decl
));
5404 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
5407 mips_declare_object (stream
, name
, "", ":\n", 0);
5410 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5413 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
5417 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
5418 if (!flag_inhibit_size_directive
5419 && DECL_SIZE (decl
) != 0
5420 && !at_end
&& top_level
5421 && DECL_INITIAL (decl
) == error_mark_node
5422 && !size_directive_output
)
5426 size_directive_output
= 1;
5427 size
= int_size_in_bytes (TREE_TYPE (decl
));
5428 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
5433 /* Return true if X is a small data address that can be rewritten
5437 mips_rewrite_small_data_p (rtx x
)
5439 enum mips_symbol_type symbol_type
;
5441 return (TARGET_EXPLICIT_RELOCS
5442 && mips_symbolic_constant_p (x
, &symbol_type
)
5443 && symbol_type
== SYMBOL_SMALL_DATA
);
5447 /* A for_each_rtx callback for mips_small_data_pattern_p. */
5450 mips_small_data_pattern_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
5452 if (GET_CODE (*loc
) == LO_SUM
)
5455 return mips_rewrite_small_data_p (*loc
);
5458 /* Return true if OP refers to small data symbols directly, not through
5462 mips_small_data_pattern_p (rtx op
)
5464 return for_each_rtx (&op
, mips_small_data_pattern_1
, 0);
5467 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5470 mips_rewrite_small_data_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
5472 if (mips_rewrite_small_data_p (*loc
))
5473 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
5475 if (GET_CODE (*loc
) == LO_SUM
)
5481 /* If possible, rewrite OP so that it refers to small data using
5482 explicit relocations. */
5485 mips_rewrite_small_data (rtx op
)
5487 op
= copy_insn (op
);
5488 for_each_rtx (&op
, mips_rewrite_small_data_1
, 0);
5492 /* Return true if the current function has an insn that implicitly
5496 mips_function_has_gp_insn (void)
5498 /* Don't bother rechecking if we found one last time. */
5499 if (!cfun
->machine
->has_gp_insn_p
)
5503 push_topmost_sequence ();
5504 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5506 && GET_CODE (PATTERN (insn
)) != USE
5507 && GET_CODE (PATTERN (insn
)) != CLOBBER
5508 && (get_attr_got (insn
) != GOT_UNSET
5509 || small_data_pattern (PATTERN (insn
), VOIDmode
)))
5511 pop_topmost_sequence ();
5513 cfun
->machine
->has_gp_insn_p
= (insn
!= 0);
5515 return cfun
->machine
->has_gp_insn_p
;
5519 /* Return the register that should be used as the global pointer
5520 within this function. Return 0 if the function doesn't need
5521 a global pointer. */
5524 mips_global_pointer (void)
5528 /* $gp is always available in non-abicalls code. */
5529 if (!TARGET_ABICALLS
)
5530 return GLOBAL_POINTER_REGNUM
;
5532 /* We must always provide $gp when it is used implicitly. */
5533 if (!TARGET_EXPLICIT_RELOCS
)
5534 return GLOBAL_POINTER_REGNUM
;
5536 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
5538 if (current_function_profile
)
5539 return GLOBAL_POINTER_REGNUM
;
5541 /* If the function has a nonlocal goto, $gp must hold the correct
5542 global pointer for the target function. */
5543 if (current_function_has_nonlocal_goto
)
5544 return GLOBAL_POINTER_REGNUM
;
5546 /* If the gp is never referenced, there's no need to initialize it.
5547 Note that reload can sometimes introduce constant pool references
5548 into a function that otherwise didn't need them. For example,
5549 suppose we have an instruction like:
5551 (set (reg:DF R1) (float:DF (reg:SI R2)))
5553 If R2 turns out to be constant such as 1, the instruction may have a
5554 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
5555 using this constant if R2 doesn't get allocated to a register.
5557 In cases like these, reload will have added the constant to the pool
5558 but no instruction will yet refer to it. */
5559 if (!regs_ever_live
[GLOBAL_POINTER_REGNUM
]
5560 && !current_function_uses_const_pool
5561 && !mips_function_has_gp_insn ())
5564 /* We need a global pointer, but perhaps we can use a call-clobbered
5565 register instead of $gp. */
5566 if (TARGET_NEWABI
&& current_function_is_leaf
)
5567 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
5568 if (!regs_ever_live
[regno
]
5569 && call_used_regs
[regno
]
5570 && !fixed_regs
[regno
]
5571 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
5574 return GLOBAL_POINTER_REGNUM
;
5578 /* Return true if the current function must save REGNO. */
5581 mips_save_reg_p (unsigned int regno
)
5583 /* We only need to save $gp for NewABI PIC. */
5584 if (regno
== GLOBAL_POINTER_REGNUM
)
5585 return (TARGET_ABICALLS
&& TARGET_NEWABI
5586 && cfun
->machine
->global_pointer
== regno
);
5588 /* Check call-saved registers. */
5589 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
5592 /* We need to save the old frame pointer before setting up a new one. */
5593 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5596 /* We need to save the incoming return address if it is ever clobbered
5597 within the function. */
5598 if (regno
== GP_REG_FIRST
+ 31 && regs_ever_live
[regno
])
5605 return_type
= DECL_RESULT (current_function_decl
);
5607 /* $18 is a special case in mips16 code. It may be used to call
5608 a function which returns a floating point value, but it is
5609 marked in call_used_regs. */
5610 if (regno
== GP_REG_FIRST
+ 18 && regs_ever_live
[regno
])
5613 /* $31 is also a special case. It will be used to copy a return
5614 value into the floating point registers if the return value is
5616 if (regno
== GP_REG_FIRST
+ 31
5617 && mips16_hard_float
5618 && !aggregate_value_p (return_type
, current_function_decl
)
5619 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
5620 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
5628 /* Return the bytes needed to compute the frame pointer from the current
5629 stack pointer. SIZE is the size (in bytes) of the local variables.
5631 Mips stack frames look like:
5633 Before call After call
5634 +-----------------------+ +-----------------------+
5637 | caller's temps. | | caller's temps. |
5639 +-----------------------+ +-----------------------+
5641 | arguments on stack. | | arguments on stack. |
5643 +-----------------------+ +-----------------------+
5644 | 4 words to save | | 4 words to save |
5645 | arguments passed | | arguments passed |
5646 | in registers, even | | in registers, even |
5647 SP->| if not passed. | VFP->| if not passed. |
5648 +-----------------------+ +-----------------------+
5650 | fp register save |
5652 +-----------------------+
5654 | gp register save |
5656 +-----------------------+
5660 +-----------------------+
5662 | alloca allocations |
5664 +-----------------------+
5666 | GP save for V.4 abi |
5668 +-----------------------+
5670 | arguments on stack |
5672 +-----------------------+
5674 | arguments passed |
5675 | in registers, even |
5676 low SP->| if not passed. |
5677 memory +-----------------------+
5682 compute_frame_size (HOST_WIDE_INT size
)
5685 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
5686 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
5687 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
5688 HOST_WIDE_INT cprestore_size
; /* # bytes that the cprestore slot takes up */
5689 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
5690 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
5691 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
5692 unsigned int mask
; /* mask of saved gp registers */
5693 unsigned int fmask
; /* mask of saved fp registers */
5695 cfun
->machine
->global_pointer
= mips_global_pointer ();
5701 var_size
= MIPS_STACK_ALIGN (size
);
5702 args_size
= current_function_outgoing_args_size
;
5703 cprestore_size
= MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET
) - args_size
;
5705 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
5706 functions. If the function has local variables, we're committed
5707 to allocating it anyway. Otherwise reclaim it here. */
5708 if (var_size
== 0 && current_function_is_leaf
)
5709 cprestore_size
= args_size
= 0;
5711 /* The MIPS 3.0 linker does not like functions that dynamically
5712 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5713 looks like we are trying to create a second frame pointer to the
5714 function, so allocate some stack space to make it happy. */
5716 if (args_size
== 0 && current_function_calls_alloca
)
5717 args_size
= 4 * UNITS_PER_WORD
;
5719 total_size
= var_size
+ args_size
+ cprestore_size
;
5721 /* Calculate space needed for gp registers. */
5722 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
5723 if (mips_save_reg_p (regno
))
5725 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
5726 mask
|= 1 << (regno
- GP_REG_FIRST
);
5729 /* We need to restore these for the handler. */
5730 if (current_function_calls_eh_return
)
5735 regno
= EH_RETURN_DATA_REGNO (i
);
5736 if (regno
== INVALID_REGNUM
)
5738 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
5739 mask
|= 1 << (regno
- GP_REG_FIRST
);
5743 /* This loop must iterate over the same space as its companion in
5744 save_restore_insns. */
5745 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
5746 regno
>= FP_REG_FIRST
;
5749 if (mips_save_reg_p (regno
))
5751 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
5752 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
5756 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
5757 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
5759 /* Add in space reserved on the stack by the callee for storing arguments
5760 passed in registers. */
5762 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
5764 /* Save other computed information. */
5765 cfun
->machine
->frame
.total_size
= total_size
;
5766 cfun
->machine
->frame
.var_size
= var_size
;
5767 cfun
->machine
->frame
.args_size
= args_size
;
5768 cfun
->machine
->frame
.cprestore_size
= cprestore_size
;
5769 cfun
->machine
->frame
.gp_reg_size
= gp_reg_size
;
5770 cfun
->machine
->frame
.fp_reg_size
= fp_reg_size
;
5771 cfun
->machine
->frame
.mask
= mask
;
5772 cfun
->machine
->frame
.fmask
= fmask
;
5773 cfun
->machine
->frame
.initialized
= reload_completed
;
5774 cfun
->machine
->frame
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
5775 cfun
->machine
->frame
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
5779 HOST_WIDE_INT offset
;
5781 offset
= (args_size
+ cprestore_size
+ var_size
5782 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
5783 cfun
->machine
->frame
.gp_sp_offset
= offset
;
5784 cfun
->machine
->frame
.gp_save_offset
= offset
- total_size
;
5788 cfun
->machine
->frame
.gp_sp_offset
= 0;
5789 cfun
->machine
->frame
.gp_save_offset
= 0;
5794 HOST_WIDE_INT offset
;
5796 offset
= (args_size
+ cprestore_size
+ var_size
5797 + gp_reg_rounded
+ fp_reg_size
5798 - FP_INC
* UNITS_PER_FPREG
);
5799 cfun
->machine
->frame
.fp_sp_offset
= offset
;
5800 cfun
->machine
->frame
.fp_save_offset
= offset
- total_size
;
5804 cfun
->machine
->frame
.fp_sp_offset
= 0;
5805 cfun
->machine
->frame
.fp_save_offset
= 0;
5808 /* Ok, we're done. */
5812 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
5813 pointer or argument pointer. TO is either the stack pointer or
5814 hard frame pointer. */
5817 mips_initial_elimination_offset (int from
, int to
)
5819 HOST_WIDE_INT offset
;
5821 compute_frame_size (get_frame_size ());
5823 /* Set OFFSET to the offset from the stack pointer. */
5826 case FRAME_POINTER_REGNUM
:
5830 case ARG_POINTER_REGNUM
:
5831 offset
= cfun
->machine
->frame
.total_size
;
5833 offset
-= current_function_pretend_args_size
;
5840 if (TARGET_MIPS16
&& to
== HARD_FRAME_POINTER_REGNUM
)
5841 offset
-= cfun
->machine
->frame
.args_size
;
5846 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
5847 back to a previous frame. */
5849 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5854 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
5857 /* Use FN to save or restore register REGNO. MODE is the register's
5858 mode and OFFSET is the offset of its save slot from the current
5862 mips_save_restore_reg (enum machine_mode mode
, int regno
,
5863 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
5867 mem
= gen_rtx_MEM (mode
, plus_constant (stack_pointer_rtx
, offset
));
5869 fn (gen_rtx_REG (mode
, regno
), mem
);
5873 /* Call FN for each register that is saved by the current function.
5874 SP_OFFSET is the offset of the current stack pointer from the start
5878 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
5880 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
5882 enum machine_mode fpr_mode
;
5883 HOST_WIDE_INT offset
;
5886 /* Save registers starting from high to low. The debuggers prefer at least
5887 the return register be stored at func+4, and also it allows us not to
5888 need a nop in the epilog if at least one register is reloaded in
5889 addition to return address. */
5890 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
5891 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5892 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
5894 mips_save_restore_reg (gpr_mode
, regno
, offset
, fn
);
5895 offset
-= GET_MODE_SIZE (gpr_mode
);
5898 /* This loop must iterate over the same space as its companion in
5899 compute_frame_size. */
5900 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
5901 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
5902 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
5903 regno
>= FP_REG_FIRST
;
5905 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
5907 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
5908 offset
-= GET_MODE_SIZE (fpr_mode
);
5913 /* If we're generating n32 or n64 abicalls, and the current function
5914 does not use $28 as its global pointer, emit a cplocal directive.
5915 Use pic_offset_table_rtx as the argument to the directive. */
5918 mips_output_cplocal (void)
5920 if (!TARGET_EXPLICIT_RELOCS
5921 && cfun
->machine
->global_pointer
> 0
5922 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
5923 output_asm_insn (".cplocal %+", 0);
5926 /* If we're generating n32 or n64 abicalls, emit instructions
5927 to set up the global pointer. */
5930 mips_emit_loadgp (void)
5932 if (TARGET_ABICALLS
&& TARGET_NEWABI
&& cfun
->machine
->global_pointer
> 0)
5934 rtx addr
, offset
, incoming_address
;
5936 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
5937 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
5938 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
5939 emit_insn (gen_loadgp (offset
, incoming_address
));
5940 if (!TARGET_EXPLICIT_RELOCS
)
5941 emit_insn (gen_loadgp_blockage ());
5945 /* Set up the stack and frame (if desired) for the function. */
5948 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5951 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
5953 #ifdef SDB_DEBUGGING_INFO
5954 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5955 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
), 0);
5958 /* In mips16 mode, we may need to generate a 32 bit to handle
5959 floating point arguments. The linker will arrange for any 32 bit
5960 functions to call this stub, which will then jump to the 16 bit
5962 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
5963 && current_function_args_info
.fp_code
!= 0)
5964 build_mips16_function_stub (file
);
5966 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5968 /* Get the function name the same way that toplev.c does before calling
5969 assemble_start_function. This is needed so that the name used here
5970 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5971 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5973 if (!flag_inhibit_size_directive
)
5975 fputs ("\t.ent\t", file
);
5976 assemble_name (file
, fnname
);
5980 assemble_name (file
, fnname
);
5981 fputs (":\n", file
);
5984 /* Stop mips_file_end from treating this function as external. */
5985 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
5986 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
5988 if (!flag_inhibit_size_directive
)
5990 /* .frame FRAMEREG, FRAMESIZE, RETREG */
5992 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
5993 "# vars= " HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
5994 ", args= " HOST_WIDE_INT_PRINT_DEC
5995 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
5996 (reg_names
[(frame_pointer_needed
)
5997 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
5998 ((frame_pointer_needed
&& TARGET_MIPS16
)
5999 ? tsize
- cfun
->machine
->frame
.args_size
6001 reg_names
[GP_REG_FIRST
+ 31],
6002 cfun
->machine
->frame
.var_size
,
6003 cfun
->machine
->frame
.num_gp
,
6004 cfun
->machine
->frame
.num_fp
,
6005 cfun
->machine
->frame
.args_size
,
6006 cfun
->machine
->frame
.cprestore_size
);
6008 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6009 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6010 cfun
->machine
->frame
.mask
,
6011 cfun
->machine
->frame
.gp_save_offset
);
6012 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6013 cfun
->machine
->frame
.fmask
,
6014 cfun
->machine
->frame
.fp_save_offset
);
6017 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6018 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6021 if (TARGET_ABICALLS
&& !TARGET_NEWABI
&& cfun
->machine
->global_pointer
> 0)
6023 /* Handle the initialization of $gp for SVR4 PIC. */
6024 if (!cfun
->machine
->all_noreorder_p
)
6025 output_asm_insn ("%(.cpload\t%^%)", 0);
6027 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6029 else if (cfun
->machine
->all_noreorder_p
)
6030 output_asm_insn ("%(%<", 0);
6032 /* Tell the assembler which register we're using as the global
6033 pointer. This is needed for thunks, since they can use either
6034 explicit relocs or assembler macros. */
6035 mips_output_cplocal ();
6038 /* Make the last instruction frame related and note that it performs
6039 the operation described by FRAME_PATTERN. */
6042 mips_set_frame_expr (rtx frame_pattern
)
6046 insn
= get_last_insn ();
6047 RTX_FRAME_RELATED_P (insn
) = 1;
6048 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6054 /* Return a frame-related rtx that stores REG at MEM.
6055 REG must be a single register. */
6058 mips_frame_set (rtx mem
, rtx reg
)
6060 rtx set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
6061 RTX_FRAME_RELATED_P (set
) = 1;
6066 /* Save register REG to MEM. Make the instruction frame-related. */
6069 mips_save_reg (rtx reg
, rtx mem
)
6071 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
6075 if (mips_split_64bit_move_p (mem
, reg
))
6076 mips_split_64bit_move (mem
, reg
);
6078 emit_move_insn (mem
, reg
);
6080 x1
= mips_frame_set (mips_subword (mem
, 0), mips_subword (reg
, 0));
6081 x2
= mips_frame_set (mips_subword (mem
, 1), mips_subword (reg
, 1));
6082 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
6087 && REGNO (reg
) != GP_REG_FIRST
+ 31
6088 && !M16_REG_P (REGNO (reg
)))
6090 /* Save a non-mips16 register by moving it through a temporary.
6091 We don't need to do this for $31 since there's a special
6092 instruction for it. */
6093 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
6094 emit_move_insn (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
6097 emit_move_insn (mem
, reg
);
6099 mips_set_frame_expr (mips_frame_set (mem
, reg
));
6104 /* Expand the prologue into a bunch of separate insns. */
6107 mips_expand_prologue (void)
6111 if (cfun
->machine
->global_pointer
> 0)
6112 REGNO (pic_offset_table_rtx
) = cfun
->machine
->global_pointer
;
6114 size
= compute_frame_size (get_frame_size ());
6116 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6117 bytes beforehand; this is enough to cover the register save area
6118 without going out of range. */
6119 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6121 HOST_WIDE_INT step1
;
6123 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
6124 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6126 GEN_INT (-step1
)))) = 1;
6128 mips_for_each_saved_reg (size
, mips_save_reg
);
6131 /* Allocate the rest of the frame. */
6134 if (SMALL_OPERAND (-size
))
6135 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6137 GEN_INT (-size
)))) = 1;
6140 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
6143 /* There are no instructions to add or subtract registers
6144 from the stack pointer, so use the frame pointer as a
6145 temporary. We should always be using a frame pointer
6146 in this case anyway. */
6147 if (!frame_pointer_needed
)
6150 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6151 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
6152 hard_frame_pointer_rtx
,
6153 MIPS_PROLOGUE_TEMP (Pmode
)));
6154 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
6157 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
6159 MIPS_PROLOGUE_TEMP (Pmode
)));
6161 /* Describe the combined effect of the previous instructions. */
6163 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6164 plus_constant (stack_pointer_rtx
, -size
)));
6168 /* Set up the frame pointer, if we're using one. In mips16 code,
6169 we point the frame pointer ahead of the outgoing argument area.
6170 This should allow more variables & incoming arguments to be
6171 accessed with unextended instructions. */
6172 if (frame_pointer_needed
)
6174 if (TARGET_MIPS16
&& cfun
->machine
->frame
.args_size
!= 0)
6176 rtx offset
= GEN_INT (cfun
->machine
->frame
.args_size
);
6178 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
6183 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx
,
6184 stack_pointer_rtx
)) = 1;
6187 /* If generating o32/o64 abicalls, save $gp on the stack. */
6188 if (TARGET_ABICALLS
&& !TARGET_NEWABI
&& !current_function_is_leaf
)
6189 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size
)));
6191 mips_emit_loadgp ();
6193 /* If we are profiling, make sure no instructions are scheduled before
6194 the call to mcount. */
6196 if (current_function_profile
)
6197 emit_insn (gen_blockage ());
6200 /* Do any necessary cleanup after a function to restore stack, frame,
6203 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6206 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
6207 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6209 /* Reinstate the normal $gp. */
6210 REGNO (pic_offset_table_rtx
) = GLOBAL_POINTER_REGNUM
;
6211 mips_output_cplocal ();
6213 if (cfun
->machine
->all_noreorder_p
)
6215 /* Avoid using %>%) since it adds excess whitespace. */
6216 output_asm_insn (".set\tmacro", 0);
6217 output_asm_insn (".set\treorder", 0);
6218 set_noreorder
= set_nomacro
= 0;
6221 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
6225 /* Get the function name the same way that toplev.c does before calling
6226 assemble_start_function. This is needed so that the name used here
6227 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6228 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6229 fputs ("\t.end\t", file
);
6230 assemble_name (file
, fnname
);
6235 /* Emit instructions to restore register REG from slot MEM. */
6238 mips_restore_reg (rtx reg
, rtx mem
)
6240 /* There's no mips16 instruction to load $31 directly. Load into
6241 $7 instead and adjust the return insn appropriately. */
6242 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
6243 reg
= gen_rtx_REG (GET_MODE (reg
), 7);
6245 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
6247 /* Can't restore directly; move through a temporary. */
6248 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
6249 emit_move_insn (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
6252 emit_move_insn (reg
, mem
);
6256 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6257 if this epilogue precedes a sibling call, false if it is for a normal
6258 "epilogue" pattern. */
6261 mips_expand_epilogue (int sibcall_p
)
6263 HOST_WIDE_INT step1
, step2
;
6266 if (!sibcall_p
&& mips_can_use_return_insn ())
6268 emit_jump_insn (gen_return ());
6272 /* Split the frame into two. STEP1 is the amount of stack we should
6273 deallocate before restoring the registers. STEP2 is the amount we
6274 should deallocate afterwards.
6276 Start off by assuming that no registers need to be restored. */
6277 step1
= cfun
->machine
->frame
.total_size
;
6280 /* Work out which register holds the frame address. Account for the
6281 frame pointer offset used by mips16 code. */
6282 if (!frame_pointer_needed
)
6283 base
= stack_pointer_rtx
;
6286 base
= hard_frame_pointer_rtx
;
6288 step1
-= cfun
->machine
->frame
.args_size
;
6291 /* If we need to restore registers, deallocate as much stack as
6292 possible in the second step without going out of range. */
6293 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6295 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
6299 /* Set TARGET to BASE + STEP1. */
6305 /* Get an rtx for STEP1 that we can add to BASE. */
6306 adjust
= GEN_INT (step1
);
6307 if (!SMALL_OPERAND (step1
))
6309 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
6310 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
6313 /* Normal mode code can copy the result straight into $sp. */
6315 target
= stack_pointer_rtx
;
6317 emit_insn (gen_add3_insn (target
, base
, adjust
));
6320 /* Copy TARGET into the stack pointer. */
6321 if (target
!= stack_pointer_rtx
)
6322 emit_move_insn (stack_pointer_rtx
, target
);
6324 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6325 implicitly used by all SYMBOL_REFs. We must emit a blockage
6326 insn before restoring it. */
6327 if (TARGET_ABICALLS
&& TARGET_NEWABI
&& !TARGET_EXPLICIT_RELOCS
)
6328 emit_insn (gen_blockage ());
6330 /* Restore the registers. */
6331 mips_for_each_saved_reg (cfun
->machine
->frame
.total_size
- step2
,
6334 /* Deallocate the final bit of the frame. */
6336 emit_insn (gen_add3_insn (stack_pointer_rtx
,
6340 /* Add in the __builtin_eh_return stack adjustment. We need to
6341 use a temporary in mips16 code. */
6342 if (current_function_calls_eh_return
)
6346 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
6347 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
6348 MIPS_EPILOGUE_TEMP (Pmode
),
6349 EH_RETURN_STACKADJ_RTX
));
6350 emit_move_insn (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
6353 emit_insn (gen_add3_insn (stack_pointer_rtx
,
6355 EH_RETURN_STACKADJ_RTX
));
6360 /* The mips16 loads the return address into $7, not $31. */
6361 if (TARGET_MIPS16
&& (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
6362 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
6363 GP_REG_FIRST
+ 7)));
6365 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
6366 GP_REG_FIRST
+ 31)));
6370 /* Return nonzero if this function is known to have a null epilogue.
6371 This allows the optimizer to omit jumps to jumps if no stack
6375 mips_can_use_return_insn (void)
6379 if (! reload_completed
)
6382 if (regs_ever_live
[31] || current_function_profile
)
6385 return_type
= DECL_RESULT (current_function_decl
);
6387 /* In mips16 mode, a function which returns a floating point value
6388 needs to arrange to copy the return value into the floating point
6391 && mips16_hard_float
6392 && ! aggregate_value_p (return_type
, current_function_decl
)
6393 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6394 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
6397 if (cfun
->machine
->frame
.initialized
)
6398 return cfun
->machine
->frame
.total_size
== 0;
6400 return compute_frame_size (get_frame_size ()) == 0;
6403 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6404 in order to avoid duplicating too much logic from elsewhere. */
6407 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
6408 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
6411 rtx
this, temp1
, temp2
, insn
, fnaddr
;
6413 /* Pretend to be a post-reload pass while generating rtl. */
6415 reload_completed
= 1;
6416 reset_block_changes ();
6418 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6419 for TARGET_NEWABI since the latter is a call-saved register. */
6420 if (TARGET_ABICALLS
)
6421 cfun
->machine
->global_pointer
6422 = REGNO (pic_offset_table_rtx
)
6423 = TARGET_NEWABI
? 15 : GLOBAL_POINTER_REGNUM
;
6425 /* Set up the global pointer for n32 or n64 abicalls. */
6426 mips_emit_loadgp ();
6428 /* We need two temporary registers in some cases. */
6429 temp1
= gen_rtx_REG (Pmode
, 2);
6430 temp2
= gen_rtx_REG (Pmode
, 3);
6432 /* Find out which register contains the "this" pointer. */
6433 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
6434 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
6436 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
6438 /* Add DELTA to THIS. */
6441 rtx offset
= GEN_INT (delta
);
6442 if (!SMALL_OPERAND (delta
))
6444 emit_move_insn (temp1
, offset
);
6447 emit_insn (gen_add3_insn (this, this, offset
));
6450 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6451 if (vcall_offset
!= 0)
6455 /* Set TEMP1 to *THIS. */
6456 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, this));
6458 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6459 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
6461 /* Load the offset and add it to THIS. */
6462 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, addr
));
6463 emit_insn (gen_add3_insn (this, this, temp1
));
6466 /* Jump to the target function. Use a sibcall if direct jumps are
6467 allowed, otherwise load the address into a register first. */
6468 fnaddr
= XEXP (DECL_RTL (function
), 0);
6469 if (TARGET_MIPS16
|| TARGET_ABICALLS
|| TARGET_LONG_CALLS
)
6471 /* This is messy. gas treats "la $25,foo" as part of a call
6472 sequence and may allow a global "foo" to be lazily bound.
6473 The general move patterns therefore reject this combination.
6475 In this context, lazy binding would actually be OK for o32 and o64,
6476 but it's still wrong for n32 and n64; see mips_load_call_address.
6477 We must therefore load the address via a temporary register if
6478 mips_dangerous_for_la25_p.
6480 If we jump to the temporary register rather than $25, the assembler
6481 can use the move insn to fill the jump's delay slot. */
6482 if (TARGET_ABICALLS
&& !mips_dangerous_for_la25_p (fnaddr
))
6483 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
6484 mips_load_call_address (temp1
, fnaddr
, true);
6486 if (TARGET_ABICALLS
&& REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
6487 emit_move_insn (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
6488 emit_jump_insn (gen_indirect_jump (temp1
));
6492 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
6493 SIBLING_CALL_P (insn
) = 1;
6496 /* Run just enough of rest_of_compilation. This sequence was
6497 "borrowed" from alpha.c. */
6498 insn
= get_insns ();
6499 insn_locators_initialize ();
6500 split_all_insns_noflow ();
6502 mips16_lay_out_constants ();
6503 shorten_branches (insn
);
6504 final_start_function (insn
, file
, 1);
6505 final (insn
, file
, 1, 0);
6506 final_end_function ();
6508 /* Clean up the vars set above. Note that final_end_function resets
6509 the global pointer for us. */
6510 reload_completed
= 0;
6514 /* Returns nonzero if X contains a SYMBOL_REF. */
6517 symbolic_expression_p (rtx x
)
6519 if (GET_CODE (x
) == SYMBOL_REF
)
6522 if (GET_CODE (x
) == CONST
)
6523 return symbolic_expression_p (XEXP (x
, 0));
6526 return symbolic_expression_p (XEXP (x
, 0));
6528 if (ARITHMETIC_P (x
))
6529 return (symbolic_expression_p (XEXP (x
, 0))
6530 || symbolic_expression_p (XEXP (x
, 1)));
6535 /* Choose the section to use for the constant rtx expression X that has
6539 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
6540 unsigned HOST_WIDE_INT align
)
6544 /* In mips16 mode, the constant table always goes in the same section
6545 as the function, so that constants can be loaded using PC relative
6547 function_section (current_function_decl
);
6549 else if (TARGET_EMBEDDED_DATA
)
6551 /* For embedded applications, always put constants in read-only data,
6552 in order to reduce RAM usage. */
6553 mergeable_constant_section (mode
, align
, 0);
6557 /* For hosted applications, always put constants in small data if
6558 possible, as this gives the best performance. */
6559 /* ??? Consider using mergeable small data sections. */
6561 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
6562 && mips_section_threshold
> 0)
6563 named_section (0, ".sdata", 0);
6564 else if (flag_pic
&& symbolic_expression_p (x
))
6565 named_section (0, ".data.rel.ro", 3);
6567 mergeable_constant_section (mode
, align
, 0);
6571 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6572 access DECL using %gp_rel(...)($gp). */
6575 mips_in_small_data_p (tree decl
)
6579 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
6582 /* We don't yet generate small-data references for -mabicalls. See related
6583 -G handling in override_options. */
6584 if (TARGET_ABICALLS
)
6587 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
6591 /* Reject anything that isn't in a known small-data section. */
6592 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6593 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
6596 /* If a symbol is defined externally, the assembler will use the
6597 usual -G rules when deciding how to implement macros. */
6598 if (TARGET_EXPLICIT_RELOCS
|| !DECL_EXTERNAL (decl
))
6601 else if (TARGET_EMBEDDED_DATA
)
6603 /* Don't put constants into the small data section: we want them
6604 to be in ROM rather than RAM. */
6605 if (TREE_CODE (decl
) != VAR_DECL
)
6608 if (TREE_READONLY (decl
)
6609 && !TREE_SIDE_EFFECTS (decl
)
6610 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
6614 size
= int_size_in_bytes (TREE_TYPE (decl
));
6615 return (size
> 0 && size
<= mips_section_threshold
);
6618 /* See whether VALTYPE is a record whose fields should be returned in
6619 floating-point registers. If so, return the number of fields and
6620 list them in FIELDS (which should have two elements). Return 0
6623 For n32 & n64, a structure with one or two fields is returned in
6624 floating-point registers as long as every field has a floating-point
6628 mips_fpr_return_fields (tree valtype
, tree
*fields
)
6636 if (TREE_CODE (valtype
) != RECORD_TYPE
)
6640 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
6642 if (TREE_CODE (field
) != FIELD_DECL
)
6645 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
)
6651 fields
[i
++] = field
;
6657 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6658 a value in the most significant part of $2/$3 if:
6660 - the target is big-endian;
6662 - the value has a structure or union type (we generalize this to
6663 cover aggregates from other languages too); and
6665 - the structure is not returned in floating-point registers. */
6668 mips_return_in_msb (tree valtype
)
6672 return (TARGET_NEWABI
6673 && TARGET_BIG_ENDIAN
6674 && AGGREGATE_TYPE_P (valtype
)
6675 && mips_fpr_return_fields (valtype
, fields
) == 0);
6679 /* Return a composite value in a pair of floating-point registers.
6680 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6681 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6684 For n32 & n64, $f0 always holds the first value and $f2 the second.
6685 Otherwise the values are packed together as closely as possible. */
6688 mips_return_fpr_pair (enum machine_mode mode
,
6689 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
6690 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
6694 inc
= (TARGET_NEWABI
? 2 : FP_INC
);
6695 return gen_rtx_PARALLEL
6698 gen_rtx_EXPR_LIST (VOIDmode
,
6699 gen_rtx_REG (mode1
, FP_RETURN
),
6701 gen_rtx_EXPR_LIST (VOIDmode
,
6702 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
6703 GEN_INT (offset2
))));
6708 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
6709 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
6710 VALTYPE is null and MODE is the mode of the return value. */
6713 mips_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6714 enum machine_mode mode
)
6721 mode
= TYPE_MODE (valtype
);
6722 unsignedp
= TYPE_UNSIGNED (valtype
);
6724 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
6725 true, we must promote the mode just as PROMOTE_MODE does. */
6726 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
6728 /* Handle structures whose fields are returned in $f0/$f2. */
6729 switch (mips_fpr_return_fields (valtype
, fields
))
6732 return gen_rtx_REG (mode
, FP_RETURN
);
6735 return mips_return_fpr_pair (mode
,
6736 TYPE_MODE (TREE_TYPE (fields
[0])),
6737 int_byte_position (fields
[0]),
6738 TYPE_MODE (TREE_TYPE (fields
[1])),
6739 int_byte_position (fields
[1]));
6742 /* If a value is passed in the most significant part of a register, see
6743 whether we have to round the mode up to a whole number of words. */
6744 if (mips_return_in_msb (valtype
))
6746 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
6747 if (size
% UNITS_PER_WORD
!= 0)
6749 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
6750 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6755 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
6756 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
6757 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
6758 return gen_rtx_REG (mode
, FP_RETURN
);
6760 /* Handle long doubles for n32 & n64. */
6762 return mips_return_fpr_pair (mode
,
6764 DImode
, GET_MODE_SIZE (mode
) / 2);
6766 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6767 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)
6768 return mips_return_fpr_pair (mode
,
6769 GET_MODE_INNER (mode
), 0,
6770 GET_MODE_INNER (mode
),
6771 GET_MODE_SIZE (mode
) / 2);
6773 return gen_rtx_REG (mode
, GP_RETURN
);
6776 /* Return nonzero when an argument must be passed by reference. */
6779 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6780 enum machine_mode mode
, tree type
,
6781 bool named ATTRIBUTE_UNUSED
)
6783 if (mips_abi
== ABI_EABI
)
6787 /* ??? How should SCmode be handled? */
6788 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
6791 size
= int_size_in_bytes (type
);
6792 return size
== -1 || size
> UNITS_PER_WORD
;
6796 /* If we have a variable-sized parameter, we have no choice. */
6797 return targetm
.calls
.must_pass_in_stack (mode
, type
);
6801 /* Return the class of registers for which a mode change from FROM to TO
6804 In little-endian mode, the hi-lo registers are numbered backwards,
6805 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
6808 Similarly, when using paired floating-point registers, the first
6809 register holds the low word, regardless of endianness. So in big
6810 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
6813 Also, loading a 32-bit value into a 64-bit floating-point register
6814 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
6815 We can't allow 64-bit float registers to change from a 32-bit
6816 mode to a 64-bit mode. */
6819 mips_cannot_change_mode_class (enum machine_mode from
,
6820 enum machine_mode to
, enum reg_class
class)
6822 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
6824 if (TARGET_BIG_ENDIAN
)
6825 return reg_classes_intersect_p (FP_REGS
, class);
6827 return reg_classes_intersect_p (HI_AND_FP_REGS
, class);
6828 return reg_classes_intersect_p (HI_REG
, class);
6833 /* Return true if X should not be moved directly into register $25.
6834 We need this because many versions of GAS will treat "la $25,foo" as
6835 part of a call sequence and so allow a global "foo" to be lazily bound. */
6838 mips_dangerous_for_la25_p (rtx x
)
6840 HOST_WIDE_INT offset
;
6842 if (TARGET_EXPLICIT_RELOCS
)
6845 mips_split_const (x
, &x
, &offset
);
6846 return global_got_operand (x
, VOIDmode
);
6849 /* Implement PREFERRED_RELOAD_CLASS. */
6852 mips_preferred_reload_class (rtx x
, enum reg_class
class)
6854 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
6857 if (TARGET_HARD_FLOAT
6858 && FLOAT_MODE_P (GET_MODE (x
))
6859 && reg_class_subset_p (FP_REGS
, class))
6862 if (reg_class_subset_p (GR_REGS
, class))
6865 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
6871 /* This function returns the register class required for a secondary
6872 register when copying between one of the registers in CLASS, and X,
6873 using MODE. If IN_P is nonzero, the copy is going from X to the
6874 register, otherwise the register is the source. A return value of
6875 NO_REGS means that no secondary register is required. */
6878 mips_secondary_reload_class (enum reg_class
class,
6879 enum machine_mode mode
, rtx x
, int in_p
)
6881 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
6885 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
6886 regno
= true_regnum (x
);
6888 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
6890 if (mips_dangerous_for_la25_p (x
))
6893 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], 25))
6897 /* Copying from HI or LO to anywhere other than a general register
6898 requires a general register. */
6899 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
6901 if (TARGET_MIPS16
&& in_p
)
6903 /* We can't really copy to HI or LO at all in mips16 mode. */
6906 return gp_reg_p
? NO_REGS
: gr_regs
;
6908 if (MD_REG_P (regno
))
6910 if (TARGET_MIPS16
&& ! in_p
)
6912 /* We can't really copy to HI or LO at all in mips16 mode. */
6915 return class == gr_regs
? NO_REGS
: gr_regs
;
6918 /* We can only copy a value to a condition code register from a
6919 floating point register, and even then we require a scratch
6920 floating point register. We can only copy a value out of a
6921 condition code register into a general register. */
6922 if (class == ST_REGS
)
6926 return gp_reg_p
? NO_REGS
: gr_regs
;
6928 if (ST_REG_P (regno
))
6932 return class == gr_regs
? NO_REGS
: gr_regs
;
6935 if (class == FP_REGS
)
6937 if (GET_CODE (x
) == MEM
)
6939 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
6942 else if (CONSTANT_P (x
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6944 /* We can use the l.s and l.d macros to load floating-point
6945 constants. ??? For l.s, we could probably get better
6946 code by returning GR_REGS here. */
6949 else if (gp_reg_p
|| x
== CONST0_RTX (mode
))
6951 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
6954 else if (FP_REG_P (regno
))
6956 /* In this case we can use mov.s or mov.d. */
6961 /* Otherwise, we need to reload through an integer register. */
6966 /* In mips16 mode, going between memory and anything but M16_REGS
6967 requires an M16_REG. */
6970 if (class != M16_REGS
&& class != M16_NA_REGS
)
6978 if (class == M16_REGS
|| class == M16_NA_REGS
)
6987 /* Implement CLASS_MAX_NREGS.
6989 Usually all registers are word-sized. The only supported exception
6990 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
6991 registers. A word-based calculation is correct even in that case,
6992 since -msingle-float disallows multi-FPR values.
6994 The FP status registers are an exception to this rule. They are always
6995 4 bytes wide as they only hold condition code modes, and CCmode is always
6996 considered to be 4 bytes wide. */
6999 mips_class_max_nregs (enum reg_class
class ATTRIBUTE_UNUSED
,
7000 enum machine_mode mode
)
7002 if (class == ST_REGS
)
7003 return (GET_MODE_SIZE (mode
) + 3) / 4;
7005 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7009 mips_valid_pointer_mode (enum machine_mode mode
)
7011 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
7014 /* Target hook for vector_mode_supported_p. */
7016 mips_vector_mode_supported_p (enum machine_mode mode
)
7018 if (mode
== V2SFmode
&& TARGET_PAIRED_SINGLE_FLOAT
)
7024 /* If we can access small data directly (using gp-relative relocation
7025 operators) return the small data pointer, otherwise return null.
7027 For each mips16 function which refers to GP relative symbols, we
7028 use a pseudo register, initialized at the start of the function, to
7029 hold the $gp value. */
7032 mips16_gp_pseudo_reg (void)
7034 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
7039 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
7041 /* We want to initialize this to a value which gcc will believe
7044 unspec
= gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, const0_rtx
), UNSPEC_GP
);
7045 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
7046 gen_rtx_CONST (Pmode
, unspec
));
7047 insn
= get_insns ();
7050 push_topmost_sequence ();
7051 /* We need to emit the initialization after the FUNCTION_BEG
7052 note, so that it will be integrated. */
7053 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
7054 if (GET_CODE (scan
) == NOTE
7055 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
7057 if (scan
== NULL_RTX
)
7058 scan
= get_insns ();
7059 insn
= emit_insn_after (insn
, scan
);
7060 pop_topmost_sequence ();
7063 return cfun
->machine
->mips16_gp_pseudo_rtx
;
7066 /* Write out code to move floating point arguments in or out of
7067 general registers. Output the instructions to FILE. FP_CODE is
7068 the code describing which arguments are present (see the comment at
7069 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7070 we are copying from the floating point registers. */
7073 mips16_fp_args (FILE *file
, int fp_code
, int from_fp_p
)
7079 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7087 gparg
= GP_ARG_FIRST
;
7088 fparg
= FP_ARG_FIRST
;
7089 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7093 if ((fparg
& 1) != 0)
7095 fprintf (file
, "\t%s\t%s,%s\n", s
,
7096 reg_names
[gparg
], reg_names
[fparg
]);
7098 else if ((f
& 3) == 2)
7101 fprintf (file
, "\td%s\t%s,%s\n", s
,
7102 reg_names
[gparg
], reg_names
[fparg
]);
7105 if ((fparg
& 1) != 0)
7107 if (TARGET_BIG_ENDIAN
)
7108 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7109 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
7110 reg_names
[gparg
+ 1], reg_names
[fparg
]);
7112 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7113 reg_names
[gparg
], reg_names
[fparg
], s
,
7114 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
7127 /* Build a mips16 function stub. This is used for functions which
7128 take arguments in the floating point registers. It is 32 bit code
7129 that moves the floating point args into the general registers, and
7130 then jumps to the 16 bit code. */
7133 build_mips16_function_stub (FILE *file
)
7136 char *secname
, *stubname
;
7137 tree stubid
, stubdecl
;
7141 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7142 secname
= (char *) alloca (strlen (fnname
) + 20);
7143 sprintf (secname
, ".mips16.fn.%s", fnname
);
7144 stubname
= (char *) alloca (strlen (fnname
) + 20);
7145 sprintf (stubname
, "__fn_stub_%s", fnname
);
7146 stubid
= get_identifier (stubname
);
7147 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
7148 build_function_type (void_type_node
, NULL_TREE
));
7149 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
7151 fprintf (file
, "\t# Stub function for %s (", current_function_name ());
7153 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
7155 fprintf (file
, "%s%s",
7156 need_comma
? ", " : "",
7157 (f
& 3) == 1 ? "float" : "double");
7160 fprintf (file
, ")\n");
7162 fprintf (file
, "\t.set\tnomips16\n");
7163 function_section (stubdecl
);
7164 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
7166 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7167 within a .ent, and we cannot emit another .ent. */
7168 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7170 fputs ("\t.ent\t", file
);
7171 assemble_name (file
, stubname
);
7175 assemble_name (file
, stubname
);
7176 fputs (":\n", file
);
7178 /* We don't want the assembler to insert any nops here. */
7179 fprintf (file
, "\t.set\tnoreorder\n");
7181 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
7183 fprintf (asm_out_file
, "\t.set\tnoat\n");
7184 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
7185 assemble_name (file
, fnname
);
7186 fprintf (file
, "\n");
7187 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
7188 fprintf (asm_out_file
, "\t.set\tat\n");
7190 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7191 with one of the mfc1 instructions, because the result is not
7192 available for one instruction, so if the very first instruction
7193 in the function refers to the register, it will see the wrong
7195 fprintf (file
, "\tnop\n");
7197 fprintf (file
, "\t.set\treorder\n");
7199 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7201 fputs ("\t.end\t", file
);
7202 assemble_name (file
, stubname
);
7206 fprintf (file
, "\t.set\tmips16\n");
7208 function_section (current_function_decl
);
7211 /* We keep a list of functions for which we have already built stubs
7212 in build_mips16_call_stub. */
7216 struct mips16_stub
*next
;
7221 static struct mips16_stub
*mips16_stubs
;
7223 /* Build a call stub for a mips16 call. A stub is needed if we are
7224 passing any floating point values which should go into the floating
7225 point registers. If we are, and the call turns out to be to a 32
7226 bit function, the stub will be used to move the values into the
7227 floating point registers before calling the 32 bit function. The
7228 linker will magically adjust the function call to either the 16 bit
7229 function or the 32 bit stub, depending upon where the function call
7230 is actually defined.
7232 Similarly, we need a stub if the return value might come back in a
7233 floating point register.
7235 RETVAL is the location of the return value, or null if this is
7236 a call rather than a call_value. FN is the address of the
7237 function and ARG_SIZE is the size of the arguments. FP_CODE
7238 is the code built by function_arg. This function returns a nonzero
7239 value if it builds the call instruction itself. */
7242 build_mips16_call_stub (rtx retval
, rtx fn
, rtx arg_size
, int fp_code
)
7246 char *secname
, *stubname
;
7247 struct mips16_stub
*l
;
7248 tree stubid
, stubdecl
;
7252 /* We don't need to do anything if we aren't in mips16 mode, or if
7253 we were invoked with the -msoft-float option. */
7254 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
7257 /* Figure out whether the value might come back in a floating point
7259 fpret
= (retval
!= 0
7260 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
7261 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
7263 /* We don't need to do anything if there were no floating point
7264 arguments and the value will not be returned in a floating point
7266 if (fp_code
== 0 && ! fpret
)
7269 /* We don't need to do anything if this is a call to a special
7270 mips16 support function. */
7271 if (GET_CODE (fn
) == SYMBOL_REF
7272 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
7275 /* This code will only work for o32 and o64 abis. The other ABI's
7276 require more sophisticated support. */
7280 /* We can only handle SFmode and DFmode floating point return
7282 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
7285 /* If we're calling via a function pointer, then we must always call
7286 via a stub. There are magic stubs provided in libgcc.a for each
7287 of the required cases. Each of them expects the function address
7288 to arrive in register $2. */
7290 if (GET_CODE (fn
) != SYMBOL_REF
)
7296 /* ??? If this code is modified to support other ABI's, we need
7297 to handle PARALLEL return values here. */
7299 sprintf (buf
, "__mips16_call_stub_%s%d",
7301 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
7304 id
= get_identifier (buf
);
7305 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
7307 emit_move_insn (gen_rtx_REG (Pmode
, 2), fn
);
7309 if (retval
== NULL_RTX
)
7310 insn
= gen_call_internal (stub_fn
, arg_size
);
7312 insn
= gen_call_value_internal (retval
, stub_fn
, arg_size
);
7313 insn
= emit_call_insn (insn
);
7315 /* Put the register usage information on the CALL. */
7316 if (GET_CODE (insn
) != CALL_INSN
)
7318 CALL_INSN_FUNCTION_USAGE (insn
) =
7319 gen_rtx_EXPR_LIST (VOIDmode
,
7320 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
7321 CALL_INSN_FUNCTION_USAGE (insn
));
7323 /* If we are handling a floating point return value, we need to
7324 save $18 in the function prologue. Putting a note on the
7325 call will mean that regs_ever_live[$18] will be true if the
7326 call is not eliminated, and we can check that in the prologue
7329 CALL_INSN_FUNCTION_USAGE (insn
) =
7330 gen_rtx_EXPR_LIST (VOIDmode
,
7331 gen_rtx_USE (VOIDmode
,
7332 gen_rtx_REG (word_mode
, 18)),
7333 CALL_INSN_FUNCTION_USAGE (insn
));
7335 /* Return 1 to tell the caller that we've generated the call
7340 /* We know the function we are going to call. If we have already
7341 built a stub, we don't need to do anything further. */
7343 fnname
= XSTR (fn
, 0);
7344 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
7345 if (strcmp (l
->name
, fnname
) == 0)
7350 /* Build a special purpose stub. When the linker sees a
7351 function call in mips16 code, it will check where the target
7352 is defined. If the target is a 32 bit call, the linker will
7353 search for the section defined here. It can tell which
7354 symbol this section is associated with by looking at the
7355 relocation information (the name is unreliable, since this
7356 might be a static function). If such a section is found, the
7357 linker will redirect the call to the start of the magic
7360 If the function does not return a floating point value, the
7361 special stub section is named
7364 If the function does return a floating point value, the stub
7366 .mips16.call.fp.FNNAME
7369 secname
= (char *) alloca (strlen (fnname
) + 40);
7370 sprintf (secname
, ".mips16.call.%s%s",
7373 stubname
= (char *) alloca (strlen (fnname
) + 20);
7374 sprintf (stubname
, "__call_stub_%s%s",
7377 stubid
= get_identifier (stubname
);
7378 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
7379 build_function_type (void_type_node
, NULL_TREE
));
7380 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
7382 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7384 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7388 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7390 fprintf (asm_out_file
, "%s%s",
7391 need_comma
? ", " : "",
7392 (f
& 3) == 1 ? "float" : "double");
7395 fprintf (asm_out_file
, ")\n");
7397 fprintf (asm_out_file
, "\t.set\tnomips16\n");
7398 assemble_start_function (stubdecl
, stubname
);
7400 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7402 fputs ("\t.ent\t", asm_out_file
);
7403 assemble_name (asm_out_file
, stubname
);
7404 fputs ("\n", asm_out_file
);
7406 assemble_name (asm_out_file
, stubname
);
7407 fputs (":\n", asm_out_file
);
7410 /* We build the stub code by hand. That's the only way we can
7411 do it, since we can't generate 32 bit code during a 16 bit
7414 /* We don't want the assembler to insert any nops here. */
7415 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
7417 mips16_fp_args (asm_out_file
, fp_code
, 0);
7421 fprintf (asm_out_file
, "\t.set\tnoat\n");
7422 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
7424 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
7425 fprintf (asm_out_file
, "\t.set\tat\n");
7426 /* Unfortunately, we can't fill the jump delay slot. We
7427 can't fill with one of the mtc1 instructions, because the
7428 result is not available for one instruction, so if the
7429 very first instruction in the function refers to the
7430 register, it will see the wrong value. */
7431 fprintf (asm_out_file
, "\tnop\n");
7435 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7436 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
7437 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
7438 /* As above, we can't fill the delay slot. */
7439 fprintf (asm_out_file
, "\tnop\n");
7440 if (GET_MODE (retval
) == SFmode
)
7441 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
7442 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
7445 if (TARGET_BIG_ENDIAN
)
7447 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
7448 reg_names
[GP_REG_FIRST
+ 2],
7449 reg_names
[FP_REG_FIRST
+ 1]);
7450 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
7451 reg_names
[GP_REG_FIRST
+ 3],
7452 reg_names
[FP_REG_FIRST
+ 0]);
7456 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
7457 reg_names
[GP_REG_FIRST
+ 2],
7458 reg_names
[FP_REG_FIRST
+ 0]);
7459 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
7460 reg_names
[GP_REG_FIRST
+ 3],
7461 reg_names
[FP_REG_FIRST
+ 1]);
7464 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7465 /* As above, we can't fill the delay slot. */
7466 fprintf (asm_out_file
, "\tnop\n");
7469 fprintf (asm_out_file
, "\t.set\treorder\n");
7471 #ifdef ASM_DECLARE_FUNCTION_SIZE
7472 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7475 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7477 fputs ("\t.end\t", asm_out_file
);
7478 assemble_name (asm_out_file
, stubname
);
7479 fputs ("\n", asm_out_file
);
7482 fprintf (asm_out_file
, "\t.set\tmips16\n");
7484 /* Record this stub. */
7485 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
7486 l
->name
= xstrdup (fnname
);
7488 l
->next
= mips16_stubs
;
7492 /* If we expect a floating point return value, but we've built a
7493 stub which does not expect one, then we're in trouble. We can't
7494 use the existing stub, because it won't handle the floating point
7495 value. We can't build a new stub, because the linker won't know
7496 which stub to use for the various calls in this object file.
7497 Fortunately, this case is illegal, since it means that a function
7498 was declared in two different ways in a single compilation. */
7499 if (fpret
&& ! l
->fpret
)
7500 error ("cannot handle inconsistent calls to `%s'", fnname
);
7502 /* If we are calling a stub which handles a floating point return
7503 value, we need to arrange to save $18 in the prologue. We do
7504 this by marking the function call as using the register. The
7505 prologue will later see that it is used, and emit code to save
7512 if (retval
== NULL_RTX
)
7513 insn
= gen_call_internal (fn
, arg_size
);
7515 insn
= gen_call_value_internal (retval
, fn
, arg_size
);
7516 insn
= emit_call_insn (insn
);
7518 if (GET_CODE (insn
) != CALL_INSN
)
7521 CALL_INSN_FUNCTION_USAGE (insn
) =
7522 gen_rtx_EXPR_LIST (VOIDmode
,
7523 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
7524 CALL_INSN_FUNCTION_USAGE (insn
));
7526 /* Return 1 to tell the caller that we've generated the call
7531 /* Return 0 to let the caller generate the call insn. */
7535 /* An entry in the mips16 constant pool. VALUE is the pool constant,
7536 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
7538 struct mips16_constant
{
7539 struct mips16_constant
*next
;
7542 enum machine_mode mode
;
7545 /* Information about an incomplete mips16 constant pool. FIRST is the
7546 first constant, HIGHEST_ADDRESS is the highest address that the first
7547 byte of the pool can have, and INSN_ADDRESS is the current instruction
7550 struct mips16_constant_pool
{
7551 struct mips16_constant
*first
;
7552 int highest_address
;
7556 /* Add constant VALUE to POOL and return its label. MODE is the
7557 value's mode (used for CONST_INTs, etc.). */
7560 add_constant (struct mips16_constant_pool
*pool
,
7561 rtx value
, enum machine_mode mode
)
7563 struct mips16_constant
**p
, *c
;
7564 bool first_of_size_p
;
7566 /* See whether the constant is already in the pool. If so, return the
7567 existing label, otherwise leave P pointing to the place where the
7568 constant should be added.
7570 Keep the pool sorted in increasing order of mode size so that we can
7571 reduce the number of alignments needed. */
7572 first_of_size_p
= true;
7573 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
7575 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
7577 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
7579 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
7580 first_of_size_p
= false;
7583 /* In the worst case, the constant needed by the earliest instruction
7584 will end up at the end of the pool. The entire pool must then be
7585 accessible from that instruction.
7587 When adding the first constant, set the pool's highest address to
7588 the address of the first out-of-range byte. Adjust this address
7589 downwards each time a new constant is added. */
7590 if (pool
->first
== 0)
7591 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
7592 is the address of the instruction with the lowest two bits clear.
7593 The base PC value for ld has the lowest three bits clear. Assume
7594 the worst case here. */
7595 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
7596 pool
->highest_address
-= GET_MODE_SIZE (mode
);
7597 if (first_of_size_p
)
7598 /* Take into account the worst possible padding due to alignment. */
7599 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
7601 /* Create a new entry. */
7602 c
= (struct mips16_constant
*) xmalloc (sizeof *c
);
7605 c
->label
= gen_label_rtx ();
7612 /* Output constant VALUE after instruction INSN and return the last
7613 instruction emitted. MODE is the mode of the constant. */
7616 dump_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
7618 switch (GET_MODE_CLASS (mode
))
7622 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
7623 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
7627 return emit_insn_after (gen_consttable_float (value
), insn
);
7629 case MODE_VECTOR_FLOAT
:
7630 case MODE_VECTOR_INT
:
7633 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
7634 insn
= dump_constants_1 (GET_MODE_INNER (mode
),
7635 CONST_VECTOR_ELT (value
, i
), insn
);
7645 /* Dump out the constants in CONSTANTS after INSN. */
7648 dump_constants (struct mips16_constant
*constants
, rtx insn
)
7650 struct mips16_constant
*c
, *next
;
7654 for (c
= constants
; c
!= NULL
; c
= next
)
7656 /* If necessary, increase the alignment of PC. */
7657 if (align
< GET_MODE_SIZE (c
->mode
))
7659 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
7660 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
7662 align
= GET_MODE_SIZE (c
->mode
);
7664 insn
= emit_label_after (c
->label
, insn
);
7665 insn
= dump_constants_1 (c
->mode
, c
->value
, insn
);
7671 emit_barrier_after (insn
);
7674 /* Return the length of instruction INSN.
7676 ??? MIPS16 switch tables go in .text, but we don't define
7677 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
7678 compute their lengths correctly. */
7681 mips16_insn_length (rtx insn
)
7683 if (GET_CODE (insn
) == JUMP_INSN
)
7685 rtx body
= PATTERN (insn
);
7686 if (GET_CODE (body
) == ADDR_VEC
)
7687 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
7688 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
7689 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
7691 return get_attr_length (insn
);
7694 /* Rewrite *X so that constant pool references refer to the constant's
7695 label instead. DATA points to the constant pool structure. */
7698 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
7700 struct mips16_constant_pool
*pool
= data
;
7701 if (GET_CODE (*x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (*x
))
7702 *x
= gen_rtx_LABEL_REF (Pmode
, add_constant (pool
,
7703 get_pool_constant (*x
),
7704 get_pool_mode (*x
)));
7708 /* Build MIPS16 constant pools. */
7711 mips16_lay_out_constants (void)
7713 struct mips16_constant_pool pool
;
7717 memset (&pool
, 0, sizeof (pool
));
7718 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7720 /* Rewrite constant pool references in INSN. */
7722 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &pool
);
7724 pool
.insn_address
+= mips16_insn_length (insn
);
7726 if (pool
.first
!= NULL
)
7728 /* If there are no natural barriers between the first user of
7729 the pool and the highest acceptable address, we'll need to
7730 create a new instruction to jump around the constant pool.
7731 In the worst case, this instruction will be 4 bytes long.
7733 If it's too late to do this transformation after INSN,
7734 do it immediately before INSN. */
7735 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
7739 label
= gen_label_rtx ();
7741 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
7742 JUMP_LABEL (jump
) = label
;
7743 LABEL_NUSES (label
) = 1;
7744 barrier
= emit_barrier_after (jump
);
7746 emit_label_after (label
, barrier
);
7747 pool
.insn_address
+= 4;
7750 /* See whether the constant pool is now out of range of the first
7751 user. If so, output the constants after the previous barrier.
7752 Note that any instructions between BARRIER and INSN (inclusive)
7753 will use negative offsets to refer to the pool. */
7754 if (pool
.insn_address
> pool
.highest_address
)
7756 dump_constants (pool
.first
, barrier
);
7760 else if (BARRIER_P (insn
))
7764 dump_constants (pool
.first
, get_last_insn ());
7767 /* A temporary variable used by for_each_rtx callbacks, etc. */
7768 static rtx mips_sim_insn
;
7770 /* A structure representing the state of the processor pipeline.
7771 Used by the mips_sim_* family of functions. */
7773 /* The maximum number of instructions that can be issued in a cycle.
7774 (Caches mips_issue_rate.) */
7775 unsigned int issue_rate
;
7777 /* The current simulation time. */
7780 /* How many more instructions can be issued in the current cycle. */
7781 unsigned int insns_left
;
7783 /* LAST_SET[X].INSN is the last instruction to set register X.
7784 LAST_SET[X].TIME is the time at which that instruction was issued.
7785 INSN is null if no instruction has yet set register X. */
7789 } last_set
[FIRST_PSEUDO_REGISTER
];
7791 /* The pipeline's current DFA state. */
7795 /* Reset STATE to the initial simulation state. */
7798 mips_sim_reset (struct mips_sim
*state
)
7801 state
->insns_left
= state
->issue_rate
;
7802 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
7803 state_reset (state
->dfa_state
);
7806 /* Initialize STATE before its first use. DFA_STATE points to an
7807 allocated but uninitialized DFA state. */
7810 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
7812 state
->issue_rate
= mips_issue_rate ();
7813 state
->dfa_state
= dfa_state
;
7814 mips_sim_reset (state
);
7817 /* Advance STATE by one clock cycle. */
7820 mips_sim_next_cycle (struct mips_sim
*state
)
7823 state
->insns_left
= state
->issue_rate
;
7824 state_transition (state
->dfa_state
, 0);
7827 /* Advance simulation state STATE until instruction INSN can read
7831 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
7835 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)); i
++)
7836 if (state
->last_set
[REGNO (reg
) + i
].insn
!= 0)
7840 t
= state
->last_set
[REGNO (reg
) + i
].time
;
7841 t
+= insn_latency (state
->last_set
[REGNO (reg
) + i
].insn
, insn
);
7842 while (state
->time
< t
)
7843 mips_sim_next_cycle (state
);
7847 /* A for_each_rtx callback. If *X is a register, advance simulation state
7848 DATA until mips_sim_insn can read the register's value. */
7851 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
7854 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
7858 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
7861 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
7863 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
7866 /* Advance simulation state STATE until all of INSN's register
7867 dependencies are satisfied. */
7870 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
7872 mips_sim_insn
= insn
;
7873 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
7876 /* Advance simulation state STATE until the units required by
7877 instruction INSN are available. */
7880 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
7884 tmp_state
= alloca (state_size ());
7885 while (state
->insns_left
== 0
7886 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
7887 state_transition (tmp_state
, insn
) >= 0))
7888 mips_sim_next_cycle (state
);
7891 /* Advance simulation state STATE until INSN is ready to issue. */
7894 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
7896 mips_sim_wait_regs (state
, insn
);
7897 mips_sim_wait_units (state
, insn
);
7900 /* mips_sim_insn has just set X. Update the LAST_SET array
7901 in simulation state DATA. */
7904 mips_sim_record_set (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
7906 struct mips_sim
*state
;
7911 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
7913 state
->last_set
[REGNO (x
) + i
].insn
= mips_sim_insn
;
7914 state
->last_set
[REGNO (x
) + i
].time
= state
->time
;
7918 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
7919 can issue immediately (i.e., that mips_sim_wait_insn has already
7923 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
7925 state_transition (state
->dfa_state
, insn
);
7926 state
->insns_left
--;
7928 mips_sim_insn
= insn
;
7929 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
7932 /* Simulate issuing a NOP in state STATE. */
7935 mips_sim_issue_nop (struct mips_sim
*state
)
7937 if (state
->insns_left
== 0)
7938 mips_sim_next_cycle (state
);
7939 state
->insns_left
--;
7942 /* Update simulation state STATE so that it's ready to accept the instruction
7943 after INSN. INSN should be part of the main rtl chain, not a member of a
7947 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
7949 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
7951 mips_sim_issue_nop (state
);
7953 switch (GET_CODE (SEQ_BEGIN (insn
)))
7957 /* We can't predict the processor state after a call or label. */
7958 mips_sim_reset (state
);
7962 /* The delay slots of branch likely instructions are only executed
7963 when the branch is taken. Therefore, if the caller has simulated
7964 the delay slot instruction, STATE does not really reflect the state
7965 of the pipeline for the instruction after the delay slot. Also,
7966 branch likely instructions tend to incur a penalty when not taken,
7967 so there will probably be an extra delay between the branch and
7968 the instruction after the delay slot. */
7969 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
7970 mips_sim_reset (state
);
7978 /* The VR4130 pipeline issues aligned pairs of instructions together,
7979 but it stalls the second instruction if it depends on the first.
7980 In order to cut down the amount of logic required, this dependence
7981 check is not based on a full instruction decode. Instead, any non-SPECIAL
7982 instruction is assumed to modify the register specified by bits 20-16
7983 (which is usually the "rt" field).
7985 In beq, beql, bne and bnel instructions, the rt field is actually an
7986 input, so we can end up with a false dependence between the branch
7987 and its delay slot. If this situation occurs in instruction INSN,
7988 try to avoid it by swapping rs and rt. */
7991 vr4130_avoid_branch_rt_conflict (rtx insn
)
7995 first
= SEQ_BEGIN (insn
);
7996 second
= SEQ_END (insn
);
7997 if (GET_CODE (first
) == JUMP_INSN
7998 && GET_CODE (second
) == INSN
7999 && GET_CODE (PATTERN (first
)) == SET
8000 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
8001 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
8003 /* Check for the right kind of condition. */
8004 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
8005 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8006 && REG_P (XEXP (cond
, 0))
8007 && REG_P (XEXP (cond
, 1))
8008 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
8009 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
8011 /* SECOND mentions the rt register but not the rs register. */
8012 rtx tmp
= XEXP (cond
, 0);
8013 XEXP (cond
, 0) = XEXP (cond
, 1);
8014 XEXP (cond
, 1) = tmp
;
8019 /* Implement -mvr4130-align. Go through each basic block and simulate the
8020 processor pipeline. If we find that a pair of instructions could execute
8021 in parallel, and the first of those instruction is not 8-byte aligned,
8022 insert a nop to make it aligned. */
8025 vr4130_align_insns (void)
8027 struct mips_sim state
;
8028 rtx insn
, subinsn
, last
, last2
, next
;
8033 /* LAST is the last instruction before INSN to have a nonzero length.
8034 LAST2 is the last such instruction before LAST. */
8038 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8041 mips_sim_init (&state
, alloca (state_size ()));
8042 for (insn
= get_insns (); insn
!= 0; insn
= next
)
8044 unsigned int length
;
8046 next
= NEXT_INSN (insn
);
8048 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8049 This isn't really related to the alignment pass, but we do it on
8050 the fly to avoid a separate instruction walk. */
8051 vr4130_avoid_branch_rt_conflict (insn
);
8053 if (USEFUL_INSN_P (insn
))
8054 FOR_EACH_SUBINSN (subinsn
, insn
)
8056 mips_sim_wait_insn (&state
, subinsn
);
8058 /* If we want this instruction to issue in parallel with the
8059 previous one, make sure that the previous instruction is
8060 aligned. There are several reasons why this isn't worthwhile
8061 when the second instruction is a call:
8063 - Calls are less likely to be performance critical,
8064 - There's a good chance that the delay slot can execute
8065 in parallel with the call.
8066 - The return address would then be unaligned.
8068 In general, if we're going to insert a nop between instructions
8069 X and Y, it's better to insert it immediately after X. That
8070 way, if the nop makes Y aligned, it will also align any labels
8072 if (state
.insns_left
!= state
.issue_rate
8073 && GET_CODE (subinsn
) != CALL_INSN
)
8075 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
8077 /* SUBINSN is the first instruction in INSN and INSN is
8078 aligned. We want to align the previous instruction
8079 instead, so insert a nop between LAST2 and LAST.
8081 Note that LAST could be either a single instruction
8082 or a branch with a delay slot. In the latter case,
8083 LAST, like INSN, is already aligned, but the delay
8084 slot must have some extra delay that stops it from
8085 issuing at the same time as the branch. We therefore
8086 insert a nop before the branch in order to align its
8088 emit_insn_after (gen_nop (), last2
);
8091 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
8093 /* SUBINSN is the delay slot of INSN, but INSN is
8094 currently unaligned. Insert a nop between
8095 LAST and INSN to align it. */
8096 emit_insn_after (gen_nop (), last
);
8100 mips_sim_issue_insn (&state
, subinsn
);
8102 mips_sim_finish_insn (&state
, insn
);
8104 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8105 length
= get_attr_length (insn
);
8108 /* If the instruction is an asm statement or multi-instruction
8109 mips.md patern, the length is only an estimate. Insert an
8110 8 byte alignment after it so that the following instructions
8111 can be handled correctly. */
8112 if (GET_CODE (SEQ_BEGIN (insn
)) == INSN
8113 && (recog_memoized (insn
) < 0 || length
>= 8))
8115 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
8116 next
= NEXT_INSN (next
);
8117 mips_sim_next_cycle (&state
);
8120 else if (length
& 4)
8121 aligned_p
= !aligned_p
;
8126 /* See whether INSN is an aligned label. */
8127 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
8133 /* Subroutine of mips_reorg. If there is a hazard between INSN
8134 and a previous instruction, avoid it by inserting nops after
8137 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8138 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8139 before using the value of that register. *HILO_DELAY counts the
8140 number of instructions since the last hilo hazard (that is,
8141 the number of instructions since the last mflo or mfhi).
8143 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8144 for the next instruction.
8146 LO_REG is an rtx for the LO register, used in dependence checking. */
8149 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
8150 rtx
*delayed_reg
, rtx lo_reg
)
8158 pattern
= PATTERN (insn
);
8160 /* Do not put the whole function in .set noreorder if it contains
8161 an asm statement. We don't know whether there will be hazards
8162 between the asm statement and the gcc-generated code. */
8163 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
8164 cfun
->machine
->all_noreorder_p
= false;
8166 /* Ignore zero-length instructions (barriers and the like). */
8167 ninsns
= get_attr_length (insn
) / 4;
8171 /* Work out how many nops are needed. Note that we only care about
8172 registers that are explicitly mentioned in the instruction's pattern.
8173 It doesn't matter that calls use the argument registers or that they
8174 clobber hi and lo. */
8175 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
8176 nops
= 2 - *hilo_delay
;
8177 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
8182 /* Insert the nops between this instruction and the previous one.
8183 Each new nop takes us further from the last hilo hazard. */
8184 *hilo_delay
+= nops
;
8186 emit_insn_after (gen_hazard_nop (), after
);
8188 /* Set up the state for the next instruction. */
8189 *hilo_delay
+= ninsns
;
8191 if (INSN_CODE (insn
) >= 0)
8192 switch (get_attr_hazard (insn
))
8202 set
= single_set (insn
);
8205 *delayed_reg
= SET_DEST (set
);
8211 /* Go through the instruction stream and insert nops where necessary.
8212 See if the whole function can then be put into .set noreorder &
8216 mips_avoid_hazards (void)
8218 rtx insn
, last_insn
, lo_reg
, delayed_reg
;
8221 /* Force all instructions to be split into their final form. */
8222 split_all_insns_noflow ();
8224 /* Recalculate instruction lengths without taking nops into account. */
8225 cfun
->machine
->ignore_hazard_length_p
= true;
8226 shorten_branches (get_insns ());
8228 /* The profiler code uses assembler macros. -mfix-vr4120 relies on
8229 assembler nop insertion. */
8230 cfun
->machine
->all_noreorder_p
= (!current_function_profile
8231 && !TARGET_FIX_VR4120
);
8236 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
8238 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
8241 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8242 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
8243 mips_avoid_hazard (last_insn
, XVECEXP (PATTERN (insn
), 0, i
),
8244 &hilo_delay
, &delayed_reg
, lo_reg
);
8246 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
8247 &delayed_reg
, lo_reg
);
8254 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8260 mips16_lay_out_constants ();
8261 else if (TARGET_EXPLICIT_RELOCS
)
8263 if (mips_flag_delayed_branch
)
8264 dbr_schedule (get_insns (), dump_file
);
8265 mips_avoid_hazards ();
8266 if (TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
8267 vr4130_align_insns ();
8271 /* This function does three things:
8273 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8274 - Register the mips16 hardware floating point stubs.
8275 - Register the gofast functions if selected using --enable-gofast. */
8277 #include "config/gofast.h"
8280 mips_init_libfuncs (void)
8282 if (TARGET_FIX_VR4120
)
8284 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
8285 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
8288 if (TARGET_MIPS16
&& mips16_hard_float
)
8290 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
8291 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
8292 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
8293 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
8295 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
8296 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
8297 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
8298 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
8299 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
8300 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
8302 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
8303 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
8305 if (TARGET_DOUBLE_FLOAT
)
8307 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
8308 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
8309 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
8310 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
8312 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
8313 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
8314 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
8315 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
8316 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
8317 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
8319 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__mips16_extendsfdf2");
8320 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__mips16_truncdfsf2");
8322 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__mips16_fix_truncdfsi");
8323 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__mips16_floatsidf");
8327 gofast_maybe_init_libfuncs ();
8330 /* Return a number assessing the cost of moving a register in class
8331 FROM to class TO. The classes are expressed using the enumeration
8332 values such as `GENERAL_REGS'. A value of 2 is the default; other
8333 values are interpreted relative to that.
8335 It is not required that the cost always equal 2 when FROM is the
8336 same as TO; on some machines it is expensive to move between
8337 registers if they are not general registers.
8339 If reload sees an insn consisting of a single `set' between two
8340 hard registers, and if `REGISTER_MOVE_COST' applied to their
8341 classes returns a value of 2, reload does not check to ensure that
8342 the constraints of the insn are met. Setting a cost of other than
8343 2 will allow reload to verify that the constraints are met. You
8344 should do this if the `movM' pattern's constraints do not allow
8347 ??? We make the cost of moving from HI/LO into general
8348 registers the same as for one of moving general registers to
8349 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8350 pseudo to HI/LO. This might hurt optimizations though, it
8351 isn't clear if it is wise. And it might not work in all cases. We
8352 could solve the DImode LO reg problem by using a multiply, just
8353 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8354 problem by using divide instructions. divu puts the remainder in
8355 the HI reg, so doing a divide by -1 will move the value in the HI
8356 reg for all values except -1. We could handle that case by using a
8357 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8358 a compare/branch to test the input value to see which instruction
8359 we need to use. This gets pretty messy, but it is feasible. */
8362 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
8363 enum reg_class to
, enum reg_class from
)
8365 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
8367 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
8369 else if (GR_REG_CLASS_P (from
))
8373 else if (to
== M16_NA_REGS
)
8375 else if (GR_REG_CLASS_P (to
))
8382 else if (to
== FP_REGS
)
8384 else if (to
== HI_REG
|| to
== LO_REG
|| to
== MD_REGS
)
8391 else if (COP_REG_CLASS_P (to
))
8395 } /* GR_REG_CLASS_P (from) */
8396 else if (from
== FP_REGS
)
8398 if (GR_REG_CLASS_P (to
))
8400 else if (to
== FP_REGS
)
8402 else if (to
== ST_REGS
)
8404 } /* from == FP_REGS */
8405 else if (from
== HI_REG
|| from
== LO_REG
|| from
== MD_REGS
)
8407 if (GR_REG_CLASS_P (to
))
8414 } /* from == HI_REG, etc. */
8415 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
8417 else if (COP_REG_CLASS_P (from
))
8420 } /* COP_REG_CLASS_P (from) */
8427 /* Return the length of INSN. LENGTH is the initial length computed by
8428 attributes in the machine-description file. */
8431 mips_adjust_insn_length (rtx insn
, int length
)
8433 /* A unconditional jump has an unfilled delay slot if it is not part
8434 of a sequence. A conditional jump normally has a delay slot, but
8435 does not on MIPS16. */
8436 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
8439 /* See how many nops might be needed to avoid hardware hazards. */
8440 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
8441 switch (get_attr_hazard (insn
))
8455 /* All MIPS16 instructions are a measly two bytes. */
8463 /* Return an asm sequence to start a noat block and load the address
8464 of a label into $1. */
8467 mips_output_load_label (void)
8469 if (TARGET_EXPLICIT_RELOCS
)
8473 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8476 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8479 if (ISA_HAS_LOAD_DELAY
)
8480 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8481 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8485 if (Pmode
== DImode
)
8486 return "%[dla\t%@,%0";
8488 return "%[la\t%@,%0";
8493 /* Output assembly instructions to peform a conditional branch.
8495 INSN is the branch instruction. OPERANDS[0] is the condition.
8496 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8497 of the first operand to the condition. If TWO_OPERANDS_P is
8498 nonzero the comparison takes two operands; OPERANDS[3] will be the
8501 If INVERTED_P is nonzero we are to branch if the condition does
8502 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8504 LENGTH is the length (in bytes) of the sequence we are to generate.
8505 That tells us whether to generate a simple conditional branch, or a
8506 reversed conditional branch around a `jr' instruction. */
8508 mips_output_conditional_branch (rtx insn
, rtx
*operands
, int two_operands_p
,
8509 int float_p
, int inverted_p
, int length
)
8511 static char buffer
[200];
8512 /* The kind of comparison we are doing. */
8513 enum rtx_code code
= GET_CODE (operands
[0]);
8514 /* Nonzero if the opcode for the comparison needs a `z' indicating
8515 that it is a comparison against zero. */
8517 /* A string to use in the assembly output to represent the first
8519 const char *op1
= "%z2";
8520 /* A string to use in the assembly output to represent the second
8521 operand. Use the hard-wired zero register if there's no second
8523 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
8524 /* The operand-printing string for the comparison. */
8525 const char *const comp
= (float_p
? "%F0" : "%C0");
8526 /* The operand-printing string for the inverted comparison. */
8527 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
8529 /* The MIPS processors (for levels of the ISA at least two), have
8530 "likely" variants of each branch instruction. These instructions
8531 annul the instruction in the delay slot if the branch is not
8533 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
8535 if (!two_operands_p
)
8537 /* To compute whether than A > B, for example, we normally
8538 subtract B from A and then look at the sign bit. But, if we
8539 are doing an unsigned comparison, and B is zero, we don't
8540 have to do the subtraction. Instead, we can just check to
8541 see if A is nonzero. Thus, we change the CODE here to
8542 reflect the simpler comparison operation. */
8554 /* A condition which will always be true. */
8560 /* A condition which will always be false. */
8566 /* Not a special case. */
8571 /* Relative comparisons are always done against zero. But
8572 equality comparisons are done between two operands, and therefore
8573 do not require a `z' in the assembly language output. */
8574 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
8575 /* For comparisons against zero, the zero is not provided
8580 /* Begin by terminating the buffer. That way we can always use
8581 strcat to add to it. */
8588 /* Just a simple conditional branch. */
8590 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1%%/",
8591 inverted_p
? inverted_comp
: comp
);
8593 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1%%/",
8594 inverted_p
? inverted_comp
: comp
,
8595 need_z_p
? "z" : "",
8605 /* Generate a reversed conditional branch around ` j'
8618 If the original branch was a likely branch, the delay slot
8619 must be executed only if the branch is taken, so generate:
8631 When generating PIC, instead of:
8644 rtx target
= gen_label_rtx ();
8646 orig_target
= operands
[1];
8647 operands
[1] = target
;
8648 /* Generate the reversed comparison. This takes four
8651 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
8652 inverted_p
? comp
: inverted_comp
);
8654 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
8655 inverted_p
? comp
: inverted_comp
,
8656 need_z_p
? "z" : "",
8659 output_asm_insn (buffer
, operands
);
8661 if (length
!= 16 && length
!= 28 && ! mips_branch_likely
)
8663 /* Output delay slot instruction. */
8664 rtx insn
= final_sequence
;
8665 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
8666 optimize
, 0, 1, NULL
);
8667 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
8670 output_asm_insn ("%#", 0);
8673 output_asm_insn ("j\t%0", &orig_target
);
8676 output_asm_insn (mips_output_load_label (), &orig_target
);
8677 output_asm_insn ("jr\t%@%]", 0);
8680 if (length
!= 16 && length
!= 28 && mips_branch_likely
)
8682 /* Output delay slot instruction. */
8683 rtx insn
= final_sequence
;
8684 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
8685 optimize
, 0, 1, NULL
);
8686 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
8689 output_asm_insn ("%#", 0);
8691 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
8692 CODE_LABEL_NUMBER (target
));
8705 /* Used to output div or ddiv instruction DIVISION, which has the operands
8706 given by OPERANDS. Add in a divide-by-zero check if needed.
8708 When working around R4000 and R4400 errata, we need to make sure that
8709 the division is not immediately followed by a shift[1][2]. We also
8710 need to stop the division from being put into a branch delay slot[3].
8711 The easiest way to avoid both problems is to add a nop after the
8712 division. When a divide-by-zero check is needed, this nop can be
8713 used to fill the branch delay slot.
8715 [1] If a double-word or a variable shift executes immediately
8716 after starting an integer division, the shift may give an
8717 incorrect result. See quotations of errata #16 and #28 from
8718 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
8719 in mips.md for details.
8721 [2] A similar bug to [1] exists for all revisions of the
8722 R4000 and the R4400 when run in an MC configuration.
8723 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
8725 "19. In this following sequence:
8727 ddiv (or ddivu or div or divu)
8728 dsll32 (or dsrl32, dsra32)
8730 if an MPT stall occurs, while the divide is slipping the cpu
8731 pipeline, then the following double shift would end up with an
8734 Workaround: The compiler needs to avoid generating any
8735 sequence with divide followed by extended double shift."
8737 This erratum is also present in "MIPS R4400MC Errata, Processor
8738 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
8739 & 3.0" as errata #10 and #4, respectively.
8741 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
8742 (also valid for MIPS R4000MC processors):
8744 "52. R4000SC: This bug does not apply for the R4000PC.
8746 There are two flavors of this bug:
8748 1) If the instruction just after divide takes an RF exception
8749 (tlb-refill, tlb-invalid) and gets an instruction cache
8750 miss (both primary and secondary) and the line which is
8751 currently in secondary cache at this index had the first
8752 data word, where the bits 5..2 are set, then R4000 would
8753 get a wrong result for the div.
8758 ------------------- # end-of page. -tlb-refill
8763 ------------------- # end-of page. -tlb-invalid
8766 2) If the divide is in the taken branch delay slot, where the
8767 target takes RF exception and gets an I-cache miss for the
8768 exception vector or where I-cache miss occurs for the
8769 target address, under the above mentioned scenarios, the
8770 div would get wrong results.
8773 j r2 # to next page mapped or unmapped
8774 div r8,r9 # this bug would be there as long
8775 # as there is an ICache miss and
8776 nop # the "data pattern" is present
8779 beq r0, r0, NextPage # to Next page
8783 This bug is present for div, divu, ddiv, and ddivu
8786 Workaround: For item 1), OS could make sure that the next page
8787 after the divide instruction is also mapped. For item 2), the
8788 compiler could make sure that the divide instruction is not in
8789 the branch delay slot."
8791 These processors have PRId values of 0x00004220 and 0x00004300 for
8792 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
8795 mips_output_division (const char *division
, rtx
*operands
)
8800 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
8802 output_asm_insn (s
, operands
);
8805 if (TARGET_CHECK_ZERO_DIV
)
8809 output_asm_insn (s
, operands
);
8810 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
8814 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
8815 output_asm_insn (s
, operands
);
8816 s
= "break\t7%)\n1:";
8822 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
8823 with a final "000" replaced by "k". Ignore case.
8825 Note: this function is shared between GCC and GAS. */
8828 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
8830 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
8831 given
++, canonical
++;
8833 return ((*given
== 0 && *canonical
== 0)
8834 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
8838 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
8839 CPU name. We've traditionally allowed a lot of variation here.
8841 Note: this function is shared between GCC and GAS. */
8844 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
8846 /* First see if the name matches exactly, or with a final "000"
8848 if (mips_strict_matching_cpu_name_p (canonical
, given
))
8851 /* If not, try comparing based on numerical designation alone.
8852 See if GIVEN is an unadorned number, or 'r' followed by a number. */
8853 if (TOLOWER (*given
) == 'r')
8855 if (!ISDIGIT (*given
))
8858 /* Skip over some well-known prefixes in the canonical name,
8859 hoping to find a number there too. */
8860 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
8862 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
8864 else if (TOLOWER (canonical
[0]) == 'r')
8867 return mips_strict_matching_cpu_name_p (canonical
, given
);
8871 /* Parse an option that takes the name of a processor as its argument.
8872 OPTION is the name of the option and CPU_STRING is the argument.
8873 Return the corresponding processor enumeration if the CPU_STRING is
8874 recognized, otherwise report an error and return null.
8876 A similar function exists in GAS. */
8878 static const struct mips_cpu_info
*
8879 mips_parse_cpu (const char *option
, const char *cpu_string
)
8881 const struct mips_cpu_info
*p
;
8884 /* In the past, we allowed upper-case CPU names, but it doesn't
8885 work well with the multilib machinery. */
8886 for (s
= cpu_string
; *s
!= 0; s
++)
8889 warning ("the cpu name must be lower case");
8893 /* 'from-abi' selects the most compatible architecture for the given
8894 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
8895 EABIs, we have to decide whether we're using the 32-bit or 64-bit
8896 version. Look first at the -mgp options, if given, otherwise base
8897 the choice on MASK_64BIT in TARGET_DEFAULT. */
8898 if (strcasecmp (cpu_string
, "from-abi") == 0)
8899 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
8900 : ABI_NEEDS_64BIT_REGS
? 3
8901 : (TARGET_64BIT
? 3 : 1));
8903 /* 'default' has traditionally been a no-op. Probably not very useful. */
8904 if (strcasecmp (cpu_string
, "default") == 0)
8907 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
8908 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
8911 error ("bad value (%s) for %s", cpu_string
, option
);
8916 /* Return the processor associated with the given ISA level, or null
8917 if the ISA isn't valid. */
8919 static const struct mips_cpu_info
*
8920 mips_cpu_info_from_isa (int isa
)
8922 const struct mips_cpu_info
*p
;
8924 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
8931 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
8932 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
8933 they only hold condition code modes, and CCmode is always considered to
8934 be 4 bytes wide. All other registers are word sized. */
8937 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
8939 if (ST_REG_P (regno
))
8940 return ((GET_MODE_SIZE (mode
) + 3) / 4);
8941 else if (! FP_REG_P (regno
))
8942 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
8944 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
8947 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
8948 all BLKmode objects are returned in memory. Under the new (N32 and
8949 64-bit MIPS ABIs) small structures are returned in a register.
8950 Objects with varying size must still be returned in memory, of
8954 mips_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
8957 return (TYPE_MODE (type
) == BLKmode
);
8959 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
8960 || (int_size_in_bytes (type
) == -1));
8964 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
8966 return !TARGET_OLDABI
;
8969 /* Return true if INSN is a multiply-add or multiply-subtract
8970 instruction and PREV assigns to the accumulator operand. */
8973 mips_linked_madd_p (rtx prev
, rtx insn
)
8977 x
= single_set (insn
);
8983 if (GET_CODE (x
) == PLUS
8984 && GET_CODE (XEXP (x
, 0)) == MULT
8985 && reg_set_p (XEXP (x
, 1), prev
))
8988 if (GET_CODE (x
) == MINUS
8989 && GET_CODE (XEXP (x
, 1)) == MULT
8990 && reg_set_p (XEXP (x
, 0), prev
))
8996 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
8997 that may clobber hi or lo. */
8999 static rtx mips_macc_chains_last_hilo
;
9001 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9002 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9005 mips_macc_chains_record (rtx insn
)
9007 if (get_attr_may_clobber_hilo (insn
))
9008 mips_macc_chains_last_hilo
= insn
;
9011 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9012 has NREADY elements, looking for a multiply-add or multiply-subtract
9013 instruction that is cumulative with mips_macc_chains_last_hilo.
9014 If there is one, promote it ahead of anything else that might
9015 clobber hi or lo. */
9018 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9022 if (mips_macc_chains_last_hilo
!= 0)
9023 for (i
= nready
- 1; i
>= 0; i
--)
9024 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9026 for (j
= nready
- 1; j
> i
; j
--)
9027 if (recog_memoized (ready
[j
]) >= 0
9028 && get_attr_may_clobber_hilo (ready
[j
]))
9030 mips_promote_ready (ready
, i
, j
);
9037 /* The last instruction to be scheduled. */
9039 static rtx vr4130_last_insn
;
9041 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9042 points to an rtx that is initially an instruction. Nullify the rtx
9043 if the instruction uses the value of register X. */
9046 vr4130_true_reg_dependence_p_1 (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
9048 rtx
*insn_ptr
= data
;
9051 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9055 /* Return true if there is true register dependence between vr4130_last_insn
9059 vr4130_true_reg_dependence_p (rtx insn
)
9061 note_stores (PATTERN (vr4130_last_insn
),
9062 vr4130_true_reg_dependence_p_1
, &insn
);
9066 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9067 the ready queue and that INSN2 is the instruction after it, return
9068 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9069 in which INSN1 and INSN2 can probably issue in parallel, but for
9070 which (INSN2, INSN1) should be less sensitive to instruction
9071 alignment than (INSN1, INSN2). See 4130.md for more details. */
9074 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9078 /* Check for the following case:
9080 1) there is some other instruction X with an anti dependence on INSN1;
9081 2) X has a higher priority than INSN2; and
9082 3) X is an arithmetic instruction (and thus has no unit restrictions).
9084 If INSN1 is the last instruction blocking X, it would better to
9085 choose (INSN1, X) over (INSN2, INSN1). */
9086 for (dep
= INSN_DEPEND (insn1
); dep
!= 0; dep
= XEXP (dep
, 1))
9087 if (REG_NOTE_KIND (dep
) == REG_DEP_ANTI
9088 && INSN_PRIORITY (XEXP (dep
, 0)) > INSN_PRIORITY (insn2
)
9089 && recog_memoized (XEXP (dep
, 0)) >= 0
9090 && get_attr_vr4130_class (XEXP (dep
, 0)) == VR4130_CLASS_ALU
)
9093 if (vr4130_last_insn
!= 0
9094 && recog_memoized (insn1
) >= 0
9095 && recog_memoized (insn2
) >= 0)
9097 /* See whether INSN1 and INSN2 use different execution units,
9098 or if they are both ALU-type instructions. If so, they can
9099 probably execute in parallel. */
9100 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9101 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9102 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9104 /* If only one of the instructions has a dependence on
9105 vr4130_last_insn, prefer to schedule the other one first. */
9106 bool dep1
= vr4130_true_reg_dependence_p (insn1
);
9107 bool dep2
= vr4130_true_reg_dependence_p (insn2
);
9111 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9112 is not an ALU-type instruction and if INSN1 uses the same
9113 execution unit. (Note that if this condition holds, we already
9114 know that INSN2 uses a different execution unit.) */
9115 if (class1
!= VR4130_CLASS_ALU
9116 && recog_memoized (vr4130_last_insn
) >= 0
9117 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9124 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9125 queue with at least two instructions. Swap the first two if
9126 vr4130_swap_insns_p says that it could be worthwhile. */
9129 vr4130_reorder (rtx
*ready
, int nready
)
9131 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9132 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9135 /* Remove the instruction at index LOWER from ready queue READY and
9136 reinsert it in front of the instruction at index HIGHER. LOWER must
9140 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9145 new_head
= ready
[lower
];
9146 for (i
= lower
; i
< higher
; i
++)
9147 ready
[i
] = ready
[i
+ 1];
9148 ready
[i
] = new_head
;
9151 /* Implement TARGET_SCHED_REORDER. */
9154 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9155 rtx
*ready
, int *nreadyp
, int cycle
)
9157 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9160 mips_macc_chains_last_hilo
= 0;
9162 mips_macc_chains_reorder (ready
, *nreadyp
);
9164 if (reload_completed
&& TUNE_MIPS4130
&& !TARGET_VR4130_ALIGN
)
9167 vr4130_last_insn
= 0;
9169 vr4130_reorder (ready
, *nreadyp
);
9171 return mips_issue_rate ();
9174 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9177 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9180 switch (GET_CODE (PATTERN (insn
)))
9184 /* Don't count USEs and CLOBBERs against the issue rate. */
9189 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9190 mips_macc_chains_record (insn
);
9191 vr4130_last_insn
= insn
;
9197 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9198 dependencies have no cost. */
9201 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9202 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9204 if (REG_NOTE_KIND (link
) != 0)
9209 /* Return the number of instructions that can be issued per cycle. */
9212 mips_issue_rate (void)
9216 case PROCESSOR_R4130
:
9217 case PROCESSOR_R5400
:
9218 case PROCESSOR_R5500
:
9219 case PROCESSOR_R7000
:
9220 case PROCESSOR_R9000
:
9224 /* This is actually 4, but we get better performance if we claim 3.
9225 This is partly because of unwanted speculative code motion with the
9226 larger number, and partly because in most common cases we can't
9227 reach the theoretical max of 4. */
9238 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9239 be as wide as the scheduling freedom in the DFA. */
9242 mips_multipass_dfa_lookahead (void)
9244 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9245 if (mips_tune
== PROCESSOR_SB1
)
9251 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9252 return the first operand of the associated "pref" or "prefx" insn. */
9255 mips_prefetch_cookie (rtx write
, rtx locality
)
9257 /* store_streamed / load_streamed. */
9258 if (INTVAL (locality
) <= 0)
9259 return GEN_INT (INTVAL (write
) + 4);
9262 if (INTVAL (locality
) <= 2)
9265 /* store_retained / load_retained. */
9266 return GEN_INT (INTVAL (write
) + 6);
9269 /* MIPS builtin function support. */
9271 struct builtin_description
9273 /* The code of the main .md file instruction. See mips_builtin_type
9274 for more information. */
9275 enum insn_code icode
;
9277 /* The name of the builtin function. */
9280 /* Specifies how the function should be expanded. */
9281 enum mips_builtin_type builtin_type
;
9283 /* The function's prototype. */
9284 enum mips_function_type function_type
;
9286 /* The target flags required for this function. */
9290 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9291 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9292 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9293 { CODE_FOR_mips_ ## INSN, "__builtin_mips_" #INSN, \
9294 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9296 /* Define builtins for scalar comparison instructions CODE_FOR_mips_<INSN>_s
9297 and CODE_FOR_mips_<INSN>_d, both of which require TARGET_FLAGS. */
9298 #define CMP_SCALAR_BUILTINS(INSN, TARGET_FLAGS) \
9299 { CODE_FOR_mips_ ## INSN ## _s, "__builtin_mips_" #INSN "_s", \
9300 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9301 { CODE_FOR_mips_ ## INSN ## _d, "__builtin_mips_" #INSN "_d", \
9302 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9304 /* Define builtins for PS comparison instruction CODE_FOR_mips_<INSN>_ps.
9305 The lower and upper forms require TARGET_FLAGS while the any and all
9306 forms require MASK_MIPS3D. */
9307 #define CMP_PS_BUILTINS(INSN, TARGET_FLAGS) \
9308 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_any_" #INSN "_ps", \
9309 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9310 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_all_" #INSN "_ps", \
9311 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9312 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_lower_" #INSN "_ps", \
9313 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9314 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_upper_" #INSN "_ps", \
9315 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9317 /* Define builtins for instruction CODE_FOR_mips_<INSN>_4s, which compares
9318 two pairs of V2SF vectors. The functions require MASK_MIPS3D. */
9319 #define CMP_4S_BUILTINS(INSN) \
9320 { CODE_FOR_mips_ ## INSN ## _4s, "__builtin_mips_any_" #INSN "_4s", \
9321 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9323 { CODE_FOR_mips_ ## INSN ## _4s, "__builtin_mips_all_" #INSN "_4s", \
9324 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9327 /* Define movt and movf builtins that use CODE_FOR_mips_<INSN>_ps as
9328 the comparison instruction. The comparison instruction requires
9330 #define MOVTF_BUILTINS(INSN, TARGET_FLAGS) \
9331 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_movt_" #INSN "_ps", \
9332 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9334 { CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_movf_" #INSN "_ps", \
9335 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9338 /* Define all the builtins related to c.cond.fmt condition COND. */
9339 #define CMP_BUILTINS(COND) \
9340 MOVTF_BUILTINS (c_ ## COND, MASK_PAIRED_SINGLE), \
9341 MOVTF_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
9342 CMP_SCALAR_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
9343 CMP_PS_BUILTINS (c_ ## COND, MASK_PAIRED_SINGLE), \
9344 CMP_PS_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
9345 CMP_4S_BUILTINS (c_ ## COND), \
9346 CMP_4S_BUILTINS (cabs_ ## COND)
9348 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9349 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
9351 static const struct builtin_description mips_bdesc
[] =
9353 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE
),
9354 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE
),
9355 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE
),
9356 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE
),
9357 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE
),
9358 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE
),
9359 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE
),
9360 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE
),
9362 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, MASK_PAIRED_SINGLE
),
9363 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9364 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9365 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9366 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9368 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
9369 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
9370 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9371 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
9372 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
9373 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9375 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
9376 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
9377 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9378 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
9379 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
9380 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9391 CMP_BUILTINS (ngle
),
9401 /* Take the head of argument list *ARGLIST and convert it into a form
9402 suitable for input operand OP of instruction ICODE. Return the value
9403 and point *ARGLIST at the next element of the list. */
9406 mips_prepare_builtin_arg (enum insn_code icode
,
9407 unsigned int op
, tree
*arglist
)
9410 enum machine_mode mode
;
9412 value
= expand_expr (TREE_VALUE (*arglist
), NULL_RTX
, VOIDmode
, 0);
9413 mode
= insn_data
[icode
].operand
[op
].mode
;
9414 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
9415 value
= copy_to_mode_reg (mode
, value
);
9417 *arglist
= TREE_CHAIN (*arglist
);
9421 /* Return an rtx suitable for output operand OP of instruction ICODE.
9422 If TARGET is non-null, try to use it where possible. */
9425 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
9427 enum machine_mode mode
;
9429 mode
= insn_data
[icode
].operand
[op
].mode
;
9430 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
9431 target
= gen_reg_rtx (mode
);
9436 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
9439 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9440 enum machine_mode mode ATTRIBUTE_UNUSED
,
9441 int ignore ATTRIBUTE_UNUSED
)
9443 enum insn_code icode
;
9444 enum mips_builtin_type type
;
9445 tree fndecl
, arglist
;
9448 fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9449 arglist
= TREE_OPERAND (exp
, 1);
9450 fcode
= DECL_FUNCTION_CODE (fndecl
);
9451 if (fcode
>= ARRAY_SIZE (mips_bdesc
))
9454 icode
= mips_bdesc
[fcode
].icode
;
9455 type
= mips_bdesc
[fcode
].builtin_type
;
9458 case MIPS_BUILTIN_DIRECT
:
9459 return mips_expand_builtin_direct (icode
, target
, arglist
);
9461 case MIPS_BUILTIN_MOVT
:
9462 case MIPS_BUILTIN_MOVF
:
9463 return mips_expand_builtin_movtf (type
, icode
, target
, arglist
);
9465 case MIPS_BUILTIN_CMP_ANY
:
9466 case MIPS_BUILTIN_CMP_ALL
:
9467 case MIPS_BUILTIN_CMP_UPPER
:
9468 case MIPS_BUILTIN_CMP_LOWER
:
9469 case MIPS_BUILTIN_CMP_SINGLE
:
9470 return mips_expand_builtin_compare (type
, icode
, target
, arglist
);
9477 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
9480 mips_init_builtins (void)
9482 const struct builtin_description
*d
;
9483 tree types
[(int) MIPS_MAX_FTYPE_MAX
];
9484 tree V2SF_type_node
;
9486 /* We have only builtins for -mpaired-single and -mips3d. */
9487 if (!TARGET_PAIRED_SINGLE_FLOAT
)
9490 V2SF_type_node
= build_vector_type_for_mode (float_type_node
, V2SFmode
);
9492 types
[MIPS_V2SF_FTYPE_V2SF
]
9493 = build_function_type_list (V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
9495 types
[MIPS_V2SF_FTYPE_V2SF_V2SF
]
9496 = build_function_type_list (V2SF_type_node
,
9497 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
9499 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_INT
]
9500 = build_function_type_list (V2SF_type_node
,
9501 V2SF_type_node
, V2SF_type_node
,
9502 integer_type_node
, NULL_TREE
);
9504 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
]
9505 = build_function_type_list (V2SF_type_node
,
9506 V2SF_type_node
, V2SF_type_node
,
9507 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
9509 types
[MIPS_V2SF_FTYPE_SF_SF
]
9510 = build_function_type_list (V2SF_type_node
,
9511 float_type_node
, float_type_node
, NULL_TREE
);
9513 types
[MIPS_INT_FTYPE_V2SF_V2SF
]
9514 = build_function_type_list (integer_type_node
,
9515 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
9517 types
[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
]
9518 = build_function_type_list (integer_type_node
,
9519 V2SF_type_node
, V2SF_type_node
,
9520 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
9522 types
[MIPS_INT_FTYPE_SF_SF
]
9523 = build_function_type_list (integer_type_node
,
9524 float_type_node
, float_type_node
, NULL_TREE
);
9526 types
[MIPS_INT_FTYPE_DF_DF
]
9527 = build_function_type_list (integer_type_node
,
9528 double_type_node
, double_type_node
, NULL_TREE
);
9530 types
[MIPS_SF_FTYPE_V2SF
]
9531 = build_function_type_list (float_type_node
, V2SF_type_node
, NULL_TREE
);
9533 types
[MIPS_SF_FTYPE_SF
]
9534 = build_function_type_list (float_type_node
,
9535 float_type_node
, NULL_TREE
);
9537 types
[MIPS_SF_FTYPE_SF_SF
]
9538 = build_function_type_list (float_type_node
,
9539 float_type_node
, float_type_node
, NULL_TREE
);
9541 types
[MIPS_DF_FTYPE_DF
]
9542 = build_function_type_list (double_type_node
,
9543 double_type_node
, NULL_TREE
);
9545 types
[MIPS_DF_FTYPE_DF_DF
]
9546 = build_function_type_list (double_type_node
,
9547 double_type_node
, double_type_node
, NULL_TREE
);
9549 for (d
= mips_bdesc
; d
< &mips_bdesc
[ARRAY_SIZE (mips_bdesc
)]; d
++)
9550 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
9551 lang_hooks
.builtin_function (d
->name
, types
[d
->function_type
],
9552 d
- mips_bdesc
, BUILT_IN_MD
, NULL
, NULL
);
9555 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
9556 .md pattern and ARGLIST is the list of function arguments. TARGET,
9557 if nonnull, suggests a good place to put the result. */
9560 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree arglist
)
9562 rtx ops
[MAX_RECOG_OPERANDS
];
9565 target
= mips_prepare_builtin_target (icode
, 0, target
);
9566 for (i
= 1; i
< insn_data
[icode
].n_operands
; i
++)
9567 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, &arglist
);
9569 switch (insn_data
[icode
].n_operands
)
9572 emit_insn (GEN_FCN (icode
) (target
, ops
[1]));
9576 emit_insn (GEN_FCN (icode
) (target
, ops
[1], ops
[2]));
9580 emit_insn (GEN_FCN (icode
) (target
, ops
[1], ops
[2], ops
[3]));
9589 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
9590 function (TYPE says which). ARGLIST is the list of arguments to
9591 the function and ICODE says which instruction should be used to
9592 compare the first two arguments. TARGET, if nonnull, suggests a
9593 good place to put the result. */
9596 mips_expand_builtin_movtf (enum mips_builtin_type type
, enum insn_code icode
,
9597 rtx target
, tree arglist
)
9599 rtx cmp_result
, op0
, op1
;
9601 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
9602 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
9603 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
9604 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
));
9606 icode
= CODE_FOR_mips_cond_move_tf_ps
;
9607 target
= mips_prepare_builtin_target (icode
, 0, target
);
9608 if (type
== MIPS_BUILTIN_MOVT
)
9610 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
9611 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
9615 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
9616 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
9618 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
9622 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code of
9623 the comparison instruction and ARGLIST is the list of function arguments.
9624 TARGET, if nonnull, suggests a good place to put the boolean result. */
9627 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
9628 enum insn_code icode
, rtx target
, tree arglist
)
9630 rtx label1
, label2
, if_then_else
;
9631 rtx pat
, cmp_result
, ops
[MAX_RECOG_OPERANDS
];
9632 rtx target_if_equal
, target_if_unequal
;
9635 if (target
== 0 || GET_MODE (target
) != SImode
)
9636 target
= gen_reg_rtx (SImode
);
9638 /* Prepare the operands to the comparison. */
9639 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
9640 for (i
= 1; i
< insn_data
[icode
].n_operands
; i
++)
9641 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, &arglist
);
9643 switch (insn_data
[icode
].n_operands
)
9646 pat
= GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2]);
9650 pat
= GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2], ops
[3], ops
[4]);
9657 /* If the comparison sets more than one register, we define the result
9658 to be 0 if all registers are false and -1 if all registers are true.
9659 The value of the complete result is indeterminate otherwise. It is
9660 possible to test individual registers using SUBREGs.
9662 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
9663 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
9664 and TARGET_IF_UNEQUAL otherwise. */
9665 if (builtin_type
== MIPS_BUILTIN_CMP_ALL
)
9668 target_if_equal
= const1_rtx
;
9669 target_if_unequal
= const0_rtx
;
9674 target_if_equal
= const0_rtx
;
9675 target_if_unequal
= const1_rtx
;
9676 if (builtin_type
== MIPS_BUILTIN_CMP_UPPER
)
9677 cmp_result
= simplify_gen_subreg (CCmode
, cmp_result
, CCV2mode
, 4);
9678 else if (builtin_type
== MIPS_BUILTIN_CMP_LOWER
)
9679 cmp_result
= simplify_gen_subreg (CCmode
, cmp_result
, CCV2mode
, 0);
9682 /* First assume that CMP_RESULT == CMP_VALUE. */
9683 emit_move_insn (target
, target_if_equal
);
9685 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
9687 label1
= gen_label_rtx ();
9688 label2
= gen_label_rtx ();
9690 = gen_rtx_IF_THEN_ELSE (VOIDmode
,
9691 gen_rtx_fmt_ee (NE
, GET_MODE (cmp_result
),
9692 cmp_result
, GEN_INT (cmp_value
)),
9693 gen_rtx_LABEL_REF (VOIDmode
, label1
), pc_rtx
);
9694 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
9695 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
9696 gen_rtx_LABEL_REF (VOIDmode
, label2
)));
9698 emit_label (label1
);
9700 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
9701 emit_move_insn (target
, target_if_unequal
);
9702 emit_label (label2
);
9707 #include "gt-mips.h"