| blob | 4d927c2b259b7e3c2b5691f3791f3ec82b6a8657 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
62 enum upper_128bits_state
63 {
65 unused,
66 used
67 };
70 {
71 /* State of the upper 128bits of AVX registers at exit. */
73 /* TRUE if state of the upper 128bits of AVX registers is unchanged
74 in this block. */
76 /* TRUE if block has been processed. */
78 /* TRUE if block has been scanned. */
80 /* Previous state of the upper 128bits of AVX registers at entry. */
84 #define BLOCK_INFO(B) ((block_info) (B)->aux)
86 enum call_avx256_state
87 {
88 /* Callee returns 256bit AVX register. */
90 /* Callee returns and passes 256bit AVX register. */
91 callee_return_pass_avx256,
92 /* Callee passes 256bit AVX register. */
93 callee_pass_avx256,
94 /* Callee doesn't return nor passe 256bit AVX register, or no
95 256bit AVX register in function return. */
96 call_no_avx256,
97 /* vzeroupper intrinsic. */
98 vzeroupper_intrinsic
99 };
101 /* Check if a 256bit AVX register is referenced in stores. */
103 static void
105 {
111 {
115 }
116 }
118 /* Helper function for move_or_delete_vzeroupper_1. Look for vzeroupper
119 in basic block BB. Delete it if upper 128bit AVX registers are
120 unused. If it isn't deleted, move it to just before a jump insn.
122 STATE is state of the upper 128bits of AVX registers at entry. */
124 static void
127 {
130 rtx pat;
135 {
142 }
145 {
150 }
160 /* BB_END changes when it is deleted. */
164 {
170 /* Move vzeroupper before jump/call. */
172 {
177 {
179 {
184 }
187 }
190 }
194 /* Check insn for vzeroupper intrinsic. */
197 {
199 {
200 /* Found vzeroupper intrinsic. */
203 }
204 }
205 else
206 {
207 /* Check insn for vzeroall intrinsic. */
211 {
215 /* Delete pending vzeroupper insertion. */
217 {
220 }
221 }
223 {
227 }
229 }
231 /* Process vzeroupper intrinsic. */
235 {
236 /* Since the upper 128bits are cleared, callee must not pass
237 256bit AVX register. We only need to check if callee
238 returns 256bit AVX register. */
240 {
243 }
245 /* Remove unnecessary vzeroupper since upper 128bits are
246 cleared. */
248 {
251 }
253 }
254 else
255 {
256 /* Set state to UNUSED if callee doesn't return 256bit AVX
257 register. */
263 {
264 /* Must remove vzeroupper since callee passes in 256bit
265 AVX register. */
267 {
270 }
272 }
273 else
274 {
277 }
278 }
279 }
288 state);
289 }
291 /* Helper function for move_or_delete_vzeroupper. Process vzeroupper
292 in BLOCK and check its predecessor blocks. Treat UNKNOWN state
293 as USED if UNKNOWN_IS_UNUSED is true. Return TRUE if the exit
294 state is changed. */
296 static bool
298 {
299 edge e;
300 edge_iterator ei;
313 /* Check all predecessor edges of this block. */
316 {
320 {
329 }
330 }
335 done:
343 /* Need to rescan if the upper 128bits of AVX registers are changed
344 to USED at exit. */
346 {
350 }
351 else
353 }
355 /* Go through the instruction stream looking for vzeroupper. Delete
356 it if upper 128bit AVX registers are unused. If it isn't deleted,
357 move it to just before a jump insn. */
359 static void
361 {
362 edge e;
363 edge_iterator ei;
364 basic_block bb;
371 /* Set up block info for each basic block. */
374 /* Process outgoing edges of entry point. */
379 {
384 }
386 /* Compute reverse completion order of depth first search of the CFG
387 so that the data-flow runs faster. */
402 /* Don't check outgoing edges of entry point. */
407 else
408 {
411 }
417 {
430 {
435 {
436 edge_iterator ei;
442 {
448 {
450 {
451 /* Send E->DEST to next round. */
456 }
457 }
459 {
460 /* Add E->DEST to current round. */
464 }
465 }
466 }
467 }
471 }
487 }
491 #ifndef CHECK_STACK_LIMIT
492 #define CHECK_STACK_LIMIT (-1)
493 #endif
495 /* Return index of given mode in mult and division cost tables. */
496 #define MODE_INDEX(mode) \
497 ((mode) == QImode ? 0 \
498 : (mode) == HImode ? 1 \
499 : (mode) == SImode ? 2 \
500 : (mode) == DImode ? 3 \
501 : 4)
503 /* Processor costs (relative to an add) */
504 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
505 #define COSTS_N_BYTES(N) ((N) * 2)
507 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
509 const
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
537 in SFmode, DFmode and XFmode */
539 in SFmode, DFmode and XFmode */
542 in SImode and DImode */
544 in SImode and DImode */
547 in SImode, DImode and TImode */
549 in SImode, DImode and TImode */
577 };
579 /* Processor costs (relative to an add) */
580 static const
603 in QImode, HImode and SImode.
604 Relative to reg-reg move (2). */
608 in SFmode, DFmode and XFmode */
610 in SFmode, DFmode and XFmode */
613 in SImode and DImode */
615 in SImode and DImode */
618 in SImode, DImode and TImode */
620 in SImode, DImode and TImode */
634 DUMMY_STRINGOP_ALGS},
636 DUMMY_STRINGOP_ALGS},
648 };
650 static const
673 in QImode, HImode and SImode.
674 Relative to reg-reg move (2). */
678 in SFmode, DFmode and XFmode */
680 in SFmode, DFmode and XFmode */
683 in SImode and DImode */
685 in SImode and DImode */
688 in SImode, DImode and TImode */
690 in SImode, DImode and TImode */
693 shared for code and data, so 4kB is
694 not really precise. */
706 DUMMY_STRINGOP_ALGS},
708 DUMMY_STRINGOP_ALGS},
720 };
722 static const
745 in QImode, HImode and SImode.
746 Relative to reg-reg move (2). */
750 in SFmode, DFmode and XFmode */
752 in SFmode, DFmode and XFmode */
755 in SImode and DImode */
757 in SImode and DImode */
760 in SImode, DImode and TImode */
762 in SImode, DImode and TImode */
776 DUMMY_STRINGOP_ALGS},
778 DUMMY_STRINGOP_ALGS},
790 };
792 static const
815 in QImode, HImode and SImode.
816 Relative to reg-reg move (2). */
820 in SFmode, DFmode and XFmode */
822 in SFmode, DFmode and XFmode */
825 in SImode and DImode */
827 in SImode and DImode */
830 in SImode, DImode and TImode */
832 in SImode, DImode and TImode */
845 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
846 (we ensure the alignment). For small blocks inline loop is still a
847 noticeable win, for bigger blocks either rep movsl or rep movsb is
848 way to go. Rep movsb has apparently more expensive startup time in CPU,
849 but after 4K the difference is down in the noise. */
852 DUMMY_STRINGOP_ALGS},
855 DUMMY_STRINGOP_ALGS},
867 };
869 static const
892 in QImode, HImode and SImode.
893 Relative to reg-reg move (2). */
897 in SFmode, DFmode and XFmode */
899 in SFmode, DFmode and XFmode */
903 in SImode and DImode */
905 in SImode and DImode */
908 in SImode, DImode and TImode */
910 in SImode, DImode and TImode */
924 DUMMY_STRINGOP_ALGS},
926 DUMMY_STRINGOP_ALGS},
938 };
940 static const
963 in QImode, HImode and SImode.
964 Relative to reg-reg move (2). */
968 in SFmode, DFmode and XFmode */
970 in SFmode, DFmode and XFmode */
973 in SImode and DImode */
975 in SImode and DImode */
978 in SImode, DImode and TImode */
980 in SImode, DImode and TImode */
984 have integrated l2 cache, but
985 optimizing for k6 is not important
986 enough to worry about that. */
997 DUMMY_STRINGOP_ALGS},
999 DUMMY_STRINGOP_ALGS},
1011 };
1013 static const
1036 in QImode, HImode and SImode.
1037 Relative to reg-reg move (2). */
1041 in SFmode, DFmode and XFmode */
1043 in SFmode, DFmode and XFmode */
1046 in SImode and DImode */
1048 in SImode and DImode */
1051 in SImode, DImode and TImode */
1053 in SImode, DImode and TImode */
1066 /* For some reason, Athlon deals better with REP prefix (relative to loops)
1067 compared to K8. Alignment becomes important after 8 bytes for memcpy and
1068 128 bytes for memset. */
1070 DUMMY_STRINGOP_ALGS},
1072 DUMMY_STRINGOP_ALGS},
1084 };
1086 static const
1109 in QImode, HImode and SImode.
1110 Relative to reg-reg move (2). */
1114 in SFmode, DFmode and XFmode */
1116 in SFmode, DFmode and XFmode */
1119 in SImode and DImode */
1121 in SImode and DImode */
1124 in SImode, DImode and TImode */
1126 in SImode, DImode and TImode */
1131 /* New AMD processors never drop prefetches; if they cannot be performed
1132 immediately, they are queued. We set number of simultaneous prefetches
1133 to a large constant to reflect this (it probably is not a good idea not
1134 to limit number of prefetches at all, as their execution also takes some
1135 time). */
1144 /* K8 has optimized REP instruction for medium sized blocks, but for very
1145 small blocks it is better to use loop. For large blocks, libcall can
1146 do nontemporary accesses and beat inline considerably. */
1163 };
1187 in QImode, HImode and SImode.
1188 Relative to reg-reg move (2). */
1192 in SFmode, DFmode and XFmode */
1194 in SFmode, DFmode and XFmode */
1197 in SImode and DImode */
1199 in SImode and DImode */
1202 in SImode, DImode and TImode */
1204 in SImode, DImode and TImode */
1206 /* On K8:
1207 MOVD reg64, xmmreg Double FSTORE 4
1208 MOVD reg32, xmmreg Double FSTORE 4
1209 On AMDFAM10:
1210 MOVD reg64, xmmreg Double FADD 3
1211 1/1 1/1
1212 MOVD reg32, xmmreg Double FADD 3
1213 1/1 1/1 */
1217 /* New AMD processors never drop prefetches; if they cannot be performed
1218 immediately, they are queued. We set number of simultaneous prefetches
1219 to a large constant to reflect this (it probably is not a good idea not
1220 to limit number of prefetches at all, as their execution also takes some
1221 time). */
1231 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
1232 very small blocks it is better to use loop. For large blocks, libcall can
1233 do nontemporary accesses and beat inline considerably. */
1250 };
1274 in QImode, HImode and SImode.
1275 Relative to reg-reg move (2). */
1279 in SFmode, DFmode and XFmode */
1281 in SFmode, DFmode and XFmode */
1284 in SImode and DImode */
1286 in SImode and DImode */
1289 in SImode, DImode and TImode */
1291 in SImode, DImode and TImode */
1293 /* On K8:
1294 MOVD reg64, xmmreg Double FSTORE 4
1295 MOVD reg32, xmmreg Double FSTORE 4
1296 On AMDFAM10:
1297 MOVD reg64, xmmreg Double FADD 3
1298 1/1 1/1
1299 MOVD reg32, xmmreg Double FADD 3
1300 1/1 1/1 */
1304 /* New AMD processors never drop prefetches; if they cannot be performed
1305 immediately, they are queued. We set number of simultaneous prefetches
1306 to a large constant to reflect this (it probably is not a good idea not
1307 to limit number of prefetches at all, as their execution also takes some
1308 time). */
1318 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
1319 very small blocks it is better to use loop. For large blocks, libcall
1320 can do nontemporary accesses and beat inline considerably. */
1337 };
1361 in QImode, HImode and SImode.
1362 Relative to reg-reg move (2). */
1366 in SFmode, DFmode and XFmode */
1368 in SFmode, DFmode and XFmode */
1371 in SImode and DImode */
1373 in SImode and DImode */
1376 in SImode, DImode and TImode */
1378 in SImode, DImode and TImode */
1380 /* On K8:
1381 MOVD reg64, xmmreg Double FSTORE 4
1382 MOVD reg32, xmmreg Double FSTORE 4
1383 On AMDFAM10:
1384 MOVD reg64, xmmreg Double FADD 3
1385 1/1 1/1
1386 MOVD reg32, xmmreg Double FADD 3
1387 1/1 1/1 */
1400 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1401 very small blocks it is better to use loop. For large blocks, libcall can
1402 do nontemporary accesses and beat inline considerably. */
1419 };
1421 static const
1444 in QImode, HImode and SImode.
1445 Relative to reg-reg move (2). */
1449 in SFmode, DFmode and XFmode */
1451 in SFmode, DFmode and XFmode */
1454 in SImode and DImode */
1456 in SImode and DImode */
1459 in SImode, DImode and TImode */
1461 in SImode, DImode and TImode */
1475 DUMMY_STRINGOP_ALGS},
1478 DUMMY_STRINGOP_ALGS},
1490 };
1492 static const
1515 in QImode, HImode and SImode.
1516 Relative to reg-reg move (2). */
1520 in SFmode, DFmode and XFmode */
1522 in SFmode, DFmode and XFmode */
1525 in SImode and DImode */
1527 in SImode and DImode */
1530 in SImode, DImode and TImode */
1532 in SImode, DImode and TImode */
1563 };
1565 static const
1588 in QImode, HImode and SImode.
1589 Relative to reg-reg move (2). */
1593 in SFmode, DFmode and XFmode */
1595 in SFmode, DFmode and XFmode */
1598 in SImode and DImode */
1600 in SImode and DImode */
1603 in SImode, DImode and TImode */
1605 in SImode, DImode and TImode */
1636 };
1638 /* Generic64 should produce code tuned for Nocona and K8. */
1639 static const
1642 /* On all chips taken into consideration lea is 2 cycles and more. With
1643 this cost however our current implementation of synth_mult results in
1644 use of unnecessary temporary registers causing regression on several
1645 SPECfp benchmarks. */
1666 in QImode, HImode and SImode.
1667 Relative to reg-reg move (2). */
1671 in SFmode, DFmode and XFmode */
1673 in SFmode, DFmode and XFmode */
1676 in SImode and DImode */
1678 in SImode and DImode */
1681 in SImode, DImode and TImode */
1683 in SImode, DImode and TImode */
1689 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1690 value is increased to perhaps more appropriate value of 5. */
1713 };
1715 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1716 Athlon and K8. */
1717 static const
1740 in QImode, HImode and SImode.
1741 Relative to reg-reg move (2). */
1745 in SFmode, DFmode and XFmode */
1747 in SFmode, DFmode and XFmode */
1750 in SImode and DImode */
1752 in SImode and DImode */
1755 in SImode, DImode and TImode */
1757 in SImode, DImode and TImode */
1771 DUMMY_STRINGOP_ALGS},
1773 DUMMY_STRINGOP_ALGS},
1785 };
1789 /* Processor feature/optimization bitmasks. */
1790 #define m_386 (1<<PROCESSOR_I386)
1791 #define m_486 (1<<PROCESSOR_I486)
1792 #define m_PENT (1<<PROCESSOR_PENTIUM)
1793 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1794 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1795 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1796 #define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
1797 #define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
1798 #define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
1799 #define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
1800 #define m_COREI7 (m_COREI7_32 | m_COREI7_64)
1801 #define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
1802 #define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
1803 #define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
1804 #define m_ATOM (1<<PROCESSOR_ATOM)
1806 #define m_GEODE (1<<PROCESSOR_GEODE)
1807 #define m_K6 (1<<PROCESSOR_K6)
1808 #define m_K6_GEODE (m_K6 | m_GEODE)
1809 #define m_K8 (1<<PROCESSOR_K8)
1810 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1811 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1812 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1813 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1814 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1815 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1 | m_BTVER1)
1817 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1818 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1820 /* Generic instruction choice should be common subset of supported CPUs
1821 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1822 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1824 /* Feature tests against the various tunings. */
1827 /* Feature tests against the various tunings used to create ix86_tune_features
1828 based on the processor mask. */
1830 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1831 negatively, so enabling for Generic64 seems like good code size
1832 tradeoff. We can't enable it for 32bit generic because it does not
1833 work well with PPro base chips. */
1836 /* X86_TUNE_PUSH_MEMORY */
1840 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1843 /* X86_TUNE_UNROLL_STRLEN */
1847 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1851 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1852 on simulation result. But after P4 was made, no performance benefit
1853 was observed with branch hints. It also increases the code size.
1854 As a result, icc never generates branch hints. */
1857 /* X86_TUNE_DOUBLE_WITH_ADD */
1860 /* X86_TUNE_USE_SAHF */
1864 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1865 partial dependencies. */
1869 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1870 register stalls on Generic32 compilation setting as well. However
1871 in current implementation the partial register stalls are not eliminated
1872 very well - they can be introduced via subregs synthesized by combine
1873 and can happen in caller/callee saving sequences. Because this option
1874 pays back little on PPro based chips and is in conflict with partial reg
1875 dependencies used by Athlon/P4 based chips, it is better to leave it off
1876 for generic32 for now. */
1877 m_PPRO,
1879 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1882 /* X86_TUNE_USE_HIMODE_FIOP */
1885 /* X86_TUNE_USE_SIMODE_FIOP */
1888 /* X86_TUNE_USE_MOV0 */
1889 m_K6,
1891 /* X86_TUNE_USE_CLTD */
1894 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1895 m_PENT4,
1897 /* X86_TUNE_SPLIT_LONG_MOVES */
1898 m_PPRO,
1900 /* X86_TUNE_READ_MODIFY_WRITE */
1903 /* X86_TUNE_READ_MODIFY */
1906 /* X86_TUNE_PROMOTE_QIMODE */
1910 /* X86_TUNE_FAST_PREFIX */
1913 /* X86_TUNE_SINGLE_STRINGOP */
1916 /* X86_TUNE_QIMODE_MATH */
1919 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1920 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1921 might be considered for Generic32 if our scheme for avoiding partial
1922 stalls was more effective. */
1925 /* X86_TUNE_PROMOTE_QI_REGS */
1928 /* X86_TUNE_PROMOTE_HI_REGS */
1929 m_PPRO,
1931 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1932 over esp addition. */
1935 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1936 over esp addition. */
1937 m_PENT,
1939 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1940 over esp subtraction. */
1943 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1944 over esp subtraction. */
1947 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1948 for DFmode copies */
1952 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1955 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1956 conflict here in between PPro/Pentium4 based chips that thread 128bit
1957 SSE registers as single units versus K8 based chips that divide SSE
1958 registers to two 64bit halves. This knob promotes all store destinations
1959 to be 128bit to allow register renaming on 128bit SSE units, but usually
1960 results in one extra microop on 64bit SSE units. Experimental results
1961 shows that disabling this option on P4 brings over 20% SPECfp regression,
1962 while enabling it on K8 brings roughly 2.4% regression that can be partly
1963 masked by careful scheduling of moves. */
1967 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1970 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1973 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1974 m_BDVER1,
1976 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1977 are resolved on SSE register parts instead of whole registers, so we may
1978 maintain just lower part of scalar values in proper format leaving the
1979 upper part undefined. */
1980 m_ATHLON_K8,
1982 /* X86_TUNE_SSE_TYPELESS_STORES */
1983 m_AMD_MULTIPLE,
1985 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1988 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1991 /* X86_TUNE_PROLOGUE_USING_MOVE */
1994 /* X86_TUNE_EPILOGUE_USING_MOVE */
1997 /* X86_TUNE_SHIFT1 */
2000 /* X86_TUNE_USE_FFREEP */
2001 m_AMD_MULTIPLE,
2003 /* X86_TUNE_INTER_UNIT_MOVES */
2006 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
2009 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
2010 than 4 branch instructions in the 16 byte window. */
2014 /* X86_TUNE_SCHEDULE */
2018 /* X86_TUNE_USE_BT */
2021 /* X86_TUNE_USE_INCDEC */
2024 /* X86_TUNE_PAD_RETURNS */
2027 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
2028 m_ATOM,
2030 /* X86_TUNE_EXT_80387_CONSTANTS */
2034 /* X86_TUNE_SHORTEN_X87_SSE */
2037 /* X86_TUNE_AVOID_VECTOR_DECODE */
2040 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
2041 and SImode multiply, but 386 and 486 do HImode multiply faster. */
2044 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
2045 vector path on AMD machines. */
2048 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
2049 machines. */
2052 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
2053 than a MOV. */
2054 m_PENT,
2056 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
2057 but one byte longer. */
2058 m_PENT,
2060 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
2061 operand that cannot be represented using a modRM byte. The XOR
2062 replacement is long decoded, so this split helps here as well. */
2063 m_K6,
2065 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
2066 from FP to FP. */
2069 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
2070 from integer to FP. */
2071 m_AMDFAM10,
2073 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
2074 with a subsequent conditional jump instruction into a single
2075 compare-and-branch uop. */
2076 m_BDVER1,
2078 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2079 will impact LEA instruction selection. */
2080 m_ATOM,
2082 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2083 instructions. */
2085 };
2087 /* Feature tests against the various architecture variations. */
2090 /* Feature tests against the various architecture variations, used to create
2091 ix86_arch_features based on the processor mask. */
2093 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
2096 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2099 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2102 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2105 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2107 };
2109 static const unsigned int x86_accumulate_outgoing_args
2113 static const unsigned int x86_arch_always_fancy_math_387
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 };
2159 /* The "default" register map used in 32bit mode. */
2162 {
2170 };
2172 /* The "default" register map used in 64bit mode. */
2175 {
2183 };
2185 /* Define the register numbers to be used in Dwarf debugging information.
2186 The SVR4 reference port C compiler uses the following register numbers
2187 in its Dwarf output code:
2188 0 for %eax (gcc regno = 0)
2189 1 for %ecx (gcc regno = 2)
2190 2 for %edx (gcc regno = 1)
2191 3 for %ebx (gcc regno = 3)
2192 4 for %esp (gcc regno = 7)
2193 5 for %ebp (gcc regno = 6)
2194 6 for %esi (gcc regno = 4)
2195 7 for %edi (gcc regno = 5)
2196 The following three DWARF register numbers are never generated by
2197 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2198 believes these numbers have these meanings.
2199 8 for %eip (no gcc equivalent)
2200 9 for %eflags (gcc regno = 17)
2201 10 for %trapno (no gcc equivalent)
2202 It is not at all clear how we should number the FP stack registers
2203 for the x86 architecture. If the version of SDB on x86/svr4 were
2204 a bit less brain dead with respect to floating-point then we would
2205 have a precedent to follow with respect to DWARF register numbers
2206 for x86 FP registers, but the SDB on x86/svr4 is so completely
2207 broken with respect to FP registers that it is hardly worth thinking
2208 of it as something to strive for compatibility with.
2209 The version of x86/svr4 SDB I have at the moment does (partially)
2210 seem to believe that DWARF register number 11 is associated with
2211 the x86 register %st(0), but that's about all. Higher DWARF
2212 register numbers don't seem to be associated with anything in
2213 particular, and even for DWARF regno 11, SDB only seems to under-
2214 stand that it should say that a variable lives in %st(0) (when
2215 asked via an `=' command) if we said it was in DWARF regno 11,
2216 but SDB still prints garbage when asked for the value of the
2217 variable in question (via a `/' command).
2218 (Also note that the labels SDB prints for various FP stack regs
2219 when doing an `x' command are all wrong.)
2220 Note that these problems generally don't affect the native SVR4
2221 C compiler because it doesn't allow the use of -O with -g and
2222 because when it is *not* optimizing, it allocates a memory
2223 location for each floating-point variable, and the memory
2224 location is what gets described in the DWARF AT_location
2225 attribute for the variable in question.
2226 Regardless of the severe mental illness of the x86/svr4 SDB, we
2227 do something sensible here and we use the following DWARF
2228 register numbers. Note that these are all stack-top-relative
2229 numbers.
2230 11 for %st(0) (gcc regno = 8)
2231 12 for %st(1) (gcc regno = 9)
2232 13 for %st(2) (gcc regno = 10)
2233 14 for %st(3) (gcc regno = 11)
2234 15 for %st(4) (gcc regno = 12)
2235 16 for %st(5) (gcc regno = 13)
2236 17 for %st(6) (gcc regno = 14)
2237 18 for %st(7) (gcc regno = 15)
2238 */
2240 {
2248 };
2250 /* Define parameter passing and return registers. */
2253 {
2255 };
2258 {
2260 };
2263 {
2265 };
2267 /* Define the structure for the machine field in struct function. */
2272 rtx rtl;
2274 };
2276 /* Structure describing stack frame layout.
2277 Stack grows downward:
2279 [arguments]
2280 <- ARG_POINTER
2281 saved pc
2283 saved static chain if ix86_static_chain_on_stack
2285 saved frame pointer if frame_pointer_needed
2286 <- HARD_FRAME_POINTER
2287 [saved regs]
2288 <- regs_save_offset
2289 [padding0]
2291 [saved SSE regs]
2292 <- sse_regs_save_offset
2293 [padding1] |
2294 | <- FRAME_POINTER
2295 [va_arg registers] |
2296 |
2297 [frame] |
2298 |
2299 [padding2] | = to_allocate
2300 <- STACK_POINTER
2301 */
2302 struct ix86_frame
2303 {
2309 HOST_WIDE_INT frame;
2311 /* The offsets relative to ARG_POINTER. */
2312 HOST_WIDE_INT frame_pointer_offset;
2313 HOST_WIDE_INT hard_frame_pointer_offset;
2314 HOST_WIDE_INT stack_pointer_offset;
2315 HOST_WIDE_INT hfp_save_offset;
2316 HOST_WIDE_INT reg_save_offset;
2317 HOST_WIDE_INT sse_reg_save_offset;
2319 /* When save_regs_using_mov is set, emit prologue using
2320 move instead of push instructions. */
2322 };
2324 /* Code model option. */
2326 /* Asm dialect. */
2328 /* TLS dialects. */
2331 /* Which unit we are generating floating point math for. */
2334 /* Which cpu are we scheduling for. */
2337 /* Which cpu are we optimizing for. */
2340 /* Which instruction set architecture to use. */
2343 /* true if sse prefetch instruction is not NOOP. */
2346 /* ix86_regparm_string as a number */
2349 /* -mstackrealign option */
2364 /* Preferred alignment for stack boundary in bits. */
2367 /* Alignment for incoming stack boundary in bits specified at
2368 command line. */
2371 /* Default alignment for incoming stack boundary in bits. */
2374 /* Alignment for incoming stack boundary in bits. */
2377 /* The abi used by target. */
2380 /* Values 1-5: see jump.c */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Variables which are this size or smaller are put in the data/bss
2388 or ldata/lbss sections. */
2392 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2396 /* Fence to use after loop using movnt. */
2397 tree x86_mfence;
2399 /* Register class used for passing given 64bit part of the argument.
2400 These represent classes as documented by the PS ABI, with the exception
2401 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2402 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2404 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2405 whenever possible (upper half does contain padding). */
2406 enum x86_64_reg_class
2407 {
2408 X86_64_NO_CLASS,
2409 X86_64_INTEGER_CLASS,
2410 X86_64_INTEGERSI_CLASS,
2411 X86_64_SSE_CLASS,
2412 X86_64_SSESF_CLASS,
2413 X86_64_SSEDF_CLASS,
2414 X86_64_SSEUP_CLASS,
2415 X86_64_X87_CLASS,
2416 X86_64_X87UP_CLASS,
2417 X86_64_COMPLEX_X87_CLASS,
2418 X86_64_MEMORY_CLASS
2419 };
2421 #define MAX_CLASSES 4
2423 /* Table of constants used by fldpi, fldln2, etc.... */
2427 \f
2432 const_tree);
2445 enum ix86_function_specific_strings
2446 {
2447 IX86_FUNCTION_SPECIFIC_ARCH,
2448 IX86_FUNCTION_SPECIFIC_TUNE,
2449 IX86_FUNCTION_SPECIFIC_FPMATH,
2450 IX86_FUNCTION_SPECIFIC_MAX
2451 };
2468 \f
2469 #ifndef SUBTARGET32_DEFAULT_CPU
2471 #endif
2473 /* The svr4 ABI for the i386 says that records and unions are returned
2474 in memory. */
2475 #ifndef DEFAULT_PCC_STRUCT_RETURN
2476 #define DEFAULT_PCC_STRUCT_RETURN 1
2477 #endif
2479 /* Whether -mtune= or -march= were specified */
2483 /* A mask of ix86_isa_flags that includes bit X if X
2484 was set or cleared on the command line. */
2487 /* Define a set of ISAs which are available when a given ISA is
2488 enabled. MMX and SSE ISAs are handled separately. */
2490 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2491 #define OPTION_MASK_ISA_3DNOW_SET \
2492 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2494 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2495 #define OPTION_MASK_ISA_SSE2_SET \
2496 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2497 #define OPTION_MASK_ISA_SSE3_SET \
2498 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2499 #define OPTION_MASK_ISA_SSSE3_SET \
2500 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2501 #define OPTION_MASK_ISA_SSE4_1_SET \
2502 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2503 #define OPTION_MASK_ISA_SSE4_2_SET \
2504 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2505 #define OPTION_MASK_ISA_AVX_SET \
2506 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2507 #define OPTION_MASK_ISA_FMA_SET \
2508 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2510 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2511 as -msse4.2. */
2512 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2514 #define OPTION_MASK_ISA_SSE4A_SET \
2515 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2516 #define OPTION_MASK_ISA_FMA4_SET \
2517 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2518 | OPTION_MASK_ISA_AVX_SET)
2519 #define OPTION_MASK_ISA_XOP_SET \
2520 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2521 #define OPTION_MASK_ISA_LWP_SET \
2522 OPTION_MASK_ISA_LWP
2524 /* AES and PCLMUL need SSE2 because they use xmm registers */
2525 #define OPTION_MASK_ISA_AES_SET \
2526 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2527 #define OPTION_MASK_ISA_PCLMUL_SET \
2528 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2530 #define OPTION_MASK_ISA_ABM_SET \
2531 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2533 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
2534 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
2535 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2536 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2537 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2538 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2539 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2541 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
2542 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
2543 #define OPTION_MASK_ISA_F16C_SET \
2544 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
2546 /* Define a set of ISAs which aren't available when a given ISA is
2547 disabled. MMX and SSE ISAs are handled separately. */
2549 #define OPTION_MASK_ISA_MMX_UNSET \
2550 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2551 #define OPTION_MASK_ISA_3DNOW_UNSET \
2552 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2553 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2555 #define OPTION_MASK_ISA_SSE_UNSET \
2556 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2557 #define OPTION_MASK_ISA_SSE2_UNSET \
2558 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2559 #define OPTION_MASK_ISA_SSE3_UNSET \
2560 (OPTION_MASK_ISA_SSE3 \
2561 | OPTION_MASK_ISA_SSSE3_UNSET \
2562 | OPTION_MASK_ISA_SSE4A_UNSET )
2563 #define OPTION_MASK_ISA_SSSE3_UNSET \
2564 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2565 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2566 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2567 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2568 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2569 #define OPTION_MASK_ISA_AVX_UNSET \
2570 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2571 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET)
2572 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2574 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2575 as -mno-sse4.1. */
2576 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2578 #define OPTION_MASK_ISA_SSE4A_UNSET \
2579 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2581 #define OPTION_MASK_ISA_FMA4_UNSET \
2582 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2583 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2584 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2586 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2587 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2588 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2589 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
2590 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
2591 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2592 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2593 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2594 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2595 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2597 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
2598 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
2599 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
2601 /* Vectorization library interface and handlers. */
2607 /* Processor target table, indexed by processor number */
2608 struct ptt
2609 {
2616 };
2619 {
2630 /* Core 2 32-bit. */
2632 /* Core 2 64-bit. */
2634 /* Core i7 32-bit. */
2636 /* Core i7 64-bit. */
2644 };
2647 {
2672 "btver1"
2673 };
2674 \f
2675 /* Return true if a red-zone is in use. */
2679 {
2681 }
2683 /* Implement TARGET_HANDLE_OPTION. */
2685 static bool
2687 {
2689 {
2692 {
2695 }
2696 else
2697 {
2700 }
2705 {
2708 }
2709 else
2710 {
2713 }
2721 {
2724 }
2725 else
2726 {
2729 }
2734 {
2737 }
2738 else
2739 {
2742 }
2747 {
2750 }
2751 else
2752 {
2755 }
2760 {
2763 }
2764 else
2765 {
2768 }
2773 {
2776 }
2777 else
2778 {
2781 }
2786 {
2789 }
2790 else
2791 {
2794 }
2799 {
2802 }
2803 else
2804 {
2807 }
2812 {
2815 }
2816 else
2817 {
2820 }
2835 {
2838 }
2839 else
2840 {
2843 }
2848 {
2851 }
2852 else
2853 {
2856 }
2861 {
2864 }
2865 else
2866 {
2869 }
2874 {
2877 }
2878 else
2879 {
2882 }
2887 {
2890 }
2891 else
2892 {
2895 }
2900 {
2903 }
2904 else
2905 {
2908 }
2913 {
2916 }
2917 else
2918 {
2921 }
2926 {
2929 }
2930 else
2931 {
2934 }
2939 {
2942 }
2943 else
2944 {
2947 }
2952 {
2955 }
2956 else
2957 {
2960 }
2965 {
2968 }
2969 else
2970 {
2973 }
2978 {
2981 }
2982 else
2983 {
2986 }
2991 {
2994 }
2995 else
2996 {
2999 }
3004 {
3007 }
3008 else
3009 {
3012 }
3017 {
3020 }
3021 else
3022 {
3025 }
3030 {
3033 }
3034 else
3035 {
3038 }
3043 {
3046 }
3047 else
3048 {
3051 }
3056 }
3057 }
3058 \f
3059 /* Return a string that documents the current -m options. The caller is
3060 responsible for freeing the string. */
3065 {
3066 struct ix86_target_opts
3067 {
3070 };
3072 /* This table is ordered so that options like -msse4.2 that imply
3073 preceding options while match those first. */
3075 {
3102 };
3104 /* Flag options. */
3106 {
3130 };
3146 /* Add -march= option. */
3148 {
3151 }
3153 /* Add -mtune= option. */
3155 {
3158 }
3160 /* Pick out the options in isa options. */
3162 {
3164 {
3167 }
3168 }
3171 {
3174 }
3176 /* Add flag options. */
3178 {
3180 {
3183 }
3184 }
3187 {
3190 }
3192 /* Add -fpmath= option. */
3194 {
3197 }
3199 /* Any options? */
3205 /* Size the string. */
3209 {
3214 }
3216 /* Build the string. */
3221 {
3228 {
3230 line_len++;
3233 {
3237 }
3238 }
3242 {
3246 }
3247 }
3253 }
3255 /* Return TRUE if software prefetching is beneficial for the
3256 given CPU. */
3258 static bool
3260 {
3262 {
3273 }
3274 }
3276 /* Return true, if profiling code should be emitted before
3277 prologue. Otherwise it returns false.
3278 Note: For x86 with "hotfix" it is sorried. */
3279 static bool
3281 {
3283 }
3285 /* Function that is callable from the debugger to print the current
3286 options. */
3287 void
3289 {
3295 {
3298 }
3299 else
3303 }
3304 \f
3305 /* Override various settings based on options. If MAIN_ARGS_P, the
3306 options are from the command line, otherwise they are from
3307 attributes. */
3309 static void
3311 {
3319 /* Comes from final.c -- no real reason to change it. */
3320 #define MAX_CODE_ALIGN 16
3322 enum pta_flags
3323 {
3353 /* if this reaches 32, need to widen struct pta flags below */
3354 };
3356 static struct pta
3357 {
3362 }
3364 {
3461 };
3465 /* Set up prefix/suffix so the error messages refer to either the command
3466 line argument, or the attribute(target). */
3468 {
3472 }
3473 else
3474 {
3478 }
3480 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3481 SUBTARGET_OVERRIDE_OPTIONS;
3482 #endif
3484 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3485 SUBSUBTARGET_OVERRIDE_OPTIONS;
3486 #endif
3488 /* -fPIC is the default for x86_64. */
3492 /* Need to check -mtune=generic first. */
3494 {
3497 /* As special support for cross compilers we read -mtune=native
3498 as -mtune=generic. With native compilers we won't see the
3499 -mtune=native, as it was changed by the driver. */
3501 {
3504 else
3506 }
3507 /* If this call is for setting the option attribute, allow the
3508 generic32/generic64 that was previously set. */
3512 ;
3520 }
3521 else
3522 {
3526 {
3529 }
3531 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3532 need to use a sensible tune option. */
3536 {
3539 else
3541 }
3542 }
3545 {
3554 /* rep; movq isn't available in 32-bit code. */
3562 else
3565 }
3569 else
3572 /* Validate -mabi= value. */
3574 {
3579 else
3582 }
3583 else
3587 {
3600 else
3603 }
3604 else
3605 {
3606 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3607 use of rip-relative addressing. This eliminates fixups that
3608 would otherwise be needed if this object is to be placed in a
3609 DLL, and is essentially just as efficient as direct addressing. */
3614 else
3616 }
3618 {
3624 else
3627 }
3637 {
3640 /* Default cpu tuning to the architecture. */
3732 }
3747 {
3751 {
3753 {
3755 {
3763 }
3764 else
3767 }
3768 }
3769 else
3770 {
3771 /* Adjust tuning when compiling for 32-bit ABI. */
3773 {
3789 }
3790 }
3791 /* Intel CPUs have always interpreted SSE prefetch instructions as
3792 NOPs; so, we can enable SSE prefetch instructions even when
3793 -mtune (rather than -march) points us to a processor that has them.
3794 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3795 higher processors. */
3800 }
3810 #ifndef USE_IX86_FRAME_POINTER
3811 #define USE_IX86_FRAME_POINTER 0
3812 #endif
3814 #ifndef USE_X86_64_FRAME_POINTER
3815 #define USE_X86_64_FRAME_POINTER 0
3816 #endif
3818 /* Set the default values for switches whose default depends on TARGET_64BIT
3819 in case they weren't overwritten by command line options. */
3821 {
3830 }
3831 else
3832 {
3839 }
3843 else
3846 /* Arrange to set up i386_stack_locals for all functions. */
3849 /* Validate -mregparm= value. */
3851 {
3858 else
3860 }
3864 /* If the user has provided any of the -malign-* options,
3865 warn and use that value only if -falign-* is not set.
3866 Remove this code in GCC 3.2 or later. */
3868 {
3872 {
3877 else
3879 }
3880 }
3883 {
3887 {
3892 else
3894 }
3895 }
3898 {
3902 {
3907 else
3909 }
3910 }
3912 /* Default align_* from the processor table. */
3914 {
3917 }
3919 {
3922 }
3924 {
3926 }
3928 /* Validate -mbranch-cost= value, or provide default. */
3931 {
3935 else
3937 }
3939 {
3943 else
3945 }
3948 {
3953 else
3956 }
3959 {
3963 }
3966 {
3969 /* Enable by default the SSE and MMX builtins. Do allow the user to
3970 explicitly disable any of these. In particular, disabling SSE and
3971 MMX for kernel code is extremely useful. */
3973 ix86_isa_flags
3979 }
3980 else
3981 {
3985 ix86_isa_flags
3988 /* i386 ABI does not specify red zone. It still makes sense to use it
3989 when programmer takes care to stack from being destroyed. */
3992 }
3994 /* Keep nonleaf frame pointers. */
4000 /* If we're doing fast math, we don't care about comparison order
4001 wrt NaNs. This lets us use a shorter comparison sequence. */
4005 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4006 since the insns won't need emulation. */
4010 /* Likewise, if the target doesn't have a 387, or we've specified
4011 software floating point, don't use 387 inline intrinsics. */
4015 /* Turn on MMX builtins for -msse. */
4017 {
4020 }
4022 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
4026 /* Validate -mpreferred-stack-boundary= value or default it to
4027 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4030 {
4036 {
4040 else
4043 }
4044 else
4046 }
4048 /* Set the default value for -mstackrealign. */
4054 /* Validate -mincoming-stack-boundary= value or default it to
4055 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4058 {
4063 else
4064 {
4066 ix86_incoming_stack_boundary
4068 }
4069 }
4071 /* Accept -msseregparm only if at least SSE support is enabled. */
4078 {
4082 {
4084 {
4087 }
4088 else
4090 }
4096 {
4098 {
4101 }
4103 {
4106 }
4107 else
4109 }
4110 else
4113 }
4115 /* If the i387 is disabled, then do not return values in it. */
4119 /* Use external vectorized library in vectorizing intrinsics. */
4121 {
4126 else
4130 }
4138 /* ??? Unwind info is not correct around the CFG unless either a frame
4139 pointer is present or M_A_O_A is set. Fixing this requires rewriting
4140 unwind info generation to be aware of the CFG and propagating states
4141 around edges. */
4144 && flag_omit_frame_pointer
4146 {
4152 }
4154 /* If stack probes are required, the space used for large function
4155 arguments on the stack must also be probed, so enable
4156 -maccumulate-outgoing-args so this happens in the prologue. */
4159 {
4164 }
4166 /* For sane SSE instruction set generation we need fcomi instruction.
4167 It is safe to enable all CMOVE instructions. */
4171 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4172 {
4178 }
4180 /* When scheduling description is not available, disable scheduler pass
4181 so it won't slow down the compilation and make x87 code slower. */
4199 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4201 && HAVE_prefetch
4206 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4207 can be optimized to ap = __builtin_next_arg (0). */
4212 {
4223 }
4224 else
4225 {
4236 }
4238 #ifdef USE_IX86_CLD
4239 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4242 #endif
4245 {
4250 }
4252 {
4256 }
4258 {
4259 #if defined(PROFILE_BEFORE_PROLOGUE)
4261 #else
4263 #endif
4264 }
4266 /* Save the initial options in case the user does function specific options */
4268 target_option_default_node = target_option_current_node
4272 {
4273 /* When not optimize for size, enable vzeroupper optimization for
4274 TARGET_AVX with -fexpensive-optimizations. */
4276 && flag_expensive_optimizations
4279 }
4280 else
4281 {
4282 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
4284 }
4285 }
4287 /* Return TRUE if VAL is passed in register with 256bit AVX modes. */
4289 static bool
4291 {
4299 {
4301 rtx r;
4304 {
4312 }
4313 }
4316 }
4318 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4320 static void
4322 {
4324 }
4326 /* Update register usage after having seen the compiler flags. */
4328 static void
4330 {
4335 {
4340 }
4342 /* The PIC register, if it exists, is fixed. */
4347 /* The MS_ABI changes the set of call-used registers. */
4349 {
4356 }
4358 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
4359 other call-clobbered regs for 64-bit. */
4361 {
4368 }
4370 /* If MMX is disabled, squash the registers. */
4376 /* If SSE is disabled, squash the registers. */
4382 /* If the FPU is disabled, squash the registers. */
4388 /* If 32-bit, squash the 64-bit registers. */
4390 {
4395 }
4396 }
4398 \f
4399 /* Save the current options */
4401 static void
4403 {
4414 /* The fields are char but the variables are not; make sure the
4415 values fit in the fields. */
4421 }
4423 /* Restore the current options */
4425 static void
4427 {
4443 /* Recreate the arch feature tests if the arch changed */
4445 {
4450 }
4452 /* Recreate the tune optimization tests */
4454 {
4459 }
4460 }
4462 /* Print the current options */
4464 static void
4467 {
4492 {
4495 }
4496 }
4498 \f
4499 /* Inner function to process the attribute((target(...))), take an argument and
4500 set the current options from the argument. If we have a list, recursively go
4501 over the list. */
4503 static bool
4505 {
4509 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4510 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4511 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4512 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4514 enum ix86_opt_type
4515 {
4516 ix86_opt_unknown,
4517 ix86_opt_yes,
4518 ix86_opt_no,
4519 ix86_opt_str,
4520 ix86_opt_isa
4521 };
4523 static const struct
4524 {
4531 /* isa options */
4556 /* string options */
4561 /* flag options */
4563 OPT_mcld,
4564 MASK_CLD),
4567 OPT_mfancy_math_387,
4568 MASK_NO_FANCY_MATH_387),
4571 OPT_mieee_fp,
4572 MASK_IEEE_FP),
4575 OPT_minline_all_stringops,
4576 MASK_INLINE_ALL_STRINGOPS),
4579 OPT_minline_stringops_dynamically,
4580 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4583 OPT_mno_align_stringops,
4584 MASK_NO_ALIGN_STRINGOPS),
4587 OPT_mrecip,
4588 MASK_RECIP),
4590 };
4592 /* If this is a list, recurse to get the options. */
4594 {
4603 }
4608 /* Handle multiple arguments separated by commas. */
4612 {
4626 {
4630 }
4631 else
4632 {
4635 }
4637 /* Recognize no-xxx. */
4639 {
4643 }
4644 else
4647 /* Find the option. */
4651 {
4657 {
4662 }
4663 }
4665 /* Process the option. */
4667 {
4670 }
4676 {
4682 else
4684 }
4687 {
4689 {
4692 }
4693 else
4695 }
4697 else
4699 }
4702 }
4704 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4706 tree
4708 {
4720 /* Process each of the options on the chain. */
4724 /* If the changed options are different from the default, rerun
4725 ix86_option_override_internal, and then save the options away.
4726 The string options are are attribute options, and will be undone
4727 when we copy the save structure. */
4733 {
4734 /* If we are using the default tune= or arch=, undo the string assigned,
4735 and use the default. */
4746 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4752 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4755 /* Add any builtin functions with the new isa if any. */
4758 /* Save the current options unless we are validating options for
4759 #pragma. */
4766 /* Free up memory allocated to hold the strings */
4770 }
4773 }
4775 /* Hook to validate attribute((target("string"))). */
4777 static bool
4780 tree args,
4782 {
4789 /* If the function changed the optimization levels as well as setting target
4790 options, start with the optimizations specified. */
4795 /* The target attributes may also change some optimization flags, so update
4796 the optimization options if necessary. */
4805 {
4810 }
4819 }
4821 \f
4822 /* Hook to determine if one function can safely inline another. */
4824 static bool
4826 {
4831 /* If callee has no option attributes, then it is ok to inline. */
4835 /* If caller has no option attributes, but callee does then it is not ok to
4836 inline. */
4840 else
4841 {
4845 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4846 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4847 function. */
4852 /* See if we have the same non-isa options. */
4856 /* See if arch, tune, etc. are the same. */
4869 else
4871 }
4874 }
4876 \f
4877 /* Remember the last target of ix86_set_current_function. */
4880 /* Establish appropriate back-end context for processing the function
4881 FNDECL. The argument might be NULL to indicate processing at top
4882 level, outside of any function scope. */
4883 static void
4885 {
4886 /* Only change the context if the function changes. This hook is called
4887 several times in the course of compiling a function, and we don't want to
4888 slow things down too much or call target_reinit when it isn't safe. */
4890 {
4891 tree old_tree = (ix86_previous_fndecl
4895 tree new_tree = (fndecl
4901 ;
4904 {
4908 }
4911 {
4917 }
4918 }
4919 }
4921 \f
4922 /* Return true if this goes in large data/bss. */
4924 static bool
4926 {
4930 /* Functions are never large data. */
4935 {
4941 }
4942 else
4943 {
4946 /* If this is an incomplete type with size 0, then we can't put it
4947 in data because it might be too big when completed. */
4950 }
4953 }
4955 /* Switch to the appropriate section for output of DECL.
4956 DECL is either a `VAR_DECL' node or a constant of some sort.
4957 RELOC indicates whether forming the initial value of DECL requires
4958 link-time relocations. */
4961 ATTRIBUTE_UNUSED;
4966 {
4969 {
4973 {
5007 /* We don't split these for medium model. Place them into
5008 default sections and hope for best. */
5010 }
5012 {
5013 /* We might get called with string constants, but get_named_section
5014 doesn't like them as they are not DECLs. Also, we need to set
5015 flags in that case. */
5019 }
5020 }
5022 }
5024 /* Build up a unique section name, expressed as a
5025 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5026 RELOC indicates whether the initial value of EXP requires
5027 link-time relocations. */
5029 static void ATTRIBUTE_UNUSED
5031 {
5034 {
5036 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5040 {
5064 /* We don't split these for medium model. Place them into
5065 default sections and hope for best. */
5067 }
5069 {
5076 /* If we're using one_only, then there needs to be a .gnu.linkonce
5077 prefix to the section name. */
5084 }
5085 }
5087 }
5089 #ifdef COMMON_ASM_OP
5090 /* This says how to output assembler code to declare an
5091 uninitialized external linkage data object.
5093 For medium model x86-64 we need to use .largecomm opcode for
5094 large objects. */
5095 void
5099 {
5103 else
5108 }
5109 #endif
5111 /* Utility function for targets to use in implementing
5112 ASM_OUTPUT_ALIGNED_BSS. */
5114 void
5118 {
5122 else
5125 #ifdef ASM_DECLARE_OBJECT_NAME
5128 #else
5129 /* Standard thing is just output label for the object. */
5133 }
5134 \f
5136 {
5137 /* Turn off -fschedule-insns by default. It tends to make the
5138 problem with not enough registers even worse. */
5139 #ifdef INSN_SCHEDULING
5141 #endif
5143 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
5144 SUBTARGET_OPTIMIZATION_OPTIONS,
5145 #endif
5147 };
5149 /* Implement TARGET_OPTION_INIT_STRUCT. */
5151 static void
5153 {
5155 /* The Darwin libraries never set errno, so we might as well
5156 avoid calling them when that's the only reason we would. */
5162 }
5164 /* Decide whether we must probe the stack before any space allocation
5165 on this target. It's essentially TARGET_STACK_PROBE except when
5166 -fstack-check causes the stack to be already probed differently. */
5168 bool
5170 {
5171 /* Do not probe the stack twice if static stack checking is enabled. */
5176 }
5177 \f
5178 /* Decide whether we can make a sibling call to a function. DECL is the
5179 declaration of the function being targeted by the call and EXP is the
5180 CALL_EXPR representing the call. */
5182 static bool
5184 {
5188 /* If we are generating position-independent code, we cannot sibcall
5189 optimize any indirect call, or a direct call to a global function,
5190 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5192 && !TARGET_64BIT
5193 && flag_pic
5197 /* If we need to align the outgoing stack, then sibcalling would
5198 unalign the stack, which may break the called function. */
5204 {
5207 }
5208 else
5209 {
5210 /* We're looking at the CALL_EXPR, we need the type of the function. */
5215 }
5217 /* Check that the return value locations are the same. Like
5218 if we are returning floats on the 80387 register stack, we cannot
5219 make a sibcall from a function that doesn't return a float to a
5220 function that does or, conversely, from a function that does return
5221 a float to a function that doesn't; the necessary stack adjustment
5222 would not be executed. This is also the place we notice
5223 differences in the return value ABI. Note that it is ok for one
5224 of the functions to have void return type as long as the return
5225 value of the other is passed in a register. */
5230 {
5233 }
5235 {
5236 /* Disable sibcall if we need to generate vzeroupper after
5237 callee returns. */
5242 }
5247 {
5248 /* The SYSV ABI has more call-clobbered registers;
5249 disallow sibcalls from MS to SYSV. */
5253 }
5254 else
5255 {
5256 /* If this call is indirect, we'll need to be able to use a
5257 call-clobbered register for the address of the target function.
5258 Make sure that all such registers are not used for passing
5259 parameters. Note that DLLIMPORT functions are indirect. */
5262 {
5264 {
5265 /* ??? Need to count the actual number of registers to be used,
5266 not the possible number of registers. Fix later. */
5268 }
5269 }
5270 }
5272 /* Otherwise okay. That also includes certain types of indirect calls. */
5274 }
5276 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5277 and "sseregparm" calling convention attributes;
5278 arguments as in struct attribute_spec.handler. */
5280 static tree
5282 tree args,
5285 {
5290 {
5292 name);
5295 }
5297 /* Can combine regparm with all attributes but fastcall. */
5299 {
5300 tree cst;
5303 {
5305 }
5308 {
5310 }
5314 {
5317 name);
5319 }
5321 {
5325 }
5328 }
5331 {
5332 /* Do not warn when emulating the MS ABI. */
5337 name);
5340 }
5342 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5344 {
5346 {
5348 }
5350 {
5352 }
5354 {
5356 }
5358 {
5360 }
5361 }
5363 /* Can combine stdcall with fastcall (redundant), regparm and
5364 sseregparm. */
5366 {
5368 {
5370 }
5372 {
5374 }
5376 {
5378 }
5379 }
5381 /* Can combine cdecl with regparm and sseregparm. */
5383 {
5385 {
5387 }
5389 {
5391 }
5393 {
5395 }
5396 }
5398 {
5401 name);
5403 {
5405 }
5407 {
5409 }
5411 {
5413 }
5414 }
5416 /* Can combine sseregparm with all attributes. */
5419 }
5421 /* Return 0 if the attributes for two types are incompatible, 1 if they
5422 are compatible, and 2 if they are nearly compatible (which causes a
5423 warning to be generated). */
5425 static int
5427 {
5428 /* Check for mismatch of non-default calling convention. */
5435 /* Check for mismatched fastcall/regparm types. */
5442 /* Check for mismatched sseregparm types. */
5447 /* Check for mismatched thiscall types. */
5452 /* Check for mismatched return types (cdecl vs stdcall). */
5458 }
5459 \f
5460 /* Return the regparm value for a function with the indicated TYPE and DECL.
5461 DECL may be NULL when calling function indirectly
5462 or considering a libcall. */
5464 static int
5466 {
5467 tree attr;
5477 {
5480 }
5488 /* Use register calling convention for local functions when possible. */
5491 && optimize
5493 {
5494 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5497 {
5500 /* Make sure no regparm register is taken by a
5501 fixed register variable. */
5506 /* We don't want to use regparm(3) for nested functions as
5507 these use a static chain pointer in the third argument. */
5511 /* In 32-bit mode save a register for the split stack. */
5515 /* Each fixed register usage increases register pressure,
5516 so less registers should be used for argument passing.
5517 This functionality can be overriden by an explicit
5518 regparm value. */
5521 globals++;
5523 local_regparm
5528 }
5529 }
5532 }
5534 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5535 DFmode (2) arguments in SSE registers for a function with the
5536 indicated TYPE and DECL. DECL may be NULL when calling function
5537 indirectly or considering a libcall. Otherwise return 0. */
5539 static int
5541 {
5544 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5545 by the sseregparm attribute. */
5548 {
5550 {
5552 {
5556 else
5559 }
5561 }
5564 }
5566 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5567 (and DFmode for SSE2) arguments in SSE registers. */
5570 {
5571 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5575 }
5578 }
5580 /* Return true if EAX is live at the start of the function. Used by
5581 ix86_expand_prologue to determine if we need special help before
5582 calling allocate_stack_worker. */
5584 static bool
5586 {
5587 /* Cheat. Don't bother working forward from ix86_function_regparm
5588 to the function type to whether an actual argument is located in
5589 eax. Instead just look at cfg info, which is still close enough
5590 to correct at this point. This gives false positives for broken
5591 functions that might use uninitialized data that happens to be
5592 allocated in eax, but who cares? */
5594 }
5596 static bool
5598 {
5599 tree attr;
5607 }
5609 /* Value is the number of bytes of arguments automatically
5610 popped when returning from a subroutine call.
5611 FUNDECL is the declaration node of the function (as a tree),
5612 FUNTYPE is the data type of the function (as a tree),
5613 or for a library call it is an identifier node for the subroutine name.
5614 SIZE is the number of bytes of arguments passed on the stack.
5616 On the 80386, the RTD insn may be used to pop them if the number
5617 of args is fixed, but if the number is variable then the caller
5618 must pop them all. RTD can't be used for library calls now
5619 because the library is compiled with the Unix compiler.
5620 Use of RTD is a selectable option, since it is incompatible with
5621 standard Unix calling sequences. If the option is not selected,
5622 the caller must always pop the args.
5624 The attribute stdcall is equivalent to RTD on a per module basis. */
5626 static int
5628 {
5631 /* None of the 64-bit ABIs pop arguments. */
5637 /* Cdecl functions override -mrtd, and never pop the stack. */
5639 {
5640 /* Stdcall and fastcall functions will pop the stack if not
5641 variable args. */
5649 }
5651 /* Lose any fake structure return argument if it is passed on the stack. */
5654 {
5658 }
5661 }
5662 \f
5663 /* Argument support functions. */
5665 /* Return true when register may be used to pass function parameters. */
5666 bool
5668 {
5673 {
5677 else
5683 }
5686 {
5689 }
5690 else
5691 {
5695 }
5697 /* TODO: The function should depend on current function ABI but
5698 builtins.c would need updating then. Therefore we use the
5699 default ABI. */
5701 /* RAX is used as hidden argument to va_arg functions. */
5707 else
5714 }
5716 /* Return if we do not know how to pass TYPE solely in registers. */
5718 static bool
5720 {
5724 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5725 The layout_type routine is crafty and tries to trick us into passing
5726 currently unsupported vector types on the stack by using TImode. */
5729 }
5731 /* It returns the size, in bytes, of the area reserved for arguments passed
5732 in registers for the function represented by fndecl dependent to the used
5733 abi format. */
5734 int
5736 {
5740 else
5745 }
5747 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5748 call abi used. */
5749 enum calling_abi
5751 {
5753 {
5756 {
5759 }
5763 }
5765 }
5767 static bool
5769 {
5771 {
5775 else
5777 }
5779 }
5781 static enum calling_abi
5783 {
5787 }
5789 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5790 call abi used. */
5791 enum calling_abi
5793 {
5797 }
5799 /* Write the extra assembler code needed to declare a function properly. */
5801 void
5803 tree decl)
5804 {
5808 {
5814 }
5816 #ifdef SUBTARGET_ASM_UNWIND_INIT
5818 #endif
5822 /* Output magic byte marker, if hot-patch attribute is set. */
5824 {
5826 {
5827 /* leaq [%rsp + 0], %rsp */
5830 }
5831 else
5832 {
5833 /* movl.s %edi, %edi
5834 push %ebp
5835 movl.s %esp, %ebp */
5838 }
5839 }
5840 }
5842 /* regclass.c */
5845 /* Implementation of call abi switching target hook. Specific to FNDECL
5846 the specific call register sets are set. See also
5847 ix86_conditional_register_usage for more details. */
5848 void
5850 {
5853 else
5855 }
5857 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
5858 re-initialization of init_regs each time we switch function context since
5859 this is needed only during RTL expansion. */
5860 static void
5862 {
5866 }
5868 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5869 for a call to a function whose data type is FNTYPE.
5870 For a library call, FNTYPE is 0. */
5872 void
5876 tree fndecl,
5878 {
5880 tree fnret_type;
5884 /* Initialize for the current callee. */
5886 {
5889 }
5892 {
5896 }
5897 else
5898 {
5903 else
5905 }
5908 {
5912 {
5913 /* The return value of this function uses 256bit AVX modes. */
5916 else
5918 }
5919 }
5923 /* Set up the number of registers to use for passing arguments. */
5930 {
5932 ? X86_64_REGPARM_MAX
5934 }
5936 {
5939 {
5941 ? X86_64_SSE_REGPARM_MAX
5943 }
5944 }
5951 /* Because type might mismatch in between caller and callee, we need to
5952 use actual type of function for local calls.
5953 FIXME: cgraph_analyze can be told to actually record if function uses
5954 va_start so for local functions maybe_vaarg can be made aggressive
5955 helping K&R code.
5956 FIXME: once typesytem is fixed, we won't need this code anymore. */
5964 {
5965 /* If there are variable arguments, then we won't pass anything
5966 in registers in 32-bit mode. */
5968 {
5976 }
5978 /* Use ecx and edx registers if function has fastcall attribute,
5979 else look for regparm information. */
5981 {
5983 {
5986 }
5988 {
5991 }
5992 else
5994 }
5996 /* Set up the number of SSE registers used for passing SFmode
5997 and DFmode arguments. Warn for mismatching ABI. */
5999 }
6000 }
6002 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6003 But in the case of vector types, it is some vector mode.
6005 When we have only some of our vector isa extensions enabled, then there
6006 are some modes for which vector_mode_supported_p is false. For these
6007 modes, the generic vector support in gcc will choose some non-vector mode
6008 in order to implement the type. By computing the natural mode, we'll
6009 select the proper ABI location for the operand and not depend on whatever
6010 the middle-end decides to do with these vector types.
6012 The midde-end can't deal with the vector types > 16 bytes. In this
6013 case, we return the original mode and warn ABI change if CUM isn't
6014 NULL. */
6016 static enum machine_mode
6018 {
6022 {
6025 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6027 {
6032 else
6035 /* Get the mode which has this inner mode and number of units. */
6039 {
6041 {
6045 && !warnedavx
6047 {
6051 }
6053 }
6054 else
6056 }
6059 }
6060 }
6063 }
6065 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6066 this may not agree with the mode that the type system has chosen for the
6067 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6068 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6070 static rtx
6073 {
6074 rtx tmp;
6078 else
6079 {
6083 }
6086 }
6088 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6089 of this code is to classify each 8bytes of incoming argument by the register
6090 class and assign registers accordingly. */
6092 /* Return the union class of CLASS1 and CLASS2.
6093 See the x86-64 PS ABI for details. */
6095 static enum x86_64_reg_class
6097 {
6098 /* Rule #1: If both classes are equal, this is the resulting class. */
6102 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6103 the other class. */
6109 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6113 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6121 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6122 MEMORY is used. */
6131 /* Rule #6: Otherwise class SSE is used. */
6133 }
6135 /* Classify the argument of type TYPE and mode MODE.
6136 CLASSES will be filled by the register class used to pass each word
6137 of the operand. The number of words is returned. In case the parameter
6138 should be passed in memory, 0 is returned. As a special case for zero
6139 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6141 BIT_OFFSET is used internally for handling records and specifies offset
6142 of the offset in bits modulo 256 to avoid overflow cases.
6144 See the x86-64 PS ABI for details.
6145 */
6147 static int
6150 {
6151 HOST_WIDE_INT bytes =
6155 /* Variable sized entities are always passed/returned in memory. */
6164 {
6166 tree field;
6169 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6176 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6177 signalize memory class, so handle it as special case. */
6179 {
6182 }
6184 /* Classify each field of record and merge classes. */
6186 {
6188 /* And now merge the fields of structure. */
6190 {
6192 {
6198 /* Bitfields are always classified as integer. Handle them
6199 early, since later code would consider them to be
6200 misaligned integers. */
6202 {
6210 }
6211 else
6212 {
6217 /* Flexible array member is ignored. */
6224 {
6228 {
6231 "the ABI of passing struct with"
6232 " a flexible array member has"
6234 }
6236 }
6238 subclasses,
6247 }
6248 }
6249 }
6253 /* Arrays are handled as small records. */
6254 {
6261 /* The partial classes are now full classes. */
6272 }
6275 /* Unions are similar to RECORD_TYPE but offset is always 0.
6276 */
6278 {
6280 {
6288 bit_offset);
6293 }
6294 }
6299 }
6302 {
6303 /* When size > 16 bytes, if the first one isn't
6304 X86_64_SSE_CLASS or any other ones aren't
6305 X86_64_SSEUP_CLASS, everything should be passed in
6306 memory. */
6313 }
6315 /* Final merger cleanup. */
6317 {
6318 /* If one class is MEMORY, everything should be passed in
6319 memory. */
6323 /* The X86_64_SSEUP_CLASS should be always preceded by
6324 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6328 {
6329 /* The first one should never be X86_64_SSEUP_CLASS. */
6332 }
6334 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6335 everything should be passed in memory. */
6338 {
6341 /* The first one should never be X86_64_X87UP_CLASS. */
6344 {
6347 "the ABI of passing union with long double"
6349 }
6351 }
6352 }
6354 }
6356 /* Compute alignment needed. We align all types to natural boundaries with
6357 exception of XFmode that is aligned to 64bits. */
6359 {
6368 /* Misaligned fields are always returned in memory. */
6371 }
6373 /* for V1xx modes, just use the base mode */
6378 /* Classification of atomic types. */
6380 {
6396 {
6400 {
6403 }
6405 {
6408 }
6410 {
6414 }
6416 {
6419 }
6420 else
6422 }
6429 /* OImode shouldn't be used directly. */
6436 else
6454 else
6455 {
6459 {
6462 "the ABI of passing structure with complex float"
6464 }
6467 }
6476 /* This modes is larger than 16 bytes. */
6519 else
6523 }
6524 }
6526 /* Examine the argument and return set number of register required in each
6527 class. Return 0 iff parameter should be passed in memory. */
6528 static int
6531 {
6541 {
6563 }
6565 }
6567 /* Construct container for the argument used by GCC interface. See
6568 FUNCTION_ARG for the detailed description. */
6570 static rtx
6574 {
6575 /* The following variables hold the static issued_error state. */
6589 rtx ret;
6600 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6601 some less clueful developer tries to use floating-point anyway. */
6603 {
6605 {
6607 {
6610 }
6611 }
6613 {
6616 }
6618 }
6620 /* Likewise, error if the ABI requires us to return values in the
6621 x87 registers and the user specified -mno-80387. */
6627 {
6629 {
6632 }
6634 }
6636 /* First construct simple cases. Avoid SCmode, since we want to use
6637 single register to pass this type. */
6640 {
6655 /* Zero sized array, struct or class. */
6659 }
6680 /* Otherwise figure out the entries of the PARALLEL. */
6682 {
6686 {
6691 /* Merge TImodes on aligned occasions here too. */
6696 else
6698 /* We've requested 24 bytes we don't have mode for. Use DImode. */
6704 intreg++;
6711 sse_regno++;
6718 sse_regno++;
6723 {
6729 {
6731 i++;
6732 }
6733 else
6746 }
6751 sse_regno++;
6755 }
6756 }
6758 /* Empty aligned struct, union or class. */
6766 }
6768 /* Update the data in CUM to advance over an argument of mode MODE
6769 and data type TYPE. (TYPE is null for libcalls where that information
6770 may not be available.) */
6772 static void
6775 HOST_WIDE_INT words)
6776 {
6778 {
6785 /* FALLTHRU */
6796 {
6799 }
6803 /* OImode shouldn't be used directly. */
6812 /* FALLTHRU */
6828 {
6833 {
6836 }
6837 }
6847 {
6852 {
6855 }
6856 }
6858 }
6859 }
6861 static void
6864 {
6867 /* Unnamed 256bit vector mode parameters are passed on stack. */
6873 {
6878 }
6879 else
6880 {
6884 }
6885 }
6887 static void
6889 HOST_WIDE_INT words)
6890 {
6891 /* Otherwise, this should be passed indirect. */
6896 {
6899 }
6900 }
6902 /* Update the data in CUM to advance over an argument of mode MODE and
6903 data type TYPE. (TYPE is null for libcalls where that information
6904 may not be available.) */
6906 static void
6909 {
6914 else
6925 else
6927 }
6929 /* Define where to put the arguments to a function.
6930 Value is zero to push the argument on the stack,
6931 or a hard register in which to store the argument.
6933 MODE is the argument's machine mode.
6934 TYPE is the data type of the argument (as a tree).
6935 This is null for libcalls where that information may
6936 not be available.
6937 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6938 the preceding args and about the function being called.
6939 NAMED is nonzero if this argument is a named parameter
6940 (otherwise it is an extra parameter matching an ellipsis). */
6942 static rtx
6946 {
6949 /* Avoid the AL settings for the Unix64 ABI. */
6954 {
6961 /* FALLTHRU */
6967 {
6970 /* Fastcall allocates the first two DWORD (SImode) or
6971 smaller arguments to ECX and EDX if it isn't an
6972 aggregate type . */
6974 {
6980 /* ECX not EAX is the first allocated register. */
6983 }
6985 }
6994 /* FALLTHRU */
6996 /* In 32bit, we pass TImode in xmm registers. */
7004 {
7006 {
7010 }
7014 }
7018 /* OImode shouldn't be used directly. */
7028 {
7032 }
7042 {
7044 {
7048 }
7052 }
7054 }
7057 }
7059 static rtx
7062 {
7063 /* Handle a hidden AL argument containing number of registers
7064 for varargs x86-64 functions. */
7068 ? X86_64_SSE_REGPARM_MAX
7073 {
7083 /* Unnamed 256bit vector mode parameters are passed on stack. */
7087 }
7093 }
7095 static rtx
7098 HOST_WIDE_INT bytes)
7099 {
7102 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7103 We use value of -2 to specify that current function call is MSABI. */
7107 /* If we've run out of registers, it goes on the stack. */
7113 /* Only floating point modes are passed in anything but integer regs. */
7115 {
7118 else
7119 {
7122 /* Unnamed floating parameters are passed in both the
7123 SSE and integer registers. */
7129 }
7130 }
7131 /* Handle aggregated types passed in register. */
7133 {
7138 }
7141 }
7143 /* Return where to put the arguments to a function.
7144 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7146 MODE is the argument's machine mode. TYPE is the data type of the
7147 argument. It is null for libcalls where that information may not be
7148 available. CUM gives information about the preceding args and about
7149 the function being called. NAMED is nonzero if this argument is a
7150 named parameter (otherwise it is an extra parameter matching an
7151 ellipsis). */
7153 static rtx
7156 {
7159 rtx arg;
7163 else
7167 /* To simplify the code below, represent vector types with a vector mode
7168 even if MMX/SSE are not active. */
7176 else
7180 {
7181 /* This argument uses 256bit AVX modes. */
7184 else
7186 }
7189 }
7191 /* A C expression that indicates when an argument must be passed by
7192 reference. If nonzero for an argument, a copy of that argument is
7193 made in memory and a pointer to the argument is passed instead of
7194 the argument itself. The pointer is passed in whatever way is
7195 appropriate for passing a pointer to that type. */
7197 static bool
7201 {
7202 /* See Windows x64 Software Convention. */
7204 {
7207 {
7208 /* Arrays are passed by reference. */
7213 {
7214 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7215 are passed by reference. */
7217 }
7218 }
7220 /* __m128 is passed by reference. */
7226 }
7227 }
7232 }
7234 /* Return true when TYPE should be 128bit aligned for 32bit argument
7235 passing ABI. XXX: This function is obsolete and is only used for
7236 checking psABI compatibility with previous versions of GCC. */
7238 static bool
7240 {
7252 {
7253 /* Walk the aggregates recursively. */
7255 {
7259 {
7260 tree field;
7262 /* Walk all the structure fields. */
7264 {
7268 }
7270 }
7273 /* Just for use if some languages passes arrays by value. */
7280 }
7281 }
7283 }
7285 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7286 XXX: This function is obsolete and is only used for checking psABI
7287 compatibility with previous versions of GCC. */
7289 static unsigned int
7292 {
7293 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7294 natural boundaries. */
7296 {
7297 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7298 make an exception for SSE modes since these require 128bit
7299 alignment.
7301 The handling here differs from field_alignment. ICC aligns MMX
7302 arguments to 4 byte boundaries, while structure fields are aligned
7303 to 8 byte boundaries. */
7305 {
7308 }
7309 else
7310 {
7313 }
7314 }
7318 }
7320 /* Return true when TYPE should be 128bit aligned for 32bit argument
7321 passing ABI. */
7323 static bool
7325 {
7335 {
7336 /* Walk the aggregates recursively. */
7338 {
7342 {
7343 tree field;
7345 /* Walk all the structure fields. */
7347 field;
7349 {
7353 }
7355 }
7358 /* Just for use if some languages passes arrays by value. */
7365 }
7366 }
7367 else
7371 }
7373 /* Gives the alignment boundary, in bits, of an argument with the
7374 specified mode and type. */
7376 static unsigned int
7378 {
7381 {
7382 /* Since the main variant type is used for call, we convert it to
7383 the main variant type. */
7386 }
7387 else
7391 else
7392 {
7397 {
7398 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7400 {
7403 }
7409 }
7412 && !warned
7414 saved_align))
7415 {
7418 "The ABI for passing parameters with %d-byte"
7421 }
7422 }
7425 }
7427 /* Return true if N is a possible register number of function value. */
7429 static bool
7431 {
7433 {
7438 /* TODO: The function should depend on current function ABI but
7439 builtins.c would need updating then. Therefore we use the
7440 default ABI. */
7452 }
7455 }
7457 /* Define how to find the value returned by a function.
7458 VALTYPE is the data type of the value (as a tree).
7459 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7460 otherwise, FUNC is 0. */
7462 static rtx
7465 {
7468 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7469 we normally prevent this case when mmx is not available. However
7470 some ABIs may require the result to be returned like DImode. */
7474 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7475 we prevent this case when sse is not available. However some ABIs
7476 may require the result to be returned like integer TImode. */
7481 /* 32-byte vector modes in %ymm0. */
7485 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7488 else
7489 /* Most things go in %eax. */
7492 /* Override FP return register with %xmm0 for local functions when
7493 SSE math is enabled or for functions with sseregparm attribute. */
7495 {
7500 }
7502 /* OImode shouldn't be used directly. */
7506 }
7508 static rtx
7510 const_tree valtype)
7511 {
7512 rtx ret;
7514 /* Handle libcalls, which don't provide a type node. */
7516 {
7518 {
7535 }
7536 }
7542 /* For zero sized structures, construct_container returns NULL, but we
7543 need to keep rest of compiler happy by returning meaningful value. */
7548 }
7550 static rtx
7552 {
7556 {
7558 {
7571 }
7572 }
7574 }
7576 static rtx
7579 {
7591 else
7593 }
7595 static rtx
7598 {
7604 }
7606 rtx
7608 {
7610 }
7612 /* Return true iff type is returned in memory. */
7614 static bool ATTRIBUTE_UNUSED
7616 {
7617 HOST_WIDE_INT size;
7628 {
7629 /* User-created vectors small enough to fit in EAX. */
7633 /* MMX/3dNow values are returned in MM0,
7634 except when it doesn't exits or the ABI prescribes otherwise. */
7638 /* SSE values are returned in XMM0, except when it doesn't exist. */
7642 /* AVX values are returned in YMM0, except when it doesn't exist. */
7645 }
7653 /* OImode shouldn't be used directly. */
7657 }
7659 static bool ATTRIBUTE_UNUSED
7661 {
7664 }
7666 static bool ATTRIBUTE_UNUSED
7668 {
7671 /* __m128 is returned in xmm0. */
7676 /* Otherwise, the size must be exactly in [1248]. */
7678 }
7680 static bool
7682 {
7683 #ifdef SUBTARGET_RETURN_IN_MEMORY
7685 #else
7689 {
7692 else
7694 }
7695 else
7697 #endif
7698 }
7700 /* When returning SSE vector types, we have a choice of either
7701 (1) being abi incompatible with a -march switch, or
7702 (2) generating an error.
7703 Given no good solution, I think the safest thing is one warning.
7704 The user won't be able to use -Werror, but....
7706 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7707 called in response to actually generating a caller or callee that
7708 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7709 via aggregate_value_p for general type probing from tree-ssa. */
7711 static rtx
7713 {
7717 {
7718 /* Look at the return type of the function, not the function type. */
7722 {
7725 {
7729 }
7730 }
7733 {
7735 {
7739 }
7740 }
7741 }
7744 }
7746 \f
7747 /* Create the va_list data type. */
7749 /* Returns the calling convention specific va_list date type.
7750 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7752 static tree
7754 {
7757 /* For i386 we use plain pointer to argument area. */
7767 unsigned_type_node);
7770 unsigned_type_node);
7773 ptr_type_node);
7776 ptr_type_node);
7795 /* The correct type is an array type of one element. */
7797 }
7799 /* Setup the builtin va_list data type and for 64-bit the additional
7800 calling convention specific va_list data types. */
7802 static tree
7804 {
7807 /* Initialize abi specific va_list builtin types. */
7809 {
7810 tree t;
7812 {
7817 }
7818 else
7819 {
7824 }
7826 {
7831 }
7832 else
7833 {
7838 }
7839 }
7842 }
7844 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7846 static void
7848 {
7850 alias_set_type set;
7853 /* GPR size of varargs save area. */
7856 else
7859 /* FPR size of varargs save area. We don't need it if we don't pass
7860 anything in SSE registers. */
7863 else
7877 {
7884 }
7887 {
7891 /* Now emit code to save SSE registers. The AX parameter contains number
7892 of SSE parameter registers used to call this function, though all we
7893 actually check here is the zero/non-zero status. */
7898 label));
7900 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7901 we used movdqa (i.e. TImode) instead? Perhaps even better would
7902 be if we could determine the real mode of the data, via a hook
7903 into pass_stdarg. Ignore all that for now. */
7913 {
7921 }
7924 }
7925 }
7927 static void
7929 {
7934 {
7945 }
7946 }
7948 static void
7952 {
7953 CUMULATIVE_ARGS next_cum;
7954 tree fntype;
7956 /* This argument doesn't appear to be used anymore. Which is good,
7957 because the old code here didn't suppress rtl generation. */
7965 /* For varargs, we do not want to skip the dummy va_dcl argument.
7966 For stdargs, we do want to skip the last named argument. */
7973 else
7975 }
7977 /* Checks if TYPE is of kind va_list char *. */
7979 static bool
7981 {
7982 tree canonic;
7984 /* For 32-bit it is always true. */
7990 }
7992 /* Implement va_start. */
7994 static void
7996 {
8000 tree type;
8001 rtx ovf_rtx;
8005 {
8008 /* When we are splitting the stack, we can't refer to the stack
8009 arguments using internal_arg_pointer, because they may be on
8010 the old stack. The split stack prologue will arrange to
8011 leave a pointer to the old stack arguments in a scratch
8012 register, which we here copy to a pseudo-register. The split
8013 stack prologue can't set the pseudo-register directly because
8014 it (the prologue) runs before any registers have been saved. */
8018 {
8032 }
8033 }
8035 /* Only 64bit target needs something special. */
8037 {
8040 else
8041 {
8050 }
8052 }
8061 /* The following should be folded into the MEM_REF offset. */
8071 /* Count number of gp and fp argument registers used. */
8077 {
8083 }
8086 {
8092 }
8094 /* Find the overflow area. */
8098 else
8109 {
8110 /* Find the register save area.
8111 Prologue of the function save it right above stack frame. */
8120 }
8121 }
8123 /* Implement va_arg. */
8125 static tree
8128 {
8135 rtx container;
8137 tree ptrtype;
8141 /* Only 64bit target needs something special. */
8165 {
8172 /* Unnamed 256bit vector mode parameters are passed on stack. */
8174 {
8177 }
8185 }
8187 /* Pull the value out of the saved registers. */
8192 {
8206 /* In case we are passing structure, verify that it is consecutive block
8207 on the register save area. If not we need to do moves. */
8209 {
8210 /* Verify that all registers are strictly consecutive */
8212 {
8216 {
8221 }
8222 }
8223 else
8224 {
8228 {
8233 }
8234 }
8235 }
8237 {
8240 }
8241 else
8242 {
8245 }
8247 /* First ensure that we fit completely in registers. */
8249 {
8256 }
8258 {
8266 }
8268 /* Compute index to start of area used for integer regs. */
8270 {
8271 /* int_addr = gpr + sav; */
8275 }
8277 {
8278 /* sse_addr = fpr + sav; */
8282 }
8284 {
8288 /* addr = &temp; */
8293 {
8297 tree piece_type;
8298 tree addr_type;
8299 tree daddr_type;
8308 {
8313 }
8317 else
8324 {
8327 }
8328 else
8329 {
8332 }
8341 {
8346 }
8347 else
8348 {
8349 tree copy
8354 }
8356 }
8357 }
8360 {
8364 }
8367 {
8371 }
8376 }
8378 /* ... otherwise out of the overflow area. */
8380 /* When we align parameter on stack for caller, if the parameter
8381 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8382 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8383 here with caller. */
8388 /* Care for on-stack alignment if needed. */
8391 else
8392 {
8400 }
8418 }
8419 \f
8420 /* Return true if OPNUM's MEM should be matched
8421 in movabs* patterns. */
8423 bool
8425 {
8437 }
8438 \f
8439 /* Initialize the table of extra 80387 mathematical constants. */
8441 static void
8443 {
8445 {
8451 };
8455 {
8457 /* Ensure each constant is rounded to XFmode precision. */
8460 }
8463 }
8465 /* Return non-zero if the constant is something that
8466 can be loaded with a special instruction. */
8468 int
8470 {
8473 REAL_VALUE_TYPE r;
8485 /* For XFmode constants, try to find a special 80387 instruction when
8486 optimizing for size or on those CPUs that benefit from them. */
8489 {
8498 }
8500 /* Load of the constant -0.0 or -1.0 will be split as
8501 fldz;fchs or fld1;fchs sequence. */
8508 }
8510 /* Return the opcode of the special instruction to be used to load
8511 the constant X. */
8515 {
8517 {
8537 }
8538 }
8540 /* Return the CONST_DOUBLE representing the 80387 constant that is
8541 loaded by the specified special instruction. The argument IDX
8542 matches the return value from standard_80387_constant_p. */
8544 rtx
8546 {
8553 {
8564 }
8567 XFmode);
8568 }
8570 /* Return 1 if X is all 0s and 2 if x is all 1s
8571 in supported SSE vector mode. */
8573 int
8575 {
8582 {
8591 }
8594 }
8596 /* Return the opcode of the special instruction to be used to load
8597 the constant X. */
8601 {
8603 {
8606 {
8612 else
8617 else
8624 else
8629 else
8633 }
8638 }
8640 }
8642 /* Returns true if OP contains a symbol reference */
8644 bool
8646 {
8655 {
8657 {
8663 }
8667 }
8670 }
8672 /* Return true if it is appropriate to emit `ret' instructions in the
8673 body of a function. Do this only if the epilogue is simple, needing a
8674 couple of insns. Prior to reloading, we can't tell how many registers
8675 must be saved, so return false then. Return false if there is no frame
8676 marker to de-allocate. */
8678 bool
8680 {
8686 /* Don't allow more than 32k pop, since that's all we can do
8687 with one instruction. */
8694 }
8695 \f
8696 /* Value should be nonzero if functions must have frame pointers.
8697 Zero means the frame pointer need not be set up (and parms may
8698 be accessed via the stack pointer) in functions that seem suitable. */
8700 static bool
8702 {
8703 /* If we accessed previous frames, then the generated code expects
8704 to be able to access the saved ebp value in our frame. */
8708 /* Several x86 os'es need a frame pointer for other reasons,
8709 usually pertaining to setjmp. */
8713 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8714 turns off the frame pointer by default. Turn it back on now if
8715 we've not got a leaf function. */
8717 && (!current_function_is_leaf
8725 }
8727 /* Record that the current function accesses previous call frames. */
8729 void
8731 {
8733 }
8734 \f
8735 #ifndef USE_HIDDEN_LINKONCE
8736 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
8737 # define USE_HIDDEN_LINKONCE 1
8738 # else
8739 # define USE_HIDDEN_LINKONCE 0
8740 # endif
8741 #endif
8745 /* Fills in the label name that should be used for a pc thunk for
8746 the given register. */
8748 static void
8750 {
8755 else
8757 }
8760 /* This function generates code for -fpic that loads %ebx with
8761 the return address of the caller and then returns. */
8763 static void
8765 {
8770 {
8772 tree decl;
8787 #if TARGET_MACHO
8789 {
8798 }
8799 else
8800 #endif
8802 {
8813 }
8814 else
8815 {
8818 }
8824 /* Make sure unwind info is emitted for the thunk if needed. */
8827 /* Pad stack IP move with 4 instructions (two NOPs count
8828 as one instruction). */
8830 {
8835 }
8846 }
8850 }
8852 /* Emit code for the SET_GOT patterns. */
8856 {
8862 {
8863 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8868 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8869 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8870 an unadorned address. */
8875 }
8880 {
8885 else
8886 {
8888 #ifdef DWARF2_UNWIND_INFO
8889 /* The call to next label acts as a push. */
8891 {
8892 rtx insn;
8896 stack_pointer_rtx,
8901 }
8902 #endif
8903 }
8905 #if TARGET_MACHO
8906 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8907 is what will be referenced by the Mach-O PIC subsystem. */
8910 #endif
8916 {
8918 #ifdef DWARF2_UNWIND_INFO
8919 /* The pop is a pop and clobbers dest, but doesn't restore it
8920 for unwind info purposes. */
8922 {
8923 rtx insn;
8929 stack_pointer_rtx,
8934 }
8935 #endif
8936 }
8937 }
8938 else
8939 {
8944 #ifdef DWARF2_UNWIND_INFO
8945 /* Ensure all queued register saves are flushed before the
8946 call. */
8949 #endif
8953 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8954 is what will be referenced by the Mach-O PIC subsystem. */
8955 #if TARGET_MACHO
8958 else
8961 #endif
8962 }
8969 else
8973 }
8975 /* Generate an "push" pattern for input ARG. */
8977 static rtx
8979 {
8989 stack_pointer_rtx)),
8990 arg);
8991 }
8993 /* Generate an "pop" pattern for input ARG. */
8995 static rtx
8997 {
8999 arg,
9002 stack_pointer_rtx)));
9003 }
9005 /* Return >= 0 if there is an unused call-clobbered register available
9006 for the entire function. */
9008 static unsigned int
9010 {
9014 {
9016 /* Can't use the same register for both PIC and DRAP. */
9019 else
9024 }
9027 }
9029 /* Return 1 if we need to save REGNO. */
9030 static int
9032 {
9039 {
9043 }
9046 {
9049 {
9055 }
9056 }
9065 }
9067 /* Return number of saved general prupose registers. */
9069 static int
9071 {
9077 nregs ++;
9079 }
9081 /* Return number of saved SSE registrers. */
9083 static int
9085 {
9093 nregs ++;
9095 }
9097 /* Given FROM and TO register numbers, say whether this elimination is
9098 allowed. If stack alignment is needed, we can only replace argument
9099 pointer with hard frame pointer, or replace frame pointer with stack
9100 pointer. Otherwise, frame pointer elimination is automatically
9101 handled and all other eliminations are valid. */
9103 static bool
9105 {
9111 else
9113 }
9115 /* Return the offset between two registers, one to be eliminated, and the other
9116 its replacement, at the start of a routine. */
9118 HOST_WIDE_INT
9120 {
9129 else
9130 {
9138 }
9139 }
9141 /* In a dynamically-aligned function, we can't know the offset from
9142 stack pointer to frame pointer, so we must ensure that setjmp
9143 eliminates fp against the hard fp (%ebp) rather than trying to
9144 index from %esp up to the top of the frame across a gap that is
9145 of unknown (at compile-time) size. */
9146 static rtx
9148 {
9150 }
9152 /* On the x86 -fsplit-stack and -fstack-protector both use the same
9153 field in the TCB, so they can not be used together. */
9155 static bool
9158 {
9161 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
9165 #else
9167 {
9172 }
9173 #endif
9176 }
9178 /* When using -fsplit-stack, the allocation routines set a field in
9179 the TCB to the bottom of the stack plus this much space, measured
9180 in bytes. */
9182 #define SPLIT_STACK_AVAILABLE 256
9184 /* Fill structure ix86_frame about frame of currently computed function. */
9186 static void
9188 {
9190 HOST_WIDE_INT offset;
9193 HOST_WIDE_INT to_allocate;
9201 /* MS ABI seem to require stack alignment to be always 16 except for function
9202 prologues and leaf. */
9206 {
9211 }
9217 /* For SEH we have to limit the amount of code movement into the prologue.
9218 At present we do this via a BLOCKAGE, at which point there's very little
9219 scheduling that can be done, which means that there's very little point
9220 in doing anything except PUSHs. */
9224 /* During reload iteration the amount of registers saved can change.
9225 Recompute the value as needed. Do not recompute when amount of registers
9226 didn't change as reload does multiple calls to the function and does not
9227 expect the decision to change within single iteration. */
9230 {
9236 /* The fast prologue uses move instead of push to save registers. This
9237 is significantly longer, but also executes faster as modern hardware
9238 can execute the moves in parallel, but can't do that for push/pop.
9240 Be careful about choosing what prologue to emit: When function takes
9241 many instructions to execute we may use slow version as well as in
9242 case function is known to be outside hot spot (this is known with
9243 feedback only). Weight the size of function by number of registers
9244 to save as it is cheap to use one or two push instructions but very
9245 slow to use many of them. */
9249 || (flag_branch_probabilities
9252 else
9255 }
9259 else
9262 /* If static stack checking is enabled and done with probes, the registers
9263 need to be saved before allocating the frame. */
9267 /* Skip return address. */
9270 /* Skip pushed static chain. */
9274 /* Skip saved base pointer. */
9279 /* The traditional frame pointer location is at the top of the frame. */
9282 /* Register save area */
9286 /* Align and set SSE register save area. */
9288 {
9289 /* The only ABI that has saved SSE registers (Win64) also has a
9290 16-byte aligned default stack, and thus we don't need to be
9291 within the re-aligned local stack frame to save them. */
9295 }
9298 /* The re-aligned stack starts here. Values before this point are not
9299 directly comparable with values below this point. In order to make
9300 sure that no value happens to be the same before and after, force
9301 the alignment computation below to add a non-zero value. */
9305 /* Va-arg area */
9309 /* Align start of frame for local function. */
9312 /* Frame pointer points here. */
9317 /* Add outgoing arguments area. Can be skipped if we eliminated
9318 all the function calls as dead code.
9319 Skipping is however impossible when function calls alloca. Alloca
9320 expander assumes that last crtl->outgoing_args_size
9321 of stack frame are unused. */
9325 {
9328 }
9329 else
9332 /* Align stack boundary. Only needed if we're calling another function
9333 or using alloca. */
9338 /* We've reached end of stack frame. */
9341 /* Size prologue needs to allocate. */
9349 && current_function_sp_is_unchanging
9350 && current_function_is_leaf
9352 {
9358 }
9359 else
9363 /* The SEH frame pointer location is near the bottom of the frame.
9364 This is enforced by the fact that the difference between the
9365 stack pointer and the frame pointer is limited to 240 bytes in
9366 the unwind data structure. */
9368 {
9369 HOST_WIDE_INT diff;
9371 /* If we can leave the frame pointer where it is, do so. */
9374 {
9375 /* Ideally we'd determine what portion of the local stack frame
9376 (within the constraint of the lowest 240) is most heavily used.
9377 But without that complication, simply bias the frame pointer
9378 by 128 bytes so as to maximize the amount of the local stack
9379 frame that is addressable with 8-bit offsets. */
9381 }
9382 }
9383 }
9385 /* This is semi-inlined memory_address_length, but simplified
9386 since we know that we're always dealing with reg+offset, and
9387 to avoid having to create and discard all that rtl. */
9391 {
9395 {
9396 /* EBP and R13 cannot be encoded without an offset. */
9398 }
9402 /* ESP and R12 must be encoded with a SIB byte. */
9404 len++;
9407 }
9409 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9410 The valid base registers are taken from CFUN->MACHINE->FS. */
9412 static rtx
9414 {
9420 {
9421 /* Choose the base register most likely to allow the most scheduling
9422 opportunities. Generally FP is valid througout the function,
9423 while DRAP must be reloaded within the epilogue. But choose either
9424 over the SP due to increased encoding size. */
9427 {
9430 }
9432 {
9435 }
9437 {
9440 }
9441 }
9442 else
9443 {
9444 HOST_WIDE_INT toffset;
9447 /* Choose the base register with the smallest address encoding.
9448 With a tie, choose FP > DRAP > SP. */
9450 {
9454 }
9456 {
9460 {
9464 }
9465 }
9467 {
9471 {
9475 }
9476 }
9477 }
9481 }
9483 /* Emit code to save registers in the prologue. */
9485 static void
9487 {
9489 rtx insn;
9493 {
9496 }
9497 }
9499 /* Emit a single register save at CFA - CFA_OFFSET. */
9501 static void
9503 HOST_WIDE_INT cfa_offset)
9504 {
9512 /* For SSE saves, we need to indicate the 128-bit alignment. */
9523 /* When saving registers into a re-aligned local stack frame, avoid
9524 any tricky guessing by dwarf2out. */
9526 {
9530 {
9531 /* A bit of a hack. We force the DRAP register to be saved in
9532 the re-aligned stack frame, which provides us with a copy
9533 of the CFA that will last past the prologue. Install it. */
9539 }
9540 else
9541 {
9542 /* The frame pointer is a stable reference within the
9543 aligned frame. Use it. */
9550 }
9551 }
9553 /* The memory may not be relative to the current CFA register,
9554 which means that we may need to generate a new pattern for
9555 use by the unwind info. */
9557 {
9561 }
9562 }
9564 /* Emit code to save registers using MOV insns.
9565 First register is stored at CFA - CFA_OFFSET. */
9566 static void
9568 {
9573 {
9576 }
9577 }
9579 /* Emit code to save SSE registers using MOV insns.
9580 First register is stored at CFA - CFA_OFFSET. */
9581 static void
9583 {
9588 {
9591 }
9592 }
9596 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9597 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9598 Don't add the note if the previously saved value will be left untouched
9599 within stack red-zone till return, as unwinders can find the same value
9600 in the register and on the stack. */
9602 static void
9604 {
9609 {
9612 }
9613 else
9614 queued_cfa_restores
9616 }
9618 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9620 static void
9622 {
9623 rtx last;
9627 ;
9632 }
9634 /* Expand prologue or epilogue stack adjustment.
9635 The pattern exist to put a dependency on all ebp-based memory accesses.
9636 STYLE should be negative if instructions should be marked as frame related,
9637 zero if %r11 register is live and cannot be freely used and positive
9638 otherwise. */
9640 static void
9643 {
9645 rtx insn;
9652 else
9653 {
9654 rtx tmp;
9655 /* r11 is used by indirect sibcall return as well, set before the
9656 epilogue and used after the epilogue. */
9659 else
9660 {
9664 }
9670 }
9677 {
9678 rtx r;
9688 }
9690 {
9693 {
9697 }
9698 }
9701 {
9706 {
9709 }
9711 {
9714 }
9715 else
9716 {
9717 /* Else there are two possibilities: SP itself, which we set
9718 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9719 taken care of this by hand along the eh_return path. */
9722 }
9726 }
9727 }
9729 /* Find an available register to be used as dynamic realign argument
9730 pointer regsiter. Such a register will be written in prologue and
9731 used in begin of body, so it must not be
9732 1. parameter passing register.
9733 2. GOT pointer.
9734 We reuse static-chain register if it is available. Otherwise, we
9735 use DI for i386 and R13 for x86-64. We chose R13 since it has
9736 shorter encoding.
9738 Return: the regno of chosen register. */
9740 static unsigned int
9742 {
9746 {
9747 /* Use R13 for nested function or function need static chain.
9748 Since function with tail call may use any caller-saved
9749 registers in epilogue, DRAP must not use caller-saved
9750 register in such case. */
9755 }
9756 else
9757 {
9758 /* Use DI for nested function or function need static chain.
9759 Since function with tail call may use any caller-saved
9760 registers in epilogue, DRAP must not use caller-saved
9761 register in such case. */
9765 /* Reuse static chain register if it isn't used for parameter
9766 passing. */
9773 else
9775 }
9776 }
9778 /* Return minimum incoming stack alignment. */
9780 static unsigned int
9782 {
9785 /* Prefer the one specified at command line. */
9788 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9789 if -mstackrealign is used, it isn't used for sibcall check and
9790 estimated stack alignment is 128bit. */
9792 && !TARGET_64BIT
9793 && ix86_force_align_arg_pointer
9796 else
9799 /* Incoming stack alignment can be changed on individual functions
9800 via force_align_arg_pointer attribute. We use the smallest
9801 incoming stack boundary. */
9807 /* The incoming stack frame has to be aligned at least at
9808 parm_stack_boundary. */
9812 /* Stack at entrance of main is aligned by runtime. We use the
9813 smallest incoming stack boundary. */
9821 }
9823 /* Update incoming stack boundary and estimated stack alignment. */
9825 static void
9827 {
9828 ix86_incoming_stack_boundary
9831 /* x86_64 vararg needs 16byte stack alignment for register save
9832 area. */
9837 }
9839 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9840 needed or an rtx for DRAP otherwise. */
9842 static rtx
9844 {
9849 {
9850 /* Assign DRAP to vDRAP and returns vDRAP */
9852 rtx drap_vreg;
9853 rtx arg_ptr;
9866 {
9869 }
9871 }
9872 else
9874 }
9876 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9878 static rtx
9880 {
9882 }
9885 rtx reg;
9887 };
9889 /* Return a short-lived scratch register for use on function entry.
9890 In 32-bit mode, it is valid only after the registers are saved
9891 in the prologue. This register must be released by means of
9892 release_scratch_register_on_entry once it is dead. */
9894 static void
9896 {
9902 {
9903 /* We always use R11 in 64-bit mode. */
9905 }
9906 else
9907 {
9909 bool fastcall_p
9913 int drap_regno
9916 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9917 for the static chain register. */
9923 /* ecx is the static chain register. */
9929 /* esi is the static chain register. */
9935 else
9936 {
9939 }
9940 }
9944 {
9947 }
9948 }
9950 /* Release a scratch register obtained from the preceding function. */
9952 static void
9954 {
9956 {
9959 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9964 }
9965 }
9967 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9969 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9971 static void
9973 {
9974 /* We skip the probe for the first interval + a small dope of 4 words and
9975 probe that many bytes past the specified size to maintain a protection
9976 area at the botton of the stack. */
9980 /* See if we have a constant small number of probes to generate. If so,
9981 that's the easy case. The run-time loop is made up of 11 insns in the
9982 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9983 for n # of intervals. */
9985 {
9989 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9990 values of N from 1 until it exceeds SIZE. If only one probe is
9991 needed, this will not generate any code. Then adjust and probe
9992 to PROBE_INTERVAL + SIZE. */
9994 {
9996 {
9999 }
10000 else
10006 }
10010 else
10017 /* Adjust back to account for the additional first interval. */
10021 }
10023 /* Otherwise, do the same as above, but in a loop. Note that we must be
10024 extra careful with variables wrapping around because we might be at
10025 the very top (or the very bottom) of the address space and we have
10026 to be able to handle this case properly; in particular, we use an
10027 equality test for the loop condition. */
10028 else
10029 {
10030 HOST_WIDE_INT rounded_size;
10036 /* Step 1: round SIZE to the previous multiple of the interval. */
10041 /* Step 2: compute initial and final value of the loop counter. */
10043 /* SP = SP_0 + PROBE_INTERVAL. */
10048 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10052 stack_pointer_rtx)));
10055 /* Step 3: the loop
10057 while (SP != LAST_ADDR)
10058 {
10059 SP = SP + PROBE_INTERVAL
10060 probe at SP
10061 }
10063 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10064 values of N from 1 until it is equal to ROUNDED_SIZE. */
10069 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10070 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10073 {
10078 }
10080 /* Adjust back to account for the additional first interval. */
10086 }
10091 /* Make sure nothing is scheduled before we are done. */
10093 }
10095 /* Adjust the stack pointer up to REG while probing it. */
10099 {
10109 /* Jump to END_LAB if SP == LAST_ADDR. */
10117 /* SP = SP + PROBE_INTERVAL. */
10121 /* Probe at SP. */
10132 }
10134 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10135 inclusive. These are offsets from the current stack pointer. */
10137 static void
10139 {
10140 /* See if we have a constant small number of probes to generate. If so,
10141 that's the easy case. The run-time loop is made up of 7 insns in the
10142 generic case while the compile-time loop is made up of n insns for n #
10143 of intervals. */
10145 {
10146 HOST_WIDE_INT i;
10148 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10149 it exceeds SIZE. If only one probe is needed, this will not
10150 generate any code. Then probe at FIRST + SIZE. */
10155 }
10157 /* Otherwise, do the same as above, but in a loop. Note that we must be
10158 extra careful with variables wrapping around because we might be at
10159 the very top (or the very bottom) of the address space and we have
10160 to be able to handle this case properly; in particular, we use an
10161 equality test for the loop condition. */
10162 else
10163 {
10170 /* Step 1: round SIZE to the previous multiple of the interval. */
10175 /* Step 2: compute initial and final value of the loop counter. */
10177 /* TEST_OFFSET = FIRST. */
10180 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10184 /* Step 3: the loop
10186 while (TEST_ADDR != LAST_ADDR)
10187 {
10188 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10189 probe at TEST_ADDR
10190 }
10192 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10193 until it is equal to ROUNDED_SIZE. */
10198 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10199 that SIZE is equal to ROUNDED_SIZE. */
10203 stack_pointer_rtx,
10208 }
10210 /* Make sure nothing is scheduled before we are done. */
10212 }
10214 /* Probe a range of stack addresses from REG to END, inclusive. These are
10215 offsets from the current stack pointer. */
10219 {
10229 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10237 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10241 /* Probe at TEST_ADDR. */
10254 }
10256 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10257 to be generated in correct form. */
10258 static void
10260 {
10261 /* Check if stack realign is really needed after reload, and
10262 stores result in cfun */
10263 unsigned int incoming_stack_boundary
10267 < (current_function_is_leaf
10272 {
10273 /* After stack_realign_needed is finalized, we can't no longer
10274 change it. */
10276 }
10277 else
10278 {
10281 }
10282 }
10284 /* Expand the prologue into a bunch of separate insns. */
10286 void
10288 {
10293 HOST_WIDE_INT allocate;
10298 /* DRAP should not coexist with stack_realign_fp */
10303 /* Initialize CFA state for before the prologue. */
10307 /* Track SP offset to the CFA. We continue tracking this after we've
10308 swapped the CFA register away from SP. In the case of re-alignment
10309 this is fudged; we're interested to offsets within the local frame. */
10316 {
10317 /* We should have already generated an error for any use of
10318 ms_hook on a nested function. */
10321 /* Check if profiling is active and we shall use profiling before
10322 prologue variant. If so sorry. */
10327 /* In ix86_asm_output_function_label we emitted:
10328 8b ff movl.s %edi,%edi
10329 55 push %ebp
10330 8b ec movl.s %esp,%ebp
10332 This matches the hookable function prologue in Win32 API
10333 functions in Microsoft Windows XP Service Pack 2 and newer.
10334 Wine uses this to enable Windows apps to hook the Win32 API
10335 functions provided by Wine.
10337 What that means is that we've already set up the frame pointer. */
10341 {
10344 /* We've decided to use the frame pointer already set up.
10345 Describe this to the unwinder by pretending that both
10346 push and mov insns happen right here.
10348 Putting the unwind info here at the end of the ms_hook
10349 is done so that we can make absolutely certain we get
10350 the required byte sequence at the start of the function,
10351 rather than relying on an assembler that can produce
10352 the exact encoding required.
10354 However it does mean (in the unpatched case) that we have
10355 a 1 insn window where the asynchronous unwind info is
10356 incorrect. However, if we placed the unwind info at
10357 its correct location we would have incorrect unwind info
10358 in the patched case. Which is probably all moot since
10359 I don't expect Wine generates dwarf2 unwind info for the
10360 system libraries that use this feature. */
10366 stack_pointer_rtx);
10374 /* Note that gen_push incremented m->fs.cfa_offset, even
10375 though we didn't emit the push insn here. */
10379 }
10380 else
10381 {
10382 /* The frame pointer is not needed so pop %ebp again.
10383 This leaves us with a pristine state. */
10385 }
10386 }
10388 /* The first insn of a function that accepts its static chain on the
10389 stack is to push the register that would be filled in by a direct
10390 call. This insn will be skipped by the trampoline. */
10392 {
10396 /* We don't want to interpret this push insn as a register save,
10397 only as a stack adjustment. The real copy of the register as
10398 a save will be done later, if needed. */
10403 }
10405 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10406 of DRAP is needed and stack realignment is really needed after reload */
10408 {
10411 /* Only need to push parameter pointer reg if it is caller saved. */
10413 {
10414 /* Push arg pointer reg */
10417 }
10419 /* Grab the argument pointer. */
10426 /* Align the stack. */
10428 stack_pointer_rtx,
10432 /* Replicate the return address on the stack so that return
10433 address can be reached via (argp - 1) slot. This is needed
10434 to implement macro RETURN_ADDR_RTX and intrinsic function
10435 expand_builtin_return_addr etc. */
10441 /* For the purposes of frame and register save area addressing,
10442 we've started over with a new frame. */
10445 }
10448 {
10449 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10450 slower on all targets. Also sdb doesn't like it. */
10455 {
10463 }
10464 }
10469 {
10470 /* If saving registers via PUSH, do so now. */
10472 {
10476 }
10478 /* When using red zone we may start register saving before allocating
10479 the stack frame saving one cycle of the prologue. However, avoid
10480 doing this if we have to probe the stack; at least on x86_64 the
10481 stack probe can turn into a call that clobbers a red zone location. */
10483 && (! TARGET_STACK_PROBE
10485 {
10488 }
10489 }
10492 {
10496 /* The computation of the size of the re-aligned stack frame means
10497 that we must allocate the size of the register save area before
10498 performing the actual alignment. Otherwise we cannot guarantee
10499 that there's enough storage above the realignment point. */
10506 /* Align the stack. */
10508 stack_pointer_rtx,
10511 /* For the purposes of register save area addressing, the stack
10512 pointer is no longer valid. As for the value of sp_offset,
10513 see ix86_compute_frame_layout, which we need to match in order
10514 to pass verification of stack_pointer_offset at the end. */
10517 }
10522 {
10523 /* We start to count from ARG_POINTER. */
10526 /* If it was realigned, take into account the fake frame. */
10528 {
10535 /* This over-estimates by 1 minimal-stack-alignment-unit but
10536 mitigates that by counting in the new return address slot. */
10537 current_function_dynamic_stack_size
10539 }
10542 }
10544 /* The stack has already been decremented by the instruction calling us
10545 so we need to probe unconditionally to preserve the protection area. */
10547 {
10548 /* We expect the registers to be saved when probes are used. */
10552 {
10555 }
10556 else
10557 {
10565 else
10567 }
10568 }
10571 ;
10574 {
10578 }
10579 else
10580 {
10594 {
10597 }
10599 {
10603 }
10608 /* Use the fact that AX still contains ALLOCATE. */
10609 adjust_stack_insn = (TARGET_64BIT
10610 ? gen_pro_epilogue_adjust_stack_di_sub
10616 /* Note that SEH directives need to continue tracking the stack
10617 pointer even after the frame pointer has been set up. */
10619 {
10628 }
10632 {
10637 }
10639 {
10642 }
10643 }
10646 /* If we havn't already set up the frame pointer, do so now. */
10648 {
10660 }
10671 {
10678 }
10681 {
10683 {
10685 {
10695 }
10696 else
10698 }
10699 else
10701 }
10703 /* In the pic_reg_used case, make sure that the got load isn't deleted
10704 when mcount needs it. Blockage to avoid call movement across mcount
10705 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10706 note. */
10711 {
10712 /* vDRAP is setup but after reload it turns out stack realign
10713 isn't necessary, here we will emit prologue to setup DRAP
10714 without stack realign adjustment */
10717 }
10719 /* Prevent instructions from being scheduled into register save push
10720 sequence when access to the redzone area is done through frame pointer.
10721 The offset between the frame pointer and the stack pointer is calculated
10722 relative to the value of the stack pointer at the end of the function
10723 prologue, and moving instructions that access redzone area via frame
10724 pointer inside push sequence violates this assumption. */
10728 /* Emit cld instruction if stringops are used in the function. */
10732 /* SEH requires that the prologue end within 256 bytes of the start of
10733 the function. Prevent instruction schedules that would extend that. */
10736 }
10738 /* Emit code to restore REG using a POP insn. */
10740 static void
10742 {
10751 {
10752 /* Previously we'd represented the CFA as an expression
10753 like *(%ebp - 8). We've just popped that value from
10754 the stack, which means we need to reset the CFA to
10755 the drap register. This will remain until we restore
10756 the stack pointer. */
10760 /* This means that the DRAP register is valid for addressing too. */
10763 }
10766 {
10773 }
10775 /* When the frame pointer is the CFA, and we pop it, we are
10776 swapping back to the stack pointer as the CFA. This happens
10777 for stack frames that don't allocate other data, so we assume
10778 the stack pointer is now pointing at the return address, i.e.
10779 the function entry state, which makes the offset be 1 word. */
10781 {
10784 {
10792 }
10793 }
10794 }
10796 /* Emit code to restore saved registers using POP insns. */
10798 static void
10800 {
10806 }
10808 /* Emit code and notes for the LEAVE instruction. */
10810 static void
10812 {
10824 {
10833 }
10834 }
10836 /* Emit code to restore saved registers using MOV insns.
10837 First register is restored from CFA - CFA_OFFSET. */
10838 static void
10841 {
10847 {
10856 {
10857 /* Previously we'd represented the CFA as an expression
10858 like *(%ebp - 8). We've just popped that value from
10859 the stack, which means we need to reset the CFA to
10860 the drap register. This will remain until we restore
10861 the stack pointer. */
10865 /* This means that the DRAP register is valid for addressing. */
10867 }
10868 else
10872 }
10873 }
10875 /* Emit code to restore saved registers using MOV insns.
10876 First register is restored from CFA - CFA_OFFSET. */
10877 static void
10880 {
10885 {
10887 rtx mem;
10897 }
10898 }
10900 /* Restore function stack, frame, and registers. */
10902 void
10904 {
10915 || (current_function_sp_is_unchanging
10920 /* The FP must be valid if the frame pointer is present. */
10925 /* We must have *some* valid pointer to the stack frame. */
10928 /* The DRAP is never valid at this point. */
10931 /* See the comment about red zone and frame
10932 pointer usage in ix86_expand_prologue. */
10939 /* Determine the CFA offset of the end of the red-zone. */
10942 {
10943 /* The red-zone begins below the return address. */
10946 /* When the register save area is in the aligned portion of
10947 the stack, determine the maximum runtime displacement that
10948 matches up with the aligned frame. */
10952 }
10954 /* Special care must be taken for the normal return case of a function
10955 using eh_return: the eax and edx registers are marked as saved, but
10956 not restored along this path. Adjust the save location to match. */
10960 /* EH_RETURN requires the use of moves to function properly. */
10963 /* SEH requires the use of pops to identify the epilogue. */
10966 /* If we're only restoring one register and sp is not valid then
10967 using a move instruction to restore the register since it's
10968 less work than reloading sp and popping the register. */
10981 && TARGET_USE_LEAVE
10985 else
10989 {
10990 /* Ensure that the entire register save area is addressable via
10991 the stack pointer, if we will restore via sp. */
10996 {
11000 style,
11002 }
11003 }
11005 /* If there are any SSE registers to restore, then we have to do it
11006 via moves, since there's obviously no pop for SSE regs. */
11012 {
11013 rtx t;
11018 /* eh_return epilogues need %ecx added to the stack pointer. */
11020 {
11023 /* Stack align doesn't work with eh_return. */
11025 /* Neither does regparm nested functions. */
11029 {
11037 /* Note that we use SA as a temporary CFA, as the return
11038 address is at the proper place relative to it. We
11039 pretend this happens at the FP restore insn because
11040 prior to this insn the FP would be stored at the wrong
11041 offset relative to SA, and after this insn we have no
11042 other reasonable register to use for the CFA. We don't
11043 bother resetting the CFA to the SP for the duration of
11044 the return insn. */
11057 }
11058 else
11059 {
11067 {
11071 UNITS_PER_WORD));
11073 }
11074 }
11077 }
11078 }
11079 else
11080 {
11081 /* SEH requires that the function end with (1) a stack adjustment
11082 if necessary, (2) a sequence of pops, and (3) a return or
11083 jump instruction. Prevent insns from the function body from
11084 being scheduled into this sequence. */
11086 {
11087 /* Prevent a catch region from being adjacent to the standard
11088 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11089 several other flags that would be interesting to test are
11090 not yet set up. */
11093 else
11095 }
11097 /* First step is to deallocate the stack frame so that we can
11098 pop the registers. */
11100 {
11105 }
11107 {
11111 style,
11113 }
11116 }
11118 /* If we used a stack pointer and haven't already got rid of it,
11119 then do so now. */
11121 {
11122 /* If the stack pointer is valid and pointing at the frame
11123 pointer store address, then we only need a pop. */
11126 /* Leave results in shorter dependency chains on CPUs that are
11127 able to grok it fast. */
11132 else
11133 {
11135 hard_frame_pointer_rtx,
11138 }
11139 }
11142 {
11144 rtx insn;
11170 }
11172 /* At this point the stack pointer must be valid, and we must have
11173 restored all of the registers. We may not have deallocated the
11174 entire stack frame. We've delayed this until now because it may
11175 be possible to merge the local stack deallocation with the
11176 deallocation forced by ix86_static_chain_on_stack. */
11181 {
11185 }
11187 /* Sibcall epilogues don't want a return instruction. */
11189 {
11192 }
11194 /* Emit vzeroupper if needed. */
11201 {
11204 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11205 address, do explicit add, and jump indirectly to the caller. */
11208 {
11210 rtx insn;
11212 /* There is no "pascal" calling convention in any 64bit ABI. */
11228 }
11229 else
11231 }
11232 else
11235 /* Restore the state back to the state from the prologue,
11236 so that it's correct for the next epilogue. */
11238 }
11240 /* Reset from the function's potential modifications. */
11242 static void
11244 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11245 {
11248 #if TARGET_MACHO
11249 /* Mach-O doesn't support labels at the end of objects, so if
11250 it looks like we might want one, insert a NOP. */
11251 {
11262 }
11263 #endif
11265 }
11267 /* Return a scratch register to use in the split stack prologue. The
11268 split stack prologue is used for -fsplit-stack. It is the first
11269 instructions in the function, even before the regular prologue.
11270 The scratch register can be any caller-saved register which is not
11271 used for parameters or for the static chain. */
11273 static unsigned int
11275 {
11278 else
11279 {
11289 {
11291 {
11295 }
11297 }
11299 {
11302 else
11303 {
11305 {
11309 }
11311 }
11312 }
11313 else
11314 {
11315 /* FIXME: We could make this work by pushing a register
11316 around the addition and comparison. */
11319 }
11320 }
11321 }
11323 /* A SYMBOL_REF for the function which allocates new stackspace for
11324 -fsplit-stack. */
11328 /* A SYMBOL_REF for the more stack function when using the large
11329 model. */
11333 /* Handle -fsplit-stack. These are the first instructions in the
11334 function, even before the regular prologue. */
11336 void
11338 {
11340 HOST_WIDE_INT allocate;
11345 rtx fn;
11353 /* This is the label we will branch to if we have enough stack
11354 space. We expect the basic block reordering pass to reverse this
11355 branch if optimizing, so that we branch in the unlikely case. */
11358 /* We need to compare the stack pointer minus the frame size with
11359 the stack boundary in the TCB. The stack boundary always gives
11360 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11361 can compare directly. Otherwise we need to do an addition. */
11364 UNSPEC_STACK_CHECK);
11369 else
11370 {
11372 rtx offset;
11374 /* We need a scratch register to hold the stack pointer minus
11375 the required frame size. Since this is the very start of the
11376 function, the scratch register can be any caller-saved
11377 register which is not used for parameters. */
11384 {
11385 /* We don't use ix86_gen_add3 in this case because it will
11386 want to split to lea, but when not optimizing the insn
11387 will not be split after this point. */
11390 offset)));
11391 }
11392 else
11393 {
11396 stack_pointer_rtx));
11397 }
11399 }
11405 /* Mark the jump as very likely to be taken. */
11413 /* Get more stack space. We pass in the desired stack space and the
11414 size of the arguments to copy to the new stack. In 32-bit mode
11415 we push the parameters; __morestack will return on a new stack
11416 anyhow. In 64-bit mode we pass the parameters in r10 and
11417 r11. */
11422 {
11428 /* If this function uses a static chain, it will be in %r10.
11429 Preserve it across the call to __morestack. */
11431 {
11432 rtx rax;
11437 }
11440 {
11441 HOST_WIDE_INT argval;
11443 /* When using the large model we need to load the address
11444 into a register, and we've run out of registers. So we
11445 switch to a different calling convention, and we call a
11446 different function: __morestack_large. We pass the
11447 argument size in the upper 32 bits of r10 and pass the
11448 frame size in the lower 32 bits. */
11453 split_stack_fn_large =
11457 {
11467 UNSPEC_GOT);
11473 }
11474 else
11481 }
11482 else
11483 {
11487 }
11490 }
11491 else
11492 {
11495 }
11501 /* In order to make call/return prediction work right, we now need
11502 to execute a return instruction. See
11503 libgcc/config/i386/morestack.S for the details on how this works.
11505 For flow purposes gcc must not see this as a return
11506 instruction--we need control flow to continue at the subsequent
11507 label. Therefore, we use an unspec. */
11511 /* If we are in 64-bit mode and this function uses a static chain,
11512 we saved %r10 in %rax before calling _morestack. */
11517 /* If this function calls va_start, we need to store a pointer to
11518 the arguments on the old stack, because they may not have been
11519 all copied to the new stack. At this point the old stack can be
11520 found at the frame pointer value used by __morestack, because
11521 __morestack has set that up before calling back to us. Here we
11522 store that pointer in a scratch register, and in
11523 ix86_expand_prologue we store the scratch register in a stack
11524 slot. */
11526 {
11528 rtx frame_reg;
11535 /* 64-bit:
11536 fp -> old fp value
11537 return address within this function
11538 return address of caller of this function
11539 stack arguments
11540 So we add three words to get to the stack arguments.
11542 32-bit:
11543 fp -> old fp value
11544 return address within this function
11545 first argument to __morestack
11546 second argument to __morestack
11547 return address of caller of this function
11548 stack arguments
11549 So we add five words to get to the stack arguments.
11550 */
11561 }
11566 /* If this function calls va_start, we now have to set the scratch
11567 register for the case where we do not call __morestack. In this
11568 case we need to set it based on the stack pointer. */
11570 {
11577 }
11578 }
11580 /* We may have to tell the dataflow pass that the split stack prologue
11581 is initializing a scratch register. */
11583 static void
11585 {
11587 {
11590 }
11591 }
11592 \f
11593 /* Extract the parts of an RTL expression that is a valid memory address
11594 for an instruction. Return 0 if the structure of the address is
11595 grossly off. Return -1 if the address contains ASHIFT, so it is not
11596 strictly valid, but still used for computing length of lea instruction. */
11598 int
11600 {
11605 rtx tmp;
11612 {
11617 do
11618 {
11623 }
11630 {
11633 {
11656 && TARGET_TLS_DIRECT_SEG_REFS
11659 else
11669 else
11684 }
11685 }
11686 }
11688 {
11691 }
11693 {
11694 /* We're called for lea too, which implements ashift on occasion. */
11704 }
11705 else
11708 /* Extract the integral value of scale. */
11710 {
11714 }
11719 /* Avoid useless 0 displacement. */
11723 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11728 {
11729 rtx tmp;
11732 }
11734 /* Special case: %ebp cannot be encoded as a base without a displacement.
11735 Similarly %r13. */
11737 && base_reg
11746 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11747 Avoid this by transforming to [%esi+0].
11748 Reload calls address legitimization without cfun defined, so we need
11749 to test cfun for being non-NULL. */
11755 /* Special case: encode reg+reg instead of reg*2. */
11759 /* Special case: scaling cannot be encoded without base or displacement. */
11770 }
11771 \f
11772 /* Return cost of the memory address x.
11773 For i386, it is better to use a complex address than let gcc copy
11774 the address into a reg and make a new pseudo. But not if the address
11775 requires to two regs - that would mean more pseudos with longer
11776 lifetimes. */
11777 static int
11779 {
11791 /* Attempt to minimize number of registers in the address. */
11797 cost++;
11804 cost++;
11806 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11807 since it's predecode logic can't detect the length of instructions
11808 and it degenerates to vector decoded. Increase cost of such
11809 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11810 to split such addresses or even refuse such addresses at all.
11812 Following addressing modes are affected:
11813 [base+scale*index]
11814 [scale*index+disp]
11815 [base+index]
11817 The first and last case may be avoidable by explicitly coding the zero in
11818 memory address, but I don't have AMD-K6 machine handy to check this
11819 theory. */
11828 }
11829 \f
11830 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11831 this is used for to form addresses to local data when -fPIC is in
11832 use. */
11834 static bool
11836 {
11839 }
11841 /* Determine if a given RTX is a valid constant. We already know this
11842 satisfies CONSTANT_P. */
11844 bool
11846 {
11848 {
11853 {
11857 }
11862 /* Only some unspecs are valid as "constants". */
11865 {
11881 }
11883 /* We must have drilled down to a symbol. */
11888 /* FALLTHRU */
11891 /* TLS symbols are never valid. */
11895 /* DLLIMPORT symbols are never valid. */
11900 #if TARGET_MACHO
11901 /* mdynamic-no-pic */
11904 #endif
11920 }
11922 /* Otherwise we handle everything else in the move patterns. */
11924 }
11926 /* Determine if it's legal to put X into the constant pool. This
11927 is not possible for the address of thread-local symbols, which
11928 is checked above. */
11930 static bool
11932 {
11933 /* We can always put integral constants and vectors in memory. */
11935 {
11943 }
11945 }
11948 /* Nonzero if the constant value X is a legitimate general operand
11949 when generating PIC code. It is given that flag_pic is on and
11950 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11952 bool
11954 {
11955 rtx inner;
11958 {
11965 /* Only some unspecs are valid as "constants". */
11968 {
11981 }
11982 /* FALLTHRU */
11990 }
11991 }
11993 /* Determine if a given CONST RTX is a valid memory displacement
11994 in PIC mode. */
11996 bool
11998 {
12001 /* In 64bit mode we can allow direct addresses of symbols and labels
12002 when they are not dynamic symbols. */
12004 {
12008 {
12025 /* FALLTHRU */
12028 /* TLS references should always be enclosed in UNSPEC. */
12038 }
12039 }
12045 {
12046 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12047 of GOT tables. We should not need these anyway. */
12059 }
12063 {
12068 }
12077 {
12081 /* We need to check for both symbols and labels because VxWorks loads
12082 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12083 details. */
12087 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12088 While ABI specify also 32bit relocation but we don't produce it in
12089 small PIC model at all. */
12111 }
12114 }
12116 /* Recognizes RTL expressions that are valid memory addresses for an
12117 instruction. The MODE argument is the machine mode for the MEM
12118 expression that wants to use this address.
12120 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12121 convert common non-canonical forms to canonical form so that they will
12122 be recognized. */
12124 static bool
12127 {
12130 HOST_WIDE_INT scale;
12133 /* Decomposition failed. */
12141 /* Validate base register.
12143 Don't allow SUBREG's that span more than a word here. It can lead to spill
12144 failures when the base is one word out of a two word structure, which is
12145 represented internally as a DImode int. */
12148 {
12149 rtx reg;
12158 else
12159 /* Base is not a register. */
12163 /* Base is not in Pmode. */
12168 /* Base is not valid. */
12170 }
12172 /* Validate index register.
12174 Don't allow SUBREG's that span more than a word here -- same as above. */
12177 {
12178 rtx reg;
12187 else
12188 /* Index is not a register. */
12192 /* Index is not in Pmode. */
12197 /* Index is not valid. */
12199 }
12201 /* Validate scale factor. */
12203 {
12205 /* Scale without index. */
12209 /* Scale is not a valid multiplier. */
12211 }
12213 /* Validate displacement. */
12215 {
12220 {
12221 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12222 used. While ABI specify also 32bit relocations, we don't produce
12223 them at all and use IP relative instead. */
12230 /* 64bit address unspec. */
12250 /* Invalid address unspec. */
12252 }
12255 && (flag_pic
12256 || (TARGET_MACHO
12257 #if TARGET_MACHO
12258 && MACHOPIC_INDIRECT
12260 #endif
12261 )))
12262 {
12264 is_legitimate_pic:
12266 {
12267 /* foo@dtpoff(%rX) is ok. */
12274 /* Non-constant pic memory reference. */
12276 }
12279 /* Displacement is an invalid pic construct. */
12281 #if TARGET_MACHO
12283 /* displacment must be referenced via non_lazy_pointer */
12285 #endif
12287 /* This code used to verify that a symbolic pic displacement
12288 includes the pic_offset_table_rtx register.
12290 While this is good idea, unfortunately these constructs may
12291 be created by "adds using lea" optimization for incorrect
12292 code like:
12294 int a;
12295 int foo(int i)
12296 {
12297 return *(&a+i);
12298 }
12300 This code is nonsensical, but results in addressing
12301 GOT table with pic_offset_table_rtx base. We can't
12302 just refuse it easily, since it gets matched by
12303 "addsi3" pattern, that later gets split to lea in the
12304 case output register differs from input. While this
12305 can be handled by separate addsi pattern for this case
12306 that never results in lea, this seems to be easier and
12307 correct fix for crash to disable this test. */
12308 }
12315 /* Displacement is not constant. */
12319 /* Displacement is out of range. */
12321 }
12323 /* Everything looks valid. */
12325 }
12327 /* Determine if a given RTX is a valid constant address. */
12329 bool
12331 {
12333 }
12334 \f
12335 /* Return a unique alias set for the GOT. */
12337 static alias_set_type
12339 {
12344 }
12346 /* Return a legitimate reference for ORIG (an address) using the
12347 register REG. If REG is 0, a new pseudo is generated.
12349 There are two types of references that must be handled:
12351 1. Global data references must load the address from the GOT, via
12352 the PIC reg. An insn is emitted to do this load, and the reg is
12353 returned.
12355 2. Static data references, constant pool addresses, and code labels
12356 compute the address as an offset from the GOT, whose base is in
12357 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12358 differentiate them from global data objects. The returned
12359 address is the PIC reg + an unspec constant.
12361 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12362 reg also appears in the address. */
12364 static rtx
12366 {
12369 rtx base;
12371 #if TARGET_MACHO
12373 {
12376 /* Use the generic Mach-O PIC machinery. */
12378 }
12379 #endif
12386 {
12387 rtx tmpreg;
12388 /* This symbol may be referenced via a displacement from the PIC
12389 base address (@GOTOFF). */
12396 {
12398 UNSPEC_GOTOFF);
12400 }
12401 else
12406 else
12411 {
12415 }
12417 }
12419 {
12420 /* This symbol may be referenced via a displacement from the PIC
12421 base address (@GOTOFF). */
12428 {
12430 UNSPEC_GOTOFF);
12432 }
12433 else
12439 {
12442 }
12443 }
12445 /* We can't use @GOTOFF for text labels on VxWorks;
12446 see gotoff_operand. */
12448 {
12450 {
12456 {
12459 }
12460 }
12462 /* For x64 PE-COFF there is no GOT table. So we use address
12463 directly. */
12465 {
12473 }
12475 {
12483 /* Use directly gen_movsi, otherwise the address is loaded
12484 into register for CSE. We don't want to CSE this addresses,
12485 instead we CSE addresses from the GOT table, so skip this. */
12488 }
12489 else
12490 {
12491 /* This symbol must be referenced via a load from the
12492 Global Offset Table (@GOT). */
12508 }
12509 }
12510 else
12511 {
12514 {
12516 {
12519 }
12520 else
12522 }
12524 {
12527 /* We must match stuff we generate before. Assume the only
12528 unspecs that can get here are ours. Not that we could do
12529 anything with them anyway.... */
12535 }
12537 {
12540 /* Check first to see if this is a constant offset from a @GOTOFF
12541 symbol reference. */
12544 {
12546 {
12550 UNSPEC_GOTOFF);
12556 {
12559 }
12560 }
12561 else
12562 {
12565 {
12569 }
12570 }
12571 }
12572 else
12573 {
12580 else
12581 {
12583 {
12586 }
12588 }
12589 }
12590 }
12591 }
12593 }
12594 \f
12595 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12597 static rtx
12599 {
12611 }
12613 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12614 false if we expect this to be used for a memory address and true if
12615 we expect to load the address into a register. */
12617 static rtx
12619 {
12624 {
12630 {
12640 }
12643 else
12647 {
12651 }
12659 {
12671 }
12674 else
12678 {
12683 }
12691 {
12695 }
12701 {
12703 {
12704 /* The Sun linker took the AMD64 TLS spec literally
12705 and can only handle %rax as destination of the
12706 initial executable code sequence. */
12711 }
12715 }
12717 {
12722 }
12724 {
12728 }
12729 else
12730 {
12733 }
12743 {
12747 }
12748 else
12749 {
12753 }
12763 {
12766 }
12767 else
12768 {
12772 }
12777 }
12780 }
12782 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12783 to symbol DECL. */
12786 htab_t dllimport_map;
12788 static tree
12790 {
12797 tree to;
12798 rtx rtl;
12842 }
12844 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
12845 true if we require the result be a register. */
12847 static rtx
12849 {
12850 tree imp_decl;
12851 rtx x;
12860 }
12862 /* Try machine-dependent ways of modifying an illegitimate address
12863 to be legitimate. If we find one, return the new, valid address.
12864 This macro is used in only one place: `memory_address' in explow.c.
12866 OLDX is the address as it was before break_out_memory_refs was called.
12867 In some cases it is useful to look at this to decide what needs to be done.
12869 It is always safe for this macro to do nothing. It exists to recognize
12870 opportunities to optimize the output.
12872 For the 80386, we handle X+REG by loading X into a register R and
12873 using R+REG. R will go in a general reg and indexing will be used.
12874 However, if REG is a broken-out memory address or multiplication,
12875 nothing needs to be done because REG can certainly go in a general reg.
12877 When -fpic is used, special handling is needed for symbolic references.
12878 See comments by legitimize_pic_address in i386.c for details. */
12880 static rtx
12883 {
12894 {
12898 }
12901 {
12908 {
12911 }
12912 }
12917 #if TARGET_MACHO
12920 #endif
12922 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
12926 {
12931 }
12934 {
12935 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
12940 {
12946 }
12951 {
12957 }
12959 /* Put multiply first if it isn't already. */
12961 {
12966 }
12968 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
12969 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
12970 created by virtual register instantiation, register elimination, and
12971 similar optimizations. */
12973 {
12979 }
12981 /* Canonicalize
12982 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
12983 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
12988 {
12989 rtx constant;
12993 {
12996 }
12998 {
13001 }
13002 else
13006 {
13012 }
13013 }
13019 {
13022 }
13025 {
13028 }
13036 {
13039 }
13045 {
13053 }
13056 {
13064 }
13065 }
13068 }
13069 \f
13070 /* Print an integer constant expression in assembler syntax. Addition
13071 and subtraction are the only arithmetic that may appear in these
13072 expressions. FILE is the stdio stream to write to, X is the rtx, and
13073 CODE is the operand print code from the output string. */
13075 static void
13077 {
13081 {
13090 else
13091 {
13094 /* Mark the decl as referenced so that cgraph will
13095 output the function. */
13099 #if TARGET_MACHO
13103 #endif
13105 }
13113 /* FALLTHRU */
13124 /* This used to output parentheses around the expression,
13125 but that does not work on the 386 (either ATT or BSD assembler). */
13131 {
13132 /* We can use %d if the number is <32 bits and positive. */
13137 else
13139 }
13140 else
13141 /* We can't handle floating point constants;
13142 TARGET_PRINT_OPERAND must handle them. */
13147 /* Some assemblers need integer constants to appear first. */
13149 {
13153 }
13154 else
13155 {
13160 }
13175 {
13179 }
13184 {
13203 /* FIXME: This might be @TPOFF in Sun ld too. */
13212 else
13222 else
13228 #if TARGET_MACHO
13233 #endif
13237 }
13242 }
13243 }
13245 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13246 We need to emit DTP-relative relocations. */
13248 static void ATTRIBUTE_UNUSED
13250 {
13255 {
13263 }
13264 }
13266 /* Return true if X is a representation of the PIC register. This copes
13267 with calls from ix86_find_base_term, where the register might have
13268 been replaced by a cselib value. */
13270 static bool
13272 {
13276 else
13278 }
13280 /* Helper function for ix86_delegitimize_address.
13281 Attempt to delegitimize TLS local-exec accesses. */
13283 static rtx
13285 {
13310 {
13315 }
13321 }
13323 /* In the name of slightly smaller debug output, and to cater to
13324 general assembler lossage, recognize PIC+GOTOFF and turn it back
13325 into a direct symbol reference.
13327 On Darwin, this is necessary to avoid a crash, because Darwin
13328 has a different PIC label for each routine but the DWARF debugging
13329 information is not associated with any particular routine, so it's
13330 necessary to remove references to the PIC label from RTL stored by
13331 the DWARF output code. */
13333 static rtx
13335 {
13337 /* addend is NULL or some rtx if x is something+GOTOFF where
13338 something doesn't include the PIC register. */
13340 /* reg_addend is NULL or a multiple of some register. */
13342 /* const_addend is NULL or a const_int. */
13344 /* This is the result, or NULL. */
13353 {
13362 {
13366 }
13368 }
13375 /* %ebx + GOT/GOTOFF */
13376 ;
13378 {
13379 /* %ebx + %reg * scale + GOT/GOTOFF */
13385 else
13386 {
13389 }
13390 }
13391 else
13397 {
13400 }
13419 {
13420 /* If the rest of original X doesn't involve the PIC register, add
13421 addend and subtract pic_offset_table_rtx. This can happen e.g.
13422 for code like:
13423 leal (%ebx, %ecx, 4), %ecx
13424 ...
13425 movl foo@GOTOFF(%ecx), %edx
13426 in which case we return (%ecx - %ebx) + foo. */
13429 pic_offset_table_rtx),
13430 result);
13431 else
13433 }
13435 {
13439 }
13441 }
13443 /* If X is a machine specific address (i.e. a symbol or label being
13444 referenced as a displacement from the GOT implemented using an
13445 UNSPEC), then return the base term. Otherwise return X. */
13447 rtx
13449 {
13450 rtx term;
13453 {
13467 }
13470 }
13471 \f
13472 static void
13475 {
13479 {
13482 }
13487 {
13490 {
13509 }
13513 {
13532 }
13539 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13540 Those same assemblers have the same but opposite lossage on cmov. */
13545 else
13550 {
13563 }
13571 {
13584 }
13587 /* ??? As above. */
13596 /* ??? As above. */
13601 else
13612 }
13614 }
13616 /* Print the name of register X to FILE based on its machine mode and number.
13617 If CODE is 'w', pretend the mode is HImode.
13618 If CODE is 'b', pretend the mode is QImode.
13619 If CODE is 'k', pretend the mode is SImode.
13620 If CODE is 'q', pretend the mode is DImode.
13621 If CODE is 'x', pretend the mode is V4SFmode.
13622 If CODE is 't', pretend the mode is V8SFmode.
13623 If CODE is 'h', pretend the reg is the 'high' byte register.
13624 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13625 If CODE is 'd', duplicate the operand for AVX instruction.
13626 */
13628 void
13630 {
13645 {
13649 }
13667 else
13670 /* Irritatingly, AMD extended registers use different naming convention
13671 from the normal registers. */
13673 {
13676 {
13695 }
13697 }
13701 {
13704 {
13707 }
13708 /* FALLTHRU */
13714 /* FALLTHRU */
13717 normal:
13732 {
13737 }
13741 }
13745 {
13748 else
13750 }
13751 }
13753 /* Locate some local-dynamic symbol still in use by this function
13754 so that we can print its name in some tls_local_dynamic_base
13755 pattern. */
13757 static int
13759 {
13764 {
13767 }
13770 }
13774 {
13775 rtx insn;
13786 }
13788 /* Meaning of CODE:
13789 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
13790 C -- print opcode suffix for set/cmov insn.
13791 c -- like C, but print reversed condition
13792 F,f -- likewise, but for floating-point.
13793 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
13794 otherwise nothing
13795 R -- print the prefix for register names.
13796 z -- print the opcode suffix for the size of the current operand.
13797 Z -- likewise, with special suffixes for x87 instructions.
13798 * -- print a star (in certain assembler syntax)
13799 A -- print an absolute memory reference.
13800 w -- print the operand as if it's a "word" (HImode) even if it isn't.
13801 s -- print a shift double count, followed by the assemblers argument
13802 delimiter.
13803 b -- print the QImode name of the register for the indicated operand.
13804 %b0 would print %al if operands[0] is reg 0.
13805 w -- likewise, print the HImode name of the register.
13806 k -- likewise, print the SImode name of the register.
13807 q -- likewise, print the DImode name of the register.
13808 x -- likewise, print the V4SFmode name of the register.
13809 t -- likewise, print the V8SFmode name of the register.
13810 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
13811 y -- print "st(0)" instead of "st" as a register.
13812 d -- print duplicated register operand for AVX instruction.
13813 D -- print condition for SSE cmp instruction.
13814 P -- if PIC, print an @PLT suffix.
13815 X -- don't print any sort of PIC '@' suffix for a symbol.
13816 & -- print some in-use local-dynamic symbol name.
13817 H -- print a memory address offset by 8; used for sse high-parts
13818 Y -- print condition for XOP pcom* instruction.
13819 + -- print a branch hint as 'cs' or 'ds' prefix
13820 ; -- print a semicolon (after prefixes due to bug in older gas).
13821 @ -- print a segment register of thread base pointer load
13822 */
13824 void
13826 {
13828 {
13830 {
13837 {
13842 else
13845 }
13849 {
13855 /* Intel syntax. For absolute addresses, registers should not
13856 be surrounded by braces. */
13858 {
13863 }
13868 }
13906 {
13907 /* Opcodes don't get size suffixes if using Intel opcodes. */
13912 {
13930 output_operand_lossage
13933 }
13934 }
13937 warning
13939 /* FALLTHRU */
13942 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
13947 {
13949 {
13951 #ifdef HAVE_AS_IX86_FILDS
13953 #endif
13961 #ifdef HAVE_AS_IX86_FILDQ
13963 #else
13965 #endif
13970 }
13971 }
13973 {
13974 /* 387 opcodes don't get size suffixes
13975 if the operands are registers. */
13980 {
13996 }
13997 }
13998 else
13999 {
14000 output_operand_lossage
14003 }
14005 output_operand_lossage
14024 {
14027 }
14031 /* Little bit of braindamage here. The SSE compare instructions
14032 does use completely different names for the comparisons that the
14033 fp conditional moves. */
14035 {
14037 {
14084 }
14085 }
14086 else
14087 {
14089 {
14124 }
14125 }
14128 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14130 {
14132 {
14139 }
14141 }
14142 #endif
14146 {
14148 "condition code, invalid operand code "
14151 }
14156 {
14158 "condition code, invalid operand code "
14161 }
14162 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14165 #endif
14169 /* Like above, but reverse condition */
14171 /* Check to see if argument to %c is really a constant
14172 and not a condition code which needs to be reversed. */
14174 {
14176 "condition code, invalid operand "
14179 }
14184 {
14186 "condition code, invalid operand "
14189 }
14190 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14193 #endif
14198 /* It doesn't actually matter what mode we use here, as we're
14199 only going to use this for printing. */
14204 {
14205 rtx x;
14213 {
14218 {
14222 /* Emit hints only in the case default branch prediction
14223 heuristics would fail. */
14225 {
14226 /* We use 3e (DS) prefix for taken branches and
14227 2e (CS) prefix for not taken branches. */
14230 else
14232 }
14233 }
14234 }
14236 }
14240 {
14291 }
14295 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14297 #endif
14304 /* The kernel uses a different segment register for performance
14305 reasons; a system call would not have to trash the userspace
14306 segment register, which would be expensive. */
14309 else
14315 }
14316 }
14322 {
14323 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14326 {
14329 {
14338 else
14344 }
14346 /* Check for explicit size override (codes 'b', 'w' and 'k') */
14356 }
14359 /* Avoid (%rip) for call operands. */
14365 else
14367 }
14370 {
14371 REAL_VALUE_TYPE r;
14379 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14382 else
14384 }
14386 /* These float cases don't actually occur as immediate operands. */
14388 {
14393 }
14397 {
14402 }
14404 else
14405 {
14406 /* We have patterns that allow zero sets of memory, for instance.
14407 In 64-bit mode, we should probably support all 8-byte vectors,
14408 since we can in fact encode that into an immediate. */
14410 {
14413 }
14416 {
14418 {
14421 }
14424 {
14427 else
14429 }
14430 }
14435 else
14437 }
14438 }
14440 static bool
14442 {
14445 }
14446 \f
14447 /* Print a memory operand whose address is ADDR. */
14449 static void
14451 {
14465 {
14476 }
14478 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14480 {
14492 }
14494 {
14495 /* Displacement only requires special attention. */
14498 {
14502 }
14505 else
14507 }
14508 else
14509 {
14511 {
14513 {
14518 else
14520 }
14526 {
14531 }
14533 }
14534 else
14535 {
14539 {
14540 /* Pull out the offset of a symbol; print any symbol itself. */
14544 {
14548 }
14556 else
14558 }
14562 {
14565 {
14569 }
14570 }
14573 else
14577 {
14582 }
14584 }
14585 }
14586 }
14588 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14590 static bool
14592 {
14593 rtx op;
14600 {
14603 /* FIXME: This might be @TPOFF in Sun ld. */
14614 else
14626 else
14633 #if TARGET_MACHO
14639 #endif
14642 {
14647 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14649 #else
14651 #endif
14654 }
14659 }
14662 }
14663 \f
14664 /* Split one or more double-mode RTL references into pairs of half-mode
14665 references. The RTL can be REG, offsettable MEM, integer constant, or
14666 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14667 split and "num" is its length. lo_half and hi_half are output arrays
14668 that parallel "operands". */
14670 void
14673 {
14678 {
14687 }
14692 {
14695 /* simplify_subreg refuse to split volatile memory addresses,
14696 but we still have to handle it. */
14698 {
14701 }
14702 else
14703 {
14710 }
14711 }
14712 }
14713 \f
14714 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
14715 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
14716 is the expression of the binary operation. The output may either be
14717 emitted here, or returned to the caller, like all output_* functions.
14719 There is no guarantee that the operands are the same mode, as they
14720 might be within FLOAT or FLOAT_EXTEND expressions. */
14722 #ifndef SYSV386_COMPAT
14723 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
14724 wants to fix the assemblers because that causes incompatibility
14725 with gcc. No-one wants to fix gcc because that causes
14726 incompatibility with assemblers... You can use the option of
14727 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
14728 #define SYSV386_COMPAT 1
14729 #endif
14733 {
14739 #ifdef ENABLE_CHECKING
14740 /* Even if we do not want to check the inputs, this documents input
14741 constraints. Which helps in understanding the following code. */
14751 else
14753 #endif
14756 {
14761 else
14770 else
14779 else
14788 else
14795 }
14798 {
14800 {
14804 else
14806 }
14807 else
14808 {
14812 else
14814 }
14816 }
14820 {
14824 {
14828 }
14830 /* know operands[0] == operands[1]. */
14833 {
14836 }
14839 {
14841 /* How is it that we are storing to a dead operand[2]?
14842 Well, presumably operands[1] is dead too. We can't
14843 store the result to st(0) as st(0) gets popped on this
14844 instruction. Instead store to operands[2] (which I
14845 think has to be st(1)). st(1) will be popped later.
14846 gcc <= 2.8.1 didn't have this check and generated
14847 assembly code that the Unixware assembler rejected. */
14849 else
14852 }
14856 else
14863 {
14866 }
14869 {
14872 }
14875 {
14876 #if SYSV386_COMPAT
14877 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
14878 derived assemblers, confusingly reverse the direction of
14879 the operation for fsub{r} and fdiv{r} when the
14880 destination register is not st(0). The Intel assembler
14881 doesn't have this brain damage. Read !SYSV386_COMPAT to
14882 figure out what the hardware really does. */
14885 else
14887 #else
14889 /* As above for fmul/fadd, we can't store to st(0). */
14891 else
14893 #endif
14895 }
14898 {
14899 #if SYSV386_COMPAT
14902 else
14904 #else
14907 else
14909 #endif
14911 }
14914 {
14917 else
14920 }
14922 {
14923 #if SYSV386_COMPAT
14925 #else
14927 #endif
14928 }
14929 else
14930 {
14931 #if SYSV386_COMPAT
14933 #else
14935 #endif
14936 }
14941 }
14945 }
14947 /* Return needed mode for entity in optimize_mode_switching pass. */
14949 int
14951 {
14954 /* The mode UNINITIALIZED is used to store control word after a
14955 function call or ASM pattern. The mode ANY specify that function
14956 has no requirements on the control word and make no changes in the
14957 bits we are interested in. */
14971 {
14994 }
14997 }
14999 /* Output code to initialize control word copies used by trunc?f?i and
15000 rounding patterns. CURRENT_MODE is set to current control word,
15001 while NEW_MODE is set to new control word. */
15003 void
15005 {
15007 rtx new_mode;
15018 {
15020 {
15022 /* round toward zero (truncate) */
15028 /* round down toward -oo */
15035 /* round up toward +oo */
15042 /* mask precision exception for nearbyint() */
15049 }
15050 }
15051 else
15052 {
15054 {
15056 /* round toward zero (truncate) */
15062 /* round down toward -oo */
15068 /* round up toward +oo */
15074 /* mask precision exception for nearbyint() */
15081 }
15082 }
15088 }
15090 /* Output code for INSN to convert a float to a signed int. OPERANDS
15091 are the insn operands. The output may be [HSD]Imode and the input
15092 operand may be [SDX]Fmode. */
15096 {
15101 /* Jump through a hoop or two for DImode, since the hardware has no
15102 non-popping instruction. We used to do this a different way, but
15103 that was somewhat fragile and broke with post-reload splitters. */
15113 else
15114 {
15119 else
15123 }
15126 }
15128 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15129 have the values zero or one, indicates the ffreep insn's operand
15130 from the OPERANDS array. */
15134 {
15136 #ifdef HAVE_AS_IX86_FFREEP
15138 #else
15139 {
15149 }
15150 #endif
15153 }
15156 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15157 should be used. UNORDERED_P is true when fucom should be used. */
15161 {
15167 {
15170 }
15171 else
15172 {
15175 }
15178 {
15187 else
15189 else
15192 else
15194 }
15201 {
15203 {
15206 }
15207 else
15209 }
15212 && stack_top_dies
15215 {
15216 /* If both the top of the 387 stack dies, and the other operand
15217 is also a stack register that dies, then this must be a
15218 `fcompp' float compare */
15221 {
15222 /* There is no double popping fcomi variant. Fortunately,
15223 eflags is immune from the fstp's cc clobbering. */
15226 else
15229 }
15230 else
15231 {
15234 else
15236 }
15237 }
15238 else
15239 {
15240 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15243 {
15251 NULL,
15252 NULL,
15259 NULL,
15260 NULL,
15261 NULL,
15262 NULL
15263 };
15278 }
15279 }
15281 void
15283 {
15286 #ifdef ASM_QUAD
15289 #else
15291 #endif
15294 }
15296 void
15298 {
15301 #ifdef ASM_QUAD
15304 #else
15306 #endif
15307 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15313 #if TARGET_MACHO
15315 {
15319 }
15320 #endif
15321 else
15324 }
15325 \f
15326 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15327 for the target. */
15329 void
15331 {
15332 rtx tmp;
15334 /* We play register width games, which are only valid after reload. */
15337 /* Avoid HImode and its attendant prefix byte. */
15342 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15344 {
15347 }
15350 }
15352 /* X is an unchanging MEM. If it is a constant pool reference, return
15353 the constant pool rtx, else NULL. */
15355 rtx
15357 {
15364 }
15366 void
15368 {
15376 {
15379 {
15384 }
15388 }
15392 {
15405 {
15411 }
15412 }
15416 {
15418 {
15419 #if TARGET_MACHO
15420 /* dynamic-no-pic */
15422 {
15423 rtx temp = ((reload_in_progress
15431 }
15433 {
15437 }
15440 else
15441 {
15449 }
15450 /* dynamic-no-pic */
15451 #endif
15452 }
15453 else
15454 {
15458 {
15463 }
15464 }
15465 }
15466 else
15467 {
15478 /* Force large constants in 64bit compilation into register
15479 to get them CSEed. */
15491 {
15492 /* If we are loading a floating point constant to a register,
15493 force the value to memory now, since we'll get better code
15494 out the back end. */
15498 {
15503 }
15504 }
15505 }
15508 }
15510 void
15512 {
15516 /* Force constants other than zero into memory. We do not know how
15517 the instructions used to build constants modify the upper 64 bits
15518 of the register, once we have that information we may be able
15519 to handle some of them more efficiently. */
15528 /* We need to check memory alignment for SSE mode since attribute
15529 can make operands unaligned. */
15534 {
15537 /* ix86_expand_vector_move_misalign() does not like constants ... */
15543 /* ... nor both arguments in memory. */
15551 }
15553 /* Make operand1 a register if it isn't already. */
15557 {
15560 }
15563 }
15565 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
15566 straight to ix86_expand_vector_move. */
15567 /* Code generation for scalar reg-reg moves of single and double precision data:
15568 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
15569 movaps reg, reg
15570 else
15571 movss reg, reg
15572 if (x86_sse_partial_reg_dependency == true)
15573 movapd reg, reg
15574 else
15575 movsd reg, reg
15577 Code generation for scalar loads of double precision data:
15578 if (x86_sse_split_regs == true)
15579 movlpd mem, reg (gas syntax)
15580 else
15581 movsd mem, reg
15583 Code generation for unaligned packed loads of single precision data
15584 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
15585 if (x86_sse_unaligned_move_optimal)
15586 movups mem, reg
15588 if (x86_sse_partial_reg_dependency == true)
15589 {
15590 xorps reg, reg
15591 movlps mem, reg
15592 movhps mem+8, reg
15593 }
15594 else
15595 {
15596 movlps mem, reg
15597 movhps mem+8, reg
15598 }
15600 Code generation for unaligned packed loads of double precision data
15601 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
15602 if (x86_sse_unaligned_move_optimal)
15603 movupd mem, reg
15605 if (x86_sse_split_regs == true)
15606 {
15607 movlpd mem, reg
15608 movhpd mem+8, reg
15609 }
15610 else
15611 {
15612 movsd mem, reg
15613 movhpd mem+8, reg
15614 }
15615 */
15617 void
15619 {
15626 {
15628 {
15632 {
15634 /* If we're optimizing for size, movups is the smallest. */
15636 {
15641 }
15653 }
15660 {
15669 {
15674 }
15682 }
15687 }
15690 }
15693 {
15694 /* If we're optimizing for size, movups is the smallest. */
15697 {
15702 }
15704 /* ??? If we have typed data, then it would appear that using
15705 movdqu is the only way to get unaligned data loaded with
15706 integer type. */
15708 {
15713 }
15716 {
15717 rtx zero;
15720 {
15725 }
15727 /* When SSE registers are split into halves, we can avoid
15728 writing to the top half twice. */
15730 {
15733 }
15734 else
15735 {
15736 /* ??? Not sure about the best option for the Intel chips.
15737 The following would seem to satisfy; the register is
15738 entirely cleared, breaking the dependency chain. We
15739 then store to the upper half, with a dependency depth
15740 of one. A rumor has it that Intel recommends two movsd
15741 followed by an unpacklpd, but this is unconfirmed. And
15742 given that the dependency depth of the unpacklpd would
15743 still be one, I'm not sure why this would be better. */
15745 }
15751 }
15752 else
15753 {
15755 {
15760 }
15764 else
15773 }
15774 }
15776 {
15777 /* If we're optimizing for size, movups is the smallest. */
15780 {
15785 }
15787 /* ??? Similar to above, only less clear because of quote
15788 typeless stores unquote. */
15791 {
15796 }
15799 {
15801 {
15805 }
15806 else
15807 {
15812 }
15813 }
15814 else
15815 {
15820 {
15823 }
15824 else
15825 {
15830 }
15831 }
15832 }
15833 else
15835 }
15837 /* Expand a push in MODE. This is some mode for which we do not support
15838 proper push instructions, at least from the registers that we expect
15839 the value to live in. */
15841 void
15843 {
15844 rtx tmp;
15854 /* When we push an operand onto stack, it has to be aligned at least
15855 at the function argument boundary. However since we don't have
15856 the argument type, we can't determine the actual argument
15857 boundary. */
15859 }
15861 /* Helper function of ix86_fixup_binary_operands to canonicalize
15862 operand order. Returns true if the operands should be swapped. */
15864 static bool
15866 rtx operands[])
15867 {
15872 /* If the operation is not commutative, we can't do anything. */
15876 /* Highest priority is that src1 should match dst. */
15882 /* Next highest priority is that immediate constants come second. */
15888 /* Lowest priority is that memory references should come second. */
15895 }
15898 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
15899 destination to use for the operation. If different from the true
15900 destination in operands[0], a copy operation will be required. */
15902 rtx
15904 rtx operands[])
15905 {
15910 /* Canonicalize operand order. */
15912 {
15913 rtx temp;
15915 /* It is invalid to swap operands of different modes. */
15921 }
15923 /* Both source operands cannot be in memory. */
15925 {
15926 /* Optimization: Only read from memory once. */
15928 {
15931 }
15932 else
15934 }
15936 /* If the destination is memory, and we do not have matching source
15937 operands, do things in registers. */
15941 /* Source 1 cannot be a constant. */
15945 /* Source 1 cannot be a non-matching memory. */
15952 }
15954 /* Similarly, but assume that the destination has already been
15955 set up properly. */
15957 void
15960 {
15963 }
15965 /* Attempt to expand a binary operator. Make the expansion closer to the
15966 actual machine, then just general_operand, which will allow 3 separate
15967 memory references (one output, two input) in a single insn. */
15969 void
15971 rtx operands[])
15972 {
15979 /* Emit the instruction. */
15983 {
15984 /* Reload doesn't know about the flags register, and doesn't know that
15985 it doesn't want to clobber it. We can only do this with PLUS. */
15988 }
15992 {
15993 /* This is going to be an LEA; avoid splitting it later. */
15995 }
15996 else
15997 {
16000 }
16002 /* Fix up the destination if needed. */
16005 }
16007 /* Return TRUE or FALSE depending on whether the binary operator meets the
16008 appropriate constraints. */
16010 bool
16013 {
16018 /* Both source operands cannot be in memory. */
16022 /* Canonicalize operand order for commutative operators. */
16024 {
16028 }
16030 /* If the destination is memory, we must have a matching source operand. */
16034 /* Source 1 cannot be a constant. */
16038 /* Source 1 cannot be a non-matching memory. */
16040 {
16041 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16049 }
16052 }
16054 /* Attempt to expand a unary operator. Make the expansion closer to the
16055 actual machine, then just general_operand, which will allow 2 separate
16056 memory references (one output, one input) in a single insn. */
16058 void
16060 rtx operands[])
16061 {
16068 /* If the destination is memory, and we do not have matching source
16069 operands, do things in registers. */
16072 {
16075 else
16077 }
16079 /* When source operand is memory, destination must match. */
16083 /* Emit the instruction. */
16087 {
16088 /* Reload doesn't know about the flags register, and doesn't know that
16089 it doesn't want to clobber it. */
16092 }
16093 else
16094 {
16097 }
16099 /* Fix up the destination if needed. */
16102 }
16104 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16105 divisor are within the the range [0-255]. */
16107 void
16110 {
16119 {
16132 }
16139 /* Use 8bit unsigned divimod if dividend and divisor are within the
16140 the range [0-255]. */
16149 pc_rtx);
16154 /* Generate original signed/unsigned divimod. */
16159 /* Branch to the end. */
16163 /* Generate 8bit unsigned divide. */
16165 /* Don't use operands[0] for result of 8bit divide since not all
16166 registers support QImode ZERO_EXTRACT. */
16173 {
16176 }
16177 else
16178 {
16181 }
16183 /* Extract remainder from AH. */
16187 else
16188 {
16189 /* Need a new scratch register since the old one has result
16190 of 8bit divide. */
16194 }
16197 /* Zero extend quotient from AL. */
16203 }
16205 #define LEA_SEARCH_THRESHOLD 12
16207 /* Search backward for non-agu definition of register number REGNO1
16208 or register number REGNO2 in INSN's basic block until
16209 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16210 2. Reach BB boundary, or
16211 3. Reach agu definition.
16212 Returns the distance between the non-agu definition point and INSN.
16213 If no definition point, returns -1. */
16215 static int
16217 rtx insn)
16218 {
16225 {
16228 {
16230 {
16231 distance++;
16237 {
16241 }
16242 }
16246 }
16247 }
16250 {
16251 edge e;
16252 edge_iterator ei;
16257 {
16260 }
16263 {
16268 {
16270 {
16271 distance++;
16277 {
16281 }
16282 }
16284 }
16285 }
16286 }
16290 done:
16291 /* get_attr_type may modify recog data. We want to make sure
16292 that recog data is valid for instruction INSN, on which
16293 distance_non_agu_define is called. INSN is unchanged here. */
16296 }
16298 /* Return the distance between INSN and the next insn that uses
16299 register number REGNO0 in memory address. Return -1 if no such
16300 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
16302 static int
16304 {
16311 {
16314 {
16316 {
16317 distance++;
16323 {
16324 /* Return DISTANCE if OP0 is used in memory
16325 address in NEXT. */
16327 }
16333 {
16334 /* Return -1 if OP0 is set in NEXT. */
16336 }
16337 }
16341 }
16342 }
16345 {
16346 edge e;
16347 edge_iterator ei;
16352 {
16355 }
16358 {
16363 {
16365 {
16366 distance++;
16372 {
16373 /* Return DISTANCE if OP0 is used in memory
16374 address in NEXT. */
16376 }
16382 {
16383 /* Return -1 if OP0 is set in NEXT. */
16385 }
16387 }
16389 }
16390 }
16391 }
16394 }
16396 /* Define this macro to tune LEA priority vs ADD, it take effect when
16397 there is a dilemma of choicing LEA or ADD
16398 Negative value: ADD is more preferred than LEA
16399 Zero: Netrual
16400 Positive value: LEA is more preferred than ADD*/
16401 #define IX86_LEA_PRIORITY 2
16403 /* Return true if it is ok to optimize an ADD operation to LEA
16404 operation to avoid flag register consumation. For most processors,
16405 ADD is faster than LEA. For the processors like ATOM, if the
16406 destination register of LEA holds an actual address which will be
16407 used soon, LEA is better and otherwise ADD is better. */
16409 bool
16411 {
16416 /* If a = b + c, (a!=b && a!=c), must use lea form. */
16422 else
16423 {
16426 /* Return false if REGNO0 isn't used in memory address. */
16435 /* If this insn has both backward non-agu dependence and forward
16436 agu dependence, the one with short distance take effect. */
16441 }
16442 }
16444 /* Return true if destination reg of SET_BODY is shift count of
16445 USE_BODY. */
16447 static bool
16449 {
16450 rtx set_dest;
16451 rtx shift_rtx;
16454 /* Retrieve destination of SET_BODY. */
16456 {
16465 use_body))
16470 }
16472 /* Retrieve shift count of USE_BODY. */
16474 {
16486 }
16494 {
16497 /* Return true if shift count is dest of SET_BODY. */
16501 }
16504 }
16506 /* Return true if destination reg of SET_INSN is shift count of
16507 USE_INSN. */
16509 bool
16511 {
16514 }
16516 /* Return TRUE or FALSE depending on whether the unary operator meets the
16517 appropriate constraints. */
16519 bool
16523 {
16524 /* If one of operands is memory, source and destination must match. */
16530 }
16532 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
16533 are ok, keeping in mind the possible movddup alternative. */
16535 bool
16537 {
16543 }
16545 /* Post-reload splitter for converting an SF or DFmode value in an
16546 SSE register into an unsigned SImode. */
16548 void
16550 {
16561 /* Load up the value into the low element. We must ensure that the other
16562 elements are valid floats -- zero is the easiest such value. */
16564 {
16567 else
16569 }
16570 else
16571 {
16576 else
16578 }
16598 else
16603 }
16605 /* Convert an unsigned DImode value into a DFmode, using only SSE.
16606 Expects the 64-bit DImode to be supplied in a pair of integral
16607 registers. Requires SSE2; will use SSE3 if available. For x86_32,
16608 -mfpmath=sse, !optimize_size only. */
16610 void
16612 {
16616 rtx x;
16622 {
16625 }
16626 else
16627 {
16631 }
16639 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
16642 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
16643 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
16644 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
16645 (0x1.0p84 + double(fp_value_hi_xmm)).
16646 Note these exponents differ by 32. */
16650 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
16651 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
16660 /* Add the upper and lower DFmode values together. */
16663 else
16664 {
16668 }
16671 }
16673 /* Not used, but eases macroization of patterns. */
16674 void
16676 rtx input ATTRIBUTE_UNUSED)
16677 {
16679 }
16681 /* Convert an unsigned SImode value into a DFmode. Only currently used
16682 for SSE, but applicable anywhere. */
16684 void
16686 {
16687 REAL_VALUE_TYPE TWO31r;
16702 }
16704 /* Convert a signed DImode value into a DFmode. Only used for SSE in
16705 32-bit mode; otherwise we have a direct convert instruction. */
16707 void
16709 {
16710 REAL_VALUE_TYPE TWO32r;
16728 }
16730 /* Convert an unsigned SImode value into a SFmode, using only SSE.
16731 For x86_32, -mfpmath=sse, !optimize_size only. */
16732 void
16734 {
16735 REAL_VALUE_TYPE ONE16r;
16754 }
16756 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
16757 then replicate the value for all elements of the vector
16758 register. */
16760 rtx
16762 {
16763 rtvec v;
16765 {
16780 else
16790 else
16798 else
16806 else
16812 }
16813 }
16815 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
16816 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
16817 for an SSE register. If VECT is true, then replicate the mask for
16818 all elements of the vector register. If INVERT is true, then create
16819 a mask excluding the sign bit. */
16821 rtx
16823 {
16827 rtx v;
16828 rtx mask;
16830 /* Find the sign bit, sign extended to 2*HWI. */
16832 {
16850 else
16858 {
16861 }
16862 else
16863 {
16864 rtvec vec;
16870 {
16873 }
16874 else
16884 }
16889 }
16894 /* Force this value into the low part of a fp vector constant. */
16903 }
16905 /* Generate code for floating point ABS or NEG. */
16907 void
16909 rtx operands[])
16910 {
16921 {
16927 }
16929 /* NEG and ABS performed with SSE use bitwise mask operations.
16930 Create the appropriate mask now. */
16933 else
16943 {
16945 rtvec par;
16950 else
16951 {
16954 }
16956 }
16957 else
16959 }
16961 /* Expand a copysign operation. Special case operand 0 being a constant. */
16963 void
16965 {
16979 else
16983 {
16990 {
16993 else
16994 {
16998 }
16999 }
17009 else
17013 }
17014 else
17015 {
17025 else
17029 }
17030 }
17032 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
17033 be a constant, and so has already been expanded into a vector constant. */
17035 void
17037 {
17053 {
17056 }
17057 }
17059 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
17060 so we have to do two masks. */
17062 void
17064 {
17079 {
17080 /* Shouldn't happen often (it's useless, obviously), but when it does
17081 we'd generate incorrect code if we continue below. */
17084 }
17087 {
17098 }
17099 else
17100 {
17102 {
17104 }
17106 {
17110 }
17114 {
17117 }
17119 {
17124 }
17126 }
17130 }
17132 /* Return TRUE or FALSE depending on whether the first SET in INSN
17133 has source and destination with matching CC modes, and that the
17134 CC mode is at least as constrained as REQ_MODE. */
17136 bool
17138 {
17139 rtx set;
17150 {
17160 /* FALLTHRU */
17164 /* FALLTHRU */
17168 /* FALLTHRU */
17178 }
17181 }
17183 /* Generate insn patterns to do an integer compare of OPERANDS. */
17185 static rtx
17187 {
17194 /* This is very simple, but making the interface the same as in the
17195 FP case makes the rest of the code easier. */
17199 /* Return the test that should be put into the flags user, i.e.
17200 the bcc, scc, or cmov instruction. */
17202 }
17204 /* Figure out whether to use ordered or unordered fp comparisons.
17205 Return the appropriate mode to use. */
17207 enum machine_mode
17209 {
17210 /* ??? In order to make all comparisons reversible, we do all comparisons
17211 non-trapping when compiling for IEEE. Once gcc is able to distinguish
17212 all forms trapping and nontrapping comparisons, we can make inequality
17213 comparisons trapping again, since it results in better code when using
17214 FCOM based compares. */
17216 }
17218 enum machine_mode
17220 {
17224 {
17227 }
17230 {
17231 /* Only zero flag is needed. */
17235 /* Codes needing carry flag. */
17238 /* Detect overflow checks. They need just the carry flag. */
17242 else
17246 /* Detect overflow checks. They need just the carry flag. */
17250 else
17252 /* Codes possibly doable only with sign flag when
17253 comparing against zero. */
17258 else
17259 /* For other cases Carry flag is not required. */
17261 /* Codes doable only with sign flag when comparing
17262 against zero, but we miss jump instruction for it
17263 so we need to use relational tests against overflow
17264 that thus needs to be zero. */
17269 else
17271 /* strcmp pattern do (use flags) and combine may ask us for proper
17272 mode. */
17277 }
17278 }
17280 /* Return the fixed registers used for condition codes. */
17282 static bool
17284 {
17288 }
17290 /* If two condition code modes are compatible, return a condition code
17291 mode which is compatible with both. Otherwise, return
17292 VOIDmode. */
17294 static enum machine_mode
17296 {
17308 {
17322 {
17336 }
17340 /* These are only compatible with themselves, which we already
17341 checked above. */
17343 }
17344 }
17347 /* Return a comparison we can do and that it is equivalent to
17348 swap_condition (code) apart possibly from orderedness.
17349 But, never change orderedness if TARGET_IEEE_FP, returning
17350 UNKNOWN in that case if necessary. */
17352 static enum rtx_code
17354 {
17356 {
17367 }
17368 }
17370 /* Return cost of comparison CODE using the best strategy for performance.
17371 All following functions do use number of instructions as a cost metrics.
17372 In future this should be tweaked to compute bytes for optimize_size and
17373 take into account performance of various instructions on various CPUs. */
17375 static int
17377 {
17380 /* The cost of code using bit-twiddling on %ah. */
17382 {
17405 }
17408 {
17415 }
17416 }
17418 /* Return strategy to use for floating-point. We assume that fcomi is always
17419 preferrable where available, since that is also true when looking at size
17420 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
17422 enum ix86_fpcmp_strategy
17424 {
17425 /* Do fcomi/sahf based test when profitable. */
17434 }
17436 /* Swap, force into registers, or otherwise massage the two operands
17437 to a fp comparison. The operands are updated in place; the new
17438 comparison code is returned. */
17440 static enum rtx_code
17442 {
17448 /* All of the unordered compare instructions only work on registers.
17449 The same is true of the fcomi compare instructions. The XFmode
17450 compare instructions require registers except when comparing
17451 against zero or when converting operand 1 from fixed point to
17452 floating point. */
17461 {
17464 }
17465 else
17466 {
17467 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
17468 things around if they appear profitable, otherwise force op0
17469 into a register. */
17475 {
17478 {
17479 rtx tmp;
17482 }
17483 }
17489 {
17494 {
17497 }
17498 else
17500 }
17501 }
17503 /* Try to rearrange the comparison to make it cheaper. */
17507 {
17508 rtx tmp;
17513 }
17518 }
17520 /* Convert comparison codes we use to represent FP comparison to integer
17521 code that will result in proper branch. Return UNKNOWN if no such code
17522 is available. */
17524 enum rtx_code
17526 {
17528 {
17551 }
17552 }
17554 /* Generate insn patterns to do a floating point compare of OPERANDS. */
17556 static rtx
17558 {
17565 /* Do fcomi/sahf based test when profitable. */
17567 {
17572 tmp);
17580 tmp);
17589 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
17596 /* In the unordered case, we have to check C2 for NaN's, which
17597 doesn't happen to work out to anything nice combination-wise.
17598 So do some bit twiddling on the value we've got in AH to come
17599 up with an appropriate set of condition codes. */
17603 {
17607 {
17610 }
17611 else
17612 {
17618 }
17623 {
17628 }
17629 else
17630 {
17633 }
17638 {
17641 }
17642 else
17643 {
17647 }
17652 {
17658 }
17659 else
17660 {
17663 }
17668 {
17673 }
17674 else
17675 {
17678 }
17683 {
17688 }
17689 else
17690 {
17693 }
17707 }
17712 }
17714 /* Return the test that should be put into the flags user, i.e.
17715 the bcc, scc, or cmov instruction. */
17718 const0_rtx);
17719 }
17721 static rtx
17723 {
17724 rtx ret;
17730 {
17733 }
17734 else
17738 }
17740 void
17742 {
17744 rtx tmp;
17747 {
17754 simple:
17758 pc_rtx);
17766 /* Expand DImode branch into multiple compare+branch. */
17767 {
17773 {
17776 }
17783 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
17784 avoid two branches. This costs one extra insn, so disable when
17785 optimizing for size. */
17790 {
17808 }
17810 /* Otherwise, if we are doing less-than or greater-or-equal-than,
17811 op1 is a constant and the low word is zero, then we can just
17812 examine the high word. Similarly for low word -1 and
17813 less-or-equal-than or greater-than. */
17817 {
17820 {
17823 }
17827 {
17830 }
17834 }
17836 /* Otherwise, we need two or three jumps. */
17845 {
17859 }
17861 /*
17862 * a < b =>
17863 * if (hi(a) < hi(b)) goto true;
17864 * if (hi(a) > hi(b)) goto false;
17865 * if (lo(a) < lo(b)) goto true;
17866 * false:
17867 */
17879 }
17884 }
17885 }
17887 /* Split branch based on floating point condition. */
17888 void
17891 {
17892 rtx condition;
17893 rtx i;
17896 {
17901 }
17904 tmp);
17906 /* Remove pushed operand from stack. */
17916 }
17918 void
17920 {
17921 rtx ret;
17928 }
17930 /* Expand comparison setting or clearing carry flag. Return true when
17931 successful and set pop for the operation. */
17932 static bool
17934 {
17938 /* Do not handle double-mode compares that go through special path. */
17943 {
17948 /* Shortcut: following common codes never translate
17949 into carry flag compares. */
17954 /* These comparisons require zero flag; swap operands so they won't. */
17957 {
17962 }
17964 /* Try to expand the comparison and verify that we end up with
17965 carry flag based comparison. This fails to be true only when
17966 we decide to expand comparison using arithmetic that is not
17967 too common scenario. */
17976 else
17985 }
17991 {
17996 /* Convert a==0 into (unsigned)a<1. */
18005 /* Convert a>b into b<a or a>=b-1. */
18009 {
18011 /* Bail out on overflow. We still can swap operands but that
18012 would force loading of the constant into register. */
18017 }
18018 else
18019 {
18024 }
18027 /* Convert a>=0 into (unsigned)a<0x80000000. */
18045 }
18046 /* Swapping operands may cause constant to appear as first operand. */
18048 {
18052 }
18056 }
18058 bool
18060 {
18079 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
18080 HImode insns, we'd be swallowed in word prefix ops. */
18086 {
18090 HOST_WIDE_INT diff;
18093 /* Sign bit compares are better done using shifts than we do by using
18094 sbb. */
18097 {
18098 /* Detect overlap between destination and compare sources. */
18102 {
18103 rtx flags;
18112 {
18114 compare_code
18116 }
18118 /* To simplify rest of code, restrict to the GEU case. */
18120 {
18126 }
18127 else
18128 {
18131 reverse_condition_maybe_unordered
18133 else
18136 }
18145 else
18148 }
18149 else
18150 {
18153 else
18154 {
18159 }
18161 }
18164 {
18165 /*
18166 * cmpl op0,op1
18167 * sbbl dest,dest
18168 * [addl dest, ct]
18169 *
18170 * Size 5 - 8.
18171 */
18176 }
18178 {
18179 /*
18180 * cmpl op0,op1
18181 * sbbl dest,dest
18182 * orl $ct, dest
18183 *
18184 * Size 8.
18185 */
18189 }
18191 {
18192 /*
18193 * cmpl op0,op1
18194 * sbbl dest,dest
18195 * notl dest
18196 * [addl dest, cf]
18197 *
18198 * Size 8 - 11.
18199 */
18205 }
18206 else
18207 {
18208 /*
18209 * cmpl op0,op1
18210 * sbbl dest,dest
18211 * [notl dest]
18212 * andl cf - ct, dest
18213 * [addl dest, ct]
18214 *
18215 * Size 8 - 11.
18216 */
18219 {
18223 }
18233 }
18239 }
18242 {
18245 HOST_WIDE_INT tmp;
18250 {
18253 /* We may be reversing unordered compare to normal compare, that
18254 is not valid in general (we may convert non-trapping condition
18255 to trapping one), however on i386 we currently emit all
18256 comparisons unordered. */
18259 }
18260 else
18261 {
18264 }
18265 }
18270 {
18275 {
18280 }
18281 }
18283 /* Optimize dest = (op0 < 0) ? -1 : cf. */
18287 {
18288 /* If lea code below could be used, only optimize
18289 if it results in a 2 insn sequence. */
18295 {
18296 /*
18297 * notl op1 (if necessary)
18298 * sarl $31, op1
18299 * orl cf, op1
18300 */
18302 {
18306 }
18317 }
18318 }
18326 {
18327 /*
18328 * xorl dest,dest
18329 * cmpl op1,op2
18330 * setcc dest
18331 * lea cf(dest*(ct-cf)),dest
18332 *
18333 * Size 14.
18334 *
18335 * This also catches the degenerate setcc-only case.
18336 */
18338 rtx tmp;
18344 /* On x86_64 the lea instruction operates on Pmode, so we need
18345 to get arithmetics done in proper mode to match. */
18348 else
18349 {
18350 rtx out1;
18353 nops++;
18355 {
18357 nops++;
18358 }
18359 }
18361 {
18363 nops++;
18364 }
18366 {
18369 else
18371 }
18376 }
18378 /*
18379 * General case: Jumpful:
18380 * xorl dest,dest cmpl op1, op2
18381 * cmpl op1, op2 movl ct, dest
18382 * setcc dest jcc 1f
18383 * decl dest movl cf, dest
18384 * andl (cf-ct),dest 1:
18385 * addl ct,dest
18386 *
18387 * Size 20. Size 14.
18388 *
18389 * This is reasonably steep, but branch mispredict costs are
18390 * high on modern cpus, so consider failing only if optimizing
18391 * for space.
18392 */
18397 {
18399 {
18406 {
18409 /* We may be reversing unordered compare to normal compare,
18410 that is not valid in general (we may convert non-trapping
18411 condition to trapping one), however on i386 we currently
18412 emit all comparisons unordered. */
18414 }
18415 else
18416 {
18420 }
18421 }
18424 {
18425 /* notl op1 (if needed)
18426 sarl $31, op1
18427 andl (cf-ct), op1
18428 addl ct, op1
18430 For x < 0 (resp. x <= -1) there will be no notl,
18431 so if possible swap the constants to get rid of the
18432 complement.
18433 True/false will be -1/0 while code below (store flag
18434 followed by decrement) is 0/-1, so the constants need
18435 to be exchanged once more. */
18438 {
18441 }
18442 else
18443 {
18447 }
18450 }
18451 else
18452 {
18456 constm1_rtx,
18458 }
18470 }
18471 }
18474 {
18475 /* Try a few things more with specific constants and a variable. */
18477 optab op;
18483 /* If one of the two operands is an interesting constant, load a
18484 constant with the above and mask it in with a logical operation. */
18487 {
18493 else
18495 }
18497 {
18503 else
18505 }
18506 else
18513 /* Recurse to get the constant loaded. */
18517 /* Mask in the interesting variable. */
18519 OPTAB_WIDEN);
18524 }
18526 /*
18527 * For comparison with above,
18528 *
18529 * movl cf,dest
18530 * movl ct,tmp
18531 * cmpl op1,op2
18532 * cmovcc tmp,dest
18533 *
18534 * Size 15.
18535 */
18557 }
18559 /* Swap, force into registers, or otherwise massage the two operands
18560 to an sse comparison with a mask result. Thus we differ a bit from
18561 ix86_prepare_fp_compare_args which expects to produce a flags result.
18563 The DEST operand exists to help determine whether to commute commutative
18564 operators. The POP0/POP1 operands are updated in place. The new
18565 comparison code is returned, or UNKNOWN if not implementable. */
18567 static enum rtx_code
18570 {
18571 rtx tmp;
18574 {
18577 /* We have no LTGT as an operator. We could implement it with
18578 NE & ORDERED, but this requires an extra temporary. It's
18579 not clear that it's worth it. */
18586 /* These are supported directly. */
18593 /* For commutative operators, try to canonicalize the destination
18594 operand to be first in the comparison - this helps reload to
18595 avoid extra moves. */
18598 /* FALLTHRU */
18604 /* These are not supported directly. Swap the comparison operands
18605 to transform into something that is supported. */
18614 }
18617 }
18619 /* Detect conditional moves that exactly match min/max operational
18620 semantics. Note that this is IEEE safe, as long as we don't
18621 interchange the operands.
18623 Returns FALSE if this conditional move doesn't match a MIN/MAX,
18624 and TRUE if the operation is successful and instructions are emitted. */
18626 static bool
18629 {
18632 rtx tmp;
18635 ;
18637 {
18641 }
18642 else
18649 else
18654 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
18655 but MODE may be a vector mode and thus not appropriate. */
18657 {
18659 rtvec v;
18664 }
18665 else
18666 {
18669 }
18673 }
18675 /* Expand an sse vector comparison. Return the register with the result. */
18677 static rtx
18680 {
18682 rtx x;
18697 }
18699 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
18700 operations. This is used for both scalar and vector conditional moves. */
18702 static void
18704 {
18709 {
18713 }
18715 {
18720 }
18722 {
18725 op_true,
18726 op_false));
18728 }
18729 else
18730 {
18737 else
18749 }
18750 }
18752 /* Expand a floating-point conditional move. Return true if successful. */
18754 bool
18756 {
18764 {
18767 /* Since we've no cmove for sse registers, don't force bad register
18768 allocation just to gain access to it. Deny movcc when the
18769 comparison mode doesn't match the move mode. */
18788 }
18790 /* The floating point conditional move instructions don't directly
18791 support conditions resulting from a signed integer comparison. */
18795 {
18800 }
18807 }
18809 /* Expand a floating-point vector conditional move; a vcond operation
18810 rather than a movcc operation. */
18812 bool
18814 {
18816 rtx cmp;
18831 }
18833 /* Expand a signed/unsigned integral vector conditional move. */
18835 bool
18837 {
18846 /* XOP supports all of the comparisons on all vector int types. */
18848 {
18849 /* Canonicalize the comparison to EQ, GT, GTU. */
18851 {
18868 /* FALLTHRU */
18878 }
18880 /* Only SSE4.1/SSE4.2 supports V2DImode. */
18882 {
18884 {
18886 /* SSE4.1 supports EQ. */
18893 /* SSE4.2 supports GT/GTU. */
18900 }
18901 }
18903 /* Unsigned parallel compare is not supported by the hardware.
18904 Play some tricks to turn this into a signed comparison
18905 against 0. */
18907 {
18911 {
18914 {
18918 /* Subtract (-(INT MAX) - 1) from both operands to make
18919 them signed. */
18932 }
18937 /* Perform a parallel unsigned saturating subtraction. */
18950 }
18951 }
18952 }
18960 }
18962 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
18963 true if we should do zero extension, else sign extension. HIGH_P is
18964 true if we want the N/2 high elements, else the low elements. */
18966 void
18968 {
18974 {
18978 else
18984 else
18990 else
18995 }
19001 else
19006 }
19008 /* This function performs the same task as ix86_expand_sse_unpack,
19009 but with SSE4.1 instructions. */
19011 void
19013 {
19019 {
19023 else
19029 else
19035 else
19040 }
19044 {
19045 /* Shift higher 8 bytes to lower 8 bytes. */
19050 }
19051 else
19055 }
19057 /* Expand conditional increment or decrement using adb/sbb instructions.
19058 The default case using setcc followed by the conditional move can be
19059 done by generic code. */
19060 bool
19062 {
19064 rtx flags;
19066 rtx compare_op;
19084 {
19087 }
19090 {
19094 reverse_condition_maybe_unordered
19096 else
19098 }
19102 /* Construct either adc or sbb insn. */
19104 {
19106 {
19121 }
19122 }
19123 else
19124 {
19126 {
19141 }
19142 }
19146 }
19149 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
19150 but works for floating pointer parameters and nonoffsetable memories.
19151 For pushes, it returns just stack offsets; the values will be saved
19152 in the right order. Maximally three parts are generated. */
19154 static int
19156 {
19161 else
19167 /* Optimize constant pool reference to immediates. This is used by fp
19168 moves, that force all constants to memory to allow combining. */
19170 {
19174 }
19177 {
19178 /* The only non-offsetable memories we handle are pushes. */
19187 }
19190 {
19192 /* Caution: if we looked through a constant pool memory above,
19193 the operand may actually have a different mode now. That's
19194 ok, since we want to pun this all the way back to an integer. */
19198 }
19201 {
19204 else
19205 {
19209 {
19213 }
19215 {
19220 }
19222 {
19223 REAL_VALUE_TYPE r;
19228 {
19243 }
19246 }
19247 else
19249 }
19250 }
19251 else
19252 {
19256 {
19259 {
19263 }
19265 {
19269 }
19271 {
19272 REAL_VALUE_TYPE r;
19278 /* Do not use shift by 32 to avoid warning on 32bit systems. */
19281 = gen_int_mode
19284 DImode);
19285 else
19292 = gen_int_mode
19295 DImode);
19296 else
19298 }
19299 else
19301 }
19302 }
19305 }
19307 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
19308 Return false when normal moves are needed; true when all required
19309 insns have been emitted. Operands 2-4 contain the input values
19310 int the correct order; operands 5-7 contain the output values. */
19312 void
19314 {
19322 /* The DFmode expanders may ask us to move double.
19323 For 64bit target this is single move. By hiding the fact
19324 here we simplify i386.md splitters. */
19326 {
19327 /* Optimize constant pool reference to immediates. This is used by
19328 fp moves, that force all constants to memory to allow combining. */
19335 {
19338 }
19339 else
19344 }
19346 /* The only non-offsettable memory we handle is push. */
19349 else
19356 /* When emitting push, take care for source operands on the stack. */
19359 {
19362 /* Compensate for the stack decrement by 4. */
19367 /* src_base refers to the stack pointer and is
19368 automatically decreased by emitted push. */
19372 }
19374 /* We need to do copy in the right order in case an address register
19375 of the source overlaps the destination. */
19377 {
19378 rtx tmp;
19381 {
19385 collisions++;
19386 }
19388 /* Collision in the middle part can be handled by reordering. */
19390 {
19393 }
19397 {
19399 {
19402 }
19403 else
19404 {
19407 }
19408 }
19410 /* If there are more collisions, we can't handle it by reordering.
19411 Do an lea to the last part and use only one colliding move. */
19413 {
19414 rtx base;
19420 /* Handle the case when the last part isn't valid for lea.
19421 Happens in 64-bit mode storing the 12-byte XFmode. */
19428 {
19431 }
19432 }
19433 }
19436 {
19438 {
19440 {
19445 }
19447 {
19450 }
19451 }
19452 else
19453 {
19454 /* In 64bit mode we don't have 32bit push available. In case this is
19455 register, it is OK - we will just use larger counterpart. We also
19456 retype memory - these comes from attempt to avoid REX prefix on
19457 moving of second half of TFmode value. */
19459 {
19461 {
19472 }
19476 }
19477 }
19481 }
19483 /* Choose correct order to not overwrite the source before it is copied. */
19493 {
19495 {
19498 }
19499 }
19500 else
19501 {
19503 {
19506 }
19507 }
19509 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
19511 {
19520 }
19526 }
19528 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
19529 left shift by a constant, either using a single shift or
19530 a sequence of add instructions. */
19532 static void
19534 {
19540 {
19544 }
19545 else
19546 {
19549 }
19550 }
19552 void
19554 {
19563 {
19568 {
19574 }
19575 else
19576 {
19584 }
19586 }
19593 {
19594 /* Assuming we've chosen a QImode capable registers, then 1 << N
19595 can be done with two 32/64-bit shifts, no branches, no cmoves. */
19597 {
19613 }
19615 /* Otherwise, we can get the same results by manually performing
19616 a bit extract operation on bit 5/6, and then performing the two
19617 shifts. The two methods of getting 0/1 into low/high are exactly
19618 the same size. Avoiding the shift in the bit extract case helps
19619 pentium4 a bit; no one else seems to care much either way. */
19620 else
19621 {
19626 HOST_WIDE_INT bits;
19627 rtx x;
19630 {
19636 }
19637 else
19638 {
19644 }
19648 else
19656 }
19661 }
19664 {
19665 /* For -1 << N, we can avoid the shld instruction, because we
19666 know that we're shifting 0...31/63 ones into a -1. */
19670 else
19672 }
19673 else
19674 {
19682 }
19687 {
19693 }
19694 else
19695 {
19700 }
19701 }
19703 void
19705 {
19715 {
19720 {
19726 }
19728 {
19737 }
19738 else
19739 {
19747 }
19748 }
19749 else
19750 {
19762 {
19770 scratch));
19771 }
19772 else
19773 {
19778 }
19779 }
19780 }
19782 void
19784 {
19794 {
19799 {
19806 }
19807 else
19808 {
19816 }
19817 }
19818 else
19819 {
19831 {
19837 scratch));
19838 }
19839 else
19840 {
19845 }
19846 }
19847 }
19849 /* Predict just emitted jump instruction to be taken with probability PROB. */
19850 static void
19852 {
19856 }
19858 /* Helper function for the string operations below. Dest VARIABLE whether
19859 it is aligned to VALUE bytes. If true, jump to the label. */
19860 static rtx
19862 {
19867 else
19873 else
19876 }
19878 /* Adjust COUNTER by the VALUE. */
19879 static void
19881 {
19886 }
19888 /* Zero extend possibly SImode EXP to Pmode register. */
19889 rtx
19891 {
19892 rtx r;
19900 }
19902 /* Divide COUNTREG by SCALE. */
19903 static rtx
19905 {
19906 rtx sc;
19918 }
19920 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
19921 DImode for constant loop counts. */
19923 static enum machine_mode
19925 {
19933 }
19935 /* When SRCPTR is non-NULL, output simple loop to move memory
19936 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
19937 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
19938 equivalent loop to set memory by VALUE (supposed to be in MODE).
19940 The size is rounded down to whole number of chunk size moved at once.
19941 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
19944 static void
19949 {
19954 rtx size;
19955 rtx x_addr;
19956 rtx y_addr;
19965 /* Those two should combine. */
19967 {
19971 }
19981 {
19985 /* When unrolling for chips that reorder memory reads and writes,
19986 we can save registers by using single temporary.
19987 Also using 4 temporaries is overkill in 32bit mode. */
19989 {
19991 {
19993 {
19994 destmem =
19996 srcmem =
19998 }
20000 }
20001 }
20002 else
20003 {
20007 {
20010 {
20011 srcmem =
20013 }
20015 }
20017 {
20019 {
20020 destmem =
20022 }
20024 }
20025 }
20026 }
20027 else
20029 {
20031 destmem =
20034 }
20044 {
20050 else
20052 }
20053 else
20061 {
20066 }
20068 }
20070 /* Output "rep; mov" instruction.
20071 Arguments have same meaning as for previous function */
20072 static void
20075 rtx count,
20077 {
20078 rtx destexp;
20079 rtx srcexp;
20080 rtx countreg;
20082 /* If the size is known, it is shorter to use rep movs. */
20093 {
20100 }
20101 else
20102 {
20105 }
20107 {
20114 }
20115 else
20116 {
20121 }
20124 }
20126 /* Output "rep; stos" instruction.
20127 Arguments have same meaning as for previous function */
20128 static void
20131 rtx orig_value)
20132 {
20133 rtx destexp;
20134 rtx countreg;
20141 {
20145 }
20146 else
20149 {
20154 }
20158 }
20160 static void
20163 {
20167 }
20169 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
20170 static void
20173 {
20176 {
20181 {
20183 {
20186 }
20187 else
20190 }
20192 {
20195 else
20196 {
20199 }
20201 }
20203 {
20206 }
20208 {
20211 }
20213 {
20216 }
20218 }
20220 {
20226 }
20228 /* When there are stringops, we can cheaply increase dest and src pointers.
20229 Otherwise we save code size by maintaining offset (zero is readily
20230 available from preceding rep operation) and using x86 addressing modes.
20231 */
20233 {
20235 {
20242 }
20244 {
20251 }
20253 {
20260 }
20261 }
20262 else
20263 {
20265 rtx tmp;
20268 {
20279 }
20281 {
20294 }
20296 {
20305 }
20306 }
20307 }
20309 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20310 static void
20313 {
20314 count =
20320 }
20322 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20323 static void
20325 {
20326 rtx dest;
20329 {
20334 {
20336 {
20341 }
20342 else
20345 }
20347 {
20349 {
20352 }
20353 else
20354 {
20359 }
20361 }
20363 {
20367 }
20369 {
20373 }
20375 {
20379 }
20381 }
20383 {
20386 }
20388 {
20391 {
20395 }
20396 else
20397 {
20403 }
20406 }
20408 {
20411 {
20414 }
20415 else
20416 {
20420 }
20423 }
20425 {
20431 }
20433 {
20439 }
20441 {
20447 }
20448 }
20450 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
20451 DESIRED_ALIGNMENT. */
20452 static void
20456 {
20458 {
20466 }
20468 {
20476 }
20478 {
20486 }
20488 }
20490 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
20491 ALIGN_BYTES is how many bytes need to be copied. */
20492 static rtx
20495 {
20505 {
20510 }
20512 {
20523 }
20525 {
20531 {
20539 }
20542 }
20548 {
20560 }
20567 }
20569 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
20570 DESIRED_ALIGNMENT. */
20571 static void
20574 {
20576 {
20583 }
20585 {
20592 }
20594 {
20601 }
20603 }
20605 /* Set enough from DST to align DST known to by aligned by ALIGN to
20606 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
20607 static rtx
20610 {
20614 {
20619 }
20621 {
20628 }
20630 {
20637 }
20644 }
20646 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
20647 static enum stringop_alg
20650 {
20653 /* Algorithms using the rep prefix want at least edi and ecx;
20654 additionally, memset wants eax and memcpy wants esi. Don't
20655 consider such algorithms if the user has appropriated those
20656 registers for their own purposes. */
20658 || (memset
20661 #define ALG_USABLE_P(alg) (rep_prefix_usable \
20662 || (alg != rep_prefix_1_byte \
20663 && alg != rep_prefix_4_byte \
20664 && alg != rep_prefix_8_byte))
20667 /* Even if the string operation call is cold, we still might spend a lot
20668 of time processing large blocks. */
20673 else
20681 else
20685 /* rep; movq or rep; movl is the smallest variant. */
20687 {
20690 else
20692 }
20693 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
20694 */
20698 {
20702 {
20703 /* We get here if the algorithms that were not libcall-based
20704 were rep-prefix based and we are unable to use rep prefixes
20705 based on global register usage. Break out of the loop and
20706 use the heuristic below. */
20710 {
20715 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
20716 last non-libcall inline algorithm. */
20718 {
20719 /* When the current size is best to be copied by a libcall,
20720 but we are still forced to inline, run the heuristic below
20721 that will pick code for medium sized blocks. */
20725 }
20728 }
20729 }
20731 }
20732 /* When asked to inline the call anyway, try to pick meaningful choice.
20733 We look for maximal size of block that is faster to copy by hand and
20734 take blocks of at most of that size guessing that average size will
20735 be roughly half of the block.
20737 If this turns out to be bad, we might simply specify the preferred
20738 choice in ix86_costs. */
20741 {
20748 {
20755 }
20756 /* If there aren't any usable algorithms, then recursing on
20757 smaller sizes isn't going to find anything. Just return the
20758 simple byte-at-a-time copy loop. */
20760 {
20761 /* Pick something reasonable. */
20765 }
20774 }
20776 #undef ALG_USABLE_P
20777 }
20779 /* Decide on alignment. We know that the operand is already aligned to ALIGN
20780 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
20781 static int
20785 {
20788 {
20799 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20800 copying whole cacheline at once. */
20803 else
20807 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20808 copying whole cacheline at once. */
20811 else
20819 }
20828 }
20830 /* Return the smallest power of 2 greater than VAL. */
20831 static int
20833 {
20838 }
20840 /* Expand string move (memcpy) operation. Use i386 string operations when
20841 profitable. expand_setmem contains similar code. The code depends upon
20842 architecture, block size and alignment, but always has the same
20843 overall structure:
20845 1) Prologue guard: Conditional that jumps up to epilogues for small
20846 blocks that can be handled by epilogue alone. This is faster but
20847 also needed for correctness, since prologue assume the block is larger
20848 than the desired alignment.
20850 Optional dynamic check for size and libcall for large
20851 blocks is emitted here too, with -minline-stringops-dynamically.
20853 2) Prologue: copy first few bytes in order to get destination aligned
20854 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
20855 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
20856 We emit either a jump tree on power of two sized blocks, or a byte loop.
20858 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
20859 with specified algorithm.
20861 4) Epilogue: code copying tail of the block that is too small to be
20862 handled by main body (or up to size guarded by prologue guard). */
20864 bool
20867 {
20868 rtx destreg;
20869 rtx srcreg;
20871 rtx tmp;
20884 /* i386 can do misaligned access on reasonably increased cost. */
20888 /* ALIGN is the minimum of destination and source alignment, but we care here
20889 just about destination alignment. */
20898 /* Make sure we don't need to care about overflow later on. */
20902 /* Step 0: Decide on preferred algorithm, desired alignment and
20903 size of chunks to be copied by main loop. */
20919 {
20944 }
20948 /* Step 1: Prologue guard. */
20950 /* Alignment code needs count to be in register. */
20952 {
20955 {
20956 align_bytes
20960 else
20962 }
20965 }
20968 /* Ensure that alignment prologue won't copy past end of block. */
20970 {
20972 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
20973 Make sure it is power of 2. */
20977 {
20979 {
20980 /* If main algorithm works on QImode, no epilogue is needed.
20981 For small sizes just don't align anything. */
20984 else
20986 }
20987 }
20988 else
20989 {
20996 else
20998 }
20999 }
21001 /* Emit code to decide on runtime whether library call or inline should be
21002 used. */
21004 {
21006 {
21008 {
21012 }
21013 }
21014 else
21015 {
21024 }
21025 }
21027 /* Step 2: Alignment prologue. */
21030 {
21032 {
21033 /* Except for the first move in epilogue, we no longer know
21034 constant offset in aliasing info. It don't seems to worth
21035 the pain to maintain it for the first move, so throw away
21036 the info early. */
21040 desired_align);
21041 }
21042 else
21043 {
21044 /* If we know how many bytes need to be stored before dst is
21045 sufficiently aligned, maintain aliasing info accurately. */
21050 }
21056 {
21057 /* It is possible that we copied enough so the main loop will not
21058 execute. */
21068 else
21070 }
21071 }
21073 {
21078 }
21082 /* Step 3: Main loop. */
21085 {
21098 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
21099 registers for 4 temporaries anyway. */
21102 expected_size);
21106 DImode);
21110 SImode);
21114 QImode);
21116 }
21117 /* Adjust properly the offset of src and dest memory for aliasing. */
21119 {
21124 }
21125 else
21126 {
21129 }
21131 /* Step 4: Epilogue to copy the remaining bytes. */
21132 epilogue:
21134 {
21135 /* When the main loop is done, COUNT_EXP might hold original count,
21136 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
21137 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
21138 bytes. Compensate if needed. */
21141 {
21142 tmp =
21145 OPTAB_DIRECT);
21148 }
21151 }
21155 epilogue_size_needed);
21159 }
21161 /* Helper function for memcpy. For QImode value 0xXY produce
21162 0xXYXYXYXY of wide specified by MODE. This is essentially
21163 a * 0x10101010, but we can do slightly better than
21164 synth_mult by unwinding the sequence by hand on CPUs with
21165 slow multiply. */
21166 static rtx
21168 {
21170 rtx tmp;
21177 {
21185 }
21194 nops--;
21199 {
21203 OPTAB_DIRECT);
21204 }
21205 else
21206 {
21212 else
21214 else
21215 {
21218 reg =
21220 }
21230 }
21231 }
21233 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
21234 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
21235 alignment from ALIGN to DESIRED_ALIGN. */
21236 static rtx
21238 {
21239 rtx promoted_val;
21248 else
21252 }
21254 /* Expand string clear operation (bzero). Use i386 string operations when
21255 profitable. See expand_movmem comment for explanation of individual
21256 steps performed. */
21257 bool
21260 {
21261 rtx destreg;
21263 rtx tmp;
21278 /* i386 can do misaligned access on reasonably increased cost. */
21287 /* Make sure we don't need to care about overflow later on. */
21291 /* Step 0: Decide on preferred algorithm, desired alignment and
21292 size of chunks to be copied by main loop. */
21307 {
21332 }
21335 /* Step 1: Prologue guard. */
21337 /* Alignment code needs count to be in register. */
21339 {
21342 {
21343 align_bytes
21347 else
21349 }
21351 {
21356 }
21357 }
21358 /* Do the cheap promotion to allow better CSE across the
21359 main loop and epilogue (ie one load of the big constant in the
21360 front of all code. */
21364 /* Ensure that alignment prologue won't copy past end of block. */
21366 {
21368 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
21369 Make sure it is power of 2. */
21372 /* To improve performance of small blocks, we jump around the VAL
21373 promoting mode. This mean that if the promoted VAL is not constant,
21374 we might not use it in the epilogue and have to use byte
21375 loop variant. */
21379 {
21381 {
21382 /* If main algorithm works on QImode, no epilogue is needed.
21383 For small sizes just don't align anything. */
21386 else
21388 }
21389 }
21390 else
21391 {
21398 else
21400 }
21401 }
21403 {
21412 }
21414 /* Step 2: Alignment prologue. */
21416 /* Do the expensive promotion once we branched off the small blocks. */
21423 {
21425 {
21426 /* Except for the first move in epilogue, we no longer know
21427 constant offset in aliasing info. It don't seems to worth
21428 the pain to maintain it for the first move, so throw away
21429 the info early. */
21432 desired_align);
21433 }
21434 else
21435 {
21436 /* If we know how many bytes need to be stored before dst is
21437 sufficiently aligned, maintain aliasing info accurately. */
21442 }
21448 {
21449 /* It is possible that we copied enough so the main loop will not
21450 execute. */
21460 else
21462 }
21463 }
21465 {
21471 }
21475 /* Step 3: Main loop. */
21478 {
21506 }
21507 /* Adjust properly the offset of src and dest memory for aliasing. */
21511 else
21514 /* Step 4: Epilogue to copy the remaining bytes. */
21517 {
21518 /* When the main loop is done, COUNT_EXP might hold original count,
21519 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
21520 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
21521 bytes. Compensate if needed. */
21524 {
21525 tmp =
21528 OPTAB_DIRECT);
21531 }
21534 }
21535 epilogue:
21537 {
21540 epilogue_size_needed);
21541 else
21543 epilogue_size_needed);
21544 }
21548 }
21550 /* Expand the appropriate insns for doing strlen if not just doing
21551 repnz; scasb
21553 out = result, initialized with the start address
21554 align_rtx = alignment of the address.
21555 scratch = scratch register, initialized with the startaddress when
21556 not aligned, otherwise undefined
21558 This is just the body. It needs the initializations mentioned above and
21559 some address computing at the end. These things are done in i386.md. */
21561 static void
21563 {
21565 rtx tmp;
21570 rtx mem;
21573 rtx cmp;
21579 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
21581 /* Is there a known alignment and is it less than 4? */
21583 {
21586 /* Is there a known alignment and is it not 2? */
21588 {
21592 /* Leave just the 3 lower bits. */
21602 }
21603 else
21604 {
21605 /* Since the alignment is 2, we have to check 2 or 0 bytes;
21606 check if is aligned to 4 - byte. */
21613 }
21617 /* Now compare the bytes. */
21619 /* Compare the first n unaligned byte on a byte per byte basis. */
21623 /* Increment the address. */
21626 /* Not needed with an alignment of 2 */
21628 {
21632 end_0_label);
21637 }
21640 end_0_label);
21643 }
21645 /* Generate loop to check 4 bytes at a time. It is not a good idea to
21646 align this loop. It gives only huge programs, but does not help to
21647 speed up. */
21654 /* This formula yields a nonzero result iff one of the bytes is zero.
21655 This saves three branches inside loop and many cycles. */
21663 align_4_label);
21666 {
21672 /* If zero is not in the first two bytes, move two bytes forward. */
21678 reg,
21679 tmpreg)));
21680 /* Emit lea manually to avoid clobbering of flags. */
21688 reg2,
21689 out)));
21690 }
21691 else
21692 {
21694 /* Is zero in the first two bytes? */
21701 pc_rtx);
21705 /* Not in the first two. Move two bytes forward. */
21711 }
21713 /* Avoid branch in fixing the byte. */
21721 }
21723 /* Expand strlen. */
21725 bool
21727 {
21730 /* The generic case of strlen expander is long. Avoid it's
21731 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
21734 && !TARGET_INLINE_ALL_STRINGOPS
21744 {
21745 /* Well it seems that some optimizer does not combine a call like
21746 foo(strlen(bar), strlen(bar));
21747 when the move and the subtraction is done here. It does calculate
21748 the length just once when these instructions are done inside of
21749 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
21750 often used and I use one fewer register for the lifetime of
21751 output_strlen_unroll() this is better. */
21757 /* strlensi_unroll_1 returns the address of the zero at the end of
21758 the string, like memchr(), so compute the length by subtracting
21759 the start address. */
21761 }
21762 else
21763 {
21764 rtx unspec;
21766 /* Can't use this if the user has appropriated eax, ecx, or edi. */
21779 /* If .md starts supporting :P, this can be done in .md. */
21785 }
21787 }
21789 /* For given symbol (function) construct code to compute address of it's PLT
21790 entry in large x86-64 PIC model. */
21791 rtx
21793 {
21803 }
21805 rtx
21807 rtx callarg2,
21809 {
21817 {
21818 #if TARGET_MACHO
21821 #endif
21822 }
21823 else
21824 {
21825 /* Static functions and indirect calls don't need the pic register. */
21830 }
21833 {
21837 }
21847 {
21850 }
21856 {
21860 }
21864 {
21865 /* We need to represent that SI and DI registers are clobbered
21866 by SYSV calls. */
21872 };
21876 UNSPEC_MS_TO_SYSV_CALL);
21883 gen_rtx_REG
21891 }
21893 /* Add UNSPEC_CALL_NEEDS_VZEROUPPER decoration. */
21895 {
21896 rtx unspec;
21900 {
21903 else
21905 }
21908 else
21913 else
21914 {
21917 UNSPEC_CALL_NEEDS_VZEROUPPER);
21920 }
21921 }
21928 }
21930 void
21932 {
21936 }
21938 /* Output the assembly for a call instruction. */
21942 {
21949 {
21952 /* SEH epilogue detection requires the indirect branch case
21953 to include REX.W. */
21956 else
21958 }
21960 /* SEH unwinding can require an extra nop to be emitted in several
21961 circumstances. Determine if we have one of those. */
21963 {
21964 rtx i;
21967 {
21968 /* If we get to another real insn, we don't need the nop. */
21972 /* If we get to the epilogue note, prevent a catch region from
21973 being adjacent to the standard epilogue sequence. If non-
21974 call-exceptions, we'll have done this during epilogue emission. */
21976 && !flag_non_call_exceptions
21978 {
21981 }
21982 }
21984 /* If we didn't find a real insn following the call, prevent the
21985 unwinder from looking into the next function. */
21988 }
21991 {
21994 else
21996 }
21997 else
21998 {
22001 else
22003 }
22004 }
22005 \f
22006 /* Clear stack slot assignments remembered from previous functions.
22007 This is called from INIT_EXPANDERS once before RTL is emitted for each
22008 function. */
22012 {
22021 }
22023 /* Return a MEM corresponding to a stack slot with mode MODE.
22024 Allocate a new slot if necessary.
22026 The RTL for a function can have several slots available: N is
22027 which slot to use. */
22029 rtx
22031 {
22036 /* Virtual slot is valid only before vregs are instantiated. */
22051 }
22053 /* Construct the SYMBOL_REF for the tls_get_addr function. */
22056 rtx
22058 {
22061 {
22063 (TARGET_ANY_GNU_TLS
22067 }
22070 }
22072 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
22075 rtx
22077 {
22080 {
22085 }
22088 }
22089 \f
22090 /* Calculate the length of the memory address in the instruction
22091 encoding. Does not include the one-byte modrm, opcode, or prefix. */
22093 int
22095 {
22120 /* Rule of thumb:
22121 - esp as the base always wants an index,
22122 - ebp as the base always wants a displacement,
22123 - r12 as the base always wants an index,
22124 - r13 as the base always wants a displacement. */
22126 /* Register Indirect. */
22128 {
22129 /* esp (for its index) and ebp (for its displacement) need
22130 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
22131 code. */
22140 }
22142 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
22143 is not disp32, but disp32(%rip), so for disp32
22144 SIB byte is needed, unless print_operand_address
22145 optimizes it into disp32(%rip) or (%rip) is implied
22146 by UNSPEC. */
22148 {
22151 {
22168 }
22169 }
22171 else
22172 {
22173 /* Find the length of the displacement constant. */
22175 {
22178 else
22180 }
22181 /* ebp always wants a displacement. Similarly r13. */
22186 /* An index requires the two-byte modrm form.... */
22188 /* ...like esp (or r12), which always wants an index. */
22194 }
22197 {
22204 }
22207 }
22209 /* Compute default value for "length_immediate" attribute. When SHORTFORM
22210 is set, expect that insn have 8bit immediate alternative. */
22211 int
22213 {
22219 {
22224 {
22227 {
22239 }
22241 {
22244 }
22245 }
22247 {
22257 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
22263 }
22264 }
22266 }
22267 /* Compute default value for "length_address" attribute. */
22268 int
22270 {
22274 {
22284 {
22289 }
22292 }
22297 {
22300 {
22305 constraints++;
22308 ;
22309 /* Skip ignored operands. */
22312 }
22314 }
22316 }
22318 /* Compute default value for "length_vex" attribute. It includes
22319 2 or 3 byte VEX prefix and 1 opcode byte. */
22321 int
22324 {
22327 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
22328 byte VEX prefix. */
22332 /* We can always use 2 byte VEX prefix in 32bit. */
22340 {
22341 /* REX.W bit uses 3 byte VEX prefix. */
22345 }
22346 else
22347 {
22348 /* REX.X or REX.B bits use 3 byte VEX prefix. */
22352 }
22355 }
22356 \f
22357 /* Return the maximum number of instructions a cpu can issue. */
22359 static int
22361 {
22363 {
22387 }
22388 }
22390 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
22391 by DEP_INSN and nothing set by DEP_INSN. */
22393 static int
22395 {
22398 /* Simplify the test for uninteresting insns. */
22406 {
22409 }
22414 {
22417 }
22418 else
22424 /* This test is true if the dependent insn reads the flags but
22425 not any other potentially set register. */
22433 }
22435 /* Return true iff USE_INSN has a memory address with operands set by
22436 SET_INSN. */
22438 bool
22440 {
22445 {
22448 }
22450 }
22452 static int
22454 {
22460 /* Anti and output dependencies have zero cost on all CPUs. */
22466 /* If we can't recognize the insns, we can't really do anything. */
22474 {
22476 /* Address Generation Interlock adds a cycle of latency. */
22478 {
22489 }
22493 /* ??? Compares pair with jump/setcc. */
22497 /* Floating point stores require value to be ready one cycle earlier. */
22507 /* INT->FP conversion is expensive. */
22511 /* There is one cycle extra latency between an FP op and a store. */
22519 /* Show ability of reorder buffer to hide latency of load by executing
22520 in parallel with previous instruction in case
22521 previous instruction is not needed to compute the address. */
22524 {
22525 /* Claim moves to take one cycle, as core can issue one load
22526 at time and the next load can start cycle later. */
22531 cost--;
22532 }
22538 /* The esp dependency is resolved before the instruction is really
22539 finished. */
22544 /* INT->FP conversion is expensive. */
22548 /* Show ability of reorder buffer to hide latency of load by executing
22549 in parallel with previous instruction in case
22550 previous instruction is not needed to compute the address. */
22553 {
22554 /* Claim moves to take one cycle, as core can issue one load
22555 at time and the next load can start cycle later. */
22561 else
22563 }
22576 /* Show ability of reorder buffer to hide latency of load by executing
22577 in parallel with previous instruction in case
22578 previous instruction is not needed to compute the address. */
22581 {
22585 /* Because of the difference between the length of integer and
22586 floating unit pipeline preparation stages, the memory operands
22587 for floating point are cheaper.
22589 ??? For Athlon it the difference is most probably 2. */
22592 else
22597 else
22599 }
22603 }
22606 }
22608 /* How many alternative schedules to try. This should be as wide as the
22609 scheduling freedom in the DFA, but no wider. Making this value too
22610 large results extra work for the scheduler. */
22612 static int
22614 {
22616 {
22628 /* Generally, we want haifa-sched:max_issue() to look ahead as far
22629 as many instructions can be executed on a cycle, i.e.,
22630 issue_rate. I wonder why tuning for many CPUs does not do this. */
22635 }
22636 }
22638 \f
22640 /* Model decoder of Core 2/i7.
22641 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
22642 track the instruction fetch block boundaries and make sure that long
22643 (9+ bytes) instructions are assigned to D0. */
22645 /* Maximum length of an insn that can be handled by
22646 a secondary decoder unit. '8' for Core 2/i7. */
22649 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
22650 '16' for Core 2/i7. */
22653 /* Maximum number of instructions decoder can handle per cycle.
22654 '6' for Core 2/i7. */
22658 ix86_first_cycle_multipass_data_t;
22660 const_ix86_first_cycle_multipass_data_t;
22662 /* A variable to store target state across calls to max_issue within
22663 one cycle. */
22667 /* Initialize DATA. */
22668 static void
22670 {
22671 ix86_first_cycle_multipass_data_t data
22678 }
22680 /* Advancing the cycle; reset ifetch block counts. */
22681 static void
22683 {
22690 }
22694 /* Filter out insns from ready_try that the core will not be able to issue
22695 on current cycle due to decoder. */
22696 static void
22697 core2i7_first_cycle_multipass_filter_ready_try
22700 {
22702 {
22703 rtx insn;
22713 (!first_cycle_insn_p
22715 /* ... or it would not fit into the ifetch block ... */
22717 /* ... or the decoder is full already ... */
22719 /* ... mask the insn out. */
22720 {
22725 }
22726 }
22727 }
22729 /* Prepare for a new round of multipass lookahead scheduling. */
22730 static void
22733 {
22734 ix86_first_cycle_multipass_data_t data
22736 const_ix86_first_cycle_multipass_data_t prev_data
22739 /* Restore the state from the end of the previous round. */
22743 /* Filter instructions that cannot be issued on current cycle due to
22744 decoder restrictions. */
22746 first_cycle_insn_p);
22747 }
22749 /* INSN is being issued in current solution. Account for its impact on
22750 the decoder model. */
22751 static void
22754 {
22755 ix86_first_cycle_multipass_data_t data
22757 const_ix86_first_cycle_multipass_data_t prev_data
22767 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
22769 {
22772 }
22774 {
22778 }
22781 /* Filter out insns from ready_try that the core will not be able to issue
22782 on current cycle due to decoder. */
22785 }
22787 /* Revert the effect on ready_try. */
22788 static void
22792 {
22793 const_ix86_first_cycle_multipass_data_t data
22796 sbitmap_iterator sbi;
22800 {
22802 }
22803 }
22805 /* Save the result of multipass lookahead scheduling for the next round. */
22806 static void
22808 {
22809 const_ix86_first_cycle_multipass_data_t data
22811 ix86_first_cycle_multipass_data_t next_data
22815 {
22818 }
22819 }
22821 /* Deallocate target data. */
22822 static void
22824 {
22825 ix86_first_cycle_multipass_data_t data
22829 {
22833 }
22834 }
22836 /* Prepare for scheduling pass. */
22837 static void
22841 {
22842 /* Install scheduling hooks for current CPU. Some of these hooks are used
22843 in time-critical parts of the scheduler, so we only set them up when
22844 they are actually used. */
22846 {
22866 /* Set decoder parameters. */
22881 }
22882 }
22884 \f
22885 /* Compute the alignment given to a constant that is being placed in memory.
22886 EXP is the constant and ALIGN is the alignment that the object would
22887 ordinarily have.
22888 The value of this function is used instead of that alignment to align
22889 the object. */
22891 int
22893 {
22896 {
22901 }
22907 }
22909 /* Compute the alignment for a static variable.
22910 TYPE is the data type, and ALIGN is the alignment that
22911 the object would ordinarily have. The value of this function is used
22912 instead of that alignment to align the object. */
22914 int
22916 {
22927 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
22928 to 16byte boundary. */
22930 {
22937 }
22940 {
22945 }
22947 {
22954 }
22959 {
22964 }
22967 {
22972 }
22975 }
22977 /* Compute the alignment for a local variable or a stack slot. EXP is
22978 the data type or decl itself, MODE is the widest mode available and
22979 ALIGN is the alignment that the object would ordinarily have. The
22980 value of this macro is used instead of that alignment to align the
22981 object. */
22983 unsigned int
22986 {
22990 {
22993 }
22994 else
22995 {
22998 }
23000 /* Don't do dynamic stack realignment for long long objects with
23001 -mpreferred-stack-boundary=2. */
23010 /* If TYPE is NULL, we are allocating a stack slot for caller-save
23011 register in MODE. We will return the largest alignment of XF
23012 and DF. */
23014 {
23018 }
23020 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
23021 to 16byte boundary. Exact wording is:
23023 An array uses the same alignment as its elements, except that a local or
23024 global array variable of length at least 16 bytes or
23025 a C99 variable-length array variable always has alignment of at least 16 bytes.
23027 This was added to allow use of aligned SSE instructions at arrays. This
23028 rule is meant for static storage (where compiler can not do the analysis
23029 by itself). We follow it for automatic variables only when convenient.
23030 We fully control everything in the function compiled and functions from
23031 other unit can not rely on the alignment.
23033 Exclude va_list type. It is the common case of local array where
23034 we can not benefit from the alignment. */
23037 {
23047 }
23049 {
23054 }
23056 {
23062 }
23067 {
23072 }
23075 {
23081 }
23083 }
23085 /* Compute the minimum required alignment for dynamic stack realignment
23086 purposes for a local variable, parameter or a stack slot. EXP is
23087 the data type or decl itself, MODE is its mode and ALIGN is the
23088 alignment that the object would ordinarily have. */
23090 unsigned int
23093 {
23097 {
23100 }
23101 else
23102 {
23105 }
23110 /* Don't do dynamic stack realignment for long long objects with
23111 -mpreferred-stack-boundary=2. */
23118 }
23119 \f
23120 /* Find a location for the static chain incoming to a nested function.
23121 This is a register, unless all free registers are used by arguments. */
23123 static rtx
23125 {
23132 {
23133 /* We always use R10 in 64-bit mode. */
23135 }
23136 else
23137 {
23138 tree fntype;
23139 /* By default in 32-bit mode we use ECX to pass the static chain. */
23144 {
23145 /* Fastcall functions use ecx/edx for arguments, which leaves
23146 us with EAX for the static chain. */
23148 }
23150 {
23151 /* Thiscall functions use ecx for arguments, which leaves
23152 us with EAX for the static chain. */
23154 }
23156 {
23157 /* For regparm 3, we have no free call-clobbered registers in
23158 which to store the static chain. In order to implement this,
23159 we have the trampoline push the static chain to the stack.
23160 However, we can't push a value below the return address when
23161 we call the nested function directly, so we have to use an
23162 alternate entry point. For this we use ESI, and have the
23163 alternate entry point push ESI, so that things appear the
23164 same once we're executing the nested function. */
23166 {
23171 }
23173 }
23174 }
23177 }
23179 /* Emit RTL insns to initialize the variable parts of a trampoline.
23180 FNDECL is the decl of the target address; M_TRAMP is a MEM for
23181 the trampoline, and CHAIN_VALUE is an RTX for the static chain
23182 to be passed to the target function. */
23184 static void
23186 {
23192 {
23196 /* Depending on the static chain location, either load a register
23197 with a constant, or push the constant to the stack. All of the
23198 instructions are the same size. */
23201 {
23206 else
23208 }
23209 else
23218 /* Compute offset from the end of the jmp to the target function.
23219 In the case in which the trampoline stores the static chain on
23220 the stack, we need to skip the first insn which pushes the
23221 (call-saved) register static chain; this push is 1 byte. */
23232 }
23233 else
23234 {
23237 /* Load the function address to r11. Try to load address using
23238 the shorter movl instead of movabs. We may want to support
23239 movq for kernel mode, but kernel does not use trampolines at
23240 the moment. */
23242 {
23251 }
23252 else
23253 {
23260 }
23262 /* Load static chain using movabs to r10. */
23270 /* Jump to r11; the last (unused) byte is a nop, only there to
23271 pad the write out to a single 32-bit store. */
23277 }
23279 #ifdef ENABLE_EXECUTE_STACK
23280 #ifdef CHECK_EXECUTE_STACK_ENABLED
23282 #endif
23285 #endif
23286 }
23287 \f
23288 /* The following file contains several enumerations and data structures
23289 built from the definitions in i386-builtin-types.def. */
23293 /* Table for the ix86 builtin non-function types. */
23296 /* Retrieve an element from the above table, building some of
23297 the types lazily. */
23299 static tree
23301 {
23313 {
23321 }
23322 else
23323 {
23329 else
23337 }
23341 }
23343 /* Table for the ix86 builtin function types. */
23346 /* Retrieve an element from the above table, building some of
23347 the types lazily. */
23349 static tree
23351 {
23352 tree type;
23361 {
23369 {
23372 }
23375 }
23376 else
23377 {
23383 }
23387 }
23390 /* Codes for all the SSE/MMX builtins. */
23391 enum ix86_builtins
23392 {
23393 IX86_BUILTIN_ADDPS,
23394 IX86_BUILTIN_ADDSS,
23395 IX86_BUILTIN_DIVPS,
23396 IX86_BUILTIN_DIVSS,
23397 IX86_BUILTIN_MULPS,
23398 IX86_BUILTIN_MULSS,
23399 IX86_BUILTIN_SUBPS,
23400 IX86_BUILTIN_SUBSS,
23402 IX86_BUILTIN_CMPEQPS,
23403 IX86_BUILTIN_CMPLTPS,
23404 IX86_BUILTIN_CMPLEPS,
23405 IX86_BUILTIN_CMPGTPS,
23406 IX86_BUILTIN_CMPGEPS,
23407 IX86_BUILTIN_CMPNEQPS,
23408 IX86_BUILTIN_CMPNLTPS,
23409 IX86_BUILTIN_CMPNLEPS,
23410 IX86_BUILTIN_CMPNGTPS,
23411 IX86_BUILTIN_CMPNGEPS,
23412 IX86_BUILTIN_CMPORDPS,
23413 IX86_BUILTIN_CMPUNORDPS,
23414 IX86_BUILTIN_CMPEQSS,
23415 IX86_BUILTIN_CMPLTSS,
23416 IX86_BUILTIN_CMPLESS,
23417 IX86_BUILTIN_CMPNEQSS,
23418 IX86_BUILTIN_CMPNLTSS,
23419 IX86_BUILTIN_CMPNLESS,
23420 IX86_BUILTIN_CMPNGTSS,
23421 IX86_BUILTIN_CMPNGESS,
23422 IX86_BUILTIN_CMPORDSS,
23423 IX86_BUILTIN_CMPUNORDSS,
23425 IX86_BUILTIN_COMIEQSS,
23426 IX86_BUILTIN_COMILTSS,
23427 IX86_BUILTIN_COMILESS,
23428 IX86_BUILTIN_COMIGTSS,
23429 IX86_BUILTIN_COMIGESS,
23430 IX86_BUILTIN_COMINEQSS,
23431 IX86_BUILTIN_UCOMIEQSS,
23432 IX86_BUILTIN_UCOMILTSS,
23433 IX86_BUILTIN_UCOMILESS,
23434 IX86_BUILTIN_UCOMIGTSS,
23435 IX86_BUILTIN_UCOMIGESS,
23436 IX86_BUILTIN_UCOMINEQSS,
23438 IX86_BUILTIN_CVTPI2PS,
23439 IX86_BUILTIN_CVTPS2PI,
23440 IX86_BUILTIN_CVTSI2SS,
23441 IX86_BUILTIN_CVTSI642SS,
23442 IX86_BUILTIN_CVTSS2SI,
23443 IX86_BUILTIN_CVTSS2SI64,
23444 IX86_BUILTIN_CVTTPS2PI,
23445 IX86_BUILTIN_CVTTSS2SI,
23446 IX86_BUILTIN_CVTTSS2SI64,
23448 IX86_BUILTIN_MAXPS,
23449 IX86_BUILTIN_MAXSS,
23450 IX86_BUILTIN_MINPS,
23451 IX86_BUILTIN_MINSS,
23453 IX86_BUILTIN_LOADUPS,
23454 IX86_BUILTIN_STOREUPS,
23455 IX86_BUILTIN_MOVSS,
23457 IX86_BUILTIN_MOVHLPS,
23458 IX86_BUILTIN_MOVLHPS,
23459 IX86_BUILTIN_LOADHPS,
23460 IX86_BUILTIN_LOADLPS,
23461 IX86_BUILTIN_STOREHPS,
23462 IX86_BUILTIN_STORELPS,
23464 IX86_BUILTIN_MASKMOVQ,
23465 IX86_BUILTIN_MOVMSKPS,
23466 IX86_BUILTIN_PMOVMSKB,
23468 IX86_BUILTIN_MOVNTPS,
23469 IX86_BUILTIN_MOVNTQ,
23471 IX86_BUILTIN_LOADDQU,
23472 IX86_BUILTIN_STOREDQU,
23474 IX86_BUILTIN_PACKSSWB,
23475 IX86_BUILTIN_PACKSSDW,
23476 IX86_BUILTIN_PACKUSWB,
23478 IX86_BUILTIN_PADDB,
23479 IX86_BUILTIN_PADDW,
23480 IX86_BUILTIN_PADDD,
23481 IX86_BUILTIN_PADDQ,
23482 IX86_BUILTIN_PADDSB,
23483 IX86_BUILTIN_PADDSW,
23484 IX86_BUILTIN_PADDUSB,
23485 IX86_BUILTIN_PADDUSW,
23486 IX86_BUILTIN_PSUBB,
23487 IX86_BUILTIN_PSUBW,
23488 IX86_BUILTIN_PSUBD,
23489 IX86_BUILTIN_PSUBQ,
23490 IX86_BUILTIN_PSUBSB,
23491 IX86_BUILTIN_PSUBSW,
23492 IX86_BUILTIN_PSUBUSB,
23493 IX86_BUILTIN_PSUBUSW,
23495 IX86_BUILTIN_PAND,
23496 IX86_BUILTIN_PANDN,
23497 IX86_BUILTIN_POR,
23498 IX86_BUILTIN_PXOR,
23500 IX86_BUILTIN_PAVGB,
23501 IX86_BUILTIN_PAVGW,
23503 IX86_BUILTIN_PCMPEQB,
23504 IX86_BUILTIN_PCMPEQW,
23505 IX86_BUILTIN_PCMPEQD,
23506 IX86_BUILTIN_PCMPGTB,
23507 IX86_BUILTIN_PCMPGTW,
23508 IX86_BUILTIN_PCMPGTD,
23510 IX86_BUILTIN_PMADDWD,
23512 IX86_BUILTIN_PMAXSW,
23513 IX86_BUILTIN_PMAXUB,
23514 IX86_BUILTIN_PMINSW,
23515 IX86_BUILTIN_PMINUB,
23517 IX86_BUILTIN_PMULHUW,
23518 IX86_BUILTIN_PMULHW,
23519 IX86_BUILTIN_PMULLW,
23521 IX86_BUILTIN_PSADBW,
23522 IX86_BUILTIN_PSHUFW,
23524 IX86_BUILTIN_PSLLW,
23525 IX86_BUILTIN_PSLLD,
23526 IX86_BUILTIN_PSLLQ,
23527 IX86_BUILTIN_PSRAW,
23528 IX86_BUILTIN_PSRAD,
23529 IX86_BUILTIN_PSRLW,
23530 IX86_BUILTIN_PSRLD,
23531 IX86_BUILTIN_PSRLQ,
23532 IX86_BUILTIN_PSLLWI,
23533 IX86_BUILTIN_PSLLDI,
23534 IX86_BUILTIN_PSLLQI,
23535 IX86_BUILTIN_PSRAWI,
23536 IX86_BUILTIN_PSRADI,
23537 IX86_BUILTIN_PSRLWI,
23538 IX86_BUILTIN_PSRLDI,
23539 IX86_BUILTIN_PSRLQI,
23541 IX86_BUILTIN_PUNPCKHBW,
23542 IX86_BUILTIN_PUNPCKHWD,
23543 IX86_BUILTIN_PUNPCKHDQ,
23544 IX86_BUILTIN_PUNPCKLBW,
23545 IX86_BUILTIN_PUNPCKLWD,
23546 IX86_BUILTIN_PUNPCKLDQ,
23548 IX86_BUILTIN_SHUFPS,
23550 IX86_BUILTIN_RCPPS,
23551 IX86_BUILTIN_RCPSS,
23552 IX86_BUILTIN_RSQRTPS,
23553 IX86_BUILTIN_RSQRTPS_NR,
23554 IX86_BUILTIN_RSQRTSS,
23555 IX86_BUILTIN_RSQRTF,
23556 IX86_BUILTIN_SQRTPS,
23557 IX86_BUILTIN_SQRTPS_NR,
23558 IX86_BUILTIN_SQRTSS,
23560 IX86_BUILTIN_UNPCKHPS,
23561 IX86_BUILTIN_UNPCKLPS,
23563 IX86_BUILTIN_ANDPS,
23564 IX86_BUILTIN_ANDNPS,
23565 IX86_BUILTIN_ORPS,
23566 IX86_BUILTIN_XORPS,
23568 IX86_BUILTIN_EMMS,
23569 IX86_BUILTIN_LDMXCSR,
23570 IX86_BUILTIN_STMXCSR,
23571 IX86_BUILTIN_SFENCE,
23573 /* 3DNow! Original */
23574 IX86_BUILTIN_FEMMS,
23575 IX86_BUILTIN_PAVGUSB,
23576 IX86_BUILTIN_PF2ID,
23577 IX86_BUILTIN_PFACC,
23578 IX86_BUILTIN_PFADD,
23579 IX86_BUILTIN_PFCMPEQ,
23580 IX86_BUILTIN_PFCMPGE,
23581 IX86_BUILTIN_PFCMPGT,
23582 IX86_BUILTIN_PFMAX,
23583 IX86_BUILTIN_PFMIN,
23584 IX86_BUILTIN_PFMUL,
23585 IX86_BUILTIN_PFRCP,
23586 IX86_BUILTIN_PFRCPIT1,
23587 IX86_BUILTIN_PFRCPIT2,
23588 IX86_BUILTIN_PFRSQIT1,
23589 IX86_BUILTIN_PFRSQRT,
23590 IX86_BUILTIN_PFSUB,
23591 IX86_BUILTIN_PFSUBR,
23592 IX86_BUILTIN_PI2FD,
23593 IX86_BUILTIN_PMULHRW,
23595 /* 3DNow! Athlon Extensions */
23596 IX86_BUILTIN_PF2IW,
23597 IX86_BUILTIN_PFNACC,
23598 IX86_BUILTIN_PFPNACC,
23599 IX86_BUILTIN_PI2FW,
23600 IX86_BUILTIN_PSWAPDSI,
23601 IX86_BUILTIN_PSWAPDSF,
23603 /* SSE2 */
23604 IX86_BUILTIN_ADDPD,
23605 IX86_BUILTIN_ADDSD,
23606 IX86_BUILTIN_DIVPD,
23607 IX86_BUILTIN_DIVSD,
23608 IX86_BUILTIN_MULPD,
23609 IX86_BUILTIN_MULSD,
23610 IX86_BUILTIN_SUBPD,
23611 IX86_BUILTIN_SUBSD,
23613 IX86_BUILTIN_CMPEQPD,
23614 IX86_BUILTIN_CMPLTPD,
23615 IX86_BUILTIN_CMPLEPD,
23616 IX86_BUILTIN_CMPGTPD,
23617 IX86_BUILTIN_CMPGEPD,
23618 IX86_BUILTIN_CMPNEQPD,
23619 IX86_BUILTIN_CMPNLTPD,
23620 IX86_BUILTIN_CMPNLEPD,
23621 IX86_BUILTIN_CMPNGTPD,
23622 IX86_BUILTIN_CMPNGEPD,
23623 IX86_BUILTIN_CMPORDPD,
23624 IX86_BUILTIN_CMPUNORDPD,
23625 IX86_BUILTIN_CMPEQSD,
23626 IX86_BUILTIN_CMPLTSD,
23627 IX86_BUILTIN_CMPLESD,
23628 IX86_BUILTIN_CMPNEQSD,
23629 IX86_BUILTIN_CMPNLTSD,
23630 IX86_BUILTIN_CMPNLESD,
23631 IX86_BUILTIN_CMPORDSD,
23632 IX86_BUILTIN_CMPUNORDSD,
23634 IX86_BUILTIN_COMIEQSD,
23635 IX86_BUILTIN_COMILTSD,
23636 IX86_BUILTIN_COMILESD,
23637 IX86_BUILTIN_COMIGTSD,
23638 IX86_BUILTIN_COMIGESD,
23639 IX86_BUILTIN_COMINEQSD,
23640 IX86_BUILTIN_UCOMIEQSD,
23641 IX86_BUILTIN_UCOMILTSD,
23642 IX86_BUILTIN_UCOMILESD,
23643 IX86_BUILTIN_UCOMIGTSD,
23644 IX86_BUILTIN_UCOMIGESD,
23645 IX86_BUILTIN_UCOMINEQSD,
23647 IX86_BUILTIN_MAXPD,
23648 IX86_BUILTIN_MAXSD,
23649 IX86_BUILTIN_MINPD,
23650 IX86_BUILTIN_MINSD,
23652 IX86_BUILTIN_ANDPD,
23653 IX86_BUILTIN_ANDNPD,
23654 IX86_BUILTIN_ORPD,
23655 IX86_BUILTIN_XORPD,
23657 IX86_BUILTIN_SQRTPD,
23658 IX86_BUILTIN_SQRTSD,
23660 IX86_BUILTIN_UNPCKHPD,
23661 IX86_BUILTIN_UNPCKLPD,
23663 IX86_BUILTIN_SHUFPD,
23665 IX86_BUILTIN_LOADUPD,
23666 IX86_BUILTIN_STOREUPD,
23667 IX86_BUILTIN_MOVSD,
23669 IX86_BUILTIN_LOADHPD,
23670 IX86_BUILTIN_LOADLPD,
23672 IX86_BUILTIN_CVTDQ2PD,
23673 IX86_BUILTIN_CVTDQ2PS,
23675 IX86_BUILTIN_CVTPD2DQ,
23676 IX86_BUILTIN_CVTPD2PI,
23677 IX86_BUILTIN_CVTPD2PS,
23678 IX86_BUILTIN_CVTTPD2DQ,
23679 IX86_BUILTIN_CVTTPD2PI,
23681 IX86_BUILTIN_CVTPI2PD,
23682 IX86_BUILTIN_CVTSI2SD,
23683 IX86_BUILTIN_CVTSI642SD,
23685 IX86_BUILTIN_CVTSD2SI,
23686 IX86_BUILTIN_CVTSD2SI64,
23687 IX86_BUILTIN_CVTSD2SS,
23688 IX86_BUILTIN_CVTSS2SD,
23689 IX86_BUILTIN_CVTTSD2SI,
23690 IX86_BUILTIN_CVTTSD2SI64,
23692 IX86_BUILTIN_CVTPS2DQ,
23693 IX86_BUILTIN_CVTPS2PD,
23694 IX86_BUILTIN_CVTTPS2DQ,
23696 IX86_BUILTIN_MOVNTI,
23697 IX86_BUILTIN_MOVNTPD,
23698 IX86_BUILTIN_MOVNTDQ,
23700 IX86_BUILTIN_MOVQ128,
23702 /* SSE2 MMX */
23703 IX86_BUILTIN_MASKMOVDQU,
23704 IX86_BUILTIN_MOVMSKPD,
23705 IX86_BUILTIN_PMOVMSKB128,
23707 IX86_BUILTIN_PACKSSWB128,
23708 IX86_BUILTIN_PACKSSDW128,
23709 IX86_BUILTIN_PACKUSWB128,
23711 IX86_BUILTIN_PADDB128,
23712 IX86_BUILTIN_PADDW128,
23713 IX86_BUILTIN_PADDD128,
23714 IX86_BUILTIN_PADDQ128,
23715 IX86_BUILTIN_PADDSB128,
23716 IX86_BUILTIN_PADDSW128,
23717 IX86_BUILTIN_PADDUSB128,
23718 IX86_BUILTIN_PADDUSW128,
23719 IX86_BUILTIN_PSUBB128,
23720 IX86_BUILTIN_PSUBW128,
23721 IX86_BUILTIN_PSUBD128,
23722 IX86_BUILTIN_PSUBQ128,
23723 IX86_BUILTIN_PSUBSB128,
23724 IX86_BUILTIN_PSUBSW128,
23725 IX86_BUILTIN_PSUBUSB128,
23726 IX86_BUILTIN_PSUBUSW128,
23728 IX86_BUILTIN_PAND128,
23729 IX86_BUILTIN_PANDN128,
23730 IX86_BUILTIN_POR128,
23731 IX86_BUILTIN_PXOR128,
23733 IX86_BUILTIN_PAVGB128,
23734 IX86_BUILTIN_PAVGW128,
23736 IX86_BUILTIN_PCMPEQB128,
23737 IX86_BUILTIN_PCMPEQW128,
23738 IX86_BUILTIN_PCMPEQD128,
23739 IX86_BUILTIN_PCMPGTB128,
23740 IX86_BUILTIN_PCMPGTW128,
23741 IX86_BUILTIN_PCMPGTD128,
23743 IX86_BUILTIN_PMADDWD128,
23745 IX86_BUILTIN_PMAXSW128,
23746 IX86_BUILTIN_PMAXUB128,
23747 IX86_BUILTIN_PMINSW128,
23748 IX86_BUILTIN_PMINUB128,
23750 IX86_BUILTIN_PMULUDQ,
23751 IX86_BUILTIN_PMULUDQ128,
23752 IX86_BUILTIN_PMULHUW128,
23753 IX86_BUILTIN_PMULHW128,
23754 IX86_BUILTIN_PMULLW128,
23756 IX86_BUILTIN_PSADBW128,
23757 IX86_BUILTIN_PSHUFHW,
23758 IX86_BUILTIN_PSHUFLW,
23759 IX86_BUILTIN_PSHUFD,
23761 IX86_BUILTIN_PSLLDQI128,
23762 IX86_BUILTIN_PSLLWI128,
23763 IX86_BUILTIN_PSLLDI128,
23764 IX86_BUILTIN_PSLLQI128,
23765 IX86_BUILTIN_PSRAWI128,
23766 IX86_BUILTIN_PSRADI128,
23767 IX86_BUILTIN_PSRLDQI128,
23768 IX86_BUILTIN_PSRLWI128,
23769 IX86_BUILTIN_PSRLDI128,
23770 IX86_BUILTIN_PSRLQI128,
23772 IX86_BUILTIN_PSLLDQ128,
23773 IX86_BUILTIN_PSLLW128,
23774 IX86_BUILTIN_PSLLD128,
23775 IX86_BUILTIN_PSLLQ128,
23776 IX86_BUILTIN_PSRAW128,
23777 IX86_BUILTIN_PSRAD128,
23778 IX86_BUILTIN_PSRLW128,
23779 IX86_BUILTIN_PSRLD128,
23780 IX86_BUILTIN_PSRLQ128,
23782 IX86_BUILTIN_PUNPCKHBW128,
23783 IX86_BUILTIN_PUNPCKHWD128,
23784 IX86_BUILTIN_PUNPCKHDQ128,
23785 IX86_BUILTIN_PUNPCKHQDQ128,
23786 IX86_BUILTIN_PUNPCKLBW128,
23787 IX86_BUILTIN_PUNPCKLWD128,
23788 IX86_BUILTIN_PUNPCKLDQ128,
23789 IX86_BUILTIN_PUNPCKLQDQ128,
23791 IX86_BUILTIN_CLFLUSH,
23792 IX86_BUILTIN_MFENCE,
23793 IX86_BUILTIN_LFENCE,
23795 IX86_BUILTIN_BSRSI,
23796 IX86_BUILTIN_BSRDI,
23797 IX86_BUILTIN_RDPMC,
23798 IX86_BUILTIN_RDTSC,
23799 IX86_BUILTIN_RDTSCP,
23800 IX86_BUILTIN_ROLQI,
23801 IX86_BUILTIN_ROLHI,
23802 IX86_BUILTIN_RORQI,
23803 IX86_BUILTIN_RORHI,
23805 /* SSE3. */
23806 IX86_BUILTIN_ADDSUBPS,
23807 IX86_BUILTIN_HADDPS,
23808 IX86_BUILTIN_HSUBPS,
23809 IX86_BUILTIN_MOVSHDUP,
23810 IX86_BUILTIN_MOVSLDUP,
23811 IX86_BUILTIN_ADDSUBPD,
23812 IX86_BUILTIN_HADDPD,
23813 IX86_BUILTIN_HSUBPD,
23814 IX86_BUILTIN_LDDQU,
23816 IX86_BUILTIN_MONITOR,
23817 IX86_BUILTIN_MWAIT,
23819 /* SSSE3. */
23820 IX86_BUILTIN_PHADDW,
23821 IX86_BUILTIN_PHADDD,
23822 IX86_BUILTIN_PHADDSW,
23823 IX86_BUILTIN_PHSUBW,
23824 IX86_BUILTIN_PHSUBD,
23825 IX86_BUILTIN_PHSUBSW,
23826 IX86_BUILTIN_PMADDUBSW,
23827 IX86_BUILTIN_PMULHRSW,
23828 IX86_BUILTIN_PSHUFB,
23829 IX86_BUILTIN_PSIGNB,
23830 IX86_BUILTIN_PSIGNW,
23831 IX86_BUILTIN_PSIGND,
23832 IX86_BUILTIN_PALIGNR,
23833 IX86_BUILTIN_PABSB,
23834 IX86_BUILTIN_PABSW,
23835 IX86_BUILTIN_PABSD,
23837 IX86_BUILTIN_PHADDW128,
23838 IX86_BUILTIN_PHADDD128,
23839 IX86_BUILTIN_PHADDSW128,
23840 IX86_BUILTIN_PHSUBW128,
23841 IX86_BUILTIN_PHSUBD128,
23842 IX86_BUILTIN_PHSUBSW128,
23843 IX86_BUILTIN_PMADDUBSW128,
23844 IX86_BUILTIN_PMULHRSW128,
23845 IX86_BUILTIN_PSHUFB128,
23846 IX86_BUILTIN_PSIGNB128,
23847 IX86_BUILTIN_PSIGNW128,
23848 IX86_BUILTIN_PSIGND128,
23849 IX86_BUILTIN_PALIGNR128,
23850 IX86_BUILTIN_PABSB128,
23851 IX86_BUILTIN_PABSW128,
23852 IX86_BUILTIN_PABSD128,
23854 /* AMDFAM10 - SSE4A New Instructions. */
23855 IX86_BUILTIN_MOVNTSD,
23856 IX86_BUILTIN_MOVNTSS,
23857 IX86_BUILTIN_EXTRQI,
23858 IX86_BUILTIN_EXTRQ,
23859 IX86_BUILTIN_INSERTQI,
23860 IX86_BUILTIN_INSERTQ,
23862 /* SSE4.1. */
23863 IX86_BUILTIN_BLENDPD,
23864 IX86_BUILTIN_BLENDPS,
23865 IX86_BUILTIN_BLENDVPD,
23866 IX86_BUILTIN_BLENDVPS,
23867 IX86_BUILTIN_PBLENDVB128,
23868 IX86_BUILTIN_PBLENDW128,
23870 IX86_BUILTIN_DPPD,
23871 IX86_BUILTIN_DPPS,
23873 IX86_BUILTIN_INSERTPS128,
23875 IX86_BUILTIN_MOVNTDQA,
23876 IX86_BUILTIN_MPSADBW128,
23877 IX86_BUILTIN_PACKUSDW128,
23878 IX86_BUILTIN_PCMPEQQ,
23879 IX86_BUILTIN_PHMINPOSUW128,
23881 IX86_BUILTIN_PMAXSB128,
23882 IX86_BUILTIN_PMAXSD128,
23883 IX86_BUILTIN_PMAXUD128,
23884 IX86_BUILTIN_PMAXUW128,
23886 IX86_BUILTIN_PMINSB128,
23887 IX86_BUILTIN_PMINSD128,
23888 IX86_BUILTIN_PMINUD128,
23889 IX86_BUILTIN_PMINUW128,
23891 IX86_BUILTIN_PMOVSXBW128,
23892 IX86_BUILTIN_PMOVSXBD128,
23893 IX86_BUILTIN_PMOVSXBQ128,
23894 IX86_BUILTIN_PMOVSXWD128,
23895 IX86_BUILTIN_PMOVSXWQ128,
23896 IX86_BUILTIN_PMOVSXDQ128,
23898 IX86_BUILTIN_PMOVZXBW128,
23899 IX86_BUILTIN_PMOVZXBD128,
23900 IX86_BUILTIN_PMOVZXBQ128,
23901 IX86_BUILTIN_PMOVZXWD128,
23902 IX86_BUILTIN_PMOVZXWQ128,
23903 IX86_BUILTIN_PMOVZXDQ128,
23905 IX86_BUILTIN_PMULDQ128,
23906 IX86_BUILTIN_PMULLD128,
23908 IX86_BUILTIN_ROUNDPD,
23909 IX86_BUILTIN_ROUNDPS,
23910 IX86_BUILTIN_ROUNDSD,
23911 IX86_BUILTIN_ROUNDSS,
23913 IX86_BUILTIN_PTESTZ,
23914 IX86_BUILTIN_PTESTC,
23915 IX86_BUILTIN_PTESTNZC,
23917 IX86_BUILTIN_VEC_INIT_V2SI,
23918 IX86_BUILTIN_VEC_INIT_V4HI,
23919 IX86_BUILTIN_VEC_INIT_V8QI,
23920 IX86_BUILTIN_VEC_EXT_V2DF,
23921 IX86_BUILTIN_VEC_EXT_V2DI,
23922 IX86_BUILTIN_VEC_EXT_V4SF,
23923 IX86_BUILTIN_VEC_EXT_V4SI,
23924 IX86_BUILTIN_VEC_EXT_V8HI,
23925 IX86_BUILTIN_VEC_EXT_V2SI,
23926 IX86_BUILTIN_VEC_EXT_V4HI,
23927 IX86_BUILTIN_VEC_EXT_V16QI,
23928 IX86_BUILTIN_VEC_SET_V2DI,
23929 IX86_BUILTIN_VEC_SET_V4SF,
23930 IX86_BUILTIN_VEC_SET_V4SI,
23931 IX86_BUILTIN_VEC_SET_V8HI,
23932 IX86_BUILTIN_VEC_SET_V4HI,
23933 IX86_BUILTIN_VEC_SET_V16QI,
23935 IX86_BUILTIN_VEC_PACK_SFIX,
23937 /* SSE4.2. */
23938 IX86_BUILTIN_CRC32QI,
23939 IX86_BUILTIN_CRC32HI,
23940 IX86_BUILTIN_CRC32SI,
23941 IX86_BUILTIN_CRC32DI,
23943 IX86_BUILTIN_PCMPESTRI128,
23944 IX86_BUILTIN_PCMPESTRM128,
23945 IX86_BUILTIN_PCMPESTRA128,
23946 IX86_BUILTIN_PCMPESTRC128,
23947 IX86_BUILTIN_PCMPESTRO128,
23948 IX86_BUILTIN_PCMPESTRS128,
23949 IX86_BUILTIN_PCMPESTRZ128,
23950 IX86_BUILTIN_PCMPISTRI128,
23951 IX86_BUILTIN_PCMPISTRM128,
23952 IX86_BUILTIN_PCMPISTRA128,
23953 IX86_BUILTIN_PCMPISTRC128,
23954 IX86_BUILTIN_PCMPISTRO128,
23955 IX86_BUILTIN_PCMPISTRS128,
23956 IX86_BUILTIN_PCMPISTRZ128,
23958 IX86_BUILTIN_PCMPGTQ,
23960 /* AES instructions */
23961 IX86_BUILTIN_AESENC128,
23962 IX86_BUILTIN_AESENCLAST128,
23963 IX86_BUILTIN_AESDEC128,
23964 IX86_BUILTIN_AESDECLAST128,
23965 IX86_BUILTIN_AESIMC128,
23966 IX86_BUILTIN_AESKEYGENASSIST128,
23968 /* PCLMUL instruction */
23969 IX86_BUILTIN_PCLMULQDQ128,
23971 /* AVX */
23972 IX86_BUILTIN_ADDPD256,
23973 IX86_BUILTIN_ADDPS256,
23974 IX86_BUILTIN_ADDSUBPD256,
23975 IX86_BUILTIN_ADDSUBPS256,
23976 IX86_BUILTIN_ANDPD256,
23977 IX86_BUILTIN_ANDPS256,
23978 IX86_BUILTIN_ANDNPD256,
23979 IX86_BUILTIN_ANDNPS256,
23980 IX86_BUILTIN_BLENDPD256,
23981 IX86_BUILTIN_BLENDPS256,
23982 IX86_BUILTIN_BLENDVPD256,
23983 IX86_BUILTIN_BLENDVPS256,
23984 IX86_BUILTIN_DIVPD256,
23985 IX86_BUILTIN_DIVPS256,
23986 IX86_BUILTIN_DPPS256,
23987 IX86_BUILTIN_HADDPD256,
23988 IX86_BUILTIN_HADDPS256,
23989 IX86_BUILTIN_HSUBPD256,
23990 IX86_BUILTIN_HSUBPS256,
23991 IX86_BUILTIN_MAXPD256,
23992 IX86_BUILTIN_MAXPS256,
23993 IX86_BUILTIN_MINPD256,
23994 IX86_BUILTIN_MINPS256,
23995 IX86_BUILTIN_MULPD256,
23996 IX86_BUILTIN_MULPS256,
23997 IX86_BUILTIN_ORPD256,
23998 IX86_BUILTIN_ORPS256,
23999 IX86_BUILTIN_SHUFPD256,
24000 IX86_BUILTIN_SHUFPS256,
24001 IX86_BUILTIN_SUBPD256,
24002 IX86_BUILTIN_SUBPS256,
24003 IX86_BUILTIN_XORPD256,
24004 IX86_BUILTIN_XORPS256,
24005 IX86_BUILTIN_CMPSD,
24006 IX86_BUILTIN_CMPSS,
24007 IX86_BUILTIN_CMPPD,
24008 IX86_BUILTIN_CMPPS,
24009 IX86_BUILTIN_CMPPD256,
24010 IX86_BUILTIN_CMPPS256,
24011 IX86_BUILTIN_CVTDQ2PD256,
24012 IX86_BUILTIN_CVTDQ2PS256,
24013 IX86_BUILTIN_CVTPD2PS256,
24014 IX86_BUILTIN_CVTPS2DQ256,
24015 IX86_BUILTIN_CVTPS2PD256,
24016 IX86_BUILTIN_CVTTPD2DQ256,
24017 IX86_BUILTIN_CVTPD2DQ256,
24018 IX86_BUILTIN_CVTTPS2DQ256,
24019 IX86_BUILTIN_EXTRACTF128PD256,
24020 IX86_BUILTIN_EXTRACTF128PS256,
24021 IX86_BUILTIN_EXTRACTF128SI256,
24022 IX86_BUILTIN_VZEROALL,
24023 IX86_BUILTIN_VZEROUPPER,
24024 IX86_BUILTIN_VPERMILVARPD,
24025 IX86_BUILTIN_VPERMILVARPS,
24026 IX86_BUILTIN_VPERMILVARPD256,
24027 IX86_BUILTIN_VPERMILVARPS256,
24028 IX86_BUILTIN_VPERMILPD,
24029 IX86_BUILTIN_VPERMILPS,
24030 IX86_BUILTIN_VPERMILPD256,
24031 IX86_BUILTIN_VPERMILPS256,
24032 IX86_BUILTIN_VPERMIL2PD,
24033 IX86_BUILTIN_VPERMIL2PS,
24034 IX86_BUILTIN_VPERMIL2PD256,
24035 IX86_BUILTIN_VPERMIL2PS256,
24036 IX86_BUILTIN_VPERM2F128PD256,
24037 IX86_BUILTIN_VPERM2F128PS256,
24038 IX86_BUILTIN_VPERM2F128SI256,
24039 IX86_BUILTIN_VBROADCASTSS,
24040 IX86_BUILTIN_VBROADCASTSD256,
24041 IX86_BUILTIN_VBROADCASTSS256,
24042 IX86_BUILTIN_VBROADCASTPD256,
24043 IX86_BUILTIN_VBROADCASTPS256,
24044 IX86_BUILTIN_VINSERTF128PD256,
24045 IX86_BUILTIN_VINSERTF128PS256,
24046 IX86_BUILTIN_VINSERTF128SI256,
24047 IX86_BUILTIN_LOADUPD256,
24048 IX86_BUILTIN_LOADUPS256,
24049 IX86_BUILTIN_STOREUPD256,
24050 IX86_BUILTIN_STOREUPS256,
24051 IX86_BUILTIN_LDDQU256,
24052 IX86_BUILTIN_MOVNTDQ256,
24053 IX86_BUILTIN_MOVNTPD256,
24054 IX86_BUILTIN_MOVNTPS256,
24055 IX86_BUILTIN_LOADDQU256,
24056 IX86_BUILTIN_STOREDQU256,
24057 IX86_BUILTIN_MASKLOADPD,
24058 IX86_BUILTIN_MASKLOADPS,
24059 IX86_BUILTIN_MASKSTOREPD,
24060 IX86_BUILTIN_MASKSTOREPS,
24061 IX86_BUILTIN_MASKLOADPD256,
24062 IX86_BUILTIN_MASKLOADPS256,
24063 IX86_BUILTIN_MASKSTOREPD256,
24064 IX86_BUILTIN_MASKSTOREPS256,
24065 IX86_BUILTIN_MOVSHDUP256,
24066 IX86_BUILTIN_MOVSLDUP256,
24067 IX86_BUILTIN_MOVDDUP256,
24069 IX86_BUILTIN_SQRTPD256,
24070 IX86_BUILTIN_SQRTPS256,
24071 IX86_BUILTIN_SQRTPS_NR256,
24072 IX86_BUILTIN_RSQRTPS256,
24073 IX86_BUILTIN_RSQRTPS_NR256,
24075 IX86_BUILTIN_RCPPS256,
24077 IX86_BUILTIN_ROUNDPD256,
24078 IX86_BUILTIN_ROUNDPS256,
24080 IX86_BUILTIN_UNPCKHPD256,
24081 IX86_BUILTIN_UNPCKLPD256,
24082 IX86_BUILTIN_UNPCKHPS256,
24083 IX86_BUILTIN_UNPCKLPS256,
24085 IX86_BUILTIN_SI256_SI,
24086 IX86_BUILTIN_PS256_PS,
24087 IX86_BUILTIN_PD256_PD,
24088 IX86_BUILTIN_SI_SI256,
24089 IX86_BUILTIN_PS_PS256,
24090 IX86_BUILTIN_PD_PD256,
24092 IX86_BUILTIN_VTESTZPD,
24093 IX86_BUILTIN_VTESTCPD,
24094 IX86_BUILTIN_VTESTNZCPD,
24095 IX86_BUILTIN_VTESTZPS,
24096 IX86_BUILTIN_VTESTCPS,
24097 IX86_BUILTIN_VTESTNZCPS,
24098 IX86_BUILTIN_VTESTZPD256,
24099 IX86_BUILTIN_VTESTCPD256,
24100 IX86_BUILTIN_VTESTNZCPD256,
24101 IX86_BUILTIN_VTESTZPS256,
24102 IX86_BUILTIN_VTESTCPS256,
24103 IX86_BUILTIN_VTESTNZCPS256,
24104 IX86_BUILTIN_PTESTZ256,
24105 IX86_BUILTIN_PTESTC256,
24106 IX86_BUILTIN_PTESTNZC256,
24108 IX86_BUILTIN_MOVMSKPD256,
24109 IX86_BUILTIN_MOVMSKPS256,
24111 /* TFmode support builtins. */
24112 IX86_BUILTIN_INFQ,
24113 IX86_BUILTIN_HUGE_VALQ,
24114 IX86_BUILTIN_FABSQ,
24115 IX86_BUILTIN_COPYSIGNQ,
24117 /* Vectorizer support builtins. */
24118 IX86_BUILTIN_CPYSGNPS,
24119 IX86_BUILTIN_CPYSGNPD,
24120 IX86_BUILTIN_CPYSGNPS256,
24121 IX86_BUILTIN_CPYSGNPD256,
24123 IX86_BUILTIN_CVTUDQ2PS,
24125 IX86_BUILTIN_VEC_PERM_V2DF,
24126 IX86_BUILTIN_VEC_PERM_V4SF,
24127 IX86_BUILTIN_VEC_PERM_V2DI,
24128 IX86_BUILTIN_VEC_PERM_V4SI,
24129 IX86_BUILTIN_VEC_PERM_V8HI,
24130 IX86_BUILTIN_VEC_PERM_V16QI,
24131 IX86_BUILTIN_VEC_PERM_V2DI_U,
24132 IX86_BUILTIN_VEC_PERM_V4SI_U,
24133 IX86_BUILTIN_VEC_PERM_V8HI_U,
24134 IX86_BUILTIN_VEC_PERM_V16QI_U,
24135 IX86_BUILTIN_VEC_PERM_V4DF,
24136 IX86_BUILTIN_VEC_PERM_V8SF,
24138 /* FMA4 and XOP instructions. */
24139 IX86_BUILTIN_VFMADDSS,
24140 IX86_BUILTIN_VFMADDSD,
24141 IX86_BUILTIN_VFMADDPS,
24142 IX86_BUILTIN_VFMADDPD,
24143 IX86_BUILTIN_VFMADDPS256,
24144 IX86_BUILTIN_VFMADDPD256,
24145 IX86_BUILTIN_VFMADDSUBPS,
24146 IX86_BUILTIN_VFMADDSUBPD,
24147 IX86_BUILTIN_VFMADDSUBPS256,
24148 IX86_BUILTIN_VFMADDSUBPD256,
24150 IX86_BUILTIN_VPCMOV,
24151 IX86_BUILTIN_VPCMOV_V2DI,
24152 IX86_BUILTIN_VPCMOV_V4SI,
24153 IX86_BUILTIN_VPCMOV_V8HI,
24154 IX86_BUILTIN_VPCMOV_V16QI,
24155 IX86_BUILTIN_VPCMOV_V4SF,
24156 IX86_BUILTIN_VPCMOV_V2DF,
24157 IX86_BUILTIN_VPCMOV256,
24158 IX86_BUILTIN_VPCMOV_V4DI256,
24159 IX86_BUILTIN_VPCMOV_V8SI256,
24160 IX86_BUILTIN_VPCMOV_V16HI256,
24161 IX86_BUILTIN_VPCMOV_V32QI256,
24162 IX86_BUILTIN_VPCMOV_V8SF256,
24163 IX86_BUILTIN_VPCMOV_V4DF256,
24165 IX86_BUILTIN_VPPERM,
24167 IX86_BUILTIN_VPMACSSWW,
24168 IX86_BUILTIN_VPMACSWW,
24169 IX86_BUILTIN_VPMACSSWD,
24170 IX86_BUILTIN_VPMACSWD,
24171 IX86_BUILTIN_VPMACSSDD,
24172 IX86_BUILTIN_VPMACSDD,
24173 IX86_BUILTIN_VPMACSSDQL,
24174 IX86_BUILTIN_VPMACSSDQH,
24175 IX86_BUILTIN_VPMACSDQL,
24176 IX86_BUILTIN_VPMACSDQH,
24177 IX86_BUILTIN_VPMADCSSWD,
24178 IX86_BUILTIN_VPMADCSWD,
24180 IX86_BUILTIN_VPHADDBW,
24181 IX86_BUILTIN_VPHADDBD,
24182 IX86_BUILTIN_VPHADDBQ,
24183 IX86_BUILTIN_VPHADDWD,
24184 IX86_BUILTIN_VPHADDWQ,
24185 IX86_BUILTIN_VPHADDDQ,
24186 IX86_BUILTIN_VPHADDUBW,
24187 IX86_BUILTIN_VPHADDUBD,
24188 IX86_BUILTIN_VPHADDUBQ,
24189 IX86_BUILTIN_VPHADDUWD,
24190 IX86_BUILTIN_VPHADDUWQ,
24191 IX86_BUILTIN_VPHADDUDQ,
24192 IX86_BUILTIN_VPHSUBBW,
24193 IX86_BUILTIN_VPHSUBWD,
24194 IX86_BUILTIN_VPHSUBDQ,
24196 IX86_BUILTIN_VPROTB,
24197 IX86_BUILTIN_VPROTW,
24198 IX86_BUILTIN_VPROTD,
24199 IX86_BUILTIN_VPROTQ,
24200 IX86_BUILTIN_VPROTB_IMM,
24201 IX86_BUILTIN_VPROTW_IMM,
24202 IX86_BUILTIN_VPROTD_IMM,
24203 IX86_BUILTIN_VPROTQ_IMM,
24205 IX86_BUILTIN_VPSHLB,
24206 IX86_BUILTIN_VPSHLW,
24207 IX86_BUILTIN_VPSHLD,
24208 IX86_BUILTIN_VPSHLQ,
24209 IX86_BUILTIN_VPSHAB,
24210 IX86_BUILTIN_VPSHAW,
24211 IX86_BUILTIN_VPSHAD,
24212 IX86_BUILTIN_VPSHAQ,
24214 IX86_BUILTIN_VFRCZSS,
24215 IX86_BUILTIN_VFRCZSD,
24216 IX86_BUILTIN_VFRCZPS,
24217 IX86_BUILTIN_VFRCZPD,
24218 IX86_BUILTIN_VFRCZPS256,
24219 IX86_BUILTIN_VFRCZPD256,
24221 IX86_BUILTIN_VPCOMEQUB,
24222 IX86_BUILTIN_VPCOMNEUB,
24223 IX86_BUILTIN_VPCOMLTUB,
24224 IX86_BUILTIN_VPCOMLEUB,
24225 IX86_BUILTIN_VPCOMGTUB,
24226 IX86_BUILTIN_VPCOMGEUB,
24227 IX86_BUILTIN_VPCOMFALSEUB,
24228 IX86_BUILTIN_VPCOMTRUEUB,
24230 IX86_BUILTIN_VPCOMEQUW,
24231 IX86_BUILTIN_VPCOMNEUW,
24232 IX86_BUILTIN_VPCOMLTUW,
24233 IX86_BUILTIN_VPCOMLEUW,
24234 IX86_BUILTIN_VPCOMGTUW,
24235 IX86_BUILTIN_VPCOMGEUW,
24236 IX86_BUILTIN_VPCOMFALSEUW,
24237 IX86_BUILTIN_VPCOMTRUEUW,
24239 IX86_BUILTIN_VPCOMEQUD,
24240 IX86_BUILTIN_VPCOMNEUD,
24241 IX86_BUILTIN_VPCOMLTUD,
24242 IX86_BUILTIN_VPCOMLEUD,
24243 IX86_BUILTIN_VPCOMGTUD,
24244 IX86_BUILTIN_VPCOMGEUD,
24245 IX86_BUILTIN_VPCOMFALSEUD,
24246 IX86_BUILTIN_VPCOMTRUEUD,
24248 IX86_BUILTIN_VPCOMEQUQ,
24249 IX86_BUILTIN_VPCOMNEUQ,
24250 IX86_BUILTIN_VPCOMLTUQ,
24251 IX86_BUILTIN_VPCOMLEUQ,
24252 IX86_BUILTIN_VPCOMGTUQ,
24253 IX86_BUILTIN_VPCOMGEUQ,
24254 IX86_BUILTIN_VPCOMFALSEUQ,
24255 IX86_BUILTIN_VPCOMTRUEUQ,
24257 IX86_BUILTIN_VPCOMEQB,
24258 IX86_BUILTIN_VPCOMNEB,
24259 IX86_BUILTIN_VPCOMLTB,
24260 IX86_BUILTIN_VPCOMLEB,
24261 IX86_BUILTIN_VPCOMGTB,
24262 IX86_BUILTIN_VPCOMGEB,
24263 IX86_BUILTIN_VPCOMFALSEB,
24264 IX86_BUILTIN_VPCOMTRUEB,
24266 IX86_BUILTIN_VPCOMEQW,
24267 IX86_BUILTIN_VPCOMNEW,
24268 IX86_BUILTIN_VPCOMLTW,
24269 IX86_BUILTIN_VPCOMLEW,
24270 IX86_BUILTIN_VPCOMGTW,
24271 IX86_BUILTIN_VPCOMGEW,
24272 IX86_BUILTIN_VPCOMFALSEW,
24273 IX86_BUILTIN_VPCOMTRUEW,
24275 IX86_BUILTIN_VPCOMEQD,
24276 IX86_BUILTIN_VPCOMNED,
24277 IX86_BUILTIN_VPCOMLTD,
24278 IX86_BUILTIN_VPCOMLED,
24279 IX86_BUILTIN_VPCOMGTD,
24280 IX86_BUILTIN_VPCOMGED,
24281 IX86_BUILTIN_VPCOMFALSED,
24282 IX86_BUILTIN_VPCOMTRUED,
24284 IX86_BUILTIN_VPCOMEQQ,
24285 IX86_BUILTIN_VPCOMNEQ,
24286 IX86_BUILTIN_VPCOMLTQ,
24287 IX86_BUILTIN_VPCOMLEQ,
24288 IX86_BUILTIN_VPCOMGTQ,
24289 IX86_BUILTIN_VPCOMGEQ,
24290 IX86_BUILTIN_VPCOMFALSEQ,
24291 IX86_BUILTIN_VPCOMTRUEQ,
24293 /* LWP instructions. */
24294 IX86_BUILTIN_LLWPCB,
24295 IX86_BUILTIN_SLWPCB,
24296 IX86_BUILTIN_LWPVAL32,
24297 IX86_BUILTIN_LWPVAL64,
24298 IX86_BUILTIN_LWPINS32,
24299 IX86_BUILTIN_LWPINS64,
24301 IX86_BUILTIN_CLZS,
24303 /* BMI instructions. */
24304 IX86_BUILTIN_BEXTR32,
24305 IX86_BUILTIN_BEXTR64,
24306 IX86_BUILTIN_CTZS,
24308 /* TBM instructions. */
24309 IX86_BUILTIN_BEXTRI32,
24310 IX86_BUILTIN_BEXTRI64,
24313 /* FSGSBASE instructions. */
24314 IX86_BUILTIN_RDFSBASE32,
24315 IX86_BUILTIN_RDFSBASE64,
24316 IX86_BUILTIN_RDGSBASE32,
24317 IX86_BUILTIN_RDGSBASE64,
24318 IX86_BUILTIN_WRFSBASE32,
24319 IX86_BUILTIN_WRFSBASE64,
24320 IX86_BUILTIN_WRGSBASE32,
24321 IX86_BUILTIN_WRGSBASE64,
24323 /* RDRND instructions. */
24324 IX86_BUILTIN_RDRAND16_STEP,
24325 IX86_BUILTIN_RDRAND32_STEP,
24326 IX86_BUILTIN_RDRAND64_STEP,
24328 /* F16C instructions. */
24329 IX86_BUILTIN_CVTPH2PS,
24330 IX86_BUILTIN_CVTPH2PS256,
24331 IX86_BUILTIN_CVTPS2PH,
24332 IX86_BUILTIN_CVTPS2PH256,
24334 IX86_BUILTIN_MAX
24335 };
24337 /* Table for the ix86 builtin decls. */
24340 /* Table of all of the builtin functions that are possible with different ISA's
24341 but are waiting to be built until a function is declared to use that
24342 ISA. */
24349 };
24354 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
24355 of which isa_flags to use in the ix86_builtins_isa array. Stores the
24356 function decl in the ix86_builtins array. Returns the function decl or
24357 NULL_TREE, if the builtin was not added.
24359 If the front end has a special hook for builtin functions, delay adding
24360 builtin functions that aren't in the current ISA until the ISA is changed
24361 with function specific optimization. Doing so, can save about 300K for the
24362 default compiler. When the builtin is expanded, check at that time whether
24363 it is valid.
24365 If the front end doesn't have a special hook, record all builtins, even if
24366 it isn't an instruction set in the current ISA in case the user uses
24367 function specific options for a different ISA, so that we don't get scope
24368 errors if a builtin is added in the middle of a function scope. */
24373 {
24377 {
24386 {
24392 }
24393 else
24394 {
24400 }
24401 }
24404 }
24406 /* Like def_builtin, but also marks the function decl "const". */
24411 {
24415 else
24419 }
24421 /* Add any new builtin functions for a given ISA that may not have been
24422 declared. This saves a bit of space compared to adding all of the
24423 declarations to the tree, even if we didn't use them. */
24425 static void
24427 {
24431 {
24434 {
24437 /* Don't define the builtin again. */
24443 NULL_TREE);
24448 }
24449 }
24450 }
24452 /* Bits for builtin_description.flag. */
24454 /* Set when we don't support the comparison natively, and should
24455 swap_comparison in order to support it. */
24456 #define BUILTIN_DESC_SWAP_OPERANDS 1
24458 struct builtin_description
24459 {
24466 };
24469 {
24470 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
24471 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
24472 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
24473 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
24474 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
24475 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
24476 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
24477 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
24478 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
24479 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
24480 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
24481 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
24482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
24483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
24484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
24485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
24486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
24487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
24488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
24489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
24490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
24491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
24492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
24493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
24494 };
24497 {
24498 /* SSE4.2 */
24499 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
24500 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
24501 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
24502 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
24503 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
24504 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
24505 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
24506 };
24509 {
24510 /* SSE4.2 */
24511 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
24512 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
24513 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
24514 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
24515 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
24516 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
24517 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
24518 };
24520 /* Special builtins with variable number of arguments. */
24522 {
24523 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
24524 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
24526 /* MMX */
24527 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24529 /* 3DNow! */
24530 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24532 /* SSE */
24533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24534 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24537 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24538 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24539 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24540 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24542 /* SSE or 3DNow!A */
24543 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24544 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
24546 /* SSE2 */
24547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
24551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
24553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
24554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
24555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24560 /* SSE3 */
24561 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24563 /* SSE4.1 */
24564 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
24566 /* SSE4A */
24567 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24568 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24570 /* AVX */
24571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
24572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
24574 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24575 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24576 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
24578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
24580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
24586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
24589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
24593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
24594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
24595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
24596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
24597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
24598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
24599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
24601 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
24602 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
24603 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
24604 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
24605 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
24606 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
24608 /* FSGSBASE */
24609 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24610 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24611 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24612 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24613 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24614 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24615 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24616 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24617 };
24619 /* Builtins with variable number of arguments. */
24621 {
24622 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
24623 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
24624 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
24625 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24626 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24627 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24628 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24630 /* MMX */
24631 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24632 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24634 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24635 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24638 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24639 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24642 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24643 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24644 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24650 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24651 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24653 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24656 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24657 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24658 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24659 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24660 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24662 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24663 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24664 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
24667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
24669 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
24671 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
24675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24678 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24680 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24682 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24683 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24684 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24685 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24686 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24687 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24689 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24690 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24691 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24692 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24694 /* 3DNow! */
24695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24696 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24698 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24700 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24701 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24702 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24703 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24704 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24705 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24706 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24707 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24708 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24709 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24710 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24711 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24712 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24713 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24714 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24716 /* 3DNow!A */
24717 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24718 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24719 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
24720 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24721 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24722 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24724 /* SSE */
24725 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
24726 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24727 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24729 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24730 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24733 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24736 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24740 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24741 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24742 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
24760 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24772 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24773 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24777 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24779 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24780 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24782 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24787 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24788 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24790 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
24791 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
24792 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
24794 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
24796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24800 /* SSE MMX or 3Dnow!A */
24801 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24802 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24803 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24805 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24806 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24807 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24808 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24810 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
24811 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
24813 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
24815 /* SSE2 */
24816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24818 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
24819 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
24820 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
24821 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
24822 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
24823 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
24824 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
24825 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
24826 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
24827 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
24828 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
24829 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
24831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
24832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
24833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
24834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
24835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
24841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
24846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24848 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24849 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
24853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24855 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24856 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24857 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24858 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24860 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24862 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
24865 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
24866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
24867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
24869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
24871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
24872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
24873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
24877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
24878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
24879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24880 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
24881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
24882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
24883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24886 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24890 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24892 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24893 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24895 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24898 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24899 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24901 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
24903 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24904 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24905 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24906 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24907 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24908 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24909 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24910 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24921 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24922 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
24924 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24926 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24927 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24929 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24939 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24940 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24941 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24944 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24945 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24946 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24947 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24948 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24949 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24950 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24951 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
24954 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
24955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
24957 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24958 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
24960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
24961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
24963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
24965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
24966 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
24967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
24968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
24970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
24971 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24972 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24973 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
24974 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24975 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24976 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
24978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
24979 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24980 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24981 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
24982 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24983 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24984 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
24986 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24987 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24988 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24989 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
24992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
24993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
24995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
24997 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
24998 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
25000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
25002 /* SSE2 MMX */
25003 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
25004 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
25006 /* SSE3 */
25007 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
25008 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
25010 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25011 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25012 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25013 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25014 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25015 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25017 /* SSSE3 */
25018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
25019 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
25020 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
25021 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
25022 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
25023 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
25025 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25026 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25027 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25028 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25029 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25030 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25031 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25032 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25033 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25034 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25035 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25036 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25037 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
25038 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
25039 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25040 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25041 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25042 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
25043 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25044 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
25045 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25046 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25047 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25048 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25050 /* SSSE3. */
25051 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
25052 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
25054 /* SSE4.1 */
25055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
25058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
25059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25062 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
25063 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
25064 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
25066 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
25067 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
25068 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
25069 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
25070 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
25071 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
25072 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
25073 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
25074 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
25075 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
25076 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
25077 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
25078 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
25080 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
25081 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25082 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25083 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25084 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25085 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25086 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25087 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25088 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25089 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25090 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
25091 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25093 /* SSE4.1 */
25094 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
25095 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
25096 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25097 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25099 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25100 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25101 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25103 /* SSE4.2 */
25104 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25105 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
25106 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
25107 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25108 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25110 /* SSE4A */
25111 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
25112 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
25113 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
25114 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25116 /* AES */
25117 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
25118 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
25120 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25121 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25122 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25123 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25125 /* PCLMUL */
25126 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
25128 /* AVX */
25129 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25130 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25133 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25134 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25137 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25143 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25144 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25145 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25146 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25147 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25148 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25149 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25150 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25151 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25152 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25153 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25154 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
25157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
25158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
25159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
25161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
25164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
25165 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25170 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25172 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25173 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25174 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
25175 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
25176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
25177 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
25178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
25179 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
25180 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
25182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
25188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
25189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
25190 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
25193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
25194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
25196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25200 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25202 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25204 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25213 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25216 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
25217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
25218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
25219 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
25220 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
25221 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
25223 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25224 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25225 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25226 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25227 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25230 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25231 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25232 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25234 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25235 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25236 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25237 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
25240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
25242 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25243 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25245 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25247 /* BMI */
25248 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25249 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25250 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25252 /* TBM */
25253 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25254 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25256 /* F16C */
25257 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
25258 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
25259 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
25260 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
25261 };
25263 /* FMA4 and XOP. */
25264 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
25265 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
25266 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
25267 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
25268 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
25269 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
25270 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
25271 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
25272 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
25273 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
25274 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
25275 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
25276 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
25277 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
25278 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
25279 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
25280 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
25281 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
25282 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
25283 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
25284 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
25285 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
25286 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
25287 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
25288 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
25289 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
25290 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
25291 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
25292 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
25293 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
25294 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
25295 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
25296 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
25297 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
25298 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
25299 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
25300 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
25301 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
25302 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
25303 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
25304 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
25305 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
25306 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
25307 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
25308 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
25309 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
25310 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
25311 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
25312 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
25313 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
25314 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
25315 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
25318 {
25352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
25353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
25354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
25355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
25356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
25357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
25358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
25360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
25363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
25364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
25365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
25366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
25368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
25370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
25385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
25386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
25387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
25388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
25389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
25390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
25391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
25393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
25394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
25395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
25397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
25398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
25400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
25401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
25402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
25403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
25404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
25405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
25407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
25424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
25427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
25428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
25429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
25431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
25432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
25435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
25436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
25437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
25439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
25440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
25443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
25444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
25445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
25447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
25451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
25452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
25453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
25455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
25456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
25459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
25460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
25461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
25463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
25464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
25467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
25468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
25469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
25471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
25472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
25475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
25476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
25477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
25479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
25483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
25484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
25485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
25487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
25506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
25507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
25508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
25510 };
25512 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
25513 in the current target ISA to allow the user to compile particular modules
25514 with different target specific options that differ from the command line
25515 options. */
25516 static void
25518 {
25523 /* Add all special builtins with variable number of operands. */
25527 {
25533 }
25535 /* Add all builtins with variable number of operands. */
25539 {
25545 }
25547 /* pcmpestr[im] insns. */
25551 {
25554 else
25557 }
25559 /* pcmpistr[im] insns. */
25563 {
25566 else
25569 }
25571 /* comi/ucomi insns. */
25573 {
25576 else
25579 }
25581 /* SSE */
25587 /* SSE or 3DNow!A */
25590 IX86_BUILTIN_MASKMOVQ);
25592 /* SSE2 */
25601 /* SSE3. */
25607 /* AES */
25621 /* PCLMUL */
25625 /* RDRND */
25632 IX86_BUILTIN_RDRAND64_STEP);
25634 /* MMX access to the vec_init patterns. */
25639 V4HI_FTYPE_HI_HI_HI_HI,
25640 IX86_BUILTIN_VEC_INIT_V4HI);
25643 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
25644 IX86_BUILTIN_VEC_INIT_V8QI);
25646 /* Access to the vec_extract patterns. */
25668 /* Access to the vec_set patterns. */
25689 /* Add FMA4 multi-arg argument instructions */
25691 {
25697 }
25698 }
25700 /* Internal method for ix86_init_builtins. */
25702 static void
25704 {
25716 sysv_va_ref =
25719 fnvoid_va_end_ms =
25721 fnvoid_va_start_ms =
25723 fnvoid_va_end_sysv =
25725 fnvoid_va_start_sysv =
25727 NULL_TREE);
25728 fnvoid_va_copy_ms =
25730 NULL_TREE);
25731 fnvoid_va_copy_sysv =
25747 }
25749 static void
25751 {
25754 /* The __float80 type. */
25757 {
25758 /* The __float80 type. */
25763 }
25766 /* The __float128 type. */
25772 /* This macro is built by i386-builtin-types.awk. */
25773 DEFINE_BUILTIN_PRIMITIVE_TYPES;
25774 }
25776 static void
25778 {
25779 tree t;
25783 /* TFmode support builtins. */
25789 /* We will expand them to normal call if SSE2 isn't available since
25790 they are used by libgcc. */
25808 #ifdef SUBTARGET_INIT_BUILTINS
25809 SUBTARGET_INIT_BUILTINS;
25810 #endif
25811 }
25813 /* Return the ix86 builtin for CODE. */
25815 static tree
25817 {
25822 }
25824 /* Errors in the source file can cause expand_expr to return const0_rtx
25825 where we expect a vector. To avoid crashing, use one of the vector
25826 clear instructions. */
25827 static rtx
25829 {
25833 }
25835 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
25837 static rtx
25839 {
25840 rtx pat;
25860 {
25864 }
25878 }
25880 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
25882 static rtx
25886 {
25887 rtx pat;
25895 rtx op;
25902 {
25982 }
25992 {
25999 {
26001 {
26004 }
26005 }
26006 else
26007 {
26011 /* If we aren't optimizing, only allow one memory operand to be
26012 generated. */
26014 num_memory++;
26022 }
26026 }
26029 {
26040 else
26041 {
26047 }
26060 }
26067 }
26069 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
26070 insns with vec_merge. */
26072 static rtx
26074 rtx target)
26075 {
26076 rtx pat;
26103 }
26105 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
26107 static rtx
26110 {
26111 rtx pat;
26116 rtx op2;
26127 /* Swap operands if we have a comparison that isn't available in
26128 hardware. */
26130 {
26135 }
26155 }
26157 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
26159 static rtx
26161 rtx target)
26162 {
26163 rtx pat;
26177 /* Swap operands if we have a comparison that isn't available in
26178 hardware. */
26180 {
26184 }
26205 const0_rtx)));
26208 }
26210 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
26212 static rtx
26214 rtx target)
26215 {
26216 rtx pat;
26249 const0_rtx)));
26252 }
26254 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
26256 static rtx
26259 {
26260 rtx pat;
26298 {
26301 }
26304 {
26313 }
26315 {
26324 }
26325 else
26326 {
26333 }
26341 {
26346 emit_insn
26350 FLAGS_REG),
26351 const0_rtx)));
26353 }
26354 else
26356 }
26359 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
26361 static rtx
26364 {
26365 rtx pat;
26393 {
26396 }
26399 {
26408 }
26410 {
26419 }
26420 else
26421 {
26428 }
26436 {
26441 emit_insn
26445 FLAGS_REG),
26446 const0_rtx)));
26448 }
26449 else
26451 }
26453 /* Subroutine of ix86_expand_builtin to take care of insns with
26454 variable number of operands. */
26456 static rtx
26459 {
26464 struct
26465 {
26466 rtx op;
26478 {
26693 }
26698 {
26701 }
26704 {
26711 }
26712 else
26713 {
26716 }
26719 {
26726 {
26727 /* SIMD shift insns take either an 8-bit immediate or
26728 register as count. But builtin functions take int as
26729 count. If count doesn't match, we put it in register. */
26731 {
26735 }
26736 }
26738 {
26741 {
26783 {
26786 {
26789 }
26795 }
26797 }
26798 }
26799 else
26800 {
26804 /* If we aren't optimizing, only allow one memory operand to
26805 be generated. */
26807 num_memory++;
26810 {
26813 }
26814 else
26815 {
26818 }
26819 }
26823 }
26826 {
26843 }
26850 }
26852 /* Subroutine of ix86_expand_builtin to take care of special insns
26853 with variable number of operands. */
26855 static rtx
26858 {
26859 tree arg;
26862 struct
26863 {
26864 rtx op;
26874 {
26921 /* Reserve memory operand for target. */
26944 /* Reserve memory operand for target. */
26958 }
26963 {
26969 else
26972 }
26973 else
26974 {
26981 }
26984 {
26993 {
26995 {
27001 else
27004 }
27005 }
27006 else
27007 {
27009 {
27010 /* This must be the memory operand. */
27014 }
27015 else
27016 {
27017 /* This must be register. */
27024 }
27025 }
27029 }
27032 {
27047 }
27053 }
27055 /* Return the integer constant in ARG. Constrain it to be in the range
27056 of the subparts of VEC_TYPE; issue an error if not. */
27058 static int
27060 {
27065 {
27068 }
27071 }
27073 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27074 ix86_expand_vector_init. We DO have language-level syntax for this, in
27075 the form of (type){ init-list }. Except that since we can't place emms
27076 instructions from inside the compiler, we can't allow the use of MMX
27077 registers unless the user explicitly asks for it. So we do *not* define
27078 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
27079 we have builtins invoked by mmintrin.h that gives us license to emit
27080 these sorts of instructions. */
27082 static rtx
27084 {
27094 {
27097 }
27104 }
27106 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27107 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
27108 had a language-level syntax for referencing vector elements. */
27110 static rtx
27112 {
27116 rtx op0;
27136 }
27138 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27139 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
27140 a language-level syntax for referencing vector elements. */
27142 static rtx
27144 {
27168 /* OP0 is the source of these builtin functions and shouldn't be
27169 modified. Create a copy, use it and return it as target. */
27175 }
27177 /* Expand an expression EXP that calls a built-in function,
27178 with result going to TARGET if that's convenient
27179 (and in mode MODE if that's convenient).
27180 SUBTARGET may be used as the target for computing one of EXP's operands.
27181 IGNORE is nonzero if the value is to be ignored. */
27183 static rtx
27187 {
27197 /* Determine whether the builtin function is available under the current ISA.
27198 Originally the builtin was not created if it wasn't applicable to the
27199 current ISA based on the command line switches. With function specific
27200 options, we need to check in the context of the function making the call
27201 whether it is supported. */
27204 {
27210 else
27211 {
27215 }
27217 }
27220 {
27224 ? CODE_FOR_mmx_maskmovq
27226 /* Note the arg order is different from the operand order. */
27341 {
27342 REAL_VALUE_TYPE inf;
27343 rtx tmp;
27355 }
27381 ? CODE_FOR_tbm_bextri_si
27384 {
27387 }
27388 else
27389 {
27398 }
27414 rdrand_step:
27421 /* Emit SImode conditional move. */
27423 {
27426 }
27429 else
27433 const0_rtx);
27447 }
27460 {
27464 /* Emit a normal call if SSE2 isn't available. */
27468 }
27493 }
27495 /* Returns a function decl for a vectorized version of the builtin function
27496 with builtin function code FN and the result vector type TYPE, or NULL_TREE
27497 if it is not available. */
27499 static tree
27501 tree type_in)
27502 {
27518 {
27521 {
27526 }
27531 {
27536 }
27547 {
27552 }
27557 {
27562 }
27567 {
27572 }
27577 {
27582 }
27587 {
27592 }
27597 }
27599 /* Dispatch to a handler for a vectorization library. */
27602 type_in);
27605 }
27607 /* Handler for an SVML-style interface to
27608 a library with vectorized intrinsics. */
27610 static tree
27612 {
27620 /* The SVML is suitable for unsafe math only. */
27633 {
27680 }
27689 {
27692 }
27693 else
27696 /* Convert to uppercase. */
27702 arity++;
27706 else
27709 /* Build a function declaration for the vectorized function. */
27718 }
27720 /* Handler for an ACML-style interface to
27721 a library with vectorized intrinsics. */
27723 static tree
27725 {
27733 /* The ACML is 64bits only and suitable for unsafe math only as
27734 it does not correctly support parts of IEEE with the required
27735 precision such as denormals. */
27749 {
27779 }
27787 arity++;
27791 else
27794 /* Build a function declaration for the vectorized function. */
27803 }
27806 /* Returns a decl of a function that implements conversion of an integer vector
27807 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
27808 are the types involved when converting according to CODE.
27809 Return NULL_TREE if it is not available. */
27811 static tree
27814 {
27819 {
27822 {
27825 {
27832 ? NULL_TREE
27836 }
27840 {
27843 ? NULL_TREE
27847 }
27851 }
27855 {
27858 {
27861 ? NULL_TREE
27865 ? NULL_TREE
27869 }
27874 {
27877 ? NULL_TREE
27881 }
27886 }
27890 }
27893 }
27895 /* Returns a code for a target-specific builtin that implements
27896 reciprocal of the function, or NULL_TREE if not available. */
27898 static tree
27901 {
27908 /* Machine dependent builtins. */
27910 {
27911 /* Vectorized version of sqrt to rsqrt conversion. */
27920 }
27921 else
27922 /* Normal builtins. */
27924 {
27925 /* Sqrt to rsqrt conversion. */
27931 }
27932 }
27933 \f
27934 /* Helper for avx_vpermilps256_operand et al. This is also used by
27935 the expansion functions to turn the parallel back into a mask.
27936 The return value is 0 for no match and the imm8+1 for a match. */
27938 int
27940 {
27948 /* Validate that all of the elements are constants, and not totally
27949 out of range. Copy the data into an integral array to make the
27950 subsequent checks easier. */
27952 {
27962 }
27965 {
27967 /* In the 256-bit DFmode case, we can only move elements within
27968 a 128-bit lane. */
27970 {
27974 }
27976 {
27980 }
27984 /* In the 256-bit SFmode case, we have full freedom of movement
27985 within the low 128-bit lane, but the high 128-bit lane must
27986 mirror the exact same pattern. */
27991 /* FALLTHRU */
27995 /* In the 128-bit case, we've full freedom in the placement of
27996 the elements from the source operand. */
28003 }
28005 /* Make sure success has a non-zero value by adding one. */
28007 }
28009 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
28010 the expansion functions to turn the parallel back into a mask.
28011 The return value is 0 for no match and the imm8+1 for a match. */
28013 int
28015 {
28023 /* Validate that all of the elements are constants, and not totally
28024 out of range. Copy the data into an integral array to make the
28025 subsequent checks easier. */
28027 {
28037 }
28039 /* Validate that the halves of the permute are halves. */
28047 /* Reconstruct the mask. */
28049 {
28055 }
28057 /* Make sure success has a non-zero value by adding one. */
28059 }
28060 \f
28062 /* Store OPERAND to the memory after reload is completed. This means
28063 that we can't easily use assign_stack_local. */
28064 rtx
28066 {
28067 rtx result;
28071 {
28074 stack_pointer_rtx,
28077 }
28079 {
28081 {
28085 /* FALLTHRU */
28091 stack_pointer_rtx)),
28092 operand));
28096 }
28098 }
28099 else
28100 {
28102 {
28104 {
28111 stack_pointer_rtx)),
28117 stack_pointer_rtx)),
28119 }
28122 /* Store HImodes as SImodes. */
28124 /* FALLTHRU */
28130 stack_pointer_rtx)),
28131 operand));
28135 }
28137 }
28139 }
28141 /* Free operand from the memory. */
28142 void
28144 {
28146 {
28151 else
28153 /* Use LEA to deallocate stack space. In peephole2 it will be converted
28154 to pop or add instruction if registers are available. */
28158 }
28159 }
28161 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
28162 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
28163 same. */
28166 {
28169 };
28172 };
28175 }
28177 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
28179 Put float CONST_DOUBLE in the constant pool instead of fp regs.
28180 QImode must go into class Q_REGS.
28181 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
28182 movdf to do mem-to-mem moves through integer regs. */
28184 static reg_class_t
28186 {
28189 /* We're only allowed to return a subclass of CLASS. Many of the
28190 following checks fail for NO_REGS, so eliminate that early. */
28194 /* All classes can load zeros. */
28198 /* Force constants into memory if we are loading a (nonzero) constant into
28199 an MMX or SSE register. This is because there are no MMX/SSE instructions
28200 to load from a constant. */
28205 /* Prefer SSE regs only, if we can use them for math. */
28209 /* Floating-point constants need more complex checks. */
28211 {
28212 /* General regs can load everything. */
28216 /* Floats can load 0 and 1 plus some others. Note that we eliminated
28217 zero above. We only want to wind up preferring 80387 registers if
28218 we plan on doing computation with them. */
28221 {
28222 /* Limit class to non-sse. */
28231 }
28234 }
28236 /* Generally when we see PLUS here, it's the function invariant
28237 (plus soft-fp const_int). Which can only be computed into general
28238 regs. */
28242 /* QImode constants are easy to load, but non-constant QImode data
28243 must go into Q_REGS. */
28245 {
28251 }
28254 }
28256 /* Discourage putting floating-point values in SSE registers unless
28257 SSE math is being used, and likewise for the 387 registers. */
28258 static reg_class_t
28260 {
28263 /* Restrict the output reload class to the register bank that we are doing
28264 math on. If we would like not to return a subset of CLASS, reject this
28265 alternative: if reload cannot do this, it will still use its choice. */
28271 {
28276 else
28278 }
28281 }
28283 static reg_class_t
28287 {
28288 /* QImode spills from non-QI registers require
28289 intermediate register on 32bit targets. */
28294 {
28299 else
28305 /* Return Q_REGS if the operand is in memory. */
28308 }
28311 }
28313 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
28315 static bool
28317 {
28319 {
28334 }
28337 }
28339 /* If we are copying between general and FP registers, we need a memory
28340 location. The same is true for SSE and MMX registers.
28342 To optimize register_move_cost performance, allow inline variant.
28344 The macro can't work reliably when one of the CLASSES is class containing
28345 registers from multiple units (SSE, MMX, integer). We avoid this by never
28346 combining those units in single alternative in the machine description.
28347 Ensure that this constraint holds to avoid unexpected surprises.
28349 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
28350 enforce these sanity checks. */
28355 {
28362 {
28365 }
28370 /* ??? This is a lie. We do have moves between mmx/general, and for
28371 mmx/sse2. But by saying we need secondary memory we discourage the
28372 register allocator from using the mmx registers unless needed. */
28377 {
28378 /* SSE1 doesn't have any direct moves from other classes. */
28382 /* If the target says that inter-unit moves are more expensive
28383 than moving through memory, then don't generate them. */
28387 /* Between SSE and general, we have moves no larger than word size. */
28390 }
28393 }
28395 bool
28398 {
28400 }
28402 /* Return true if the registers in CLASS cannot represent the change from
28403 modes FROM to TO. */
28405 bool
28408 {
28412 /* x87 registers can't do subreg at all, as all values are reformatted
28413 to extended precision. */
28418 {
28419 /* Vector registers do not support QI or HImode loads. If we don't
28420 disallow a change to these modes, reload will assume it's ok to
28421 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
28422 the vec_dupv4hi pattern. */
28426 /* Vector registers do not support subreg with nonzero offsets, which
28427 are otherwise valid for integer registers. Since we can't see
28428 whether we have a nonzero offset from here, prohibit all
28429 nonparadoxical subregs changing size. */
28432 }
28435 }
28437 /* Return the cost of moving data of mode M between a
28438 register and memory. A value of 2 is the default; this cost is
28439 relative to those in `REGISTER_MOVE_COST'.
28441 This function is used extensively by register_move_cost that is used to
28442 build tables at startup. Make it inline in this case.
28443 When IN is 2, return maximum of in and out move cost.
28445 If moving between registers and memory is more expensive than
28446 between two registers, you should define this macro to express the
28447 relative cost.
28449 Model also increased moving costs of QImode registers in non
28450 Q_REGS classes.
28451 */
28455 {
28458 {
28461 {
28473 }
28477 }
28479 {
28482 {
28494 }
28498 }
28500 {
28503 {
28512 }
28516 }
28518 {
28521 {
28527 else
28532 }
28533 else
28534 {
28539 else
28541 }
28548 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
28555 else
28559 }
28560 }
28562 static int
28565 {
28567 }
28570 /* Return the cost of moving data from a register in class CLASS1 to
28571 one in class CLASS2.
28573 It is not required that the cost always equal 2 when FROM is the same as TO;
28574 on some machines it is expensive to move between registers if they are not
28575 general registers. */
28577 static int
28579 reg_class_t class2_i)
28580 {
28584 /* In case we require secondary memory, compute cost of the store followed
28585 by load. In order to avoid bad register allocation choices, we need
28586 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
28589 {
28595 /* In case of copying from general_purpose_register we may emit multiple
28596 stores followed by single load causing memory size mismatch stall.
28597 Count this as arbitrarily high cost of 20. */
28601 /* In the case of FP/MMX moves, the registers actually overlap, and we
28602 have to switch modes in order to treat them differently. */
28608 }
28610 /* Moves between SSE/MMX and integer unit are expensive. */
28614 /* ??? By keeping returned value relatively high, we limit the number
28615 of moves between integer and MMX/SSE registers for all targets.
28616 Additionally, high value prevents problem with x86_modes_tieable_p(),
28617 where integer modes in MMX/SSE registers are not tieable
28618 because of missing QImode and HImode moves to, from or between
28619 MMX/SSE registers. */
28629 }
28631 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
28633 bool
28635 {
28636 /* Flags and only flags can only hold CCmode values. */
28646 {
28647 /* We implement the move patterns for all vector modes into and
28648 out of SSE registers, even when no operation instructions
28649 are available. OImode move is available only when AVX is
28650 enabled. */
28657 }
28659 {
28660 /* We implement the move patterns for 3DNOW modes even in MMX mode,
28661 so if the register is available at all, then we can move data of
28662 the given mode into or out of it. */
28665 }
28668 {
28669 /* Take care for QImode values - they can be in non-QI regs,
28670 but then they do cause partial register stalls. */
28676 }
28677 /* We handle both integer and floats in the general purpose registers. */
28684 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
28685 on to use that value in smaller contexts, this can easily force a
28686 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
28687 supporting DImode, allow it. */
28692 }
28694 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
28695 tieable integer mode. */
28697 static bool
28699 {
28701 {
28714 }
28715 }
28717 /* Return true if MODE1 is accessible in a register that can hold MODE2
28718 without copying. That is, all register classes that can hold MODE2
28719 can also hold MODE1. */
28721 bool
28723 {
28731 /* MODE2 being XFmode implies fp stack or general regs, which means we
28732 can tie any smaller floating point modes to it. Note that we do not
28733 tie this with TFmode. */
28737 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
28738 that we can tie it with SFmode. */
28742 /* If MODE2 is only appropriate for an SSE register, then tie with
28743 any other mode acceptable to SSE registers. */
28749 /* If MODE2 is appropriate for an MMX register, then tie
28750 with any other mode acceptable to MMX registers. */
28757 }
28759 /* Compute a (partial) cost for rtx X. Return true if the complete
28760 cost has been computed, and false if subexpressions should be
28761 scanned. In either case, *TOTAL contains the cost result. */
28763 static bool
28765 {
28771 {
28781 && (!TARGET_64BIT
28786 else
28793 else
28795 {
28804 /* Start with (MEM (SYMBOL_REF)), since that's where
28805 it'll probably end up. Add a penalty for size. */
28810 }
28814 /* The zero extensions is often completely free on x86_64, so make
28815 it as cheap as possible. */
28821 else
28832 {
28835 {
28838 }
28841 {
28844 }
28845 }
28846 /* FALLTHRU */
28853 {
28855 {
28858 else
28860 }
28861 else
28862 {
28865 else
28867 }
28868 }
28869 else
28870 {
28873 else
28875 }
28879 {
28880 rtx sub;
28885 /* ??? SSE scalar/vector cost should be used here. */
28886 /* ??? Bald assumption that fma has the same cost as fmul. */
28890 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
28901 }
28905 {
28906 /* ??? SSE scalar cost should be used here. */
28909 }
28911 {
28914 }
28916 {
28917 /* ??? SSE vector cost should be used here. */
28920 }
28921 else
28922 {
28927 {
28930 nbits++;
28931 }
28932 else
28933 /* This is arbitrary. */
28936 /* Compute costs correctly for widening multiplication. */
28940 {
28947 {
28951 else
28953 }
28957 }
28964 }
28971 /* ??? SSE cost should be used here. */
28976 /* ??? SSE vector cost should be used here. */
28978 else
28985 {
28990 {
28993 {
29000 }
29001 }
29004 {
29007 {
29012 }
29013 }
29015 {
29021 }
29022 }
29023 /* FALLTHRU */
29027 {
29028 /* ??? SSE cost should be used here. */
29031 }
29033 {
29036 }
29038 {
29039 /* ??? SSE vector cost should be used here. */
29042 }
29043 /* FALLTHRU */
29049 {
29056 }
29057 /* FALLTHRU */
29061 {
29062 /* ??? SSE cost should be used here. */
29065 }
29067 {
29070 }
29072 {
29073 /* ??? SSE vector cost should be used here. */
29076 }
29077 /* FALLTHRU */
29082 else
29091 {
29092 /* This kind of construct is implemented using test[bwl].
29093 Treat it as if we had an AND. */
29098 }
29108 /* ??? SSE cost should be used here. */
29113 /* ??? SSE vector cost should be used here. */
29119 /* ??? SSE cost should be used here. */
29124 /* ??? SSE vector cost should be used here. */
29137 /* ??? Assume all of these vector manipulation patterns are
29138 recognizable. In which case they all pretty much have the
29139 same cost. */
29145 }
29146 }
29148 #if TARGET_MACHO
29152 /* Given a symbol name and its associated stub, write out the
29153 definition of the stub. */
29155 void
29157 {
29162 /* For 64-bit we shouldn't get here. */
29165 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
29181 {
29184 else
29186 }
29187 else
29194 {
29196 }
29198 {
29199 /* PIC stub. */
29201 {
29202 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29206 }
29207 else
29208 {
29209 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %eax". */
29212 }
29214 }
29215 else
29218 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
29219 it needs no stub-binding-helper. */
29226 {
29229 }
29230 else
29235 /* N.B. Keep the correspondence of these
29236 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
29237 old-pic/new-pic/non-pic stubs; altering this will break
29238 compatibility with existing dylibs. */
29240 {
29241 /* PIC stubs. */
29243 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29245 else
29246 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %ebx". */
29248 }
29249 else
29250 /* 16-byte -mdynamic-no-pic stub. */
29256 }
29259 /* Order the registers for register allocator. */
29261 void
29263 {
29267 /* First allocate the local general purpose registers. */
29272 /* Global general purpose registers. */
29277 /* x87 registers come first in case we are doing FP math
29278 using them. */
29283 /* SSE registers. */
29289 /* x87 registers. */
29297 /* Initialize the rest of array as we do not allocate some registers
29298 at all. */
29301 }
29303 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
29304 in struct attribute_spec handler. */
29305 static tree
29307 tree args,
29310 {
29315 {
29317 name);
29320 }
29322 {
29324 name);
29327 }
29329 {
29330 tree cst;
29334 {
29337 name);
29339 }
29342 {
29345 name);
29347 }
29350 }
29353 }
29355 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
29356 struct attribute_spec.handler. */
29357 static tree
29359 tree args ATTRIBUTE_UNUSED,
29361 {
29366 {
29368 name);
29371 }
29373 {
29375 name);
29378 }
29380 /* Can combine regparm with all attributes but fastcall. */
29382 {
29384 {
29386 }
29389 }
29391 {
29393 {
29395 }
29398 }
29401 }
29403 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29404 struct attribute_spec.handler. */
29405 static tree
29407 tree args ATTRIBUTE_UNUSED,
29409 {
29412 {
29415 }
29416 else
29421 {
29423 name);
29425 }
29431 {
29433 name);
29435 }
29438 }
29440 static tree
29442 tree args ATTRIBUTE_UNUSED,
29444 {
29446 {
29448 name);
29450 }
29452 }
29454 static bool
29456 {
29460 }
29462 /* Returns an expression indicating where the this parameter is
29463 located on entry to the FUNCTION. */
29465 static rtx
29467 {
29473 {
29478 else
29481 }
29486 {
29492 {
29497 }
29498 else
29499 {
29502 {
29507 }
29508 }
29510 }
29513 }
29515 /* Determine whether x86_output_mi_thunk can succeed. */
29517 static bool
29519 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
29521 {
29522 /* 64-bit can handle anything. */
29526 /* For 32-bit, everything's fine if we have one free register. */
29530 /* Need a free register for vcall_offset. */
29534 /* Need a free register for GOT references. */
29538 /* Otherwise ok. */
29540 }
29542 /* Output the assembler code for a thunk function. THUNK_DECL is the
29543 declaration for the thunk function itself, FUNCTION is the decl for
29544 the target function. DELTA is an immediate constant offset to be
29545 added to THIS. If VCALL_OFFSET is nonzero, the word at
29546 *(*this + vcall_offset) should be added to THIS. */
29548 static void
29552 {
29557 /* Make sure unwind info is emitted for the thunk if needed. */
29560 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
29561 pull it in now and let DELTA benefit. */
29565 {
29566 /* Put the this parameter into %eax. */
29570 }
29571 else
29574 /* Adjust the this parameter by a fixed constant. */
29576 {
29580 {
29582 {
29588 }
29591 else
29593 }
29596 else
29598 }
29600 /* Adjust the this parameter by a value stored in the vtable. */
29602 {
29605 else
29606 {
29614 }
29620 /* Adjust the this parameter. */
29623 {
29629 }
29632 }
29634 /* If necessary, drop THIS back to its stack slot. */
29636 {
29640 }
29644 {
29648 /* All thunks should be in the same object as their target,
29649 and thus binds_local_p should be true. */
29652 else
29653 {
29659 }
29660 }
29661 else
29662 {
29665 else
29666 #if TARGET_MACHO
29668 {
29671 sym_ref = (gen_rtx_SYMBOL_REF
29677 }
29678 else
29680 {
29687 }
29688 }
29690 }
29692 static void
29694 {
29696 #if TARGET_MACHO
29698 #endif
29705 }
29707 int
29709 {
29721 }
29723 /* Output assembler code to FILE to increment profiler label # LABELNO
29724 for profiling a function entry. */
29725 void
29727 {
29732 {
29733 #ifndef NO_PROFILE_COUNTERS
29735 #endif
29739 else
29741 }
29743 {
29744 #ifndef NO_PROFILE_COUNTERS
29747 #endif
29749 }
29750 else
29751 {
29752 #ifndef NO_PROFILE_COUNTERS
29755 #endif
29757 }
29758 }
29760 /* We don't have exact information about the insn sizes, but we may assume
29761 quite safely that we are informed about all 1 byte insns and memory
29762 address sizes. This is enough to eliminate unnecessary padding in
29763 99% of cases. */
29765 static int
29767 {
29773 /* Discard alignments we've emit and jump instructions. */
29780 /* Important case - calls are always 5 bytes.
29781 It is common to have many calls in the row. */
29790 /* For normal instructions we rely on get_attr_length being exact,
29791 with a few exceptions. */
29793 {
29797 {
29807 /* Otherwise trust get_attr_length. */
29809 }
29814 }
29817 else
29819 }
29821 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
29823 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
29824 window. */
29826 static void
29828 {
29833 /* Look for all minimal intervals of instructions containing 4 jumps.
29834 The intervals are bounded by START and INSN. NBYTES is the total
29835 size of instructions in the interval including INSN and not including
29836 START. When the NBYTES is smaller than 16 bytes, it is possible
29837 that the end of START and INSN ends up in the same 16byte page.
29839 The smallest offset in the page INSN can start is the case where START
29840 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
29841 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
29842 */
29844 {
29848 {
29854 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
29855 already in the current 16 byte page, because otherwise
29856 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
29857 bytes to reach 16 byte boundary. */
29865 {
29867 {
29874 else
29877 }
29878 }
29880 }
29891 njumps++;
29892 else
29896 {
29903 else
29906 }
29913 {
29920 }
29921 }
29922 }
29923 #endif
29925 /* AMD Athlon works faster
29926 when RET is not destination of conditional jump or directly preceded
29927 by other jump instruction. We avoid the penalty by inserting NOP just
29928 before the RET instructions in such cases. */
29929 static void
29931 {
29932 edge e;
29933 edge_iterator ei;
29936 {
29939 rtx prev;
29949 {
29950 edge e;
29951 edge_iterator ei;
29957 }
29959 {
29965 /* Empty functions get branch mispredict even when
29966 the jump destination is not visible to us. */
29969 }
29971 {
29974 }
29975 }
29976 }
29978 /* Count the minimum number of instructions in BB. Return 4 if the
29979 number of instructions >= 4. */
29981 static int
29983 {
29984 rtx insn;
29987 /* Count number of instructions in this block. Return 4 if the number
29988 of instructions >= 4. */
29990 {
29991 /* Only happen in exit blocks. */
29999 {
30000 insn_count++;
30003 }
30004 }
30007 }
30010 /* Count the minimum number of instructions in code path in BB.
30011 Return 4 if the number of instructions >= 4. */
30013 static int
30015 {
30016 edge e;
30017 edge_iterator ei;
30020 /* Only bother counting instructions along paths with no
30021 more than 2 basic blocks between entry and exit. Given
30022 that BB has an edge to exit, determine if a predecessor
30023 of BB has an edge from entry. If so, compute the number
30024 of instructions in the predecessor block. If there
30025 happen to be multiple such blocks, compute the minimum. */
30028 {
30029 edge prev_e;
30030 edge_iterator prev_ei;
30033 {
30036 }
30038 {
30040 {
30045 }
30046 }
30047 }
30053 }
30055 /* Pad short funtion to 4 instructions. */
30057 static void
30059 {
30060 edge e;
30061 edge_iterator ei;
30064 {
30067 {
30070 /* Pad short function. */
30072 {
30075 /* Find epilogue. */
30084 /* Two NOPs count as one instruction. */
30087 }
30088 }
30089 }
30090 }
30092 /* Implement machine specific optimizations. We implement padding of returns
30093 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
30094 static void
30096 {
30097 /* We are freeing block_for_insn in the toplev to keep compatibility
30098 with old MDEP_REORGS that are not CFG based. Recompute it now. */
30102 {
30107 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
30110 #endif
30111 }
30113 /* Run the vzeroupper optimization if needed. */
30116 }
30118 /* Return nonzero when QImode register that must be represented via REX prefix
30119 is used. */
30120 bool
30122 {
30130 }
30132 /* Return nonzero when P points to register encoded via REX prefix.
30133 Called via for_each_rtx. */
30134 static int
30136 {
30142 }
30144 /* Return true when INSN mentions register that must be encoded using REX
30145 prefix. */
30146 bool
30148 {
30151 }
30153 /* If profitable, negate (without causing overflow) integer constant
30154 of mode MODE at location LOC. Return true in this case. */
30155 bool
30157 {
30158 HOST_WIDE_INT val;
30164 {
30166 /* DImode x86_64 constants must fit in 32 bits. */
30179 }
30181 /* Avoid overflows. */
30187 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
30188 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
30191 {
30194 }
30197 }
30199 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
30200 optabs would emit if we didn't have TFmode patterns. */
30202 void
30204 {
30238 }
30239 \f
30240 /* AVX does not support 32-byte integer vector operations,
30241 thus the longest vector we are faced with is V16QImode. */
30242 #define MAX_VECT_LEN 16
30244 struct expand_vec_perm_d
30245 {
30251 };
30256 /* Get a vector mode of the same size as the original but with elements
30257 twice as wide. This is only guaranteed to apply to integral vectors. */
30261 {
30262 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
30267 }
30269 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30270 with all elements equal to VAR. Return true if successful. */
30272 static bool
30275 {
30279 {
30284 /* FALLTHRU */
30294 {
30297 /* First attempt to recognize VAL as-is. */
30301 {
30302 rtx seq;
30303 /* If that fails, force VAL into a register. */
30314 }
30315 }
30322 {
30323 rtx x;
30330 }
30340 {
30344 permute:
30351 /* Extend to SImode using a paradoxical SUBREG. */
30355 /* Insert the SImode value as low element of a V4SImode vector. */
30363 }
30371 widen:
30372 /* Replicate the value once into the next wider mode and recurse. */
30373 {
30375 rtx x;
30391 }
30395 {
30404 }
30409 }
30410 }
30412 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30413 whose ONE_VAR element is VAR, and other elements are zero. Return true
30414 if successful. */
30416 static bool
30419 {
30421 rtx new_target;
30426 {
30428 /* For SSE4.1, we normally use vector set. But if the second
30429 element is zero and inter-unit moves are OK, we use movq
30430 instead. */
30431 use_vector_set = (TARGET_64BIT
30432 && TARGET_SSE4_1
30433 && !(TARGET_INTER_UNIT_MOVES
30455 /* Use ix86_expand_vector_set in 64bit mode only. */
30460 }
30463 {
30468 }
30471 {
30476 /* FALLTHRU */
30491 else
30498 {
30499 /* We need to shuffle the value to the correct position, so
30500 create a new pseudo to store the intermediate result. */
30502 /* With SSE2, we can use the integer shuffle insns. */
30504 {
30506 const1_rtx,
30513 }
30515 /* Otherwise convert the intermediate result to V4SFmode and
30516 use the SSE1 shuffle instructions. */
30518 {
30521 }
30522 else
30526 const1_rtx,
30535 }
30550 widen:
30554 /* Zero extend the variable element to SImode and recurse. */
30567 }
30568 }
30570 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30571 consisting of the values in VALS. It is known that all elements
30572 except ONE_VAR are constants. Return true if successful. */
30574 static bool
30577 {
30587 {
30592 /* For the two element vectors, it's just as easy to use
30593 the general case. */
30597 /* Use ix86_expand_vector_set in 64bit mode only. */
30619 widen:
30620 /* There's no way to set one QImode entry easily. Combine
30621 the variable value with its adjacent constant value, and
30622 promote to an HImode set. */
30625 {
30630 }
30631 else
30632 {
30635 }
30649 }
30654 }
30656 /* A subroutine of ix86_expand_vector_init_general. Use vector
30657 concatenate to handle the most general case: all values variable,
30658 and none identical. */
30660 static void
30663 {
30666 rtvec v;
30670 {
30673 {
30706 }
30719 {
30734 }
30739 {
30750 }
30753 half:
30754 /* FIXME: We process inputs backward to help RA. PR 36222. */
30758 {
30763 }
30767 {
30770 {
30774 }
30777 }
30778 else
30784 }
30785 }
30787 /* A subroutine of ix86_expand_vector_init_general. Use vector
30788 interleave to handle the most general case: all values variable,
30789 and none identical. */
30791 static void
30794 {
30803 {
30824 }
30827 {
30828 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
30832 /* Insert the SImode value as low element of V4SImode vector. */
30836 op0),
30838 const1_rtx);
30841 /* Cast the V4SImode vector back to a vector in orignal mode. */
30845 /* Load even elements into the second positon. */
30849 const1_rtx));
30851 /* Cast vector to FIRST_IMODE vector. */
30854 }
30856 /* Interleave low FIRST_IMODE vectors. */
30858 {
30862 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
30865 }
30867 /* Interleave low SECOND_IMODE vectors. */
30869 {
30872 {
30877 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
30878 vector. */
30881 }
30884 /* FALLTHRU */
30891 /* Cast the SECOND_IMODE vector back to a vector on original
30892 mode. */
30899 }
30900 }
30902 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
30903 all values variable, and none identical. */
30905 static void
30908 {
30914 {
30919 /* FALLTHRU */
30943 half:
30960 /* FALLTHRU */
30966 /* Don't use ix86_expand_vector_init_interleave if we can't
30967 move from GPR to SSE register directly. */
30983 }
30985 {
30997 {
31001 {
31007 else
31008 {
31013 }
31014 }
31017 }
31022 {
31028 }
31030 {
31036 }
31037 else
31039 }
31040 }
31042 /* Initialize vector TARGET via VALS. Suppress the use of MMX
31043 instructions unless MMX_OK is true. */
31045 void
31047 {
31054 rtx x;
31057 {
31067 }
31069 /* Constants are best loaded from the constant pool. */
31071 {
31074 }
31076 /* If all values are identical, broadcast the value. */
31082 /* Values where only one field is non-constant are best loaded from
31083 the pool and overwritten via move later. */
31085 {
31089 one_var))
31094 }
31097 }
31099 void
31101 {
31106 rtx tmp;
31108 = {
31115 };
31117 = {
31124 };
31128 {
31132 {
31137 else
31141 }
31150 {
31153 /* For the two element vectors, we implement a VEC_CONCAT with
31154 the extraction of the other element. */
31161 else
31166 }
31175 {
31181 /* tmp = target = A B C D */
31183 /* target = A A B B */
31185 /* target = X A B B */
31187 /* target = A X C D */
31194 /* tmp = target = A B C D */
31196 /* tmp = X B C D */
31198 /* target = A B X D */
31205 /* tmp = target = A B C D */
31207 /* tmp = X B C D */
31209 /* target = A B X D */
31217 }
31225 /* Element 0 handled by vec_merge below. */
31227 {
31230 }
31233 {
31234 /* With SSE2, use integer shuffles to swap element 0 and ELT,
31235 store into element 0, then shuffle them back. */
31252 }
31253 else
31254 {
31255 /* For SSE1, we have to reuse the V4SF code. */
31258 }
31311 half:
31312 /* Compute offset. */
31318 /* Extract the half. */
31322 /* Put val in tmp at elt. */
31325 /* Put it back. */
31331 }
31334 {
31338 }
31339 else
31340 {
31349 }
31350 }
31352 void
31354 {
31358 rtx tmp;
31361 {
31366 /* FALLTHRU */
31379 {
31399 }
31411 {
31413 {
31433 }
31437 }
31438 else
31439 {
31440 /* For SSE1, we have to reuse the V4SF code. */
31444 }
31459 /* ??? Could extract the appropriate HImode element and shift. */
31462 }
31465 {
31469 /* Let the rtl optimizers know about the zero extension performed. */
31471 {
31474 }
31477 }
31478 else
31479 {
31486 }
31487 }
31489 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
31490 pattern to reduce; DEST is the destination; IN is the input vector. */
31492 void
31494 {
31508 }
31509 \f
31510 /* Target hook for scalar_mode_supported_p. */
31511 static bool
31513 {
31518 else
31520 }
31522 /* Implements target hook vector_mode_supported_p. */
31523 static bool
31525 {
31537 }
31539 /* Target hook for c_mode_for_suffix. */
31540 static enum machine_mode
31542 {
31549 }
31551 /* Worker function for TARGET_MD_ASM_CLOBBERS.
31553 We do this in the new i386 backend to maintain source compatibility
31554 with the old cc0-based compiler. */
31556 static tree
31558 tree inputs ATTRIBUTE_UNUSED,
31559 tree clobbers)
31560 {
31562 clobbers);
31564 clobbers);
31566 }
31568 /* Implements target vector targetm.asm.encode_section_info. This
31569 is not used by netware. */
31571 static void ATTRIBUTE_UNUSED
31573 {
31580 }
31582 /* Worker function for REVERSE_CONDITION. */
31584 enum rtx_code
31586 {
31590 }
31592 /* Output code to perform an x87 FP register move, from OPERANDS[1]
31593 to OPERANDS[0]. */
31597 {
31599 {
31602 {
31606 }
31610 }
31612 {
31616 else
31617 {
31618 /* There is no non-popping store to memory for XFmode.
31619 So if we need one, follow the store with a load. */
31622 else
31624 }
31625 }
31626 else
31628 }
31630 /* Output code to perform a conditional jump to LABEL, if C2 flag in
31631 FP status register is set. */
31633 void
31635 {
31637 rtx temp;
31642 {
31647 }
31648 else
31649 {
31654 }
31658 pc_rtx);
31663 }
31665 /* Output code to perform a log1p XFmode calculation. */
31668 {
31674 rtx test;
31680 XFmode));
31694 }
31696 /* Output code to perform a Newton-Rhapson approximation of a single precision
31697 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
31700 {
31715 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
31717 /* x0 = rcp(b) estimate */
31720 UNSPEC_RCP)));
31721 /* e0 = x0 * a */
31724 /* e1 = x0 * b */
31727 /* x1 = 2. - e1 */
31730 /* res = e0 * x1 */
31733 }
31735 /* Output code to perform a Newton-Rhapson approximation of a
31736 single precision floating point [reciprocal] square root. */
31740 {
31742 REAL_VALUE_TYPE r;
31757 {
31760 }
31762 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
31763 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
31765 /* x0 = rsqrt(a) estimate */
31768 UNSPEC_RSQRT)));
31770 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
31772 {
31784 }
31786 /* e0 = x0 * a */
31789 /* e1 = e0 * x0 */
31793 /* e2 = e1 - 3. */
31800 /* e3 = -.5 * x0 */
31803 else
31804 /* e3 = -.5 * e0 */
31807 /* ret = e2 * e3 */
31810 }
31812 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
31814 static void ATTRIBUTE_UNUSED
31816 tree decl)
31817 {
31818 /* With Binutils 2.15, the "@unwind" marker must be specified on
31819 every occurrence of the ".eh_frame" section, not just the first
31820 one. */
31823 {
31827 }
31829 }
31831 /* Return the mangling of TYPE if it is an extended fundamental type. */
31835 {
31843 {
31845 /* __float128 is "g". */
31848 /* "long double" or __float80 is "e". */
31852 }
31853 }
31855 /* For 32-bit code we can save PIC register setup by using
31856 __stack_chk_fail_local hidden function instead of calling
31857 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
31858 register, so it is better to call __stack_chk_fail directly. */
31860 static tree
31862 {
31863 return TARGET_64BIT
31866 }
31868 /* Select a format to encode pointers in exception handling data. CODE
31869 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
31870 true if the symbol may be affected by dynamic relocations.
31872 ??? All x86 object file formats are capable of representing this.
31873 After all, the relocation needed is the same as for the call insn.
31874 Whether or not a particular assembler allows us to enter such, I
31875 guess we'll have to see. */
31876 int
31878 {
31880 {
31887 }
31892 }
31893 \f
31894 /* Expand copysign from SIGN to the positive value ABS_VALUE
31895 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
31896 the sign-bit. */
31897 static void
31899 {
31903 {
31910 else
31915 {
31916 /* We need to generate a scalar mode mask in this case. */
31921 }
31922 }
31923 else
31929 }
31931 /* Expand fabs (OP0) and return a new rtx that holds the result. The
31932 mask for masking out the sign-bit is stored in *SMASK, if that is
31933 non-null. */
31934 static rtx
31936 {
31945 else
31949 {
31950 /* We need to generate a scalar mode mask in this case. */
31955 }
31963 }
31965 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
31966 swapping the operands if SWAP_OPERANDS is true. The expanded
31967 code is a forward jump to a newly created label in case the
31968 comparison is true. The generated label rtx is returned. */
31969 static rtx
31972 {
31976 {
31980 }
31993 }
31995 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
31996 using comparison code CODE. Operands are swapped for the comparison if
31997 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
31998 static rtx
32001 {
32006 {
32010 }
32015 else
32020 }
32022 /* Generate and return a rtx of mode MODE for 2**n where n is the number
32023 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
32024 static rtx
32026 {
32027 REAL_VALUE_TYPE TWO52r;
32028 rtx TWO52;
32035 }
32037 /* Expand SSE sequence for computing lround from OP1 storing
32038 into OP0. */
32039 void
32041 {
32042 /* C code for the stuff we're doing below:
32043 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
32044 return (long)tmp;
32045 */
32049 rtx adj;
32051 /* load nextafter (0.5, 0.0) */
32056 /* adj = copysign (0.5, op1) */
32060 /* adj = op1 + adj */
32063 /* op0 = (imode)adj */
32065 }
32067 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
32068 into OPERAND0. */
32069 void
32071 {
32072 /* C code for the stuff we're doing below (for do_floor):
32073 xi = (long)op1;
32074 xi -= (double)xi > op1 ? 1 : 0;
32075 return xi;
32076 */
32081 /* reg = (long)op1 */
32085 /* freg = (double)reg */
32089 /* ireg = (freg > op1) ? ireg - 1 : ireg */
32100 }
32102 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
32103 result in OPERAND0. */
32104 void
32106 {
32107 /* C code for the stuff we're doing below:
32108 xa = fabs (operand1);
32109 if (!isless (xa, 2**52))
32110 return operand1;
32111 xa = xa + 2**52 - 2**52;
32112 return copysign (xa, operand1);
32113 */
32120 /* xa = abs (operand1) */
32123 /* if (!isless (xa, TWO52)) goto label; */
32136 }
32138 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
32139 into OPERAND0. */
32140 void
32142 {
32143 /* C code for the stuff we expand below.
32144 double xa = fabs (x), x2;
32145 if (!isless (xa, TWO52))
32146 return x;
32147 xa = xa + TWO52 - TWO52;
32148 x2 = copysign (xa, x);
32149 Compensate. Floor:
32150 if (x2 > x)
32151 x2 -= 1;
32152 Compensate. Ceil:
32153 if (x2 < x)
32154 x2 -= -1;
32155 return x2;
32156 */
32162 /* Temporary for holding the result, initialized to the input
32163 operand to ease control flow. */
32167 /* xa = abs (operand1) */
32170 /* if (!isless (xa, TWO52)) goto label; */
32173 /* xa = xa + TWO52 - TWO52; */
32177 /* xa = copysign (xa, operand1) */
32180 /* generate 1.0 or -1.0 */
32185 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32189 /* We always need to subtract here to preserve signed zero. */
32198 }
32200 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
32201 into OPERAND0. */
32202 void
32204 {
32205 /* C code for the stuff we expand below.
32206 double xa = fabs (x), x2;
32207 if (!isless (xa, TWO52))
32208 return x;
32209 x2 = (double)(long)x;
32210 Compensate. Floor:
32211 if (x2 > x)
32212 x2 -= 1;
32213 Compensate. Ceil:
32214 if (x2 < x)
32215 x2 += 1;
32216 if (HONOR_SIGNED_ZEROS (mode))
32217 return copysign (x2, x);
32218 return x2;
32219 */
32225 /* Temporary for holding the result, initialized to the input
32226 operand to ease control flow. */
32230 /* xa = abs (operand1) */
32233 /* if (!isless (xa, TWO52)) goto label; */
32236 /* xa = (double)(long)x */
32241 /* generate 1.0 */
32244 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32259 }
32261 /* Expand SSE sequence for computing round from OPERAND1 storing
32262 into OPERAND0. Sequence that works without relying on DImode truncation
32263 via cvttsd2siq that is only available on 64bit targets. */
32264 void
32266 {
32267 /* C code for the stuff we expand below.
32268 double xa = fabs (x), xa2, x2;
32269 if (!isless (xa, TWO52))
32270 return x;
32271 Using the absolute value and copying back sign makes
32272 -0.0 -> -0.0 correct.
32273 xa2 = xa + TWO52 - TWO52;
32274 Compensate.
32275 dxa = xa2 - xa;
32276 if (dxa <= -0.5)
32277 xa2 += 1;
32278 else if (dxa > 0.5)
32279 xa2 -= 1;
32280 x2 = copysign (xa2, x);
32281 return x2;
32282 */
32288 /* Temporary for holding the result, initialized to the input
32289 operand to ease control flow. */
32293 /* xa = abs (operand1) */
32296 /* if (!isless (xa, TWO52)) goto label; */
32299 /* xa2 = xa + TWO52 - TWO52; */
32303 /* dxa = xa2 - xa; */
32306 /* generate 0.5, 1.0 and -0.5 */
32312 /* Compensate. */
32314 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
32319 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
32325 /* res = copysign (xa2, operand1) */
32332 }
32334 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32335 into OPERAND0. */
32336 void
32338 {
32339 /* C code for SSE variant we expand below.
32340 double xa = fabs (x), x2;
32341 if (!isless (xa, TWO52))
32342 return x;
32343 x2 = (double)(long)x;
32344 if (HONOR_SIGNED_ZEROS (mode))
32345 return copysign (x2, x);
32346 return x2;
32347 */
32353 /* Temporary for holding the result, initialized to the input
32354 operand to ease control flow. */
32358 /* xa = abs (operand1) */
32361 /* if (!isless (xa, TWO52)) goto label; */
32364 /* x = (double)(long)x */
32376 }
32378 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32379 into OPERAND0. */
32380 void
32382 {
32386 /* C code for SSE variant we expand below.
32387 double xa = fabs (x), x2;
32388 if (!isless (xa, TWO52))
32389 return x;
32390 xa2 = xa + TWO52 - TWO52;
32391 Compensate:
32392 if (xa2 > xa)
32393 xa2 -= 1.0;
32394 x2 = copysign (xa2, x);
32395 return x2;
32396 */
32400 /* Temporary for holding the result, initialized to the input
32401 operand to ease control flow. */
32405 /* xa = abs (operand1) */
32408 /* if (!isless (xa, TWO52)) goto label; */
32411 /* res = xa + TWO52 - TWO52; */
32416 /* generate 1.0 */
32419 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
32427 /* res = copysign (res, operand1) */
32434 }
32436 /* Expand SSE sequence for computing round from OPERAND1 storing
32437 into OPERAND0. */
32438 void
32440 {
32441 /* C code for the stuff we're doing below:
32442 double xa = fabs (x);
32443 if (!isless (xa, TWO52))
32444 return x;
32445 xa = (double)(long)(xa + nextafter (0.5, 0.0));
32446 return copysign (xa, x);
32447 */
32453 /* Temporary for holding the result, initialized to the input
32454 operand to ease control flow. */
32462 /* load nextafter (0.5, 0.0) */
32467 /* xa = xa + 0.5 */
32471 /* xa = (double)(int64_t)xa */
32476 /* res = copysign (xa, operand1) */
32483 }
32484 \f
32486 /* Table of valid machine attributes. */
32488 {
32489 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
32490 /* Stdcall attribute says callee is responsible for popping arguments
32491 if they are not variable. */
32493 /* Fastcall attribute says callee is responsible for popping arguments
32494 if they are not variable. */
32496 /* Thiscall attribute says callee is responsible for popping arguments
32497 if they are not variable. */
32499 /* Cdecl attribute says the callee is a normal C declaration */
32501 /* Regparm attribute specifies how many integer arguments are to be
32502 passed in registers. */
32504 /* Sseregparm attribute says we are using x86_64 calling conventions
32505 for FP arguments. */
32507 /* force_align_arg_pointer says this function realigns the stack at entry. */
32510 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
32514 #endif
32517 #ifdef SUBTARGET_ATTRIBUTE_TABLE
32518 SUBTARGET_ATTRIBUTE_TABLE,
32519 #endif
32520 /* ms_abi and sysv_abi calling convention function attributes. */
32525 ix86_handle_callee_pop_aggregate_return },
32526 /* End element. */
32528 };
32530 /* Implement targetm.vectorize.builtin_vectorization_cost. */
32531 static int
32533 tree vectype ATTRIBUTE_UNUSED,
32535 {
32537 {
32577 }
32578 }
32581 /* Implement targetm.vectorize.builtin_vec_perm. */
32583 static tree
32585 {
32593 {
32600 get_di:
32611 get_si:
32630 }
32637 }
32639 /* Return a vector mode with twice as many elements as VMODE. */
32640 /* ??? Consider moving this to a table generated by genmodes.c. */
32642 static enum machine_mode
32644 {
32646 {
32669 }
32670 }
32672 /* Construct (set target (vec_select op0 (parallel perm))) and
32673 return true if that's a valid instruction in the active ISA. */
32675 static bool
32677 {
32690 {
32693 }
32695 }
32697 /* Similar, but generate a vec_concat from op0 and op1 as well. */
32699 static bool
32702 {
32704 rtx x;
32709 }
32711 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32712 in terms of blendp[sd] / pblendw / pblendvb. */
32714 static bool
32716 {
32726 /* This is a blend, not a permute. Elements must stay in their
32727 respective lanes. */
32729 {
32733 }
32738 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
32739 decision should be extracted elsewhere, so that we only try that
32740 sequence once all budget==3 options have been tried. */
32742 /* For bytes, see if bytes move in pairs so we can use pblendw with
32743 an immediate argument, rather than pblendvb with a vector argument. */
32745 {
32751 {
32762 }
32763 }
32771 {
32795 do_subreg:
32804 }
32806 /* This matches five different patterns with the different modes. */
32812 }
32814 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32815 in terms of the variable form of vpermilps.
32817 Note that we will have already failed the immediate input vpermilps,
32818 which requires that the high and low part shuffle be identical; the
32819 variable form doesn't require that. */
32821 static bool
32823 {
32830 /* We can only permute within the 128-bit lane. */
32832 {
32836 }
32842 {
32845 /* Within each 128-bit lane, the elements of op0 are numbered
32846 from 0 and the elements of op1 are numbered from 4. */
32853 }
32860 }
32862 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32863 in terms of pshufb or vpperm. */
32865 static bool
32867 {
32883 {
32887 }
32896 else
32897 {
32900 }
32903 }
32905 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
32906 in a single instruction. */
32908 static bool
32910 {
32914 /* Check plain VEC_SELECT first, because AVX has instructions that could
32915 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
32916 input where SEL+CONCAT may not. */
32918 {
32927 /* There are plenty of patterns in sse.md that are written for
32928 SEL+CONCAT and are not replicated for a single op. Perhaps
32929 that should be changed, to avoid the nastiness here. */
32931 /* Recognize interleave style patterns, which means incrementing
32932 every other permutation operand. */
32934 {
32937 }
32941 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
32943 {
32945 {
32950 }
32954 }
32955 }
32957 /* Finally, try the fully general two operand permute. */
32961 /* Recognize interleave style patterns with reversed operands. */
32963 {
32965 {
32969 else
32972 }
32976 }
32978 /* Try the SSE4.1 blend variable merge instructions. */
32982 /* Try one of the AVX vpermil variable permutations. */
32986 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
32991 }
32993 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32994 in terms of a pair of pshuflw + pshufhw instructions. */
32996 static bool
32998 {
33006 /* The two permutations only operate in 64-bit lanes. */
33017 /* Emit the pshuflw. */
33024 /* Emit the pshufhw. */
33032 }
33034 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
33035 the permutation using the SSSE3 palignr instruction. This succeeds
33036 when all of the elements in PERM fit within one vector and we merely
33037 need to shift them down so that a single vector permutation has a
33038 chance to succeed. */
33040 static bool
33042 {
33046 rtx shift;
33048 /* Even with AVX, palignr only operates on 128-bit vectors. */
33054 {
33060 }
33064 /* Given that we have SSSE3, we know we'll be able to implement the
33065 single operand permutation after the palignr with pshufb. */
33078 {
33083 }
33085 /* Test for the degenerate case where the alignment by itself
33086 produces the desired permutation. */
33094 }
33096 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
33097 a two vector permutation into a single vector permutation by using
33098 an interleave operation to merge the vectors. */
33100 static bool
33102 {
33107 rtx seq;
33113 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
33114 lanes. We can use similar techniques with the vperm2f128 instruction,
33115 but it requires slightly different logic. */
33119 /* Examine from whence the elements come. */
33124 /* Split the two input vectors into 4 halves. */
33133 /* If the elements from the low halves use interleave low, and similarly
33134 for interleave high. If the elements are from mis-matched halves, we
33135 can use shufps for V4SF/V4SI or do a DImode shuffle. */
33137 {
33139 {
33144 }
33145 }
33147 {
33149 {
33154 }
33155 }
33157 {
33159 {
33164 }
33166 {
33171 }
33172 }
33174 {
33176 {
33181 }
33183 {
33188 }
33189 }
33190 else
33193 /* Use the remapping array set up above to move the elements from their
33194 swizzled locations into their final destinations. */
33197 {
33201 }
33206 /* Test if the final remap can be done with a single insn. For V4SFmode or
33207 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
33217 {
33221 }
33228 }
33230 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
33231 permutation with two pshufb insns and an ior. We should have already
33232 failed all two instruction sequences. */
33234 static bool
33236 {
33247 /* Generate two permutation masks. If the required element is within
33248 the given vector it is shuffled into the proper lane. If the required
33249 element is in the other vector, force a zero into the lane by setting
33250 bit 7 in the permutation mask. */
33253 {
33260 {
33263 }
33264 }
33284 }
33286 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
33287 and extract-odd permutations. */
33289 static bool
33291 {
33295 {
33300 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
33304 /* Now an unpck[lh]pd will produce the result required. */
33307 else
33313 {
33320 /* Shuffle within the 128-bit lanes to produce:
33321 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
33325 /* Shuffle the lanes around to produce:
33326 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
33330 /* Shuffle within the 128-bit lanes to produce:
33331 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
33334 /* Shuffle within the 128-bit lanes to produce:
33335 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
33338 /* Shuffle the lanes around to produce:
33339 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
33342 }
33349 /* These are always directly implementable by expand_vec_perm_1. */
33355 else
33356 {
33357 /* We need 2*log2(N)-1 operations to achieve odd/even
33358 with interleave. */
33367 else
33370 }
33376 else
33377 {
33389 else
33392 }
33397 }
33400 }
33402 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33403 extract-even and extract-odd permutations. */
33405 static bool
33407 {
33419 }
33421 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
33422 permutations. We assume that expand_vec_perm_1 has already failed. */
33424 static bool
33426 {
33434 {
33437 /* These are special-cased in sse.md so that we can optionally
33438 use the vbroadcast instruction. They expand to two insns
33439 if the input happens to be in a register. */
33446 /* These are always implementable using standard shuffle patterns. */
33451 /* These can be implemented via interleave. We save one insn by
33452 stopping once we have promoted to V4SImode and then use pshufd. */
33453 do
33454 {
33458 {
33461 }
33467 }
33477 }
33478 }
33480 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33481 broadcast permutations. */
33483 static bool
33485 {
33497 }
33499 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
33500 With all of the interface bits taken care of, perform the expansion
33501 in D and return true on success. */
33503 static bool
33505 {
33506 /* Try a single instruction expansion. */
33510 /* Try sequences of two instructions. */
33524 /* Try sequences of three instructions. */
33529 /* ??? Look for narrow permutations whose element orderings would
33530 allow the promotion to a wider mode. */
33532 /* ??? Look for sequences of interleave or a wider permute that place
33533 the data into the correct lanes for a half-vector shuffle like
33534 pshuf[lh]w or vpermilps. */
33536 /* ??? Look for sequences of interleave that produce the desired results.
33537 The combinatorics of punpck[lh] get pretty ugly... */
33543 }
33545 /* Extract the values from the vector CST into the permutation array in D.
33546 Return 0 on error, 1 if all values from the permutation come from the
33547 first vector, 2 if all values from the second vector, and 3 otherwise. */
33549 static int
33551 {
33557 {
33568 }
33571 /* For all elements from second vector, fold the elements to first. */
33577 }
33579 static rtx
33581 {
33595 {
33599 }
33602 {
33612 {
33618 }
33620 /* The elements of PERM do not suggest that only the first operand
33621 is used, but both operands are identical. Allow easier matching
33622 of the permutation by folding the permutation into the single
33623 input vector. */
33624 {
33629 }
33630 /* FALLTHRU */
33643 }
33649 /* For compiler generated permutations, we should never got here, because
33650 the compiler should also be checking the ok hook. But since this is a
33651 builtin the user has access too, so don't abort. */
33653 {
33676 }
33677 exit_error:
33679 }
33681 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
33683 static bool
33685 {
33694 /* Given sufficient ISA support we can just return true here
33695 for selected vector modes. */
33697 {
33698 /* All implementable with a single vpperm insn. */
33701 /* All implementable with 2 pshufb + 1 ior. */
33704 /* All implementable with shufpd or unpck[lh]pd. */
33707 }
33711 /* This hook is cannot be called in response to something that the
33712 user does (unlike the builtin expander) so we shouldn't ever see
33713 an error generated from the extract. */
33717 /* Implementable with shufps or pshufd. */
33721 /* Otherwise we have to go through the motions and see if we can
33722 figure out how to generate the requested permutation. */
33733 }
33735 void
33737 {
33751 /* We'll either be able to implement the permutation directly... */
33755 /* ... or we use the special-case patterns. */
33757 }
33758 \f
33759 /* This function returns the calling abi specific va_list type node.
33760 It returns the FNDECL specific va_list type. */
33762 static tree
33764 {
33771 else
33773 }
33775 /* Returns the canonical va_list type specified by TYPE. If there
33776 is no valid TYPE provided, it return NULL_TREE. */
33778 static tree
33780 {
33783 /* Resolve references and pointers to va_list type. */
33792 {
33797 {
33798 /* If va_list is an array type, the argument may have decayed
33799 to a pointer type, e.g. by being passed to another function.
33800 In that case, unwrap both types so that we can compare the
33801 underlying records. */
33804 {
33807 }
33808 }
33815 {
33816 /* If va_list is an array type, the argument may have decayed
33817 to a pointer type, e.g. by being passed to another function.
33818 In that case, unwrap both types so that we can compare the
33819 underlying records. */
33822 {
33825 }
33826 }
33833 {
33834 /* If va_list is an array type, the argument may have decayed
33835 to a pointer type, e.g. by being passed to another function.
33836 In that case, unwrap both types so that we can compare the
33837 underlying records. */
33840 {
33843 }
33844 }
33848 }
33850 }
33852 /* Iterate through the target-specific builtin types for va_list.
33853 IDX denotes the iterator, *PTREE is set to the result type of
33854 the va_list builtin, and *PNAME to its internal type.
33855 Returns zero if there is no element for this index, otherwise
33856 IDX should be increased upon the next call.
33857 Note, do not iterate a base builtin's name like __builtin_va_list.
33858 Used from c_common_nodes_and_builtins. */
33860 static int
33862 {
33864 {
33866 {
33879 }
33880 }
33883 }
33885 #undef TARGET_SCHED_DISPATCH
33886 #define TARGET_SCHED_DISPATCH has_dispatch
33887 #undef TARGET_SCHED_DISPATCH_DO
33888 #define TARGET_SCHED_DISPATCH_DO do_dispatch
33890 /* The size of the dispatch window is the total number of bytes of
33891 object code allowed in a window. */
33892 #define DISPATCH_WINDOW_SIZE 16
33894 /* Number of dispatch windows considered for scheduling. */
33895 #define MAX_DISPATCH_WINDOWS 3
33897 /* Maximum number of instructions in a window. */
33898 #define MAX_INSN 4
33900 /* Maximum number of immediate operands in a window. */
33901 #define MAX_IMM 4
33903 /* Maximum number of immediate bits allowed in a window. */
33904 #define MAX_IMM_SIZE 128
33906 /* Maximum number of 32 bit immediates allowed in a window. */
33907 #define MAX_IMM_32 4
33909 /* Maximum number of 64 bit immediates allowed in a window. */
33910 #define MAX_IMM_64 2
33912 /* Maximum total of loads or prefetches allowed in a window. */
33913 #define MAX_LOAD 2
33915 /* Maximum total of stores allowed in a window. */
33916 #define MAX_STORE 1
33918 #undef BIG
33919 #define BIG 100
33922 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
33925 disp_load,
33926 disp_store,
33927 disp_load_store,
33928 disp_prefetch,
33929 disp_imm,
33930 disp_imm_32,
33931 disp_imm_64,
33932 disp_branch,
33933 disp_cmp,
33934 disp_jcc,
33935 disp_last
33936 };
33938 /* Number of allowable groups in a dispatch window. It is an array
33939 indexed by dispatch_group enum. 100 is used as a big number,
33940 because the number of these kind of operations does not have any
33941 effect in dispatch window, but we need them for other reasons in
33942 the table. */
33945 };
33951 };
33953 /* Instruction path. */
33959 last_path
33960 };
33962 /* sched_insn_info defines a window to the instructions scheduled in
33963 the basic block. It contains a pointer to the insn_info table and
33964 the instruction scheduled.
33966 Windows are allocated for each basic block and are linked
33967 together. */
33969 rtx insn;
33976 /* Linked list of dispatch windows. This is a two way list of
33977 dispatch windows of a basic block. It contains information about
33978 the number of uops in the window and the total number of
33979 instructions and of bytes in the object code for this dispatch
33980 window. */
33998 /* Immediate valuse used in an insn. */
34000 {
34009 /* Get dispatch group of insn. */
34011 static enum dispatch_group
34013 {
34029 }
34031 /* Return true if insn is a compare instruction. */
34033 static bool
34035 {
34043 }
34045 /* Return true if a dispatch violation encountered. */
34047 static bool
34049 {
34053 }
34055 /* Return true if insn is a branch instruction. */
34057 static bool
34059 {
34061 }
34063 /* Return true if insn is a prefetch instruction. */
34065 static bool
34067 {
34069 }
34071 /* This function initializes a dispatch window and the list container holding a
34072 pointer to the window. */
34074 static void
34076 {
34082 else
34100 {
34106 }
34108 }
34110 /* This function allocates and initializes a dispatch window and the
34111 list container holding a pointer to the window. */
34115 {
34120 }
34122 /* This routine initializes the dispatch scheduling information. It
34123 initiates building dispatch scheduler tables and constructs the
34124 first dispatch window. */
34126 static void
34128 {
34129 /* Allocate a dispatch list and a window. */
34134 }
34136 /* This function returns true if a branch is detected. End of a basic block
34137 does not have to be a branch, but here we assume only branches end a
34138 window. */
34140 static bool
34142 {
34144 }
34146 /* This function is called when the end of a window processing is reached. */
34148 static void
34150 {
34153 {
34158 }
34160 }
34162 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
34163 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
34164 for 48 bytes of instructions. Note that these windows are not dispatch
34165 windows that their sizes are DISPATCH_WINDOW_SIZE. */
34169 {
34171 {
34176 }
34182 }
34184 /* Increment the number of immediate operands of an instruction. */
34186 static int
34188 {
34193 {
34200 else
34211 {
34214 }
34219 }
34222 }
34224 /* Compute number of immediate operands of an instruction. */
34226 static void
34228 {
34231 }
34233 /* Return total size of immediate operands of an instruction along with number
34234 of corresponding immediate-operands. It initializes its parameters to zero
34235 befor calling FIND_CONSTANT.
34236 INSN is the input instruction. IMM is the total of immediates.
34237 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
34238 bit immediates. */
34240 static int
34242 {
34250 }
34252 /* This function indicates if an operand of an instruction is an
34253 immediate. */
34255 static bool
34257 {
34266 }
34268 /* Return single or double path for instructions. */
34270 static enum insn_path
34272 {
34282 }
34284 /* Return insn dispatch group. */
34286 static enum dispatch_group
34288 {
34306 }
34308 /* Count number of GROUP restricted instructions in a dispatch
34309 window WINDOW_LIST. */
34311 static int
34313 {
34324 {
34343 }
34356 }
34358 /* This function returns true if insn satisfies dispatch rules on the
34359 last window scheduled. */
34361 static bool
34363 {
34371 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
34372 instructions should be given the lowest priority in the
34373 scheduling process in Haifa scheduler to make sure they will be
34374 scheduled in the same dispatch window as the refrence to them. */
34378 /* Check nonrestricted. */
34382 /* Get last dispatch window. */
34387 {
34392 /* Window 1 is full. Go for next window. */
34394 }
34401 /* See if it fits in the first window. */
34403 {
34404 /* The first widow should have only single and double path
34405 uops. */
34411 }
34413 }
34415 /* Add an instruction INSN with NUM_UOPS micro-operations to the
34416 dispatch window WINDOW_LIST. */
34418 static void
34420 {
34438 /* Initialize window with new instruction. */
34459 {
34462 }
34463 }
34465 /* Adds a scheduled instruction, INSN, to the current dispatch window.
34466 If the total bytes of instructions or the number of instructions in
34467 the window exceed allowable, it allocates a new window. */
34469 static void
34471 {
34494 /* Get the last dispatch window. */
34502 else
34505 /* If current window is full, get a new window.
34506 Window number zero is full, if MAX_INSN uops are scheduled in it.
34507 Window number one is full, if window zero's bytes plus window
34508 one's bytes is 32, or if the bytes of the new instruction added
34509 to the total makes it greater than 48, or it has already MAX_INSN
34510 instructions in it. */
34519 {
34522 }
34525 {
34529 {
34532 }
34533 }
34535 {
34540 {
34543 }
34546 }
34547 else
34551 {
34552 /* End of basic block is reached do end-basic-block process. */
34555 }
34556 }
34558 /* Print the dispatch window, WINDOW_NUM, to FILE. */
34560 DEBUG_FUNCTION static void
34562 {
34568 else
34582 {
34585 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
34591 }
34592 }
34594 /* Print to stdout a dispatch window. */
34596 DEBUG_FUNCTION void
34598 {
34600 }
34602 /* Print INSN dispatch information to FILE. */
34604 DEBUG_FUNCTION static void
34606 {
34629 }
34631 /* Print to STDERR the status of the ready list with respect to
34632 dispatch windows. */
34634 DEBUG_FUNCTION void
34636 {
34644 }
34646 /* This routine is the driver of the dispatch scheduler. */
34648 static void
34650 {
34655 }
34657 /* Return TRUE if Dispatch Scheduling is supported. */
34659 static bool
34661 {
34664 {
34680 }
34683 }
34685 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
34686 place emms and femms instructions. */
34688 static enum machine_mode
34690 {
34691 /* Disable double precision vectorizer if needed. */
34699 {
34714 }
34717 }
34719 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
34720 vectors. */
34722 static unsigned int
34724 {
34726 }
34728 /* Initialize the GCC target structure. */
34729 #undef TARGET_RETURN_IN_MEMORY
34730 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
34732 #undef TARGET_LEGITIMIZE_ADDRESS
34733 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
34735 #undef TARGET_ATTRIBUTE_TABLE
34736 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
34737 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
34738 # undef TARGET_MERGE_DECL_ATTRIBUTES
34739 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
34740 #endif
34742 #undef TARGET_COMP_TYPE_ATTRIBUTES
34743 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
34745 #undef TARGET_INIT_BUILTINS
34746 #define TARGET_INIT_BUILTINS ix86_init_builtins
34747 #undef TARGET_BUILTIN_DECL
34748 #define TARGET_BUILTIN_DECL ix86_builtin_decl
34749 #undef TARGET_EXPAND_BUILTIN
34750 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
34752 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
34753 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
34754 ix86_builtin_vectorized_function
34756 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
34757 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
34759 #undef TARGET_BUILTIN_RECIPROCAL
34760 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
34762 #undef TARGET_ASM_FUNCTION_EPILOGUE
34763 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
34765 #undef TARGET_ENCODE_SECTION_INFO
34766 #ifndef SUBTARGET_ENCODE_SECTION_INFO
34767 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
34768 #else
34769 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
34770 #endif
34772 #undef TARGET_ASM_OPEN_PAREN
34774 #undef TARGET_ASM_CLOSE_PAREN
34777 #undef TARGET_ASM_BYTE_OP
34778 #define TARGET_ASM_BYTE_OP ASM_BYTE
34780 #undef TARGET_ASM_ALIGNED_HI_OP
34781 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
34782 #undef TARGET_ASM_ALIGNED_SI_OP
34783 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
34784 #ifdef ASM_QUAD
34785 #undef TARGET_ASM_ALIGNED_DI_OP
34786 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
34787 #endif
34789 #undef TARGET_PROFILE_BEFORE_PROLOGUE
34790 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
34792 #undef TARGET_ASM_UNALIGNED_HI_OP
34793 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
34794 #undef TARGET_ASM_UNALIGNED_SI_OP
34795 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
34796 #undef TARGET_ASM_UNALIGNED_DI_OP
34797 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
34799 #undef TARGET_PRINT_OPERAND
34800 #define TARGET_PRINT_OPERAND ix86_print_operand
34801 #undef TARGET_PRINT_OPERAND_ADDRESS
34802 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
34803 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
34804 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
34805 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
34806 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
34808 #undef TARGET_SCHED_INIT_GLOBAL
34809 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
34810 #undef TARGET_SCHED_ADJUST_COST
34811 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
34812 #undef TARGET_SCHED_ISSUE_RATE
34813 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
34814 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
34815 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
34816 ia32_multipass_dfa_lookahead
34818 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
34819 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
34821 #ifdef HAVE_AS_TLS
34822 #undef TARGET_HAVE_TLS
34823 #define TARGET_HAVE_TLS true
34824 #endif
34825 #undef TARGET_CANNOT_FORCE_CONST_MEM
34826 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
34827 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
34828 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
34830 #undef TARGET_DELEGITIMIZE_ADDRESS
34831 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
34833 #undef TARGET_MS_BITFIELD_LAYOUT_P
34834 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
34836 #if TARGET_MACHO
34837 #undef TARGET_BINDS_LOCAL_P
34838 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
34839 #endif
34840 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
34841 #undef TARGET_BINDS_LOCAL_P
34842 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
34843 #endif
34845 #undef TARGET_ASM_OUTPUT_MI_THUNK
34846 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
34847 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
34848 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
34850 #undef TARGET_ASM_FILE_START
34851 #define TARGET_ASM_FILE_START x86_file_start
34853 #undef TARGET_DEFAULT_TARGET_FLAGS
34854 #define TARGET_DEFAULT_TARGET_FLAGS \
34855 (TARGET_DEFAULT \
34856 | TARGET_SUBTARGET_DEFAULT \
34857 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
34859 #undef TARGET_HANDLE_OPTION
34860 #define TARGET_HANDLE_OPTION ix86_handle_option
34862 #undef TARGET_OPTION_OVERRIDE
34863 #define TARGET_OPTION_OVERRIDE ix86_option_override
34864 #undef TARGET_OPTION_OPTIMIZATION_TABLE
34865 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
34866 #undef TARGET_OPTION_INIT_STRUCT
34867 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
34869 #undef TARGET_REGISTER_MOVE_COST
34870 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
34871 #undef TARGET_MEMORY_MOVE_COST
34872 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
34873 #undef TARGET_RTX_COSTS
34874 #define TARGET_RTX_COSTS ix86_rtx_costs
34875 #undef TARGET_ADDRESS_COST
34876 #define TARGET_ADDRESS_COST ix86_address_cost
34878 #undef TARGET_FIXED_CONDITION_CODE_REGS
34879 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
34880 #undef TARGET_CC_MODES_COMPATIBLE
34881 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
34883 #undef TARGET_MACHINE_DEPENDENT_REORG
34884 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
34886 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
34887 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
34889 #undef TARGET_BUILD_BUILTIN_VA_LIST
34890 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
34892 #undef TARGET_ENUM_VA_LIST_P
34893 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
34895 #undef TARGET_FN_ABI_VA_LIST
34896 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
34898 #undef TARGET_CANONICAL_VA_LIST_TYPE
34899 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
34901 #undef TARGET_EXPAND_BUILTIN_VA_START
34902 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
34904 #undef TARGET_MD_ASM_CLOBBERS
34905 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
34907 #undef TARGET_PROMOTE_PROTOTYPES
34908 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
34909 #undef TARGET_STRUCT_VALUE_RTX
34910 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
34911 #undef TARGET_SETUP_INCOMING_VARARGS
34912 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
34913 #undef TARGET_MUST_PASS_IN_STACK
34914 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
34915 #undef TARGET_FUNCTION_ARG_ADVANCE
34916 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
34917 #undef TARGET_FUNCTION_ARG
34918 #define TARGET_FUNCTION_ARG ix86_function_arg
34919 #undef TARGET_FUNCTION_ARG_BOUNDARY
34920 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
34921 #undef TARGET_PASS_BY_REFERENCE
34922 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
34923 #undef TARGET_INTERNAL_ARG_POINTER
34924 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
34925 #undef TARGET_UPDATE_STACK_BOUNDARY
34926 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
34927 #undef TARGET_GET_DRAP_RTX
34928 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
34929 #undef TARGET_STRICT_ARGUMENT_NAMING
34930 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
34931 #undef TARGET_STATIC_CHAIN
34932 #define TARGET_STATIC_CHAIN ix86_static_chain
34933 #undef TARGET_TRAMPOLINE_INIT
34934 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
34935 #undef TARGET_RETURN_POPS_ARGS
34936 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
34938 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
34939 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
34941 #undef TARGET_SCALAR_MODE_SUPPORTED_P
34942 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
34944 #undef TARGET_VECTOR_MODE_SUPPORTED_P
34945 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
34947 #undef TARGET_C_MODE_FOR_SUFFIX
34948 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
34950 #ifdef HAVE_AS_TLS
34951 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
34952 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
34953 #endif
34955 #ifdef SUBTARGET_INSERT_ATTRIBUTES
34956 #undef TARGET_INSERT_ATTRIBUTES
34957 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
34958 #endif
34960 #undef TARGET_MANGLE_TYPE
34961 #define TARGET_MANGLE_TYPE ix86_mangle_type
34963 #undef TARGET_STACK_PROTECT_FAIL
34964 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
34966 #undef TARGET_SUPPORTS_SPLIT_STACK
34967 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
34969 #undef TARGET_FUNCTION_VALUE
34970 #define TARGET_FUNCTION_VALUE ix86_function_value
34972 #undef TARGET_FUNCTION_VALUE_REGNO_P
34973 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
34975 #undef TARGET_SECONDARY_RELOAD
34976 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
34978 #undef TARGET_PREFERRED_RELOAD_CLASS
34979 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
34980 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
34981 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
34982 #undef TARGET_CLASS_LIKELY_SPILLED_P
34983 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
34985 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
34986 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
34987 ix86_builtin_vectorization_cost
34988 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
34989 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
34990 ix86_vectorize_builtin_vec_perm
34991 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
34992 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
34993 ix86_vectorize_builtin_vec_perm_ok
34994 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
34995 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
34996 ix86_preferred_simd_mode
34997 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
34998 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
34999 ix86_autovectorize_vector_sizes
35001 #undef TARGET_SET_CURRENT_FUNCTION
35002 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
35004 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
35005 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
35007 #undef TARGET_OPTION_SAVE
35008 #define TARGET_OPTION_SAVE ix86_function_specific_save
35010 #undef TARGET_OPTION_RESTORE
35011 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
35013 #undef TARGET_OPTION_PRINT
35014 #define TARGET_OPTION_PRINT ix86_function_specific_print
35016 #undef TARGET_CAN_INLINE_P
35017 #define TARGET_CAN_INLINE_P ix86_can_inline_p
35019 #undef TARGET_EXPAND_TO_RTL_HOOK
35020 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
35022 #undef TARGET_LEGITIMATE_ADDRESS_P
35023 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
35025 #undef TARGET_IRA_COVER_CLASSES
35026 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
35028 #undef TARGET_FRAME_POINTER_REQUIRED
35029 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
35031 #undef TARGET_CAN_ELIMINATE
35032 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
35034 #undef TARGET_EXTRA_LIVE_ON_ENTRY
35035 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
35037 #undef TARGET_ASM_CODE_END
35038 #define TARGET_ASM_CODE_END ix86_code_end
35040 #undef TARGET_CONDITIONAL_REGISTER_USAGE
35041 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
35044 \f