| blob | 1da1128b7d63ae554a80cd6a007a38f7cc67b60b |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
63 #endif
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
71 : 4)
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 const
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
107 in SFmode, DFmode and XFmode */
109 in SFmode, DFmode and XFmode */
112 in SImode and DImode */
114 in SImode and DImode */
117 in SImode, DImode and TImode */
119 in SImode, DImode and TImode */
147 };
149 /* Processor costs (relative to an add) */
150 static const
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
178 in SFmode, DFmode and XFmode */
180 in SFmode, DFmode and XFmode */
183 in SImode and DImode */
185 in SImode and DImode */
188 in SImode, DImode and TImode */
190 in SImode, DImode and TImode */
204 DUMMY_STRINGOP_ALGS},
206 DUMMY_STRINGOP_ALGS},
218 };
220 static const
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
248 in SFmode, DFmode and XFmode */
250 in SFmode, DFmode and XFmode */
253 in SImode and DImode */
255 in SImode and DImode */
258 in SImode, DImode and TImode */
260 in SImode, DImode and TImode */
263 shared for code and data, so 4kB is
264 not really precise. */
276 DUMMY_STRINGOP_ALGS},
278 DUMMY_STRINGOP_ALGS},
290 };
292 static const
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
320 in SFmode, DFmode and XFmode */
322 in SFmode, DFmode and XFmode */
325 in SImode and DImode */
327 in SImode and DImode */
330 in SImode, DImode and TImode */
332 in SImode, DImode and TImode */
346 DUMMY_STRINGOP_ALGS},
348 DUMMY_STRINGOP_ALGS},
360 };
362 static const
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
390 in SFmode, DFmode and XFmode */
392 in SFmode, DFmode and XFmode */
395 in SImode and DImode */
397 in SImode and DImode */
400 in SImode, DImode and TImode */
402 in SImode, DImode and TImode */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
416 (we ensure the alignment). For small blocks inline loop is still a
417 noticeable win, for bigger blocks either rep movsl or rep movsb is
418 way to go. Rep movsb has apparently more expensive startup time in CPU,
419 but after 4K the difference is down in the noise. */
422 DUMMY_STRINGOP_ALGS},
425 DUMMY_STRINGOP_ALGS},
437 };
439 static const
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
467 in SFmode, DFmode and XFmode */
469 in SFmode, DFmode and XFmode */
473 in SImode and DImode */
475 in SImode and DImode */
478 in SImode, DImode and TImode */
480 in SImode, DImode and TImode */
494 DUMMY_STRINGOP_ALGS},
496 DUMMY_STRINGOP_ALGS},
508 };
510 static const
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
538 in SFmode, DFmode and XFmode */
540 in SFmode, DFmode and XFmode */
543 in SImode and DImode */
545 in SImode and DImode */
548 in SImode, DImode and TImode */
550 in SImode, DImode and TImode */
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
567 DUMMY_STRINGOP_ALGS},
569 DUMMY_STRINGOP_ALGS},
581 };
583 static const
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
611 in SFmode, DFmode and XFmode */
613 in SFmode, DFmode and XFmode */
616 in SImode and DImode */
618 in SImode and DImode */
621 in SImode, DImode and TImode */
623 in SImode, DImode and TImode */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
640 DUMMY_STRINGOP_ALGS},
642 DUMMY_STRINGOP_ALGS},
654 };
656 static const
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
684 in SFmode, DFmode and XFmode */
686 in SFmode, DFmode and XFmode */
689 in SImode and DImode */
691 in SImode and DImode */
694 in SImode, DImode and TImode */
696 in SImode, DImode and TImode */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
705 time). */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very
715 small blocks it is better to use loop. For large blocks, libcall can
716 do nontemporary accesses and beat inline considerably. */
733 };
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
762 in SFmode, DFmode and XFmode */
764 in SFmode, DFmode and XFmode */
767 in SImode and DImode */
769 in SImode and DImode */
772 in SImode, DImode and TImode */
774 in SImode, DImode and TImode */
776 /* On K8:
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
779 On AMDFAM10:
780 MOVD reg64, xmmreg Double FADD 3
781 1/1 1/1
782 MOVD reg32, xmmreg Double FADD 3
783 1/1 1/1 */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
791 time). */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
820 };
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
889 very small blocks it is better to use loop. For large blocks, libcall
890 can do nontemporary accesses and beat inline considerably. */
907 };
909 static const
932 in QImode, HImode and SImode.
933 Relative to reg-reg move (2). */
937 in SFmode, DFmode and XFmode */
939 in SFmode, DFmode and XFmode */
942 in SImode and DImode */
944 in SImode and DImode */
947 in SImode, DImode and TImode */
949 in SImode, DImode and TImode */
963 DUMMY_STRINGOP_ALGS},
966 DUMMY_STRINGOP_ALGS},
978 };
980 static const
1003 in QImode, HImode and SImode.
1004 Relative to reg-reg move (2). */
1008 in SFmode, DFmode and XFmode */
1010 in SFmode, DFmode and XFmode */
1013 in SImode and DImode */
1015 in SImode and DImode */
1018 in SImode, DImode and TImode */
1020 in SImode, DImode and TImode */
1051 };
1053 static const
1076 in QImode, HImode and SImode.
1077 Relative to reg-reg move (2). */
1081 in SFmode, DFmode and XFmode */
1083 in SFmode, DFmode and XFmode */
1086 in SImode and DImode */
1088 in SImode and DImode */
1091 in SImode, DImode and TImode */
1093 in SImode, DImode and TImode */
1124 };
1126 static const
1149 in QImode, HImode and SImode.
1150 Relative to reg-reg move (2). */
1154 in SFmode, DFmode and XFmode */
1156 in SFmode, DFmode and XFmode */
1159 in SImode and DImode */
1161 in SImode and DImode */
1164 in SImode, DImode and TImode */
1166 in SImode, DImode and TImode */
1197 };
1199 /* Generic64 should produce code tuned for Nocona and K8. */
1200 static const
1203 /* On all chips taken into consideration lea is 2 cycles and more. With
1204 this cost however our current implementation of synth_mult results in
1205 use of unnecessary temporary registers causing regression on several
1206 SPECfp benchmarks. */
1227 in QImode, HImode and SImode.
1228 Relative to reg-reg move (2). */
1232 in SFmode, DFmode and XFmode */
1234 in SFmode, DFmode and XFmode */
1237 in SImode and DImode */
1239 in SImode and DImode */
1242 in SImode, DImode and TImode */
1244 in SImode, DImode and TImode */
1250 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1251 value is increased to perhaps more appropriate value of 5. */
1274 };
1276 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1277 Athlon and K8. */
1278 static const
1301 in QImode, HImode and SImode.
1302 Relative to reg-reg move (2). */
1306 in SFmode, DFmode and XFmode */
1308 in SFmode, DFmode and XFmode */
1311 in SImode and DImode */
1313 in SImode and DImode */
1316 in SImode, DImode and TImode */
1318 in SImode, DImode and TImode */
1332 DUMMY_STRINGOP_ALGS},
1334 DUMMY_STRINGOP_ALGS},
1346 };
1350 /* Processor feature/optimization bitmasks. */
1351 #define m_386 (1<<PROCESSOR_I386)
1352 #define m_486 (1<<PROCESSOR_I486)
1353 #define m_PENT (1<<PROCESSOR_PENTIUM)
1354 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1355 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1356 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1357 #define m_CORE2 (1<<PROCESSOR_CORE2)
1358 #define m_ATOM (1<<PROCESSOR_ATOM)
1360 #define m_GEODE (1<<PROCESSOR_GEODE)
1361 #define m_K6 (1<<PROCESSOR_K6)
1362 #define m_K6_GEODE (m_K6 | m_GEODE)
1363 #define m_K8 (1<<PROCESSOR_K8)
1364 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1365 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1366 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1367 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1368 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1)
1370 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1371 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1373 /* Generic instruction choice should be common subset of supported CPUs
1374 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1375 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1377 /* Feature tests against the various tunings. */
1380 /* Feature tests against the various tunings used to create ix86_tune_features
1381 based on the processor mask. */
1383 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1384 negatively, so enabling for Generic64 seems like good code size
1385 tradeoff. We can't enable it for 32bit generic because it does not
1386 work well with PPro base chips. */
1389 /* X86_TUNE_PUSH_MEMORY */
1393 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1396 /* X86_TUNE_UNROLL_STRLEN */
1400 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1403 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1404 on simulation result. But after P4 was made, no performance benefit
1405 was observed with branch hints. It also increases the code size.
1406 As a result, icc never generates branch hints. */
1409 /* X86_TUNE_DOUBLE_WITH_ADD */
1412 /* X86_TUNE_USE_SAHF */
1416 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1417 partial dependencies. */
1421 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1422 register stalls on Generic32 compilation setting as well. However
1423 in current implementation the partial register stalls are not eliminated
1424 very well - they can be introduced via subregs synthesized by combine
1425 and can happen in caller/callee saving sequences. Because this option
1426 pays back little on PPro based chips and is in conflict with partial reg
1427 dependencies used by Athlon/P4 based chips, it is better to leave it off
1428 for generic32 for now. */
1429 m_PPRO,
1431 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1434 /* X86_TUNE_USE_HIMODE_FIOP */
1437 /* X86_TUNE_USE_SIMODE_FIOP */
1440 /* X86_TUNE_USE_MOV0 */
1441 m_K6,
1443 /* X86_TUNE_USE_CLTD */
1446 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1447 m_PENT4,
1449 /* X86_TUNE_SPLIT_LONG_MOVES */
1450 m_PPRO,
1452 /* X86_TUNE_READ_MODIFY_WRITE */
1455 /* X86_TUNE_READ_MODIFY */
1458 /* X86_TUNE_PROMOTE_QIMODE */
1462 /* X86_TUNE_FAST_PREFIX */
1465 /* X86_TUNE_SINGLE_STRINGOP */
1468 /* X86_TUNE_QIMODE_MATH */
1471 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1472 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1473 might be considered for Generic32 if our scheme for avoiding partial
1474 stalls was more effective. */
1477 /* X86_TUNE_PROMOTE_QI_REGS */
1480 /* X86_TUNE_PROMOTE_HI_REGS */
1481 m_PPRO,
1483 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1484 over esp addition. */
1487 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1488 over esp addition. */
1489 m_PENT,
1491 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1492 over esp subtraction. */
1495 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1496 over esp subtraction. */
1499 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1500 for DFmode copies */
1504 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1507 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1508 conflict here in between PPro/Pentium4 based chips that thread 128bit
1509 SSE registers as single units versus K8 based chips that divide SSE
1510 registers to two 64bit halves. This knob promotes all store destinations
1511 to be 128bit to allow register renaming on 128bit SSE units, but usually
1512 results in one extra microop on 64bit SSE units. Experimental results
1513 shows that disabling this option on P4 brings over 20% SPECfp regression,
1514 while enabling it on K8 brings roughly 2.4% regression that can be partly
1515 masked by careful scheduling of moves. */
1519 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1522 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1523 m_BDVER1,
1525 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1526 m_BDVER1,
1528 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1529 are resolved on SSE register parts instead of whole registers, so we may
1530 maintain just lower part of scalar values in proper format leaving the
1531 upper part undefined. */
1532 m_ATHLON_K8,
1534 /* X86_TUNE_SSE_TYPELESS_STORES */
1535 m_AMD_MULTIPLE,
1537 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1540 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1543 /* X86_TUNE_PROLOGUE_USING_MOVE */
1546 /* X86_TUNE_EPILOGUE_USING_MOVE */
1549 /* X86_TUNE_SHIFT1 */
1552 /* X86_TUNE_USE_FFREEP */
1553 m_AMD_MULTIPLE,
1555 /* X86_TUNE_INTER_UNIT_MOVES */
1558 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1561 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1562 than 4 branch instructions in the 16 byte window. */
1566 /* X86_TUNE_SCHEDULE */
1570 /* X86_TUNE_USE_BT */
1573 /* X86_TUNE_USE_INCDEC */
1576 /* X86_TUNE_PAD_RETURNS */
1579 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1580 m_ATOM,
1582 /* X86_TUNE_EXT_80387_CONSTANTS */
1586 /* X86_TUNE_SHORTEN_X87_SSE */
1589 /* X86_TUNE_AVOID_VECTOR_DECODE */
1592 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1593 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1596 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1597 vector path on AMD machines. */
1600 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1601 machines. */
1604 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1605 than a MOV. */
1606 m_PENT,
1608 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1609 but one byte longer. */
1610 m_PENT,
1612 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1613 operand that cannot be represented using a modRM byte. The XOR
1614 replacement is long decoded, so this split helps here as well. */
1615 m_K6,
1617 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1618 from FP to FP. */
1621 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1622 from integer to FP. */
1623 m_AMDFAM10,
1625 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1626 with a subsequent conditional jump instruction into a single
1627 compare-and-branch uop. */
1630 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1631 will impact LEA instruction selection. */
1632 m_ATOM,
1634 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
1635 instructions. */
1637 };
1639 /* Feature tests against the various architecture variations. */
1642 /* Feature tests against the various architecture variations, used to create
1643 ix86_arch_features based on the processor mask. */
1645 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1648 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1651 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1654 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1657 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1659 };
1661 static const unsigned int x86_accumulate_outgoing_args
1665 static const unsigned int x86_arch_always_fancy_math_387
1671 /* In case the average insn count for single function invocation is
1672 lower than this constant, emit fast (but longer) prologue and
1673 epilogue code. */
1674 #define FAST_PROLOGUE_INSN_COUNT 20
1676 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1681 /* Array of the smallest class containing reg number REGNO, indexed by
1682 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1685 {
1686 /* ax, dx, cx, bx */
1688 /* si, di, bp, sp */
1690 /* FP registers */
1693 /* arg pointer */
1694 NON_Q_REGS,
1695 /* flags, fpsr, fpcr, frame */
1697 /* SSE registers */
1700 /* MMX registers */
1703 /* REX registers */
1706 /* SSE REX registers */
1709 };
1711 /* The "default" register map used in 32bit mode. */
1714 {
1722 };
1724 /* The "default" register map used in 64bit mode. */
1727 {
1735 };
1737 /* Define the register numbers to be used in Dwarf debugging information.
1738 The SVR4 reference port C compiler uses the following register numbers
1739 in its Dwarf output code:
1740 0 for %eax (gcc regno = 0)
1741 1 for %ecx (gcc regno = 2)
1742 2 for %edx (gcc regno = 1)
1743 3 for %ebx (gcc regno = 3)
1744 4 for %esp (gcc regno = 7)
1745 5 for %ebp (gcc regno = 6)
1746 6 for %esi (gcc regno = 4)
1747 7 for %edi (gcc regno = 5)
1748 The following three DWARF register numbers are never generated by
1749 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1750 believes these numbers have these meanings.
1751 8 for %eip (no gcc equivalent)
1752 9 for %eflags (gcc regno = 17)
1753 10 for %trapno (no gcc equivalent)
1754 It is not at all clear how we should number the FP stack registers
1755 for the x86 architecture. If the version of SDB on x86/svr4 were
1756 a bit less brain dead with respect to floating-point then we would
1757 have a precedent to follow with respect to DWARF register numbers
1758 for x86 FP registers, but the SDB on x86/svr4 is so completely
1759 broken with respect to FP registers that it is hardly worth thinking
1760 of it as something to strive for compatibility with.
1761 The version of x86/svr4 SDB I have at the moment does (partially)
1762 seem to believe that DWARF register number 11 is associated with
1763 the x86 register %st(0), but that's about all. Higher DWARF
1764 register numbers don't seem to be associated with anything in
1765 particular, and even for DWARF regno 11, SDB only seems to under-
1766 stand that it should say that a variable lives in %st(0) (when
1767 asked via an `=' command) if we said it was in DWARF regno 11,
1768 but SDB still prints garbage when asked for the value of the
1769 variable in question (via a `/' command).
1770 (Also note that the labels SDB prints for various FP stack regs
1771 when doing an `x' command are all wrong.)
1772 Note that these problems generally don't affect the native SVR4
1773 C compiler because it doesn't allow the use of -O with -g and
1774 because when it is *not* optimizing, it allocates a memory
1775 location for each floating-point variable, and the memory
1776 location is what gets described in the DWARF AT_location
1777 attribute for the variable in question.
1778 Regardless of the severe mental illness of the x86/svr4 SDB, we
1779 do something sensible here and we use the following DWARF
1780 register numbers. Note that these are all stack-top-relative
1781 numbers.
1782 11 for %st(0) (gcc regno = 8)
1783 12 for %st(1) (gcc regno = 9)
1784 13 for %st(2) (gcc regno = 10)
1785 14 for %st(3) (gcc regno = 11)
1786 15 for %st(4) (gcc regno = 12)
1787 16 for %st(5) (gcc regno = 13)
1788 17 for %st(6) (gcc regno = 14)
1789 18 for %st(7) (gcc regno = 15)
1790 */
1792 {
1800 };
1802 /* Define parameter passing and return registers. */
1805 {
1807 };
1810 {
1812 };
1815 {
1817 };
1819 /* Define the structure for the machine field in struct function. */
1824 rtx rtl;
1826 };
1828 /* Structure describing stack frame layout.
1829 Stack grows downward:
1831 [arguments]
1832 <- ARG_POINTER
1833 saved pc
1835 saved static chain if ix86_static_chain_on_stack
1837 saved frame pointer if frame_pointer_needed
1838 <- HARD_FRAME_POINTER
1839 [saved regs]
1840 <- regs_save_offset
1841 [padding0]
1843 [saved SSE regs]
1844 <- sse_regs_save_offset
1845 [padding1] |
1846 | <- FRAME_POINTER
1847 [va_arg registers] |
1848 |
1849 [frame] |
1850 |
1851 [padding2] | = to_allocate
1852 <- STACK_POINTER
1853 */
1854 struct ix86_frame
1855 {
1861 HOST_WIDE_INT frame;
1863 /* The offsets relative to ARG_POINTER. */
1864 HOST_WIDE_INT frame_pointer_offset;
1865 HOST_WIDE_INT hard_frame_pointer_offset;
1866 HOST_WIDE_INT stack_pointer_offset;
1867 HOST_WIDE_INT reg_save_offset;
1868 HOST_WIDE_INT sse_reg_save_offset;
1870 /* When save_regs_using_mov is set, emit prologue using
1871 move instead of push instructions. */
1873 };
1875 /* Code model option. */
1877 /* Asm dialect. */
1879 /* TLS dialects. */
1882 /* Which unit we are generating floating point math for. */
1885 /* Which cpu are we scheduling for. */
1888 /* Which cpu are we optimizing for. */
1891 /* Which instruction set architecture to use. */
1894 /* true if sse prefetch instruction is not NOOP. */
1897 /* ix86_regparm_string as a number */
1900 /* -mstackrealign option */
1916 /* Preferred alignment for stack boundary in bits. */
1919 /* Alignment for incoming stack boundary in bits specified at
1920 command line. */
1923 /* Default alignment for incoming stack boundary in bits. */
1926 /* Alignment for incoming stack boundary in bits. */
1929 /* The abi used by target. */
1932 /* Values 1-5: see jump.c */
1935 /* Calling abi specific va_list type nodes. */
1939 /* Variables which are this size or smaller are put in the data/bss
1940 or ldata/lbss sections. */
1944 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1948 /* Fence to use after loop using movnt. */
1949 tree x86_mfence;
1951 /* Register class used for passing given 64bit part of the argument.
1952 These represent classes as documented by the PS ABI, with the exception
1953 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1954 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1956 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1957 whenever possible (upper half does contain padding). */
1958 enum x86_64_reg_class
1959 {
1960 X86_64_NO_CLASS,
1961 X86_64_INTEGER_CLASS,
1962 X86_64_INTEGERSI_CLASS,
1963 X86_64_SSE_CLASS,
1964 X86_64_SSESF_CLASS,
1965 X86_64_SSEDF_CLASS,
1966 X86_64_SSEUP_CLASS,
1967 X86_64_X87_CLASS,
1968 X86_64_X87UP_CLASS,
1969 X86_64_COMPLEX_X87_CLASS,
1970 X86_64_MEMORY_CLASS
1971 };
1973 #define MAX_CLASSES 4
1975 /* Table of constants used by fldpi, fldln2, etc.... */
1979 \f
1995 enum ix86_function_specific_strings
1996 {
1997 IX86_FUNCTION_SPECIFIC_ARCH,
1998 IX86_FUNCTION_SPECIFIC_TUNE,
1999 IX86_FUNCTION_SPECIFIC_FPMATH,
2000 IX86_FUNCTION_SPECIFIC_MAX
2001 };
2018 \f
2019 #ifndef SUBTARGET32_DEFAULT_CPU
2021 #endif
2023 /* The svr4 ABI for the i386 says that records and unions are returned
2024 in memory. */
2025 #ifndef DEFAULT_PCC_STRUCT_RETURN
2026 #define DEFAULT_PCC_STRUCT_RETURN 1
2027 #endif
2029 /* Whether -mtune= or -march= were specified */
2033 /* A mask of ix86_isa_flags that includes bit X if X
2034 was set or cleared on the command line. */
2037 /* Define a set of ISAs which are available when a given ISA is
2038 enabled. MMX and SSE ISAs are handled separately. */
2040 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2041 #define OPTION_MASK_ISA_3DNOW_SET \
2042 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2044 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2045 #define OPTION_MASK_ISA_SSE2_SET \
2046 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2047 #define OPTION_MASK_ISA_SSE3_SET \
2048 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2049 #define OPTION_MASK_ISA_SSSE3_SET \
2050 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2051 #define OPTION_MASK_ISA_SSE4_1_SET \
2052 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2053 #define OPTION_MASK_ISA_SSE4_2_SET \
2054 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2055 #define OPTION_MASK_ISA_AVX_SET \
2056 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2057 #define OPTION_MASK_ISA_FMA_SET \
2058 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2060 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2061 as -msse4.2. */
2062 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2064 #define OPTION_MASK_ISA_SSE4A_SET \
2065 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2066 #define OPTION_MASK_ISA_FMA4_SET \
2067 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2068 | OPTION_MASK_ISA_AVX_SET)
2069 #define OPTION_MASK_ISA_XOP_SET \
2070 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2071 #define OPTION_MASK_ISA_LWP_SET \
2072 OPTION_MASK_ISA_LWP
2074 /* AES and PCLMUL need SSE2 because they use xmm registers */
2075 #define OPTION_MASK_ISA_AES_SET \
2076 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2077 #define OPTION_MASK_ISA_PCLMUL_SET \
2078 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2080 #define OPTION_MASK_ISA_ABM_SET \
2081 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2083 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2084 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2085 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2086 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2087 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2089 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
2090 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
2091 #define OPTION_MASK_ISA_F16C_SET \
2092 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
2094 /* Define a set of ISAs which aren't available when a given ISA is
2095 disabled. MMX and SSE ISAs are handled separately. */
2097 #define OPTION_MASK_ISA_MMX_UNSET \
2098 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2099 #define OPTION_MASK_ISA_3DNOW_UNSET \
2100 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2101 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2103 #define OPTION_MASK_ISA_SSE_UNSET \
2104 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2105 #define OPTION_MASK_ISA_SSE2_UNSET \
2106 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2107 #define OPTION_MASK_ISA_SSE3_UNSET \
2108 (OPTION_MASK_ISA_SSE3 \
2109 | OPTION_MASK_ISA_SSSE3_UNSET \
2110 | OPTION_MASK_ISA_SSE4A_UNSET )
2111 #define OPTION_MASK_ISA_SSSE3_UNSET \
2112 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2113 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2114 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2115 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2116 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2117 #define OPTION_MASK_ISA_AVX_UNSET \
2118 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2119 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET)
2120 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2122 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2123 as -mno-sse4.1. */
2124 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2126 #define OPTION_MASK_ISA_SSE4A_UNSET \
2127 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2129 #define OPTION_MASK_ISA_FMA4_UNSET \
2130 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2131 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2132 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2134 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2135 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2136 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2137 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2138 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2139 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2140 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2141 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2143 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
2144 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
2145 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
2147 /* Vectorization library interface and handlers. */
2153 /* Processor target table, indexed by processor number */
2154 struct ptt
2155 {
2162 };
2165 {
2182 };
2185 {
2208 "bdver1"
2209 };
2210 \f
2211 /* Return true if a red-zone is in use. */
2215 {
2217 }
2219 /* Implement TARGET_HANDLE_OPTION. */
2221 static bool
2223 {
2225 {
2228 {
2231 }
2232 else
2233 {
2236 }
2241 {
2244 }
2245 else
2246 {
2249 }
2257 {
2260 }
2261 else
2262 {
2265 }
2270 {
2273 }
2274 else
2275 {
2278 }
2283 {
2286 }
2287 else
2288 {
2291 }
2296 {
2299 }
2300 else
2301 {
2304 }
2309 {
2312 }
2313 else
2314 {
2317 }
2322 {
2325 }
2326 else
2327 {
2330 }
2335 {
2338 }
2339 else
2340 {
2343 }
2348 {
2351 }
2352 else
2353 {
2356 }
2371 {
2374 }
2375 else
2376 {
2379 }
2384 {
2387 }
2388 else
2389 {
2392 }
2397 {
2400 }
2401 else
2402 {
2405 }
2410 {
2413 }
2414 else
2415 {
2418 }
2423 {
2426 }
2427 else
2428 {
2431 }
2436 {
2439 }
2440 else
2441 {
2444 }
2449 {
2452 }
2453 else
2454 {
2457 }
2462 {
2465 }
2466 else
2467 {
2470 }
2475 {
2478 }
2479 else
2480 {
2483 }
2488 {
2491 }
2492 else
2493 {
2496 }
2501 {
2504 }
2505 else
2506 {
2509 }
2514 {
2517 }
2518 else
2519 {
2522 }
2527 {
2530 }
2531 else
2532 {
2535 }
2540 {
2543 }
2544 else
2545 {
2548 }
2553 {
2556 }
2557 else
2558 {
2561 }
2566 }
2567 }
2568 \f
2569 /* Return a string that documents the current -m options. The caller is
2570 responsible for freeing the string. */
2575 {
2576 struct ix86_target_opts
2577 {
2580 };
2582 /* This table is ordered so that options like -msse4.2 that imply
2583 preceding options while match those first. */
2585 {
2610 };
2612 /* Flag options. */
2614 {
2636 };
2652 /* Add -march= option. */
2654 {
2657 }
2659 /* Add -mtune= option. */
2661 {
2664 }
2666 /* Pick out the options in isa options. */
2668 {
2670 {
2673 }
2674 }
2677 {
2680 }
2682 /* Add flag options. */
2684 {
2686 {
2689 }
2690 }
2693 {
2696 }
2698 /* Add -fpmath= option. */
2700 {
2703 }
2705 /* Any options? */
2711 /* Size the string. */
2715 {
2720 }
2722 /* Build the string. */
2727 {
2734 {
2736 line_len++;
2739 {
2743 }
2744 }
2748 {
2752 }
2753 }
2759 }
2761 /* Return TRUE if software prefetching is beneficial for the
2762 given CPU. */
2764 static bool
2766 {
2768 {
2778 }
2779 }
2781 /* Return true, if profiling code should be emitted before
2782 prologue. Otherwise it returns false.
2783 Note: For x86 with "hotfix" it is sorried. */
2784 static bool
2786 {
2788 }
2790 /* Function that is callable from the debugger to print the current
2791 options. */
2792 void
2794 {
2800 {
2803 }
2804 else
2808 }
2809 \f
2810 /* Override various settings based on options. If MAIN_ARGS_P, the
2811 options are from the command line, otherwise they are from
2812 attributes. */
2814 static void
2816 {
2824 /* Comes from final.c -- no real reason to change it. */
2825 #define MAX_CODE_ALIGN 16
2827 enum pta_flags
2828 {
2856 };
2858 static struct pta
2859 {
2864 }
2866 {
2953 };
2957 /* Set up prefix/suffix so the error messages refer to either the command
2958 line argument, or the attribute(target). */
2960 {
2964 }
2965 else
2966 {
2970 }
2972 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2973 SUBTARGET_OVERRIDE_OPTIONS;
2974 #endif
2976 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2977 SUBSUBTARGET_OVERRIDE_OPTIONS;
2978 #endif
2980 /* -fPIC is the default for x86_64. */
2984 /* Need to check -mtune=generic first. */
2986 {
2989 /* As special support for cross compilers we read -mtune=native
2990 as -mtune=generic. With native compilers we won't see the
2991 -mtune=native, as it was changed by the driver. */
2993 {
2996 else
2998 }
2999 /* If this call is for setting the option attribute, allow the
3000 generic32/generic64 that was previously set. */
3004 ;
3012 }
3013 else
3014 {
3018 {
3021 }
3023 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3024 need to use a sensible tune option. */
3028 {
3031 else
3033 }
3034 }
3037 {
3046 /* rep; movq isn't available in 32-bit code. */
3054 else
3057 }
3061 else
3064 /* Validate -mabi= value. */
3066 {
3071 else
3074 }
3075 else
3079 {
3092 else
3095 }
3096 else
3097 {
3098 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3099 use of rip-relative addressing. This eliminates fixups that
3100 would otherwise be needed if this object is to be placed in a
3101 DLL, and is essentially just as efficient as direct addressing. */
3106 else
3108 }
3110 {
3116 else
3119 }
3129 {
3132 /* Default cpu tuning to the architecture. */
3218 }
3233 {
3237 {
3239 {
3247 }
3248 else
3251 }
3252 /* Intel CPUs have always interpreted SSE prefetch instructions as
3253 NOPs; so, we can enable SSE prefetch instructions even when
3254 -mtune (rather than -march) points us to a processor that has them.
3255 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3256 higher processors. */
3261 }
3271 #ifndef USE_IX86_FRAME_POINTER
3272 #define USE_IX86_FRAME_POINTER 0
3273 #endif
3275 /* Set the default values for switches whose default depends on TARGET_64BIT
3276 in case they weren't overwritten by command line options. */
3278 {
3287 }
3288 else
3289 {
3298 }
3302 else
3305 /* Arrange to set up i386_stack_locals for all functions. */
3308 /* Validate -mregparm= value. */
3310 {
3317 else
3319 }
3323 /* If the user has provided any of the -malign-* options,
3324 warn and use that value only if -falign-* is not set.
3325 Remove this code in GCC 3.2 or later. */
3327 {
3331 {
3336 else
3338 }
3339 }
3342 {
3346 {
3351 else
3353 }
3354 }
3357 {
3361 {
3366 else
3368 }
3369 }
3371 /* Default align_* from the processor table. */
3373 {
3376 }
3378 {
3381 }
3383 {
3385 }
3387 /* Validate -mbranch-cost= value, or provide default. */
3390 {
3394 else
3396 }
3398 {
3402 else
3404 }
3407 {
3412 else
3415 }
3418 {
3422 }
3425 {
3428 /* Enable by default the SSE and MMX builtins. Do allow the user to
3429 explicitly disable any of these. In particular, disabling SSE and
3430 MMX for kernel code is extremely useful. */
3432 ix86_isa_flags
3438 }
3439 else
3440 {
3444 ix86_isa_flags
3447 /* i386 ABI does not specify red zone. It still makes sense to use it
3448 when programmer takes care to stack from being destroyed. */
3451 }
3453 /* Keep nonleaf frame pointers. */
3459 /* If we're doing fast math, we don't care about comparison order
3460 wrt NaNs. This lets us use a shorter comparison sequence. */
3464 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3465 since the insns won't need emulation. */
3469 /* Likewise, if the target doesn't have a 387, or we've specified
3470 software floating point, don't use 387 inline intrinsics. */
3474 /* Turn on MMX builtins for -msse. */
3476 {
3479 }
3481 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3485 /* Validate -mpreferred-stack-boundary= value or default it to
3486 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3489 {
3494 else
3496 }
3498 /* Set the default value for -mstackrealign. */
3504 /* Validate -mincoming-stack-boundary= value or default it to
3505 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3508 {
3513 else
3514 {
3516 ix86_incoming_stack_boundary
3518 }
3519 }
3521 /* Accept -msseregparm only if at least SSE support is enabled. */
3528 {
3532 {
3534 {
3537 }
3538 else
3540 }
3546 {
3548 {
3551 }
3553 {
3556 }
3557 else
3559 }
3560 else
3563 }
3565 /* If the i387 is disabled, then do not return values in it. */
3569 /* Use external vectorized library in vectorizing intrinsics. */
3571 {
3576 else
3580 }
3588 /* ??? Unwind info is not correct around the CFG unless either a frame
3589 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3590 unwind info generation to be aware of the CFG and propagating states
3591 around edges. */
3594 && flag_omit_frame_pointer
3596 {
3602 }
3604 /* If stack probes are required, the space used for large function
3605 arguments on the stack must also be probed, so enable
3606 -maccumulate-outgoing-args so this happens in the prologue. */
3609 {
3614 }
3616 /* For sane SSE instruction set generation we need fcomi instruction.
3617 It is safe to enable all CMOVE instructions. */
3621 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3622 {
3628 }
3630 /* When scheduling description is not available, disable scheduler pass
3631 so it won't slow down the compilation and make x87 code slower. */
3645 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3647 && HAVE_prefetch
3652 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3653 can be optimized to ap = __builtin_next_arg (0). */
3658 {
3669 }
3670 else
3671 {
3682 }
3684 #ifdef USE_IX86_CLD
3685 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3688 #endif
3691 {
3695 }
3697 {
3698 #if defined(PROFILE_BEFORE_PROLOGUE)
3700 #else
3702 #endif
3703 }
3705 /* Save the initial options in case the user does function specific options */
3707 target_option_default_node = target_option_current_node
3709 }
3711 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3713 static void
3715 {
3717 }
3719 /* Update register usage after having seen the compiler flags. */
3721 void
3723 {
3728 {
3733 }
3735 /* The PIC register, if it exists, is fixed. */
3740 /* The MS_ABI changes the set of call-used registers. */
3742 {
3749 }
3751 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3752 other call-clobbered regs for 64-bit. */
3754 {
3761 }
3763 /* If MMX is disabled, squash the registers. */
3769 /* If SSE is disabled, squash the registers. */
3775 /* If the FPU is disabled, squash the registers. */
3781 /* If 32-bit, squash the 64-bit registers. */
3783 {
3788 }
3789 }
3791 \f
3792 /* Save the current options */
3794 static void
3796 {
3807 /* The fields are char but the variables are not; make sure the
3808 values fit in the fields. */
3814 }
3816 /* Restore the current options */
3818 static void
3820 {
3836 /* Recreate the arch feature tests if the arch changed */
3838 {
3843 }
3845 /* Recreate the tune optimization tests */
3847 {
3852 }
3853 }
3855 /* Print the current options */
3857 static void
3860 {
3885 {
3888 }
3889 }
3891 \f
3892 /* Inner function to process the attribute((target(...))), take an argument and
3893 set the current options from the argument. If we have a list, recursively go
3894 over the list. */
3896 static bool
3898 {
3902 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3903 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3904 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3905 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3907 enum ix86_opt_type
3908 {
3909 ix86_opt_unknown,
3910 ix86_opt_yes,
3911 ix86_opt_no,
3912 ix86_opt_str,
3913 ix86_opt_isa
3914 };
3916 static const struct
3917 {
3924 /* isa options */
3947 /* string options */
3952 /* flag options */
3954 OPT_mcld,
3955 MASK_CLD),
3958 OPT_mfancy_math_387,
3959 MASK_NO_FANCY_MATH_387),
3962 OPT_mieee_fp,
3963 MASK_IEEE_FP),
3966 OPT_minline_all_stringops,
3967 MASK_INLINE_ALL_STRINGOPS),
3970 OPT_minline_stringops_dynamically,
3971 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3974 OPT_mno_align_stringops,
3975 MASK_NO_ALIGN_STRINGOPS),
3978 OPT_mrecip,
3979 MASK_RECIP),
3981 };
3983 /* If this is a list, recurse to get the options. */
3985 {
3994 }
3999 /* Handle multiple arguments separated by commas. */
4003 {
4017 {
4021 }
4022 else
4023 {
4026 }
4028 /* Recognize no-xxx. */
4030 {
4034 }
4035 else
4038 /* Find the option. */
4042 {
4048 {
4053 }
4054 }
4056 /* Process the option. */
4058 {
4061 }
4067 {
4073 else
4075 }
4078 {
4080 {
4083 }
4084 else
4086 }
4088 else
4090 }
4093 }
4095 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4097 tree
4099 {
4111 /* Process each of the options on the chain. */
4115 /* If the changed options are different from the default, rerun
4116 ix86_option_override_internal, and then save the options away.
4117 The string options are are attribute options, and will be undone
4118 when we copy the save structure. */
4124 {
4125 /* If we are using the default tune= or arch=, undo the string assigned,
4126 and use the default. */
4137 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4143 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4146 /* Add any builtin functions with the new isa if any. */
4149 /* Save the current options unless we are validating options for
4150 #pragma. */
4157 /* Free up memory allocated to hold the strings */
4161 }
4164 }
4166 /* Hook to validate attribute((target("string"))). */
4168 static bool
4171 tree args,
4173 {
4180 /* If the function changed the optimization levels as well as setting target
4181 options, start with the optimizations specified. */
4185 /* The target attributes may also change some optimization flags, so update
4186 the optimization options if necessary. */
4195 {
4200 }
4208 }
4210 \f
4211 /* Hook to determine if one function can safely inline another. */
4213 static bool
4215 {
4220 /* If callee has no option attributes, then it is ok to inline. */
4224 /* If caller has no option attributes, but callee does then it is not ok to
4225 inline. */
4229 else
4230 {
4234 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4235 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4236 function. */
4241 /* See if we have the same non-isa options. */
4245 /* See if arch, tune, etc. are the same. */
4258 else
4260 }
4263 }
4265 \f
4266 /* Remember the last target of ix86_set_current_function. */
4269 /* Establish appropriate back-end context for processing the function
4270 FNDECL. The argument might be NULL to indicate processing at top
4271 level, outside of any function scope. */
4272 static void
4274 {
4275 /* Only change the context if the function changes. This hook is called
4276 several times in the course of compiling a function, and we don't want to
4277 slow things down too much or call target_reinit when it isn't safe. */
4279 {
4280 tree old_tree = (ix86_previous_fndecl
4284 tree new_tree = (fndecl
4290 ;
4293 {
4296 }
4299 {
4305 }
4306 }
4307 }
4309 \f
4310 /* Return true if this goes in large data/bss. */
4312 static bool
4314 {
4318 /* Functions are never large data. */
4323 {
4329 }
4330 else
4331 {
4334 /* If this is an incomplete type with size 0, then we can't put it
4335 in data because it might be too big when completed. */
4338 }
4341 }
4343 /* Switch to the appropriate section for output of DECL.
4344 DECL is either a `VAR_DECL' node or a constant of some sort.
4345 RELOC indicates whether forming the initial value of DECL requires
4346 link-time relocations. */
4349 ATTRIBUTE_UNUSED;
4354 {
4357 {
4361 {
4395 /* We don't split these for medium model. Place them into
4396 default sections and hope for best. */
4398 }
4400 {
4401 /* We might get called with string constants, but get_named_section
4402 doesn't like them as they are not DECLs. Also, we need to set
4403 flags in that case. */
4407 }
4408 }
4410 }
4412 /* Build up a unique section name, expressed as a
4413 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4414 RELOC indicates whether the initial value of EXP requires
4415 link-time relocations. */
4417 static void ATTRIBUTE_UNUSED
4419 {
4422 {
4424 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4428 {
4452 /* We don't split these for medium model. Place them into
4453 default sections and hope for best. */
4455 }
4457 {
4464 /* If we're using one_only, then there needs to be a .gnu.linkonce
4465 prefix to the section name. */
4472 }
4473 }
4475 }
4477 #ifdef COMMON_ASM_OP
4478 /* This says how to output assembler code to declare an
4479 uninitialized external linkage data object.
4481 For medium model x86-64 we need to use .largecomm opcode for
4482 large objects. */
4483 void
4487 {
4491 else
4496 }
4497 #endif
4499 /* Utility function for targets to use in implementing
4500 ASM_OUTPUT_ALIGNED_BSS. */
4502 void
4506 {
4510 else
4513 #ifdef ASM_DECLARE_OBJECT_NAME
4516 #else
4517 /* Standard thing is just output label for the object. */
4521 }
4522 \f
4523 static void
4525 {
4526 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4527 make the problem with not enough registers even worse. */
4528 #ifdef INSN_SCHEDULING
4531 #endif
4534 /* The Darwin libraries never set errno, so we might as well
4535 avoid calling them when that's the only reason we would. */
4538 /* The default values of these switches depend on the TARGET_64BIT
4539 that is not known at this moment. Mark these values with 2 and
4540 let user the to override these. In case there is no command line
4541 option specifying them, we will set the defaults in
4542 ix86_option_override_internal. */
4546 /* For -O2 and beyond, turn on -fzee for x86_64 target. */
4553 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4554 SUBTARGET_OPTIMIZATION_OPTIONS;
4555 #endif
4556 }
4558 /* Decide whether we must probe the stack before any space allocation
4559 on this target. It's essentially TARGET_STACK_PROBE except when
4560 -fstack-check causes the stack to be already probed differently. */
4562 bool
4564 {
4565 /* Do not probe the stack twice if static stack checking is enabled. */
4570 }
4571 \f
4572 /* Decide whether we can make a sibling call to a function. DECL is the
4573 declaration of the function being targeted by the call and EXP is the
4574 CALL_EXPR representing the call. */
4576 static bool
4578 {
4582 /* If we are generating position-independent code, we cannot sibcall
4583 optimize any indirect call, or a direct call to a global function,
4584 as the PLT requires %ebx be live. */
4588 /* If we need to align the outgoing stack, then sibcalling would
4589 unalign the stack, which may break the called function. */
4595 {
4598 }
4599 else
4600 {
4601 /* We're looking at the CALL_EXPR, we need the type of the function. */
4606 }
4608 /* Check that the return value locations are the same. Like
4609 if we are returning floats on the 80387 register stack, we cannot
4610 make a sibcall from a function that doesn't return a float to a
4611 function that does or, conversely, from a function that does return
4612 a float to a function that doesn't; the necessary stack adjustment
4613 would not be executed. This is also the place we notice
4614 differences in the return value ABI. Note that it is ok for one
4615 of the functions to have void return type as long as the return
4616 value of the other is passed in a register. */
4621 {
4624 }
4626 ;
4631 {
4632 /* The SYSV ABI has more call-clobbered registers;
4633 disallow sibcalls from MS to SYSV. */
4637 }
4638 else
4639 {
4640 /* If this call is indirect, we'll need to be able to use a
4641 call-clobbered register for the address of the target function.
4642 Make sure that all such registers are not used for passing
4643 parameters. Note that DLLIMPORT functions are indirect. */
4646 {
4648 {
4649 /* ??? Need to count the actual number of registers to be used,
4650 not the possible number of registers. Fix later. */
4652 }
4653 }
4654 }
4656 /* Otherwise okay. That also includes certain types of indirect calls. */
4658 }
4660 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4661 and "sseregparm" calling convention attributes;
4662 arguments as in struct attribute_spec.handler. */
4664 static tree
4666 tree args,
4669 {
4674 {
4676 name);
4679 }
4681 /* Can combine regparm with all attributes but fastcall. */
4683 {
4684 tree cst;
4687 {
4689 }
4692 {
4694 }
4698 {
4701 name);
4703 }
4705 {
4709 }
4712 }
4715 {
4716 /* Do not warn when emulating the MS ABI. */
4721 name);
4724 }
4726 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4728 {
4730 {
4732 }
4734 {
4736 }
4738 {
4740 }
4742 {
4744 }
4745 }
4747 /* Can combine stdcall with fastcall (redundant), regparm and
4748 sseregparm. */
4750 {
4752 {
4754 }
4756 {
4758 }
4760 {
4762 }
4763 }
4765 /* Can combine cdecl with regparm and sseregparm. */
4767 {
4769 {
4771 }
4773 {
4775 }
4777 {
4779 }
4780 }
4782 {
4785 name);
4787 {
4789 }
4791 {
4793 }
4795 {
4797 }
4798 }
4800 /* Can combine sseregparm with all attributes. */
4803 }
4805 /* Return 0 if the attributes for two types are incompatible, 1 if they
4806 are compatible, and 2 if they are nearly compatible (which causes a
4807 warning to be generated). */
4809 static int
4811 {
4812 /* Check for mismatch of non-default calling convention. */
4819 /* Check for mismatched fastcall/regparm types. */
4826 /* Check for mismatched sseregparm types. */
4831 /* Check for mismatched thiscall types. */
4836 /* Check for mismatched return types (cdecl vs stdcall). */
4842 }
4843 \f
4844 /* Return the regparm value for a function with the indicated TYPE and DECL.
4845 DECL may be NULL when calling function indirectly
4846 or considering a libcall. */
4848 static int
4850 {
4851 tree attr;
4861 {
4864 }
4872 /* Use register calling convention for local functions when possible. */
4875 && optimize
4877 {
4878 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4881 {
4884 /* Make sure no regparm register is taken by a
4885 fixed register variable. */
4890 /* We don't want to use regparm(3) for nested functions as
4891 these use a static chain pointer in the third argument. */
4895 /* In 32-bit mode save a register for the split stack. */
4899 /* Each fixed register usage increases register pressure,
4900 so less registers should be used for argument passing.
4901 This functionality can be overriden by an explicit
4902 regparm value. */
4905 globals++;
4907 local_regparm
4912 }
4913 }
4916 }
4918 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4919 DFmode (2) arguments in SSE registers for a function with the
4920 indicated TYPE and DECL. DECL may be NULL when calling function
4921 indirectly or considering a libcall. Otherwise return 0. */
4923 static int
4925 {
4928 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4929 by the sseregparm attribute. */
4932 {
4934 {
4936 {
4940 else
4943 }
4945 }
4948 }
4950 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4951 (and DFmode for SSE2) arguments in SSE registers. */
4954 {
4955 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4959 }
4962 }
4964 /* Return true if EAX is live at the start of the function. Used by
4965 ix86_expand_prologue to determine if we need special help before
4966 calling allocate_stack_worker. */
4968 static bool
4970 {
4971 /* Cheat. Don't bother working forward from ix86_function_regparm
4972 to the function type to whether an actual argument is located in
4973 eax. Instead just look at cfg info, which is still close enough
4974 to correct at this point. This gives false positives for broken
4975 functions that might use uninitialized data that happens to be
4976 allocated in eax, but who cares? */
4978 }
4980 /* Value is the number of bytes of arguments automatically
4981 popped when returning from a subroutine call.
4982 FUNDECL is the declaration node of the function (as a tree),
4983 FUNTYPE is the data type of the function (as a tree),
4984 or for a library call it is an identifier node for the subroutine name.
4985 SIZE is the number of bytes of arguments passed on the stack.
4987 On the 80386, the RTD insn may be used to pop them if the number
4988 of args is fixed, but if the number is variable then the caller
4989 must pop them all. RTD can't be used for library calls now
4990 because the library is compiled with the Unix compiler.
4991 Use of RTD is a selectable option, since it is incompatible with
4992 standard Unix calling sequences. If the option is not selected,
4993 the caller must always pop the args.
4995 The attribute stdcall is equivalent to RTD on a per module basis. */
4997 static int
4999 {
5002 /* None of the 64-bit ABIs pop arguments. */
5008 /* Cdecl functions override -mrtd, and never pop the stack. */
5010 {
5011 /* Stdcall and fastcall functions will pop the stack if not
5012 variable args. */
5020 }
5022 /* Lose any fake structure return argument if it is passed on the stack. */
5025 {
5029 }
5032 }
5033 \f
5034 /* Argument support functions. */
5036 /* Return true when register may be used to pass function parameters. */
5037 bool
5039 {
5044 {
5048 else
5054 }
5057 {
5060 }
5061 else
5062 {
5066 }
5068 /* TODO: The function should depend on current function ABI but
5069 builtins.c would need updating then. Therefore we use the
5070 default ABI. */
5072 /* RAX is used as hidden argument to va_arg functions. */
5078 else
5085 }
5087 /* Return if we do not know how to pass TYPE solely in registers. */
5089 static bool
5091 {
5095 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5096 The layout_type routine is crafty and tries to trick us into passing
5097 currently unsupported vector types on the stack by using TImode. */
5100 }
5102 /* It returns the size, in bytes, of the area reserved for arguments passed
5103 in registers for the function represented by fndecl dependent to the used
5104 abi format. */
5105 int
5107 {
5111 else
5116 }
5118 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5119 call abi used. */
5120 enum calling_abi
5122 {
5124 {
5127 {
5130 }
5134 }
5136 }
5138 static bool
5140 {
5142 {
5146 else
5148 }
5150 }
5152 static enum calling_abi
5154 {
5158 }
5160 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5161 call abi used. */
5162 enum calling_abi
5164 {
5168 }
5170 /* Write the extra assembler code needed to declare a function properly. */
5172 void
5174 tree decl)
5175 {
5179 {
5185 }
5189 /* Output magic byte marker, if hot-patch attribute is set. */
5191 {
5193 {
5194 /* leaq [%rsp + 0], %rsp */
5197 }
5198 else
5199 {
5200 /* movl.s %edi, %edi
5201 push %ebp
5202 movl.s %esp, %ebp */
5205 }
5206 }
5207 }
5209 /* regclass.c */
5212 /* Implementation of call abi switching target hook. Specific to FNDECL
5213 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
5214 for more details. */
5215 void
5217 {
5220 else
5222 }
5224 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
5225 re-initialization of init_regs each time we switch function context since
5226 this is needed only during RTL expansion. */
5227 static void
5229 {
5233 }
5235 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5236 for a call to a function whose data type is FNTYPE.
5237 For a library call, FNTYPE is 0. */
5239 void
5243 tree fndecl)
5244 {
5250 else
5252 /* Set up the number of registers to use for passing arguments. */
5259 {
5261 ? X86_64_REGPARM_MAX
5263 }
5265 {
5268 {
5270 ? X86_64_SSE_REGPARM_MAX
5272 }
5273 }
5280 /* Because type might mismatch in between caller and callee, we need to
5281 use actual type of function for local calls.
5282 FIXME: cgraph_analyze can be told to actually record if function uses
5283 va_start so for local functions maybe_vaarg can be made aggressive
5284 helping K&R code.
5285 FIXME: once typesytem is fixed, we won't need this code anymore. */
5293 {
5294 /* If there are variable arguments, then we won't pass anything
5295 in registers in 32-bit mode. */
5297 {
5305 }
5307 /* Use ecx and edx registers if function has fastcall attribute,
5308 else look for regparm information. */
5310 {
5312 {
5315 }
5317 {
5320 }
5321 else
5323 }
5325 /* Set up the number of SSE registers used for passing SFmode
5326 and DFmode arguments. Warn for mismatching ABI. */
5328 }
5329 }
5331 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5332 But in the case of vector types, it is some vector mode.
5334 When we have only some of our vector isa extensions enabled, then there
5335 are some modes for which vector_mode_supported_p is false. For these
5336 modes, the generic vector support in gcc will choose some non-vector mode
5337 in order to implement the type. By computing the natural mode, we'll
5338 select the proper ABI location for the operand and not depend on whatever
5339 the middle-end decides to do with these vector types.
5341 The midde-end can't deal with the vector types > 16 bytes. In this
5342 case, we return the original mode and warn ABI change if CUM isn't
5343 NULL. */
5345 static enum machine_mode
5347 {
5351 {
5354 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5356 {
5361 else
5364 /* Get the mode which has this inner mode and number of units. */
5368 {
5370 {
5374 && !warnedavx
5376 {
5380 }
5382 }
5383 else
5385 }
5388 }
5389 }
5392 }
5394 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5395 this may not agree with the mode that the type system has chosen for the
5396 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5397 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5399 static rtx
5402 {
5403 rtx tmp;
5407 else
5408 {
5412 }
5415 }
5417 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5418 of this code is to classify each 8bytes of incoming argument by the register
5419 class and assign registers accordingly. */
5421 /* Return the union class of CLASS1 and CLASS2.
5422 See the x86-64 PS ABI for details. */
5424 static enum x86_64_reg_class
5426 {
5427 /* Rule #1: If both classes are equal, this is the resulting class. */
5431 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5432 the other class. */
5438 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5442 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5450 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5451 MEMORY is used. */
5460 /* Rule #6: Otherwise class SSE is used. */
5462 }
5464 /* Classify the argument of type TYPE and mode MODE.
5465 CLASSES will be filled by the register class used to pass each word
5466 of the operand. The number of words is returned. In case the parameter
5467 should be passed in memory, 0 is returned. As a special case for zero
5468 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5470 BIT_OFFSET is used internally for handling records and specifies offset
5471 of the offset in bits modulo 256 to avoid overflow cases.
5473 See the x86-64 PS ABI for details.
5474 */
5476 static int
5479 {
5480 HOST_WIDE_INT bytes =
5484 /* Variable sized entities are always passed/returned in memory. */
5493 {
5495 tree field;
5498 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5505 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5506 signalize memory class, so handle it as special case. */
5508 {
5511 }
5513 /* Classify each field of record and merge classes. */
5515 {
5517 /* And now merge the fields of structure. */
5519 {
5521 {
5527 /* Bitfields are always classified as integer. Handle them
5528 early, since later code would consider them to be
5529 misaligned integers. */
5531 {
5539 }
5540 else
5541 {
5546 /* Flexible array member is ignored. */
5553 {
5557 {
5560 "The ABI of passing struct with"
5561 " a flexible array member has"
5563 }
5565 }
5567 subclasses,
5576 }
5577 }
5578 }
5582 /* Arrays are handled as small records. */
5583 {
5590 /* The partial classes are now full classes. */
5601 }
5604 /* Unions are similar to RECORD_TYPE but offset is always 0.
5605 */
5607 {
5609 {
5617 bit_offset);
5622 }
5623 }
5628 }
5631 {
5632 /* When size > 16 bytes, if the first one isn't
5633 X86_64_SSE_CLASS or any other ones aren't
5634 X86_64_SSEUP_CLASS, everything should be passed in
5635 memory. */
5642 }
5644 /* Final merger cleanup. */
5646 {
5647 /* If one class is MEMORY, everything should be passed in
5648 memory. */
5652 /* The X86_64_SSEUP_CLASS should be always preceded by
5653 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5657 {
5658 /* The first one should never be X86_64_SSEUP_CLASS. */
5661 }
5663 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5664 everything should be passed in memory. */
5667 {
5670 /* The first one should never be X86_64_X87UP_CLASS. */
5673 {
5676 "The ABI of passing union with long double"
5678 }
5680 }
5681 }
5683 }
5685 /* Compute alignment needed. We align all types to natural boundaries with
5686 exception of XFmode that is aligned to 64bits. */
5688 {
5697 /* Misaligned fields are always returned in memory. */
5700 }
5702 /* for V1xx modes, just use the base mode */
5707 /* Classification of atomic types. */
5709 {
5725 {
5729 {
5732 }
5734 {
5737 }
5739 {
5743 }
5745 {
5748 }
5749 else
5751 }
5758 /* OImode shouldn't be used directly. */
5765 else
5783 else
5784 {
5788 {
5791 "The ABI of passing structure with complex float"
5793 }
5796 }
5805 /* This modes is larger than 16 bytes. */
5848 else
5852 }
5853 }
5855 /* Examine the argument and return set number of register required in each
5856 class. Return 0 iff parameter should be passed in memory. */
5857 static int
5860 {
5870 {
5892 }
5894 }
5896 /* Construct container for the argument used by GCC interface. See
5897 FUNCTION_ARG for the detailed description. */
5899 static rtx
5903 {
5904 /* The following variables hold the static issued_error state. */
5918 rtx ret;
5929 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5930 some less clueful developer tries to use floating-point anyway. */
5932 {
5934 {
5936 {
5939 }
5940 }
5942 {
5945 }
5947 }
5949 /* Likewise, error if the ABI requires us to return values in the
5950 x87 registers and the user specified -mno-80387. */
5956 {
5958 {
5961 }
5963 }
5965 /* First construct simple cases. Avoid SCmode, since we want to use
5966 single register to pass this type. */
5969 {
5984 /* Zero sized array, struct or class. */
5988 }
6009 /* Otherwise figure out the entries of the PARALLEL. */
6011 {
6015 {
6020 /* Merge TImodes on aligned occasions here too. */
6025 else
6027 /* We've requested 24 bytes we don't have mode for. Use DImode. */
6033 intreg++;
6040 sse_regno++;
6047 sse_regno++;
6052 {
6058 {
6060 i++;
6061 }
6062 else
6075 }
6080 sse_regno++;
6084 }
6085 }
6087 /* Empty aligned struct, union or class. */
6095 }
6097 /* Update the data in CUM to advance over an argument of mode MODE
6098 and data type TYPE. (TYPE is null for libcalls where that information
6099 may not be available.) */
6101 static void
6104 HOST_WIDE_INT words)
6105 {
6107 {
6114 /* FALLTHRU */
6125 {
6128 }
6132 /* OImode shouldn't be used directly. */
6141 /* FALLTHRU */
6157 {
6162 {
6165 }
6166 }
6176 {
6181 {
6184 }
6185 }
6187 }
6188 }
6190 static void
6193 {
6196 /* Unnamed 256bit vector mode parameters are passed on stack. */
6202 {
6207 }
6208 else
6209 {
6213 }
6214 }
6216 static void
6218 HOST_WIDE_INT words)
6219 {
6220 /* Otherwise, this should be passed indirect. */
6225 {
6228 }
6229 }
6231 /* Update the data in CUM to advance over an argument of mode MODE and
6232 data type TYPE. (TYPE is null for libcalls where that information
6233 may not be available.) */
6235 static void
6238 {
6243 else
6254 else
6256 }
6258 /* Define where to put the arguments to a function.
6259 Value is zero to push the argument on the stack,
6260 or a hard register in which to store the argument.
6262 MODE is the argument's machine mode.
6263 TYPE is the data type of the argument (as a tree).
6264 This is null for libcalls where that information may
6265 not be available.
6266 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6267 the preceding args and about the function being called.
6268 NAMED is nonzero if this argument is a named parameter
6269 (otherwise it is an extra parameter matching an ellipsis). */
6271 static rtx
6275 {
6278 /* Avoid the AL settings for the Unix64 ABI. */
6283 {
6290 /* FALLTHRU */
6296 {
6299 /* Fastcall allocates the first two DWORD (SImode) or
6300 smaller arguments to ECX and EDX if it isn't an
6301 aggregate type . */
6303 {
6309 /* ECX not EAX is the first allocated register. */
6312 }
6314 }
6323 /* FALLTHRU */
6325 /* In 32bit, we pass TImode in xmm registers. */
6333 {
6335 {
6339 }
6343 }
6347 /* OImode shouldn't be used directly. */
6357 {
6361 }
6371 {
6373 {
6377 }
6381 }
6383 }
6386 }
6388 static rtx
6391 {
6392 /* Handle a hidden AL argument containing number of registers
6393 for varargs x86-64 functions. */
6397 ? X86_64_SSE_REGPARM_MAX
6402 {
6412 /* Unnamed 256bit vector mode parameters are passed on stack. */
6416 }
6422 }
6424 static rtx
6427 HOST_WIDE_INT bytes)
6428 {
6431 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6432 We use value of -2 to specify that current function call is MSABI. */
6436 /* If we've run out of registers, it goes on the stack. */
6442 /* Only floating point modes are passed in anything but integer regs. */
6444 {
6447 else
6448 {
6451 /* Unnamed floating parameters are passed in both the
6452 SSE and integer registers. */
6458 }
6459 }
6460 /* Handle aggregated types passed in register. */
6462 {
6467 }
6470 }
6472 /* Return where to put the arguments to a function.
6473 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6475 MODE is the argument's machine mode. TYPE is the data type of the
6476 argument. It is null for libcalls where that information may not be
6477 available. CUM gives information about the preceding args and about
6478 the function being called. NAMED is nonzero if this argument is a
6479 named parameter (otherwise it is an extra parameter matching an
6480 ellipsis). */
6482 static rtx
6485 {
6491 else
6495 /* To simplify the code below, represent vector types with a vector mode
6496 even if MMX/SSE are not active. */
6504 else
6506 }
6508 /* A C expression that indicates when an argument must be passed by
6509 reference. If nonzero for an argument, a copy of that argument is
6510 made in memory and a pointer to the argument is passed instead of
6511 the argument itself. The pointer is passed in whatever way is
6512 appropriate for passing a pointer to that type. */
6514 static bool
6518 {
6519 /* See Windows x64 Software Convention. */
6521 {
6524 {
6525 /* Arrays are passed by reference. */
6530 {
6531 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6532 are passed by reference. */
6534 }
6535 }
6537 /* __m128 is passed by reference. */
6543 }
6544 }
6549 }
6551 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6552 ABI. */
6553 static bool
6555 {
6567 {
6568 /* Walk the aggregates recursively. */
6570 {
6574 {
6575 tree field;
6577 /* Walk all the structure fields. */
6579 {
6583 }
6585 }
6588 /* Just for use if some languages passes arrays by value. */
6595 }
6596 }
6598 }
6600 /* Gives the alignment boundary, in bits, of an argument with the
6601 specified mode and type. */
6603 int
6605 {
6608 {
6609 /* Since the main variant type is used for call, we convert it to
6610 the main variant type. */
6613 }
6614 else
6618 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6619 natural boundaries. */
6621 {
6622 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6623 make an exception for SSE modes since these require 128bit
6624 alignment.
6626 The handling here differs from field_alignment. ICC aligns MMX
6627 arguments to 4 byte boundaries, while structure fields are aligned
6628 to 8 byte boundaries. */
6630 {
6633 }
6634 else
6635 {
6638 }
6639 }
6643 }
6645 /* Return true if N is a possible register number of function value. */
6647 static bool
6649 {
6651 {
6656 /* TODO: The function should depend on current function ABI but
6657 builtins.c would need updating then. Therefore we use the
6658 default ABI. */
6670 }
6673 }
6675 /* Define how to find the value returned by a function.
6676 VALTYPE is the data type of the value (as a tree).
6677 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6678 otherwise, FUNC is 0. */
6680 static rtx
6683 {
6686 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6687 we normally prevent this case when mmx is not available. However
6688 some ABIs may require the result to be returned like DImode. */
6692 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6693 we prevent this case when sse is not available. However some ABIs
6694 may require the result to be returned like integer TImode. */
6699 /* 32-byte vector modes in %ymm0. */
6703 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6706 else
6707 /* Most things go in %eax. */
6710 /* Override FP return register with %xmm0 for local functions when
6711 SSE math is enabled or for functions with sseregparm attribute. */
6713 {
6718 }
6720 /* OImode shouldn't be used directly. */
6724 }
6726 static rtx
6728 const_tree valtype)
6729 {
6730 rtx ret;
6732 /* Handle libcalls, which don't provide a type node. */
6734 {
6736 {
6753 }
6754 }
6760 /* For zero sized structures, construct_container returns NULL, but we
6761 need to keep rest of compiler happy by returning meaningful value. */
6766 }
6768 static rtx
6770 {
6774 {
6776 {
6789 }
6790 }
6792 }
6794 static rtx
6797 {
6809 else
6811 }
6813 static rtx
6816 {
6822 }
6824 rtx
6826 {
6828 }
6830 /* Return true iff type is returned in memory. */
6832 static bool ATTRIBUTE_UNUSED
6834 {
6835 HOST_WIDE_INT size;
6846 {
6847 /* User-created vectors small enough to fit in EAX. */
6851 /* MMX/3dNow values are returned in MM0,
6852 except when it doesn't exits. */
6856 /* SSE values are returned in XMM0, except when it doesn't exist. */
6860 /* AVX values are returned in YMM0, except when it doesn't exist. */
6863 }
6871 /* OImode shouldn't be used directly. */
6875 }
6877 static bool ATTRIBUTE_UNUSED
6879 {
6882 }
6884 static bool ATTRIBUTE_UNUSED
6886 {
6889 /* __m128 is returned in xmm0. */
6894 /* Otherwise, the size must be exactly in [1248]. */
6896 }
6898 static bool
6900 {
6901 #ifdef SUBTARGET_RETURN_IN_MEMORY
6903 #else
6907 {
6910 else
6912 }
6913 else
6915 #endif
6916 }
6918 /* Return false iff TYPE is returned in memory. This version is used
6919 on Solaris 2. It is similar to the generic ix86_return_in_memory,
6920 but differs notably in that when MMX is available, 8-byte vectors
6921 are returned in memory, rather than in MMX registers. */
6923 bool
6925 {
6938 {
6939 /* Return in memory only if MMX registers *are* available. This
6940 seems backwards, but it is consistent with the existing
6941 Solaris x86 ABI. */
6946 }
6953 }
6955 /* When returning SSE vector types, we have a choice of either
6956 (1) being abi incompatible with a -march switch, or
6957 (2) generating an error.
6958 Given no good solution, I think the safest thing is one warning.
6959 The user won't be able to use -Werror, but....
6961 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6962 called in response to actually generating a caller or callee that
6963 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6964 via aggregate_value_p for general type probing from tree-ssa. */
6966 static rtx
6968 {
6972 {
6973 /* Look at the return type of the function, not the function type. */
6977 {
6980 {
6984 }
6985 }
6988 {
6990 {
6994 }
6995 }
6996 }
6999 }
7001 \f
7002 /* Create the va_list data type. */
7004 /* Returns the calling convention specific va_list date type.
7005 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7007 static tree
7009 {
7012 /* For i386 we use plain pointer to argument area. */
7022 unsigned_type_node);
7025 unsigned_type_node);
7028 ptr_type_node);
7031 ptr_type_node);
7050 /* The correct type is an array type of one element. */
7052 }
7054 /* Setup the builtin va_list data type and for 64-bit the additional
7055 calling convention specific va_list data types. */
7057 static tree
7059 {
7062 /* Initialize abi specific va_list builtin types. */
7064 {
7065 tree t;
7067 {
7072 }
7073 else
7074 {
7079 }
7081 {
7086 }
7087 else
7088 {
7093 }
7094 }
7097 }
7099 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7101 static void
7103 {
7105 alias_set_type set;
7108 /* GPR size of varargs save area. */
7111 else
7114 /* FPR size of varargs save area. We don't need it if we don't pass
7115 anything in SSE registers. */
7118 else
7132 {
7139 }
7142 {
7146 /* Now emit code to save SSE registers. The AX parameter contains number
7147 of SSE parameter registers used to call this function, though all we
7148 actually check here is the zero/non-zero status. */
7153 label));
7155 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7156 we used movdqa (i.e. TImode) instead? Perhaps even better would
7157 be if we could determine the real mode of the data, via a hook
7158 into pass_stdarg. Ignore all that for now. */
7168 {
7176 }
7179 }
7180 }
7182 static void
7184 {
7189 {
7200 }
7201 }
7203 static void
7207 {
7208 CUMULATIVE_ARGS next_cum;
7209 tree fntype;
7211 /* This argument doesn't appear to be used anymore. Which is good,
7212 because the old code here didn't suppress rtl generation. */
7220 /* For varargs, we do not want to skip the dummy va_dcl argument.
7221 For stdargs, we do want to skip the last named argument. */
7228 else
7230 }
7232 /* Checks if TYPE is of kind va_list char *. */
7234 static bool
7236 {
7237 tree canonic;
7239 /* For 32-bit it is always true. */
7245 }
7247 /* Implement va_start. */
7249 static void
7251 {
7255 tree type;
7257 rtx ovf_rtx;
7261 {
7265 /* When we are splitting the stack, we can't refer to the stack
7266 arguments using internal_arg_pointer, because they may be on
7267 the old stack. The split stack prologue will arrange to
7268 leave a pointer to the old stack arguments in a scratch
7269 register, which we here copy to a pseudo-register. The split
7270 stack prologue can't set the pseudo-register directly because
7271 it (the prologue) runs before any registers have been saved. */
7284 }
7286 /* Only 64bit target needs something special. */
7288 {
7291 else
7292 {
7301 }
7303 }
7312 /* The following should be folded into the MEM_REF offset. */
7322 /* Count number of gp and fp argument registers used. */
7328 {
7334 }
7337 {
7343 }
7345 /* Find the overflow area. */
7349 else
7360 {
7361 /* Find the register save area.
7362 Prologue of the function save it right above stack frame. */
7371 }
7372 }
7374 /* Implement va_arg. */
7376 static tree
7379 {
7386 rtx container;
7388 tree ptrtype;
7392 /* Only 64bit target needs something special. */
7416 {
7423 /* Unnamed 256bit vector mode parameters are passed on stack. */
7425 {
7428 }
7436 }
7438 /* Pull the value out of the saved registers. */
7443 {
7457 /* In case we are passing structure, verify that it is consecutive block
7458 on the register save area. If not we need to do moves. */
7460 {
7461 /* Verify that all registers are strictly consecutive */
7463 {
7467 {
7472 }
7473 }
7474 else
7475 {
7479 {
7484 }
7485 }
7486 }
7488 {
7491 }
7492 else
7493 {
7496 }
7498 /* First ensure that we fit completely in registers. */
7500 {
7507 }
7509 {
7517 }
7519 /* Compute index to start of area used for integer regs. */
7521 {
7522 /* int_addr = gpr + sav; */
7526 }
7528 {
7529 /* sse_addr = fpr + sav; */
7533 }
7535 {
7539 /* addr = &temp; */
7544 {
7548 tree piece_type;
7549 tree addr_type;
7550 tree daddr_type;
7557 {
7562 }
7566 else
7573 {
7576 }
7577 else
7578 {
7581 }
7590 {
7595 }
7596 else
7597 {
7598 tree copy
7603 }
7605 }
7606 }
7609 {
7613 }
7616 {
7620 }
7625 }
7627 /* ... otherwise out of the overflow area. */
7629 /* When we align parameter on stack for caller, if the parameter
7630 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7631 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7632 here with caller. */
7637 /* Care for on-stack alignment if needed. */
7640 else
7641 {
7649 }
7667 }
7668 \f
7669 /* Return true if OPNUM's MEM should be matched
7670 in movabs* patterns. */
7672 bool
7674 {
7686 }
7687 \f
7688 /* Initialize the table of extra 80387 mathematical constants. */
7690 static void
7692 {
7694 {
7700 };
7704 {
7706 /* Ensure each constant is rounded to XFmode precision. */
7709 }
7712 }
7714 /* Return non-zero if the constant is something that
7715 can be loaded with a special instruction. */
7717 int
7719 {
7722 REAL_VALUE_TYPE r;
7734 /* For XFmode constants, try to find a special 80387 instruction when
7735 optimizing for size or on those CPUs that benefit from them. */
7738 {
7747 }
7749 /* Load of the constant -0.0 or -1.0 will be split as
7750 fldz;fchs or fld1;fchs sequence. */
7757 }
7759 /* Return the opcode of the special instruction to be used to load
7760 the constant X. */
7764 {
7766 {
7786 }
7787 }
7789 /* Return the CONST_DOUBLE representing the 80387 constant that is
7790 loaded by the specified special instruction. The argument IDX
7791 matches the return value from standard_80387_constant_p. */
7793 rtx
7795 {
7802 {
7813 }
7816 XFmode);
7817 }
7819 /* Return 1 if X is all 0s and 2 if x is all 1s
7820 in supported SSE vector mode. */
7822 int
7824 {
7831 {
7840 }
7843 }
7845 /* Return the opcode of the special instruction to be used to load
7846 the constant X. */
7850 {
7852 {
7855 {
7861 else
7866 else
7873 else
7878 else
7882 }
7887 }
7889 }
7891 /* Returns true if OP contains a symbol reference */
7893 bool
7895 {
7904 {
7906 {
7912 }
7916 }
7919 }
7921 /* Return true if it is appropriate to emit `ret' instructions in the
7922 body of a function. Do this only if the epilogue is simple, needing a
7923 couple of insns. Prior to reloading, we can't tell how many registers
7924 must be saved, so return false then. Return false if there is no frame
7925 marker to de-allocate. */
7927 bool
7929 {
7935 /* Don't allow more than 32k pop, since that's all we can do
7936 with one instruction. */
7943 }
7944 \f
7945 /* Value should be nonzero if functions must have frame pointers.
7946 Zero means the frame pointer need not be set up (and parms may
7947 be accessed via the stack pointer) in functions that seem suitable. */
7949 static bool
7951 {
7952 /* If we accessed previous frames, then the generated code expects
7953 to be able to access the saved ebp value in our frame. */
7957 /* Several x86 os'es need a frame pointer for other reasons,
7958 usually pertaining to setjmp. */
7962 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
7963 turns off the frame pointer by default. Turn it back on now if
7964 we've not got a leaf function. */
7966 && (!current_function_is_leaf
7974 }
7976 /* Record that the current function accesses previous call frames. */
7978 void
7980 {
7982 }
7983 \f
7984 #ifndef USE_HIDDEN_LINKONCE
7985 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7986 # define USE_HIDDEN_LINKONCE 1
7987 # else
7988 # define USE_HIDDEN_LINKONCE 0
7989 # endif
7990 #endif
7994 /* Fills in the label name that should be used for a pc thunk for
7995 the given register. */
7997 static void
7999 {
8004 else
8006 }
8009 /* This function generates code for -fpic that loads %ebx with
8010 the return address of the caller and then returns. */
8012 static void
8014 {
8019 {
8021 tree decl;
8036 #if TARGET_MACHO
8038 {
8047 }
8048 else
8049 #endif
8051 {
8062 }
8063 else
8064 {
8067 }
8073 /* Make sure unwind info is emitted for the thunk if needed. */
8078 /* Pad stack IP move with 4 instructions. 2 NOPs count as 1
8079 instruction. */
8082 xops);
8090 }
8094 }
8096 /* Emit code for the SET_GOT patterns. */
8100 {
8106 {
8107 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8112 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8113 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8114 an unadorned address. */
8119 }
8124 {
8129 else
8130 {
8132 #ifdef DWARF2_UNWIND_INFO
8133 /* The call to next label acts as a push. */
8135 {
8136 rtx insn;
8140 stack_pointer_rtx,
8145 }
8146 #endif
8147 }
8149 #if TARGET_MACHO
8150 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8151 is what will be referenced by the Mach-O PIC subsystem. */
8154 #endif
8160 {
8162 #ifdef DWARF2_UNWIND_INFO
8163 /* The pop is a pop and clobbers dest, but doesn't restore it
8164 for unwind info purposes. */
8166 {
8167 rtx insn;
8173 stack_pointer_rtx,
8178 }
8179 #endif
8180 }
8181 }
8182 else
8183 {
8188 #ifdef DWARF2_UNWIND_INFO
8189 /* Ensure all queued register saves are flushed before the
8190 call. */
8193 #endif
8197 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8198 is what will be referenced by the Mach-O PIC subsystem. */
8199 #if TARGET_MACHO
8202 else
8205 #endif
8206 }
8213 else
8217 }
8219 /* Generate an "push" pattern for input ARG. */
8221 static rtx
8223 {
8233 stack_pointer_rtx)),
8234 arg);
8235 }
8237 /* Generate an "pop" pattern for input ARG. */
8239 static rtx
8241 {
8243 arg,
8246 stack_pointer_rtx)));
8247 }
8249 /* Return >= 0 if there is an unused call-clobbered register available
8250 for the entire function. */
8252 static unsigned int
8254 {
8258 {
8260 /* Can't use the same register for both PIC and DRAP. */
8263 else
8268 }
8271 }
8273 /* Return 1 if we need to save REGNO. */
8274 static int
8276 {
8283 {
8287 }
8290 {
8293 {
8299 }
8300 }
8309 }
8311 /* Return number of saved general prupose registers. */
8313 static int
8315 {
8321 nregs ++;
8323 }
8325 /* Return number of saved SSE registrers. */
8327 static int
8329 {
8337 nregs ++;
8339 }
8341 /* Given FROM and TO register numbers, say whether this elimination is
8342 allowed. If stack alignment is needed, we can only replace argument
8343 pointer with hard frame pointer, or replace frame pointer with stack
8344 pointer. Otherwise, frame pointer elimination is automatically
8345 handled and all other eliminations are valid. */
8347 static bool
8349 {
8355 else
8357 }
8359 /* Return the offset between two registers, one to be eliminated, and the other
8360 its replacement, at the start of a routine. */
8362 HOST_WIDE_INT
8364 {
8373 else
8374 {
8382 }
8383 }
8385 /* In a dynamically-aligned function, we can't know the offset from
8386 stack pointer to frame pointer, so we must ensure that setjmp
8387 eliminates fp against the hard fp (%ebp) rather than trying to
8388 index from %esp up to the top of the frame across a gap that is
8389 of unknown (at compile-time) size. */
8390 static rtx
8392 {
8394 }
8396 /* On the x86 -fsplit-stack and -fstack-protector both use the same
8397 field in the TCB, so they can not be used together. */
8399 static bool
8401 {
8404 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
8408 #endif
8411 }
8413 /* When using -fsplit-stack, the allocation routines set a field in
8414 the TCB to the bottom of the stack plus this much space, measured
8415 in bytes. */
8417 #define SPLIT_STACK_AVAILABLE 256
8419 /* Fill structure ix86_frame about frame of currently computed function. */
8421 static void
8423 {
8425 HOST_WIDE_INT offset;
8428 HOST_WIDE_INT to_allocate;
8436 /* MS ABI seem to require stack alignment to be always 16 except for function
8437 prologues and leaf. */
8441 {
8446 }
8452 /* During reload iteration the amount of registers saved can change.
8453 Recompute the value as needed. Do not recompute when amount of registers
8454 didn't change as reload does multiple calls to the function and does not
8455 expect the decision to change within single iteration. */
8458 {
8463 /* The fast prologue uses move instead of push to save registers. This
8464 is significantly longer, but also executes faster as modern hardware
8465 can execute the moves in parallel, but can't do that for push/pop.
8467 Be careful about choosing what prologue to emit: When function takes
8468 many instructions to execute we may use slow version as well as in
8469 case function is known to be outside hot spot (this is known with
8470 feedback only). Weight the size of function by number of registers
8471 to save as it is cheap to use one or two push instructions but very
8472 slow to use many of them. */
8476 || (flag_branch_probabilities
8479 else
8482 }
8486 else
8489 /* If static stack checking is enabled and done with probes, the registers
8490 need to be saved before allocating the frame. */
8494 /* Skip return address. */
8497 /* Skip pushed static chain. */
8501 /* Skip saved base pointer. */
8507 /* Register save area */
8511 /* Align and set SSE register save area. */
8513 {
8514 /* The only ABI that has saved SSE registers (Win64) also has a
8515 16-byte aligned default stack, and thus we don't need to be
8516 within the re-aligned local stack frame to save them. */
8520 }
8523 /* The re-aligned stack starts here. Values before this point are not
8524 directly comparable with values below this point. In order to make
8525 sure that no value happens to be the same before and after, force
8526 the alignment computation below to add a non-zero value. */
8530 /* Va-arg area */
8534 /* Align start of frame for local function. */
8537 /* Frame pointer points here. */
8542 /* Add outgoing arguments area. Can be skipped if we eliminated
8543 all the function calls as dead code.
8544 Skipping is however impossible when function calls alloca. Alloca
8545 expander assumes that last crtl->outgoing_args_size
8546 of stack frame are unused. */
8550 {
8553 }
8554 else
8557 /* Align stack boundary. Only needed if we're calling another function
8558 or using alloca. */
8563 /* We've reached end of stack frame. */
8566 /* Size prologue needs to allocate. */
8574 && current_function_sp_is_unchanging
8575 && current_function_is_leaf
8577 {
8583 }
8584 else
8587 }
8589 /* This is semi-inlined memory_address_length, but simplified
8590 since we know that we're always dealing with reg+offset, and
8591 to avoid having to create and discard all that rtl. */
8595 {
8599 {
8600 /* EBP and R13 cannot be encoded without an offset. */
8602 }
8606 /* ESP and R12 must be encoded with a SIB byte. */
8608 len++;
8611 }
8613 /* Return an RTX that points to CFA_OFFSET within the stack frame.
8614 The valid base registers are taken from CFUN->MACHINE->FS. */
8616 static rtx
8618 {
8624 {
8625 /* Choose the base register most likely to allow the most scheduling
8626 opportunities. Generally FP is valid througout the function,
8627 while DRAP must be reloaded within the epilogue. But choose either
8628 over the SP due to increased encoding size. */
8631 {
8634 }
8636 {
8639 }
8641 {
8644 }
8645 }
8646 else
8647 {
8648 HOST_WIDE_INT toffset;
8651 /* Choose the base register with the smallest address encoding.
8652 With a tie, choose FP > DRAP > SP. */
8654 {
8658 }
8660 {
8664 {
8668 }
8669 }
8671 {
8675 {
8679 }
8680 }
8681 }
8685 }
8687 /* Emit code to save registers in the prologue. */
8689 static void
8691 {
8693 rtx insn;
8697 {
8700 }
8701 }
8703 /* Emit a single register save at CFA - CFA_OFFSET. */
8705 static void
8707 HOST_WIDE_INT cfa_offset)
8708 {
8716 /* For SSE saves, we need to indicate the 128-bit alignment. */
8727 /* When saving registers into a re-aligned local stack frame, avoid
8728 any tricky guessing by dwarf2out. */
8730 {
8734 {
8735 /* A bit of a hack. We force the DRAP register to be saved in
8736 the re-aligned stack frame, which provides us with a copy
8737 of the CFA that will last past the prologue. Install it. */
8743 }
8744 else
8745 {
8746 /* The frame pointer is a stable reference within the
8747 aligned frame. Use it. */
8754 }
8755 }
8757 /* The memory may not be relative to the current CFA register,
8758 which means that we may need to generate a new pattern for
8759 use by the unwind info. */
8761 {
8765 }
8766 }
8768 /* Emit code to save registers using MOV insns.
8769 First register is stored at CFA - CFA_OFFSET. */
8770 static void
8772 {
8777 {
8780 }
8781 }
8783 /* Emit code to save SSE registers using MOV insns.
8784 First register is stored at CFA - CFA_OFFSET. */
8785 static void
8787 {
8792 {
8795 }
8796 }
8800 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8801 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
8802 Don't add the note if the previously saved value will be left untouched
8803 within stack red-zone till return, as unwinders can find the same value
8804 in the register and on the stack. */
8806 static void
8808 {
8813 {
8816 }
8817 else
8818 queued_cfa_restores
8820 }
8822 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8824 static void
8826 {
8827 rtx last;
8831 ;
8836 }
8838 /* Expand prologue or epilogue stack adjustment.
8839 The pattern exist to put a dependency on all ebp-based memory accesses.
8840 STYLE should be negative if instructions should be marked as frame related,
8841 zero if %r11 register is live and cannot be freely used and positive
8842 otherwise. */
8844 static void
8847 {
8849 rtx insn;
8855 else
8856 {
8857 rtx tmp;
8858 /* r11 is used by indirect sibcall return as well, set before the
8859 epilogue and used after the epilogue. */
8862 else
8863 {
8867 }
8872 offset));
8873 }
8879 {
8880 rtx r;
8890 }
8895 {
8900 {
8903 }
8905 {
8908 }
8909 else
8910 {
8911 /* Else there are two possibilities: SP itself, which we set
8912 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
8913 taken care of this by hand along the eh_return path. */
8916 }
8920 }
8921 }
8923 /* Find an available register to be used as dynamic realign argument
8924 pointer regsiter. Such a register will be written in prologue and
8925 used in begin of body, so it must not be
8926 1. parameter passing register.
8927 2. GOT pointer.
8928 We reuse static-chain register if it is available. Otherwise, we
8929 use DI for i386 and R13 for x86-64. We chose R13 since it has
8930 shorter encoding.
8932 Return: the regno of chosen register. */
8934 static unsigned int
8936 {
8940 {
8941 /* Use R13 for nested function or function need static chain.
8942 Since function with tail call may use any caller-saved
8943 registers in epilogue, DRAP must not use caller-saved
8944 register in such case. */
8949 }
8950 else
8951 {
8952 /* Use DI for nested function or function need static chain.
8953 Since function with tail call may use any caller-saved
8954 registers in epilogue, DRAP must not use caller-saved
8955 register in such case. */
8959 /* Reuse static chain register if it isn't used for parameter
8960 passing. */
8967 else
8969 }
8970 }
8972 /* Return minimum incoming stack alignment. */
8974 static unsigned int
8976 {
8979 /* Prefer the one specified at command line. */
8982 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8983 if -mstackrealign is used, it isn't used for sibcall check and
8984 estimated stack alignment is 128bit. */
8986 && !TARGET_64BIT
8987 && ix86_force_align_arg_pointer
8990 else
8993 /* Incoming stack alignment can be changed on individual functions
8994 via force_align_arg_pointer attribute. We use the smallest
8995 incoming stack boundary. */
9001 /* The incoming stack frame has to be aligned at least at
9002 parm_stack_boundary. */
9006 /* Stack at entrance of main is aligned by runtime. We use the
9007 smallest incoming stack boundary. */
9015 }
9017 /* Update incoming stack boundary and estimated stack alignment. */
9019 static void
9021 {
9022 ix86_incoming_stack_boundary
9025 /* x86_64 vararg needs 16byte stack alignment for register save
9026 area. */
9031 }
9033 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9034 needed or an rtx for DRAP otherwise. */
9036 static rtx
9038 {
9043 {
9044 /* Assign DRAP to vDRAP and returns vDRAP */
9046 rtx drap_vreg;
9047 rtx arg_ptr;
9060 {
9063 }
9065 }
9066 else
9068 }
9070 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9072 static rtx
9074 {
9076 }
9079 rtx reg;
9081 };
9083 /* Return a short-lived scratch register for use on function entry.
9084 In 32-bit mode, it is valid only after the registers are saved
9085 in the prologue. This register must be released by means of
9086 release_scratch_register_on_entry once it is dead. */
9088 static void
9090 {
9096 {
9097 /* We always use R11 in 64-bit mode. */
9099 }
9100 else
9101 {
9103 bool fastcall_p
9107 int drap_regno
9110 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9111 for the static chain register. */
9117 /* ecx is the static chain register. */
9123 /* esi is the static chain register. */
9129 else
9130 {
9133 }
9134 }
9138 {
9141 }
9142 }
9144 /* Release a scratch register obtained from the preceding function. */
9146 static void
9148 {
9150 {
9153 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9158 }
9159 }
9161 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9163 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9165 static void
9167 {
9168 /* We skip the probe for the first interval + a small dope of 4 words and
9169 probe that many bytes past the specified size to maintain a protection
9170 area at the botton of the stack. */
9174 /* See if we have a constant small number of probes to generate. If so,
9175 that's the easy case. The run-time loop is made up of 11 insns in the
9176 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9177 for n # of intervals. */
9179 {
9183 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9184 values of N from 1 until it exceeds SIZE. If only one probe is
9185 needed, this will not generate any code. Then adjust and probe
9186 to PROBE_INTERVAL + SIZE. */
9188 {
9190 {
9193 }
9194 else
9200 }
9204 else
9211 /* Adjust back to account for the additional first interval. */
9215 }
9217 /* Otherwise, do the same as above, but in a loop. Note that we must be
9218 extra careful with variables wrapping around because we might be at
9219 the very top (or the very bottom) of the address space and we have
9220 to be able to handle this case properly; in particular, we use an
9221 equality test for the loop condition. */
9222 else
9223 {
9224 HOST_WIDE_INT rounded_size;
9230 /* Step 1: round SIZE to the previous multiple of the interval. */
9235 /* Step 2: compute initial and final value of the loop counter. */
9237 /* SP = SP_0 + PROBE_INTERVAL. */
9242 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9246 stack_pointer_rtx)));
9249 /* Step 3: the loop
9251 while (SP != LAST_ADDR)
9252 {
9253 SP = SP + PROBE_INTERVAL
9254 probe at SP
9255 }
9257 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9258 values of N from 1 until it is equal to ROUNDED_SIZE. */
9263 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9264 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9267 {
9272 }
9274 /* Adjust back to account for the additional first interval. */
9280 }
9285 /* Make sure nothing is scheduled before we are done. */
9287 }
9289 /* Adjust the stack pointer up to REG while probing it. */
9293 {
9303 /* Jump to END_LAB if SP == LAST_ADDR. */
9311 /* SP = SP + PROBE_INTERVAL. */
9315 /* Probe at SP. */
9326 }
9328 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9329 inclusive. These are offsets from the current stack pointer. */
9331 static void
9333 {
9334 /* See if we have a constant small number of probes to generate. If so,
9335 that's the easy case. The run-time loop is made up of 7 insns in the
9336 generic case while the compile-time loop is made up of n insns for n #
9337 of intervals. */
9339 {
9340 HOST_WIDE_INT i;
9342 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9343 it exceeds SIZE. If only one probe is needed, this will not
9344 generate any code. Then probe at FIRST + SIZE. */
9349 }
9351 /* Otherwise, do the same as above, but in a loop. Note that we must be
9352 extra careful with variables wrapping around because we might be at
9353 the very top (or the very bottom) of the address space and we have
9354 to be able to handle this case properly; in particular, we use an
9355 equality test for the loop condition. */
9356 else
9357 {
9364 /* Step 1: round SIZE to the previous multiple of the interval. */
9369 /* Step 2: compute initial and final value of the loop counter. */
9371 /* TEST_OFFSET = FIRST. */
9374 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9378 /* Step 3: the loop
9380 while (TEST_ADDR != LAST_ADDR)
9381 {
9382 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9383 probe at TEST_ADDR
9384 }
9386 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9387 until it is equal to ROUNDED_SIZE. */
9392 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9393 that SIZE is equal to ROUNDED_SIZE. */
9397 stack_pointer_rtx,
9402 }
9404 /* Make sure nothing is scheduled before we are done. */
9406 }
9408 /* Probe a range of stack addresses from REG to END, inclusive. These are
9409 offsets from the current stack pointer. */
9413 {
9423 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
9431 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
9435 /* Probe at TEST_ADDR. */
9448 }
9450 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
9451 to be generated in correct form. */
9452 static void
9454 {
9455 /* Check if stack realign is really needed after reload, and
9456 stores result in cfun */
9457 unsigned int incoming_stack_boundary
9461 < (current_function_is_leaf
9466 {
9467 /* After stack_realign_needed is finalized, we can't no longer
9468 change it. */
9470 }
9471 else
9472 {
9475 }
9476 }
9478 /* Expand the prologue into a bunch of separate insns. */
9480 void
9482 {
9487 HOST_WIDE_INT allocate;
9492 /* DRAP should not coexist with stack_realign_fp */
9497 /* Initialize CFA state for before the prologue. */
9501 /* Track SP offset to the CFA. We continue tracking this after we've
9502 swapped the CFA register away from SP. In the case of re-alignment
9503 this is fudged; we're interested to offsets within the local frame. */
9510 {
9511 /* We should have already generated an error for any use of
9512 ms_hook on a nested function. */
9515 /* Check if profiling is active and we shall use profiling before
9516 prologue variant. If so sorry. */
9520 /* In ix86_asm_output_function_label we emitted:
9521 8b ff movl.s %edi,%edi
9522 55 push %ebp
9523 8b ec movl.s %esp,%ebp
9525 This matches the hookable function prologue in Win32 API
9526 functions in Microsoft Windows XP Service Pack 2 and newer.
9527 Wine uses this to enable Windows apps to hook the Win32 API
9528 functions provided by Wine.
9530 What that means is that we've already set up the frame pointer. */
9534 {
9537 /* We've decided to use the frame pointer already set up.
9538 Describe this to the unwinder by pretending that both
9539 push and mov insns happen right here.
9541 Putting the unwind info here at the end of the ms_hook
9542 is done so that we can make absolutely certain we get
9543 the required byte sequence at the start of the function,
9544 rather than relying on an assembler that can produce
9545 the exact encoding required.
9547 However it does mean (in the unpatched case) that we have
9548 a 1 insn window where the asynchronous unwind info is
9549 incorrect. However, if we placed the unwind info at
9550 its correct location we would have incorrect unwind info
9551 in the patched case. Which is probably all moot since
9552 I don't expect Wine generates dwarf2 unwind info for the
9553 system libraries that use this feature. */
9559 stack_pointer_rtx);
9567 /* Note that gen_push incremented m->fs.cfa_offset, even
9568 though we didn't emit the push insn here. */
9572 }
9573 else
9574 {
9575 /* The frame pointer is not needed so pop %ebp again.
9576 This leaves us with a pristine state. */
9578 }
9579 }
9581 /* The first insn of a function that accepts its static chain on the
9582 stack is to push the register that would be filled in by a direct
9583 call. This insn will be skipped by the trampoline. */
9585 {
9589 /* We don't want to interpret this push insn as a register save,
9590 only as a stack adjustment. The real copy of the register as
9591 a save will be done later, if needed. */
9596 }
9598 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
9599 of DRAP is needed and stack realignment is really needed after reload */
9601 {
9604 /* Only need to push parameter pointer reg if it is caller saved. */
9606 {
9607 /* Push arg pointer reg */
9610 }
9612 /* Grab the argument pointer. */
9619 /* Align the stack. */
9621 stack_pointer_rtx,
9625 /* Replicate the return address on the stack so that return
9626 address can be reached via (argp - 1) slot. This is needed
9627 to implement macro RETURN_ADDR_RTX and intrinsic function
9628 expand_builtin_return_addr etc. */
9634 /* For the purposes of frame and register save area addressing,
9635 we've started over with a new frame. */
9638 }
9641 {
9642 /* Note: AT&T enter does NOT have reversed args. Enter is probably
9643 slower on all targets. Also sdb doesn't like it. */
9655 }
9660 {
9661 /* If saving registers via PUSH, do so now. */
9663 {
9667 }
9669 /* When using red zone we may start register saving before allocating
9670 the stack frame saving one cycle of the prologue. However, avoid
9671 doing this if we have to probe the stack; at least on x86_64 the
9672 stack probe can turn into a call that clobbers a red zone location. */
9674 && (! TARGET_STACK_PROBE
9676 {
9679 }
9680 }
9683 {
9687 /* The computation of the size of the re-aligned stack frame means
9688 that we must allocate the size of the register save area before
9689 performing the actual alignment. Otherwise we cannot guarantee
9690 that there's enough storage above the realignment point. */
9697 /* Align the stack. */
9699 stack_pointer_rtx,
9702 /* For the purposes of register save area addressing, the stack
9703 pointer is no longer valid. As for the value of sp_offset,
9704 see ix86_compute_frame_layout, which we need to match in order
9705 to pass verification of stack_pointer_offset at the end. */
9708 }
9713 {
9714 /* We start to count from ARG_POINTER. */
9717 /* If it was realigned, take into account the fake frame. */
9719 {
9726 /* This over-estimates by 1 minimal-stack-alignment-unit but
9727 mitigates that by counting in the new return address slot. */
9728 current_function_dynamic_stack_size
9730 }
9733 }
9735 /* The stack has already been decremented by the instruction calling us
9736 so we need to probe unconditionally to preserve the protection area. */
9738 {
9739 /* We expect the registers to be saved when probes are used. */
9743 {
9746 }
9747 else
9748 {
9756 else
9758 }
9759 }
9762 ;
9765 {
9769 }
9770 else
9771 {
9777 else
9781 {
9784 }
9791 {
9797 }
9801 {
9804 }
9805 }
9817 {
9824 }
9827 {
9829 {
9831 {
9841 }
9842 else
9844 }
9845 else
9847 }
9849 /* In the pic_reg_used case, make sure that the got load isn't deleted
9850 when mcount needs it. Blockage to avoid call movement across mcount
9851 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
9852 note. */
9857 {
9858 /* vDRAP is setup but after reload it turns out stack realign
9859 isn't necessary, here we will emit prologue to setup DRAP
9860 without stack realign adjustment */
9863 }
9865 /* Prevent instructions from being scheduled into register save push
9866 sequence when access to the redzone area is done through frame pointer.
9867 The offset between the frame pointer and the stack pointer is calculated
9868 relative to the value of the stack pointer at the end of the function
9869 prologue, and moving instructions that access redzone area via frame
9870 pointer inside push sequence violates this assumption. */
9874 /* Emit cld instruction if stringops are used in the function. */
9877 }
9879 /* Emit code to restore REG using a POP insn. */
9881 static void
9883 {
9892 {
9893 /* Previously we'd represented the CFA as an expression
9894 like *(%ebp - 8). We've just popped that value from
9895 the stack, which means we need to reset the CFA to
9896 the drap register. This will remain until we restore
9897 the stack pointer. */
9901 /* This means that the DRAP register is valid for addressing too. */
9904 }
9907 {
9914 }
9916 /* When the frame pointer is the CFA, and we pop it, we are
9917 swapping back to the stack pointer as the CFA. This happens
9918 for stack frames that don't allocate other data, so we assume
9919 the stack pointer is now pointing at the return address, i.e.
9920 the function entry state, which makes the offset be 1 word. */
9922 {
9925 {
9933 }
9934 }
9935 }
9937 /* Emit code to restore saved registers using POP insns. */
9939 static void
9941 {
9947 }
9949 /* Emit code and notes for the LEAVE instruction. */
9951 static void
9953 {
9965 {
9974 }
9975 }
9977 /* Emit code to restore saved registers using MOV insns.
9978 First register is restored from CFA - CFA_OFFSET. */
9979 static void
9982 {
9988 {
9997 {
9998 /* Previously we'd represented the CFA as an expression
9999 like *(%ebp - 8). We've just popped that value from
10000 the stack, which means we need to reset the CFA to
10001 the drap register. This will remain until we restore
10002 the stack pointer. */
10006 /* This means that the DRAP register is valid for addressing. */
10008 }
10009 else
10013 }
10014 }
10016 /* Emit code to restore saved registers using MOV insns.
10017 First register is restored from CFA - CFA_OFFSET. */
10018 static void
10021 {
10026 {
10028 rtx mem;
10038 }
10039 }
10041 /* Restore function stack, frame, and registers. */
10043 void
10045 {
10056 || (current_function_sp_is_unchanging
10061 /* The FP must be valid if the frame pointer is present. */
10066 /* We must have *some* valid pointer to the stack frame. */
10069 /* The DRAP is never valid at this point. */
10072 /* See the comment about red zone and frame
10073 pointer usage in ix86_expand_prologue. */
10080 /* Determine the CFA offset of the end of the red-zone. */
10083 {
10084 /* The red-zone begins below the return address. */
10087 /* When the register save area is in the aligned portion of
10088 the stack, determine the maximum runtime displacement that
10089 matches up with the aligned frame. */
10093 }
10095 /* Special care must be taken for the normal return case of a function
10096 using eh_return: the eax and edx registers are marked as saved, but
10097 not restored along this path. Adjust the save location to match. */
10101 /* If we're only restoring one register and sp is not valid then
10102 using a move instruction to restore the register since it's
10103 less work than reloading sp and popping the register. */
10106 /* EH_RETURN requires the use of moves to function properly. */
10119 && TARGET_USE_LEAVE
10123 else
10127 {
10128 /* Ensure that the entire register save area is addressable via
10129 the stack pointer, if we will restore via sp. */
10134 {
10138 style,
10140 }
10141 }
10143 /* If there are any SSE registers to restore, then we have to do it
10144 via moves, since there's obviously no pop for SSE regs. */
10150 {
10151 rtx t;
10156 /* eh_return epilogues need %ecx added to the stack pointer. */
10158 {
10161 /* Stack align doesn't work with eh_return. */
10163 /* Neither does regparm nested functions. */
10167 {
10175 /* Note that we use SA as a temporary CFA, as the return
10176 address is at the proper place relative to it. We
10177 pretend this happens at the FP restore insn because
10178 prior to this insn the FP would be stored at the wrong
10179 offset relative to SA, and after this insn we have no
10180 other reasonable register to use for the CFA. We don't
10181 bother resetting the CFA to the SP for the duration of
10182 the return insn. */
10195 }
10196 else
10197 {
10205 {
10209 UNITS_PER_WORD));
10211 }
10212 }
10215 }
10216 }
10217 else
10218 {
10219 /* First step is to deallocate the stack frame so that we can
10220 pop the registers. */
10222 {
10227 }
10229 {
10233 style,
10235 }
10238 }
10240 /* If we used a stack pointer and haven't already got rid of it,
10241 then do so now. */
10243 {
10244 /* If the stack pointer is valid and pointing at the frame
10245 pointer store address, then we only need a pop. */
10248 /* Leave results in shorter dependency chains on CPUs that are
10249 able to grok it fast. */
10254 else
10255 {
10257 hard_frame_pointer_rtx,
10260 }
10261 }
10264 {
10266 rtx insn;
10292 }
10294 /* At this point the stack pointer must be valid, and we must have
10295 restored all of the registers. We may not have deallocated the
10296 entire stack frame. We've delayed this until now because it may
10297 be possible to merge the local stack deallocation with the
10298 deallocation forced by ix86_static_chain_on_stack. */
10303 {
10307 }
10309 /* Sibcall epilogues don't want a return instruction. */
10311 {
10314 }
10317 {
10320 /* i386 can only pop 64K bytes. If asked to pop more, pop return
10321 address, do explicit add, and jump indirectly to the caller. */
10324 {
10326 rtx insn;
10328 /* There is no "pascal" calling convention in any 64bit ABI. */
10344 }
10345 else
10347 }
10348 else
10351 /* Restore the state back to the state from the prologue,
10352 so that it's correct for the next epilogue. */
10354 }
10356 /* Reset from the function's potential modifications. */
10358 static void
10360 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10361 {
10364 #if TARGET_MACHO
10365 /* Mach-O doesn't support labels at the end of objects, so if
10366 it looks like we might want one, insert a NOP. */
10367 {
10378 }
10379 #endif
10381 }
10383 /* Return a scratch register to use in the split stack prologue. The
10384 split stack prologue is used for -fsplit-stack. It is the first
10385 instructions in the function, even before the regular prologue.
10386 The scratch register can be any caller-saved register which is not
10387 used for parameters or for the static chain. */
10389 static unsigned int
10391 {
10394 else
10395 {
10405 {
10410 }
10412 {
10415 else
10416 {
10421 }
10422 }
10423 else
10424 {
10425 /* FIXME: We could make this work by pushing a register
10426 around the addition and comparison. */
10429 }
10430 }
10431 }
10433 /* A SYMBOL_REF for the function which allocates new stackspace for
10434 -fsplit-stack. */
10438 /* Handle -fsplit-stack. These are the first instructions in the
10439 function, even before the regular prologue. */
10441 void
10443 {
10445 HOST_WIDE_INT allocate;
10457 /* This is the label we will branch to if we have enough stack
10458 space. We expect the basic block reordering pass to reverse this
10459 branch if optimizing, so that we branch in the unlikely case. */
10462 /* We need to compare the stack pointer minus the frame size with
10463 the stack boundary in the TCB. The stack boundary always gives
10464 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
10465 can compare directly. Otherwise we need to do an addition. */
10468 UNSPEC_STACK_CHECK);
10473 else
10474 {
10476 rtx offset;
10478 /* We need a scratch register to hold the stack pointer minus
10479 the required frame size. Since this is the very start of the
10480 function, the scratch register can be any caller-saved
10481 register which is not used for parameters. */
10487 else
10488 {
10490 {
10491 /* We don't use gen_adddi3 in this case because it will
10492 want to split to lea, but when not optimizing the
10493 insn will not be split after this point. */
10496 }
10497 else
10498 {
10501 stack_pointer_rtx));
10502 }
10503 }
10505 }
10511 /* Mark the jump as very likely to be taken. */
10515 /* Get more stack space. We pass in the desired stack space and the
10516 size of the arguments to copy to the new stack. In 32-bit mode
10517 we push the parameters; __morestack will return on a new stack
10518 anyhow. In 64-bit mode we pass the parameters in r10 and
10519 r11. */
10524 {
10527 }
10528 else
10529 {
10530 rtx reg;
10534 /* If this function uses a static chain, it will be in %r10.
10535 Preserve it across the call to __morestack. */
10537 {
10538 rtx rax;
10543 }
10550 }
10558 /* In order to make call/return prediction work right, we now need
10559 to execute a return instruction. See
10560 libgcc/config/i386/morestack.S for the details on how this works.
10562 In order to support backtracing, we need to set the CFA around
10563 the call, so that the unwinder knows how to correctly pick up the
10564 return address. We set the CFA around the call because the
10565 unwinder looks up to the point of the call but not after the
10566 call. */
10572 /* For flow purposes gcc must not see this as a return
10573 instruction--we need control flow to continue at the subsequent
10574 label. Therefore, we use an unspec. */
10577 else
10578 {
10582 }
10584 /* If we are in 64-bit mode and this function uses a static chain,
10585 we saved %r10 in %rax before calling _morestack. */
10590 /* If this function calls va_start, we need to store a pointer to
10591 the arguments on the old stack, because they may not have been
10592 all copied to the new stack. At this point the old stack can be
10593 found at the frame pointer value used by __morestack, because
10594 __morestack has set that up before calling back to us. Here we
10595 store that pointer in a scratch register, and in
10596 ix86_expand_prologue we store the scratch register in a stack
10597 slot. */
10599 {
10601 rtx frame_reg;
10607 /* fp -> old fp value
10608 return address within this function
10609 return address of caller of this function
10610 stack arguments
10611 So we add three words to get to the stack arguments.
10612 */
10622 }
10627 /* If this function calls va_start, we now have to set the scratch
10628 register for the case where we do not call __morestack. In this
10629 case we need to set it based on the stack pointer. */
10631 {
10638 }
10639 }
10641 /* We may have to tell the dataflow pass that the split stack prologue
10642 is initializing a scratch register. */
10644 static void
10646 {
10648 {
10651 }
10652 }
10653 \f
10654 /* Extract the parts of an RTL expression that is a valid memory address
10655 for an instruction. Return 0 if the structure of the address is
10656 grossly off. Return -1 if the address contains ASHIFT, so it is not
10657 strictly valid, but still used for computing length of lea instruction. */
10659 int
10661 {
10666 rtx tmp;
10673 {
10678 do
10679 {
10684 }
10691 {
10694 {
10717 && TARGET_TLS_DIRECT_SEG_REFS
10720 else
10730 else
10745 }
10746 }
10747 }
10749 {
10752 }
10754 {
10755 /* We're called for lea too, which implements ashift on occasion. */
10765 }
10766 else
10769 /* Extract the integral value of scale. */
10771 {
10775 }
10780 /* Avoid useless 0 displacement. */
10784 /* Allow arg pointer and stack pointer as index if there is not scaling. */
10789 {
10790 rtx tmp;
10793 }
10795 /* Special case: %ebp cannot be encoded as a base without a displacement.
10796 Similarly %r13. */
10798 && base_reg
10807 /* Special case: on K6, [%esi] makes the instruction vector decoded.
10808 Avoid this by transforming to [%esi+0].
10809 Reload calls address legitimization without cfun defined, so we need
10810 to test cfun for being non-NULL. */
10816 /* Special case: encode reg+reg instead of reg*2. */
10820 /* Special case: scaling cannot be encoded without base or displacement. */
10831 }
10832 \f
10833 /* Return cost of the memory address x.
10834 For i386, it is better to use a complex address than let gcc copy
10835 the address into a reg and make a new pseudo. But not if the address
10836 requires to two regs - that would mean more pseudos with longer
10837 lifetimes. */
10838 static int
10840 {
10852 /* Attempt to minimize number of registers in the address. */
10858 cost++;
10865 cost++;
10867 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
10868 since it's predecode logic can't detect the length of instructions
10869 and it degenerates to vector decoded. Increase cost of such
10870 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
10871 to split such addresses or even refuse such addresses at all.
10873 Following addressing modes are affected:
10874 [base+scale*index]
10875 [scale*index+disp]
10876 [base+index]
10878 The first and last case may be avoidable by explicitly coding the zero in
10879 memory address, but I don't have AMD-K6 machine handy to check this
10880 theory. */
10889 }
10890 \f
10891 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
10892 this is used for to form addresses to local data when -fPIC is in
10893 use. */
10895 static bool
10897 {
10900 }
10902 /* Determine if a given RTX is a valid constant. We already know this
10903 satisfies CONSTANT_P. */
10905 bool
10907 {
10909 {
10914 {
10918 }
10923 /* Only some unspecs are valid as "constants". */
10926 {
10942 }
10944 /* We must have drilled down to a symbol. */
10949 /* FALLTHRU */
10952 /* TLS symbols are never valid. */
10956 /* DLLIMPORT symbols are never valid. */
10975 }
10977 /* Otherwise we handle everything else in the move patterns. */
10979 }
10981 /* Determine if it's legal to put X into the constant pool. This
10982 is not possible for the address of thread-local symbols, which
10983 is checked above. */
10985 static bool
10987 {
10988 /* We can always put integral constants and vectors in memory. */
10990 {
10998 }
11000 }
11003 /* Nonzero if the constant value X is a legitimate general operand
11004 when generating PIC code. It is given that flag_pic is on and
11005 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11007 bool
11009 {
11010 rtx inner;
11013 {
11020 /* Only some unspecs are valid as "constants". */
11023 {
11036 }
11037 /* FALLTHRU */
11045 }
11046 }
11048 /* Determine if a given CONST RTX is a valid memory displacement
11049 in PIC mode. */
11051 bool
11053 {
11056 /* In 64bit mode we can allow direct addresses of symbols and labels
11057 when they are not dynamic symbols. */
11059 {
11063 {
11080 /* FALLTHRU */
11083 /* TLS references should always be enclosed in UNSPEC. */
11093 }
11094 }
11100 {
11101 /* We are unsafe to allow PLUS expressions. This limit allowed distance
11102 of GOT tables. We should not need these anyway. */
11113 }
11117 {
11122 }
11131 {
11135 /* We need to check for both symbols and labels because VxWorks loads
11136 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
11137 details. */
11141 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
11142 While ABI specify also 32bit relocation but we don't produce it in
11143 small PIC model at all. */
11165 }
11168 }
11170 /* Recognizes RTL expressions that are valid memory addresses for an
11171 instruction. The MODE argument is the machine mode for the MEM
11172 expression that wants to use this address.
11174 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
11175 convert common non-canonical forms to canonical form so that they will
11176 be recognized. */
11178 static bool
11181 {
11184 HOST_WIDE_INT scale;
11187 /* Decomposition failed. */
11195 /* Validate base register.
11197 Don't allow SUBREG's that span more than a word here. It can lead to spill
11198 failures when the base is one word out of a two word structure, which is
11199 represented internally as a DImode int. */
11202 {
11203 rtx reg;
11212 else
11213 /* Base is not a register. */
11217 /* Base is not in Pmode. */
11222 /* Base is not valid. */
11224 }
11226 /* Validate index register.
11228 Don't allow SUBREG's that span more than a word here -- same as above. */
11231 {
11232 rtx reg;
11241 else
11242 /* Index is not a register. */
11246 /* Index is not in Pmode. */
11251 /* Index is not valid. */
11253 }
11255 /* Validate scale factor. */
11257 {
11259 /* Scale without index. */
11263 /* Scale is not a valid multiplier. */
11265 }
11267 /* Validate displacement. */
11269 {
11274 {
11275 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
11276 used. While ABI specify also 32bit relocations, we don't produce
11277 them at all and use IP relative instead. */
11284 /* 64bit address unspec. */
11303 /* Invalid address unspec. */
11305 }
11308 && (flag_pic
11309 || (TARGET_MACHO
11310 #if TARGET_MACHO
11311 && MACHOPIC_INDIRECT
11313 #endif
11314 )))
11315 {
11317 is_legitimate_pic:
11319 {
11320 /* foo@dtpoff(%rX) is ok. */
11327 /* Non-constant pic memory reference. */
11329 }
11331 /* Displacement is an invalid pic construct. */
11334 /* This code used to verify that a symbolic pic displacement
11335 includes the pic_offset_table_rtx register.
11337 While this is good idea, unfortunately these constructs may
11338 be created by "adds using lea" optimization for incorrect
11339 code like:
11341 int a;
11342 int foo(int i)
11343 {
11344 return *(&a+i);
11345 }
11347 This code is nonsensical, but results in addressing
11348 GOT table with pic_offset_table_rtx base. We can't
11349 just refuse it easily, since it gets matched by
11350 "addsi3" pattern, that later gets split to lea in the
11351 case output register differs from input. While this
11352 can be handled by separate addsi pattern for this case
11353 that never results in lea, this seems to be easier and
11354 correct fix for crash to disable this test. */
11355 }
11362 /* Displacement is not constant. */
11366 /* Displacement is out of range. */
11368 }
11370 /* Everything looks valid. */
11372 }
11374 /* Determine if a given RTX is a valid constant address. */
11376 bool
11378 {
11380 }
11381 \f
11382 /* Return a unique alias set for the GOT. */
11384 static alias_set_type
11386 {
11391 }
11393 /* Return a legitimate reference for ORIG (an address) using the
11394 register REG. If REG is 0, a new pseudo is generated.
11396 There are two types of references that must be handled:
11398 1. Global data references must load the address from the GOT, via
11399 the PIC reg. An insn is emitted to do this load, and the reg is
11400 returned.
11402 2. Static data references, constant pool addresses, and code labels
11403 compute the address as an offset from the GOT, whose base is in
11404 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
11405 differentiate them from global data objects. The returned
11406 address is the PIC reg + an unspec constant.
11408 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
11409 reg also appears in the address. */
11411 static rtx
11413 {
11416 rtx base;
11418 #if TARGET_MACHO
11420 {
11423 /* Use the generic Mach-O PIC machinery. */
11425 }
11426 #endif
11433 {
11434 rtx tmpreg;
11435 /* This symbol may be referenced via a displacement from the PIC
11436 base address (@GOTOFF). */
11443 {
11445 UNSPEC_GOTOFF);
11447 }
11448 else
11453 else
11458 {
11462 }
11464 }
11466 {
11467 /* This symbol may be referenced via a displacement from the PIC
11468 base address (@GOTOFF). */
11475 {
11477 UNSPEC_GOTOFF);
11479 }
11480 else
11486 {
11489 }
11490 }
11492 /* We can't use @GOTOFF for text labels on VxWorks;
11493 see gotoff_operand. */
11495 {
11497 {
11503 {
11506 }
11507 }
11510 {
11518 /* Use directly gen_movsi, otherwise the address is loaded
11519 into register for CSE. We don't want to CSE this addresses,
11520 instead we CSE addresses from the GOT table, so skip this. */
11523 }
11524 else
11525 {
11526 /* This symbol must be referenced via a load from the
11527 Global Offset Table (@GOT). */
11543 }
11544 }
11545 else
11546 {
11549 {
11551 {
11554 }
11555 else
11557 }
11559 {
11562 /* We must match stuff we generate before. Assume the only
11563 unspecs that can get here are ours. Not that we could do
11564 anything with them anyway.... */
11570 }
11572 {
11575 /* Check first to see if this is a constant offset from a @GOTOFF
11576 symbol reference. */
11579 {
11581 {
11585 UNSPEC_GOTOFF);
11591 {
11594 }
11595 }
11596 else
11597 {
11600 {
11604 }
11605 }
11606 }
11607 else
11608 {
11615 else
11616 {
11618 {
11621 }
11623 }
11624 }
11625 }
11626 }
11628 }
11629 \f
11630 /* Load the thread pointer. If TO_REG is true, force it into a register. */
11632 static rtx
11634 {
11646 }
11648 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
11649 false if we expect this to be used for a memory address and true if
11650 we expect to load the address into a register. */
11652 static rtx
11654 {
11659 {
11665 {
11675 }
11678 else
11682 {
11686 }
11694 {
11706 }
11709 else
11713 {
11718 }
11726 {
11730 }
11736 {
11739 }
11741 {
11746 }
11748 {
11752 }
11753 else
11754 {
11757 }
11767 {
11771 }
11772 else
11773 {
11777 }
11787 {
11790 }
11791 else
11792 {
11796 }
11801 }
11804 }
11806 /* Create or return the unique __imp_DECL dllimport symbol corresponding
11807 to symbol DECL. */
11810 htab_t dllimport_map;
11812 static tree
11814 {
11821 tree to;
11822 rtx rtl;
11866 }
11868 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
11869 true if we require the result be a register. */
11871 static rtx
11873 {
11874 tree imp_decl;
11875 rtx x;
11884 }
11886 /* Try machine-dependent ways of modifying an illegitimate address
11887 to be legitimate. If we find one, return the new, valid address.
11888 This macro is used in only one place: `memory_address' in explow.c.
11890 OLDX is the address as it was before break_out_memory_refs was called.
11891 In some cases it is useful to look at this to decide what needs to be done.
11893 It is always safe for this macro to do nothing. It exists to recognize
11894 opportunities to optimize the output.
11896 For the 80386, we handle X+REG by loading X into a register R and
11897 using R+REG. R will go in a general reg and indexing will be used.
11898 However, if REG is a broken-out memory address or multiplication,
11899 nothing needs to be done because REG can certainly go in a general reg.
11901 When -fpic is used, special handling is needed for symbolic references.
11902 See comments by legitimize_pic_address in i386.c for details. */
11904 static rtx
11907 {
11918 {
11922 }
11925 {
11932 {
11935 }
11936 }
11941 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
11945 {
11950 }
11953 {
11954 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
11959 {
11965 }
11970 {
11976 }
11978 /* Put multiply first if it isn't already. */
11980 {
11985 }
11987 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
11988 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
11989 created by virtual register instantiation, register elimination, and
11990 similar optimizations. */
11992 {
11998 }
12000 /* Canonicalize
12001 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
12002 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
12007 {
12008 rtx constant;
12012 {
12015 }
12017 {
12020 }
12021 else
12025 {
12031 }
12032 }
12038 {
12041 }
12044 {
12047 }
12055 {
12058 }
12064 {
12072 }
12075 {
12083 }
12084 }
12087 }
12088 \f
12089 /* Print an integer constant expression in assembler syntax. Addition
12090 and subtraction are the only arithmetic that may appear in these
12091 expressions. FILE is the stdio stream to write to, X is the rtx, and
12092 CODE is the operand print code from the output string. */
12094 static void
12096 {
12100 {
12109 else
12110 {
12113 /* Mark the decl as referenced so that cgraph will
12114 output the function. */
12118 #if TARGET_MACHO
12122 #endif
12124 }
12132 /* FALLTHRU */
12143 /* This used to output parentheses around the expression,
12144 but that does not work on the 386 (either ATT or BSD assembler). */
12150 {
12151 /* We can use %d if the number is <32 bits and positive. */
12156 else
12158 }
12159 else
12160 /* We can't handle floating point constants;
12161 TARGET_PRINT_OPERAND must handle them. */
12166 /* Some assemblers need integer constants to appear first. */
12168 {
12172 }
12173 else
12174 {
12179 }
12194 {
12198 }
12203 {
12218 /* FIXME: This might be @TPOFF in Sun ld too. */
12227 else
12237 else
12243 #if TARGET_MACHO
12248 #endif
12252 }
12257 }
12258 }
12260 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12261 We need to emit DTP-relative relocations. */
12263 static void ATTRIBUTE_UNUSED
12265 {
12270 {
12278 }
12279 }
12281 /* Return true if X is a representation of the PIC register. This copes
12282 with calls from ix86_find_base_term, where the register might have
12283 been replaced by a cselib value. */
12285 static bool
12287 {
12291 else
12293 }
12295 /* In the name of slightly smaller debug output, and to cater to
12296 general assembler lossage, recognize PIC+GOTOFF and turn it back
12297 into a direct symbol reference.
12299 On Darwin, this is necessary to avoid a crash, because Darwin
12300 has a different PIC label for each routine but the DWARF debugging
12301 information is not associated with any particular routine, so it's
12302 necessary to remove references to the PIC label from RTL stored by
12303 the DWARF output code. */
12305 static rtx
12307 {
12309 /* addend is NULL or some rtx if x is something+GOTOFF where
12310 something doesn't include the PIC register. */
12312 /* reg_addend is NULL or a multiple of some register. */
12314 /* const_addend is NULL or a const_int. */
12316 /* This is the result, or NULL. */
12325 {
12335 }
12342 /* %ebx + GOT/GOTOFF */
12343 ;
12345 {
12346 /* %ebx + %reg * scale + GOT/GOTOFF */
12352 else
12353 {
12356 }
12357 }
12358 else
12364 {
12367 }
12386 {
12387 /* If the rest of original X doesn't involve the PIC register, add
12388 addend and subtract pic_offset_table_rtx. This can happen e.g.
12389 for code like:
12390 leal (%ebx, %ecx, 4), %ecx
12391 ...
12392 movl foo@GOTOFF(%ecx), %edx
12393 in which case we return (%ecx - %ebx) + foo. */
12396 pic_offset_table_rtx),
12397 result);
12398 else
12400 }
12404 }
12406 /* If X is a machine specific address (i.e. a symbol or label being
12407 referenced as a displacement from the GOT implemented using an
12408 UNSPEC), then return the base term. Otherwise return X. */
12410 rtx
12412 {
12413 rtx term;
12416 {
12429 }
12432 }
12433 \f
12434 static void
12437 {
12441 {
12444 }
12449 {
12452 {
12471 }
12475 {
12494 }
12501 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
12502 Those same assemblers have the same but opposite lossage on cmov. */
12507 else
12512 {
12525 }
12533 {
12546 }
12549 /* ??? As above. */
12558 /* ??? As above. */
12563 else
12574 }
12576 }
12578 /* Print the name of register X to FILE based on its machine mode and number.
12579 If CODE is 'w', pretend the mode is HImode.
12580 If CODE is 'b', pretend the mode is QImode.
12581 If CODE is 'k', pretend the mode is SImode.
12582 If CODE is 'q', pretend the mode is DImode.
12583 If CODE is 'x', pretend the mode is V4SFmode.
12584 If CODE is 't', pretend the mode is V8SFmode.
12585 If CODE is 'h', pretend the reg is the 'high' byte register.
12586 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
12587 If CODE is 'd', duplicate the operand for AVX instruction.
12588 */
12590 void
12592 {
12607 {
12611 }
12629 else
12632 /* Irritatingly, AMD extended registers use different naming convention
12633 from the normal registers. */
12635 {
12638 {
12657 }
12659 }
12663 {
12666 {
12669 }
12670 /* FALLTHRU */
12676 /* FALLTHRU */
12679 normal:
12694 {
12699 }
12703 }
12707 {
12710 else
12712 }
12713 }
12715 /* Locate some local-dynamic symbol still in use by this function
12716 so that we can print its name in some tls_local_dynamic_base
12717 pattern. */
12719 static int
12721 {
12726 {
12729 }
12732 }
12736 {
12737 rtx insn;
12748 }
12750 /* Meaning of CODE:
12751 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
12752 C -- print opcode suffix for set/cmov insn.
12753 c -- like C, but print reversed condition
12754 F,f -- likewise, but for floating-point.
12755 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
12756 otherwise nothing
12757 R -- print the prefix for register names.
12758 z -- print the opcode suffix for the size of the current operand.
12759 Z -- likewise, with special suffixes for x87 instructions.
12760 * -- print a star (in certain assembler syntax)
12761 A -- print an absolute memory reference.
12762 w -- print the operand as if it's a "word" (HImode) even if it isn't.
12763 s -- print a shift double count, followed by the assemblers argument
12764 delimiter.
12765 b -- print the QImode name of the register for the indicated operand.
12766 %b0 would print %al if operands[0] is reg 0.
12767 w -- likewise, print the HImode name of the register.
12768 k -- likewise, print the SImode name of the register.
12769 q -- likewise, print the DImode name of the register.
12770 x -- likewise, print the V4SFmode name of the register.
12771 t -- likewise, print the V8SFmode name of the register.
12772 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
12773 y -- print "st(0)" instead of "st" as a register.
12774 d -- print duplicated register operand for AVX instruction.
12775 D -- print condition for SSE cmp instruction.
12776 P -- if PIC, print an @PLT suffix.
12777 X -- don't print any sort of PIC '@' suffix for a symbol.
12778 & -- print some in-use local-dynamic symbol name.
12779 H -- print a memory address offset by 8; used for sse high-parts
12780 Y -- print condition for XOP pcom* instruction.
12781 + -- print a branch hint as 'cs' or 'ds' prefix
12782 ; -- print a semicolon (after prefixes due to bug in older gas).
12783 @ -- print a segment register of thread base pointer load
12784 */
12786 void
12788 {
12790 {
12792 {
12799 {
12804 else
12807 }
12811 {
12817 /* Intel syntax. For absolute addresses, registers should not
12818 be surrounded by braces. */
12820 {
12825 }
12830 }
12868 {
12869 /* Opcodes don't get size suffixes if using Intel opcodes. */
12874 {
12892 output_operand_lossage
12895 }
12896 }
12899 warning
12901 /* FALLTHRU */
12904 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
12909 {
12911 {
12913 #ifdef HAVE_AS_IX86_FILDS
12915 #endif
12923 #ifdef HAVE_AS_IX86_FILDQ
12925 #else
12927 #endif
12932 }
12933 }
12935 {
12936 /* 387 opcodes don't get size suffixes
12937 if the operands are registers. */
12942 {
12958 }
12959 }
12960 else
12961 {
12962 output_operand_lossage
12965 }
12967 output_operand_lossage
12986 {
12989 }
12993 /* Little bit of braindamage here. The SSE compare instructions
12994 does use completely different names for the comparisons that the
12995 fp conditional moves. */
12997 {
12999 {
13046 }
13047 }
13048 else
13049 {
13051 {
13086 }
13087 }
13090 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13092 {
13094 {
13101 }
13103 }
13104 #endif
13108 {
13110 "condition code, invalid operand code "
13113 }
13118 {
13120 "condition code, invalid operand code "
13123 }
13124 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13127 #endif
13131 /* Like above, but reverse condition */
13133 /* Check to see if argument to %c is really a constant
13134 and not a condition code which needs to be reversed. */
13136 {
13138 "condition code, invalid operand "
13141 }
13146 {
13148 "condition code, invalid operand "
13151 }
13152 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13155 #endif
13160 /* It doesn't actually matter what mode we use here, as we're
13161 only going to use this for printing. */
13166 {
13167 rtx x;
13175 {
13180 {
13184 /* Emit hints only in the case default branch prediction
13185 heuristics would fail. */
13187 {
13188 /* We use 3e (DS) prefix for taken branches and
13189 2e (CS) prefix for not taken branches. */
13192 else
13194 }
13195 }
13196 }
13198 }
13202 {
13253 }
13257 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
13259 #endif
13266 /* The kernel uses a different segment register for performance
13267 reasons; a system call would not have to trash the userspace
13268 segment register, which would be expensive. */
13271 else
13277 }
13278 }
13284 {
13285 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
13288 {
13291 {
13300 else
13306 }
13308 /* Check for explicit size override (codes 'b', 'w' and 'k') */
13318 }
13321 /* Avoid (%rip) for call operands. */
13327 else
13329 }
13332 {
13333 REAL_VALUE_TYPE r;
13341 /* Sign extend 32bit SFmode immediate to 8 bytes. */
13344 else
13346 }
13348 /* These float cases don't actually occur as immediate operands. */
13350 {
13355 }
13359 {
13364 }
13366 else
13367 {
13368 /* We have patterns that allow zero sets of memory, for instance.
13369 In 64-bit mode, we should probably support all 8-byte vectors,
13370 since we can in fact encode that into an immediate. */
13372 {
13375 }
13378 {
13380 {
13383 }
13386 {
13389 else
13391 }
13392 }
13397 else
13399 }
13400 }
13402 static bool
13404 {
13407 }
13408 \f
13409 /* Print a memory operand whose address is ADDR. */
13411 static void
13413 {
13427 {
13438 }
13440 /* Use one byte shorter RIP relative addressing for 64bit mode. */
13442 {
13454 }
13456 {
13457 /* Displacement only requires special attention. */
13460 {
13464 }
13467 else
13469 }
13470 else
13471 {
13473 {
13475 {
13480 else
13482 }
13488 {
13493 }
13495 }
13496 else
13497 {
13501 {
13502 /* Pull out the offset of a symbol; print any symbol itself. */
13506 {
13510 }
13518 else
13520 }
13524 {
13527 {
13531 }
13532 }
13535 else
13539 {
13544 }
13546 }
13547 }
13548 }
13550 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
13552 static bool
13554 {
13555 rtx op;
13562 {
13565 /* FIXME: This might be @TPOFF in Sun ld. */
13576 else
13588 else
13595 #if TARGET_MACHO
13601 #endif
13604 {
13609 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
13611 #else
13613 #endif
13616 }
13621 }
13624 }
13625 \f
13626 /* Split one or more DImode RTL references into pairs of SImode
13627 references. The RTL can be REG, offsettable MEM, integer constant, or
13628 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
13629 split and "num" is its length. lo_half and hi_half are output arrays
13630 that parallel "operands". */
13632 void
13634 {
13636 {
13639 /* simplify_subreg refuse to split volatile memory addresses,
13640 but we still have to handle it. */
13642 {
13645 }
13646 else
13647 {
13654 }
13655 }
13656 }
13657 /* Split one or more TImode RTL references into pairs of DImode
13658 references. The RTL can be REG, offsettable MEM, integer constant, or
13659 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
13660 split and "num" is its length. lo_half and hi_half are output arrays
13661 that parallel "operands". */
13663 void
13665 {
13667 {
13670 /* simplify_subreg refuse to split volatile memory addresses, but we
13671 still have to handle it. */
13673 {
13676 }
13677 else
13678 {
13681 }
13682 }
13683 }
13684 \f
13685 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
13686 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
13687 is the expression of the binary operation. The output may either be
13688 emitted here, or returned to the caller, like all output_* functions.
13690 There is no guarantee that the operands are the same mode, as they
13691 might be within FLOAT or FLOAT_EXTEND expressions. */
13693 #ifndef SYSV386_COMPAT
13694 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
13695 wants to fix the assemblers because that causes incompatibility
13696 with gcc. No-one wants to fix gcc because that causes
13697 incompatibility with assemblers... You can use the option of
13698 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
13699 #define SYSV386_COMPAT 1
13700 #endif
13704 {
13710 #ifdef ENABLE_CHECKING
13711 /* Even if we do not want to check the inputs, this documents input
13712 constraints. Which helps in understanding the following code. */
13722 else
13724 #endif
13727 {
13732 else
13741 else
13750 else
13759 else
13766 }
13769 {
13771 {
13775 else
13777 }
13778 else
13779 {
13783 else
13785 }
13787 }
13791 {
13795 {
13799 }
13801 /* know operands[0] == operands[1]. */
13804 {
13807 }
13810 {
13812 /* How is it that we are storing to a dead operand[2]?
13813 Well, presumably operands[1] is dead too. We can't
13814 store the result to st(0) as st(0) gets popped on this
13815 instruction. Instead store to operands[2] (which I
13816 think has to be st(1)). st(1) will be popped later.
13817 gcc <= 2.8.1 didn't have this check and generated
13818 assembly code that the Unixware assembler rejected. */
13820 else
13823 }
13827 else
13834 {
13837 }
13840 {
13843 }
13846 {
13847 #if SYSV386_COMPAT
13848 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
13849 derived assemblers, confusingly reverse the direction of
13850 the operation for fsub{r} and fdiv{r} when the
13851 destination register is not st(0). The Intel assembler
13852 doesn't have this brain damage. Read !SYSV386_COMPAT to
13853 figure out what the hardware really does. */
13856 else
13858 #else
13860 /* As above for fmul/fadd, we can't store to st(0). */
13862 else
13864 #endif
13866 }
13869 {
13870 #if SYSV386_COMPAT
13873 else
13875 #else
13878 else
13880 #endif
13882 }
13885 {
13888 else
13891 }
13893 {
13894 #if SYSV386_COMPAT
13896 #else
13898 #endif
13899 }
13900 else
13901 {
13902 #if SYSV386_COMPAT
13904 #else
13906 #endif
13907 }
13912 }
13916 }
13918 /* Return needed mode for entity in optimize_mode_switching pass. */
13920 int
13922 {
13925 /* The mode UNINITIALIZED is used to store control word after a
13926 function call or ASM pattern. The mode ANY specify that function
13927 has no requirements on the control word and make no changes in the
13928 bits we are interested in. */
13942 {
13965 }
13968 }
13970 /* Output code to initialize control word copies used by trunc?f?i and
13971 rounding patterns. CURRENT_MODE is set to current control word,
13972 while NEW_MODE is set to new control word. */
13974 void
13976 {
13978 rtx new_mode;
13989 {
13991 {
13993 /* round toward zero (truncate) */
13999 /* round down toward -oo */
14006 /* round up toward +oo */
14013 /* mask precision exception for nearbyint() */
14020 }
14021 }
14022 else
14023 {
14025 {
14027 /* round toward zero (truncate) */
14033 /* round down toward -oo */
14039 /* round up toward +oo */
14045 /* mask precision exception for nearbyint() */
14052 }
14053 }
14059 }
14061 /* Output code for INSN to convert a float to a signed int. OPERANDS
14062 are the insn operands. The output may be [HSD]Imode and the input
14063 operand may be [SDX]Fmode. */
14067 {
14072 /* Jump through a hoop or two for DImode, since the hardware has no
14073 non-popping instruction. We used to do this a different way, but
14074 that was somewhat fragile and broke with post-reload splitters. */
14084 else
14085 {
14090 else
14094 }
14097 }
14099 /* Output code for x87 ffreep insn. The OPNO argument, which may only
14100 have the values zero or one, indicates the ffreep insn's operand
14101 from the OPERANDS array. */
14105 {
14107 #ifdef HAVE_AS_IX86_FFREEP
14109 #else
14110 {
14120 }
14121 #endif
14124 }
14127 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
14128 should be used. UNORDERED_P is true when fucom should be used. */
14132 {
14138 {
14141 }
14142 else
14143 {
14146 }
14149 {
14158 else
14160 else
14163 else
14165 }
14172 {
14174 {
14177 }
14178 else
14180 }
14183 && stack_top_dies
14186 {
14187 /* If both the top of the 387 stack dies, and the other operand
14188 is also a stack register that dies, then this must be a
14189 `fcompp' float compare */
14192 {
14193 /* There is no double popping fcomi variant. Fortunately,
14194 eflags is immune from the fstp's cc clobbering. */
14197 else
14200 }
14201 else
14202 {
14205 else
14207 }
14208 }
14209 else
14210 {
14211 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
14214 {
14222 NULL,
14223 NULL,
14230 NULL,
14231 NULL,
14232 NULL,
14233 NULL
14234 };
14249 }
14250 }
14252 void
14254 {
14257 #ifdef ASM_QUAD
14260 #else
14262 #endif
14265 }
14267 void
14269 {
14272 #ifdef ASM_QUAD
14275 #else
14277 #endif
14278 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
14284 #if TARGET_MACHO
14286 {
14290 }
14291 #endif
14292 else
14295 }
14296 \f
14297 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
14298 for the target. */
14300 void
14302 {
14303 rtx tmp;
14305 /* We play register width games, which are only valid after reload. */
14308 /* Avoid HImode and its attendant prefix byte. */
14313 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
14315 {
14318 }
14321 }
14323 /* X is an unchanging MEM. If it is a constant pool reference, return
14324 the constant pool rtx, else NULL. */
14326 rtx
14328 {
14335 }
14337 void
14339 {
14347 {
14350 {
14355 }
14359 }
14363 {
14376 {
14382 }
14383 }
14386 {
14388 {
14389 #if TARGET_MACHO
14391 {
14392 rtx temp = ((reload_in_progress
14399 }
14404 #endif
14405 }
14406 else
14407 {
14411 {
14416 }
14417 }
14418 }
14419 else
14420 {
14431 /* Force large constants in 64bit compilation into register
14432 to get them CSEed. */
14444 {
14445 /* If we are loading a floating point constant to a register,
14446 force the value to memory now, since we'll get better code
14447 out the back end. */
14451 {
14456 }
14457 }
14458 }
14461 }
14463 void
14465 {
14469 /* Force constants other than zero into memory. We do not know how
14470 the instructions used to build constants modify the upper 64 bits
14471 of the register, once we have that information we may be able
14472 to handle some of them more efficiently. */
14481 /* We need to check memory alignment for SSE mode since attribute
14482 can make operands unaligned. */
14487 {
14490 /* ix86_expand_vector_move_misalign() does not like constants ... */
14496 /* ... nor both arguments in memory. */
14504 }
14506 /* Make operand1 a register if it isn't already. */
14510 {
14513 }
14516 }
14518 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
14519 straight to ix86_expand_vector_move. */
14520 /* Code generation for scalar reg-reg moves of single and double precision data:
14521 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
14522 movaps reg, reg
14523 else
14524 movss reg, reg
14525 if (x86_sse_partial_reg_dependency == true)
14526 movapd reg, reg
14527 else
14528 movsd reg, reg
14530 Code generation for scalar loads of double precision data:
14531 if (x86_sse_split_regs == true)
14532 movlpd mem, reg (gas syntax)
14533 else
14534 movsd mem, reg
14536 Code generation for unaligned packed loads of single precision data
14537 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
14538 if (x86_sse_unaligned_move_optimal)
14539 movups mem, reg
14541 if (x86_sse_partial_reg_dependency == true)
14542 {
14543 xorps reg, reg
14544 movlps mem, reg
14545 movhps mem+8, reg
14546 }
14547 else
14548 {
14549 movlps mem, reg
14550 movhps mem+8, reg
14551 }
14553 Code generation for unaligned packed loads of double precision data
14554 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
14555 if (x86_sse_unaligned_move_optimal)
14556 movupd mem, reg
14558 if (x86_sse_split_regs == true)
14559 {
14560 movlpd mem, reg
14561 movhpd mem+8, reg
14562 }
14563 else
14564 {
14565 movsd mem, reg
14566 movhpd mem+8, reg
14567 }
14568 */
14570 void
14572 {
14579 {
14581 {
14585 {
14587 /* If we're optimizing for size, movups is the smallest. */
14589 {
14594 }
14606 }
14613 {
14622 {
14627 }
14635 }
14640 }
14643 }
14646 {
14647 /* If we're optimizing for size, movups is the smallest. */
14650 {
14655 }
14657 /* ??? If we have typed data, then it would appear that using
14658 movdqu is the only way to get unaligned data loaded with
14659 integer type. */
14661 {
14666 }
14669 {
14670 rtx zero;
14673 {
14678 }
14680 /* When SSE registers are split into halves, we can avoid
14681 writing to the top half twice. */
14683 {
14686 }
14687 else
14688 {
14689 /* ??? Not sure about the best option for the Intel chips.
14690 The following would seem to satisfy; the register is
14691 entirely cleared, breaking the dependency chain. We
14692 then store to the upper half, with a dependency depth
14693 of one. A rumor has it that Intel recommends two movsd
14694 followed by an unpacklpd, but this is unconfirmed. And
14695 given that the dependency depth of the unpacklpd would
14696 still be one, I'm not sure why this would be better. */
14698 }
14704 }
14705 else
14706 {
14708 {
14713 }
14717 else
14726 }
14727 }
14729 {
14730 /* If we're optimizing for size, movups is the smallest. */
14733 {
14738 }
14740 /* ??? Similar to above, only less clear because of quote
14741 typeless stores unquote. */
14744 {
14749 }
14752 {
14754 {
14758 }
14759 else
14760 {
14765 }
14766 }
14767 else
14768 {
14773 {
14776 }
14777 else
14778 {
14783 }
14784 }
14785 }
14786 else
14788 }
14790 /* Expand a push in MODE. This is some mode for which we do not support
14791 proper push instructions, at least from the registers that we expect
14792 the value to live in. */
14794 void
14796 {
14797 rtx tmp;
14807 /* When we push an operand onto stack, it has to be aligned at least
14808 at the function argument boundary. However since we don't have
14809 the argument type, we can't determine the actual argument
14810 boundary. */
14812 }
14814 /* Helper function of ix86_fixup_binary_operands to canonicalize
14815 operand order. Returns true if the operands should be swapped. */
14817 static bool
14819 rtx operands[])
14820 {
14825 /* If the operation is not commutative, we can't do anything. */
14829 /* Highest priority is that src1 should match dst. */
14835 /* Next highest priority is that immediate constants come second. */
14841 /* Lowest priority is that memory references should come second. */
14848 }
14851 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
14852 destination to use for the operation. If different from the true
14853 destination in operands[0], a copy operation will be required. */
14855 rtx
14857 rtx operands[])
14858 {
14863 /* Canonicalize operand order. */
14865 {
14866 rtx temp;
14868 /* It is invalid to swap operands of different modes. */
14874 }
14876 /* Both source operands cannot be in memory. */
14878 {
14879 /* Optimization: Only read from memory once. */
14881 {
14884 }
14885 else
14887 }
14889 /* If the destination is memory, and we do not have matching source
14890 operands, do things in registers. */
14894 /* Source 1 cannot be a constant. */
14898 /* Source 1 cannot be a non-matching memory. */
14905 }
14907 /* Similarly, but assume that the destination has already been
14908 set up properly. */
14910 void
14913 {
14916 }
14918 /* Attempt to expand a binary operator. Make the expansion closer to the
14919 actual machine, then just general_operand, which will allow 3 separate
14920 memory references (one output, two input) in a single insn. */
14922 void
14924 rtx operands[])
14925 {
14932 /* Emit the instruction. */
14936 {
14937 /* Reload doesn't know about the flags register, and doesn't know that
14938 it doesn't want to clobber it. We can only do this with PLUS. */
14941 }
14942 else
14943 {
14946 }
14948 /* Fix up the destination if needed. */
14951 }
14953 /* Return TRUE or FALSE depending on whether the binary operator meets the
14954 appropriate constraints. */
14956 bool
14959 {
14964 /* Both source operands cannot be in memory. */
14968 /* Canonicalize operand order for commutative operators. */
14970 {
14974 }
14976 /* If the destination is memory, we must have a matching source operand. */
14980 /* Source 1 cannot be a constant. */
14984 /* Source 1 cannot be a non-matching memory. */
14989 }
14991 /* Attempt to expand a unary operator. Make the expansion closer to the
14992 actual machine, then just general_operand, which will allow 2 separate
14993 memory references (one output, one input) in a single insn. */
14995 void
14997 rtx operands[])
14998 {
15005 /* If the destination is memory, and we do not have matching source
15006 operands, do things in registers. */
15009 {
15012 else
15014 }
15016 /* When source operand is memory, destination must match. */
15020 /* Emit the instruction. */
15024 {
15025 /* Reload doesn't know about the flags register, and doesn't know that
15026 it doesn't want to clobber it. */
15029 }
15030 else
15031 {
15034 }
15036 /* Fix up the destination if needed. */
15039 }
15041 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
15042 divisor are within the the range [0-255]. */
15044 void
15047 {
15056 {
15069 }
15076 /* Use 8bit unsigned divimod if dividend and divisor are within the
15077 the range [0-255]. */
15086 pc_rtx);
15091 /* Generate original signed/unsigned divimod. */
15096 /* Branch to the end. */
15100 /* Generate 8bit unsigned divide. */
15102 /* Don't use operands[0] for result of 8bit divide since not all
15103 registers support QImode ZERO_EXTRACT. */
15110 {
15113 }
15114 else
15115 {
15118 }
15120 /* Extract remainder from AH. */
15124 else
15125 {
15126 /* Need a new scratch register since the old one has result
15127 of 8bit divide. */
15131 }
15134 /* Zero extend quotient from AL. */
15140 }
15142 #define LEA_SEARCH_THRESHOLD 12
15144 /* Search backward for non-agu definition of register number REGNO1
15145 or register number REGNO2 in INSN's basic block until
15146 1. Pass LEA_SEARCH_THRESHOLD instructions, or
15147 2. Reach BB boundary, or
15148 3. Reach agu definition.
15149 Returns the distance between the non-agu definition point and INSN.
15150 If no definition point, returns -1. */
15152 static int
15154 rtx insn)
15155 {
15162 {
15165 {
15167 {
15168 distance++;
15174 {
15178 }
15179 }
15183 }
15184 }
15187 {
15188 edge e;
15189 edge_iterator ei;
15194 {
15197 }
15200 {
15205 {
15207 {
15208 distance++;
15214 {
15218 }
15219 }
15221 }
15222 }
15223 }
15227 done:
15228 /* get_attr_type may modify recog data. We want to make sure
15229 that recog data is valid for instruction INSN, on which
15230 distance_non_agu_define is called. INSN is unchanged here. */
15233 }
15235 /* Return the distance between INSN and the next insn that uses
15236 register number REGNO0 in memory address. Return -1 if no such
15237 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
15239 static int
15241 {
15248 {
15251 {
15253 {
15254 distance++;
15260 {
15261 /* Return DISTANCE if OP0 is used in memory
15262 address in NEXT. */
15264 }
15270 {
15271 /* Return -1 if OP0 is set in NEXT. */
15273 }
15274 }
15278 }
15279 }
15282 {
15283 edge e;
15284 edge_iterator ei;
15289 {
15292 }
15295 {
15300 {
15302 {
15303 distance++;
15309 {
15310 /* Return DISTANCE if OP0 is used in memory
15311 address in NEXT. */
15313 }
15319 {
15320 /* Return -1 if OP0 is set in NEXT. */
15322 }
15324 }
15326 }
15327 }
15328 }
15331 }
15333 /* Define this macro to tune LEA priority vs ADD, it take effect when
15334 there is a dilemma of choicing LEA or ADD
15335 Negative value: ADD is more preferred than LEA
15336 Zero: Netrual
15337 Positive value: LEA is more preferred than ADD*/
15338 #define IX86_LEA_PRIORITY 2
15340 /* Return true if it is ok to optimize an ADD operation to LEA
15341 operation to avoid flag register consumation. For most processors,
15342 ADD is faster than LEA. For the processors like ATOM, if the
15343 destination register of LEA holds an actual address which will be
15344 used soon, LEA is better and otherwise ADD is better. */
15346 bool
15348 {
15353 /* If a = b + c, (a!=b && a!=c), must use lea form. */
15359 else
15360 {
15363 /* Return false if REGNO0 isn't used in memory address. */
15372 /* If this insn has both backward non-agu dependence and forward
15373 agu dependence, the one with short distance take effect. */
15378 }
15379 }
15381 /* Return true if destination reg of SET_BODY is shift count of
15382 USE_BODY. */
15384 static bool
15386 {
15387 rtx set_dest;
15388 rtx shift_rtx;
15391 /* Retrieve destination of SET_BODY. */
15393 {
15402 use_body))
15407 }
15409 /* Retrieve shift count of USE_BODY. */
15411 {
15423 }
15431 {
15434 /* Return true if shift count is dest of SET_BODY. */
15438 }
15441 }
15443 /* Return true if destination reg of SET_INSN is shift count of
15444 USE_INSN. */
15446 bool
15448 {
15451 }
15453 /* Return TRUE or FALSE depending on whether the unary operator meets the
15454 appropriate constraints. */
15456 bool
15460 {
15461 /* If one of operands is memory, source and destination must match. */
15467 }
15469 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
15470 are ok, keeping in mind the possible movddup alternative. */
15472 bool
15474 {
15480 }
15482 /* Post-reload splitter for converting an SF or DFmode value in an
15483 SSE register into an unsigned SImode. */
15485 void
15487 {
15498 /* Load up the value into the low element. We must ensure that the other
15499 elements are valid floats -- zero is the easiest such value. */
15501 {
15504 else
15506 }
15507 else
15508 {
15513 else
15515 }
15535 else
15540 }
15542 /* Convert an unsigned DImode value into a DFmode, using only SSE.
15543 Expects the 64-bit DImode to be supplied in a pair of integral
15544 registers. Requires SSE2; will use SSE3 if available. For x86_32,
15545 -mfpmath=sse, !optimize_size only. */
15547 void
15549 {
15553 rtx x;
15559 {
15562 }
15563 else
15564 {
15568 }
15576 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
15579 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
15580 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
15581 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
15582 (0x1.0p84 + double(fp_value_hi_xmm)).
15583 Note these exponents differ by 32. */
15587 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
15588 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
15597 /* Add the upper and lower DFmode values together. */
15600 else
15601 {
15605 }
15608 }
15610 /* Not used, but eases macroization of patterns. */
15611 void
15613 rtx input ATTRIBUTE_UNUSED)
15614 {
15616 }
15618 /* Convert an unsigned SImode value into a DFmode. Only currently used
15619 for SSE, but applicable anywhere. */
15621 void
15623 {
15624 REAL_VALUE_TYPE TWO31r;
15639 }
15641 /* Convert a signed DImode value into a DFmode. Only used for SSE in
15642 32-bit mode; otherwise we have a direct convert instruction. */
15644 void
15646 {
15647 REAL_VALUE_TYPE TWO32r;
15665 }
15667 /* Convert an unsigned SImode value into a SFmode, using only SSE.
15668 For x86_32, -mfpmath=sse, !optimize_size only. */
15669 void
15671 {
15672 REAL_VALUE_TYPE ONE16r;
15691 }
15693 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
15694 then replicate the value for all elements of the vector
15695 register. */
15697 rtx
15699 {
15700 rtvec v;
15702 {
15716 else
15724 else
15730 }
15731 }
15733 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
15734 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
15735 for an SSE register. If VECT is true, then replicate the mask for
15736 all elements of the vector register. If INVERT is true, then create
15737 a mask excluding the sign bit. */
15739 rtx
15741 {
15745 rtx v;
15746 rtx mask;
15748 /* Find the sign bit, sign extended to 2*HWI. */
15750 {
15764 else
15772 {
15775 }
15776 else
15777 {
15778 rtvec vec;
15784 {
15787 }
15788 else
15798 }
15803 }
15808 /* Force this value into the low part of a fp vector constant. */
15817 }
15819 /* Generate code for floating point ABS or NEG. */
15821 void
15823 rtx operands[])
15824 {
15831 {
15834 }
15840 /* NEG and ABS performed with SSE use bitwise mask operations.
15841 Create the appropriate mask now. */
15844 else
15851 {
15855 }
15856 else
15857 {
15861 {
15866 }
15867 else
15869 }
15870 }
15872 /* Expand a copysign operation. Special case operand 0 being a constant. */
15874 void
15876 {
15887 {
15894 {
15901 else
15902 {
15906 }
15907 }
15917 else
15921 }
15922 else
15923 {
15933 else
15937 }
15938 }
15940 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
15941 be a constant, and so has already been expanded into a vector constant. */
15943 void
15945 {
15961 {
15964 }
15965 }
15967 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
15968 so we have to do two masks. */
15970 void
15972 {
15987 {
15988 /* Shouldn't happen often (it's useless, obviously), but when it does
15989 we'd generate incorrect code if we continue below. */
15992 }
15995 {
16006 }
16007 else
16008 {
16010 {
16012 }
16014 {
16018 }
16022 {
16025 }
16027 {
16032 }
16034 }
16038 }
16040 /* Return TRUE or FALSE depending on whether the first SET in INSN
16041 has source and destination with matching CC modes, and that the
16042 CC mode is at least as constrained as REQ_MODE. */
16044 bool
16046 {
16047 rtx set;
16058 {
16068 /* FALLTHRU */
16072 /* FALLTHRU */
16076 /* FALLTHRU */
16086 }
16089 }
16091 /* Generate insn patterns to do an integer compare of OPERANDS. */
16093 static rtx
16095 {
16102 /* This is very simple, but making the interface the same as in the
16103 FP case makes the rest of the code easier. */
16107 /* Return the test that should be put into the flags user, i.e.
16108 the bcc, scc, or cmov instruction. */
16110 }
16112 /* Figure out whether to use ordered or unordered fp comparisons.
16113 Return the appropriate mode to use. */
16115 enum machine_mode
16117 {
16118 /* ??? In order to make all comparisons reversible, we do all comparisons
16119 non-trapping when compiling for IEEE. Once gcc is able to distinguish
16120 all forms trapping and nontrapping comparisons, we can make inequality
16121 comparisons trapping again, since it results in better code when using
16122 FCOM based compares. */
16124 }
16126 enum machine_mode
16128 {
16132 {
16135 }
16138 {
16139 /* Only zero flag is needed. */
16143 /* Codes needing carry flag. */
16146 /* Detect overflow checks. They need just the carry flag. */
16150 else
16154 /* Detect overflow checks. They need just the carry flag. */
16158 else
16160 /* Codes possibly doable only with sign flag when
16161 comparing against zero. */
16166 else
16167 /* For other cases Carry flag is not required. */
16169 /* Codes doable only with sign flag when comparing
16170 against zero, but we miss jump instruction for it
16171 so we need to use relational tests against overflow
16172 that thus needs to be zero. */
16177 else
16179 /* strcmp pattern do (use flags) and combine may ask us for proper
16180 mode. */
16185 }
16186 }
16188 /* Return the fixed registers used for condition codes. */
16190 static bool
16192 {
16196 }
16198 /* If two condition code modes are compatible, return a condition code
16199 mode which is compatible with both. Otherwise, return
16200 VOIDmode. */
16202 static enum machine_mode
16204 {
16216 {
16230 {
16244 }
16248 /* These are only compatible with themselves, which we already
16249 checked above. */
16251 }
16252 }
16255 /* Return a comparison we can do and that it is equivalent to
16256 swap_condition (code) apart possibly from orderedness.
16257 But, never change orderedness if TARGET_IEEE_FP, returning
16258 UNKNOWN in that case if necessary. */
16260 static enum rtx_code
16262 {
16264 {
16275 }
16276 }
16278 /* Return cost of comparison CODE using the best strategy for performance.
16279 All following functions do use number of instructions as a cost metrics.
16280 In future this should be tweaked to compute bytes for optimize_size and
16281 take into account performance of various instructions on various CPUs. */
16283 static int
16285 {
16288 /* The cost of code using bit-twiddling on %ah. */
16290 {
16313 }
16316 {
16323 }
16324 }
16326 /* Return strategy to use for floating-point. We assume that fcomi is always
16327 preferrable where available, since that is also true when looking at size
16328 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
16330 enum ix86_fpcmp_strategy
16332 {
16333 /* Do fcomi/sahf based test when profitable. */
16342 }
16344 /* Swap, force into registers, or otherwise massage the two operands
16345 to a fp comparison. The operands are updated in place; the new
16346 comparison code is returned. */
16348 static enum rtx_code
16350 {
16356 /* All of the unordered compare instructions only work on registers.
16357 The same is true of the fcomi compare instructions. The XFmode
16358 compare instructions require registers except when comparing
16359 against zero or when converting operand 1 from fixed point to
16360 floating point. */
16369 {
16372 }
16373 else
16374 {
16375 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
16376 things around if they appear profitable, otherwise force op0
16377 into a register. */
16383 {
16386 {
16387 rtx tmp;
16390 }
16391 }
16397 {
16402 {
16405 }
16406 else
16408 }
16409 }
16411 /* Try to rearrange the comparison to make it cheaper. */
16415 {
16416 rtx tmp;
16421 }
16426 }
16428 /* Convert comparison codes we use to represent FP comparison to integer
16429 code that will result in proper branch. Return UNKNOWN if no such code
16430 is available. */
16432 enum rtx_code
16434 {
16436 {
16459 }
16460 }
16462 /* Generate insn patterns to do a floating point compare of OPERANDS. */
16464 static rtx
16466 {
16473 /* Do fcomi/sahf based test when profitable. */
16475 {
16480 tmp);
16488 tmp);
16497 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
16504 /* In the unordered case, we have to check C2 for NaN's, which
16505 doesn't happen to work out to anything nice combination-wise.
16506 So do some bit twiddling on the value we've got in AH to come
16507 up with an appropriate set of condition codes. */
16511 {
16515 {
16518 }
16519 else
16520 {
16526 }
16531 {
16536 }
16537 else
16538 {
16541 }
16546 {
16549 }
16550 else
16551 {
16555 }
16560 {
16566 }
16567 else
16568 {
16571 }
16576 {
16581 }
16582 else
16583 {
16586 }
16591 {
16596 }
16597 else
16598 {
16601 }
16615 }
16620 }
16622 /* Return the test that should be put into the flags user, i.e.
16623 the bcc, scc, or cmov instruction. */
16626 const0_rtx);
16627 }
16629 static rtx
16631 {
16632 rtx ret;
16638 {
16641 }
16642 else
16646 }
16648 void
16650 {
16651 rtx tmp;
16654 {
16661 simple:
16665 pc_rtx);
16673 /* Expand DImode branch into multiple compare+branch. */
16674 {
16680 {
16683 }
16685 {
16689 }
16690 else
16691 {
16695 }
16697 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
16698 avoid two branches. This costs one extra insn, so disable when
16699 optimizing for size. */
16704 {
16722 }
16724 /* Otherwise, if we are doing less-than or greater-or-equal-than,
16725 op1 is a constant and the low word is zero, then we can just
16726 examine the high word. Similarly for low word -1 and
16727 less-or-equal-than or greater-than. */
16731 {
16734 {
16737 }
16741 {
16744 }
16748 }
16750 /* Otherwise, we need two or three jumps. */
16759 {
16773 }
16775 /*
16776 * a < b =>
16777 * if (hi(a) < hi(b)) goto true;
16778 * if (hi(a) > hi(b)) goto false;
16779 * if (lo(a) < lo(b)) goto true;
16780 * false:
16781 */
16793 }
16798 }
16799 }
16801 /* Split branch based on floating point condition. */
16802 void
16805 {
16806 rtx condition;
16807 rtx i;
16810 {
16815 }
16818 tmp);
16820 /* Remove pushed operand from stack. */
16830 }
16832 void
16834 {
16835 rtx ret;
16842 }
16844 /* Expand comparison setting or clearing carry flag. Return true when
16845 successful and set pop for the operation. */
16846 static bool
16848 {
16852 /* Do not handle DImode compares that go through special path. */
16857 {
16862 /* Shortcut: following common codes never translate
16863 into carry flag compares. */
16868 /* These comparisons require zero flag; swap operands so they won't. */
16871 {
16876 }
16878 /* Try to expand the comparison and verify that we end up with
16879 carry flag based comparison. This fails to be true only when
16880 we decide to expand comparison using arithmetic that is not
16881 too common scenario. */
16890 else
16899 }
16905 {
16910 /* Convert a==0 into (unsigned)a<1. */
16919 /* Convert a>b into b<a or a>=b-1. */
16923 {
16925 /* Bail out on overflow. We still can swap operands but that
16926 would force loading of the constant into register. */
16931 }
16932 else
16933 {
16938 }
16941 /* Convert a>=0 into (unsigned)a<0x80000000. */
16959 }
16960 /* Swapping operands may cause constant to appear as first operand. */
16962 {
16966 }
16970 }
16972 bool
16974 {
16993 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
16994 HImode insns, we'd be swallowed in word prefix ops. */
17000 {
17004 HOST_WIDE_INT diff;
17007 /* Sign bit compares are better done using shifts than we do by using
17008 sbb. */
17011 {
17012 /* Detect overlap between destination and compare sources. */
17016 {
17017 rtx flags;
17026 {
17028 compare_code
17030 }
17032 /* To simplify rest of code, restrict to the GEU case. */
17034 {
17040 }
17041 else
17042 {
17045 reverse_condition_maybe_unordered
17047 else
17050 }
17059 else
17062 }
17063 else
17064 {
17067 else
17068 {
17073 }
17075 }
17078 {
17079 /*
17080 * cmpl op0,op1
17081 * sbbl dest,dest
17082 * [addl dest, ct]
17083 *
17084 * Size 5 - 8.
17085 */
17090 }
17092 {
17093 /*
17094 * cmpl op0,op1
17095 * sbbl dest,dest
17096 * orl $ct, dest
17097 *
17098 * Size 8.
17099 */
17103 }
17105 {
17106 /*
17107 * cmpl op0,op1
17108 * sbbl dest,dest
17109 * notl dest
17110 * [addl dest, cf]
17111 *
17112 * Size 8 - 11.
17113 */
17119 }
17120 else
17121 {
17122 /*
17123 * cmpl op0,op1
17124 * sbbl dest,dest
17125 * [notl dest]
17126 * andl cf - ct, dest
17127 * [addl dest, ct]
17128 *
17129 * Size 8 - 11.
17130 */
17133 {
17137 }
17147 }
17153 }
17156 {
17159 HOST_WIDE_INT tmp;
17164 {
17167 /* We may be reversing unordered compare to normal compare, that
17168 is not valid in general (we may convert non-trapping condition
17169 to trapping one), however on i386 we currently emit all
17170 comparisons unordered. */
17173 }
17174 else
17175 {
17178 }
17179 }
17184 {
17189 {
17194 }
17195 }
17197 /* Optimize dest = (op0 < 0) ? -1 : cf. */
17201 {
17202 /* If lea code below could be used, only optimize
17203 if it results in a 2 insn sequence. */
17209 {
17210 /*
17211 * notl op1 (if necessary)
17212 * sarl $31, op1
17213 * orl cf, op1
17214 */
17216 {
17220 }
17231 }
17232 }
17240 {
17241 /*
17242 * xorl dest,dest
17243 * cmpl op1,op2
17244 * setcc dest
17245 * lea cf(dest*(ct-cf)),dest
17246 *
17247 * Size 14.
17248 *
17249 * This also catches the degenerate setcc-only case.
17250 */
17252 rtx tmp;
17258 /* On x86_64 the lea instruction operates on Pmode, so we need
17259 to get arithmetics done in proper mode to match. */
17262 else
17263 {
17264 rtx out1;
17267 nops++;
17269 {
17271 nops++;
17272 }
17273 }
17275 {
17277 nops++;
17278 }
17280 {
17283 else
17285 }
17290 }
17292 /*
17293 * General case: Jumpful:
17294 * xorl dest,dest cmpl op1, op2
17295 * cmpl op1, op2 movl ct, dest
17296 * setcc dest jcc 1f
17297 * decl dest movl cf, dest
17298 * andl (cf-ct),dest 1:
17299 * addl ct,dest
17300 *
17301 * Size 20. Size 14.
17302 *
17303 * This is reasonably steep, but branch mispredict costs are
17304 * high on modern cpus, so consider failing only if optimizing
17305 * for space.
17306 */
17311 {
17313 {
17320 {
17323 /* We may be reversing unordered compare to normal compare,
17324 that is not valid in general (we may convert non-trapping
17325 condition to trapping one), however on i386 we currently
17326 emit all comparisons unordered. */
17328 }
17329 else
17330 {
17334 }
17335 }
17338 {
17339 /* notl op1 (if needed)
17340 sarl $31, op1
17341 andl (cf-ct), op1
17342 addl ct, op1
17344 For x < 0 (resp. x <= -1) there will be no notl,
17345 so if possible swap the constants to get rid of the
17346 complement.
17347 True/false will be -1/0 while code below (store flag
17348 followed by decrement) is 0/-1, so the constants need
17349 to be exchanged once more. */
17352 {
17355 }
17356 else
17357 {
17361 }
17364 }
17365 else
17366 {
17370 constm1_rtx,
17372 }
17384 }
17385 }
17388 {
17389 /* Try a few things more with specific constants and a variable. */
17391 optab op;
17397 /* If one of the two operands is an interesting constant, load a
17398 constant with the above and mask it in with a logical operation. */
17401 {
17407 else
17409 }
17411 {
17417 else
17419 }
17420 else
17427 /* Recurse to get the constant loaded. */
17431 /* Mask in the interesting variable. */
17433 OPTAB_WIDEN);
17438 }
17440 /*
17441 * For comparison with above,
17442 *
17443 * movl cf,dest
17444 * movl ct,tmp
17445 * cmpl op1,op2
17446 * cmovcc tmp,dest
17447 *
17448 * Size 15.
17449 */
17471 }
17473 /* Swap, force into registers, or otherwise massage the two operands
17474 to an sse comparison with a mask result. Thus we differ a bit from
17475 ix86_prepare_fp_compare_args which expects to produce a flags result.
17477 The DEST operand exists to help determine whether to commute commutative
17478 operators. The POP0/POP1 operands are updated in place. The new
17479 comparison code is returned, or UNKNOWN if not implementable. */
17481 static enum rtx_code
17484 {
17485 rtx tmp;
17488 {
17491 /* We have no LTGT as an operator. We could implement it with
17492 NE & ORDERED, but this requires an extra temporary. It's
17493 not clear that it's worth it. */
17500 /* These are supported directly. */
17507 /* For commutative operators, try to canonicalize the destination
17508 operand to be first in the comparison - this helps reload to
17509 avoid extra moves. */
17512 /* FALLTHRU */
17518 /* These are not supported directly. Swap the comparison operands
17519 to transform into something that is supported. */
17528 }
17531 }
17533 /* Detect conditional moves that exactly match min/max operational
17534 semantics. Note that this is IEEE safe, as long as we don't
17535 interchange the operands.
17537 Returns FALSE if this conditional move doesn't match a MIN/MAX,
17538 and TRUE if the operation is successful and instructions are emitted. */
17540 static bool
17543 {
17546 rtx tmp;
17549 ;
17551 {
17555 }
17556 else
17563 else
17568 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
17569 but MODE may be a vector mode and thus not appropriate. */
17571 {
17573 rtvec v;
17578 }
17579 else
17580 {
17583 }
17587 }
17589 /* Expand an sse vector comparison. Return the register with the result. */
17591 static rtx
17594 {
17596 rtx x;
17611 }
17613 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
17614 operations. This is used for both scalar and vector conditional moves. */
17616 static void
17618 {
17623 {
17627 }
17629 {
17634 }
17636 {
17639 op_true,
17640 op_false));
17642 }
17643 else
17644 {
17651 else
17663 }
17664 }
17666 /* Expand a floating-point conditional move. Return true if successful. */
17668 bool
17670 {
17678 {
17681 /* Since we've no cmove for sse registers, don't force bad register
17682 allocation just to gain access to it. Deny movcc when the
17683 comparison mode doesn't match the move mode. */
17702 }
17704 /* The floating point conditional move instructions don't directly
17705 support conditions resulting from a signed integer comparison. */
17709 {
17714 }
17721 }
17723 /* Expand a floating-point vector conditional move; a vcond operation
17724 rather than a movcc operation. */
17726 bool
17728 {
17730 rtx cmp;
17745 }
17747 /* Expand a signed/unsigned integral vector conditional move. */
17749 bool
17751 {
17760 /* XOP supports all of the comparisons on all vector int types. */
17762 {
17763 /* Canonicalize the comparison to EQ, GT, GTU. */
17765 {
17782 /* FALLTHRU */
17792 }
17794 /* Only SSE4.1/SSE4.2 supports V2DImode. */
17796 {
17798 {
17800 /* SSE4.1 supports EQ. */
17807 /* SSE4.2 supports GT/GTU. */
17814 }
17815 }
17817 /* Unsigned parallel compare is not supported by the hardware.
17818 Play some tricks to turn this into a signed comparison
17819 against 0. */
17821 {
17825 {
17828 {
17832 /* Subtract (-(INT MAX) - 1) from both operands to make
17833 them signed. */
17847 }
17852 /* Perform a parallel unsigned saturating subtraction. */
17865 }
17866 }
17867 }
17875 }
17877 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
17878 true if we should do zero extension, else sign extension. HIGH_P is
17879 true if we want the N/2 high elements, else the low elements. */
17881 void
17883 {
17889 {
17893 else
17899 else
17905 else
17910 }
17916 else
17921 }
17923 /* This function performs the same task as ix86_expand_sse_unpack,
17924 but with SSE4.1 instructions. */
17926 void
17928 {
17934 {
17938 else
17944 else
17950 else
17955 }
17959 {
17960 /* Shift higher 8 bytes to lower 8 bytes. */
17965 }
17966 else
17970 }
17972 /* Expand conditional increment or decrement using adb/sbb instructions.
17973 The default case using setcc followed by the conditional move can be
17974 done by generic code. */
17975 bool
17977 {
17979 rtx flags;
17981 rtx compare_op;
17999 {
18002 }
18005 {
18009 reverse_condition_maybe_unordered
18011 else
18013 }
18017 /* Construct either adc or sbb insn. */
18019 {
18021 {
18036 }
18037 }
18038 else
18039 {
18041 {
18056 }
18057 }
18061 }
18064 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
18065 works for floating pointer parameters and nonoffsetable memories.
18066 For pushes, it returns just stack offsets; the values will be saved
18067 in the right order. Maximally three parts are generated. */
18069 static int
18071 {
18076 else
18082 /* Optimize constant pool reference to immediates. This is used by fp
18083 moves, that force all constants to memory to allow combining. */
18085 {
18089 }
18092 {
18093 /* The only non-offsetable memories we handle are pushes. */
18102 }
18105 {
18107 /* Caution: if we looked through a constant pool memory above,
18108 the operand may actually have a different mode now. That's
18109 ok, since we want to pun this all the way back to an integer. */
18113 }
18116 {
18119 else
18120 {
18124 {
18128 }
18130 {
18135 }
18137 {
18138 REAL_VALUE_TYPE r;
18143 {
18158 }
18161 }
18162 else
18164 }
18165 }
18166 else
18167 {
18171 {
18174 {
18178 }
18180 {
18184 }
18186 {
18187 REAL_VALUE_TYPE r;
18193 /* Do not use shift by 32 to avoid warning on 32bit systems. */
18196 = gen_int_mode
18199 DImode);
18200 else
18207 = gen_int_mode
18210 DImode);
18211 else
18213 }
18214 else
18216 }
18217 }
18220 }
18222 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
18223 Return false when normal moves are needed; true when all required
18224 insns have been emitted. Operands 2-4 contain the input values
18225 int the correct order; operands 5-7 contain the output values. */
18227 void
18229 {
18237 /* The DFmode expanders may ask us to move double.
18238 For 64bit target this is single move. By hiding the fact
18239 here we simplify i386.md splitters. */
18241 {
18242 /* Optimize constant pool reference to immediates. This is used by
18243 fp moves, that force all constants to memory to allow combining. */
18250 {
18253 }
18254 else
18259 }
18261 /* The only non-offsettable memory we handle is push. */
18264 else
18271 /* When emitting push, take care for source operands on the stack. */
18274 {
18277 /* Compensate for the stack decrement by 4. */
18282 /* src_base refers to the stack pointer and is
18283 automatically decreased by emitted push. */
18287 }
18289 /* We need to do copy in the right order in case an address register
18290 of the source overlaps the destination. */
18292 {
18293 rtx tmp;
18296 {
18300 collisions++;
18301 }
18303 /* Collision in the middle part can be handled by reordering. */
18305 {
18308 }
18312 {
18314 {
18317 }
18318 else
18319 {
18322 }
18323 }
18325 /* If there are more collisions, we can't handle it by reordering.
18326 Do an lea to the last part and use only one colliding move. */
18328 {
18329 rtx base;
18335 /* Handle the case when the last part isn't valid for lea.
18336 Happens in 64-bit mode storing the 12-byte XFmode. */
18343 {
18346 }
18347 }
18348 }
18351 {
18353 {
18355 {
18360 }
18362 {
18365 }
18366 }
18367 else
18368 {
18369 /* In 64bit mode we don't have 32bit push available. In case this is
18370 register, it is OK - we will just use larger counterpart. We also
18371 retype memory - these comes from attempt to avoid REX prefix on
18372 moving of second half of TFmode value. */
18374 {
18376 {
18387 }
18391 }
18392 }
18396 }
18398 /* Choose correct order to not overwrite the source before it is copied. */
18408 {
18410 {
18413 }
18414 }
18415 else
18416 {
18418 {
18421 }
18422 }
18424 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
18426 {
18435 }
18441 }
18443 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
18444 left shift by a constant, either using a single shift or
18445 a sequence of add instructions. */
18447 static void
18449 {
18451 {
18453 ? gen_addsi3
18455 }
18458 {
18461 {
18463 ? gen_addsi3
18465 }
18466 }
18467 else
18469 ? gen_ashlsi3
18471 }
18473 void
18475 {
18481 {
18486 {
18492 }
18493 else
18494 {
18498 ? gen_x86_shld
18501 }
18503 }
18508 {
18509 /* Assuming we've chosen a QImode capable registers, then 1 << N
18510 can be done with two 32/64-bit shifts, no branches, no cmoves. */
18512 {
18528 }
18530 /* Otherwise, we can get the same results by manually performing
18531 a bit extract operation on bit 5/6, and then performing the two
18532 shifts. The two methods of getting 0/1 into low/high are exactly
18533 the same size. Avoiding the shift in the bit extract case helps
18534 pentium4 a bit; no one else seems to care much either way. */
18535 else
18536 {
18537 rtx x;
18541 else
18546 ? gen_lshrsi3
18550 ? gen_andsi3
18554 ? gen_xorsi3
18556 }
18559 ? gen_ashlsi3
18562 ? gen_ashlsi3
18565 }
18568 {
18569 /* For -1 << N, we can avoid the shld instruction, because we
18570 know that we're shifting 0...31/63 ones into a -1. */
18574 else
18576 }
18577 else
18578 {
18584 ? gen_x86_shld
18586 }
18589 ? gen_ashlsi3
18593 {
18596 ? gen_x86_shiftsi_adj_1
18598 scratch));
18599 }
18600 else
18602 ? gen_x86_shiftsi_adj_2
18604 }
18606 void
18608 {
18614 {
18619 {
18622 ? gen_ashrsi3
18627 }
18629 {
18633 ? gen_ashrsi3
18638 ? gen_ashrsi3
18641 }
18642 else
18643 {
18647 ? gen_x86_shrd
18650 ? gen_ashrsi3
18652 }
18653 }
18654 else
18655 {
18662 ? gen_x86_shrd
18665 ? gen_ashrsi3
18669 {
18672 ? gen_ashrsi3
18676 ? gen_x86_shiftsi_adj_1
18678 scratch));
18679 }
18680 else
18682 ? gen_x86_shiftsi_adj_3
18684 }
18685 }
18687 void
18689 {
18695 {
18700 {
18706 ? gen_lshrsi3
18709 }
18710 else
18711 {
18715 ? gen_x86_shrd
18718 ? gen_lshrsi3
18720 }
18721 }
18722 else
18723 {
18730 ? gen_x86_shrd
18733 ? gen_lshrsi3
18736 /* Heh. By reversing the arguments, we can reuse this pattern. */
18738 {
18741 ? gen_x86_shiftsi_adj_1
18743 scratch));
18744 }
18745 else
18747 ? gen_x86_shiftsi_adj_2
18749 }
18750 }
18752 /* Predict just emitted jump instruction to be taken with probability PROB. */
18753 static void
18755 {
18759 }
18761 /* Helper function for the string operations below. Dest VARIABLE whether
18762 it is aligned to VALUE bytes. If true, jump to the label. */
18763 static rtx
18765 {
18770 else
18776 else
18779 }
18781 /* Adjust COUNTER by the VALUE. */
18782 static void
18784 {
18787 else
18789 }
18791 /* Zero extend possibly SImode EXP to Pmode register. */
18792 rtx
18794 {
18795 rtx r;
18803 }
18805 /* Divide COUNTREG by SCALE. */
18806 static rtx
18808 {
18809 rtx sc;
18821 }
18823 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
18824 DImode for constant loop counts. */
18826 static enum machine_mode
18828 {
18836 }
18838 /* When SRCPTR is non-NULL, output simple loop to move memory
18839 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
18840 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
18841 equivalent loop to set memory by VALUE (supposed to be in MODE).
18843 The size is rounded down to whole number of chunk size moved at once.
18844 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
18847 static void
18852 {
18857 rtx size;
18858 rtx x_addr;
18859 rtx y_addr;
18868 /* Those two should combine. */
18870 {
18874 }
18884 {
18888 /* When unrolling for chips that reorder memory reads and writes,
18889 we can save registers by using single temporary.
18890 Also using 4 temporaries is overkill in 32bit mode. */
18892 {
18894 {
18896 {
18897 destmem =
18899 srcmem =
18901 }
18903 }
18904 }
18905 else
18906 {
18910 {
18913 {
18914 srcmem =
18916 }
18918 }
18920 {
18922 {
18923 destmem =
18925 }
18927 }
18928 }
18929 }
18930 else
18932 {
18934 destmem =
18937 }
18947 {
18953 else
18955 }
18956 else
18964 {
18969 }
18971 }
18973 /* Output "rep; mov" instruction.
18974 Arguments have same meaning as for previous function */
18975 static void
18978 rtx count,
18980 {
18981 rtx destexp;
18982 rtx srcexp;
18983 rtx countreg;
18985 /* If the size is known, it is shorter to use rep movs. */
18996 {
19003 }
19004 else
19005 {
19008 }
19010 {
19017 }
19018 else
19019 {
19024 }
19027 }
19029 /* Output "rep; stos" instruction.
19030 Arguments have same meaning as for previous function */
19031 static void
19034 rtx orig_value)
19035 {
19036 rtx destexp;
19037 rtx countreg;
19044 {
19048 }
19049 else
19052 {
19057 }
19061 }
19063 static void
19066 {
19070 }
19072 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
19073 static void
19076 {
19079 {
19084 {
19086 {
19089 }
19090 else
19093 }
19095 {
19098 else
19099 {
19102 }
19104 }
19106 {
19109 }
19111 {
19114 }
19116 {
19119 }
19121 }
19123 {
19129 }
19131 /* When there are stringops, we can cheaply increase dest and src pointers.
19132 Otherwise we save code size by maintaining offset (zero is readily
19133 available from preceding rep operation) and using x86 addressing modes.
19134 */
19136 {
19138 {
19145 }
19147 {
19154 }
19156 {
19163 }
19164 }
19165 else
19166 {
19168 rtx tmp;
19171 {
19182 }
19184 {
19197 }
19199 {
19208 }
19209 }
19210 }
19212 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
19213 static void
19216 {
19217 count =
19223 }
19225 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
19226 static void
19228 {
19229 rtx dest;
19232 {
19237 {
19239 {
19244 }
19245 else
19248 }
19250 {
19252 {
19255 }
19256 else
19257 {
19262 }
19264 }
19266 {
19270 }
19272 {
19276 }
19278 {
19282 }
19284 }
19286 {
19289 }
19291 {
19294 {
19298 }
19299 else
19300 {
19306 }
19309 }
19311 {
19314 {
19317 }
19318 else
19319 {
19323 }
19326 }
19328 {
19334 }
19336 {
19342 }
19344 {
19350 }
19351 }
19353 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
19354 DESIRED_ALIGNMENT. */
19355 static void
19359 {
19361 {
19369 }
19371 {
19379 }
19381 {
19389 }
19391 }
19393 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
19394 ALIGN_BYTES is how many bytes need to be copied. */
19395 static rtx
19398 {
19408 {
19413 }
19415 {
19426 }
19428 {
19434 {
19442 }
19445 }
19451 {
19463 }
19470 }
19472 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
19473 DESIRED_ALIGNMENT. */
19474 static void
19477 {
19479 {
19486 }
19488 {
19495 }
19497 {
19504 }
19506 }
19508 /* Set enough from DST to align DST known to by aligned by ALIGN to
19509 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
19510 static rtx
19513 {
19517 {
19522 }
19524 {
19531 }
19533 {
19540 }
19547 }
19549 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
19550 static enum stringop_alg
19553 {
19556 /* Algorithms using the rep prefix want at least edi and ecx;
19557 additionally, memset wants eax and memcpy wants esi. Don't
19558 consider such algorithms if the user has appropriated those
19559 registers for their own purposes. */
19561 || (memset
19564 #define ALG_USABLE_P(alg) (rep_prefix_usable \
19565 || (alg != rep_prefix_1_byte \
19566 && alg != rep_prefix_4_byte \
19567 && alg != rep_prefix_8_byte))
19570 /* Even if the string operation call is cold, we still might spend a lot
19571 of time processing large blocks. */
19576 else
19584 else
19588 /* rep; movq or rep; movl is the smallest variant. */
19590 {
19593 else
19595 }
19596 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
19597 */
19601 {
19605 {
19606 /* We get here if the algorithms that were not libcall-based
19607 were rep-prefix based and we are unable to use rep prefixes
19608 based on global register usage. Break out of the loop and
19609 use the heuristic below. */
19613 {
19618 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
19619 last non-libcall inline algorithm. */
19621 {
19622 /* When the current size is best to be copied by a libcall,
19623 but we are still forced to inline, run the heuristic below
19624 that will pick code for medium sized blocks. */
19628 }
19631 }
19632 }
19634 }
19635 /* When asked to inline the call anyway, try to pick meaningful choice.
19636 We look for maximal size of block that is faster to copy by hand and
19637 take blocks of at most of that size guessing that average size will
19638 be roughly half of the block.
19640 If this turns out to be bad, we might simply specify the preferred
19641 choice in ix86_costs. */
19644 {
19651 {
19658 }
19659 /* If there aren't any usable algorithms, then recursing on
19660 smaller sizes isn't going to find anything. Just return the
19661 simple byte-at-a-time copy loop. */
19663 {
19664 /* Pick something reasonable. */
19668 }
19677 }
19679 #undef ALG_USABLE_P
19680 }
19682 /* Decide on alignment. We know that the operand is already aligned to ALIGN
19683 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
19684 static int
19688 {
19691 {
19702 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
19703 copying whole cacheline at once. */
19706 else
19710 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
19711 copying whole cacheline at once. */
19714 else
19722 }
19731 }
19733 /* Return the smallest power of 2 greater than VAL. */
19734 static int
19736 {
19741 }
19743 /* Expand string move (memcpy) operation. Use i386 string operations when
19744 profitable. expand_setmem contains similar code. The code depends upon
19745 architecture, block size and alignment, but always has the same
19746 overall structure:
19748 1) Prologue guard: Conditional that jumps up to epilogues for small
19749 blocks that can be handled by epilogue alone. This is faster but
19750 also needed for correctness, since prologue assume the block is larger
19751 than the desired alignment.
19753 Optional dynamic check for size and libcall for large
19754 blocks is emitted here too, with -minline-stringops-dynamically.
19756 2) Prologue: copy first few bytes in order to get destination aligned
19757 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
19758 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
19759 We emit either a jump tree on power of two sized blocks, or a byte loop.
19761 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
19762 with specified algorithm.
19764 4) Epilogue: code copying tail of the block that is too small to be
19765 handled by main body (or up to size guarded by prologue guard). */
19767 bool
19770 {
19771 rtx destreg;
19772 rtx srcreg;
19774 rtx tmp;
19787 /* i386 can do misaligned access on reasonably increased cost. */
19791 /* ALIGN is the minimum of destination and source alignment, but we care here
19792 just about destination alignment. */
19801 /* Make sure we don't need to care about overflow later on. */
19805 /* Step 0: Decide on preferred algorithm, desired alignment and
19806 size of chunks to be copied by main loop. */
19822 {
19847 }
19851 /* Step 1: Prologue guard. */
19853 /* Alignment code needs count to be in register. */
19855 {
19858 {
19859 align_bytes
19863 else
19865 }
19868 }
19871 /* Ensure that alignment prologue won't copy past end of block. */
19873 {
19875 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
19876 Make sure it is power of 2. */
19880 {
19882 {
19883 /* If main algorithm works on QImode, no epilogue is needed.
19884 For small sizes just don't align anything. */
19887 else
19889 }
19890 }
19891 else
19892 {
19899 else
19901 }
19902 }
19904 /* Emit code to decide on runtime whether library call or inline should be
19905 used. */
19907 {
19909 {
19911 {
19915 }
19916 }
19917 else
19918 {
19927 }
19928 }
19930 /* Step 2: Alignment prologue. */
19933 {
19935 {
19936 /* Except for the first move in epilogue, we no longer know
19937 constant offset in aliasing info. It don't seems to worth
19938 the pain to maintain it for the first move, so throw away
19939 the info early. */
19943 desired_align);
19944 }
19945 else
19946 {
19947 /* If we know how many bytes need to be stored before dst is
19948 sufficiently aligned, maintain aliasing info accurately. */
19953 }
19959 {
19960 /* It is possible that we copied enough so the main loop will not
19961 execute. */
19971 else
19973 }
19974 }
19976 {
19981 }
19985 /* Step 3: Main loop. */
19988 {
20001 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
20002 registers for 4 temporaries anyway. */
20005 expected_size);
20009 DImode);
20013 SImode);
20017 QImode);
20019 }
20020 /* Adjust properly the offset of src and dest memory for aliasing. */
20022 {
20027 }
20028 else
20029 {
20032 }
20034 /* Step 4: Epilogue to copy the remaining bytes. */
20035 epilogue:
20037 {
20038 /* When the main loop is done, COUNT_EXP might hold original count,
20039 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
20040 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
20041 bytes. Compensate if needed. */
20044 {
20045 tmp =
20048 OPTAB_DIRECT);
20051 }
20054 }
20058 epilogue_size_needed);
20062 }
20064 /* Helper function for memcpy. For QImode value 0xXY produce
20065 0xXYXYXYXY of wide specified by MODE. This is essentially
20066 a * 0x10101010, but we can do slightly better than
20067 synth_mult by unwinding the sequence by hand on CPUs with
20068 slow multiply. */
20069 static rtx
20071 {
20073 rtx tmp;
20080 {
20088 }
20097 nops--;
20102 {
20106 OPTAB_DIRECT);
20107 }
20108 else
20109 {
20115 else
20117 else
20118 {
20121 reg =
20123 }
20133 }
20134 }
20136 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
20137 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
20138 alignment from ALIGN to DESIRED_ALIGN. */
20139 static rtx
20141 {
20142 rtx promoted_val;
20151 else
20155 }
20157 /* Expand string clear operation (bzero). Use i386 string operations when
20158 profitable. See expand_movmem comment for explanation of individual
20159 steps performed. */
20160 bool
20163 {
20164 rtx destreg;
20166 rtx tmp;
20181 /* i386 can do misaligned access on reasonably increased cost. */
20190 /* Make sure we don't need to care about overflow later on. */
20194 /* Step 0: Decide on preferred algorithm, desired alignment and
20195 size of chunks to be copied by main loop. */
20210 {
20235 }
20238 /* Step 1: Prologue guard. */
20240 /* Alignment code needs count to be in register. */
20242 {
20245 {
20246 align_bytes
20250 else
20252 }
20254 {
20259 }
20260 }
20261 /* Do the cheap promotion to allow better CSE across the
20262 main loop and epilogue (ie one load of the big constant in the
20263 front of all code. */
20267 /* Ensure that alignment prologue won't copy past end of block. */
20269 {
20271 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
20272 Make sure it is power of 2. */
20275 /* To improve performance of small blocks, we jump around the VAL
20276 promoting mode. This mean that if the promoted VAL is not constant,
20277 we might not use it in the epilogue and have to use byte
20278 loop variant. */
20282 {
20284 {
20285 /* If main algorithm works on QImode, no epilogue is needed.
20286 For small sizes just don't align anything. */
20289 else
20291 }
20292 }
20293 else
20294 {
20301 else
20303 }
20304 }
20306 {
20315 }
20317 /* Step 2: Alignment prologue. */
20319 /* Do the expensive promotion once we branched off the small blocks. */
20326 {
20328 {
20329 /* Except for the first move in epilogue, we no longer know
20330 constant offset in aliasing info. It don't seems to worth
20331 the pain to maintain it for the first move, so throw away
20332 the info early. */
20335 desired_align);
20336 }
20337 else
20338 {
20339 /* If we know how many bytes need to be stored before dst is
20340 sufficiently aligned, maintain aliasing info accurately. */
20345 }
20351 {
20352 /* It is possible that we copied enough so the main loop will not
20353 execute. */
20363 else
20365 }
20366 }
20368 {
20374 }
20378 /* Step 3: Main loop. */
20381 {
20409 }
20410 /* Adjust properly the offset of src and dest memory for aliasing. */
20414 else
20417 /* Step 4: Epilogue to copy the remaining bytes. */
20420 {
20421 /* When the main loop is done, COUNT_EXP might hold original count,
20422 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
20423 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
20424 bytes. Compensate if needed. */
20427 {
20428 tmp =
20431 OPTAB_DIRECT);
20434 }
20437 }
20438 epilogue:
20440 {
20443 epilogue_size_needed);
20444 else
20446 epilogue_size_needed);
20447 }
20451 }
20453 /* Expand the appropriate insns for doing strlen if not just doing
20454 repnz; scasb
20456 out = result, initialized with the start address
20457 align_rtx = alignment of the address.
20458 scratch = scratch register, initialized with the startaddress when
20459 not aligned, otherwise undefined
20461 This is just the body. It needs the initializations mentioned above and
20462 some address computing at the end. These things are done in i386.md. */
20464 static void
20466 {
20468 rtx tmp;
20473 rtx mem;
20476 rtx cmp;
20482 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
20484 /* Is there a known alignment and is it less than 4? */
20486 {
20489 /* Is there a known alignment and is it not 2? */
20491 {
20495 /* Leave just the 3 lower bits. */
20505 }
20506 else
20507 {
20508 /* Since the alignment is 2, we have to check 2 or 0 bytes;
20509 check if is aligned to 4 - byte. */
20516 }
20520 /* Now compare the bytes. */
20522 /* Compare the first n unaligned byte on a byte per byte basis. */
20526 /* Increment the address. */
20529 /* Not needed with an alignment of 2 */
20531 {
20535 end_0_label);
20540 }
20543 end_0_label);
20546 }
20548 /* Generate loop to check 4 bytes at a time. It is not a good idea to
20549 align this loop. It gives only huge programs, but does not help to
20550 speed up. */
20557 /* This formula yields a nonzero result iff one of the bytes is zero.
20558 This saves three branches inside loop and many cycles. */
20566 align_4_label);
20569 {
20575 /* If zero is not in the first two bytes, move two bytes forward. */
20581 reg,
20582 tmpreg)));
20583 /* Emit lea manually to avoid clobbering of flags. */
20591 reg2,
20592 out)));
20593 }
20594 else
20595 {
20597 /* Is zero in the first two bytes? */
20604 pc_rtx);
20608 /* Not in the first two. Move two bytes forward. */
20614 }
20616 /* Avoid branch in fixing the byte. */
20624 }
20626 /* Expand strlen. */
20628 bool
20630 {
20633 /* The generic case of strlen expander is long. Avoid it's
20634 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
20637 && !TARGET_INLINE_ALL_STRINGOPS
20647 {
20648 /* Well it seems that some optimizer does not combine a call like
20649 foo(strlen(bar), strlen(bar));
20650 when the move and the subtraction is done here. It does calculate
20651 the length just once when these instructions are done inside of
20652 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
20653 often used and I use one fewer register for the lifetime of
20654 output_strlen_unroll() this is better. */
20660 /* strlensi_unroll_1 returns the address of the zero at the end of
20661 the string, like memchr(), so compute the length by subtracting
20662 the start address. */
20664 }
20665 else
20666 {
20667 rtx unspec;
20669 /* Can't use this if the user has appropriated eax, ecx, or edi. */
20682 /* If .md starts supporting :P, this can be done in .md. */
20688 }
20690 }
20692 /* For given symbol (function) construct code to compute address of it's PLT
20693 entry in large x86-64 PIC model. */
20694 rtx
20696 {
20706 }
20708 rtx
20710 rtx callarg2,
20712 {
20720 {
20721 #if TARGET_MACHO
20724 #endif
20725 }
20726 else
20727 {
20728 /* Static functions and indirect calls don't need the pic register. */
20733 }
20736 {
20740 }
20750 {
20753 }
20759 {
20763 }
20767 {
20768 /* We need to represent that SI and DI registers are clobbered
20769 by SYSV calls. */
20775 };
20779 UNSPEC_MS_TO_SYSV_CALL);
20786 gen_rtx_REG
20794 }
20801 }
20803 \f
20804 /* Clear stack slot assignments remembered from previous functions.
20805 This is called from INIT_EXPANDERS once before RTL is emitted for each
20806 function. */
20810 {
20819 }
20821 /* Return a MEM corresponding to a stack slot with mode MODE.
20822 Allocate a new slot if necessary.
20824 The RTL for a function can have several slots available: N is
20825 which slot to use. */
20827 rtx
20829 {
20834 /* Virtual slot is valid only before vregs are instantiated. */
20849 }
20851 /* Construct the SYMBOL_REF for the tls_get_addr function. */
20854 rtx
20856 {
20859 {
20861 (TARGET_ANY_GNU_TLS
20865 }
20868 }
20870 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
20873 rtx
20875 {
20878 {
20883 }
20886 }
20887 \f
20888 /* Calculate the length of the memory address in the instruction
20889 encoding. Does not include the one-byte modrm, opcode, or prefix. */
20891 int
20893 {
20918 /* Rule of thumb:
20919 - esp as the base always wants an index,
20920 - ebp as the base always wants a displacement,
20921 - r12 as the base always wants an index,
20922 - r13 as the base always wants a displacement. */
20924 /* Register Indirect. */
20926 {
20927 /* esp (for its index) and ebp (for its displacement) need
20928 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
20929 code. */
20938 }
20940 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
20941 is not disp32, but disp32(%rip), so for disp32
20942 SIB byte is needed, unless print_operand_address
20943 optimizes it into disp32(%rip) or (%rip) is implied
20944 by UNSPEC. */
20946 {
20949 {
20965 }
20966 }
20968 else
20969 {
20970 /* Find the length of the displacement constant. */
20972 {
20975 else
20977 }
20978 /* ebp always wants a displacement. Similarly r13. */
20983 /* An index requires the two-byte modrm form.... */
20985 /* ...like esp (or r12), which always wants an index. */
20991 }
20994 {
21001 }
21004 }
21006 /* Compute default value for "length_immediate" attribute. When SHORTFORM
21007 is set, expect that insn have 8bit immediate alternative. */
21008 int
21010 {
21016 {
21021 {
21024 {
21036 }
21038 {
21041 }
21042 }
21044 {
21054 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
21060 }
21061 }
21063 }
21064 /* Compute default value for "length_address" attribute. */
21065 int
21067 {
21071 {
21081 {
21086 }
21089 }
21094 {
21097 {
21102 constraints++;
21105 ;
21106 /* Skip ignored operands. */
21109 }
21111 }
21113 }
21115 /* Compute default value for "length_vex" attribute. It includes
21116 2 or 3 byte VEX prefix and 1 opcode byte. */
21118 int
21121 {
21124 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
21125 byte VEX prefix. */
21129 /* We can always use 2 byte VEX prefix in 32bit. */
21137 {
21138 /* REX.W bit uses 3 byte VEX prefix. */
21142 }
21143 else
21144 {
21145 /* REX.X or REX.B bits use 3 byte VEX prefix. */
21149 }
21152 }
21153 \f
21154 /* Return the maximum number of instructions a cpu can issue. */
21156 static int
21158 {
21160 {
21182 }
21183 }
21185 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
21186 by DEP_INSN and nothing set by DEP_INSN. */
21188 static int
21190 {
21193 /* Simplify the test for uninteresting insns. */
21201 {
21204 }
21209 {
21212 }
21213 else
21219 /* This test is true if the dependent insn reads the flags but
21220 not any other potentially set register. */
21228 }
21230 /* Return true iff USE_INSN has a memory address with operands set by
21231 SET_INSN. */
21233 bool
21235 {
21240 {
21243 }
21245 }
21247 static int
21249 {
21255 /* Anti and output dependencies have zero cost on all CPUs. */
21261 /* If we can't recognize the insns, we can't really do anything. */
21269 {
21271 /* Address Generation Interlock adds a cycle of latency. */
21273 {
21284 }
21288 /* ??? Compares pair with jump/setcc. */
21292 /* Floating point stores require value to be ready one cycle earlier. */
21302 /* INT->FP conversion is expensive. */
21306 /* There is one cycle extra latency between an FP op and a store. */
21314 /* Show ability of reorder buffer to hide latency of load by executing
21315 in parallel with previous instruction in case
21316 previous instruction is not needed to compute the address. */
21319 {
21320 /* Claim moves to take one cycle, as core can issue one load
21321 at time and the next load can start cycle later. */
21326 cost--;
21327 }
21333 /* The esp dependency is resolved before the instruction is really
21334 finished. */
21339 /* INT->FP conversion is expensive. */
21343 /* Show ability of reorder buffer to hide latency of load by executing
21344 in parallel with previous instruction in case
21345 previous instruction is not needed to compute the address. */
21348 {
21349 /* Claim moves to take one cycle, as core can issue one load
21350 at time and the next load can start cycle later. */
21356 else
21358 }
21370 /* Show ability of reorder buffer to hide latency of load by executing
21371 in parallel with previous instruction in case
21372 previous instruction is not needed to compute the address. */
21375 {
21379 /* Because of the difference between the length of integer and
21380 floating unit pipeline preparation stages, the memory operands
21381 for floating point are cheaper.
21383 ??? For Athlon it the difference is most probably 2. */
21386 else
21391 else
21393 }
21397 }
21400 }
21402 /* How many alternative schedules to try. This should be as wide as the
21403 scheduling freedom in the DFA, but no wider. Making this value too
21404 large results extra work for the scheduler. */
21406 static int
21408 {
21410 {
21420 }
21421 }
21423 \f
21424 /* Compute the alignment given to a constant that is being placed in memory.
21425 EXP is the constant and ALIGN is the alignment that the object would
21426 ordinarily have.
21427 The value of this function is used instead of that alignment to align
21428 the object. */
21430 int
21432 {
21435 {
21440 }
21446 }
21448 /* Compute the alignment for a static variable.
21449 TYPE is the data type, and ALIGN is the alignment that
21450 the object would ordinarily have. The value of this function is used
21451 instead of that alignment to align the object. */
21453 int
21455 {
21466 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
21467 to 16byte boundary. */
21469 {
21476 }
21479 {
21484 }
21486 {
21493 }
21498 {
21503 }
21506 {
21511 }
21514 }
21516 /* Compute the alignment for a local variable or a stack slot. EXP is
21517 the data type or decl itself, MODE is the widest mode available and
21518 ALIGN is the alignment that the object would ordinarily have. The
21519 value of this macro is used instead of that alignment to align the
21520 object. */
21522 unsigned int
21525 {
21529 {
21532 }
21533 else
21534 {
21537 }
21539 /* Don't do dynamic stack realignment for long long objects with
21540 -mpreferred-stack-boundary=2. */
21549 /* If TYPE is NULL, we are allocating a stack slot for caller-save
21550 register in MODE. We will return the largest alignment of XF
21551 and DF. */
21553 {
21557 }
21559 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
21560 to 16byte boundary. Exact wording is:
21562 An array uses the same alignment as its elements, except that a local or
21563 global array variable of length at least 16 bytes or
21564 a C99 variable-length array variable always has alignment of at least 16 bytes.
21566 This was added to allow use of aligned SSE instructions at arrays. This
21567 rule is meant for static storage (where compiler can not do the analysis
21568 by itself). We follow it for automatic variables only when convenient.
21569 We fully control everything in the function compiled and functions from
21570 other unit can not rely on the alignment.
21572 Exclude va_list type. It is the common case of local array where
21573 we can not benefit from the alignment. */
21576 {
21585 }
21587 {
21592 }
21594 {
21600 }
21605 {
21610 }
21613 {
21619 }
21621 }
21623 /* Compute the minimum required alignment for dynamic stack realignment
21624 purposes for a local variable, parameter or a stack slot. EXP is
21625 the data type or decl itself, MODE is its mode and ALIGN is the
21626 alignment that the object would ordinarily have. */
21628 unsigned int
21631 {
21638 {
21641 }
21642 else
21643 {
21646 }
21648 /* Don't do dynamic stack realignment for long long objects with
21649 -mpreferred-stack-boundary=2. */
21656 }
21657 \f
21658 /* Find a location for the static chain incoming to a nested function.
21659 This is a register, unless all free registers are used by arguments. */
21661 static rtx
21663 {
21670 {
21671 /* We always use R10 in 64-bit mode. */
21673 }
21674 else
21675 {
21676 tree fntype;
21677 /* By default in 32-bit mode we use ECX to pass the static chain. */
21682 {
21683 /* Fastcall functions use ecx/edx for arguments, which leaves
21684 us with EAX for the static chain. */
21686 }
21688 {
21689 /* Thiscall functions use ecx for arguments, which leaves
21690 us with EAX for the static chain. */
21692 }
21694 {
21695 /* For regparm 3, we have no free call-clobbered registers in
21696 which to store the static chain. In order to implement this,
21697 we have the trampoline push the static chain to the stack.
21698 However, we can't push a value below the return address when
21699 we call the nested function directly, so we have to use an
21700 alternate entry point. For this we use ESI, and have the
21701 alternate entry point push ESI, so that things appear the
21702 same once we're executing the nested function. */
21704 {
21709 }
21711 }
21712 }
21715 }
21717 /* Emit RTL insns to initialize the variable parts of a trampoline.
21718 FNDECL is the decl of the target address; M_TRAMP is a MEM for
21719 the trampoline, and CHAIN_VALUE is an RTX for the static chain
21720 to be passed to the target function. */
21722 static void
21724 {
21730 {
21734 /* Depending on the static chain location, either load a register
21735 with a constant, or push the constant to the stack. All of the
21736 instructions are the same size. */
21739 {
21744 else
21746 }
21747 else
21756 /* Compute offset from the end of the jmp to the target function.
21757 In the case in which the trampoline stores the static chain on
21758 the stack, we need to skip the first insn which pushes the
21759 (call-saved) register static chain; this push is 1 byte. */
21770 }
21771 else
21772 {
21775 /* Load the function address to r11. Try to load address using
21776 the shorter movl instead of movabs. We may want to support
21777 movq for kernel mode, but kernel does not use trampolines at
21778 the moment. */
21780 {
21789 }
21790 else
21791 {
21798 }
21800 /* Load static chain using movabs to r10. */
21808 /* Jump to r11; the last (unused) byte is a nop, only there to
21809 pad the write out to a single 32-bit store. */
21815 }
21817 #ifdef ENABLE_EXECUTE_STACK
21818 #ifdef CHECK_EXECUTE_STACK_ENABLED
21820 #endif
21823 #endif
21824 }
21825 \f
21826 /* The following file contains several enumerations and data structures
21827 built from the definitions in i386-builtin-types.def. */
21831 /* Table for the ix86 builtin non-function types. */
21834 /* Retrieve an element from the above table, building some of
21835 the types lazily. */
21837 static tree
21839 {
21851 {
21859 }
21860 else
21861 {
21867 else
21875 }
21879 }
21881 /* Table for the ix86 builtin function types. */
21884 /* Retrieve an element from the above table, building some of
21885 the types lazily. */
21887 static tree
21889 {
21890 tree type;
21899 {
21907 {
21910 }
21913 }
21914 else
21915 {
21921 }
21925 }
21928 /* Codes for all the SSE/MMX builtins. */
21929 enum ix86_builtins
21930 {
21931 IX86_BUILTIN_ADDPS,
21932 IX86_BUILTIN_ADDSS,
21933 IX86_BUILTIN_DIVPS,
21934 IX86_BUILTIN_DIVSS,
21935 IX86_BUILTIN_MULPS,
21936 IX86_BUILTIN_MULSS,
21937 IX86_BUILTIN_SUBPS,
21938 IX86_BUILTIN_SUBSS,
21940 IX86_BUILTIN_CMPEQPS,
21941 IX86_BUILTIN_CMPLTPS,
21942 IX86_BUILTIN_CMPLEPS,
21943 IX86_BUILTIN_CMPGTPS,
21944 IX86_BUILTIN_CMPGEPS,
21945 IX86_BUILTIN_CMPNEQPS,
21946 IX86_BUILTIN_CMPNLTPS,
21947 IX86_BUILTIN_CMPNLEPS,
21948 IX86_BUILTIN_CMPNGTPS,
21949 IX86_BUILTIN_CMPNGEPS,
21950 IX86_BUILTIN_CMPORDPS,
21951 IX86_BUILTIN_CMPUNORDPS,
21952 IX86_BUILTIN_CMPEQSS,
21953 IX86_BUILTIN_CMPLTSS,
21954 IX86_BUILTIN_CMPLESS,
21955 IX86_BUILTIN_CMPNEQSS,
21956 IX86_BUILTIN_CMPNLTSS,
21957 IX86_BUILTIN_CMPNLESS,
21958 IX86_BUILTIN_CMPNGTSS,
21959 IX86_BUILTIN_CMPNGESS,
21960 IX86_BUILTIN_CMPORDSS,
21961 IX86_BUILTIN_CMPUNORDSS,
21963 IX86_BUILTIN_COMIEQSS,
21964 IX86_BUILTIN_COMILTSS,
21965 IX86_BUILTIN_COMILESS,
21966 IX86_BUILTIN_COMIGTSS,
21967 IX86_BUILTIN_COMIGESS,
21968 IX86_BUILTIN_COMINEQSS,
21969 IX86_BUILTIN_UCOMIEQSS,
21970 IX86_BUILTIN_UCOMILTSS,
21971 IX86_BUILTIN_UCOMILESS,
21972 IX86_BUILTIN_UCOMIGTSS,
21973 IX86_BUILTIN_UCOMIGESS,
21974 IX86_BUILTIN_UCOMINEQSS,
21976 IX86_BUILTIN_CVTPI2PS,
21977 IX86_BUILTIN_CVTPS2PI,
21978 IX86_BUILTIN_CVTSI2SS,
21979 IX86_BUILTIN_CVTSI642SS,
21980 IX86_BUILTIN_CVTSS2SI,
21981 IX86_BUILTIN_CVTSS2SI64,
21982 IX86_BUILTIN_CVTTPS2PI,
21983 IX86_BUILTIN_CVTTSS2SI,
21984 IX86_BUILTIN_CVTTSS2SI64,
21986 IX86_BUILTIN_MAXPS,
21987 IX86_BUILTIN_MAXSS,
21988 IX86_BUILTIN_MINPS,
21989 IX86_BUILTIN_MINSS,
21991 IX86_BUILTIN_LOADUPS,
21992 IX86_BUILTIN_STOREUPS,
21993 IX86_BUILTIN_MOVSS,
21995 IX86_BUILTIN_MOVHLPS,
21996 IX86_BUILTIN_MOVLHPS,
21997 IX86_BUILTIN_LOADHPS,
21998 IX86_BUILTIN_LOADLPS,
21999 IX86_BUILTIN_STOREHPS,
22000 IX86_BUILTIN_STORELPS,
22002 IX86_BUILTIN_MASKMOVQ,
22003 IX86_BUILTIN_MOVMSKPS,
22004 IX86_BUILTIN_PMOVMSKB,
22006 IX86_BUILTIN_MOVNTPS,
22007 IX86_BUILTIN_MOVNTQ,
22009 IX86_BUILTIN_LOADDQU,
22010 IX86_BUILTIN_STOREDQU,
22012 IX86_BUILTIN_PACKSSWB,
22013 IX86_BUILTIN_PACKSSDW,
22014 IX86_BUILTIN_PACKUSWB,
22016 IX86_BUILTIN_PADDB,
22017 IX86_BUILTIN_PADDW,
22018 IX86_BUILTIN_PADDD,
22019 IX86_BUILTIN_PADDQ,
22020 IX86_BUILTIN_PADDSB,
22021 IX86_BUILTIN_PADDSW,
22022 IX86_BUILTIN_PADDUSB,
22023 IX86_BUILTIN_PADDUSW,
22024 IX86_BUILTIN_PSUBB,
22025 IX86_BUILTIN_PSUBW,
22026 IX86_BUILTIN_PSUBD,
22027 IX86_BUILTIN_PSUBQ,
22028 IX86_BUILTIN_PSUBSB,
22029 IX86_BUILTIN_PSUBSW,
22030 IX86_BUILTIN_PSUBUSB,
22031 IX86_BUILTIN_PSUBUSW,
22033 IX86_BUILTIN_PAND,
22034 IX86_BUILTIN_PANDN,
22035 IX86_BUILTIN_POR,
22036 IX86_BUILTIN_PXOR,
22038 IX86_BUILTIN_PAVGB,
22039 IX86_BUILTIN_PAVGW,
22041 IX86_BUILTIN_PCMPEQB,
22042 IX86_BUILTIN_PCMPEQW,
22043 IX86_BUILTIN_PCMPEQD,
22044 IX86_BUILTIN_PCMPGTB,
22045 IX86_BUILTIN_PCMPGTW,
22046 IX86_BUILTIN_PCMPGTD,
22048 IX86_BUILTIN_PMADDWD,
22050 IX86_BUILTIN_PMAXSW,
22051 IX86_BUILTIN_PMAXUB,
22052 IX86_BUILTIN_PMINSW,
22053 IX86_BUILTIN_PMINUB,
22055 IX86_BUILTIN_PMULHUW,
22056 IX86_BUILTIN_PMULHW,
22057 IX86_BUILTIN_PMULLW,
22059 IX86_BUILTIN_PSADBW,
22060 IX86_BUILTIN_PSHUFW,
22062 IX86_BUILTIN_PSLLW,
22063 IX86_BUILTIN_PSLLD,
22064 IX86_BUILTIN_PSLLQ,
22065 IX86_BUILTIN_PSRAW,
22066 IX86_BUILTIN_PSRAD,
22067 IX86_BUILTIN_PSRLW,
22068 IX86_BUILTIN_PSRLD,
22069 IX86_BUILTIN_PSRLQ,
22070 IX86_BUILTIN_PSLLWI,
22071 IX86_BUILTIN_PSLLDI,
22072 IX86_BUILTIN_PSLLQI,
22073 IX86_BUILTIN_PSRAWI,
22074 IX86_BUILTIN_PSRADI,
22075 IX86_BUILTIN_PSRLWI,
22076 IX86_BUILTIN_PSRLDI,
22077 IX86_BUILTIN_PSRLQI,
22079 IX86_BUILTIN_PUNPCKHBW,
22080 IX86_BUILTIN_PUNPCKHWD,
22081 IX86_BUILTIN_PUNPCKHDQ,
22082 IX86_BUILTIN_PUNPCKLBW,
22083 IX86_BUILTIN_PUNPCKLWD,
22084 IX86_BUILTIN_PUNPCKLDQ,
22086 IX86_BUILTIN_SHUFPS,
22088 IX86_BUILTIN_RCPPS,
22089 IX86_BUILTIN_RCPSS,
22090 IX86_BUILTIN_RSQRTPS,
22091 IX86_BUILTIN_RSQRTPS_NR,
22092 IX86_BUILTIN_RSQRTSS,
22093 IX86_BUILTIN_RSQRTF,
22094 IX86_BUILTIN_SQRTPS,
22095 IX86_BUILTIN_SQRTPS_NR,
22096 IX86_BUILTIN_SQRTSS,
22098 IX86_BUILTIN_UNPCKHPS,
22099 IX86_BUILTIN_UNPCKLPS,
22101 IX86_BUILTIN_ANDPS,
22102 IX86_BUILTIN_ANDNPS,
22103 IX86_BUILTIN_ORPS,
22104 IX86_BUILTIN_XORPS,
22106 IX86_BUILTIN_EMMS,
22107 IX86_BUILTIN_LDMXCSR,
22108 IX86_BUILTIN_STMXCSR,
22109 IX86_BUILTIN_SFENCE,
22111 /* 3DNow! Original */
22112 IX86_BUILTIN_FEMMS,
22113 IX86_BUILTIN_PAVGUSB,
22114 IX86_BUILTIN_PF2ID,
22115 IX86_BUILTIN_PFACC,
22116 IX86_BUILTIN_PFADD,
22117 IX86_BUILTIN_PFCMPEQ,
22118 IX86_BUILTIN_PFCMPGE,
22119 IX86_BUILTIN_PFCMPGT,
22120 IX86_BUILTIN_PFMAX,
22121 IX86_BUILTIN_PFMIN,
22122 IX86_BUILTIN_PFMUL,
22123 IX86_BUILTIN_PFRCP,
22124 IX86_BUILTIN_PFRCPIT1,
22125 IX86_BUILTIN_PFRCPIT2,
22126 IX86_BUILTIN_PFRSQIT1,
22127 IX86_BUILTIN_PFRSQRT,
22128 IX86_BUILTIN_PFSUB,
22129 IX86_BUILTIN_PFSUBR,
22130 IX86_BUILTIN_PI2FD,
22131 IX86_BUILTIN_PMULHRW,
22133 /* 3DNow! Athlon Extensions */
22134 IX86_BUILTIN_PF2IW,
22135 IX86_BUILTIN_PFNACC,
22136 IX86_BUILTIN_PFPNACC,
22137 IX86_BUILTIN_PI2FW,
22138 IX86_BUILTIN_PSWAPDSI,
22139 IX86_BUILTIN_PSWAPDSF,
22141 /* SSE2 */
22142 IX86_BUILTIN_ADDPD,
22143 IX86_BUILTIN_ADDSD,
22144 IX86_BUILTIN_DIVPD,
22145 IX86_BUILTIN_DIVSD,
22146 IX86_BUILTIN_MULPD,
22147 IX86_BUILTIN_MULSD,
22148 IX86_BUILTIN_SUBPD,
22149 IX86_BUILTIN_SUBSD,
22151 IX86_BUILTIN_CMPEQPD,
22152 IX86_BUILTIN_CMPLTPD,
22153 IX86_BUILTIN_CMPLEPD,
22154 IX86_BUILTIN_CMPGTPD,
22155 IX86_BUILTIN_CMPGEPD,
22156 IX86_BUILTIN_CMPNEQPD,
22157 IX86_BUILTIN_CMPNLTPD,
22158 IX86_BUILTIN_CMPNLEPD,
22159 IX86_BUILTIN_CMPNGTPD,
22160 IX86_BUILTIN_CMPNGEPD,
22161 IX86_BUILTIN_CMPORDPD,
22162 IX86_BUILTIN_CMPUNORDPD,
22163 IX86_BUILTIN_CMPEQSD,
22164 IX86_BUILTIN_CMPLTSD,
22165 IX86_BUILTIN_CMPLESD,
22166 IX86_BUILTIN_CMPNEQSD,
22167 IX86_BUILTIN_CMPNLTSD,
22168 IX86_BUILTIN_CMPNLESD,
22169 IX86_BUILTIN_CMPORDSD,
22170 IX86_BUILTIN_CMPUNORDSD,
22172 IX86_BUILTIN_COMIEQSD,
22173 IX86_BUILTIN_COMILTSD,
22174 IX86_BUILTIN_COMILESD,
22175 IX86_BUILTIN_COMIGTSD,
22176 IX86_BUILTIN_COMIGESD,
22177 IX86_BUILTIN_COMINEQSD,
22178 IX86_BUILTIN_UCOMIEQSD,
22179 IX86_BUILTIN_UCOMILTSD,
22180 IX86_BUILTIN_UCOMILESD,
22181 IX86_BUILTIN_UCOMIGTSD,
22182 IX86_BUILTIN_UCOMIGESD,
22183 IX86_BUILTIN_UCOMINEQSD,
22185 IX86_BUILTIN_MAXPD,
22186 IX86_BUILTIN_MAXSD,
22187 IX86_BUILTIN_MINPD,
22188 IX86_BUILTIN_MINSD,
22190 IX86_BUILTIN_ANDPD,
22191 IX86_BUILTIN_ANDNPD,
22192 IX86_BUILTIN_ORPD,
22193 IX86_BUILTIN_XORPD,
22195 IX86_BUILTIN_SQRTPD,
22196 IX86_BUILTIN_SQRTSD,
22198 IX86_BUILTIN_UNPCKHPD,
22199 IX86_BUILTIN_UNPCKLPD,
22201 IX86_BUILTIN_SHUFPD,
22203 IX86_BUILTIN_LOADUPD,
22204 IX86_BUILTIN_STOREUPD,
22205 IX86_BUILTIN_MOVSD,
22207 IX86_BUILTIN_LOADHPD,
22208 IX86_BUILTIN_LOADLPD,
22210 IX86_BUILTIN_CVTDQ2PD,
22211 IX86_BUILTIN_CVTDQ2PS,
22213 IX86_BUILTIN_CVTPD2DQ,
22214 IX86_BUILTIN_CVTPD2PI,
22215 IX86_BUILTIN_CVTPD2PS,
22216 IX86_BUILTIN_CVTTPD2DQ,
22217 IX86_BUILTIN_CVTTPD2PI,
22219 IX86_BUILTIN_CVTPI2PD,
22220 IX86_BUILTIN_CVTSI2SD,
22221 IX86_BUILTIN_CVTSI642SD,
22223 IX86_BUILTIN_CVTSD2SI,
22224 IX86_BUILTIN_CVTSD2SI64,
22225 IX86_BUILTIN_CVTSD2SS,
22226 IX86_BUILTIN_CVTSS2SD,
22227 IX86_BUILTIN_CVTTSD2SI,
22228 IX86_BUILTIN_CVTTSD2SI64,
22230 IX86_BUILTIN_CVTPS2DQ,
22231 IX86_BUILTIN_CVTPS2PD,
22232 IX86_BUILTIN_CVTTPS2DQ,
22234 IX86_BUILTIN_MOVNTI,
22235 IX86_BUILTIN_MOVNTPD,
22236 IX86_BUILTIN_MOVNTDQ,
22238 IX86_BUILTIN_MOVQ128,
22240 /* SSE2 MMX */
22241 IX86_BUILTIN_MASKMOVDQU,
22242 IX86_BUILTIN_MOVMSKPD,
22243 IX86_BUILTIN_PMOVMSKB128,
22245 IX86_BUILTIN_PACKSSWB128,
22246 IX86_BUILTIN_PACKSSDW128,
22247 IX86_BUILTIN_PACKUSWB128,
22249 IX86_BUILTIN_PADDB128,
22250 IX86_BUILTIN_PADDW128,
22251 IX86_BUILTIN_PADDD128,
22252 IX86_BUILTIN_PADDQ128,
22253 IX86_BUILTIN_PADDSB128,
22254 IX86_BUILTIN_PADDSW128,
22255 IX86_BUILTIN_PADDUSB128,
22256 IX86_BUILTIN_PADDUSW128,
22257 IX86_BUILTIN_PSUBB128,
22258 IX86_BUILTIN_PSUBW128,
22259 IX86_BUILTIN_PSUBD128,
22260 IX86_BUILTIN_PSUBQ128,
22261 IX86_BUILTIN_PSUBSB128,
22262 IX86_BUILTIN_PSUBSW128,
22263 IX86_BUILTIN_PSUBUSB128,
22264 IX86_BUILTIN_PSUBUSW128,
22266 IX86_BUILTIN_PAND128,
22267 IX86_BUILTIN_PANDN128,
22268 IX86_BUILTIN_POR128,
22269 IX86_BUILTIN_PXOR128,
22271 IX86_BUILTIN_PAVGB128,
22272 IX86_BUILTIN_PAVGW128,
22274 IX86_BUILTIN_PCMPEQB128,
22275 IX86_BUILTIN_PCMPEQW128,
22276 IX86_BUILTIN_PCMPEQD128,
22277 IX86_BUILTIN_PCMPGTB128,
22278 IX86_BUILTIN_PCMPGTW128,
22279 IX86_BUILTIN_PCMPGTD128,
22281 IX86_BUILTIN_PMADDWD128,
22283 IX86_BUILTIN_PMAXSW128,
22284 IX86_BUILTIN_PMAXUB128,
22285 IX86_BUILTIN_PMINSW128,
22286 IX86_BUILTIN_PMINUB128,
22288 IX86_BUILTIN_PMULUDQ,
22289 IX86_BUILTIN_PMULUDQ128,
22290 IX86_BUILTIN_PMULHUW128,
22291 IX86_BUILTIN_PMULHW128,
22292 IX86_BUILTIN_PMULLW128,
22294 IX86_BUILTIN_PSADBW128,
22295 IX86_BUILTIN_PSHUFHW,
22296 IX86_BUILTIN_PSHUFLW,
22297 IX86_BUILTIN_PSHUFD,
22299 IX86_BUILTIN_PSLLDQI128,
22300 IX86_BUILTIN_PSLLWI128,
22301 IX86_BUILTIN_PSLLDI128,
22302 IX86_BUILTIN_PSLLQI128,
22303 IX86_BUILTIN_PSRAWI128,
22304 IX86_BUILTIN_PSRADI128,
22305 IX86_BUILTIN_PSRLDQI128,
22306 IX86_BUILTIN_PSRLWI128,
22307 IX86_BUILTIN_PSRLDI128,
22308 IX86_BUILTIN_PSRLQI128,
22310 IX86_BUILTIN_PSLLDQ128,
22311 IX86_BUILTIN_PSLLW128,
22312 IX86_BUILTIN_PSLLD128,
22313 IX86_BUILTIN_PSLLQ128,
22314 IX86_BUILTIN_PSRAW128,
22315 IX86_BUILTIN_PSRAD128,
22316 IX86_BUILTIN_PSRLW128,
22317 IX86_BUILTIN_PSRLD128,
22318 IX86_BUILTIN_PSRLQ128,
22320 IX86_BUILTIN_PUNPCKHBW128,
22321 IX86_BUILTIN_PUNPCKHWD128,
22322 IX86_BUILTIN_PUNPCKHDQ128,
22323 IX86_BUILTIN_PUNPCKHQDQ128,
22324 IX86_BUILTIN_PUNPCKLBW128,
22325 IX86_BUILTIN_PUNPCKLWD128,
22326 IX86_BUILTIN_PUNPCKLDQ128,
22327 IX86_BUILTIN_PUNPCKLQDQ128,
22329 IX86_BUILTIN_CLFLUSH,
22330 IX86_BUILTIN_MFENCE,
22331 IX86_BUILTIN_LFENCE,
22333 IX86_BUILTIN_BSRSI,
22334 IX86_BUILTIN_BSRDI,
22335 IX86_BUILTIN_RDPMC,
22336 IX86_BUILTIN_RDTSC,
22337 IX86_BUILTIN_RDTSCP,
22338 IX86_BUILTIN_ROLQI,
22339 IX86_BUILTIN_ROLHI,
22340 IX86_BUILTIN_RORQI,
22341 IX86_BUILTIN_RORHI,
22343 /* SSE3. */
22344 IX86_BUILTIN_ADDSUBPS,
22345 IX86_BUILTIN_HADDPS,
22346 IX86_BUILTIN_HSUBPS,
22347 IX86_BUILTIN_MOVSHDUP,
22348 IX86_BUILTIN_MOVSLDUP,
22349 IX86_BUILTIN_ADDSUBPD,
22350 IX86_BUILTIN_HADDPD,
22351 IX86_BUILTIN_HSUBPD,
22352 IX86_BUILTIN_LDDQU,
22354 IX86_BUILTIN_MONITOR,
22355 IX86_BUILTIN_MWAIT,
22357 /* SSSE3. */
22358 IX86_BUILTIN_PHADDW,
22359 IX86_BUILTIN_PHADDD,
22360 IX86_BUILTIN_PHADDSW,
22361 IX86_BUILTIN_PHSUBW,
22362 IX86_BUILTIN_PHSUBD,
22363 IX86_BUILTIN_PHSUBSW,
22364 IX86_BUILTIN_PMADDUBSW,
22365 IX86_BUILTIN_PMULHRSW,
22366 IX86_BUILTIN_PSHUFB,
22367 IX86_BUILTIN_PSIGNB,
22368 IX86_BUILTIN_PSIGNW,
22369 IX86_BUILTIN_PSIGND,
22370 IX86_BUILTIN_PALIGNR,
22371 IX86_BUILTIN_PABSB,
22372 IX86_BUILTIN_PABSW,
22373 IX86_BUILTIN_PABSD,
22375 IX86_BUILTIN_PHADDW128,
22376 IX86_BUILTIN_PHADDD128,
22377 IX86_BUILTIN_PHADDSW128,
22378 IX86_BUILTIN_PHSUBW128,
22379 IX86_BUILTIN_PHSUBD128,
22380 IX86_BUILTIN_PHSUBSW128,
22381 IX86_BUILTIN_PMADDUBSW128,
22382 IX86_BUILTIN_PMULHRSW128,
22383 IX86_BUILTIN_PSHUFB128,
22384 IX86_BUILTIN_PSIGNB128,
22385 IX86_BUILTIN_PSIGNW128,
22386 IX86_BUILTIN_PSIGND128,
22387 IX86_BUILTIN_PALIGNR128,
22388 IX86_BUILTIN_PABSB128,
22389 IX86_BUILTIN_PABSW128,
22390 IX86_BUILTIN_PABSD128,
22392 /* AMDFAM10 - SSE4A New Instructions. */
22393 IX86_BUILTIN_MOVNTSD,
22394 IX86_BUILTIN_MOVNTSS,
22395 IX86_BUILTIN_EXTRQI,
22396 IX86_BUILTIN_EXTRQ,
22397 IX86_BUILTIN_INSERTQI,
22398 IX86_BUILTIN_INSERTQ,
22400 /* SSE4.1. */
22401 IX86_BUILTIN_BLENDPD,
22402 IX86_BUILTIN_BLENDPS,
22403 IX86_BUILTIN_BLENDVPD,
22404 IX86_BUILTIN_BLENDVPS,
22405 IX86_BUILTIN_PBLENDVB128,
22406 IX86_BUILTIN_PBLENDW128,
22408 IX86_BUILTIN_DPPD,
22409 IX86_BUILTIN_DPPS,
22411 IX86_BUILTIN_INSERTPS128,
22413 IX86_BUILTIN_MOVNTDQA,
22414 IX86_BUILTIN_MPSADBW128,
22415 IX86_BUILTIN_PACKUSDW128,
22416 IX86_BUILTIN_PCMPEQQ,
22417 IX86_BUILTIN_PHMINPOSUW128,
22419 IX86_BUILTIN_PMAXSB128,
22420 IX86_BUILTIN_PMAXSD128,
22421 IX86_BUILTIN_PMAXUD128,
22422 IX86_BUILTIN_PMAXUW128,
22424 IX86_BUILTIN_PMINSB128,
22425 IX86_BUILTIN_PMINSD128,
22426 IX86_BUILTIN_PMINUD128,
22427 IX86_BUILTIN_PMINUW128,
22429 IX86_BUILTIN_PMOVSXBW128,
22430 IX86_BUILTIN_PMOVSXBD128,
22431 IX86_BUILTIN_PMOVSXBQ128,
22432 IX86_BUILTIN_PMOVSXWD128,
22433 IX86_BUILTIN_PMOVSXWQ128,
22434 IX86_BUILTIN_PMOVSXDQ128,
22436 IX86_BUILTIN_PMOVZXBW128,
22437 IX86_BUILTIN_PMOVZXBD128,
22438 IX86_BUILTIN_PMOVZXBQ128,
22439 IX86_BUILTIN_PMOVZXWD128,
22440 IX86_BUILTIN_PMOVZXWQ128,
22441 IX86_BUILTIN_PMOVZXDQ128,
22443 IX86_BUILTIN_PMULDQ128,
22444 IX86_BUILTIN_PMULLD128,
22446 IX86_BUILTIN_ROUNDPD,
22447 IX86_BUILTIN_ROUNDPS,
22448 IX86_BUILTIN_ROUNDSD,
22449 IX86_BUILTIN_ROUNDSS,
22451 IX86_BUILTIN_PTESTZ,
22452 IX86_BUILTIN_PTESTC,
22453 IX86_BUILTIN_PTESTNZC,
22455 IX86_BUILTIN_VEC_INIT_V2SI,
22456 IX86_BUILTIN_VEC_INIT_V4HI,
22457 IX86_BUILTIN_VEC_INIT_V8QI,
22458 IX86_BUILTIN_VEC_EXT_V2DF,
22459 IX86_BUILTIN_VEC_EXT_V2DI,
22460 IX86_BUILTIN_VEC_EXT_V4SF,
22461 IX86_BUILTIN_VEC_EXT_V4SI,
22462 IX86_BUILTIN_VEC_EXT_V8HI,
22463 IX86_BUILTIN_VEC_EXT_V2SI,
22464 IX86_BUILTIN_VEC_EXT_V4HI,
22465 IX86_BUILTIN_VEC_EXT_V16QI,
22466 IX86_BUILTIN_VEC_SET_V2DI,
22467 IX86_BUILTIN_VEC_SET_V4SF,
22468 IX86_BUILTIN_VEC_SET_V4SI,
22469 IX86_BUILTIN_VEC_SET_V8HI,
22470 IX86_BUILTIN_VEC_SET_V4HI,
22471 IX86_BUILTIN_VEC_SET_V16QI,
22473 IX86_BUILTIN_VEC_PACK_SFIX,
22475 /* SSE4.2. */
22476 IX86_BUILTIN_CRC32QI,
22477 IX86_BUILTIN_CRC32HI,
22478 IX86_BUILTIN_CRC32SI,
22479 IX86_BUILTIN_CRC32DI,
22481 IX86_BUILTIN_PCMPESTRI128,
22482 IX86_BUILTIN_PCMPESTRM128,
22483 IX86_BUILTIN_PCMPESTRA128,
22484 IX86_BUILTIN_PCMPESTRC128,
22485 IX86_BUILTIN_PCMPESTRO128,
22486 IX86_BUILTIN_PCMPESTRS128,
22487 IX86_BUILTIN_PCMPESTRZ128,
22488 IX86_BUILTIN_PCMPISTRI128,
22489 IX86_BUILTIN_PCMPISTRM128,
22490 IX86_BUILTIN_PCMPISTRA128,
22491 IX86_BUILTIN_PCMPISTRC128,
22492 IX86_BUILTIN_PCMPISTRO128,
22493 IX86_BUILTIN_PCMPISTRS128,
22494 IX86_BUILTIN_PCMPISTRZ128,
22496 IX86_BUILTIN_PCMPGTQ,
22498 /* AES instructions */
22499 IX86_BUILTIN_AESENC128,
22500 IX86_BUILTIN_AESENCLAST128,
22501 IX86_BUILTIN_AESDEC128,
22502 IX86_BUILTIN_AESDECLAST128,
22503 IX86_BUILTIN_AESIMC128,
22504 IX86_BUILTIN_AESKEYGENASSIST128,
22506 /* PCLMUL instruction */
22507 IX86_BUILTIN_PCLMULQDQ128,
22509 /* AVX */
22510 IX86_BUILTIN_ADDPD256,
22511 IX86_BUILTIN_ADDPS256,
22512 IX86_BUILTIN_ADDSUBPD256,
22513 IX86_BUILTIN_ADDSUBPS256,
22514 IX86_BUILTIN_ANDPD256,
22515 IX86_BUILTIN_ANDPS256,
22516 IX86_BUILTIN_ANDNPD256,
22517 IX86_BUILTIN_ANDNPS256,
22518 IX86_BUILTIN_BLENDPD256,
22519 IX86_BUILTIN_BLENDPS256,
22520 IX86_BUILTIN_BLENDVPD256,
22521 IX86_BUILTIN_BLENDVPS256,
22522 IX86_BUILTIN_DIVPD256,
22523 IX86_BUILTIN_DIVPS256,
22524 IX86_BUILTIN_DPPS256,
22525 IX86_BUILTIN_HADDPD256,
22526 IX86_BUILTIN_HADDPS256,
22527 IX86_BUILTIN_HSUBPD256,
22528 IX86_BUILTIN_HSUBPS256,
22529 IX86_BUILTIN_MAXPD256,
22530 IX86_BUILTIN_MAXPS256,
22531 IX86_BUILTIN_MINPD256,
22532 IX86_BUILTIN_MINPS256,
22533 IX86_BUILTIN_MULPD256,
22534 IX86_BUILTIN_MULPS256,
22535 IX86_BUILTIN_ORPD256,
22536 IX86_BUILTIN_ORPS256,
22537 IX86_BUILTIN_SHUFPD256,
22538 IX86_BUILTIN_SHUFPS256,
22539 IX86_BUILTIN_SUBPD256,
22540 IX86_BUILTIN_SUBPS256,
22541 IX86_BUILTIN_XORPD256,
22542 IX86_BUILTIN_XORPS256,
22543 IX86_BUILTIN_CMPSD,
22544 IX86_BUILTIN_CMPSS,
22545 IX86_BUILTIN_CMPPD,
22546 IX86_BUILTIN_CMPPS,
22547 IX86_BUILTIN_CMPPD256,
22548 IX86_BUILTIN_CMPPS256,
22549 IX86_BUILTIN_CVTDQ2PD256,
22550 IX86_BUILTIN_CVTDQ2PS256,
22551 IX86_BUILTIN_CVTPD2PS256,
22552 IX86_BUILTIN_CVTPS2DQ256,
22553 IX86_BUILTIN_CVTPS2PD256,
22554 IX86_BUILTIN_CVTTPD2DQ256,
22555 IX86_BUILTIN_CVTPD2DQ256,
22556 IX86_BUILTIN_CVTTPS2DQ256,
22557 IX86_BUILTIN_EXTRACTF128PD256,
22558 IX86_BUILTIN_EXTRACTF128PS256,
22559 IX86_BUILTIN_EXTRACTF128SI256,
22560 IX86_BUILTIN_VZEROALL,
22561 IX86_BUILTIN_VZEROUPPER,
22562 IX86_BUILTIN_VPERMILVARPD,
22563 IX86_BUILTIN_VPERMILVARPS,
22564 IX86_BUILTIN_VPERMILVARPD256,
22565 IX86_BUILTIN_VPERMILVARPS256,
22566 IX86_BUILTIN_VPERMILPD,
22567 IX86_BUILTIN_VPERMILPS,
22568 IX86_BUILTIN_VPERMILPD256,
22569 IX86_BUILTIN_VPERMILPS256,
22570 IX86_BUILTIN_VPERMIL2PD,
22571 IX86_BUILTIN_VPERMIL2PS,
22572 IX86_BUILTIN_VPERMIL2PD256,
22573 IX86_BUILTIN_VPERMIL2PS256,
22574 IX86_BUILTIN_VPERM2F128PD256,
22575 IX86_BUILTIN_VPERM2F128PS256,
22576 IX86_BUILTIN_VPERM2F128SI256,
22577 IX86_BUILTIN_VBROADCASTSS,
22578 IX86_BUILTIN_VBROADCASTSD256,
22579 IX86_BUILTIN_VBROADCASTSS256,
22580 IX86_BUILTIN_VBROADCASTPD256,
22581 IX86_BUILTIN_VBROADCASTPS256,
22582 IX86_BUILTIN_VINSERTF128PD256,
22583 IX86_BUILTIN_VINSERTF128PS256,
22584 IX86_BUILTIN_VINSERTF128SI256,
22585 IX86_BUILTIN_LOADUPD256,
22586 IX86_BUILTIN_LOADUPS256,
22587 IX86_BUILTIN_STOREUPD256,
22588 IX86_BUILTIN_STOREUPS256,
22589 IX86_BUILTIN_LDDQU256,
22590 IX86_BUILTIN_MOVNTDQ256,
22591 IX86_BUILTIN_MOVNTPD256,
22592 IX86_BUILTIN_MOVNTPS256,
22593 IX86_BUILTIN_LOADDQU256,
22594 IX86_BUILTIN_STOREDQU256,
22595 IX86_BUILTIN_MASKLOADPD,
22596 IX86_BUILTIN_MASKLOADPS,
22597 IX86_BUILTIN_MASKSTOREPD,
22598 IX86_BUILTIN_MASKSTOREPS,
22599 IX86_BUILTIN_MASKLOADPD256,
22600 IX86_BUILTIN_MASKLOADPS256,
22601 IX86_BUILTIN_MASKSTOREPD256,
22602 IX86_BUILTIN_MASKSTOREPS256,
22603 IX86_BUILTIN_MOVSHDUP256,
22604 IX86_BUILTIN_MOVSLDUP256,
22605 IX86_BUILTIN_MOVDDUP256,
22607 IX86_BUILTIN_SQRTPD256,
22608 IX86_BUILTIN_SQRTPS256,
22609 IX86_BUILTIN_SQRTPS_NR256,
22610 IX86_BUILTIN_RSQRTPS256,
22611 IX86_BUILTIN_RSQRTPS_NR256,
22613 IX86_BUILTIN_RCPPS256,
22615 IX86_BUILTIN_ROUNDPD256,
22616 IX86_BUILTIN_ROUNDPS256,
22618 IX86_BUILTIN_UNPCKHPD256,
22619 IX86_BUILTIN_UNPCKLPD256,
22620 IX86_BUILTIN_UNPCKHPS256,
22621 IX86_BUILTIN_UNPCKLPS256,
22623 IX86_BUILTIN_SI256_SI,
22624 IX86_BUILTIN_PS256_PS,
22625 IX86_BUILTIN_PD256_PD,
22626 IX86_BUILTIN_SI_SI256,
22627 IX86_BUILTIN_PS_PS256,
22628 IX86_BUILTIN_PD_PD256,
22630 IX86_BUILTIN_VTESTZPD,
22631 IX86_BUILTIN_VTESTCPD,
22632 IX86_BUILTIN_VTESTNZCPD,
22633 IX86_BUILTIN_VTESTZPS,
22634 IX86_BUILTIN_VTESTCPS,
22635 IX86_BUILTIN_VTESTNZCPS,
22636 IX86_BUILTIN_VTESTZPD256,
22637 IX86_BUILTIN_VTESTCPD256,
22638 IX86_BUILTIN_VTESTNZCPD256,
22639 IX86_BUILTIN_VTESTZPS256,
22640 IX86_BUILTIN_VTESTCPS256,
22641 IX86_BUILTIN_VTESTNZCPS256,
22642 IX86_BUILTIN_PTESTZ256,
22643 IX86_BUILTIN_PTESTC256,
22644 IX86_BUILTIN_PTESTNZC256,
22646 IX86_BUILTIN_MOVMSKPD256,
22647 IX86_BUILTIN_MOVMSKPS256,
22649 /* TFmode support builtins. */
22650 IX86_BUILTIN_INFQ,
22651 IX86_BUILTIN_HUGE_VALQ,
22652 IX86_BUILTIN_FABSQ,
22653 IX86_BUILTIN_COPYSIGNQ,
22655 /* Vectorizer support builtins. */
22656 IX86_BUILTIN_CPYSGNPS,
22657 IX86_BUILTIN_CPYSGNPD,
22659 IX86_BUILTIN_CVTUDQ2PS,
22661 IX86_BUILTIN_VEC_PERM_V2DF,
22662 IX86_BUILTIN_VEC_PERM_V4SF,
22663 IX86_BUILTIN_VEC_PERM_V2DI,
22664 IX86_BUILTIN_VEC_PERM_V4SI,
22665 IX86_BUILTIN_VEC_PERM_V8HI,
22666 IX86_BUILTIN_VEC_PERM_V16QI,
22667 IX86_BUILTIN_VEC_PERM_V2DI_U,
22668 IX86_BUILTIN_VEC_PERM_V4SI_U,
22669 IX86_BUILTIN_VEC_PERM_V8HI_U,
22670 IX86_BUILTIN_VEC_PERM_V16QI_U,
22671 IX86_BUILTIN_VEC_PERM_V4DF,
22672 IX86_BUILTIN_VEC_PERM_V8SF,
22674 /* FMA4 and XOP instructions. */
22675 IX86_BUILTIN_VFMADDSS,
22676 IX86_BUILTIN_VFMADDSD,
22677 IX86_BUILTIN_VFMADDPS,
22678 IX86_BUILTIN_VFMADDPD,
22679 IX86_BUILTIN_VFMSUBSS,
22680 IX86_BUILTIN_VFMSUBSD,
22681 IX86_BUILTIN_VFMSUBPS,
22682 IX86_BUILTIN_VFMSUBPD,
22683 IX86_BUILTIN_VFMADDSUBPS,
22684 IX86_BUILTIN_VFMADDSUBPD,
22685 IX86_BUILTIN_VFMSUBADDPS,
22686 IX86_BUILTIN_VFMSUBADDPD,
22687 IX86_BUILTIN_VFNMADDSS,
22688 IX86_BUILTIN_VFNMADDSD,
22689 IX86_BUILTIN_VFNMADDPS,
22690 IX86_BUILTIN_VFNMADDPD,
22691 IX86_BUILTIN_VFNMSUBSS,
22692 IX86_BUILTIN_VFNMSUBSD,
22693 IX86_BUILTIN_VFNMSUBPS,
22694 IX86_BUILTIN_VFNMSUBPD,
22695 IX86_BUILTIN_VFMADDPS256,
22696 IX86_BUILTIN_VFMADDPD256,
22697 IX86_BUILTIN_VFMSUBPS256,
22698 IX86_BUILTIN_VFMSUBPD256,
22699 IX86_BUILTIN_VFMADDSUBPS256,
22700 IX86_BUILTIN_VFMADDSUBPD256,
22701 IX86_BUILTIN_VFMSUBADDPS256,
22702 IX86_BUILTIN_VFMSUBADDPD256,
22703 IX86_BUILTIN_VFNMADDPS256,
22704 IX86_BUILTIN_VFNMADDPD256,
22705 IX86_BUILTIN_VFNMSUBPS256,
22706 IX86_BUILTIN_VFNMSUBPD256,
22708 IX86_BUILTIN_VPCMOV,
22709 IX86_BUILTIN_VPCMOV_V2DI,
22710 IX86_BUILTIN_VPCMOV_V4SI,
22711 IX86_BUILTIN_VPCMOV_V8HI,
22712 IX86_BUILTIN_VPCMOV_V16QI,
22713 IX86_BUILTIN_VPCMOV_V4SF,
22714 IX86_BUILTIN_VPCMOV_V2DF,
22715 IX86_BUILTIN_VPCMOV256,
22716 IX86_BUILTIN_VPCMOV_V4DI256,
22717 IX86_BUILTIN_VPCMOV_V8SI256,
22718 IX86_BUILTIN_VPCMOV_V16HI256,
22719 IX86_BUILTIN_VPCMOV_V32QI256,
22720 IX86_BUILTIN_VPCMOV_V8SF256,
22721 IX86_BUILTIN_VPCMOV_V4DF256,
22723 IX86_BUILTIN_VPPERM,
22725 IX86_BUILTIN_VPMACSSWW,
22726 IX86_BUILTIN_VPMACSWW,
22727 IX86_BUILTIN_VPMACSSWD,
22728 IX86_BUILTIN_VPMACSWD,
22729 IX86_BUILTIN_VPMACSSDD,
22730 IX86_BUILTIN_VPMACSDD,
22731 IX86_BUILTIN_VPMACSSDQL,
22732 IX86_BUILTIN_VPMACSSDQH,
22733 IX86_BUILTIN_VPMACSDQL,
22734 IX86_BUILTIN_VPMACSDQH,
22735 IX86_BUILTIN_VPMADCSSWD,
22736 IX86_BUILTIN_VPMADCSWD,
22738 IX86_BUILTIN_VPHADDBW,
22739 IX86_BUILTIN_VPHADDBD,
22740 IX86_BUILTIN_VPHADDBQ,
22741 IX86_BUILTIN_VPHADDWD,
22742 IX86_BUILTIN_VPHADDWQ,
22743 IX86_BUILTIN_VPHADDDQ,
22744 IX86_BUILTIN_VPHADDUBW,
22745 IX86_BUILTIN_VPHADDUBD,
22746 IX86_BUILTIN_VPHADDUBQ,
22747 IX86_BUILTIN_VPHADDUWD,
22748 IX86_BUILTIN_VPHADDUWQ,
22749 IX86_BUILTIN_VPHADDUDQ,
22750 IX86_BUILTIN_VPHSUBBW,
22751 IX86_BUILTIN_VPHSUBWD,
22752 IX86_BUILTIN_VPHSUBDQ,
22754 IX86_BUILTIN_VPROTB,
22755 IX86_BUILTIN_VPROTW,
22756 IX86_BUILTIN_VPROTD,
22757 IX86_BUILTIN_VPROTQ,
22758 IX86_BUILTIN_VPROTB_IMM,
22759 IX86_BUILTIN_VPROTW_IMM,
22760 IX86_BUILTIN_VPROTD_IMM,
22761 IX86_BUILTIN_VPROTQ_IMM,
22763 IX86_BUILTIN_VPSHLB,
22764 IX86_BUILTIN_VPSHLW,
22765 IX86_BUILTIN_VPSHLD,
22766 IX86_BUILTIN_VPSHLQ,
22767 IX86_BUILTIN_VPSHAB,
22768 IX86_BUILTIN_VPSHAW,
22769 IX86_BUILTIN_VPSHAD,
22770 IX86_BUILTIN_VPSHAQ,
22772 IX86_BUILTIN_VFRCZSS,
22773 IX86_BUILTIN_VFRCZSD,
22774 IX86_BUILTIN_VFRCZPS,
22775 IX86_BUILTIN_VFRCZPD,
22776 IX86_BUILTIN_VFRCZPS256,
22777 IX86_BUILTIN_VFRCZPD256,
22779 IX86_BUILTIN_VPCOMEQUB,
22780 IX86_BUILTIN_VPCOMNEUB,
22781 IX86_BUILTIN_VPCOMLTUB,
22782 IX86_BUILTIN_VPCOMLEUB,
22783 IX86_BUILTIN_VPCOMGTUB,
22784 IX86_BUILTIN_VPCOMGEUB,
22785 IX86_BUILTIN_VPCOMFALSEUB,
22786 IX86_BUILTIN_VPCOMTRUEUB,
22788 IX86_BUILTIN_VPCOMEQUW,
22789 IX86_BUILTIN_VPCOMNEUW,
22790 IX86_BUILTIN_VPCOMLTUW,
22791 IX86_BUILTIN_VPCOMLEUW,
22792 IX86_BUILTIN_VPCOMGTUW,
22793 IX86_BUILTIN_VPCOMGEUW,
22794 IX86_BUILTIN_VPCOMFALSEUW,
22795 IX86_BUILTIN_VPCOMTRUEUW,
22797 IX86_BUILTIN_VPCOMEQUD,
22798 IX86_BUILTIN_VPCOMNEUD,
22799 IX86_BUILTIN_VPCOMLTUD,
22800 IX86_BUILTIN_VPCOMLEUD,
22801 IX86_BUILTIN_VPCOMGTUD,
22802 IX86_BUILTIN_VPCOMGEUD,
22803 IX86_BUILTIN_VPCOMFALSEUD,
22804 IX86_BUILTIN_VPCOMTRUEUD,
22806 IX86_BUILTIN_VPCOMEQUQ,
22807 IX86_BUILTIN_VPCOMNEUQ,
22808 IX86_BUILTIN_VPCOMLTUQ,
22809 IX86_BUILTIN_VPCOMLEUQ,
22810 IX86_BUILTIN_VPCOMGTUQ,
22811 IX86_BUILTIN_VPCOMGEUQ,
22812 IX86_BUILTIN_VPCOMFALSEUQ,
22813 IX86_BUILTIN_VPCOMTRUEUQ,
22815 IX86_BUILTIN_VPCOMEQB,
22816 IX86_BUILTIN_VPCOMNEB,
22817 IX86_BUILTIN_VPCOMLTB,
22818 IX86_BUILTIN_VPCOMLEB,
22819 IX86_BUILTIN_VPCOMGTB,
22820 IX86_BUILTIN_VPCOMGEB,
22821 IX86_BUILTIN_VPCOMFALSEB,
22822 IX86_BUILTIN_VPCOMTRUEB,
22824 IX86_BUILTIN_VPCOMEQW,
22825 IX86_BUILTIN_VPCOMNEW,
22826 IX86_BUILTIN_VPCOMLTW,
22827 IX86_BUILTIN_VPCOMLEW,
22828 IX86_BUILTIN_VPCOMGTW,
22829 IX86_BUILTIN_VPCOMGEW,
22830 IX86_BUILTIN_VPCOMFALSEW,
22831 IX86_BUILTIN_VPCOMTRUEW,
22833 IX86_BUILTIN_VPCOMEQD,
22834 IX86_BUILTIN_VPCOMNED,
22835 IX86_BUILTIN_VPCOMLTD,
22836 IX86_BUILTIN_VPCOMLED,
22837 IX86_BUILTIN_VPCOMGTD,
22838 IX86_BUILTIN_VPCOMGED,
22839 IX86_BUILTIN_VPCOMFALSED,
22840 IX86_BUILTIN_VPCOMTRUED,
22842 IX86_BUILTIN_VPCOMEQQ,
22843 IX86_BUILTIN_VPCOMNEQ,
22844 IX86_BUILTIN_VPCOMLTQ,
22845 IX86_BUILTIN_VPCOMLEQ,
22846 IX86_BUILTIN_VPCOMGTQ,
22847 IX86_BUILTIN_VPCOMGEQ,
22848 IX86_BUILTIN_VPCOMFALSEQ,
22849 IX86_BUILTIN_VPCOMTRUEQ,
22851 /* LWP instructions. */
22852 IX86_BUILTIN_LLWPCB,
22853 IX86_BUILTIN_SLWPCB,
22854 IX86_BUILTIN_LWPVAL32,
22855 IX86_BUILTIN_LWPVAL64,
22856 IX86_BUILTIN_LWPINS32,
22857 IX86_BUILTIN_LWPINS64,
22859 IX86_BUILTIN_CLZS,
22861 /* FSGSBASE instructions. */
22862 IX86_BUILTIN_RDFSBASE32,
22863 IX86_BUILTIN_RDFSBASE64,
22864 IX86_BUILTIN_RDGSBASE32,
22865 IX86_BUILTIN_RDGSBASE64,
22866 IX86_BUILTIN_WRFSBASE32,
22867 IX86_BUILTIN_WRFSBASE64,
22868 IX86_BUILTIN_WRGSBASE32,
22869 IX86_BUILTIN_WRGSBASE64,
22871 /* RDRND instructions. */
22872 IX86_BUILTIN_RDRAND16,
22873 IX86_BUILTIN_RDRAND32,
22874 IX86_BUILTIN_RDRAND64,
22876 /* F16C instructions. */
22877 IX86_BUILTIN_CVTPH2PS,
22878 IX86_BUILTIN_CVTPH2PS256,
22879 IX86_BUILTIN_CVTPS2PH,
22880 IX86_BUILTIN_CVTPS2PH256,
22882 IX86_BUILTIN_MAX
22883 };
22885 /* Table for the ix86 builtin decls. */
22888 /* Table of all of the builtin functions that are possible with different ISA's
22889 but are waiting to be built until a function is declared to use that
22890 ISA. */
22897 };
22902 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
22903 of which isa_flags to use in the ix86_builtins_isa array. Stores the
22904 function decl in the ix86_builtins array. Returns the function decl or
22905 NULL_TREE, if the builtin was not added.
22907 If the front end has a special hook for builtin functions, delay adding
22908 builtin functions that aren't in the current ISA until the ISA is changed
22909 with function specific optimization. Doing so, can save about 300K for the
22910 default compiler. When the builtin is expanded, check at that time whether
22911 it is valid.
22913 If the front end doesn't have a special hook, record all builtins, even if
22914 it isn't an instruction set in the current ISA in case the user uses
22915 function specific options for a different ISA, so that we don't get scope
22916 errors if a builtin is added in the middle of a function scope. */
22921 {
22925 {
22934 {
22940 }
22941 else
22942 {
22948 }
22949 }
22952 }
22954 /* Like def_builtin, but also marks the function decl "const". */
22959 {
22963 else
22967 }
22969 /* Add any new builtin functions for a given ISA that may not have been
22970 declared. This saves a bit of space compared to adding all of the
22971 declarations to the tree, even if we didn't use them. */
22973 static void
22975 {
22979 {
22982 {
22985 /* Don't define the builtin again. */
22991 NULL_TREE);
22996 }
22997 }
22998 }
23000 /* Bits for builtin_description.flag. */
23002 /* Set when we don't support the comparison natively, and should
23003 swap_comparison in order to support it. */
23004 #define BUILTIN_DESC_SWAP_OPERANDS 1
23006 struct builtin_description
23007 {
23014 };
23017 {
23018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
23019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
23020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
23021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
23022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
23023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
23024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
23025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
23026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
23027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
23028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
23029 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
23030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
23031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
23032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
23033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
23034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
23035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
23036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
23037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
23038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
23039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
23040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
23041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
23042 };
23045 {
23046 /* SSE4.2 */
23047 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
23048 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
23049 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
23050 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
23051 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
23052 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
23053 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
23054 };
23057 {
23058 /* SSE4.2 */
23059 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
23060 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
23061 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
23062 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
23063 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
23064 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
23065 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
23066 };
23068 /* Special builtins with variable number of arguments. */
23070 {
23071 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
23072 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
23074 /* MMX */
23075 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
23077 /* 3DNow! */
23078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
23080 /* SSE */
23081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
23082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
23083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
23085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
23086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
23087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
23088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
23090 /* SSE or 3DNow!A */
23091 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
23092 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
23094 /* SSE2 */
23095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
23096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
23097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
23098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
23099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
23100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
23101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
23102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
23103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
23105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
23106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
23108 /* SSE3 */
23109 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
23111 /* SSE4.1 */
23112 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
23114 /* SSE4A */
23115 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
23116 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
23118 /* AVX */
23119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
23120 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
23122 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
23123 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
23124 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
23125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
23126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
23128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
23129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
23130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
23131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
23132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
23133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
23134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
23136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
23137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
23138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
23140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
23141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
23142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
23143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
23144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
23145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
23146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
23147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
23149 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
23150 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
23151 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
23152 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
23153 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
23154 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
23156 /* FSGSBASE */
23157 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
23158 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
23159 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
23160 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
23161 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
23162 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
23163 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
23164 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
23166 /* RDRND */
23167 { OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandhi, "__builtin_ia32_rdrand16", IX86_BUILTIN_RDRAND16, UNKNOWN, (int) UINT16_FTYPE_VOID },
23168 { OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandsi, "__builtin_ia32_rdrand32", IX86_BUILTIN_RDRAND32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
23169 { OPTION_MASK_ISA_RDRND | OPTION_MASK_ISA_64BIT, CODE_FOR_rdranddi, "__builtin_ia32_rdrand64", IX86_BUILTIN_RDRAND64, UNKNOWN, (int) UINT64_FTYPE_VOID },
23170 };
23172 /* Builtins with variable number of arguments. */
23174 {
23175 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
23176 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
23177 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
23178 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
23179 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
23180 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
23181 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
23183 /* MMX */
23184 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23185 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23186 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23187 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23188 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23189 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23191 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23192 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23193 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23194 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23196 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23197 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23198 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23200 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23201 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23203 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23204 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23205 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23206 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23208 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23209 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23210 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23211 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23212 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23213 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23218 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
23220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
23222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
23223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
23224 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
23226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
23228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
23229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
23230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
23231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
23232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
23233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
23235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
23236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
23237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
23238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
23239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
23240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
23242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
23243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
23244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
23245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
23247 /* 3DNow! */
23248 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
23249 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
23250 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
23251 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
23253 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23254 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23255 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23256 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
23257 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
23258 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
23259 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23260 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23261 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23262 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23263 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23264 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23265 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23266 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23267 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23269 /* 3DNow!A */
23270 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
23271 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
23272 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
23273 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
23274 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23275 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
23277 /* SSE */
23278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
23279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23280 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23282 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
23285 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
23286 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
23287 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
23288 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
23289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
23291 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23293 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23294 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23295 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23296 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23297 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23298 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23299 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23300 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
23303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
23304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
23305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
23306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
23307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
23308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
23309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
23310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
23311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
23312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
23313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
23314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
23315 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
23316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
23317 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
23318 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
23319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
23320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
23321 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
23322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
23323 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
23325 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23326 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23327 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23330 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23331 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23332 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23333 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23335 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23337 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23340 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23341 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23343 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
23344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
23345 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
23347 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
23349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
23350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
23351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
23353 /* SSE MMX or 3Dnow!A */
23354 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23355 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23356 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23358 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23359 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23360 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23361 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23363 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
23364 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
23366 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
23368 /* SSE2 */
23369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23371 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
23372 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
23373 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
23374 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
23375 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
23376 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
23377 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
23378 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
23379 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
23380 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
23381 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
23382 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
23384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
23385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
23386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
23387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
23388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
23389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
23391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
23392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
23393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
23394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
23395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
23397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
23399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
23400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
23401 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
23402 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
23404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
23405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
23406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
23408 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23409 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23410 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23411 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
23418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
23419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
23420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
23421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
23422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
23423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
23424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
23425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
23426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
23427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
23428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
23429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
23430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
23431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
23432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
23433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
23434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
23435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
23436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
23438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23439 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23443 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23445 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23446 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23448 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23451 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23452 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23454 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
23456 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23457 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23458 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23459 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23460 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23461 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23462 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23463 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23474 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23475 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
23477 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23479 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23480 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23492 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23493 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23494 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23497 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23498 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23499 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23500 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23501 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23502 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23503 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23504 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
23507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
23508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
23510 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
23513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
23514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
23516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
23518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
23519 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
23520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
23521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
23523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
23524 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
23525 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
23526 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
23527 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
23528 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
23529 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
23531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
23532 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
23533 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
23534 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
23535 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
23536 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
23537 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
23539 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
23540 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
23541 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
23542 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
23544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
23545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
23546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
23548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
23550 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
23551 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
23553 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
23555 /* SSE2 MMX */
23556 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
23557 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
23559 /* SSE3 */
23560 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
23561 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
23563 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23564 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23565 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23566 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23567 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
23568 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
23570 /* SSSE3 */
23571 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
23572 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
23573 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
23574 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
23575 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
23576 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
23578 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23579 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23580 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23581 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23582 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23583 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23584 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23585 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23586 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23587 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23588 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23589 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23590 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
23591 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
23592 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23593 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23594 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23595 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23596 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23597 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
23598 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23599 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
23600 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23601 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
23603 /* SSSE3. */
23604 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
23605 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
23607 /* SSE4.1 */
23608 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23609 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23610 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
23611 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
23612 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23613 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23614 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23615 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
23616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
23617 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
23619 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
23620 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
23621 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
23622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
23623 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
23624 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
23625 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
23626 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
23627 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
23628 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
23629 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
23630 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
23631 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
23633 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
23634 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23635 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23636 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23637 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23638 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23639 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
23640 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23641 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23642 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
23643 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
23644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
23646 /* SSE4.1 */
23647 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
23648 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
23649 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23650 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23652 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
23653 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
23654 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
23656 /* SSE4.2 */
23657 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23658 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
23659 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
23660 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
23661 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
23663 /* SSE4A */
23664 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
23665 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
23666 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
23667 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23669 /* AES */
23670 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
23671 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
23673 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23674 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23675 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23676 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
23678 /* PCLMUL */
23679 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
23681 /* AVX */
23682 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23683 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23686 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23687 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23690 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23696 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23697 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23698 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23699 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23700 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23701 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23702 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23703 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23704 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23705 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23706 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23707 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
23710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
23711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
23712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
23714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
23715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
23716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
23717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
23718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
23719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
23720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
23721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
23724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
23725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
23726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
23727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
23728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
23729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
23730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
23731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
23732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
23733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
23734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
23735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
23736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
23737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
23738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
23739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
23740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
23741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
23742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
23743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
23744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
23745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
23746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
23747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
23749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
23753 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
23754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23755 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23757 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
23761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
23762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
23764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
23766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
23769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
23770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
23771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
23772 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
23773 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
23774 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
23776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
23777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
23778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
23779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
23780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
23781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
23782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
23783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
23784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
23785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
23786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
23787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
23788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
23789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
23790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
23792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
23793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
23795 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
23797 /* F16C */
23798 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
23799 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
23800 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
23801 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
23802 };
23804 /* FMA4 and XOP. */
23805 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
23806 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
23807 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
23808 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
23809 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
23810 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
23811 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
23812 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
23813 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
23814 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
23815 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
23816 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
23817 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
23818 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
23819 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
23820 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
23821 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
23822 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
23823 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
23824 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
23825 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
23826 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
23827 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
23828 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
23829 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
23830 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
23831 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
23832 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
23833 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
23834 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
23835 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
23836 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
23837 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
23838 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
23839 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
23840 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
23841 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
23842 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
23843 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
23844 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
23845 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
23846 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
23847 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
23848 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
23849 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
23850 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
23851 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
23852 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
23853 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
23854 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
23855 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
23856 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
23859 {
23860 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
23861 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
23862 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23863 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23864 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
23865 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
23866 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23867 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23869 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
23870 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
23871 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23872 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23873 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
23874 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
23875 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23876 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23878 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23879 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23880 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
23881 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
23883 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23884 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23885 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23886 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23888 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23889 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23890 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23891 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23893 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23894 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23895 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23896 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23898 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
23899 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
23900 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
23901 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
23902 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
23903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
23904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
23906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
23907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
23908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
23909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
23910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
23911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
23912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
23914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
23916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
23917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
23918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
23919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
23920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
23921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
23922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
23923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
23924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
23925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
23926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
23927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
23929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
23930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
23931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
23932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
23933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
23934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
23935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
23936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
23937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
23938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
23939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
23940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
23941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
23942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
23943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
23944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
23946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
23947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
23948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
23949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
23950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
23951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
23953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
23954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
23955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
23956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
23957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
23958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
23959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
23960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
23961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
23962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
23963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
23964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
23965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
23966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
23967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
23969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
23970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
23971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
23972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
23973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
23974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
23975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
23977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
23978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
23979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
23980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
23981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
23982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
23983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
23985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
23986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
23987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
23988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
23989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
23990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
23991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
23993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
23994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
23995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
23996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
23997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
23998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
23999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
24001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
24002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
24003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
24004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
24005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
24006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
24007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
24009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
24010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
24011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
24012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
24013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
24014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
24015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
24017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
24018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
24019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
24020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
24021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
24022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
24023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
24025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
24026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
24027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
24028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
24029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
24030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
24031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
24033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
24034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
24035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
24036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
24037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
24038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
24039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
24040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
24042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
24043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
24044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
24045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
24046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
24047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
24048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
24049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
24051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
24052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
24053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
24054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
24056 };
24058 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
24059 in the current target ISA to allow the user to compile particular modules
24060 with different target specific options that differ from the command line
24061 options. */
24062 static void
24064 {
24069 /* Add all special builtins with variable number of operands. */
24073 {
24079 }
24081 /* Add all builtins with variable number of operands. */
24085 {
24091 }
24093 /* pcmpestr[im] insns. */
24097 {
24100 else
24103 }
24105 /* pcmpistr[im] insns. */
24109 {
24112 else
24115 }
24117 /* comi/ucomi insns. */
24119 {
24122 else
24125 }
24127 /* SSE */
24133 /* SSE or 3DNow!A */
24136 IX86_BUILTIN_MASKMOVQ);
24138 /* SSE2 */
24147 /* SSE3. */
24153 /* AES */
24167 /* PCLMUL */
24171 /* MMX access to the vec_init patterns. */
24176 V4HI_FTYPE_HI_HI_HI_HI,
24177 IX86_BUILTIN_VEC_INIT_V4HI);
24180 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
24181 IX86_BUILTIN_VEC_INIT_V8QI);
24183 /* Access to the vec_extract patterns. */
24205 /* Access to the vec_set patterns. */
24226 /* Add FMA4 multi-arg argument instructions */
24228 {
24234 }
24235 }
24237 /* Internal method for ix86_init_builtins. */
24239 static void
24241 {
24253 sysv_va_ref =
24256 fnvoid_va_end_ms =
24258 fnvoid_va_start_ms =
24260 fnvoid_va_end_sysv =
24262 fnvoid_va_start_sysv =
24264 NULL_TREE);
24265 fnvoid_va_copy_ms =
24267 NULL_TREE);
24268 fnvoid_va_copy_sysv =
24284 }
24286 static void
24288 {
24291 /* The __float80 type. */
24294 {
24295 /* The __float80 type. */
24300 }
24303 /* The __float128 type. */
24309 /* This macro is built by i386-builtin-types.awk. */
24310 DEFINE_BUILTIN_PRIMITIVE_TYPES;
24311 }
24313 static void
24315 {
24316 tree t;
24320 /* TFmode support builtins. */
24326 /* We will expand them to normal call if SSE2 isn't available since
24327 they are used by libgcc. */
24344 }
24346 /* Return the ix86 builtin for CODE. */
24348 static tree
24350 {
24355 }
24357 /* Errors in the source file can cause expand_expr to return const0_rtx
24358 where we expect a vector. To avoid crashing, use one of the vector
24359 clear instructions. */
24360 static rtx
24362 {
24366 }
24368 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
24370 static rtx
24372 {
24373 rtx pat;
24393 {
24397 }
24411 }
24413 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
24415 static rtx
24419 {
24420 rtx pat;
24428 rtx op;
24435 {
24515 }
24525 {
24532 {
24534 {
24537 }
24538 }
24539 else
24540 {
24544 /* If we aren't optimizing, only allow one memory operand to be
24545 generated. */
24547 num_memory++;
24555 }
24559 }
24562 {
24573 else
24574 {
24580 }
24593 }
24600 }
24602 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24603 insns with vec_merge. */
24605 static rtx
24607 rtx target)
24608 {
24609 rtx pat;
24636 }
24638 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24640 static rtx
24643 {
24644 rtx pat;
24649 rtx op2;
24660 /* Swap operands if we have a comparison that isn't available in
24661 hardware. */
24663 {
24668 }
24688 }
24690 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24692 static rtx
24694 rtx target)
24695 {
24696 rtx pat;
24710 /* Swap operands if we have a comparison that isn't available in
24711 hardware. */
24713 {
24717 }
24738 const0_rtx)));
24741 }
24743 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24745 static rtx
24747 rtx target)
24748 {
24749 rtx pat;
24782 const0_rtx)));
24785 }
24787 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24789 static rtx
24792 {
24793 rtx pat;
24831 {
24834 }
24837 {
24846 }
24848 {
24857 }
24858 else
24859 {
24866 }
24874 {
24879 emit_insn
24883 FLAGS_REG),
24884 const0_rtx)));
24886 }
24887 else
24889 }
24892 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24894 static rtx
24897 {
24898 rtx pat;
24926 {
24929 }
24932 {
24941 }
24943 {
24952 }
24953 else
24954 {
24961 }
24969 {
24974 emit_insn
24978 FLAGS_REG),
24979 const0_rtx)));
24981 }
24982 else
24984 }
24986 /* Subroutine of ix86_expand_builtin to take care of insns with
24987 variable number of operands. */
24989 static rtx
24992 {
24997 struct
24998 {
24999 rtx op;
25011 {
25226 }
25231 {
25234 }
25237 {
25244 }
25245 else
25246 {
25249 }
25252 {
25259 {
25260 /* SIMD shift insns take either an 8-bit immediate or
25261 register as count. But builtin functions take int as
25262 count. If count doesn't match, we put it in register. */
25264 {
25268 }
25269 }
25271 {
25274 {
25316 {
25319 {
25322 }
25328 }
25330 }
25331 }
25332 else
25333 {
25337 /* If we aren't optimizing, only allow one memory operand to
25338 be generated. */
25340 num_memory++;
25343 {
25346 }
25347 else
25348 {
25351 }
25352 }
25356 }
25359 {
25376 }
25383 }
25385 /* Subroutine of ix86_expand_builtin to take care of special insns
25386 with variable number of operands. */
25388 static rtx
25391 {
25392 tree arg;
25395 struct
25396 {
25397 rtx op;
25407 {
25453 /* Reserve memory operand for target. */
25476 /* Reserve memory operand for target. */
25490 }
25495 {
25501 else
25504 }
25505 else
25506 {
25513 }
25516 {
25525 {
25527 {
25533 else
25536 }
25537 }
25538 else
25539 {
25541 {
25542 /* This must be the memory operand. */
25546 }
25547 else
25548 {
25549 /* This must be register. */
25556 }
25557 }
25561 }
25564 {
25579 }
25585 }
25587 /* Return the integer constant in ARG. Constrain it to be in the range
25588 of the subparts of VEC_TYPE; issue an error if not. */
25590 static int
25592 {
25597 {
25600 }
25603 }
25605 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25606 ix86_expand_vector_init. We DO have language-level syntax for this, in
25607 the form of (type){ init-list }. Except that since we can't place emms
25608 instructions from inside the compiler, we can't allow the use of MMX
25609 registers unless the user explicitly asks for it. So we do *not* define
25610 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25611 we have builtins invoked by mmintrin.h that gives us license to emit
25612 these sorts of instructions. */
25614 static rtx
25616 {
25626 {
25629 }
25636 }
25638 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25639 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25640 had a language-level syntax for referencing vector elements. */
25642 static rtx
25644 {
25648 rtx op0;
25668 }
25670 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25671 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25672 a language-level syntax for referencing vector elements. */
25674 static rtx
25676 {
25700 /* OP0 is the source of these builtin functions and shouldn't be
25701 modified. Create a copy, use it and return it as target. */
25707 }
25709 /* Expand an expression EXP that calls a built-in function,
25710 with result going to TARGET if that's convenient
25711 (and in mode MODE if that's convenient).
25712 SUBTARGET may be used as the target for computing one of EXP's operands.
25713 IGNORE is nonzero if the value is to be ignored. */
25715 static rtx
25719 {
25729 /* Determine whether the builtin function is available under the current ISA.
25730 Originally the builtin was not created if it wasn't applicable to the
25731 current ISA based on the command line switches. With function specific
25732 options, we need to check in the context of the function making the call
25733 whether it is supported. */
25736 {
25742 else
25743 {
25747 }
25749 }
25752 {
25756 ? CODE_FOR_mmx_maskmovq
25758 /* Note the arg order is different from the operand order. */
25873 {
25874 REAL_VALUE_TYPE inf;
25875 rtx tmp;
25887 }
25908 }
25921 {
25925 /* Emit a normal call if SSE2 isn't available. */
25929 }
25954 }
25956 /* Returns a function decl for a vectorized version of the builtin function
25957 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25958 if it is not available. */
25960 static tree
25962 tree type_in)
25963 {
25979 {
26017 ;
26018 }
26020 /* Dispatch to a handler for a vectorization library. */
26023 type_in);
26026 }
26028 /* Handler for an SVML-style interface to
26029 a library with vectorized intrinsics. */
26031 static tree
26033 {
26041 /* The SVML is suitable for unsafe math only. */
26054 {
26101 }
26110 {
26113 }
26114 else
26117 /* Convert to uppercase. */
26123 arity++;
26127 else
26130 /* Build a function declaration for the vectorized function. */
26139 }
26141 /* Handler for an ACML-style interface to
26142 a library with vectorized intrinsics. */
26144 static tree
26146 {
26154 /* The ACML is 64bits only and suitable for unsafe math only as
26155 it does not correctly support parts of IEEE with the required
26156 precision such as denormals. */
26170 {
26200 }
26208 arity++;
26212 else
26215 /* Build a function declaration for the vectorized function. */
26224 }
26227 /* Returns a decl of a function that implements conversion of an integer vector
26228 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
26229 are the types involved when converting according to CODE.
26230 Return NULL_TREE if it is not available. */
26232 static tree
26235 {
26240 {
26243 {
26246 {
26253 ? NULL_TREE
26257 }
26261 {
26264 ? NULL_TREE
26268 }
26272 }
26276 {
26279 {
26282 ? NULL_TREE
26286 ? NULL_TREE
26290 }
26295 {
26298 ? NULL_TREE
26302 }
26307 }
26311 }
26314 }
26316 /* Returns a code for a target-specific builtin that implements
26317 reciprocal of the function, or NULL_TREE if not available. */
26319 static tree
26322 {
26329 /* Machine dependent builtins. */
26331 {
26332 /* Vectorized version of sqrt to rsqrt conversion. */
26338 }
26339 else
26340 /* Normal builtins. */
26342 {
26343 /* Sqrt to rsqrt conversion. */
26349 }
26350 }
26351 \f
26352 /* Helper for avx_vpermilps256_operand et al. This is also used by
26353 the expansion functions to turn the parallel back into a mask.
26354 The return value is 0 for no match and the imm8+1 for a match. */
26356 int
26358 {
26366 /* Validate that all of the elements are constants, and not totally
26367 out of range. Copy the data into an integral array to make the
26368 subsequent checks easier. */
26370 {
26380 }
26383 {
26385 /* In the 256-bit DFmode case, we can only move elements within
26386 a 128-bit lane. */
26388 {
26392 }
26394 {
26398 }
26402 /* In the 256-bit SFmode case, we have full freedom of movement
26403 within the low 128-bit lane, but the high 128-bit lane must
26404 mirror the exact same pattern. */
26409 /* FALLTHRU */
26413 /* In the 128-bit case, we've full freedom in the placement of
26414 the elements from the source operand. */
26421 }
26423 /* Make sure success has a non-zero value by adding one. */
26425 }
26427 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
26428 the expansion functions to turn the parallel back into a mask.
26429 The return value is 0 for no match and the imm8+1 for a match. */
26431 int
26433 {
26441 /* Validate that all of the elements are constants, and not totally
26442 out of range. Copy the data into an integral array to make the
26443 subsequent checks easier. */
26445 {
26455 }
26457 /* Validate that the halves of the permute are halves. */
26465 /* Reconstruct the mask. */
26467 {
26473 }
26475 /* Make sure success has a non-zero value by adding one. */
26477 }
26478 \f
26480 /* Store OPERAND to the memory after reload is completed. This means
26481 that we can't easily use assign_stack_local. */
26482 rtx
26484 {
26485 rtx result;
26489 {
26492 stack_pointer_rtx,
26495 }
26497 {
26499 {
26503 /* FALLTHRU */
26509 stack_pointer_rtx)),
26510 operand));
26514 }
26516 }
26517 else
26518 {
26520 {
26522 {
26529 stack_pointer_rtx)),
26535 stack_pointer_rtx)),
26537 }
26540 /* Store HImodes as SImodes. */
26542 /* FALLTHRU */
26548 stack_pointer_rtx)),
26549 operand));
26553 }
26555 }
26557 }
26559 /* Free operand from the memory. */
26560 void
26562 {
26564 {
26569 else
26571 /* Use LEA to deallocate stack space. In peephole2 it will be converted
26572 to pop or add instruction if registers are available. */
26576 }
26577 }
26579 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
26580 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
26581 same. */
26584 {
26587 };
26590 };
26593 }
26595 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
26596 QImode must go into class Q_REGS.
26597 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
26598 movdf to do mem-to-mem moves through integer regs. */
26599 enum reg_class
26601 {
26604 /* We're only allowed to return a subclass of CLASS. Many of the
26605 following checks fail for NO_REGS, so eliminate that early. */
26609 /* All classes can load zeros. */
26613 /* Force constants into memory if we are loading a (nonzero) constant into
26614 an MMX or SSE register. This is because there are no MMX/SSE instructions
26615 to load from a constant. */
26620 /* Prefer SSE regs only, if we can use them for math. */
26624 /* Floating-point constants need more complex checks. */
26626 {
26627 /* General regs can load everything. */
26631 /* Floats can load 0 and 1 plus some others. Note that we eliminated
26632 zero above. We only want to wind up preferring 80387 registers if
26633 we plan on doing computation with them. */
26636 {
26637 /* Limit class to non-sse. */
26646 }
26649 }
26651 /* Generally when we see PLUS here, it's the function invariant
26652 (plus soft-fp const_int). Which can only be computed into general
26653 regs. */
26657 /* QImode constants are easy to load, but non-constant QImode data
26658 must go into Q_REGS. */
26660 {
26666 }
26669 }
26671 /* Discourage putting floating-point values in SSE registers unless
26672 SSE math is being used, and likewise for the 387 registers. */
26673 enum reg_class
26675 {
26678 /* Restrict the output reload class to the register bank that we are doing
26679 math on. If we would like not to return a subset of CLASS, reject this
26680 alternative: if reload cannot do this, it will still use its choice. */
26686 {
26691 else
26693 }
26696 }
26698 static reg_class_t
26702 {
26703 /* QImode spills from non-QI registers require
26704 intermediate register on 32bit targets. */
26709 {
26714 else
26720 /* Return Q_REGS if the operand is in memory. */
26723 }
26726 }
26728 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
26730 static bool
26732 {
26734 {
26749 }
26752 }
26754 /* If we are copying between general and FP registers, we need a memory
26755 location. The same is true for SSE and MMX registers.
26757 To optimize register_move_cost performance, allow inline variant.
26759 The macro can't work reliably when one of the CLASSES is class containing
26760 registers from multiple units (SSE, MMX, integer). We avoid this by never
26761 combining those units in single alternative in the machine description.
26762 Ensure that this constraint holds to avoid unexpected surprises.
26764 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
26765 enforce these sanity checks. */
26770 {
26777 {
26780 }
26785 /* ??? This is a lie. We do have moves between mmx/general, and for
26786 mmx/sse2. But by saying we need secondary memory we discourage the
26787 register allocator from using the mmx registers unless needed. */
26792 {
26793 /* SSE1 doesn't have any direct moves from other classes. */
26797 /* If the target says that inter-unit moves are more expensive
26798 than moving through memory, then don't generate them. */
26802 /* Between SSE and general, we have moves no larger than word size. */
26805 }
26808 }
26810 bool
26813 {
26815 }
26817 /* Return true if the registers in CLASS cannot represent the change from
26818 modes FROM to TO. */
26820 bool
26823 {
26827 /* x87 registers can't do subreg at all, as all values are reformatted
26828 to extended precision. */
26833 {
26834 /* Vector registers do not support QI or HImode loads. If we don't
26835 disallow a change to these modes, reload will assume it's ok to
26836 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26837 the vec_dupv4hi pattern. */
26841 /* Vector registers do not support subreg with nonzero offsets, which
26842 are otherwise valid for integer registers. Since we can't see
26843 whether we have a nonzero offset from here, prohibit all
26844 nonparadoxical subregs changing size. */
26847 }
26850 }
26852 /* Return the cost of moving data of mode M between a
26853 register and memory. A value of 2 is the default; this cost is
26854 relative to those in `REGISTER_MOVE_COST'.
26856 This function is used extensively by register_move_cost that is used to
26857 build tables at startup. Make it inline in this case.
26858 When IN is 2, return maximum of in and out move cost.
26860 If moving between registers and memory is more expensive than
26861 between two registers, you should define this macro to express the
26862 relative cost.
26864 Model also increased moving costs of QImode registers in non
26865 Q_REGS classes.
26866 */
26870 {
26873 {
26876 {
26888 }
26892 }
26894 {
26897 {
26909 }
26913 }
26915 {
26918 {
26927 }
26931 }
26933 {
26936 {
26942 else
26947 }
26948 else
26949 {
26954 else
26956 }
26963 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26970 else
26974 }
26975 }
26977 static int
26980 {
26982 }
26985 /* Return the cost of moving data from a register in class CLASS1 to
26986 one in class CLASS2.
26988 It is not required that the cost always equal 2 when FROM is the same as TO;
26989 on some machines it is expensive to move between registers if they are not
26990 general registers. */
26992 static int
26994 reg_class_t class2_i)
26995 {
26999 /* In case we require secondary memory, compute cost of the store followed
27000 by load. In order to avoid bad register allocation choices, we need
27001 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
27004 {
27010 /* In case of copying from general_purpose_register we may emit multiple
27011 stores followed by single load causing memory size mismatch stall.
27012 Count this as arbitrarily high cost of 20. */
27016 /* In the case of FP/MMX moves, the registers actually overlap, and we
27017 have to switch modes in order to treat them differently. */
27023 }
27025 /* Moves between SSE/MMX and integer unit are expensive. */
27029 /* ??? By keeping returned value relatively high, we limit the number
27030 of moves between integer and MMX/SSE registers for all targets.
27031 Additionally, high value prevents problem with x86_modes_tieable_p(),
27032 where integer modes in MMX/SSE registers are not tieable
27033 because of missing QImode and HImode moves to, from or between
27034 MMX/SSE registers. */
27044 }
27046 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
27048 bool
27050 {
27051 /* Flags and only flags can only hold CCmode values. */
27061 {
27062 /* We implement the move patterns for all vector modes into and
27063 out of SSE registers, even when no operation instructions
27064 are available. OImode move is available only when AVX is
27065 enabled. */
27072 }
27074 {
27075 /* We implement the move patterns for 3DNOW modes even in MMX mode,
27076 so if the register is available at all, then we can move data of
27077 the given mode into or out of it. */
27080 }
27083 {
27084 /* Take care for QImode values - they can be in non-QI regs,
27085 but then they do cause partial register stalls. */
27091 }
27092 /* We handle both integer and floats in the general purpose registers. */
27099 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
27100 on to use that value in smaller contexts, this can easily force a
27101 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
27102 supporting DImode, allow it. */
27107 }
27109 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
27110 tieable integer mode. */
27112 static bool
27114 {
27116 {
27129 }
27130 }
27132 /* Return true if MODE1 is accessible in a register that can hold MODE2
27133 without copying. That is, all register classes that can hold MODE2
27134 can also hold MODE1. */
27136 bool
27138 {
27146 /* MODE2 being XFmode implies fp stack or general regs, which means we
27147 can tie any smaller floating point modes to it. Note that we do not
27148 tie this with TFmode. */
27152 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
27153 that we can tie it with SFmode. */
27157 /* If MODE2 is only appropriate for an SSE register, then tie with
27158 any other mode acceptable to SSE registers. */
27164 /* If MODE2 is appropriate for an MMX register, then tie
27165 with any other mode acceptable to MMX registers. */
27172 }
27174 /* Compute a (partial) cost for rtx X. Return true if the complete
27175 cost has been computed, and false if subexpressions should be
27176 scanned. In either case, *TOTAL contains the cost result. */
27178 static bool
27180 {
27186 {
27196 && (!TARGET_64BIT
27201 else
27208 else
27210 {
27219 /* Start with (MEM (SYMBOL_REF)), since that's where
27220 it'll probably end up. Add a penalty for size. */
27225 }
27229 /* The zero extensions is often completely free on x86_64, so make
27230 it as cheap as possible. */
27236 else
27247 {
27250 {
27253 }
27256 {
27259 }
27260 }
27261 /* FALLTHRU */
27268 {
27270 {
27273 else
27275 }
27276 else
27277 {
27280 else
27282 }
27283 }
27284 else
27285 {
27288 else
27290 }
27295 {
27296 /* ??? SSE scalar cost should be used here. */
27299 }
27301 {
27304 }
27306 {
27307 /* ??? SSE vector cost should be used here. */
27310 }
27311 else
27312 {
27317 {
27320 nbits++;
27321 }
27322 else
27323 /* This is arbitrary. */
27326 /* Compute costs correctly for widening multiplication. */
27330 {
27337 {
27341 else
27343 }
27347 }
27354 }
27361 /* ??? SSE cost should be used here. */
27366 /* ??? SSE vector cost should be used here. */
27368 else
27375 {
27380 {
27383 {
27390 }
27391 }
27394 {
27397 {
27402 }
27403 }
27405 {
27411 }
27412 }
27413 /* FALLTHRU */
27417 {
27418 /* ??? SSE cost should be used here. */
27421 }
27423 {
27426 }
27428 {
27429 /* ??? SSE vector cost should be used here. */
27432 }
27433 /* FALLTHRU */
27439 {
27446 }
27447 /* FALLTHRU */
27451 {
27452 /* ??? SSE cost should be used here. */
27455 }
27457 {
27460 }
27462 {
27463 /* ??? SSE vector cost should be used here. */
27466 }
27467 /* FALLTHRU */
27472 else
27481 {
27482 /* This kind of construct is implemented using test[bwl].
27483 Treat it as if we had an AND. */
27488 }
27498 /* ??? SSE cost should be used here. */
27503 /* ??? SSE vector cost should be used here. */
27509 /* ??? SSE cost should be used here. */
27514 /* ??? SSE vector cost should be used here. */
27527 /* ??? Assume all of these vector manipulation patterns are
27528 recognizable. In which case they all pretty much have the
27529 same cost. */
27535 }
27536 }
27538 #if TARGET_MACHO
27542 /* Given a symbol name and its associated stub, write out the
27543 definition of the stub. */
27545 void
27547 {
27552 /* For 64-bit we shouldn't get here. */
27555 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27570 else
27577 {
27581 }
27582 else
27588 {
27591 }
27592 else
27601 }
27604 /* Order the registers for register allocator. */
27606 void
27608 {
27612 /* First allocate the local general purpose registers. */
27617 /* Global general purpose registers. */
27622 /* x87 registers come first in case we are doing FP math
27623 using them. */
27628 /* SSE registers. */
27634 /* x87 registers. */
27642 /* Initialize the rest of array as we do not allocate some registers
27643 at all. */
27646 }
27648 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
27649 struct attribute_spec.handler. */
27650 static tree
27652 tree args ATTRIBUTE_UNUSED,
27654 {
27659 {
27661 name);
27664 }
27666 {
27668 name);
27671 }
27673 /* Can combine regparm with all attributes but fastcall. */
27675 {
27677 {
27679 }
27682 }
27684 {
27686 {
27688 }
27691 }
27694 }
27696 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27697 struct attribute_spec.handler. */
27698 static tree
27700 tree args ATTRIBUTE_UNUSED,
27702 {
27705 {
27708 }
27709 else
27714 {
27716 name);
27718 }
27724 {
27726 name);
27728 }
27731 }
27733 static tree
27735 tree args ATTRIBUTE_UNUSED,
27737 {
27739 {
27741 name);
27743 }
27745 }
27747 static bool
27749 {
27753 }
27755 /* Returns an expression indicating where the this parameter is
27756 located on entry to the FUNCTION. */
27758 static rtx
27760 {
27766 {
27771 else
27774 }
27779 {
27785 {
27790 }
27791 else
27792 {
27795 {
27800 }
27801 }
27803 }
27806 }
27808 /* Determine whether x86_output_mi_thunk can succeed. */
27810 static bool
27812 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27814 {
27815 /* 64-bit can handle anything. */
27819 /* For 32-bit, everything's fine if we have one free register. */
27823 /* Need a free register for vcall_offset. */
27827 /* Need a free register for GOT references. */
27831 /* Otherwise ok. */
27833 }
27835 /* Output the assembler code for a thunk function. THUNK_DECL is the
27836 declaration for the thunk function itself, FUNCTION is the decl for
27837 the target function. DELTA is an immediate constant offset to be
27838 added to THIS. If VCALL_OFFSET is nonzero, the word at
27839 *(*this + vcall_offset) should be added to THIS. */
27841 static void
27845 {
27850 /* Make sure unwind info is emitted for the thunk if needed. */
27853 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27854 pull it in now and let DELTA benefit. */
27858 {
27859 /* Put the this parameter into %eax. */
27863 }
27864 else
27867 /* Adjust the this parameter by a fixed constant. */
27869 {
27873 {
27875 {
27881 }
27884 else
27886 }
27889 else
27891 }
27893 /* Adjust the this parameter by a value stored in the vtable. */
27895 {
27898 else
27899 {
27907 }
27913 /* Adjust the this parameter. */
27916 {
27922 }
27925 }
27927 /* If necessary, drop THIS back to its stack slot. */
27929 {
27933 }
27937 {
27940 /* All thunks should be in the same object as their target,
27941 and thus binds_local_p should be true. */
27944 else
27945 {
27951 }
27952 }
27953 else
27954 {
27957 else
27958 #if TARGET_MACHO
27960 {
27963 sym_ref = (gen_rtx_SYMBOL_REF
27969 }
27970 else
27972 {
27979 }
27980 }
27982 }
27984 static void
27986 {
27988 #if TARGET_MACHO
27990 #endif
27997 }
27999 int
28001 {
28013 }
28015 /* Output assembler code to FILE to increment profiler label # LABELNO
28016 for profiling a function entry. */
28017 void
28019 {
28024 {
28025 #ifndef NO_PROFILE_COUNTERS
28027 #endif
28031 else
28033 }
28035 {
28036 #ifndef NO_PROFILE_COUNTERS
28039 #endif
28041 }
28042 else
28043 {
28044 #ifndef NO_PROFILE_COUNTERS
28047 #endif
28049 }
28050 }
28052 /* We don't have exact information about the insn sizes, but we may assume
28053 quite safely that we are informed about all 1 byte insns and memory
28054 address sizes. This is enough to eliminate unnecessary padding in
28055 99% of cases. */
28057 static int
28059 {
28065 /* Discard alignments we've emit and jump instructions. */
28072 /* Important case - calls are always 5 bytes.
28073 It is common to have many calls in the row. */
28082 /* For normal instructions we rely on get_attr_length being exact,
28083 with a few exceptions. */
28085 {
28089 {
28099 /* Otherwise trust get_attr_length. */
28101 }
28106 }
28109 else
28111 }
28113 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
28115 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
28116 window. */
28118 static void
28120 {
28125 /* Look for all minimal intervals of instructions containing 4 jumps.
28126 The intervals are bounded by START and INSN. NBYTES is the total
28127 size of instructions in the interval including INSN and not including
28128 START. When the NBYTES is smaller than 16 bytes, it is possible
28129 that the end of START and INSN ends up in the same 16byte page.
28131 The smallest offset in the page INSN can start is the case where START
28132 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
28133 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
28134 */
28136 {
28140 {
28146 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
28147 already in the current 16 byte page, because otherwise
28148 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
28149 bytes to reach 16 byte boundary. */
28157 {
28159 {
28166 else
28169 }
28170 }
28172 }
28183 njumps++;
28184 else
28188 {
28195 else
28198 }
28205 {
28212 }
28213 }
28214 }
28215 #endif
28217 /* AMD Athlon works faster
28218 when RET is not destination of conditional jump or directly preceded
28219 by other jump instruction. We avoid the penalty by inserting NOP just
28220 before the RET instructions in such cases. */
28221 static void
28223 {
28224 edge e;
28225 edge_iterator ei;
28228 {
28231 rtx prev;
28241 {
28242 edge e;
28243 edge_iterator ei;
28249 }
28251 {
28257 /* Empty functions get branch mispredict even when the jump destination
28258 is not visible to us. */
28261 }
28263 {
28266 }
28267 }
28268 }
28270 /* Count the minimum number of instructions in BB. Return 4 if the
28271 number of instructions >= 4. */
28273 static int
28275 {
28276 rtx insn;
28279 /* Count number of instructions in this block. Return 4 if the number
28280 of instructions >= 4. */
28282 {
28283 /* Only happen in exit blocks. */
28291 {
28292 insn_count++;
28295 }
28296 }
28299 }
28302 /* Count the minimum number of instructions in code path in BB.
28303 Return 4 if the number of instructions >= 4. */
28305 static int
28307 {
28308 edge e;
28309 edge_iterator ei;
28312 /* Only bother counting instructions along paths with no
28313 more than 2 basic blocks between entry and exit. Given
28314 that BB has an edge to exit, determine if a predecessor
28315 of BB has an edge from entry. If so, compute the number
28316 of instructions in the predecessor block. If there
28317 happen to be multiple such blocks, compute the minimum. */
28320 {
28321 edge prev_e;
28322 edge_iterator prev_ei;
28325 {
28328 }
28330 {
28332 {
28337 }
28338 }
28339 }
28345 }
28347 /* Pad short funtion to 4 instructions. */
28349 static void
28351 {
28352 edge e;
28353 edge_iterator ei;
28356 {
28359 {
28362 /* Pad short function. */
28364 {
28367 /* Find epilogue. */
28376 /* Two NOPs are counted as one instruction. */
28379 }
28380 }
28381 }
28382 }
28384 /* Implement machine specific optimizations. We implement padding of returns
28385 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
28386 static void
28388 {
28390 {
28395 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
28398 #endif
28399 }
28400 }
28402 /* Return nonzero when QImode register that must be represented via REX prefix
28403 is used. */
28404 bool
28406 {
28414 }
28416 /* Return nonzero when P points to register encoded via REX prefix.
28417 Called via for_each_rtx. */
28418 static int
28420 {
28426 }
28428 /* Return true when INSN mentions register that must be encoded using REX
28429 prefix. */
28430 bool
28432 {
28435 }
28437 /* If profitable, negate (without causing overflow) integer constant
28438 of mode MODE at location LOC. Return true in this case. */
28439 bool
28441 {
28442 HOST_WIDE_INT val;
28448 {
28450 /* DImode x86_64 constants must fit in 32 bits. */
28463 }
28465 /* Avoid overflows. */
28471 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
28472 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
28475 {
28478 }
28481 }
28483 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
28484 optabs would emit if we didn't have TFmode patterns. */
28486 void
28488 {
28522 }
28523 \f
28524 /* AVX does not support 32-byte integer vector operations,
28525 thus the longest vector we are faced with is V16QImode. */
28526 #define MAX_VECT_LEN 16
28528 struct expand_vec_perm_d
28529 {
28535 };
28540 /* Get a vector mode of the same size as the original but with elements
28541 twice as wide. This is only guaranteed to apply to integral vectors. */
28545 {
28546 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
28551 }
28553 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28554 with all elements equal to VAR. Return true if successful. */
28556 static bool
28559 {
28563 {
28568 /* FALLTHRU */
28578 {
28581 /* First attempt to recognize VAL as-is. */
28585 {
28586 rtx seq;
28587 /* If that fails, force VAL into a register. */
28598 }
28599 }
28606 {
28607 rtx x;
28614 }
28624 {
28628 permute:
28635 /* Extend to SImode using a paradoxical SUBREG. */
28639 /* Insert the SImode value as low element of a V4SImode vector. */
28647 }
28655 widen:
28656 /* Replicate the value once into the next wider mode and recurse. */
28657 {
28659 rtx x;
28675 }
28679 {
28688 }
28693 }
28694 }
28696 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28697 whose ONE_VAR element is VAR, and other elements are zero. Return true
28698 if successful. */
28700 static bool
28703 {
28705 rtx new_target;
28710 {
28712 /* For SSE4.1, we normally use vector set. But if the second
28713 element is zero and inter-unit moves are OK, we use movq
28714 instead. */
28715 use_vector_set = (TARGET_64BIT
28716 && TARGET_SSE4_1
28717 && !(TARGET_INTER_UNIT_MOVES
28739 /* Use ix86_expand_vector_set in 64bit mode only. */
28744 }
28747 {
28752 }
28755 {
28760 /* FALLTHRU */
28775 else
28782 {
28783 /* We need to shuffle the value to the correct position, so
28784 create a new pseudo to store the intermediate result. */
28786 /* With SSE2, we can use the integer shuffle insns. */
28788 {
28790 const1_rtx,
28797 }
28799 /* Otherwise convert the intermediate result to V4SFmode and
28800 use the SSE1 shuffle instructions. */
28802 {
28805 }
28806 else
28810 const1_rtx,
28819 }
28834 widen:
28838 /* Zero extend the variable element to SImode and recurse. */
28851 }
28852 }
28854 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28855 consisting of the values in VALS. It is known that all elements
28856 except ONE_VAR are constants. Return true if successful. */
28858 static bool
28861 {
28871 {
28876 /* For the two element vectors, it's just as easy to use
28877 the general case. */
28881 /* Use ix86_expand_vector_set in 64bit mode only. */
28903 widen:
28904 /* There's no way to set one QImode entry easily. Combine
28905 the variable value with its adjacent constant value, and
28906 promote to an HImode set. */
28909 {
28914 }
28915 else
28916 {
28919 }
28933 }
28938 }
28940 /* A subroutine of ix86_expand_vector_init_general. Use vector
28941 concatenate to handle the most general case: all values variable,
28942 and none identical. */
28944 static void
28947 {
28950 rtvec v;
28954 {
28957 {
28990 }
29003 {
29018 }
29023 {
29034 }
29037 half:
29038 /* FIXME: We process inputs backward to help RA. PR 36222. */
29042 {
29047 }
29051 {
29054 {
29058 }
29061 }
29062 else
29068 }
29069 }
29071 /* A subroutine of ix86_expand_vector_init_general. Use vector
29072 interleave to handle the most general case: all values variable,
29073 and none identical. */
29075 static void
29078 {
29087 {
29108 }
29111 {
29112 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
29116 /* Insert the SImode value as low element of V4SImode vector. */
29120 op0),
29122 const1_rtx);
29125 /* Cast the V4SImode vector back to a vector in orignal mode. */
29129 /* Load even elements into the second positon. */
29133 const1_rtx));
29135 /* Cast vector to FIRST_IMODE vector. */
29138 }
29140 /* Interleave low FIRST_IMODE vectors. */
29142 {
29146 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
29149 }
29151 /* Interleave low SECOND_IMODE vectors. */
29153 {
29156 {
29161 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
29162 vector. */
29165 }
29168 /* FALLTHRU */
29175 /* Cast the SECOND_IMODE vector back to a vector on original
29176 mode. */
29183 }
29184 }
29186 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
29187 all values variable, and none identical. */
29189 static void
29192 {
29198 {
29203 /* FALLTHRU */
29227 half:
29244 /* FALLTHRU */
29250 /* Don't use ix86_expand_vector_init_interleave if we can't
29251 move from GPR to SSE register directly. */
29267 }
29269 {
29281 {
29285 {
29291 else
29292 {
29297 }
29298 }
29301 }
29306 {
29312 }
29314 {
29320 }
29321 else
29323 }
29324 }
29326 /* Initialize vector TARGET via VALS. Suppress the use of MMX
29327 instructions unless MMX_OK is true. */
29329 void
29331 {
29338 rtx x;
29341 {
29351 }
29353 /* Constants are best loaded from the constant pool. */
29355 {
29358 }
29360 /* If all values are identical, broadcast the value. */
29366 /* Values where only one field is non-constant are best loaded from
29367 the pool and overwritten via move later. */
29369 {
29373 one_var))
29378 }
29381 }
29383 void
29385 {
29390 rtx tmp;
29392 = {
29399 };
29401 = {
29408 };
29412 {
29416 {
29421 else
29425 }
29434 {
29437 /* For the two element vectors, we implement a VEC_CONCAT with
29438 the extraction of the other element. */
29445 else
29450 }
29459 {
29465 /* tmp = target = A B C D */
29467 /* target = A A B B */
29469 /* target = X A B B */
29471 /* target = A X C D */
29478 /* tmp = target = A B C D */
29480 /* tmp = X B C D */
29482 /* target = A B X D */
29489 /* tmp = target = A B C D */
29491 /* tmp = X B C D */
29493 /* target = A B X D */
29501 }
29509 /* Element 0 handled by vec_merge below. */
29511 {
29514 }
29517 {
29518 /* With SSE2, use integer shuffles to swap element 0 and ELT,
29519 store into element 0, then shuffle them back. */
29536 }
29537 else
29538 {
29539 /* For SSE1, we have to reuse the V4SF code. */
29542 }
29595 half:
29596 /* Compute offset. */
29602 /* Extract the half. */
29606 /* Put val in tmp at elt. */
29609 /* Put it back. */
29615 }
29618 {
29622 }
29623 else
29624 {
29633 }
29634 }
29636 void
29638 {
29642 rtx tmp;
29645 {
29650 /* FALLTHRU */
29663 {
29683 }
29695 {
29697 {
29717 }
29721 }
29722 else
29723 {
29724 /* For SSE1, we have to reuse the V4SF code. */
29728 }
29743 /* ??? Could extract the appropriate HImode element and shift. */
29746 }
29749 {
29753 /* Let the rtl optimizers know about the zero extension performed. */
29755 {
29758 }
29761 }
29762 else
29763 {
29770 }
29771 }
29773 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
29774 pattern to reduce; DEST is the destination; IN is the input vector. */
29776 void
29778 {
29792 }
29793 \f
29794 /* Target hook for scalar_mode_supported_p. */
29795 static bool
29797 {
29802 else
29804 }
29806 /* Implements target hook vector_mode_supported_p. */
29807 static bool
29809 {
29821 }
29823 /* Target hook for c_mode_for_suffix. */
29824 static enum machine_mode
29826 {
29833 }
29835 /* Worker function for TARGET_MD_ASM_CLOBBERS.
29837 We do this in the new i386 backend to maintain source compatibility
29838 with the old cc0-based compiler. */
29840 static tree
29842 tree inputs ATTRIBUTE_UNUSED,
29843 tree clobbers)
29844 {
29846 clobbers);
29848 clobbers);
29850 }
29852 /* Implements target vector targetm.asm.encode_section_info. This
29853 is not used by netware. */
29855 static void ATTRIBUTE_UNUSED
29857 {
29864 }
29866 /* Worker function for REVERSE_CONDITION. */
29868 enum rtx_code
29870 {
29874 }
29876 /* Output code to perform an x87 FP register move, from OPERANDS[1]
29877 to OPERANDS[0]. */
29881 {
29883 {
29886 {
29890 }
29894 }
29896 {
29900 else
29901 {
29902 /* There is no non-popping store to memory for XFmode.
29903 So if we need one, follow the store with a load. */
29906 else
29908 }
29909 }
29910 else
29912 }
29914 /* Output code to perform a conditional jump to LABEL, if C2 flag in
29915 FP status register is set. */
29917 void
29919 {
29921 rtx temp;
29926 {
29931 }
29932 else
29933 {
29938 }
29942 pc_rtx);
29947 }
29949 /* Output code to perform a log1p XFmode calculation. */
29952 {
29958 rtx test;
29964 XFmode));
29978 }
29980 /* Output code to perform a Newton-Rhapson approximation of a single precision
29981 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
29984 {
29999 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
30001 /* x0 = rcp(b) estimate */
30004 UNSPEC_RCP)));
30005 /* e0 = x0 * a */
30008 /* e1 = x0 * b */
30011 /* x1 = 2. - e1 */
30014 /* res = e0 * x1 */
30017 }
30019 /* Output code to perform a Newton-Rhapson approximation of a
30020 single precision floating point [reciprocal] square root. */
30024 {
30026 REAL_VALUE_TYPE r;
30041 {
30044 }
30046 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
30047 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
30049 /* x0 = rsqrt(a) estimate */
30052 UNSPEC_RSQRT)));
30054 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
30056 {
30068 }
30070 /* e0 = x0 * a */
30073 /* e1 = e0 * x0 */
30077 /* e2 = e1 - 3. */
30084 /* e3 = -.5 * x0 */
30087 else
30088 /* e3 = -.5 * e0 */
30091 /* ret = e2 * e3 */
30094 }
30096 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
30098 static void ATTRIBUTE_UNUSED
30100 tree decl)
30101 {
30102 /* With Binutils 2.15, the "@unwind" marker must be specified on
30103 every occurrence of the ".eh_frame" section, not just the first
30104 one. */
30107 {
30111 }
30113 }
30115 /* Return the mangling of TYPE if it is an extended fundamental type. */
30119 {
30127 {
30129 /* __float128 is "g". */
30132 /* "long double" or __float80 is "e". */
30136 }
30137 }
30139 /* For 32-bit code we can save PIC register setup by using
30140 __stack_chk_fail_local hidden function instead of calling
30141 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
30142 register, so it is better to call __stack_chk_fail directly. */
30144 static tree
30146 {
30147 return TARGET_64BIT
30150 }
30152 /* Select a format to encode pointers in exception handling data. CODE
30153 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
30154 true if the symbol may be affected by dynamic relocations.
30156 ??? All x86 object file formats are capable of representing this.
30157 After all, the relocation needed is the same as for the call insn.
30158 Whether or not a particular assembler allows us to enter such, I
30159 guess we'll have to see. */
30160 int
30162 {
30164 {
30171 }
30176 }
30177 \f
30178 /* Expand copysign from SIGN to the positive value ABS_VALUE
30179 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
30180 the sign-bit. */
30181 static void
30183 {
30187 {
30190 {
30191 /* We need to generate a scalar mode mask in this case. */
30196 }
30197 }
30198 else
30204 }
30206 /* Expand fabs (OP0) and return a new rtx that holds the result. The
30207 mask for masking out the sign-bit is stored in *SMASK, if that is
30208 non-null. */
30209 static rtx
30211 {
30218 {
30219 /* We need to generate a scalar mode mask in this case. */
30224 }
30232 }
30234 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
30235 swapping the operands if SWAP_OPERANDS is true. The expanded
30236 code is a forward jump to a newly created label in case the
30237 comparison is true. The generated label rtx is returned. */
30238 static rtx
30241 {
30245 {
30249 }
30262 }
30264 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
30265 using comparison code CODE. Operands are swapped for the comparison if
30266 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
30267 static rtx
30270 {
30275 {
30279 }
30284 else
30289 }
30291 /* Generate and return a rtx of mode MODE for 2**n where n is the number
30292 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
30293 static rtx
30295 {
30296 REAL_VALUE_TYPE TWO52r;
30297 rtx TWO52;
30304 }
30306 /* Expand SSE sequence for computing lround from OP1 storing
30307 into OP0. */
30308 void
30310 {
30311 /* C code for the stuff we're doing below:
30312 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
30313 return (long)tmp;
30314 */
30318 rtx adj;
30320 /* load nextafter (0.5, 0.0) */
30325 /* adj = copysign (0.5, op1) */
30329 /* adj = op1 + adj */
30332 /* op0 = (imode)adj */
30334 }
30336 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
30337 into OPERAND0. */
30338 void
30340 {
30341 /* C code for the stuff we're doing below (for do_floor):
30342 xi = (long)op1;
30343 xi -= (double)xi > op1 ? 1 : 0;
30344 return xi;
30345 */
30350 /* reg = (long)op1 */
30354 /* freg = (double)reg */
30358 /* ireg = (freg > op1) ? ireg - 1 : ireg */
30369 }
30371 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
30372 result in OPERAND0. */
30373 void
30375 {
30376 /* C code for the stuff we're doing below:
30377 xa = fabs (operand1);
30378 if (!isless (xa, 2**52))
30379 return operand1;
30380 xa = xa + 2**52 - 2**52;
30381 return copysign (xa, operand1);
30382 */
30389 /* xa = abs (operand1) */
30392 /* if (!isless (xa, TWO52)) goto label; */
30405 }
30407 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
30408 into OPERAND0. */
30409 void
30411 {
30412 /* C code for the stuff we expand below.
30413 double xa = fabs (x), x2;
30414 if (!isless (xa, TWO52))
30415 return x;
30416 xa = xa + TWO52 - TWO52;
30417 x2 = copysign (xa, x);
30418 Compensate. Floor:
30419 if (x2 > x)
30420 x2 -= 1;
30421 Compensate. Ceil:
30422 if (x2 < x)
30423 x2 -= -1;
30424 return x2;
30425 */
30431 /* Temporary for holding the result, initialized to the input
30432 operand to ease control flow. */
30436 /* xa = abs (operand1) */
30439 /* if (!isless (xa, TWO52)) goto label; */
30442 /* xa = xa + TWO52 - TWO52; */
30446 /* xa = copysign (xa, operand1) */
30449 /* generate 1.0 or -1.0 */
30454 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
30458 /* We always need to subtract here to preserve signed zero. */
30467 }
30469 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
30470 into OPERAND0. */
30471 void
30473 {
30474 /* C code for the stuff we expand below.
30475 double xa = fabs (x), x2;
30476 if (!isless (xa, TWO52))
30477 return x;
30478 x2 = (double)(long)x;
30479 Compensate. Floor:
30480 if (x2 > x)
30481 x2 -= 1;
30482 Compensate. Ceil:
30483 if (x2 < x)
30484 x2 += 1;
30485 if (HONOR_SIGNED_ZEROS (mode))
30486 return copysign (x2, x);
30487 return x2;
30488 */
30494 /* Temporary for holding the result, initialized to the input
30495 operand to ease control flow. */
30499 /* xa = abs (operand1) */
30502 /* if (!isless (xa, TWO52)) goto label; */
30505 /* xa = (double)(long)x */
30510 /* generate 1.0 */
30513 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
30528 }
30530 /* Expand SSE sequence for computing round from OPERAND1 storing
30531 into OPERAND0. Sequence that works without relying on DImode truncation
30532 via cvttsd2siq that is only available on 64bit targets. */
30533 void
30535 {
30536 /* C code for the stuff we expand below.
30537 double xa = fabs (x), xa2, x2;
30538 if (!isless (xa, TWO52))
30539 return x;
30540 Using the absolute value and copying back sign makes
30541 -0.0 -> -0.0 correct.
30542 xa2 = xa + TWO52 - TWO52;
30543 Compensate.
30544 dxa = xa2 - xa;
30545 if (dxa <= -0.5)
30546 xa2 += 1;
30547 else if (dxa > 0.5)
30548 xa2 -= 1;
30549 x2 = copysign (xa2, x);
30550 return x2;
30551 */
30557 /* Temporary for holding the result, initialized to the input
30558 operand to ease control flow. */
30562 /* xa = abs (operand1) */
30565 /* if (!isless (xa, TWO52)) goto label; */
30568 /* xa2 = xa + TWO52 - TWO52; */
30572 /* dxa = xa2 - xa; */
30575 /* generate 0.5, 1.0 and -0.5 */
30581 /* Compensate. */
30583 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
30588 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
30594 /* res = copysign (xa2, operand1) */
30601 }
30603 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30604 into OPERAND0. */
30605 void
30607 {
30608 /* C code for SSE variant we expand below.
30609 double xa = fabs (x), x2;
30610 if (!isless (xa, TWO52))
30611 return x;
30612 x2 = (double)(long)x;
30613 if (HONOR_SIGNED_ZEROS (mode))
30614 return copysign (x2, x);
30615 return x2;
30616 */
30622 /* Temporary for holding the result, initialized to the input
30623 operand to ease control flow. */
30627 /* xa = abs (operand1) */
30630 /* if (!isless (xa, TWO52)) goto label; */
30633 /* x = (double)(long)x */
30645 }
30647 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30648 into OPERAND0. */
30649 void
30651 {
30655 /* C code for SSE variant we expand below.
30656 double xa = fabs (x), x2;
30657 if (!isless (xa, TWO52))
30658 return x;
30659 xa2 = xa + TWO52 - TWO52;
30660 Compensate:
30661 if (xa2 > xa)
30662 xa2 -= 1.0;
30663 x2 = copysign (xa2, x);
30664 return x2;
30665 */
30669 /* Temporary for holding the result, initialized to the input
30670 operand to ease control flow. */
30674 /* xa = abs (operand1) */
30677 /* if (!isless (xa, TWO52)) goto label; */
30680 /* res = xa + TWO52 - TWO52; */
30685 /* generate 1.0 */
30688 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
30696 /* res = copysign (res, operand1) */
30703 }
30705 /* Expand SSE sequence for computing round from OPERAND1 storing
30706 into OPERAND0. */
30707 void
30709 {
30710 /* C code for the stuff we're doing below:
30711 double xa = fabs (x);
30712 if (!isless (xa, TWO52))
30713 return x;
30714 xa = (double)(long)(xa + nextafter (0.5, 0.0));
30715 return copysign (xa, x);
30716 */
30722 /* Temporary for holding the result, initialized to the input
30723 operand to ease control flow. */
30731 /* load nextafter (0.5, 0.0) */
30736 /* xa = xa + 0.5 */
30740 /* xa = (double)(int64_t)xa */
30745 /* res = copysign (xa, operand1) */
30752 }
30753 \f
30755 /* Table of valid machine attributes. */
30757 {
30758 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
30759 /* Stdcall attribute says callee is responsible for popping arguments
30760 if they are not variable. */
30762 /* Fastcall attribute says callee is responsible for popping arguments
30763 if they are not variable. */
30765 /* Thiscall attribute says callee is responsible for popping arguments
30766 if they are not variable. */
30768 /* Cdecl attribute says the callee is a normal C declaration */
30770 /* Regparm attribute specifies how many integer arguments are to be
30771 passed in registers. */
30773 /* Sseregparm attribute says we are using x86_64 calling conventions
30774 for FP arguments. */
30776 /* force_align_arg_pointer says this function realigns the stack at entry. */
30779 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30783 #endif
30786 #ifdef SUBTARGET_ATTRIBUTE_TABLE
30787 SUBTARGET_ATTRIBUTE_TABLE,
30788 #endif
30789 /* ms_abi and sysv_abi calling convention function attributes. */
30793 /* End element. */
30795 };
30797 /* Implement targetm.vectorize.builtin_vectorization_cost. */
30798 static int
30800 tree vectype ATTRIBUTE_UNUSED,
30802 {
30804 {
30844 }
30845 }
30848 /* Implement targetm.vectorize.builtin_vec_perm. */
30850 static tree
30852 {
30860 {
30867 get_di:
30878 get_si:
30897 }
30904 }
30906 /* Return a vector mode with twice as many elements as VMODE. */
30907 /* ??? Consider moving this to a table generated by genmodes.c. */
30909 static enum machine_mode
30911 {
30913 {
30936 }
30937 }
30939 /* Construct (set target (vec_select op0 (parallel perm))) and
30940 return true if that's a valid instruction in the active ISA. */
30942 static bool
30944 {
30957 {
30960 }
30962 }
30964 /* Similar, but generate a vec_concat from op0 and op1 as well. */
30966 static bool
30969 {
30971 rtx x;
30976 }
30978 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
30979 in terms of blendp[sd] / pblendw / pblendvb. */
30981 static bool
30983 {
30993 /* This is a blend, not a permute. Elements must stay in their
30994 respective lanes. */
30996 {
31000 }
31005 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
31006 decision should be extracted elsewhere, so that we only try that
31007 sequence once all budget==3 options have been tried. */
31009 /* For bytes, see if bytes move in pairs so we can use pblendw with
31010 an immediate argument, rather than pblendvb with a vector argument. */
31012 {
31018 {
31029 }
31030 }
31038 {
31062 do_subreg:
31071 }
31073 /* This matches five different patterns with the different modes. */
31079 }
31081 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
31082 in terms of the variable form of vpermilps.
31084 Note that we will have already failed the immediate input vpermilps,
31085 which requires that the high and low part shuffle be identical; the
31086 variable form doesn't require that. */
31088 static bool
31090 {
31097 /* We can only permute within the 128-bit lane. */
31099 {
31103 }
31109 {
31112 /* Within each 128-bit lane, the elements of op0 are numbered
31113 from 0 and the elements of op1 are numbered from 4. */
31120 }
31127 }
31129 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
31130 in terms of pshufb or vpperm. */
31132 static bool
31134 {
31150 {
31154 }
31163 else
31164 {
31167 }
31170 }
31172 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
31173 in a single instruction. */
31175 static bool
31177 {
31181 /* Check plain VEC_SELECT first, because AVX has instructions that could
31182 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
31183 input where SEL+CONCAT may not. */
31185 {
31194 /* There are plenty of patterns in sse.md that are written for
31195 SEL+CONCAT and are not replicated for a single op. Perhaps
31196 that should be changed, to avoid the nastiness here. */
31198 /* Recognize interleave style patterns, which means incrementing
31199 every other permutation operand. */
31201 {
31204 }
31208 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
31210 {
31212 {
31217 }
31221 }
31222 }
31224 /* Finally, try the fully general two operand permute. */
31228 /* Recognize interleave style patterns with reversed operands. */
31230 {
31232 {
31236 else
31239 }
31243 }
31245 /* Try the SSE4.1 blend variable merge instructions. */
31249 /* Try one of the AVX vpermil variable permutations. */
31253 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
31258 }
31260 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
31261 in terms of a pair of pshuflw + pshufhw instructions. */
31263 static bool
31265 {
31273 /* The two permutations only operate in 64-bit lanes. */
31284 /* Emit the pshuflw. */
31291 /* Emit the pshufhw. */
31299 }
31301 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
31302 the permutation using the SSSE3 palignr instruction. This succeeds
31303 when all of the elements in PERM fit within one vector and we merely
31304 need to shift them down so that a single vector permutation has a
31305 chance to succeed. */
31307 static bool
31309 {
31313 rtx shift;
31315 /* Even with AVX, palignr only operates on 128-bit vectors. */
31321 {
31327 }
31331 /* Given that we have SSSE3, we know we'll be able to implement the
31332 single operand permutation after the palignr with pshufb. */
31345 {
31350 }
31352 /* Test for the degenerate case where the alignment by itself
31353 produces the desired permutation. */
31361 }
31363 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
31364 a two vector permutation into a single vector permutation by using
31365 an interleave operation to merge the vectors. */
31367 static bool
31369 {
31374 rtx seq;
31380 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
31381 lanes. We can use similar techniques with the vperm2f128 instruction,
31382 but it requires slightly different logic. */
31386 /* Examine from whence the elements come. */
31391 /* Split the two input vectors into 4 halves. */
31400 /* If the elements from the low halves use interleave low, and similarly
31401 for interleave high. If the elements are from mis-matched halves, we
31402 can use shufps for V4SF/V4SI or do a DImode shuffle. */
31404 {
31406 {
31411 }
31412 }
31414 {
31416 {
31421 }
31422 }
31424 {
31426 {
31431 }
31433 {
31438 }
31439 }
31441 {
31443 {
31448 }
31450 {
31455 }
31456 }
31457 else
31460 /* Use the remapping array set up above to move the elements from their
31461 swizzled locations into their final destinations. */
31464 {
31468 }
31473 /* Test if the final remap can be done with a single insn. For V4SFmode or
31474 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
31484 {
31488 }
31495 }
31497 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
31498 permutation with two pshufb insns and an ior. We should have already
31499 failed all two instruction sequences. */
31501 static bool
31503 {
31514 /* Generate two permutation masks. If the required element is within
31515 the given vector it is shuffled into the proper lane. If the required
31516 element is in the other vector, force a zero into the lane by setting
31517 bit 7 in the permutation mask. */
31520 {
31527 {
31530 }
31531 }
31551 }
31553 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
31554 and extract-odd permutations. */
31556 static bool
31558 {
31562 {
31567 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
31571 /* Now an unpck[lh]pd will produce the result required. */
31574 else
31580 {
31590 /* Shuffle within the 128-bit lanes to produce:
31591 { 0 2 1 3 4 6 5 7 } and { 8 a 9 b c e d f }. */
31595 /* Shuffle the lanes around to produce:
31596 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
31600 /* Now a vpermil2p will produce the result required. */
31601 /* ??? The vpermil2p requires a vector constant. Another option
31602 is a unpck[lh]ps to merge the two vectors to produce
31603 { 0 4 2 6 8 c a e } or { 1 5 3 7 9 d b f }. Then use another
31604 vpermilps to get the elements into the final order. */
31609 }
31616 /* These are always directly implementable by expand_vec_perm_1. */
31622 else
31623 {
31624 /* We need 2*log2(N)-1 operations to achieve odd/even
31625 with interleave. */
31634 else
31637 }
31643 else
31644 {
31656 else
31659 }
31664 }
31667 }
31669 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
31670 extract-even and extract-odd permutations. */
31672 static bool
31674 {
31686 }
31688 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
31689 permutations. We assume that expand_vec_perm_1 has already failed. */
31691 static bool
31693 {
31701 {
31704 /* These are special-cased in sse.md so that we can optionally
31705 use the vbroadcast instruction. They expand to two insns
31706 if the input happens to be in a register. */
31713 /* These are always implementable using standard shuffle patterns. */
31718 /* These can be implemented via interleave. We save one insn by
31719 stopping once we have promoted to V4SImode and then use pshufd. */
31720 do
31721 {
31725 {
31728 }
31734 }
31744 }
31745 }
31747 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
31748 broadcast permutations. */
31750 static bool
31752 {
31764 }
31766 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
31767 With all of the interface bits taken care of, perform the expansion
31768 in D and return true on success. */
31770 static bool
31772 {
31773 /* Try a single instruction expansion. */
31777 /* Try sequences of two instructions. */
31791 /* Try sequences of three instructions. */
31796 /* ??? Look for narrow permutations whose element orderings would
31797 allow the promotion to a wider mode. */
31799 /* ??? Look for sequences of interleave or a wider permute that place
31800 the data into the correct lanes for a half-vector shuffle like
31801 pshuf[lh]w or vpermilps. */
31803 /* ??? Look for sequences of interleave that produce the desired results.
31804 The combinatorics of punpck[lh] get pretty ugly... */
31810 }
31812 /* Extract the values from the vector CST into the permutation array in D.
31813 Return 0 on error, 1 if all values from the permutation come from the
31814 first vector, 2 if all values from the second vector, and 3 otherwise. */
31816 static int
31818 {
31824 {
31835 }
31838 /* For all elements from second vector, fold the elements to first. */
31844 }
31846 static rtx
31848 {
31862 {
31866 }
31869 {
31879 {
31885 }
31887 /* The elements of PERM do not suggest that only the first operand
31888 is used, but both operands are identical. Allow easier matching
31889 of the permutation by folding the permutation into the single
31890 input vector. */
31891 {
31896 }
31897 /* FALLTHRU */
31910 }
31916 /* For compiler generated permutations, we should never got here, because
31917 the compiler should also be checking the ok hook. But since this is a
31918 builtin the user has access too, so don't abort. */
31920 {
31943 }
31944 exit_error:
31946 }
31948 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
31950 static bool
31952 {
31961 /* Given sufficient ISA support we can just return true here
31962 for selected vector modes. */
31964 {
31965 /* All implementable with a single vpperm insn. */
31968 /* All implementable with 2 pshufb + 1 ior. */
31971 /* All implementable with shufpd or unpck[lh]pd. */
31974 }
31978 /* This hook is cannot be called in response to something that the
31979 user does (unlike the builtin expander) so we shouldn't ever see
31980 an error generated from the extract. */
31984 /* Implementable with shufps or pshufd. */
31988 /* Otherwise we have to go through the motions and see if we can
31989 figure out how to generate the requested permutation. */
32000 }
32002 void
32004 {
32018 /* We'll either be able to implement the permutation directly... */
32022 /* ... or we use the special-case patterns. */
32024 }
32025 \f
32026 /* This function returns the calling abi specific va_list type node.
32027 It returns the FNDECL specific va_list type. */
32029 static tree
32031 {
32038 else
32040 }
32042 /* Returns the canonical va_list type specified by TYPE. If there
32043 is no valid TYPE provided, it return NULL_TREE. */
32045 static tree
32047 {
32050 /* Resolve references and pointers to va_list type. */
32059 {
32064 {
32065 /* If va_list is an array type, the argument may have decayed
32066 to a pointer type, e.g. by being passed to another function.
32067 In that case, unwrap both types so that we can compare the
32068 underlying records. */
32071 {
32074 }
32075 }
32082 {
32083 /* If va_list is an array type, the argument may have decayed
32084 to a pointer type, e.g. by being passed to another function.
32085 In that case, unwrap both types so that we can compare the
32086 underlying records. */
32089 {
32092 }
32093 }
32100 {
32101 /* If va_list is an array type, the argument may have decayed
32102 to a pointer type, e.g. by being passed to another function.
32103 In that case, unwrap both types so that we can compare the
32104 underlying records. */
32107 {
32110 }
32111 }
32115 }
32117 }
32119 /* Iterate through the target-specific builtin types for va_list.
32120 IDX denotes the iterator, *PTREE is set to the result type of
32121 the va_list builtin, and *PNAME to its internal type.
32122 Returns zero if there is no element for this index, otherwise
32123 IDX should be increased upon the next call.
32124 Note, do not iterate a base builtin's name like __builtin_va_list.
32125 Used from c_common_nodes_and_builtins. */
32127 static int
32129 {
32131 {
32133 {
32146 }
32147 }
32150 }
32152 #undef TARGET_SCHED_DISPATCH
32153 #define TARGET_SCHED_DISPATCH has_dispatch
32154 #undef TARGET_SCHED_DISPATCH_DO
32155 #define TARGET_SCHED_DISPATCH_DO do_dispatch
32157 /* The size of the dispatch window is the total number of bytes of
32158 object code allowed in a window. */
32159 #define DISPATCH_WINDOW_SIZE 16
32161 /* Number of dispatch windows considered for scheduling. */
32162 #define MAX_DISPATCH_WINDOWS 3
32164 /* Maximum number of instructions in a window. */
32165 #define MAX_INSN 4
32167 /* Maximum number of immediate operands in a window. */
32168 #define MAX_IMM 4
32170 /* Maximum number of immediate bits allowed in a window. */
32171 #define MAX_IMM_SIZE 128
32173 /* Maximum number of 32 bit immediates allowed in a window. */
32174 #define MAX_IMM_32 4
32176 /* Maximum number of 64 bit immediates allowed in a window. */
32177 #define MAX_IMM_64 2
32179 /* Maximum total of loads or prefetches allowed in a window. */
32180 #define MAX_LOAD 2
32182 /* Maximum total of stores allowed in a window. */
32183 #define MAX_STORE 1
32185 #undef BIG
32186 #define BIG 100
32189 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
32192 disp_load,
32193 disp_store,
32194 disp_load_store,
32195 disp_prefetch,
32196 disp_imm,
32197 disp_imm_32,
32198 disp_imm_64,
32199 disp_branch,
32200 disp_cmp,
32201 disp_jcc,
32202 disp_last
32203 };
32205 /* Number of allowable groups in a dispatch window. It is an array
32206 indexed by dispatch_group enum. 100 is used as a big number,
32207 because the number of these kind of operations does not have any
32208 effect in dispatch window, but we need them for other reasons in
32209 the table. */
32212 };
32218 };
32220 /* Instruction path. */
32226 last_path
32227 };
32229 /* sched_insn_info defines a window to the instructions scheduled in
32230 the basic block. It contains a pointer to the insn_info table and
32231 the instruction scheduled.
32233 Windows are allocated for each basic block and are linked
32234 together. */
32236 rtx insn;
32243 /* Linked list of dispatch windows. This is a two way list of
32244 dispatch windows of a basic block. It contains information about
32245 the number of uops in the window and the total number of
32246 instructions and of bytes in the object code for this dispatch
32247 window. */
32265 /* Immediate valuse used in an insn. */
32267 {
32276 /* Get dispatch group of insn. */
32278 static enum dispatch_group
32280 {
32296 }
32298 /* Return true if insn is a compare instruction. */
32300 static bool
32302 {
32310 }
32312 /* Return true if a dispatch violation encountered. */
32314 static bool
32316 {
32320 }
32322 /* Return true if insn is a branch instruction. */
32324 static bool
32326 {
32328 }
32330 /* Return true if insn is a prefetch instruction. */
32332 static bool
32334 {
32336 }
32338 /* This function initializes a dispatch window and the list container holding a
32339 pointer to the window. */
32341 static void
32343 {
32349 else
32367 {
32373 }
32375 }
32377 /* This function allocates and initializes a dispatch window and the
32378 list container holding a pointer to the window. */
32382 {
32387 }
32389 /* This routine initializes the dispatch scheduling information. It
32390 initiates building dispatch scheduler tables and constructs the
32391 first dispatch window. */
32393 static void
32395 {
32396 /* Allocate a dispatch list and a window. */
32401 }
32403 /* This function returns true if a branch is detected. End of a basic block
32404 does not have to be a branch, but here we assume only branches end a
32405 window. */
32407 static bool
32409 {
32411 }
32413 /* This function is called when the end of a window processing is reached. */
32415 static void
32417 {
32420 {
32425 }
32427 }
32429 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
32430 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
32431 for 48 bytes of instructions. Note that these windows are not dispatch
32432 windows that their sizes are DISPATCH_WINDOW_SIZE. */
32436 {
32438 {
32443 }
32449 }
32451 /* Increment the number of immediate operands of an instruction. */
32453 static int
32455 {
32460 {
32467 else
32478 {
32481 }
32486 }
32489 }
32491 /* Compute number of immediate operands of an instruction. */
32493 static void
32495 {
32498 }
32500 /* Return total size of immediate operands of an instruction along with number
32501 of corresponding immediate-operands. It initializes its parameters to zero
32502 befor calling FIND_CONSTANT.
32503 INSN is the input instruction. IMM is the total of immediates.
32504 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
32505 bit immediates. */
32507 static int
32509 {
32517 }
32519 /* This function indicates if an operand of an instruction is an
32520 immediate. */
32522 static bool
32524 {
32533 }
32535 /* Return single or double path for instructions. */
32537 static enum insn_path
32539 {
32549 }
32551 /* Return insn dispatch group. */
32553 static enum dispatch_group
32555 {
32573 }
32575 /* Count number of GROUP restricted instructions in a dispatch
32576 window WINDOW_LIST. */
32578 static int
32580 {
32591 {
32610 }
32623 }
32625 /* This function returns true if insn satisfies dispatch rules on the
32626 last window scheduled. */
32628 static bool
32630 {
32638 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
32639 instructions should be given the lowest priority in the
32640 scheduling process in Haifa scheduler to make sure they will be
32641 scheduled in the same dispatch window as the refrence to them. */
32645 /* Check nonrestricted. */
32649 /* Get last dispatch window. */
32654 {
32659 /* Window 1 is full. Go for next window. */
32661 }
32668 /* See if it fits in the first window. */
32670 {
32671 /* The first widow should have only single and double path
32672 uops. */
32678 }
32680 }
32682 /* Add an instruction INSN with NUM_UOPS micro-operations to the
32683 dispatch window WINDOW_LIST. */
32685 static void
32687 {
32705 /* Initialize window with new instruction. */
32726 {
32729 }
32730 }
32732 /* Adds a scheduled instruction, INSN, to the current dispatch window.
32733 If the total bytes of instructions or the number of instructions in
32734 the window exceed allowable, it allocates a new window. */
32736 static void
32738 {
32761 /* Get the last dispatch window. */
32769 else
32772 /* If current window is full, get a new window.
32773 Window number zero is full, if MAX_INSN uops are scheduled in it.
32774 Window number one is full, if window zero's bytes plus window
32775 one's bytes is 32, or if the bytes of the new instruction added
32776 to the total makes it greater than 48, or it has already MAX_INSN
32777 instructions in it. */
32786 {
32789 }
32792 {
32796 {
32799 }
32800 }
32802 {
32807 {
32810 }
32813 }
32814 else
32818 {
32819 /* End of basic block is reached do end-basic-block process. */
32822 }
32823 }
32825 /* Print the dispatch window, WINDOW_NUM, to FILE. */
32827 DEBUG_FUNCTION static void
32829 {
32835 else
32849 {
32852 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
32858 }
32859 }
32861 /* Print to stdout a dispatch window. */
32863 DEBUG_FUNCTION void
32865 {
32867 }
32869 /* Print INSN dispatch information to FILE. */
32871 DEBUG_FUNCTION static void
32873 {
32896 }
32898 /* Print to STDERR the status of the ready list with respect to
32899 dispatch windows. */
32901 DEBUG_FUNCTION void
32903 {
32911 }
32913 /* This routine is the driver of the dispatch scheduler. */
32915 static void
32917 {
32922 }
32924 /* Return TRUE if Dispatch Scheduling is supported. */
32926 static bool
32928 {
32931 {
32947 }
32950 }
32952 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
32953 place emms and femms instructions. */
32955 static unsigned int
32957 {
32958 /* Disable double precision vectorizer if needed. */
32962 #if 0
32963 /* FIXME: AVX has 32byte floating point vector operations and 16byte
32964 integer vector operations. But vectorizer doesn't support
32965 different sizes for integer and floating point vectors. We limit
32966 vector size to 16byte. */
32969 else
32970 #endif
32972 }
32974 /* Initialize the GCC target structure. */
32975 #undef TARGET_RETURN_IN_MEMORY
32976 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
32978 #undef TARGET_LEGITIMIZE_ADDRESS
32979 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
32981 #undef TARGET_ATTRIBUTE_TABLE
32982 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
32983 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
32984 # undef TARGET_MERGE_DECL_ATTRIBUTES
32985 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
32986 #endif
32988 #undef TARGET_COMP_TYPE_ATTRIBUTES
32989 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
32991 #undef TARGET_INIT_BUILTINS
32992 #define TARGET_INIT_BUILTINS ix86_init_builtins
32993 #undef TARGET_BUILTIN_DECL
32994 #define TARGET_BUILTIN_DECL ix86_builtin_decl
32995 #undef TARGET_EXPAND_BUILTIN
32996 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
32998 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
32999 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
33000 ix86_builtin_vectorized_function
33002 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
33003 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
33005 #undef TARGET_BUILTIN_RECIPROCAL
33006 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
33008 #undef TARGET_ASM_FUNCTION_EPILOGUE
33009 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
33011 #undef TARGET_ENCODE_SECTION_INFO
33012 #ifndef SUBTARGET_ENCODE_SECTION_INFO
33013 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
33014 #else
33015 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
33016 #endif
33018 #undef TARGET_ASM_OPEN_PAREN
33020 #undef TARGET_ASM_CLOSE_PAREN
33023 #undef TARGET_ASM_BYTE_OP
33024 #define TARGET_ASM_BYTE_OP ASM_BYTE
33026 #undef TARGET_ASM_ALIGNED_HI_OP
33027 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
33028 #undef TARGET_ASM_ALIGNED_SI_OP
33029 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
33030 #ifdef ASM_QUAD
33031 #undef TARGET_ASM_ALIGNED_DI_OP
33032 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
33033 #endif
33035 #undef TARGET_PROFILE_BEFORE_PROLOGUE
33036 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
33038 #undef TARGET_ASM_UNALIGNED_HI_OP
33039 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
33040 #undef TARGET_ASM_UNALIGNED_SI_OP
33041 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
33042 #undef TARGET_ASM_UNALIGNED_DI_OP
33043 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
33045 #undef TARGET_PRINT_OPERAND
33046 #define TARGET_PRINT_OPERAND ix86_print_operand
33047 #undef TARGET_PRINT_OPERAND_ADDRESS
33048 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
33049 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
33050 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
33051 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
33052 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
33054 #undef TARGET_SCHED_ADJUST_COST
33055 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
33056 #undef TARGET_SCHED_ISSUE_RATE
33057 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
33058 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
33059 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
33060 ia32_multipass_dfa_lookahead
33062 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
33063 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
33065 #ifdef HAVE_AS_TLS
33066 #undef TARGET_HAVE_TLS
33067 #define TARGET_HAVE_TLS true
33068 #endif
33069 #undef TARGET_CANNOT_FORCE_CONST_MEM
33070 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
33071 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
33072 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
33074 #undef TARGET_DELEGITIMIZE_ADDRESS
33075 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
33077 #undef TARGET_MS_BITFIELD_LAYOUT_P
33078 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
33080 #if TARGET_MACHO
33081 #undef TARGET_BINDS_LOCAL_P
33082 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
33083 #endif
33084 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
33085 #undef TARGET_BINDS_LOCAL_P
33086 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
33087 #endif
33089 #undef TARGET_ASM_OUTPUT_MI_THUNK
33090 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
33091 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
33092 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
33094 #undef TARGET_ASM_FILE_START
33095 #define TARGET_ASM_FILE_START x86_file_start
33097 #undef TARGET_DEFAULT_TARGET_FLAGS
33098 #define TARGET_DEFAULT_TARGET_FLAGS \
33099 (TARGET_DEFAULT \
33100 | TARGET_SUBTARGET_DEFAULT \
33101 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
33102 | MASK_FUSED_MADD)
33104 #undef TARGET_HANDLE_OPTION
33105 #define TARGET_HANDLE_OPTION ix86_handle_option
33107 #undef TARGET_OPTION_OVERRIDE
33108 #define TARGET_OPTION_OVERRIDE ix86_option_override
33109 #undef TARGET_OPTION_OPTIMIZATION
33110 #define TARGET_OPTION_OPTIMIZATION ix86_option_optimization
33112 #undef TARGET_REGISTER_MOVE_COST
33113 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
33114 #undef TARGET_MEMORY_MOVE_COST
33115 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
33116 #undef TARGET_RTX_COSTS
33117 #define TARGET_RTX_COSTS ix86_rtx_costs
33118 #undef TARGET_ADDRESS_COST
33119 #define TARGET_ADDRESS_COST ix86_address_cost
33121 #undef TARGET_FIXED_CONDITION_CODE_REGS
33122 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
33123 #undef TARGET_CC_MODES_COMPATIBLE
33124 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
33126 #undef TARGET_MACHINE_DEPENDENT_REORG
33127 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
33129 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
33130 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
33132 #undef TARGET_BUILD_BUILTIN_VA_LIST
33133 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
33135 #undef TARGET_ENUM_VA_LIST_P
33136 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
33138 #undef TARGET_FN_ABI_VA_LIST
33139 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
33141 #undef TARGET_CANONICAL_VA_LIST_TYPE
33142 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
33144 #undef TARGET_EXPAND_BUILTIN_VA_START
33145 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
33147 #undef TARGET_MD_ASM_CLOBBERS
33148 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
33150 #undef TARGET_PROMOTE_PROTOTYPES
33151 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
33152 #undef TARGET_STRUCT_VALUE_RTX
33153 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
33154 #undef TARGET_SETUP_INCOMING_VARARGS
33155 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
33156 #undef TARGET_MUST_PASS_IN_STACK
33157 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
33158 #undef TARGET_FUNCTION_ARG_ADVANCE
33159 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
33160 #undef TARGET_FUNCTION_ARG
33161 #define TARGET_FUNCTION_ARG ix86_function_arg
33162 #undef TARGET_PASS_BY_REFERENCE
33163 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
33164 #undef TARGET_INTERNAL_ARG_POINTER
33165 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
33166 #undef TARGET_UPDATE_STACK_BOUNDARY
33167 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
33168 #undef TARGET_GET_DRAP_RTX
33169 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
33170 #undef TARGET_STRICT_ARGUMENT_NAMING
33171 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
33172 #undef TARGET_STATIC_CHAIN
33173 #define TARGET_STATIC_CHAIN ix86_static_chain
33174 #undef TARGET_TRAMPOLINE_INIT
33175 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
33176 #undef TARGET_RETURN_POPS_ARGS
33177 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
33179 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
33180 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
33182 #undef TARGET_SCALAR_MODE_SUPPORTED_P
33183 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
33185 #undef TARGET_VECTOR_MODE_SUPPORTED_P
33186 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
33188 #undef TARGET_C_MODE_FOR_SUFFIX
33189 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
33191 #ifdef HAVE_AS_TLS
33192 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
33193 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
33194 #endif
33196 #ifdef SUBTARGET_INSERT_ATTRIBUTES
33197 #undef TARGET_INSERT_ATTRIBUTES
33198 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
33199 #endif
33201 #undef TARGET_MANGLE_TYPE
33202 #define TARGET_MANGLE_TYPE ix86_mangle_type
33204 #undef TARGET_STACK_PROTECT_FAIL
33205 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
33207 #undef TARGET_SUPPORTS_SPLIT_STACK
33208 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
33210 #undef TARGET_FUNCTION_VALUE
33211 #define TARGET_FUNCTION_VALUE ix86_function_value
33213 #undef TARGET_FUNCTION_VALUE_REGNO_P
33214 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
33216 #undef TARGET_SECONDARY_RELOAD
33217 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
33219 #undef TARGET_CLASS_LIKELY_SPILLED_P
33220 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
33222 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
33223 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
33224 ix86_builtin_vectorization_cost
33225 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
33226 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
33227 ix86_vectorize_builtin_vec_perm
33228 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
33229 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
33230 ix86_vectorize_builtin_vec_perm_ok
33231 #undef TARGET_VECTORIZE_UNITS_PER_SIMD_WORD
33232 #define TARGET_VECTORIZE_UNITS_PER_SIMD_WORD \
33233 ix86_units_per_simd_word
33235 #undef TARGET_SET_CURRENT_FUNCTION
33236 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
33238 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
33239 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
33241 #undef TARGET_OPTION_SAVE
33242 #define TARGET_OPTION_SAVE ix86_function_specific_save
33244 #undef TARGET_OPTION_RESTORE
33245 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
33247 #undef TARGET_OPTION_PRINT
33248 #define TARGET_OPTION_PRINT ix86_function_specific_print
33250 #undef TARGET_CAN_INLINE_P
33251 #define TARGET_CAN_INLINE_P ix86_can_inline_p
33253 #undef TARGET_EXPAND_TO_RTL_HOOK
33254 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
33256 #undef TARGET_LEGITIMATE_ADDRESS_P
33257 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
33259 #undef TARGET_IRA_COVER_CLASSES
33260 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
33262 #undef TARGET_FRAME_POINTER_REQUIRED
33263 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
33265 #undef TARGET_CAN_ELIMINATE
33266 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
33268 #undef TARGET_EXTRA_LIVE_ON_ENTRY
33269 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
33271 #undef TARGET_ASM_CODE_END
33272 #define TARGET_ASM_CODE_END ix86_code_end
33275 \f