gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()                       \
  27   do                                                    \
  28     {                                                   \
  29       builtin_define ("__aarch64__");                   \
  30       if (TARGET_BIG_END)                               \
  31         builtin_define ("__AARCH64EB__");               \
  32       else                                              \
  33         builtin_define ("__AARCH64EL__");               \
  34                                                         \
  35       if (TARGET_SIMD)                                  \
  36         builtin_define ("__ARM_NEON");                  \
  37                                                         \
  38       switch (aarch64_cmodel)                           \
  39         {                                               \
  40           case AARCH64_CMODEL_TINY:                     \
  41           case AARCH64_CMODEL_TINY_PIC:                 \
  42             builtin_define ("__AARCH64_CMODEL_TINY__"); \
  43             break;                                      \
  44           case AARCH64_CMODEL_SMALL:                    \
  45           case AARCH64_CMODEL_SMALL_PIC:                \
  46             builtin_define ("__AARCH64_CMODEL_SMALL__");\
  47             break;                                      \
  48           case AARCH64_CMODEL_LARGE:                    \
  49             builtin_define ("__AARCH64_CMODEL_LARGE__");        \
  50             break;                                      \
  51           default:                                      \
  52             break;                                      \
  53         }                                               \
  54                                                         \
  55       if (TARGET_ILP32)                                 \
  56         {                                               \
  57           cpp_define (parse_in, "_ILP32");              \
  58           cpp_define (parse_in, "__ILP32__");           \
  59         }                                               \
  60       if (TARGET_CRYPTO)                                \
  61         builtin_define ("__ARM_FEATURE_CRYPTO");        \
  62     } while (0)
  63
  64 \f
  65
  66 /* Target machine storage layout.  */
  67
  68 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  69   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  70       && GET_MODE_SIZE (MODE) < 4)              \
  71     {                                           \
  72       if (MODE == QImode || MODE == HImode)     \
  73         {                                       \
  74           MODE = SImode;                        \
  75         }                                       \
  76     }
  77
  78 /* Bits are always numbered from the LSBit.  */
  79 #define BITS_BIG_ENDIAN 0
  80
  81 /* Big/little-endian flavour.  */
  82 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  83 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  84
  85 /* AdvSIMD is supported in the default configuration, unless disabled by
  86    -mgeneral-regs-only or by the +nosimd extension.  */
  87 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  88 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  89
  90 #define UNITS_PER_WORD          8
  91
  92 #define UNITS_PER_VREG          16
  93
  94 #define PARM_BOUNDARY           64
  95
  96 #define STACK_BOUNDARY          128
  97
  98 #define FUNCTION_BOUNDARY       32
  99
 100 #define EMPTY_FIELD_BOUNDARY    32
 101
 102 #define BIGGEST_ALIGNMENT       128
 103
 104 #define SHORT_TYPE_SIZE         16
 105
 106 #define INT_TYPE_SIZE           32
 107
 108 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
 109
 110 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
 111
 112 #define LONG_LONG_TYPE_SIZE     64
 113
 114 #define FLOAT_TYPE_SIZE         32
 115
 116 #define DOUBLE_TYPE_SIZE        64
 117
 118 #define LONG_DOUBLE_TYPE_SIZE   128
 119
 120 /* The architecture reserves all bits of the address for hardware use,
 121    so the vbit must go into the delta field of pointers to member
 122    functions.  This is the same config as that in the AArch32
 123    port.  */
 124 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
 125
 126 /* Make strings word-aligned so that strcpy from constants will be
 127    faster.  */
 128 #define CONSTANT_ALIGNMENT(EXP, ALIGN)          \
 129   ((TREE_CODE (EXP) == STRING_CST               \
 130     && !optimize_size                           \
 131     && (ALIGN) < BITS_PER_WORD)                 \
 132    ? BITS_PER_WORD : ALIGN)
 133
 134 #define DATA_ALIGNMENT(EXP, ALIGN)              \
 135   ((((ALIGN) < BITS_PER_WORD)                   \
 136     && (TREE_CODE (EXP) == ARRAY_TYPE           \
 137         || TREE_CODE (EXP) == UNION_TYPE        \
 138         || TREE_CODE (EXP) == RECORD_TYPE))     \
 139    ? BITS_PER_WORD : (ALIGN))
 140
 141 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
 142
 143 #define STRUCTURE_SIZE_BOUNDARY         8
 144
 145 /* Defined by the ABI */
 146 #define WCHAR_TYPE "unsigned int"
 147 #define WCHAR_TYPE_SIZE                 32
 148
 149 /* Using long long breaks -ansi and -std=c90, so these will need to be
 150    made conditional for an LLP64 ABI.  */
 151
 152 #define SIZE_TYPE       "long unsigned int"
 153
 154 #define PTRDIFF_TYPE    "long int"
 155
 156 #define PCC_BITFIELD_TYPE_MATTERS       1
 157
 158
 159 /* Instruction tuning/selection flags.  */
 160
 161 /* Bit values used to identify processor capabilities.  */
 162 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 163 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 164 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 165 #define AARCH64_FL_SLOWMUL    (1 << 3)  /* A slow multiply core.  */
 166 #define AARCH64_FL_CRC        (1 << 4)  /* Has CRC.  */
 167
 168 /* Has FP and SIMD.  */
 169 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 170
 171 /* Has FP without SIMD.  */
 172 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 173
 174 /* Architecture flags that effect instruction selection.  */
 175 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 176
 177 /* Macros to test ISA flags.  */
 178 extern unsigned long aarch64_isa_flags;
 179 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 180 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 181 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 182 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 183
 184 /* Macros to test tuning flags.  */
 185 extern unsigned long aarch64_tune_flags;
 186 #define AARCH64_TUNE_SLOWMUL       (aarch64_tune_flags & AARCH64_FL_SLOWMUL)
 187
 188 /* Crypto is an optional extension to AdvSIMD.  */
 189 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 190
 191 /* Standard register usage.  */
 192
 193 /* 31 64-bit general purpose registers R0-R30:
 194    R30          LR (link register)
 195    R29          FP (frame pointer)
 196    R19-R28      Callee-saved registers
 197    R18          The platform register; use as temporary register.
 198    R17          IP1 The second intra-procedure-call temporary register
 199                 (can be used by call veneers and PLT code); otherwise use
 200                 as a temporary register
 201    R16          IP0 The first intra-procedure-call temporary register (can
 202                 be used by call veneers and PLT code); otherwise use as a
 203                 temporary register
 204    R9-R15       Temporary registers
 205    R8           Structure value parameter / temporary register
 206    R0-R7        Parameter/result registers
 207
 208    SP           stack pointer, encoded as X/R31 where permitted.
 209    ZR           zero register, encoded as X/R31 elsewhere
 210
 211    32 x 128-bit floating-point/vector registers
 212    V16-V31      Caller-saved (temporary) registers
 213    V8-V15       Callee-saved registers
 214    V0-V7        Parameter/result registers
 215
 216    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 217    significant bits.  Unlike AArch32 S1 is not packed into D0,
 218    etc.  */
 219
 220 /* Note that we don't mark X30 as a call-clobbered register.  The idea is
 221    that it's really the call instructions themselves which clobber X30.
 222    We don't care what the called function does with it afterwards.
 223
 224    This approach makes it easier to implement sibcalls.  Unlike normal
 225    calls, sibcalls don't clobber X30, so the register reaches the
 226    called function intact.  EPILOGUE_USES says that X30 is useful
 227    to the called function.  */
 228
 229 #define FIXED_REGISTERS                                 \
 230   {                                                     \
 231     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 232     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 233     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 234     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 235     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 236     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 237     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 238     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 239     1, 1, 1,                    /* SFP, AP, CC */       \
 240   }
 241
 242 #define CALL_USED_REGISTERS                             \
 243   {                                                     \
 244     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 245     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 246     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 247     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 248     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 249     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 250     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 251     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 252     1, 1, 1,                    /* SFP, AP, CC */       \
 253   }
 254
 255 #define REGISTER_NAMES                                          \
 256   {                                                             \
 257     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 258     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 259     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 260     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 261     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 262     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 263     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 264     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 265     "sfp", "ap",  "cc",                                         \
 266   }
 267
 268 /* Generate the register aliases for core register N */
 269 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 270                      {"w" # N, R0_REGNUM + (N)}
 271
 272 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 273                      {"d" # N, V0_REGNUM + (N)}, \
 274                      {"s" # N, V0_REGNUM + (N)}, \
 275                      {"h" # N, V0_REGNUM + (N)}, \
 276                      {"b" # N, V0_REGNUM + (N)}
 277
 278 /* Provide aliases for all of the ISA defined register name forms.
 279    These aliases are convenient for use in the clobber lists of inline
 280    asm statements.  */
 281
 282 #define ADDITIONAL_REGISTER_NAMES \
 283   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 284     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 285     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 286     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 287     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 288     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 289     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 290     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 291     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 292     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 293     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 294     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 295     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 296     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 297     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 298     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 299   }
 300
 301 /* Say that the epilogue uses the return address register.  Note that
 302    in the case of sibcalls, the values "used by the epilogue" are
 303    considered live at the start of the called function.  */
 304
 305 #define EPILOGUE_USES(REGNO) \
 306   ((REGNO) == LR_REGNUM)
 307
 308 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 309    the stack pointer does not matter.  The value is tested only in
 310    functions that have frame pointers.  */
 311 #define EXIT_IGNORE_STACK       1
 312
 313 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 314 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 315 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 316 #define STACK_POINTER_REGNUM            SP_REGNUM
 317 #define ARG_POINTER_REGNUM              AP_REGNUM
 318 #define FIRST_PSEUDO_REGISTER           67
 319
 320 /* The number of (integer) argument register available.  */
 321 #define NUM_ARG_REGS                    8
 322 #define NUM_FP_ARG_REGS                 8
 323
 324 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 325    four members.  */
 326 #define HA_MAX_NUM_FLDS         4
 327
 328 /* External dwarf register number scheme.  These number are used to
 329    identify registers in dwarf debug information, the values are
 330    defined by the AArch64 ABI.  The numbering scheme is independent of
 331    GCC's internal register numbering scheme.  */
 332
 333 #define AARCH64_DWARF_R0        0
 334
 335 /* The number of R registers, note 31! not 32.  */
 336 #define AARCH64_DWARF_NUMBER_R 31
 337
 338 #define AARCH64_DWARF_SP       31
 339 #define AARCH64_DWARF_V0       64
 340
 341 /* The number of V registers.  */
 342 #define AARCH64_DWARF_NUMBER_V 32
 343
 344 /* For signal frames we need to use an alternative return column.  This
 345    value must not correspond to a hard register and must be out of the
 346    range of DWARF_FRAME_REGNUM().  */
 347 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 348   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 349
 350 /* We add 1 extra frame register for use as the
 351    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 352 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 353
 354
 355 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 356 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 357    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 358    as the default definition in dwarf2out.c.  */
 359 #undef DWARF_FRAME_REGNUM
 360 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 361
 362 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 363
 364 #define HARD_REGNO_NREGS(REGNO, MODE)   aarch64_hard_regno_nregs (REGNO, MODE)
 365
 366 #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE)
 367
 368 #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
 369
 370 #define DWARF2_UNWIND_INFO 1
 371
 372 /* Use R0 through R3 to pass exception handling information.  */
 373 #define EH_RETURN_DATA_REGNO(N) \
 374   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 375
 376 /* Select a format to encode pointers in exception handling data.  */
 377 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 378   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 379
 380 /* The register that holds the return address in exception handlers.  */
 381 #define AARCH64_EH_STACKADJ_REGNUM      (R0_REGNUM + 4)
 382 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM)
 383
 384 /* Don't use __builtin_setjmp until we've defined it.  */
 385 #undef DONT_USE_BUILTIN_SETJMP
 386 #define DONT_USE_BUILTIN_SETJMP 1
 387
 388 /* Register in which the structure value is to be returned.  */
 389 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 390
 391 /* Non-zero if REGNO is part of the Core register set.
 392
 393    The rather unusual way of expressing this check is to avoid
 394    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 395    is unsigned.  */
 396 #define GP_REGNUM_P(REGNO)                                              \
 397   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 398
 399 #define FP_REGNUM_P(REGNO)                      \
 400   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 401
 402 #define FP_LO_REGNUM_P(REGNO)            \
 403   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 404
 405 \f
 406 /* Register and constant classes.  */
 407
 408 enum reg_class
 409 {
 410   NO_REGS,
 411   CORE_REGS,
 412   GENERAL_REGS,
 413   STACK_REG,
 414   POINTER_REGS,
 415   FP_LO_REGS,
 416   FP_REGS,
 417   ALL_REGS,
 418   LIM_REG_CLASSES               /* Last */
 419 };
 420
 421 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 422
 423 #define REG_CLASS_NAMES                         \
 424 {                                               \
 425   "NO_REGS",                                    \
 426   "CORE_REGS",                                  \
 427   "GENERAL_REGS",                               \
 428   "STACK_REG",                                  \
 429   "POINTER_REGS",                               \
 430   "FP_LO_REGS",                                 \
 431   "FP_REGS",                                    \
 432   "ALL_REGS"                                    \
 433 }
 434
 435 #define REG_CLASS_CONTENTS                                              \
 436 {                                                                       \
 437   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 438   { 0x7fffffff, 0x00000000, 0x00000003 },       /* CORE_REGS */         \
 439   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 440   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 441   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 442   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 443   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 444   { 0xffffffff, 0xffffffff, 0x00000007 }        /* ALL_REGS */          \
 445 }
 446
 447 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 448
 449 #define INDEX_REG_CLASS CORE_REGS
 450 #define BASE_REG_CLASS  POINTER_REGS
 451
 452 /* Register pairs used to eliminate unneeded registers that point into
 453    the stack frame.  */
 454 #define ELIMINABLE_REGS                                                 \
 455 {                                                                       \
 456   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 457   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 458   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 459   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 460 }
 461
 462 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 463   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 464
 465 /* CPU/ARCH option handling.  */
 466 #include "config/aarch64/aarch64-opts.h"
 467
 468 enum target_cpus
 469 {
 470 #define AARCH64_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
 471   TARGET_CPU_##INTERNAL_IDENT,
 472 #include "aarch64-cores.def"
 473 #undef AARCH64_CORE
 474   TARGET_CPU_generic
 475 };
 476
 477 /* If there is no CPU defined at configure, use generic as default.  */
 478 #ifndef TARGET_CPU_DEFAULT
 479 #define TARGET_CPU_DEFAULT \
 480   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 481 #endif
 482
 483 /* The processor for which instructions should be scheduled.  */
 484 extern enum aarch64_processor aarch64_tune;
 485
 486 /* RTL generation support.  */
 487 #define INIT_EXPANDERS aarch64_init_expanders ()
 488 \f
 489
 490 /* Stack layout; function entry, exit and calling.  */
 491 #define STACK_GROWS_DOWNWARD    1
 492
 493 #define FRAME_GROWS_DOWNWARD    1
 494
 495 #define STARTING_FRAME_OFFSET   0
 496
 497 #define ACCUMULATE_OUTGOING_ARGS        1
 498
 499 #define FIRST_PARM_OFFSET(FNDECL) 0
 500
 501 /* Fix for VFP */
 502 #define LIBCALL_VALUE(MODE)  \
 503   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 504
 505 #define DEFAULT_PCC_STRUCT_RETURN 0
 506
 507 #define AARCH64_ROUND_UP(X, ALIGNMENT) \
 508   (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1))
 509
 510 #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \
 511   ((X) & ~((ALIGNMENT) - 1))
 512
 513 #ifdef HOST_WIDE_INT
 514 struct GTY (()) aarch64_frame
 515 {
 516   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 517   HOST_WIDE_INT saved_regs_size;
 518   /* Padding if needed after the all the callee save registers have
 519      been saved.  */
 520   HOST_WIDE_INT padding0;
 521   HOST_WIDE_INT hardfp_offset;  /* HARD_FRAME_POINTER_REGNUM */
 522
 523   bool laid_out;
 524 };
 525
 526 typedef struct GTY (()) machine_function
 527 {
 528   struct aarch64_frame frame;
 529
 530   /* The number of extra stack bytes taken up by register varargs.
 531      This area is allocated by the callee at the very top of the frame.  */
 532   HOST_WIDE_INT saved_varargs_size;
 533
 534 } machine_function;
 535 #endif
 536
 537 /* Which ABI to use.  */
 538 enum aarch64_abi_type
 539 {
 540   AARCH64_ABI_LP64 = 0,
 541   AARCH64_ABI_ILP32 = 1
 542 };
 543
 544 #ifndef AARCH64_ABI_DEFAULT
 545 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 546 #endif
 547
 548 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 549
 550 enum arm_pcs
 551 {
 552   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 553   ARM_PCS_UNKNOWN
 554 };
 555
 556
 557 extern enum arm_pcs arm_pcs_variant;
 558
 559 #ifndef ARM_DEFAULT_PCS
 560 #define ARM_DEFAULT_PCS ARM_PCS_AAPCS64
 561 #endif
 562
 563 /* We can't use enum machine_mode inside a generator file because it
 564    hasn't been created yet; we shouldn't be using any code that
 565    needs the real definition though, so this ought to be safe.  */
 566 #ifdef GENERATOR_FILE
 567 #define MACHMODE int
 568 #else
 569 #include "insn-modes.h"
 570 #define MACHMODE enum machine_mode
 571 #endif
 572
 573
 574 /* AAPCS related state tracking.  */
 575 typedef struct
 576 {
 577   enum arm_pcs pcs_variant;
 578   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 579   int aapcs_ncrn;               /* Next Core register number.  */
 580   int aapcs_nextncrn;           /* Next next core register number.  */
 581   int aapcs_nvrn;               /* Next Vector register number.  */
 582   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 583   rtx aapcs_reg;                /* Register assigned to this argument.  This
 584                                    is NULL_RTX if this parameter goes on
 585                                    the stack.  */
 586   MACHMODE aapcs_vfp_rmode;
 587   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 588                                    is the number of words needed, after rounding
 589                                    up.  Only meaningful when
 590                                    aapcs_reg == NULL_RTX.  */
 591   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 592                                    stack arg area so far.  */
 593 } CUMULATIVE_ARGS;
 594
 595 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
 596   (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward)
 597
 598 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 599   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
 600
 601 #define PAD_VARARGS_DOWN        0
 602
 603 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 604   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 605
 606 #define FUNCTION_ARG_REGNO_P(REGNO) \
 607   aarch64_function_arg_regno_p(REGNO)
 608 \f
 609
 610 /* ISA Features.  */
 611
 612 /* Addressing modes, etc.  */
 613 #define HAVE_POST_INCREMENT     1
 614 #define HAVE_PRE_INCREMENT      1
 615 #define HAVE_POST_DECREMENT     1
 616 #define HAVE_PRE_DECREMENT      1
 617 #define HAVE_POST_MODIFY_DISP   1
 618 #define HAVE_PRE_MODIFY_DISP    1
 619
 620 #define MAX_REGS_PER_ADDRESS    2
 621
 622 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 623
 624 /* Try a machine-dependent way of reloading an illegitimate address
 625    operand.  If we find one, push the reload and jump to WIN.  This
 626    macro is used in only one place: `find_reloads_address' in reload.c.  */
 627
 628 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN)          \
 629 do {                                                                         \
 630   rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE,    \
 631                                                  IND_L);                     \
 632   if (new_x)                                                                 \
 633     {                                                                        \
 634       X = new_x;                                                             \
 635       goto WIN;                                                              \
 636     }                                                                        \
 637 } while (0)
 638
 639 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 640   aarch64_regno_ok_for_base_p (REGNO, true)
 641
 642 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 643   aarch64_regno_ok_for_index_p (REGNO, true)
 644
 645 #define LEGITIMATE_PIC_OPERAND_P(X) \
 646   aarch64_legitimate_pic_operand_p (X)
 647
 648 #define CASE_VECTOR_MODE Pmode
 649
 650 #define DEFAULT_SIGNED_CHAR 0
 651
 652 /* An integer expression for the size in bits of the largest integer machine
 653    mode that should actually be used.  We allow pairs of registers.  */
 654 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 655
 656 /* Maximum bytes moved by a single instruction (load/store pair).  */
 657 #define MOVE_MAX (UNITS_PER_WORD * 2)
 658
 659 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 660 #define AARCH64_CALL_RATIO 8
 661
 662 /* When optimizing for size, give a better estimate of the length of a memcpy
 663    call, but use the default otherwise.  But move_by_pieces_ninsns() counts
 664    memory-to-memory moves, and we'll have to generate a load & store for each,
 665    so halve the value to take that into account.  */
 666 #define MOVE_RATIO(speed) \
 667   (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)
 668
 669 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 670    of the length of a memset call, but use the default otherwise.  */
 671 #define CLEAR_RATIO(speed) \
 672   ((speed) ? 15 : AARCH64_CALL_RATIO)
 673
 674 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 675    optimizing for size adjust the ratio to account for the overhead of loading
 676    the constant.  */
 677 #define SET_RATIO(speed) \
 678   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 679
 680 /* STORE_BY_PIECES_P can be used when copying a constant string, but
 681    in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
 682    For now we always fail this and let the move_by_pieces code copy
 683    the string from read-only memory.  */
 684 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
 685
 686 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 687    rarely a good idea in straight-line code since it adds an extra address
 688    dependency between each instruction.  Better to use incrementing offsets.  */
 689 #define USE_LOAD_POST_INCREMENT(MODE)   0
 690 #define USE_LOAD_POST_DECREMENT(MODE)   0
 691 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 692 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 693 #define USE_STORE_POST_INCREMENT(MODE)  0
 694 #define USE_STORE_POST_DECREMENT(MODE)  0
 695 #define USE_STORE_PRE_INCREMENT(MODE)   0
 696 #define USE_STORE_PRE_DECREMENT(MODE)   0
 697
 698 /* ?? #define WORD_REGISTER_OPERATIONS  */
 699
 700 /* Define if loading from memory in MODE, an integral mode narrower than
 701    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 702    macro should be the code that says which one of the two operations is
 703    implicitly done, or UNKNOWN if none.  */
 704 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 705
 706 /* Define this macro to be non-zero if instructions will fail to work
 707    if given data not on the nominal alignment.  */
 708 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 709
 710 /* Define this macro to be non-zero if accessing less than a word of
 711    memory is no faster than accessing a word of memory, i.e., if such
 712    accesses require more than one instruction or if there is no
 713    difference in cost.
 714    Although there's no difference in instruction count or cycles,
 715    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 716    if we don't have to, for power-saving reasons.  */
 717 #define SLOW_BYTE_ACCESS                0
 718
 719 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 720
 721 #define NO_FUNCTION_CSE 1
 722
 723 /* Specify the machine mode that the hardware addresses have.
 724    After generation of rtl, the compiler makes no further distinction
 725    between pointers and any other objects of this machine mode.  */
 726 #define Pmode           DImode
 727
 728 /* A C expression whose value is zero if pointers that need to be extended
 729    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 730    greater then zero if they are zero-extended and less then zero if the
 731    ptr_extend instruction should be used.  */
 732 #define POINTERS_EXTEND_UNSIGNED 1
 733
 734 /* Mode of a function address in a call instruction (for indexing purposes).  */
 735 #define FUNCTION_MODE   Pmode
 736
 737 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 738
 739 #define REVERSIBLE_CC_MODE(MODE) 1
 740
 741 #define REVERSE_CONDITION(CODE, MODE)           \
 742   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 743    ? reverse_condition_maybe_unordered (CODE)   \
 744    : reverse_condition (CODE))
 745
 746 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 747   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
 748 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 749   ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
 750
 751 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 752
 753 #define RETURN_ADDR_RTX aarch64_return_addr
 754
 755 /* 3 insns + padding + 2 pointer-sized entries.  */
 756 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 757
 758 /* Trampolines contain dwords, so must be dword aligned.  */
 759 #define TRAMPOLINE_ALIGNMENT 64
 760
 761 /* Put trampolines in the text section so that mapping symbols work
 762    correctly.  */
 763 #define TRAMPOLINE_SECTION text_section
 764
 765 /* To start with.  */
 766 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2
 767 \f
 768
 769 /* Assembly output.  */
 770
 771 /* For now we'll make all jump tables pc-relative.  */
 772 #define CASE_VECTOR_PC_RELATIVE 1
 773
 774 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 775   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 776    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 777    : QImode)
 778
 779 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 780 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 781
 782 #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE)
 783
 784 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
 785   aarch64_print_operand_address (STREAM, X)
 786
 787 #define MCOUNT_NAME "_mcount"
 788
 789 #define NO_PROFILE_COUNTERS 1
 790
 791 /* Emit rtl for profiling.  Output assembler code to FILE
 792    to call "_mcount" for profiling a function entry.  */
 793 #define PROFILE_HOOK(LABEL)                                             \
 794   {                                                                     \
 795     rtx fun, lr;                                                        \
 796     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
 797     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 798     emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode);        \
 799   }
 800
 801 /* All the work done in PROFILE_HOOK, but still required.  */
 802 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 803
 804 /* For some reason, the Linux headers think they know how to define
 805    these macros.  They don't!!!  */
 806 #undef ASM_APP_ON
 807 #undef ASM_APP_OFF
 808 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
 809 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
 810
 811 #define CONSTANT_POOL_BEFORE_FUNCTION 0
 812
 813 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
 814    should be undefined in aarch64-linux.h and a clear_cache pattern
 815    implmented to emit either the call to __aarch64_sync_cache_range()
 816    directly or preferably the appropriate sycall or cache clear
 817    instructions inline.  */
 818 #define CLEAR_INSN_CACHE(beg, end)                              \
 819   extern void  __aarch64_sync_cache_range (void *, void *);     \
 820   __aarch64_sync_cache_range (beg, end)
 821
 822 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)       \
 823   aarch64_cannot_change_mode_class (FROM, TO, CLASS)
 824
 825 #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
 826
 827 /* Callee only saves lower 64-bits of a 128-bit register.  Tell the
 828    compiler the callee clobbers the top 64-bits when restoring the
 829    bottom 64-bits.  */
 830 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
 831                 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8)
 832
 833 /* Check TLS Descriptors mechanism is selected.  */
 834 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
 835
 836 extern enum aarch64_code_model aarch64_cmodel;
 837
 838 /* When using the tiny addressing model conditional and unconditional branches
 839    can span the whole of the available address space (1MB).  */
 840 #define HAS_LONG_COND_BRANCH                            \
 841   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 842    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 843
 844 #define HAS_LONG_UNCOND_BRANCH                          \
 845   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 846    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 847
 848 /* Modes valid for AdvSIMD Q registers.  */
 849 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
 850   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
 851    || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode)
 852
 853 #define ENDIAN_LANE_N(mode, n)  \
 854   (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
 855
 856 #define BIG_LITTLE_SPEC \
 857    " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
 858
 859 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
 860 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
 861   { "rewrite_mcpu", aarch64_rewrite_mcpu },
 862
 863 #define ASM_CPU_SPEC \
 864    BIG_LITTLE_SPEC
 865
 866 #define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
 867
 868 #define EXTRA_SPECS                                             \
 869   { "asm_cpu_spec",             ASM_CPU_SPEC }
 870
 871 #endif /* GCC_AARCH64_H */