* sr.po: Update.
[official-gcc.git] / gcc / recog.c
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1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "tm_p.h"
31 #include "insn-config.h"
32 #include "regs.h"
33 #include "emit-rtl.h"
34 #include "recog.h"
35 #include "insn-attr.h"
36 #include "addresses.h"
37 #include "cfgrtl.h"
38 #include "cfgbuild.h"
39 #include "cfgcleanup.h"
40 #include "reload.h"
41 #include "tree-pass.h"
43 #ifndef STACK_POP_CODE
44 #if STACK_GROWS_DOWNWARD
45 #define STACK_POP_CODE POST_INC
46 #else
47 #define STACK_POP_CODE POST_DEC
48 #endif
49 #endif
51 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
52 static void validate_replace_src_1 (rtx *, void *);
53 static rtx_insn *split_insn (rtx_insn *);
55 struct target_recog default_target_recog;
56 #if SWITCHABLE_TARGET
57 struct target_recog *this_target_recog = &default_target_recog;
58 #endif
60 /* Nonzero means allow operands to be volatile.
61 This should be 0 if you are generating rtl, such as if you are calling
62 the functions in optabs.c and expmed.c (most of the time).
63 This should be 1 if all valid insns need to be recognized,
64 such as in reginfo.c and final.c and reload.c.
66 init_recog and init_recog_no_volatile are responsible for setting this. */
68 int volatile_ok;
70 struct recog_data_d recog_data;
72 /* Contains a vector of operand_alternative structures, such that
73 operand OP of alternative A is at index A * n_operands + OP.
74 Set up by preprocess_constraints. */
75 const operand_alternative *recog_op_alt;
77 /* Used to provide recog_op_alt for asms. */
78 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
79 * MAX_RECOG_ALTERNATIVES];
81 /* On return from `constrain_operands', indicate which alternative
82 was satisfied. */
84 int which_alternative;
86 /* Nonzero after end of reload pass.
87 Set to 1 or 0 by toplev.c.
88 Controls the significance of (SUBREG (MEM)). */
90 int reload_completed;
92 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
93 int epilogue_completed;
95 /* Initialize data used by the function `recog'.
96 This must be called once in the compilation of a function
97 before any insn recognition may be done in the function. */
99 void
100 init_recog_no_volatile (void)
102 volatile_ok = 0;
105 void
106 init_recog (void)
108 volatile_ok = 1;
112 /* Return true if labels in asm operands BODY are LABEL_REFs. */
114 static bool
115 asm_labels_ok (rtx body)
117 rtx asmop;
118 int i;
120 asmop = extract_asm_operands (body);
121 if (asmop == NULL_RTX)
122 return true;
124 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
125 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
126 return false;
128 return true;
131 /* Check that X is an insn-body for an `asm' with operands
132 and that the operands mentioned in it are legitimate. */
135 check_asm_operands (rtx x)
137 int noperands;
138 rtx *operands;
139 const char **constraints;
140 int i;
142 if (!asm_labels_ok (x))
143 return 0;
145 /* Post-reload, be more strict with things. */
146 if (reload_completed)
148 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
149 rtx_insn *insn = make_insn_raw (x);
150 extract_insn (insn);
151 constrain_operands (1, get_enabled_alternatives (insn));
152 return which_alternative >= 0;
155 noperands = asm_noperands (x);
156 if (noperands < 0)
157 return 0;
158 if (noperands == 0)
159 return 1;
161 operands = XALLOCAVEC (rtx, noperands);
162 constraints = XALLOCAVEC (const char *, noperands);
164 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
166 for (i = 0; i < noperands; i++)
168 const char *c = constraints[i];
169 if (c[0] == '%')
170 c++;
171 if (! asm_operand_ok (operands[i], c, constraints))
172 return 0;
175 return 1;
178 /* Static data for the next two routines. */
180 struct change_t
182 rtx object;
183 int old_code;
184 rtx *loc;
185 rtx old;
186 bool unshare;
189 static change_t *changes;
190 static int changes_allocated;
192 static int num_changes = 0;
194 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
195 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
196 the change is simply made.
198 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
199 will be called with the address and mode as parameters. If OBJECT is
200 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
201 the change in place.
203 IN_GROUP is nonzero if this is part of a group of changes that must be
204 performed as a group. In that case, the changes will be stored. The
205 function `apply_change_group' will validate and apply the changes.
207 If IN_GROUP is zero, this is a single change. Try to recognize the insn
208 or validate the memory reference with the change applied. If the result
209 is not valid for the machine, suppress the change and return zero.
210 Otherwise, perform the change and return 1. */
212 static bool
213 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
215 rtx old = *loc;
217 if (old == new_rtx || rtx_equal_p (old, new_rtx))
218 return 1;
220 gcc_assert (in_group != 0 || num_changes == 0);
222 *loc = new_rtx;
224 /* Save the information describing this change. */
225 if (num_changes >= changes_allocated)
227 if (changes_allocated == 0)
228 /* This value allows for repeated substitutions inside complex
229 indexed addresses, or changes in up to 5 insns. */
230 changes_allocated = MAX_RECOG_OPERANDS * 5;
231 else
232 changes_allocated *= 2;
234 changes = XRESIZEVEC (change_t, changes, changes_allocated);
237 changes[num_changes].object = object;
238 changes[num_changes].loc = loc;
239 changes[num_changes].old = old;
240 changes[num_changes].unshare = unshare;
242 if (object && !MEM_P (object))
244 /* Set INSN_CODE to force rerecognition of insn. Save old code in
245 case invalid. */
246 changes[num_changes].old_code = INSN_CODE (object);
247 INSN_CODE (object) = -1;
250 num_changes++;
252 /* If we are making a group of changes, return 1. Otherwise, validate the
253 change group we made. */
255 if (in_group)
256 return 1;
257 else
258 return apply_change_group ();
261 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 UNSHARE to false. */
264 bool
265 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
267 return validate_change_1 (object, loc, new_rtx, in_group, false);
270 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
271 UNSHARE to true. */
273 bool
274 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
276 return validate_change_1 (object, loc, new_rtx, in_group, true);
280 /* Keep X canonicalized if some changes have made it non-canonical; only
281 modifies the operands of X, not (for example) its code. Simplifications
282 are not the job of this routine.
284 Return true if anything was changed. */
285 bool
286 canonicalize_change_group (rtx_insn *insn, rtx x)
288 if (COMMUTATIVE_P (x)
289 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
291 /* Oops, the caller has made X no longer canonical.
292 Let's redo the changes in the correct order. */
293 rtx tem = XEXP (x, 0);
294 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
295 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
296 return true;
298 else
299 return false;
303 /* This subroutine of apply_change_group verifies whether the changes to INSN
304 were valid; i.e. whether INSN can still be recognized.
306 If IN_GROUP is true clobbers which have to be added in order to
307 match the instructions will be added to the current change group.
308 Otherwise the changes will take effect immediately. */
311 insn_invalid_p (rtx_insn *insn, bool in_group)
313 rtx pat = PATTERN (insn);
314 int num_clobbers = 0;
315 /* If we are before reload and the pattern is a SET, see if we can add
316 clobbers. */
317 int icode = recog (pat, insn,
318 (GET_CODE (pat) == SET
319 && ! reload_completed
320 && ! reload_in_progress)
321 ? &num_clobbers : 0);
322 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
325 /* If this is an asm and the operand aren't legal, then fail. Likewise if
326 this is not an asm and the insn wasn't recognized. */
327 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
328 || (!is_asm && icode < 0))
329 return 1;
331 /* If we have to add CLOBBERs, fail if we have to add ones that reference
332 hard registers since our callers can't know if they are live or not.
333 Otherwise, add them. */
334 if (num_clobbers > 0)
336 rtx newpat;
338 if (added_clobbers_hard_reg_p (icode))
339 return 1;
341 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
342 XVECEXP (newpat, 0, 0) = pat;
343 add_clobbers (newpat, icode);
344 if (in_group)
345 validate_change (insn, &PATTERN (insn), newpat, 1);
346 else
347 PATTERN (insn) = pat = newpat;
350 /* After reload, verify that all constraints are satisfied. */
351 if (reload_completed)
353 extract_insn (insn);
355 if (! constrain_operands (1, get_preferred_alternatives (insn)))
356 return 1;
359 INSN_CODE (insn) = icode;
360 return 0;
363 /* Return number of changes made and not validated yet. */
365 num_changes_pending (void)
367 return num_changes;
370 /* Tentatively apply the changes numbered NUM and up.
371 Return 1 if all changes are valid, zero otherwise. */
374 verify_changes (int num)
376 int i;
377 rtx last_validated = NULL_RTX;
379 /* The changes have been applied and all INSN_CODEs have been reset to force
380 rerecognition.
382 The changes are valid if we aren't given an object, or if we are
383 given a MEM and it still is a valid address, or if this is in insn
384 and it is recognized. In the latter case, if reload has completed,
385 we also require that the operands meet the constraints for
386 the insn. */
388 for (i = num; i < num_changes; i++)
390 rtx object = changes[i].object;
392 /* If there is no object to test or if it is the same as the one we
393 already tested, ignore it. */
394 if (object == 0 || object == last_validated)
395 continue;
397 if (MEM_P (object))
399 if (! memory_address_addr_space_p (GET_MODE (object),
400 XEXP (object, 0),
401 MEM_ADDR_SPACE (object)))
402 break;
404 else if (/* changes[i].old might be zero, e.g. when putting a
405 REG_FRAME_RELATED_EXPR into a previously empty list. */
406 changes[i].old
407 && REG_P (changes[i].old)
408 && asm_noperands (PATTERN (object)) > 0
409 && REG_EXPR (changes[i].old) != NULL_TREE
410 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
411 && DECL_REGISTER (REG_EXPR (changes[i].old)))
413 /* Don't allow changes of hard register operands to inline
414 assemblies if they have been defined as register asm ("x"). */
415 break;
417 else if (DEBUG_INSN_P (object))
418 continue;
419 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
421 rtx pat = PATTERN (object);
423 /* Perhaps we couldn't recognize the insn because there were
424 extra CLOBBERs at the end. If so, try to re-recognize
425 without the last CLOBBER (later iterations will cause each of
426 them to be eliminated, in turn). But don't do this if we
427 have an ASM_OPERAND. */
428 if (GET_CODE (pat) == PARALLEL
429 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
430 && asm_noperands (PATTERN (object)) < 0)
432 rtx newpat;
434 if (XVECLEN (pat, 0) == 2)
435 newpat = XVECEXP (pat, 0, 0);
436 else
438 int j;
440 newpat
441 = gen_rtx_PARALLEL (VOIDmode,
442 rtvec_alloc (XVECLEN (pat, 0) - 1));
443 for (j = 0; j < XVECLEN (newpat, 0); j++)
444 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
447 /* Add a new change to this group to replace the pattern
448 with this new pattern. Then consider this change
449 as having succeeded. The change we added will
450 cause the entire call to fail if things remain invalid.
452 Note that this can lose if a later change than the one
453 we are processing specified &XVECEXP (PATTERN (object), 0, X)
454 but this shouldn't occur. */
456 validate_change (object, &PATTERN (object), newpat, 1);
457 continue;
459 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
460 || GET_CODE (pat) == VAR_LOCATION)
461 /* If this insn is a CLOBBER or USE, it is always valid, but is
462 never recognized. */
463 continue;
464 else
465 break;
467 last_validated = object;
470 return (i == num_changes);
473 /* A group of changes has previously been issued with validate_change
474 and verified with verify_changes. Call df_insn_rescan for each of
475 the insn changed and clear num_changes. */
477 void
478 confirm_change_group (void)
480 int i;
481 rtx last_object = NULL;
483 for (i = 0; i < num_changes; i++)
485 rtx object = changes[i].object;
487 if (changes[i].unshare)
488 *changes[i].loc = copy_rtx (*changes[i].loc);
490 /* Avoid unnecessary rescanning when multiple changes to same instruction
491 are made. */
492 if (object)
494 if (object != last_object && last_object && INSN_P (last_object))
495 df_insn_rescan (as_a <rtx_insn *> (last_object));
496 last_object = object;
500 if (last_object && INSN_P (last_object))
501 df_insn_rescan (as_a <rtx_insn *> (last_object));
502 num_changes = 0;
505 /* Apply a group of changes previously issued with `validate_change'.
506 If all changes are valid, call confirm_change_group and return 1,
507 otherwise, call cancel_changes and return 0. */
510 apply_change_group (void)
512 if (verify_changes (0))
514 confirm_change_group ();
515 return 1;
517 else
519 cancel_changes (0);
520 return 0;
525 /* Return the number of changes so far in the current group. */
528 num_validated_changes (void)
530 return num_changes;
533 /* Retract the changes numbered NUM and up. */
535 void
536 cancel_changes (int num)
538 int i;
540 /* Back out all the changes. Do this in the opposite order in which
541 they were made. */
542 for (i = num_changes - 1; i >= num; i--)
544 *changes[i].loc = changes[i].old;
545 if (changes[i].object && !MEM_P (changes[i].object))
546 INSN_CODE (changes[i].object) = changes[i].old_code;
548 num_changes = num;
551 /* Reduce conditional compilation elsewhere. */
552 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
553 rtx. */
555 static void
556 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
557 machine_mode op0_mode)
559 rtx x = *loc;
560 enum rtx_code code = GET_CODE (x);
561 rtx new_rtx = NULL_RTX;
563 if (SWAPPABLE_OPERANDS_P (x)
564 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
566 validate_unshare_change (object, loc,
567 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
568 : swap_condition (code),
569 GET_MODE (x), XEXP (x, 1),
570 XEXP (x, 0)), 1);
571 x = *loc;
572 code = GET_CODE (x);
575 /* Canonicalize arithmetics with all constant operands. */
576 switch (GET_RTX_CLASS (code))
578 case RTX_UNARY:
579 if (CONSTANT_P (XEXP (x, 0)))
580 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
581 op0_mode);
582 break;
583 case RTX_COMM_ARITH:
584 case RTX_BIN_ARITH:
585 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
586 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
587 XEXP (x, 1));
588 break;
589 case RTX_COMPARE:
590 case RTX_COMM_COMPARE:
591 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
592 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
593 XEXP (x, 0), XEXP (x, 1));
594 break;
595 default:
596 break;
598 if (new_rtx)
600 validate_change (object, loc, new_rtx, 1);
601 return;
604 switch (code)
606 case PLUS:
607 /* If we have a PLUS whose second operand is now a CONST_INT, use
608 simplify_gen_binary to try to simplify it.
609 ??? We may want later to remove this, once simplification is
610 separated from this function. */
611 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
612 validate_change (object, loc,
613 simplify_gen_binary
614 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
615 break;
616 case MINUS:
617 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
618 validate_change (object, loc,
619 simplify_gen_binary
620 (PLUS, GET_MODE (x), XEXP (x, 0),
621 simplify_gen_unary (NEG,
622 GET_MODE (x), XEXP (x, 1),
623 GET_MODE (x))), 1);
624 break;
625 case ZERO_EXTEND:
626 case SIGN_EXTEND:
627 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
629 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
630 op0_mode);
631 /* If any of the above failed, substitute in something that
632 we know won't be recognized. */
633 if (!new_rtx)
634 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
635 validate_change (object, loc, new_rtx, 1);
637 break;
638 case SUBREG:
639 /* All subregs possible to simplify should be simplified. */
640 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
641 SUBREG_BYTE (x));
643 /* Subregs of VOIDmode operands are incorrect. */
644 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
645 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
646 if (new_rtx)
647 validate_change (object, loc, new_rtx, 1);
648 break;
649 case ZERO_EXTRACT:
650 case SIGN_EXTRACT:
651 /* If we are replacing a register with memory, try to change the memory
652 to be the mode required for memory in extract operations (this isn't
653 likely to be an insertion operation; if it was, nothing bad will
654 happen, we might just fail in some cases). */
656 if (MEM_P (XEXP (x, 0))
657 && CONST_INT_P (XEXP (x, 1))
658 && CONST_INT_P (XEXP (x, 2))
659 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
660 MEM_ADDR_SPACE (XEXP (x, 0)))
661 && !MEM_VOLATILE_P (XEXP (x, 0)))
663 machine_mode wanted_mode = VOIDmode;
664 machine_mode is_mode = GET_MODE (XEXP (x, 0));
665 int pos = INTVAL (XEXP (x, 2));
667 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
669 wanted_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
670 if (wanted_mode == VOIDmode)
671 wanted_mode = word_mode;
673 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
675 wanted_mode = insn_data[targetm.code_for_extv].operand[1].mode;
676 if (wanted_mode == VOIDmode)
677 wanted_mode = word_mode;
680 /* If we have a narrower mode, we can do something. */
681 if (wanted_mode != VOIDmode
682 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
684 int offset = pos / BITS_PER_UNIT;
685 rtx newmem;
687 /* If the bytes and bits are counted differently, we
688 must adjust the offset. */
689 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
690 offset =
691 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
692 offset);
694 gcc_assert (GET_MODE_PRECISION (wanted_mode)
695 == GET_MODE_BITSIZE (wanted_mode));
696 pos %= GET_MODE_BITSIZE (wanted_mode);
698 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
700 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
701 validate_change (object, &XEXP (x, 0), newmem, 1);
705 break;
707 default:
708 break;
712 /* Replace every occurrence of FROM in X with TO. Mark each change with
713 validate_change passing OBJECT. */
715 static void
716 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
717 bool simplify)
719 int i, j;
720 const char *fmt;
721 rtx x = *loc;
722 enum rtx_code code;
723 machine_mode op0_mode = VOIDmode;
724 int prev_changes = num_changes;
726 if (!x)
727 return;
729 code = GET_CODE (x);
730 fmt = GET_RTX_FORMAT (code);
731 if (fmt[0] == 'e')
732 op0_mode = GET_MODE (XEXP (x, 0));
734 /* X matches FROM if it is the same rtx or they are both referring to the
735 same register in the same mode. Avoid calling rtx_equal_p unless the
736 operands look similar. */
738 if (x == from
739 || (REG_P (x) && REG_P (from)
740 && GET_MODE (x) == GET_MODE (from)
741 && REGNO (x) == REGNO (from))
742 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
743 && rtx_equal_p (x, from)))
745 validate_unshare_change (object, loc, to, 1);
746 return;
749 /* Call ourself recursively to perform the replacements.
750 We must not replace inside already replaced expression, otherwise we
751 get infinite recursion for replacements like (reg X)->(subreg (reg X))
752 so we must special case shared ASM_OPERANDS. */
754 if (GET_CODE (x) == PARALLEL)
756 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
758 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
759 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
761 /* Verify that operands are really shared. */
762 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
763 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
764 (x, 0, j))));
765 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
766 from, to, object, simplify);
768 else
769 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
770 simplify);
773 else
774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
776 if (fmt[i] == 'e')
777 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
778 else if (fmt[i] == 'E')
779 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
780 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
781 simplify);
784 /* If we didn't substitute, there is nothing more to do. */
785 if (num_changes == prev_changes)
786 return;
788 /* ??? The regmove is no more, so is this aberration still necessary? */
789 /* Allow substituted expression to have different mode. This is used by
790 regmove to change mode of pseudo register. */
791 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
792 op0_mode = GET_MODE (XEXP (x, 0));
794 /* Do changes needed to keep rtx consistent. Don't do any other
795 simplifications, as it is not our job. */
796 if (simplify)
797 simplify_while_replacing (loc, to, object, op0_mode);
800 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
801 with TO. After all changes have been made, validate by seeing
802 if INSN is still valid. */
805 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
807 validate_replace_rtx_1 (loc, from, to, insn, true);
808 return apply_change_group ();
811 /* Try replacing every occurrence of FROM in INSN with TO. After all
812 changes have been made, validate by seeing if INSN is still valid. */
815 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
817 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
818 return apply_change_group ();
821 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
822 is a part of INSN. After all changes have been made, validate by seeing if
823 INSN is still valid.
824 validate_replace_rtx (from, to, insn) is equivalent to
825 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
828 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
830 validate_replace_rtx_1 (where, from, to, insn, true);
831 return apply_change_group ();
834 /* Same as above, but do not simplify rtx afterwards. */
836 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
837 rtx_insn *insn)
839 validate_replace_rtx_1 (where, from, to, insn, false);
840 return apply_change_group ();
844 /* Try replacing every occurrence of FROM in INSN with TO. This also
845 will replace in REG_EQUAL and REG_EQUIV notes. */
847 void
848 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
850 rtx note;
851 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
852 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
853 if (REG_NOTE_KIND (note) == REG_EQUAL
854 || REG_NOTE_KIND (note) == REG_EQUIV)
855 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
858 /* Function called by note_uses to replace used subexpressions. */
859 struct validate_replace_src_data
861 rtx from; /* Old RTX */
862 rtx to; /* New RTX */
863 rtx_insn *insn; /* Insn in which substitution is occurring. */
866 static void
867 validate_replace_src_1 (rtx *x, void *data)
869 struct validate_replace_src_data *d
870 = (struct validate_replace_src_data *) data;
872 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
875 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
876 SET_DESTs. */
878 void
879 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
881 struct validate_replace_src_data d;
883 d.from = from;
884 d.to = to;
885 d.insn = insn;
886 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
889 /* Try simplify INSN.
890 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
891 pattern and return true if something was simplified. */
893 bool
894 validate_simplify_insn (rtx_insn *insn)
896 int i;
897 rtx pat = NULL;
898 rtx newpat = NULL;
900 pat = PATTERN (insn);
902 if (GET_CODE (pat) == SET)
904 newpat = simplify_rtx (SET_SRC (pat));
905 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
906 validate_change (insn, &SET_SRC (pat), newpat, 1);
907 newpat = simplify_rtx (SET_DEST (pat));
908 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
909 validate_change (insn, &SET_DEST (pat), newpat, 1);
911 else if (GET_CODE (pat) == PARALLEL)
912 for (i = 0; i < XVECLEN (pat, 0); i++)
914 rtx s = XVECEXP (pat, 0, i);
916 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
918 newpat = simplify_rtx (SET_SRC (s));
919 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
920 validate_change (insn, &SET_SRC (s), newpat, 1);
921 newpat = simplify_rtx (SET_DEST (s));
922 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
923 validate_change (insn, &SET_DEST (s), newpat, 1);
926 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
929 /* Return 1 if the insn using CC0 set by INSN does not contain
930 any ordered tests applied to the condition codes.
931 EQ and NE tests do not count. */
934 next_insn_tests_no_inequality (rtx_insn *insn)
936 rtx_insn *next = next_cc0_user (insn);
938 /* If there is no next insn, we have to take the conservative choice. */
939 if (next == 0)
940 return 0;
942 return (INSN_P (next)
943 && ! inequality_comparisons_p (PATTERN (next)));
946 /* Return 1 if OP is a valid general operand for machine mode MODE.
947 This is either a register reference, a memory reference,
948 or a constant. In the case of a memory reference, the address
949 is checked for general validity for the target machine.
951 Register and memory references must have mode MODE in order to be valid,
952 but some constants have no machine mode and are valid for any mode.
954 If MODE is VOIDmode, OP is checked for validity for whatever mode
955 it has.
957 The main use of this function is as a predicate in match_operand
958 expressions in the machine description. */
961 general_operand (rtx op, machine_mode mode)
963 enum rtx_code code = GET_CODE (op);
965 if (mode == VOIDmode)
966 mode = GET_MODE (op);
968 /* Don't accept CONST_INT or anything similar
969 if the caller wants something floating. */
970 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
971 && GET_MODE_CLASS (mode) != MODE_INT
972 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
973 return 0;
975 if (CONST_INT_P (op)
976 && mode != VOIDmode
977 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
978 return 0;
980 if (CONSTANT_P (op))
981 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
982 || mode == VOIDmode)
983 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
984 && targetm.legitimate_constant_p (mode == VOIDmode
985 ? GET_MODE (op)
986 : mode, op));
988 /* Except for certain constants with VOIDmode, already checked for,
989 OP's mode must match MODE if MODE specifies a mode. */
991 if (GET_MODE (op) != mode)
992 return 0;
994 if (code == SUBREG)
996 rtx sub = SUBREG_REG (op);
998 #ifdef INSN_SCHEDULING
999 /* On machines that have insn scheduling, we want all memory
1000 reference to be explicit, so outlaw paradoxical SUBREGs.
1001 However, we must allow them after reload so that they can
1002 get cleaned up by cleanup_subreg_operands. */
1003 if (!reload_completed && MEM_P (sub)
1004 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
1005 return 0;
1006 #endif
1007 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1008 may result in incorrect reference. We should simplify all valid
1009 subregs of MEM anyway. But allow this after reload because we
1010 might be called from cleanup_subreg_operands.
1012 ??? This is a kludge. */
1013 if (!reload_completed && SUBREG_BYTE (op) != 0
1014 && MEM_P (sub))
1015 return 0;
1017 #ifdef CANNOT_CHANGE_MODE_CLASS
1018 if (REG_P (sub)
1019 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1020 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1021 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1022 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1023 /* LRA can generate some invalid SUBREGS just for matched
1024 operand reload presentation. LRA needs to treat them as
1025 valid. */
1026 && ! LRA_SUBREG_P (op))
1027 return 0;
1028 #endif
1030 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1031 create such rtl, and we must reject it. */
1032 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1033 /* LRA can use subreg to store a floating point value in an
1034 integer mode. Although the floating point and the
1035 integer modes need the same number of hard registers, the
1036 size of floating point mode can be less than the integer
1037 mode. */
1038 && ! lra_in_progress
1039 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1040 return 0;
1042 op = sub;
1043 code = GET_CODE (op);
1046 if (code == REG)
1047 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1048 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
1050 if (code == MEM)
1052 rtx y = XEXP (op, 0);
1054 if (! volatile_ok && MEM_VOLATILE_P (op))
1055 return 0;
1057 /* Use the mem's mode, since it will be reloaded thus. LRA can
1058 generate move insn with invalid addresses which is made valid
1059 and efficiently calculated by LRA through further numerous
1060 transformations. */
1061 if (lra_in_progress
1062 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
1063 return 1;
1066 return 0;
1069 /* Return 1 if OP is a valid memory address for a memory reference
1070 of mode MODE.
1072 The main use of this function is as a predicate in match_operand
1073 expressions in the machine description. */
1076 address_operand (rtx op, machine_mode mode)
1078 return memory_address_p (mode, op);
1081 /* Return 1 if OP is a register reference of mode MODE.
1082 If MODE is VOIDmode, accept a register in any mode.
1084 The main use of this function is as a predicate in match_operand
1085 expressions in the machine description. */
1088 register_operand (rtx op, machine_mode mode)
1090 if (GET_CODE (op) == SUBREG)
1092 rtx sub = SUBREG_REG (op);
1094 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1095 because it is guaranteed to be reloaded into one.
1096 Just make sure the MEM is valid in itself.
1097 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1098 but currently it does result from (SUBREG (REG)...) where the
1099 reg went on the stack.) */
1100 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1101 return 0;
1103 else if (!REG_P (op))
1104 return 0;
1105 return general_operand (op, mode);
1108 /* Return 1 for a register in Pmode; ignore the tested mode. */
1111 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1113 return register_operand (op, Pmode);
1116 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1117 or a hard register. */
1120 scratch_operand (rtx op, machine_mode mode)
1122 if (GET_MODE (op) != mode && mode != VOIDmode)
1123 return 0;
1125 return (GET_CODE (op) == SCRATCH
1126 || (REG_P (op)
1127 && (lra_in_progress
1128 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1129 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1132 /* Return 1 if OP is a valid immediate operand for mode MODE.
1134 The main use of this function is as a predicate in match_operand
1135 expressions in the machine description. */
1138 immediate_operand (rtx op, machine_mode mode)
1140 /* Don't accept CONST_INT or anything similar
1141 if the caller wants something floating. */
1142 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1143 && GET_MODE_CLASS (mode) != MODE_INT
1144 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1145 return 0;
1147 if (CONST_INT_P (op)
1148 && mode != VOIDmode
1149 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1150 return 0;
1152 return (CONSTANT_P (op)
1153 && (GET_MODE (op) == mode || mode == VOIDmode
1154 || GET_MODE (op) == VOIDmode)
1155 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1156 && targetm.legitimate_constant_p (mode == VOIDmode
1157 ? GET_MODE (op)
1158 : mode, op));
1161 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1164 const_int_operand (rtx op, machine_mode mode)
1166 if (!CONST_INT_P (op))
1167 return 0;
1169 if (mode != VOIDmode
1170 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1171 return 0;
1173 return 1;
1176 #if TARGET_SUPPORTS_WIDE_INT
1177 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1178 of mode MODE. */
1180 const_scalar_int_operand (rtx op, machine_mode mode)
1182 if (!CONST_SCALAR_INT_P (op))
1183 return 0;
1185 if (CONST_INT_P (op))
1186 return const_int_operand (op, mode);
1188 if (mode != VOIDmode)
1190 int prec = GET_MODE_PRECISION (mode);
1191 int bitsize = GET_MODE_BITSIZE (mode);
1193 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1194 return 0;
1196 if (prec == bitsize)
1197 return 1;
1198 else
1200 /* Multiword partial int. */
1201 HOST_WIDE_INT x
1202 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1203 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1206 return 1;
1209 /* Returns 1 if OP is an operand that is a constant integer or constant
1210 floating-point number of MODE. */
1213 const_double_operand (rtx op, machine_mode mode)
1215 return (GET_CODE (op) == CONST_DOUBLE)
1216 && (GET_MODE (op) == mode || mode == VOIDmode);
1218 #else
1219 /* Returns 1 if OP is an operand that is a constant integer or constant
1220 floating-point number of MODE. */
1223 const_double_operand (rtx op, machine_mode mode)
1225 /* Don't accept CONST_INT or anything similar
1226 if the caller wants something floating. */
1227 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1228 && GET_MODE_CLASS (mode) != MODE_INT
1229 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1230 return 0;
1232 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1233 && (mode == VOIDmode || GET_MODE (op) == mode
1234 || GET_MODE (op) == VOIDmode));
1236 #endif
1237 /* Return 1 if OP is a general operand that is not an immediate
1238 operand of mode MODE. */
1241 nonimmediate_operand (rtx op, machine_mode mode)
1243 return (general_operand (op, mode) && ! CONSTANT_P (op));
1246 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1249 nonmemory_operand (rtx op, machine_mode mode)
1251 if (CONSTANT_P (op))
1252 return immediate_operand (op, mode);
1253 return register_operand (op, mode);
1256 /* Return 1 if OP is a valid operand that stands for pushing a
1257 value of mode MODE onto the stack.
1259 The main use of this function is as a predicate in match_operand
1260 expressions in the machine description. */
1263 push_operand (rtx op, machine_mode mode)
1265 unsigned int rounded_size = GET_MODE_SIZE (mode);
1267 #ifdef PUSH_ROUNDING
1268 rounded_size = PUSH_ROUNDING (rounded_size);
1269 #endif
1271 if (!MEM_P (op))
1272 return 0;
1274 if (mode != VOIDmode && GET_MODE (op) != mode)
1275 return 0;
1277 op = XEXP (op, 0);
1279 if (rounded_size == GET_MODE_SIZE (mode))
1281 if (GET_CODE (op) != STACK_PUSH_CODE)
1282 return 0;
1284 else
1286 if (GET_CODE (op) != PRE_MODIFY
1287 || GET_CODE (XEXP (op, 1)) != PLUS
1288 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1289 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1290 || INTVAL (XEXP (XEXP (op, 1), 1))
1291 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1292 return 0;
1295 return XEXP (op, 0) == stack_pointer_rtx;
1298 /* Return 1 if OP is a valid operand that stands for popping a
1299 value of mode MODE off the stack.
1301 The main use of this function is as a predicate in match_operand
1302 expressions in the machine description. */
1305 pop_operand (rtx op, machine_mode mode)
1307 if (!MEM_P (op))
1308 return 0;
1310 if (mode != VOIDmode && GET_MODE (op) != mode)
1311 return 0;
1313 op = XEXP (op, 0);
1315 if (GET_CODE (op) != STACK_POP_CODE)
1316 return 0;
1318 return XEXP (op, 0) == stack_pointer_rtx;
1321 /* Return 1 if ADDR is a valid memory address
1322 for mode MODE in address space AS. */
1325 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1326 rtx addr, addr_space_t as)
1328 #ifdef GO_IF_LEGITIMATE_ADDRESS
1329 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1330 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1331 return 0;
1333 win:
1334 return 1;
1335 #else
1336 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1337 #endif
1340 /* Return 1 if OP is a valid memory reference with mode MODE,
1341 including a valid address.
1343 The main use of this function is as a predicate in match_operand
1344 expressions in the machine description. */
1347 memory_operand (rtx op, machine_mode mode)
1349 rtx inner;
1351 if (! reload_completed)
1352 /* Note that no SUBREG is a memory operand before end of reload pass,
1353 because (SUBREG (MEM...)) forces reloading into a register. */
1354 return MEM_P (op) && general_operand (op, mode);
1356 if (mode != VOIDmode && GET_MODE (op) != mode)
1357 return 0;
1359 inner = op;
1360 if (GET_CODE (inner) == SUBREG)
1361 inner = SUBREG_REG (inner);
1363 return (MEM_P (inner) && general_operand (op, mode));
1366 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1367 that is, a memory reference whose address is a general_operand. */
1370 indirect_operand (rtx op, machine_mode mode)
1372 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1373 if (! reload_completed
1374 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1376 int offset = SUBREG_BYTE (op);
1377 rtx inner = SUBREG_REG (op);
1379 if (mode != VOIDmode && GET_MODE (op) != mode)
1380 return 0;
1382 /* The only way that we can have a general_operand as the resulting
1383 address is if OFFSET is zero and the address already is an operand
1384 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1385 operand. */
1387 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1388 || (GET_CODE (XEXP (inner, 0)) == PLUS
1389 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1390 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1391 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1394 return (MEM_P (op)
1395 && memory_operand (op, mode)
1396 && general_operand (XEXP (op, 0), Pmode));
1399 /* Return 1 if this is an ordered comparison operator (not including
1400 ORDERED and UNORDERED). */
1403 ordered_comparison_operator (rtx op, machine_mode mode)
1405 if (mode != VOIDmode && GET_MODE (op) != mode)
1406 return false;
1407 switch (GET_CODE (op))
1409 case EQ:
1410 case NE:
1411 case LT:
1412 case LTU:
1413 case LE:
1414 case LEU:
1415 case GT:
1416 case GTU:
1417 case GE:
1418 case GEU:
1419 return true;
1420 default:
1421 return false;
1425 /* Return 1 if this is a comparison operator. This allows the use of
1426 MATCH_OPERATOR to recognize all the branch insns. */
1429 comparison_operator (rtx op, machine_mode mode)
1431 return ((mode == VOIDmode || GET_MODE (op) == mode)
1432 && COMPARISON_P (op));
1435 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1438 extract_asm_operands (rtx body)
1440 rtx tmp;
1441 switch (GET_CODE (body))
1443 case ASM_OPERANDS:
1444 return body;
1446 case SET:
1447 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1448 tmp = SET_SRC (body);
1449 if (GET_CODE (tmp) == ASM_OPERANDS)
1450 return tmp;
1451 break;
1453 case PARALLEL:
1454 tmp = XVECEXP (body, 0, 0);
1455 if (GET_CODE (tmp) == ASM_OPERANDS)
1456 return tmp;
1457 if (GET_CODE (tmp) == SET)
1459 tmp = SET_SRC (tmp);
1460 if (GET_CODE (tmp) == ASM_OPERANDS)
1461 return tmp;
1463 break;
1465 default:
1466 break;
1468 return NULL;
1471 /* If BODY is an insn body that uses ASM_OPERANDS,
1472 return the number of operands (both input and output) in the insn.
1473 Otherwise return -1. */
1476 asm_noperands (const_rtx body)
1478 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1479 int n_sets = 0;
1481 if (asm_op == NULL)
1482 return -1;
1484 if (GET_CODE (body) == SET)
1485 n_sets = 1;
1486 else if (GET_CODE (body) == PARALLEL)
1488 int i;
1489 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1491 /* Multiple output operands, or 1 output plus some clobbers:
1492 body is
1493 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1494 /* Count backwards through CLOBBERs to determine number of SETs. */
1495 for (i = XVECLEN (body, 0); i > 0; i--)
1497 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1498 break;
1499 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1500 return -1;
1503 /* N_SETS is now number of output operands. */
1504 n_sets = i;
1506 /* Verify that all the SETs we have
1507 came from a single original asm_operands insn
1508 (so that invalid combinations are blocked). */
1509 for (i = 0; i < n_sets; i++)
1511 rtx elt = XVECEXP (body, 0, i);
1512 if (GET_CODE (elt) != SET)
1513 return -1;
1514 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1515 return -1;
1516 /* If these ASM_OPERANDS rtx's came from different original insns
1517 then they aren't allowed together. */
1518 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1519 != ASM_OPERANDS_INPUT_VEC (asm_op))
1520 return -1;
1523 else
1525 /* 0 outputs, but some clobbers:
1526 body is [(asm_operands ...) (clobber (reg ...))...]. */
1527 /* Make sure all the other parallel things really are clobbers. */
1528 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1529 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1530 return -1;
1534 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1535 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1538 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1539 copy its operands (both input and output) into the vector OPERANDS,
1540 the locations of the operands within the insn into the vector OPERAND_LOCS,
1541 and the constraints for the operands into CONSTRAINTS.
1542 Write the modes of the operands into MODES.
1543 Return the assembler-template.
1545 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1546 we don't store that info. */
1548 const char *
1549 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1550 const char **constraints, machine_mode *modes,
1551 location_t *loc)
1553 int nbase = 0, n, i;
1554 rtx asmop;
1556 switch (GET_CODE (body))
1558 case ASM_OPERANDS:
1559 /* Zero output asm: BODY is (asm_operands ...). */
1560 asmop = body;
1561 break;
1563 case SET:
1564 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1565 asmop = SET_SRC (body);
1567 /* The output is in the SET.
1568 Its constraint is in the ASM_OPERANDS itself. */
1569 if (operands)
1570 operands[0] = SET_DEST (body);
1571 if (operand_locs)
1572 operand_locs[0] = &SET_DEST (body);
1573 if (constraints)
1574 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1575 if (modes)
1576 modes[0] = GET_MODE (SET_DEST (body));
1577 nbase = 1;
1578 break;
1580 case PARALLEL:
1582 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1584 asmop = XVECEXP (body, 0, 0);
1585 if (GET_CODE (asmop) == SET)
1587 asmop = SET_SRC (asmop);
1589 /* At least one output, plus some CLOBBERs. The outputs are in
1590 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1591 for (i = 0; i < nparallel; i++)
1593 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1594 break; /* Past last SET */
1595 if (operands)
1596 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1597 if (operand_locs)
1598 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1599 if (constraints)
1600 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1601 if (modes)
1602 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1604 nbase = i;
1606 break;
1609 default:
1610 gcc_unreachable ();
1613 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1614 for (i = 0; i < n; i++)
1616 if (operand_locs)
1617 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1618 if (operands)
1619 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1620 if (constraints)
1621 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1622 if (modes)
1623 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1625 nbase += n;
1627 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1628 for (i = 0; i < n; i++)
1630 if (operand_locs)
1631 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1632 if (operands)
1633 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1634 if (constraints)
1635 constraints[nbase + i] = "";
1636 if (modes)
1637 modes[nbase + i] = Pmode;
1640 if (loc)
1641 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1643 return ASM_OPERANDS_TEMPLATE (asmop);
1646 /* Parse inline assembly string STRING and determine which operands are
1647 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1648 to true if operand I is referenced.
1650 This is intended to distinguish barrier-like asms such as:
1652 asm ("" : "=m" (...));
1654 from real references such as:
1656 asm ("sw\t$0, %0" : "=m" (...)); */
1658 void
1659 get_referenced_operands (const char *string, bool *used,
1660 unsigned int noperands)
1662 memset (used, 0, sizeof (bool) * noperands);
1663 const char *p = string;
1664 while (*p)
1665 switch (*p)
1667 case '%':
1668 p += 1;
1669 /* A letter followed by a digit indicates an operand number. */
1670 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1671 p += 1;
1672 if (ISDIGIT (*p))
1674 char *endptr;
1675 unsigned long opnum = strtoul (p, &endptr, 10);
1676 if (endptr != p && opnum < noperands)
1677 used[opnum] = true;
1678 p = endptr;
1680 else
1681 p += 1;
1682 break;
1684 default:
1685 p++;
1686 break;
1690 /* Check if an asm_operand matches its constraints.
1691 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1694 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1696 int result = 0;
1697 bool incdec_ok = false;
1699 /* Use constrain_operands after reload. */
1700 gcc_assert (!reload_completed);
1702 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1703 many alternatives as required to match the other operands. */
1704 if (*constraint == '\0')
1705 result = 1;
1707 while (*constraint)
1709 enum constraint_num cn;
1710 char c = *constraint;
1711 int len;
1712 switch (c)
1714 case ',':
1715 constraint++;
1716 continue;
1718 case '0': case '1': case '2': case '3': case '4':
1719 case '5': case '6': case '7': case '8': case '9':
1720 /* If caller provided constraints pointer, look up
1721 the matching constraint. Otherwise, our caller should have
1722 given us the proper matching constraint, but we can't
1723 actually fail the check if they didn't. Indicate that
1724 results are inconclusive. */
1725 if (constraints)
1727 char *end;
1728 unsigned long match;
1730 match = strtoul (constraint, &end, 10);
1731 if (!result)
1732 result = asm_operand_ok (op, constraints[match], NULL);
1733 constraint = (const char *) end;
1735 else
1738 constraint++;
1739 while (ISDIGIT (*constraint));
1740 if (! result)
1741 result = -1;
1743 continue;
1745 /* The rest of the compiler assumes that reloading the address
1746 of a MEM into a register will make it fit an 'o' constraint.
1747 That is, if it sees a MEM operand for an 'o' constraint,
1748 it assumes that (mem (base-reg)) will fit.
1750 That assumption fails on targets that don't have offsettable
1751 addresses at all. We therefore need to treat 'o' asm
1752 constraints as a special case and only accept operands that
1753 are already offsettable, thus proving that at least one
1754 offsettable address exists. */
1755 case 'o': /* offsettable */
1756 if (offsettable_nonstrict_memref_p (op))
1757 result = 1;
1758 break;
1760 case 'g':
1761 if (general_operand (op, VOIDmode))
1762 result = 1;
1763 break;
1765 case '<':
1766 case '>':
1767 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1768 to exist, excepting those that expand_call created. Further,
1769 on some machines which do not have generalized auto inc/dec,
1770 an inc/dec is not a memory_operand.
1772 Match any memory and hope things are resolved after reload. */
1773 incdec_ok = true;
1774 default:
1775 cn = lookup_constraint (constraint);
1776 switch (get_constraint_type (cn))
1778 case CT_REGISTER:
1779 if (!result
1780 && reg_class_for_constraint (cn) != NO_REGS
1781 && GET_MODE (op) != BLKmode
1782 && register_operand (op, VOIDmode))
1783 result = 1;
1784 break;
1786 case CT_CONST_INT:
1787 if (!result
1788 && CONST_INT_P (op)
1789 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1790 result = 1;
1791 break;
1793 case CT_MEMORY:
1794 case CT_SPECIAL_MEMORY:
1795 /* Every memory operand can be reloaded to fit. */
1796 result = result || memory_operand (op, VOIDmode);
1797 break;
1799 case CT_ADDRESS:
1800 /* Every address operand can be reloaded to fit. */
1801 result = result || address_operand (op, VOIDmode);
1802 break;
1804 case CT_FIXED_FORM:
1805 result = result || constraint_satisfied_p (op, cn);
1806 break;
1808 break;
1810 len = CONSTRAINT_LEN (c, constraint);
1812 constraint++;
1813 while (--len && *constraint);
1814 if (len)
1815 return 0;
1818 /* For operands without < or > constraints reject side-effects. */
1819 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1820 switch (GET_CODE (XEXP (op, 0)))
1822 case PRE_INC:
1823 case POST_INC:
1824 case PRE_DEC:
1825 case POST_DEC:
1826 case PRE_MODIFY:
1827 case POST_MODIFY:
1828 return 0;
1829 default:
1830 break;
1833 return result;
1836 /* Given an rtx *P, if it is a sum containing an integer constant term,
1837 return the location (type rtx *) of the pointer to that constant term.
1838 Otherwise, return a null pointer. */
1840 rtx *
1841 find_constant_term_loc (rtx *p)
1843 rtx *tem;
1844 enum rtx_code code = GET_CODE (*p);
1846 /* If *P IS such a constant term, P is its location. */
1848 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1849 || code == CONST)
1850 return p;
1852 /* Otherwise, if not a sum, it has no constant term. */
1854 if (GET_CODE (*p) != PLUS)
1855 return 0;
1857 /* If one of the summands is constant, return its location. */
1859 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1860 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1861 return p;
1863 /* Otherwise, check each summand for containing a constant term. */
1865 if (XEXP (*p, 0) != 0)
1867 tem = find_constant_term_loc (&XEXP (*p, 0));
1868 if (tem != 0)
1869 return tem;
1872 if (XEXP (*p, 1) != 0)
1874 tem = find_constant_term_loc (&XEXP (*p, 1));
1875 if (tem != 0)
1876 return tem;
1879 return 0;
1882 /* Return 1 if OP is a memory reference
1883 whose address contains no side effects
1884 and remains valid after the addition
1885 of a positive integer less than the
1886 size of the object being referenced.
1888 We assume that the original address is valid and do not check it.
1890 This uses strict_memory_address_p as a subroutine, so
1891 don't use it before reload. */
1894 offsettable_memref_p (rtx op)
1896 return ((MEM_P (op))
1897 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1898 MEM_ADDR_SPACE (op)));
1901 /* Similar, but don't require a strictly valid mem ref:
1902 consider pseudo-regs valid as index or base regs. */
1905 offsettable_nonstrict_memref_p (rtx op)
1907 return ((MEM_P (op))
1908 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1909 MEM_ADDR_SPACE (op)));
1912 /* Return 1 if Y is a memory address which contains no side effects
1913 and would remain valid for address space AS after the addition of
1914 a positive integer less than the size of that mode.
1916 We assume that the original address is valid and do not check it.
1917 We do check that it is valid for narrower modes.
1919 If STRICTP is nonzero, we require a strictly valid address,
1920 for the sake of use in reload.c. */
1923 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1924 addr_space_t as)
1926 enum rtx_code ycode = GET_CODE (y);
1927 rtx z;
1928 rtx y1 = y;
1929 rtx *y2;
1930 int (*addressp) (machine_mode, rtx, addr_space_t) =
1931 (strictp ? strict_memory_address_addr_space_p
1932 : memory_address_addr_space_p);
1933 unsigned int mode_sz = GET_MODE_SIZE (mode);
1935 if (CONSTANT_ADDRESS_P (y))
1936 return 1;
1938 /* Adjusting an offsettable address involves changing to a narrower mode.
1939 Make sure that's OK. */
1941 if (mode_dependent_address_p (y, as))
1942 return 0;
1944 machine_mode address_mode = GET_MODE (y);
1945 if (address_mode == VOIDmode)
1946 address_mode = targetm.addr_space.address_mode (as);
1947 #ifdef POINTERS_EXTEND_UNSIGNED
1948 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1949 #endif
1951 /* ??? How much offset does an offsettable BLKmode reference need?
1952 Clearly that depends on the situation in which it's being used.
1953 However, the current situation in which we test 0xffffffff is
1954 less than ideal. Caveat user. */
1955 if (mode_sz == 0)
1956 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1958 /* If the expression contains a constant term,
1959 see if it remains valid when max possible offset is added. */
1961 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1963 int good;
1965 y1 = *y2;
1966 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1967 /* Use QImode because an odd displacement may be automatically invalid
1968 for any wider mode. But it should be valid for a single byte. */
1969 good = (*addressp) (QImode, y, as);
1971 /* In any case, restore old contents of memory. */
1972 *y2 = y1;
1973 return good;
1976 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1977 return 0;
1979 /* The offset added here is chosen as the maximum offset that
1980 any instruction could need to add when operating on something
1981 of the specified mode. We assume that if Y and Y+c are
1982 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1983 go inside a LO_SUM here, so we do so as well. */
1984 if (GET_CODE (y) == LO_SUM
1985 && mode != BLKmode
1986 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1987 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
1988 plus_constant (address_mode, XEXP (y, 1),
1989 mode_sz - 1));
1990 #ifdef POINTERS_EXTEND_UNSIGNED
1991 /* Likewise for a ZERO_EXTEND from pointer_mode. */
1992 else if (POINTERS_EXTEND_UNSIGNED > 0
1993 && GET_CODE (y) == ZERO_EXTEND
1994 && GET_MODE (XEXP (y, 0)) == pointer_mode)
1995 z = gen_rtx_ZERO_EXTEND (address_mode,
1996 plus_constant (pointer_mode, XEXP (y, 0),
1997 mode_sz - 1));
1998 #endif
1999 else
2000 z = plus_constant (address_mode, y, mode_sz - 1);
2002 /* Use QImode because an odd displacement may be automatically invalid
2003 for any wider mode. But it should be valid for a single byte. */
2004 return (*addressp) (QImode, z, as);
2007 /* Return 1 if ADDR is an address-expression whose effect depends
2008 on the mode of the memory reference it is used in.
2010 ADDRSPACE is the address space associated with the address.
2012 Autoincrement addressing is a typical example of mode-dependence
2013 because the amount of the increment depends on the mode. */
2015 bool
2016 mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2018 /* Auto-increment addressing with anything other than post_modify
2019 or pre_modify always introduces a mode dependency. Catch such
2020 cases now instead of deferring to the target. */
2021 if (GET_CODE (addr) == PRE_INC
2022 || GET_CODE (addr) == POST_INC
2023 || GET_CODE (addr) == PRE_DEC
2024 || GET_CODE (addr) == POST_DEC)
2025 return true;
2027 return targetm.mode_dependent_address_p (addr, addrspace);
2030 /* Return true if boolean attribute ATTR is supported. */
2032 static bool
2033 have_bool_attr (bool_attr attr)
2035 switch (attr)
2037 case BA_ENABLED:
2038 return HAVE_ATTR_enabled;
2039 case BA_PREFERRED_FOR_SIZE:
2040 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2041 case BA_PREFERRED_FOR_SPEED:
2042 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2044 gcc_unreachable ();
2047 /* Return the value of ATTR for instruction INSN. */
2049 static bool
2050 get_bool_attr (rtx_insn *insn, bool_attr attr)
2052 switch (attr)
2054 case BA_ENABLED:
2055 return get_attr_enabled (insn);
2056 case BA_PREFERRED_FOR_SIZE:
2057 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2058 case BA_PREFERRED_FOR_SPEED:
2059 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2061 gcc_unreachable ();
2064 /* Like get_bool_attr_mask, but don't use the cache. */
2066 static alternative_mask
2067 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2069 /* Temporarily install enough information for get_attr_<foo> to assume
2070 that the insn operands are already cached. As above, the attribute
2071 mustn't depend on the values of operands, so we don't provide their
2072 real values here. */
2073 rtx_insn *old_insn = recog_data.insn;
2074 int old_alternative = which_alternative;
2076 recog_data.insn = insn;
2077 alternative_mask mask = ALL_ALTERNATIVES;
2078 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2079 for (int i = 0; i < n_alternatives; i++)
2081 which_alternative = i;
2082 if (!get_bool_attr (insn, attr))
2083 mask &= ~ALTERNATIVE_BIT (i);
2086 recog_data.insn = old_insn;
2087 which_alternative = old_alternative;
2088 return mask;
2091 /* Return the mask of operand alternatives that are allowed for INSN
2092 by boolean attribute ATTR. This mask depends only on INSN and on
2093 the current target; it does not depend on things like the values of
2094 operands. */
2096 static alternative_mask
2097 get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2099 /* Quick exit for asms and for targets that don't use these attributes. */
2100 int code = INSN_CODE (insn);
2101 if (code < 0 || !have_bool_attr (attr))
2102 return ALL_ALTERNATIVES;
2104 /* Calling get_attr_<foo> can be expensive, so cache the mask
2105 for speed. */
2106 if (!this_target_recog->x_bool_attr_masks[code][attr])
2107 this_target_recog->x_bool_attr_masks[code][attr]
2108 = get_bool_attr_mask_uncached (insn, attr);
2109 return this_target_recog->x_bool_attr_masks[code][attr];
2112 /* Return the set of alternatives of INSN that are allowed by the current
2113 target. */
2115 alternative_mask
2116 get_enabled_alternatives (rtx_insn *insn)
2118 return get_bool_attr_mask (insn, BA_ENABLED);
2121 /* Return the set of alternatives of INSN that are allowed by the current
2122 target and are preferred for the current size/speed optimization
2123 choice. */
2125 alternative_mask
2126 get_preferred_alternatives (rtx_insn *insn)
2128 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2129 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2130 else
2131 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2134 /* Return the set of alternatives of INSN that are allowed by the current
2135 target and are preferred for the size/speed optimization choice
2136 associated with BB. Passing a separate BB is useful if INSN has not
2137 been emitted yet or if we are considering moving it to a different
2138 block. */
2140 alternative_mask
2141 get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2143 if (optimize_bb_for_speed_p (bb))
2144 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2145 else
2146 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2149 /* Assert that the cached boolean attributes for INSN are still accurate.
2150 The backend is required to define these attributes in a way that only
2151 depends on the current target (rather than operands, compiler phase,
2152 etc.). */
2154 bool
2155 check_bool_attrs (rtx_insn *insn)
2157 int code = INSN_CODE (insn);
2158 if (code >= 0)
2159 for (int i = 0; i <= BA_LAST; ++i)
2161 enum bool_attr attr = (enum bool_attr) i;
2162 if (this_target_recog->x_bool_attr_masks[code][attr])
2163 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2164 == get_bool_attr_mask_uncached (insn, attr));
2166 return true;
2169 /* Like extract_insn, but save insn extracted and don't extract again, when
2170 called again for the same insn expecting that recog_data still contain the
2171 valid information. This is used primary by gen_attr infrastructure that
2172 often does extract insn again and again. */
2173 void
2174 extract_insn_cached (rtx_insn *insn)
2176 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2177 return;
2178 extract_insn (insn);
2179 recog_data.insn = insn;
2182 /* Do uncached extract_insn, constrain_operands and complain about failures.
2183 This should be used when extracting a pre-existing constrained instruction
2184 if the caller wants to know which alternative was chosen. */
2185 void
2186 extract_constrain_insn (rtx_insn *insn)
2188 extract_insn (insn);
2189 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2190 fatal_insn_not_found (insn);
2193 /* Do cached extract_insn, constrain_operands and complain about failures.
2194 Used by insn_attrtab. */
2195 void
2196 extract_constrain_insn_cached (rtx_insn *insn)
2198 extract_insn_cached (insn);
2199 if (which_alternative == -1
2200 && !constrain_operands (reload_completed,
2201 get_enabled_alternatives (insn)))
2202 fatal_insn_not_found (insn);
2205 /* Do cached constrain_operands on INSN and complain about failures. */
2207 constrain_operands_cached (rtx_insn *insn, int strict)
2209 if (which_alternative == -1)
2210 return constrain_operands (strict, get_enabled_alternatives (insn));
2211 else
2212 return 1;
2215 /* Analyze INSN and fill in recog_data. */
2217 void
2218 extract_insn (rtx_insn *insn)
2220 int i;
2221 int icode;
2222 int noperands;
2223 rtx body = PATTERN (insn);
2225 recog_data.n_operands = 0;
2226 recog_data.n_alternatives = 0;
2227 recog_data.n_dups = 0;
2228 recog_data.is_asm = false;
2230 switch (GET_CODE (body))
2232 case USE:
2233 case CLOBBER:
2234 case ASM_INPUT:
2235 case ADDR_VEC:
2236 case ADDR_DIFF_VEC:
2237 case VAR_LOCATION:
2238 return;
2240 case SET:
2241 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2242 goto asm_insn;
2243 else
2244 goto normal_insn;
2245 case PARALLEL:
2246 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2247 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2248 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2249 goto asm_insn;
2250 else
2251 goto normal_insn;
2252 case ASM_OPERANDS:
2253 asm_insn:
2254 recog_data.n_operands = noperands = asm_noperands (body);
2255 if (noperands >= 0)
2257 /* This insn is an `asm' with operands. */
2259 /* expand_asm_operands makes sure there aren't too many operands. */
2260 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2262 /* Now get the operand values and constraints out of the insn. */
2263 decode_asm_operands (body, recog_data.operand,
2264 recog_data.operand_loc,
2265 recog_data.constraints,
2266 recog_data.operand_mode, NULL);
2267 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2268 if (noperands > 0)
2270 const char *p = recog_data.constraints[0];
2271 recog_data.n_alternatives = 1;
2272 while (*p)
2273 recog_data.n_alternatives += (*p++ == ',');
2275 recog_data.is_asm = true;
2276 break;
2278 fatal_insn_not_found (insn);
2280 default:
2281 normal_insn:
2282 /* Ordinary insn: recognize it, get the operands via insn_extract
2283 and get the constraints. */
2285 icode = recog_memoized (insn);
2286 if (icode < 0)
2287 fatal_insn_not_found (insn);
2289 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2290 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2291 recog_data.n_dups = insn_data[icode].n_dups;
2293 insn_extract (insn);
2295 for (i = 0; i < noperands; i++)
2297 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2298 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2299 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2300 /* VOIDmode match_operands gets mode from their real operand. */
2301 if (recog_data.operand_mode[i] == VOIDmode)
2302 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2305 for (i = 0; i < noperands; i++)
2306 recog_data.operand_type[i]
2307 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2308 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2309 : OP_IN);
2311 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2313 recog_data.insn = NULL;
2314 which_alternative = -1;
2317 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2318 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2319 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2320 has N_OPERANDS entries. */
2322 void
2323 preprocess_constraints (int n_operands, int n_alternatives,
2324 const char **constraints,
2325 operand_alternative *op_alt_base)
2327 for (int i = 0; i < n_operands; i++)
2329 int j;
2330 struct operand_alternative *op_alt;
2331 const char *p = constraints[i];
2333 op_alt = op_alt_base;
2335 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2337 op_alt[i].cl = NO_REGS;
2338 op_alt[i].constraint = p;
2339 op_alt[i].matches = -1;
2340 op_alt[i].matched = -1;
2342 if (*p == '\0' || *p == ',')
2344 op_alt[i].anything_ok = 1;
2345 continue;
2348 for (;;)
2350 char c = *p;
2351 if (c == '#')
2353 c = *++p;
2354 while (c != ',' && c != '\0');
2355 if (c == ',' || c == '\0')
2357 p++;
2358 break;
2361 switch (c)
2363 case '?':
2364 op_alt[i].reject += 6;
2365 break;
2366 case '!':
2367 op_alt[i].reject += 600;
2368 break;
2369 case '&':
2370 op_alt[i].earlyclobber = 1;
2371 break;
2373 case '0': case '1': case '2': case '3': case '4':
2374 case '5': case '6': case '7': case '8': case '9':
2376 char *end;
2377 op_alt[i].matches = strtoul (p, &end, 10);
2378 op_alt[op_alt[i].matches].matched = i;
2379 p = end;
2381 continue;
2383 case 'X':
2384 op_alt[i].anything_ok = 1;
2385 break;
2387 case 'g':
2388 op_alt[i].cl =
2389 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2390 break;
2392 default:
2393 enum constraint_num cn = lookup_constraint (p);
2394 enum reg_class cl;
2395 switch (get_constraint_type (cn))
2397 case CT_REGISTER:
2398 cl = reg_class_for_constraint (cn);
2399 if (cl != NO_REGS)
2400 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2401 break;
2403 case CT_CONST_INT:
2404 break;
2406 case CT_MEMORY:
2407 case CT_SPECIAL_MEMORY:
2408 op_alt[i].memory_ok = 1;
2409 break;
2411 case CT_ADDRESS:
2412 op_alt[i].is_address = 1;
2413 op_alt[i].cl
2414 = (reg_class_subunion
2415 [(int) op_alt[i].cl]
2416 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2417 ADDRESS, SCRATCH)]);
2418 break;
2420 case CT_FIXED_FORM:
2421 break;
2423 break;
2425 p += CONSTRAINT_LEN (c, p);
2431 /* Return an array of operand_alternative instructions for
2432 instruction ICODE. */
2434 const operand_alternative *
2435 preprocess_insn_constraints (unsigned int icode)
2437 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2438 if (this_target_recog->x_op_alt[icode])
2439 return this_target_recog->x_op_alt[icode];
2441 int n_operands = insn_data[icode].n_operands;
2442 if (n_operands == 0)
2443 return 0;
2444 /* Always provide at least one alternative so that which_op_alt ()
2445 works correctly. If the instruction has 0 alternatives (i.e. all
2446 constraint strings are empty) then each operand in this alternative
2447 will have anything_ok set. */
2448 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2449 int n_entries = n_operands * n_alternatives;
2451 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2452 const char **constraints = XALLOCAVEC (const char *, n_operands);
2454 for (int i = 0; i < n_operands; ++i)
2455 constraints[i] = insn_data[icode].operand[i].constraint;
2456 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2458 this_target_recog->x_op_alt[icode] = op_alt;
2459 return op_alt;
2462 /* After calling extract_insn, you can use this function to extract some
2463 information from the constraint strings into a more usable form.
2464 The collected data is stored in recog_op_alt. */
2466 void
2467 preprocess_constraints (rtx_insn *insn)
2469 int icode = INSN_CODE (insn);
2470 if (icode >= 0)
2471 recog_op_alt = preprocess_insn_constraints (icode);
2472 else
2474 int n_operands = recog_data.n_operands;
2475 int n_alternatives = recog_data.n_alternatives;
2476 int n_entries = n_operands * n_alternatives;
2477 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2478 preprocess_constraints (n_operands, n_alternatives,
2479 recog_data.constraints, asm_op_alt);
2480 recog_op_alt = asm_op_alt;
2484 /* Check the operands of an insn against the insn's operand constraints
2485 and return 1 if they match any of the alternatives in ALTERNATIVES.
2487 The information about the insn's operands, constraints, operand modes
2488 etc. is obtained from the global variables set up by extract_insn.
2490 WHICH_ALTERNATIVE is set to a number which indicates which
2491 alternative of constraints was matched: 0 for the first alternative,
2492 1 for the next, etc.
2494 In addition, when two operands are required to match
2495 and it happens that the output operand is (reg) while the
2496 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2497 make the output operand look like the input.
2498 This is because the output operand is the one the template will print.
2500 This is used in final, just before printing the assembler code and by
2501 the routines that determine an insn's attribute.
2503 If STRICT is a positive nonzero value, it means that we have been
2504 called after reload has been completed. In that case, we must
2505 do all checks strictly. If it is zero, it means that we have been called
2506 before reload has completed. In that case, we first try to see if we can
2507 find an alternative that matches strictly. If not, we try again, this
2508 time assuming that reload will fix up the insn. This provides a "best
2509 guess" for the alternative and is used to compute attributes of insns prior
2510 to reload. A negative value of STRICT is used for this internal call. */
2512 struct funny_match
2514 int this_op, other;
2518 constrain_operands (int strict, alternative_mask alternatives)
2520 const char *constraints[MAX_RECOG_OPERANDS];
2521 int matching_operands[MAX_RECOG_OPERANDS];
2522 int earlyclobber[MAX_RECOG_OPERANDS];
2523 int c;
2525 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2526 int funny_match_index;
2528 which_alternative = 0;
2529 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2530 return 1;
2532 for (c = 0; c < recog_data.n_operands; c++)
2534 constraints[c] = recog_data.constraints[c];
2535 matching_operands[c] = -1;
2540 int seen_earlyclobber_at = -1;
2541 int opno;
2542 int lose = 0;
2543 funny_match_index = 0;
2545 if (!TEST_BIT (alternatives, which_alternative))
2547 int i;
2549 for (i = 0; i < recog_data.n_operands; i++)
2550 constraints[i] = skip_alternative (constraints[i]);
2552 which_alternative++;
2553 continue;
2556 for (opno = 0; opno < recog_data.n_operands; opno++)
2558 rtx op = recog_data.operand[opno];
2559 machine_mode mode = GET_MODE (op);
2560 const char *p = constraints[opno];
2561 int offset = 0;
2562 int win = 0;
2563 int val;
2564 int len;
2566 earlyclobber[opno] = 0;
2568 /* A unary operator may be accepted by the predicate, but it
2569 is irrelevant for matching constraints. */
2570 if (UNARY_P (op))
2571 op = XEXP (op, 0);
2573 if (GET_CODE (op) == SUBREG)
2575 if (REG_P (SUBREG_REG (op))
2576 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2577 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2578 GET_MODE (SUBREG_REG (op)),
2579 SUBREG_BYTE (op),
2580 GET_MODE (op));
2581 op = SUBREG_REG (op);
2584 /* An empty constraint or empty alternative
2585 allows anything which matched the pattern. */
2586 if (*p == 0 || *p == ',')
2587 win = 1;
2590 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2592 case '\0':
2593 len = 0;
2594 break;
2595 case ',':
2596 c = '\0';
2597 break;
2599 case '#':
2600 /* Ignore rest of this alternative as far as
2601 constraint checking is concerned. */
2603 p++;
2604 while (*p && *p != ',');
2605 len = 0;
2606 break;
2608 case '&':
2609 earlyclobber[opno] = 1;
2610 if (seen_earlyclobber_at < 0)
2611 seen_earlyclobber_at = opno;
2612 break;
2614 case '0': case '1': case '2': case '3': case '4':
2615 case '5': case '6': case '7': case '8': case '9':
2617 /* This operand must be the same as a previous one.
2618 This kind of constraint is used for instructions such
2619 as add when they take only two operands.
2621 Note that the lower-numbered operand is passed first.
2623 If we are not testing strictly, assume that this
2624 constraint will be satisfied. */
2626 char *end;
2627 int match;
2629 match = strtoul (p, &end, 10);
2630 p = end;
2632 if (strict < 0)
2633 val = 1;
2634 else
2636 rtx op1 = recog_data.operand[match];
2637 rtx op2 = recog_data.operand[opno];
2639 /* A unary operator may be accepted by the predicate,
2640 but it is irrelevant for matching constraints. */
2641 if (UNARY_P (op1))
2642 op1 = XEXP (op1, 0);
2643 if (UNARY_P (op2))
2644 op2 = XEXP (op2, 0);
2646 val = operands_match_p (op1, op2);
2649 matching_operands[opno] = match;
2650 matching_operands[match] = opno;
2652 if (val != 0)
2653 win = 1;
2655 /* If output is *x and input is *--x, arrange later
2656 to change the output to *--x as well, since the
2657 output op is the one that will be printed. */
2658 if (val == 2 && strict > 0)
2660 funny_match[funny_match_index].this_op = opno;
2661 funny_match[funny_match_index++].other = match;
2664 len = 0;
2665 break;
2667 case 'p':
2668 /* p is used for address_operands. When we are called by
2669 gen_reload, no one will have checked that the address is
2670 strictly valid, i.e., that all pseudos requiring hard regs
2671 have gotten them. */
2672 if (strict <= 0
2673 || (strict_memory_address_p (recog_data.operand_mode[opno],
2674 op)))
2675 win = 1;
2676 break;
2678 /* No need to check general_operand again;
2679 it was done in insn-recog.c. Well, except that reload
2680 doesn't check the validity of its replacements, but
2681 that should only matter when there's a bug. */
2682 case 'g':
2683 /* Anything goes unless it is a REG and really has a hard reg
2684 but the hard reg is not in the class GENERAL_REGS. */
2685 if (REG_P (op))
2687 if (strict < 0
2688 || GENERAL_REGS == ALL_REGS
2689 || (reload_in_progress
2690 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2691 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2692 win = 1;
2694 else if (strict < 0 || general_operand (op, mode))
2695 win = 1;
2696 break;
2698 default:
2700 enum constraint_num cn = lookup_constraint (p);
2701 enum reg_class cl = reg_class_for_constraint (cn);
2702 if (cl != NO_REGS)
2704 if (strict < 0
2705 || (strict == 0
2706 && REG_P (op)
2707 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2708 || (strict == 0 && GET_CODE (op) == SCRATCH)
2709 || (REG_P (op)
2710 && reg_fits_class_p (op, cl, offset, mode)))
2711 win = 1;
2714 else if (constraint_satisfied_p (op, cn))
2715 win = 1;
2717 else if (insn_extra_memory_constraint (cn)
2718 /* Every memory operand can be reloaded to fit. */
2719 && ((strict < 0 && MEM_P (op))
2720 /* Before reload, accept what reload can turn
2721 into a mem. */
2722 || (strict < 0 && CONSTANT_P (op))
2723 /* Before reload, accept a pseudo,
2724 since LRA can turn it into a mem. */
2725 || (strict < 0 && targetm.lra_p () && REG_P (op)
2726 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2727 /* During reload, accept a pseudo */
2728 || (reload_in_progress && REG_P (op)
2729 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2730 win = 1;
2731 else if (insn_extra_address_constraint (cn)
2732 /* Every address operand can be reloaded to fit. */
2733 && strict < 0)
2734 win = 1;
2735 /* Cater to architectures like IA-64 that define extra memory
2736 constraints without using define_memory_constraint. */
2737 else if (reload_in_progress
2738 && REG_P (op)
2739 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2740 && reg_renumber[REGNO (op)] < 0
2741 && reg_equiv_mem (REGNO (op)) != 0
2742 && constraint_satisfied_p
2743 (reg_equiv_mem (REGNO (op)), cn))
2744 win = 1;
2745 break;
2748 while (p += len, c);
2750 constraints[opno] = p;
2751 /* If this operand did not win somehow,
2752 this alternative loses. */
2753 if (! win)
2754 lose = 1;
2756 /* This alternative won; the operands are ok.
2757 Change whichever operands this alternative says to change. */
2758 if (! lose)
2760 int opno, eopno;
2762 /* See if any earlyclobber operand conflicts with some other
2763 operand. */
2765 if (strict > 0 && seen_earlyclobber_at >= 0)
2766 for (eopno = seen_earlyclobber_at;
2767 eopno < recog_data.n_operands;
2768 eopno++)
2769 /* Ignore earlyclobber operands now in memory,
2770 because we would often report failure when we have
2771 two memory operands, one of which was formerly a REG. */
2772 if (earlyclobber[eopno]
2773 && REG_P (recog_data.operand[eopno]))
2774 for (opno = 0; opno < recog_data.n_operands; opno++)
2775 if ((MEM_P (recog_data.operand[opno])
2776 || recog_data.operand_type[opno] != OP_OUT)
2777 && opno != eopno
2778 /* Ignore things like match_operator operands. */
2779 && *recog_data.constraints[opno] != 0
2780 && ! (matching_operands[opno] == eopno
2781 && operands_match_p (recog_data.operand[opno],
2782 recog_data.operand[eopno]))
2783 && ! safe_from_earlyclobber (recog_data.operand[opno],
2784 recog_data.operand[eopno]))
2785 lose = 1;
2787 if (! lose)
2789 while (--funny_match_index >= 0)
2791 recog_data.operand[funny_match[funny_match_index].other]
2792 = recog_data.operand[funny_match[funny_match_index].this_op];
2795 /* For operands without < or > constraints reject side-effects. */
2796 if (AUTO_INC_DEC && recog_data.is_asm)
2798 for (opno = 0; opno < recog_data.n_operands; opno++)
2799 if (MEM_P (recog_data.operand[opno]))
2800 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2802 case PRE_INC:
2803 case POST_INC:
2804 case PRE_DEC:
2805 case POST_DEC:
2806 case PRE_MODIFY:
2807 case POST_MODIFY:
2808 if (strchr (recog_data.constraints[opno], '<') == NULL
2809 && strchr (recog_data.constraints[opno], '>')
2810 == NULL)
2811 return 0;
2812 break;
2813 default:
2814 break;
2818 return 1;
2822 which_alternative++;
2824 while (which_alternative < recog_data.n_alternatives);
2826 which_alternative = -1;
2827 /* If we are about to reject this, but we are not to test strictly,
2828 try a very loose test. Only return failure if it fails also. */
2829 if (strict == 0)
2830 return constrain_operands (-1, alternatives);
2831 else
2832 return 0;
2835 /* Return true iff OPERAND (assumed to be a REG rtx)
2836 is a hard reg in class CLASS when its regno is offset by OFFSET
2837 and changed to mode MODE.
2838 If REG occupies multiple hard regs, all of them must be in CLASS. */
2840 bool
2841 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2842 machine_mode mode)
2844 unsigned int regno = REGNO (operand);
2846 if (cl == NO_REGS)
2847 return false;
2849 /* Regno must not be a pseudo register. Offset may be negative. */
2850 return (HARD_REGISTER_NUM_P (regno)
2851 && HARD_REGISTER_NUM_P (regno + offset)
2852 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2853 regno + offset));
2856 /* Split single instruction. Helper function for split_all_insns and
2857 split_all_insns_noflow. Return last insn in the sequence if successful,
2858 or NULL if unsuccessful. */
2860 static rtx_insn *
2861 split_insn (rtx_insn *insn)
2863 /* Split insns here to get max fine-grain parallelism. */
2864 rtx_insn *first = PREV_INSN (insn);
2865 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2866 rtx insn_set, last_set, note;
2868 if (last == insn)
2869 return NULL;
2871 /* If the original instruction was a single set that was known to be
2872 equivalent to a constant, see if we can say the same about the last
2873 instruction in the split sequence. The two instructions must set
2874 the same destination. */
2875 insn_set = single_set (insn);
2876 if (insn_set)
2878 last_set = single_set (last);
2879 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2881 note = find_reg_equal_equiv_note (insn);
2882 if (note && CONSTANT_P (XEXP (note, 0)))
2883 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2884 else if (CONSTANT_P (SET_SRC (insn_set)))
2885 set_unique_reg_note (last, REG_EQUAL,
2886 copy_rtx (SET_SRC (insn_set)));
2890 /* try_split returns the NOTE that INSN became. */
2891 SET_INSN_DELETED (insn);
2893 /* ??? Coddle to md files that generate subregs in post-reload
2894 splitters instead of computing the proper hard register. */
2895 if (reload_completed && first != last)
2897 first = NEXT_INSN (first);
2898 for (;;)
2900 if (INSN_P (first))
2901 cleanup_subreg_operands (first);
2902 if (first == last)
2903 break;
2904 first = NEXT_INSN (first);
2908 return last;
2911 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2913 void
2914 split_all_insns (void)
2916 sbitmap blocks;
2917 bool changed;
2918 basic_block bb;
2920 blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
2921 bitmap_clear (blocks);
2922 changed = false;
2924 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2926 rtx_insn *insn, *next;
2927 bool finish = false;
2929 rtl_profile_for_bb (bb);
2930 for (insn = BB_HEAD (bb); !finish ; insn = next)
2932 /* Can't use `next_real_insn' because that might go across
2933 CODE_LABELS and short-out basic blocks. */
2934 next = NEXT_INSN (insn);
2935 finish = (insn == BB_END (bb));
2936 if (INSN_P (insn))
2938 rtx set = single_set (insn);
2940 /* Don't split no-op move insns. These should silently
2941 disappear later in final. Splitting such insns would
2942 break the code that handles LIBCALL blocks. */
2943 if (set && set_noop_p (set))
2945 /* Nops get in the way while scheduling, so delete them
2946 now if register allocation has already been done. It
2947 is too risky to try to do this before register
2948 allocation, and there are unlikely to be very many
2949 nops then anyways. */
2950 if (reload_completed)
2951 delete_insn_and_edges (insn);
2953 else
2955 if (split_insn (insn))
2957 bitmap_set_bit (blocks, bb->index);
2958 changed = true;
2965 default_rtl_profile ();
2966 if (changed)
2967 find_many_sub_basic_blocks (blocks);
2969 checking_verify_flow_info ();
2971 sbitmap_free (blocks);
2974 /* Same as split_all_insns, but do not expect CFG to be available.
2975 Used by machine dependent reorg passes. */
2977 unsigned int
2978 split_all_insns_noflow (void)
2980 rtx_insn *next, *insn;
2982 for (insn = get_insns (); insn; insn = next)
2984 next = NEXT_INSN (insn);
2985 if (INSN_P (insn))
2987 /* Don't split no-op move insns. These should silently
2988 disappear later in final. Splitting such insns would
2989 break the code that handles LIBCALL blocks. */
2990 rtx set = single_set (insn);
2991 if (set && set_noop_p (set))
2993 /* Nops get in the way while scheduling, so delete them
2994 now if register allocation has already been done. It
2995 is too risky to try to do this before register
2996 allocation, and there are unlikely to be very many
2997 nops then anyways.
2999 ??? Should we use delete_insn when the CFG isn't valid? */
3000 if (reload_completed)
3001 delete_insn_and_edges (insn);
3003 else
3004 split_insn (insn);
3007 return 0;
3010 struct peep2_insn_data
3012 rtx_insn *insn;
3013 regset live_before;
3016 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
3017 static int peep2_current;
3019 static bool peep2_do_rebuild_jump_labels;
3020 static bool peep2_do_cleanup_cfg;
3022 /* The number of instructions available to match a peep2. */
3023 int peep2_current_count;
3025 /* A marker indicating the last insn of the block. The live_before regset
3026 for this element is correct, indicating DF_LIVE_OUT for the block. */
3027 #define PEEP2_EOB invalid_insn_rtx
3029 /* Wrap N to fit into the peep2_insn_data buffer. */
3031 static int
3032 peep2_buf_position (int n)
3034 if (n >= MAX_INSNS_PER_PEEP2 + 1)
3035 n -= MAX_INSNS_PER_PEEP2 + 1;
3036 return n;
3039 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3040 does not exist. Used by the recognizer to find the next insn to match
3041 in a multi-insn pattern. */
3043 rtx_insn *
3044 peep2_next_insn (int n)
3046 gcc_assert (n <= peep2_current_count);
3048 n = peep2_buf_position (peep2_current + n);
3050 return peep2_insn_data[n].insn;
3053 /* Return true if REGNO is dead before the Nth non-note insn
3054 after `current'. */
3057 peep2_regno_dead_p (int ofs, int regno)
3059 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3061 ofs = peep2_buf_position (peep2_current + ofs);
3063 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3065 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
3068 /* Similarly for a REG. */
3071 peep2_reg_dead_p (int ofs, rtx reg)
3073 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3075 ofs = peep2_buf_position (peep2_current + ofs);
3077 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3079 unsigned int end_regno = END_REGNO (reg);
3080 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3081 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3082 return 0;
3083 return 1;
3086 /* Regno offset to be used in the register search. */
3087 static int search_ofs;
3089 /* Try to find a hard register of mode MODE, matching the register class in
3090 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3091 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3092 in which case the only condition is that the register must be available
3093 before CURRENT_INSN.
3094 Registers that already have bits set in REG_SET will not be considered.
3096 If an appropriate register is available, it will be returned and the
3097 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3098 returned. */
3101 peep2_find_free_register (int from, int to, const char *class_str,
3102 machine_mode mode, HARD_REG_SET *reg_set)
3104 enum reg_class cl;
3105 HARD_REG_SET live;
3106 df_ref def;
3107 int i;
3109 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3110 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3112 from = peep2_buf_position (peep2_current + from);
3113 to = peep2_buf_position (peep2_current + to);
3115 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3116 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3118 while (from != to)
3120 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3122 /* Don't use registers set or clobbered by the insn. */
3123 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3124 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3126 from = peep2_buf_position (from + 1);
3129 cl = reg_class_for_constraint (lookup_constraint (class_str));
3131 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3133 int raw_regno, regno, success, j;
3135 /* Distribute the free registers as much as possible. */
3136 raw_regno = search_ofs + i;
3137 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3138 raw_regno -= FIRST_PSEUDO_REGISTER;
3139 #ifdef REG_ALLOC_ORDER
3140 regno = reg_alloc_order[raw_regno];
3141 #else
3142 regno = raw_regno;
3143 #endif
3145 /* Can it support the mode we need? */
3146 if (! HARD_REGNO_MODE_OK (regno, mode))
3147 continue;
3149 success = 1;
3150 for (j = 0; success && j < hard_regno_nregs[regno][mode]; j++)
3152 /* Don't allocate fixed registers. */
3153 if (fixed_regs[regno + j])
3155 success = 0;
3156 break;
3158 /* Don't allocate global registers. */
3159 if (global_regs[regno + j])
3161 success = 0;
3162 break;
3164 /* Make sure the register is of the right class. */
3165 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3167 success = 0;
3168 break;
3170 /* And that we don't create an extra save/restore. */
3171 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3173 success = 0;
3174 break;
3177 if (! targetm.hard_regno_scratch_ok (regno + j))
3179 success = 0;
3180 break;
3183 /* And we don't clobber traceback for noreturn functions. */
3184 if ((regno + j == FRAME_POINTER_REGNUM
3185 || regno + j == HARD_FRAME_POINTER_REGNUM)
3186 && (! reload_completed || frame_pointer_needed))
3188 success = 0;
3189 break;
3192 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3193 || TEST_HARD_REG_BIT (live, regno + j))
3195 success = 0;
3196 break;
3200 if (success)
3202 add_to_hard_reg_set (reg_set, mode, regno);
3204 /* Start the next search with the next register. */
3205 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3206 raw_regno = 0;
3207 search_ofs = raw_regno;
3209 return gen_rtx_REG (mode, regno);
3213 search_ofs = 0;
3214 return NULL_RTX;
3217 /* Forget all currently tracked instructions, only remember current
3218 LIVE regset. */
3220 static void
3221 peep2_reinit_state (regset live)
3223 int i;
3225 /* Indicate that all slots except the last holds invalid data. */
3226 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3227 peep2_insn_data[i].insn = NULL;
3228 peep2_current_count = 0;
3230 /* Indicate that the last slot contains live_after data. */
3231 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3232 peep2_current = MAX_INSNS_PER_PEEP2;
3234 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3237 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3238 starting at INSN. Perform the replacement, removing the old insns and
3239 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3240 if the replacement is rejected. */
3242 static rtx_insn *
3243 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3245 int i;
3246 rtx_insn *last, *before_try, *x;
3247 rtx eh_note, as_note;
3248 rtx_insn *old_insn;
3249 rtx_insn *new_insn;
3250 bool was_call = false;
3252 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3253 match more than one insn, or to be split into more than one insn. */
3254 old_insn = peep2_insn_data[peep2_current].insn;
3255 if (RTX_FRAME_RELATED_P (old_insn))
3257 bool any_note = false;
3258 rtx note;
3260 if (match_len != 0)
3261 return NULL;
3263 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3264 may be in the stream for the purpose of register allocation. */
3265 if (active_insn_p (attempt))
3266 new_insn = attempt;
3267 else
3268 new_insn = next_active_insn (attempt);
3269 if (next_active_insn (new_insn))
3270 return NULL;
3272 /* We have a 1-1 replacement. Copy over any frame-related info. */
3273 RTX_FRAME_RELATED_P (new_insn) = 1;
3275 /* Allow the backend to fill in a note during the split. */
3276 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
3277 switch (REG_NOTE_KIND (note))
3279 case REG_FRAME_RELATED_EXPR:
3280 case REG_CFA_DEF_CFA:
3281 case REG_CFA_ADJUST_CFA:
3282 case REG_CFA_OFFSET:
3283 case REG_CFA_REGISTER:
3284 case REG_CFA_EXPRESSION:
3285 case REG_CFA_RESTORE:
3286 case REG_CFA_SET_VDRAP:
3287 any_note = true;
3288 break;
3289 default:
3290 break;
3293 /* If the backend didn't supply a note, copy one over. */
3294 if (!any_note)
3295 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1))
3296 switch (REG_NOTE_KIND (note))
3298 case REG_FRAME_RELATED_EXPR:
3299 case REG_CFA_DEF_CFA:
3300 case REG_CFA_ADJUST_CFA:
3301 case REG_CFA_OFFSET:
3302 case REG_CFA_REGISTER:
3303 case REG_CFA_EXPRESSION:
3304 case REG_CFA_RESTORE:
3305 case REG_CFA_SET_VDRAP:
3306 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3307 any_note = true;
3308 break;
3309 default:
3310 break;
3313 /* If there still isn't a note, make sure the unwind info sees the
3314 same expression as before the split. */
3315 if (!any_note)
3317 rtx old_set, new_set;
3319 /* The old insn had better have been simple, or annotated. */
3320 old_set = single_set (old_insn);
3321 gcc_assert (old_set != NULL);
3323 new_set = single_set (new_insn);
3324 if (!new_set || !rtx_equal_p (new_set, old_set))
3325 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3328 /* Copy prologue/epilogue status. This is required in order to keep
3329 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3330 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3333 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3334 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3335 cfg-related call notes. */
3336 for (i = 0; i <= match_len; ++i)
3338 int j;
3339 rtx note;
3341 j = peep2_buf_position (peep2_current + i);
3342 old_insn = peep2_insn_data[j].insn;
3343 if (!CALL_P (old_insn))
3344 continue;
3345 was_call = true;
3347 new_insn = attempt;
3348 while (new_insn != NULL_RTX)
3350 if (CALL_P (new_insn))
3351 break;
3352 new_insn = NEXT_INSN (new_insn);
3355 gcc_assert (new_insn != NULL_RTX);
3357 CALL_INSN_FUNCTION_USAGE (new_insn)
3358 = CALL_INSN_FUNCTION_USAGE (old_insn);
3359 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3361 for (note = REG_NOTES (old_insn);
3362 note;
3363 note = XEXP (note, 1))
3364 switch (REG_NOTE_KIND (note))
3366 case REG_NORETURN:
3367 case REG_SETJMP:
3368 case REG_TM:
3369 add_reg_note (new_insn, REG_NOTE_KIND (note),
3370 XEXP (note, 0));
3371 break;
3372 default:
3373 /* Discard all other reg notes. */
3374 break;
3377 /* Croak if there is another call in the sequence. */
3378 while (++i <= match_len)
3380 j = peep2_buf_position (peep2_current + i);
3381 old_insn = peep2_insn_data[j].insn;
3382 gcc_assert (!CALL_P (old_insn));
3384 break;
3387 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3388 move those notes over to the new sequence. */
3389 as_note = NULL;
3390 for (i = match_len; i >= 0; --i)
3392 int j = peep2_buf_position (peep2_current + i);
3393 old_insn = peep2_insn_data[j].insn;
3395 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3396 if (as_note)
3397 break;
3400 i = peep2_buf_position (peep2_current + match_len);
3401 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3403 /* Replace the old sequence with the new. */
3404 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3405 last = emit_insn_after_setloc (attempt,
3406 peep2_insn_data[i].insn,
3407 INSN_LOCATION (peepinsn));
3408 before_try = PREV_INSN (insn);
3409 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3411 /* Re-insert the EH_REGION notes. */
3412 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3414 edge eh_edge;
3415 edge_iterator ei;
3417 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3418 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3419 break;
3421 if (eh_note)
3422 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3424 if (eh_edge)
3425 for (x = last; x != before_try; x = PREV_INSN (x))
3426 if (x != BB_END (bb)
3427 && (can_throw_internal (x)
3428 || can_nonlocal_goto (x)))
3430 edge nfte, nehe;
3431 int flags;
3433 nfte = split_block (bb, x);
3434 flags = (eh_edge->flags
3435 & (EDGE_EH | EDGE_ABNORMAL));
3436 if (CALL_P (x))
3437 flags |= EDGE_ABNORMAL_CALL;
3438 nehe = make_edge (nfte->src, eh_edge->dest,
3439 flags);
3441 nehe->probability = eh_edge->probability;
3442 nfte->probability
3443 = REG_BR_PROB_BASE - nehe->probability;
3445 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3446 bb = nfte->src;
3447 eh_edge = nehe;
3450 /* Converting possibly trapping insn to non-trapping is
3451 possible. Zap dummy outgoing edges. */
3452 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3455 /* Re-insert the ARGS_SIZE notes. */
3456 if (as_note)
3457 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3459 /* If we generated a jump instruction, it won't have
3460 JUMP_LABEL set. Recompute after we're done. */
3461 for (x = last; x != before_try; x = PREV_INSN (x))
3462 if (JUMP_P (x))
3464 peep2_do_rebuild_jump_labels = true;
3465 break;
3468 return last;
3471 /* After performing a replacement in basic block BB, fix up the life
3472 information in our buffer. LAST is the last of the insns that we
3473 emitted as a replacement. PREV is the insn before the start of
3474 the replacement. MATCH_LEN is the number of instructions that were
3475 matched, and which now need to be replaced in the buffer. */
3477 static void
3478 peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3479 rtx_insn *prev)
3481 int i = peep2_buf_position (peep2_current + match_len + 1);
3482 rtx_insn *x;
3483 regset_head live;
3485 INIT_REG_SET (&live);
3486 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3488 gcc_assert (peep2_current_count >= match_len + 1);
3489 peep2_current_count -= match_len + 1;
3491 x = last;
3494 if (INSN_P (x))
3496 df_insn_rescan (x);
3497 if (peep2_current_count < MAX_INSNS_PER_PEEP2)
3499 peep2_current_count++;
3500 if (--i < 0)
3501 i = MAX_INSNS_PER_PEEP2;
3502 peep2_insn_data[i].insn = x;
3503 df_simulate_one_insn_backwards (bb, x, &live);
3504 COPY_REG_SET (peep2_insn_data[i].live_before, &live);
3507 x = PREV_INSN (x);
3509 while (x != prev);
3510 CLEAR_REG_SET (&live);
3512 peep2_current = i;
3515 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3516 Return true if we added it, false otherwise. The caller will try to match
3517 peepholes against the buffer if we return false; otherwise it will try to
3518 add more instructions to the buffer. */
3520 static bool
3521 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3523 int pos;
3525 /* Once we have filled the maximum number of insns the buffer can hold,
3526 allow the caller to match the insns against peepholes. We wait until
3527 the buffer is full in case the target has similar peepholes of different
3528 length; we always want to match the longest if possible. */
3529 if (peep2_current_count == MAX_INSNS_PER_PEEP2)
3530 return false;
3532 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3533 any other pattern, lest it change the semantics of the frame info. */
3534 if (RTX_FRAME_RELATED_P (insn))
3536 /* Let the buffer drain first. */
3537 if (peep2_current_count > 0)
3538 return false;
3539 /* Now the insn will be the only thing in the buffer. */
3542 pos = peep2_buf_position (peep2_current + peep2_current_count);
3543 peep2_insn_data[pos].insn = insn;
3544 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3545 peep2_current_count++;
3547 df_simulate_one_insn_forwards (bb, insn, live);
3548 return true;
3551 /* Perform the peephole2 optimization pass. */
3553 static void
3554 peephole2_optimize (void)
3556 rtx_insn *insn;
3557 bitmap live;
3558 int i;
3559 basic_block bb;
3561 peep2_do_cleanup_cfg = false;
3562 peep2_do_rebuild_jump_labels = false;
3564 df_set_flags (DF_LR_RUN_DCE);
3565 df_note_add_problem ();
3566 df_analyze ();
3568 /* Initialize the regsets we're going to use. */
3569 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3570 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3571 search_ofs = 0;
3572 live = BITMAP_ALLOC (&reg_obstack);
3574 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3576 bool past_end = false;
3577 int pos;
3579 rtl_profile_for_bb (bb);
3581 /* Start up propagation. */
3582 bitmap_copy (live, DF_LR_IN (bb));
3583 df_simulate_initialize_forwards (bb, live);
3584 peep2_reinit_state (live);
3586 insn = BB_HEAD (bb);
3587 for (;;)
3589 rtx_insn *attempt, *head;
3590 int match_len;
3592 if (!past_end && !NONDEBUG_INSN_P (insn))
3594 next_insn:
3595 insn = NEXT_INSN (insn);
3596 if (insn == NEXT_INSN (BB_END (bb)))
3597 past_end = true;
3598 continue;
3600 if (!past_end && peep2_fill_buffer (bb, insn, live))
3601 goto next_insn;
3603 /* If we did not fill an empty buffer, it signals the end of the
3604 block. */
3605 if (peep2_current_count == 0)
3606 break;
3608 /* The buffer filled to the current maximum, so try to match. */
3610 pos = peep2_buf_position (peep2_current + peep2_current_count);
3611 peep2_insn_data[pos].insn = PEEP2_EOB;
3612 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3614 /* Match the peephole. */
3615 head = peep2_insn_data[peep2_current].insn;
3616 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3617 if (attempt != NULL)
3619 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3620 if (last)
3622 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3623 continue;
3627 /* No match: advance the buffer by one insn. */
3628 peep2_current = peep2_buf_position (peep2_current + 1);
3629 peep2_current_count--;
3633 default_rtl_profile ();
3634 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3635 BITMAP_FREE (peep2_insn_data[i].live_before);
3636 BITMAP_FREE (live);
3637 if (peep2_do_rebuild_jump_labels)
3638 rebuild_jump_labels (get_insns ());
3639 if (peep2_do_cleanup_cfg)
3640 cleanup_cfg (CLEANUP_CFG_CHANGED);
3643 /* Common predicates for use with define_bypass. */
3645 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3646 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3647 must be either a single_set or a PARALLEL with SETs inside. */
3650 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3652 rtx out_set, in_set;
3653 rtx out_pat, in_pat;
3654 rtx out_exp, in_exp;
3655 int i, j;
3657 in_set = single_set (in_insn);
3658 if (in_set)
3660 if (!MEM_P (SET_DEST (in_set)))
3661 return false;
3663 out_set = single_set (out_insn);
3664 if (out_set)
3666 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3667 return false;
3669 else
3671 out_pat = PATTERN (out_insn);
3673 if (GET_CODE (out_pat) != PARALLEL)
3674 return false;
3676 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3678 out_exp = XVECEXP (out_pat, 0, i);
3680 if (GET_CODE (out_exp) == CLOBBER)
3681 continue;
3683 gcc_assert (GET_CODE (out_exp) == SET);
3685 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3686 return false;
3690 else
3692 in_pat = PATTERN (in_insn);
3693 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3695 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3697 in_exp = XVECEXP (in_pat, 0, i);
3699 if (GET_CODE (in_exp) == CLOBBER)
3700 continue;
3702 gcc_assert (GET_CODE (in_exp) == SET);
3704 if (!MEM_P (SET_DEST (in_exp)))
3705 return false;
3707 out_set = single_set (out_insn);
3708 if (out_set)
3710 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3711 return false;
3713 else
3715 out_pat = PATTERN (out_insn);
3716 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3718 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3720 out_exp = XVECEXP (out_pat, 0, j);
3722 if (GET_CODE (out_exp) == CLOBBER)
3723 continue;
3725 gcc_assert (GET_CODE (out_exp) == SET);
3727 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3728 return false;
3734 return true;
3737 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3738 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3739 or multiple set; IN_INSN should be single_set for truth, but for convenience
3740 of insn categorization may be any JUMP or CALL insn. */
3743 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3745 rtx out_set, in_set;
3747 in_set = single_set (in_insn);
3748 if (! in_set)
3750 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3751 return false;
3754 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3755 return false;
3756 in_set = SET_SRC (in_set);
3758 out_set = single_set (out_insn);
3759 if (out_set)
3761 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3762 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3763 return false;
3765 else
3767 rtx out_pat;
3768 int i;
3770 out_pat = PATTERN (out_insn);
3771 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3773 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3775 rtx exp = XVECEXP (out_pat, 0, i);
3777 if (GET_CODE (exp) == CLOBBER)
3778 continue;
3780 gcc_assert (GET_CODE (exp) == SET);
3782 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3783 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3784 return false;
3788 return true;
3791 static unsigned int
3792 rest_of_handle_peephole2 (void)
3794 if (HAVE_peephole2)
3795 peephole2_optimize ();
3797 return 0;
3800 namespace {
3802 const pass_data pass_data_peephole2 =
3804 RTL_PASS, /* type */
3805 "peephole2", /* name */
3806 OPTGROUP_NONE, /* optinfo_flags */
3807 TV_PEEPHOLE2, /* tv_id */
3808 0, /* properties_required */
3809 0, /* properties_provided */
3810 0, /* properties_destroyed */
3811 0, /* todo_flags_start */
3812 TODO_df_finish, /* todo_flags_finish */
3815 class pass_peephole2 : public rtl_opt_pass
3817 public:
3818 pass_peephole2 (gcc::context *ctxt)
3819 : rtl_opt_pass (pass_data_peephole2, ctxt)
3822 /* opt_pass methods: */
3823 /* The epiphany backend creates a second instance of this pass, so we need
3824 a clone method. */
3825 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3826 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3827 virtual unsigned int execute (function *)
3829 return rest_of_handle_peephole2 ();
3832 }; // class pass_peephole2
3834 } // anon namespace
3836 rtl_opt_pass *
3837 make_pass_peephole2 (gcc::context *ctxt)
3839 return new pass_peephole2 (ctxt);
3842 namespace {
3844 const pass_data pass_data_split_all_insns =
3846 RTL_PASS, /* type */
3847 "split1", /* name */
3848 OPTGROUP_NONE, /* optinfo_flags */
3849 TV_NONE, /* tv_id */
3850 0, /* properties_required */
3851 0, /* properties_provided */
3852 0, /* properties_destroyed */
3853 0, /* todo_flags_start */
3854 0, /* todo_flags_finish */
3857 class pass_split_all_insns : public rtl_opt_pass
3859 public:
3860 pass_split_all_insns (gcc::context *ctxt)
3861 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3864 /* opt_pass methods: */
3865 /* The epiphany backend creates a second instance of this pass, so
3866 we need a clone method. */
3867 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3868 virtual unsigned int execute (function *)
3870 split_all_insns ();
3871 return 0;
3874 }; // class pass_split_all_insns
3876 } // anon namespace
3878 rtl_opt_pass *
3879 make_pass_split_all_insns (gcc::context *ctxt)
3881 return new pass_split_all_insns (ctxt);
3884 static unsigned int
3885 rest_of_handle_split_after_reload (void)
3887 /* If optimizing, then go ahead and split insns now. */
3888 #ifndef STACK_REGS
3889 if (optimize > 0)
3890 #endif
3891 split_all_insns ();
3892 return 0;
3895 namespace {
3897 const pass_data pass_data_split_after_reload =
3899 RTL_PASS, /* type */
3900 "split2", /* name */
3901 OPTGROUP_NONE, /* optinfo_flags */
3902 TV_NONE, /* tv_id */
3903 0, /* properties_required */
3904 0, /* properties_provided */
3905 0, /* properties_destroyed */
3906 0, /* todo_flags_start */
3907 0, /* todo_flags_finish */
3910 class pass_split_after_reload : public rtl_opt_pass
3912 public:
3913 pass_split_after_reload (gcc::context *ctxt)
3914 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3917 /* opt_pass methods: */
3918 virtual unsigned int execute (function *)
3920 return rest_of_handle_split_after_reload ();
3923 }; // class pass_split_after_reload
3925 } // anon namespace
3927 rtl_opt_pass *
3928 make_pass_split_after_reload (gcc::context *ctxt)
3930 return new pass_split_after_reload (ctxt);
3933 namespace {
3935 const pass_data pass_data_split_before_regstack =
3937 RTL_PASS, /* type */
3938 "split3", /* name */
3939 OPTGROUP_NONE, /* optinfo_flags */
3940 TV_NONE, /* tv_id */
3941 0, /* properties_required */
3942 0, /* properties_provided */
3943 0, /* properties_destroyed */
3944 0, /* todo_flags_start */
3945 0, /* todo_flags_finish */
3948 class pass_split_before_regstack : public rtl_opt_pass
3950 public:
3951 pass_split_before_regstack (gcc::context *ctxt)
3952 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3955 /* opt_pass methods: */
3956 virtual bool gate (function *);
3957 virtual unsigned int execute (function *)
3959 split_all_insns ();
3960 return 0;
3963 }; // class pass_split_before_regstack
3965 bool
3966 pass_split_before_regstack::gate (function *)
3968 #if HAVE_ATTR_length && defined (STACK_REGS)
3969 /* If flow2 creates new instructions which need splitting
3970 and scheduling after reload is not done, they might not be
3971 split until final which doesn't allow splitting
3972 if HAVE_ATTR_length. */
3973 # ifdef INSN_SCHEDULING
3974 return (optimize && !flag_schedule_insns_after_reload);
3975 # else
3976 return (optimize);
3977 # endif
3978 #else
3979 return 0;
3980 #endif
3983 } // anon namespace
3985 rtl_opt_pass *
3986 make_pass_split_before_regstack (gcc::context *ctxt)
3988 return new pass_split_before_regstack (ctxt);
3991 static unsigned int
3992 rest_of_handle_split_before_sched2 (void)
3994 #ifdef INSN_SCHEDULING
3995 split_all_insns ();
3996 #endif
3997 return 0;
4000 namespace {
4002 const pass_data pass_data_split_before_sched2 =
4004 RTL_PASS, /* type */
4005 "split4", /* name */
4006 OPTGROUP_NONE, /* optinfo_flags */
4007 TV_NONE, /* tv_id */
4008 0, /* properties_required */
4009 0, /* properties_provided */
4010 0, /* properties_destroyed */
4011 0, /* todo_flags_start */
4012 0, /* todo_flags_finish */
4015 class pass_split_before_sched2 : public rtl_opt_pass
4017 public:
4018 pass_split_before_sched2 (gcc::context *ctxt)
4019 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4022 /* opt_pass methods: */
4023 virtual bool gate (function *)
4025 #ifdef INSN_SCHEDULING
4026 return optimize > 0 && flag_schedule_insns_after_reload;
4027 #else
4028 return false;
4029 #endif
4032 virtual unsigned int execute (function *)
4034 return rest_of_handle_split_before_sched2 ();
4037 }; // class pass_split_before_sched2
4039 } // anon namespace
4041 rtl_opt_pass *
4042 make_pass_split_before_sched2 (gcc::context *ctxt)
4044 return new pass_split_before_sched2 (ctxt);
4047 namespace {
4049 const pass_data pass_data_split_for_shorten_branches =
4051 RTL_PASS, /* type */
4052 "split5", /* name */
4053 OPTGROUP_NONE, /* optinfo_flags */
4054 TV_NONE, /* tv_id */
4055 0, /* properties_required */
4056 0, /* properties_provided */
4057 0, /* properties_destroyed */
4058 0, /* todo_flags_start */
4059 0, /* todo_flags_finish */
4062 class pass_split_for_shorten_branches : public rtl_opt_pass
4064 public:
4065 pass_split_for_shorten_branches (gcc::context *ctxt)
4066 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4069 /* opt_pass methods: */
4070 virtual bool gate (function *)
4072 /* The placement of the splitting that we do for shorten_branches
4073 depends on whether regstack is used by the target or not. */
4074 #if HAVE_ATTR_length && !defined (STACK_REGS)
4075 return true;
4076 #else
4077 return false;
4078 #endif
4081 virtual unsigned int execute (function *)
4083 return split_all_insns_noflow ();
4086 }; // class pass_split_for_shorten_branches
4088 } // anon namespace
4090 rtl_opt_pass *
4091 make_pass_split_for_shorten_branches (gcc::context *ctxt)
4093 return new pass_split_for_shorten_branches (ctxt);
4096 /* (Re)initialize the target information after a change in target. */
4098 void
4099 recog_init ()
4101 /* The information is zero-initialized, so we don't need to do anything
4102 first time round. */
4103 if (!this_target_recog->x_initialized)
4105 this_target_recog->x_initialized = true;
4106 return;
4108 memset (this_target_recog->x_bool_attr_masks, 0,
4109 sizeof (this_target_recog->x_bool_attr_masks));
4110 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4111 if (this_target_recog->x_op_alt[i])
4113 free (this_target_recog->x_op_alt[i]);
4114 this_target_recog->x_op_alt[i] = 0;