| blob | ab08288413c3e64911e8d7a8199b9809e0282d8e |
1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007-2016 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 ;; Thumb-2 only allows shift by constant on data processing instructions
28 (define_insn "*thumb_andsi_not_shiftsi_si"
29 [(set (match_operand:SI 0 "s_register_operand" "=r")
30 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
31 [(match_operand:SI 2 "s_register_operand" "r")
32 (match_operand:SI 3 "const_int_operand" "M")]))
33 (match_operand:SI 1 "s_register_operand" "r")))]
34 "TARGET_THUMB2"
35 "bic%?\\t%0, %1, %2%S4"
36 [(set_attr "predicable" "yes")
37 (set_attr "predicable_short_it" "no")
38 (set_attr "shift" "2")
39 (set_attr "type" "alu_shift_imm")]
40 )
42 ;; We use the '0' constraint for operand 1 because reload should
43 ;; be smart enough to generate an appropriate move for the r/r/r case.
44 (define_insn_and_split "*thumb2_smaxsi3"
45 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
46 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
47 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
48 (clobber (reg:CC CC_REGNUM))]
49 "TARGET_THUMB2"
50 "#"
51 ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
52 "TARGET_THUMB2 && reload_completed"
53 [(set (reg:CC CC_REGNUM)
54 (compare:CC (match_dup 1) (match_dup 2)))
55 (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
56 (set (match_dup 0)
57 (match_dup 2)))]
58 ""
59 [(set_attr "conds" "clob")
60 (set_attr "enabled_for_depr_it" "yes,yes,no")
61 (set_attr "length" "6,6,10")
62 (set_attr "type" "multiple")]
63 )
65 (define_insn_and_split "*thumb2_sminsi3"
66 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
67 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
68 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
69 (clobber (reg:CC CC_REGNUM))]
70 "TARGET_THUMB2"
71 "#"
72 ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
73 "TARGET_THUMB2 && reload_completed"
74 [(set (reg:CC CC_REGNUM)
75 (compare:CC (match_dup 1) (match_dup 2)))
76 (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
77 (set (match_dup 0)
78 (match_dup 2)))]
79 ""
80 [(set_attr "conds" "clob")
81 (set_attr "enabled_for_depr_it" "yes,yes,no")
82 (set_attr "length" "6,6,10")
83 (set_attr "type" "multiple")]
84 )
86 (define_insn_and_split "*thumb32_umaxsi3"
87 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
88 (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
89 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
90 (clobber (reg:CC CC_REGNUM))]
91 "TARGET_THUMB2"
92 "#"
93 ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
94 "TARGET_THUMB2 && reload_completed"
95 [(set (reg:CC CC_REGNUM)
96 (compare:CC (match_dup 1) (match_dup 2)))
97 (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
98 (set (match_dup 0)
99 (match_dup 2)))]
100 ""
101 [(set_attr "conds" "clob")
102 (set_attr "length" "6,6,10")
103 (set_attr "enabled_for_depr_it" "yes,yes,no")
104 (set_attr "type" "multiple")]
105 )
107 (define_insn_and_split "*thumb2_uminsi3"
108 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
109 (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
110 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
111 (clobber (reg:CC CC_REGNUM))]
112 "TARGET_THUMB2"
113 "#"
114 ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
115 "TARGET_THUMB2 && reload_completed"
116 [(set (reg:CC CC_REGNUM)
117 (compare:CC (match_dup 1) (match_dup 2)))
118 (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
119 (set (match_dup 0)
120 (match_dup 2)))]
121 ""
122 [(set_attr "conds" "clob")
123 (set_attr "length" "6,6,10")
124 (set_attr "enabled_for_depr_it" "yes,yes,no")
125 (set_attr "type" "multiple")]
126 )
128 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
129 (define_insn_and_split "*thumb2_negdi2"
130 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
131 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
132 (clobber (reg:CC CC_REGNUM))]
133 "TARGET_THUMB2"
134 "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
135 "&& reload_completed"
136 [(parallel [(set (reg:CC CC_REGNUM)
137 (compare:CC (const_int 0) (match_dup 1)))
138 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
139 (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
140 (ashift:SI (match_dup 3)
141 (const_int 1)))
142 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
143 {
144 operands[2] = gen_highpart (SImode, operands[0]);
145 operands[0] = gen_lowpart (SImode, operands[0]);
146 operands[3] = gen_highpart (SImode, operands[1]);
147 operands[1] = gen_lowpart (SImode, operands[1]);
148 }
149 [(set_attr "conds" "clob")
150 (set_attr "length" "8")
151 (set_attr "type" "multiple")]
152 )
154 (define_insn_and_split "*thumb2_abssi2"
155 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
156 (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
157 (clobber (reg:CC CC_REGNUM))]
158 "TARGET_THUMB2"
159 "#"
160 ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
161 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
162 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
163 "&& reload_completed"
164 [(const_int 0)]
165 {
166 if (REGNO(operands[0]) == REGNO(operands[1]))
167 {
168 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
170 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
171 const0_rtx)));
172 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
173 (gen_rtx_LT (SImode,
174 cc_reg,
175 const0_rtx)),
176 (gen_rtx_SET (operands[0],
177 (gen_rtx_MINUS (SImode,
178 const0_rtx,
179 operands[1]))))));
180 }
181 else
182 {
183 emit_insn (gen_rtx_SET (operands[0],
184 gen_rtx_XOR (SImode,
185 gen_rtx_ASHIFTRT (SImode,
186 operands[1],
187 GEN_INT (31)),
188 operands[1])));
189 emit_insn (gen_rtx_SET (operands[0],
190 gen_rtx_MINUS (SImode,
191 operands[0],
192 gen_rtx_ASHIFTRT (SImode,
193 operands[1],
194 GEN_INT (31)))));
195 }
196 DONE;
197 }
198 [(set_attr "conds" "*,clob,clob")
199 (set_attr "shift" "1")
200 (set_attr "predicable" "yes,no,no")
201 (set_attr "predicable_short_it" "no")
202 (set_attr "enabled_for_depr_it" "yes,yes,no")
203 (set_attr "ce_count" "2")
204 (set_attr "length" "8,6,10")
205 (set_attr "type" "multiple")]
206 )
208 (define_insn_and_split "*thumb2_neg_abssi2"
209 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
210 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
211 (clobber (reg:CC CC_REGNUM))]
212 "TARGET_THUMB2"
213 "#"
214 ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
215 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
216 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
217 "&& reload_completed"
218 [(const_int 0)]
219 {
220 if (REGNO(operands[0]) == REGNO(operands[1]))
221 {
222 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
224 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
225 const0_rtx)));
226 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
227 (gen_rtx_GT (SImode,
228 cc_reg,
229 const0_rtx)),
230 (gen_rtx_SET (operands[0],
231 (gen_rtx_MINUS (SImode,
232 const0_rtx,
233 operands[1]))))));
234 }
235 else
236 {
237 emit_insn (gen_rtx_SET (operands[0],
238 gen_rtx_XOR (SImode,
239 gen_rtx_ASHIFTRT (SImode,
240 operands[1],
241 GEN_INT (31)),
242 operands[1])));
243 emit_insn (gen_rtx_SET (operands[0],
244 gen_rtx_MINUS (SImode,
245 gen_rtx_ASHIFTRT (SImode,
246 operands[1],
247 GEN_INT (31)),
248 operands[0])));
249 }
250 DONE;
251 }
252 [(set_attr "conds" "*,clob,clob")
253 (set_attr "shift" "1")
254 (set_attr "predicable" "yes,no,no")
255 (set_attr "enabled_for_depr_it" "yes,yes,no")
256 (set_attr "predicable_short_it" "no")
257 (set_attr "ce_count" "2")
258 (set_attr "length" "8,6,10")
259 (set_attr "type" "multiple")]
260 )
262 ;; Pop a single register as its size is preferred over a post-incremental load
263 (define_insn "*thumb2_pop_single"
264 [(set (match_operand:SI 0 "low_register_operand" "=r")
265 (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
266 "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
267 "pop\t{%0}"
268 [(set_attr "type" "load1")
269 (set_attr "length" "2")
270 (set_attr "predicable" "yes")]
271 )
273 ;; We have two alternatives here for memory loads (and similarly for stores)
274 ;; to reflect the fact that the permissible constant pool ranges differ
275 ;; between ldr instructions taking low regs and ldr instructions taking high
276 ;; regs. The high register alternatives are not taken into account when
277 ;; choosing register preferences in order to reflect their expense.
278 (define_insn "*thumb2_movsi_insn"
279 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
280 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))]
281 "TARGET_THUMB2 && ! TARGET_IWMMXT
282 && !(TARGET_HARD_FLOAT && TARGET_VFP)
283 && ( register_operand (operands[0], SImode)
284 || register_operand (operands[1], SImode))"
285 "@
286 mov%?\\t%0, %1
287 mov%?\\t%0, %1
288 mov%?\\t%0, %1
289 mvn%?\\t%0, #%B1
290 movw%?\\t%0, %1
291 ldr%?\\t%0, %1
292 ldr%?\\t%0, %1
293 str%?\\t%1, %0
294 str%?\\t%1, %0"
295 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load1,load1,store1,store1")
296 (set_attr "length" "2,4,2,4,4,4,4,4,4")
297 (set_attr "predicable" "yes")
298 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
299 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
300 (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
301 )
303 (define_insn "tls_load_dot_plus_four"
304 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
305 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
306 (const_int 4)
307 (match_operand 3 "" "")]
308 UNSPEC_PIC_BASE)))
309 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
310 "TARGET_THUMB2"
311 "*
312 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
313 INTVAL (operands[3]));
314 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
315 "
316 [(set_attr "length" "4,4,6,6")
317 (set_attr "type" "multiple")]
318 )
320 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
321 ;; of the messiness associated with the ARM patterns.
322 (define_insn "*thumb2_movhi_insn"
323 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
324 (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))]
325 "TARGET_THUMB2
326 && (register_operand (operands[0], HImode)
327 || register_operand (operands[1], HImode))"
328 "@
329 mov%?\\t%0, %1\\t%@ movhi
330 mov%?\\t%0, %1\\t%@ movhi
331 mov%?\\t%0, %1\\t%@ movhi
332 movw%?\\t%0, %L1\\t%@ movhi
333 strh%?\\t%1, %0\\t%@ movhi
334 ldrh%?\\t%0, %1\\t%@ movhi"
335 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
336 (set_attr "predicable" "yes")
337 (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
338 (set_attr "length" "2,4,2,4,4,4")
339 (set_attr "pool_range" "*,*,*,*,*,4094")
340 (set_attr "neg_pool_range" "*,*,*,*,*,250")]
341 )
343 (define_insn "*thumb2_storewb_pairsi"
344 [(set (match_operand:SI 0 "register_operand" "=&kr")
345 (plus:SI (match_operand:SI 1 "register_operand" "0")
346 (match_operand:SI 2 "const_int_operand" "n")))
347 (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
348 (match_operand:SI 3 "register_operand" "r"))
349 (set (mem:SI (plus:SI (match_dup 0)
350 (match_operand:SI 5 "const_int_operand" "n")))
351 (match_operand:SI 4 "register_operand" "r"))]
352 "TARGET_THUMB2
353 && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
354 "strd\\t%3, %4, [%0, %2]!"
355 [(set_attr "type" "store2")]
356 )
358 (define_insn "*thumb2_cmpsi_neg_shiftsi"
359 [(set (reg:CC CC_REGNUM)
360 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
361 (neg:SI (match_operator:SI 3 "shift_operator"
362 [(match_operand:SI 1 "s_register_operand" "r")
363 (match_operand:SI 2 "const_int_operand" "M")]))))]
364 "TARGET_THUMB2"
365 "cmn%?\\t%0, %1%S3"
366 [(set_attr "conds" "set")
367 (set_attr "shift" "1")
368 (set_attr "type" "alus_shift_imm")]
369 )
371 (define_insn_and_split "*thumb2_mov_scc"
372 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
373 (match_operator:SI 1 "arm_comparison_operator_mode"
374 [(match_operand 2 "cc_register" "") (const_int 0)]))]
375 "TARGET_THUMB2"
376 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
377 "TARGET_THUMB2"
378 [(set (match_dup 0)
379 (if_then_else:SI (match_dup 1)
380 (const_int 1)
381 (const_int 0)))]
382 ""
383 [(set_attr "conds" "use")
384 (set_attr "enabled_for_depr_it" "yes,no")
385 (set_attr "length" "8,10")
386 (set_attr "type" "multiple")]
387 )
389 (define_insn_and_split "*thumb2_mov_negscc"
390 [(set (match_operand:SI 0 "s_register_operand" "=r")
391 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
392 [(match_operand 2 "cc_register" "") (const_int 0)])))]
393 "TARGET_THUMB2 && !arm_restrict_it"
394 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
395 "TARGET_THUMB2"
396 [(set (match_dup 0)
397 (if_then_else:SI (match_dup 1)
398 (match_dup 3)
399 (const_int 0)))]
400 {
401 operands[3] = GEN_INT (~0);
402 }
403 [(set_attr "conds" "use")
404 (set_attr "length" "10")
405 (set_attr "type" "multiple")]
406 )
408 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
409 [(set (match_operand:SI 0 "low_register_operand" "=l")
410 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
411 [(match_operand 2 "cc_register" "") (const_int 0)])))]
412 "TARGET_THUMB2 && arm_restrict_it"
413 "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
414 "&& reload_completed"
415 [(set (match_dup 0)
416 (match_dup 3))
417 (cond_exec (match_dup 4)
418 (set (match_dup 0)
419 (const_int 0)))]
420 {
421 operands[3] = GEN_INT (~0);
422 machine_mode mode = GET_MODE (operands[2]);
423 enum rtx_code rc = GET_CODE (operands[1]);
425 if (mode == CCFPmode || mode == CCFPEmode)
426 rc = reverse_condition_maybe_unordered (rc);
427 else
428 rc = reverse_condition (rc);
429 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
431 }
432 [(set_attr "conds" "use")
433 (set_attr "length" "8")
434 (set_attr "type" "multiple")]
435 )
437 (define_insn_and_split "*thumb2_mov_notscc"
438 [(set (match_operand:SI 0 "s_register_operand" "=r")
439 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
440 [(match_operand 2 "cc_register" "") (const_int 0)])))]
441 "TARGET_THUMB2 && !arm_restrict_it"
442 "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
443 "TARGET_THUMB2"
444 [(set (match_dup 0)
445 (if_then_else:SI (match_dup 1)
446 (match_dup 3)
447 (match_dup 4)))]
448 {
449 operands[3] = GEN_INT (~1);
450 operands[4] = GEN_INT (~0);
451 }
452 [(set_attr "conds" "use")
453 (set_attr "length" "10")
454 (set_attr "type" "multiple")]
455 )
457 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
458 [(set (match_operand:SI 0 "low_register_operand" "=l")
459 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
460 [(match_operand 2 "cc_register" "") (const_int 0)])))]
461 "TARGET_THUMB2 && arm_restrict_it"
462 "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
463 "&& reload_completed"
464 [(set (match_dup 0)
465 (match_dup 3))
466 (cond_exec (match_dup 4)
467 (set (match_dup 0)
468 (ashift:SI (match_dup 0)
469 (const_int 1))))]
470 {
471 operands[3] = GEN_INT (~0);
472 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
473 VOIDmode, operands[2], const0_rtx);
474 }
475 [(set_attr "conds" "use")
476 (set_attr "length" "8")
477 (set_attr "type" "multiple")]
478 )
480 (define_insn_and_split "*thumb2_movsicc_insn"
481 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
482 (if_then_else:SI
483 (match_operator 3 "arm_comparison_operator"
484 [(match_operand 4 "cc_register" "") (const_int 0)])
485 (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
486 (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
487 "TARGET_THUMB2"
488 "@
489 it\\t%D3\;mov%D3\\t%0, %2
490 it\\t%d3\;mov%d3\\t%0, %1
491 it\\t%D3\;mov%D3\\t%0, %2
492 it\\t%D3\;mvn%D3\\t%0, #%B2
493 it\\t%d3\;mov%d3\\t%0, %1
494 it\\t%d3\;mvn%d3\\t%0, #%B1
495 #
496 #
497 #
498 #
499 #
500 #"
501 ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
502 ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
503 ; alt 8: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
504 ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
505 ; alt 10: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
506 ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
507 "&& reload_completed"
508 [(const_int 0)]
509 {
510 enum rtx_code rev_code;
511 machine_mode mode;
512 rtx rev_cond;
514 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
515 operands[3],
516 gen_rtx_SET (operands[0], operands[1])));
517 rev_code = GET_CODE (operands[3]);
518 mode = GET_MODE (operands[4]);
519 if (mode == CCFPmode || mode == CCFPEmode)
520 rev_code = reverse_condition_maybe_unordered (rev_code);
521 else
522 rev_code = reverse_condition (rev_code);
524 rev_cond = gen_rtx_fmt_ee (rev_code,
525 VOIDmode,
526 gen_rtx_REG (mode, CC_REGNUM),
527 const0_rtx);
528 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
529 rev_cond,
530 gen_rtx_SET (operands[0], operands[2])));
531 DONE;
532 }
533 [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
534 (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
535 (set_attr "conds" "use")
536 (set_attr_alternative "type"
537 [(if_then_else (match_operand 2 "const_int_operand" "")
538 (const_string "mov_imm")
539 (const_string "mov_reg"))
540 (if_then_else (match_operand 1 "const_int_operand" "")
541 (const_string "mov_imm")
542 (const_string "mov_reg"))
543 (if_then_else (match_operand 2 "const_int_operand" "")
544 (const_string "mov_imm")
545 (const_string "mov_reg"))
546 (const_string "mvn_imm")
547 (if_then_else (match_operand 1 "const_int_operand" "")
548 (const_string "mov_imm")
549 (const_string "mov_reg"))
550 (const_string "mvn_imm")
551 (const_string "multiple")
552 (const_string "multiple")
553 (const_string "multiple")
554 (const_string "multiple")
555 (const_string "multiple")
556 (const_string "multiple")])]
557 )
559 (define_insn "*thumb2_movsfcc_soft_insn"
560 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
561 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
562 [(match_operand 4 "cc_register" "") (const_int 0)])
563 (match_operand:SF 1 "s_register_operand" "0,r")
564 (match_operand:SF 2 "s_register_operand" "r,0")))]
565 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
566 "@
567 it\\t%D3\;mov%D3\\t%0, %2
568 it\\t%d3\;mov%d3\\t%0, %1"
569 [(set_attr "length" "6,6")
570 (set_attr "conds" "use")
571 (set_attr "type" "multiple")]
572 )
574 (define_insn "*call_reg_thumb2"
575 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
576 (match_operand 1 "" ""))
577 (use (match_operand 2 "" ""))
578 (clobber (reg:SI LR_REGNUM))]
579 "TARGET_THUMB2"
580 "blx%?\\t%0"
581 [(set_attr "type" "call")]
582 )
584 (define_insn "*call_value_reg_thumb2"
585 [(set (match_operand 0 "" "")
586 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
587 (match_operand 2 "" "")))
588 (use (match_operand 3 "" ""))
589 (clobber (reg:SI LR_REGNUM))]
590 "TARGET_THUMB2"
591 "blx\\t%1"
592 [(set_attr "type" "call")]
593 )
595 (define_insn "*thumb2_indirect_jump"
596 [(set (pc)
597 (match_operand:SI 0 "register_operand" "l*r"))]
598 "TARGET_THUMB2"
599 "bx\\t%0"
600 [(set_attr "conds" "clob")
601 (set_attr "type" "branch")]
602 )
603 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
604 ;; addresses will have the thumb bit set correctly.
607 (define_insn_and_split "*thumb2_and_scc"
608 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
609 (and:SI (match_operator:SI 1 "arm_comparison_operator"
610 [(match_operand 2 "cc_register" "") (const_int 0)])
611 (match_operand:SI 3 "s_register_operand" "r")))]
612 "TARGET_THUMB2"
613 "#" ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
614 "&& reload_completed"
615 [(set (match_dup 0)
616 (and:SI (match_dup 3) (const_int 1)))
617 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
618 {
619 machine_mode mode = GET_MODE (operands[2]);
620 enum rtx_code rc = GET_CODE (operands[1]);
622 if (mode == CCFPmode || mode == CCFPEmode)
623 rc = reverse_condition_maybe_unordered (rc);
624 else
625 rc = reverse_condition (rc);
626 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
627 }
628 [(set_attr "conds" "use")
629 (set_attr "type" "multiple")
630 (set (attr "length") (if_then_else (match_test "arm_restrict_it")
631 (const_int 8)
632 (const_int 10)))]
633 )
635 (define_insn_and_split "*thumb2_ior_scc"
636 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
637 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
638 [(match_operand 2 "cc_register" "") (const_int 0)])
639 (match_operand:SI 3 "s_register_operand" "0,?r")))]
640 "TARGET_THUMB2 && !arm_restrict_it"
641 "@
642 it\\t%d1\;orr%d1\\t%0, %3, #1
643 #"
644 ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
645 "&& reload_completed
646 && REGNO (operands [0]) != REGNO (operands[3])"
647 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
648 (cond_exec (match_dup 4) (set (match_dup 0)
649 (ior:SI (match_dup 3) (const_int 1))))]
650 {
651 machine_mode mode = GET_MODE (operands[2]);
652 enum rtx_code rc = GET_CODE (operands[1]);
654 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
655 if (mode == CCFPmode || mode == CCFPEmode)
656 rc = reverse_condition_maybe_unordered (rc);
657 else
658 rc = reverse_condition (rc);
659 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
660 }
661 [(set_attr "conds" "use")
662 (set_attr "length" "6,10")
663 (set_attr "type" "multiple")]
664 )
666 (define_insn_and_split "*thumb2_ior_scc_strict_it"
667 [(set (match_operand:SI 0 "s_register_operand" "=&r")
668 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
669 [(match_operand 3 "cc_register" "") (const_int 0)])
670 (match_operand:SI 1 "s_register_operand" "r")))]
671 "TARGET_THUMB2 && arm_restrict_it"
672 "#" ; orr\\t%0, %1, #1\;it\\t%D2\;mov%D2\\t%0, %1
673 "&& reload_completed"
674 [(set (match_dup 0) (ior:SI (match_dup 1) (const_int 1)))
675 (cond_exec (match_dup 4)
676 (set (match_dup 0) (match_dup 1)))]
677 {
678 machine_mode mode = GET_MODE (operands[3]);
679 rtx_code rc = GET_CODE (operands[2]);
681 if (mode == CCFPmode || mode == CCFPEmode)
682 rc = reverse_condition_maybe_unordered (rc);
683 else
684 rc = reverse_condition (rc);
685 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
686 }
687 [(set_attr "conds" "use")
688 (set_attr "length" "8")
689 (set_attr "type" "multiple")]
690 )
692 (define_insn "*thumb2_cond_move"
693 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
694 (if_then_else:SI (match_operator 3 "equality_operator"
695 [(match_operator 4 "arm_comparison_operator"
696 [(match_operand 5 "cc_register" "") (const_int 0)])
697 (const_int 0)])
698 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
699 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
700 "TARGET_THUMB2"
701 "*
702 if (GET_CODE (operands[3]) == NE)
703 {
704 if (which_alternative != 1)
705 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
706 if (which_alternative != 0)
707 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
708 return \"\";
709 }
710 switch (which_alternative)
711 {
712 case 0:
713 output_asm_insn (\"it\\t%d4\", operands);
714 break;
715 case 1:
716 output_asm_insn (\"it\\t%D4\", operands);
717 break;
718 case 2:
719 if (arm_restrict_it)
720 output_asm_insn (\"it\\t%D4\", operands);
721 else
722 output_asm_insn (\"ite\\t%D4\", operands);
723 break;
724 default:
725 abort();
726 }
727 if (which_alternative != 0)
728 {
729 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
730 if (arm_restrict_it && which_alternative == 2)
731 output_asm_insn (\"it\\t%d4\", operands);
732 }
733 if (which_alternative != 1)
734 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
735 return \"\";
736 "
737 [(set_attr "conds" "use")
738 (set_attr "length" "6,6,10")
739 (set_attr "type" "multiple")]
740 )
742 (define_insn "*thumb2_cond_arith"
743 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
744 (match_operator:SI 5 "shiftable_operator"
745 [(match_operator:SI 4 "arm_comparison_operator"
746 [(match_operand:SI 2 "s_register_operand" "r,r")
747 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
748 (match_operand:SI 1 "s_register_operand" "0,?r")]))
749 (clobber (reg:CC CC_REGNUM))]
750 "TARGET_THUMB2 && !arm_restrict_it"
751 "*
752 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
753 return \"%i5\\t%0, %1, %2, lsr #31\";
755 output_asm_insn (\"cmp\\t%2, %3\", operands);
756 if (GET_CODE (operands[5]) == AND)
757 {
758 output_asm_insn (\"ite\\t%D4\", operands);
759 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
760 }
761 else if (GET_CODE (operands[5]) == MINUS)
762 {
763 output_asm_insn (\"ite\\t%D4\", operands);
764 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
765 }
766 else if (which_alternative != 0)
767 {
768 output_asm_insn (\"ite\\t%D4\", operands);
769 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
770 }
771 else
772 output_asm_insn (\"it\\t%d4\", operands);
773 return \"%i5%d4\\t%0, %1, #1\";
774 "
775 [(set_attr "conds" "clob")
776 (set_attr "length" "14")
777 (set_attr "type" "multiple")]
778 )
780 (define_insn_and_split "*thumb2_cond_arith_strict_it"
781 [(set (match_operand:SI 0 "s_register_operand" "=l")
782 (match_operator:SI 5 "shiftable_operator_strict_it"
783 [(match_operator:SI 4 "arm_comparison_operator"
784 [(match_operand:SI 2 "s_register_operand" "r")
785 (match_operand:SI 3 "arm_rhs_operand" "rI")])
786 (match_operand:SI 1 "s_register_operand" "0")]))
787 (clobber (reg:CC CC_REGNUM))]
788 "TARGET_THUMB2 && arm_restrict_it"
789 "#"
790 "&& reload_completed"
791 [(const_int 0)]
792 {
793 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
794 {
795 /* %i5 %0, %1, %2, lsr #31 */
796 rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
797 rtx op = NULL_RTX;
799 switch (GET_CODE (operands[5]))
800 {
801 case AND:
802 op = gen_rtx_AND (SImode, shifted_op, operands[1]);
803 break;
804 case PLUS:
805 op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
806 break;
807 default: gcc_unreachable ();
808 }
809 emit_insn (gen_rtx_SET (operands[0], op));
810 DONE;
811 }
813 /* "cmp %2, %3" */
814 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
815 gen_rtx_COMPARE (CCmode, operands[2],
816 operands[3])));
818 if (GET_CODE (operands[5]) == AND)
819 {
820 /* %i5 %0, %1, #1
821 it%D4
822 mov%D4 %0, #0 */
823 enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
824 emit_insn (gen_rtx_SET (operands[0], gen_rtx_AND (SImode, operands[1],
825 GEN_INT (1))));
826 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
827 gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
828 gen_rtx_SET (operands[0], const0_rtx)));
829 DONE;
830 }
831 else
832 {
833 /* it\\t%d4
834 %i5%d4\\t%0, %1, #1 */
835 emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
836 VOIDmode,
837 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
838 gen_rtx_SET (operands[0],
839 gen_rtx_PLUS (SImode,
840 operands[1],
841 GEN_INT (1)))));
842 DONE;
843 }
844 FAIL;
845 }
846 [(set_attr "conds" "clob")
847 (set_attr "length" "12")
848 (set_attr "type" "multiple")]
849 )
851 (define_insn "*thumb2_cond_sub"
852 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
853 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
854 (match_operator:SI 4 "arm_comparison_operator"
855 [(match_operand:SI 2 "s_register_operand" "r,r")
856 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
857 (clobber (reg:CC CC_REGNUM))]
858 "TARGET_THUMB2"
859 "*
860 output_asm_insn (\"cmp\\t%2, %3\", operands);
861 if (which_alternative != 0)
862 {
863 if (arm_restrict_it)
864 {
865 output_asm_insn (\"mov\\t%0, %1\", operands);
866 output_asm_insn (\"it\\t%d4\", operands);
867 }
868 else
869 {
870 output_asm_insn (\"ite\\t%D4\", operands);
871 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
872 }
873 }
874 else
875 output_asm_insn (\"it\\t%d4\", operands);
876 return \"sub%d4\\t%0, %1, #1\";
877 "
878 [(set_attr "conds" "clob")
879 (set_attr "length" "10,14")
880 (set_attr "type" "multiple")]
881 )
883 (define_insn_and_split "*thumb2_negscc"
884 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
885 (neg:SI (match_operator 3 "arm_comparison_operator"
886 [(match_operand:SI 1 "s_register_operand" "r")
887 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
888 (clobber (reg:CC CC_REGNUM))]
889 "TARGET_THUMB2"
890 "#"
891 "&& reload_completed"
892 [(const_int 0)]
893 {
894 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
896 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
897 {
898 /* Emit asr\\t%0, %1, #31 */
899 emit_insn (gen_rtx_SET (operands[0],
900 gen_rtx_ASHIFTRT (SImode,
901 operands[1],
902 GEN_INT (31))));
903 DONE;
904 }
905 else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
906 {
907 /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
908 if (CONST_INT_P (operands[2]))
909 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
910 GEN_INT (- INTVAL (operands[2]))));
911 else
912 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
914 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
915 gen_rtx_NE (SImode,
916 cc_reg,
917 const0_rtx),
918 gen_rtx_SET (operands[0],
919 GEN_INT (~0))));
920 DONE;
921 }
922 else
923 {
924 /* Emit: cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
925 enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
926 machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
927 rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
929 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[1],
930 operands[2])));
932 emit_insn (gen_rtx_SET (operands[0], GEN_INT (~0)));
934 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
935 gen_rtx_fmt_ee (rc,
936 VOIDmode,
937 tmp1,
938 const0_rtx),
939 gen_rtx_SET (operands[0], const0_rtx)));
940 DONE;
941 }
942 FAIL;
943 }
944 [(set_attr "conds" "clob")
945 (set_attr "length" "14")
946 (set_attr "type" "multiple")]
947 )
949 (define_insn "*thumb2_movcond"
950 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
951 (if_then_else:SI
952 (match_operator 5 "arm_comparison_operator"
953 [(match_operand:SI 3 "s_register_operand" "r,r,r")
954 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
955 (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
956 (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
957 (clobber (reg:CC CC_REGNUM))]
958 "TARGET_THUMB2"
959 "*
960 if (GET_CODE (operands[5]) == LT
961 && (operands[4] == const0_rtx))
962 {
963 if (which_alternative != 1 && REG_P (operands[1]))
964 {
965 if (operands[2] == const0_rtx)
966 return \"and\\t%0, %1, %3, asr #31\";
967 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
968 }
969 else if (which_alternative != 0 && REG_P (operands[2]))
970 {
971 if (operands[1] == const0_rtx)
972 return \"bic\\t%0, %2, %3, asr #31\";
973 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
974 }
975 /* The only case that falls through to here is when both ops 1 & 2
976 are constants. */
977 }
979 if (GET_CODE (operands[5]) == GE
980 && (operands[4] == const0_rtx))
981 {
982 if (which_alternative != 1 && REG_P (operands[1]))
983 {
984 if (operands[2] == const0_rtx)
985 return \"bic\\t%0, %1, %3, asr #31\";
986 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
987 }
988 else if (which_alternative != 0 && REG_P (operands[2]))
989 {
990 if (operands[1] == const0_rtx)
991 return \"and\\t%0, %2, %3, asr #31\";
992 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
993 }
994 /* The only case that falls through to here is when both ops 1 & 2
995 are constants. */
996 }
997 if (CONST_INT_P (operands[4])
998 && !const_ok_for_arm (INTVAL (operands[4])))
999 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
1000 else
1001 output_asm_insn (\"cmp\\t%3, %4\", operands);
1002 switch (which_alternative)
1003 {
1004 case 0:
1005 output_asm_insn (\"it\\t%D5\", operands);
1006 break;
1007 case 1:
1008 output_asm_insn (\"it\\t%d5\", operands);
1009 break;
1010 case 2:
1011 if (arm_restrict_it)
1012 {
1013 output_asm_insn (\"mov\\t%0, %1\", operands);
1014 output_asm_insn (\"it\\t%D5\", operands);
1015 }
1016 else
1017 output_asm_insn (\"ite\\t%d5\", operands);
1018 break;
1019 default:
1020 abort();
1021 }
1022 if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1023 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1024 if (which_alternative != 1)
1025 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1026 return \"\";
1027 "
1028 [(set_attr "conds" "clob")
1029 (set_attr "length" "10,10,14")
1030 (set_attr "type" "multiple")]
1031 )
1033 ;; Zero and sign extension instructions.
1035 ;; All supported Thumb2 implementations are armv6, so only that case is
1036 ;; provided.
1037 (define_insn "*thumb2_extendqisi_v6"
1038 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1039 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1040 "TARGET_THUMB2 && arm_arch6"
1041 "@
1042 sxtb%?\\t%0, %1
1043 ldrsb%?\\t%0, %1"
1044 [(set_attr "type" "extend,load_byte")
1045 (set_attr "predicable" "yes")
1046 (set_attr "predicable_short_it" "no")
1047 (set_attr "pool_range" "*,4094")
1048 (set_attr "neg_pool_range" "*,250")]
1049 )
1051 (define_insn "*thumb2_zero_extendhisi2_v6"
1052 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1053 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1054 "TARGET_THUMB2 && arm_arch6"
1055 "@
1056 uxth%?\\t%0, %1
1057 ldrh%?\\t%0, %1"
1058 [(set_attr "type" "extend,load_byte")
1059 (set_attr "predicable" "yes")
1060 (set_attr "predicable_short_it" "no")
1061 (set_attr "pool_range" "*,4094")
1062 (set_attr "neg_pool_range" "*,250")]
1063 )
1065 (define_insn "thumb2_zero_extendqisi2_v6"
1066 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1067 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1068 "TARGET_THUMB2 && arm_arch6"
1069 "@
1070 uxtb%?\\t%0, %1
1071 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
1072 [(set_attr "type" "extend,load_byte")
1073 (set_attr "predicable" "yes")
1074 (set_attr "predicable_short_it" "no")
1075 (set_attr "pool_range" "*,4094")
1076 (set_attr "neg_pool_range" "*,250")]
1077 )
1079 (define_insn "thumb2_casesi_internal"
1080 [(parallel [(set (pc)
1081 (if_then_else
1082 (leu (match_operand:SI 0 "s_register_operand" "r")
1083 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1084 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1085 (label_ref (match_operand 2 "" ""))))
1086 (label_ref (match_operand 3 "" ""))))
1087 (clobber (reg:CC CC_REGNUM))
1088 (clobber (match_scratch:SI 4 "=&r"))
1089 (use (label_ref (match_dup 2)))])]
1090 "TARGET_THUMB2 && !flag_pic"
1091 "* return thumb2_output_casesi(operands);"
1092 [(set_attr "conds" "clob")
1093 (set_attr "length" "16")
1094 (set_attr "type" "multiple")]
1095 )
1097 (define_insn "thumb2_casesi_internal_pic"
1098 [(parallel [(set (pc)
1099 (if_then_else
1100 (leu (match_operand:SI 0 "s_register_operand" "r")
1101 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1102 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1103 (label_ref (match_operand 2 "" ""))))
1104 (label_ref (match_operand 3 "" ""))))
1105 (clobber (reg:CC CC_REGNUM))
1106 (clobber (match_scratch:SI 4 "=&r"))
1107 (clobber (match_scratch:SI 5 "=r"))
1108 (use (label_ref (match_dup 2)))])]
1109 "TARGET_THUMB2 && flag_pic"
1110 "* return thumb2_output_casesi(operands);"
1111 [(set_attr "conds" "clob")
1112 (set_attr "length" "20")
1113 (set_attr "type" "multiple")]
1114 )
1116 (define_insn "*thumb2_return"
1117 [(simple_return)]
1118 "TARGET_THUMB2"
1119 "* return output_return_instruction (const_true_rtx, true, false, true);"
1120 [(set_attr "type" "branch")
1121 (set_attr "length" "4")]
1122 )
1124 (define_insn_and_split "thumb2_eh_return"
1125 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1126 VUNSPEC_EH_RETURN)
1127 (clobber (match_scratch:SI 1 "=&r"))]
1128 "TARGET_THUMB2"
1129 "#"
1130 "&& reload_completed"
1131 [(const_int 0)]
1132 "
1133 {
1134 thumb_set_return_address (operands[0], operands[1]);
1135 DONE;
1136 }"
1137 )
1139 (define_insn "*thumb2_alusi3_short"
1140 [(set (match_operand:SI 0 "s_register_operand" "=l")
1141 (match_operator:SI 3 "thumb_16bit_operator"
1142 [(match_operand:SI 1 "s_register_operand" "0")
1143 (match_operand:SI 2 "s_register_operand" "l")]))
1144 (clobber (reg:CC CC_REGNUM))]
1145 "TARGET_THUMB2 && reload_completed
1146 && GET_CODE(operands[3]) != PLUS
1147 && GET_CODE(operands[3]) != MINUS"
1148 "%I3%!\\t%0, %1, %2"
1149 [(set_attr "predicable" "yes")
1150 (set_attr "length" "2")
1151 (set_attr "type" "alu_sreg")]
1152 )
1154 (define_insn "*thumb2_shiftsi3_short"
1155 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1156 (match_operator:SI 3 "shift_operator"
1157 [(match_operand:SI 1 "low_register_operand" "0,l")
1158 (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1159 (clobber (reg:CC CC_REGNUM))]
1160 "TARGET_THUMB2 && reload_completed
1161 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1162 || REG_P (operands[2]))"
1163 "* return arm_output_shift(operands, 2);"
1164 [(set_attr "predicable" "yes")
1165 (set_attr "shift" "1")
1166 (set_attr "length" "2")
1167 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1168 (const_string "alu_shift_imm")
1169 (const_string "alu_shift_reg")))]
1170 )
1172 (define_insn "*thumb2_mov<mode>_shortim"
1173 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1174 (match_operand:QHSI 1 "const_int_operand" "I"))
1175 (clobber (reg:CC CC_REGNUM))]
1176 "TARGET_THUMB2 && reload_completed"
1177 "mov%!\t%0, %1"
1178 [(set_attr "predicable" "yes")
1179 (set_attr "length" "2")
1180 (set_attr "type" "mov_imm")]
1181 )
1183 (define_insn "*thumb2_addsi_short"
1184 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1185 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1186 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1187 (clobber (reg:CC CC_REGNUM))]
1188 "TARGET_THUMB2 && reload_completed"
1189 "*
1190 HOST_WIDE_INT val;
1192 if (CONST_INT_P (operands[2]))
1193 val = INTVAL(operands[2]);
1194 else
1195 val = 0;
1197 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1198 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1199 return \"sub%!\\t%0, %1, #%n2\";
1200 else
1201 return \"add%!\\t%0, %1, %2\";
1202 "
1203 [(set_attr "predicable" "yes")
1204 (set_attr "length" "2")
1205 (set_attr_alternative "type"
1206 [(if_then_else (match_operand 2 "const_int_operand" "")
1207 (const_string "alu_imm")
1208 (const_string "alu_sreg"))
1209 (const_string "alu_imm")])]
1210 )
1212 (define_insn "*thumb2_subsi_short"
1213 [(set (match_operand:SI 0 "low_register_operand" "=l")
1214 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1215 (match_operand:SI 2 "low_register_operand" "l")))
1216 (clobber (reg:CC CC_REGNUM))]
1217 "TARGET_THUMB2 && reload_completed"
1218 "sub%!\\t%0, %1, %2"
1219 [(set_attr "predicable" "yes")
1220 (set_attr "length" "2")
1221 (set_attr "type" "alu_sreg")]
1222 )
1224 (define_peephole2
1225 [(set (match_operand:CC 0 "cc_register" "")
1226 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1227 (match_operand:SI 2 "const_int_operand" "")))]
1228 "TARGET_THUMB2
1229 && peep2_reg_dead_p (1, operands[1])
1230 && satisfies_constraint_Pw (operands[2])"
1231 [(parallel
1232 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1233 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1234 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1235 )
1237 (define_peephole2
1238 [(match_scratch:SI 3 "l")
1239 (set (match_operand:CC 0 "cc_register" "")
1240 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1241 (match_operand:SI 2 "const_int_operand" "")))]
1242 "TARGET_THUMB2
1243 && satisfies_constraint_Px (operands[2])"
1244 [(parallel
1245 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1246 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1247 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1248 )
1250 (define_insn "thumb2_addsi3_compare0"
1251 [(set (reg:CC_NOOV CC_REGNUM)
1252 (compare:CC_NOOV
1253 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1254 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1255 (const_int 0)))
1256 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1257 (plus:SI (match_dup 1) (match_dup 2)))]
1258 "TARGET_THUMB2"
1259 "*
1260 HOST_WIDE_INT val;
1262 if (CONST_INT_P (operands[2]))
1263 val = INTVAL (operands[2]);
1264 else
1265 val = 0;
1267 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1268 return \"subs\\t%0, %1, #%n2\";
1269 else
1270 return \"adds\\t%0, %1, %2\";
1271 "
1272 [(set_attr "conds" "set")
1273 (set_attr "length" "2,2,4")
1274 (set_attr_alternative "type"
1275 [(if_then_else (match_operand 2 "const_int_operand" "")
1276 (const_string "alus_imm")
1277 (const_string "alus_sreg"))
1278 (const_string "alus_imm")
1279 (if_then_else (match_operand 2 "const_int_operand" "")
1280 (const_string "alus_imm")
1281 (const_string "alus_sreg"))])]
1282 )
1284 (define_insn "*thumb2_addsi3_compare0_scratch"
1285 [(set (reg:CC_NOOV CC_REGNUM)
1286 (compare:CC_NOOV
1287 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1288 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1289 (const_int 0)))]
1290 "TARGET_THUMB2"
1291 "*
1292 HOST_WIDE_INT val;
1294 if (CONST_INT_P (operands[1]))
1295 val = INTVAL (operands[1]);
1296 else
1297 val = 0;
1299 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1300 return \"cmp\\t%0, #%n1\";
1301 else
1302 return \"cmn\\t%0, %1\";
1303 "
1304 [(set_attr "conds" "set")
1305 (set_attr "length" "2,4")
1306 (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
1307 (const_string "alus_imm")
1308 (const_string "alus_sreg")))]
1309 )
1311 (define_insn "*thumb2_mulsi_short"
1312 [(set (match_operand:SI 0 "low_register_operand" "=l")
1313 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1314 (match_operand:SI 2 "low_register_operand" "l")))
1315 (clobber (reg:CC CC_REGNUM))]
1316 "TARGET_THUMB2 && optimize_size && reload_completed"
1317 "mul%!\\t%0, %2, %0"
1318 [(set_attr "predicable" "yes")
1319 (set_attr "length" "2")
1320 (set_attr "type" "muls")])
1322 (define_insn "*thumb2_mulsi_short_compare0"
1323 [(set (reg:CC_NOOV CC_REGNUM)
1324 (compare:CC_NOOV
1325 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1326 (match_operand:SI 2 "register_operand" "l"))
1327 (const_int 0)))
1328 (set (match_operand:SI 0 "register_operand" "=l")
1329 (mult:SI (match_dup 1) (match_dup 2)))]
1330 "TARGET_THUMB2 && optimize_size"
1331 "muls\\t%0, %2, %0"
1332 [(set_attr "length" "2")
1333 (set_attr "type" "muls")])
1335 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1336 [(set (reg:CC_NOOV CC_REGNUM)
1337 (compare:CC_NOOV
1338 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1339 (match_operand:SI 2 "register_operand" "l"))
1340 (const_int 0)))
1341 (clobber (match_scratch:SI 0 "=l"))]
1342 "TARGET_THUMB2 && optimize_size"
1343 "muls\\t%0, %2, %0"
1344 [(set_attr "length" "2")
1345 (set_attr "type" "muls")])
1347 (define_insn "*thumb2_cbz"
1348 [(set (pc) (if_then_else
1349 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1350 (const_int 0))
1351 (label_ref (match_operand 1 "" ""))
1352 (pc)))
1353 (clobber (reg:CC CC_REGNUM))]
1354 "TARGET_THUMB2"
1355 "*
1356 if (get_attr_length (insn) == 2)
1357 return \"cbz\\t%0, %l1\";
1358 else
1359 return \"cmp\\t%0, #0\;beq\\t%l1\";
1360 "
1361 [(set (attr "length")
1362 (if_then_else
1363 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1364 (le (minus (match_dup 1) (pc)) (const_int 128))
1365 (not (match_test "which_alternative")))
1366 (const_int 2)
1367 (const_int 8)))
1368 (set_attr "type" "branch,multiple")]
1369 )
1371 (define_insn "*thumb2_cbnz"
1372 [(set (pc) (if_then_else
1373 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1374 (const_int 0))
1375 (label_ref (match_operand 1 "" ""))
1376 (pc)))
1377 (clobber (reg:CC CC_REGNUM))]
1378 "TARGET_THUMB2"
1379 "*
1380 if (get_attr_length (insn) == 2)
1381 return \"cbnz\\t%0, %l1\";
1382 else
1383 return \"cmp\\t%0, #0\;bne\\t%l1\";
1384 "
1385 [(set (attr "length")
1386 (if_then_else
1387 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1388 (le (minus (match_dup 1) (pc)) (const_int 128))
1389 (not (match_test "which_alternative")))
1390 (const_int 2)
1391 (const_int 8)))
1392 (set_attr "type" "branch,multiple")]
1393 )
1395 (define_insn "*thumb2_one_cmplsi2_short"
1396 [(set (match_operand:SI 0 "low_register_operand" "=l")
1397 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1398 (clobber (reg:CC CC_REGNUM))]
1399 "TARGET_THUMB2 && reload_completed"
1400 "mvn%!\t%0, %1"
1401 [(set_attr "predicable" "yes")
1402 (set_attr "length" "2")
1403 (set_attr "type" "mvn_reg")]
1404 )
1406 (define_insn "*thumb2_negsi2_short"
1407 [(set (match_operand:SI 0 "low_register_operand" "=l")
1408 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1409 (clobber (reg:CC CC_REGNUM))]
1410 "TARGET_THUMB2 && reload_completed"
1411 "neg%!\t%0, %1"
1412 [(set_attr "predicable" "yes")
1413 (set_attr "length" "2")
1414 (set_attr "type" "alu_sreg")]
1415 )
1417 ; Constants for op 2 will never be given to these patterns.
1418 (define_insn_and_split "*iordi_notdi_di"
1419 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1420 (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1421 (match_operand:DI 2 "s_register_operand" "r,0")))]
1422 "TARGET_THUMB2"
1423 "#"
1424 "TARGET_THUMB2 && reload_completed"
1425 [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1426 (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1427 "
1428 {
1429 operands[3] = gen_highpart (SImode, operands[0]);
1430 operands[0] = gen_lowpart (SImode, operands[0]);
1431 operands[4] = gen_highpart (SImode, operands[1]);
1432 operands[1] = gen_lowpart (SImode, operands[1]);
1433 operands[5] = gen_highpart (SImode, operands[2]);
1434 operands[2] = gen_lowpart (SImode, operands[2]);
1435 }"
1436 [(set_attr "length" "8")
1437 (set_attr "predicable" "yes")
1438 (set_attr "predicable_short_it" "no")
1439 (set_attr "type" "multiple")]
1440 )
1442 (define_insn_and_split "*iordi_notzesidi_di"
1443 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1444 (ior:DI (not:DI (zero_extend:DI
1445 (match_operand:SI 2 "s_register_operand" "r,r")))
1446 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1447 "TARGET_THUMB2"
1448 "#"
1449 ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1450 "TARGET_THUMB2 && reload_completed"
1451 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1452 (set (match_dup 3) (const_int -1))]
1453 "
1454 {
1455 operands[3] = gen_highpart (SImode, operands[0]);
1456 operands[0] = gen_lowpart (SImode, operands[0]);
1457 operands[1] = gen_lowpart (SImode, operands[1]);
1458 }"
1459 [(set_attr "length" "4,8")
1460 (set_attr "predicable" "yes")
1461 (set_attr "predicable_short_it" "no")
1462 (set_attr "type" "multiple")]
1463 )
1465 (define_insn_and_split "*iordi_notdi_zesidi"
1466 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1467 (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1468 (zero_extend:DI
1469 (match_operand:SI 1 "s_register_operand" "r,r"))))]
1470 "TARGET_THUMB2"
1471 "#"
1472 "TARGET_THUMB2 && reload_completed"
1473 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1474 (set (match_dup 3) (not:SI (match_dup 4)))]
1475 "
1476 {
1477 operands[3] = gen_highpart (SImode, operands[0]);
1478 operands[0] = gen_lowpart (SImode, operands[0]);
1479 operands[1] = gen_lowpart (SImode, operands[1]);
1480 operands[4] = gen_highpart (SImode, operands[2]);
1481 operands[2] = gen_lowpart (SImode, operands[2]);
1482 }"
1483 [(set_attr "length" "8")
1484 (set_attr "predicable" "yes")
1485 (set_attr "predicable_short_it" "no")
1486 (set_attr "type" "multiple")]
1487 )
1489 (define_insn_and_split "*iordi_notsesidi_di"
1490 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1491 (ior:DI (not:DI (sign_extend:DI
1492 (match_operand:SI 2 "s_register_operand" "r,r")))
1493 (match_operand:DI 1 "s_register_operand" "0,r")))]
1494 "TARGET_THUMB2"
1495 "#"
1496 "TARGET_THUMB2 && reload_completed"
1497 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1498 (set (match_dup 3) (ior:SI (not:SI
1499 (ashiftrt:SI (match_dup 2) (const_int 31)))
1500 (match_dup 4)))]
1501 "
1502 {
1503 operands[3] = gen_highpart (SImode, operands[0]);
1504 operands[0] = gen_lowpart (SImode, operands[0]);
1505 operands[4] = gen_highpart (SImode, operands[1]);
1506 operands[1] = gen_lowpart (SImode, operands[1]);
1507 }"
1508 [(set_attr "length" "8")
1509 (set_attr "predicable" "yes")
1510 (set_attr "predicable_short_it" "no")
1511 (set_attr "type" "multiple")]
1512 )
1514 (define_insn "*orsi_notsi_si"
1515 [(set (match_operand:SI 0 "s_register_operand" "=r")
1516 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1517 (match_operand:SI 1 "s_register_operand" "r")))]
1518 "TARGET_THUMB2"
1519 "orn%?\\t%0, %1, %2"
1520 [(set_attr "predicable" "yes")
1521 (set_attr "predicable_short_it" "no")
1522 (set_attr "type" "logic_reg")]
1523 )
1525 (define_insn "*orsi_not_shiftsi_si"
1526 [(set (match_operand:SI 0 "s_register_operand" "=r")
1527 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1528 [(match_operand:SI 2 "s_register_operand" "r")
1529 (match_operand:SI 3 "const_int_operand" "M")]))
1530 (match_operand:SI 1 "s_register_operand" "r")))]
1531 "TARGET_THUMB2"
1532 "orn%?\\t%0, %1, %2%S4"
1533 [(set_attr "predicable" "yes")
1534 (set_attr "predicable_short_it" "no")
1535 (set_attr "shift" "2")
1536 (set_attr "type" "alu_shift_imm")]
1537 )
1539 (define_peephole2
1540 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1541 (compare:CC_NOOV (zero_extract:SI
1542 (match_operand:SI 1 "low_register_operand" "")
1543 (const_int 1)
1544 (match_operand:SI 2 "const_int_operand" ""))
1545 (const_int 0)))
1546 (match_scratch:SI 3 "l")
1547 (set (pc)
1548 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1549 [(match_dup 0) (const_int 0)])
1550 (match_operand 5 "" "")
1551 (match_operand 6 "" "")))]
1552 "TARGET_THUMB2
1553 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1554 && peep2_reg_dead_p (2, operands[0])"
1555 [(parallel [(set (match_dup 0)
1556 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1557 (const_int 0)))
1558 (clobber (match_dup 3))])
1559 (set (pc)
1560 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1561 (match_dup 5) (match_dup 6)))]
1562 "
1563 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1564 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1565 VOIDmode, operands[0], const0_rtx);
1566 ")
1568 (define_peephole2
1569 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1570 (compare:CC_NOOV (zero_extract:SI
1571 (match_operand:SI 1 "low_register_operand" "")
1572 (match_operand:SI 2 "const_int_operand" "")
1573 (const_int 0))
1574 (const_int 0)))
1575 (match_scratch:SI 3 "l")
1576 (set (pc)
1577 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1578 [(match_dup 0) (const_int 0)])
1579 (match_operand 5 "" "")
1580 (match_operand 6 "" "")))]
1581 "TARGET_THUMB2
1582 && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
1583 && peep2_reg_dead_p (2, operands[0])"
1584 [(parallel [(set (match_dup 0)
1585 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1586 (const_int 0)))
1587 (clobber (match_dup 3))])
1588 (set (pc)
1589 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1590 (match_dup 5) (match_dup 6)))]
1591 "
1592 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1593 ")
1595 ;; Define the subtract-one-and-jump insns so loop.c
1596 ;; knows what to generate.
1597 (define_expand "doloop_end"
1598 [(use (match_operand 0 "" "")) ; loop pseudo
1599 (use (match_operand 1 "" ""))] ; label
1600 "TARGET_32BIT"
1601 "
1602 {
1603 /* Currently SMS relies on the do-loop pattern to recognize loops
1604 where (1) the control part consists of all insns defining and/or
1605 using a certain 'count' register and (2) the loop count can be
1606 adjusted by modifying this register prior to the loop.
1607 ??? The possible introduction of a new block to initialize the
1608 new IV can potentially affect branch optimizations. */
1609 if (optimize > 0 && flag_modulo_sched)
1610 {
1611 rtx s0;
1612 rtx bcomp;
1613 rtx loc_ref;
1614 rtx cc_reg;
1615 rtx insn;
1616 rtx cmp;
1618 if (GET_MODE (operands[0]) != SImode)
1619 FAIL;
1621 s0 = operands [0];
1622 if (TARGET_THUMB2)
1623 insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1624 else
1625 insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1627 cmp = XVECEXP (PATTERN (insn), 0, 0);
1628 cc_reg = SET_DEST (cmp);
1629 bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1630 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1631 emit_jump_insn (gen_rtx_SET (pc_rtx,
1632 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1633 loc_ref, pc_rtx)));
1634 DONE;
1635 }else
1636 FAIL;
1637 }")