| blob | cf22bfec3f5513f56d22c866231edbf322ff6945 |
1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
53 machine_mode *);
59 /* Debug facility for use in GDB. */
61 \f
62 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
63 the result of operation CODE applied to OP0 (and OP1 if it is a binary
64 operation). OP0_MODE is OP0's mode.
66 If the last insn does not set TARGET, don't do anything, but return 1.
68 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
69 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
70 try again, ensuring that TARGET is not one of the operands. */
72 static int
75 {
77 rtx set;
78 rtx note;
95 ;
97 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
98 a value changing in the insn, so the note would be invalid for CSE. */
101 {
105 {
106 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
107 over expanding it as temp = MEM op X, MEM = temp. If the target
108 supports MEM = MEM op X instructions, it is sometimes too hard
109 to reconstruct that form later, especially if X is also a memory,
110 and due to multiple occurrences of addresses the address might
111 be forced into register unnecessarily.
112 Note that not emitting the REG_EQUIV note might inhibit
113 CSE in some cases. */
122 }
124 }
131 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
138 {
147 {
153 else
157 }
158 /* FALLTHRU */
162 }
163 else
169 }
170 \f
171 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
172 for a widening operation would be. In most cases this would be OP0, but if
173 that's a constant it'll be VOIDmode, which isn't useful. */
175 static machine_mode
177 {
180 machine_mode result;
186 else
193 }
194 \f
195 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
196 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
197 not actually do a sign-extend or zero-extend, but can leave the
198 higher-order bits of the result rtx undefined, for example, in the case
199 of logical operations, but not right shifts. */
201 static rtx
204 {
205 rtx result;
206 scalar_int_mode int_mode;
208 /* If we don't have to extend and this is a constant, return it. */
212 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
213 extend since it will be more efficient to do so unless the signedness of
214 a promoted object differs from our extension. */
221 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
222 SUBREG. */
226 /* Otherwise, get an object of MODE, clobber it, and set the low-order
227 part to OP. */
233 }
234 \f
235 /* Expand vector widening operations.
237 There are two different classes of operations handled here:
238 1) Operations whose result is wider than all the arguments to the operation.
239 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
240 In this case OP0 and optionally OP1 would be initialized,
241 but WIDE_OP wouldn't (not relevant for this case).
242 2) Operations whose result is of the same size as the last argument to the
243 operation, but wider than all the other arguments to the operation.
244 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
245 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
247 E.g, when called to expand the following operations, this is how
248 the arguments will be initialized:
249 nops OP0 OP1 WIDE_OP
250 widening-sum 2 oprnd0 - oprnd1
251 widening-dot-product 3 oprnd0 oprnd1 oprnd2
252 widening-mult 2 oprnd0 oprnd1 -
253 type-promotion (vec-unpack) 1 oprnd0 - - */
255 rtx
258 {
262 optab widen_pattern_optab;
275 /* The sign is from the result type rather than operand's type
276 for these ops. */
277 widen_pattern_optab
285 {
286 /* For VEC_UNPACK_{LO,HI}_EXPR if the mode of op0 and result is
287 the same scalar mode for VECTOR_BOOLEAN_TYPE_P vectors, use
288 vec_unpacks_sbool_{lo,hi}_optab, so that we can pass in
289 the pattern number of elements in the wider vector. */
290 widen_pattern_optab
294 }
296 {
301 ;
303 {
305 /* Same as optab_vector_mixed_sign but flip the operands. */
307 }
310 else
313 widen_pattern_optab
315 }
316 else
317 widen_pattern_optab
323 tmode0);
324 else
331 {
335 }
337 /* The last operand is of a wider mode than the rest of the operands. */
341 {
345 }
356 }
358 /* Generate code to perform an operation specified by TERNARY_OPTAB
359 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
361 UNSIGNEDP is for the case where we have to widen the operands
362 to perform the operation. It says to use zero-extension.
364 If TARGET is nonzero, the value
365 is generated there, if it is convenient to do so.
366 In all cases an rtx is returned for the locus of the value;
367 this may or may not be TARGET. */
369 rtx
372 {
384 }
387 /* Like expand_binop, but return a constant rtx if the result can be
388 calculated at compile time. The arguments and return value are
389 otherwise the same as for expand_binop. */
391 rtx
395 {
397 {
402 }
405 }
407 /* Like simplify_expand_binop, but always put the result in TARGET.
408 Return true if the expansion succeeded. */
410 bool
414 {
422 }
424 /* Create a new vector value in VMODE with all elements set to OP. The
425 mode of OP must be the element mode of VMODE. If OP is a constant,
426 then the return value will be a constant. */
428 rtx
430 {
432 rtvec vec;
441 {
447 }
452 /* ??? If the target doesn't have a vec_init, then we have no easy way
453 of performing this operation. Most of this sort of generic support
454 is hidden away in the vector lowering support in gimple. */
467 }
469 /* This subroutine of expand_doubleword_shift handles the cases in which
470 the effective shift value is >= BITS_PER_WORD. The arguments and return
471 value are the same as for the parent routine, except that SUPERWORD_OP1
472 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
473 INTO_TARGET may be null if the caller has decided to calculate it. */
475 static bool
479 {
486 {
487 /* For a signed right shift, we must fill OUTOF_TARGET with copies
488 of the sign bit, otherwise we must fill it with zeros. */
491 else
497 }
499 }
501 /* This subroutine of expand_doubleword_shift handles the cases in which
502 the effective shift value is < BITS_PER_WORD. The arguments and return
503 value are the same as for the parent routine. */
505 static bool
511 {
518 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
519 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
520 the opposite direction to BINOPTAB. */
522 {
528 }
529 else
530 {
531 /* We must avoid shifting by BITS_PER_WORD bits since that is either
532 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
533 has unknown behavior. Do a single shift first, then shift by the
534 remainder. It's OK to use ~OP1 as the remainder if shift counts
535 are truncated to the mode size. */
539 {
540 tmp = immed_wide_int_const
544 }
545 else
546 {
551 }
552 }
560 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
561 so the result can go directly into INTO_TARGET if convenient. */
567 /* Now OR in the bits carried over from OUTOF_INPUT. */
572 /* Use a standard word_mode shift for the out-of half. */
579 }
582 /* Try implementing expand_doubleword_shift using conditional moves.
583 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
584 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
585 are the shift counts to use in the former and latter case. All other
586 arguments are the same as the parent routine. */
588 static bool
596 {
599 /* Put the superword version of the output into OUTOF_SUPERWORD and
600 INTO_SUPERWORD. */
603 {
604 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
605 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
610 }
611 else
612 {
618 }
620 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
627 /* Select between them. Do the INTO half first because INTO_SUPERWORD
628 might be the current value of OUTOF_TARGET. */
641 }
643 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
644 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
645 input operand; the shift moves bits in the direction OUTOF_INPUT->
646 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
647 of the target. OP1 is the shift count and OP1_MODE is its mode.
648 If OP1 is constant, it will have been truncated as appropriate
649 and is known to be nonzero.
651 If SHIFT_MASK is zero, the result of word shifts is undefined when the
652 shift count is outside the range [0, BITS_PER_WORD). This routine must
653 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
655 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
656 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
657 fill with zeros or sign bits as appropriate.
659 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
660 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
661 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
662 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
663 are undefined.
665 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
666 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
667 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
668 function wants to calculate it itself.
670 Return true if the shift could be successfully synthesized. */
672 static bool
678 {
682 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
683 fill the result with sign or zero bits as appropriate. If so, the value
684 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
685 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
686 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
688 This isn't worthwhile for constant shifts since the optimizers will
689 cope better with in-range shift counts. */
693 {
703 }
705 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
706 is true when the effective shift value is less than BITS_PER_WORD.
707 Set SUPERWORD_OP1 to the shift count that should be used to shift
708 OUTOF_INPUT into INTO_TARGET when the condition is false. */
711 {
712 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
713 is a subword shift count. */
719 }
720 else
721 {
722 /* Set CMP1 to OP1 - BITS_PER_WORD. */
728 }
732 /* If we can compute the condition at compile time, pick the
733 appropriate subroutine. */
736 {
741 else
746 }
748 /* Try using conditional moves to generate straight-line code. */
750 {
760 }
762 /* As a last resort, use branches to select the correct alternative. */
766 NO_DEFER_POP;
770 OK_DEFER_POP;
789 }
790 \f
791 /* Subroutine of expand_binop. Perform a double word multiplication of
792 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
793 as the target's word_mode. This function return NULL_RTX if anything
794 goes wrong, in which case it may have already emitted instructions
795 which need to be deleted.
797 If we want to multiply two two-word values and have normal and widening
798 multiplies of single-word values, we can do this with three smaller
799 multiplications.
801 The multiplication proceeds as follows:
802 _______________________
803 [__op0_high_|__op0_low__]
804 _______________________
805 * [__op1_high_|__op1_low__]
806 _______________________________________________
807 _______________________
808 (1) [__op0_low__*__op1_low__]
809 _______________________
810 (2a) [__op0_low__*__op1_high_]
811 _______________________
812 (2b) [__op0_high_*__op1_low__]
813 _______________________
814 (3) [__op0_high_*__op1_high_]
817 This gives a 4-word result. Since we are only interested in the
818 lower 2 words, partial result (3) and the upper words of (2a) and
819 (2b) don't need to be calculated. Hence (2a) and (2b) can be
820 calculated using non-widening multiplication.
822 (1), however, needs to be calculated with an unsigned widening
823 multiplication. If this operation is not directly supported we
824 try using a signed widening multiplication and adjust the result.
825 This adjustment works as follows:
827 If both operands are positive then no adjustment is needed.
829 If the operands have different signs, for example op0_low < 0 and
830 op1_low >= 0, the instruction treats the most significant bit of
831 op0_low as a sign bit instead of a bit with significance
832 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
833 with 2**BITS_PER_WORD - op0_low, and two's complements the
834 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
835 the result.
837 Similarly, if both operands are negative, we need to add
838 (op0_low + op1_low) * 2**BITS_PER_WORD.
840 We use a trick to adjust quickly. We logically shift op0_low right
841 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
842 op0_high (op1_high) before it is used to calculate 2b (2a). If no
843 logical shift exists, we do an arithmetic right shift and subtract
844 the 0 or -1. */
846 static rtx
849 {
861 /* If we're using an unsigned multiply to directly compute the product
862 of the low-order words of the operands and perform any required
863 adjustments of the operands, we begin by trying two more multiplications
864 and then computing the appropriate sum.
866 We have checked above that the required addition is provided.
867 Full-word addition will normally always succeed, especially if
868 it is provided at all, so we don't worry about its failure. The
869 multiplication may well fail, however, so we do handle that. */
872 {
873 /* ??? This could be done with emit_store_flag where available. */
879 else
880 {
887 }
891 }
898 /* OP0_HIGH should now be dead. */
901 {
902 /* ??? This could be done with emit_store_flag where available. */
908 else
909 {
916 }
920 }
927 /* OP1_HIGH should now be dead. */
935 /* *_widen_optab needs to determine operand mode, make sure at least
936 one operand has non-VOID mode. */
943 else
955 }
957 /* Subroutine of expand_binop. Optimize unsigned double-word OP0 % OP1 for
958 constant OP1. If for some bit in [BITS_PER_WORD / 2, BITS_PER_WORD] range
959 (prefer higher bits) ((1w << bit) % OP1) == 1, then the modulo can be
960 computed in word-mode as ((OP0 & (bit - 1)) + ((OP0 >> bit) & (bit - 1))
961 + (OP0 >> (2 * bit))) % OP1. Whether we need to sum 2, 3 or 4 values
962 depends on the bit value, if 2, then carry from the addition needs to be
963 added too, i.e. like:
964 sum += __builtin_add_overflow (low, high, &sum)
966 Optimize signed double-word OP0 % OP1 similarly, just apply some correction
967 factor to the sum before doing unsigned remainder, in the form of
968 sum += (((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & const);
969 then perform unsigned
970 remainder = sum % OP1;
971 and finally
972 remainder += ((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1); */
974 static rtx
976 {
982 {
988 {
989 /* For signed modulo we need to add correction to the sum
990 and that might again overflow. */
1013 OPTAB_DIRECT);
1016 }
1017 else
1018 {
1019 /* Code below uses GEN_INT, so we need the masks to be representable
1020 in HOST_WIDE_INTs. */
1023 /* If op0 is e.g. -1 or -2 unsigned, then the 2 additions might
1024 overflow. Consider 64-bit -1ULL for word size 32, if we add
1025 0x7fffffffU + 0x7fffffffU + 3U, it wraps around to 1. */
1033 {
1034 /* For signed modulo, compute it as unsigned modulo of
1035 sum with a correction added to it if OP0 is negative,
1036 such that the result can be computed as unsigned
1037 remainder + ((OP1 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1). */
1041 /* wmod2 == -wmod1. */
1044 {
1048 /* Now verify if the count sums can't overflow, and punt
1049 if they could. */
1060 mode);
1069 OPTAB_DIRECT);
1072 }
1073 }
1076 {
1090 OPTAB_DIRECT);
1095 else
1100 }
1102 {
1107 }
1108 }
1111 word_mode),
1117 {
1119 {
1121 mode);
1127 }
1130 word_mode),
1138 }
1141 /* Punt if we need any library calls. */
1144 else
1150 }
1152 }
1154 /* Similarly to the above function, but compute both quotient and remainder.
1155 Quotient can be computed from the remainder as:
1156 rem = op0 % op1; // Handled using expand_doubleword_mod
1157 quot = (op0 - rem) * inv; // inv is multiplicative inverse of op1 modulo
1158 // 2 * BITS_PER_WORD
1160 We can also handle cases where op1 is a multiple of power of two constant
1161 and constant handled by expand_doubleword_mod.
1162 op11 = 1 << __builtin_ctz (op1);
1163 op12 = op1 / op11;
1164 rem1 = op0 % op12; // Handled using expand_doubleword_mod
1165 quot1 = (op0 - rem1) * inv; // inv is multiplicative inverse of op12 modulo
1166 // 2 * BITS_PER_WORD
1167 rem = (quot1 % op11) * op12 + rem1;
1168 quot = quot1 / op11; */
1170 rtx
1173 {
1176 /* Negative dividend should have been optimized into positive,
1177 similarly modulo by 1 and modulo by power of two is optimized
1178 differently too. */
1185 {
1189 }
1213 {
1236 }
1238 /* Punt if we need any library calls. */
1241 else
1249 }
1250 \f
1251 /* Wrapper around expand_binop which takes an rtx code to specify
1252 the operation to perform, not an optab pointer. All other
1253 arguments are the same. */
1254 rtx
1258 {
1263 }
1265 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1266 binop. Order them according to commutative_operand_precedence and, if
1267 possible, try to put TARGET or a pseudo first. */
1268 static bool
1270 {
1280 /* With equal precedence, both orders are ok, but it is better if the
1281 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1284 else
1286 }
1288 /* Return true if BINOPTAB implements a shift operation. */
1290 static bool
1292 {
1294 {
1306 }
1307 }
1309 /* Return true if BINOPTAB implements a commutative binary operation. */
1311 static bool
1313 {
1319 }
1321 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1322 optimizing, and if the operand is a constant that costs more than
1323 1 instruction, force the constant into a register and return that
1324 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1326 static rtx
1329 {
1333 && optimize
1337 {
1339 {
1343 }
1344 else
1347 }
1349 }
1351 /* Helper function for expand_binop: handle the case where there
1352 is an insn ICODE that directly implements the indicated operation.
1353 Returns null if this is not possible. */
1354 static rtx
1359 {
1369 /* If it is a commutative operator and the modes would match
1370 if we would swap the operands, we can save the conversions. */
1377 /* If we are optimizing, force expensive constants into a register. */
1381 else
1382 /* Shifts and rotates often use a different mode for op1 from op0;
1383 for VOIDmode constants we don't know the mode, so force it
1384 to be canonicalized using convert_modes. */
1387 /* In case the insn wants input operands in modes different from
1388 those of the actual operands, convert the operands. It would
1389 seem that we don't need to convert CONST_INTs, but we do, so
1390 that they're properly zero-extended, sign-extended or truncated
1391 for their mode. */
1395 {
1398 }
1403 {
1406 }
1408 /* If operation is commutative,
1409 try to make the first operand a register.
1410 Even better, try to make it the same as the target.
1411 Also try to make the last operand a constant. */
1416 /* Now, if insn's predicates don't allow our operands, put them into
1417 pseudo regs. */
1426 {
1427 /* The mode of the result is different then the mode of the
1428 arguments. */
1432 {
1435 }
1436 }
1437 else
1445 {
1446 /* If PAT is composed of more than one insn, try to add an appropriate
1447 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1448 operand, call expand_binop again, this time without a target. */
1453 {
1457 }
1461 }
1464 }
1466 /* Generate code to perform an operation specified by BINOPTAB
1467 on operands OP0 and OP1, with result having machine-mode MODE.
1469 UNSIGNEDP is for the case where we have to widen the operands
1470 to perform the operation. It says to use zero-extension.
1472 If TARGET is nonzero, the value
1473 is generated there, if it is convenient to do so.
1474 In all cases an rtx is returned for the locus of the value;
1475 this may or may not be TARGET. */
1477 rtx
1480 {
1481 enum optab_methods next_methods
1486 machine_mode wider_mode;
1487 scalar_int_mode int_mode;
1488 rtx libfunc;
1489 rtx temp;
1495 /* If subtracting an integer constant, convert this into an addition of
1496 the negated constant. */
1499 {
1502 }
1503 /* For shifts, constant invalid op1 might be expanded from different
1504 mode than MODE. As those are invalid, force them to a register
1505 to avoid further problems during expansion. */
1509 {
1512 }
1514 /* Record where to delete back to if we backtrack. */
1517 /* If we can do it with a three-operand insn, do so. */
1520 {
1522 {
1525 }
1526 else
1529 {
1534 }
1535 }
1537 /* If we were trying to rotate, and that didn't work, try rotating
1538 the other direction before falling back to shifts and bitwise-or. */
1544 {
1546 rtx newop1;
1553 else
1562 }
1564 /* If this is a multiply, see if we can do a widening operation that
1565 takes operands of this mode and makes a wider mode. */
1570 ? umul_widen_optab
1573 {
1574 /* *_widen_optab needs to determine operand mode, make sure at least
1575 one operand has non-VOID mode. */
1583 {
1587 else
1589 }
1590 }
1592 /* If this is a vector shift by a scalar, see if we can do a vector
1593 shift by a vector. If so, broadcast the scalar into a vector. */
1595 {
1611 {
1612 /* The scalar may have been extended to be too wide. Truncate
1613 it back to the proper size to fit in the broadcast vector. */
1623 {
1628 }
1629 }
1630 }
1632 /* Look for a wider mode of the same class for which we think we
1633 can open-code the operation. Check for a widening multiply at the
1634 wider mode as well. */
1639 {
1640 machine_mode next_mode;
1645 ? umul_widen_optab
1649 {
1653 /* For certain integer operations, we need not actually extend
1654 the narrow operands, as long as we will truncate
1655 the results to the same narrowness. */
1662 {
1669 }
1673 /* The second operand of a shift must always be extended. */
1680 {
1683 {
1688 }
1689 else
1691 }
1692 else
1694 }
1695 }
1697 /* If operation is commutative,
1698 try to make the first operand a register.
1699 Even better, try to make it the same as the target.
1700 Also try to make the last operand a constant. */
1705 /* These can be done a word at a time. */
1710 {
1714 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1715 won't be accurate, so use a new target. */
1726 /* Do the actual arithmetic. */
1734 {
1746 }
1752 {
1755 }
1756 }
1758 /* Synthesize double word shifts from single word shifts. */
1768 {
1770 scalar_int_mode op1_mode;
1778 /* Apply the truncation to constant shifts. */
1785 /* Make sure that this is a combination that expand_doubleword_shift
1786 can handle. See the comments there for details. */
1790 {
1796 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1797 won't be accurate, so use a new target. */
1808 /* OUTOF_* is the word we are shifting bits away from, and
1809 INTO_* is the word that we are shifting bits towards, thus
1810 they differ depending on the direction of the shift and
1811 WORDS_BIG_ENDIAN. */
1826 {
1832 }
1834 }
1835 }
1837 /* Synthesize double word rotates from single word shifts. */
1844 {
1848 rtx inter;
1851 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1852 won't be accurate, so use a new target. Do this also if target is not
1853 a REG, first because having a register instead may open optimization
1854 opportunities, and second because if target and op0 happen to be MEMs
1855 designating the same location, we would risk clobbering it too early
1856 in the code sequence we generate below. */
1870 /* OUTOF_* is the word we are shifting bits away from, and
1871 INTO_* is the word that we are shifting bits towards, thus
1872 they differ depending on the direction of the shift and
1873 WORDS_BIG_ENDIAN. */
1885 {
1886 /* This is just a word swap. */
1890 }
1891 else
1892 {
1904 {
1907 }
1908 else
1909 {
1912 }
1913 rtx first_shift_count_rtx
1915 rtx second_shift_count_rtx
1928 else
1948 }
1954 {
1957 }
1958 }
1960 /* These can be done a word at a time by propagating carries. */
1965 {
1972 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1973 value is one of those, use it. Otherwise, use 1 since it is the
1974 one easiest to get. */
1975 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1977 #else
1979 #endif
1981 /* Prepare the operands. */
1990 /* Indicate for flow that the entire target reg is being set. */
1994 /* Do the actual arithmetic. */
1996 {
2001 rtx x;
2003 /* Main add/subtract of the input operands. */
2011 {
2012 /* Store carry from main add/subtract. */
2019 }
2022 {
2023 rtx newx;
2025 /* Add/subtract previous carry to main result. */
2032 {
2033 /* Get out carry from adding/subtracting carry in. */
2041 /* Logical-ior the two poss. carry together. */
2047 }
2049 }
2050 else
2051 {
2054 }
2057 }
2060 {
2063 {
2070 target);
2071 }
2072 else
2076 }
2078 else
2080 }
2082 /* Attempt to synthesize double word multiplies using a sequence of word
2083 mode multiplications. We first attempt to generate a sequence using a
2084 more efficient unsigned widening multiply, and if that fails we then
2085 try using a signed widening multiply. */
2092 {
2096 {
2101 }
2106 {
2111 }
2114 {
2116 {
2118 product);
2120 REG_EQUAL,
2125 }
2127 }
2128 }
2130 /* Attempt to synthetize double word modulo by constant divisor. */
2135 && optimize
2141 int_mode) == CODE_FOR_nothing
2145 {
2151 else
2152 {
2154 binoptab == umod_optab
2160 }
2162 {
2164 {
2166 res);
2171 }
2173 }
2174 else
2176 }
2178 /* It can't be open-coded in this mode.
2179 Use a library call if one is available and caller says that's ok. */
2184 {
2188 rtx value;
2193 {
2195 /* Specify unsigned here,
2196 since negative shift counts are meaningless. */
2198 }
2204 /* Pass 1 for NO_QUEUE so we don't lose any increments
2205 if the libcall is cse'd or moved. */
2216 trapv ? NULL_RTX
2221 }
2225 /* It can't be done in this mode. Can we do it in a wider mode? */
2229 {
2230 /* Caller says, don't even try. */
2233 }
2235 /* Compute the value of METHODS to pass to recursive calls.
2236 Don't allow widening to be tried recursively. */
2240 /* Look for a wider mode of the same class for which it appears we can do
2241 the operation. */
2244 {
2245 /* This code doesn't make sense for conversion optabs, since we
2246 wouldn't then want to extend the operands to be the same size
2247 as the result. */
2250 {
2254 {
2258 /* For certain integer operations, we need not actually extend
2259 the narrow operands, as long as we will truncate
2260 the results to the same narrowness. */
2272 /* The second operand of a shift must always be extended. */
2279 {
2282 {
2287 }
2288 else
2290 }
2291 else
2293 }
2294 }
2295 }
2299 }
2300 \f
2301 /* Expand a binary operator which has both signed and unsigned forms.
2302 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2303 signed operations.
2305 If we widen unsigned operands, we may use a signed wider operation instead
2306 of an unsigned wider operation, since the result would be the same. */
2308 rtx
2312 {
2313 rtx temp;
2317 /* Do it without widening, if possible. */
2323 /* Try widening to a signed int. Disable any direct use of any
2324 signed insn in the current mode. */
2330 /* For unsigned operands, try widening to an unsigned int. */
2337 /* Use the right width libcall if that exists. */
2343 /* Must widen and use a libcall, use either signed or unsigned. */
2350 egress:
2351 /* Undo the fiddling above. */
2355 }
2356 \f
2357 /* Generate code to perform an operation specified by UNOPPTAB
2358 on operand OP0, with two results to TARG0 and TARG1.
2359 We assume that the order of the operands for the instruction
2360 is TARG0, TARG1, OP0.
2362 Either TARG0 or TARG1 may be zero, but what that means is that
2363 the result is not actually wanted. We will generate it into
2364 a dummy pseudo-reg and discard it. They may not both be zero.
2366 Returns 1 if this operation can be performed; 0 if not. */
2368 int
2371 {
2374 machine_mode wider_mode;
2385 /* Record where to go back to if we fail. */
2389 {
2398 }
2400 /* It can't be done in this mode. Can we do it in a wider mode? */
2403 {
2405 {
2407 {
2413 {
2417 }
2418 else
2420 }
2421 }
2422 }
2426 }
2427 \f
2428 /* Generate code to perform an operation specified by BINOPTAB
2429 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2430 We assume that the order of the operands for the instruction
2431 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2432 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2434 Either TARG0 or TARG1 may be zero, but what that means is that
2435 the result is not actually wanted. We will generate it into
2436 a dummy pseudo-reg and discard it. They may not both be zero.
2438 Returns 1 if this operation can be performed; 0 if not. */
2440 int
2443 {
2446 machine_mode wider_mode;
2457 /* Record where to go back to if we fail. */
2461 {
2468 /* If we are optimizing, force expensive constants into a register. */
2479 }
2481 /* It can't be done in this mode. Can we do it in a wider mode? */
2484 {
2486 {
2488 {
2496 {
2500 }
2501 else
2503 }
2504 }
2505 }
2509 }
2511 /* Expand the two-valued library call indicated by BINOPTAB, but
2512 preserve only one of the values. If TARG0 is non-NULL, the first
2513 value is placed into TARG0; otherwise the second value is placed
2514 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2515 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2516 This routine assumes that the value returned by the library call is
2517 as if the return value was of an integral mode twice as wide as the
2518 mode of OP0. Returns 1 if the call was successful. */
2520 bool
2523 {
2524 machine_mode mode;
2525 machine_mode libval_mode;
2526 rtx libval;
2528 rtx libfunc;
2530 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2538 /* The value returned by the library function will have twice as
2539 many bits as the nominal MODE. */
2543 libval_mode,
2546 /* Get the part of VAL containing the value that we want. */
2551 /* Move the into the desired location. */
2556 }
2558 \f
2559 /* Wrapper around expand_unop which takes an rtx code to specify
2560 the operation to perform, not an optab pointer. All other
2561 arguments are the same. */
2562 rtx
2565 {
2570 }
2572 /* Try calculating
2573 (clz:narrow x)
2574 as
2575 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2577 A similar operation can be used for clrsb. UNOPTAB says which operation
2578 we are trying to expand. */
2579 static rtx
2581 {
2582 opt_scalar_int_mode wider_mode_iter;
2584 {
2587 {
2600 temp = expand_binop
2604 wider_mode),
2610 }
2611 }
2613 }
2615 /* Attempt to emit (clrsb:mode op0) as
2616 (plus:mode (clz:mode (xor:mode op0 (ashr:mode op0 (const_int prec-1))))
2617 (const_int -1))
2618 if CLZ_DEFINED_VALUE_AT_ZERO (mode, val) is 2 and val is prec,
2619 or as
2620 (clz:mode (ior:mode (xor:mode (ashl:mode op0 (const_int 1))
2621 (ashr:mode op0 (const_int prec-1)))
2622 (const_int 1)))
2623 otherwise. */
2625 static rtx
2627 {
2637 else
2642 {
2646 {
2647 fail:
2650 }
2651 }
2660 OPTAB_DIRECT);
2665 {
2670 }
2676 {
2681 }
2689 }
2691 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2692 quantities, choosing which based on whether the high word is nonzero. */
2693 static rtx
2695 {
2704 /* If we were not given a target, use a word_mode register, not a
2705 'mode' register. The result will fit, and nobody is expecting
2706 anything bigger (the return type of __builtin_clz* is int). */
2710 /* In any case, write to a word_mode scratch in both branches of the
2711 conditional, so we can ensure there is a single move insn setting
2712 'target' to tag a REG_EQUAL note on. */
2717 /* If the high word is not equal to zero,
2718 then clz of the full value is clz of the high word. */
2732 /* Else clz of the full value is clz of the low word plus the number
2733 of bits in the high word. */
2757 fail:
2760 }
2762 /* Try calculating popcount of a double-word quantity as two popcount's of
2763 word-sized quantities and summing up the results. */
2764 static rtx
2766 {
2779 {
2782 }
2784 /* If we were not given a target, use a word_mode register, not a
2785 'mode' register. The result will fit, and nobody is expecting
2786 anything bigger (the return type of __builtin_popcount* is int). */
2798 }
2800 /* Try calculating
2801 (parity:wide x)
2802 as
2803 (parity:narrow (low (x) ^ high (x))) */
2804 static rtx
2806 {
2812 }
2814 /* Try calculating
2815 (bswap:narrow x)
2816 as
2817 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2818 static rtx
2820 {
2821 rtx x;
2823 opt_scalar_int_mode wider_mode_iter;
2848 {
2852 }
2853 else
2857 }
2859 /* Try calculating bswap as two bswaps of two word-sized operands. */
2861 static rtx
2863 {
2879 }
2881 /* Try calculating (parity x) as (and (popcount x) 1), where
2882 popcount can also be done in a wider mode. */
2883 static rtx
2885 {
2887 opt_scalar_int_mode wider_mode_iter;
2889 {
2892 {
2909 {
2913 else
2915 }
2916 else
2918 }
2919 }
2921 }
2923 /* Try calculating ctz(x) as K - clz(x & -x) ,
2924 where K is GET_MODE_PRECISION(mode) - 1.
2926 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2927 don't have to worry about what the hardware does in that case. (If
2928 the clz instruction produces the usual value at 0, which is K, the
2929 result of this code sequence will be -1; expand_ffs, below, relies
2930 on this. It might be nice to have it be K instead, for consistency
2931 with the (very few) processors that provide a ctz with a defined
2932 value, but that would take one more instruction, and it would be
2933 less convenient for expand_ffs anyway. */
2935 static rtx
2937 {
2939 rtx temp;
2958 {
2961 }
2969 }
2972 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2973 else with the sequence used by expand_clz.
2975 The ffs builtin promises to return zero for a zero value and ctz/clz
2976 may have an undefined value in that case. If they do not give us a
2977 convenient value, we have to generate a test and branch. */
2978 static rtx
2980 {
2983 rtx temp;
2987 {
2995 }
2997 {
3004 {
3007 }
3008 }
3009 else
3014 else
3015 {
3016 /* We don't try to do anything clever with the situation found
3017 on some processors (eg Alpha) where ctz(0:mode) ==
3018 bitsize(mode). If someone can think of a way to send N to -1
3019 and leave alone all values in the range 0..N-1 (where N is a
3020 power of two), cheaper than this test-and-branch, please add it.
3022 The test-and-branch is done after the operation itself, in case
3023 the operation sets condition codes that can be recycled for this.
3024 (This is true on i386, for instance.) */
3032 }
3034 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
3035 to produce a value in the range 0..bitsize. */
3048 fail:
3051 }
3053 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
3054 conditions, VAL may already be a SUBREG against which we cannot generate
3055 a further SUBREG. In this case, we expect forcing the value into a
3056 register will work around the situation. */
3058 static rtx
3060 machine_mode imode)
3061 {
3062 rtx ret;
3065 {
3069 }
3071 }
3073 /* Expand a floating point absolute value or negation operation via a
3074 logical operation on the sign bit. */
3076 static rtx
3079 {
3082 scalar_int_mode imode;
3083 rtx temp;
3086 /* The format has to have a simple sign bit. */
3095 /* Don't create negative zeros if the format doesn't support them. */
3100 {
3105 }
3106 else
3107 {
3112 else
3116 }
3129 {
3133 {
3138 {
3140 op0_piece,
3145 }
3146 else
3148 }
3154 }
3155 else
3156 {
3165 target);
3166 }
3169 }
3171 /* As expand_unop, but will fail rather than attempt the operation in a
3172 different mode or with a libcall. */
3173 static rtx
3176 {
3178 {
3188 {
3193 {
3196 }
3201 }
3202 }
3204 }
3206 /* Generate code to perform an operation specified by UNOPTAB
3207 on operand OP0, with result having machine-mode MODE.
3209 UNSIGNEDP is for the case where we have to widen the operands
3210 to perform the operation. It says to use zero-extension.
3212 If TARGET is nonzero, the value
3213 is generated there, if it is convenient to do so.
3214 In all cases an rtx is returned for the locus of the value;
3215 this may or may not be TARGET. */
3217 rtx
3220 {
3222 machine_mode wider_mode;
3223 scalar_int_mode int_mode;
3224 scalar_float_mode float_mode;
3225 rtx temp;
3226 rtx libfunc;
3232 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3234 /* Widening (or narrowing) clz needs special treatment. */
3236 {
3238 {
3245 {
3249 }
3250 }
3253 }
3256 {
3258 {
3265 }
3267 }
3274 {
3278 }
3286 {
3290 }
3292 /* Widening (or narrowing) bswap needs special treatment. */
3294 {
3295 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3296 or ROTATERT. First try these directly; if this fails, then try the
3297 obvious pair of shifts with allowed widening, as this will probably
3298 be always more efficient than the other fallback methods. */
3300 {
3305 {
3311 }
3314 {
3320 }
3331 {
3336 }
3339 }
3342 {
3347 /* We do not provide a 128-bit bswap in libgcc so force the use of
3348 a double bswap for 64-bit targets. */
3352 {
3356 }
3357 }
3360 }
3364 {
3366 {
3370 /* For certain operations, we need not actually extend
3371 the narrow operand, as long as we will truncate the
3372 results to the same narrowness. */
3380 unsignedp);
3383 {
3386 {
3391 }
3392 else
3394 }
3395 else
3397 }
3398 }
3400 /* These can be done a word at a time. */
3405 {
3417 /* Do the actual arithmetic. */
3419 {
3427 }
3434 }
3436 /* Emit ~op0 as op0 ^ -1. */
3440 {
3445 }
3448 {
3449 /* Try negating floating point values by flipping the sign bit. */
3451 {
3455 }
3457 /* If there is no negation pattern, and we have no negative zero,
3458 try subtracting from zero. */
3460 {
3467 }
3468 }
3470 /* Try calculating parity (x) as popcount (x) % 2. */
3472 {
3476 }
3478 /* Try implementing ffs (x) in terms of clz (x). */
3480 {
3484 }
3486 /* Try implementing ctz (x) in terms of clz (x). */
3488 {
3492 }
3494 try_libcall:
3495 /* Now try a library call in this mode. */
3498 {
3500 rtx value;
3501 rtx eq_value;
3504 /* All of these functions return small values. Thus we choose to
3505 have them return something that isn't a double-word. */
3509 outmode
3515 /* Pass 1 for NO_QUEUE so we don't lose any increments
3516 if the libcall is cse'd or moved. */
3526 else
3527 {
3534 }
3538 }
3540 /* It can't be done in this mode. Can we do it in a wider mode? */
3543 {
3545 {
3548 {
3552 /* For certain operations, we need not actually extend
3553 the narrow operand, as long as we will truncate the
3554 results to the same narrowness. */
3562 unsignedp);
3564 /* If we are generating clz using wider mode, adjust the
3565 result. Similarly for clrsb. */
3568 {
3569 scalar_int_mode wider_int_mode
3572 temp = expand_binop
3576 wider_int_mode),
3578 }
3580 /* Likewise for bswap. */
3582 {
3583 scalar_int_mode wider_int_mode
3595 }
3598 {
3600 {
3605 }
3606 else
3608 }
3609 else
3611 }
3612 }
3613 }
3615 /* One final attempt at implementing negation via subtraction,
3616 this time allowing widening of the operand. */
3618 {
3619 rtx temp;
3626 }
3629 }
3630 \f
3631 /* Emit code to compute the absolute value of OP0, with result to
3632 TARGET if convenient. (TARGET may be 0.) The return value says
3633 where the result actually is to be found.
3635 MODE is the mode of the operand; the mode of the result is
3636 different but can be deduced from MODE.
3638 */
3640 rtx
3643 {
3644 rtx temp;
3650 /* First try to do it with a special abs instruction. */
3656 /* For floating point modes, try clearing the sign bit. */
3657 scalar_float_mode float_mode;
3659 {
3663 }
3665 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3668 {
3675 OPTAB_WIDEN);
3681 }
3683 /* If this machine has expensive jumps, we can do integer absolute
3684 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3685 where W is the width of MODE. */
3687 scalar_int_mode int_mode;
3691 {
3697 OPTAB_LIB_WIDEN);
3705 }
3708 }
3710 rtx
3713 {
3714 rtx temp;
3725 /* If that does not win, use conditional jump and negate. */
3727 /* It is safe to use the target if it is the same
3728 as the source if this is also a pseudo register */
3742 NO_DEFER_POP;
3753 OK_DEFER_POP;
3755 }
3757 /* Emit code to compute the one's complement absolute value of OP0
3758 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3759 (TARGET may be NULL_RTX.) The return value says where the result
3760 actually is to be found.
3762 MODE is the mode of the operand; the mode of the result is
3763 different but can be deduced from MODE. */
3765 rtx
3767 {
3768 rtx temp;
3770 /* Not applicable for floating point modes. */
3774 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3776 {
3782 OPTAB_WIDEN);
3788 }
3790 /* If this machine has expensive jumps, we can do one's complement
3791 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3793 scalar_int_mode int_mode;
3797 {
3803 OPTAB_LIB_WIDEN);
3807 }
3810 }
3812 /* A subroutine of expand_copysign, perform the copysign operation using the
3813 abs and neg primitives advertised to exist on the target. The assumption
3814 is that we have a split register file, and leaving op0 in fp registers,
3815 and not playing with subregs so much, will help the register allocator. */
3817 static rtx
3820 {
3821 scalar_int_mode imode;
3823 rtx sign;
3829 /* Check if the back end provides an insn that handles signbit for the
3830 argument's mode. */
3833 {
3837 }
3838 else
3839 {
3841 {
3845 }
3846 else
3847 {
3853 else
3857 }
3863 }
3866 {
3871 }
3872 else
3873 {
3876 else
3878 }
3885 else
3893 }
3896 /* A subroutine of expand_copysign, perform the entire copysign operation
3897 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3898 is true if op0 is known to have its sign bit clear. */
3900 static rtx
3903 {
3904 scalar_int_mode imode;
3906 rtx temp;
3910 {
3915 }
3916 else
3917 {
3922 else
3926 }
3939 {
3943 {
3948 {
3950 op0_piece
3963 }
3964 else
3966 }
3972 }
3973 else
3974 {
3988 }
3991 }
3993 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3994 scalar floating point mode. Return NULL if we do not know how to
3995 expand the operation inline. */
3997 rtx
3999 {
4000 scalar_float_mode mode;
4003 rtx temp;
4008 /* First try to do it with a special instruction. */
4020 {
4024 }
4030 {
4035 }
4041 }
4042 \f
4043 /* Generate an instruction whose insn-code is INSN_CODE,
4044 with two operands: an output TARGET and an input OP0.
4045 TARGET *must* be nonzero, and the output is always stored there.
4046 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4047 the value that is stored into TARGET.
4049 Return false if expansion failed. */
4051 bool
4054 {
4074 }
4075 /* Generate an instruction whose insn-code is INSN_CODE,
4076 with two operands: an output TARGET and an input OP0.
4077 TARGET *must* be nonzero, and the output is always stored there.
4078 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4079 the value that is stored into TARGET. */
4081 void
4083 {
4086 }
4087 \f
4088 struct no_conflict_data
4089 {
4090 rtx target;
4093 };
4095 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
4096 the currently examined clobber / store has to stay in the list of
4097 insns that constitute the actual libcall block. */
4098 static void
4100 {
4103 /* If this inns directly contributes to setting the target, it must stay. */
4106 /* If we haven't committed to keeping any other insns in the list yet,
4107 there is nothing more to check. */
4110 /* If this insn sets / clobbers a register that feeds one of the insns
4111 already in the list, this insn has to stay too. */
4115 /* Likewise if this insn depends on a register set by a previous
4116 insn in the list, or if it sets a result (presumably a hard
4117 register) that is set or clobbered by a previous insn.
4118 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
4119 SET_DEST perform the former check on the address, and the latter
4120 check on the MEM. */
4127 }
4129 \f
4130 /* Emit code to make a call to a constant function or a library call.
4132 INSNS is a list containing all insns emitted in the call.
4133 These insns leave the result in RESULT. Our block is to copy RESULT
4134 to TARGET, which is logically equivalent to EQUIV.
4136 We first emit any insns that set a pseudo on the assumption that these are
4137 loading constants into registers; doing so allows them to be safely cse'ed
4138 between blocks. Then we emit all the other insns in the block, followed by
4139 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
4140 note with an operand of EQUIV. */
4142 static void
4145 {
4149 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
4150 into a MEM later. Protect the libcall block from this change. */
4154 /* If we're using non-call exceptions, a libcall corresponding to an
4155 operation that may trap may also trap. */
4156 /* ??? See the comment in front of make_reg_eh_region_note. */
4159 {
4162 {
4165 {
4169 }
4170 }
4171 }
4172 else
4173 {
4174 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
4175 reg note to indicate that this call cannot throw or execute a nonlocal
4176 goto (unless there is already a REG_EH_REGION note, in which case
4177 we update it). */
4181 }
4183 /* First emit all insns that set pseudos. Remove them from the list as
4184 we go. Avoid insns that set pseudos which were referenced in previous
4185 insns. These can be generated by move_by_pieces, for example,
4186 to update an address. Similarly, avoid insns that reference things
4187 set in previous insns. */
4190 {
4197 {
4206 {
4209 else
4216 }
4217 }
4219 /* Some ports use a loop to copy large arguments onto the stack.
4220 Don't move anything outside such a loop. */
4223 }
4225 /* Write the remaining insns followed by the final copy. */
4227 {
4231 }
4239 }
4241 void
4243 {
4245 }
4246 \f
4247 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4248 PURPOSE describes how this comparison will be used. CODE is the rtx
4249 comparison code we will be using.
4251 ??? Actually, CODE is slightly weaker than that. A target is still
4252 required to implement all of the normal bcc operations, but not
4253 required to implement all (or any) of the unordered bcc operations. */
4255 int
4258 {
4259 rtx test;
4261 do
4262 {
4279 }
4283 }
4285 /* Return whether RTL code CODE corresponds to an unsigned optab. */
4287 static bool
4289 {
4291 }
4293 /* Return whether the backend-emitted comparison for code CODE, comparing
4294 operands of mode VALUE_MODE and producing a result with MASK_MODE, matches
4295 operand OPNO of pattern ICODE. */
4297 static bool
4300 machine_mode value_mode)
4301 {
4306 }
4308 /* Return whether the backend can emit a vector comparison (vec_cmp/vec_cmpu)
4309 for code CODE, comparing operands of mode VALUE_MODE and producing a result
4310 with MASK_MODE. */
4312 bool
4314 machine_mode mask_mode)
4315 {
4316 enum insn_code icode
4322 }
4324 /* Return whether the backend can emit a vector comparison (vcond/vcondu) for
4325 code CODE, comparing operands of mode CMP_OP_MODE and producing a result
4326 with VALUE_MODE. */
4328 bool
4330 machine_mode cmp_op_mode)
4331 {
4332 enum insn_code icode
4338 }
4340 /* Return whether the backend can emit vector set instructions for inserting
4341 element into vector at variable index position. */
4343 bool
4345 {
4364 }
4366 /* This function is called when we are going to emit a compare instruction that
4367 compares the values found in X and Y, using the rtl operator COMPARISON.
4369 If they have mode BLKmode, then SIZE specifies the size of both operands.
4371 UNSIGNEDP nonzero says that the operands are unsigned;
4372 this matters if they need to be widened (as given by METHODS).
4374 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
4375 if we failed to produce one.
4377 *PMODE is the mode of the inputs (in case they are const_int).
4379 This function performs all the setup necessary so that the caller only has
4380 to emit a single comparison insn. This setup can involve doing a BLKmode
4381 comparison or emitting a library call to perform the comparison if no insn
4382 is available to handle it.
4383 The values which are passed in through pointers can be modified; the caller
4384 should perform the comparison on the modified values. Constant
4385 comparisons must have already been folded. */
4387 static void
4391 {
4394 machine_mode cmp_mode;
4396 /* The other methods are not needed. */
4403 /* If we are optimizing, force expensive constants into a register. */
4416 /* Don't let both operands fail to indicate the mode. */
4422 /* Handle all BLKmode compares. */
4425 {
4426 machine_mode result_mode;
4428 rtx result;
4429 rtx opalign
4434 /* Try to use a memory block compare insn - either cmpstr
4435 or cmpmem will do. */
4436 opt_scalar_int_mode cmp_mode_iter;
4438 {
4448 /* Must make sure the size fits the insn's mode. */
4463 }
4468 /* Otherwise call a library function. */
4476 }
4478 /* Don't allow operands to the compare to trap, as that can put the
4479 compare and branch in different basic blocks. */
4481 {
4488 }
4491 {
4496 {
4499 }
4500 else
4502 }
4506 {
4511 {
4518 {
4524 }
4526 }
4530 }
4536 {
4537 /* Small trick if UNORDERED isn't implemented by the hardware. */
4539 {
4544 }
4547 }
4548 else
4549 {
4550 rtx result;
4551 machine_mode ret_mode;
4553 /* Handle a libcall just for the mode we are using. */
4557 /* If we want unsigned, and this mode has a distinct unsigned
4558 comparison routine, use that. */
4560 {
4564 }
4570 /* There are two kinds of comparison routines. Biased routines
4571 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4572 of gcc expect that the comparison operation is equivalent
4573 to the modified comparison. For signed comparisons compare the
4574 result against 1 in the biased case, and zero in the unbiased
4575 case. For unsigned comparisons always compare against 1 after
4576 biasing the unbiased result by adding 1. This gives us a way to
4577 represent LTU.
4578 The comparisons in the fixed-point helper library are always
4579 biased. */
4584 {
4587 else
4589 }
4594 }
4598 fail:
4600 }
4602 /* Before emitting an insn with code ICODE, make sure that X, which is going
4603 to be used for operand OPNUM of the insn, is converted from mode MODE to
4604 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4605 that it is accepted by the operand predicate. Return the new value. */
4607 rtx
4610 {
4615 {
4622 }
4625 }
4627 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4628 we can do the branch. */
4630 static void
4634 {
4635 machine_mode optab_mode;
4649 else
4655 && insn
4660 }
4662 /* PTEST points to a comparison that compares its first operand with zero.
4663 Check to see if it can be performed as a bit-test-and-branch instead.
4664 On success, return the instruction that performs the bit-test-and-branch
4665 and replace the second operand of *PTEST with the bit number to test.
4666 On failure, return CODE_FOR_nothing and leave *PTEST unchanged.
4668 Note that the comparison described by *PTEST should not be taken
4669 literally after a successful return. *PTEST is just a convenient
4670 place to store the two operands of the bit-and-test.
4672 VAL must contain the original tree expression for the first operand
4673 of *PTEST. */
4675 static enum insn_code
4677 {
4683 direct_optab optab;
4689 else
4694 /* If the target supports the testbit comparison directly, great. */
4700 {
4706 }
4722 }
4724 /* Generate code to compare X with Y so that the condition codes are
4725 set and to jump to LABEL if the condition is true. If X is a
4726 constant and Y is not a constant, then the comparison is swapped to
4727 ensure that the comparison RTL has the canonical form.
4729 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4730 need to be widened. UNSIGNEDP is also used to select the proper
4731 branch condition code.
4733 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4735 MODE is the mode of the inputs (in case they are const_int).
4737 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4738 It will be potentially converted into an unsigned variant based on
4739 UNSIGNEDP to select a proper jump instruction.
4741 PROB is the probability of jumping to LABEL. If the comparison is against
4742 zero then VAL contains the expression from which the non-zero RTL is
4743 derived. */
4745 void
4748 profile_probability prob)
4749 {
4751 rtx test;
4753 /* Swap operands and condition to ensure canonical RTL. */
4756 {
4759 }
4761 /* If OP0 is still a constant, then both X and Y must be constants
4762 or the opposite comparison is not supported. Force X into a register
4763 to create canonical RTL. */
4773 /* Check if we're comparing a truth type with 0, and if so check if
4774 the target supports tbranch. */
4776 direct_optab optab;
4780 {
4783 }
4786 }
4788 /* Overloaded version of emit_cmp_and_jump_insns in which VAL is unknown. */
4790 void
4793 profile_probability prob)
4794 {
4797 }
4800 /* Emit a library call comparison between floating point X and Y.
4801 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4803 static void
4806 {
4810 machine_mode mode;
4819 {
4826 {
4830 }
4834 {
4838 }
4839 }
4844 {
4847 }
4849 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4850 the RTL. The allows the RTL optimizers to delete the libcall if the
4851 condition can be determined at compile-time. */
4854 {
4857 }
4858 else
4859 {
4861 {
4894 }
4895 }
4898 {
4903 }
4904 else
4905 {
4910 }
4925 else
4929 }
4930 \f
4931 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4933 void
4935 {
4938 else
4939 {
4944 }
4945 }
4946 \f
4948 /* Emit a conditional move instruction if the machine supports one for that
4949 condition and machine mode.
4951 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4952 the mode to use should they be constants. If it is VOIDmode, they cannot
4953 both be constants.
4955 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4956 should be stored there. MODE is the mode to use should they be constants.
4957 If it is VOIDmode, they cannot both be constants.
4959 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4960 is not supported. */
4962 rtx
4966 {
4967 rtx comparison;
4972 /* If the two source operands are identical, that's just a move. */
4975 {
4981 }
4983 /* If one operand is constant, make it the second one. Only do this
4984 if the other operand is not constant as well. */
4987 {
4990 }
4992 /* get_condition will prefer to generate LT and GT even if the old
4993 comparison was against zero, so undo that canonicalization here since
4994 comparisons against zero are cheaper. */
5010 {
5014 }
5028 {
5030 comparison =
5034 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5035 punt and let the caller figure out how best to deal with this
5036 situation. */
5038 {
5039 saved_pending_stack_adjust save;
5048 {
5053 }
5056 }
5061 /* If the preferred op2/op3 order is not usable, retry with other
5062 operand order, perhaps it will expand successfully. */
5067 NULL))
5070 else
5073 }
5074 }
5076 /* Helper function that, in addition to COMPARISON, also tries
5077 the reversed REV_COMPARISON with swapped OP2 and OP3. As opposed
5078 to when we pass the specific constituents of a comparison, no
5079 additional insns are emitted for it. It might still be necessary
5080 to emit more than one insn for the final conditional move, though. */
5082 rtx
5085 {
5092 }
5094 /* Helper for emitting a conditional move. */
5096 static rtx
5099 {
5105 /* If the two source operands are identical, that's just a move.
5106 As the comparison comes in non-canonicalized, we must make
5107 sure not to discard any possible side effects. If there are
5108 side effects, just let the target handle it. */
5110 {
5116 }
5137 {
5141 }
5144 }
5147 /* Emit a conditional negate or bitwise complement using the
5148 negcc or notcc optabs if available. Return NULL_RTX if such operations
5149 are not available. Otherwise return the RTX holding the result.
5150 TARGET is the desired destination of the result. COMP is the comparison
5151 on which to negate. If COND is true move into TARGET the negation
5152 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
5153 CODE is either NEG or NOT. MODE is the machine mode in which the
5154 operation is performed. */
5156 rtx
5159 rtx op2)
5160 {
5166 else
5186 {
5191 }
5194 }
5196 /* Emit a conditional addition instruction if the machine supports one for that
5197 condition and machine mode.
5199 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
5200 the mode to use should they be constants. If it is VOIDmode, they cannot
5201 both be constants.
5203 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
5204 should be stored there. MODE is the mode to use should they be constants.
5205 If it is VOIDmode, they cannot both be constants.
5207 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
5208 is not supported. */
5210 rtx
5214 {
5215 rtx comparison;
5219 /* If one operand is constant, make it the second one. Only do this
5220 if the other operand is not constant as well. */
5223 {
5226 }
5228 /* get_condition will prefer to generate LT and GT even if the old
5229 comparison was against zero, so undo that canonicalization here since
5230 comparisons against zero are cheaper. */
5253 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5254 return NULL and let the caller figure out how best to deal with this
5255 situation. */
5265 {
5273 {
5277 }
5278 }
5281 }
5282 \f
5283 /* These functions attempt to generate an insn body, rather than
5284 emitting the insn, but if the gen function already emits them, we
5285 make no attempt to turn them back into naked patterns. */
5287 /* Generate and return an insn body to add Y to X. */
5289 rtx_insn *
5291 {
5299 }
5301 /* Generate and return an insn body to add r1 and c,
5302 storing the result in r0. */
5304 rtx_insn *
5306 {
5316 }
5318 int
5320 {
5336 }
5338 /* Generate and return an insn body to add Y to X. */
5340 rtx_insn *
5342 {
5350 }
5352 /* Return true if the target implements an addptr pattern and X, Y,
5353 and Z are valid for the pattern predicates. */
5355 int
5357 {
5373 }
5375 /* Generate and return an insn body to subtract Y from X. */
5377 rtx_insn *
5379 {
5387 }
5389 /* Generate and return an insn body to subtract r1 and c,
5390 storing the result in r0. */
5392 rtx_insn *
5394 {
5404 }
5406 int
5408 {
5424 }
5425 \f
5426 /* Generate the body of an insn to extend Y (with mode MFROM)
5427 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
5429 rtx_insn *
5432 {
5435 }
5436 \f
5437 /* Generate code to convert FROM to floating point
5438 and store in TO. FROM must be fixed point and not VOIDmode.
5439 UNSIGNEDP nonzero means regard FROM as unsigned.
5440 Normally this is done by correcting the final value
5441 if it is negative. */
5443 void
5445 {
5452 /* Crash now, because we won't be able to decide which mode to use. */
5455 /* Look for an insn to do the conversion. Do it in the specified
5456 modes if possible; otherwise convert either input, output or both to
5457 wider mode. If the integer mode is wider than the mode of FROM,
5458 we can do the conversion signed even if the input is unsigned. */
5462 {
5472 {
5478 }
5481 {
5494 }
5495 }
5497 /* Unsigned integer, and no way to convert directly. Convert as signed,
5498 then unconditionally adjust the result. */
5500 && can_do_signed
5503 {
5504 opt_scalar_mode fmode_iter;
5506 rtx temp;
5507 REAL_VALUE_TYPE offset;
5509 /* Look for a usable floating mode FMODE wider than the source and at
5510 least as wide as the target. Using FMODE will avoid rounding woes
5511 with unsigned values greater than the signed maximum value. */
5514 {
5519 }
5522 {
5523 /* There is no such mode. Pretend the target is wide enough. */
5526 /* Avoid double-rounding when TO is narrower than FROM. */
5529 {
5530 rtx temp1;
5533 /* Don't use TARGET if it isn't a register, is a hard register,
5534 or is the wrong mode. */
5543 /* Test whether the sign bit is set. */
5547 /* The sign bit is not set. Convert as signed. */
5552 /* The sign bit is set.
5553 Convert to a usable (positive signed) value by shifting right
5554 one bit, while remembering if a nonzero bit was shifted
5555 out; i.e., compute (from & 1) | (from >> 1). */
5562 OPTAB_LIB_WIDEN);
5565 /* Multiply by 2 to undo the shift above. */
5574 }
5575 }
5577 /* If we are about to do some arithmetic to correct for an
5578 unsigned operand, do it in a pseudo-register. */
5584 /* Convert as signed integer to floating. */
5587 /* If FROM is negative (and therefore TO is negative),
5588 correct its value by 2**bitwidth. */
5605 }
5607 /* No hardware instruction available; call a library routine. */
5608 {
5609 rtx libfunc;
5611 rtx value;
5630 }
5632 done:
5634 /* Copy result to requested destination
5635 if we have been computing in a temp location. */
5638 {
5641 else
5643 }
5644 }
5645 \f
5646 /* Generate code to convert FROM to fixed point and store in TO. FROM
5647 must be floating point. */
5649 void
5651 {
5655 opt_scalar_mode fmode_iter;
5658 /* We first try to find a pair of modes, one real and one integer, at
5659 least as wide as FROM and TO, respectively, in which we can open-code
5660 this conversion. If the integer mode is wider than the mode of TO,
5661 we can do the conversion either signed or unsigned. */
5665 {
5673 {
5680 {
5684 }
5691 {
5695 }
5697 }
5698 }
5700 /* For an unsigned conversion, there is one more way to do it.
5701 If we have a signed conversion, we generate code that compares
5702 the real value to the largest representable positive number. If if
5703 is smaller, the conversion is done normally. Otherwise, subtract
5704 one plus the highest signed number, convert, and add it back.
5706 We only need to check all real modes, since we know we didn't find
5707 anything with a wider integer mode.
5709 This code used to extend FP value into mode wider than the destination.
5710 This is needed for decimal float modes which cannot accurately
5711 represent one plus the highest signed number of the same size, but
5712 not for binary modes. Consider, for instance conversion from SFmode
5713 into DImode.
5715 The hot path through the code is dealing with inputs smaller than 2^63
5716 and doing just the conversion, so there is no bits to lose.
5718 In the other path we know the value is positive in the range 2^63..2^64-1
5719 inclusive. (as for other input overflow happens and result is undefined)
5720 So we know that the most important bit set in mantissa corresponds to
5721 2^63. The subtraction of 2^63 should not generate any rounding as it
5722 simply clears out that bit. The rest is trivial. */
5724 scalar_int_mode to_mode;
5729 {
5735 {
5737 REAL_VALUE_TYPE offset;
5738 rtx limit;
5751 /* See if we need to do the subtraction. */
5756 /* If not, do the signed "fix" and branch around fixup code. */
5761 /* Otherwise, subtract 2**(N-1), convert to signed number,
5762 then add 2**(N-1). Do the addition using XOR since this
5763 will often generate better code. */
5769 gen_int_mode
5771 to_mode),
5780 {
5781 /* Make a place for a REG_NOTE and add it. */
5786 to);
5787 }
5790 }
5791 }
5793 /* We can't do it with an insn, so use a library call. But first ensure
5794 that the mode of TO is at least as wide as SImode, since those are the
5795 only library calls we know about. */
5798 {
5802 }
5803 else
5804 {
5806 rtx value;
5807 rtx libfunc;
5823 }
5826 {
5829 else
5831 }
5832 }
5835 /* Promote integer arguments for a libcall if necessary.
5836 emit_library_call_value cannot do the promotion because it does not
5837 know if it should do a signed or unsigned promotion. This is because
5838 there are no tree types defined for libcalls. */
5840 static rtx
5842 {
5843 scalar_int_mode mode;
5844 machine_mode arg_mode;
5846 {
5847 /* If we need to promote the integer function argument we need to do
5848 it here instead of inside emit_library_call_value because in
5849 emit_library_call_value we don't know if we should do a signed or
5850 unsigned promotion. */
5857 }
5859 }
5861 /* Generate code to convert FROM or TO a fixed-point.
5862 If UINTP is true, either TO or FROM is an unsigned integer.
5863 If SATP is true, we need to saturate the result. */
5865 void
5867 {
5870 convert_optab tab;
5874 rtx value;
5875 rtx libfunc;
5878 {
5881 }
5884 {
5887 }
5888 else
5889 {
5892 }
5895 {
5898 }
5914 }
5916 /* Generate code to convert FROM to fixed point and store in TO. FROM
5917 must be floating point, TO must be signed. Use the conversion optab
5918 TAB to do the conversion. */
5920 bool
5922 {
5927 /* We first try to find a pair of modes, one real and one integer, at
5928 least as wide as FROM and TO, respectively, in which we can open-code
5929 this conversion. If the integer mode is wider than the mode of TO,
5930 we can do the conversion either signed or unsigned. */
5934 {
5938 {
5947 {
5950 }
5954 }
5955 }
5958 }
5959 \f
5960 /* Report whether we have an instruction to perform the operation
5961 specified by CODE on operands of mode MODE. */
5962 int
5964 {
5968 }
5970 /* Print information about the current contents of the optabs on
5971 STDERR. */
5973 DEBUG_FUNCTION void
5975 {
5978 /* Dump the arithmetic optabs. */
5981 {
5984 {
5990 }
5991 }
5993 /* Dump the conversion optabs. */
5997 {
6001 {
6008 }
6009 }
6010 }
6012 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6013 CODE. Return 0 on failure. */
6015 rtx_insn *
6017 {
6021 rtx trap_rtx;
6030 /* Some targets only accept a zero trap code. */
6040 else
6042 tcode);
6044 /* If that failed, then give up. */
6046 {
6049 }
6055 }
6057 /* Return rtx code for TCODE or UNKNOWN. Use UNSIGNEDP to select signed
6058 or unsigned operation code. */
6060 enum rtx_code
6062 {
6065 {
6121 }
6123 }
6125 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6126 or unsigned operation code. */
6128 enum rtx_code
6130 {
6134 }
6136 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
6137 select signed or unsigned operators. OPNO holds the index of the
6138 first comparison operand for insn ICODE. Do not generate the
6139 compare instruction itself. */
6141 rtx
6145 {
6153 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
6154 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
6155 cases, use the original mode. */
6157 EXPAND_STACK_PARM);
6163 EXPAND_STACK_PARM);
6173 }
6175 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
6176 the first vec_perm operand, assuming the second operand (for left shift
6177 first operand) is a constant vector of zeros. Return the shift distance
6178 in bits if so, or NULL_RTX if the vec_perm is not a shift. MODE is the
6179 mode of the value being shifted. SHIFT_OPTAB is vec_shr_optab for right
6180 shift or vec_shl_optab for left shift. */
6181 static rtx
6183 optab shift_optab)
6184 {
6191 {
6197 {
6199 {
6203 }
6208 }
6213 }
6215 {
6220 {
6222 /* Indices into the second vector are all equivalent. */
6227 }
6228 }
6231 }
6233 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
6235 static rtx
6238 {
6248 /* Make an effort to preserve v0 == v1. The target expander is able to
6249 rely on this to determine if we're permuting a single input operand. */
6251 {
6259 }
6260 else
6261 {
6264 }
6269 }
6271 /* Implement a permutation of vectors v0 and v1 using the permutation
6272 vector in SEL and return the result. Use TARGET to hold the result
6273 if nonnull and convenient.
6275 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
6276 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
6277 to have a particular mode. */
6279 rtx
6282 rtx target)
6283 {
6287 /* Set QIMODE to a different vector mode with byte elements.
6288 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6289 machine_mode qimode;
6296 /* Always specify two input vectors here and leave the target to handle
6297 cases in which the inputs are equal. Not all backends can cope with
6298 the single-input representation when testing for a double-input
6299 target instruction. */
6302 /* See if this can be handled with a vec_shr or vec_shl. We only do this
6303 if the second (for vec_shr) or first (for vec_shl) vector is all
6304 zeroes. */
6312 {
6315 }
6317 {
6322 }
6324 {
6327 {
6332 {
6338 }
6340 {
6347 }
6348 }
6349 }
6352 {
6359 indices))
6361 }
6363 /* Fall back to a constant byte-based permutation. */
6364 vec_perm_indices qimode_indices;
6367 {
6376 }
6383 /* Otherwise expand as a fully variable permuation. */
6385 /* The optabs are only defined for selectors with the same width
6386 as the values being permuted. */
6387 machine_mode required_sel_mode;
6389 {
6392 }
6394 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
6395 If that isn't the mode we want then we need to prove that using
6396 REQUIRED_SEL_MODE is OK. */
6398 {
6400 {
6403 }
6405 }
6409 {
6414 }
6418 {
6421 {
6426 }
6427 }
6431 }
6433 /* Implement a permutation of vectors v0 and v1 using the permutation
6434 vector in SEL and return the result. Use TARGET to hold the result
6435 if nonnull and convenient.
6437 MODE is the mode of the vectors being permuted (V0 and V1).
6438 SEL must have the integer equivalent of MODE and is known to be
6439 unsuitable for permutes with a constant permutation vector. */
6441 rtx
6443 {
6455 {
6459 }
6461 /* As a special case to aid several targets, lower the element-based
6462 permutation to a byte-based permutation and try again. */
6463 machine_mode qimode;
6471 /* Multiply each element by its byte size. */
6476 else
6482 /* Broadcast the low byte each element into each of its bytes.
6483 The encoding has U interleaved stepped patterns, one for each
6484 byte of an element. */
6494 /* Add the byte offset to each byte element. */
6495 /* Note that the definition of the indicies here is memory ordering,
6496 so there should be no difference between big and little endian. */
6511 }
6513 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
6514 Use TARGET for the result if nonnull and convenient. */
6516 rtx
6518 {
6532 }
6534 /* Generate insns for a vector comparison into a mask. */
6536 rtx
6538 {
6541 rtx comparison;
6543 machine_mode vmode;
6557 {
6562 }
6572 }
6574 /* Expand a highpart multiply. */
6576 rtx
6579 {
6583 machine_mode wmode;
6589 {
6595 OPTAB_LIB_WIDEN);
6608 }
6628 vec_perm_builder sel;
6630 {
6631 /* The encoding has 2 interleaved stepped patterns. */
6636 }
6637 else
6638 {
6639 /* The encoding has a single interleaved stepped pattern. */
6643 }
6646 }
6647 \f
6648 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6649 pattern. */
6651 static void
6653 {
6656 {
6660 }
6661 }
6663 /* This is a helper function for the other atomic operations. This function
6664 emits a loop that contains SEQ that iterates until a compare-and-swap
6665 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6666 a set of instructions that takes a value from OLD_REG as an input and
6667 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6668 set to the current contents of MEM. After SEQ, a compare-and-swap will
6669 attempt to update MEM with NEW_REG. The function returns true when the
6670 loop was generated successfully. */
6672 static bool
6674 {
6679 /* The loop we want to generate looks like
6681 cmp_reg = mem;
6682 label:
6683 old_reg = cmp_reg;
6684 seq;
6685 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6686 if (success)
6687 goto label;
6689 Note that we only do the plain load from memory once. Subsequent
6690 iterations use the value loaded by the compare-and-swap pattern. */
6705 MEMMODEL_RELAXED))
6711 /* Mark this jump predicted not taken. */
6716 }
6719 /* This function tries to emit an atomic_exchange intruction. VAL is written
6720 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6721 using TARGET if possible. */
6723 static rtx
6725 {
6729 /* If the target supports the exchange directly, great. */
6732 {
6741 }
6744 }
6746 /* This function tries to implement an atomic exchange operation using
6747 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6748 The previous contents of *MEM are returned, using TARGET if possible.
6749 Since this instructionn is an acquire barrier only, stronger memory
6750 models may require additional barriers to be emitted. */
6752 static rtx
6755 {
6762 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6763 exists, and the memory model is stronger than acquire, add a release
6764 barrier before the instruction. */
6770 {
6777 }
6779 /* If an external test-and-set libcall is provided, use that instead of
6780 any external compare-and-swap that we might get from the compare-and-
6781 swap-loop expansion later. */
6783 {
6786 {
6787 rtx addr;
6793 }
6794 }
6796 /* If the test_and_set can't be emitted, eliminate any barrier that might
6797 have been emitted. */
6800 }
6802 /* This function tries to implement an atomic exchange operation using a
6803 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6804 *MEM are returned, using TARGET if possible. No memory model is required
6805 since a compare_and_swap loop is seq-cst. */
6807 static rtx
6809 {
6813 {
6818 }
6821 }
6823 /* This function tries to implement an atomic test-and-set operation
6824 using the atomic_test_and_set instruction pattern. A boolean value
6825 is returned from the operation, using TARGET if possible. */
6827 static rtx
6829 {
6830 machine_mode pat_bool_mode;
6836 /* While we always get QImode from __atomic_test_and_set, we get
6837 other memory modes from __sync_lock_test_and_set. Note that we
6838 use no endian adjustment here. This matches the 4.6 behavior
6839 in the Sparc backend. */
6853 }
6855 /* This function expands the legacy _sync_lock test_and_set operation which is
6856 generally an atomic exchange. Some limited targets only allow the
6857 constant 1 to be stored. This is an ACQUIRE operation.
6859 TARGET is an optional place to stick the return value.
6860 MEM is where VAL is stored. */
6862 rtx
6864 {
6865 rtx ret;
6867 /* Try an atomic_exchange first. */
6873 MEMMODEL_SYNC_ACQUIRE);
6881 /* If there are no other options, try atomic_test_and_set if the value
6882 being stored is 1. */
6887 }
6889 /* This function expands the atomic test_and_set operation:
6890 atomically store a boolean TRUE into MEM and return the previous value.
6892 MEMMODEL is the memory model variant to use.
6893 TARGET is an optional place to stick the return value. */
6895 rtx
6897 {
6905 /* Be binary compatible with non-default settings of trueval, and different
6906 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6907 another only has atomic-exchange. */
6909 {
6912 }
6913 else
6914 {
6917 }
6919 /* Try the atomic-exchange optab... */
6922 /* ... then an atomic-compare-and-swap loop ... */
6926 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6930 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6931 things with the value 1. Thus we try again without trueval. */
6935 /* Failing all else, assume a single threaded environment and simply
6936 perform the operation. */
6938 {
6939 /* If the result is ignored skip the move to target. */
6945 }
6947 /* Recall that have to return a boolean value; rectify if trueval
6948 is not exactly one. */
6953 }
6955 /* This function expands the atomic exchange operation:
6956 atomically store VAL in MEM and return the previous value in MEM.
6958 MEMMODEL is the memory model variant to use.
6959 TARGET is an optional place to stick the return value. */
6961 rtx
6963 {
6965 rtx ret;
6967 /* If loads are not atomic for the required size and we are not called to
6968 provide a __sync builtin, do not do anything so that we stay consistent
6969 with atomic loads of the same size. */
6975 /* Next try a compare-and-swap loop for the exchange. */
6980 }
6982 /* This function expands the atomic compare exchange operation:
6984 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6985 *PTARGET_OVAL is an optional place to store the old value from memory.
6986 Both target parameters may be NULL or const0_rtx to indicate that we do
6987 not care about that return value. Both target parameters are updated on
6988 success to the actual location of the corresponding result.
6990 MEMMODEL is the memory model variant to use.
6992 The return value of the function is true for success. */
6994 bool
6999 {
7004 rtx libfunc;
7006 /* If loads are not atomic for the required size and we are not called to
7007 provide a __sync builtin, do not do anything so that we stay consistent
7008 with atomic loads of the same size. */
7012 /* Load expected into a register for the compare and swap. */
7016 /* Make sure we always have some place to put the return oldval.
7017 Further, make sure that place is distinct from the input expected,
7018 just in case we need that path down below. */
7029 {
7035 /* Make sure we always have a place for the bool operand. */
7041 /* Emit the compare_and_swap. */
7051 {
7052 /* Return success/failure. */
7056 }
7057 }
7059 /* Otherwise fall back to the original __sync_val_compare_and_swap
7060 which is always seq-cst. */
7063 {
7064 rtx cc_reg;
7075 /* If the caller isn't interested in the boolean return value,
7076 skip the computation of it. */
7080 /* Otherwise, work out if the compare-and-swap succeeded. */
7085 {
7089 }
7091 }
7093 /* Also check for library support for __sync_val_compare_and_swap. */
7096 {
7103 /* Compute the boolean return value only if requested. */
7106 else
7108 }
7110 /* Failure. */
7113 success_bool_from_val:
7116 success:
7117 /* Make sure that the oval output winds up where the caller asked. */
7123 }
7125 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
7127 static void
7129 {
7142 }
7144 /* Do not propagate memory accesses across this point. */
7146 static void
7148 {
7151 else
7153 }
7155 /* Generate asm volatile("" : : : "memory") as a memory blockage, at the
7156 same time clobbering the register set specified by REGS. */
7158 void
7160 {
7166 num_of_regs++;
7183 {
7187 {
7189 j++;
7190 }
7192 }
7195 }
7197 /* This routine will either emit the mem_thread_fence pattern or issue a
7198 sync_synchronize to generate a fence for memory model MEMMODEL. */
7200 void
7202 {
7206 {
7209 }
7214 else
7216 }
7218 /* Emit a signal fence with given memory model. */
7220 void
7222 {
7223 /* No machine barrier is required to implement a signal fence, but
7224 a compiler memory barrier must be issued, except for relaxed MM. */
7227 }
7229 /* This function expands the atomic load operation:
7230 return the atomically loaded value in MEM.
7232 MEMMODEL is the memory model variant to use.
7233 TARGET is an option place to stick the return value. */
7235 rtx
7237 {
7241 /* If the target supports the load directly, great. */
7244 {
7254 {
7258 }
7260 }
7262 /* If the size of the object is greater than word size on this target,
7263 then we assume that a load will not be atomic. We could try to
7264 emulate a load with a compare-and-swap operation, but the store that
7265 doing this could result in would be incorrect if this is a volatile
7266 atomic load or targetting read-only-mapped memory. */
7268 /* If there is no atomic load, leave the library call. */
7271 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7275 /* For SEQ_CST, emit a barrier before the load. */
7281 /* Emit the appropriate barrier after the load. */
7285 }
7287 /* This function expands the atomic store operation:
7288 Atomically store VAL in MEM.
7289 MEMMODEL is the memory model variant to use.
7290 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7291 function returns const0_rtx if a pattern was emitted. */
7293 rtx
7295 {
7300 /* If the target supports the store directly, great. */
7303 {
7311 {
7315 }
7317 }
7319 /* If using __sync_lock_release is a viable alternative, try it.
7320 Note that this will not be set to true if we are expanding a generic
7321 __atomic_store_n. */
7323 {
7326 {
7330 {
7331 /* lock_release is only a release barrier. */
7335 }
7336 }
7337 }
7339 /* If the size of the object is greater than word size on this target,
7340 a default store will not be atomic. */
7342 {
7343 /* If loads are atomic or we are called to provide a __sync builtin,
7344 we can try a atomic_exchange and throw away the result. Otherwise,
7345 don't do anything so that we do not create an inconsistency between
7346 loads and stores. */
7348 {
7352 val);
7355 }
7357 }
7359 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7364 /* For SEQ_CST, also emit a barrier after the store. */
7369 }
7372 /* Structure containing the pointers and values required to process the
7373 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7375 struct atomic_op_functions
7376 {
7377 direct_optab mem_fetch_before;
7378 direct_optab mem_fetch_after;
7379 direct_optab mem_no_result;
7380 optab fetch_before;
7381 optab fetch_after;
7382 direct_optab no_result;
7384 };
7387 /* Fill in structure pointed to by OP with the various optab entries for an
7388 operation of type CODE. */
7390 static void
7392 {
7395 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7396 in the source code during compilation, and the optab entries are not
7397 computable until runtime. Fill in the values at runtime. */
7399 {
7456 }
7457 }
7459 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7460 using memory order MODEL. If AFTER is true the operation needs to return
7461 the value of *MEM after the operation, otherwise the previous value.
7462 TARGET is an optional place to place the result. The result is unused if
7463 it is const0_rtx.
7464 Return the result if there is a better sequence, otherwise NULL_RTX. */
7466 static rtx
7469 {
7470 /* If the value is prefetched, or not used, it may be possible to replace
7471 the sequence with a native exchange operation. */
7473 {
7474 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7476 {
7480 }
7482 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7484 {
7488 }
7489 }
7492 }
7494 /* Try to emit an instruction for a specific operation varaition.
7495 OPTAB contains the OP functions.
7496 TARGET is an optional place to return the result. const0_rtx means unused.
7497 MEM is the memory location to operate on.
7498 VAL is the value to use in the operation.
7499 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7500 MODEL is the memory model, if used.
7501 AFTER is true if the returned result is the value after the operation. */
7503 static rtx
7506 {
7513 /* Check to see if there is a result returned. */
7515 {
7517 {
7521 }
7522 else
7523 {
7526 }
7527 }
7528 /* Otherwise, we need to generate a result. */
7529 else
7530 {
7532 {
7537 }
7538 else
7539 {
7543 }
7545 }
7550 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7557 }
7560 /* This function expands an atomic fetch_OP or OP_fetch operation:
7561 TARGET is an option place to stick the return value. const0_rtx indicates
7562 the result is unused.
7563 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7564 CODE is the operation being performed (OP)
7565 MEMMODEL is the memory model variant to use.
7566 AFTER is true to return the result of the operation (OP_fetch).
7567 AFTER is false to return the value before the operation (fetch_OP).
7569 This function will *only* generate instructions if there is a direct
7570 optab. No compare and swap loops or libcalls will be generated. */
7572 static rtx
7576 {
7579 rtx result;
7584 /* Check to see if there are any better instructions. */
7589 /* Check for the case where the result isn't used and try those patterns. */
7591 {
7592 /* Try the memory model variant first. */
7597 /* Next try the old style withuot a memory model. */
7602 /* There is no no-result pattern, so try patterns with a result. */
7604 }
7606 /* Try the __atomic version. */
7611 /* Try the older __sync version. */
7616 /* If the fetch value can be calculated from the other variation of fetch,
7617 try that operation. */
7619 {
7620 /* Try the __atomic version, then the older __sync version. */
7626 {
7627 /* If the result isn't used, no need to do compensation code. */
7631 /* Issue compensation code. Fetch_after == fetch_before OP val.
7632 Fetch_before == after REVERSE_OP val. */
7636 {
7640 }
7641 else
7645 }
7646 }
7648 /* No direct opcode can be generated. */
7650 }
7654 /* This function expands an atomic fetch_OP or OP_fetch operation:
7655 TARGET is an option place to stick the return value. const0_rtx indicates
7656 the result is unused.
7657 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7658 CODE is the operation being performed (OP)
7659 MEMMODEL is the memory model variant to use.
7660 AFTER is true to return the result of the operation (OP_fetch).
7661 AFTER is false to return the value before the operation (fetch_OP). */
7662 rtx
7665 {
7667 rtx result;
7670 /* If loads are not atomic for the required size and we are not called to
7671 provide a __sync builtin, do not do anything so that we stay consistent
7672 with atomic loads of the same size. */
7677 after);
7682 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7684 {
7685 rtx tmp;
7693 {
7694 /* PLUS worked so emit the insns and return. */
7699 }
7701 /* PLUS did not work, so throw away the negation code and continue. */
7703 }
7705 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7707 {
7708 rtx libfunc;
7718 {
7724 }
7726 {
7735 }
7737 /* We need the original code for any further attempts. */
7739 }
7741 /* If nothing else has succeeded, default to a compare and swap loop. */
7743 {
7749 /* If the result is used, get a register for it. */
7751 {
7754 /* If fetch_before, copy the value now. */
7757 }
7758 else
7763 {
7767 }
7768 else
7770 OPTAB_LIB_WIDEN);
7772 /* For after, copy the value now. */
7780 }
7783 }
7784 \f
7785 /* Return true if OPERAND is suitable for operand number OPNO of
7786 instruction ICODE. */
7788 bool
7790 {
7794 }
7795 \f
7796 /* TARGET is a target of a multiword operation that we are going to
7797 implement as a series of word-mode operations. Return true if
7798 TARGET is suitable for this purpose. */
7800 bool
7802 {
7803 machine_mode mode;
7813 }
7815 /* Make OP describe an input operand that has value INTVAL and that has
7816 no inherent mode. This function should only be used for operands that
7817 are always expand-time constants. The backend may request that INTVAL
7818 be copied into a different kind of rtx, but it must specify the mode
7819 of that rtx if so. */
7821 void
7823 {
7827 }
7829 /* Like maybe_legitimize_operand, but do not change the code of the
7830 current rtx value. */
7832 static bool
7835 {
7836 /* See if the operand matches in its current form. */
7840 /* If the operand is a memory whose address has no side effects,
7841 try forcing the address into a non-virtual pseudo register.
7842 The check for side effects is important because copy_to_mode_reg
7843 cannot handle things like auto-modified addresses. */
7845 {
7852 {
7854 machine_mode mode;
7860 {
7863 }
7865 }
7866 }
7869 }
7871 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7872 on success, storing the new operand value back in OP. */
7874 static bool
7877 {
7882 {
7884 {
7887 }
7902 input:
7920 else
7921 /* The caller must tell us what mode this value has. */
7928 {
7931 }
7933 {
7937 }
7950 {
7953 }
7955 }
7957 }
7959 /* Make OP describe an input operand that should have the same value
7960 as VALUE, after any mode conversion that the target might request.
7961 TYPE is the type of VALUE. */
7963 void
7966 {
7969 }
7971 /* Return true if the requirements on operands OP1 and OP2 of instruction
7972 ICODE are similar enough for the result of legitimizing OP1 to be
7973 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7974 with OP1 and OP2 respectively. */
7981 {
7982 /* Check requirements that are common to all types. */
7989 /* Check the requirements for specific types. */
7991 {
7993 /* Outputs must remain distinct. */
8005 }
8007 }
8009 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8010 of instruction ICODE. Return true on success, leaving the new operand
8011 values in the OPS themselves. Emit no code on failure. */
8013 bool
8016 {
8020 {
8023 /* First try reusing the result of an earlier legitimization.
8024 This avoids duplicate rtl and ensures that tied operands
8025 remain tied.
8027 This search is linear, but NOPS is bounded at compile time
8028 to a small number (current a single digit). */
8035 {
8038 }
8040 /* Otherwise try legitimizing the operand on its own. */
8042 {
8045 }
8046 }
8048 }
8050 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8051 as its operands. Return the instruction pattern on success,
8052 and emit any necessary set-up code. Return null and emit no
8053 code on failure. */
8055 rtx_insn *
8058 {
8064 {
8094 }
8096 }
8098 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8099 as its operands. Return true on success and emit no code on failure. */
8101 bool
8104 {
8107 {
8110 }
8112 }
8114 /* Like maybe_expand_insn, but for jumps. */
8116 bool
8119 {
8122 {
8125 }
8127 }
8129 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8130 as its operands. */
8132 void
8135 {
8138 }
8140 /* Like expand_insn, but for jumps. */
8142 void
8145 {
8148 }