gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VSPLTISW     141)
  24    (UNSPEC_VSPLTISH     140)
  25    (UNSPEC_VSPLTISB     139)
  26    ])
  27
  28 ;; Generic LVX load instruction.
  29 (define_insn "altivec_lvx_4si"
  30   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  31         (match_operand:V4SI 1 "memory_operand" "m"))]
  32   "TARGET_ALTIVEC"
  33   "lvx %0,%y1"
  34   [(set_attr "type" "vecload")])
  35
  36 (define_insn "altivec_lvx_8hi"
  37   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  38         (match_operand:V8HI 1 "memory_operand" "m"))]
  39   "TARGET_ALTIVEC"
  40   "lvx %0,%y1"
  41   [(set_attr "type" "vecload")])
  42
  43 (define_insn "altivec_lvx_16qi"
  44   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  45         (match_operand:V16QI 1 "memory_operand" "m"))]
  46   "TARGET_ALTIVEC"
  47   "lvx %0,%y1"
  48   [(set_attr "type" "vecload")])
  49
  50 (define_insn "altivec_lvx_4sf"
  51   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  52         (match_operand:V4SF 1 "memory_operand" "m"))]
  53   "TARGET_ALTIVEC"
  54   "lvx %0,%y1"
  55   [(set_attr "type" "vecload")])
  56
  57 ;; Generic STVX store instruction.
  58 (define_insn "altivec_stvx_4si"
  59   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  60         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  61   "TARGET_ALTIVEC"
  62   "stvx %1,%y0"
  63   [(set_attr "type" "vecstore")])
  64
  65 (define_insn "altivec_stvx_8hi"
  66   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  67         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  68   "TARGET_ALTIVEC"
  69   "stvx %1,%y0"
  70   [(set_attr "type" "vecstore")])
  71
  72 (define_insn "altivec_stvx_16qi"
  73   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  74         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 (define_insn "altivec_stvx_4sf"
  80   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  81         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  82   "TARGET_ALTIVEC"
  83   "stvx %1,%y0"
  84   [(set_attr "type" "vecstore")])
  85
  86 ;; Vector move instructions.
  87 (define_expand "movv4si"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  89         (match_operand:V4SI 1 "any_operand" ""))]
  90   "TARGET_ALTIVEC"
  91   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  92
  93 (define_insn "*movv4si_internal"
  94   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  95         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
  96   "TARGET_ALTIVEC"
  97   "*
  98 {
  99   switch (which_alternative)
 100     {
 101     case 0: return \"stvx %1,%y0\";
 102     case 1: return \"lvx %0,%y1\";
 103     case 2: return \"vor %0,%1,%1\";
 104     case 3: return \"stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0\";
 105     case 4: return \"lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1\";
 106     case 5: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
 107     case 6: return output_vec_const_move (operands);
 108     default: abort();
 109     }
 110 }"
 111   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")
 112    (set_attr "length" "*,*,*,16,16,16,*")])
 113
 114 (define_split
 115   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 116         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 117   "TARGET_ALTIVEC && reload_completed"
 118   [(set (match_dup 0)
 119         (unspec:V4SI [(match_dup 3)] UNSPEC_VSPLTISW))
 120    (set (match_dup 0)
 121         (plus:V4SI (match_dup 0)
 122                    (match_dup 0)))]
 123   "
 124 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 125
 126 (define_expand "movv8hi"
 127   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 128         (match_operand:V8HI 1 "any_operand" ""))]
 129   "TARGET_ALTIVEC"
 130   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 131
 132 (define_insn "*movv8hi_internal1"
 133   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 134         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
 135   "TARGET_ALTIVEC"
 136   "*
 137 {
 138    switch (which_alternative)
 139      {
 140      case 0: return \"stvx %1,%y0\";
 141      case 1: return \"lvx %0,%y1\";
 142      case 2: return \"vor %0,%1,%1\";
 143      case 3: return \"stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0\";
 144      case 4: return \"lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1\";
 145      case 5: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
 146      case 6: return output_vec_const_move (operands);
 147      default: abort ();
 148      }
 149 }"
 150   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")
 151    (set_attr "length" "*,*,*,16,16,16,*")])
 152
 153 (define_split
 154   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 155         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 156   "TARGET_ALTIVEC && reload_completed"
 157   [(set (match_dup 0)
 158         (unspec:V8HI [(match_dup 3)] UNSPEC_VSPLTISH))
 159    (set (match_dup 0)
 160         (plus:V8HI (match_dup 0)
 161                    (match_dup 0)))]
 162   "
 163 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 164
 165 (define_expand "movv16qi"
 166   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 167         (match_operand:V16QI 1 "any_operand" ""))]
 168   "TARGET_ALTIVEC"
 169   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 170
 171 (define_insn "*movv16qi_internal1"
 172   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 173         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
 174   "TARGET_ALTIVEC"
 175   "*
 176 {
 177   switch (which_alternative)
 178     {
 179     case 0: return \"stvx %1,%y0\";
 180     case 1: return \"lvx %0,%y1\";
 181     case 2: return \"vor %0,%1,%1\";
 182     case 3: return \"stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0\";
 183     case 4: return \"lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1\";
 184     case 5: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
 185     case 6: return output_vec_const_move (operands);
 186     default: abort ();
 187     }
 188 }"
 189   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")
 190    (set_attr "length" "*,*,*,16,16,16,*")])
 191
 192 (define_split
 193   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 194         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 195   "TARGET_ALTIVEC && reload_completed"
 196   [(set (match_dup 0)
 197         (unspec:V16QI [(match_dup 3)] UNSPEC_VSPLTISB))
 198    (set (match_dup 0)
 199         (plus:V16QI (match_dup 0)
 200                    (match_dup 0)))]
 201   "
 202 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 203
 204 (define_expand "movv4sf"
 205   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 206         (match_operand:V4SF 1 "any_operand" ""))]
 207   "TARGET_ALTIVEC"
 208   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 209
 210 (define_insn "*movv4sf_internal1"
 211   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 212         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
 213   "TARGET_ALTIVEC"
 214   "*
 215 {
 216   switch (which_alternative)
 217     {
 218     case 0: return \"stvx %1,%y0\";
 219     case 1: return \"lvx %0,%y1\";
 220     case 2: return \"vor %0,%1,%1\";
 221     case 3: return \"stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0\";
 222     case 4: return \"lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1\";
 223     case 5: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
 224     case 6: return output_vec_const_move (operands);
 225     default: abort ();
 226     }
 227 }"
 228   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")
 229    (set_attr "length" "*,*,*,16,16,16,*")])
 230
 231 (define_insn "get_vrsave_internal"
 232   [(set (match_operand:SI 0 "register_operand" "=r")
 233         (unspec:SI [(reg:SI 109)] 214))]
 234   "TARGET_ALTIVEC"
 235   "*
 236 {
 237   if (TARGET_MACHO)
 238      return \"mfspr %0,256\";
 239   else
 240      return \"mfvrsave %0\";
 241 }"
 242   [(set_attr "type" "*")])
 243
 244 (define_insn "*set_vrsave_internal"
 245   [(match_parallel 0 "vrsave_operation"
 246      [(set (reg:SI 109)
 247            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 248                                 (reg:SI 109)] 30))])]
 249   "TARGET_ALTIVEC"
 250   "*
 251 {
 252   if (TARGET_MACHO)
 253     return \"mtspr 256,%1\";
 254   else
 255     return \"mtvrsave %1\";
 256 }"
 257   [(set_attr "type" "*")])
 258
 259 ;; Simple binary operations.
 260
 261 (define_insn "addv16qi3"
 262   [(set (match_operand:V16QI 0 "register_operand" "=v")
 263         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 264                     (match_operand:V16QI 2 "register_operand" "v")))]
 265   "TARGET_ALTIVEC"
 266   "vaddubm %0,%1,%2"
 267   [(set_attr "type" "vecsimple")])
 268
 269 (define_insn "addv8hi3"
 270   [(set (match_operand:V8HI 0 "register_operand" "=v")
 271         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 272                    (match_operand:V8HI 2 "register_operand" "v")))]
 273   "TARGET_ALTIVEC"
 274   "vadduhm %0,%1,%2"
 275   [(set_attr "type" "vecsimple")])
 276
 277 (define_insn "addv4si3"
 278   [(set (match_operand:V4SI 0 "register_operand" "=v")
 279         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 280                    (match_operand:V4SI 2 "register_operand" "v")))]
 281   "TARGET_ALTIVEC"
 282   "vadduwm %0,%1,%2"
 283   [(set_attr "type" "vecsimple")])
 284
 285 (define_insn "addv4sf3"
 286   [(set (match_operand:V4SF 0 "register_operand" "=v")
 287         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 288                    (match_operand:V4SF 2 "register_operand" "v")))]
 289   "TARGET_ALTIVEC"
 290   "vaddfp %0,%1,%2"
 291   [(set_attr "type" "vecfloat")])
 292
 293 (define_insn "altivec_vaddcuw"
 294   [(set (match_operand:V4SI 0 "register_operand" "=v")
 295         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 296                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 297   "TARGET_ALTIVEC"
 298   "vaddcuw %0,%1,%2"
 299   [(set_attr "type" "vecsimple")])
 300
 301 (define_insn "altivec_vaddubs"
 302   [(set (match_operand:V16QI 0 "register_operand" "=v")
 303         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 304                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 305    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 306   "TARGET_ALTIVEC"
 307   "vaddubs %0,%1,%2"
 308   [(set_attr "type" "vecsimple")])
 309
 310 (define_insn "altivec_vaddsbs"
 311   [(set (match_operand:V16QI 0 "register_operand" "=v")
 312         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 313                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 314    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 315   "TARGET_ALTIVEC"
 316   "vaddsbs %0,%1,%2"
 317   [(set_attr "type" "vecsimple")])
 318
 319 (define_insn "altivec_vadduhs"
 320   [(set (match_operand:V8HI 0 "register_operand" "=v")
 321         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 322                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 323    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 324   "TARGET_ALTIVEC"
 325   "vadduhs %0,%1,%2"
 326   [(set_attr "type" "vecsimple")])
 327
 328 (define_insn "altivec_vaddshs"
 329   [(set (match_operand:V8HI 0 "register_operand" "=v")
 330         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 331                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 332    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 333   "TARGET_ALTIVEC"
 334   "vaddshs %0,%1,%2"
 335   [(set_attr "type" "vecsimple")])
 336
 337 (define_insn "altivec_vadduws"
 338   [(set (match_operand:V4SI 0 "register_operand" "=v")
 339         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 340                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 341    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 342   "TARGET_ALTIVEC"
 343   "vadduws %0,%1,%2"
 344   [(set_attr "type" "vecsimple")])
 345
 346 (define_insn "altivec_vaddsws"
 347   [(set (match_operand:V4SI 0 "register_operand" "=v")
 348         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 349                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 350    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 351   "TARGET_ALTIVEC"
 352   "vaddsws %0,%1,%2"
 353   [(set_attr "type" "vecsimple")])
 354
 355 (define_insn "andv4si3"
 356   [(set (match_operand:V4SI 0 "register_operand" "=v")
 357         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 358                   (match_operand:V4SI 2 "register_operand" "v")))]
 359   "TARGET_ALTIVEC"
 360   "vand %0,%1,%2"
 361   [(set_attr "type" "vecsimple")])
 362
 363 (define_insn "altivec_vandc"
 364   [(set (match_operand:V4SI 0 "register_operand" "=v")
 365         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 366                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 367   "TARGET_ALTIVEC"
 368   "vandc %0,%1,%2"
 369   [(set_attr "type" "vecsimple")])
 370
 371 (define_insn "altivec_vavgub"
 372   [(set (match_operand:V16QI 0 "register_operand" "=v")
 373         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 374                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 375   "TARGET_ALTIVEC"
 376   "vavgub %0,%1,%2"
 377   [(set_attr "type" "vecsimple")])
 378
 379 (define_insn "altivec_vavgsb"
 380   [(set (match_operand:V16QI 0 "register_operand" "=v")
 381         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 382                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 383   "TARGET_ALTIVEC"
 384   "vavgsb %0,%1,%2"
 385   [(set_attr "type" "vecsimple")])
 386
 387 (define_insn "altivec_vavguh"
 388   [(set (match_operand:V8HI 0 "register_operand" "=v")
 389         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 390                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 391   "TARGET_ALTIVEC"
 392   "vavguh %0,%1,%2"
 393   [(set_attr "type" "vecsimple")])
 394
 395 (define_insn "altivec_vavgsh"
 396   [(set (match_operand:V8HI 0 "register_operand" "=v")
 397         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 398                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 399   "TARGET_ALTIVEC"
 400   "vavgsh %0,%1,%2"
 401   [(set_attr "type" "vecsimple")])
 402
 403 (define_insn "altivec_vavguw"
 404   [(set (match_operand:V4SI 0 "register_operand" "=v")
 405         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 406                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 407   "TARGET_ALTIVEC"
 408   "vavguw %0,%1,%2"
 409   [(set_attr "type" "vecsimple")])
 410
 411 (define_insn "altivec_vavgsw"
 412   [(set (match_operand:V4SI 0 "register_operand" "=v")
 413         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 414                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 415   "TARGET_ALTIVEC"
 416   "vavgsw %0,%1,%2"
 417   [(set_attr "type" "vecsimple")])
 418
 419 (define_insn "altivec_vcmpbfp"
 420   [(set (match_operand:V4SI 0 "register_operand" "=v")
 421         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 422                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 423   "TARGET_ALTIVEC"
 424   "vcmpbfp %0,%1,%2"
 425   [(set_attr "type" "veccmp")])
 426
 427 (define_insn "altivec_vcmpequb"
 428   [(set (match_operand:V16QI 0 "register_operand" "=v")
 429         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 430                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 431   "TARGET_ALTIVEC"
 432   "vcmpequb %0,%1,%2"
 433   [(set_attr "type" "vecsimple")])
 434
 435 (define_insn "altivec_vcmpequh"
 436   [(set (match_operand:V8HI 0 "register_operand" "=v")
 437         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 438                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 439   "TARGET_ALTIVEC"
 440   "vcmpequh %0,%1,%2"
 441   [(set_attr "type" "vecsimple")])
 442
 443 (define_insn "altivec_vcmpequw"
 444   [(set (match_operand:V4SI 0 "register_operand" "=v")
 445         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 446                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 447   "TARGET_ALTIVEC"
 448   "vcmpequw %0,%1,%2"
 449   [(set_attr "type" "vecsimple")])
 450
 451 (define_insn "altivec_vcmpeqfp"
 452   [(set (match_operand:V4SI 0 "register_operand" "=v")
 453         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 454                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 455   "TARGET_ALTIVEC"
 456   "vcmpeqfp %0,%1,%2"
 457   [(set_attr "type" "veccmp")])
 458
 459 (define_insn "altivec_vcmpgefp"
 460   [(set (match_operand:V4SI 0 "register_operand" "=v")
 461         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 462                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 463   "TARGET_ALTIVEC"
 464   "vcmpgefp %0,%1,%2"
 465   [(set_attr "type" "veccmp")])
 466
 467 (define_insn "altivec_vcmpgtub"
 468   [(set (match_operand:V16QI 0 "register_operand" "=v")
 469         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 470                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 471   "TARGET_ALTIVEC"
 472   "vcmpgtub %0,%1,%2"
 473   [(set_attr "type" "vecsimple")])
 474
 475 (define_insn "altivec_vcmpgtsb"
 476   [(set (match_operand:V16QI 0 "register_operand" "=v")
 477         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 478                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 479   "TARGET_ALTIVEC"
 480   "vcmpgtsb %0,%1,%2"
 481   [(set_attr "type" "vecsimple")])
 482
 483 (define_insn "altivec_vcmpgtuh"
 484   [(set (match_operand:V8HI 0 "register_operand" "=v")
 485         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 486                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 487   "TARGET_ALTIVEC"
 488   "vcmpgtuh %0,%1,%2"
 489   [(set_attr "type" "vecsimple")])
 490
 491 (define_insn "altivec_vcmpgtsh"
 492   [(set (match_operand:V8HI 0 "register_operand" "=v")
 493         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 494                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 495   "TARGET_ALTIVEC"
 496   "vcmpgtsh %0,%1,%2"
 497   [(set_attr "type" "vecsimple")])
 498
 499 (define_insn "altivec_vcmpgtuw"
 500   [(set (match_operand:V4SI 0 "register_operand" "=v")
 501         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 502                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 503   "TARGET_ALTIVEC"
 504   "vcmpgtuw %0,%1,%2"
 505   [(set_attr "type" "vecsimple")])
 506
 507 (define_insn "altivec_vcmpgtsw"
 508   [(set (match_operand:V4SI 0 "register_operand" "=v")
 509         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 510                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 511   "TARGET_ALTIVEC"
 512   "vcmpgtsw %0,%1,%2"
 513   [(set_attr "type" "vecsimple")])
 514
 515 (define_insn "altivec_vcmpgtfp"
 516   [(set (match_operand:V4SI 0 "register_operand" "=v")
 517         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 518                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 519   "TARGET_ALTIVEC"
 520   "vcmpgtfp %0,%1,%2"
 521   [(set_attr "type" "veccmp")])
 522
 523 ;; Fused multiply add
 524 (define_insn "altivec_vmaddfp"
 525   [(set (match_operand:V4SF 0 "register_operand" "=v")
 526         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 527                               (match_operand:V4SF 2 "register_operand" "v"))
 528                    (match_operand:V4SF 3 "register_operand" "v")))]
 529   "TARGET_ALTIVEC"
 530   "vmaddfp %0,%1,%2,%3"
 531   [(set_attr "type" "vecfloat")])
 532
 533 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 534
 535 (define_expand "mulv4sf3"
 536   [(use (match_operand:V4SF 0 "register_operand" ""))
 537    (use (match_operand:V4SF 1 "register_operand" ""))
 538    (use (match_operand:V4SF 2 "register_operand" ""))]
 539   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 540   "
 541 {
 542   rtx neg0;
 543
 544   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 545   neg0 = gen_reg_rtx (V4SFmode);
 546   emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
 547   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 548
 549   /* Use the multiply-add.  */
 550   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 551                                   neg0));
 552   DONE;
 553 }")
 554
 555 ;; Fused multiply subtract
 556 (define_insn "altivec_vnmsubfp"
 557   [(set (match_operand:V4SF 0 "register_operand" "=v")
 558         (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 559                                (match_operand:V4SF 2 "register_operand" "v"))
 560                     (match_operand:V4SF 3 "register_operand" "v")))]
 561   "TARGET_ALTIVEC"
 562   "vnmsubfp %0,%1,%2,%3"
 563   [(set_attr "type" "vecfloat")])
 564
 565
 566 (define_insn "altivec_vmsumubm"
 567   [(set (match_operand:V4SI 0 "register_operand" "=v")
 568         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 569                       (match_operand:V16QI 2 "register_operand" "v")
 570                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 571   "TARGET_ALTIVEC"
 572   "vmsumubm %0,%1,%2,%3"
 573   [(set_attr "type" "veccomplex")])
 574
 575 (define_insn "altivec_vmsummbm"
 576   [(set (match_operand:V4SI 0 "register_operand" "=v")
 577         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 578                       (match_operand:V16QI 2 "register_operand" "v")
 579                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 580   "TARGET_ALTIVEC"
 581   "vmsumubm %0,%1,%2,%3"
 582   [(set_attr "type" "veccomplex")])
 583
 584 (define_insn "altivec_vmsumuhm"
 585   [(set (match_operand:V4SI 0 "register_operand" "=v")
 586         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 587                       (match_operand:V8HI 2 "register_operand" "v")
 588                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 589   "TARGET_ALTIVEC"
 590   "vmsumuhm %0,%1,%2,%3"
 591   [(set_attr "type" "veccomplex")])
 592
 593 (define_insn "altivec_vmsumshm"
 594   [(set (match_operand:V4SI 0 "register_operand" "=v")
 595         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 596                       (match_operand:V8HI 2 "register_operand" "v")
 597                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 598   "TARGET_ALTIVEC"
 599   "vmsumshm %0,%1,%2,%3"
 600   [(set_attr "type" "veccomplex")])
 601
 602 (define_insn "altivec_vmsumuhs"
 603   [(set (match_operand:V4SI 0 "register_operand" "=v")
 604         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 605                       (match_operand:V8HI 2 "register_operand" "v")
 606                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 607    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 608   "TARGET_ALTIVEC"
 609   "vmsumuhs %0,%1,%2,%3"
 610   [(set_attr "type" "veccomplex")])
 611
 612 (define_insn "altivec_vmsumshs"
 613   [(set (match_operand:V4SI 0 "register_operand" "=v")
 614         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 615                       (match_operand:V8HI 2 "register_operand" "v")
 616                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 617    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 618   "TARGET_ALTIVEC"
 619   "vmsumshs %0,%1,%2,%3"
 620   [(set_attr "type" "veccomplex")])
 621
 622 (define_insn "umaxv16qi3"
 623   [(set (match_operand:V16QI 0 "register_operand" "=v")
 624         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 625                     (match_operand:V16QI 2 "register_operand" "v")))]
 626   "TARGET_ALTIVEC"
 627   "vmaxub %0,%1,%2"
 628   [(set_attr "type" "vecsimple")])
 629
 630 (define_insn "smaxv16qi3"
 631   [(set (match_operand:V16QI 0 "register_operand" "=v")
 632         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 633                     (match_operand:V16QI 2 "register_operand" "v")))]
 634   "TARGET_ALTIVEC"
 635   "vmaxsb %0,%1,%2"
 636   [(set_attr "type" "vecsimple")])
 637
 638 (define_insn "umaxv8hi3"
 639   [(set (match_operand:V8HI 0 "register_operand" "=v")
 640         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 641                    (match_operand:V8HI 2 "register_operand" "v")))]
 642   "TARGET_ALTIVEC"
 643   "vmaxuh %0,%1,%2"
 644   [(set_attr "type" "vecsimple")])
 645
 646 (define_insn "smaxv8hi3"
 647   [(set (match_operand:V8HI 0 "register_operand" "=v")
 648         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 649                    (match_operand:V8HI 2 "register_operand" "v")))]
 650   "TARGET_ALTIVEC"
 651   "vmaxsh %0,%1,%2"
 652   [(set_attr "type" "vecsimple")])
 653
 654 (define_insn "umaxv4si3"
 655   [(set (match_operand:V4SI 0 "register_operand" "=v")
 656         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 657                    (match_operand:V4SI 2 "register_operand" "v")))]
 658   "TARGET_ALTIVEC"
 659   "vmaxuw %0,%1,%2"
 660   [(set_attr "type" "vecsimple")])
 661
 662 (define_insn "smaxv4si3"
 663   [(set (match_operand:V4SI 0 "register_operand" "=v")
 664         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 665                    (match_operand:V4SI 2 "register_operand" "v")))]
 666   "TARGET_ALTIVEC"
 667   "vmaxsw %0,%1,%2"
 668   [(set_attr "type" "vecsimple")])
 669
 670 (define_insn "smaxv4sf3"
 671   [(set (match_operand:V4SF 0 "register_operand" "=v")
 672         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 673                    (match_operand:V4SF 2 "register_operand" "v")))]
 674   "TARGET_ALTIVEC"
 675   "vmaxfp %0,%1,%2"
 676   [(set_attr "type" "veccmp")])
 677
 678 (define_insn "altivec_vmhaddshs"
 679   [(set (match_operand:V8HI 0 "register_operand" "=v")
 680         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 681                       (match_operand:V8HI 2 "register_operand" "v")
 682                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 683    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 684   "TARGET_ALTIVEC"
 685   "vmhaddshs %0,%1,%2,%3"
 686   [(set_attr "type" "veccomplex")])
 687 (define_insn "altivec_vmhraddshs"
 688   [(set (match_operand:V8HI 0 "register_operand" "=v")
 689         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 690                       (match_operand:V8HI 2 "register_operand" "v")
 691                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 692    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 693   "TARGET_ALTIVEC"
 694   "vmhraddshs %0,%1,%2,%3"
 695   [(set_attr "type" "veccomplex")])
 696 (define_insn "altivec_vmladduhm"
 697   [(set (match_operand:V8HI 0 "register_operand" "=v")
 698         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 699                       (match_operand:V8HI 2 "register_operand" "v")
 700                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 701   "TARGET_ALTIVEC"
 702   "vmladduhm %0,%1,%2,%3"
 703   [(set_attr "type" "veccomplex")])
 704
 705 (define_insn "altivec_vmrghb"
 706   [(set (match_operand:V16QI 0 "register_operand" "=v")
 707         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 708                                            (parallel [(const_int 8)
 709                                                       (const_int 9)
 710                                                       (const_int 10)
 711                                                       (const_int 11)
 712                                                       (const_int 12)
 713                                                       (const_int 13)
 714                                                       (const_int 14)
 715                                                       (const_int 15)
 716                                                       (const_int 0)
 717                                                       (const_int 1)
 718                                                       (const_int 2)
 719                                                       (const_int 3)
 720                                                       (const_int 4)
 721                                                       (const_int 5)
 722                                                       (const_int 6)
 723                                                       (const_int 7)]))
 724                       (match_operand:V16QI 2 "register_operand" "v")
 725                       (const_int 255)))]
 726   "TARGET_ALTIVEC"
 727   "vmrghb %0,%1,%2"
 728   [(set_attr "type" "vecperm")])
 729
 730 (define_insn "altivec_vmrghh"
 731   [(set (match_operand:V8HI 0 "register_operand" "=v")
 732         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 733                                            (parallel [(const_int 4)
 734                                                       (const_int 5)
 735                                                       (const_int 6)
 736                                                       (const_int 7)
 737                                                       (const_int 0)
 738                                                       (const_int 1)
 739                                                       (const_int 2)
 740                                                       (const_int 3)]))
 741                       (match_operand:V8HI 2 "register_operand" "v")
 742                       (const_int 15)))]
 743   "TARGET_ALTIVEC"
 744   "vmrghh %0,%1,%2"
 745   [(set_attr "type" "vecperm")])
 746
 747 (define_insn "altivec_vmrghw"
 748   [(set (match_operand:V4SI 0 "register_operand" "=v")
 749         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 750                                          (parallel [(const_int 2)
 751                                                     (const_int 3)
 752                                                     (const_int 0)
 753                                                     (const_int 1)]))
 754                       (match_operand:V4SI 2 "register_operand" "v")
 755                       (const_int 12)))]
 756   "TARGET_ALTIVEC"
 757   "vmrghw %0,%1,%2"
 758   [(set_attr "type" "vecperm")])
 759
 760 (define_insn "altivec_vmrglb"
 761   [(set (match_operand:V16QI 0 "register_operand" "=v")
 762         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 763                                            (parallel [(const_int 0)
 764                                                       (const_int 1)
 765                                                       (const_int 2)
 766                                                       (const_int 3)
 767                                                       (const_int 4)
 768                                                       (const_int 5)
 769                                                       (const_int 6)
 770                                                       (const_int 7)
 771                                                       (const_int 8)
 772                                                       (const_int 9)
 773                                                       (const_int 10)
 774                                                       (const_int 11)
 775                                                       (const_int 12)
 776                                                       (const_int 13)
 777                                                       (const_int 14)
 778                                                       (const_int 15)]))
 779                       (match_operand:V16QI 1 "register_operand" "v")
 780                       (const_int 255)))]
 781   "TARGET_ALTIVEC"
 782   "vmrglb %0,%1,%2"
 783   [(set_attr "type" "vecperm")])
 784
 785 (define_insn "altivec_vmrglh"
 786   [(set (match_operand:V8HI 0 "register_operand" "=v")
 787         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 788                                            (parallel [(const_int 0)
 789                                                       (const_int 1)
 790                                                       (const_int 2)
 791                                                       (const_int 3)
 792                                                       (const_int 4)
 793                                                       (const_int 5)
 794                                                       (const_int 6)
 795                                                       (const_int 7)]))
 796                       (match_operand:V8HI 1 "register_operand" "v")
 797                       (const_int 15)))]
 798   "TARGET_ALTIVEC"
 799   "vmrglh %0,%1,%2"
 800   [(set_attr "type" "vecperm")])
 801
 802 (define_insn "altivec_vmrglw"
 803   [(set (match_operand:V4SI 0 "register_operand" "=v")
 804         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 805                                          (parallel [(const_int 0)
 806                                                     (const_int 1)
 807                                                     (const_int 2)
 808                                                     (const_int 3)]))
 809                       (match_operand:V4SI 1 "register_operand" "v")
 810                       (const_int 12)))]
 811   "TARGET_ALTIVEC"
 812   "vmrglw %0,%1,%2"
 813   [(set_attr "type" "vecperm")])
 814
 815 (define_insn "uminv16qi3"
 816   [(set (match_operand:V16QI 0 "register_operand" "=v")
 817         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 818                     (match_operand:V16QI 2 "register_operand" "v")))]
 819   "TARGET_ALTIVEC"
 820   "vminub %0,%1,%2"
 821   [(set_attr "type" "vecsimple")])
 822
 823 (define_insn "sminv16qi3"
 824   [(set (match_operand:V16QI 0 "register_operand" "=v")
 825         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 826                     (match_operand:V16QI 2 "register_operand" "v")))]
 827   "TARGET_ALTIVEC"
 828   "vminsb %0,%1,%2"
 829   [(set_attr "type" "vecsimple")])
 830
 831 (define_insn "uminv8hi3"
 832   [(set (match_operand:V8HI 0 "register_operand" "=v")
 833         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 834                    (match_operand:V8HI 2 "register_operand" "v")))]
 835   "TARGET_ALTIVEC"
 836   "vminuh %0,%1,%2"
 837   [(set_attr "type" "vecsimple")])
 838
 839 (define_insn "sminv8hi3"
 840   [(set (match_operand:V8HI 0 "register_operand" "=v")
 841         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 842                    (match_operand:V8HI 2 "register_operand" "v")))]
 843   "TARGET_ALTIVEC"
 844   "vminsh %0,%1,%2"
 845   [(set_attr "type" "vecsimple")])
 846
 847 (define_insn "uminv4si3"
 848   [(set (match_operand:V4SI 0 "register_operand" "=v")
 849         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 850                    (match_operand:V4SI 2 "register_operand" "v")))]
 851   "TARGET_ALTIVEC"
 852   "vminuw %0,%1,%2"
 853   [(set_attr "type" "vecsimple")])
 854
 855 (define_insn "sminv4si3"
 856   [(set (match_operand:V4SI 0 "register_operand" "=v")
 857         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 858                    (match_operand:V4SI 2 "register_operand" "v")))]
 859   "TARGET_ALTIVEC"
 860   "vminsw %0,%1,%2"
 861   [(set_attr "type" "vecsimple")])
 862
 863 (define_insn "sminv4sf3"
 864   [(set (match_operand:V4SF 0 "register_operand" "=v")
 865         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 866                    (match_operand:V4SF 2 "register_operand" "v")))]
 867   "TARGET_ALTIVEC"
 868   "vminfp %0,%1,%2"
 869   [(set_attr "type" "veccmp")])
 870
 871 (define_insn "altivec_vmuleub"
 872   [(set (match_operand:V8HI 0 "register_operand" "=v")
 873         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 874                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 875   "TARGET_ALTIVEC"
 876   "vmuleub %0,%1,%2"
 877   [(set_attr "type" "veccomplex")])
 878
 879 (define_insn "altivec_vmulesb"
 880   [(set (match_operand:V8HI 0 "register_operand" "=v")
 881         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 882                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 883   "TARGET_ALTIVEC"
 884   "vmulesb %0,%1,%2"
 885   [(set_attr "type" "veccomplex")])
 886
 887 (define_insn "altivec_vmuleuh"
 888   [(set (match_operand:V4SI 0 "register_operand" "=v")
 889         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 890                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 891   "TARGET_ALTIVEC"
 892   "vmuleuh %0,%1,%2"
 893   [(set_attr "type" "veccomplex")])
 894
 895 (define_insn "altivec_vmulesh"
 896   [(set (match_operand:V4SI 0 "register_operand" "=v")
 897         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 898                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 899   "TARGET_ALTIVEC"
 900   "vmulesh %0,%1,%2"
 901   [(set_attr "type" "veccomplex")])
 902
 903 (define_insn "altivec_vmuloub"
 904   [(set (match_operand:V8HI 0 "register_operand" "=v")
 905         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 906                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 907   "TARGET_ALTIVEC"
 908   "vmuloub %0,%1,%2"
 909   [(set_attr "type" "veccomplex")])
 910
 911 (define_insn "altivec_vmulosb"
 912   [(set (match_operand:V8HI 0 "register_operand" "=v")
 913         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 914                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 915   "TARGET_ALTIVEC"
 916   "vmulosb %0,%1,%2"
 917   [(set_attr "type" "veccomplex")])
 918
 919 (define_insn "altivec_vmulouh"
 920   [(set (match_operand:V4SI 0 "register_operand" "=v")
 921         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 922                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 923   "TARGET_ALTIVEC"
 924   "vmulouh %0,%1,%2"
 925   [(set_attr "type" "veccomplex")])
 926
 927 (define_insn "altivec_vmulosh"
 928   [(set (match_operand:V4SI 0 "register_operand" "=v")
 929         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 930                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 931   "TARGET_ALTIVEC"
 932   "vmulosh %0,%1,%2"
 933   [(set_attr "type" "veccomplex")])
 934
 935 (define_insn "altivec_vnor"
 936   [(set (match_operand:V4SI 0 "register_operand" "=v")
 937         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 938                             (match_operand:V4SI 2 "register_operand" "v"))))]
 939   "TARGET_ALTIVEC"
 940   "vnor %0,%1,%2"
 941   [(set_attr "type" "vecsimple")])
 942
 943 (define_insn "iorv4si3"
 944   [(set (match_operand:V4SI 0 "register_operand" "=v")
 945         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 946                   (match_operand:V4SI 2 "register_operand" "v")))]
 947   "TARGET_ALTIVEC"
 948   "vor %0,%1,%2"
 949   [(set_attr "type" "vecsimple")])
 950
 951 (define_insn "altivec_vpkuhum"
 952   [(set (match_operand:V16QI 0 "register_operand" "=v")
 953         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 954                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 955   "TARGET_ALTIVEC"
 956   "vpkuhum %0,%1,%2"
 957   [(set_attr "type" "vecperm")])
 958
 959 (define_insn "altivec_vpkuwum"
 960   [(set (match_operand:V8HI 0 "register_operand" "=v")
 961         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 962                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 963   "TARGET_ALTIVEC"
 964   "vpkuwum %0,%1,%2"
 965   [(set_attr "type" "vecperm")])
 966
 967 (define_insn "altivec_vpkpx"
 968   [(set (match_operand:V8HI 0 "register_operand" "=v")
 969         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 970                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
 971   "TARGET_ALTIVEC"
 972   "vpkpx %0,%1,%2"
 973   [(set_attr "type" "vecperm")])
 974
 975 (define_insn "altivec_vpkuhss"
 976   [(set (match_operand:V16QI 0 "register_operand" "=v")
 977         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 978                        (match_operand:V8HI 2 "register_operand" "v")] 96))
 979    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 980   "TARGET_ALTIVEC"
 981   "vpkuhss %0,%1,%2"
 982   [(set_attr "type" "vecperm")])
 983
 984 (define_insn "altivec_vpkshss"
 985   [(set (match_operand:V16QI 0 "register_operand" "=v")
 986         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 987                        (match_operand:V8HI 2 "register_operand" "v")] 97))
 988    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 989   "TARGET_ALTIVEC"
 990   "vpkshss %0,%1,%2"
 991   [(set_attr "type" "vecperm")])
 992
 993 (define_insn "altivec_vpkuwss"
 994   [(set (match_operand:V8HI 0 "register_operand" "=v")
 995         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 996                       (match_operand:V4SI 2 "register_operand" "v")] 98))
 997    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 998   "TARGET_ALTIVEC"
 999   "vpkuwss %0,%1,%2"
1000   [(set_attr "type" "vecperm")])
1001
1002 (define_insn "altivec_vpkswss"
1003   [(set (match_operand:V8HI 0 "register_operand" "=v")
1004         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1005                       (match_operand:V4SI 2 "register_operand" "v")] 99))
1006    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1007   "TARGET_ALTIVEC"
1008   "vpkswss %0,%1,%2"
1009   [(set_attr "type" "vecperm")])
1010
1011 (define_insn "altivec_vpkuhus"
1012   [(set (match_operand:V16QI 0 "register_operand" "=v")
1013         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1014                        (match_operand:V8HI 2 "register_operand" "v")] 100))
1015    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1016   "TARGET_ALTIVEC"
1017   "vpkuhus %0,%1,%2"
1018   [(set_attr "type" "vecperm")])
1019
1020 (define_insn "altivec_vpkshus"
1021   [(set (match_operand:V16QI 0 "register_operand" "=v")
1022         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1023                        (match_operand:V8HI 2 "register_operand" "v")] 101))
1024    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1025   "TARGET_ALTIVEC"
1026   "vpkshus %0,%1,%2"
1027   [(set_attr "type" "vecperm")])
1028
1029 (define_insn "altivec_vpkuwus"
1030   [(set (match_operand:V8HI 0 "register_operand" "=v")
1031         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1032                       (match_operand:V4SI 2 "register_operand" "v")] 102))
1033    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1034   "TARGET_ALTIVEC"
1035   "vpkuwus %0,%1,%2"
1036   [(set_attr "type" "vecperm")])
1037
1038 (define_insn "altivec_vpkswus"
1039   [(set (match_operand:V8HI 0 "register_operand" "=v")
1040         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1041                       (match_operand:V4SI 2 "register_operand" "v")] 103))
1042    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1043   "TARGET_ALTIVEC"
1044   "vpkswus %0,%1,%2"
1045   [(set_attr "type" "vecperm")])
1046
1047 (define_insn "altivec_vrlb"
1048   [(set (match_operand:V16QI 0 "register_operand" "=v")
1049         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1050                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1051   "TARGET_ALTIVEC"
1052   "vrlb %0,%1,%2"
1053   [(set_attr "type" "vecsimple")])
1054
1055 (define_insn "altivec_vrlh"
1056   [(set (match_operand:V8HI 0 "register_operand" "=v")
1057         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1058                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1059   "TARGET_ALTIVEC"
1060   "vrlh %0,%1,%2"
1061   [(set_attr "type" "vecsimple")])
1062
1063 (define_insn "altivec_vrlw"
1064   [(set (match_operand:V4SI 0 "register_operand" "=v")
1065         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1066                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1067   "TARGET_ALTIVEC"
1068   "vrlw %0,%1,%2"
1069   [(set_attr "type" "vecsimple")])
1070
1071 (define_insn "altivec_vslb"
1072   [(set (match_operand:V16QI 0 "register_operand" "=v")
1073         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1074                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1075   "TARGET_ALTIVEC"
1076   "vslb %0,%1,%2"
1077   [(set_attr "type" "vecsimple")])
1078
1079 (define_insn "altivec_vslh"
1080   [(set (match_operand:V8HI 0 "register_operand" "=v")
1081         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1082                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1083   "TARGET_ALTIVEC"
1084   "vslh %0,%1,%2"
1085   [(set_attr "type" "vecsimple")])
1086
1087 (define_insn "altivec_vslw"
1088   [(set (match_operand:V4SI 0 "register_operand" "=v")
1089         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1090                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1091   "TARGET_ALTIVEC"
1092   "vslw %0,%1,%2"
1093   [(set_attr "type" "vecsimple")])
1094
1095 (define_insn "altivec_vslw_v4sf"
1096   [(set (match_operand:V4SF 0 "register_operand" "=v")
1097         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1098                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
1099   "TARGET_ALTIVEC"
1100   "vslw %0,%1,%2"
1101   [(set_attr "type" "vecsimple")])
1102
1103 (define_insn "altivec_vsl"
1104   [(set (match_operand:V4SI 0 "register_operand" "=v")
1105         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1106                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1107   "TARGET_ALTIVEC"
1108   "vsl %0,%1,%2"
1109   [(set_attr "type" "vecperm")])
1110
1111 (define_insn "altivec_vslo"
1112   [(set (match_operand:V4SI 0 "register_operand" "=v")
1113         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1114                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1115   "TARGET_ALTIVEC"
1116   "vslo %0,%1,%2"
1117   [(set_attr "type" "vecperm")])
1118
1119 (define_insn "altivec_vsrb"
1120   [(set (match_operand:V16QI 0 "register_operand" "=v")
1121         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1122                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1123   "TARGET_ALTIVEC"
1124   "vsrb %0,%1,%2"
1125   [(set_attr "type" "vecsimple")])
1126
1127 (define_insn "altivec_vsrh"
1128   [(set (match_operand:V8HI 0 "register_operand" "=v")
1129         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1130                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1131   "TARGET_ALTIVEC"
1132   "vsrh %0,%1,%2"
1133   [(set_attr "type" "vecsimple")])
1134
1135 (define_insn "altivec_vsrw"
1136   [(set (match_operand:V4SI 0 "register_operand" "=v")
1137         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1138                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1139   "TARGET_ALTIVEC"
1140   "vsrw %0,%1,%2"
1141   [(set_attr "type" "vecsimple")])
1142
1143 (define_insn "altivec_vsrab"
1144   [(set (match_operand:V16QI 0 "register_operand" "=v")
1145         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1146                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1147   "TARGET_ALTIVEC"
1148   "vsrab %0,%1,%2"
1149   [(set_attr "type" "vecsimple")])
1150
1151 (define_insn "altivec_vsrah"
1152   [(set (match_operand:V8HI 0 "register_operand" "=v")
1153         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1154                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1155   "TARGET_ALTIVEC"
1156   "vsrah %0,%1,%2"
1157   [(set_attr "type" "vecsimple")])
1158
1159 (define_insn "altivec_vsraw"
1160   [(set (match_operand:V4SI 0 "register_operand" "=v")
1161         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1162                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1163   "TARGET_ALTIVEC"
1164   "vsraw %0,%1,%2"
1165   [(set_attr "type" "vecsimple")])
1166
1167 (define_insn "altivec_vsr"
1168   [(set (match_operand:V4SI 0 "register_operand" "=v")
1169         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1170                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1171   "TARGET_ALTIVEC"
1172   "vsr %0,%1,%2"
1173   [(set_attr "type" "vecperm")])
1174
1175 (define_insn "altivec_vsro"
1176   [(set (match_operand:V4SI 0 "register_operand" "=v")
1177         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1178                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1179   "TARGET_ALTIVEC"
1180   "vsro %0,%1,%2"
1181   [(set_attr "type" "vecperm")])
1182
1183 (define_insn "subv16qi3"
1184   [(set (match_operand:V16QI 0 "register_operand" "=v")
1185         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1186                      (match_operand:V16QI 2 "register_operand" "v")))]
1187   "TARGET_ALTIVEC"
1188   "vsububm %0,%1,%2"
1189   [(set_attr "type" "vecsimple")])
1190
1191 (define_insn "subv8hi3"
1192   [(set (match_operand:V8HI 0 "register_operand" "=v")
1193         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1194                     (match_operand:V8HI 2 "register_operand" "v")))]
1195   "TARGET_ALTIVEC"
1196   "vsubuhm %0,%1,%2"
1197   [(set_attr "type" "vecsimple")])
1198
1199 (define_insn "subv4si3"
1200   [(set (match_operand:V4SI 0 "register_operand" "=v")
1201         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1202                     (match_operand:V4SI 2 "register_operand" "v")))]
1203   "TARGET_ALTIVEC"
1204   "vsubuwm %0,%1,%2"
1205   [(set_attr "type" "vecsimple")])
1206
1207 (define_insn "subv4sf3"
1208   [(set (match_operand:V4SF 0 "register_operand" "=v")
1209         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1210                     (match_operand:V4SF 2 "register_operand" "v")))]
1211   "TARGET_ALTIVEC"
1212   "vsubfp %0,%1,%2"
1213   [(set_attr "type" "vecfloat")])
1214
1215 (define_insn "altivec_vsubcuw"
1216   [(set (match_operand:V4SI 0 "register_operand" "=v")
1217         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1218                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1219   "TARGET_ALTIVEC"
1220   "vsubcuw %0,%1,%2"
1221   [(set_attr "type" "vecsimple")])
1222
1223 (define_insn "altivec_vsububs"
1224   [(set (match_operand:V16QI 0 "register_operand" "=v")
1225         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1226                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1227    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1228   "TARGET_ALTIVEC"
1229   "vsububs %0,%1,%2"
1230   [(set_attr "type" "vecsimple")])
1231
1232 (define_insn "altivec_vsubsbs"
1233   [(set (match_operand:V16QI 0 "register_operand" "=v")
1234         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1235                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1236    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1237   "TARGET_ALTIVEC"
1238   "vsubsbs %0,%1,%2"
1239   [(set_attr "type" "vecsimple")])
1240
1241 (define_insn "altivec_vsubuhs"
1242   [(set (match_operand:V8HI 0 "register_operand" "=v")
1243         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1244                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1245    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1246   "TARGET_ALTIVEC"
1247   "vsubuhs %0,%1,%2"
1248   [(set_attr "type" "vecsimple")])
1249
1250 (define_insn "altivec_vsubshs"
1251   [(set (match_operand:V8HI 0 "register_operand" "=v")
1252         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1253                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1254    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1255   "TARGET_ALTIVEC"
1256   "vsubshs %0,%1,%2"
1257   [(set_attr "type" "vecsimple")])
1258
1259 (define_insn "altivec_vsubuws"
1260   [(set (match_operand:V4SI 0 "register_operand" "=v")
1261         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1262                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1263    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1264   "TARGET_ALTIVEC"
1265   "vsubuws %0,%1,%2"
1266   [(set_attr "type" "vecsimple")])
1267
1268 (define_insn "altivec_vsubsws"
1269   [(set (match_operand:V4SI 0 "register_operand" "=v")
1270         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1271                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1272    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1273   "TARGET_ALTIVEC"
1274   "vsubsws %0,%1,%2"
1275   [(set_attr "type" "vecsimple")])
1276
1277 (define_insn "altivec_vsum4ubs"
1278   [(set (match_operand:V4SI 0 "register_operand" "=v")
1279         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1280                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1281    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1282   "TARGET_ALTIVEC"
1283   "vsum4ubs %0,%1,%2"
1284   [(set_attr "type" "veccomplex")])
1285
1286 (define_insn "altivec_vsum4sbs"
1287   [(set (match_operand:V4SI 0 "register_operand" "=v")
1288         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1289                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1290    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1291   "TARGET_ALTIVEC"
1292   "vsum4sbs %0,%1,%2"
1293   [(set_attr "type" "veccomplex")])
1294
1295 (define_insn "altivec_vsum4shs"
1296   [(set (match_operand:V4SI 0 "register_operand" "=v")
1297         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1298                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1299    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1300   "TARGET_ALTIVEC"
1301   "vsum4shs %0,%1,%2"
1302   [(set_attr "type" "veccomplex")])
1303
1304 (define_insn "altivec_vsum2sws"
1305   [(set (match_operand:V4SI 0 "register_operand" "=v")
1306         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1307                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1308    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1309   "TARGET_ALTIVEC"
1310   "vsum2sws %0,%1,%2"
1311   [(set_attr "type" "veccomplex")])
1312
1313 (define_insn "altivec_vsumsws"
1314   [(set (match_operand:V4SI 0 "register_operand" "=v")
1315         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1316                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1317    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1318   "TARGET_ALTIVEC"
1319   "vsumsws %0,%1,%2"
1320   [(set_attr "type" "veccomplex")])
1321
1322 ;; Vector xor's
1323 (define_insn "xorv4si3"
1324   [(set (match_operand:V4SI 0 "register_operand" "=v")
1325         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1326                   (match_operand:V4SI 2 "register_operand" "v")))]
1327   "TARGET_ALTIVEC"
1328   "vxor %0,%1,%2"
1329   [(set_attr "type" "vecsimple")])
1330
1331 (define_insn "xorv8hi3"
1332   [(set (match_operand:V8HI 0 "register_operand" "=v")
1333         (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1334                   (match_operand:V8HI 2 "register_operand" "v")))]
1335   "TARGET_ALTIVEC"
1336   "vxor %0,%1,%2"
1337   [(set_attr "type" "vecsimple")])
1338
1339 (define_insn "xorv16qi3"
1340   [(set (match_operand:V16QI 0 "register_operand" "=v")
1341         (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1342                    (match_operand:V16QI 2 "register_operand" "v")))]
1343   "TARGET_ALTIVEC"
1344   "vxor %0,%1,%2"
1345   [(set_attr "type" "vecsimple")])
1346
1347 (define_insn "altivec_vspltb"
1348   [(set (match_operand:V16QI 0 "register_operand" "=v")
1349         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1350                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1351   "TARGET_ALTIVEC"
1352   "vspltb %0,%1,%2"
1353   [(set_attr "type" "vecperm")])
1354 ;; End of vector xor's
1355
1356 (define_insn "altivec_vsplth"
1357   [(set (match_operand:V8HI 0 "register_operand" "=v")
1358         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1359                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1360   "TARGET_ALTIVEC"
1361   "vsplth %0,%1,%2"
1362   [(set_attr "type" "vecperm")])
1363
1364 (define_insn "altivec_vspltw"
1365   [(set (match_operand:V4SI 0 "register_operand" "=v")
1366         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1367                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1368   "TARGET_ALTIVEC"
1369   "vspltw %0,%1,%2"
1370   [(set_attr "type" "vecperm")])
1371
1372 (define_insn "altivec_vspltisb"
1373   [(set (match_operand:V16QI 0 "register_operand" "=v")
1374         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1375                       UNSPEC_VSPLTISB))]
1376   "TARGET_ALTIVEC"
1377   "vspltisb %0,%1"
1378   [(set_attr "type" "vecperm")])
1379
1380 (define_insn "altivec_vspltish"
1381   [(set (match_operand:V8HI 0 "register_operand" "=v")
1382         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1383                      UNSPEC_VSPLTISH))]
1384   "TARGET_ALTIVEC"
1385   "vspltish %0,%1"
1386   [(set_attr "type" "vecperm")])
1387
1388 (define_insn "altivec_vspltisw"
1389   [(set (match_operand:V4SI 0 "register_operand" "=v")
1390         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1391                      UNSPEC_VSPLTISW))]
1392   "TARGET_ALTIVEC"
1393   "vspltisw %0,%1"
1394   [(set_attr "type" "vecperm")])
1395
1396 (define_insn "altivec_vspltisw_v4sf"
1397   [(set (match_operand:V4SF 0 "register_operand" "=v")
1398         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1399   "TARGET_ALTIVEC"
1400   "vspltisw %0,%1"
1401   [(set_attr "type" "vecperm")])
1402
1403 (define_insn "ftruncv4sf2"
1404   [(set (match_operand:V4SF 0 "register_operand" "=v")
1405         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1406   "TARGET_ALTIVEC"
1407   "vrfiz %0,%1"
1408   [(set_attr "type" "vecfloat")])
1409
1410 (define_insn "altivec_vperm_4si"
1411   [(set (match_operand:V4SI 0 "register_operand" "=v")
1412         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1413                       (match_operand:V4SI 2 "register_operand" "v")
1414                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1415   "TARGET_ALTIVEC"
1416   "vperm %0,%1,%2,%3"
1417   [(set_attr "type" "vecperm")])
1418
1419 (define_insn "altivec_vperm_4sf"
1420   [(set (match_operand:V4SF 0 "register_operand" "=v")
1421         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1422                       (match_operand:V4SF 2 "register_operand" "v")
1423                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1424   "TARGET_ALTIVEC"
1425   "vperm %0,%1,%2,%3"
1426   [(set_attr "type" "vecperm")])
1427
1428 (define_insn "altivec_vperm_8hi"
1429   [(set (match_operand:V8HI 0 "register_operand" "=v")
1430         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1431                       (match_operand:V8HI 2 "register_operand" "v")
1432                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1433   "TARGET_ALTIVEC"
1434   "vperm %0,%1,%2,%3"
1435   [(set_attr "type" "vecperm")])
1436
1437 (define_insn "altivec_vperm_16qi"
1438   [(set (match_operand:V16QI 0 "register_operand" "=v")
1439         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1440                        (match_operand:V16QI 2 "register_operand" "v")
1441                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1442   "TARGET_ALTIVEC"
1443   "vperm %0,%1,%2,%3"
1444   [(set_attr "type" "vecperm")])
1445
1446 (define_insn "altivec_vrfip"
1447   [(set (match_operand:V4SF 0 "register_operand" "=v")
1448         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1449   "TARGET_ALTIVEC"
1450   "vrfip %0,%1"
1451   [(set_attr "type" "vecfloat")])
1452
1453 (define_insn "altivec_vrfin"
1454   [(set (match_operand:V4SF 0 "register_operand" "=v")
1455         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1456   "TARGET_ALTIVEC"
1457   "vrfin %0,%1"
1458   [(set_attr "type" "vecfloat")])
1459
1460 (define_insn "altivec_vrfim"
1461   [(set (match_operand:V4SF 0 "register_operand" "=v")
1462         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1463   "TARGET_ALTIVEC"
1464   "vrfim %0,%1"
1465   [(set_attr "type" "vecfloat")])
1466
1467 (define_insn "altivec_vcfux"
1468   [(set (match_operand:V4SF 0 "register_operand" "=v")
1469         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1470                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1471   "TARGET_ALTIVEC"
1472   "vcfux %0,%1,%2"
1473   [(set_attr "type" "vecfloat")])
1474
1475 (define_insn "altivec_vcfsx"
1476   [(set (match_operand:V4SF 0 "register_operand" "=v")
1477         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1478                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1479   "TARGET_ALTIVEC"
1480   "vcfsx %0,%1,%2"
1481   [(set_attr "type" "vecfloat")])
1482
1483 (define_insn "altivec_vctuxs"
1484   [(set (match_operand:V4SI 0 "register_operand" "=v")
1485         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1486                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1487    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1488   "TARGET_ALTIVEC"
1489   "vctuxs %0,%1,%2"
1490   [(set_attr "type" "vecfloat")])
1491
1492 (define_insn "altivec_vctsxs"
1493   [(set (match_operand:V4SI 0 "register_operand" "=v")
1494         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1495                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1496    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1497   "TARGET_ALTIVEC"
1498   "vctsxs %0,%1,%2"
1499   [(set_attr "type" "vecfloat")])
1500
1501 (define_insn "altivec_vlogefp"
1502   [(set (match_operand:V4SF 0 "register_operand" "=v")
1503         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1504   "TARGET_ALTIVEC"
1505   "vlogefp %0,%1"
1506   [(set_attr "type" "vecfloat")])
1507
1508 (define_insn "altivec_vexptefp"
1509   [(set (match_operand:V4SF 0 "register_operand" "=v")
1510         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1511   "TARGET_ALTIVEC"
1512   "vexptefp %0,%1"
1513   [(set_attr "type" "vecfloat")])
1514
1515 (define_insn "altivec_vrsqrtefp"
1516   [(set (match_operand:V4SF 0 "register_operand" "=v")
1517         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1518   "TARGET_ALTIVEC"
1519   "vrsqrtefp %0,%1"
1520   [(set_attr "type" "vecfloat")])
1521
1522 (define_insn "altivec_vrefp"
1523   [(set (match_operand:V4SF 0 "register_operand" "=v")
1524         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1525   "TARGET_ALTIVEC"
1526   "vrefp %0,%1"
1527   [(set_attr "type" "vecfloat")])
1528
1529 (define_insn "altivec_vsel_4si"
1530   [(set (match_operand:V4SI 0 "register_operand" "=v")
1531         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1532                       (match_operand:V4SI 2 "register_operand" "v")
1533                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1534   "TARGET_ALTIVEC"
1535   "vsel %0,%1,%2,%3"
1536   [(set_attr "type" "vecperm")])
1537
1538 (define_insn "altivec_vsel_4sf"
1539   [(set (match_operand:V4SF 0 "register_operand" "=v")
1540         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1541                       (match_operand:V4SF 2 "register_operand" "v")
1542                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1543   "TARGET_ALTIVEC"
1544   "vsel %0,%1,%2,%3"
1545   [(set_attr "type" "vecperm")])
1546
1547 (define_insn "altivec_vsel_8hi"
1548   [(set (match_operand:V8HI 0 "register_operand" "=v")
1549         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1550                       (match_operand:V8HI 2 "register_operand" "v")
1551                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1552   "TARGET_ALTIVEC"
1553   "vsel %0,%1,%2,%3"
1554   [(set_attr "type" "vecperm")])
1555
1556 (define_insn "altivec_vsel_16qi"
1557   [(set (match_operand:V16QI 0 "register_operand" "=v")
1558         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1559                        (match_operand:V16QI 2 "register_operand" "v")
1560                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1561   "TARGET_ALTIVEC"
1562   "vsel %0,%1,%2,%3"
1563   [(set_attr "type" "vecperm")])
1564
1565 (define_insn "altivec_vsldoi_4si"
1566   [(set (match_operand:V4SI 0 "register_operand" "=v")
1567         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1568                       (match_operand:V4SI 2 "register_operand" "v")
1569                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1570   "TARGET_ALTIVEC"
1571   "vsldoi %0,%1,%2,%3"
1572   [(set_attr "type" "vecperm")])
1573
1574 (define_insn "altivec_vsldoi_4sf"
1575   [(set (match_operand:V4SF 0 "register_operand" "=v")
1576         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1577                       (match_operand:V4SF 2 "register_operand" "v")
1578                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1579   "TARGET_ALTIVEC"
1580   "vsldoi %0,%1,%2,%3"
1581   [(set_attr "type" "vecperm")])
1582
1583 (define_insn "altivec_vsldoi_8hi"
1584   [(set (match_operand:V8HI 0 "register_operand" "=v")
1585         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1586                       (match_operand:V8HI 2 "register_operand" "v")
1587                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1588   "TARGET_ALTIVEC"
1589   "vsldoi %0,%1,%2,%3"
1590   [(set_attr "type" "vecperm")])
1591
1592 (define_insn "altivec_vsldoi_16qi"
1593   [(set (match_operand:V16QI 0 "register_operand" "=v")
1594         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1595                        (match_operand:V16QI 2 "register_operand" "v")
1596                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1597   "TARGET_ALTIVEC"
1598   "vsldoi %0,%1,%2,%3"
1599   [(set_attr "type" "vecperm")])
1600
1601 (define_insn "altivec_vupkhsb"
1602   [(set (match_operand:V8HI 0 "register_operand" "=v")
1603         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1604   "TARGET_ALTIVEC"
1605   "vupkhsb %0,%1"
1606   [(set_attr "type" "vecperm")])
1607
1608 (define_insn "altivec_vupkhpx"
1609   [(set (match_operand:V4SI 0 "register_operand" "=v")
1610         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1611   "TARGET_ALTIVEC"
1612   "vupkhpx %0,%1"
1613   [(set_attr "type" "vecperm")])
1614
1615 (define_insn "altivec_vupkhsh"
1616   [(set (match_operand:V4SI 0 "register_operand" "=v")
1617         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1618   "TARGET_ALTIVEC"
1619   "vupkhsh %0,%1"
1620   [(set_attr "type" "vecperm")])
1621
1622 (define_insn "altivec_vupklsb"
1623   [(set (match_operand:V8HI 0 "register_operand" "=v")
1624         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1625   "TARGET_ALTIVEC"
1626   "vupklsb %0,%1"
1627   [(set_attr "type" "vecperm")])
1628
1629 (define_insn "altivec_vupklpx"
1630   [(set (match_operand:V4SI 0 "register_operand" "=v")
1631         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1632   "TARGET_ALTIVEC"
1633   "vupklpx %0,%1"
1634   [(set_attr "type" "vecperm")])
1635
1636 (define_insn "altivec_vupklsh"
1637   [(set (match_operand:V4SI 0 "register_operand" "=v")
1638         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1639   "TARGET_ALTIVEC"
1640   "vupklsh %0,%1"
1641   [(set_attr "type" "vecperm")])
1642
1643 ;; AltiVec predicates.
1644
1645 (define_expand "cr6_test_for_zero"
1646   [(set (match_operand:SI 0 "register_operand" "=r")
1647         (eq:SI (reg:CC 74)
1648                (const_int 0)))]
1649   "TARGET_ALTIVEC"
1650   "")
1651
1652 (define_expand "cr6_test_for_zero_reverse"
1653   [(set (match_operand:SI 0 "register_operand" "=r")
1654         (eq:SI (reg:CC 74)
1655                (const_int 0)))
1656    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1657   "TARGET_ALTIVEC"
1658   "")
1659
1660 (define_expand "cr6_test_for_lt"
1661   [(set (match_operand:SI 0 "register_operand" "=r")
1662         (lt:SI (reg:CC 74)
1663                (const_int 0)))]
1664   "TARGET_ALTIVEC"
1665   "")
1666
1667 (define_expand "cr6_test_for_lt_reverse"
1668   [(set (match_operand:SI 0 "register_operand" "=r")
1669         (lt:SI (reg:CC 74)
1670                (const_int 0)))
1671    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1672   "TARGET_ALTIVEC"
1673   "")
1674
1675 ;; We can get away with generating the opcode on the fly (%3 below)
1676 ;; because all the predicates have the same scheduling parameters.
1677
1678 (define_insn "altivec_predicate_v4si"
1679   [(set (reg:CC 74)
1680         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1681                     (match_operand:V4SI 2 "register_operand" "v")
1682                     (match_operand 3 "any_operand" "")] 173))
1683    (clobber (match_scratch:V4SI 0 "=v"))]
1684   "TARGET_ALTIVEC"
1685   "%3 %0,%1,%2"
1686 [(set_attr "type" "veccmp")])
1687
1688 (define_insn "altivec_predicate_v4sf"
1689   [(set (reg:CC 74)
1690         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1691                     (match_operand:V4SF 2 "register_operand" "v")
1692                     (match_operand 3 "any_operand" "")] 174))
1693    (clobber (match_scratch:V4SF 0 "=v"))]
1694   "TARGET_ALTIVEC"
1695   "%3 %0,%1,%2"
1696 [(set_attr "type" "veccmp")])
1697
1698 (define_insn "altivec_predicate_v8hi"
1699   [(set (reg:CC 74)
1700         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1701                     (match_operand:V8HI 2 "register_operand" "v")
1702                     (match_operand 3 "any_operand" "")] 175))
1703    (clobber (match_scratch:V8HI 0 "=v"))]
1704   "TARGET_ALTIVEC"
1705   "%3 %0,%1,%2"
1706 [(set_attr "type" "veccmp")])
1707
1708 (define_insn "altivec_predicate_v16qi"
1709   [(set (reg:CC 74)
1710         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1711                     (match_operand:V16QI 2 "register_operand" "v")
1712                     (match_operand 3 "any_operand" "")] 175))
1713    (clobber (match_scratch:V16QI 0 "=v"))]
1714   "TARGET_ALTIVEC"
1715   "%3 %0,%1,%2"
1716 [(set_attr "type" "veccmp")])
1717
1718 (define_insn "altivec_mtvscr"
1719   [(set (reg:SI 110)
1720         (unspec_volatile:SI
1721          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1722   "TARGET_ALTIVEC"
1723   "mtvscr %0"
1724   [(set_attr "type" "vecsimple")])
1725
1726 (define_insn "altivec_mfvscr"
1727   [(set (match_operand:V8HI 0 "register_operand" "=v")
1728         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1729   "TARGET_ALTIVEC"
1730   "mfvscr %0"
1731   [(set_attr "type" "vecsimple")])
1732
1733 (define_insn "altivec_dssall"
1734   [(unspec [(const_int 0)] 188)]
1735   "TARGET_ALTIVEC"
1736   "dssall"
1737   [(set_attr "type" "vecsimple")])
1738
1739 (define_insn "altivec_dss"
1740   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1741   "TARGET_ALTIVEC"
1742   "dss %0"
1743   [(set_attr "type" "vecsimple")])
1744
1745 (define_insn "altivec_dst"
1746   [(unspec [(match_operand:SI 0 "register_operand" "b")
1747             (match_operand:SI 1 "register_operand" "r")
1748             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1749   "TARGET_ALTIVEC"
1750   "dst %0,%1,%2"
1751   [(set_attr "type" "vecsimple")])
1752
1753 (define_insn "altivec_dstt"
1754   [(unspec [(match_operand:SI 0 "register_operand" "b")
1755             (match_operand:SI 1 "register_operand" "r")
1756             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1757   "TARGET_ALTIVEC"
1758   "dstt %0,%1,%2"
1759   [(set_attr "type" "vecsimple")])
1760
1761 (define_insn "altivec_dstst"
1762   [(unspec [(match_operand:SI 0 "register_operand" "b")
1763             (match_operand:SI 1 "register_operand" "r")
1764             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1765   "TARGET_ALTIVEC"
1766   "dstst %0,%1,%2"
1767   [(set_attr "type" "vecsimple")])
1768
1769 (define_insn "altivec_dststt"
1770   [(unspec [(match_operand:SI 0 "register_operand" "b")
1771             (match_operand:SI 1 "register_operand" "r")
1772             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1773   "TARGET_ALTIVEC"
1774   "dststt %0,%1,%2"
1775   [(set_attr "type" "vecsimple")])
1776
1777 (define_insn "altivec_lvsl"
1778   [(set (match_operand:V16QI 0 "register_operand" "=v")
1779         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1780                        (match_operand:SI 2 "register_operand" "r")] 194))]
1781   "TARGET_ALTIVEC"
1782   "lvsl %0,%1,%2"
1783   [(set_attr "type" "vecload")])
1784
1785 (define_insn "altivec_lvsr"
1786   [(set (match_operand:V16QI 0 "register_operand" "=v")
1787         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1788                        (match_operand:SI 2 "register_operand" "r")] 195))]
1789   "TARGET_ALTIVEC"
1790   "lvsr %0,%1,%2"
1791   [(set_attr "type" "vecload")])
1792
1793 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1794 ;; identical rtl but different instructions-- and gcc gets confused.
1795
1796 (define_insn "altivec_lvebx"
1797   [(parallel
1798     [(set (match_operand:V16QI 0 "register_operand" "=v")
1799           (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b")
1800                               (match_operand:SI 2 "register_operand" "r"))))
1801      (unspec [(const_int 0)] 196)])]
1802   "TARGET_ALTIVEC"
1803   "lvebx %0,%1,%2"
1804   [(set_attr "type" "vecload")])
1805
1806 (define_insn "altivec_lvehx"
1807   [(parallel
1808     [(set (match_operand:V8HI 0 "register_operand" "=v")
1809           (mem:V8HI
1810            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1811                             (match_operand:SI 2 "register_operand" "r"))
1812                    (const_int -2))))
1813      (unspec [(const_int 0)] 197)])]
1814   "TARGET_ALTIVEC"
1815   "lvehx %0,%1,%2"
1816   [(set_attr "type" "vecload")])
1817
1818 (define_insn "altivec_lvewx"
1819   [(parallel
1820     [(set (match_operand:V4SI 0 "register_operand" "=v")
1821           (mem:V4SI
1822            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1823                             (match_operand:SI 2 "register_operand" "r"))
1824                    (const_int -4))))
1825      (unspec [(const_int 0)] 198)])]
1826   "TARGET_ALTIVEC"
1827   "lvewx %0,%1,%2"
1828   [(set_attr "type" "vecload")])
1829
1830 (define_insn "altivec_lvxl"
1831   [(parallel
1832     [(set (match_operand:V4SI 0 "register_operand" "=v")
1833           (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1834                              (match_operand:SI 2 "register_operand" "r"))))
1835      (unspec [(const_int 0)] 213)])]
1836   "TARGET_ALTIVEC"
1837   "lvxl %0,%1,%2"
1838   [(set_attr "type" "vecload")])
1839
1840 (define_insn "altivec_lvx"
1841   [(set (match_operand:V4SI 0 "register_operand" "=v")
1842         (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1843                            (match_operand:SI 2 "register_operand" "r"))))]
1844   "TARGET_ALTIVEC"
1845   "lvx %0,%1,%2"
1846   [(set_attr "type" "vecload")])
1847
1848 (define_insn "altivec_stvx"
1849   [(parallel
1850     [(set (mem:V4SI
1851            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1852                             (match_operand:SI 1 "register_operand" "r"))
1853                    (const_int -16)))
1854           (match_operand:V4SI 2 "register_operand" "v"))
1855      (unspec [(const_int 0)] 201)])]
1856   "TARGET_ALTIVEC"
1857   "stvx %2,%0,%1"
1858   [(set_attr "type" "vecstore")])
1859
1860 (define_insn "altivec_stvxl"
1861   [(parallel
1862     [(set (mem:V4SI
1863            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1864                             (match_operand:SI 1 "register_operand" "r"))
1865                    (const_int -16)))
1866           (match_operand:V4SI 2 "register_operand" "v"))
1867      (unspec [(const_int 0)] 202)])]
1868   "TARGET_ALTIVEC"
1869   "stvxl %2,%0,%1"
1870   [(set_attr "type" "vecstore")])
1871
1872 (define_insn "altivec_stvebx"
1873   [(parallel
1874     [(set (mem:V16QI
1875            (plus:SI (match_operand:SI 0 "register_operand" "b")
1876                     (match_operand:SI 1 "register_operand" "r")))
1877           (match_operand:V16QI 2 "register_operand" "v"))
1878      (unspec [(const_int 0)] 203)])]
1879   "TARGET_ALTIVEC"
1880   "stvebx %2,%0,%1"
1881   [(set_attr "type" "vecstore")])
1882
1883 (define_insn "altivec_stvehx"
1884   [(parallel
1885     [(set (mem:V8HI
1886            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1887                             (match_operand:SI 1 "register_operand" "r"))
1888                    (const_int -2)))
1889           (match_operand:V8HI 2 "register_operand" "v"))
1890      (unspec [(const_int 0)] 204)])]
1891   "TARGET_ALTIVEC"
1892   "stvehx %2,%0,%1"
1893   [(set_attr "type" "vecstore")])
1894
1895 (define_insn "altivec_stvewx"
1896   [(parallel
1897     [(set (mem:V4SI
1898            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1899                             (match_operand:SI 1 "register_operand" "r"))
1900                    (const_int -4)))
1901           (match_operand:V4SI 2 "register_operand" "v"))
1902      (unspec [(const_int 0)] 205)])]
1903   "TARGET_ALTIVEC"
1904   "stvewx %2,%0,%1"
1905   [(set_attr "type" "vecstore")])
1906
1907 (define_insn "absv16qi2"
1908   [(set (match_operand:V16QI 0 "register_operand" "=v")
1909         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1910    (clobber (match_scratch:V16QI 2 "=&v"))
1911    (clobber (match_scratch:V16QI 3 "=&v"))]
1912   "TARGET_ALTIVEC"
1913   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1914   [(set_attr "type" "vecsimple")
1915    (set_attr "length" "12")])
1916
1917 (define_insn "absv8hi2"
1918   [(set (match_operand:V8HI 0 "register_operand" "=v")
1919         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1920    (clobber (match_scratch:V8HI 2 "=&v"))
1921    (clobber (match_scratch:V8HI 3 "=&v"))]
1922   "TARGET_ALTIVEC"
1923   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1924   [(set_attr "type" "vecsimple")
1925    (set_attr "length" "12")])
1926
1927 (define_insn "absv4si2"
1928   [(set (match_operand:V4SI 0 "register_operand" "=v")
1929         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1930    (clobber (match_scratch:V4SI 2 "=&v"))
1931    (clobber (match_scratch:V4SI 3 "=&v"))]
1932   "TARGET_ALTIVEC"
1933   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1934   [(set_attr "type" "vecsimple")
1935    (set_attr "length" "12")])
1936
1937 (define_insn "absv4sf2"
1938   [(set (match_operand:V4SF 0 "register_operand" "=v")
1939         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1940    (clobber (match_scratch:V4SF 2 "=&v"))
1941    (clobber (match_scratch:V4SF 3 "=&v"))]
1942   "TARGET_ALTIVEC"
1943   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1944   [(set_attr "type" "vecsimple")
1945    (set_attr "length" "12")])
1946
1947 (define_insn "altivec_abss_v16qi"
1948   [(set (match_operand:V16QI 0 "register_operand" "=v")
1949         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1950    (clobber (match_scratch:V16QI 2 "=&v"))
1951    (clobber (match_scratch:V16QI 3 "=&v"))]
1952   "TARGET_ALTIVEC"
1953   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1954   [(set_attr "type" "vecsimple")
1955    (set_attr "length" "12")])
1956
1957 (define_insn "altivec_abss_v8hi"
1958   [(set (match_operand:V8HI 0 "register_operand" "=v")
1959         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1960    (clobber (match_scratch:V8HI 2 "=&v"))
1961    (clobber (match_scratch:V8HI 3 "=&v"))]
1962   "TARGET_ALTIVEC"
1963   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1964   [(set_attr "type" "vecsimple")
1965    (set_attr "length" "12")])
1966
1967 (define_insn "altivec_abss_v4si"
1968   [(set (match_operand:V4SI 0 "register_operand" "=v")
1969         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1970    (clobber (match_scratch:V4SI 2 "=&v"))
1971    (clobber (match_scratch:V4SI 3 "=&v"))]
1972   "TARGET_ALTIVEC"
1973   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1974   [(set_attr "type" "vecsimple")
1975    (set_attr "length" "12")])