1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu
;
55 static const char * const alpha_cpu_name
[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp
;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm
;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm
;
72 /* Specify bit size of immediate TLS offsets. */
74 int alpha_tls_size
= 32;
76 /* Strings decoded into the above options. */
78 const char *alpha_cpu_string
; /* -mcpu= */
79 const char *alpha_tune_string
; /* -mtune= */
80 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
81 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
82 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
83 const char *alpha_mlat_string
; /* -mmemory-latency= */
84 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
86 /* Save information from a "cmpxx" operation until the branch or scc is
89 struct alpha_compare alpha_compare
;
91 /* Non-zero if inside of a function, because the Alpha asm can't
92 handle .files inside of functions. */
94 static int inside_function
= FALSE
;
96 /* The number of cycles of latency we should assume on memory reads. */
98 int alpha_memory_latency
= 3;
100 /* Whether the function needs the GP. */
102 static int alpha_function_needs_gp
;
104 /* The alias set for prologue/epilogue register save/restore. */
106 static int alpha_sr_alias_set
;
108 /* The assembler name of the current function. */
110 static const char *alpha_fnname
;
112 /* The next explicit relocation sequence number. */
113 int alpha_next_sequence_number
= 1;
115 /* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117 int alpha_this_literal_sequence_number
;
118 int alpha_this_gpdisp_sequence_number
;
120 /* Declarations of static functions. */
121 static int tls_symbolic_operand_1
122 PARAMS ((rtx
, enum machine_mode
, int, int));
123 static enum tls_model tls_symbolic_operand_type
125 static bool decl_in_text_section
127 static bool alpha_in_small_data_p
129 static void alpha_encode_section_info
130 PARAMS ((tree
, int));
131 static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
133 static int some_small_symbolic_operand_1
134 PARAMS ((rtx
*, void *));
135 static int split_small_symbolic_operand_1
136 PARAMS ((rtx
*, void *));
137 static void alpha_set_memflags_1
138 PARAMS ((rtx
, int, int, int));
139 static rtx alpha_emit_set_const_1
140 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
141 static void alpha_expand_unaligned_load_words
142 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
143 static void alpha_expand_unaligned_store_words
144 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
145 static void alpha_sa_mask
146 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
147 static int find_lo_sum
148 PARAMS ((rtx
*, void *));
149 static int alpha_does_function_need_gp
151 static int alpha_ra_ever_killed
153 static const char *get_trap_mode_suffix
155 static const char *get_round_mode_suffix
157 static const char *get_some_local_dynamic_name
159 static int get_some_local_dynamic_name_1
160 PARAMS ((rtx
*, void *));
161 static rtx set_frame_related_p
163 static const char *alpha_lookup_xfloating_lib_func
164 PARAMS ((enum rtx_code
));
165 static int alpha_compute_xfloating_mode_arg
166 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
167 static void alpha_emit_xfloating_libcall
168 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
169 static rtx alpha_emit_xfloating_compare
170 PARAMS ((enum rtx_code
, rtx
, rtx
));
171 static void alpha_output_function_end_prologue
173 static int alpha_adjust_cost
174 PARAMS ((rtx
, rtx
, rtx
, int));
175 static int alpha_issue_rate
177 static int alpha_use_dfa_pipeline_interface
179 static int alpha_multipass_dfa_lookahead
182 #ifdef OBJECT_FORMAT_ELF
183 static void alpha_elf_select_rtx_section
184 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
187 static void alpha_init_machine_status
188 PARAMS ((struct function
*p
));
189 static void alpha_mark_machine_status
190 PARAMS ((struct function
*p
));
191 static void alpha_free_machine_status
192 PARAMS ((struct function
*p
));
194 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
195 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
196 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
197 static int unicosmk_need_dex
PARAMS ((rtx
));
199 /* Get the number of args of a function in one of two ways. */
200 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
201 #define NUM_ARGS current_function_args_info.num_args
203 #define NUM_ARGS current_function_args_info
209 /* Initialize the GCC target structure. */
210 #if TARGET_ABI_OPEN_VMS
211 const struct attribute_spec vms_attribute_table
[];
212 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
213 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
214 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
215 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
216 # undef TARGET_ATTRIBUTE_TABLE
217 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
218 # undef TARGET_SECTION_TYPE_FLAGS
219 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
222 #undef TARGET_IN_SMALL_DATA_P
223 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
224 #undef TARGET_ENCODE_SECTION_INFO
225 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
229 #if TARGET_ABI_UNICOSMK
230 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
231 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
232 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
234 static void unicosmk_unique_section
PARAMS ((tree
, int));
235 # undef TARGET_INSERT_ATTRIBUTES
236 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
237 # undef TARGET_SECTION_TYPE_FLAGS
238 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
239 # undef TARGET_ASM_UNIQUE_SECTION
240 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
243 #undef TARGET_ASM_ALIGNED_HI_OP
244 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
245 #undef TARGET_ASM_ALIGNED_DI_OP
246 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
248 /* Default unaligned ops are provided for ELF systems. To get unaligned
249 data for non-ELF systems, we have to turn off auto alignment. */
250 #ifndef OBJECT_FORMAT_ELF
251 #undef TARGET_ASM_UNALIGNED_HI_OP
252 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
253 #undef TARGET_ASM_UNALIGNED_SI_OP
254 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
255 #undef TARGET_ASM_UNALIGNED_DI_OP
256 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
259 #ifdef OBJECT_FORMAT_ELF
260 #undef TARGET_ASM_SELECT_RTX_SECTION
261 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
264 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
265 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
267 #undef TARGET_SCHED_ADJUST_COST
268 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
269 #undef TARGET_SCHED_ISSUE_RATE
270 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
271 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
272 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
273 alpha_use_dfa_pipeline_interface
274 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
275 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
276 alpha_multipass_dfa_lookahead
278 #undef TARGET_HAVE_TLS
279 #define TARGET_HAVE_TLS HAVE_AS_TLS
281 struct gcc_target targetm
= TARGET_INITIALIZER
;
283 /* Parse target option strings. */
289 static const struct cpu_table
{
290 const char *const name
;
291 const enum processor_type processor
;
294 #define EV5_MASK (MASK_CPU_EV5)
295 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
296 { "ev4", PROCESSOR_EV4
, 0 },
297 { "ev45", PROCESSOR_EV4
, 0 },
298 { "21064", PROCESSOR_EV4
, 0 },
299 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
300 { "21164", PROCESSOR_EV5
, EV5_MASK
},
301 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
302 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
303 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
304 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
305 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
306 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
307 { "21264", PROCESSOR_EV6
, EV6_MASK
},
308 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
309 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
313 /* Unicos/Mk doesn't have shared libraries. */
314 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
316 warning ("-f%s ignored for Unicos/Mk (not supported)",
317 (flag_pic
> 1) ? "PIC" : "pic");
321 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
322 floating-point instructions. Make that the default for this target. */
323 if (TARGET_ABI_UNICOSMK
)
324 alpha_fprm
= ALPHA_FPRM_DYN
;
326 alpha_fprm
= ALPHA_FPRM_NORM
;
328 alpha_tp
= ALPHA_TP_PROG
;
329 alpha_fptm
= ALPHA_FPTM_N
;
331 /* We cannot use su and sui qualifiers for conversion instructions on
332 Unicos/Mk. I'm not sure if this is due to assembler or hardware
333 limitations. Right now, we issue a warning if -mieee is specified
334 and then ignore it; eventually, we should either get it right or
335 disable the option altogether. */
339 if (TARGET_ABI_UNICOSMK
)
340 warning ("-mieee not supported on Unicos/Mk");
343 alpha_tp
= ALPHA_TP_INSN
;
344 alpha_fptm
= ALPHA_FPTM_SU
;
348 if (TARGET_IEEE_WITH_INEXACT
)
350 if (TARGET_ABI_UNICOSMK
)
351 warning ("-mieee-with-inexact not supported on Unicos/Mk");
354 alpha_tp
= ALPHA_TP_INSN
;
355 alpha_fptm
= ALPHA_FPTM_SUI
;
361 if (! strcmp (alpha_tp_string
, "p"))
362 alpha_tp
= ALPHA_TP_PROG
;
363 else if (! strcmp (alpha_tp_string
, "f"))
364 alpha_tp
= ALPHA_TP_FUNC
;
365 else if (! strcmp (alpha_tp_string
, "i"))
366 alpha_tp
= ALPHA_TP_INSN
;
368 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
371 if (alpha_fprm_string
)
373 if (! strcmp (alpha_fprm_string
, "n"))
374 alpha_fprm
= ALPHA_FPRM_NORM
;
375 else if (! strcmp (alpha_fprm_string
, "m"))
376 alpha_fprm
= ALPHA_FPRM_MINF
;
377 else if (! strcmp (alpha_fprm_string
, "c"))
378 alpha_fprm
= ALPHA_FPRM_CHOP
;
379 else if (! strcmp (alpha_fprm_string
,"d"))
380 alpha_fprm
= ALPHA_FPRM_DYN
;
382 error ("bad value `%s' for -mfp-rounding-mode switch",
386 if (alpha_fptm_string
)
388 if (strcmp (alpha_fptm_string
, "n") == 0)
389 alpha_fptm
= ALPHA_FPTM_N
;
390 else if (strcmp (alpha_fptm_string
, "u") == 0)
391 alpha_fptm
= ALPHA_FPTM_U
;
392 else if (strcmp (alpha_fptm_string
, "su") == 0)
393 alpha_fptm
= ALPHA_FPTM_SU
;
394 else if (strcmp (alpha_fptm_string
, "sui") == 0)
395 alpha_fptm
= ALPHA_FPTM_SUI
;
397 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
400 if (alpha_tls_size_string
)
402 if (strcmp (alpha_tls_size_string
, "16") == 0)
404 else if (strcmp (alpha_tls_size_string
, "32") == 0)
406 else if (strcmp (alpha_tls_size_string
, "64") == 0)
409 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
413 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
414 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
416 if (alpha_cpu_string
)
418 for (i
= 0; cpu_table
[i
].name
; i
++)
419 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
421 alpha_cpu
= cpu_table
[i
].processor
;
422 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
423 | MASK_CPU_EV5
| MASK_CPU_EV6
);
424 target_flags
|= cpu_table
[i
].flags
;
427 if (! cpu_table
[i
].name
)
428 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
431 if (alpha_tune_string
)
433 for (i
= 0; cpu_table
[i
].name
; i
++)
434 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
436 alpha_cpu
= cpu_table
[i
].processor
;
439 if (! cpu_table
[i
].name
)
440 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
443 /* Do some sanity checks on the above options. */
445 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
447 warning ("trap mode not supported on Unicos/Mk");
448 alpha_fptm
= ALPHA_FPTM_N
;
451 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
452 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
454 warning ("fp software completion requires -mtrap-precision=i");
455 alpha_tp
= ALPHA_TP_INSN
;
460 /* Except for EV6 pass 1 (not released), we always have precise
461 arithmetic traps. Which means we can do software completion
462 without minding trap shadows. */
463 alpha_tp
= ALPHA_TP_PROG
;
466 if (TARGET_FLOAT_VAX
)
468 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
470 warning ("rounding mode not supported for VAX floats");
471 alpha_fprm
= ALPHA_FPRM_NORM
;
473 if (alpha_fptm
== ALPHA_FPTM_SUI
)
475 warning ("trap mode not supported for VAX floats");
476 alpha_fptm
= ALPHA_FPTM_SU
;
484 if (!alpha_mlat_string
)
485 alpha_mlat_string
= "L1";
487 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
488 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
490 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
491 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
492 && alpha_mlat_string
[2] == '\0')
494 static int const cache_latency
[][4] =
496 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
497 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
498 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
501 lat
= alpha_mlat_string
[1] - '0';
502 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
504 warning ("L%d cache latency unknown for %s",
505 lat
, alpha_cpu_name
[alpha_cpu
]);
509 lat
= cache_latency
[alpha_cpu
][lat
-1];
511 else if (! strcmp (alpha_mlat_string
, "main"))
513 /* Most current memories have about 370ns latency. This is
514 a reasonable guess for a fast cpu. */
519 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
523 alpha_memory_latency
= lat
;
526 /* Default the definition of "small data" to 8 bytes. */
530 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
532 target_flags
|= MASK_SMALL_DATA
;
533 else if (flag_pic
== 2)
534 target_flags
&= ~MASK_SMALL_DATA
;
536 /* Align labels and loops for optimal branching. */
537 /* ??? Kludge these by not doing anything if we don't optimize and also if
538 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
539 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
541 if (align_loops
<= 0)
543 if (align_jumps
<= 0)
546 if (align_functions
<= 0)
547 align_functions
= 16;
549 /* Acquire a unique set number for our register saves and restores. */
550 alpha_sr_alias_set
= new_alias_set ();
552 /* Register variables and functions with the garbage collector. */
554 /* Set up function hooks. */
555 init_machine_status
= alpha_init_machine_status
;
556 mark_machine_status
= alpha_mark_machine_status
;
557 free_machine_status
= alpha_free_machine_status
;
560 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
568 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
570 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
576 /* Returns 1 if OP is either the constant zero or a register. If a
577 register, it must be in the proper mode unless MODE is VOIDmode. */
580 reg_or_0_operand (op
, mode
)
582 enum machine_mode mode
;
584 return op
== const0_rtx
|| register_operand (op
, mode
);
587 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
591 reg_or_6bit_operand (op
, mode
)
593 enum machine_mode mode
;
595 return ((GET_CODE (op
) == CONST_INT
596 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
597 || register_operand (op
, mode
));
601 /* Return 1 if OP is an 8-bit constant or any register. */
604 reg_or_8bit_operand (op
, mode
)
606 enum machine_mode mode
;
608 return ((GET_CODE (op
) == CONST_INT
609 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
610 || register_operand (op
, mode
));
613 /* Return 1 if OP is an 8-bit constant. */
616 cint8_operand (op
, mode
)
618 enum machine_mode mode ATTRIBUTE_UNUSED
;
620 return ((GET_CODE (op
) == CONST_INT
621 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
624 /* Return 1 if the operand is a valid second operand to an add insn. */
627 add_operand (op
, mode
)
629 enum machine_mode mode
;
631 if (GET_CODE (op
) == CONST_INT
)
632 /* Constraints I, J, O and P are covered by K. */
633 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
634 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
636 return register_operand (op
, mode
);
639 /* Return 1 if the operand is a valid second operand to a sign-extending
643 sext_add_operand (op
, mode
)
645 enum machine_mode mode
;
647 if (GET_CODE (op
) == CONST_INT
)
648 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
649 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
651 return reg_not_elim_operand (op
, mode
);
654 /* Return 1 if OP is the constant 4 or 8. */
657 const48_operand (op
, mode
)
659 enum machine_mode mode ATTRIBUTE_UNUSED
;
661 return (GET_CODE (op
) == CONST_INT
662 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
665 /* Return 1 if OP is a valid first operand to an AND insn. */
668 and_operand (op
, mode
)
670 enum machine_mode mode
;
672 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
673 return (zap_mask (CONST_DOUBLE_LOW (op
))
674 && zap_mask (CONST_DOUBLE_HIGH (op
)));
676 if (GET_CODE (op
) == CONST_INT
)
677 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
678 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
679 || zap_mask (INTVAL (op
)));
681 return register_operand (op
, mode
);
684 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
687 or_operand (op
, mode
)
689 enum machine_mode mode
;
691 if (GET_CODE (op
) == CONST_INT
)
692 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
693 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
695 return register_operand (op
, mode
);
698 /* Return 1 if OP is a constant that is the width, in bits, of an integral
699 mode smaller than DImode. */
702 mode_width_operand (op
, mode
)
704 enum machine_mode mode ATTRIBUTE_UNUSED
;
706 return (GET_CODE (op
) == CONST_INT
707 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
708 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
711 /* Return 1 if OP is a constant that is the width of an integral machine mode
712 smaller than an integer. */
715 mode_mask_operand (op
, mode
)
717 enum machine_mode mode ATTRIBUTE_UNUSED
;
719 #if HOST_BITS_PER_WIDE_INT == 32
720 if (GET_CODE (op
) == CONST_DOUBLE
)
721 return (CONST_DOUBLE_LOW (op
) == -1
722 && (CONST_DOUBLE_HIGH (op
) == -1
723 || CONST_DOUBLE_HIGH (op
) == 0));
725 if (GET_CODE (op
) == CONST_DOUBLE
)
726 return (CONST_DOUBLE_LOW (op
) == -1 && CONST_DOUBLE_HIGH (op
) == 0);
729 return (GET_CODE (op
) == CONST_INT
730 && (INTVAL (op
) == 0xff
731 || INTVAL (op
) == 0xffff
732 || INTVAL (op
) == (HOST_WIDE_INT
)0xffffffff
733 #if HOST_BITS_PER_WIDE_INT == 64
739 /* Return 1 if OP is a multiple of 8 less than 64. */
742 mul8_operand (op
, mode
)
744 enum machine_mode mode ATTRIBUTE_UNUSED
;
746 return (GET_CODE (op
) == CONST_INT
747 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
748 && (INTVAL (op
) & 7) == 0);
751 /* Return 1 if OP is the constant zero in floating-point. */
754 fp0_operand (op
, mode
)
756 enum machine_mode mode
;
758 return (GET_MODE (op
) == mode
759 && GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
));
762 /* Return 1 if OP is the floating-point constant zero or a register. */
765 reg_or_fp0_operand (op
, mode
)
767 enum machine_mode mode
;
769 return fp0_operand (op
, mode
) || register_operand (op
, mode
);
772 /* Return 1 if OP is a hard floating-point register. */
775 hard_fp_register_operand (op
, mode
)
777 enum machine_mode mode
;
779 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
782 if (GET_CODE (op
) == SUBREG
)
783 op
= SUBREG_REG (op
);
784 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
787 /* Return 1 if OP is a hard general register. */
790 hard_int_register_operand (op
, mode
)
792 enum machine_mode mode
;
794 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
797 if (GET_CODE (op
) == SUBREG
)
798 op
= SUBREG_REG (op
);
799 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
802 /* Return 1 if OP is a register or a constant integer. */
806 reg_or_cint_operand (op
, mode
)
808 enum machine_mode mode
;
810 return (GET_CODE (op
) == CONST_INT
811 || register_operand (op
, mode
));
814 /* Return 1 if OP is something that can be reloaded into a register;
815 if it is a MEM, it need not be valid. */
818 some_operand (op
, mode
)
820 enum machine_mode mode
;
822 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
825 switch (GET_CODE (op
))
827 case REG
: case MEM
: case CONST_DOUBLE
: case CONST_INT
: case LABEL_REF
:
828 case SYMBOL_REF
: case CONST
: case HIGH
:
832 return some_operand (SUBREG_REG (op
), VOIDmode
);
841 /* Likewise, but don't accept constants. */
844 some_ni_operand (op
, mode
)
846 enum machine_mode mode
;
848 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
851 if (GET_CODE (op
) == SUBREG
)
852 op
= SUBREG_REG (op
);
854 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
857 /* Return 1 if OP is a valid operand for the source of a move insn. */
860 input_operand (op
, mode
)
862 enum machine_mode mode
;
864 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
867 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
870 switch (GET_CODE (op
))
875 if (TARGET_EXPLICIT_RELOCS
)
877 /* We don't split symbolic operands into something unintelligable
878 until after reload, but we do not wish non-small, non-global
879 symbolic operands to be reconstructed from their high/lo_sum
881 return (small_symbolic_operand (op
, mode
)
882 || global_symbolic_operand (op
, mode
)
883 || gotdtp_symbolic_operand (op
, mode
)
884 || gottp_symbolic_operand (op
, mode
));
887 /* This handles both the Windows/NT and OSF cases. */
888 return mode
== ptr_mode
|| mode
== DImode
;
891 return (TARGET_EXPLICIT_RELOCS
892 && local_symbolic_operand (XEXP (op
, 0), mode
));
899 if (register_operand (op
, mode
))
901 /* ... fall through ... */
903 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
904 && general_operand (op
, mode
));
907 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
910 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
922 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
923 file, and in the same section as the current function. */
926 current_file_function_operand (op
, mode
)
928 enum machine_mode mode ATTRIBUTE_UNUSED
;
930 if (GET_CODE (op
) != SYMBOL_REF
)
933 /* Easy test for recursion. */
934 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
937 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
938 So SYMBOL_REF_FLAG has been declared to imply that the function is
939 in the default text section. So we must also check that the current
940 function is also in the text section. */
941 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
947 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
950 direct_call_operand (op
, mode
)
952 enum machine_mode mode
;
954 /* Must be defined in this file. */
955 if (! current_file_function_operand (op
, mode
))
958 /* If profiling is implemented via linker tricks, we can't jump
959 to the nogp alternate entry point. */
960 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
961 but is approximately correct for the OSF ABIs. Don't know
962 what to do for VMS, NT, or UMK. */
963 if (! TARGET_PROFILING_NEEDS_GP
964 && ! current_function_profile
)
970 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
971 a variable known to be defined in this file. */
974 local_symbolic_operand (op
, mode
)
976 enum machine_mode mode
;
980 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
983 if (GET_CODE (op
) == LABEL_REF
)
986 if (GET_CODE (op
) == CONST
987 && GET_CODE (XEXP (op
, 0)) == PLUS
988 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
989 op
= XEXP (XEXP (op
, 0), 0);
991 if (GET_CODE (op
) != SYMBOL_REF
)
995 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
998 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
999 run into problems with the rtl inliner in that the symbol was
1000 once external, but is local after inlining, which results in
1001 unrecognizable insns. */
1005 /* If @[VS], then alpha_encode_section_info sez it's local. */
1006 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1009 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1010 if (str
[0] == '*' && str
[1] == '$')
1016 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1017 known to be defined in this file in the small data area. */
1020 small_symbolic_operand (op
, mode
)
1022 enum machine_mode mode ATTRIBUTE_UNUSED
;
1026 if (! TARGET_SMALL_DATA
)
1029 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1032 if (GET_CODE (op
) == CONST
1033 && GET_CODE (XEXP (op
, 0)) == PLUS
1034 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1035 op
= XEXP (XEXP (op
, 0), 0);
1037 if (GET_CODE (op
) != SYMBOL_REF
)
1040 if (CONSTANT_POOL_ADDRESS_P (op
))
1041 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1045 return str
[0] == '@' && str
[1] == 'S';
1049 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1050 not known (or known not) to be defined in this file. */
1053 global_symbolic_operand (op
, mode
)
1055 enum machine_mode mode
;
1059 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1062 if (GET_CODE (op
) == CONST
1063 && GET_CODE (XEXP (op
, 0)) == PLUS
1064 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1065 op
= XEXP (XEXP (op
, 0), 0);
1067 if (GET_CODE (op
) != SYMBOL_REF
)
1070 if (local_symbolic_operand (op
, mode
))
1073 /* Also verify that it's not a TLS symbol. */
1075 return str
[0] != '%' && str
[0] != '@';
1078 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1081 call_operand (op
, mode
)
1083 enum machine_mode mode
;
1088 if (GET_CODE (op
) == REG
)
1092 /* Disallow virtual registers to cope with pathalogical test cases
1093 such as compile/930117-1.c in which the virtual reg decomposes
1094 to the frame pointer. Which is a hard reg that is not $27. */
1095 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1100 if (TARGET_ABI_UNICOSMK
)
1102 if (GET_CODE (op
) == SYMBOL_REF
)
1108 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1109 possibly with an offset. */
1112 symbolic_operand (op
, mode
)
1114 enum machine_mode mode
;
1116 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1118 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1120 if (GET_CODE (op
) == CONST
1121 && GET_CODE (XEXP (op
,0)) == PLUS
1122 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1123 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1128 /* Return true if OP is valid for a particular TLS relocation. */
1131 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1133 enum machine_mode mode
;
1139 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1142 if (GET_CODE (op
) != CONST
)
1146 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1148 op
= XVECEXP (op
, 0, 0);
1150 if (GET_CODE (op
) != SYMBOL_REF
)
1159 else if (str
[0] == '@')
1161 if (alpha_tls_size
> size
)
1167 letter
= (unspec
== UNSPEC_DTPREL
? 'D' : 'T');
1169 return str
[1] == letter
;
1172 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1175 dtp16_symbolic_operand (op
, mode
)
1177 enum machine_mode mode
;
1179 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1182 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1185 dtp32_symbolic_operand (op
, mode
)
1187 enum machine_mode mode
;
1189 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1192 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1195 gotdtp_symbolic_operand (op
, mode
)
1197 enum machine_mode mode
;
1199 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1202 /* Return true if OP is valid for 16-bit TP relative relocations. */
1205 tp16_symbolic_operand (op
, mode
)
1207 enum machine_mode mode
;
1209 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1212 /* Return true if OP is valid for 32-bit TP relative relocations. */
1215 tp32_symbolic_operand (op
, mode
)
1217 enum machine_mode mode
;
1219 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1222 /* Return true if OP is valid for 64-bit TP relative relocations. */
1225 gottp_symbolic_operand (op
, mode
)
1227 enum machine_mode mode
;
1229 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1232 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1233 comparisons are valid in which insn. */
1236 alpha_comparison_operator (op
, mode
)
1238 enum machine_mode mode
;
1240 enum rtx_code code
= GET_CODE (op
);
1242 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1245 return (code
== EQ
|| code
== LE
|| code
== LT
1246 || code
== LEU
|| code
== LTU
);
1249 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1250 Here we know which comparisons are valid in which insn. */
1253 alpha_zero_comparison_operator (op
, mode
)
1255 enum machine_mode mode
;
1257 enum rtx_code code
= GET_CODE (op
);
1259 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1262 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1263 || code
== LEU
|| code
== LTU
);
1266 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1269 alpha_swapped_comparison_operator (op
, mode
)
1271 enum machine_mode mode
;
1273 enum rtx_code code
= GET_CODE (op
);
1275 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1276 || GET_RTX_CLASS (code
) != '<')
1279 code
= swap_condition (code
);
1280 return (code
== EQ
|| code
== LE
|| code
== LT
1281 || code
== LEU
|| code
== LTU
);
1284 /* Return 1 if OP is a signed comparison operation. */
1287 signed_comparison_operator (op
, mode
)
1289 enum machine_mode mode ATTRIBUTE_UNUSED
;
1291 enum rtx_code code
= GET_CODE (op
);
1293 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1296 return (code
== EQ
|| code
== NE
1297 || code
== LE
|| code
== LT
1298 || code
== GE
|| code
== GT
);
1301 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1302 Here we know which comparisons are valid in which insn. */
1305 alpha_fp_comparison_operator (op
, mode
)
1307 enum machine_mode mode
;
1309 enum rtx_code code
= GET_CODE (op
);
1311 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1314 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1317 /* Return 1 if this is a divide or modulus operator. */
1320 divmod_operator (op
, mode
)
1322 enum machine_mode mode ATTRIBUTE_UNUSED
;
1324 switch (GET_CODE (op
))
1326 case DIV
: case MOD
: case UDIV
: case UMOD
:
1336 /* Return 1 if this memory address is a known aligned register plus
1337 a constant. It must be a valid address. This means that we can do
1338 this as an aligned reference plus some offset.
1340 Take into account what reload will do. */
1343 aligned_memory_operand (op
, mode
)
1345 enum machine_mode mode
;
1349 if (reload_in_progress
)
1352 if (GET_CODE (tmp
) == SUBREG
)
1353 tmp
= SUBREG_REG (tmp
);
1354 if (GET_CODE (tmp
) == REG
1355 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1357 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1363 if (GET_CODE (op
) != MEM
1364 || GET_MODE (op
) != mode
)
1368 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1369 sorts of constructs. Dig for the real base register. */
1370 if (reload_in_progress
1371 && GET_CODE (op
) == PLUS
1372 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1373 base
= XEXP (XEXP (op
, 0), 0);
1376 if (! memory_address_p (mode
, op
))
1378 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1381 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1384 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1387 unaligned_memory_operand (op
, mode
)
1389 enum machine_mode mode
;
1393 if (reload_in_progress
)
1396 if (GET_CODE (tmp
) == SUBREG
)
1397 tmp
= SUBREG_REG (tmp
);
1398 if (GET_CODE (tmp
) == REG
1399 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1401 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1407 if (GET_CODE (op
) != MEM
1408 || GET_MODE (op
) != mode
)
1412 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1413 sorts of constructs. Dig for the real base register. */
1414 if (reload_in_progress
1415 && GET_CODE (op
) == PLUS
1416 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1417 base
= XEXP (XEXP (op
, 0), 0);
1420 if (! memory_address_p (mode
, op
))
1422 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1425 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1428 /* Return 1 if OP is either a register or an unaligned memory location. */
1431 reg_or_unaligned_mem_operand (op
, mode
)
1433 enum machine_mode mode
;
1435 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1438 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1441 any_memory_operand (op
, mode
)
1443 enum machine_mode mode ATTRIBUTE_UNUSED
;
1445 return (GET_CODE (op
) == MEM
1446 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1447 || (reload_in_progress
&& GET_CODE (op
) == REG
1448 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1449 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1450 && GET_CODE (SUBREG_REG (op
)) == REG
1451 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1454 /* Returns 1 if OP is not an eliminable register.
1456 This exists to cure a pathological abort in the s8addq (et al) patterns,
1458 long foo () { long t; bar(); return (long) &t * 26107; }
1460 which run afoul of a hack in reload to cure a (presumably) similar
1461 problem with lea-type instructions on other targets. But there is
1462 one of us and many of them, so work around the problem by selectively
1463 preventing combine from making the optimization. */
1466 reg_not_elim_operand (op
, mode
)
1468 enum machine_mode mode
;
1471 if (GET_CODE (op
) == SUBREG
)
1472 inner
= SUBREG_REG (op
);
1473 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1476 return register_operand (op
, mode
);
1479 /* Return 1 is OP is a memory location that is not a reference (using
1480 an AND) to an unaligned location. Take into account what reload
1484 normal_memory_operand (op
, mode
)
1486 enum machine_mode mode ATTRIBUTE_UNUSED
;
1488 if (reload_in_progress
)
1491 if (GET_CODE (tmp
) == SUBREG
)
1492 tmp
= SUBREG_REG (tmp
);
1493 if (GET_CODE (tmp
) == REG
1494 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1496 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1498 /* This may not have been assigned an equivalent address if it will
1499 be eliminated. In that case, it doesn't matter what we do. */
1505 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1508 /* Accept a register, but not a subreg of any kind. This allows us to
1509 avoid pathological cases in reload wrt data movement common in
1510 int->fp conversion. */
1513 reg_no_subreg_operand (op
, mode
)
1515 enum machine_mode mode
;
1517 if (GET_CODE (op
) != REG
)
1519 return register_operand (op
, mode
);
1522 /* Recognize an addition operation that includes a constant. Used to
1523 convince reload to canonize (plus (plus reg c1) c2) during register
1527 addition_operation (op
, mode
)
1529 enum machine_mode mode
;
1531 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1533 if (GET_CODE (op
) == PLUS
1534 && register_operand (XEXP (op
, 0), mode
)
1535 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1536 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1541 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1542 the range defined for C in [I-P]. */
1545 alpha_const_ok_for_letter_p (value
, c
)
1546 HOST_WIDE_INT value
;
1552 /* An unsigned 8 bit constant. */
1553 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1555 /* The constant zero. */
1558 /* A signed 16 bit constant. */
1559 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1561 /* A shifted signed 16 bit constant appropriate for LDAH. */
1562 return ((value
& 0xffff) == 0
1563 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1565 /* A constant that can be AND'ed with using a ZAP insn. */
1566 return zap_mask (value
);
1568 /* A complemented unsigned 8 bit constant. */
1569 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1571 /* A negated unsigned 8 bit constant. */
1572 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1574 /* The constant 1, 2 or 3. */
1575 return value
== 1 || value
== 2 || value
== 3;
1582 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1583 matches for C in [GH]. */
1586 alpha_const_double_ok_for_letter_p (value
, c
)
1593 /* The floating point zero constant. */
1594 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1595 && value
== CONST0_RTX (GET_MODE (value
)));
1598 /* A valid operand of a ZAP insn. */
1599 return (GET_MODE (value
) == VOIDmode
1600 && zap_mask (CONST_DOUBLE_LOW (value
))
1601 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1608 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1612 alpha_extra_constraint (value
, c
)
1619 return normal_memory_operand (value
, VOIDmode
);
1621 return direct_call_operand (value
, Pmode
);
1623 return (GET_CODE (value
) == CONST_INT
1624 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1626 return GET_CODE (value
) == HIGH
;
1628 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1635 /* Return 1 if this function can directly return via $26. */
1640 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1642 && alpha_sa_size () == 0
1643 && get_frame_size () == 0
1644 && current_function_outgoing_args_size
== 0
1645 && current_function_pretend_args_size
== 0);
1648 /* Return the ADDR_VEC associated with a tablejump insn. */
1651 alpha_tablejump_addr_vec (insn
)
1656 tmp
= JUMP_LABEL (insn
);
1659 tmp
= NEXT_INSN (tmp
);
1662 if (GET_CODE (tmp
) == JUMP_INSN
1663 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1664 return PATTERN (tmp
);
1668 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1671 alpha_tablejump_best_label (insn
)
1674 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1675 rtx best_label
= NULL_RTX
;
1677 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1678 there for edge frequency counts from profile data. */
1682 int n_labels
= XVECLEN (jump_table
, 1);
1683 int best_count
= -1;
1686 for (i
= 0; i
< n_labels
; i
++)
1690 for (j
= i
+ 1; j
< n_labels
; j
++)
1691 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1692 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1695 if (count
> best_count
)
1696 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1700 return best_label
? best_label
: const0_rtx
;
1703 /* Return the TLS model to use for SYMBOL. */
1705 static enum tls_model
1706 tls_symbolic_operand_type (symbol
)
1711 if (GET_CODE (symbol
) != SYMBOL_REF
)
1713 str
= XSTR (symbol
, 0);
1717 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1718 have separately encoded local-ness. On well, maybe the user will use
1719 attribute visibility next time. At least we don't crash... */
1720 if (str
[1] == 'G' || str
[1] == 'D')
1721 return TLS_MODEL_GLOBAL_DYNAMIC
;
1723 return TLS_MODEL_INITIAL_EXEC
;
1725 else if (str
[0] == '@')
1729 /* Local dynamic is a waste if we're not going to combine
1730 the __tls_get_addr calls. So avoid it if not optimizing. */
1732 return TLS_MODEL_LOCAL_DYNAMIC
;
1734 return TLS_MODEL_GLOBAL_DYNAMIC
;
1738 /* 64-bit local exec is the same as initial exec except without
1739 the dynamic relocation. In either case we use a got entry. */
1740 if (alpha_tls_size
== 64)
1741 return TLS_MODEL_INITIAL_EXEC
;
1743 return TLS_MODEL_LOCAL_EXEC
;
1751 /* Return true if the function DECL will be placed in the default text
1753 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1754 decl, as that would allow us to determine if two functions are in the
1755 same section, which is what we really want to know. */
1758 decl_in_text_section (decl
)
1761 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1762 && ! (flag_function_sections
1763 || (targetm
.have_named_sections
1764 && DECL_ONE_ONLY (decl
))));
1767 /* Return true if EXP should be placed in the small data section. */
1770 alpha_in_small_data_p (exp
)
1773 /* We want to merge strings, so we never consider them small data. */
1774 if (TREE_CODE (exp
) == STRING_CST
)
1777 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1779 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1780 if (strcmp (section
, ".sdata") == 0
1781 || strcmp (section
, ".sbss") == 0)
1786 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1788 /* If this is an incomplete type with size 0, then we can't put it
1789 in sdata because it might be too big when completed. */
1790 if (size
> 0 && size
<= g_switch_value
)
1797 /* If we are referencing a function that is static, make the SYMBOL_REF
1798 special. We use this to see indicate we can branch to this function
1799 without setting PV or restoring GP.
1801 If this is a variable that is known to be defined locally, add "@v"
1802 to the name. If in addition the variable is to go in .sdata/.sbss,
1803 then add "@s" instead. */
1806 alpha_encode_section_info (decl
, first
)
1808 int first ATTRIBUTE_UNUSED
;
1810 const char *symbol_str
;
1815 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1817 /* Careful not to prod global register variables. */
1818 if (GET_CODE (rtl
) != MEM
)
1820 symbol
= XEXP (rtl
, 0);
1821 if (GET_CODE (symbol
) != SYMBOL_REF
)
1824 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1826 /* We mark public functions once they are emitted; otherwise we
1827 don't know that they exist in this unit of translation. */
1828 if (TREE_PUBLIC (decl
))
1831 /* Do not mark functions that are not in .text; otherwise we
1832 don't know that they are near enough for a direct branch. */
1833 if (! decl_in_text_section (decl
))
1836 SYMBOL_REF_FLAG (symbol
) = 1;
1840 /* Early out if we're not going to do anything with this data. */
1841 if (! TARGET_EXPLICIT_RELOCS
)
1844 symbol_str
= XSTR (symbol
, 0);
1846 /* A variable is considered "local" if it is defined in this module. */
1847 is_local
= (*targetm
.binds_local_p
) (decl
);
1849 /* Care for TLS variables. */
1850 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
1852 enum tls_model kind
;
1856 kind
= TLS_MODEL_LOCAL_EXEC
;
1858 kind
= TLS_MODEL_INITIAL_EXEC
;
1861 kind
= TLS_MODEL_LOCAL_DYNAMIC
;
1863 kind
= TLS_MODEL_GLOBAL_DYNAMIC
;
1864 if (kind
< flag_tls_default
)
1865 kind
= flag_tls_default
;
1869 case TLS_MODEL_GLOBAL_DYNAMIC
:
1872 case TLS_MODEL_LOCAL_DYNAMIC
:
1875 case TLS_MODEL_INITIAL_EXEC
:
1876 case TLS_MODEL_LOCAL_EXEC
:
1883 /* Determine if DECL will wind up in .sdata/.sbss. */
1884 if (alpha_in_small_data_p (decl
))
1890 /* Finally, encode this into the symbol string. */
1896 if (symbol_str
[0] == (is_local
? '@' : '%'))
1898 if (symbol_str
[1] == encoding
)
1903 len
= strlen (symbol_str
) + 1;
1904 newstr
= alloca (len
+ 2);
1906 newstr
[0] = (is_local
? '@' : '%');
1907 newstr
[1] = encoding
;
1908 memcpy (newstr
+ 2, symbol_str
, len
);
1910 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
1914 /* Undo the effects of the above. */
1917 alpha_strip_name_encoding (str
)
1920 if (str
[0] == '@' || str
[0] == '%')
1927 /* legitimate_address_p recognizes an RTL expression that is a valid
1928 memory address for an instruction. The MODE argument is the
1929 machine mode for the MEM expression that wants to use this address.
1931 For Alpha, we have either a constant address or the sum of a
1932 register and a constant address, or just a register. For DImode,
1933 any of those forms can be surrounded with an AND that clear the
1934 low-order three bits; this is an "unaligned" access. */
1937 alpha_legitimate_address_p (mode
, x
, strict
)
1938 enum machine_mode mode
;
1942 /* If this is an ldq_u type address, discard the outer AND. */
1944 && GET_CODE (x
) == AND
1945 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1946 && INTVAL (XEXP (x
, 1)) == -8)
1949 /* Discard non-paradoxical subregs. */
1950 if (GET_CODE (x
) == SUBREG
1951 && (GET_MODE_SIZE (GET_MODE (x
))
1952 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1955 /* Unadorned general registers are valid. */
1958 ? STRICT_REG_OK_FOR_BASE_P (x
)
1959 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1962 /* Constant addresses (i.e. +/- 32k) are valid. */
1963 if (CONSTANT_ADDRESS_P (x
))
1966 /* Register plus a small constant offset is valid. */
1967 if (GET_CODE (x
) == PLUS
)
1969 rtx ofs
= XEXP (x
, 1);
1972 /* Discard non-paradoxical subregs. */
1973 if (GET_CODE (x
) == SUBREG
1974 && (GET_MODE_SIZE (GET_MODE (x
))
1975 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1981 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1982 && GET_CODE (ofs
) == CONST_INT
)
1985 ? STRICT_REG_OK_FOR_BASE_P (x
)
1986 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1987 && CONSTANT_ADDRESS_P (ofs
))
1990 else if (GET_CODE (x
) == ADDRESSOF
1991 && GET_CODE (ofs
) == CONST_INT
)
1995 /* If we're managing explicit relocations, LO_SUM is valid, as
1996 are small data symbols. */
1997 else if (TARGET_EXPLICIT_RELOCS
)
1999 if (small_symbolic_operand (x
, Pmode
))
2002 if (GET_CODE (x
) == LO_SUM
)
2004 rtx ofs
= XEXP (x
, 1);
2007 /* Discard non-paradoxical subregs. */
2008 if (GET_CODE (x
) == SUBREG
2009 && (GET_MODE_SIZE (GET_MODE (x
))
2010 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2013 /* Must have a valid base register. */
2016 ? STRICT_REG_OK_FOR_BASE_P (x
)
2017 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2020 /* The symbol must be local. */
2021 if (local_symbolic_operand (ofs
, Pmode
)
2022 || dtp32_symbolic_operand (ofs
, Pmode
)
2023 || tp32_symbolic_operand (ofs
, Pmode
))
2031 /* Try machine-dependent ways of modifying an illegitimate address
2032 to be legitimate. If we find one, return the new, valid address. */
2035 alpha_legitimize_address (x
, scratch
, mode
)
2038 enum machine_mode mode ATTRIBUTE_UNUSED
;
2040 HOST_WIDE_INT addend
;
2042 /* If the address is (plus reg const_int) and the CONST_INT is not a
2043 valid offset, compute the high part of the constant and add it to
2044 the register. Then our address is (plus temp low-part-const). */
2045 if (GET_CODE (x
) == PLUS
2046 && GET_CODE (XEXP (x
, 0)) == REG
2047 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2048 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2050 addend
= INTVAL (XEXP (x
, 1));
2055 /* If the address is (const (plus FOO const_int)), find the low-order
2056 part of the CONST_INT. Then load FOO plus any high-order part of the
2057 CONST_INT into a register. Our address is (plus reg low-part-const).
2058 This is done to reduce the number of GOT entries. */
2060 && GET_CODE (x
) == CONST
2061 && GET_CODE (XEXP (x
, 0)) == PLUS
2062 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2064 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2065 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2069 /* If we have a (plus reg const), emit the load as in (2), then add
2070 the two registers, and finally generate (plus reg low-part-const) as
2073 && GET_CODE (x
) == PLUS
2074 && GET_CODE (XEXP (x
, 0)) == REG
2075 && GET_CODE (XEXP (x
, 1)) == CONST
2076 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2077 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2079 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2080 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2081 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2082 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2086 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2087 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2089 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2091 switch (tls_symbolic_operand_type (x
))
2093 case TLS_MODEL_GLOBAL_DYNAMIC
:
2096 r0
= gen_rtx_REG (Pmode
, 0);
2097 r16
= gen_rtx_REG (Pmode
, 16);
2098 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2099 dest
= gen_reg_rtx (Pmode
);
2100 seq
= GEN_INT (alpha_next_sequence_number
++);
2102 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2103 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2104 insn
= emit_call_insn (insn
);
2105 CONST_OR_PURE_CALL_P (insn
) = 1;
2106 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2108 insn
= get_insns ();
2111 emit_libcall_block (insn
, dest
, r0
, x
);
2114 case TLS_MODEL_LOCAL_DYNAMIC
:
2117 r0
= gen_rtx_REG (Pmode
, 0);
2118 r16
= gen_rtx_REG (Pmode
, 16);
2119 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2120 scratch
= gen_reg_rtx (Pmode
);
2121 seq
= GEN_INT (alpha_next_sequence_number
++);
2123 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2124 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2125 insn
= emit_call_insn (insn
);
2126 CONST_OR_PURE_CALL_P (insn
) = 1;
2127 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2129 insn
= get_insns ();
2132 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2133 UNSPEC_TLSLDM_CALL
);
2134 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2136 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2137 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2139 if (alpha_tls_size
== 64)
2141 dest
= gen_reg_rtx (Pmode
);
2142 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2143 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2146 if (alpha_tls_size
== 32)
2148 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2149 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2150 scratch
= gen_reg_rtx (Pmode
);
2151 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2153 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2155 case TLS_MODEL_INITIAL_EXEC
:
2156 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2157 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2158 tp
= gen_reg_rtx (Pmode
);
2159 scratch
= gen_reg_rtx (Pmode
);
2160 dest
= gen_reg_rtx (Pmode
);
2162 emit_insn (gen_load_tp (tp
));
2163 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2164 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2167 case TLS_MODEL_LOCAL_EXEC
:
2168 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2169 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2170 tp
= gen_reg_rtx (Pmode
);
2172 emit_insn (gen_load_tp (tp
));
2173 if (alpha_tls_size
== 32)
2175 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2176 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2177 tp
= gen_reg_rtx (Pmode
);
2178 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2180 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2183 if (local_symbolic_operand (x
, Pmode
))
2185 if (small_symbolic_operand (x
, Pmode
))
2189 if (!no_new_pseudos
)
2190 scratch
= gen_reg_rtx (Pmode
);
2191 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2192 gen_rtx_HIGH (Pmode
, x
)));
2193 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2202 HOST_WIDE_INT low
, high
;
2204 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2206 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2210 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2211 (no_new_pseudos
? scratch
: NULL_RTX
),
2212 1, OPTAB_LIB_WIDEN
);
2214 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2215 (no_new_pseudos
? scratch
: NULL_RTX
),
2216 1, OPTAB_LIB_WIDEN
);
2218 return plus_constant (x
, low
);
2222 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2223 small symbolic operand until after reload. At which point we need
2224 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2225 so that sched2 has the proper dependency information. */
2228 some_small_symbolic_operand (x
, mode
)
2230 enum machine_mode mode ATTRIBUTE_UNUSED
;
2232 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2236 some_small_symbolic_operand_1 (px
, data
)
2238 void *data ATTRIBUTE_UNUSED
;
2242 /* Don't re-split. */
2243 if (GET_CODE (x
) == LO_SUM
)
2246 return small_symbolic_operand (x
, Pmode
) != 0;
2250 split_small_symbolic_operand (x
)
2254 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2259 split_small_symbolic_operand_1 (px
, data
)
2261 void *data ATTRIBUTE_UNUSED
;
2265 /* Don't re-split. */
2266 if (GET_CODE (x
) == LO_SUM
)
2269 if (small_symbolic_operand (x
, Pmode
))
2271 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2279 /* Try a machine-dependent way of reloading an illegitimate address
2280 operand. If we find one, push the reload and return the new rtx. */
2283 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2285 enum machine_mode mode ATTRIBUTE_UNUSED
;
2288 int ind_levels ATTRIBUTE_UNUSED
;
2290 /* We must recognize output that we have already generated ourselves. */
2291 if (GET_CODE (x
) == PLUS
2292 && GET_CODE (XEXP (x
, 0)) == PLUS
2293 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2294 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2295 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2297 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2298 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2303 /* We wish to handle large displacements off a base register by
2304 splitting the addend across an ldah and the mem insn. This
2305 cuts number of extra insns needed from 3 to 1. */
2306 if (GET_CODE (x
) == PLUS
2307 && GET_CODE (XEXP (x
, 0)) == REG
2308 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2309 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2310 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2312 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2313 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2315 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2317 /* Check for 32-bit overflow. */
2318 if (high
+ low
!= val
)
2321 /* Reload the high part into a base reg; leave the low part
2322 in the mem directly. */
2323 x
= gen_rtx_PLUS (GET_MODE (x
),
2324 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2328 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2329 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2337 /* REF is an alignable memory location. Place an aligned SImode
2338 reference into *PALIGNED_MEM and the number of bits to shift into
2339 *PBITNUM. SCRATCH is a free register for use in reloading out
2340 of range stack slots. */
2343 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2345 rtx
*paligned_mem
, *pbitnum
;
2348 HOST_WIDE_INT offset
= 0;
2350 if (GET_CODE (ref
) != MEM
)
2353 if (reload_in_progress
2354 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2356 base
= find_replacement (&XEXP (ref
, 0));
2358 if (! memory_address_p (GET_MODE (ref
), base
))
2363 base
= XEXP (ref
, 0);
2366 if (GET_CODE (base
) == PLUS
)
2367 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2370 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2372 if (WORDS_BIG_ENDIAN
)
2373 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2374 + (offset
& 3) * 8));
2376 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2379 /* Similar, but just get the address. Handle the two reload cases.
2380 Add EXTRA_OFFSET to the address we return. */
2383 get_unaligned_address (ref
, extra_offset
)
2388 HOST_WIDE_INT offset
= 0;
2390 if (GET_CODE (ref
) != MEM
)
2393 if (reload_in_progress
2394 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2396 base
= find_replacement (&XEXP (ref
, 0));
2398 if (! memory_address_p (GET_MODE (ref
), base
))
2403 base
= XEXP (ref
, 0);
2406 if (GET_CODE (base
) == PLUS
)
2407 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2409 return plus_constant (base
, offset
+ extra_offset
);
2412 /* On the Alpha, all (non-symbolic) constants except zero go into
2413 a floating-point register via memory. Note that we cannot
2414 return anything that is not a subset of CLASS, and that some
2415 symbolic constants cannot be dropped to memory. */
2418 alpha_preferred_reload_class(x
, class)
2420 enum reg_class
class;
2422 /* Zero is present in any register class. */
2423 if (x
== CONST0_RTX (GET_MODE (x
)))
2426 /* These sorts of constants we can easily drop to memory. */
2427 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2429 if (class == FLOAT_REGS
)
2431 if (class == ALL_REGS
)
2432 return GENERAL_REGS
;
2436 /* All other kinds of constants should not (and in the case of HIGH
2437 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2438 secondary reload. */
2440 return (class == ALL_REGS
? GENERAL_REGS
: class);
2445 /* Loading and storing HImode or QImode values to and from memory
2446 usually requires a scratch register. The exceptions are loading
2447 QImode and HImode from an aligned address to a general register
2448 unless byte instructions are permitted.
2450 We also cannot load an unaligned address or a paradoxical SUBREG
2451 into an FP register.
2453 We also cannot do integral arithmetic into FP regs, as might result
2454 from register elimination into a DImode fp register. */
2457 secondary_reload_class (class, mode
, x
, in
)
2458 enum reg_class
class;
2459 enum machine_mode mode
;
2463 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2465 if (GET_CODE (x
) == MEM
2466 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2467 || (GET_CODE (x
) == SUBREG
2468 && (GET_CODE (SUBREG_REG (x
)) == MEM
2469 || (GET_CODE (SUBREG_REG (x
)) == REG
2470 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2472 if (!in
|| !aligned_memory_operand(x
, mode
))
2473 return GENERAL_REGS
;
2477 if (class == FLOAT_REGS
)
2479 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2480 return GENERAL_REGS
;
2482 if (GET_CODE (x
) == SUBREG
2483 && (GET_MODE_SIZE (GET_MODE (x
))
2484 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2485 return GENERAL_REGS
;
2487 if (in
&& INTEGRAL_MODE_P (mode
)
2488 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2489 return GENERAL_REGS
;
2495 /* Subfunction of the following function. Update the flags of any MEM
2496 found in part of X. */
2499 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2501 int in_struct_p
, volatile_p
, unchanging_p
;
2505 switch (GET_CODE (x
))
2509 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2510 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2515 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2520 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2522 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2527 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2528 MEM_VOLATILE_P (x
) = volatile_p
;
2529 RTX_UNCHANGING_P (x
) = unchanging_p
;
2530 /* Sadly, we cannot use alias sets because the extra aliasing
2531 produced by the AND interferes. Given that two-byte quantities
2532 are the only thing we would be able to differentiate anyway,
2533 there does not seem to be any point in convoluting the early
2534 out of the alias check. */
2542 /* Given INSN, which is either an INSN or a SEQUENCE generated to
2543 perform a memory operation, look for any MEMs in either a SET_DEST or
2544 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
2545 REF into each of the MEMs found. If REF is not a MEM, don't do
2549 alpha_set_memflags (insn
, ref
)
2553 int in_struct_p
, volatile_p
, unchanging_p
;
2555 if (GET_CODE (ref
) != MEM
)
2558 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2559 volatile_p
= MEM_VOLATILE_P (ref
);
2560 unchanging_p
= RTX_UNCHANGING_P (ref
);
2562 /* This is only called from alpha.md, after having had something
2563 generated from one of the insn patterns. So if everything is
2564 zero, the pattern is already up-to-date. */
2565 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2568 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2571 /* Try to output insns to set TARGET equal to the constant C if it can be
2572 done in less than N insns. Do all computations in MODE. Returns the place
2573 where the output has been placed if it can be done and the insns have been
2574 emitted. If it would take more than N insns, zero is returned and no
2575 insns and emitted. */
2578 alpha_emit_set_const (target
, mode
, c
, n
)
2580 enum machine_mode mode
;
2585 rtx orig_target
= target
;
2588 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2589 can't load this constant in one insn, do this in DImode. */
2590 if (no_new_pseudos
&& mode
== SImode
2591 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2592 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2594 target
= gen_lowpart (DImode
, target
);
2598 /* Try 1 insn, then 2, then up to N. */
2599 for (i
= 1; i
<= n
; i
++)
2601 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2604 rtx insn
= get_last_insn ();
2605 rtx set
= single_set (insn
);
2606 if (! CONSTANT_P (SET_SRC (set
)))
2607 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2612 /* Allow for the case where we changed the mode of TARGET. */
2613 if (result
== target
)
2614 result
= orig_target
;
2619 /* Internal routine for the above to check for N or below insns. */
2622 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2624 enum machine_mode mode
;
2630 /* Use a pseudo if highly optimizing and still generating RTL. */
2632 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2635 /* If this is a sign-extended 32-bit constant, we can do this in at most
2636 three insns, so do it if we have enough insns left. We always have
2637 a sign-extended 32-bit constant when compiling on a narrow machine. */
2639 if (HOST_BITS_PER_WIDE_INT
!= 64
2640 || c
>> 31 == -1 || c
>> 31 == 0)
2642 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2643 HOST_WIDE_INT tmp1
= c
- low
;
2644 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2645 HOST_WIDE_INT extra
= 0;
2647 /* If HIGH will be interpreted as negative but the constant is
2648 positive, we must adjust it to do two ldha insns. */
2650 if ((high
& 0x8000) != 0 && c
>= 0)
2654 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2657 if (c
== low
|| (low
== 0 && extra
== 0))
2659 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2660 but that meant that we can't handle INT_MIN on 32-bit machines
2661 (like NT/Alpha), because we recurse indefinitely through
2662 emit_move_insn to gen_movdi. So instead, since we know exactly
2663 what we want, create it explicitly. */
2666 target
= gen_reg_rtx (mode
);
2667 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2670 else if (n
>= 2 + (extra
!= 0))
2672 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2674 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2675 This means that if we go through expand_binop, we'll try to
2676 generate extensions, etc, which will require new pseudos, which
2677 will fail during some split phases. The SImode add patterns
2678 still exist, but are not named. So build the insns by hand. */
2683 subtarget
= gen_reg_rtx (mode
);
2684 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2685 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2691 target
= gen_reg_rtx (mode
);
2692 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2693 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2699 /* If we couldn't do it that way, try some other methods. But if we have
2700 no instructions left, don't bother. Likewise, if this is SImode and
2701 we can't make pseudos, we can't do anything since the expand_binop
2702 and expand_unop calls will widen and try to make pseudos. */
2704 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2707 /* Next, see if we can load a related constant and then shift and possibly
2708 negate it to get the constant we want. Try this once each increasing
2709 numbers of insns. */
2711 for (i
= 1; i
< n
; i
++)
2713 /* First, see if minus some low bits, we've an easy load of
2716 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2718 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2719 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2720 target
, 0, OPTAB_WIDEN
);
2722 /* Next try complementing. */
2723 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2724 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2726 /* Next try to form a constant and do a left shift. We can do this
2727 if some low-order bits are zero; the exact_log2 call below tells
2728 us that information. The bits we are shifting out could be any
2729 value, but here we'll just try the 0- and sign-extended forms of
2730 the constant. To try to increase the chance of having the same
2731 constant in more than one insn, start at the highest number of
2732 bits to shift, but try all possibilities in case a ZAPNOT will
2735 if ((bits
= exact_log2 (c
& - c
)) > 0)
2736 for (; bits
> 0; bits
--)
2737 if ((temp
= (alpha_emit_set_const
2738 (subtarget
, mode
, c
>> bits
, i
))) != 0
2739 || ((temp
= (alpha_emit_set_const
2741 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2743 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2744 target
, 0, OPTAB_WIDEN
);
2746 /* Now try high-order zero bits. Here we try the shifted-in bits as
2747 all zero and all ones. Be careful to avoid shifting outside the
2748 mode and to avoid shifting outside the host wide int size. */
2749 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2750 confuse the recursive call and set all of the high 32 bits. */
2752 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2753 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2754 for (; bits
> 0; bits
--)
2755 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2757 || ((temp
= (alpha_emit_set_const
2759 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2762 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2763 target
, 1, OPTAB_WIDEN
);
2765 /* Now try high-order 1 bits. We get that with a sign-extension.
2766 But one bit isn't enough here. Be careful to avoid shifting outside
2767 the mode and to avoid shifting outside the host wide int size. */
2769 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2770 - floor_log2 (~ c
) - 2)) > 0)
2771 for (; bits
> 0; bits
--)
2772 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2774 || ((temp
= (alpha_emit_set_const
2776 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2779 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2780 target
, 0, OPTAB_WIDEN
);
2783 #if HOST_BITS_PER_WIDE_INT == 64
2784 /* Finally, see if can load a value into the target that is the same as the
2785 constant except that all bytes that are 0 are changed to be 0xff. If we
2786 can, then we can do a ZAPNOT to obtain the desired constant. */
2789 for (i
= 0; i
< 64; i
+= 8)
2790 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2791 new |= (HOST_WIDE_INT
) 0xff << i
;
2793 /* We are only called for SImode and DImode. If this is SImode, ensure that
2794 we are sign extended to a full word. */
2797 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2799 if (new != c
&& new != -1
2800 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2801 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2802 target
, 0, OPTAB_WIDEN
);
2808 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2809 fall back to a straight forward decomposition. We do this to avoid
2810 exponential run times encountered when looking for longer sequences
2811 with alpha_emit_set_const. */
2814 alpha_emit_set_long_const (target
, c1
, c2
)
2816 HOST_WIDE_INT c1
, c2
;
2818 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2820 /* Decompose the entire word */
2821 #if HOST_BITS_PER_WIDE_INT >= 64
2822 if (c2
!= -(c1
< 0))
2824 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2826 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2827 c1
= (c1
- d2
) >> 32;
2828 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2830 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2834 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2836 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2840 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2842 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2847 /* Construct the high word */
2850 emit_move_insn (target
, GEN_INT (d4
));
2852 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2855 emit_move_insn (target
, GEN_INT (d3
));
2857 /* Shift it into place */
2858 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2860 /* Add in the low bits. */
2862 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2864 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2869 /* Expand a move instruction; return true if all work is done.
2870 We don't handle non-bwx subword loads here. */
2873 alpha_expand_mov (mode
, operands
)
2874 enum machine_mode mode
;
2877 /* If the output is not a register, the input must be. */
2878 if (GET_CODE (operands
[0]) == MEM
2879 && ! reg_or_0_operand (operands
[1], mode
))
2880 operands
[1] = force_reg (mode
, operands
[1]);
2882 /* Allow legitimize_address to perform some simplifications. */
2883 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2887 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2888 compiled at the end of compilation. In the meantime, someone can
2889 re-encode-section-info on some symbol changing it e.g. from global
2890 to local-not-small. If this happens, we'd have emitted a plain
2891 load rather than a high+losum load and not recognize the insn.
2893 So if rtl inlining is in effect, we delay the global/not-global
2894 decision until rest_of_compilation by wrapping it in an
2896 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2897 && rtx_equal_function_value_matters
2898 && global_symbolic_operand (operands
[1], mode
))
2900 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2904 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2907 if (tmp
== operands
[0])
2914 /* Early out for non-constants and valid constants. */
2915 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2918 /* Split large integers. */
2919 if (GET_CODE (operands
[1]) == CONST_INT
2920 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2922 HOST_WIDE_INT i0
, i1
;
2923 rtx temp
= NULL_RTX
;
2925 if (GET_CODE (operands
[1]) == CONST_INT
)
2927 i0
= INTVAL (operands
[1]);
2930 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2932 i0
= CONST_DOUBLE_LOW (operands
[1]);
2937 i0
= CONST_DOUBLE_LOW (operands
[1]);
2938 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2941 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2942 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2944 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2945 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2949 if (rtx_equal_p (operands
[0], temp
))
2956 /* Otherwise we've nothing left but to drop the thing to memory. */
2957 operands
[1] = force_const_mem (DImode
, operands
[1]);
2958 if (reload_in_progress
)
2960 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2961 operands
[1] = copy_rtx (operands
[1]);
2962 XEXP (operands
[1], 0) = operands
[0];
2965 operands
[1] = validize_mem (operands
[1]);
2969 /* Expand a non-bwx QImode or HImode move instruction;
2970 return true if all work is done. */
2973 alpha_expand_mov_nobwx (mode
, operands
)
2974 enum machine_mode mode
;
2977 /* If the output is not a register, the input must be. */
2978 if (GET_CODE (operands
[0]) == MEM
)
2979 operands
[1] = force_reg (mode
, operands
[1]);
2981 /* Handle four memory cases, unaligned and aligned for either the input
2982 or the output. The only case where we can be called during reload is
2983 for aligned loads; all other cases require temporaries. */
2985 if (GET_CODE (operands
[1]) == MEM
2986 || (GET_CODE (operands
[1]) == SUBREG
2987 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2988 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2989 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2990 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2991 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2992 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2994 if (aligned_memory_operand (operands
[1], mode
))
2996 if (reload_in_progress
)
2998 emit_insn ((mode
== QImode
2999 ? gen_reload_inqi_help
3000 : gen_reload_inhi_help
)
3001 (operands
[0], operands
[1],
3002 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3006 rtx aligned_mem
, bitnum
;
3007 rtx scratch
= gen_reg_rtx (SImode
);
3009 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3011 emit_insn ((mode
== QImode
3012 ? gen_aligned_loadqi
3013 : gen_aligned_loadhi
)
3014 (operands
[0], aligned_mem
, bitnum
, scratch
));
3019 /* Don't pass these as parameters since that makes the generated
3020 code depend on parameter evaluation order which will cause
3021 bootstrap failures. */
3023 rtx temp1
= gen_reg_rtx (DImode
);
3024 rtx temp2
= gen_reg_rtx (DImode
);
3025 rtx seq
= ((mode
== QImode
3026 ? gen_unaligned_loadqi
3027 : gen_unaligned_loadhi
)
3028 (operands
[0], get_unaligned_address (operands
[1], 0),
3031 alpha_set_memflags (seq
, operands
[1]);
3037 if (GET_CODE (operands
[0]) == MEM
3038 || (GET_CODE (operands
[0]) == SUBREG
3039 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3040 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3041 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3042 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3043 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3044 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3046 if (aligned_memory_operand (operands
[0], mode
))
3048 rtx aligned_mem
, bitnum
;
3049 rtx temp1
= gen_reg_rtx (SImode
);
3050 rtx temp2
= gen_reg_rtx (SImode
);
3052 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3054 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3059 rtx temp1
= gen_reg_rtx (DImode
);
3060 rtx temp2
= gen_reg_rtx (DImode
);
3061 rtx temp3
= gen_reg_rtx (DImode
);
3062 rtx seq
= ((mode
== QImode
3063 ? gen_unaligned_storeqi
3064 : gen_unaligned_storehi
)
3065 (get_unaligned_address (operands
[0], 0),
3066 operands
[1], temp1
, temp2
, temp3
));
3068 alpha_set_memflags (seq
, operands
[0]);
3077 /* Generate an unsigned DImode to FP conversion. This is the same code
3078 optabs would emit if we didn't have TFmode patterns.
3080 For SFmode, this is the only construction I've found that can pass
3081 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3082 intermediates will work, because you'll get intermediate rounding
3083 that ruins the end result. Some of this could be fixed by turning
3084 on round-to-positive-infinity, but that requires diddling the fpsr,
3085 which kills performance. I tried turning this around and converting
3086 to a negative number, so that I could turn on /m, but either I did
3087 it wrong or there's something else cause I wound up with the exact
3088 same single-bit error. There is a branch-less form of this same code:
3099 fcmoveq $f10,$f11,$f0
3101 I'm not using it because it's the same number of instructions as
3102 this branch-full form, and it has more serialized long latency
3103 instructions on the critical path.
3105 For DFmode, we can avoid rounding errors by breaking up the word
3106 into two pieces, converting them separately, and adding them back:
3108 LC0: .long 0,0x5f800000
3113 cpyse $f11,$f31,$f10
3114 cpyse $f31,$f11,$f11
3122 This doesn't seem to be a clear-cut win over the optabs form.
3123 It probably all depends on the distribution of numbers being
3124 converted -- in the optabs form, all but high-bit-set has a
3125 much lower minimum execution time. */
3128 alpha_emit_floatuns (operands
)
3131 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3132 enum machine_mode mode
;
3135 in
= force_reg (DImode
, operands
[1]);
3136 mode
= GET_MODE (out
);
3137 neglab
= gen_label_rtx ();
3138 donelab
= gen_label_rtx ();
3139 i0
= gen_reg_rtx (DImode
);
3140 i1
= gen_reg_rtx (DImode
);
3141 f0
= gen_reg_rtx (mode
);
3143 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3145 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3146 emit_jump_insn (gen_jump (donelab
));
3149 emit_label (neglab
);
3151 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3152 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3153 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3154 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3155 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3157 emit_label (donelab
);
3160 /* Generate the comparison for a conditional branch. */
3163 alpha_emit_conditional_branch (code
)
3166 enum rtx_code cmp_code
, branch_code
;
3167 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3168 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3171 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3173 if (! TARGET_HAS_XFLOATING_LIBS
)
3176 /* X_floating library comparison functions return
3180 Convert the compare against the raw return value. */
3202 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3204 alpha_compare
.fp_p
= 0;
3207 /* The general case: fold the comparison code to the types of compares
3208 that we have, choosing the branch as necessary. */
3211 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3213 /* We have these compares: */
3214 cmp_code
= code
, branch_code
= NE
;
3219 /* These must be reversed. */
3220 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3223 case GE
: case GT
: case GEU
: case GTU
:
3224 /* For FP, we swap them, for INT, we reverse them. */
3225 if (alpha_compare
.fp_p
)
3227 cmp_code
= swap_condition (code
);
3229 tem
= op0
, op0
= op1
, op1
= tem
;
3233 cmp_code
= reverse_condition (code
);
3242 if (alpha_compare
.fp_p
)
3245 if (flag_unsafe_math_optimizations
)
3247 /* When we are not as concerned about non-finite values, and we
3248 are comparing against zero, we can branch directly. */
3249 if (op1
== CONST0_RTX (DFmode
))
3250 cmp_code
= NIL
, branch_code
= code
;
3251 else if (op0
== CONST0_RTX (DFmode
))
3253 /* Undo the swap we probably did just above. */
3254 tem
= op0
, op0
= op1
, op1
= tem
;
3255 branch_code
= swap_condition (cmp_code
);
3261 /* ??? We mark the the branch mode to be CCmode to prevent the
3262 compare and branch from being combined, since the compare
3263 insn follows IEEE rules that the branch does not. */
3264 branch_mode
= CCmode
;
3271 /* The following optimizations are only for signed compares. */
3272 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3274 /* Whee. Compare and branch against 0 directly. */
3275 if (op1
== const0_rtx
)
3276 cmp_code
= NIL
, branch_code
= code
;
3278 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3279 bypass between logicals and br/cmov on EV5. But we don't want to
3280 force valid immediate constants into registers needlessly. */
3281 else if (GET_CODE (op1
) == CONST_INT
)
3283 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3285 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3286 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3287 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3289 cmp_code
= PLUS
, branch_code
= code
;
3295 if (!reg_or_0_operand (op0
, DImode
))
3296 op0
= force_reg (DImode
, op0
);
3297 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3298 op1
= force_reg (DImode
, op1
);
3301 /* Emit an initial compare instruction, if necessary. */
3303 if (cmp_code
!= NIL
)
3305 tem
= gen_reg_rtx (cmp_mode
);
3306 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3309 /* Zero the operands. */
3310 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3312 /* Return the branch comparison. */
3313 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3316 /* Certain simplifications can be done to make invalid setcc operations
3317 valid. Return the final comparison, or NULL if we can't work. */
3320 alpha_emit_setcc (code
)
3323 enum rtx_code cmp_code
;
3324 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3325 int fp_p
= alpha_compare
.fp_p
;
3328 /* Zero the operands. */
3329 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3331 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3333 if (! TARGET_HAS_XFLOATING_LIBS
)
3336 /* X_floating library comparison functions return
3340 Convert the compare against the raw return value. */
3342 if (code
== UNORDERED
|| code
== ORDERED
)
3347 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3351 if (code
== UNORDERED
)
3353 else if (code
== ORDERED
)
3359 if (fp_p
&& !TARGET_FIX
)
3362 /* The general case: fold the comparison code to the types of compares
3363 that we have, choosing the branch as necessary. */
3368 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3370 /* We have these compares. */
3372 cmp_code
= code
, code
= NE
;
3376 if (!fp_p
&& op1
== const0_rtx
)
3381 cmp_code
= reverse_condition (code
);
3385 case GE
: case GT
: case GEU
: case GTU
:
3386 /* These normally need swapping, but for integer zero we have
3387 special patterns that recognize swapped operands. */
3388 if (!fp_p
&& op1
== const0_rtx
)
3390 code
= swap_condition (code
);
3392 cmp_code
= code
, code
= NE
;
3393 tmp
= op0
, op0
= op1
, op1
= tmp
;
3402 if (!register_operand (op0
, DImode
))
3403 op0
= force_reg (DImode
, op0
);
3404 if (!reg_or_8bit_operand (op1
, DImode
))
3405 op1
= force_reg (DImode
, op1
);
3408 /* Emit an initial compare instruction, if necessary. */
3409 if (cmp_code
!= NIL
)
3411 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3413 tmp
= gen_reg_rtx (mode
);
3414 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3415 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3417 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3421 /* Return the setcc comparison. */
3422 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3426 /* Rewrite a comparison against zero CMP of the form
3427 (CODE (cc0) (const_int 0)) so it can be written validly in
3428 a conditional move (if_then_else CMP ...).
3429 If both of the operands that set cc0 are non-zero we must emit
3430 an insn to perform the compare (it can't be done within
3431 the conditional move). */
3433 alpha_emit_conditional_move (cmp
, mode
)
3435 enum machine_mode mode
;
3437 enum rtx_code code
= GET_CODE (cmp
);
3438 enum rtx_code cmov_code
= NE
;
3439 rtx op0
= alpha_compare
.op0
;
3440 rtx op1
= alpha_compare
.op1
;
3441 int fp_p
= alpha_compare
.fp_p
;
3442 enum machine_mode cmp_mode
3443 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3444 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3445 enum machine_mode cmov_mode
= VOIDmode
;
3446 int local_fast_math
= flag_unsafe_math_optimizations
;
3449 /* Zero the operands. */
3450 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3452 if (fp_p
!= FLOAT_MODE_P (mode
))
3454 enum rtx_code cmp_code
;
3459 /* If we have fp<->int register move instructions, do a cmov by
3460 performing the comparison in fp registers, and move the
3461 zero/non-zero value to integer registers, where we can then
3462 use a normal cmov, or vice-versa. */
3466 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3467 /* We have these compares. */
3468 cmp_code
= code
, code
= NE
;
3472 /* This must be reversed. */
3473 cmp_code
= EQ
, code
= EQ
;
3476 case GE
: case GT
: case GEU
: case GTU
:
3477 /* These normally need swapping, but for integer zero we have
3478 special patterns that recognize swapped operands. */
3479 if (!fp_p
&& op1
== const0_rtx
)
3480 cmp_code
= code
, code
= NE
;
3483 cmp_code
= swap_condition (code
);
3485 tem
= op0
, op0
= op1
, op1
= tem
;
3493 tem
= gen_reg_rtx (cmp_op_mode
);
3494 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3495 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3498 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3499 op0
= gen_lowpart (cmp_op_mode
, tem
);
3500 op1
= CONST0_RTX (cmp_op_mode
);
3502 local_fast_math
= 1;
3505 /* We may be able to use a conditional move directly.
3506 This avoids emitting spurious compares. */
3507 if (signed_comparison_operator (cmp
, VOIDmode
)
3508 && (!fp_p
|| local_fast_math
)
3509 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3510 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3512 /* We can't put the comparison inside the conditional move;
3513 emit a compare instruction and put that inside the
3514 conditional move. Make sure we emit only comparisons we have;
3515 swap or reverse as necessary. */
3522 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3523 /* We have these compares: */
3527 /* This must be reversed. */
3528 code
= reverse_condition (code
);
3532 case GE
: case GT
: case GEU
: case GTU
:
3533 /* These must be swapped. */
3534 if (op1
!= CONST0_RTX (cmp_mode
))
3536 code
= swap_condition (code
);
3537 tem
= op0
, op0
= op1
, op1
= tem
;
3547 if (!reg_or_0_operand (op0
, DImode
))
3548 op0
= force_reg (DImode
, op0
);
3549 if (!reg_or_8bit_operand (op1
, DImode
))
3550 op1
= force_reg (DImode
, op1
);
3553 /* ??? We mark the branch mode to be CCmode to prevent the compare
3554 and cmov from being combined, since the compare insn follows IEEE
3555 rules that the cmov does not. */
3556 if (fp_p
&& !local_fast_math
)
3559 tem
= gen_reg_rtx (cmp_op_mode
);
3560 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3561 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3564 /* Simplify a conditional move of two constants into a setcc with
3565 arithmetic. This is done with a splitter since combine would
3566 just undo the work if done during code generation. It also catches
3567 cases we wouldn't have before cse. */
3570 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3572 rtx dest
, cond
, t_rtx
, f_rtx
;
3574 HOST_WIDE_INT t
, f
, diff
;
3575 enum machine_mode mode
;
3576 rtx target
, subtarget
, tmp
;
3578 mode
= GET_MODE (dest
);
3583 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3584 || (code
== GE
|| code
== GT
))
3586 code
= reverse_condition (code
);
3587 diff
= t
, t
= f
, f
= diff
;
3591 subtarget
= target
= dest
;
3594 target
= gen_lowpart (DImode
, dest
);
3595 if (! no_new_pseudos
)
3596 subtarget
= gen_reg_rtx (DImode
);
3600 /* Below, we must be careful to use copy_rtx on target and subtarget
3601 in intermediate insns, as they may be a subreg rtx, which may not
3604 if (f
== 0 && exact_log2 (diff
) > 0
3605 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3606 viable over a longer latency cmove. On EV5, the E0 slot is a
3607 scarce resource, and on EV4 shift has the same latency as a cmove. */
3608 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3610 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3611 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3613 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3614 GEN_INT (exact_log2 (t
)));
3615 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3617 else if (f
== 0 && t
== -1)
3619 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3620 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3622 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3624 else if (diff
== 1 || diff
== 4 || diff
== 8)
3628 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3629 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3632 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3635 add_op
= GEN_INT (f
);
3636 if (sext_add_operand (add_op
, mode
))
3638 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3640 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3641 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3653 /* Look up the function X_floating library function name for the
3657 alpha_lookup_xfloating_lib_func (code
)
3662 const enum rtx_code code
;
3663 const char *const func
;
3666 static const struct xfloating_op vms_xfloating_ops
[] =
3668 { PLUS
, "OTS$ADD_X" },
3669 { MINUS
, "OTS$SUB_X" },
3670 { MULT
, "OTS$MUL_X" },
3671 { DIV
, "OTS$DIV_X" },
3672 { EQ
, "OTS$EQL_X" },
3673 { NE
, "OTS$NEQ_X" },
3674 { LT
, "OTS$LSS_X" },
3675 { LE
, "OTS$LEQ_X" },
3676 { GT
, "OTS$GTR_X" },
3677 { GE
, "OTS$GEQ_X" },
3678 { FIX
, "OTS$CVTXQ" },
3679 { FLOAT
, "OTS$CVTQX" },
3680 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3681 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3682 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3685 static const struct xfloating_op osf_xfloating_ops
[] =
3687 { PLUS
, "_OtsAddX" },
3688 { MINUS
, "_OtsSubX" },
3689 { MULT
, "_OtsMulX" },
3690 { DIV
, "_OtsDivX" },
3697 { FIX
, "_OtsCvtXQ" },
3698 { FLOAT
, "_OtsCvtQX" },
3699 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3700 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3701 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3704 const struct xfloating_op
*ops
;
3705 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3708 /* How irritating. Nothing to key off for the table. Hardcode
3709 knowledge of the G_floating routines. */
3710 if (TARGET_FLOAT_VAX
)
3712 if (TARGET_ABI_OPEN_VMS
)
3714 if (code
== FLOAT_EXTEND
)
3715 return "OTS$CVT_FLOAT_G_X";
3716 if (code
== FLOAT_TRUNCATE
)
3717 return "OTS$CVT_FLOAT_X_G";
3721 if (code
== FLOAT_EXTEND
)
3722 return "_OtsConvertFloatGX";
3723 if (code
== FLOAT_TRUNCATE
)
3724 return "_OtsConvertFloatXG";
3728 if (TARGET_ABI_OPEN_VMS
)
3729 ops
= vms_xfloating_ops
;
3731 ops
= osf_xfloating_ops
;
3733 for (i
= 0; i
< n
; ++i
)
3734 if (ops
[i
].code
== code
)
3740 /* Most X_floating operations take the rounding mode as an argument.
3741 Compute that here. */
3744 alpha_compute_xfloating_mode_arg (code
, round
)
3746 enum alpha_fp_rounding_mode round
;
3752 case ALPHA_FPRM_NORM
:
3755 case ALPHA_FPRM_MINF
:
3758 case ALPHA_FPRM_CHOP
:
3761 case ALPHA_FPRM_DYN
:
3767 /* XXX For reference, round to +inf is mode = 3. */
3770 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3776 /* Emit an X_floating library function call.
3778 Note that these functions do not follow normal calling conventions:
3779 TFmode arguments are passed in two integer registers (as opposed to
3780 indirect); TFmode return values appear in R16+R17.
3782 FUNC is the function name to call.
3783 TARGET is where the output belongs.
3784 OPERANDS are the inputs.
3785 NOPERANDS is the count of inputs.
3786 EQUIV is the expression equivalent for the function.
3790 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3797 rtx usage
= NULL_RTX
, tmp
, reg
;
3802 for (i
= 0; i
< noperands
; ++i
)
3804 switch (GET_MODE (operands
[i
]))
3807 reg
= gen_rtx_REG (TFmode
, regno
);
3812 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3817 if (GET_CODE (operands
[i
]) != CONST_INT
)
3821 reg
= gen_rtx_REG (DImode
, regno
);
3829 emit_move_insn (reg
, operands
[i
]);
3830 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3833 switch (GET_MODE (target
))
3836 reg
= gen_rtx_REG (TFmode
, 16);
3839 reg
= gen_rtx_REG (DFmode
, 32);
3842 reg
= gen_rtx_REG (DImode
, 0);
3848 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3849 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3850 const0_rtx
, const0_rtx
));
3851 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3856 emit_libcall_block (tmp
, target
, reg
, equiv
);
3859 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3862 alpha_emit_xfloating_arith (code
, operands
)
3868 rtx out_operands
[3];
3870 func
= alpha_lookup_xfloating_lib_func (code
);
3871 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3873 out_operands
[0] = operands
[1];
3874 out_operands
[1] = operands
[2];
3875 out_operands
[2] = GEN_INT (mode
);
3876 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3877 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3881 /* Emit an X_floating library function call for a comparison. */
3884 alpha_emit_xfloating_compare (code
, op0
, op1
)
3889 rtx out
, operands
[2];
3891 func
= alpha_lookup_xfloating_lib_func (code
);
3895 out
= gen_reg_rtx (DImode
);
3897 /* ??? Strange mode for equiv because what's actually returned
3898 is -1,0,1, not a proper boolean value. */
3899 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3900 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3905 /* Emit an X_floating library function call for a conversion. */
3908 alpha_emit_xfloating_cvt (code
, operands
)
3912 int noperands
= 1, mode
;
3913 rtx out_operands
[2];
3916 func
= alpha_lookup_xfloating_lib_func (code
);
3918 out_operands
[0] = operands
[1];
3923 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3924 out_operands
[1] = GEN_INT (mode
);
3927 case FLOAT_TRUNCATE
:
3928 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3929 out_operands
[1] = GEN_INT (mode
);
3936 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3937 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3941 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3942 OP[0] into OP[0,1]. Naturally, output operand ordering is
3946 alpha_split_tfmode_pair (operands
)
3949 if (GET_CODE (operands
[1]) == REG
)
3951 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3952 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3954 else if (GET_CODE (operands
[1]) == MEM
)
3956 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3957 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3959 else if (operands
[1] == CONST0_RTX (TFmode
))
3960 operands
[2] = operands
[3] = const0_rtx
;
3964 if (GET_CODE (operands
[0]) == REG
)
3966 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3967 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3969 else if (GET_CODE (operands
[0]) == MEM
)
3971 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3972 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3978 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3979 op2 is a register containing the sign bit, operation is the
3980 logical operation to be performed. */
3983 alpha_split_tfmode_frobsign (operands
, operation
)
3985 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
3987 rtx high_bit
= operands
[2];
3991 alpha_split_tfmode_pair (operands
);
3993 /* Detect three flavours of operand overlap. */
3995 if (rtx_equal_p (operands
[0], operands
[2]))
3997 else if (rtx_equal_p (operands
[1], operands
[2]))
3999 if (rtx_equal_p (operands
[0], high_bit
))
4006 emit_move_insn (operands
[0], operands
[2]);
4008 /* ??? If the destination overlaps both source tf and high_bit, then
4009 assume source tf is dead in its entirety and use the other half
4010 for a scratch register. Otherwise "scratch" is just the proper
4011 destination register. */
4012 scratch
= operands
[move
< 2 ? 1 : 3];
4014 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4018 emit_move_insn (operands
[0], operands
[2]);
4020 emit_move_insn (operands
[1], scratch
);
4024 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4028 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4029 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4030 lda r3,X(r11) lda r3,X+2(r11)
4031 extwl r1,r3,r1 extql r1,r3,r1
4032 extwh r2,r3,r2 extqh r2,r3,r2
4033 or r1.r2.r1 or r1,r2,r1
4036 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4037 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4038 lda r3,X(r11) lda r3,X(r11)
4039 extll r1,r3,r1 extll r1,r3,r1
4040 extlh r2,r3,r2 extlh r2,r3,r2
4041 or r1.r2.r1 addl r1,r2,r1
4043 quad: ldq_u r1,X(r11)
4052 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4054 HOST_WIDE_INT size
, ofs
;
4057 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4058 enum machine_mode mode
;
4060 meml
= gen_reg_rtx (DImode
);
4061 memh
= gen_reg_rtx (DImode
);
4062 addr
= gen_reg_rtx (DImode
);
4063 extl
= gen_reg_rtx (DImode
);
4064 exth
= gen_reg_rtx (DImode
);
4066 mema
= XEXP (mem
, 0);
4067 if (GET_CODE (mema
) == LO_SUM
)
4068 mema
= force_reg (Pmode
, mema
);
4070 /* AND addresses cannot be in any alias set, since they may implicitly
4071 alias surrounding code. Ideally we'd have some alias set that
4072 covered all types except those with alignment 8 or higher. */
4074 tmp
= change_address (mem
, DImode
,
4075 gen_rtx_AND (DImode
,
4076 plus_constant (mema
, ofs
),
4078 set_mem_alias_set (tmp
, 0);
4079 emit_move_insn (meml
, tmp
);
4081 tmp
= change_address (mem
, DImode
,
4082 gen_rtx_AND (DImode
,
4083 plus_constant (mema
, ofs
+ size
- 1),
4085 set_mem_alias_set (tmp
, 0);
4086 emit_move_insn (memh
, tmp
);
4088 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4090 emit_move_insn (addr
, plus_constant (mema
, -1));
4092 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4093 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4095 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4096 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4097 addr
, 1, OPTAB_WIDEN
);
4099 else if (sign
&& size
== 2)
4101 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4103 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4104 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4106 /* We must use tgt here for the target. Alpha-vms port fails if we use
4107 addr for the target, because addr is marked as a pointer and combine
4108 knows that pointers are always sign-extended 32 bit values. */
4109 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4110 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4111 addr
, 1, OPTAB_WIDEN
);
4115 if (WORDS_BIG_ENDIAN
)
4117 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4121 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4126 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4131 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4138 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4142 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4143 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4147 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4152 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4157 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4166 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4167 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4172 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4175 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4178 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4180 HOST_WIDE_INT size
, ofs
;
4182 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4184 dstl
= gen_reg_rtx (DImode
);
4185 dsth
= gen_reg_rtx (DImode
);
4186 insl
= gen_reg_rtx (DImode
);
4187 insh
= gen_reg_rtx (DImode
);
4189 dsta
= XEXP (dst
, 0);
4190 if (GET_CODE (dsta
) == LO_SUM
)
4191 dsta
= force_reg (Pmode
, dsta
);
4193 /* AND addresses cannot be in any alias set, since they may implicitly
4194 alias surrounding code. Ideally we'd have some alias set that
4195 covered all types except those with alignment 8 or higher. */
4197 meml
= change_address (dst
, DImode
,
4198 gen_rtx_AND (DImode
,
4199 plus_constant (dsta
, ofs
),
4201 set_mem_alias_set (meml
, 0);
4203 memh
= change_address (dst
, DImode
,
4204 gen_rtx_AND (DImode
,
4205 plus_constant (dsta
, ofs
+ size
- 1),
4207 set_mem_alias_set (memh
, 0);
4209 emit_move_insn (dsth
, memh
);
4210 emit_move_insn (dstl
, meml
);
4211 if (WORDS_BIG_ENDIAN
)
4213 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4215 if (src
!= const0_rtx
)
4220 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4223 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4226 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4229 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4230 GEN_INT (size
*8), addr
));
4236 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4239 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffffffff), addr
));
4243 #if HOST_BITS_PER_WIDE_INT == 32
4244 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4246 rtx msk
= constm1_rtx
;
4248 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4253 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4257 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4259 if (src
!= const0_rtx
)
4261 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4262 GEN_INT (size
*8), addr
));
4267 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4270 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4273 emit_insn (gen_insql_le (insl
, src
, addr
));
4278 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4283 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4286 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffffffff), addr
));
4290 #if HOST_BITS_PER_WIDE_INT == 32
4291 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4293 rtx msk
= constm1_rtx
;
4295 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4301 if (src
!= const0_rtx
)
4303 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4304 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4307 if (WORDS_BIG_ENDIAN
)
4309 emit_move_insn (meml
, dstl
);
4310 emit_move_insn (memh
, dsth
);
4314 /* Must store high before low for degenerate case of aligned. */
4315 emit_move_insn (memh
, dsth
);
4316 emit_move_insn (meml
, dstl
);
4320 /* The block move code tries to maximize speed by separating loads and
4321 stores at the expense of register pressure: we load all of the data
4322 before we store it back out. There are two secondary effects worth
4323 mentioning, that this speeds copying to/from aligned and unaligned
4324 buffers, and that it makes the code significantly easier to write. */
4326 #define MAX_MOVE_WORDS 8
4328 /* Load an integral number of consecutive unaligned quadwords. */
4331 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4334 HOST_WIDE_INT words
, ofs
;
4336 rtx
const im8
= GEN_INT (-8);
4337 rtx
const i64
= GEN_INT (64);
4338 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4339 rtx sreg
, areg
, tmp
, smema
;
4342 smema
= XEXP (smem
, 0);
4343 if (GET_CODE (smema
) == LO_SUM
)
4344 smema
= force_reg (Pmode
, smema
);
4346 /* Generate all the tmp registers we need. */
4347 for (i
= 0; i
< words
; ++i
)
4349 data_regs
[i
] = out_regs
[i
];
4350 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4352 data_regs
[words
] = gen_reg_rtx (DImode
);
4355 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4357 /* Load up all of the source data. */
4358 for (i
= 0; i
< words
; ++i
)
4360 tmp
= change_address (smem
, DImode
,
4361 gen_rtx_AND (DImode
,
4362 plus_constant (smema
, 8*i
),
4364 set_mem_alias_set (tmp
, 0);
4365 emit_move_insn (data_regs
[i
], tmp
);
4368 tmp
= change_address (smem
, DImode
,
4369 gen_rtx_AND (DImode
,
4370 plus_constant (smema
, 8*words
- 1),
4372 set_mem_alias_set (tmp
, 0);
4373 emit_move_insn (data_regs
[words
], tmp
);
4375 /* Extract the half-word fragments. Unfortunately DEC decided to make
4376 extxh with offset zero a noop instead of zeroing the register, so
4377 we must take care of that edge condition ourselves with cmov. */
4379 sreg
= copy_addr_to_reg (smema
);
4380 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4382 if (WORDS_BIG_ENDIAN
)
4383 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4384 for (i
= 0; i
< words
; ++i
)
4386 if (WORDS_BIG_ENDIAN
)
4388 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4389 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4393 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4394 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4396 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4397 gen_rtx_IF_THEN_ELSE (DImode
,
4398 gen_rtx_EQ (DImode
, areg
,
4400 const0_rtx
, ext_tmps
[i
])));
4403 /* Merge the half-words into whole words. */
4404 for (i
= 0; i
< words
; ++i
)
4406 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4407 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4411 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4412 may be NULL to store zeros. */
4415 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4418 HOST_WIDE_INT words
, ofs
;
4420 rtx
const im8
= GEN_INT (-8);
4421 rtx
const i64
= GEN_INT (64);
4422 #if HOST_BITS_PER_WIDE_INT == 32
4423 rtx
const im1
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4425 rtx
const im1
= constm1_rtx
;
4427 rtx ins_tmps
[MAX_MOVE_WORDS
];
4428 rtx st_tmp_1
, st_tmp_2
, dreg
;
4429 rtx st_addr_1
, st_addr_2
, dmema
;
4432 dmema
= XEXP (dmem
, 0);
4433 if (GET_CODE (dmema
) == LO_SUM
)
4434 dmema
= force_reg (Pmode
, dmema
);
4436 /* Generate all the tmp registers we need. */
4437 if (data_regs
!= NULL
)
4438 for (i
= 0; i
< words
; ++i
)
4439 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4440 st_tmp_1
= gen_reg_rtx(DImode
);
4441 st_tmp_2
= gen_reg_rtx(DImode
);
4444 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4446 st_addr_2
= change_address (dmem
, DImode
,
4447 gen_rtx_AND (DImode
,
4448 plus_constant (dmema
, words
*8 - 1),
4450 set_mem_alias_set (st_addr_2
, 0);
4452 st_addr_1
= change_address (dmem
, DImode
,
4453 gen_rtx_AND (DImode
, dmema
, im8
));
4454 set_mem_alias_set (st_addr_1
, 0);
4456 /* Load up the destination end bits. */
4457 emit_move_insn (st_tmp_2
, st_addr_2
);
4458 emit_move_insn (st_tmp_1
, st_addr_1
);
4460 /* Shift the input data into place. */
4461 dreg
= copy_addr_to_reg (dmema
);
4462 if (WORDS_BIG_ENDIAN
)
4463 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4464 if (data_regs
!= NULL
)
4466 for (i
= words
-1; i
>= 0; --i
)
4468 if (WORDS_BIG_ENDIAN
)
4470 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4471 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4475 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4476 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4479 for (i
= words
-1; i
> 0; --i
)
4481 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4482 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4487 /* Split and merge the ends with the destination data. */
4488 if (WORDS_BIG_ENDIAN
)
4490 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, im1
, dreg
));
4491 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4495 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4496 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, im1
, dreg
));
4499 if (data_regs
!= NULL
)
4501 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4502 st_tmp_2
, 1, OPTAB_WIDEN
);
4503 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4504 st_tmp_1
, 1, OPTAB_WIDEN
);
4508 if (WORDS_BIG_ENDIAN
)
4509 emit_move_insn (st_addr_1
, st_tmp_1
);
4511 emit_move_insn (st_addr_2
, st_tmp_2
);
4512 for (i
= words
-1; i
> 0; --i
)
4514 rtx tmp
= change_address (dmem
, DImode
,
4515 gen_rtx_AND (DImode
,
4516 plus_constant(dmema
,
4517 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4519 set_mem_alias_set (tmp
, 0);
4520 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4522 if (WORDS_BIG_ENDIAN
)
4523 emit_move_insn (st_addr_2
, st_tmp_2
);
4525 emit_move_insn (st_addr_1
, st_tmp_1
);
4529 /* Expand string/block move operations.
4531 operands[0] is the pointer to the destination.
4532 operands[1] is the pointer to the source.
4533 operands[2] is the number of bytes to move.
4534 operands[3] is the alignment. */
4537 alpha_expand_block_move (operands
)
4540 rtx bytes_rtx
= operands
[2];
4541 rtx align_rtx
= operands
[3];
4542 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4543 HOST_WIDE_INT bytes
= orig_bytes
;
4544 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4545 HOST_WIDE_INT dst_align
= src_align
;
4546 rtx orig_src
= operands
[1];
4547 rtx orig_dst
= operands
[0];
4548 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4550 unsigned int i
, words
, ofs
, nregs
= 0;
4552 if (orig_bytes
<= 0)
4554 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4557 /* Look for additional alignment information from recorded register info. */
4559 tmp
= XEXP (orig_src
, 0);
4560 if (GET_CODE (tmp
) == REG
)
4561 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4562 else if (GET_CODE (tmp
) == PLUS
4563 && GET_CODE (XEXP (tmp
, 0)) == REG
4564 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4566 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4567 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4571 if (a
>= 64 && c
% 8 == 0)
4573 else if (a
>= 32 && c
% 4 == 0)
4575 else if (a
>= 16 && c
% 2 == 0)
4580 tmp
= XEXP (orig_dst
, 0);
4581 if (GET_CODE (tmp
) == REG
)
4582 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4583 else if (GET_CODE (tmp
) == PLUS
4584 && GET_CODE (XEXP (tmp
, 0)) == REG
4585 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4587 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4588 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4592 if (a
>= 64 && c
% 8 == 0)
4594 else if (a
>= 32 && c
% 4 == 0)
4596 else if (a
>= 16 && c
% 2 == 0)
4601 /* Load the entire block into registers. */
4602 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4604 enum machine_mode mode
;
4606 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4608 /* Don't use the existing register if we're reading more than
4609 is held in the register. Nor if there is not a mode that
4610 handles the exact size. */
4611 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4613 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4617 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4618 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4622 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4627 /* No appropriate mode; fall back on memory. */
4628 orig_src
= replace_equiv_address (orig_src
,
4629 copy_addr_to_reg (XEXP (orig_src
, 0)));
4630 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4634 if (src_align
>= 64 && bytes
>= 8)
4638 for (i
= 0; i
< words
; ++i
)
4639 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4641 for (i
= 0; i
< words
; ++i
)
4642 emit_move_insn (data_regs
[nregs
+ i
],
4643 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4650 if (src_align
>= 32 && bytes
>= 4)
4654 for (i
= 0; i
< words
; ++i
)
4655 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4657 for (i
= 0; i
< words
; ++i
)
4658 emit_move_insn (data_regs
[nregs
+ i
],
4659 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4670 for (i
= 0; i
< words
+1; ++i
)
4671 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4673 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4681 if (! TARGET_BWX
&& bytes
>= 4)
4683 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4684 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4691 if (src_align
>= 16)
4694 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4695 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4698 } while (bytes
>= 2);
4700 else if (! TARGET_BWX
)
4702 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4703 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4711 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4712 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4719 if (nregs
> ARRAY_SIZE (data_regs
))
4722 /* Now save it back out again. */
4726 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4728 enum machine_mode mode
;
4729 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4731 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4732 if (GET_MODE (tmp
) == mode
)
4736 emit_move_insn (tmp
, data_regs
[0]);
4741 else if (nregs
== 2 && mode
== TImode
)
4743 /* Undo the subregging done above when copying between
4744 two TImode registers. */
4745 if (GET_CODE (data_regs
[0]) == SUBREG
4746 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4747 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4753 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4754 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4758 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4759 data_regs
[1], NULL_RTX
);
4767 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4768 /* ??? Optimize mode < dst_mode with strict_low_part. */
4770 /* No appropriate mode; fall back on memory. We can speed things
4771 up by recognizing extra alignment information. */
4772 orig_dst
= replace_equiv_address (orig_dst
,
4773 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4774 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4777 /* Write out the data in whatever chunks reading the source allowed. */
4778 if (dst_align
>= 64)
4780 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4782 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4789 if (dst_align
>= 32)
4791 /* If the source has remaining DImode regs, write them out in
4793 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4795 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4796 NULL_RTX
, 1, OPTAB_WIDEN
);
4798 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4799 gen_lowpart (SImode
, data_regs
[i
]));
4800 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4801 gen_lowpart (SImode
, tmp
));
4806 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4808 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4815 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4817 /* Write out a remaining block of words using unaligned methods. */
4819 for (words
= 1; i
+ words
< nregs
; words
++)
4820 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4824 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4826 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4833 /* Due to the above, this won't be aligned. */
4834 /* ??? If we have more than one of these, consider constructing full
4835 words in registers and using alpha_expand_unaligned_store_words. */
4836 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4838 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4843 if (dst_align
>= 16)
4844 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4846 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4851 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4853 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4858 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4860 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4874 alpha_expand_block_clear (operands
)
4877 rtx bytes_rtx
= operands
[1];
4878 rtx align_rtx
= operands
[2];
4879 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4880 HOST_WIDE_INT bytes
= orig_bytes
;
4881 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4882 HOST_WIDE_INT alignofs
= 0;
4883 rtx orig_dst
= operands
[0];
4885 int i
, words
, ofs
= 0;
4887 if (orig_bytes
<= 0)
4889 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4892 /* Look for stricter alignment. */
4893 tmp
= XEXP (orig_dst
, 0);
4894 if (GET_CODE (tmp
) == REG
)
4895 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4896 else if (GET_CODE (tmp
) == PLUS
4897 && GET_CODE (XEXP (tmp
, 0)) == REG
4898 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4900 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4901 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4906 align
= a
, alignofs
= 8 - c
% 8;
4908 align
= a
, alignofs
= 4 - c
% 4;
4910 align
= a
, alignofs
= 2 - c
% 2;
4913 else if (GET_CODE (tmp
) == ADDRESSOF
)
4915 enum machine_mode mode
;
4917 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4918 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4920 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4924 /* No appropriate mode; fall back on memory. */
4925 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4926 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4929 /* Handle an unaligned prefix first. */
4933 #if HOST_BITS_PER_WIDE_INT >= 64
4934 /* Given that alignofs is bounded by align, the only time BWX could
4935 generate three stores is for a 7 byte fill. Prefer two individual
4936 stores over a load/mask/store sequence. */
4937 if ((!TARGET_BWX
|| alignofs
== 7)
4939 && !(alignofs
== 4 && bytes
>= 4))
4941 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4942 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4946 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4947 set_mem_alias_set (mem
, 0);
4949 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4950 if (bytes
< alignofs
)
4952 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4963 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4964 NULL_RTX
, 1, OPTAB_WIDEN
);
4966 emit_move_insn (mem
, tmp
);
4970 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4972 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4977 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4979 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4984 if (alignofs
== 4 && bytes
>= 4)
4986 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4992 /* If we've not used the extra lead alignment information by now,
4993 we won't be able to. Downgrade align to match what's left over. */
4996 alignofs
= alignofs
& -alignofs
;
4997 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5001 /* Handle a block of contiguous long-words. */
5003 if (align
>= 64 && bytes
>= 8)
5007 for (i
= 0; i
< words
; ++i
)
5008 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5015 /* If the block is large and appropriately aligned, emit a single
5016 store followed by a sequence of stq_u insns. */
5018 if (align
>= 32 && bytes
> 16)
5022 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5026 orig_dsta
= XEXP (orig_dst
, 0);
5027 if (GET_CODE (orig_dsta
) == LO_SUM
)
5028 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5031 for (i
= 0; i
< words
; ++i
)
5034 = change_address (orig_dst
, DImode
,
5035 gen_rtx_AND (DImode
,
5036 plus_constant (orig_dsta
, ofs
+ i
*8),
5038 set_mem_alias_set (mem
, 0);
5039 emit_move_insn (mem
, const0_rtx
);
5042 /* Depending on the alignment, the first stq_u may have overlapped
5043 with the initial stl, which means that the last stq_u didn't
5044 write as much as it would appear. Leave those questionable bytes
5046 bytes
-= words
* 8 - 4;
5047 ofs
+= words
* 8 - 4;
5050 /* Handle a smaller block of aligned words. */
5052 if ((align
>= 64 && bytes
== 4)
5053 || (align
== 32 && bytes
>= 4))
5057 for (i
= 0; i
< words
; ++i
)
5058 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5065 /* An unaligned block uses stq_u stores for as many as possible. */
5071 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5077 /* Next clean up any trailing pieces. */
5079 #if HOST_BITS_PER_WIDE_INT >= 64
5080 /* Count the number of bits in BYTES for which aligned stores could
5083 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5087 /* If we have appropriate alignment (and it wouldn't take too many
5088 instructions otherwise), mask out the bytes we need. */
5089 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5096 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5097 set_mem_alias_set (mem
, 0);
5099 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5101 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5102 NULL_RTX
, 1, OPTAB_WIDEN
);
5104 emit_move_insn (mem
, tmp
);
5107 else if (align
>= 32 && bytes
< 4)
5112 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5113 set_mem_alias_set (mem
, 0);
5115 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5117 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5118 NULL_RTX
, 1, OPTAB_WIDEN
);
5120 emit_move_insn (mem
, tmp
);
5126 if (!TARGET_BWX
&& bytes
>= 4)
5128 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5138 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5142 } while (bytes
>= 2);
5144 else if (! TARGET_BWX
)
5146 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5154 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5162 /* Adjust the cost of a scheduling dependency. Return the new cost of
5163 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5166 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5172 enum attr_type insn_type
, dep_insn_type
;
5174 /* If the dependence is an anti-dependence, there is no cost. For an
5175 output dependence, there is sometimes a cost, but it doesn't seem
5176 worth handling those few cases. */
5177 if (REG_NOTE_KIND (link
) != 0)
5180 /* If we can't recognize the insns, we can't really do anything. */
5181 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5184 insn_type
= get_attr_type (insn
);
5185 dep_insn_type
= get_attr_type (dep_insn
);
5187 /* Bring in the user-defined memory latency. */
5188 if (dep_insn_type
== TYPE_ILD
5189 || dep_insn_type
== TYPE_FLD
5190 || dep_insn_type
== TYPE_LDSYM
)
5191 cost
+= alpha_memory_latency
-1;
5193 /* Everything else handled in DFA bypasses now. */
5198 /* The number of instructions that can be issued per cycle. */
5203 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5207 alpha_use_dfa_pipeline_interface ()
5212 /* How many alternative schedules to try. This should be as wide as the
5213 scheduling freedom in the DFA, but no wider. Making this value too
5214 large results extra work for the scheduler.
5216 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5217 alternative schedules. For EV5, we can choose between E0/E1 and
5218 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5221 alpha_multipass_dfa_lookahead ()
5223 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5226 /* Machine-specific function data. */
5228 struct machine_function
5230 #if TARGET_ABI_UNICOSMK
5231 /* List of call information words for calls from this function. */
5232 struct rtx_def
*first_ciw
;
5233 struct rtx_def
*last_ciw
;
5236 /* List of deferred case vectors. */
5237 struct rtx_def
*addr_list
;
5240 const char *some_ld_name
;
5242 /* Non-empty struct. */
5248 /* Register global variables and machine-specific functions with the
5249 garbage collector. */
5252 alpha_init_machine_status (p
)
5256 (struct machine_function
*) xcalloc (1, sizeof (struct machine_function
));
5258 #if TARGET_ABI_UNICOSMK
5259 p
->machine
->first_ciw
= NULL_RTX
;
5260 p
->machine
->last_ciw
= NULL_RTX
;
5261 p
->machine
->ciw_count
= 0;
5262 p
->machine
->addr_list
= NULL_RTX
;
5265 p
->machine
->some_ld_name
= NULL
;
5270 alpha_mark_machine_status (p
)
5273 struct machine_function
*machine
= p
->machine
;
5277 #if TARGET_ABI_UNICOSMK
5278 ggc_mark_rtx (machine
->first_ciw
);
5279 ggc_mark_rtx (machine
->addr_list
);
5285 alpha_free_machine_status (p
)
5292 /* Functions to save and restore alpha_return_addr_rtx. */
5294 /* Start the ball rolling with RETURN_ADDR_RTX. */
5297 alpha_return_addr (count
, frame
)
5299 rtx frame ATTRIBUTE_UNUSED
;
5304 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5307 /* Return or create a pseudo containing the gp value for the current
5308 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5311 alpha_gp_save_rtx ()
5313 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5314 if (GET_CODE (r
) != MEM
)
5315 r
= gen_mem_addressof (r
, NULL_TREE
);
5320 alpha_ra_ever_killed ()
5324 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5325 return regs_ever_live
[REG_RA
];
5327 push_topmost_sequence ();
5329 pop_topmost_sequence ();
5331 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5335 /* Return the trap mode suffix applicable to the current
5336 instruction, or NULL. */
5339 get_trap_mode_suffix ()
5341 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5345 case TRAP_SUFFIX_NONE
:
5348 case TRAP_SUFFIX_SU
:
5349 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5353 case TRAP_SUFFIX_SUI
:
5354 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5358 case TRAP_SUFFIX_V_SV
:
5366 case ALPHA_FPTM_SUI
:
5371 case TRAP_SUFFIX_V_SV_SVI
:
5380 case ALPHA_FPTM_SUI
:
5385 case TRAP_SUFFIX_U_SU_SUI
:
5394 case ALPHA_FPTM_SUI
:
5402 /* Return the rounding mode suffix applicable to the current
5403 instruction, or NULL. */
5406 get_round_mode_suffix ()
5408 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5412 case ROUND_SUFFIX_NONE
:
5414 case ROUND_SUFFIX_NORMAL
:
5417 case ALPHA_FPRM_NORM
:
5419 case ALPHA_FPRM_MINF
:
5421 case ALPHA_FPRM_CHOP
:
5423 case ALPHA_FPRM_DYN
:
5428 case ROUND_SUFFIX_C
:
5434 /* Locate some local-dynamic symbol still in use by this function
5435 so that we can print its name in some movdi_er_tlsldm pattern. */
5438 get_some_local_dynamic_name ()
5442 if (cfun
->machine
->some_ld_name
)
5443 return cfun
->machine
->some_ld_name
;
5445 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5447 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5448 return cfun
->machine
->some_ld_name
;
5454 get_some_local_dynamic_name_1 (px
, data
)
5456 void *data ATTRIBUTE_UNUSED
;
5460 if (GET_CODE (x
) == SYMBOL_REF
)
5462 const char *str
= XSTR (x
, 0);
5463 if (str
[0] == '@' && str
[1] == 'D')
5465 cfun
->machine
->some_ld_name
= str
;
5473 /* Print an operand. Recognize special options, documented below. */
5476 print_operand (file
, x
, code
)
5486 /* Print the assembler name of the current function. */
5487 assemble_name (file
, alpha_fnname
);
5491 assemble_name (file
, get_some_local_dynamic_name ());
5496 const char *trap
= get_trap_mode_suffix ();
5497 const char *round
= get_round_mode_suffix ();
5500 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5501 (trap
? trap
: ""), (round
? round
: ""));
5506 /* Generates single precision instruction suffix. */
5507 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5511 /* Generates double precision instruction suffix. */
5512 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5516 if (alpha_this_literal_sequence_number
== 0)
5517 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5518 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5522 if (alpha_this_gpdisp_sequence_number
== 0)
5523 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5524 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5528 if (GET_CODE (x
) == HIGH
)
5529 output_addr_const (file
, XEXP (x
, 0));
5531 output_operand_lossage ("invalid %%H value");
5538 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5540 x
= XVECEXP (x
, 0, 0);
5541 lituse
= "lituse_tlsgd";
5543 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5545 x
= XVECEXP (x
, 0, 0);
5546 lituse
= "lituse_tlsldm";
5548 else if (GET_CODE (x
) == CONST_INT
)
5549 lituse
= "lituse_jsr";
5552 output_operand_lossage ("invalid %%J value");
5556 if (x
!= const0_rtx
)
5557 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5562 /* If this operand is the constant zero, write it as "$31". */
5563 if (GET_CODE (x
) == REG
)
5564 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5565 else if (x
== CONST0_RTX (GET_MODE (x
)))
5566 fprintf (file
, "$31");
5568 output_operand_lossage ("invalid %%r value");
5572 /* Similar, but for floating-point. */
5573 if (GET_CODE (x
) == REG
)
5574 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5575 else if (x
== CONST0_RTX (GET_MODE (x
)))
5576 fprintf (file
, "$f31");
5578 output_operand_lossage ("invalid %%R value");
5582 /* Write the 1's complement of a constant. */
5583 if (GET_CODE (x
) != CONST_INT
)
5584 output_operand_lossage ("invalid %%N value");
5586 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5590 /* Write 1 << C, for a constant C. */
5591 if (GET_CODE (x
) != CONST_INT
)
5592 output_operand_lossage ("invalid %%P value");
5594 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5598 /* Write the high-order 16 bits of a constant, sign-extended. */
5599 if (GET_CODE (x
) != CONST_INT
)
5600 output_operand_lossage ("invalid %%h value");
5602 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5606 /* Write the low-order 16 bits of a constant, sign-extended. */
5607 if (GET_CODE (x
) != CONST_INT
)
5608 output_operand_lossage ("invalid %%L value");
5610 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5611 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5615 /* Write mask for ZAP insn. */
5616 if (GET_CODE (x
) == CONST_DOUBLE
)
5618 HOST_WIDE_INT mask
= 0;
5619 HOST_WIDE_INT value
;
5621 value
= CONST_DOUBLE_LOW (x
);
5622 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5627 value
= CONST_DOUBLE_HIGH (x
);
5628 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5631 mask
|= (1 << (i
+ sizeof (int)));
5633 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5636 else if (GET_CODE (x
) == CONST_INT
)
5638 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5640 for (i
= 0; i
< 8; i
++, value
>>= 8)
5644 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5647 output_operand_lossage ("invalid %%m value");
5651 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5652 if (GET_CODE (x
) != CONST_INT
5653 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5654 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5655 output_operand_lossage ("invalid %%M value");
5657 fprintf (file
, "%s",
5658 (INTVAL (x
) == 8 ? "b"
5659 : INTVAL (x
) == 16 ? "w"
5660 : INTVAL (x
) == 32 ? "l"
5665 /* Similar, except do it from the mask. */
5666 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xff)
5667 fprintf (file
, "b");
5668 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffff)
5669 fprintf (file
, "w");
5670 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffffffff)
5671 fprintf (file
, "l");
5672 #if HOST_BITS_PER_WIDE_INT == 32
5673 else if (GET_CODE (x
) == CONST_DOUBLE
5674 && CONST_DOUBLE_HIGH (x
) == 0
5675 && CONST_DOUBLE_LOW (x
) == -1)
5676 fprintf (file
, "l");
5677 else if (GET_CODE (x
) == CONST_DOUBLE
5678 && CONST_DOUBLE_HIGH (x
) == -1
5679 && CONST_DOUBLE_LOW (x
) == -1)
5680 fprintf (file
, "q");
5682 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == -1)
5683 fprintf (file
, "q");
5684 else if (GET_CODE (x
) == CONST_DOUBLE
5685 && CONST_DOUBLE_HIGH (x
) == 0
5686 && CONST_DOUBLE_LOW (x
) == -1)
5687 fprintf (file
, "q");
5690 output_operand_lossage ("invalid %%U value");
5694 /* Write the constant value divided by 8 for little-endian mode or
5695 (56 - value) / 8 for big-endian mode. */
5697 if (GET_CODE (x
) != CONST_INT
5698 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5701 || (INTVAL (x
) & 7) != 0)
5702 output_operand_lossage ("invalid %%s value");
5704 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5706 ? (56 - INTVAL (x
)) / 8
5711 /* Same, except compute (64 - c) / 8 */
5713 if (GET_CODE (x
) != CONST_INT
5714 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5715 && (INTVAL (x
) & 7) != 8)
5716 output_operand_lossage ("invalid %%s value");
5718 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5723 /* On Unicos/Mk systems: use a DEX expression if the symbol
5724 clashes with a register name. */
5725 int dex
= unicosmk_need_dex (x
);
5727 fprintf (file
, "DEX(%d)", dex
);
5729 output_addr_const (file
, x
);
5733 case 'C': case 'D': case 'c': case 'd':
5734 /* Write out comparison name. */
5736 enum rtx_code c
= GET_CODE (x
);
5738 if (GET_RTX_CLASS (c
) != '<')
5739 output_operand_lossage ("invalid %%C value");
5741 else if (code
== 'D')
5742 c
= reverse_condition (c
);
5743 else if (code
== 'c')
5744 c
= swap_condition (c
);
5745 else if (code
== 'd')
5746 c
= swap_condition (reverse_condition (c
));
5749 fprintf (file
, "ule");
5751 fprintf (file
, "ult");
5752 else if (c
== UNORDERED
)
5753 fprintf (file
, "un");
5755 fprintf (file
, "%s", GET_RTX_NAME (c
));
5760 /* Write the divide or modulus operator. */
5761 switch (GET_CODE (x
))
5764 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5767 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5770 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5773 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5776 output_operand_lossage ("invalid %%E value");
5782 /* Write "_u" for unaligned access. */
5783 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5784 fprintf (file
, "_u");
5788 if (GET_CODE (x
) == REG
)
5789 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5790 else if (GET_CODE (x
) == MEM
)
5791 output_address (XEXP (x
, 0));
5792 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5794 switch (XINT (XEXP (x
, 0), 1))
5798 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5801 output_operand_lossage ("unknown relocation unspec");
5806 output_addr_const (file
, x
);
5810 output_operand_lossage ("invalid %%xn code");
5815 print_operand_address (file
, addr
)
5820 HOST_WIDE_INT offset
= 0;
5822 if (GET_CODE (addr
) == AND
)
5823 addr
= XEXP (addr
, 0);
5825 if (GET_CODE (addr
) == PLUS
5826 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5828 offset
= INTVAL (XEXP (addr
, 1));
5829 addr
= XEXP (addr
, 0);
5832 if (GET_CODE (addr
) == LO_SUM
)
5834 const char *reloc16
, *reloclo
;
5835 rtx op1
= XEXP (addr
, 1);
5837 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5839 op1
= XEXP (op1
, 0);
5840 switch (XINT (op1
, 1))
5844 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5848 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5851 output_operand_lossage ("unknown relocation unspec");
5855 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5860 reloclo
= "gprellow";
5861 output_addr_const (file
, op1
);
5867 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5870 addr
= XEXP (addr
, 0);
5871 if (GET_CODE (addr
) == REG
)
5872 basereg
= REGNO (addr
);
5873 else if (GET_CODE (addr
) == SUBREG
5874 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5875 basereg
= subreg_regno (addr
);
5879 fprintf (file
, "($%d)\t\t!%s", basereg
,
5880 (basereg
== 29 ? reloc16
: reloclo
));
5884 if (GET_CODE (addr
) == REG
)
5885 basereg
= REGNO (addr
);
5886 else if (GET_CODE (addr
) == SUBREG
5887 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5888 basereg
= subreg_regno (addr
);
5889 else if (GET_CODE (addr
) == CONST_INT
)
5890 offset
= INTVAL (addr
);
5894 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5895 fprintf (file
, "($%d)", basereg
);
5898 /* Emit RTL insns to initialize the variable parts of a trampoline at
5899 TRAMP. FNADDR is an RTX for the address of the function's pure
5900 code. CXT is an RTX for the static chain value for the function.
5902 The three offset parameters are for the individual template's
5903 layout. A JMPOFS < 0 indicates that the trampoline does not
5904 contain instructions at all.
5906 We assume here that a function will be called many more times than
5907 its address is taken (e.g., it might be passed to qsort), so we
5908 take the trouble to initialize the "hint" field in the JMP insn.
5909 Note that the hint field is PC (new) + 4 * bits 13:0. */
5912 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
5913 rtx tramp
, fnaddr
, cxt
;
5914 int fnofs
, cxtofs
, jmpofs
;
5916 rtx temp
, temp1
, addr
;
5917 /* VMS really uses DImode pointers in memory at this point. */
5918 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5920 #ifdef POINTERS_EXTEND_UNSIGNED
5921 fnaddr
= convert_memory_address (mode
, fnaddr
);
5922 cxt
= convert_memory_address (mode
, cxt
);
5925 /* Store function address and CXT. */
5926 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5927 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5928 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5929 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5931 /* This has been disabled since the hint only has a 32k range, and in
5932 no existing OS is the stack within 32k of the text segment. */
5933 if (0 && jmpofs
>= 0)
5935 /* Compute hint value. */
5936 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5937 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5939 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5940 build_int_2 (2, 0), NULL_RTX
, 1);
5941 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5942 GEN_INT (0x3fff), 0);
5944 /* Merge in the hint. */
5945 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5946 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5947 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5948 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5950 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5953 #ifdef TRANSFER_FROM_TRAMPOLINE
5954 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
5955 0, VOIDmode
, 1, addr
, Pmode
);
5959 emit_insn (gen_imb ());
5962 /* Determine where to put an argument to a function.
5963 Value is zero to push the argument on the stack,
5964 or a hard register in which to store the argument.
5966 MODE is the argument's machine mode.
5967 TYPE is the data type of the argument (as a tree).
5968 This is null for libcalls where that information may
5970 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5971 the preceding args and about the function being called.
5972 NAMED is nonzero if this argument is a named parameter
5973 (otherwise it is an extra parameter matching an ellipsis).
5975 On Alpha the first 6 words of args are normally in registers
5976 and the rest are pushed. */
5979 function_arg (cum
, mode
, type
, named
)
5980 CUMULATIVE_ARGS cum
;
5981 enum machine_mode mode
;
5983 int named ATTRIBUTE_UNUSED
;
5988 /* Set up defaults for FP operands passed in FP registers, and
5989 integral operands passed in integer registers. */
5991 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5992 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
5997 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5998 the three platforms, so we can't avoid conditional compilation. */
5999 #if TARGET_ABI_OPEN_VMS
6001 if (mode
== VOIDmode
)
6002 return alpha_arg_info_reg_val (cum
);
6004 num_args
= cum
.num_args
;
6005 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6009 #if TARGET_ABI_UNICOSMK
6013 /* If this is the last argument, generate the call info word (CIW). */
6014 /* ??? We don't include the caller's line number in the CIW because
6015 I don't know how to determine it if debug infos are turned off. */
6016 if (mode
== VOIDmode
)
6025 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6026 if (cum
.reg_args_type
[i
])
6027 lo
|= (1 << (7 - i
));
6029 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6032 lo
|= cum
.num_reg_words
;
6034 #if HOST_BITS_PER_WIDE_INT == 32
6035 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6037 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6038 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6041 ciw
= immed_double_const (lo
, hi
, DImode
);
6043 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6044 UNSPEC_UMK_LOAD_CIW
);
6047 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6048 num_args
= cum
.num_reg_words
;
6049 if (MUST_PASS_IN_STACK (mode
, type
)
6050 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6052 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6056 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6057 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6059 /* The argument fits in two registers. Note that we still need to
6060 reserve a register for empty structures. */
6064 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6067 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6068 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6069 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6079 /* VOID is passed as a special flag for "last argument". */
6080 if (type
== void_type_node
)
6082 else if (MUST_PASS_IN_STACK (mode
, type
))
6084 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6087 #endif /* TARGET_ABI_UNICOSMK */
6088 #endif /* TARGET_ABI_OPEN_VMS */
6090 return gen_rtx_REG (mode
, num_args
+ basereg
);
6094 alpha_build_va_list ()
6096 tree base
, ofs
, record
, type_decl
;
6098 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6099 return ptr_type_node
;
6101 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6102 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6103 TREE_CHAIN (record
) = type_decl
;
6104 TYPE_NAME (record
) = type_decl
;
6106 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6108 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6110 DECL_FIELD_CONTEXT (ofs
) = record
;
6112 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6114 DECL_FIELD_CONTEXT (base
) = record
;
6115 TREE_CHAIN (base
) = ofs
;
6117 TYPE_FIELDS (record
) = base
;
6118 layout_type (record
);
6124 alpha_va_start (stdarg_p
, valist
, nextarg
)
6127 rtx nextarg ATTRIBUTE_UNUSED
;
6129 HOST_WIDE_INT offset
;
6130 tree t
, offset_field
, base_field
;
6132 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6135 if (TARGET_ABI_UNICOSMK
)
6136 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
6138 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6139 up by 48, storing fp arg registers in the first 48 bytes, and the
6140 integer arg registers in the next 48 bytes. This is only done,
6141 however, if any integer registers need to be stored.
6143 If no integer registers need be stored, then we must subtract 48
6144 in order to account for the integer arg registers which are counted
6145 in argsize above, but which are not actually stored on the stack. */
6147 if (NUM_ARGS
<= 5 + stdarg_p
)
6148 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6150 offset
= -6 * UNITS_PER_WORD
;
6152 if (TARGET_ABI_OPEN_VMS
)
6154 nextarg
= plus_constant (nextarg
, offset
);
6155 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6156 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6157 make_tree (ptr_type_node
, nextarg
));
6158 TREE_SIDE_EFFECTS (t
) = 1;
6160 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6164 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6165 offset_field
= TREE_CHAIN (base_field
);
6167 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6168 valist
, base_field
);
6169 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6170 valist
, offset_field
);
6172 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6173 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6174 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6175 TREE_SIDE_EFFECTS (t
) = 1;
6176 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6178 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6179 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6180 TREE_SIDE_EFFECTS (t
) = 1;
6181 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6186 alpha_va_arg (valist
, type
)
6190 tree t
, type_size
, rounded_size
;
6191 tree offset_field
, base_field
, addr_tree
, addend
;
6192 tree wide_type
, wide_ofs
;
6195 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6196 return std_expand_builtin_va_arg (valist
, type
);
6198 if (type
== error_mark_node
6199 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6200 || TREE_OVERFLOW (type_size
))
6201 rounded_size
= size_zero_node
;
6203 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6204 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6205 fold (build (PLUS_EXPR
, sizetype
,
6211 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6212 offset_field
= TREE_CHAIN (base_field
);
6214 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6215 valist
, base_field
);
6216 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6217 valist
, offset_field
);
6219 /* If the type could not be passed in registers, skip the block
6220 reserved for the registers. */
6221 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6223 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6224 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6225 offset_field
, build_int_2 (6*8, 0)));
6226 TREE_SIDE_EFFECTS (t
) = 1;
6227 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6230 wide_type
= make_signed_type (64);
6231 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6235 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6238 rounded_size
= size_int (UNITS_PER_WORD
);
6240 else if (FLOAT_TYPE_P (type
))
6242 tree fpaddend
, cond
;
6244 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6245 addend
, build_int_2 (-6*8, 0)));
6247 cond
= fold (build (LT_EXPR
, integer_type_node
,
6248 wide_ofs
, build_int_2 (6*8, 0)));
6250 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6254 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6255 base_field
, addend
);
6257 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6258 addr
= copy_to_reg (addr
);
6260 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6261 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6262 offset_field
, rounded_size
));
6263 TREE_SIDE_EFFECTS (t
) = 1;
6264 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6268 addr
= force_reg (Pmode
, addr
);
6269 addr
= gen_rtx_MEM (Pmode
, addr
);
6275 /* This page contains routines that are used to determine what the function
6276 prologue and epilogue code will do and write them out. */
6278 /* Compute the size of the save area in the stack. */
6280 /* These variables are used for communication between the following functions.
6281 They indicate various things about the current function being compiled
6282 that are used to tell what kind of prologue, epilogue and procedure
6283 descriptior to generate. */
6285 /* Nonzero if we need a stack procedure. */
6286 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6287 static enum alpha_procedure_types alpha_procedure_type
;
6289 /* Register number (either FP or SP) that is used to unwind the frame. */
6290 static int vms_unwind_regno
;
6292 /* Register number used to save FP. We need not have one for RA since
6293 we don't modify it for register procedures. This is only defined
6294 for register frame procedures. */
6295 static int vms_save_fp_regno
;
6297 /* Register number used to reference objects off our PV. */
6298 static int vms_base_regno
;
6300 /* Compute register masks for saved registers. */
6303 alpha_sa_mask (imaskP
, fmaskP
)
6304 unsigned long *imaskP
;
6305 unsigned long *fmaskP
;
6307 unsigned long imask
= 0;
6308 unsigned long fmask
= 0;
6311 /* Irritatingly, there are two kinds of thunks -- those created with
6312 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
6313 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
6314 we don't have valid register life info, but assemble_start_function
6315 wants to output .frame and .mask directives. */
6316 if (current_function_is_thunk
&& !no_new_pseudos
)
6323 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6324 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
6326 /* One for every register we have to save. */
6327 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6328 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6329 && regs_ever_live
[i
] && i
!= REG_RA
6330 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6335 fmask
|= (1L << (i
- 32));
6338 /* We need to restore these for the handler. */
6339 if (current_function_calls_eh_return
)
6342 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6343 if (regno
== INVALID_REGNUM
)
6345 imask
|= 1L << regno
;
6348 /* If any register spilled, then spill the return address also. */
6349 /* ??? This is required by the Digital stack unwind specification
6350 and isn't needed if we're doing Dwarf2 unwinding. */
6351 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6352 imask
|= (1L << REG_RA
);
6361 unsigned long mask
[2];
6365 alpha_sa_mask (&mask
[0], &mask
[1]);
6367 if (TARGET_ABI_UNICOSMK
)
6369 if (mask
[0] || mask
[1])
6374 for (j
= 0; j
< 2; ++j
)
6375 for (i
= 0; i
< 32; ++i
)
6376 if ((mask
[j
] >> i
) & 1)
6380 if (TARGET_ABI_UNICOSMK
)
6382 /* We might not need to generate a frame if we don't make any calls
6383 (including calls to __T3E_MISMATCH if this is a vararg function),
6384 don't have any local variables which require stack slots, don't
6385 use alloca and have not determined that we need a frame for other
6388 alpha_procedure_type
6389 = (sa_size
|| get_frame_size() != 0
6390 || current_function_outgoing_args_size
|| current_function_varargs
6391 || current_function_stdarg
|| current_function_calls_alloca
6392 || frame_pointer_needed
)
6393 ? PT_STACK
: PT_REGISTER
;
6395 /* Always reserve space for saving callee-saved registers if we
6396 need a frame as required by the calling convention. */
6397 if (alpha_procedure_type
== PT_STACK
)
6400 else if (TARGET_ABI_OPEN_VMS
)
6402 /* Start by assuming we can use a register procedure if we don't
6403 make any calls (REG_RA not used) or need to save any
6404 registers and a stack procedure if we do. */
6405 if ((mask
[0] >> REG_RA
) & 1)
6406 alpha_procedure_type
= PT_STACK
;
6407 else if (get_frame_size() != 0)
6408 alpha_procedure_type
= PT_REGISTER
;
6410 alpha_procedure_type
= PT_NULL
;
6412 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6413 made the final decision on stack procedure vs register procedure. */
6414 if (alpha_procedure_type
== PT_STACK
)
6417 /* Decide whether to refer to objects off our PV via FP or PV.
6418 If we need FP for something else or if we receive a nonlocal
6419 goto (which expects PV to contain the value), we must use PV.
6420 Otherwise, start by assuming we can use FP. */
6423 = (frame_pointer_needed
6424 || current_function_has_nonlocal_label
6425 || alpha_procedure_type
== PT_STACK
6426 || current_function_outgoing_args_size
)
6427 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6429 /* If we want to copy PV into FP, we need to find some register
6430 in which to save FP. */
6432 vms_save_fp_regno
= -1;
6433 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6434 for (i
= 0; i
< 32; i
++)
6435 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6436 vms_save_fp_regno
= i
;
6438 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6439 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6440 else if (alpha_procedure_type
== PT_NULL
)
6441 vms_base_regno
= REG_PV
;
6443 /* Stack unwinding should be done via FP unless we use it for PV. */
6444 vms_unwind_regno
= (vms_base_regno
== REG_PV
6445 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6447 /* If this is a stack procedure, allow space for saving FP and RA. */
6448 if (alpha_procedure_type
== PT_STACK
)
6453 /* Our size must be even (multiple of 16 bytes). */
6462 alpha_pv_save_size ()
6465 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6472 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6475 #if TARGET_ABI_OPEN_VMS
6477 const struct attribute_spec vms_attribute_table
[] =
6479 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6480 { "overlaid", 0, 0, true, false, false, NULL
},
6481 { "global", 0, 0, true, false, false, NULL
},
6482 { "initialize", 0, 0, true, false, false, NULL
},
6483 { NULL
, 0, 0, false, false, false, NULL
}
6489 find_lo_sum (px
, data
)
6491 void *data ATTRIBUTE_UNUSED
;
6493 return GET_CODE (*px
) == LO_SUM
;
6497 alpha_does_function_need_gp ()
6501 /* The GP being variable is an OSF abi thing. */
6502 if (! TARGET_ABI_OSF
)
6505 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6508 if (current_function_is_thunk
)
6511 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6512 Even if we are a static function, we still need to do this in case
6513 our address is taken and passed to something like qsort. */
6515 push_topmost_sequence ();
6516 insn
= get_insns ();
6517 pop_topmost_sequence ();
6519 for (; insn
; insn
= NEXT_INSN (insn
))
6521 && GET_CODE (PATTERN (insn
)) != USE
6522 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6524 enum attr_type type
= get_attr_type (insn
);
6525 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6527 if (TARGET_EXPLICIT_RELOCS
6528 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6535 /* Write a version stamp. Don't write anything if we are running as a
6536 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6543 alpha_write_verstamp (file
)
6544 FILE *file ATTRIBUTE_UNUSED
;
6547 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6551 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6555 set_frame_related_p ()
6557 rtx seq
= gen_sequence ();
6560 if (GET_CODE (seq
) == SEQUENCE
)
6562 int i
= XVECLEN (seq
, 0);
6564 RTX_FRAME_RELATED_P (XVECEXP (seq
, 0, i
)) = 1;
6565 return emit_insn (seq
);
6569 seq
= emit_insn (seq
);
6570 RTX_FRAME_RELATED_P (seq
) = 1;
6575 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6577 /* Write function prologue. */
6579 /* On vms we have two kinds of functions:
6581 - stack frame (PROC_STACK)
6582 these are 'normal' functions with local vars and which are
6583 calling other functions
6584 - register frame (PROC_REGISTER)
6585 keeps all data in registers, needs no stack
6587 We must pass this to the assembler so it can generate the
6588 proper pdsc (procedure descriptor)
6589 This is done with the '.pdesc' command.
6591 On not-vms, we don't really differentiate between the two, as we can
6592 simply allocate stack without saving registers. */
6595 alpha_expand_prologue ()
6597 /* Registers to save. */
6598 unsigned long imask
= 0;
6599 unsigned long fmask
= 0;
6600 /* Stack space needed for pushing registers clobbered by us. */
6601 HOST_WIDE_INT sa_size
;
6602 /* Complete stack size needed. */
6603 HOST_WIDE_INT frame_size
;
6604 /* Offset from base reg to register save area. */
6605 HOST_WIDE_INT reg_offset
;
6609 sa_size
= alpha_sa_size ();
6611 frame_size
= get_frame_size ();
6612 if (TARGET_ABI_OPEN_VMS
)
6613 frame_size
= ALPHA_ROUND (sa_size
6614 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6616 + current_function_pretend_args_size
);
6617 else if (TARGET_ABI_UNICOSMK
)
6618 /* We have to allocate space for the DSIB if we generate a frame. */
6619 frame_size
= ALPHA_ROUND (sa_size
6620 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6621 + ALPHA_ROUND (frame_size
6622 + current_function_outgoing_args_size
);
6624 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6626 + ALPHA_ROUND (frame_size
6627 + current_function_pretend_args_size
));
6629 if (TARGET_ABI_OPEN_VMS
)
6632 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6634 alpha_sa_mask (&imask
, &fmask
);
6636 /* Emit an insn to reload GP, if needed. */
6639 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6640 if (alpha_function_needs_gp
)
6641 emit_insn (gen_prologue_ldgp ());
6644 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6645 the call to mcount ourselves, rather than having the linker do it
6646 magically in response to -pg. Since _mcount has special linkage,
6647 don't represent the call as a call. */
6648 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6649 emit_insn (gen_prologue_mcount ());
6651 if (TARGET_ABI_UNICOSMK
)
6652 unicosmk_gen_dsib (&imask
);
6654 /* Adjust the stack by the frame size. If the frame size is > 4096
6655 bytes, we need to be sure we probe somewhere in the first and last
6656 4096 bytes (we can probably get away without the latter test) and
6657 every 8192 bytes in between. If the frame size is > 32768, we
6658 do this in a loop. Otherwise, we generate the explicit probe
6661 Note that we are only allowed to adjust sp once in the prologue. */
6663 if (frame_size
<= 32768)
6665 if (frame_size
> 4096)
6670 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6673 while ((probed
+= 8192) < frame_size
);
6675 /* We only have to do this probe if we aren't saving registers. */
6676 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
6677 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
6680 if (frame_size
!= 0)
6681 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6682 GEN_INT (TARGET_ABI_UNICOSMK
6688 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6689 number of 8192 byte blocks to probe. We then probe each block
6690 in the loop and then set SP to the proper location. If the
6691 amount remaining is > 4096, we have to do one more probe if we
6692 are not saving any registers. */
6694 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
6695 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
6696 rtx ptr
= gen_rtx_REG (DImode
, 22);
6697 rtx count
= gen_rtx_REG (DImode
, 23);
6700 emit_move_insn (count
, GEN_INT (blocks
));
6701 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
6702 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
6704 /* Because of the difficulty in emitting a new basic block this
6705 late in the compilation, generate the loop as a single insn. */
6706 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
6708 if (leftover
> 4096 && sa_size
== 0)
6710 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
6711 MEM_VOLATILE_P (last
) = 1;
6712 emit_move_insn (last
, const0_rtx
);
6715 if (TARGET_ABI_WINDOWS_NT
)
6717 /* For NT stack unwind (done by 'reverse execution'), it's
6718 not OK to take the result of a loop, even though the value
6719 is already in ptr, so we reload it via a single operation
6720 and subtract it to sp.
6722 Yes, that's correct -- we have to reload the whole constant
6723 into a temporary via ldah+lda then subtract from sp. To
6724 ensure we get ldah+lda, we use a special pattern. */
6726 HOST_WIDE_INT lo
, hi
;
6727 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6728 hi
= frame_size
- lo
;
6730 emit_move_insn (ptr
, GEN_INT (hi
));
6731 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
6732 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6737 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
6738 GEN_INT (-leftover
)));
6741 /* This alternative is special, because the DWARF code cannot
6742 possibly intuit through the loop above. So we invent this
6743 note it looks at instead. */
6744 RTX_FRAME_RELATED_P (seq
) = 1;
6746 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6747 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6748 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
6749 GEN_INT (TARGET_ABI_UNICOSMK
6755 if (!TARGET_ABI_UNICOSMK
)
6757 /* Cope with very large offsets to the register save area. */
6758 sa_reg
= stack_pointer_rtx
;
6759 if (reg_offset
+ sa_size
> 0x8000)
6761 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6764 if (low
+ sa_size
<= 0x8000)
6765 bias
= reg_offset
- low
, reg_offset
= low
;
6767 bias
= reg_offset
, reg_offset
= 0;
6769 sa_reg
= gen_rtx_REG (DImode
, 24);
6770 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
6774 /* Save regs in stack order. Beginning with VMS PV. */
6775 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6777 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
6778 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6779 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
6782 /* Save register RA next. */
6783 if (imask
& (1L << REG_RA
))
6785 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6786 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6787 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
6788 imask
&= ~(1L << REG_RA
);
6792 /* Now save any other registers required to be saved. */
6793 for (i
= 0; i
< 32; i
++)
6794 if (imask
& (1L << i
))
6796 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6797 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6798 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6802 for (i
= 0; i
< 32; i
++)
6803 if (fmask
& (1L << i
))
6805 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
6806 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6807 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6811 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6813 /* The standard frame on the T3E includes space for saving registers.
6814 We just have to use it. We don't have to save the return address and
6815 the old frame pointer here - they are saved in the DSIB. */
6818 for (i
= 9; i
< 15; i
++)
6819 if (imask
& (1L << i
))
6821 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6823 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6824 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6827 for (i
= 2; i
< 10; i
++)
6828 if (fmask
& (1L << i
))
6830 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
6832 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6833 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6838 if (TARGET_ABI_OPEN_VMS
)
6840 if (alpha_procedure_type
== PT_REGISTER
)
6841 /* Register frame procedures save the fp.
6842 ?? Ought to have a dwarf2 save for this. */
6843 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
6844 hard_frame_pointer_rtx
);
6846 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
6847 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
6848 gen_rtx_REG (DImode
, REG_PV
)));
6850 if (alpha_procedure_type
!= PT_NULL
6851 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6852 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6854 /* If we have to allocate space for outgoing args, do it now. */
6855 if (current_function_outgoing_args_size
!= 0)
6858 plus_constant (hard_frame_pointer_rtx
,
6860 (current_function_outgoing_args_size
)))));
6862 else if (!TARGET_ABI_UNICOSMK
)
6864 /* If we need a frame pointer, set it from the stack pointer. */
6865 if (frame_pointer_needed
)
6867 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
6868 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6870 /* This must always be the last instruction in the
6871 prologue, thus we emit a special move + clobber. */
6872 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
6873 stack_pointer_rtx
, sa_reg
)));
6877 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6878 the prologue, for exception handling reasons, we cannot do this for
6879 any insn that might fault. We could prevent this for mems with a
6880 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6881 have to prevent all such scheduling with a blockage.
6883 Linux, on the other hand, never bothered to implement OSF/1's
6884 exception handling, and so doesn't care about such things. Anyone
6885 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6887 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
6888 emit_insn (gen_blockage ());
6891 /* Output the textual info surrounding the prologue. */
6894 alpha_start_function (file
, fnname
, decl
)
6897 tree decl ATTRIBUTE_UNUSED
;
6899 unsigned long imask
= 0;
6900 unsigned long fmask
= 0;
6901 /* Stack space needed for pushing registers clobbered by us. */
6902 HOST_WIDE_INT sa_size
;
6903 /* Complete stack size needed. */
6904 HOST_WIDE_INT frame_size
;
6905 /* Offset from base reg to register save area. */
6906 HOST_WIDE_INT reg_offset
;
6907 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
6910 /* Don't emit an extern directive for functions defined in the same file. */
6911 if (TARGET_ABI_UNICOSMK
)
6914 name_tree
= get_identifier (fnname
);
6915 TREE_ASM_WRITTEN (name_tree
) = 1;
6918 alpha_fnname
= fnname
;
6919 sa_size
= alpha_sa_size ();
6921 frame_size
= get_frame_size ();
6922 if (TARGET_ABI_OPEN_VMS
)
6923 frame_size
= ALPHA_ROUND (sa_size
6924 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6926 + current_function_pretend_args_size
);
6927 else if (TARGET_ABI_UNICOSMK
)
6928 frame_size
= ALPHA_ROUND (sa_size
6929 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6930 + ALPHA_ROUND (frame_size
6931 + current_function_outgoing_args_size
);
6933 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6935 + ALPHA_ROUND (frame_size
6936 + current_function_pretend_args_size
));
6938 if (TARGET_ABI_OPEN_VMS
)
6941 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6943 alpha_sa_mask (&imask
, &fmask
);
6945 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6946 We have to do that before the .ent directive as we cannot switch
6947 files within procedures with native ecoff because line numbers are
6948 linked to procedure descriptors.
6949 Outputting the lineno helps debugging of one line functions as they
6950 would otherwise get no line number at all. Please note that we would
6951 like to put out last_linenum from final.c, but it is not accessible. */
6953 if (write_symbols
== SDB_DEBUG
)
6955 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6956 ASM_OUTPUT_SOURCE_FILENAME (file
,
6957 DECL_SOURCE_FILE (current_function_decl
));
6959 #ifdef ASM_OUTPUT_SOURCE_LINE
6960 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
6961 ASM_OUTPUT_SOURCE_LINE (file
,
6962 DECL_SOURCE_LINE (current_function_decl
));
6966 /* Issue function start and label. */
6967 if (TARGET_ABI_OPEN_VMS
6968 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
6970 fputs ("\t.ent ", file
);
6971 assemble_name (file
, fnname
);
6974 /* If the function needs GP, we'll write the "..ng" label there.
6975 Otherwise, do it here. */
6977 && ! alpha_function_needs_gp
6978 && ! current_function_is_thunk
)
6981 assemble_name (file
, fnname
);
6982 fputs ("..ng:\n", file
);
6986 strcpy (entry_label
, fnname
);
6987 if (TARGET_ABI_OPEN_VMS
)
6988 strcat (entry_label
, "..en");
6990 /* For public functions, the label must be globalized by appending an
6991 additional colon. */
6992 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
6993 strcat (entry_label
, ":");
6995 ASM_OUTPUT_LABEL (file
, entry_label
);
6996 inside_function
= TRUE
;
6998 if (TARGET_ABI_OPEN_VMS
)
6999 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7001 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7002 && !flag_inhibit_size_directive
)
7004 /* Set flags in procedure descriptor to request IEEE-conformant
7005 math-library routines. The value we set it to is PDSC_EXC_IEEE
7006 (/usr/include/pdsc.h). */
7007 fputs ("\t.eflag 48\n", file
);
7010 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7011 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7012 alpha_arg_offset
= -frame_size
+ 48;
7014 /* Describe our frame. If the frame size is larger than an integer,
7015 print it as zero to avoid an assembler error. We won't be
7016 properly describing such a frame, but that's the best we can do. */
7017 if (TARGET_ABI_UNICOSMK
)
7019 else if (TARGET_ABI_OPEN_VMS
)
7021 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7022 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7023 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7024 fputs (",$26,", file
);
7025 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7028 else if (!flag_inhibit_size_directive
)
7030 fprintf (file
, "\t.frame $%d,",
7031 (frame_pointer_needed
7032 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7033 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7034 frame_size
>= (1l << 31) ? 0 : frame_size
);
7035 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7038 /* Describe which registers were spilled. */
7039 if (TARGET_ABI_UNICOSMK
)
7041 else if (TARGET_ABI_OPEN_VMS
)
7044 /* ??? Does VMS care if mask contains ra? The old code didn't
7045 set it, so I don't here. */
7046 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7048 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7049 if (alpha_procedure_type
== PT_REGISTER
)
7050 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7052 else if (!flag_inhibit_size_directive
)
7056 fprintf (file
, "\t.mask 0x%lx,", imask
);
7057 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7058 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7061 for (i
= 0; i
< 32; ++i
)
7062 if (imask
& (1L << i
))
7068 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7069 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7070 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7075 #if TARGET_ABI_OPEN_VMS
7076 /* Ifdef'ed cause link_section are only available then. */
7077 readonly_data_section ();
7078 fprintf (file
, "\t.align 3\n");
7079 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7080 fputs ("\t.ascii \"", file
);
7081 assemble_name (file
, fnname
);
7082 fputs ("\\0\"\n", file
);
7085 fprintf (file
, "\t.align 3\n");
7086 fputs ("\t.name ", file
);
7087 assemble_name (file
, fnname
);
7088 fputs ("..na\n", file
);
7089 ASM_OUTPUT_LABEL (file
, fnname
);
7090 fprintf (file
, "\t.pdesc ");
7091 assemble_name (file
, fnname
);
7092 fprintf (file
, "..en,%s\n",
7093 alpha_procedure_type
== PT_STACK
? "stack"
7094 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
7095 alpha_need_linkage (fnname
, 1);
7100 /* Emit the .prologue note at the scheduled end of the prologue. */
7103 alpha_output_function_end_prologue (file
)
7106 if (TARGET_ABI_UNICOSMK
)
7108 else if (TARGET_ABI_OPEN_VMS
)
7109 fputs ("\t.prologue\n", file
);
7110 else if (TARGET_ABI_WINDOWS_NT
)
7111 fputs ("\t.prologue 0\n", file
);
7112 else if (!flag_inhibit_size_directive
)
7113 fprintf (file
, "\t.prologue %d\n",
7114 alpha_function_needs_gp
|| current_function_is_thunk
);
7117 /* Write function epilogue. */
7119 /* ??? At some point we will want to support full unwind, and so will
7120 need to mark the epilogue as well. At the moment, we just confuse
7123 #define FRP(exp) exp
7126 alpha_expand_epilogue ()
7128 /* Registers to save. */
7129 unsigned long imask
= 0;
7130 unsigned long fmask
= 0;
7131 /* Stack space needed for pushing registers clobbered by us. */
7132 HOST_WIDE_INT sa_size
;
7133 /* Complete stack size needed. */
7134 HOST_WIDE_INT frame_size
;
7135 /* Offset from base reg to register save area. */
7136 HOST_WIDE_INT reg_offset
;
7137 int fp_is_frame_pointer
, fp_offset
;
7138 rtx sa_reg
, sa_reg_exp
= NULL
;
7139 rtx sp_adj1
, sp_adj2
, mem
;
7143 sa_size
= alpha_sa_size ();
7145 frame_size
= get_frame_size ();
7146 if (TARGET_ABI_OPEN_VMS
)
7147 frame_size
= ALPHA_ROUND (sa_size
7148 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7150 + current_function_pretend_args_size
);
7151 else if (TARGET_ABI_UNICOSMK
)
7152 frame_size
= ALPHA_ROUND (sa_size
7153 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7154 + ALPHA_ROUND (frame_size
7155 + current_function_outgoing_args_size
);
7157 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7159 + ALPHA_ROUND (frame_size
7160 + current_function_pretend_args_size
));
7162 if (TARGET_ABI_OPEN_VMS
)
7164 if (alpha_procedure_type
== PT_STACK
)
7170 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7172 alpha_sa_mask (&imask
, &fmask
);
7175 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7176 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7178 sa_reg
= stack_pointer_rtx
;
7180 if (current_function_calls_eh_return
)
7181 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7185 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7187 /* If we have a frame pointer, restore SP from it. */
7188 if ((TARGET_ABI_OPEN_VMS
7189 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7190 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7191 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7193 /* Cope with very large offsets to the register save area. */
7194 if (reg_offset
+ sa_size
> 0x8000)
7196 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7199 if (low
+ sa_size
<= 0x8000)
7200 bias
= reg_offset
- low
, reg_offset
= low
;
7202 bias
= reg_offset
, reg_offset
= 0;
7204 sa_reg
= gen_rtx_REG (DImode
, 22);
7205 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7207 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7210 /* Restore registers in order, excepting a true frame pointer. */
7212 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7214 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7215 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7218 imask
&= ~(1L << REG_RA
);
7220 for (i
= 0; i
< 32; ++i
)
7221 if (imask
& (1L << i
))
7223 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7224 fp_offset
= reg_offset
;
7227 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7228 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7229 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7234 for (i
= 0; i
< 32; ++i
)
7235 if (fmask
& (1L << i
))
7237 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7238 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7239 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7243 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7245 /* Restore callee-saved general-purpose registers. */
7249 for (i
= 9; i
< 15; i
++)
7250 if (imask
& (1L << i
))
7252 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7254 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7255 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7259 for (i
= 2; i
< 10; i
++)
7260 if (fmask
& (1L << i
))
7262 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7264 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7265 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7269 /* Restore the return address from the DSIB. */
7271 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7272 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7273 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7276 if (frame_size
|| eh_ofs
)
7278 sp_adj1
= stack_pointer_rtx
;
7282 sp_adj1
= gen_rtx_REG (DImode
, 23);
7283 emit_move_insn (sp_adj1
,
7284 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7287 /* If the stack size is large, begin computation into a temporary
7288 register so as not to interfere with a potential fp restore,
7289 which must be consecutive with an SP restore. */
7290 if (frame_size
< 32768
7291 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7292 sp_adj2
= GEN_INT (frame_size
);
7293 else if (TARGET_ABI_UNICOSMK
)
7295 sp_adj1
= gen_rtx_REG (DImode
, 23);
7296 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7297 sp_adj2
= const0_rtx
;
7299 else if (frame_size
< 0x40007fffL
)
7301 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7303 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7304 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7308 sp_adj1
= gen_rtx_REG (DImode
, 23);
7309 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7311 sp_adj2
= GEN_INT (low
);
7315 rtx tmp
= gen_rtx_REG (DImode
, 23);
7316 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7319 /* We can't drop new things to memory this late, afaik,
7320 so build it up by pieces. */
7321 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7322 -(frame_size
< 0)));
7328 /* From now on, things must be in order. So emit blockages. */
7330 /* Restore the frame pointer. */
7331 if (TARGET_ABI_UNICOSMK
)
7333 emit_insn (gen_blockage ());
7334 mem
= gen_rtx_MEM (DImode
,
7335 plus_constant (hard_frame_pointer_rtx
, -16));
7336 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7337 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7339 else if (fp_is_frame_pointer
)
7341 emit_insn (gen_blockage ());
7342 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7343 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7344 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7346 else if (TARGET_ABI_OPEN_VMS
)
7348 emit_insn (gen_blockage ());
7349 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7350 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7353 /* Restore the stack pointer. */
7354 emit_insn (gen_blockage ());
7355 if (sp_adj2
== const0_rtx
)
7356 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7358 FRP (emit_move_insn (stack_pointer_rtx
,
7359 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7363 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7365 emit_insn (gen_blockage ());
7366 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7367 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7369 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7371 /* Decrement the frame pointer if the function does not have a
7374 emit_insn (gen_blockage ());
7375 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7376 hard_frame_pointer_rtx
, GEN_INT (-1))));
7381 /* Output the rest of the textual info surrounding the epilogue. */
7384 alpha_end_function (file
, fnname
, decl
)
7387 tree decl ATTRIBUTE_UNUSED
;
7389 /* End the function. */
7390 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7392 fputs ("\t.end ", file
);
7393 assemble_name (file
, fnname
);
7396 inside_function
= FALSE
;
7398 /* Show that we know this function if it is called again.
7400 Don't do this for global functions in object files destined for a
7401 shared library because the function may be overridden by the application
7402 or other libraries. Similarly, don't do this for weak functions.
7404 Don't do this for functions not defined in the .text section, as
7405 otherwise it's not unlikely that the destination is out of range
7406 for a direct branch. */
7408 if (!DECL_WEAK (current_function_decl
)
7409 && (!flag_pic
|| !TREE_PUBLIC (current_function_decl
))
7410 && decl_in_text_section (current_function_decl
))
7411 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl
), 0)) = 1;
7413 /* Output jump tables and the static subroutine information block. */
7414 if (TARGET_ABI_UNICOSMK
)
7416 unicosmk_output_ssib (file
, fnname
);
7417 unicosmk_output_deferred_case_vectors (file
);
7421 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7423 In order to avoid the hordes of differences between generated code
7424 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7425 lots of code loading up large constants, generate rtl and emit it
7426 instead of going straight to text.
7428 Not sure why this idea hasn't been explored before... */
7431 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7433 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7434 HOST_WIDE_INT delta
;
7437 HOST_WIDE_INT hi
, lo
;
7438 rtx
this, insn
, funexp
;
7440 /* We always require a valid GP. */
7441 emit_insn (gen_prologue_ldgp ());
7442 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7444 /* Find the "this" pointer. If the function returns a structure,
7445 the structure return pointer is in $16. */
7446 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7447 this = gen_rtx_REG (Pmode
, 17);
7449 this = gen_rtx_REG (Pmode
, 16);
7451 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7452 entire constant for the add. */
7453 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7454 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7455 if (hi
+ lo
== delta
)
7458 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7460 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7464 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7465 delta
, -(delta
< 0));
7466 emit_insn (gen_adddi3 (this, this, tmp
));
7469 /* Generate a tail call to the target function. */
7470 if (! TREE_USED (function
))
7472 assemble_external (function
);
7473 TREE_USED (function
) = 1;
7475 funexp
= XEXP (DECL_RTL (function
), 0);
7476 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7477 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7478 SIBLING_CALL_P (insn
) = 1;
7480 /* Run just enough of rest_of_compilation to get the insns emitted.
7481 There's not really enough bulk here to make other passes such as
7482 instruction scheduling worth while. Note that use_thunk calls
7483 assemble_start_function and assemble_end_function. */
7484 insn
= get_insns ();
7485 shorten_branches (insn
);
7486 final_start_function (insn
, file
, 1);
7487 final (insn
, file
, 1, 0);
7488 final_end_function ();
7491 /* Debugging support. */
7495 /* Count the number of sdb related labels are generated (to find block
7496 start and end boundaries). */
7498 int sdb_label_count
= 0;
7500 /* Next label # for each statement. */
7502 static int sym_lineno
= 0;
7504 /* Count the number of .file directives, so that .loc is up to date. */
7506 static int num_source_filenames
= 0;
7508 /* Name of the file containing the current function. */
7510 static const char *current_function_file
= "";
7512 /* Offsets to alpha virtual arg/local debugging pointers. */
7514 long alpha_arg_offset
;
7515 long alpha_auto_offset
;
7517 /* Emit a new filename to a stream. */
7520 alpha_output_filename (stream
, name
)
7524 static int first_time
= TRUE
;
7525 char ltext_label_name
[100];
7530 ++num_source_filenames
;
7531 current_function_file
= name
;
7532 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7533 output_quoted_string (stream
, name
);
7534 fprintf (stream
, "\n");
7535 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7536 fprintf (stream
, "\t#@stabs\n");
7539 else if (write_symbols
== DBX_DEBUG
)
7541 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7542 fprintf (stream
, "%s", ASM_STABS_OP
);
7543 output_quoted_string (stream
, name
);
7544 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7547 else if (name
!= current_function_file
7548 && strcmp (name
, current_function_file
) != 0)
7550 if (inside_function
&& ! TARGET_GAS
)
7551 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7554 ++num_source_filenames
;
7555 current_function_file
= name
;
7556 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7559 output_quoted_string (stream
, name
);
7560 fprintf (stream
, "\n");
7564 /* Emit a linenumber to a stream. */
7567 alpha_output_lineno (stream
, line
)
7571 if (write_symbols
== DBX_DEBUG
)
7573 /* mips-tfile doesn't understand .stabd directives. */
7575 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7576 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7579 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7582 /* Structure to show the current status of registers and memory. */
7584 struct shadow_summary
7587 unsigned int i
: 31; /* Mask of int regs */
7588 unsigned int fp
: 31; /* Mask of fp regs */
7589 unsigned int mem
: 1; /* mem == imem | fpmem */
7593 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
7594 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
7596 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7597 to the summary structure. SET is nonzero if the insn is setting the
7598 object, otherwise zero. */
7601 summarize_insn (x
, sum
, set
)
7603 struct shadow_summary
*sum
;
7606 const char *format_ptr
;
7612 switch (GET_CODE (x
))
7614 /* ??? Note that this case would be incorrect if the Alpha had a
7615 ZERO_EXTRACT in SET_DEST. */
7617 summarize_insn (SET_SRC (x
), sum
, 0);
7618 summarize_insn (SET_DEST (x
), sum
, 1);
7622 summarize_insn (XEXP (x
, 0), sum
, 1);
7626 summarize_insn (XEXP (x
, 0), sum
, 0);
7630 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7631 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7635 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7636 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7640 summarize_insn (SUBREG_REG (x
), sum
, 0);
7645 int regno
= REGNO (x
);
7646 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7648 if (regno
== 31 || regno
== 63)
7654 sum
->defd
.i
|= mask
;
7656 sum
->defd
.fp
|= mask
;
7661 sum
->used
.i
|= mask
;
7663 sum
->used
.fp
|= mask
;
7674 /* Find the regs used in memory address computation: */
7675 summarize_insn (XEXP (x
, 0), sum
, 0);
7678 case CONST_INT
: case CONST_DOUBLE
:
7679 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
7680 case SCRATCH
: case ASM_INPUT
:
7683 /* Handle common unary and binary ops for efficiency. */
7684 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
7685 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
7686 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
7687 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7688 case NE
: case EQ
: case GE
: case GT
: case LE
:
7689 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
7690 summarize_insn (XEXP (x
, 0), sum
, 0);
7691 summarize_insn (XEXP (x
, 1), sum
, 0);
7694 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
7695 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
7696 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
7697 case SQRT
: case FFS
:
7698 summarize_insn (XEXP (x
, 0), sum
, 0);
7702 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
7703 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7704 switch (format_ptr
[i
])
7707 summarize_insn (XEXP (x
, i
), sum
, 0);
7711 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7712 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
7724 /* Ensure a sufficient number of `trapb' insns are in the code when
7725 the user requests code with a trap precision of functions or
7728 In naive mode, when the user requests a trap-precision of
7729 "instruction", a trapb is needed after every instruction that may
7730 generate a trap. This ensures that the code is resumption safe but
7733 When optimizations are turned on, we delay issuing a trapb as long
7734 as possible. In this context, a trap shadow is the sequence of
7735 instructions that starts with a (potentially) trap generating
7736 instruction and extends to the next trapb or call_pal instruction
7737 (but GCC never generates call_pal by itself). We can delay (and
7738 therefore sometimes omit) a trapb subject to the following
7741 (a) On entry to the trap shadow, if any Alpha register or memory
7742 location contains a value that is used as an operand value by some
7743 instruction in the trap shadow (live on entry), then no instruction
7744 in the trap shadow may modify the register or memory location.
7746 (b) Within the trap shadow, the computation of the base register
7747 for a memory load or store instruction may not involve using the
7748 result of an instruction that might generate an UNPREDICTABLE
7751 (c) Within the trap shadow, no register may be used more than once
7752 as a destination register. (This is to make life easier for the
7755 (d) The trap shadow may not include any branch instructions. */
7758 alpha_handle_trap_shadows (insns
)
7761 struct shadow_summary shadow
;
7762 int trap_pending
, exception_nesting
;
7766 exception_nesting
= 0;
7769 shadow
.used
.mem
= 0;
7770 shadow
.defd
= shadow
.used
;
7772 for (i
= insns
; i
; i
= NEXT_INSN (i
))
7774 if (GET_CODE (i
) == NOTE
)
7776 switch (NOTE_LINE_NUMBER (i
))
7778 case NOTE_INSN_EH_REGION_BEG
:
7779 exception_nesting
++;
7784 case NOTE_INSN_EH_REGION_END
:
7785 exception_nesting
--;
7790 case NOTE_INSN_EPILOGUE_BEG
:
7791 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
7796 else if (trap_pending
)
7798 if (alpha_tp
== ALPHA_TP_FUNC
)
7800 if (GET_CODE (i
) == JUMP_INSN
7801 && GET_CODE (PATTERN (i
)) == RETURN
)
7804 else if (alpha_tp
== ALPHA_TP_INSN
)
7808 struct shadow_summary sum
;
7813 sum
.defd
= sum
.used
;
7815 switch (GET_CODE (i
))
7818 /* Annoyingly, get_attr_trap will abort on these. */
7819 if (GET_CODE (PATTERN (i
)) == USE
7820 || GET_CODE (PATTERN (i
)) == CLOBBER
)
7823 summarize_insn (PATTERN (i
), &sum
, 0);
7825 if ((sum
.defd
.i
& shadow
.defd
.i
)
7826 || (sum
.defd
.fp
& shadow
.defd
.fp
))
7828 /* (c) would be violated */
7832 /* Combine shadow with summary of current insn: */
7833 shadow
.used
.i
|= sum
.used
.i
;
7834 shadow
.used
.fp
|= sum
.used
.fp
;
7835 shadow
.used
.mem
|= sum
.used
.mem
;
7836 shadow
.defd
.i
|= sum
.defd
.i
;
7837 shadow
.defd
.fp
|= sum
.defd
.fp
;
7838 shadow
.defd
.mem
|= sum
.defd
.mem
;
7840 if ((sum
.defd
.i
& shadow
.used
.i
)
7841 || (sum
.defd
.fp
& shadow
.used
.fp
)
7842 || (sum
.defd
.mem
& shadow
.used
.mem
))
7844 /* (a) would be violated (also takes care of (b)) */
7845 if (get_attr_trap (i
) == TRAP_YES
7846 && ((sum
.defd
.i
& sum
.used
.i
)
7847 || (sum
.defd
.fp
& sum
.used
.fp
)))
7866 n
= emit_insn_before (gen_trapb (), i
);
7867 PUT_MODE (n
, TImode
);
7868 PUT_MODE (i
, TImode
);
7872 shadow
.used
.mem
= 0;
7873 shadow
.defd
= shadow
.used
;
7878 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
7879 && GET_CODE (i
) == INSN
7880 && GET_CODE (PATTERN (i
)) != USE
7881 && GET_CODE (PATTERN (i
)) != CLOBBER
7882 && get_attr_trap (i
) == TRAP_YES
)
7884 if (optimize
&& !trap_pending
)
7885 summarize_insn (PATTERN (i
), &shadow
, 0);
7891 /* Alpha can only issue instruction groups simultaneously if they are
7892 suitibly aligned. This is very processor-specific. */
7894 enum alphaev4_pipe
{
7901 enum alphaev5_pipe
{
7912 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
7913 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
7914 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
7915 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
7916 static rtx alphaev4_next_nop
PARAMS ((int *));
7917 static rtx alphaev5_next_nop
PARAMS ((int *));
7919 static void alpha_align_insns
7920 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
7922 static enum alphaev4_pipe
7923 alphaev4_insn_pipe (insn
)
7926 if (recog_memoized (insn
) < 0)
7928 if (get_attr_length (insn
) != 4)
7931 switch (get_attr_type (insn
))
7964 static enum alphaev5_pipe
7965 alphaev5_insn_pipe (insn
)
7968 if (recog_memoized (insn
) < 0)
7970 if (get_attr_length (insn
) != 4)
7973 switch (get_attr_type (insn
))
8013 /* IN_USE is a mask of the slots currently filled within the insn group.
8014 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8015 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8017 LEN is, of course, the length of the group in bytes. */
8020 alphaev4_next_group (insn
, pin_use
, plen
)
8022 int *pin_use
, *plen
;
8029 || GET_CODE (PATTERN (insn
)) == CLOBBER
8030 || GET_CODE (PATTERN (insn
)) == USE
)
8035 enum alphaev4_pipe pipe
;
8037 pipe
= alphaev4_insn_pipe (insn
);
8041 /* Force complex instructions to start new groups. */
8045 /* If this is a completely unrecognized insn, its an asm.
8046 We don't know how long it is, so record length as -1 to
8047 signal a needed realignment. */
8048 if (recog_memoized (insn
) < 0)
8051 len
= get_attr_length (insn
);
8055 if (in_use
& EV4_IB0
)
8057 if (in_use
& EV4_IB1
)
8062 in_use
|= EV4_IB0
| EV4_IBX
;
8066 if (in_use
& EV4_IB0
)
8068 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8076 if (in_use
& EV4_IB1
)
8086 /* Haifa doesn't do well scheduling branches. */
8087 if (GET_CODE (insn
) == JUMP_INSN
)
8091 insn
= next_nonnote_insn (insn
);
8093 if (!insn
|| ! INSN_P (insn
))
8096 /* Let Haifa tell us where it thinks insn group boundaries are. */
8097 if (GET_MODE (insn
) == TImode
)
8100 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8105 insn
= next_nonnote_insn (insn
);
8113 /* IN_USE is a mask of the slots currently filled within the insn group.
8114 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8115 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8117 LEN is, of course, the length of the group in bytes. */
8120 alphaev5_next_group (insn
, pin_use
, plen
)
8122 int *pin_use
, *plen
;
8129 || GET_CODE (PATTERN (insn
)) == CLOBBER
8130 || GET_CODE (PATTERN (insn
)) == USE
)
8135 enum alphaev5_pipe pipe
;
8137 pipe
= alphaev5_insn_pipe (insn
);
8141 /* Force complex instructions to start new groups. */
8145 /* If this is a completely unrecognized insn, its an asm.
8146 We don't know how long it is, so record length as -1 to
8147 signal a needed realignment. */
8148 if (recog_memoized (insn
) < 0)
8151 len
= get_attr_length (insn
);
8154 /* ??? Most of the places below, we would like to abort, as
8155 it would indicate an error either in Haifa, or in the
8156 scheduling description. Unfortunately, Haifa never
8157 schedules the last instruction of the BB, so we don't
8158 have an accurate TI bit to go off. */
8160 if (in_use
& EV5_E0
)
8162 if (in_use
& EV5_E1
)
8167 in_use
|= EV5_E0
| EV5_E01
;
8171 if (in_use
& EV5_E0
)
8173 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8181 if (in_use
& EV5_E1
)
8187 if (in_use
& EV5_FA
)
8189 if (in_use
& EV5_FM
)
8194 in_use
|= EV5_FA
| EV5_FAM
;
8198 if (in_use
& EV5_FA
)
8204 if (in_use
& EV5_FM
)
8217 /* Haifa doesn't do well scheduling branches. */
8218 /* ??? If this is predicted not-taken, slotting continues, except
8219 that no more IBR, FBR, or JSR insns may be slotted. */
8220 if (GET_CODE (insn
) == JUMP_INSN
)
8224 insn
= next_nonnote_insn (insn
);
8226 if (!insn
|| ! INSN_P (insn
))
8229 /* Let Haifa tell us where it thinks insn group boundaries are. */
8230 if (GET_MODE (insn
) == TImode
)
8233 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8238 insn
= next_nonnote_insn (insn
);
8247 alphaev4_next_nop (pin_use
)
8250 int in_use
= *pin_use
;
8253 if (!(in_use
& EV4_IB0
))
8258 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8263 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8276 alphaev5_next_nop (pin_use
)
8279 int in_use
= *pin_use
;
8282 if (!(in_use
& EV5_E1
))
8287 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8292 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8304 /* The instruction group alignment main loop. */
8307 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8309 unsigned int max_align
;
8310 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8311 rtx (*next_nop
) PARAMS ((int *));
8313 /* ALIGN is the known alignment for the insn group. */
8315 /* OFS is the offset of the current insn in the insn group. */
8317 int prev_in_use
, in_use
, len
;
8320 /* Let shorten branches care for assigning alignments to code labels. */
8321 shorten_branches (insns
);
8323 if (align_functions
< 4)
8325 else if ((unsigned int) align_functions
< max_align
)
8326 align
= align_functions
;
8330 ofs
= prev_in_use
= 0;
8332 if (GET_CODE (i
) == NOTE
)
8333 i
= next_nonnote_insn (i
);
8337 next
= (*next_group
) (i
, &in_use
, &len
);
8339 /* When we see a label, resync alignment etc. */
8340 if (GET_CODE (i
) == CODE_LABEL
)
8342 unsigned int new_align
= 1 << label_to_alignment (i
);
8344 if (new_align
>= align
)
8346 align
= new_align
< max_align
? new_align
: max_align
;
8350 else if (ofs
& (new_align
-1))
8351 ofs
= (ofs
| (new_align
-1)) + 1;
8356 /* Handle complex instructions special. */
8357 else if (in_use
== 0)
8359 /* Asms will have length < 0. This is a signal that we have
8360 lost alignment knowledge. Assume, however, that the asm
8361 will not mis-align instructions. */
8370 /* If the known alignment is smaller than the recognized insn group,
8371 realign the output. */
8372 else if ((int) align
< len
)
8374 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8377 where
= prev
= prev_nonnote_insn (i
);
8378 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8381 /* Can't realign between a call and its gp reload. */
8382 if (! (TARGET_EXPLICIT_RELOCS
8383 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8385 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8386 align
= 1 << new_log_align
;
8391 /* If the group won't fit in the same INT16 as the previous,
8392 we need to add padding to keep the group together. Rather
8393 than simply leaving the insn filling to the assembler, we
8394 can make use of the knowledge of what sorts of instructions
8395 were issued in the previous group to make sure that all of
8396 the added nops are really free. */
8397 else if (ofs
+ len
> (int) align
)
8399 int nop_count
= (align
- ofs
) / 4;
8402 /* Insert nops before labels, branches, and calls to truely merge
8403 the execution of the nops with the previous instruction group. */
8404 where
= prev_nonnote_insn (i
);
8407 if (GET_CODE (where
) == CODE_LABEL
)
8409 rtx where2
= prev_nonnote_insn (where
);
8410 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8413 else if (GET_CODE (where
) == INSN
)
8420 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8421 while (--nop_count
);
8425 ofs
= (ofs
+ len
) & (align
- 1);
8426 prev_in_use
= in_use
;
8431 /* Machine dependent reorg pass. */
8437 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8438 alpha_handle_trap_shadows (insns
);
8440 /* Due to the number of extra trapb insns, don't bother fixing up
8441 alignment when trap precision is instruction. Moreover, we can
8442 only do our job when sched2 is run. */
8443 if (optimize
&& !optimize_size
8444 && alpha_tp
!= ALPHA_TP_INSN
8445 && flag_schedule_insns_after_reload
)
8447 if (alpha_cpu
== PROCESSOR_EV4
)
8448 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8449 else if (alpha_cpu
== PROCESSOR_EV5
)
8450 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8454 /* Check a floating-point value for validity for a particular machine mode. */
8456 static const char * const float_strings
[] =
8458 /* These are for FLOAT_VAX. */
8459 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8460 "-1.70141173319264430e+38",
8461 "2.93873587705571877e-39", /* 2^-128 */
8462 "-2.93873587705571877e-39",
8463 /* These are for the default broken IEEE mode, which traps
8464 on infinity or denormal numbers. */
8465 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8466 "-3.402823466385288598117e+38",
8467 "1.1754943508222875079687e-38", /* 2^-126 */
8468 "-1.1754943508222875079687e-38",
8471 static REAL_VALUE_TYPE float_values
[8];
8472 static int inited_float_values
= 0;
8475 check_float_value (mode
, d
, overflow
)
8476 enum machine_mode mode
;
8478 int overflow ATTRIBUTE_UNUSED
;
8481 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8484 if (inited_float_values
== 0)
8487 for (i
= 0; i
< 8; i
++)
8488 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8490 inited_float_values
= 1;
8496 REAL_VALUE_TYPE
*fvptr
;
8498 if (TARGET_FLOAT_VAX
)
8499 fvptr
= &float_values
[0];
8501 fvptr
= &float_values
[4];
8503 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8504 if (REAL_VALUES_LESS (fvptr
[0], r
))
8506 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8509 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8511 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8514 else if (REAL_VALUES_LESS (dconst0
, r
)
8515 && REAL_VALUES_LESS (r
, fvptr
[2]))
8517 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8520 else if (REAL_VALUES_LESS (r
, dconst0
)
8521 && REAL_VALUES_LESS (fvptr
[3], r
))
8523 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8531 #ifdef OBJECT_FORMAT_ELF
8533 /* Switch to the section to which we should output X. The only thing
8534 special we do here is to honor small data. */
8537 alpha_elf_select_rtx_section (mode
, x
, align
)
8538 enum machine_mode mode
;
8540 unsigned HOST_WIDE_INT align
;
8542 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8543 /* ??? Consider using mergable sdata sections. */
8546 default_elf_select_rtx_section (mode
, x
, align
);
8549 #endif /* OBJECT_FORMAT_ELF */
8551 #if TARGET_ABI_OPEN_VMS
8553 /* Return the VMS argument type corresponding to MODE. */
8556 alpha_arg_type (mode
)
8557 enum machine_mode mode
;
8562 return TARGET_FLOAT_VAX
? FF
: FS
;
8564 return TARGET_FLOAT_VAX
? FD
: FT
;
8570 /* Return an rtx for an integer representing the VMS Argument Information
8574 alpha_arg_info_reg_val (cum
)
8575 CUMULATIVE_ARGS cum
;
8577 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8580 for (i
= 0; i
< 6; i
++)
8581 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8583 return GEN_INT (regval
);
8586 #include <splay-tree.h>
8588 /* Structure to collect function names for final output
8591 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8596 enum links_kind kind
;
8599 static splay_tree alpha_links
;
8601 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
8602 static void mark_alpha_links
PARAMS ((void *));
8603 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
8605 /* Protect alpha_links from garbage collection. */
8608 mark_alpha_links_node (node
, data
)
8609 splay_tree_node node
;
8610 void *data ATTRIBUTE_UNUSED
;
8612 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8613 ggc_mark_rtx (links
->linkage
);
8618 mark_alpha_links (ptr
)
8621 splay_tree tree
= *(splay_tree
*) ptr
;
8622 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8625 /* Make (or fake) .linkage entry for function call.
8627 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8629 Return an SYMBOL_REF rtx for the linkage. */
8632 alpha_need_linkage (name
, is_local
)
8636 splay_tree_node node
;
8637 struct alpha_links
*al
;
8644 /* Is this name already defined? */
8646 node
= splay_tree_lookup (alpha_links
, (splay_tree_key
) name
);
8649 al
= (struct alpha_links
*) node
->value
;
8652 /* Defined here but external assumed. */
8653 if (al
->kind
== KIND_EXTERN
)
8654 al
->kind
= KIND_LOCAL
;
8658 /* Used here but unused assumed. */
8659 if (al
->kind
== KIND_UNUSED
)
8660 al
->kind
= KIND_LOCAL
;
8667 alpha_links
= splay_tree_new ((splay_tree_compare_fn
) strcmp
,
8668 (splay_tree_delete_key_fn
) free
,
8669 (splay_tree_delete_key_fn
) free
);
8670 ggc_add_root (&alpha_links
, 1, 1, mark_alpha_links
);
8673 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
8674 name
= xstrdup (name
);
8676 /* Assume external if no definition. */
8677 al
->kind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
8679 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8680 get_identifier (name
);
8682 /* Construct a SYMBOL_REF for us to call. */
8684 size_t name_len
= strlen (name
);
8685 char *linksym
= alloca (name_len
+ 6);
8687 memcpy (linksym
+ 1, name
, name_len
);
8688 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
8689 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
8690 ggc_alloc_string (linksym
, name_len
+ 5));
8693 splay_tree_insert (alpha_links
, (splay_tree_key
) name
,
8694 (splay_tree_value
) al
);
8700 alpha_write_one_linkage (node
, data
)
8701 splay_tree_node node
;
8704 const char *const name
= (const char *) node
->key
;
8705 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8706 FILE *stream
= (FILE *) data
;
8708 if (links
->kind
== KIND_UNUSED
8709 || ! TREE_SYMBOL_REFERENCED (get_identifier (name
)))
8712 fprintf (stream
, "$%s..lk:\n", name
);
8713 if (links
->kind
== KIND_LOCAL
)
8715 /* Local and used, build linkage pair. */
8716 fprintf (stream
, "\t.quad %s..en\n", name
);
8717 fprintf (stream
, "\t.quad %s\n", name
);
8721 /* External and used, request linkage pair. */
8722 fprintf (stream
, "\t.linkage %s\n", name
);
8729 alpha_write_linkage (stream
)
8734 readonly_data_section ();
8735 fprintf (stream
, "\t.align 3\n");
8736 splay_tree_foreach (alpha_links
, alpha_write_one_linkage
, stream
);
8740 /* Given a decl, a section name, and whether the decl initializer
8741 has relocs, choose attributes for the section. */
8743 #define SECTION_VMS_OVERLAY SECTION_FORGET
8744 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8745 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8748 vms_section_type_flags (decl
, name
, reloc
)
8753 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8755 if (decl
&& DECL_ATTRIBUTES (decl
)
8756 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
8757 flags
|= SECTION_VMS_OVERLAY
;
8758 if (decl
&& DECL_ATTRIBUTES (decl
)
8759 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
8760 flags
|= SECTION_VMS_GLOBAL
;
8761 if (decl
&& DECL_ATTRIBUTES (decl
)
8762 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
8763 flags
|= SECTION_VMS_INITIALIZE
;
8768 /* Switch to an arbitrary section NAME with attributes as specified
8769 by FLAGS. ALIGN specifies any known alignment requirements for
8770 the section; 0 if the default should be used. */
8773 vms_asm_named_section (name
, flags
)
8777 fputc ('\n', asm_out_file
);
8778 fprintf (asm_out_file
, ".section\t%s", name
);
8780 if (flags
& SECTION_VMS_OVERLAY
)
8781 fprintf (asm_out_file
, ",OVR");
8782 if (flags
& SECTION_VMS_GLOBAL
)
8783 fprintf (asm_out_file
, ",GBL");
8784 if (flags
& SECTION_VMS_INITIALIZE
)
8785 fprintf (asm_out_file
, ",NOMOD");
8786 if (flags
& SECTION_DEBUG
)
8787 fprintf (asm_out_file
, ",NOWRT");
8789 fputc ('\n', asm_out_file
);
8792 /* Record an element in the table of global constructors. SYMBOL is
8793 a SYMBOL_REF of the function to be called; PRIORITY is a number
8794 between 0 and MAX_INIT_PRIORITY.
8796 Differs from default_ctors_section_asm_out_constructor in that the
8797 width of the .ctors entry is always 64 bits, rather than the 32 bits
8798 used by a normal pointer. */
8801 vms_asm_out_constructor (symbol
, priority
)
8803 int priority ATTRIBUTE_UNUSED
;
8806 assemble_align (BITS_PER_WORD
);
8807 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8811 vms_asm_out_destructor (symbol
, priority
)
8813 int priority ATTRIBUTE_UNUSED
;
8816 assemble_align (BITS_PER_WORD
);
8817 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8822 alpha_need_linkage (name
, is_local
)
8823 const char *name ATTRIBUTE_UNUSED
;
8824 int is_local ATTRIBUTE_UNUSED
;
8829 #endif /* TARGET_ABI_OPEN_VMS */
8831 #if TARGET_ABI_UNICOSMK
8833 static void unicosmk_output_module_name
PARAMS ((FILE *));
8834 static void unicosmk_output_default_externs
PARAMS ((FILE *));
8835 static void unicosmk_output_dex
PARAMS ((FILE *));
8836 static void unicosmk_output_externs
PARAMS ((FILE *));
8837 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
8838 static const char *unicosmk_ssib_name
PARAMS ((void));
8839 static int unicosmk_special_name
PARAMS ((const char *));
8841 /* Define the offset between two registers, one to be eliminated, and the
8842 other its replacement, at the start of a routine. */
8845 unicosmk_initial_elimination_offset (from
, to
)
8851 fixed_size
= alpha_sa_size();
8852 if (fixed_size
!= 0)
8855 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8857 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8859 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8860 return (ALPHA_ROUND (current_function_outgoing_args_size
)
8861 + ALPHA_ROUND (get_frame_size()));
8862 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8863 return (ALPHA_ROUND (fixed_size
)
8864 + ALPHA_ROUND (get_frame_size()
8865 + current_function_outgoing_args_size
));
8870 /* Output the module name for .ident and .end directives. We have to strip
8871 directories and add make sure that the module name starts with a letter
8875 unicosmk_output_module_name (file
)
8880 /* Strip directories. */
8882 name
= strrchr (main_input_filename
, '/');
8886 name
= main_input_filename
;
8888 /* CAM only accepts module names that start with a letter or '$'. We
8889 prefix the module name with a '$' if necessary. */
8891 if (!ISALPHA (*name
))
8893 output_clean_symbol_name (file
, name
);
8896 /* Output text that to appear at the beginning of an assembler file. */
8899 unicosmk_asm_file_start (file
)
8904 fputs ("\t.ident\t", file
);
8905 unicosmk_output_module_name (file
);
8906 fputs ("\n\n", file
);
8908 /* The Unicos/Mk assembler uses different register names. Instead of trying
8909 to support them, we simply use micro definitions. */
8911 /* CAM has different register names: rN for the integer register N and fN
8912 for the floating-point register N. Instead of trying to use these in
8913 alpha.md, we define the symbols $N and $fN to refer to the appropriate
8916 for (i
= 0; i
< 32; ++i
)
8917 fprintf (file
, "$%d <- r%d\n", i
, i
);
8919 for (i
= 0; i
< 32; ++i
)
8920 fprintf (file
, "$f%d <- f%d\n", i
, i
);
8924 /* The .align directive fill unused space with zeroes which does not work
8925 in code sections. We define the macro 'gcc@code@align' which uses nops
8926 instead. Note that it assumes that code sections always have the
8927 biggest possible alignment since . refers to the current offset from
8928 the beginning of the section. */
8930 fputs ("\t.macro gcc@code@align n\n", file
);
8931 fputs ("gcc@n@bytes = 1 << n\n", file
);
8932 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
8933 fputs ("\t.if ne, gcc@here, 0\n", file
);
8934 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
8935 fputs ("\tbis r31,r31,r31\n", file
);
8936 fputs ("\t.endr\n", file
);
8937 fputs ("\t.endif\n", file
);
8938 fputs ("\t.endm gcc@code@align\n\n", file
);
8940 /* Output extern declarations which should always be visible. */
8941 unicosmk_output_default_externs (file
);
8943 /* Open a dummy section. We always need to be inside a section for the
8944 section-switching code to work correctly.
8945 ??? This should be a module id or something like that. I still have to
8946 figure out what the rules for those are. */
8947 fputs ("\n\t.psect\t$SG00000,data\n", file
);
8950 /* Output text to appear at the end of an assembler file. This includes all
8951 pending extern declarations and DEX expressions. */
8954 unicosmk_asm_file_end (file
)
8957 fputs ("\t.endp\n\n", file
);
8959 /* Output all pending externs. */
8961 unicosmk_output_externs (file
);
8963 /* Output dex definitions used for functions whose names conflict with
8966 unicosmk_output_dex (file
);
8968 fputs ("\t.end\t", file
);
8969 unicosmk_output_module_name (file
);
8973 /* Output the definition of a common variable. */
8976 unicosmk_output_common (file
, name
, size
, align
)
8983 printf ("T3E__: common %s\n", name
);
8986 fputs("\t.endp\n\n\t.psect ", file
);
8987 assemble_name(file
, name
);
8988 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
8989 fprintf(file
, "\t.byte\t0:%d\n", size
);
8991 /* Mark the symbol as defined in this module. */
8992 name_tree
= get_identifier (name
);
8993 TREE_ASM_WRITTEN (name_tree
) = 1;
8996 #define SECTION_PUBLIC SECTION_MACH_DEP
8997 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8998 static int current_section_align
;
9001 unicosmk_section_type_flags (decl
, name
, reloc
)
9004 int reloc ATTRIBUTE_UNUSED
;
9006 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9011 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9013 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9014 if (align_functions_log
> current_section_align
)
9015 current_section_align
= align_functions_log
;
9017 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9018 flags
|= SECTION_MAIN
;
9021 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9023 if (TREE_PUBLIC (decl
))
9024 flags
|= SECTION_PUBLIC
;
9029 /* Generate a section name for decl and associate it with the
9033 unicosmk_unique_section (decl
, reloc
)
9035 int reloc ATTRIBUTE_UNUSED
;
9043 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9044 name
= alpha_strip_name_encoding (name
);
9045 len
= strlen (name
);
9047 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9051 /* It is essential that we prefix the section name here because
9052 otherwise the section names generated for constructors and
9053 destructors confuse collect2. */
9055 string
= alloca (len
+ 6);
9056 sprintf (string
, "code@%s", name
);
9057 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9059 else if (TREE_PUBLIC (decl
))
9060 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9065 string
= alloca (len
+ 6);
9066 sprintf (string
, "data@%s", name
);
9067 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9071 /* Switch to an arbitrary section NAME with attributes as specified
9072 by FLAGS. ALIGN specifies any known alignment requirements for
9073 the section; 0 if the default should be used. */
9076 unicosmk_asm_named_section (name
, flags
)
9082 /* Close the previous section. */
9084 fputs ("\t.endp\n\n", asm_out_file
);
9086 /* Find out what kind of section we are opening. */
9088 if (flags
& SECTION_MAIN
)
9089 fputs ("\t.start\tmain\n", asm_out_file
);
9091 if (flags
& SECTION_CODE
)
9093 else if (flags
& SECTION_PUBLIC
)
9098 if (current_section_align
!= 0)
9099 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9100 current_section_align
, kind
);
9102 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9106 unicosmk_insert_attributes (decl
, attr_ptr
)
9108 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9111 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9112 unicosmk_unique_section (decl
, 0);
9115 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9116 in code sections because .align fill unused space with zeroes. */
9119 unicosmk_output_align (file
, align
)
9123 if (inside_function
)
9124 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9126 fprintf (file
, "\t.align\t%d\n", align
);
9129 /* Add a case vector to the current function's list of deferred case
9130 vectors. Case vectors have to be put into a separate section because CAM
9131 does not allow data definitions in code sections. */
9134 unicosmk_defer_case_vector (lab
, vec
)
9138 struct machine_function
*machine
= cfun
->machine
;
9140 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9141 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9142 machine
->addr_list
);
9145 /* Output a case vector. */
9148 unicosmk_output_addr_vec (file
, vec
)
9152 rtx lab
= XEXP (vec
, 0);
9153 rtx body
= XEXP (vec
, 1);
9154 int vlen
= XVECLEN (body
, 0);
9157 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
9159 for (idx
= 0; idx
< vlen
; idx
++)
9161 ASM_OUTPUT_ADDR_VEC_ELT
9162 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9166 /* Output current function's deferred case vectors. */
9169 unicosmk_output_deferred_case_vectors (file
)
9172 struct machine_function
*machine
= cfun
->machine
;
9175 if (machine
->addr_list
== NULL_RTX
)
9179 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9180 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9183 /* Set up the dynamic subprogram information block (DSIB) and update the
9184 frame pointer register ($15) for subroutines which have a frame. If the
9185 subroutine doesn't have a frame, simply increment $15. */
9188 unicosmk_gen_dsib (imaskP
)
9189 unsigned long * imaskP
;
9191 if (alpha_procedure_type
== PT_STACK
)
9193 const char *ssib_name
;
9196 /* Allocate 64 bytes for the DSIB. */
9198 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9200 emit_insn (gen_blockage ());
9202 /* Save the return address. */
9204 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9205 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9206 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9207 (*imaskP
) &= ~(1L << REG_RA
);
9209 /* Save the old frame pointer. */
9211 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9212 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9213 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9214 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9216 emit_insn (gen_blockage ());
9218 /* Store the SSIB pointer. */
9220 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9221 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9222 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9224 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9225 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9226 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9228 /* Save the CIW index. */
9230 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9231 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9232 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9234 emit_insn (gen_blockage ());
9236 /* Set the new frame pointer. */
9238 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9239 stack_pointer_rtx
, GEN_INT (64))));
9244 /* Increment the frame pointer register to indicate that we do not
9247 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9248 hard_frame_pointer_rtx
, GEN_INT (1))));
9252 #define SSIB_PREFIX "__SSIB_"
9253 #define SSIB_PREFIX_LEN 7
9255 /* Generate the name of the SSIB section for the current function. */
9258 unicosmk_ssib_name ()
9260 /* This is ok since CAM won't be able to deal with names longer than that
9263 static char name
[256];
9269 x
= DECL_RTL (cfun
->decl
);
9270 if (GET_CODE (x
) != MEM
)
9273 if (GET_CODE (x
) != SYMBOL_REF
)
9275 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
9277 len
= strlen (fnname
);
9278 if (len
+ SSIB_PREFIX_LEN
> 255)
9279 len
= 255 - SSIB_PREFIX_LEN
;
9281 strcpy (name
, SSIB_PREFIX
);
9282 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9283 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9288 /* Output the static subroutine information block for the current
9292 unicosmk_output_ssib (file
, fnname
)
9300 struct machine_function
*machine
= cfun
->machine
;
9303 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9304 unicosmk_ssib_name ());
9306 /* Some required stuff and the function name length. */
9308 len
= strlen (fnname
);
9309 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9312 ??? We don't do that yet. */
9314 fputs ("\t.quad\t0\n", file
);
9316 /* Function address. */
9318 fputs ("\t.quad\t", file
);
9319 assemble_name (file
, fnname
);
9322 fputs ("\t.quad\t0\n", file
);
9323 fputs ("\t.quad\t0\n", file
);
9326 ??? We do it the same way Cray CC does it but this could be
9329 for( i
= 0; i
< len
; i
++ )
9330 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9331 if( (len
% 8) == 0 )
9332 fputs ("\t.quad\t0\n", file
);
9334 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9336 /* All call information words used in the function. */
9338 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9341 fprintf (file
, "\t.quad\t");
9342 #if HOST_BITS_PER_WIDE_INT == 32
9343 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
9344 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9346 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
9348 fprintf (file
, "\n");
9352 /* Add a call information word (CIW) to the list of the current function's
9353 CIWs and return its index.
9355 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9358 unicosmk_add_call_info_word (x
)
9362 struct machine_function
*machine
= cfun
->machine
;
9364 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9365 if (machine
->first_ciw
== NULL_RTX
)
9366 machine
->first_ciw
= node
;
9368 XEXP (machine
->last_ciw
, 1) = node
;
9370 machine
->last_ciw
= node
;
9371 ++machine
->ciw_count
;
9373 return GEN_INT (machine
->ciw_count
9374 + strlen (current_function_name
)/8 + 5);
9377 static char unicosmk_section_buf
[100];
9380 unicosmk_text_section ()
9382 static int count
= 0;
9383 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9385 return unicosmk_section_buf
;
9389 unicosmk_data_section ()
9391 static int count
= 1;
9392 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9394 return unicosmk_section_buf
;
9397 /* The Cray assembler doesn't accept extern declarations for symbols which
9398 are defined in the same file. We have to keep track of all global
9399 symbols which are referenced and/or defined in a source file and output
9400 extern declarations for those which are referenced but not defined at
9403 /* List of identifiers for which an extern declaration might have to be
9406 struct unicosmk_extern_list
9408 struct unicosmk_extern_list
*next
;
9412 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9414 /* Output extern declarations which are required for every asm file. */
9417 unicosmk_output_default_externs (file
)
9420 static const char *const externs
[] =
9421 { "__T3E_MISMATCH" };
9426 n
= ARRAY_SIZE (externs
);
9428 for (i
= 0; i
< n
; i
++)
9429 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9432 /* Output extern declarations for global symbols which are have been
9433 referenced but not defined. */
9436 unicosmk_output_externs (file
)
9439 struct unicosmk_extern_list
*p
;
9440 const char *real_name
;
9444 len
= strlen (user_label_prefix
);
9445 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9447 /* We have to strip the encoding and possibly remove user_label_prefix
9448 from the identifier in order to handle -fleading-underscore and
9449 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9450 real_name
= alpha_strip_name_encoding (p
->name
);
9451 if (len
&& p
->name
[0] == '*'
9452 && !memcmp (real_name
, user_label_prefix
, len
))
9455 name_tree
= get_identifier (real_name
);
9456 if (! TREE_ASM_WRITTEN (name_tree
))
9458 TREE_ASM_WRITTEN (name_tree
) = 1;
9459 fputs ("\t.extern\t", file
);
9460 assemble_name (file
, p
->name
);
9466 /* Record an extern. */
9469 unicosmk_add_extern (name
)
9472 struct unicosmk_extern_list
*p
;
9474 p
= (struct unicosmk_extern_list
*)
9475 permalloc (sizeof (struct unicosmk_extern_list
));
9476 p
->next
= unicosmk_extern_head
;
9478 unicosmk_extern_head
= p
;
9481 /* The Cray assembler generates incorrect code if identifiers which
9482 conflict with register names are used as instruction operands. We have
9483 to replace such identifiers with DEX expressions. */
9485 /* Structure to collect identifiers which have been replaced by DEX
9488 struct unicosmk_dex
{
9489 struct unicosmk_dex
*next
;
9493 /* List of identifiers which have been replaced by DEX expressions. The DEX
9494 number is determined by the position in the list. */
9496 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9498 /* The number of elements in the DEX list. */
9500 static int unicosmk_dex_count
= 0;
9502 /* Check if NAME must be replaced by a DEX expression. */
9505 unicosmk_special_name (name
)
9514 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9520 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9523 return (name
[2] == '\0'
9524 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9527 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9531 /* Return the DEX number if X must be replaced by a DEX expression and 0
9535 unicosmk_need_dex (x
)
9538 struct unicosmk_dex
*dex
;
9542 if (GET_CODE (x
) != SYMBOL_REF
)
9546 if (! unicosmk_special_name (name
))
9549 i
= unicosmk_dex_count
;
9550 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9552 if (! strcmp (name
, dex
->name
))
9557 dex
= (struct unicosmk_dex
*) permalloc (sizeof (struct unicosmk_dex
));
9559 dex
->next
= unicosmk_dex_list
;
9560 unicosmk_dex_list
= dex
;
9562 ++unicosmk_dex_count
;
9563 return unicosmk_dex_count
;
9566 /* Output the DEX definitions for this file. */
9569 unicosmk_output_dex (file
)
9572 struct unicosmk_dex
*dex
;
9575 if (unicosmk_dex_list
== NULL
)
9578 fprintf (file
, "\t.dexstart\n");
9580 i
= unicosmk_dex_count
;
9581 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9583 fprintf (file
, "\tDEX (%d) = ", i
);
9584 assemble_name (file
, dex
->name
);
9589 fprintf (file
, "\t.dexend\n");
9595 unicosmk_output_deferred_case_vectors (file
)
9596 FILE *file ATTRIBUTE_UNUSED
;
9600 unicosmk_gen_dsib (imaskP
)
9601 unsigned long * imaskP ATTRIBUTE_UNUSED
;
9605 unicosmk_output_ssib (file
, fnname
)
9606 FILE * file ATTRIBUTE_UNUSED
;
9607 const char * fnname ATTRIBUTE_UNUSED
;
9611 unicosmk_add_call_info_word (x
)
9612 rtx x ATTRIBUTE_UNUSED
;
9618 unicosmk_need_dex (x
)
9619 rtx x ATTRIBUTE_UNUSED
;
9624 #endif /* TARGET_ABI_UNICOSMK */