gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 #include "params.h"
 101 #include "tree-pass.h"
 102 #include "df.h"
 103 #include "valtrack.h"
 104 #include "cgraph.h"
 105 #include "obstack.h"
 106
 107 /* Number of attempts to combine instructions in this function.  */
 108
 109 static int combine_attempts;
 110
 111 /* Number of attempts that got as far as substitution in this function.  */
 112
 113 static int combine_merges;
 114
 115 /* Number of instructions combined with added SETs in this function.  */
 116
 117 static int combine_extras;
 118
 119 /* Number of instructions combined in this function.  */
 120
 121 static int combine_successes;
 122
 123 /* Totals over entire compilation.  */
 124
 125 static int total_attempts, total_merges, total_extras, total_successes;
 126
 127 /* combine_instructions may try to replace the right hand side of the
 128    second instruction with the value of an associated REG_EQUAL note
 129    before throwing it at try_combine.  That is problematic when there
 130    is a REG_DEAD note for a register used in the old right hand side
 131    and can cause distribute_notes to do wrong things.  This is the
 132    second instruction if it has been so modified, null otherwise.  */
 133
 134 static rtx i2mod;
 135
 136 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 137
 138 static rtx i2mod_old_rhs;
 139
 140 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 141
 142 static rtx i2mod_new_rhs;
 143 \f
 144 typedef struct reg_stat_struct {
 145   /* Record last point of death of (hard or pseudo) register n.  */
 146   rtx                           last_death;
 147
 148   /* Record last point of modification of (hard or pseudo) register n.  */
 149   rtx                           last_set;
 150
 151   /* The next group of fields allows the recording of the last value assigned
 152      to (hard or pseudo) register n.  We use this information to see if an
 153      operation being processed is redundant given a prior operation performed
 154      on the register.  For example, an `and' with a constant is redundant if
 155      all the zero bits are already known to be turned off.
 156
 157      We use an approach similar to that used by cse, but change it in the
 158      following ways:
 159
 160      (1) We do not want to reinitialize at each label.
 161      (2) It is useful, but not critical, to know the actual value assigned
 162          to a register.  Often just its form is helpful.
 163
 164      Therefore, we maintain the following fields:
 165
 166      last_set_value             the last value assigned
 167      last_set_label             records the value of label_tick when the
 168                                 register was assigned
 169      last_set_table_tick        records the value of label_tick when a
 170                                 value using the register is assigned
 171      last_set_invalid           set to nonzero when it is not valid
 172                                 to use the value of this register in some
 173                                 register's value
 174
 175      To understand the usage of these tables, it is important to understand
 176      the distinction between the value in last_set_value being valid and
 177      the register being validly contained in some other expression in the
 178      table.
 179
 180      (The next two parameters are out of date).
 181
 182      reg_stat[i].last_set_value is valid if it is nonzero, and either
 183      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 184
 185      Register I may validly appear in any expression returned for the value
 186      of another register if reg_n_sets[i] is 1.  It may also appear in the
 187      value for register J if reg_stat[j].last_set_invalid is zero, or
 188      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 189
 190      If an expression is found in the table containing a register which may
 191      not validly appear in an expression, the register is replaced by
 192      something that won't match, (clobber (const_int 0)).  */
 193
 194   /* Record last value assigned to (hard or pseudo) register n.  */
 195
 196   rtx                           last_set_value;
 197
 198   /* Record the value of label_tick when an expression involving register n
 199      is placed in last_set_value.  */
 200
 201   int                           last_set_table_tick;
 202
 203   /* Record the value of label_tick when the value for register n is placed in
 204      last_set_value.  */
 205
 206   int                           last_set_label;
 207
 208   /* These fields are maintained in parallel with last_set_value and are
 209      used to store the mode in which the register was last set, the bits
 210      that were known to be zero when it was last set, and the number of
 211      sign bits copies it was known to have when it was last set.  */
 212
 213   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 214   char                          last_set_sign_bit_copies;
 215   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 216
 217   /* Set nonzero if references to register n in expressions should not be
 218      used.  last_set_invalid is set nonzero when this register is being
 219      assigned to and last_set_table_tick == label_tick.  */
 220
 221   char                          last_set_invalid;
 222
 223   /* Some registers that are set more than once and used in more than one
 224      basic block are nevertheless always set in similar ways.  For example,
 225      a QImode register may be loaded from memory in two places on a machine
 226      where byte loads zero extend.
 227
 228      We record in the following fields if a register has some leading bits
 229      that are always equal to the sign bit, and what we know about the
 230      nonzero bits of a register, specifically which bits are known to be
 231      zero.
 232
 233      If an entry is zero, it means that we don't know anything special.  */
 234
 235   unsigned char                 sign_bit_copies;
 236
 237   unsigned HOST_WIDE_INT        nonzero_bits;
 238
 239   /* Record the value of the label_tick when the last truncation
 240      happened.  The field truncated_to_mode is only valid if
 241      truncation_label == label_tick.  */
 242
 243   int                           truncation_label;
 244
 245   /* Record the last truncation seen for this register.  If truncation
 246      is not a nop to this mode we might be able to save an explicit
 247      truncation if we know that value already contains a truncated
 248      value.  */
 249
 250   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 251 } reg_stat_type;
 252
 253
 254 static vec<reg_stat_type> reg_stat;
 255
 256 /* Record the luid of the last insn that invalidated memory
 257    (anything that writes memory, and subroutine calls, but not pushes).  */
 258
 259 static int mem_last_set;
 260
 261 /* Record the luid of the last CALL_INSN
 262    so we can tell whether a potential combination crosses any calls.  */
 263
 264 static int last_call_luid;
 265
 266 /* When `subst' is called, this is the insn that is being modified
 267    (by combining in a previous insn).  The PATTERN of this insn
 268    is still the old pattern partially modified and it should not be
 269    looked at, but this may be used to examine the successors of the insn
 270    to judge whether a simplification is valid.  */
 271
 272 static rtx subst_insn;
 273
 274 /* This is the lowest LUID that `subst' is currently dealing with.
 275    get_last_value will not return a value if the register was set at or
 276    after this LUID.  If not for this mechanism, we could get confused if
 277    I2 or I1 in try_combine were an insn that used the old value of a register
 278    to obtain a new value.  In that case, we might erroneously get the
 279    new value of the register when we wanted the old one.  */
 280
 281 static int subst_low_luid;
 282
 283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 284    must consider all these registers to be always live.  */
 285
 286 static HARD_REG_SET newpat_used_regs;
 287
 288 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 289    insn is the earlier than I2 or I3, combine should rescan starting at
 290    that location.  */
 291
 292 static rtx added_links_insn;
 293
 294 /* Basic block in which we are performing combines.  */
 295 static basic_block this_basic_block;
 296 static bool optimize_this_for_speed_p;
 297
 298 \f
 299 /* Length of the currently allocated uid_insn_cost array.  */
 300
 301 static int max_uid_known;
 302
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* The following array records the LOG_LINKS for every insn in the
 309    instruction stream as struct insn_link pointers.  */
 310
 311 struct insn_link {
 312   rtx insn;
 313   struct insn_link *next;
 314 };
 315
 316 static struct insn_link **uid_log_links;
 317
 318 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 319 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 320
 321 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 322   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 323
 324 /* Links for LOG_LINKS are allocated from this obstack.  */
 325
 326 static struct obstack insn_link_obstack;
 327
 328 /* Allocate a link.  */
 329
 330 static inline struct insn_link *
 331 alloc_insn_link (rtx insn, struct insn_link *next)
 332 {
 333   struct insn_link *l
 334     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 335                                           sizeof (struct insn_link));
 336   l->insn = insn;
 337   l->next = next;
 338   return l;
 339 }
 340
 341 /* Incremented for each basic block.  */
 342
 343 static int label_tick;
 344
 345 /* Reset to label_tick for each extended basic block in scanning order.  */
 346
 347 static int label_tick_ebb_start;
 348
 349 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 350    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 351
 352 static enum machine_mode nonzero_bits_mode;
 353
 354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 355    be safely used.  It is zero while computing them and after combine has
 356    completed.  This former test prevents propagating values based on
 357    previously set values, which can be incorrect if a variable is modified
 358    in a loop.  */
 359
 360 static int nonzero_sign_valid;
 361
 362 \f
 363 /* Record one modification to rtl structure
 364    to be undone by storing old_contents into *where.  */
 365
 366 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 367
 368 struct undo
 369 {
 370   struct undo *next;
 371   enum undo_kind kind;
 372   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 373   union { rtx *r; int *i; struct insn_link **l; } where;
 374 };
 375
 376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 377    num_undo says how many are currently recorded.
 378
 379    other_insn is nonzero if we have modified some other insn in the process
 380    of working on subst_insn.  It must be verified too.  */
 381
 382 struct undobuf
 383 {
 384   struct undo *undos;
 385   struct undo *frees;
 386   rtx other_insn;
 387 };
 388
 389 static struct undobuf undobuf;
 390
 391 /* Number of times the pseudo being substituted for
 392    was found and replaced.  */
 393
 394 static int n_occurrences;
 395
 396 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 397                                          enum machine_mode,
 398                                          unsigned HOST_WIDE_INT,
 399                                          unsigned HOST_WIDE_INT *);
 400 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                                 enum machine_mode,
 402                                                 unsigned int, unsigned int *);
 403 static void do_SUBST (rtx *, rtx);
 404 static void do_SUBST_INT (int *, int);
 405 static void init_reg_last (void);
 406 static void setup_incoming_promotions (rtx);
 407 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 408 static int cant_combine_insn_p (rtx);
 409 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 410 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 411 static int contains_muldiv (rtx);
 412 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 413 static void undo_all (void);
 414 static void undo_commit (void);
 415 static rtx *find_split_point (rtx *, rtx, bool);
 416 static rtx subst (rtx, rtx, rtx, int, int, int);
 417 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 418 static rtx simplify_if_then_else (rtx);
 419 static rtx simplify_set (rtx);
 420 static rtx simplify_logical (rtx);
 421 static rtx expand_compound_operation (rtx);
 422 static const_rtx expand_field_assignment (const_rtx);
 423 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 424                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 425 static rtx extract_left_shift (rtx, int);
 426 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 427                               unsigned HOST_WIDE_INT *);
 428 static rtx canon_reg_for_combine (rtx, rtx);
 429 static rtx force_to_mode (rtx, enum machine_mode,
 430                           unsigned HOST_WIDE_INT, int);
 431 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 432 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 433 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 434 static rtx make_field_assignment (rtx);
 435 static rtx apply_distributive_law (rtx);
 436 static rtx distribute_and_simplify_rtx (rtx, int);
 437 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 438                                      unsigned HOST_WIDE_INT);
 439 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 440                                    unsigned HOST_WIDE_INT);
 441 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 442                             HOST_WIDE_INT, enum machine_mode, int *);
 443 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 444 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 445                                  int);
 446 static int recog_for_combine (rtx *, rtx, rtx *);
 447 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 448 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 449 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 450 static void update_table_tick (rtx);
 451 static void record_value_for_reg (rtx, rtx, rtx);
 452 static void check_promoted_subreg (rtx, rtx);
 453 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 454 static void record_dead_and_set_regs (rtx);
 455 static int get_last_value_validate (rtx *, rtx, int, int);
 456 static rtx get_last_value (const_rtx);
 457 static int use_crosses_set_p (const_rtx, int);
 458 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 459 static int reg_dead_at_p (rtx, rtx);
 460 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 461 static int reg_bitfield_target_p (rtx, rtx);
 462 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 463 static void distribute_links (struct insn_link *);
 464 static void mark_used_regs_combine (rtx);
 465 static void record_promoted_value (rtx, rtx);
 466 static int unmentioned_reg_p_1 (rtx *, void *);
 467 static bool unmentioned_reg_p (rtx, rtx);
 468 static int record_truncated_value (rtx *, void *);
 469 static void record_truncated_values (rtx *, void *);
 470 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 471 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 472 \f
 473
 474 /* It is not safe to use ordinary gen_lowpart in combine.
 475    See comments in gen_lowpart_for_combine.  */
 476 #undef RTL_HOOKS_GEN_LOWPART
 477 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 478
 479 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 482
 483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 484 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 485
 486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 488
 489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 491
 492 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 493
 494 \f
 495 /* Convenience wrapper for the canonicalize_comparison target hook.
 496    Target hooks cannot use enum rtx_code.  */
 497 static inline void
 498 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 499                                 bool op0_preserve_value)
 500 {
 501   int code_int = (int)*code;
 502   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 503   *code = (enum rtx_code)code_int;
 504 }
 505
 506 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 507    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 508    This is a wrapper around split_insns which ensures that the
 509    reg_stat vector is made larger if the splitter creates a new
 510    register.  */
 511
 512 static rtx
 513 combine_split_insns (rtx pattern, rtx insn)
 514 {
 515   rtx ret;
 516   unsigned int nregs;
 517
 518   ret = split_insns (pattern, insn);
 519   nregs = max_reg_num ();
 520   if (nregs > reg_stat.length ())
 521     reg_stat.safe_grow_cleared (nregs);
 522   return ret;
 523 }
 524
 525 /* This is used by find_single_use to locate an rtx in LOC that
 526    contains exactly one use of DEST, which is typically either a REG
 527    or CC0.  It returns a pointer to the innermost rtx expression
 528    containing DEST.  Appearances of DEST that are being used to
 529    totally replace it are not counted.  */
 530
 531 static rtx *
 532 find_single_use_1 (rtx dest, rtx *loc)
 533 {
 534   rtx x = *loc;
 535   enum rtx_code code = GET_CODE (x);
 536   rtx *result = NULL;
 537   rtx *this_result;
 538   int i;
 539   const char *fmt;
 540
 541   switch (code)
 542     {
 543     case CONST:
 544     case LABEL_REF:
 545     case SYMBOL_REF:
 546     CASE_CONST_ANY:
 547     case CLOBBER:
 548       return 0;
 549
 550     case SET:
 551       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 552          of a REG that occupies all of the REG, the insn uses DEST if
 553          it is mentioned in the destination or the source.  Otherwise, we
 554          need just check the source.  */
 555       if (GET_CODE (SET_DEST (x)) != CC0
 556           && GET_CODE (SET_DEST (x)) != PC
 557           && !REG_P (SET_DEST (x))
 558           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 559                 && REG_P (SUBREG_REG (SET_DEST (x)))
 560                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 561                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 562                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 563                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 564         break;
 565
 566       return find_single_use_1 (dest, &SET_SRC (x));
 567
 568     case MEM:
 569     case SUBREG:
 570       return find_single_use_1 (dest, &XEXP (x, 0));
 571
 572     default:
 573       break;
 574     }
 575
 576   /* If it wasn't one of the common cases above, check each expression and
 577      vector of this code.  Look for a unique usage of DEST.  */
 578
 579   fmt = GET_RTX_FORMAT (code);
 580   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 581     {
 582       if (fmt[i] == 'e')
 583         {
 584           if (dest == XEXP (x, i)
 585               || (REG_P (dest) && REG_P (XEXP (x, i))
 586                   && REGNO (dest) == REGNO (XEXP (x, i))))
 587             this_result = loc;
 588           else
 589             this_result = find_single_use_1 (dest, &XEXP (x, i));
 590
 591           if (result == NULL)
 592             result = this_result;
 593           else if (this_result)
 594             /* Duplicate usage.  */
 595             return NULL;
 596         }
 597       else if (fmt[i] == 'E')
 598         {
 599           int j;
 600
 601           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 602             {
 603               if (XVECEXP (x, i, j) == dest
 604                   || (REG_P (dest)
 605                       && REG_P (XVECEXP (x, i, j))
 606                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 607                 this_result = loc;
 608               else
 609                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 610
 611               if (result == NULL)
 612                 result = this_result;
 613               else if (this_result)
 614                 return NULL;
 615             }
 616         }
 617     }
 618
 619   return result;
 620 }
 621
 622
 623 /* See if DEST, produced in INSN, is used only a single time in the
 624    sequel.  If so, return a pointer to the innermost rtx expression in which
 625    it is used.
 626
 627    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 628
 629    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 630    care about REG_DEAD notes or LOG_LINKS.
 631
 632    Otherwise, we find the single use by finding an insn that has a
 633    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 634    only referenced once in that insn, we know that it must be the first
 635    and last insn referencing DEST.  */
 636
 637 static rtx *
 638 find_single_use (rtx dest, rtx insn, rtx *ploc)
 639 {
 640   basic_block bb;
 641   rtx next;
 642   rtx *result;
 643   struct insn_link *link;
 644
 645 #ifdef HAVE_cc0
 646   if (dest == cc0_rtx)
 647     {
 648       next = NEXT_INSN (insn);
 649       if (next == 0
 650           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 651         return 0;
 652
 653       result = find_single_use_1 (dest, &PATTERN (next));
 654       if (result && ploc)
 655         *ploc = next;
 656       return result;
 657     }
 658 #endif
 659
 660   if (!REG_P (dest))
 661     return 0;
 662
 663   bb = BLOCK_FOR_INSN (insn);
 664   for (next = NEXT_INSN (insn);
 665        next && BLOCK_FOR_INSN (next) == bb;
 666        next = NEXT_INSN (next))
 667     if (INSN_P (next) && dead_or_set_p (next, dest))
 668       {
 669         FOR_EACH_LOG_LINK (link, next)
 670           if (link->insn == insn)
 671             break;
 672
 673         if (link)
 674           {
 675             result = find_single_use_1 (dest, &PATTERN (next));
 676             if (ploc)
 677               *ploc = next;
 678             return result;
 679           }
 680       }
 681
 682   return 0;
 683 }
 684 \f
 685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 686    insn.  The substitution can be undone by undo_all.  If INTO is already
 687    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 688    also call SUBST, we have to compute it before we put anything into
 689    the undo table.  */
 690
 691 static void
 692 do_SUBST (rtx *into, rtx newval)
 693 {
 694   struct undo *buf;
 695   rtx oldval = *into;
 696
 697   if (oldval == newval)
 698     return;
 699
 700   /* We'd like to catch as many invalid transformations here as
 701      possible.  Unfortunately, there are way too many mode changes
 702      that are perfectly valid, so we'd waste too much effort for
 703      little gain doing the checks here.  Focus on catching invalid
 704      transformations involving integer constants.  */
 705   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 706       && CONST_INT_P (newval))
 707     {
 708       /* Sanity check that we're replacing oldval with a CONST_INT
 709          that is a valid sign-extension for the original mode.  */
 710       gcc_assert (INTVAL (newval)
 711                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 712
 713       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 714          CONST_INT is not valid, because after the replacement, the
 715          original mode would be gone.  Unfortunately, we can't tell
 716          when do_SUBST is called to replace the operand thereof, so we
 717          perform this test on oldval instead, checking whether an
 718          invalid replacement took place before we got here.  */
 719       gcc_assert (!(GET_CODE (oldval) == SUBREG
 720                     && CONST_INT_P (SUBREG_REG (oldval))));
 721       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 722                     && CONST_INT_P (XEXP (oldval, 0))));
 723     }
 724
 725   if (undobuf.frees)
 726     buf = undobuf.frees, undobuf.frees = buf->next;
 727   else
 728     buf = XNEW (struct undo);
 729
 730   buf->kind = UNDO_RTX;
 731   buf->where.r = into;
 732   buf->old_contents.r = oldval;
 733   *into = newval;
 734
 735   buf->next = undobuf.undos, undobuf.undos = buf;
 736 }
 737
 738 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 739
 740 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 741    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 742    not safe.  */
 743
 744 static void
 745 do_SUBST_INT (int *into, int newval)
 746 {
 747   struct undo *buf;
 748   int oldval = *into;
 749
 750   if (oldval == newval)
 751     return;
 752
 753   if (undobuf.frees)
 754     buf = undobuf.frees, undobuf.frees = buf->next;
 755   else
 756     buf = XNEW (struct undo);
 757
 758   buf->kind = UNDO_INT;
 759   buf->where.i = into;
 760   buf->old_contents.i = oldval;
 761   *into = newval;
 762
 763   buf->next = undobuf.undos, undobuf.undos = buf;
 764 }
 765
 766 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 767
 768 /* Similar to SUBST, but just substitute the mode.  This is used when
 769    changing the mode of a pseudo-register, so that any other
 770    references to the entry in the regno_reg_rtx array will change as
 771    well.  */
 772
 773 static void
 774 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 775 {
 776   struct undo *buf;
 777   enum machine_mode oldval = GET_MODE (*into);
 778
 779   if (oldval == newval)
 780     return;
 781
 782   if (undobuf.frees)
 783     buf = undobuf.frees, undobuf.frees = buf->next;
 784   else
 785     buf = XNEW (struct undo);
 786
 787   buf->kind = UNDO_MODE;
 788   buf->where.r = into;
 789   buf->old_contents.m = oldval;
 790   adjust_reg_mode (*into, newval);
 791
 792   buf->next = undobuf.undos, undobuf.undos = buf;
 793 }
 794
 795 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 796
 797 #ifndef HAVE_cc0
 798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 799
 800 static void
 801 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 802 {
 803   struct undo *buf;
 804   struct insn_link * oldval = *into;
 805
 806   if (oldval == newval)
 807     return;
 808
 809   if (undobuf.frees)
 810     buf = undobuf.frees, undobuf.frees = buf->next;
 811   else
 812     buf = XNEW (struct undo);
 813
 814   buf->kind = UNDO_LINKS;
 815   buf->where.l = into;
 816   buf->old_contents.l = oldval;
 817   *into = newval;
 818
 819   buf->next = undobuf.undos, undobuf.undos = buf;
 820 }
 821
 822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 823 #endif
 824 \f
 825 /* Subroutine of try_combine.  Determine whether the replacement patterns
 826    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 827    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 828    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 829    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 830    of all the instructions can be estimated and the replacements are more
 831    expensive than the original sequence.  */
 832
 833 static bool
 834 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 835                        rtx newi2pat, rtx newotherpat)
 836 {
 837   int i0_cost, i1_cost, i2_cost, i3_cost;
 838   int new_i2_cost, new_i3_cost;
 839   int old_cost, new_cost;
 840
 841   /* Lookup the original insn_rtx_costs.  */
 842   i2_cost = INSN_COST (i2);
 843   i3_cost = INSN_COST (i3);
 844
 845   if (i1)
 846     {
 847       i1_cost = INSN_COST (i1);
 848       if (i0)
 849         {
 850           i0_cost = INSN_COST (i0);
 851           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 852                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 853         }
 854       else
 855         {
 856           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 857                       ? i1_cost + i2_cost + i3_cost : 0);
 858           i0_cost = 0;
 859         }
 860     }
 861   else
 862     {
 863       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 864       i1_cost = i0_cost = 0;
 865     }
 866
 867   /* Calculate the replacement insn_rtx_costs.  */
 868   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 869   if (newi2pat)
 870     {
 871       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 872       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 873                  ? new_i2_cost + new_i3_cost : 0;
 874     }
 875   else
 876     {
 877       new_cost = new_i3_cost;
 878       new_i2_cost = 0;
 879     }
 880
 881   if (undobuf.other_insn)
 882     {
 883       int old_other_cost, new_other_cost;
 884
 885       old_other_cost = INSN_COST (undobuf.other_insn);
 886       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 887       if (old_other_cost > 0 && new_other_cost > 0)
 888         {
 889           old_cost += old_other_cost;
 890           new_cost += new_other_cost;
 891         }
 892       else
 893         old_cost = 0;
 894     }
 895
 896   /* Disallow this combination if both new_cost and old_cost are greater than
 897      zero, and new_cost is greater than old cost.  */
 898   if (old_cost > 0 && new_cost > old_cost)
 899     {
 900       if (dump_file)
 901         {
 902           if (i0)
 903             {
 904               fprintf (dump_file,
 905                        "rejecting combination of insns %d, %d, %d and %d\n",
 906                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 907                        INSN_UID (i3));
 908               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 909                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 910             }
 911           else if (i1)
 912             {
 913               fprintf (dump_file,
 914                        "rejecting combination of insns %d, %d and %d\n",
 915                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 916               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 917                        i1_cost, i2_cost, i3_cost, old_cost);
 918             }
 919           else
 920             {
 921               fprintf (dump_file,
 922                        "rejecting combination of insns %d and %d\n",
 923                        INSN_UID (i2), INSN_UID (i3));
 924               fprintf (dump_file, "original costs %d + %d = %d\n",
 925                        i2_cost, i3_cost, old_cost);
 926             }
 927
 928           if (newi2pat)
 929             {
 930               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 931                        new_i2_cost, new_i3_cost, new_cost);
 932             }
 933           else
 934             fprintf (dump_file, "replacement cost %d\n", new_cost);
 935         }
 936
 937       return false;
 938     }
 939
 940   /* Update the uid_insn_cost array with the replacement costs.  */
 941   INSN_COST (i2) = new_i2_cost;
 942   INSN_COST (i3) = new_i3_cost;
 943   if (i1)
 944     {
 945       INSN_COST (i1) = 0;
 946       if (i0)
 947         INSN_COST (i0) = 0;
 948     }
 949
 950   return true;
 951 }
 952
 953
 954 /* Delete any insns that copy a register to itself.  */
 955
 956 static void
 957 delete_noop_moves (void)
 958 {
 959   rtx insn, next;
 960   basic_block bb;
 961
 962   FOR_EACH_BB (bb)
 963     {
 964       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 965         {
 966           next = NEXT_INSN (insn);
 967           if (INSN_P (insn) && noop_move_p (insn))
 968             {
 969               if (dump_file)
 970                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 971
 972               delete_insn_and_edges (insn);
 973             }
 974         }
 975     }
 976 }
 977
 978 \f
 979 /* Fill in log links field for all insns.  */
 980
 981 static void
 982 create_log_links (void)
 983 {
 984   basic_block bb;
 985   rtx *next_use, insn;
 986   df_ref *def_vec, *use_vec;
 987
 988   next_use = XCNEWVEC (rtx, max_reg_num ());
 989
 990   /* Pass through each block from the end, recording the uses of each
 991      register and establishing log links when def is encountered.
 992      Note that we do not clear next_use array in order to save time,
 993      so we have to test whether the use is in the same basic block as def.
 994
 995      There are a few cases below when we do not consider the definition or
 996      usage -- these are taken from original flow.c did. Don't ask me why it is
 997      done this way; I don't know and if it works, I don't want to know.  */
 998
 999   FOR_EACH_BB (bb)
1000     {
1001       FOR_BB_INSNS_REVERSE (bb, insn)
1002         {
1003           if (!NONDEBUG_INSN_P (insn))
1004             continue;
1005
1006           /* Log links are created only once.  */
1007           gcc_assert (!LOG_LINKS (insn));
1008
1009           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1010             {
1011               df_ref def = *def_vec;
1012               int regno = DF_REF_REGNO (def);
1013               rtx use_insn;
1014
1015               if (!next_use[regno])
1016                 continue;
1017
1018               /* Do not consider if it is pre/post modification in MEM.  */
1019               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1020                 continue;
1021
1022               /* Do not make the log link for frame pointer.  */
1023               if ((regno == FRAME_POINTER_REGNUM
1024                    && (! reload_completed || frame_pointer_needed))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026                   || (regno == HARD_FRAME_POINTER_REGNUM
1027                       && (! reload_completed || frame_pointer_needed))
1028 #endif
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 #endif
1032                   )
1033                 continue;
1034
1035               use_insn = next_use[regno];
1036               if (BLOCK_FOR_INSN (use_insn) == bb)
1037                 {
1038                   /* flow.c claimed:
1039
1040                      We don't build a LOG_LINK for hard registers contained
1041                      in ASM_OPERANDs.  If these registers get replaced,
1042                      we might wind up changing the semantics of the insn,
1043                      even if reload can make what appear to be valid
1044                      assignments later.  */
1045                   if (regno >= FIRST_PSEUDO_REGISTER
1046                       || asm_noperands (PATTERN (use_insn)) < 0)
1047                     {
1048                       /* Don't add duplicate links between instructions.  */
1049                       struct insn_link *links;
1050                       FOR_EACH_LOG_LINK (links, use_insn)
1051                         if (insn == links->insn)
1052                           break;
1053
1054                       if (!links)
1055                         LOG_LINKS (use_insn)
1056                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1057                     }
1058                 }
1059               next_use[regno] = NULL_RTX;
1060             }
1061
1062           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1063             {
1064               df_ref use = *use_vec;
1065               int regno = DF_REF_REGNO (use);
1066
1067               /* Do not consider the usage of the stack pointer
1068                  by function call.  */
1069               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1070                 continue;
1071
1072               next_use[regno] = insn;
1073             }
1074         }
1075     }
1076
1077   free (next_use);
1078 }
1079
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1081    true if we found a LOG_LINK that proves that A feeds B.  This only works
1082    if there are no instructions between A and B which could have a link
1083    depending on A, since in that case we would not record a link for B.
1084    We also check the implicit dependency created by a cc0 setter/user
1085    pair.  */
1086
1087 static bool
1088 insn_a_feeds_b (rtx a, rtx b)
1089 {
1090   struct insn_link *links;
1091   FOR_EACH_LOG_LINK (links, b)
1092     if (links->insn == a)
1093       return true;
1094 #ifdef HAVE_cc0
1095   if (sets_cc0_p (a))
1096     return true;
1097 #endif
1098   return false;
1099 }
1100 \f
1101 /* Main entry point for combiner.  F is the first insn of the function.
1102    NREGS is the first unused pseudo-reg number.
1103
1104    Return nonzero if the combiner has turned an indirect jump
1105    instruction into a direct jump.  */
1106 static int
1107 combine_instructions (rtx f, unsigned int nregs)
1108 {
1109   rtx insn, next;
1110 #ifdef HAVE_cc0
1111   rtx prev;
1112 #endif
1113   struct insn_link *links, *nextlinks;
1114   rtx first;
1115   basic_block last_bb;
1116
1117   int new_direct_jump_p = 0;
1118
1119   for (first = f; first && !INSN_P (first); )
1120     first = NEXT_INSN (first);
1121   if (!first)
1122     return 0;
1123
1124   combine_attempts = 0;
1125   combine_merges = 0;
1126   combine_extras = 0;
1127   combine_successes = 0;
1128
1129   rtl_hooks = combine_rtl_hooks;
1130
1131   reg_stat.safe_grow_cleared (nregs);
1132
1133   init_recog_no_volatile ();
1134
1135   /* Allocate array for insn info.  */
1136   max_uid_known = get_max_uid ();
1137   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139   gcc_obstack_init (&insn_link_obstack);
1140
1141   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1142
1143   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1144      problems when, for example, we have j <<= 1 in a loop.  */
1145
1146   nonzero_sign_valid = 0;
1147   label_tick = label_tick_ebb_start = 1;
1148
1149   /* Scan all SETs and see if we can deduce anything about what
1150      bits are known to be zero for some registers and how many copies
1151      of the sign bit are known to exist for those registers.
1152
1153      Also set any known values so that we can use it while searching
1154      for what bits are known to be set.  */
1155
1156   setup_incoming_promotions (first);
1157   /* Allow the entry block and the first block to fall into the same EBB.
1158      Conceptually the incoming promotions are assigned to the entry block.  */
1159   last_bb = ENTRY_BLOCK_PTR;
1160
1161   create_log_links ();
1162   FOR_EACH_BB (this_basic_block)
1163     {
1164       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165       last_call_luid = 0;
1166       mem_last_set = -1;
1167
1168       label_tick++;
1169       if (!single_pred_p (this_basic_block)
1170           || single_pred (this_basic_block) != last_bb)
1171         label_tick_ebb_start = label_tick;
1172       last_bb = this_basic_block;
1173
1174       FOR_BB_INSNS (this_basic_block, insn)
1175         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1176           {
1177 #ifdef AUTO_INC_DEC
1178             rtx links;
1179 #endif
1180
1181             subst_low_luid = DF_INSN_LUID (insn);
1182             subst_insn = insn;
1183
1184             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1185                          insn);
1186             record_dead_and_set_regs (insn);
1187
1188 #ifdef AUTO_INC_DEC
1189             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190               if (REG_NOTE_KIND (links) == REG_INC)
1191                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1192                                                   insn);
1193 #endif
1194
1195             /* Record the current insn_rtx_cost of this instruction.  */
1196             if (NONJUMP_INSN_P (insn))
1197               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198                                                 optimize_this_for_speed_p);
1199             if (dump_file)
1200               fprintf(dump_file, "insn_cost %d: %d\n",
1201                     INSN_UID (insn), INSN_COST (insn));
1202           }
1203     }
1204
1205   nonzero_sign_valid = 1;
1206
1207   /* Now scan all the insns in forward order.  */
1208   label_tick = label_tick_ebb_start = 1;
1209   init_reg_last ();
1210   setup_incoming_promotions (first);
1211   last_bb = ENTRY_BLOCK_PTR;
1212
1213   FOR_EACH_BB (this_basic_block)
1214     {
1215       rtx last_combined_insn = NULL_RTX;
1216       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217       last_call_luid = 0;
1218       mem_last_set = -1;
1219
1220       label_tick++;
1221       if (!single_pred_p (this_basic_block)
1222           || single_pred (this_basic_block) != last_bb)
1223         label_tick_ebb_start = label_tick;
1224       last_bb = this_basic_block;
1225
1226       rtl_profile_for_bb (this_basic_block);
1227       for (insn = BB_HEAD (this_basic_block);
1228            insn != NEXT_INSN (BB_END (this_basic_block));
1229            insn = next ? next : NEXT_INSN (insn))
1230         {
1231           next = 0;
1232           if (NONDEBUG_INSN_P (insn))
1233             {
1234               while (last_combined_insn
1235                      && INSN_DELETED_P (last_combined_insn))
1236                 last_combined_insn = PREV_INSN (last_combined_insn);
1237               if (last_combined_insn == NULL_RTX
1238                   || BARRIER_P (last_combined_insn)
1239                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241                 last_combined_insn = insn;
1242
1243               /* See if we know about function return values before this
1244                  insn based upon SUBREG flags.  */
1245               check_promoted_subreg (insn, PATTERN (insn));
1246
1247               /* See if we can find hardregs and subreg of pseudos in
1248                  narrower modes.  This could help turning TRUNCATEs
1249                  into SUBREGs.  */
1250               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1251
1252               /* Try this insn with each insn it links back to.  */
1253
1254               FOR_EACH_LOG_LINK (links, insn)
1255                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256                                          NULL_RTX, &new_direct_jump_p,
1257                                          last_combined_insn)) != 0)
1258                   goto retry;
1259
1260               /* Try each sequence of three linked insns ending with this one.  */
1261
1262               FOR_EACH_LOG_LINK (links, insn)
1263                 {
1264                   rtx link = links->insn;
1265
1266                   /* If the linked insn has been replaced by a note, then there
1267                      is no point in pursuing this chain any further.  */
1268                   if (NOTE_P (link))
1269                     continue;
1270
1271                   FOR_EACH_LOG_LINK (nextlinks, link)
1272                     if ((next = try_combine (insn, link, nextlinks->insn,
1273                                              NULL_RTX, &new_direct_jump_p,
1274                                              last_combined_insn)) != 0)
1275                       goto retry;
1276                 }
1277
1278 #ifdef HAVE_cc0
1279               /* Try to combine a jump insn that uses CC0
1280                  with a preceding insn that sets CC0, and maybe with its
1281                  logical predecessor as well.
1282                  This is how we make decrement-and-branch insns.
1283                  We need this special code because data flow connections
1284                  via CC0 do not get entered in LOG_LINKS.  */
1285
1286               if (JUMP_P (insn)
1287                   && (prev = prev_nonnote_insn (insn)) != 0
1288                   && NONJUMP_INSN_P (prev)
1289                   && sets_cc0_p (PATTERN (prev)))
1290                 {
1291                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292                                            &new_direct_jump_p,
1293                                            last_combined_insn)) != 0)
1294                     goto retry;
1295
1296                   FOR_EACH_LOG_LINK (nextlinks, prev)
1297                     if ((next = try_combine (insn, prev, nextlinks->insn,
1298                                              NULL_RTX, &new_direct_jump_p,
1299                                              last_combined_insn)) != 0)
1300                       goto retry;
1301                 }
1302
1303               /* Do the same for an insn that explicitly references CC0.  */
1304               if (NONJUMP_INSN_P (insn)
1305                   && (prev = prev_nonnote_insn (insn)) != 0
1306                   && NONJUMP_INSN_P (prev)
1307                   && sets_cc0_p (PATTERN (prev))
1308                   && GET_CODE (PATTERN (insn)) == SET
1309                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1310                 {
1311                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1312                                            &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315
1316                   FOR_EACH_LOG_LINK (nextlinks, prev)
1317                     if ((next = try_combine (insn, prev, nextlinks->insn,
1318                                              NULL_RTX, &new_direct_jump_p,
1319                                              last_combined_insn)) != 0)
1320                       goto retry;
1321                 }
1322
1323               /* Finally, see if any of the insns that this insn links to
1324                  explicitly references CC0.  If so, try this insn, that insn,
1325                  and its predecessor if it sets CC0.  */
1326               FOR_EACH_LOG_LINK (links, insn)
1327                 if (NONJUMP_INSN_P (links->insn)
1328                     && GET_CODE (PATTERN (links->insn)) == SET
1329                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330                     && (prev = prev_nonnote_insn (links->insn)) != 0
1331                     && NONJUMP_INSN_P (prev)
1332                     && sets_cc0_p (PATTERN (prev))
1333                     && (next = try_combine (insn, links->insn,
1334                                             prev, NULL_RTX, &new_direct_jump_p,
1335                                             last_combined_insn)) != 0)
1336                   goto retry;
1337 #endif
1338
1339               /* Try combining an insn with two different insns whose results it
1340                  uses.  */
1341               FOR_EACH_LOG_LINK (links, insn)
1342                 for (nextlinks = links->next; nextlinks;
1343                      nextlinks = nextlinks->next)
1344                   if ((next = try_combine (insn, links->insn,
1345                                            nextlinks->insn, NULL_RTX,
1346                                            &new_direct_jump_p,
1347                                            last_combined_insn)) != 0)
1348                     goto retry;
1349
1350               /* Try four-instruction combinations.  */
1351               FOR_EACH_LOG_LINK (links, insn)
1352                 {
1353                   struct insn_link *next1;
1354                   rtx link = links->insn;
1355
1356                   /* If the linked insn has been replaced by a note, then there
1357                      is no point in pursuing this chain any further.  */
1358                   if (NOTE_P (link))
1359                     continue;
1360
1361                   FOR_EACH_LOG_LINK (next1, link)
1362                     {
1363                       rtx link1 = next1->insn;
1364                       if (NOTE_P (link1))
1365                         continue;
1366                       /* I0 -> I1 -> I2 -> I3.  */
1367                       FOR_EACH_LOG_LINK (nextlinks, link1)
1368                         if ((next = try_combine (insn, link, link1,
1369                                                  nextlinks->insn,
1370                                                  &new_direct_jump_p,
1371                                                  last_combined_insn)) != 0)
1372                           goto retry;
1373                       /* I0, I1 -> I2, I2 -> I3.  */
1374                       for (nextlinks = next1->next; nextlinks;
1375                            nextlinks = nextlinks->next)
1376                         if ((next = try_combine (insn, link, link1,
1377                                                  nextlinks->insn,
1378                                                  &new_direct_jump_p,
1379                                                  last_combined_insn)) != 0)
1380                           goto retry;
1381                     }
1382
1383                   for (next1 = links->next; next1; next1 = next1->next)
1384                     {
1385                       rtx link1 = next1->insn;
1386                       if (NOTE_P (link1))
1387                         continue;
1388                       /* I0 -> I2; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                       /* I0 -> I1; I1, I2 -> I3.  */
1396                       FOR_EACH_LOG_LINK (nextlinks, link1)
1397                         if ((next = try_combine (insn, link, link1,
1398                                                  nextlinks->insn,
1399                                                  &new_direct_jump_p,
1400                                                  last_combined_insn)) != 0)
1401                           goto retry;
1402                     }
1403                 }
1404
1405               /* Try this insn with each REG_EQUAL note it links back to.  */
1406               FOR_EACH_LOG_LINK (links, insn)
1407                 {
1408                   rtx set, note;
1409                   rtx temp = links->insn;
1410                   if ((set = single_set (temp)) != 0
1411                       && (note = find_reg_equal_equiv_note (temp)) != 0
1412                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413                       /* Avoid using a register that may already been marked
1414                          dead by an earlier instruction.  */
1415                       && ! unmentioned_reg_p (note, SET_SRC (set))
1416                       && (GET_MODE (note) == VOIDmode
1417                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1419                     {
1420                       /* Temporarily replace the set's source with the
1421                          contents of the REG_EQUAL note.  The insn will
1422                          be deleted or recognized by try_combine.  */
1423                       rtx orig = SET_SRC (set);
1424                       SET_SRC (set) = note;
1425                       i2mod = temp;
1426                       i2mod_old_rhs = copy_rtx (orig);
1427                       i2mod_new_rhs = copy_rtx (note);
1428                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1429                                           &new_direct_jump_p,
1430                                           last_combined_insn);
1431                       i2mod = NULL_RTX;
1432                       if (next)
1433                         goto retry;
1434                       SET_SRC (set) = orig;
1435                     }
1436                 }
1437
1438               if (!NOTE_P (insn))
1439                 record_dead_and_set_regs (insn);
1440
1441             retry:
1442               ;
1443             }
1444         }
1445     }
1446
1447   default_rtl_profile ();
1448   clear_bb_flags ();
1449   new_direct_jump_p |= purge_all_dead_edges ();
1450   delete_noop_moves ();
1451
1452   /* Clean up.  */
1453   obstack_free (&insn_link_obstack, NULL);
1454   free (uid_log_links);
1455   free (uid_insn_cost);
1456   reg_stat.release ();
1457
1458   {
1459     struct undo *undo, *next;
1460     for (undo = undobuf.frees; undo; undo = next)
1461       {
1462         next = undo->next;
1463         free (undo);
1464       }
1465     undobuf.frees = 0;
1466   }
1467
1468   total_attempts += combine_attempts;
1469   total_merges += combine_merges;
1470   total_extras += combine_extras;
1471   total_successes += combine_successes;
1472
1473   nonzero_sign_valid = 0;
1474   rtl_hooks = general_rtl_hooks;
1475
1476   /* Make recognizer allow volatile MEMs again.  */
1477   init_recog ();
1478
1479   return new_direct_jump_p;
1480 }
1481
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1483
1484 static void
1485 init_reg_last (void)
1486 {
1487   unsigned int i;
1488   reg_stat_type *p;
1489
1490   FOR_EACH_VEC_ELT (reg_stat, i, p)
1491     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers.  */
1495
1496 static void
1497 setup_incoming_promotions (rtx first)
1498 {
1499   tree arg;
1500   bool strictly_local = false;
1501
1502   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503        arg = DECL_CHAIN (arg))
1504     {
1505       rtx x, reg = DECL_INCOMING_RTL (arg);
1506       int uns1, uns3;
1507       enum machine_mode mode1, mode2, mode3, mode4;
1508
1509       /* Only continue if the incoming argument is in a register.  */
1510       if (!REG_P (reg))
1511         continue;
1512
1513       /* Determine, if possible, whether all call sites of the current
1514          function lie within the current compilation unit.  (This does
1515          take into account the exporting of a function via taking its
1516          address, and so forth.)  */
1517       strictly_local = cgraph_local_info (current_function_decl)->local;
1518
1519       /* The mode and signedness of the argument before any promotions happen
1520          (equal to the mode of the pseudo holding it at that stage).  */
1521       mode1 = TYPE_MODE (TREE_TYPE (arg));
1522       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1523
1524       /* The mode and signedness of the argument after any source language and
1525          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1526       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1528
1529       /* The mode and signedness of the argument as it is actually passed,
1530          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1531       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532                                      TREE_TYPE (cfun->decl), 0);
1533
1534       /* The mode of the register in which the argument is being passed.  */
1535       mode4 = GET_MODE (reg);
1536
1537       /* Eliminate sign extensions in the callee when:
1538          (a) A mode promotion has occurred;  */
1539       if (mode1 == mode3)
1540         continue;
1541       /* (b) The mode of the register is the same as the mode of
1542              the argument as it is passed; */
1543       if (mode3 != mode4)
1544         continue;
1545       /* (c) There's no language level extension;  */
1546       if (mode1 == mode2)
1547         ;
1548       /* (c.1) All callers are from the current compilation unit.  If that's
1549          the case we don't have to rely on an ABI, we only have to know
1550          what we're generating right now, and we know that we will do the
1551          mode1 to mode2 promotion with the given sign.  */
1552       else if (!strictly_local)
1553         continue;
1554       /* (c.2) The combination of the two promotions is useful.  This is
1555          true when the signs match, or if the first promotion is unsigned.
1556          In the later case, (sign_extend (zero_extend x)) is the same as
1557          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1558       else if (uns1)
1559         uns3 = true;
1560       else if (uns3)
1561         continue;
1562
1563       /* Record that the value was promoted from mode1 to mode3,
1564          so that any sign extension at the head of the current
1565          function may be eliminated.  */
1566       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568       record_value_for_reg (reg, first, x);
1569     }
1570 }
1571
1572 /* Called via note_stores.  If X is a pseudo that is narrower than
1573    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1574
1575    If we are setting only a portion of X and we can't figure out what
1576    portion, assume all bits will be used since we don't know what will
1577    be happening.
1578
1579    Similarly, set how many bits of X are known to be copies of the sign bit
1580    at all locations in the function.  This is the smallest number implied
1581    by any set of X.  */
1582
1583 static void
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1585 {
1586   rtx insn = (rtx) data;
1587   unsigned int num;
1588
1589   if (REG_P (x)
1590       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591       /* If this register is undefined at the start of the file, we can't
1592          say what its contents were.  */
1593       && ! REGNO_REG_SET_P
1594            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1595       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1596     {
1597       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1598
1599       if (set == 0 || GET_CODE (set) == CLOBBER)
1600         {
1601           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602           rsp->sign_bit_copies = 1;
1603           return;
1604         }
1605
1606       /* If this register is being initialized using itself, and the
1607          register is uninitialized in this basic block, and there are
1608          no LOG_LINKS which set the register, then part of the
1609          register is uninitialized.  In that case we can't assume
1610          anything about the number of nonzero bits.
1611
1612          ??? We could do better if we checked this in
1613          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1614          could avoid making assumptions about the insn which initially
1615          sets the register, while still using the information in other
1616          insns.  We would have to be careful to check every insn
1617          involved in the combination.  */
1618
1619       if (insn
1620           && reg_referenced_p (x, PATTERN (insn))
1621           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1622                                REGNO (x)))
1623         {
1624           struct insn_link *link;
1625
1626           FOR_EACH_LOG_LINK (link, insn)
1627             if (dead_or_set_p (link->insn, x))
1628               break;
1629           if (!link)
1630             {
1631               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632               rsp->sign_bit_copies = 1;
1633               return;
1634             }
1635         }
1636
1637       /* If this is a complex assignment, see if we can convert it into a
1638          simple assignment.  */
1639       set = expand_field_assignment (set);
1640
1641       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642          set what we know about X.  */
1643
1644       if (SET_DEST (set) == x
1645           || (paradoxical_subreg_p (SET_DEST (set))
1646               && SUBREG_REG (SET_DEST (set)) == x))
1647         {
1648           rtx src = SET_SRC (set);
1649
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651           /* If X is narrower than a word and SRC is a non-negative
1652              constant that would appear negative in the mode of X,
1653              sign-extend it for use in reg_stat[].nonzero_bits because some
1654              machines (maybe most) will actually do the sign-extension
1655              and this is the conservative approach.
1656
1657              ??? For 2.5, try to tighten up the MD files in this regard
1658              instead of this kludge.  */
1659
1660           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661               && CONST_INT_P (src)
1662               && INTVAL (src) > 0
1663               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1665 #endif
1666
1667           /* Don't call nonzero_bits if it cannot change anything.  */
1668           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671           if (rsp->sign_bit_copies == 0
1672               || rsp->sign_bit_copies > num)
1673             rsp->sign_bit_copies = num;
1674         }
1675       else
1676         {
1677           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678           rsp->sign_bit_copies = 1;
1679         }
1680     }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1684    optionally insns that were previously combined into I3 or that will be
1685    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1686    INSN, SUCC, SUCC2, I3.
1687
1688    Return 0 if the combination is not allowed for any reason.
1689
1690    If the combination is allowed, *PDEST will be set to the single
1691    destination of INSN and *PSRC to the single source, and this function
1692    will return 1.  */
1693
1694 static int
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697                rtx *pdest, rtx *psrc)
1698 {
1699   int i;
1700   const_rtx set = 0;
1701   rtx src, dest;
1702   rtx p;
1703 #ifdef AUTO_INC_DEC
1704   rtx link;
1705 #endif
1706   bool all_adjacent = true;
1707   int (*is_volatile_p) (const_rtx);
1708
1709   if (succ)
1710     {
1711       if (succ2)
1712         {
1713           if (next_active_insn (succ2) != i3)
1714             all_adjacent = false;
1715           if (next_active_insn (succ) != succ2)
1716             all_adjacent = false;
1717         }
1718       else if (next_active_insn (succ) != i3)
1719         all_adjacent = false;
1720       if (next_active_insn (insn) != succ)
1721         all_adjacent = false;
1722     }
1723   else if (next_active_insn (insn) != i3)
1724     all_adjacent = false;
1725
1726   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727      or a PARALLEL consisting of such a SET and CLOBBERs.
1728
1729      If INSN has CLOBBER parallel parts, ignore them for our processing.
1730      By definition, these happen during the execution of the insn.  When it
1731      is merged with another insn, all bets are off.  If they are, in fact,
1732      needed and aren't also supplied in I3, they may be added by
1733      recog_for_combine.  Otherwise, it won't match.
1734
1735      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736      note.
1737
1738      Get the source and destination of INSN.  If more than one, can't
1739      combine.  */
1740
1741   if (GET_CODE (PATTERN (insn)) == SET)
1742     set = PATTERN (insn);
1743   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1745     {
1746       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1747         {
1748           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1749
1750           switch (GET_CODE (elt))
1751             {
1752             /* This is important to combine floating point insns
1753                for the SH4 port.  */
1754             case USE:
1755               /* Combining an isolated USE doesn't make sense.
1756                  We depend here on combinable_i3pat to reject them.  */
1757               /* The code below this loop only verifies that the inputs of
1758                  the SET in INSN do not change.  We call reg_set_between_p
1759                  to verify that the REG in the USE does not change between
1760                  I3 and INSN.
1761                  If the USE in INSN was for a pseudo register, the matching
1762                  insn pattern will likely match any register; combining this
1763                  with any other USE would only be safe if we knew that the
1764                  used registers have identical values, or if there was
1765                  something to tell them apart, e.g. different modes.  For
1766                  now, we forgo such complicated tests and simply disallow
1767                  combining of USES of pseudo registers with any other USE.  */
1768               if (REG_P (XEXP (elt, 0))
1769                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1770                 {
1771                   rtx i3pat = PATTERN (i3);
1772                   int i = XVECLEN (i3pat, 0) - 1;
1773                   unsigned int regno = REGNO (XEXP (elt, 0));
1774
1775                   do
1776                     {
1777                       rtx i3elt = XVECEXP (i3pat, 0, i);
1778
1779                       if (GET_CODE (i3elt) == USE
1780                           && REG_P (XEXP (i3elt, 0))
1781                           && (REGNO (XEXP (i3elt, 0)) == regno
1782                               ? reg_set_between_p (XEXP (elt, 0),
1783                                                    PREV_INSN (insn), i3)
1784                               : regno >= FIRST_PSEUDO_REGISTER))
1785                         return 0;
1786                     }
1787                   while (--i >= 0);
1788                 }
1789               break;
1790
1791               /* We can ignore CLOBBERs.  */
1792             case CLOBBER:
1793               break;
1794
1795             case SET:
1796               /* Ignore SETs whose result isn't used but not those that
1797                  have side-effects.  */
1798               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799                   && insn_nothrow_p (insn)
1800                   && !side_effects_p (elt))
1801                 break;
1802
1803               /* If we have already found a SET, this is a second one and
1804                  so we cannot combine with this insn.  */
1805               if (set)
1806                 return 0;
1807
1808               set = elt;
1809               break;
1810
1811             default:
1812               /* Anything else means we can't combine.  */
1813               return 0;
1814             }
1815         }
1816
1817       if (set == 0
1818           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819              so don't do anything with it.  */
1820           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1821         return 0;
1822     }
1823   else
1824     return 0;
1825
1826   if (set == 0)
1827     return 0;
1828
1829   /* The simplification in expand_field_assignment may call back to
1830      get_last_value, so set safe guard here.  */
1831   subst_low_luid = DF_INSN_LUID (insn);
1832
1833   set = expand_field_assignment (set);
1834   src = SET_SRC (set), dest = SET_DEST (set);
1835
1836   /* Don't eliminate a store in the stack pointer.  */
1837   if (dest == stack_pointer_rtx
1838       /* Don't combine with an insn that sets a register to itself if it has
1839          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1840       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841       /* Can't merge an ASM_OPERANDS.  */
1842       || GET_CODE (src) == ASM_OPERANDS
1843       /* Can't merge a function call.  */
1844       || GET_CODE (src) == CALL
1845       /* Don't eliminate a function call argument.  */
1846       || (CALL_P (i3)
1847           && (find_reg_fusage (i3, USE, dest)
1848               || (REG_P (dest)
1849                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850                   && global_regs[REGNO (dest)])))
1851       /* Don't substitute into an incremented register.  */
1852       || FIND_REG_INC_NOTE (i3, dest)
1853       || (succ && FIND_REG_INC_NOTE (succ, dest))
1854       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855       /* Don't substitute into a non-local goto, this confuses CFG.  */
1856       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857       /* Make sure that DEST is not used after SUCC but before I3.  */
1858       || (!all_adjacent
1859           && ((succ2
1860                && (reg_used_between_p (dest, succ2, i3)
1861                    || reg_used_between_p (dest, succ, succ2)))
1862               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863       /* Make sure that the value that is to be substituted for the register
1864          does not use any registers whose values alter in between.  However,
1865          If the insns are adjacent, a use can't cross a set even though we
1866          think it might (this can happen for a sequence of insns each setting
1867          the same destination; last_set of that register might point to
1868          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1869          equivalent to the memory so the substitution is valid even if there
1870          are intervening stores.  Also, don't move a volatile asm or
1871          UNSPEC_VOLATILE across any other insns.  */
1872       || (! all_adjacent
1873           && (((!MEM_P (src)
1874                 || ! find_reg_note (insn, REG_EQUIV, src))
1875                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877               || GET_CODE (src) == UNSPEC_VOLATILE))
1878       /* Don't combine across a CALL_INSN, because that would possibly
1879          change whether the life span of some REGs crosses calls or not,
1880          and it is a pain to update that information.
1881          Exception: if source is a constant, moving it later can't hurt.
1882          Accept that as a special case.  */
1883       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1884     return 0;
1885
1886   /* DEST must either be a REG or CC0.  */
1887   if (REG_P (dest))
1888     {
1889       /* If register alignment is being enforced for multi-word items in all
1890          cases except for parameters, it is possible to have a register copy
1891          insn referencing a hard register that is not allowed to contain the
1892          mode being copied and which would not be valid as an operand of most
1893          insns.  Eliminate this problem by not combining with such an insn.
1894
1895          Also, on some machines we don't want to extend the life of a hard
1896          register.  */
1897
1898       if (REG_P (src)
1899           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901               /* Don't extend the life of a hard register unless it is
1902                  user variable (if we have few registers) or it can't
1903                  fit into the desired register (meaning something special
1904                  is going on).
1905                  Also avoid substituting a return register into I3, because
1906                  reload can't handle a conflict with constraints of other
1907                  inputs.  */
1908               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1910         return 0;
1911     }
1912   else if (GET_CODE (dest) != CC0)
1913     return 0;
1914
1915
1916   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1919         {
1920           /* Don't substitute for a register intended as a clobberable
1921              operand.  */
1922           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923           if (rtx_equal_p (reg, dest))
1924             return 0;
1925
1926           /* If the clobber represents an earlyclobber operand, we must not
1927              substitute an expression containing the clobbered register.
1928              As we do not analyze the constraint strings here, we have to
1929              make the conservative assumption.  However, if the register is
1930              a fixed hard reg, the clobber cannot represent any operand;
1931              we leave it up to the machine description to either accept or
1932              reject use-and-clobber patterns.  */
1933           if (!REG_P (reg)
1934               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935               || !fixed_regs[REGNO (reg)])
1936             if (reg_overlap_mentioned_p (reg, src))
1937               return 0;
1938         }
1939
1940   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941      or not), reject, unless nothing volatile comes between it and I3 */
1942
1943   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1944     {
1945       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1946       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1947         return 0;
1948       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1949         return 0;
1950       /* We'll check insns between INSN and I3 below.  */
1951     }
1952
1953   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954      to be an explicit register variable, and was chosen for a reason.  */
1955
1956   if (GET_CODE (src) == ASM_OPERANDS
1957       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1958     return 0;
1959
1960   /* If INSN contains volatile references (specifically volatile MEMs),
1961      we cannot combine across any other volatile references.
1962      Even if INSN doesn't contain volatile references, any intervening
1963      volatile insn might affect machine state.  */
1964
1965   is_volatile_p = volatile_refs_p (PATTERN (insn))
1966     ? volatile_refs_p
1967     : volatile_insn_p;
1968
1969   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1971       return 0;
1972
1973   /* If INSN contains an autoincrement or autodecrement, make sure that
1974      register is not used between there and I3, and not already used in
1975      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1976      Also insist that I3 not be a jump; if it were one
1977      and the incremented register were spilled, we would lose.  */
1978
1979 #ifdef AUTO_INC_DEC
1980   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981     if (REG_NOTE_KIND (link) == REG_INC
1982         && (JUMP_P (i3)
1983             || reg_used_between_p (XEXP (link, 0), insn, i3)
1984             || (pred != NULL_RTX
1985                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986             || (pred2 != NULL_RTX
1987                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988             || (succ != NULL_RTX
1989                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990             || (succ2 != NULL_RTX
1991                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993       return 0;
1994 #endif
1995
1996 #ifdef HAVE_cc0
1997   /* Don't combine an insn that follows a CC0-setting insn.
1998      An insn that uses CC0 must not be separated from the one that sets it.
1999      We do, however, allow I2 to follow a CC0-setting insn if that insn
2000      is passed as I1; in that case it will be deleted also.
2001      We also allow combining in this case if all the insns are adjacent
2002      because that would leave the two CC0 insns adjacent as well.
2003      It would be more logical to test whether CC0 occurs inside I1 or I2,
2004      but that would be much slower, and this ought to be equivalent.  */
2005
2006   p = prev_nonnote_insn (insn);
2007   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008       && ! all_adjacent)
2009     return 0;
2010 #endif
2011
2012   /* If we get here, we have passed all the tests and the combination is
2013      to be allowed.  */
2014
2015   *pdest = dest;
2016   *psrc = src;
2017
2018   return 1;
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2023
2024    One problem is if I3 modifies its output, as opposed to replacing it
2025    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026    doing so would produce an insn that is not equivalent to the original insns.
2027
2028    Consider:
2029
2030          (set (reg:DI 101) (reg:DI 100))
2031          (set (subreg:SI (reg:DI 101) 0) <foo>)
2032
2033    This is NOT equivalent to:
2034
2035          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036                     (set (reg:DI 101) (reg:DI 100))])
2037
2038    Not only does this modify 100 (in which case it might still be valid
2039    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2040
2041    We can also run into a problem if I2 sets a register that I1
2042    uses and I1 gets directly substituted into I3 (not via I2).  In that
2043    case, we would be getting the wrong value of I2DEST into I3, so we
2044    must reject the combination.  This case occurs when I2 and I1 both
2045    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047    of a SET must prevent combination from occurring.  The same situation
2048    can occur for I0, in which case I0_NOT_IN_SRC is set.
2049
2050    Before doing the above check, we first try to expand a field assignment
2051    into a set of logical operations.
2052
2053    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054    we place a register that is both set and used within I3.  If more than one
2055    such register is detected, we fail.
2056
2057    Return 1 if the combination is valid, zero otherwise.  */
2058
2059 static int
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2062 {
2063   rtx x = *loc;
2064
2065   if (GET_CODE (x) == SET)
2066     {
2067       rtx set = x ;
2068       rtx dest = SET_DEST (set);
2069       rtx src = SET_SRC (set);
2070       rtx inner_dest = dest;
2071       rtx subdest;
2072
2073       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074              || GET_CODE (inner_dest) == SUBREG
2075              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076         inner_dest = XEXP (inner_dest, 0);
2077
2078       /* Check for the case where I3 modifies its output, as discussed
2079          above.  We don't want to prevent pseudos from being combined
2080          into the address of a MEM, so only prevent the combination if
2081          i1 or i2 set the same MEM.  */
2082       if ((inner_dest != dest &&
2083            (!MEM_P (inner_dest)
2084             || rtx_equal_p (i2dest, inner_dest)
2085             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2090
2091           /* This is the same test done in can_combine_p except we can't test
2092              all_adjacent; we don't have to, since this instruction will stay
2093              in place, thus we are not considering increasing the lifetime of
2094              INNER_DEST.
2095
2096              Also, if this insn sets a function argument, combining it with
2097              something that might need a spill could clobber a previous
2098              function argument; the all_adjacent test in can_combine_p also
2099              checks this; here, we do a more specific test for this case.  */
2100
2101           || (REG_P (inner_dest)
2102               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104                                         GET_MODE (inner_dest))))
2105           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2107         return 0;
2108
2109       /* If DEST is used in I3, it is being killed in this insn, so
2110          record that for later.  We have to consider paradoxical
2111          subregs here, since they kill the whole register, but we
2112          ignore partial subregs, STRICT_LOW_PART, etc.
2113          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114          STACK_POINTER_REGNUM, since these are always considered to be
2115          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2116       subdest = dest;
2117       if (GET_CODE (subdest) == SUBREG
2118           && (GET_MODE_SIZE (GET_MODE (subdest))
2119               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120         subdest = SUBREG_REG (subdest);
2121       if (pi3dest_killed
2122           && REG_P (subdest)
2123           && reg_referenced_p (subdest, PATTERN (i3))
2124           && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129           && (REGNO (subdest) != ARG_POINTER_REGNUM
2130               || ! fixed_regs [REGNO (subdest)])
2131 #endif
2132           && REGNO (subdest) != STACK_POINTER_REGNUM)
2133         {
2134           if (*pi3dest_killed)
2135             return 0;
2136
2137           *pi3dest_killed = subdest;
2138         }
2139     }
2140
2141   else if (GET_CODE (x) == PARALLEL)
2142     {
2143       int i;
2144
2145       for (i = 0; i < XVECLEN (x, 0); i++)
2146         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2148           return 0;
2149     }
2150
2151   return 1;
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155    and division.  We don't count multiplications by powers of two here.  */
2156
2157 static int
2158 contains_muldiv (rtx x)
2159 {
2160   switch (GET_CODE (x))
2161     {
2162     case MOD:  case DIV:  case UMOD:  case UDIV:
2163       return 1;
2164
2165     case MULT:
2166       return ! (CONST_INT_P (XEXP (x, 1))
2167                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2168     default:
2169       if (BINARY_P (x))
2170         return contains_muldiv (XEXP (x, 0))
2171             || contains_muldiv (XEXP (x, 1));
2172
2173       if (UNARY_P (x))
2174         return contains_muldiv (XEXP (x, 0));
2175
2176       return 0;
2177     }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination.  Return nonzero if
2181    not.  This is used in try_combine to detect early some cases where we
2182    can't perform combinations.  */
2183
2184 static int
2185 cant_combine_insn_p (rtx insn)
2186 {
2187   rtx set;
2188   rtx src, dest;
2189
2190   /* If this isn't really an insn, we can't do anything.
2191      This can occur when flow deletes an insn that it has merged into an
2192      auto-increment address.  */
2193   if (! INSN_P (insn))
2194     return 1;
2195
2196   /* Never combine loads and stores involving hard regs that are likely
2197      to be spilled.  The register allocator can usually handle such
2198      reg-reg moves by tying.  If we allow the combiner to make
2199      substitutions of likely-spilled regs, reload might die.
2200      As an exception, we allow combinations involving fixed regs; these are
2201      not available to the register allocator so there's no risk involved.  */
2202
2203   set = single_set (insn);
2204   if (! set)
2205     return 0;
2206   src = SET_SRC (set);
2207   dest = SET_DEST (set);
2208   if (GET_CODE (src) == SUBREG)
2209     src = SUBREG_REG (src);
2210   if (GET_CODE (dest) == SUBREG)
2211     dest = SUBREG_REG (dest);
2212   if (REG_P (src) && REG_P (dest)
2213       && ((HARD_REGISTER_P (src)
2214            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216           || (HARD_REGISTER_P (dest)
2217               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2219     return 1;
2220
2221   return 0;
2222 }
2223
2224 struct likely_spilled_retval_info
2225 {
2226   unsigned regno, nregs;
2227   unsigned mask;
2228 };
2229
2230 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2231    hard registers that are known to be written to / clobbered in full.  */
2232 static void
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2234 {
2235   struct likely_spilled_retval_info *const info =
2236     (struct likely_spilled_retval_info *) data;
2237   unsigned regno, nregs;
2238   unsigned new_mask;
2239
2240   if (!REG_P (XEXP (set, 0)))
2241     return;
2242   regno = REGNO (x);
2243   if (regno >= info->regno + info->nregs)
2244     return;
2245   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246   if (regno + nregs <= info->regno)
2247     return;
2248   new_mask = (2U << (nregs - 1)) - 1;
2249   if (regno < info->regno)
2250     new_mask >>= info->regno - regno;
2251   else
2252     new_mask <<= regno - info->regno;
2253   info->mask &= ~new_mask;
2254 }
2255
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257    it is likely spilled.  This can happen when more than one insn is needed
2258    to copy the return value, e.g. when we consider to combine into the
2259    second copy insn for a complex value.  */
2260
2261 static int
2262 likely_spilled_retval_p (rtx insn)
2263 {
2264   rtx use = BB_END (this_basic_block);
2265   rtx reg, p;
2266   unsigned regno, nregs;
2267   /* We assume here that no machine mode needs more than
2268      32 hard registers when the value overlaps with a register
2269      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2270   unsigned mask;
2271   struct likely_spilled_retval_info info;
2272
2273   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2274     return 0;
2275   reg = XEXP (PATTERN (use), 0);
2276   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2277     return 0;
2278   regno = REGNO (reg);
2279   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2280   if (nregs == 1)
2281     return 0;
2282   mask = (2U << (nregs - 1)) - 1;
2283
2284   /* Disregard parts of the return value that are set later.  */
2285   info.regno = regno;
2286   info.nregs = nregs;
2287   info.mask = mask;
2288   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2289     if (INSN_P (p))
2290       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2291   mask = info.mask;
2292
2293   /* Check if any of the (probably) live return value registers is
2294      likely spilled.  */
2295   nregs --;
2296   do
2297     {
2298       if ((mask & 1 << nregs)
2299           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2300         return 1;
2301     } while (nregs--);
2302   return 0;
2303 }
2304
2305 /* Adjust INSN after we made a change to its destination.
2306
2307    Changing the destination can invalidate notes that say something about
2308    the results of the insn and a LOG_LINK pointing to the insn.  */
2309
2310 static void
2311 adjust_for_new_dest (rtx insn)
2312 {
2313   /* For notes, be conservative and simply remove them.  */
2314   remove_reg_equal_equiv_notes (insn);
2315
2316   /* The new insn will have a destination that was previously the destination
2317      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2318      the next use of that destination.  */
2319   distribute_links (alloc_insn_link (insn, NULL));
2320
2321   df_insn_rescan (insn);
2322 }
2323
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325    ADDED_SETS is nonzero if the original set is still required.  */
2326 static bool
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2328 {
2329   unsigned int regno;
2330
2331   if (!REG_P(x))
2332     return false;
2333
2334   regno = REGNO (x);
2335   /* Allow hard registers if the new mode is legal, and occupies no more
2336      registers than the old mode.  */
2337   if (regno < FIRST_PSEUDO_REGISTER)
2338     return (HARD_REGNO_MODE_OK (regno, mode)
2339             && (hard_regno_nregs[regno][GET_MODE (x)]
2340                 >= hard_regno_nregs[regno][mode]));
2341
2342   /* Or a pseudo that is only used once.  */
2343   return (REG_N_SETS (regno) == 1 && !added_sets
2344           && !REG_USERVAR_P (x));
2345 }
2346
2347
2348 /* Check whether X, the destination of a set, refers to part of
2349    the register specified by REG.  */
2350
2351 static bool
2352 reg_subword_p (rtx x, rtx reg)
2353 {
2354   /* Check that reg is an integer mode register.  */
2355   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2356     return false;
2357
2358   if (GET_CODE (x) == STRICT_LOW_PART
2359       || GET_CODE (x) == ZERO_EXTRACT)
2360     x = XEXP (x, 0);
2361
2362   return GET_CODE (x) == SUBREG
2363          && SUBREG_REG (x) == reg
2364          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2365 }
2366
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368    Note that the INSN should be deleted *after* removing dead edges, so
2369    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370    but not for a (set (pc) (label_ref FOO)).  */
2371
2372 static void
2373 update_cfg_for_uncondjump (rtx insn)
2374 {
2375   basic_block bb = BLOCK_FOR_INSN (insn);
2376   gcc_assert (BB_END (bb) == insn);
2377
2378   purge_dead_edges (bb);
2379
2380   delete_insn (insn);
2381   if (EDGE_COUNT (bb->succs) == 1)
2382     {
2383       rtx insn;
2384
2385       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386
2387       /* Remove barriers from the footer if there are any.  */
2388       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389         if (BARRIER_P (insn))
2390           {
2391             if (PREV_INSN (insn))
2392               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2393             else
2394               BB_FOOTER (bb) = NEXT_INSN (insn);
2395             if (NEXT_INSN (insn))
2396               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2397           }
2398         else if (LABEL_P (insn))
2399           break;
2400     }
2401 }
2402
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404    Here I0, I1 and I2 appear earlier than I3.
2405    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406    I3.
2407
2408    If we are combining more than two insns and the resulting insn is not
2409    recognized, try splitting it into two insns.  If that happens, I2 and I3
2410    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411    Otherwise, I0, I1 and I2 are pseudo-deleted.
2412
2413    Return 0 if the combination does not work.  Then nothing is changed.
2414    If we did the combination, return the insn at which combine should
2415    resume scanning.
2416
2417    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418    new direct jump instruction.
2419
2420    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421    been I3 passed to an earlier try_combine within the same basic
2422    block.  */
2423
2424 static rtx
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426              rtx last_combined_insn)
2427 {
2428   /* New patterns for I3 and I2, respectively.  */
2429   rtx newpat, newi2pat = 0;
2430   rtvec newpat_vec_with_clobbers = 0;
2431   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433      dead.  */
2434   int added_sets_0, added_sets_1, added_sets_2;
2435   /* Total number of SETs to put into I3.  */
2436   int total_sets;
2437   /* Nonzero if I2's or I1's body now appears in I3.  */
2438   int i2_is_used = 0, i1_is_used = 0;
2439   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2440   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441   /* Contains I3 if the destination of I3 is used in its source, which means
2442      that the old life of I3 is being killed.  If that usage is placed into
2443      I2 and not in I3, a REG_DEAD note must be made.  */
2444   rtx i3dest_killed = 0;
2445   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2446   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447   /* Copy of SET_SRC of I1 and I0, if needed.  */
2448   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449   /* Set if I2DEST was reused as a scratch register.  */
2450   bool i2scratch = false;
2451   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2452   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2459   rtx new_i3_notes, new_i2_notes;
2460   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2461   int i3_subst_into_i2 = 0;
2462   /* Notes that I1, I2 or I3 is a MULT operation.  */
2463   int have_mult = 0;
2464   int swap_i2i3 = 0;
2465   int changed_i3_dest = 0;
2466
2467   int maxreg;
2468   rtx temp;
2469   struct insn_link *link;
2470   rtx other_pat = 0;
2471   rtx new_other_notes;
2472   int i;
2473
2474   /* Only try four-insn combinations when there's high likelihood of
2475      success.  Look for simple insns, such as loads of constants or
2476      binary operations involving a constant.  */
2477   if (i0)
2478     {
2479       int i;
2480       int ngood = 0;
2481       int nshift = 0;
2482
2483       if (!flag_expensive_optimizations)
2484         return 0;
2485
2486       for (i = 0; i < 4; i++)
2487         {
2488           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489           rtx set = single_set (insn);
2490           rtx src;
2491           if (!set)
2492             continue;
2493           src = SET_SRC (set);
2494           if (CONSTANT_P (src))
2495             {
2496               ngood += 2;
2497               break;
2498             }
2499           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2500             ngood++;
2501           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502                    || GET_CODE (src) == LSHIFTRT)
2503             nshift++;
2504         }
2505       if (ngood < 2 && nshift < 2)
2506         return 0;
2507     }
2508
2509   /* Exit early if one of the insns involved can't be used for
2510      combinations.  */
2511   if (cant_combine_insn_p (i3)
2512       || cant_combine_insn_p (i2)
2513       || (i1 && cant_combine_insn_p (i1))
2514       || (i0 && cant_combine_insn_p (i0))
2515       || likely_spilled_retval_p (i3))
2516     return 0;
2517
2518   combine_attempts++;
2519   undobuf.other_insn = 0;
2520
2521   /* Reset the hard register usage information.  */
2522   CLEAR_HARD_REG_SET (newpat_used_regs);
2523
2524   if (dump_file && (dump_flags & TDF_DETAILS))
2525     {
2526       if (i0)
2527         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2529       else if (i1)
2530         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2532       else
2533         fprintf (dump_file, "\nTrying %d -> %d:\n",
2534                  INSN_UID (i2), INSN_UID (i3));
2535     }
2536
2537   /* If multiple insns feed into one of I2 or I3, they can be in any
2538      order.  To simplify the code below, reorder them in sequence.  */
2539   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540     temp = i2, i2 = i0, i0 = temp;
2541   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542     temp = i1, i1 = i0, i0 = temp;
2543   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544     temp = i1, i1 = i2, i2 = temp;
2545
2546   added_links_insn = 0;
2547
2548   /* First check for one important special case that the code below will
2549      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2550      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2551      we may be able to replace that destination with the destination of I3.
2552      This occurs in the common code where we compute both a quotient and
2553      remainder into a structure, in which case we want to do the computation
2554      directly into the structure to avoid register-register copies.
2555
2556      Note that this case handles both multiple sets in I2 and also cases
2557      where I2 has a number of CLOBBERs inside the PARALLEL.
2558
2559      We make very conservative checks below and only try to handle the
2560      most common cases of this.  For example, we only handle the case
2561      where I2 and I3 are adjacent to avoid making difficult register
2562      usage tests.  */
2563
2564   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565       && REG_P (SET_SRC (PATTERN (i3)))
2566       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568       && GET_CODE (PATTERN (i2)) == PARALLEL
2569       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571          below would need to check what is inside (and reg_overlap_mentioned_p
2572          doesn't support those codes anyway).  Don't allow those destinations;
2573          the resulting insn isn't likely to be recognized anyway.  */
2574       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577                                     SET_DEST (PATTERN (i3)))
2578       && next_active_insn (i2) == i3)
2579     {
2580       rtx p2 = PATTERN (i2);
2581
2582       /* Make sure that the destination of I3,
2583          which we are going to substitute into one output of I2,
2584          is not used within another output of I2.  We must avoid making this:
2585          (parallel [(set (mem (reg 69)) ...)
2586                     (set (reg 69) ...)])
2587          which is not well-defined as to order of actions.
2588          (Besides, reload can't handle output reloads for this.)
2589
2590          The problem can also happen if the dest of I3 is a memory ref,
2591          if another dest in I2 is an indirect memory ref.  */
2592       for (i = 0; i < XVECLEN (p2, 0); i++)
2593         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596                                         SET_DEST (XVECEXP (p2, 0, i))))
2597           break;
2598
2599       if (i == XVECLEN (p2, 0))
2600         for (i = 0; i < XVECLEN (p2, 0); i++)
2601           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2603             {
2604               combine_merges++;
2605
2606               subst_insn = i3;
2607               subst_low_luid = DF_INSN_LUID (i2);
2608
2609               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610               i2src = SET_SRC (XVECEXP (p2, 0, i));
2611               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612               i2dest_killed = dead_or_set_p (i2, i2dest);
2613
2614               /* Replace the dest in I2 with our dest and make the resulting
2615                  insn the new pattern for I3.  Then skip to where we validate
2616                  the pattern.  Everything was set up above.  */
2617               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2618               newpat = p2;
2619               i3_subst_into_i2 = 1;
2620               goto validate_replacement;
2621             }
2622     }
2623
2624   /* If I2 is setting a pseudo to a constant and I3 is setting some
2625      sub-part of it to another constant, merge them by making a new
2626      constant.  */
2627   if (i1 == 0
2628       && (temp = single_set (i2)) != 0
2629       && CONST_SCALAR_INT_P (SET_SRC (temp))
2630       && GET_CODE (PATTERN (i3)) == SET
2631       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2633     {
2634       rtx dest = SET_DEST (PATTERN (i3));
2635       int offset = -1;
2636       int width = 0;
2637
2638       if (GET_CODE (dest) == ZERO_EXTRACT)
2639         {
2640           if (CONST_INT_P (XEXP (dest, 1))
2641               && CONST_INT_P (XEXP (dest, 2)))
2642             {
2643               width = INTVAL (XEXP (dest, 1));
2644               offset = INTVAL (XEXP (dest, 2));
2645               dest = XEXP (dest, 0);
2646               if (BITS_BIG_ENDIAN)
2647                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2648             }
2649         }
2650       else
2651         {
2652           if (GET_CODE (dest) == STRICT_LOW_PART)
2653             dest = XEXP (dest, 0);
2654           width = GET_MODE_PRECISION (GET_MODE (dest));
2655           offset = 0;
2656         }
2657
2658       if (offset >= 0)
2659         {
2660           /* If this is the low part, we're done.  */
2661           if (subreg_lowpart_p (dest))
2662             ;
2663           /* Handle the case where inner is twice the size of outer.  */
2664           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2665                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2666             offset += GET_MODE_PRECISION (GET_MODE (dest));
2667           /* Otherwise give up for now.  */
2668           else
2669             offset = -1;
2670         }
2671
2672       if (offset >= 0
2673           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2674               <= HOST_BITS_PER_DOUBLE_INT))
2675         {
2676           double_int m, o, i;
2677           rtx inner = SET_SRC (PATTERN (i3));
2678           rtx outer = SET_SRC (temp);
2679
2680           o = rtx_to_double_int (outer);
2681           i = rtx_to_double_int (inner);
2682
2683           m = double_int::mask (width);
2684           i &= m;
2685           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2686           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687           o = o.and_not (m) | i;
2688
2689           combine_merges++;
2690           subst_insn = i3;
2691           subst_low_luid = DF_INSN_LUID (i2);
2692           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2693           i2dest = SET_DEST (temp);
2694           i2dest_killed = dead_or_set_p (i2, i2dest);
2695
2696           /* Replace the source in I2 with the new constant and make the
2697              resulting insn the new pattern for I3.  Then skip to where we
2698              validate the pattern.  Everything was set up above.  */
2699           SUBST (SET_SRC (temp),
2700                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2701
2702           newpat = PATTERN (i2);
2703
2704           /* The dest of I3 has been replaced with the dest of I2.  */
2705           changed_i3_dest = 1;
2706           goto validate_replacement;
2707         }
2708     }
2709
2710 #ifndef HAVE_cc0
2711   /* If we have no I1 and I2 looks like:
2712         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2713                    (set Y OP)])
2714      make up a dummy I1 that is
2715         (set Y OP)
2716      and change I2 to be
2717         (set (reg:CC X) (compare:CC Y (const_int 0)))
2718
2719      (We can ignore any trailing CLOBBERs.)
2720
2721      This undoes a previous combination and allows us to match a branch-and-
2722      decrement insn.  */
2723
2724   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2725       && XVECLEN (PATTERN (i2), 0) >= 2
2726       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2727       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2728           == MODE_CC)
2729       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2730       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2731       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2732       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2733       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2734                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2735     {
2736       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2737         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2738           break;
2739
2740       if (i == 1)
2741         {
2742           /* We make I1 with the same INSN_UID as I2.  This gives it
2743              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2744              never appear in the insn stream so giving it the same INSN_UID
2745              as I2 will not cause a problem.  */
2746
2747           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2748                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2749                              INSN_LOCATION (i2), -1, NULL_RTX);
2750
2751           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2752           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2753                  SET_DEST (PATTERN (i1)));
2754           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2755         }
2756     }
2757 #endif
2758
2759   /* Verify that I2 and I1 are valid for combining.  */
2760   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2761       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2762                                  &i1dest, &i1src))
2763       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2764                                  &i0dest, &i0src)))
2765     {
2766       undo_all ();
2767       return 0;
2768     }
2769
2770   /* Record whether I2DEST is used in I2SRC and similarly for the other
2771      cases.  Knowing this will help in register status updating below.  */
2772   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2773   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2774   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2775   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2776   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2777   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2778   i2dest_killed = dead_or_set_p (i2, i2dest);
2779   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2780   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2781
2782   /* For the earlier insns, determine which of the subsequent ones they
2783      feed.  */
2784   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2785   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2786   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2787                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2788                              && reg_overlap_mentioned_p (i0dest, i2src))));
2789
2790   /* Ensure that I3's pattern can be the destination of combines.  */
2791   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2792                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2793                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2794                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2795                           &i3dest_killed))
2796     {
2797       undo_all ();
2798       return 0;
2799     }
2800
2801   /* See if any of the insns is a MULT operation.  Unless one is, we will
2802      reject a combination that is, since it must be slower.  Be conservative
2803      here.  */
2804   if (GET_CODE (i2src) == MULT
2805       || (i1 != 0 && GET_CODE (i1src) == MULT)
2806       || (i0 != 0 && GET_CODE (i0src) == MULT)
2807       || (GET_CODE (PATTERN (i3)) == SET
2808           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2809     have_mult = 1;
2810
2811   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812      We used to do this EXCEPT in one case: I3 has a post-inc in an
2813      output operand.  However, that exception can give rise to insns like
2814         mov r3,(r3)+
2815      which is a famous insn on the PDP-11 where the value of r3 used as the
2816      source was model-dependent.  Avoid this sort of thing.  */
2817
2818 #if 0
2819   if (!(GET_CODE (PATTERN (i3)) == SET
2820         && REG_P (SET_SRC (PATTERN (i3)))
2821         && MEM_P (SET_DEST (PATTERN (i3)))
2822         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2823             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2824     /* It's not the exception.  */
2825 #endif
2826 #ifdef AUTO_INC_DEC
2827     {
2828       rtx link;
2829       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2830         if (REG_NOTE_KIND (link) == REG_INC
2831             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2832                 || (i1 != 0
2833                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2834           {
2835             undo_all ();
2836             return 0;
2837           }
2838     }
2839 #endif
2840
2841   /* See if the SETs in I1 or I2 need to be kept around in the merged
2842      instruction: whenever the value set there is still needed past I3.
2843      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2844
2845      For the SET in I1, we have two cases: if I1 and I2 independently feed
2846      into I3, the set in I1 needs to be kept around unless I1DEST dies
2847      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2848      in I1 needs to be kept around unless I1DEST dies or is set in either
2849      I2 or I3.  The same considerations apply to I0.  */
2850
2851   added_sets_2 = !dead_or_set_p (i3, i2dest);
2852
2853   if (i1)
2854     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2855                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2856   else
2857     added_sets_1 = 0;
2858
2859   if (i0)
2860     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2861                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2862                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2863                           && dead_or_set_p (i2, i0dest)));
2864   else
2865     added_sets_0 = 0;
2866
2867   /* We are about to copy insns for the case where they need to be kept
2868      around.  Check that they can be copied in the merged instruction.  */
2869
2870   if (targetm.cannot_copy_insn_p
2871       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2872           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2873           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2874     {
2875       undo_all ();
2876       return 0;
2877     }
2878
2879   /* If the set in I2 needs to be kept around, we must make a copy of
2880      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881      PATTERN (I2), we are only substituting for the original I1DEST, not into
2882      an already-substituted copy.  This also prevents making self-referential
2883      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884      I2DEST.  */
2885
2886   if (added_sets_2)
2887     {
2888       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2889         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2890       else
2891         i2pat = copy_rtx (PATTERN (i2));
2892     }
2893
2894   if (added_sets_1)
2895     {
2896       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2897         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2898       else
2899         i1pat = copy_rtx (PATTERN (i1));
2900     }
2901
2902   if (added_sets_0)
2903     {
2904       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2905         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2906       else
2907         i0pat = copy_rtx (PATTERN (i0));
2908     }
2909
2910   combine_merges++;
2911
2912   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2913
2914   maxreg = max_reg_num ();
2915
2916   subst_insn = i3;
2917
2918 #ifndef HAVE_cc0
2919   /* Many machines that don't use CC0 have insns that can both perform an
2920      arithmetic operation and set the condition code.  These operations will
2921      be represented as a PARALLEL with the first element of the vector
2922      being a COMPARE of an arithmetic operation with the constant zero.
2923      The second element of the vector will set some pseudo to the result
2924      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2925      match such a pattern and so will generate an extra insn.   Here we test
2926      for this case, where both the comparison and the operation result are
2927      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2929
2930   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2931       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2932       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2933       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2934     {
2935       rtx newpat_dest;
2936       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2937       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2938       enum machine_mode compare_mode, orig_compare_mode;
2939       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2940
2941       newpat = PATTERN (i3);
2942       newpat_dest = SET_DEST (newpat);
2943       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2944
2945       if (undobuf.other_insn == 0
2946           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2947                                             &cc_use_insn)))
2948         {
2949           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2950           compare_code = simplify_compare_const (compare_code,
2951                                                  op0, &op1);
2952           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2953         }
2954
2955       /* Do the rest only if op1 is const0_rtx, which may be the
2956          result of simplification.  */
2957       if (op1 == const0_rtx)
2958         {
2959           /* If a single use of the CC is found, prepare to modify it
2960              when SELECT_CC_MODE returns a new CC-class mode, or when
2961              the above simplify_compare_const() returned a new comparison
2962              operator.  undobuf.other_insn is assigned the CC use insn
2963              when modifying it.  */
2964           if (cc_use_loc)
2965             {
2966 #ifdef SELECT_CC_MODE
2967               enum machine_mode new_mode
2968                 = SELECT_CC_MODE (compare_code, op0, op1);
2969               if (new_mode != orig_compare_mode
2970                   && can_change_dest_mode (SET_DEST (newpat),
2971                                            added_sets_2, new_mode))
2972                 {
2973                   unsigned int regno = REGNO (newpat_dest);
2974                   compare_mode = new_mode;
2975                   if (regno < FIRST_PSEUDO_REGISTER)
2976                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2977                   else
2978                     {
2979                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2980                       newpat_dest = regno_reg_rtx[regno];
2981                     }
2982                 }
2983 #endif
2984               /* Cases for modifying the CC-using comparison.  */
2985               if (compare_code != orig_compare_code
2986                   /* ??? Do we need to verify the zero rtx?  */
2987                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2988                 {
2989                   /* Replace cc_use_loc with entire new RTX.  */
2990                   SUBST (*cc_use_loc,
2991                          gen_rtx_fmt_ee (compare_code, compare_mode,
2992                                          newpat_dest, const0_rtx));
2993                   undobuf.other_insn = cc_use_insn;
2994                 }
2995               else if (compare_mode != orig_compare_mode)
2996                 {
2997                   /* Just replace the CC reg with a new mode.  */
2998                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2999                   undobuf.other_insn = cc_use_insn;
3000                 }
3001             }
3002
3003           /* Now we modify the current newpat:
3004              First, SET_DEST(newpat) is updated if the CC mode has been
3005              altered. For targets without SELECT_CC_MODE, this should be
3006              optimized away.  */
3007           if (compare_mode != orig_compare_mode)
3008             SUBST (SET_DEST (newpat), newpat_dest);
3009           /* This is always done to propagate i2src into newpat.  */
3010           SUBST (SET_SRC (newpat),
3011                  gen_rtx_COMPARE (compare_mode, op0, op1));
3012           /* Create new version of i2pat if needed; the below PARALLEL
3013              creation needs this to work correctly.  */
3014           if (! rtx_equal_p (i2src, op0))
3015             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3016           i2_is_used = 1;
3017         }
3018     }
3019 #endif
3020
3021   if (i2_is_used == 0)
3022     {
3023       /* It is possible that the source of I2 or I1 may be performing
3024          an unneeded operation, such as a ZERO_EXTEND of something
3025          that is known to have the high part zero.  Handle that case
3026          by letting subst look at the inner insns.
3027
3028          Another way to do this would be to have a function that tries
3029          to simplify a single insn instead of merging two or more
3030          insns.  We don't do this because of the potential of infinite
3031          loops and because of the potential extra memory required.
3032          However, doing it the way we are is a bit of a kludge and
3033          doesn't catch all cases.
3034
3035          But only do this if -fexpensive-optimizations since it slows
3036          things down and doesn't usually win.
3037
3038          This is not done in the COMPARE case above because the
3039          unmodified I2PAT is used in the PARALLEL and so a pattern
3040          with a modified I2SRC would not match.  */
3041
3042       if (flag_expensive_optimizations)
3043         {
3044           /* Pass pc_rtx so no substitutions are done, just
3045              simplifications.  */
3046           if (i1)
3047             {
3048               subst_low_luid = DF_INSN_LUID (i1);
3049               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3050             }
3051
3052           subst_low_luid = DF_INSN_LUID (i2);
3053           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3054         }
3055
3056       n_occurrences = 0;                /* `subst' counts here */
3057       subst_low_luid = DF_INSN_LUID (i2);
3058
3059       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060          copy of I2SRC each time we substitute it, in order to avoid creating
3061          self-referential RTL when we will be substituting I1SRC for I1DEST
3062          later.  Likewise if I0 feeds into I2, either directly or indirectly
3063          through I1, and I0DEST is in I0SRC.  */
3064       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3065                       (i1_feeds_i2_n && i1dest_in_i1src)
3066                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3067                           && i0dest_in_i0src));
3068       substed_i2 = 1;
3069
3070       /* Record whether I2's body now appears within I3's body.  */
3071       i2_is_used = n_occurrences;
3072     }
3073
3074   /* If we already got a failure, don't try to do more.  Otherwise, try to
3075      substitute I1 if we have it.  */
3076
3077   if (i1 && GET_CODE (newpat) != CLOBBER)
3078     {
3079       /* Check that an autoincrement side-effect on I1 has not been lost.
3080          This happens if I1DEST is mentioned in I2 and dies there, and
3081          has disappeared from the new pattern.  */
3082       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3083            && i1_feeds_i2_n
3084            && dead_or_set_p (i2, i1dest)
3085            && !reg_overlap_mentioned_p (i1dest, newpat))
3086            /* Before we can do this substitution, we must redo the test done
3087               above (see detailed comments there) that ensures I1DEST isn't
3088               mentioned in any SETs in NEWPAT that are field assignments.  */
3089           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3090                                 0, 0, 0))
3091         {
3092           undo_all ();
3093           return 0;
3094         }
3095
3096       n_occurrences = 0;
3097       subst_low_luid = DF_INSN_LUID (i1);
3098
3099       /* If the following substitution will modify I1SRC, make a copy of it
3100          for the case where it is substituted for I1DEST in I2PAT later.  */
3101       if (added_sets_2 && i1_feeds_i2_n)
3102         i1src_copy = copy_rtx (i1src);
3103
3104       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105          copy of I1SRC each time we substitute it, in order to avoid creating
3106          self-referential RTL when we will be substituting I0SRC for I0DEST
3107          later.  */
3108       newpat = subst (newpat, i1dest, i1src, 0, 0,
3109                       i0_feeds_i1_n && i0dest_in_i0src);
3110       substed_i1 = 1;
3111
3112       /* Record whether I1's body now appears within I3's body.  */
3113       i1_is_used = n_occurrences;
3114     }
3115
3116   /* Likewise for I0 if we have it.  */
3117
3118   if (i0 && GET_CODE (newpat) != CLOBBER)
3119     {
3120       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3121            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3122                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3123            && !reg_overlap_mentioned_p (i0dest, newpat))
3124           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3125                                 0, 0, 0))
3126         {
3127           undo_all ();
3128           return 0;
3129         }
3130
3131       /* If the following substitution will modify I0SRC, make a copy of it
3132          for the case where it is substituted for I0DEST in I1PAT later.  */
3133       if (added_sets_1 && i0_feeds_i1_n)
3134         i0src_copy = copy_rtx (i0src);
3135       /* And a copy for I0DEST in I2PAT substitution.  */
3136       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3137                            || (i0_feeds_i2_n)))
3138         i0src_copy2 = copy_rtx (i0src);
3139
3140       n_occurrences = 0;
3141       subst_low_luid = DF_INSN_LUID (i0);
3142       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3143       substed_i0 = 1;
3144     }
3145
3146   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3147      to count all the ways that I2SRC and I1SRC can be used.  */
3148   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3149        && i2_is_used + added_sets_2 > 1)
3150       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3151           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3152               > 1))
3153       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3154           && (n_occurrences + added_sets_0
3155               + (added_sets_1 && i0_feeds_i1_n)
3156               + (added_sets_2 && i0_feeds_i2_n)
3157               > 1))
3158       /* Fail if we tried to make a new register.  */
3159       || max_reg_num () != maxreg
3160       /* Fail if we couldn't do something and have a CLOBBER.  */
3161       || GET_CODE (newpat) == CLOBBER
3162       /* Fail if this new pattern is a MULT and we didn't have one before
3163          at the outer level.  */
3164       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3165           && ! have_mult))
3166     {
3167       undo_all ();
3168       return 0;
3169     }
3170
3171   /* If the actions of the earlier insns must be kept
3172      in addition to substituting them into the latest one,
3173      we must make a new PARALLEL for the latest insn
3174      to hold additional the SETs.  */
3175
3176   if (added_sets_0 || added_sets_1 || added_sets_2)
3177     {
3178       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3179       combine_extras++;
3180
3181       if (GET_CODE (newpat) == PARALLEL)
3182         {
3183           rtvec old = XVEC (newpat, 0);
3184           total_sets = XVECLEN (newpat, 0) + extra_sets;
3185           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3186           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3187                   sizeof (old->elem[0]) * old->num_elem);
3188         }
3189       else
3190         {
3191           rtx old = newpat;
3192           total_sets = 1 + extra_sets;
3193           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3194           XVECEXP (newpat, 0, 0) = old;
3195         }
3196
3197       if (added_sets_0)
3198         XVECEXP (newpat, 0, --total_sets) = i0pat;
3199
3200       if (added_sets_1)
3201         {
3202           rtx t = i1pat;
3203           if (i0_feeds_i1_n)
3204             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3205
3206           XVECEXP (newpat, 0, --total_sets) = t;
3207         }
3208       if (added_sets_2)
3209         {
3210           rtx t = i2pat;
3211           if (i1_feeds_i2_n)
3212             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3213                        i0_feeds_i1_n && i0dest_in_i0src);
3214           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3215             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3216
3217           XVECEXP (newpat, 0, --total_sets) = t;
3218         }
3219     }
3220
3221  validate_replacement:
3222
3223   /* Note which hard regs this insn has as inputs.  */
3224   mark_used_regs_combine (newpat);
3225
3226   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3227      consider splitting this pattern, we might need these clobbers.  */
3228   if (i1 && GET_CODE (newpat) == PARALLEL
3229       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3230     {
3231       int len = XVECLEN (newpat, 0);
3232
3233       newpat_vec_with_clobbers = rtvec_alloc (len);
3234       for (i = 0; i < len; i++)
3235         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3236     }
3237
3238   /* Is the result of combination a valid instruction?  */
3239   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3240
3241   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242      the second SET's destination is a register that is unused and isn't
3243      marked as an instruction that might trap in an EH region.  In that case,
3244      we just need the first SET.   This can occur when simplifying a divmod
3245      insn.  We *must* test for this case here because the code below that
3246      splits two independent SETs doesn't handle this case correctly when it
3247      updates the register status.
3248
3249      It's pointless doing this if we originally had two sets, one from
3250      i3, and one from i2.  Combining then splitting the parallel results
3251      in the original i2 again plus an invalid insn (which we delete).
3252      The net effect is only to move instructions around, which makes
3253      debug info less accurate.
3254
3255      Also check the case where the first SET's destination is unused.
3256      That would not cause incorrect code, but does cause an unneeded
3257      insn to remain.  */
3258
3259   if (insn_code_number < 0
3260       && !(added_sets_2 && i1 == 0)
3261       && GET_CODE (newpat) == PARALLEL
3262       && XVECLEN (newpat, 0) == 2
3263       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265       && asm_noperands (newpat) < 0)
3266     {
3267       rtx set0 = XVECEXP (newpat, 0, 0);
3268       rtx set1 = XVECEXP (newpat, 0, 1);
3269
3270       if (((REG_P (SET_DEST (set1))
3271             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272            || (GET_CODE (SET_DEST (set1)) == SUBREG
3273                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274           && insn_nothrow_p (i3)
3275           && !side_effects_p (SET_SRC (set1)))
3276         {
3277           newpat = set0;
3278           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3279         }
3280
3281       else if (((REG_P (SET_DEST (set0))
3282                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284                     && find_reg_note (i3, REG_UNUSED,
3285                                       SUBREG_REG (SET_DEST (set0)))))
3286                && insn_nothrow_p (i3)
3287                && !side_effects_p (SET_SRC (set0)))
3288         {
3289           newpat = set1;
3290           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3291
3292           if (insn_code_number >= 0)
3293             changed_i3_dest = 1;
3294         }
3295     }
3296
3297   /* If we were combining three insns and the result is a simple SET
3298      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299      insns.  There are two ways to do this.  It can be split using a
3300      machine-specific method (like when you have an addition of a large
3301      constant) or by combine in the function find_split_point.  */
3302
3303   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304       && asm_noperands (newpat) < 0)
3305     {
3306       rtx parallel, m_split, *split;
3307
3308       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3309          use I2DEST as a scratch register will help.  In the latter case,
3310          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3311
3312       m_split = combine_split_insns (newpat, i3);
3313
3314       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315          inputs of NEWPAT.  */
3316
3317       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318          possible to try that as a scratch reg.  This would require adding
3319          more code to make it work though.  */
3320
3321       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3322         {
3323           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3324
3325           /* First try to split using the original register as a
3326              scratch register.  */
3327           parallel = gen_rtx_PARALLEL (VOIDmode,
3328                                        gen_rtvec (2, newpat,
3329                                                   gen_rtx_CLOBBER (VOIDmode,
3330                                                                    i2dest)));
3331           m_split = combine_split_insns (parallel, i3);
3332
3333           /* If that didn't work, try changing the mode of I2DEST if
3334              we can.  */
3335           if (m_split == 0
3336               && new_mode != GET_MODE (i2dest)
3337               && new_mode != VOIDmode
3338               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3339             {
3340               enum machine_mode old_mode = GET_MODE (i2dest);
3341               rtx ni2dest;
3342
3343               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3345               else
3346                 {
3347                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3349                 }
3350
3351               parallel = (gen_rtx_PARALLEL
3352                           (VOIDmode,
3353                            gen_rtvec (2, newpat,
3354                                       gen_rtx_CLOBBER (VOIDmode,
3355                                                        ni2dest))));
3356               m_split = combine_split_insns (parallel, i3);
3357
3358               if (m_split == 0
3359                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3360                 {
3361                   struct undo *buf;
3362
3363                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364                   buf = undobuf.undos;
3365                   undobuf.undos = buf->next;
3366                   buf->next = undobuf.frees;
3367                   undobuf.frees = buf;
3368                 }
3369             }
3370
3371           i2scratch = m_split != 0;
3372         }
3373
3374       /* If recog_for_combine has discarded clobbers, try to use them
3375          again for the split.  */
3376       if (m_split == 0 && newpat_vec_with_clobbers)
3377         {
3378           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379           m_split = combine_split_insns (parallel, i3);
3380         }
3381
3382       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3383         {
3384           m_split = PATTERN (m_split);
3385           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386           if (insn_code_number >= 0)
3387             newpat = m_split;
3388         }
3389       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390                && (next_nonnote_nondebug_insn (i2) == i3
3391                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3392         {
3393           rtx i2set, i3set;
3394           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395           newi2pat = PATTERN (m_split);
3396
3397           i3set = single_set (NEXT_INSN (m_split));
3398           i2set = single_set (m_split);
3399
3400           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3401
3402           /* If I2 or I3 has multiple SETs, we won't know how to track
3403              register status, so don't use these insns.  If I2's destination
3404              is used between I2 and I3, we also can't use these insns.  */
3405
3406           if (i2_code_number >= 0 && i2set && i3set
3407               && (next_nonnote_nondebug_insn (i2) == i3
3408                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409             insn_code_number = recog_for_combine (&newi3pat, i3,
3410                                                   &new_i3_notes);
3411           if (insn_code_number >= 0)
3412             newpat = newi3pat;
3413
3414           /* It is possible that both insns now set the destination of I3.
3415              If so, we must show an extra use of it.  */
3416
3417           if (insn_code_number >= 0)
3418             {
3419               rtx new_i3_dest = SET_DEST (i3set);
3420               rtx new_i2_dest = SET_DEST (i2set);
3421
3422               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424                      || GET_CODE (new_i3_dest) == SUBREG)
3425                 new_i3_dest = XEXP (new_i3_dest, 0);
3426
3427               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429                      || GET_CODE (new_i2_dest) == SUBREG)
3430                 new_i2_dest = XEXP (new_i2_dest, 0);
3431
3432               if (REG_P (new_i3_dest)
3433                   && REG_P (new_i2_dest)
3434                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3436             }
3437         }
3438
3439       /* If we can split it and use I2DEST, go ahead and see if that
3440          helps things be recognized.  Verify that none of the registers
3441          are set between I2 and I3.  */
3442       if (insn_code_number < 0
3443           && (split = find_split_point (&newpat, i3, false)) != 0
3444 #ifdef HAVE_cc0
3445           && REG_P (i2dest)
3446 #endif
3447           /* We need I2DEST in the proper mode.  If it is a hard register
3448              or the only use of a pseudo, we can change its mode.
3449              Make sure we don't change a hard register to have a mode that
3450              isn't valid for it, or change the number of registers.  */
3451           && (GET_MODE (*split) == GET_MODE (i2dest)
3452               || GET_MODE (*split) == VOIDmode
3453               || can_change_dest_mode (i2dest, added_sets_2,
3454                                        GET_MODE (*split)))
3455           && (next_nonnote_nondebug_insn (i2) == i3
3456               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457           /* We can't overwrite I2DEST if its value is still used by
3458              NEWPAT.  */
3459           && ! reg_referenced_p (i2dest, newpat))
3460         {
3461           rtx newdest = i2dest;
3462           enum rtx_code split_code = GET_CODE (*split);
3463           enum machine_mode split_mode = GET_MODE (*split);
3464           bool subst_done = false;
3465           newi2pat = NULL_RTX;
3466
3467           i2scratch = true;
3468
3469           /* *SPLIT may be part of I2SRC, so make sure we have the
3470              original expression around for later debug processing.
3471              We should not need I2SRC any more in other cases.  */
3472           if (MAY_HAVE_DEBUG_INSNS)
3473             i2src = copy_rtx (i2src);
3474           else
3475             i2src = NULL;
3476
3477           /* Get NEWDEST as a register in the proper mode.  We have already
3478              validated that we can do this.  */
3479           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3480             {
3481               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3483               else
3484                 {
3485                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486                   newdest = regno_reg_rtx[REGNO (i2dest)];
3487                 }
3488             }
3489
3490           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491              an ASHIFT.  This can occur if it was inside a PLUS and hence
3492              appeared to be a memory address.  This is a kludge.  */
3493           if (split_code == MULT
3494               && CONST_INT_P (XEXP (*split, 1))
3495               && INTVAL (XEXP (*split, 1)) > 0
3496               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3497             {
3498               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499                                              XEXP (*split, 0), GEN_INT (i)));
3500               /* Update split_code because we may not have a multiply
3501                  anymore.  */
3502               split_code = GET_CODE (*split);
3503             }
3504
3505 #ifdef INSN_SCHEDULING
3506           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507              be written as a ZERO_EXTEND.  */
3508           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3509             {
3510 #ifdef LOAD_EXTEND_OP
3511               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512                  what it really is.  */
3513               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3514                   == SIGN_EXTEND)
3515                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516                                                     SUBREG_REG (*split)));
3517               else
3518 #endif
3519                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520                                                     SUBREG_REG (*split)));
3521             }
3522 #endif
3523
3524           /* Attempt to split binary operators using arithmetic identities.  */
3525           if (BINARY_P (SET_SRC (newpat))
3526               && split_mode == GET_MODE (SET_SRC (newpat))
3527               && ! side_effects_p (SET_SRC (newpat)))
3528             {
3529               rtx setsrc = SET_SRC (newpat);
3530               enum machine_mode mode = GET_MODE (setsrc);
3531               enum rtx_code code = GET_CODE (setsrc);
3532               rtx src_op0 = XEXP (setsrc, 0);
3533               rtx src_op1 = XEXP (setsrc, 1);
3534
3535               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3536               if (rtx_equal_p (src_op0, src_op1))
3537                 {
3538                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539                   SUBST (XEXP (setsrc, 0), newdest);
3540                   SUBST (XEXP (setsrc, 1), newdest);
3541                   subst_done = true;
3542                 }
3543               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3544               else if ((code == PLUS || code == MULT)
3545                        && GET_CODE (src_op0) == code
3546                        && GET_CODE (XEXP (src_op0, 0)) == code
3547                        && (INTEGRAL_MODE_P (mode)
3548                            || (FLOAT_MODE_P (mode)
3549                                && flag_unsafe_math_optimizations)))
3550                 {
3551                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3552                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3553                   rtx r = XEXP (src_op0, 1);
3554                   rtx s = src_op1;
3555
3556                   /* Split both "((X op Y) op X) op Y" and
3557                      "((X op Y) op Y) op X" as "T op T" where T is
3558                      "X op Y".  */
3559                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3561                     {
3562                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3563                                               XEXP (src_op0, 0));
3564                       SUBST (XEXP (setsrc, 0), newdest);
3565                       SUBST (XEXP (setsrc, 1), newdest);
3566                       subst_done = true;
3567                     }
3568                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3569                      T is "X op Y".  */
3570                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3571                     {
3572                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3573                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574                       SUBST (XEXP (setsrc, 0), newdest);
3575                       SUBST (XEXP (setsrc, 1), newdest);
3576                       subst_done = true;
3577                     }
3578                 }
3579             }
3580
3581           if (!subst_done)
3582             {
3583               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584               SUBST (*split, newdest);
3585             }
3586
3587           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3588
3589           /* recog_for_combine might have added CLOBBERs to newi2pat.
3590              Make sure NEWPAT does not depend on the clobbered regs.  */
3591           if (GET_CODE (newi2pat) == PARALLEL)
3592             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3594                 {
3595                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596                   if (reg_overlap_mentioned_p (reg, newpat))
3597                     {
3598                       undo_all ();
3599                       return 0;
3600                     }
3601                 }
3602
3603           /* If the split point was a MULT and we didn't have one before,
3604              don't use one now.  */
3605           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3607         }
3608     }
3609
3610   /* Check for a case where we loaded from memory in a narrow mode and
3611      then sign extended it, but we need both registers.  In that case,
3612      we have a PARALLEL with both loads from the same memory location.
3613      We can split this into a load from memory followed by a register-register
3614      copy.  This saves at least one insn, more if register allocation can
3615      eliminate the copy.
3616
3617      We cannot do this if the destination of the first assignment is a
3618      condition code register or cc0.  We eliminate this case by making sure
3619      the SET_DEST and SET_SRC have the same mode.
3620
3621      We cannot do this if the destination of the second assignment is
3622      a register that we have already assumed is zero-extended.  Similarly
3623      for a SUBREG of such a register.  */
3624
3625   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626            && GET_CODE (newpat) == PARALLEL
3627            && XVECLEN (newpat, 0) == 2
3628            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3636                                    DF_INSN_LUID (i2))
3637            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3640                  (REG_P (temp)
3641                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3642                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3643                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3644                   && (reg_stat[REGNO (temp)].nonzero_bits
3645                       != GET_MODE_MASK (word_mode))))
3646            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3647                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3648                      (REG_P (temp)
3649                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3650                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3651                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3652                       && (reg_stat[REGNO (temp)].nonzero_bits
3653                           != GET_MODE_MASK (word_mode)))))
3654            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3655                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3656            && ! find_reg_note (i3, REG_UNUSED,
3657                                SET_DEST (XVECEXP (newpat, 0, 0))))
3658     {
3659       rtx ni2dest;
3660
3661       newi2pat = XVECEXP (newpat, 0, 0);
3662       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3663       newpat = XVECEXP (newpat, 0, 1);
3664       SUBST (SET_SRC (newpat),
3665              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3666       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3667
3668       if (i2_code_number >= 0)
3669         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3670
3671       if (insn_code_number >= 0)
3672         swap_i2i3 = 1;
3673     }
3674
3675   /* Similarly, check for a case where we have a PARALLEL of two independent
3676      SETs but we started with three insns.  In this case, we can do the sets
3677      as two separate insns.  This case occurs when some SET allows two
3678      other insns to combine, but the destination of that SET is still live.  */
3679
3680   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3681            && GET_CODE (newpat) == PARALLEL
3682            && XVECLEN (newpat, 0) == 2
3683            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3684            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3686            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3687            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3689            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                   XVECEXP (newpat, 0, 0))
3691            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3692                                   XVECEXP (newpat, 0, 1))
3693            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3694                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3695     {
3696       /* Normally, it doesn't matter which of the two is done first,
3697          but the one that references cc0 can't be the second, and
3698          one which uses any regs/memory set in between i2 and i3 can't
3699          be first.  */
3700       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3701                               DF_INSN_LUID (i2))
3702 #ifdef HAVE_cc0
3703           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3704 #endif
3705          )
3706         {
3707           newi2pat = XVECEXP (newpat, 0, 1);
3708           newpat = XVECEXP (newpat, 0, 0);
3709         }
3710       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3711                                    DF_INSN_LUID (i2))
3712 #ifdef HAVE_cc0
3713                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3714 #endif
3715               )
3716         {
3717           newi2pat = XVECEXP (newpat, 0, 0);
3718           newpat = XVECEXP (newpat, 0, 1);
3719         }
3720       else
3721         {
3722           undo_all ();
3723           return 0;
3724         }
3725
3726       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727
3728       if (i2_code_number >= 0)
3729         {
3730           /* recog_for_combine might have added CLOBBERs to newi2pat.
3731              Make sure NEWPAT does not depend on the clobbered regs.  */
3732           if (GET_CODE (newi2pat) == PARALLEL)
3733             {
3734               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3735                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3736                   {
3737                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3738                     if (reg_overlap_mentioned_p (reg, newpat))
3739                       {
3740                         undo_all ();
3741                         return 0;
3742                       }
3743                   }
3744             }
3745
3746           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3747         }
3748     }
3749
3750   /* If it still isn't recognized, fail and change things back the way they
3751      were.  */
3752   if ((insn_code_number < 0
3753        /* Is the result a reasonable ASM_OPERANDS?  */
3754        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3755     {
3756       undo_all ();
3757       return 0;
3758     }
3759
3760   /* If we had to change another insn, make sure it is valid also.  */
3761   if (undobuf.other_insn)
3762     {
3763       CLEAR_HARD_REG_SET (newpat_used_regs);
3764
3765       other_pat = PATTERN (undobuf.other_insn);
3766       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3767                                              &new_other_notes);
3768
3769       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3770         {
3771           undo_all ();
3772           return 0;
3773         }
3774     }
3775
3776 #ifdef HAVE_cc0
3777   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778      they are adjacent to each other or not.  */
3779   {
3780     rtx p = prev_nonnote_insn (i3);
3781     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3782         && sets_cc0_p (newi2pat))
3783       {
3784         undo_all ();
3785         return 0;
3786       }
3787   }
3788 #endif
3789
3790   /* Only allow this combination if insn_rtx_costs reports that the
3791      replacement instructions are cheaper than the originals.  */
3792   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3793     {
3794       undo_all ();
3795       return 0;
3796     }
3797
3798   if (MAY_HAVE_DEBUG_INSNS)
3799     {
3800       struct undo *undo;
3801
3802       for (undo = undobuf.undos; undo; undo = undo->next)
3803         if (undo->kind == UNDO_MODE)
3804           {
3805             rtx reg = *undo->where.r;
3806             enum machine_mode new_mode = GET_MODE (reg);
3807             enum machine_mode old_mode = undo->old_contents.m;
3808
3809             /* Temporarily revert mode back.  */
3810             adjust_reg_mode (reg, old_mode);
3811
3812             if (reg == i2dest && i2scratch)
3813               {
3814                 /* If we used i2dest as a scratch register with a
3815                    different mode, substitute it for the original
3816                    i2src while its original mode is temporarily
3817                    restored, and then clear i2scratch so that we don't
3818                    do it again later.  */
3819                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3820                                      this_basic_block);
3821                 i2scratch = false;
3822                 /* Put back the new mode.  */
3823                 adjust_reg_mode (reg, new_mode);
3824               }
3825             else
3826               {
3827                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3828                 rtx first, last;
3829
3830                 if (reg == i2dest)
3831                   {
3832                     first = i2;
3833                     last = last_combined_insn;
3834                   }
3835                 else
3836                   {
3837                     first = i3;
3838                     last = undobuf.other_insn;
3839                     gcc_assert (last);
3840                     if (DF_INSN_LUID (last)
3841                         < DF_INSN_LUID (last_combined_insn))
3842                       last = last_combined_insn;
3843                   }
3844
3845                 /* We're dealing with a reg that changed mode but not
3846                    meaning, so we want to turn it into a subreg for
3847                    the new mode.  However, because of REG sharing and
3848                    because its mode had already changed, we have to do
3849                    it in two steps.  First, replace any debug uses of
3850                    reg, with its original mode temporarily restored,
3851                    with this copy we have created; then, replace the
3852                    copy with the SUBREG of the original shared reg,
3853                    once again changed to the new mode.  */
3854                 propagate_for_debug (first, last, reg, tempreg,
3855                                      this_basic_block);
3856                 adjust_reg_mode (reg, new_mode);
3857                 propagate_for_debug (first, last, tempreg,
3858                                      lowpart_subreg (old_mode, reg, new_mode),
3859                                      this_basic_block);
3860               }
3861           }
3862     }
3863
3864   /* If we will be able to accept this, we have made a
3865      change to the destination of I3.  This requires us to
3866      do a few adjustments.  */
3867
3868   if (changed_i3_dest)
3869     {
3870       PATTERN (i3) = newpat;
3871       adjust_for_new_dest (i3);
3872     }
3873
3874   /* We now know that we can do this combination.  Merge the insns and
3875      update the status of registers and LOG_LINKS.  */
3876
3877   if (undobuf.other_insn)
3878     {
3879       rtx note, next;
3880
3881       PATTERN (undobuf.other_insn) = other_pat;
3882
3883       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884          are still valid.  Then add any non-duplicate notes added by
3885          recog_for_combine.  */
3886       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3887         {
3888           next = XEXP (note, 1);
3889
3890           if (REG_NOTE_KIND (note) == REG_UNUSED
3891               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3892             remove_note (undobuf.other_insn, note);
3893         }
3894
3895       distribute_notes (new_other_notes, undobuf.other_insn,
3896                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3897                         NULL_RTX);
3898     }
3899
3900   if (swap_i2i3)
3901     {
3902       rtx insn;
3903       struct insn_link *link;
3904       rtx ni2dest;
3905
3906       /* I3 now uses what used to be its destination and which is now
3907          I2's destination.  This requires us to do a few adjustments.  */
3908       PATTERN (i3) = newpat;
3909       adjust_for_new_dest (i3);
3910
3911       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3912          so we still will.
3913
3914          However, some later insn might be using I2's dest and have
3915          a LOG_LINK pointing at I3.  We must remove this link.
3916          The simplest way to remove the link is to point it at I1,
3917          which we know will be a NOTE.  */
3918
3919       /* newi2pat is usually a SET here; however, recog_for_combine might
3920          have added some clobbers.  */
3921       if (GET_CODE (newi2pat) == PARALLEL)
3922         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3923       else
3924         ni2dest = SET_DEST (newi2pat);
3925
3926       for (insn = NEXT_INSN (i3);
3927            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3928                     || insn != BB_HEAD (this_basic_block->next_bb));
3929            insn = NEXT_INSN (insn))
3930         {
3931           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3932             {
3933               FOR_EACH_LOG_LINK (link, insn)
3934                 if (link->insn == i3)
3935                   link->insn = i1;
3936
3937               break;
3938             }
3939         }
3940     }
3941
3942   {
3943     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3944     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3945     rtx midnotes = 0;
3946     int from_luid;
3947     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3948        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3949        same as i3dest, in which case newi2pat may be setting i1dest.  */
3950     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3951                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3952                    || !i2dest_killed
3953                    ? 0 : i2dest);
3954     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3955                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3956                    || !i1dest_killed
3957                    ? 0 : i1dest);
3958     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3959                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3960                    || !i0dest_killed
3961                    ? 0 : i0dest);
3962
3963     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3964        clear them.  */
3965     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3966     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3967     if (i1)
3968       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3969     if (i0)
3970       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3971
3972     /* Ensure that we do not have something that should not be shared but
3973        occurs multiple times in the new insns.  Check this by first
3974        resetting all the `used' flags and then copying anything is shared.  */
3975
3976     reset_used_flags (i3notes);
3977     reset_used_flags (i2notes);
3978     reset_used_flags (i1notes);
3979     reset_used_flags (i0notes);
3980     reset_used_flags (newpat);
3981     reset_used_flags (newi2pat);
3982     if (undobuf.other_insn)
3983       reset_used_flags (PATTERN (undobuf.other_insn));
3984
3985     i3notes = copy_rtx_if_shared (i3notes);
3986     i2notes = copy_rtx_if_shared (i2notes);
3987     i1notes = copy_rtx_if_shared (i1notes);
3988     i0notes = copy_rtx_if_shared (i0notes);
3989     newpat = copy_rtx_if_shared (newpat);
3990     newi2pat = copy_rtx_if_shared (newi2pat);
3991     if (undobuf.other_insn)
3992       reset_used_flags (PATTERN (undobuf.other_insn));
3993
3994     INSN_CODE (i3) = insn_code_number;
3995     PATTERN (i3) = newpat;
3996
3997     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3998       {
3999         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4000
4001         reset_used_flags (call_usage);
4002         call_usage = copy_rtx (call_usage);
4003
4004         if (substed_i2)
4005           {
4006             /* I2SRC must still be meaningful at this point.  Some splitting
4007                operations can invalidate I2SRC, but those operations do not
4008                apply to calls.  */
4009             gcc_assert (i2src);
4010             replace_rtx (call_usage, i2dest, i2src);
4011           }
4012
4013         if (substed_i1)
4014           replace_rtx (call_usage, i1dest, i1src);
4015         if (substed_i0)
4016           replace_rtx (call_usage, i0dest, i0src);
4017
4018         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4019       }
4020
4021     if (undobuf.other_insn)
4022       INSN_CODE (undobuf.other_insn) = other_code_number;
4023
4024     /* We had one special case above where I2 had more than one set and
4025        we replaced a destination of one of those sets with the destination
4026        of I3.  In that case, we have to update LOG_LINKS of insns later
4027        in this basic block.  Note that this (expensive) case is rare.
4028
4029        Also, in this case, we must pretend that all REG_NOTEs for I2
4030        actually came from I3, so that REG_UNUSED notes from I2 will be
4031        properly handled.  */
4032
4033     if (i3_subst_into_i2)
4034       {
4035         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4036           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4037                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4038               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4039               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4040               && ! find_reg_note (i2, REG_UNUSED,
4041                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4042             for (temp = NEXT_INSN (i2);
4043                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4044                           || BB_HEAD (this_basic_block) != temp);
4045                  temp = NEXT_INSN (temp))
4046               if (temp != i3 && INSN_P (temp))
4047                 FOR_EACH_LOG_LINK (link, temp)
4048                   if (link->insn == i2)
4049                     link->insn = i3;
4050
4051         if (i3notes)
4052           {
4053             rtx link = i3notes;
4054             while (XEXP (link, 1))
4055               link = XEXP (link, 1);
4056             XEXP (link, 1) = i2notes;
4057           }
4058         else
4059           i3notes = i2notes;
4060         i2notes = 0;
4061       }
4062
4063     LOG_LINKS (i3) = NULL;
4064     REG_NOTES (i3) = 0;
4065     LOG_LINKS (i2) = NULL;
4066     REG_NOTES (i2) = 0;
4067
4068     if (newi2pat)
4069       {
4070         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4071           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4072                                this_basic_block);
4073         INSN_CODE (i2) = i2_code_number;
4074         PATTERN (i2) = newi2pat;
4075       }
4076     else
4077       {
4078         if (MAY_HAVE_DEBUG_INSNS && i2src)
4079           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4080                                this_basic_block);
4081         SET_INSN_DELETED (i2);
4082       }
4083
4084     if (i1)
4085       {
4086         LOG_LINKS (i1) = NULL;
4087         REG_NOTES (i1) = 0;
4088         if (MAY_HAVE_DEBUG_INSNS)
4089           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4090                                this_basic_block);
4091         SET_INSN_DELETED (i1);
4092       }
4093
4094     if (i0)
4095       {
4096         LOG_LINKS (i0) = NULL;
4097         REG_NOTES (i0) = 0;
4098         if (MAY_HAVE_DEBUG_INSNS)
4099           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4100                                this_basic_block);
4101         SET_INSN_DELETED (i0);
4102       }
4103
4104     /* Get death notes for everything that is now used in either I3 or
4105        I2 and used to die in a previous insn.  If we built two new
4106        patterns, move from I1 to I2 then I2 to I3 so that we get the
4107        proper movement on registers that I2 modifies.  */
4108
4109     if (i0)
4110       from_luid = DF_INSN_LUID (i0);
4111     else if (i1)
4112       from_luid = DF_INSN_LUID (i1);
4113     else
4114       from_luid = DF_INSN_LUID (i2);
4115     if (newi2pat)
4116       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4117     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4118
4119     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4120     if (i3notes)
4121       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4122                         elim_i2, elim_i1, elim_i0);
4123     if (i2notes)
4124       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4125                         elim_i2, elim_i1, elim_i0);
4126     if (i1notes)
4127       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4128                         elim_i2, elim_i1, elim_i0);
4129     if (i0notes)
4130       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4131                         elim_i2, elim_i1, elim_i0);
4132     if (midnotes)
4133       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4134                         elim_i2, elim_i1, elim_i0);
4135
4136     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4137        know these are REG_UNUSED and want them to go to the desired insn,
4138        so we always pass it as i3.  */
4139
4140     if (newi2pat && new_i2_notes)
4141       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4142                         NULL_RTX);
4143
4144     if (new_i3_notes)
4145       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4146                         NULL_RTX);
4147
4148     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4149        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4150        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4151        in that case, it might delete I2.  Similarly for I2 and I1.
4152        Show an additional death due to the REG_DEAD note we make here.  If
4153        we discard it in distribute_notes, we will decrement it again.  */
4154
4155     if (i3dest_killed)
4156       {
4157         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4158         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4159           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4160                             elim_i1, elim_i0);
4161         else
4162           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4163                             elim_i2, elim_i1, elim_i0);
4164       }
4165
4166     if (i2dest_in_i2src)
4167       {
4168         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4169         if (newi2pat && reg_set_p (i2dest, newi2pat))
4170           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4171                             NULL_RTX, NULL_RTX);
4172         else
4173           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4174                             NULL_RTX, NULL_RTX, NULL_RTX);
4175       }
4176
4177     if (i1dest_in_i1src)
4178       {
4179         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4180         if (newi2pat && reg_set_p (i1dest, newi2pat))
4181           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4182                             NULL_RTX, NULL_RTX);
4183         else
4184           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4185                             NULL_RTX, NULL_RTX, NULL_RTX);
4186       }
4187
4188     if (i0dest_in_i0src)
4189       {
4190         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4191         if (newi2pat && reg_set_p (i0dest, newi2pat))
4192           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4193                             NULL_RTX, NULL_RTX);
4194         else
4195           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4196                             NULL_RTX, NULL_RTX, NULL_RTX);
4197       }
4198
4199     distribute_links (i3links);
4200     distribute_links (i2links);
4201     distribute_links (i1links);
4202     distribute_links (i0links);
4203
4204     if (REG_P (i2dest))
4205       {
4206         struct insn_link *link;
4207         rtx i2_insn = 0, i2_val = 0, set;
4208
4209         /* The insn that used to set this register doesn't exist, and
4210            this life of the register may not exist either.  See if one of
4211            I3's links points to an insn that sets I2DEST.  If it does,
4212            that is now the last known value for I2DEST. If we don't update
4213            this and I2 set the register to a value that depended on its old
4214            contents, we will get confused.  If this insn is used, thing
4215            will be set correctly in combine_instructions.  */
4216         FOR_EACH_LOG_LINK (link, i3)
4217           if ((set = single_set (link->insn)) != 0
4218               && rtx_equal_p (i2dest, SET_DEST (set)))
4219             i2_insn = link->insn, i2_val = SET_SRC (set);
4220
4221         record_value_for_reg (i2dest, i2_insn, i2_val);
4222
4223         /* If the reg formerly set in I2 died only once and that was in I3,
4224            zero its use count so it won't make `reload' do any work.  */
4225         if (! added_sets_2
4226             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4227             && ! i2dest_in_i2src)
4228           INC_REG_N_SETS (REGNO (i2dest), -1);
4229       }
4230
4231     if (i1 && REG_P (i1dest))
4232       {
4233         struct insn_link *link;
4234         rtx i1_insn = 0, i1_val = 0, set;
4235
4236         FOR_EACH_LOG_LINK (link, i3)
4237           if ((set = single_set (link->insn)) != 0
4238               && rtx_equal_p (i1dest, SET_DEST (set)))
4239             i1_insn = link->insn, i1_val = SET_SRC (set);
4240
4241         record_value_for_reg (i1dest, i1_insn, i1_val);
4242
4243         if (! added_sets_1 && ! i1dest_in_i1src)
4244           INC_REG_N_SETS (REGNO (i1dest), -1);
4245       }
4246
4247     if (i0 && REG_P (i0dest))
4248       {
4249         struct insn_link *link;
4250         rtx i0_insn = 0, i0_val = 0, set;
4251
4252         FOR_EACH_LOG_LINK (link, i3)
4253           if ((set = single_set (link->insn)) != 0
4254               && rtx_equal_p (i0dest, SET_DEST (set)))
4255             i0_insn = link->insn, i0_val = SET_SRC (set);
4256
4257         record_value_for_reg (i0dest, i0_insn, i0_val);
4258
4259         if (! added_sets_0 && ! i0dest_in_i0src)
4260           INC_REG_N_SETS (REGNO (i0dest), -1);
4261       }
4262
4263     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264        been made to this insn.  The order of
4265        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4266        can affect nonzero_bits of newpat */
4267     if (newi2pat)
4268       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4269     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4270   }
4271
4272   if (undobuf.other_insn != NULL_RTX)
4273     {
4274       if (dump_file)
4275         {
4276           fprintf (dump_file, "modifying other_insn ");
4277           dump_insn_slim (dump_file, undobuf.other_insn);
4278         }
4279       df_insn_rescan (undobuf.other_insn);
4280     }
4281
4282   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4283     {
4284       if (dump_file)
4285         {
4286           fprintf (dump_file, "modifying insn i1 ");
4287           dump_insn_slim (dump_file, i0);
4288         }
4289       df_insn_rescan (i0);
4290     }
4291
4292   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4293     {
4294       if (dump_file)
4295         {
4296           fprintf (dump_file, "modifying insn i1 ");
4297           dump_insn_slim (dump_file, i1);
4298         }
4299       df_insn_rescan (i1);
4300     }
4301
4302   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4303     {
4304       if (dump_file)
4305         {
4306           fprintf (dump_file, "modifying insn i2 ");
4307           dump_insn_slim (dump_file, i2);
4308         }
4309       df_insn_rescan (i2);
4310     }
4311
4312   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4313     {
4314       if (dump_file)
4315         {
4316           fprintf (dump_file, "modifying insn i3 ");
4317           dump_insn_slim (dump_file, i3);
4318         }
4319       df_insn_rescan (i3);
4320     }
4321
4322   /* Set new_direct_jump_p if a new return or simple jump instruction
4323      has been created.  Adjust the CFG accordingly.  */
4324
4325   if (returnjump_p (i3) || any_uncondjump_p (i3))
4326     {
4327       *new_direct_jump_p = 1;
4328       mark_jump_label (PATTERN (i3), i3, 0);
4329       update_cfg_for_uncondjump (i3);
4330     }
4331
4332   if (undobuf.other_insn != NULL_RTX
4333       && (returnjump_p (undobuf.other_insn)
4334           || any_uncondjump_p (undobuf.other_insn)))
4335     {
4336       *new_direct_jump_p = 1;
4337       update_cfg_for_uncondjump (undobuf.other_insn);
4338     }
4339
4340   /* A noop might also need cleaning up of CFG, if it comes from the
4341      simplification of a jump.  */
4342   if (JUMP_P (i3)
4343       && GET_CODE (newpat) == SET
4344       && SET_SRC (newpat) == pc_rtx
4345       && SET_DEST (newpat) == pc_rtx)
4346     {
4347       *new_direct_jump_p = 1;
4348       update_cfg_for_uncondjump (i3);
4349     }
4350
4351   if (undobuf.other_insn != NULL_RTX
4352       && JUMP_P (undobuf.other_insn)
4353       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4354       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4355       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4356     {
4357       *new_direct_jump_p = 1;
4358       update_cfg_for_uncondjump (undobuf.other_insn);
4359     }
4360
4361   combine_successes++;
4362   undo_commit ();
4363
4364   if (added_links_insn
4365       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4366       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4367     return added_links_insn;
4368   else
4369     return newi2pat ? i2 : i3;
4370 }
4371 \f
4372 /* Undo all the modifications recorded in undobuf.  */
4373
4374 static void
4375 undo_all (void)
4376 {
4377   struct undo *undo, *next;
4378
4379   for (undo = undobuf.undos; undo; undo = next)
4380     {
4381       next = undo->next;
4382       switch (undo->kind)
4383         {
4384         case UNDO_RTX:
4385           *undo->where.r = undo->old_contents.r;
4386           break;
4387         case UNDO_INT:
4388           *undo->where.i = undo->old_contents.i;
4389           break;
4390         case UNDO_MODE:
4391           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4392           break;
4393         case UNDO_LINKS:
4394           *undo->where.l = undo->old_contents.l;
4395           break;
4396         default:
4397           gcc_unreachable ();
4398         }
4399
4400       undo->next = undobuf.frees;
4401       undobuf.frees = undo;
4402     }
4403
4404   undobuf.undos = 0;
4405 }
4406
4407 /* We've committed to accepting the changes we made.  Move all
4408    of the undos to the free list.  */
4409
4410 static void
4411 undo_commit (void)
4412 {
4413   struct undo *undo, *next;
4414
4415   for (undo = undobuf.undos; undo; undo = next)
4416     {
4417       next = undo->next;
4418       undo->next = undobuf.frees;
4419       undobuf.frees = undo;
4420     }
4421   undobuf.undos = 0;
4422 }
4423 \f
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425    where we have an arithmetic expression and return that point.  LOC will
4426    be inside INSN.
4427
4428    try_combine will call this function to see if an insn can be split into
4429    two insns.  */
4430
4431 static rtx *
4432 find_split_point (rtx *loc, rtx insn, bool set_src)
4433 {
4434   rtx x = *loc;
4435   enum rtx_code code = GET_CODE (x);
4436   rtx *split;
4437   unsigned HOST_WIDE_INT len = 0;
4438   HOST_WIDE_INT pos = 0;
4439   int unsignedp = 0;
4440   rtx inner = NULL_RTX;
4441
4442   /* First special-case some codes.  */
4443   switch (code)
4444     {
4445     case SUBREG:
4446 #ifdef INSN_SCHEDULING
4447       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4448          point.  */
4449       if (MEM_P (SUBREG_REG (x)))
4450         return loc;
4451 #endif
4452       return find_split_point (&SUBREG_REG (x), insn, false);
4453
4454     case MEM:
4455 #ifdef HAVE_lo_sum
4456       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457          using LO_SUM and HIGH.  */
4458       if (GET_CODE (XEXP (x, 0)) == CONST
4459           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4460         {
4461           enum machine_mode address_mode = get_address_mode (x);
4462
4463           SUBST (XEXP (x, 0),
4464                  gen_rtx_LO_SUM (address_mode,
4465                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4466                                  XEXP (x, 0)));
4467           return &XEXP (XEXP (x, 0), 0);
4468         }
4469 #endif
4470
4471       /* If we have a PLUS whose second operand is a constant and the
4472          address is not valid, perhaps will can split it up using
4473          the machine-specific way to split large constants.  We use
4474          the first pseudo-reg (one of the virtual regs) as a placeholder;
4475          it will not remain in the result.  */
4476       if (GET_CODE (XEXP (x, 0)) == PLUS
4477           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4478           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4479                                             MEM_ADDR_SPACE (x)))
4480         {
4481           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4482           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4483                                                       XEXP (x, 0)),
4484                                          subst_insn);
4485
4486           /* This should have produced two insns, each of which sets our
4487              placeholder.  If the source of the second is a valid address,
4488              we can make put both sources together and make a split point
4489              in the middle.  */
4490
4491           if (seq
4492               && NEXT_INSN (seq) != NULL_RTX
4493               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4494               && NONJUMP_INSN_P (seq)
4495               && GET_CODE (PATTERN (seq)) == SET
4496               && SET_DEST (PATTERN (seq)) == reg
4497               && ! reg_mentioned_p (reg,
4498                                     SET_SRC (PATTERN (seq)))
4499               && NONJUMP_INSN_P (NEXT_INSN (seq))
4500               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4501               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4502               && memory_address_addr_space_p
4503                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4504                     MEM_ADDR_SPACE (x)))
4505             {
4506               rtx src1 = SET_SRC (PATTERN (seq));
4507               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4508
4509               /* Replace the placeholder in SRC2 with SRC1.  If we can
4510                  find where in SRC2 it was placed, that can become our
4511                  split point and we can replace this address with SRC2.
4512                  Just try two obvious places.  */
4513
4514               src2 = replace_rtx (src2, reg, src1);
4515               split = 0;
4516               if (XEXP (src2, 0) == src1)
4517                 split = &XEXP (src2, 0);
4518               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4519                        && XEXP (XEXP (src2, 0), 0) == src1)
4520                 split = &XEXP (XEXP (src2, 0), 0);
4521
4522               if (split)
4523                 {
4524                   SUBST (XEXP (x, 0), src2);
4525                   return split;
4526                 }
4527             }
4528
4529           /* If that didn't work, perhaps the first operand is complex and
4530              needs to be computed separately, so make a split point there.
4531              This will occur on machines that just support REG + CONST
4532              and have a constant moved through some previous computation.  */
4533
4534           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4535                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4536                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4537             return &XEXP (XEXP (x, 0), 0);
4538         }
4539
4540       /* If we have a PLUS whose first operand is complex, try computing it
4541          separately by making a split there.  */
4542       if (GET_CODE (XEXP (x, 0)) == PLUS
4543           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4544                                             MEM_ADDR_SPACE (x))
4545           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4546           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4547                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4548         return &XEXP (XEXP (x, 0), 0);
4549       break;
4550
4551     case SET:
4552 #ifdef HAVE_cc0
4553       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555          we need to put the operand into a register.  So split at that
4556          point.  */
4557
4558       if (SET_DEST (x) == cc0_rtx
4559           && GET_CODE (SET_SRC (x)) != COMPARE
4560           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4561           && !OBJECT_P (SET_SRC (x))
4562           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4563                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4564         return &SET_SRC (x);
4565 #endif
4566
4567       /* See if we can split SET_SRC as it stands.  */
4568       split = find_split_point (&SET_SRC (x), insn, true);
4569       if (split && split != &SET_SRC (x))
4570         return split;
4571
4572       /* See if we can split SET_DEST as it stands.  */
4573       split = find_split_point (&SET_DEST (x), insn, false);
4574       if (split && split != &SET_DEST (x))
4575         return split;
4576
4577       /* See if this is a bitfield assignment with everything constant.  If
4578          so, this is an IOR of an AND, so split it into that.  */
4579       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4580           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4581           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4582           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4583           && CONST_INT_P (SET_SRC (x))
4584           && ((INTVAL (XEXP (SET_DEST (x), 1))
4585                + INTVAL (XEXP (SET_DEST (x), 2)))
4586               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4587           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4588         {
4589           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4590           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4591           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4592           rtx dest = XEXP (SET_DEST (x), 0);
4593           enum machine_mode mode = GET_MODE (dest);
4594           unsigned HOST_WIDE_INT mask
4595             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4596           rtx or_mask;
4597
4598           if (BITS_BIG_ENDIAN)
4599             pos = GET_MODE_PRECISION (mode) - len - pos;
4600
4601           or_mask = gen_int_mode (src << pos, mode);
4602           if (src == mask)
4603             SUBST (SET_SRC (x),
4604                    simplify_gen_binary (IOR, mode, dest, or_mask));
4605           else
4606             {
4607               rtx negmask = gen_int_mode (~(mask << pos), mode);
4608               SUBST (SET_SRC (x),
4609                      simplify_gen_binary (IOR, mode,
4610                                           simplify_gen_binary (AND, mode,
4611                                                                dest, negmask),
4612                                           or_mask));
4613             }
4614
4615           SUBST (SET_DEST (x), dest);
4616
4617           split = find_split_point (&SET_SRC (x), insn, true);
4618           if (split && split != &SET_SRC (x))
4619             return split;
4620         }
4621
4622       /* Otherwise, see if this is an operation that we can split into two.
4623          If so, try to split that.  */
4624       code = GET_CODE (SET_SRC (x));
4625
4626       switch (code)
4627         {
4628         case AND:
4629           /* If we are AND'ing with a large constant that is only a single
4630              bit and the result is only being used in a context where we
4631              need to know if it is zero or nonzero, replace it with a bit
4632              extraction.  This will avoid the large constant, which might
4633              have taken more than one insn to make.  If the constant were
4634              not a valid argument to the AND but took only one insn to make,
4635              this is no worse, but if it took more than one insn, it will
4636              be better.  */
4637
4638           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4639               && REG_P (XEXP (SET_SRC (x), 0))
4640               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4641               && REG_P (SET_DEST (x))
4642               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4643               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4644               && XEXP (*split, 0) == SET_DEST (x)
4645               && XEXP (*split, 1) == const0_rtx)
4646             {
4647               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4648                                                 XEXP (SET_SRC (x), 0),
4649                                                 pos, NULL_RTX, 1, 1, 0, 0);
4650               if (extraction != 0)
4651                 {
4652                   SUBST (SET_SRC (x), extraction);
4653                   return find_split_point (loc, insn, false);
4654                 }
4655             }
4656           break;
4657
4658         case NE:
4659           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660              is known to be on, this can be converted into a NEG of a shift.  */
4661           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4662               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4663               && 1 <= (pos = exact_log2
4664                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4665                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4666             {
4667               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4668
4669               SUBST (SET_SRC (x),
4670                      gen_rtx_NEG (mode,
4671                                   gen_rtx_LSHIFTRT (mode,
4672                                                     XEXP (SET_SRC (x), 0),
4673                                                     GEN_INT (pos))));
4674
4675               split = find_split_point (&SET_SRC (x), insn, true);
4676               if (split && split != &SET_SRC (x))
4677                 return split;
4678             }
4679           break;
4680
4681         case SIGN_EXTEND:
4682           inner = XEXP (SET_SRC (x), 0);
4683
4684           /* We can't optimize if either mode is a partial integer
4685              mode as we don't know how many bits are significant
4686              in those modes.  */
4687           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4688               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4689             break;
4690
4691           pos = 0;
4692           len = GET_MODE_PRECISION (GET_MODE (inner));
4693           unsignedp = 0;
4694           break;
4695
4696         case SIGN_EXTRACT:
4697         case ZERO_EXTRACT:
4698           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4699               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4700             {
4701               inner = XEXP (SET_SRC (x), 0);
4702               len = INTVAL (XEXP (SET_SRC (x), 1));
4703               pos = INTVAL (XEXP (SET_SRC (x), 2));
4704
4705               if (BITS_BIG_ENDIAN)
4706                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4707               unsignedp = (code == ZERO_EXTRACT);
4708             }
4709           break;
4710
4711         default:
4712           break;
4713         }
4714
4715       if (len && pos >= 0
4716           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4717         {
4718           enum machine_mode mode = GET_MODE (SET_SRC (x));
4719
4720           /* For unsigned, we have a choice of a shift followed by an
4721              AND or two shifts.  Use two shifts for field sizes where the
4722              constant might be too large.  We assume here that we can
4723              always at least get 8-bit constants in an AND insn, which is
4724              true for every current RISC.  */
4725
4726           if (unsignedp && len <= 8)
4727             {
4728               SUBST (SET_SRC (x),
4729                      gen_rtx_AND (mode,
4730                                   gen_rtx_LSHIFTRT
4731                                   (mode, gen_lowpart (mode, inner),
4732                                    GEN_INT (pos)),
4733                                   GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4734                                            - 1)));
4735
4736               split = find_split_point (&SET_SRC (x), insn, true);
4737               if (split && split != &SET_SRC (x))
4738                 return split;
4739             }
4740           else
4741             {
4742               SUBST (SET_SRC (x),
4743                      gen_rtx_fmt_ee
4744                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4745                       gen_rtx_ASHIFT (mode,
4746                                       gen_lowpart (mode, inner),
4747                                       GEN_INT (GET_MODE_PRECISION (mode)
4748                                                - len - pos)),
4749                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4750
4751               split = find_split_point (&SET_SRC (x), insn, true);
4752               if (split && split != &SET_SRC (x))
4753                 return split;
4754             }
4755         }
4756
4757       /* See if this is a simple operation with a constant as the second
4758          operand.  It might be that this constant is out of range and hence
4759          could be used as a split point.  */
4760       if (BINARY_P (SET_SRC (x))
4761           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4762           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4763               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4764                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4765         return &XEXP (SET_SRC (x), 1);
4766
4767       /* Finally, see if this is a simple operation with its first operand
4768          not in a register.  The operation might require this operand in a
4769          register, so return it as a split point.  We can always do this
4770          because if the first operand were another operation, we would have
4771          already found it as a split point.  */
4772       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4773           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4774         return &XEXP (SET_SRC (x), 0);
4775
4776       return 0;
4777
4778     case AND:
4779     case IOR:
4780       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4781          it is better to write this as (not (ior A B)) so we can split it.
4782          Similarly for IOR.  */
4783       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4784         {
4785           SUBST (*loc,
4786                  gen_rtx_NOT (GET_MODE (x),
4787                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4788                                               GET_MODE (x),
4789                                               XEXP (XEXP (x, 0), 0),
4790                                               XEXP (XEXP (x, 1), 0))));
4791           return find_split_point (loc, insn, set_src);
4792         }
4793
4794       /* Many RISC machines have a large set of logical insns.  If the
4795          second operand is a NOT, put it first so we will try to split the
4796          other operand first.  */
4797       if (GET_CODE (XEXP (x, 1)) == NOT)
4798         {
4799           rtx tem = XEXP (x, 0);
4800           SUBST (XEXP (x, 0), XEXP (x, 1));
4801           SUBST (XEXP (x, 1), tem);
4802         }
4803       break;
4804
4805     case PLUS:
4806     case MINUS:
4807       /* Canonicalization can produce (minus A (mult B C)), where C is a
4808          constant.  It may be better to try splitting (plus (mult B -C) A)
4809          instead if this isn't a multiply by a power of two.  */
4810       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4811           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4812           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4813         {
4814           enum machine_mode mode = GET_MODE (x);
4815           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4816           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4817           SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4818                                                          XEXP (XEXP (x, 1), 0),
4819                                                          GEN_INT (other_int)),
4820                                      XEXP (x, 0)));
4821           return find_split_point (loc, insn, set_src);
4822         }
4823
4824       /* Split at a multiply-accumulate instruction.  However if this is
4825          the SET_SRC, we likely do not have such an instruction and it's
4826          worthless to try this split.  */
4827       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4828         return loc;
4829
4830     default:
4831       break;
4832     }
4833
4834   /* Otherwise, select our actions depending on our rtx class.  */
4835   switch (GET_RTX_CLASS (code))
4836     {
4837     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4838     case RTX_TERNARY:
4839       split = find_split_point (&XEXP (x, 2), insn, false);
4840       if (split)
4841         return split;
4842       /* ... fall through ...  */
4843     case RTX_BIN_ARITH:
4844     case RTX_COMM_ARITH:
4845     case RTX_COMPARE:
4846     case RTX_COMM_COMPARE:
4847       split = find_split_point (&XEXP (x, 1), insn, false);
4848       if (split)
4849         return split;
4850       /* ... fall through ...  */
4851     case RTX_UNARY:
4852       /* Some machines have (and (shift ...) ...) insns.  If X is not
4853          an AND, but XEXP (X, 0) is, use it as our split point.  */
4854       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4855         return &XEXP (x, 0);
4856
4857       split = find_split_point (&XEXP (x, 0), insn, false);
4858       if (split)
4859         return split;
4860       return loc;
4861
4862     default:
4863       /* Otherwise, we don't have a split point.  */
4864       return 0;
4865     }
4866 }
4867 \f
4868 /* Throughout X, replace FROM with TO, and return the result.
4869    The result is TO if X is FROM;
4870    otherwise the result is X, but its contents may have been modified.
4871    If they were modified, a record was made in undobuf so that
4872    undo_all will (among other things) return X to its original state.
4873
4874    If the number of changes necessary is too much to record to undo,
4875    the excess changes are not made, so the result is invalid.
4876    The changes already made can still be undone.
4877    undobuf.num_undo is incremented for such changes, so by testing that
4878    the caller can tell whether the result is valid.
4879
4880    `n_occurrences' is incremented each time FROM is replaced.
4881
4882    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4883
4884    IN_COND is nonzero if we are at the top level of a condition.
4885
4886    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4887    by copying if `n_occurrences' is nonzero.  */
4888
4889 static rtx
4890 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4891 {
4892   enum rtx_code code = GET_CODE (x);
4893   enum machine_mode op0_mode = VOIDmode;
4894   const char *fmt;
4895   int len, i;
4896   rtx new_rtx;
4897
4898 /* Two expressions are equal if they are identical copies of a shared
4899    RTX or if they are both registers with the same register number
4900    and mode.  */
4901
4902 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4903   ((X) == (Y)                                           \
4904    || (REG_P (X) && REG_P (Y)   \
4905        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4906
4907   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4908     {
4909       n_occurrences++;
4910       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4911     }
4912
4913   /* If X and FROM are the same register but different modes, they
4914      will not have been seen as equal above.  However, the log links code
4915      will make a LOG_LINKS entry for that case.  If we do nothing, we
4916      will try to rerecognize our original insn and, when it succeeds,
4917      we will delete the feeding insn, which is incorrect.
4918
4919      So force this insn not to match in this (rare) case.  */
4920   if (! in_dest && code == REG && REG_P (from)
4921       && reg_overlap_mentioned_p (x, from))
4922     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4923
4924   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4925      of which may contain things that can be combined.  */
4926   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4927     return x;
4928
4929   /* It is possible to have a subexpression appear twice in the insn.
4930      Suppose that FROM is a register that appears within TO.
4931      Then, after that subexpression has been scanned once by `subst',
4932      the second time it is scanned, TO may be found.  If we were
4933      to scan TO here, we would find FROM within it and create a
4934      self-referent rtl structure which is completely wrong.  */
4935   if (COMBINE_RTX_EQUAL_P (x, to))
4936     return to;
4937
4938   /* Parallel asm_operands need special attention because all of the
4939      inputs are shared across the arms.  Furthermore, unsharing the
4940      rtl results in recognition failures.  Failure to handle this case
4941      specially can result in circular rtl.
4942
4943      Solve this by doing a normal pass across the first entry of the
4944      parallel, and only processing the SET_DESTs of the subsequent
4945      entries.  Ug.  */
4946
4947   if (code == PARALLEL
4948       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4949       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4950     {
4951       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4952
4953       /* If this substitution failed, this whole thing fails.  */
4954       if (GET_CODE (new_rtx) == CLOBBER
4955           && XEXP (new_rtx, 0) == const0_rtx)
4956         return new_rtx;
4957
4958       SUBST (XVECEXP (x, 0, 0), new_rtx);
4959
4960       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4961         {
4962           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4963
4964           if (!REG_P (dest)
4965               && GET_CODE (dest) != CC0
4966               && GET_CODE (dest) != PC)
4967             {
4968               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4969
4970               /* If this substitution failed, this whole thing fails.  */
4971               if (GET_CODE (new_rtx) == CLOBBER
4972                   && XEXP (new_rtx, 0) == const0_rtx)
4973                 return new_rtx;
4974
4975               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4976             }
4977         }
4978     }
4979   else
4980     {
4981       len = GET_RTX_LENGTH (code);
4982       fmt = GET_RTX_FORMAT (code);
4983
4984       /* We don't need to process a SET_DEST that is a register, CC0,
4985          or PC, so set up to skip this common case.  All other cases
4986          where we want to suppress replacing something inside a
4987          SET_SRC are handled via the IN_DEST operand.  */
4988       if (code == SET
4989           && (REG_P (SET_DEST (x))
4990               || GET_CODE (SET_DEST (x)) == CC0
4991               || GET_CODE (SET_DEST (x)) == PC))
4992         fmt = "ie";
4993
4994       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4995          constant.  */
4996       if (fmt[0] == 'e')
4997         op0_mode = GET_MODE (XEXP (x, 0));
4998
4999       for (i = 0; i < len; i++)
5000         {
5001           if (fmt[i] == 'E')
5002             {
5003               int j;
5004               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5005                 {
5006                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5007                     {
5008                       new_rtx = (unique_copy && n_occurrences
5009                              ? copy_rtx (to) : to);
5010                       n_occurrences++;
5011                     }
5012                   else
5013                     {
5014                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5015                                        unique_copy);
5016
5017                       /* If this substitution failed, this whole thing
5018                          fails.  */
5019                       if (GET_CODE (new_rtx) == CLOBBER
5020                           && XEXP (new_rtx, 0) == const0_rtx)
5021                         return new_rtx;
5022                     }
5023
5024                   SUBST (XVECEXP (x, i, j), new_rtx);
5025                 }
5026             }
5027           else if (fmt[i] == 'e')
5028             {
5029               /* If this is a register being set, ignore it.  */
5030               new_rtx = XEXP (x, i);
5031               if (in_dest
5032                   && i == 0
5033                   && (((code == SUBREG || code == ZERO_EXTRACT)
5034                        && REG_P (new_rtx))
5035                       || code == STRICT_LOW_PART))
5036                 ;
5037
5038               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5039                 {
5040                   /* In general, don't install a subreg involving two
5041                      modes not tieable.  It can worsen register
5042                      allocation, and can even make invalid reload
5043                      insns, since the reg inside may need to be copied
5044                      from in the outside mode, and that may be invalid
5045                      if it is an fp reg copied in integer mode.
5046
5047                      We allow two exceptions to this: It is valid if
5048                      it is inside another SUBREG and the mode of that
5049                      SUBREG and the mode of the inside of TO is
5050                      tieable and it is valid if X is a SET that copies
5051                      FROM to CC0.  */
5052
5053                   if (GET_CODE (to) == SUBREG
5054                       && ! MODES_TIEABLE_P (GET_MODE (to),
5055                                             GET_MODE (SUBREG_REG (to)))
5056                       && ! (code == SUBREG
5057                             && MODES_TIEABLE_P (GET_MODE (x),
5058                                                 GET_MODE (SUBREG_REG (to))))
5059 #ifdef HAVE_cc0
5060                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5061 #endif
5062                       )
5063                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5064
5065 #ifdef CANNOT_CHANGE_MODE_CLASS
5066                   if (code == SUBREG
5067                       && REG_P (to)
5068                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5069                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5070                                                    GET_MODE (to),
5071                                                    GET_MODE (x)))
5072                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5073 #endif
5074
5075                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5076                   n_occurrences++;
5077                 }
5078               else
5079                 /* If we are in a SET_DEST, suppress most cases unless we
5080                    have gone inside a MEM, in which case we want to
5081                    simplify the address.  We assume here that things that
5082                    are actually part of the destination have their inner
5083                    parts in the first expression.  This is true for SUBREG,
5084                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5085                    things aside from REG and MEM that should appear in a
5086                    SET_DEST.  */
5087                 new_rtx = subst (XEXP (x, i), from, to,
5088                              (((in_dest
5089                                 && (code == SUBREG || code == STRICT_LOW_PART
5090                                     || code == ZERO_EXTRACT))
5091                                || code == SET)
5092                               && i == 0),
5093                                  code == IF_THEN_ELSE && i == 0,
5094                                  unique_copy);
5095
5096               /* If we found that we will have to reject this combination,
5097                  indicate that by returning the CLOBBER ourselves, rather than
5098                  an expression containing it.  This will speed things up as
5099                  well as prevent accidents where two CLOBBERs are considered
5100                  to be equal, thus producing an incorrect simplification.  */
5101
5102               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5103                 return new_rtx;
5104
5105               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5106                 {
5107                   enum machine_mode mode = GET_MODE (x);
5108
5109                   x = simplify_subreg (GET_MODE (x), new_rtx,
5110                                        GET_MODE (SUBREG_REG (x)),
5111                                        SUBREG_BYTE (x));
5112                   if (! x)
5113                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5114                 }
5115               else if (CONST_INT_P (new_rtx)
5116                        && GET_CODE (x) == ZERO_EXTEND)
5117                 {
5118                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5119                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5120                   gcc_assert (x);
5121                 }
5122               else
5123                 SUBST (XEXP (x, i), new_rtx);
5124             }
5125         }
5126     }
5127
5128   /* Check if we are loading something from the constant pool via float
5129      extension; in this case we would undo compress_float_constant
5130      optimization and degenerate constant load to an immediate value.  */
5131   if (GET_CODE (x) == FLOAT_EXTEND
5132       && MEM_P (XEXP (x, 0))
5133       && MEM_READONLY_P (XEXP (x, 0)))
5134     {
5135       rtx tmp = avoid_constant_pool_reference (x);
5136       if (x != tmp)
5137         return x;
5138     }
5139
5140   /* Try to simplify X.  If the simplification changed the code, it is likely
5141      that further simplification will help, so loop, but limit the number
5142      of repetitions that will be performed.  */
5143
5144   for (i = 0; i < 4; i++)
5145     {
5146       /* If X is sufficiently simple, don't bother trying to do anything
5147          with it.  */
5148       if (code != CONST_INT && code != REG && code != CLOBBER)
5149         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5150
5151       if (GET_CODE (x) == code)
5152         break;
5153
5154       code = GET_CODE (x);
5155
5156       /* We no longer know the original mode of operand 0 since we
5157          have changed the form of X)  */
5158       op0_mode = VOIDmode;
5159     }
5160
5161   return x;
5162 }
5163 \f
5164 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5165    outer level; call `subst' to simplify recursively.  Return the new
5166    expression.
5167
5168    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5169    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5170    of a condition.  */
5171
5172 static rtx
5173 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5174                       int in_cond)
5175 {
5176   enum rtx_code code = GET_CODE (x);
5177   enum machine_mode mode = GET_MODE (x);
5178   rtx temp;
5179   int i;
5180
5181   /* If this is a commutative operation, put a constant last and a complex
5182      expression first.  We don't need to do this for comparisons here.  */
5183   if (COMMUTATIVE_ARITH_P (x)
5184       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5185     {
5186       temp = XEXP (x, 0);
5187       SUBST (XEXP (x, 0), XEXP (x, 1));
5188       SUBST (XEXP (x, 1), temp);
5189     }
5190
5191   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5192      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5193      things.  Check for cases where both arms are testing the same
5194      condition.
5195
5196      Don't do anything if all operands are very simple.  */
5197
5198   if ((BINARY_P (x)
5199        && ((!OBJECT_P (XEXP (x, 0))
5200             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5201                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5202            || (!OBJECT_P (XEXP (x, 1))
5203                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5204                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5205       || (UNARY_P (x)
5206           && (!OBJECT_P (XEXP (x, 0))
5207                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5208                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5209     {
5210       rtx cond, true_rtx, false_rtx;
5211
5212       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5213       if (cond != 0
5214           /* If everything is a comparison, what we have is highly unlikely
5215              to be simpler, so don't use it.  */
5216           && ! (COMPARISON_P (x)
5217                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5218         {
5219           rtx cop1 = const0_rtx;
5220           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5221
5222           if (cond_code == NE && COMPARISON_P (cond))
5223             return x;
5224
5225           /* Simplify the alternative arms; this may collapse the true and
5226              false arms to store-flag values.  Be careful to use copy_rtx
5227              here since true_rtx or false_rtx might share RTL with x as a
5228              result of the if_then_else_cond call above.  */
5229           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5230           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5231
5232           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5233              is unlikely to be simpler.  */
5234           if (general_operand (true_rtx, VOIDmode)
5235               && general_operand (false_rtx, VOIDmode))
5236             {
5237               enum rtx_code reversed;
5238
5239               /* Restarting if we generate a store-flag expression will cause
5240                  us to loop.  Just drop through in this case.  */
5241
5242               /* If the result values are STORE_FLAG_VALUE and zero, we can
5243                  just make the comparison operation.  */
5244               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5245                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5246                                              cond, cop1);
5247               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5248                        && ((reversed = reversed_comparison_code_parts
5249                                         (cond_code, cond, cop1, NULL))
5250                            != UNKNOWN))
5251                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5252                                              cond, cop1);
5253
5254               /* Likewise, we can make the negate of a comparison operation
5255                  if the result values are - STORE_FLAG_VALUE and zero.  */
5256               else if (CONST_INT_P (true_rtx)
5257                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5258                        && false_rtx == const0_rtx)
5259                 x = simplify_gen_unary (NEG, mode,
5260                                         simplify_gen_relational (cond_code,
5261                                                                  mode, VOIDmode,
5262                                                                  cond, cop1),
5263                                         mode);
5264               else if (CONST_INT_P (false_rtx)
5265                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5266                        && true_rtx == const0_rtx
5267                        && ((reversed = reversed_comparison_code_parts
5268                                         (cond_code, cond, cop1, NULL))
5269                            != UNKNOWN))
5270                 x = simplify_gen_unary (NEG, mode,
5271                                         simplify_gen_relational (reversed,
5272                                                                  mode, VOIDmode,
5273                                                                  cond, cop1),
5274                                         mode);
5275               else
5276                 return gen_rtx_IF_THEN_ELSE (mode,
5277                                              simplify_gen_relational (cond_code,
5278                                                                       mode,
5279                                                                       VOIDmode,
5280                                                                       cond,
5281                                                                       cop1),
5282                                              true_rtx, false_rtx);
5283
5284               code = GET_CODE (x);
5285               op0_mode = VOIDmode;
5286             }
5287         }
5288     }
5289
5290   /* Try to fold this expression in case we have constants that weren't
5291      present before.  */
5292   temp = 0;
5293   switch (GET_RTX_CLASS (code))
5294     {
5295     case RTX_UNARY:
5296       if (op0_mode == VOIDmode)
5297         op0_mode = GET_MODE (XEXP (x, 0));
5298       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5299       break;
5300     case RTX_COMPARE:
5301     case RTX_COMM_COMPARE:
5302       {
5303         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5304         if (cmp_mode == VOIDmode)
5305           {
5306             cmp_mode = GET_MODE (XEXP (x, 1));
5307             if (cmp_mode == VOIDmode)
5308               cmp_mode = op0_mode;
5309           }
5310         temp = simplify_relational_operation (code, mode, cmp_mode,
5311                                               XEXP (x, 0), XEXP (x, 1));
5312       }
5313       break;
5314     case RTX_COMM_ARITH:
5315     case RTX_BIN_ARITH:
5316       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5317       break;
5318     case RTX_BITFIELD_OPS:
5319     case RTX_TERNARY:
5320       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5321                                          XEXP (x, 1), XEXP (x, 2));
5322       break;
5323     default:
5324       break;
5325     }
5326
5327   if (temp)
5328     {
5329       x = temp;
5330       code = GET_CODE (temp);
5331       op0_mode = VOIDmode;
5332       mode = GET_MODE (temp);
5333     }
5334
5335   /* First see if we can apply the inverse distributive law.  */
5336   if (code == PLUS || code == MINUS
5337       || code == AND || code == IOR || code == XOR)
5338     {
5339       x = apply_distributive_law (x);
5340       code = GET_CODE (x);
5341       op0_mode = VOIDmode;
5342     }
5343
5344   /* If CODE is an associative operation not otherwise handled, see if we
5345      can associate some operands.  This can win if they are constants or
5346      if they are logically related (i.e. (a & b) & a).  */
5347   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5348        || code == AND || code == IOR || code == XOR
5349        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5350       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5351           || (flag_associative_math && FLOAT_MODE_P (mode))))
5352     {
5353       if (GET_CODE (XEXP (x, 0)) == code)
5354         {
5355           rtx other = XEXP (XEXP (x, 0), 0);
5356           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5357           rtx inner_op1 = XEXP (x, 1);
5358           rtx inner;
5359
5360           /* Make sure we pass the constant operand if any as the second
5361              one if this is a commutative operation.  */
5362           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5363             {
5364               rtx tem = inner_op0;
5365               inner_op0 = inner_op1;
5366               inner_op1 = tem;
5367             }
5368           inner = simplify_binary_operation (code == MINUS ? PLUS
5369                                              : code == DIV ? MULT
5370                                              : code,
5371                                              mode, inner_op0, inner_op1);
5372
5373           /* For commutative operations, try the other pair if that one
5374              didn't simplify.  */
5375           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5376             {
5377               other = XEXP (XEXP (x, 0), 1);
5378               inner = simplify_binary_operation (code, mode,
5379                                                  XEXP (XEXP (x, 0), 0),
5380                                                  XEXP (x, 1));
5381             }
5382
5383           if (inner)
5384             return simplify_gen_binary (code, mode, other, inner);
5385         }
5386     }
5387
5388   /* A little bit of algebraic simplification here.  */
5389   switch (code)
5390     {
5391     case MEM:
5392       /* Ensure that our address has any ASHIFTs converted to MULT in case
5393          address-recognizing predicates are called later.  */
5394       temp = make_compound_operation (XEXP (x, 0), MEM);
5395       SUBST (XEXP (x, 0), temp);
5396       break;
5397
5398     case SUBREG:
5399       if (op0_mode == VOIDmode)
5400         op0_mode = GET_MODE (SUBREG_REG (x));
5401
5402       /* See if this can be moved to simplify_subreg.  */
5403       if (CONSTANT_P (SUBREG_REG (x))
5404           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5405              /* Don't call gen_lowpart if the inner mode
5406                 is VOIDmode and we cannot simplify it, as SUBREG without
5407                 inner mode is invalid.  */
5408           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5409               || gen_lowpart_common (mode, SUBREG_REG (x))))
5410         return gen_lowpart (mode, SUBREG_REG (x));
5411
5412       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5413         break;
5414       {
5415         rtx temp;
5416         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5417                                 SUBREG_BYTE (x));
5418         if (temp)
5419           return temp;
5420
5421         /* If op is known to have all lower bits zero, the result is zero.  */
5422         if (!in_dest
5423             && SCALAR_INT_MODE_P (mode)
5424             && SCALAR_INT_MODE_P (op0_mode)
5425             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5426             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5427             && HWI_COMPUTABLE_MODE_P (op0_mode)
5428             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5429                 & GET_MODE_MASK (mode)) == 0)
5430           return CONST0_RTX (mode);
5431       }
5432
5433       /* Don't change the mode of the MEM if that would change the meaning
5434          of the address.  */
5435       if (MEM_P (SUBREG_REG (x))
5436           && (MEM_VOLATILE_P (SUBREG_REG (x))
5437               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5438                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5439         return gen_rtx_CLOBBER (mode, const0_rtx);
5440
5441       /* Note that we cannot do any narrowing for non-constants since
5442          we might have been counting on using the fact that some bits were
5443          zero.  We now do this in the SET.  */
5444
5445       break;
5446
5447     case NEG:
5448       temp = expand_compound_operation (XEXP (x, 0));
5449
5450       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5451          replaced by (lshiftrt X C).  This will convert
5452          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5453
5454       if (GET_CODE (temp) == ASHIFTRT
5455           && CONST_INT_P (XEXP (temp, 1))
5456           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5457         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5458                                      INTVAL (XEXP (temp, 1)));
5459
5460       /* If X has only a single bit that might be nonzero, say, bit I, convert
5461          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5462          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5463          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5464          or a SUBREG of one since we'd be making the expression more
5465          complex if it was just a register.  */
5466
5467       if (!REG_P (temp)
5468           && ! (GET_CODE (temp) == SUBREG
5469                 && REG_P (SUBREG_REG (temp)))
5470           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5471         {
5472           rtx temp1 = simplify_shift_const
5473             (NULL_RTX, ASHIFTRT, mode,
5474              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5475                                    GET_MODE_PRECISION (mode) - 1 - i),
5476              GET_MODE_PRECISION (mode) - 1 - i);
5477
5478           /* If all we did was surround TEMP with the two shifts, we
5479              haven't improved anything, so don't use it.  Otherwise,
5480              we are better off with TEMP1.  */
5481           if (GET_CODE (temp1) != ASHIFTRT
5482               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5483               || XEXP (XEXP (temp1, 0), 0) != temp)
5484             return temp1;
5485         }
5486       break;
5487
5488     case TRUNCATE:
5489       /* We can't handle truncation to a partial integer mode here
5490          because we don't know the real bitsize of the partial
5491          integer mode.  */
5492       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5493         break;
5494
5495       if (HWI_COMPUTABLE_MODE_P (mode))
5496         SUBST (XEXP (x, 0),
5497                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5498                               GET_MODE_MASK (mode), 0));
5499
5500       /* We can truncate a constant value and return it.  */
5501       if (CONST_INT_P (XEXP (x, 0)))
5502         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5503
5504       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5505          whose value is a comparison can be replaced with a subreg if
5506          STORE_FLAG_VALUE permits.  */
5507       if (HWI_COMPUTABLE_MODE_P (mode)
5508           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5509           && (temp = get_last_value (XEXP (x, 0)))
5510           && COMPARISON_P (temp))
5511         return gen_lowpart (mode, XEXP (x, 0));
5512       break;
5513
5514     case CONST:
5515       /* (const (const X)) can become (const X).  Do it this way rather than
5516          returning the inner CONST since CONST can be shared with a
5517          REG_EQUAL note.  */
5518       if (GET_CODE (XEXP (x, 0)) == CONST)
5519         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5520       break;
5521
5522 #ifdef HAVE_lo_sum
5523     case LO_SUM:
5524       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5525          can add in an offset.  find_split_point will split this address up
5526          again if it doesn't match.  */
5527       if (GET_CODE (XEXP (x, 0)) == HIGH
5528           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5529         return XEXP (x, 1);
5530       break;
5531 #endif
5532
5533     case PLUS:
5534       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5535          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5536          bit-field and can be replaced by either a sign_extend or a
5537          sign_extract.  The `and' may be a zero_extend and the two
5538          <c>, -<c> constants may be reversed.  */
5539       if (GET_CODE (XEXP (x, 0)) == XOR
5540           && CONST_INT_P (XEXP (x, 1))
5541           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5542           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5543           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5544               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5545           && HWI_COMPUTABLE_MODE_P (mode)
5546           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5547                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5548                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5549                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5550               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5551                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5552                       == (unsigned int) i + 1))))
5553         return simplify_shift_const
5554           (NULL_RTX, ASHIFTRT, mode,
5555            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5556                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5557                                  GET_MODE_PRECISION (mode) - (i + 1)),
5558            GET_MODE_PRECISION (mode) - (i + 1));
5559
5560       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5561          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5562          the bitsize of the mode - 1.  This allows simplification of
5563          "a = (b & 8) == 0;"  */
5564       if (XEXP (x, 1) == constm1_rtx
5565           && !REG_P (XEXP (x, 0))
5566           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5567                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5568           && nonzero_bits (XEXP (x, 0), mode) == 1)
5569         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5570            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5571                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5572                                  GET_MODE_PRECISION (mode) - 1),
5573            GET_MODE_PRECISION (mode) - 1);
5574
5575       /* If we are adding two things that have no bits in common, convert
5576          the addition into an IOR.  This will often be further simplified,
5577          for example in cases like ((a & 1) + (a & 2)), which can
5578          become a & 3.  */
5579
5580       if (HWI_COMPUTABLE_MODE_P (mode)
5581           && (nonzero_bits (XEXP (x, 0), mode)
5582               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5583         {
5584           /* Try to simplify the expression further.  */
5585           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5586           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5587
5588           /* If we could, great.  If not, do not go ahead with the IOR
5589              replacement, since PLUS appears in many special purpose
5590              address arithmetic instructions.  */
5591           if (GET_CODE (temp) != CLOBBER
5592               && (GET_CODE (temp) != IOR
5593                   || ((XEXP (temp, 0) != XEXP (x, 0)
5594                        || XEXP (temp, 1) != XEXP (x, 1))
5595                       && (XEXP (temp, 0) != XEXP (x, 1)
5596                           || XEXP (temp, 1) != XEXP (x, 0)))))
5597             return temp;
5598         }
5599       break;
5600
5601     case MINUS:
5602       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5603          (and <foo> (const_int pow2-1))  */
5604       if (GET_CODE (XEXP (x, 1)) == AND
5605           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5606           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5607           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5608         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5609                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5610       break;
5611
5612     case MULT:
5613       /* If we have (mult (plus A B) C), apply the distributive law and then
5614          the inverse distributive law to see if things simplify.  This
5615          occurs mostly in addresses, often when unrolling loops.  */
5616
5617       if (GET_CODE (XEXP (x, 0)) == PLUS)
5618         {
5619           rtx result = distribute_and_simplify_rtx (x, 0);
5620           if (result)
5621             return result;
5622         }
5623
5624       /* Try simplify a*(b/c) as (a*b)/c.  */
5625       if (FLOAT_MODE_P (mode) && flag_associative_math
5626           && GET_CODE (XEXP (x, 0)) == DIV)
5627         {
5628           rtx tem = simplify_binary_operation (MULT, mode,
5629                                                XEXP (XEXP (x, 0), 0),
5630                                                XEXP (x, 1));
5631           if (tem)
5632             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5633         }
5634       break;
5635
5636     case UDIV:
5637       /* If this is a divide by a power of two, treat it as a shift if
5638          its first operand is a shift.  */
5639       if (CONST_INT_P (XEXP (x, 1))
5640           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5641           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5642               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5643               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5644               || GET_CODE (XEXP (x, 0)) == ROTATE
5645               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5646         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5647       break;
5648
5649     case EQ:  case NE:
5650     case GT:  case GTU:  case GE:  case GEU:
5651     case LT:  case LTU:  case LE:  case LEU:
5652     case UNEQ:  case LTGT:
5653     case UNGT:  case UNGE:
5654     case UNLT:  case UNLE:
5655     case UNORDERED: case ORDERED:
5656       /* If the first operand is a condition code, we can't do anything
5657          with it.  */
5658       if (GET_CODE (XEXP (x, 0)) == COMPARE
5659           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5660               && ! CC0_P (XEXP (x, 0))))
5661         {
5662           rtx op0 = XEXP (x, 0);
5663           rtx op1 = XEXP (x, 1);
5664           enum rtx_code new_code;
5665
5666           if (GET_CODE (op0) == COMPARE)
5667             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5668
5669           /* Simplify our comparison, if possible.  */
5670           new_code = simplify_comparison (code, &op0, &op1);
5671
5672           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5673              if only the low-order bit is possibly nonzero in X (such as when
5674              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5675              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5676              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5677              (plus X 1).
5678
5679              Remove any ZERO_EXTRACT we made when thinking this was a
5680              comparison.  It may now be simpler to use, e.g., an AND.  If a
5681              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5682              the call to make_compound_operation in the SET case.
5683
5684              Don't apply these optimizations if the caller would
5685              prefer a comparison rather than a value.
5686              E.g., for the condition in an IF_THEN_ELSE most targets need
5687              an explicit comparison.  */
5688
5689           if (in_cond)
5690             ;
5691
5692           else if (STORE_FLAG_VALUE == 1
5693               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5694               && op1 == const0_rtx
5695               && mode == GET_MODE (op0)
5696               && nonzero_bits (op0, mode) == 1)
5697             return gen_lowpart (mode,
5698                                 expand_compound_operation (op0));
5699
5700           else if (STORE_FLAG_VALUE == 1
5701                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5702                    && op1 == const0_rtx
5703                    && mode == GET_MODE (op0)
5704                    && (num_sign_bit_copies (op0, mode)
5705                        == GET_MODE_PRECISION (mode)))
5706             {
5707               op0 = expand_compound_operation (op0);
5708               return simplify_gen_unary (NEG, mode,
5709                                          gen_lowpart (mode, op0),
5710                                          mode);
5711             }
5712
5713           else if (STORE_FLAG_VALUE == 1
5714                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5715                    && op1 == const0_rtx
5716                    && mode == GET_MODE (op0)
5717                    && nonzero_bits (op0, mode) == 1)
5718             {
5719               op0 = expand_compound_operation (op0);
5720               return simplify_gen_binary (XOR, mode,
5721                                           gen_lowpart (mode, op0),
5722                                           const1_rtx);
5723             }
5724
5725           else if (STORE_FLAG_VALUE == 1
5726                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5727                    && op1 == const0_rtx
5728                    && mode == GET_MODE (op0)
5729                    && (num_sign_bit_copies (op0, mode)
5730                        == GET_MODE_PRECISION (mode)))
5731             {
5732               op0 = expand_compound_operation (op0);
5733               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5734             }
5735
5736           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5737              those above.  */
5738           if (in_cond)
5739             ;
5740
5741           else if (STORE_FLAG_VALUE == -1
5742               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5743               && op1 == const0_rtx
5744               && (num_sign_bit_copies (op0, mode)
5745                   == GET_MODE_PRECISION (mode)))
5746             return gen_lowpart (mode,
5747                                 expand_compound_operation (op0));
5748
5749           else if (STORE_FLAG_VALUE == -1
5750                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5751                    && op1 == const0_rtx
5752                    && mode == GET_MODE (op0)
5753                    && nonzero_bits (op0, mode) == 1)
5754             {
5755               op0 = expand_compound_operation (op0);
5756               return simplify_gen_unary (NEG, mode,
5757                                          gen_lowpart (mode, op0),
5758                                          mode);
5759             }
5760
5761           else if (STORE_FLAG_VALUE == -1
5762                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5763                    && op1 == const0_rtx
5764                    && mode == GET_MODE (op0)
5765                    && (num_sign_bit_copies (op0, mode)
5766                        == GET_MODE_PRECISION (mode)))
5767             {
5768               op0 = expand_compound_operation (op0);
5769               return simplify_gen_unary (NOT, mode,
5770                                          gen_lowpart (mode, op0),
5771                                          mode);
5772             }
5773
5774           /* If X is 0/1, (eq X 0) is X-1.  */
5775           else if (STORE_FLAG_VALUE == -1
5776                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5777                    && op1 == const0_rtx
5778                    && mode == GET_MODE (op0)
5779                    && nonzero_bits (op0, mode) == 1)
5780             {
5781               op0 = expand_compound_operation (op0);
5782               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5783             }
5784
5785           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5786              one bit that might be nonzero, we can convert (ne x 0) to
5787              (ashift x c) where C puts the bit in the sign bit.  Remove any
5788              AND with STORE_FLAG_VALUE when we are done, since we are only
5789              going to test the sign bit.  */
5790           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5791               && HWI_COMPUTABLE_MODE_P (mode)
5792               && val_signbit_p (mode, STORE_FLAG_VALUE)
5793               && op1 == const0_rtx
5794               && mode == GET_MODE (op0)
5795               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5796             {
5797               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5798                                         expand_compound_operation (op0),
5799                                         GET_MODE_PRECISION (mode) - 1 - i);
5800               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5801                 return XEXP (x, 0);
5802               else
5803                 return x;
5804             }
5805
5806           /* If the code changed, return a whole new comparison.
5807              We also need to avoid using SUBST in cases where
5808              simplify_comparison has widened a comparison with a CONST_INT,
5809              since in that case the wider CONST_INT may fail the sanity
5810              checks in do_SUBST.  */
5811           if (new_code != code
5812               || (CONST_INT_P (op1)
5813                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5814                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5815             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5816
5817           /* Otherwise, keep this operation, but maybe change its operands.
5818              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5819           SUBST (XEXP (x, 0), op0);
5820           SUBST (XEXP (x, 1), op1);
5821         }
5822       break;
5823
5824     case IF_THEN_ELSE:
5825       return simplify_if_then_else (x);
5826
5827     case ZERO_EXTRACT:
5828     case SIGN_EXTRACT:
5829     case ZERO_EXTEND:
5830     case SIGN_EXTEND:
5831       /* If we are processing SET_DEST, we are done.  */
5832       if (in_dest)
5833         return x;
5834
5835       return expand_compound_operation (x);
5836
5837     case SET:
5838       return simplify_set (x);
5839
5840     case AND:
5841     case IOR:
5842       return simplify_logical (x);
5843
5844     case ASHIFT:
5845     case LSHIFTRT:
5846     case ASHIFTRT:
5847     case ROTATE:
5848     case ROTATERT:
5849       /* If this is a shift by a constant amount, simplify it.  */
5850       if (CONST_INT_P (XEXP (x, 1)))
5851         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5852                                      INTVAL (XEXP (x, 1)));
5853
5854       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5855         SUBST (XEXP (x, 1),
5856                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5857                               ((unsigned HOST_WIDE_INT) 1
5858                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5859                               - 1,
5860                               0));
5861       break;
5862
5863     default:
5864       break;
5865     }
5866
5867   return x;
5868 }
5869 \f
5870 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5871
5872 static rtx
5873 simplify_if_then_else (rtx x)
5874 {
5875   enum machine_mode mode = GET_MODE (x);
5876   rtx cond = XEXP (x, 0);
5877   rtx true_rtx = XEXP (x, 1);
5878   rtx false_rtx = XEXP (x, 2);
5879   enum rtx_code true_code = GET_CODE (cond);
5880   int comparison_p = COMPARISON_P (cond);
5881   rtx temp;
5882   int i;
5883   enum rtx_code false_code;
5884   rtx reversed;
5885
5886   /* Simplify storing of the truth value.  */
5887   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5888     return simplify_gen_relational (true_code, mode, VOIDmode,
5889                                     XEXP (cond, 0), XEXP (cond, 1));
5890
5891   /* Also when the truth value has to be reversed.  */
5892   if (comparison_p
5893       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5894       && (reversed = reversed_comparison (cond, mode)))
5895     return reversed;
5896
5897   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5898      in it is being compared against certain values.  Get the true and false
5899      comparisons and see if that says anything about the value of each arm.  */
5900
5901   if (comparison_p
5902       && ((false_code = reversed_comparison_code (cond, NULL))
5903           != UNKNOWN)
5904       && REG_P (XEXP (cond, 0)))
5905     {
5906       HOST_WIDE_INT nzb;
5907       rtx from = XEXP (cond, 0);
5908       rtx true_val = XEXP (cond, 1);
5909       rtx false_val = true_val;
5910       int swapped = 0;
5911
5912       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5913
5914       if (false_code == EQ)
5915         {
5916           swapped = 1, true_code = EQ, false_code = NE;
5917           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5918         }
5919
5920       /* If we are comparing against zero and the expression being tested has
5921          only a single bit that might be nonzero, that is its value when it is
5922          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5923
5924       if (true_code == EQ && true_val == const0_rtx
5925           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5926         {
5927           false_code = EQ;
5928           false_val = gen_int_mode (nzb, GET_MODE (from));
5929         }
5930       else if (true_code == EQ && true_val == const0_rtx
5931                && (num_sign_bit_copies (from, GET_MODE (from))
5932                    == GET_MODE_PRECISION (GET_MODE (from))))
5933         {
5934           false_code = EQ;
5935           false_val = constm1_rtx;
5936         }
5937
5938       /* Now simplify an arm if we know the value of the register in the
5939          branch and it is used in the arm.  Be careful due to the potential
5940          of locally-shared RTL.  */
5941
5942       if (reg_mentioned_p (from, true_rtx))
5943         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5944                                       from, true_val),
5945                           pc_rtx, pc_rtx, 0, 0, 0);
5946       if (reg_mentioned_p (from, false_rtx))
5947         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5948                                    from, false_val),
5949                            pc_rtx, pc_rtx, 0, 0, 0);
5950
5951       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5952       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5953
5954       true_rtx = XEXP (x, 1);
5955       false_rtx = XEXP (x, 2);
5956       true_code = GET_CODE (cond);
5957     }
5958
5959   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5960      reversed, do so to avoid needing two sets of patterns for
5961      subtract-and-branch insns.  Similarly if we have a constant in the true
5962      arm, the false arm is the same as the first operand of the comparison, or
5963      the false arm is more complicated than the true arm.  */
5964
5965   if (comparison_p
5966       && reversed_comparison_code (cond, NULL) != UNKNOWN
5967       && (true_rtx == pc_rtx
5968           || (CONSTANT_P (true_rtx)
5969               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5970           || true_rtx == const0_rtx
5971           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5972           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5973               && !OBJECT_P (false_rtx))
5974           || reg_mentioned_p (true_rtx, false_rtx)
5975           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5976     {
5977       true_code = reversed_comparison_code (cond, NULL);
5978       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5979       SUBST (XEXP (x, 1), false_rtx);
5980       SUBST (XEXP (x, 2), true_rtx);
5981
5982       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5983       cond = XEXP (x, 0);
5984
5985       /* It is possible that the conditional has been simplified out.  */
5986       true_code = GET_CODE (cond);
5987       comparison_p = COMPARISON_P (cond);
5988     }
5989
5990   /* If the two arms are identical, we don't need the comparison.  */
5991
5992   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5993     return true_rtx;
5994
5995   /* Convert a == b ? b : a to "a".  */
5996   if (true_code == EQ && ! side_effects_p (cond)
5997       && !HONOR_NANS (mode)
5998       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5999       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6000     return false_rtx;
6001   else if (true_code == NE && ! side_effects_p (cond)
6002            && !HONOR_NANS (mode)
6003            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6004            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6005     return true_rtx;
6006
6007   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6008
6009   if (GET_MODE_CLASS (mode) == MODE_INT
6010       && comparison_p
6011       && XEXP (cond, 1) == const0_rtx
6012       && GET_CODE (false_rtx) == NEG
6013       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6014       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6015       && ! side_effects_p (true_rtx))
6016     switch (true_code)
6017       {
6018       case GT:
6019       case GE:
6020         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6021       case LT:
6022       case LE:
6023         return
6024           simplify_gen_unary (NEG, mode,
6025                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6026                               mode);
6027       default:
6028         break;
6029       }
6030
6031   /* Look for MIN or MAX.  */
6032
6033   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6034       && comparison_p
6035       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6036       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6037       && ! side_effects_p (cond))
6038     switch (true_code)
6039       {
6040       case GE:
6041       case GT:
6042         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6043       case LE:
6044       case LT:
6045         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6046       case GEU:
6047       case GTU:
6048         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6049       case LEU:
6050       case LTU:
6051         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6052       default:
6053         break;
6054       }
6055
6056   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6057      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6058      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6059      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6060      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6061      neither 1 or -1, but it isn't worth checking for.  */
6062
6063   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6064       && comparison_p
6065       && GET_MODE_CLASS (mode) == MODE_INT
6066       && ! side_effects_p (x))
6067     {
6068       rtx t = make_compound_operation (true_rtx, SET);
6069       rtx f = make_compound_operation (false_rtx, SET);
6070       rtx cond_op0 = XEXP (cond, 0);
6071       rtx cond_op1 = XEXP (cond, 1);
6072       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6073       enum machine_mode m = mode;
6074       rtx z = 0, c1 = NULL_RTX;
6075
6076       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6077            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6078            || GET_CODE (t) == ASHIFT
6079            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6080           && rtx_equal_p (XEXP (t, 0), f))
6081         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6082
6083       /* If an identity-zero op is commutative, check whether there
6084          would be a match if we swapped the operands.  */
6085       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6086                 || GET_CODE (t) == XOR)
6087                && rtx_equal_p (XEXP (t, 1), f))
6088         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6089       else if (GET_CODE (t) == SIGN_EXTEND
6090                && (GET_CODE (XEXP (t, 0)) == PLUS
6091                    || GET_CODE (XEXP (t, 0)) == MINUS
6092                    || GET_CODE (XEXP (t, 0)) == IOR
6093                    || GET_CODE (XEXP (t, 0)) == XOR
6094                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6095                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6096                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6097                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6098                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6099                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6100                && (num_sign_bit_copies (f, GET_MODE (f))
6101                    > (unsigned int)
6102                      (GET_MODE_PRECISION (mode)
6103                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6104         {
6105           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6106           extend_op = SIGN_EXTEND;
6107           m = GET_MODE (XEXP (t, 0));
6108         }
6109       else if (GET_CODE (t) == SIGN_EXTEND
6110                && (GET_CODE (XEXP (t, 0)) == PLUS
6111                    || GET_CODE (XEXP (t, 0)) == IOR
6112                    || GET_CODE (XEXP (t, 0)) == XOR)
6113                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6114                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6115                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6116                && (num_sign_bit_copies (f, GET_MODE (f))
6117                    > (unsigned int)
6118                      (GET_MODE_PRECISION (mode)
6119                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6120         {
6121           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6122           extend_op = SIGN_EXTEND;
6123           m = GET_MODE (XEXP (t, 0));
6124         }
6125       else if (GET_CODE (t) == ZERO_EXTEND
6126                && (GET_CODE (XEXP (t, 0)) == PLUS
6127                    || GET_CODE (XEXP (t, 0)) == MINUS
6128                    || GET_CODE (XEXP (t, 0)) == IOR
6129                    || GET_CODE (XEXP (t, 0)) == XOR
6130                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6131                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6132                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6133                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6134                && HWI_COMPUTABLE_MODE_P (mode)
6135                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6136                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6137                && ((nonzero_bits (f, GET_MODE (f))
6138                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6139                    == 0))
6140         {
6141           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6142           extend_op = ZERO_EXTEND;
6143           m = GET_MODE (XEXP (t, 0));
6144         }
6145       else if (GET_CODE (t) == ZERO_EXTEND
6146                && (GET_CODE (XEXP (t, 0)) == PLUS
6147                    || GET_CODE (XEXP (t, 0)) == IOR
6148                    || GET_CODE (XEXP (t, 0)) == XOR)
6149                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6150                && HWI_COMPUTABLE_MODE_P (mode)
6151                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6152                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6153                && ((nonzero_bits (f, GET_MODE (f))
6154                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6155                    == 0))
6156         {
6157           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6158           extend_op = ZERO_EXTEND;
6159           m = GET_MODE (XEXP (t, 0));
6160         }
6161
6162       if (z)
6163         {
6164           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6165                                                  cond_op0, cond_op1),
6166                         pc_rtx, pc_rtx, 0, 0, 0);
6167           temp = simplify_gen_binary (MULT, m, temp,
6168                                       simplify_gen_binary (MULT, m, c1,
6169                                                            const_true_rtx));
6170           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6171           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6172
6173           if (extend_op != UNKNOWN)
6174             temp = simplify_gen_unary (extend_op, mode, temp, m);
6175
6176           return temp;
6177         }
6178     }
6179
6180   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6181      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6182      negation of a single bit, we can convert this operation to a shift.  We
6183      can actually do this more generally, but it doesn't seem worth it.  */
6184
6185   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6186       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6187       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6188            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6189           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6190                == GET_MODE_PRECISION (mode))
6191               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6192     return
6193       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6194                             gen_lowpart (mode, XEXP (cond, 0)), i);
6195
6196   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6197   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6198       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6199       && GET_MODE (XEXP (cond, 0)) == mode
6200       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6201           == nonzero_bits (XEXP (cond, 0), mode)
6202       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6203     return XEXP (cond, 0);
6204
6205   return x;
6206 }
6207 \f
6208 /* Simplify X, a SET expression.  Return the new expression.  */
6209
6210 static rtx
6211 simplify_set (rtx x)
6212 {
6213   rtx src = SET_SRC (x);
6214   rtx dest = SET_DEST (x);
6215   enum machine_mode mode
6216     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6217   rtx other_insn;
6218   rtx *cc_use;
6219
6220   /* (set (pc) (return)) gets written as (return).  */
6221   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6222     return src;
6223
6224   /* Now that we know for sure which bits of SRC we are using, see if we can
6225      simplify the expression for the object knowing that we only need the
6226      low-order bits.  */
6227
6228   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6229     {
6230       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6231       SUBST (SET_SRC (x), src);
6232     }
6233
6234   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6235      the comparison result and try to simplify it unless we already have used
6236      undobuf.other_insn.  */
6237   if ((GET_MODE_CLASS (mode) == MODE_CC
6238        || GET_CODE (src) == COMPARE
6239        || CC0_P (dest))
6240       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6241       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6242       && COMPARISON_P (*cc_use)
6243       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6244     {
6245       enum rtx_code old_code = GET_CODE (*cc_use);
6246       enum rtx_code new_code;
6247       rtx op0, op1, tmp;
6248       int other_changed = 0;
6249       rtx inner_compare = NULL_RTX;
6250       enum machine_mode compare_mode = GET_MODE (dest);
6251
6252       if (GET_CODE (src) == COMPARE)
6253         {
6254           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6255           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6256             {
6257               inner_compare = op0;
6258               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6259             }
6260         }
6261       else
6262         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6263
6264       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6265                                            op0, op1);
6266       if (!tmp)
6267         new_code = old_code;
6268       else if (!CONSTANT_P (tmp))
6269         {
6270           new_code = GET_CODE (tmp);
6271           op0 = XEXP (tmp, 0);
6272           op1 = XEXP (tmp, 1);
6273         }
6274       else
6275         {
6276           rtx pat = PATTERN (other_insn);
6277           undobuf.other_insn = other_insn;
6278           SUBST (*cc_use, tmp);
6279
6280           /* Attempt to simplify CC user.  */
6281           if (GET_CODE (pat) == SET)
6282             {
6283               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6284               if (new_rtx != NULL_RTX)
6285                 SUBST (SET_SRC (pat), new_rtx);
6286             }
6287
6288           /* Convert X into a no-op move.  */
6289           SUBST (SET_DEST (x), pc_rtx);
6290           SUBST (SET_SRC (x), pc_rtx);
6291           return x;
6292         }
6293
6294       /* Simplify our comparison, if possible.  */
6295       new_code = simplify_comparison (new_code, &op0, &op1);
6296
6297 #ifdef SELECT_CC_MODE
6298       /* If this machine has CC modes other than CCmode, check to see if we
6299          need to use a different CC mode here.  */
6300       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6301         compare_mode = GET_MODE (op0);
6302       else if (inner_compare
6303                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6304                && new_code == old_code
6305                && op0 == XEXP (inner_compare, 0)
6306                && op1 == XEXP (inner_compare, 1))
6307         compare_mode = GET_MODE (inner_compare);
6308       else
6309         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6310
6311 #ifndef HAVE_cc0
6312       /* If the mode changed, we have to change SET_DEST, the mode in the
6313          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6314          a hard register, just build new versions with the proper mode.  If it
6315          is a pseudo, we lose unless it is only time we set the pseudo, in
6316          which case we can safely change its mode.  */
6317       if (compare_mode != GET_MODE (dest))
6318         {
6319           if (can_change_dest_mode (dest, 0, compare_mode))
6320             {
6321               unsigned int regno = REGNO (dest);
6322               rtx new_dest;
6323
6324               if (regno < FIRST_PSEUDO_REGISTER)
6325                 new_dest = gen_rtx_REG (compare_mode, regno);
6326               else
6327                 {
6328                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6329                   new_dest = regno_reg_rtx[regno];
6330                 }
6331
6332               SUBST (SET_DEST (x), new_dest);
6333               SUBST (XEXP (*cc_use, 0), new_dest);
6334               other_changed = 1;
6335
6336               dest = new_dest;
6337             }
6338         }
6339 #endif  /* cc0 */
6340 #endif  /* SELECT_CC_MODE */
6341
6342       /* If the code changed, we have to build a new comparison in
6343          undobuf.other_insn.  */
6344       if (new_code != old_code)
6345         {
6346           int other_changed_previously = other_changed;
6347           unsigned HOST_WIDE_INT mask;
6348           rtx old_cc_use = *cc_use;
6349
6350           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6351                                           dest, const0_rtx));
6352           other_changed = 1;
6353
6354           /* If the only change we made was to change an EQ into an NE or
6355              vice versa, OP0 has only one bit that might be nonzero, and OP1
6356              is zero, check if changing the user of the condition code will
6357              produce a valid insn.  If it won't, we can keep the original code
6358              in that insn by surrounding our operation with an XOR.  */
6359
6360           if (((old_code == NE && new_code == EQ)
6361                || (old_code == EQ && new_code == NE))
6362               && ! other_changed_previously && op1 == const0_rtx
6363               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6364               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6365             {
6366               rtx pat = PATTERN (other_insn), note = 0;
6367
6368               if ((recog_for_combine (&pat, other_insn, &note) < 0
6369                    && ! check_asm_operands (pat)))
6370                 {
6371                   *cc_use = old_cc_use;
6372                   other_changed = 0;
6373
6374                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6375                                              op0, GEN_INT (mask));
6376                 }
6377             }
6378         }
6379
6380       if (other_changed)
6381         undobuf.other_insn = other_insn;
6382
6383       /* Otherwise, if we didn't previously have a COMPARE in the
6384          correct mode, we need one.  */
6385       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6386         {
6387           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6388           src = SET_SRC (x);
6389         }
6390       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6391         {
6392           SUBST (SET_SRC (x), op0);
6393           src = SET_SRC (x);
6394         }
6395       /* Otherwise, update the COMPARE if needed.  */
6396       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6397         {
6398           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6399           src = SET_SRC (x);
6400         }
6401     }
6402   else
6403     {
6404       /* Get SET_SRC in a form where we have placed back any
6405          compound expressions.  Then do the checks below.  */
6406       src = make_compound_operation (src, SET);
6407       SUBST (SET_SRC (x), src);
6408     }
6409
6410   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6411      and X being a REG or (subreg (reg)), we may be able to convert this to
6412      (set (subreg:m2 x) (op)).
6413
6414      We can always do this if M1 is narrower than M2 because that means that
6415      we only care about the low bits of the result.
6416
6417      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6418      perform a narrower operation than requested since the high-order bits will
6419      be undefined.  On machine where it is defined, this transformation is safe
6420      as long as M1 and M2 have the same number of words.  */
6421
6422   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6423       && !OBJECT_P (SUBREG_REG (src))
6424       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6425            / UNITS_PER_WORD)
6426           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6427                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6428 #ifndef WORD_REGISTER_OPERATIONS
6429       && (GET_MODE_SIZE (GET_MODE (src))
6430         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6431 #endif
6432 #ifdef CANNOT_CHANGE_MODE_CLASS
6433       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6434             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6435                                          GET_MODE (SUBREG_REG (src)),
6436                                          GET_MODE (src)))
6437 #endif
6438       && (REG_P (dest)
6439           || (GET_CODE (dest) == SUBREG
6440               && REG_P (SUBREG_REG (dest)))))
6441     {
6442       SUBST (SET_DEST (x),
6443              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6444                                       dest));
6445       SUBST (SET_SRC (x), SUBREG_REG (src));
6446
6447       src = SET_SRC (x), dest = SET_DEST (x);
6448     }
6449
6450 #ifdef HAVE_cc0
6451   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6452      in SRC.  */
6453   if (dest == cc0_rtx
6454       && GET_CODE (src) == SUBREG
6455       && subreg_lowpart_p (src)
6456       && (GET_MODE_PRECISION (GET_MODE (src))
6457           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6458     {
6459       rtx inner = SUBREG_REG (src);
6460       enum machine_mode inner_mode = GET_MODE (inner);
6461
6462       /* Here we make sure that we don't have a sign bit on.  */
6463       if (val_signbit_known_clear_p (GET_MODE (src),
6464                                      nonzero_bits (inner, inner_mode)))
6465         {
6466           SUBST (SET_SRC (x), inner);
6467           src = SET_SRC (x);
6468         }
6469     }
6470 #endif
6471
6472 #ifdef LOAD_EXTEND_OP
6473   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6474      would require a paradoxical subreg.  Replace the subreg with a
6475      zero_extend to avoid the reload that would otherwise be required.  */
6476
6477   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6478       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6479       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6480       && SUBREG_BYTE (src) == 0
6481       && paradoxical_subreg_p (src)
6482       && MEM_P (SUBREG_REG (src)))
6483     {
6484       SUBST (SET_SRC (x),
6485              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6486                             GET_MODE (src), SUBREG_REG (src)));
6487
6488       src = SET_SRC (x);
6489     }
6490 #endif
6491
6492   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6493      are comparing an item known to be 0 or -1 against 0, use a logical
6494      operation instead. Check for one of the arms being an IOR of the other
6495      arm with some value.  We compute three terms to be IOR'ed together.  In
6496      practice, at most two will be nonzero.  Then we do the IOR's.  */
6497
6498   if (GET_CODE (dest) != PC
6499       && GET_CODE (src) == IF_THEN_ELSE
6500       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6501       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6502       && XEXP (XEXP (src, 0), 1) == const0_rtx
6503       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6504 #ifdef HAVE_conditional_move
6505       && ! can_conditionally_move_p (GET_MODE (src))
6506 #endif
6507       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6508                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6509           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6510       && ! side_effects_p (src))
6511     {
6512       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6513                       ? XEXP (src, 1) : XEXP (src, 2));
6514       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6515                    ? XEXP (src, 2) : XEXP (src, 1));
6516       rtx term1 = const0_rtx, term2, term3;
6517
6518       if (GET_CODE (true_rtx) == IOR
6519           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6520         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6521       else if (GET_CODE (true_rtx) == IOR
6522                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6523         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6524       else if (GET_CODE (false_rtx) == IOR
6525                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6526         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6527       else if (GET_CODE (false_rtx) == IOR
6528                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6529         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6530
6531       term2 = simplify_gen_binary (AND, GET_MODE (src),
6532                                    XEXP (XEXP (src, 0), 0), true_rtx);
6533       term3 = simplify_gen_binary (AND, GET_MODE (src),
6534                                    simplify_gen_unary (NOT, GET_MODE (src),
6535                                                        XEXP (XEXP (src, 0), 0),
6536                                                        GET_MODE (src)),
6537                                    false_rtx);
6538
6539       SUBST (SET_SRC (x),
6540              simplify_gen_binary (IOR, GET_MODE (src),
6541                                   simplify_gen_binary (IOR, GET_MODE (src),
6542                                                        term1, term2),
6543                                   term3));
6544
6545       src = SET_SRC (x);
6546     }
6547
6548   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6549      whole thing fail.  */
6550   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6551     return src;
6552   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6553     return dest;
6554   else
6555     /* Convert this into a field assignment operation, if possible.  */
6556     return make_field_assignment (x);
6557 }
6558 \f
6559 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6560    result.  */
6561
6562 static rtx
6563 simplify_logical (rtx x)
6564 {
6565   enum machine_mode mode = GET_MODE (x);
6566   rtx op0 = XEXP (x, 0);
6567   rtx op1 = XEXP (x, 1);
6568
6569   switch (GET_CODE (x))
6570     {
6571     case AND:
6572       /* We can call simplify_and_const_int only if we don't lose
6573          any (sign) bits when converting INTVAL (op1) to
6574          "unsigned HOST_WIDE_INT".  */
6575       if (CONST_INT_P (op1)
6576           && (HWI_COMPUTABLE_MODE_P (mode)
6577               || INTVAL (op1) > 0))
6578         {
6579           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6580           if (GET_CODE (x) != AND)
6581             return x;
6582
6583           op0 = XEXP (x, 0);
6584           op1 = XEXP (x, 1);
6585         }
6586
6587       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6588          apply the distributive law and then the inverse distributive
6589          law to see if things simplify.  */
6590       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6591         {
6592           rtx result = distribute_and_simplify_rtx (x, 0);
6593           if (result)
6594             return result;
6595         }
6596       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6597         {
6598           rtx result = distribute_and_simplify_rtx (x, 1);
6599           if (result)
6600             return result;
6601         }
6602       break;
6603
6604     case IOR:
6605       /* If we have (ior (and A B) C), apply the distributive law and then
6606          the inverse distributive law to see if things simplify.  */
6607
6608       if (GET_CODE (op0) == AND)
6609         {
6610           rtx result = distribute_and_simplify_rtx (x, 0);
6611           if (result)
6612             return result;
6613         }
6614
6615       if (GET_CODE (op1) == AND)
6616         {
6617           rtx result = distribute_and_simplify_rtx (x, 1);
6618           if (result)
6619             return result;
6620         }
6621       break;
6622
6623     default:
6624       gcc_unreachable ();
6625     }
6626
6627   return x;
6628 }
6629 \f
6630 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6631    operations" because they can be replaced with two more basic operations.
6632    ZERO_EXTEND is also considered "compound" because it can be replaced with
6633    an AND operation, which is simpler, though only one operation.
6634
6635    The function expand_compound_operation is called with an rtx expression
6636    and will convert it to the appropriate shifts and AND operations,
6637    simplifying at each stage.
6638
6639    The function make_compound_operation is called to convert an expression
6640    consisting of shifts and ANDs into the equivalent compound expression.
6641    It is the inverse of this function, loosely speaking.  */
6642
6643 static rtx
6644 expand_compound_operation (rtx x)
6645 {
6646   unsigned HOST_WIDE_INT pos = 0, len;
6647   int unsignedp = 0;
6648   unsigned int modewidth;
6649   rtx tem;
6650
6651   switch (GET_CODE (x))
6652     {
6653     case ZERO_EXTEND:
6654       unsignedp = 1;
6655     case SIGN_EXTEND:
6656       /* We can't necessarily use a const_int for a multiword mode;
6657          it depends on implicitly extending the value.
6658          Since we don't know the right way to extend it,
6659          we can't tell whether the implicit way is right.
6660
6661          Even for a mode that is no wider than a const_int,
6662          we can't win, because we need to sign extend one of its bits through
6663          the rest of it, and we don't know which bit.  */
6664       if (CONST_INT_P (XEXP (x, 0)))
6665         return x;
6666
6667       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6668          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6669          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6670          reloaded. If not for that, MEM's would very rarely be safe.
6671
6672          Reject MODEs bigger than a word, because we might not be able
6673          to reference a two-register group starting with an arbitrary register
6674          (and currently gen_lowpart might crash for a SUBREG).  */
6675
6676       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6677         return x;
6678
6679       /* Reject MODEs that aren't scalar integers because turning vector
6680          or complex modes into shifts causes problems.  */
6681
6682       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6683         return x;
6684
6685       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6686       /* If the inner object has VOIDmode (the only way this can happen
6687          is if it is an ASM_OPERANDS), we can't do anything since we don't
6688          know how much masking to do.  */
6689       if (len == 0)
6690         return x;
6691
6692       break;
6693
6694     case ZERO_EXTRACT:
6695       unsignedp = 1;
6696
6697       /* ... fall through ...  */
6698
6699     case SIGN_EXTRACT:
6700       /* If the operand is a CLOBBER, just return it.  */
6701       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6702         return XEXP (x, 0);
6703
6704       if (!CONST_INT_P (XEXP (x, 1))
6705           || !CONST_INT_P (XEXP (x, 2))
6706           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6707         return x;
6708
6709       /* Reject MODEs that aren't scalar integers because turning vector
6710          or complex modes into shifts causes problems.  */
6711
6712       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6713         return x;
6714
6715       len = INTVAL (XEXP (x, 1));
6716       pos = INTVAL (XEXP (x, 2));
6717
6718       /* This should stay within the object being extracted, fail otherwise.  */
6719       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6720         return x;
6721
6722       if (BITS_BIG_ENDIAN)
6723         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6724
6725       break;
6726
6727     default:
6728       return x;
6729     }
6730   /* Convert sign extension to zero extension, if we know that the high
6731      bit is not set, as this is easier to optimize.  It will be converted
6732      back to cheaper alternative in make_extraction.  */
6733   if (GET_CODE (x) == SIGN_EXTEND
6734       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6735           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6736                 & ~(((unsigned HOST_WIDE_INT)
6737                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6738                      >> 1))
6739                == 0)))
6740     {
6741       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6742       rtx temp2 = expand_compound_operation (temp);
6743
6744       /* Make sure this is a profitable operation.  */
6745       if (set_src_cost (x, optimize_this_for_speed_p)
6746           > set_src_cost (temp2, optimize_this_for_speed_p))
6747        return temp2;
6748       else if (set_src_cost (x, optimize_this_for_speed_p)
6749                > set_src_cost (temp, optimize_this_for_speed_p))
6750        return temp;
6751       else
6752        return x;
6753     }
6754
6755   /* We can optimize some special cases of ZERO_EXTEND.  */
6756   if (GET_CODE (x) == ZERO_EXTEND)
6757     {
6758       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6759          know that the last value didn't have any inappropriate bits
6760          set.  */
6761       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6762           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6763           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6764           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6765               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6766         return XEXP (XEXP (x, 0), 0);
6767
6768       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6769       if (GET_CODE (XEXP (x, 0)) == SUBREG
6770           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6771           && subreg_lowpart_p (XEXP (x, 0))
6772           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6773           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6774               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6775         return SUBREG_REG (XEXP (x, 0));
6776
6777       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6778          is a comparison and STORE_FLAG_VALUE permits.  This is like
6779          the first case, but it works even when GET_MODE (x) is larger
6780          than HOST_WIDE_INT.  */
6781       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6782           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6783           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6784           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6785               <= HOST_BITS_PER_WIDE_INT)
6786           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6787         return XEXP (XEXP (x, 0), 0);
6788
6789       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6790       if (GET_CODE (XEXP (x, 0)) == SUBREG
6791           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6792           && subreg_lowpart_p (XEXP (x, 0))
6793           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6794           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6795               <= HOST_BITS_PER_WIDE_INT)
6796           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6797         return SUBREG_REG (XEXP (x, 0));
6798
6799     }
6800
6801   /* If we reach here, we want to return a pair of shifts.  The inner
6802      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6803      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6804      logical depending on the value of UNSIGNEDP.
6805
6806      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6807      converted into an AND of a shift.
6808
6809      We must check for the case where the left shift would have a negative
6810      count.  This can happen in a case like (x >> 31) & 255 on machines
6811      that can't shift by a constant.  On those machines, we would first
6812      combine the shift with the AND to produce a variable-position
6813      extraction.  Then the constant of 31 would be substituted in
6814      to produce such a position.  */
6815
6816   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6817   if (modewidth >= pos + len)
6818     {
6819       enum machine_mode mode = GET_MODE (x);
6820       tem = gen_lowpart (mode, XEXP (x, 0));
6821       if (!tem || GET_CODE (tem) == CLOBBER)
6822         return x;
6823       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6824                                   tem, modewidth - pos - len);
6825       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6826                                   mode, tem, modewidth - len);
6827     }
6828   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6829     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6830                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6831                                                         GET_MODE (x),
6832                                                         XEXP (x, 0), pos),
6833                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6834   else
6835     /* Any other cases we can't handle.  */
6836     return x;
6837
6838   /* If we couldn't do this for some reason, return the original
6839      expression.  */
6840   if (GET_CODE (tem) == CLOBBER)
6841     return x;
6842
6843   return tem;
6844 }
6845 \f
6846 /* X is a SET which contains an assignment of one object into
6847    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6848    or certain SUBREGS). If possible, convert it into a series of
6849    logical operations.
6850
6851    We half-heartedly support variable positions, but do not at all
6852    support variable lengths.  */
6853
6854 static const_rtx
6855 expand_field_assignment (const_rtx x)
6856 {
6857   rtx inner;
6858   rtx pos;                      /* Always counts from low bit.  */
6859   int len;
6860   rtx mask, cleared, masked;
6861   enum machine_mode compute_mode;
6862
6863   /* Loop until we find something we can't simplify.  */
6864   while (1)
6865     {
6866       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6867           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6868         {
6869           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6870           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6871           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6872         }
6873       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6874                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6875         {
6876           inner = XEXP (SET_DEST (x), 0);
6877           len = INTVAL (XEXP (SET_DEST (x), 1));
6878           pos = XEXP (SET_DEST (x), 2);
6879
6880           /* A constant position should stay within the width of INNER.  */
6881           if (CONST_INT_P (pos)
6882               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6883             break;
6884
6885           if (BITS_BIG_ENDIAN)
6886             {
6887               if (CONST_INT_P (pos))
6888                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6889                                - INTVAL (pos));
6890               else if (GET_CODE (pos) == MINUS
6891                        && CONST_INT_P (XEXP (pos, 1))
6892                        && (INTVAL (XEXP (pos, 1))
6893                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6894                 /* If position is ADJUST - X, new position is X.  */
6895                 pos = XEXP (pos, 0);
6896               else
6897                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6898                                            GEN_INT (GET_MODE_PRECISION (
6899                                                     GET_MODE (inner))
6900                                                     - len),
6901                                            pos);
6902             }
6903         }
6904
6905       /* A SUBREG between two modes that occupy the same numbers of words
6906          can be done by moving the SUBREG to the source.  */
6907       else if (GET_CODE (SET_DEST (x)) == SUBREG
6908                /* We need SUBREGs to compute nonzero_bits properly.  */
6909                && nonzero_sign_valid
6910                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6911                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6912                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6913                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6914         {
6915           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6916                            gen_lowpart
6917                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6918                             SET_SRC (x)));
6919           continue;
6920         }
6921       else
6922         break;
6923
6924       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6925         inner = SUBREG_REG (inner);
6926
6927       compute_mode = GET_MODE (inner);
6928
6929       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6930       if (! SCALAR_INT_MODE_P (compute_mode))
6931         {
6932           enum machine_mode imode;
6933
6934           /* Don't do anything for vector or complex integral types.  */
6935           if (! FLOAT_MODE_P (compute_mode))
6936             break;
6937
6938           /* Try to find an integral mode to pun with.  */
6939           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6940           if (imode == BLKmode)
6941             break;
6942
6943           compute_mode = imode;
6944           inner = gen_lowpart (imode, inner);
6945         }
6946
6947       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6948       if (len >= HOST_BITS_PER_WIDE_INT)
6949         break;
6950
6951       /* Now compute the equivalent expression.  Make a copy of INNER
6952          for the SET_DEST in case it is a MEM into which we will substitute;
6953          we don't want shared RTL in that case.  */
6954       mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6955       cleared = simplify_gen_binary (AND, compute_mode,
6956                                      simplify_gen_unary (NOT, compute_mode,
6957                                        simplify_gen_binary (ASHIFT,
6958                                                             compute_mode,
6959                                                             mask, pos),
6960                                        compute_mode),
6961                                      inner);
6962       masked = simplify_gen_binary (ASHIFT, compute_mode,
6963                                     simplify_gen_binary (
6964                                       AND, compute_mode,
6965                                       gen_lowpart (compute_mode, SET_SRC (x)),
6966                                       mask),
6967                                     pos);
6968
6969       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6970                        simplify_gen_binary (IOR, compute_mode,
6971                                             cleared, masked));
6972     }
6973
6974   return x;
6975 }
6976 \f
6977 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6978    it is an RTX that represents the (variable) starting position; otherwise,
6979    POS is the (constant) starting bit position.  Both are counted from the LSB.
6980
6981    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6982
6983    IN_DEST is nonzero if this is a reference in the destination of a SET.
6984    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6985    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6986    be used.
6987
6988    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6989    ZERO_EXTRACT should be built even for bits starting at bit 0.
6990
6991    MODE is the desired mode of the result (if IN_DEST == 0).
6992
6993    The result is an RTX for the extraction or NULL_RTX if the target
6994    can't handle it.  */
6995
6996 static rtx
6997 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6998                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6999                  int in_dest, int in_compare)
7000 {
7001   /* This mode describes the size of the storage area
7002      to fetch the overall value from.  Within that, we
7003      ignore the POS lowest bits, etc.  */
7004   enum machine_mode is_mode = GET_MODE (inner);
7005   enum machine_mode inner_mode;
7006   enum machine_mode wanted_inner_mode;
7007   enum machine_mode wanted_inner_reg_mode = word_mode;
7008   enum machine_mode pos_mode = word_mode;
7009   enum machine_mode extraction_mode = word_mode;
7010   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7011   rtx new_rtx = 0;
7012   rtx orig_pos_rtx = pos_rtx;
7013   HOST_WIDE_INT orig_pos;
7014
7015   if (pos_rtx && CONST_INT_P (pos_rtx))
7016     pos = INTVAL (pos_rtx), pos_rtx = 0;
7017
7018   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7019     {
7020       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7021          consider just the QI as the memory to extract from.
7022          The subreg adds or removes high bits; its mode is
7023          irrelevant to the meaning of this extraction,
7024          since POS and LEN count from the lsb.  */
7025       if (MEM_P (SUBREG_REG (inner)))
7026         is_mode = GET_MODE (SUBREG_REG (inner));
7027       inner = SUBREG_REG (inner);
7028     }
7029   else if (GET_CODE (inner) == ASHIFT
7030            && CONST_INT_P (XEXP (inner, 1))
7031            && pos_rtx == 0 && pos == 0
7032            && len > UINTVAL (XEXP (inner, 1)))
7033     {
7034       /* We're extracting the least significant bits of an rtx
7035          (ashift X (const_int C)), where LEN > C.  Extract the
7036          least significant (LEN - C) bits of X, giving an rtx
7037          whose mode is MODE, then shift it left C times.  */
7038       new_rtx = make_extraction (mode, XEXP (inner, 0),
7039                              0, 0, len - INTVAL (XEXP (inner, 1)),
7040                              unsignedp, in_dest, in_compare);
7041       if (new_rtx != 0)
7042         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7043     }
7044   else if (GET_CODE (inner) == TRUNCATE)
7045     inner = XEXP (inner, 0);
7046
7047   inner_mode = GET_MODE (inner);
7048
7049   /* See if this can be done without an extraction.  We never can if the
7050      width of the field is not the same as that of some integer mode. For
7051      registers, we can only avoid the extraction if the position is at the
7052      low-order bit and this is either not in the destination or we have the
7053      appropriate STRICT_LOW_PART operation available.
7054
7055      For MEM, we can avoid an extract if the field starts on an appropriate
7056      boundary and we can change the mode of the memory reference.  */
7057
7058   if (tmode != BLKmode
7059       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7060            && !MEM_P (inner)
7061            && (inner_mode == tmode
7062                || !REG_P (inner)
7063                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7064                || reg_truncated_to_mode (tmode, inner))
7065            && (! in_dest
7066                || (REG_P (inner)
7067                    && have_insn_for (STRICT_LOW_PART, tmode))))
7068           || (MEM_P (inner) && pos_rtx == 0
7069               && (pos
7070                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7071                      : BITS_PER_UNIT)) == 0
7072               /* We can't do this if we are widening INNER_MODE (it
7073                  may not be aligned, for one thing).  */
7074               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7075               && (inner_mode == tmode
7076                   || (! mode_dependent_address_p (XEXP (inner, 0),
7077                                                   MEM_ADDR_SPACE (inner))
7078                       && ! MEM_VOLATILE_P (inner))))))
7079     {
7080       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7081          field.  If the original and current mode are the same, we need not
7082          adjust the offset.  Otherwise, we do if bytes big endian.
7083
7084          If INNER is not a MEM, get a piece consisting of just the field
7085          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7086
7087       if (MEM_P (inner))
7088         {
7089           HOST_WIDE_INT offset;
7090
7091           /* POS counts from lsb, but make OFFSET count in memory order.  */
7092           if (BYTES_BIG_ENDIAN)
7093             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7094           else
7095             offset = pos / BITS_PER_UNIT;
7096
7097           new_rtx = adjust_address_nv (inner, tmode, offset);
7098         }
7099       else if (REG_P (inner))
7100         {
7101           if (tmode != inner_mode)
7102             {
7103               /* We can't call gen_lowpart in a DEST since we
7104                  always want a SUBREG (see below) and it would sometimes
7105                  return a new hard register.  */
7106               if (pos || in_dest)
7107                 {
7108                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7109
7110                   if (WORDS_BIG_ENDIAN
7111                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7112                     final_word = ((GET_MODE_SIZE (inner_mode)
7113                                    - GET_MODE_SIZE (tmode))
7114                                   / UNITS_PER_WORD) - final_word;
7115
7116                   final_word *= UNITS_PER_WORD;
7117                   if (BYTES_BIG_ENDIAN &&
7118                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7119                     final_word += (GET_MODE_SIZE (inner_mode)
7120                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7121
7122                   /* Avoid creating invalid subregs, for example when
7123                      simplifying (x>>32)&255.  */
7124                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7125                     return NULL_RTX;
7126
7127                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7128                 }
7129               else
7130                 new_rtx = gen_lowpart (tmode, inner);
7131             }
7132           else
7133             new_rtx = inner;
7134         }
7135       else
7136         new_rtx = force_to_mode (inner, tmode,
7137                              len >= HOST_BITS_PER_WIDE_INT
7138                              ? ~(unsigned HOST_WIDE_INT) 0
7139                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7140                              0);
7141
7142       /* If this extraction is going into the destination of a SET,
7143          make a STRICT_LOW_PART unless we made a MEM.  */
7144
7145       if (in_dest)
7146         return (MEM_P (new_rtx) ? new_rtx
7147                 : (GET_CODE (new_rtx) != SUBREG
7148                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7149                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7150
7151       if (mode == tmode)
7152         return new_rtx;
7153
7154       if (CONST_SCALAR_INT_P (new_rtx))
7155         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7156                                          mode, new_rtx, tmode);
7157
7158       /* If we know that no extraneous bits are set, and that the high
7159          bit is not set, convert the extraction to the cheaper of
7160          sign and zero extension, that are equivalent in these cases.  */
7161       if (flag_expensive_optimizations
7162           && (HWI_COMPUTABLE_MODE_P (tmode)
7163               && ((nonzero_bits (new_rtx, tmode)
7164                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7165                   == 0)))
7166         {
7167           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7168           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7169
7170           /* Prefer ZERO_EXTENSION, since it gives more information to
7171              backends.  */
7172           if (set_src_cost (temp, optimize_this_for_speed_p)
7173               <= set_src_cost (temp1, optimize_this_for_speed_p))
7174             return temp;
7175           return temp1;
7176         }
7177
7178       /* Otherwise, sign- or zero-extend unless we already are in the
7179          proper mode.  */
7180
7181       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7182                              mode, new_rtx));
7183     }
7184
7185   /* Unless this is a COMPARE or we have a funny memory reference,
7186      don't do anything with zero-extending field extracts starting at
7187      the low-order bit since they are simple AND operations.  */
7188   if (pos_rtx == 0 && pos == 0 && ! in_dest
7189       && ! in_compare && unsignedp)
7190     return 0;
7191
7192   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7193      if the position is not a constant and the length is not 1.  In all
7194      other cases, we would only be going outside our object in cases when
7195      an original shift would have been undefined.  */
7196   if (MEM_P (inner)
7197       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7198           || (pos_rtx != 0 && len != 1)))
7199     return 0;
7200
7201   enum extraction_pattern pattern = (in_dest ? EP_insv
7202                                      : unsignedp ? EP_extzv : EP_extv);
7203
7204   /* If INNER is not from memory, we want it to have the mode of a register
7205      extraction pattern's structure operand, or word_mode if there is no
7206      such pattern.  The same applies to extraction_mode and pos_mode
7207      and their respective operands.
7208
7209      For memory, assume that the desired extraction_mode and pos_mode
7210      are the same as for a register operation, since at present we don't
7211      have named patterns for aligned memory structures.  */
7212   struct extraction_insn insn;
7213   if (get_best_reg_extraction_insn (&insn, pattern,
7214                                     GET_MODE_BITSIZE (inner_mode), mode))
7215     {
7216       wanted_inner_reg_mode = insn.struct_mode;
7217       pos_mode = insn.pos_mode;
7218       extraction_mode = insn.field_mode;
7219     }
7220
7221   /* Never narrow an object, since that might not be safe.  */
7222
7223   if (mode != VOIDmode
7224       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7225     extraction_mode = mode;
7226
7227   if (!MEM_P (inner))
7228     wanted_inner_mode = wanted_inner_reg_mode;
7229   else
7230     {
7231       /* Be careful not to go beyond the extracted object and maintain the
7232          natural alignment of the memory.  */
7233       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7234       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7235              > GET_MODE_BITSIZE (wanted_inner_mode))
7236         {
7237           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7238           gcc_assert (wanted_inner_mode != VOIDmode);
7239         }
7240     }
7241
7242   orig_pos = pos;
7243
7244   if (BITS_BIG_ENDIAN)
7245     {
7246       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7247          BITS_BIG_ENDIAN style.  If position is constant, compute new
7248          position.  Otherwise, build subtraction.
7249          Note that POS is relative to the mode of the original argument.
7250          If it's a MEM we need to recompute POS relative to that.
7251          However, if we're extracting from (or inserting into) a register,
7252          we want to recompute POS relative to wanted_inner_mode.  */
7253       int width = (MEM_P (inner)
7254                    ? GET_MODE_BITSIZE (is_mode)
7255                    : GET_MODE_BITSIZE (wanted_inner_mode));
7256
7257       if (pos_rtx == 0)
7258         pos = width - len - pos;
7259       else
7260         pos_rtx
7261           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7262       /* POS may be less than 0 now, but we check for that below.
7263          Note that it can only be less than 0 if !MEM_P (inner).  */
7264     }
7265
7266   /* If INNER has a wider mode, and this is a constant extraction, try to
7267      make it smaller and adjust the byte to point to the byte containing
7268      the value.  */
7269   if (wanted_inner_mode != VOIDmode
7270       && inner_mode != wanted_inner_mode
7271       && ! pos_rtx
7272       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7273       && MEM_P (inner)
7274       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7275       && ! MEM_VOLATILE_P (inner))
7276     {
7277       int offset = 0;
7278
7279       /* The computations below will be correct if the machine is big
7280          endian in both bits and bytes or little endian in bits and bytes.
7281          If it is mixed, we must adjust.  */
7282
7283       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7284          adjust OFFSET to compensate.  */
7285       if (BYTES_BIG_ENDIAN
7286           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7287         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7288
7289       /* We can now move to the desired byte.  */
7290       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7291                 * GET_MODE_SIZE (wanted_inner_mode);
7292       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7293
7294       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7295           && is_mode != wanted_inner_mode)
7296         offset = (GET_MODE_SIZE (is_mode)
7297                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7298
7299       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7300     }
7301
7302   /* If INNER is not memory, get it into the proper mode.  If we are changing
7303      its mode, POS must be a constant and smaller than the size of the new
7304      mode.  */
7305   else if (!MEM_P (inner))
7306     {
7307       /* On the LHS, don't create paradoxical subregs implicitely truncating
7308          the register unless TRULY_NOOP_TRUNCATION.  */
7309       if (in_dest
7310           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7311                                              wanted_inner_mode))
7312         return NULL_RTX;
7313
7314       if (GET_MODE (inner) != wanted_inner_mode
7315           && (pos_rtx != 0
7316               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7317         return NULL_RTX;
7318
7319       if (orig_pos < 0)
7320         return NULL_RTX;
7321
7322       inner = force_to_mode (inner, wanted_inner_mode,
7323                              pos_rtx
7324                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7325                              ? ~(unsigned HOST_WIDE_INT) 0
7326                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7327                                 << orig_pos),
7328                              0);
7329     }
7330
7331   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7332      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7333   if (pos_rtx != 0
7334       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7335     {
7336       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7337                                      GET_MODE (pos_rtx));
7338
7339       /* If we know that no extraneous bits are set, and that the high
7340          bit is not set, convert extraction to cheaper one - either
7341          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7342          cases.  */
7343       if (flag_expensive_optimizations
7344           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7345               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7346                    & ~(((unsigned HOST_WIDE_INT)
7347                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7348                        >> 1))
7349                   == 0)))
7350         {
7351           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7352                                           GET_MODE (pos_rtx));
7353
7354           /* Prefer ZERO_EXTENSION, since it gives more information to
7355              backends.  */
7356           if (set_src_cost (temp1, optimize_this_for_speed_p)
7357               < set_src_cost (temp, optimize_this_for_speed_p))
7358             temp = temp1;
7359         }
7360       pos_rtx = temp;
7361     }
7362
7363   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7364      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7365      be a CONST_INT.  */
7366   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7367     pos_rtx = orig_pos_rtx;
7368
7369   else if (pos_rtx == 0)
7370     pos_rtx = GEN_INT (pos);
7371
7372   /* Make the required operation.  See if we can use existing rtx.  */
7373   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7374                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7375   if (! in_dest)
7376     new_rtx = gen_lowpart (mode, new_rtx);
7377
7378   return new_rtx;
7379 }
7380 \f
7381 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7382    with any other operations in X.  Return X without that shift if so.  */
7383
7384 static rtx
7385 extract_left_shift (rtx x, int count)
7386 {
7387   enum rtx_code code = GET_CODE (x);
7388   enum machine_mode mode = GET_MODE (x);
7389   rtx tem;
7390
7391   switch (code)
7392     {
7393     case ASHIFT:
7394       /* This is the shift itself.  If it is wide enough, we will return
7395          either the value being shifted if the shift count is equal to
7396          COUNT or a shift for the difference.  */
7397       if (CONST_INT_P (XEXP (x, 1))
7398           && INTVAL (XEXP (x, 1)) >= count)
7399         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7400                                      INTVAL (XEXP (x, 1)) - count);
7401       break;
7402
7403     case NEG:  case NOT:
7404       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7405         return simplify_gen_unary (code, mode, tem, mode);
7406
7407       break;
7408
7409     case PLUS:  case IOR:  case XOR:  case AND:
7410       /* If we can safely shift this constant and we find the inner shift,
7411          make a new operation.  */
7412       if (CONST_INT_P (XEXP (x, 1))
7413           && (UINTVAL (XEXP (x, 1))
7414               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7415           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7416         return simplify_gen_binary (code, mode, tem,
7417                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7418
7419       break;
7420
7421     default:
7422       break;
7423     }
7424
7425   return 0;
7426 }
7427 \f
7428 /* Look at the expression rooted at X.  Look for expressions
7429    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7430    Form these expressions.
7431
7432    Return the new rtx, usually just X.
7433
7434    Also, for machines like the VAX that don't have logical shift insns,
7435    try to convert logical to arithmetic shift operations in cases where
7436    they are equivalent.  This undoes the canonicalizations to logical
7437    shifts done elsewhere.
7438
7439    We try, as much as possible, to re-use rtl expressions to save memory.
7440
7441    IN_CODE says what kind of expression we are processing.  Normally, it is
7442    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7443    being kludges), it is MEM.  When processing the arguments of a comparison
7444    or a COMPARE against zero, it is COMPARE.  */
7445
7446 rtx
7447 make_compound_operation (rtx x, enum rtx_code in_code)
7448 {
7449   enum rtx_code code = GET_CODE (x);
7450   enum machine_mode mode = GET_MODE (x);
7451   int mode_width = GET_MODE_PRECISION (mode);
7452   rtx rhs, lhs;
7453   enum rtx_code next_code;
7454   int i, j;
7455   rtx new_rtx = 0;
7456   rtx tem;
7457   const char *fmt;
7458
7459   /* Select the code to be used in recursive calls.  Once we are inside an
7460      address, we stay there.  If we have a comparison, set to COMPARE,
7461      but once inside, go back to our default of SET.  */
7462
7463   next_code = (code == MEM ? MEM
7464                : ((code == PLUS || code == MINUS)
7465                   && SCALAR_INT_MODE_P (mode)) ? MEM
7466                : ((code == COMPARE || COMPARISON_P (x))
7467                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7468                : in_code == COMPARE ? SET : in_code);
7469
7470   /* Process depending on the code of this operation.  If NEW is set
7471      nonzero, it will be returned.  */
7472
7473   switch (code)
7474     {
7475     case ASHIFT:
7476       /* Convert shifts by constants into multiplications if inside
7477          an address.  */
7478       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7479           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7480           && INTVAL (XEXP (x, 1)) >= 0
7481           && SCALAR_INT_MODE_P (mode))
7482         {
7483           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7484           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7485
7486           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7487           if (GET_CODE (new_rtx) == NEG)
7488             {
7489               new_rtx = XEXP (new_rtx, 0);
7490               multval = -multval;
7491             }
7492           multval = trunc_int_for_mode (multval, mode);
7493           new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7494         }
7495       break;
7496
7497     case PLUS:
7498       lhs = XEXP (x, 0);
7499       rhs = XEXP (x, 1);
7500       lhs = make_compound_operation (lhs, next_code);
7501       rhs = make_compound_operation (rhs, next_code);
7502       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7503           && SCALAR_INT_MODE_P (mode))
7504         {
7505           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7506                                      XEXP (lhs, 1));
7507           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7508         }
7509       else if (GET_CODE (lhs) == MULT
7510                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7511         {
7512           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7513                                      simplify_gen_unary (NEG, mode,
7514                                                          XEXP (lhs, 1),
7515                                                          mode));
7516           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7517         }
7518       else
7519         {
7520           SUBST (XEXP (x, 0), lhs);
7521           SUBST (XEXP (x, 1), rhs);
7522           goto maybe_swap;
7523         }
7524       x = gen_lowpart (mode, new_rtx);
7525       goto maybe_swap;
7526
7527     case MINUS:
7528       lhs = XEXP (x, 0);
7529       rhs = XEXP (x, 1);
7530       lhs = make_compound_operation (lhs, next_code);
7531       rhs = make_compound_operation (rhs, next_code);
7532       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7533           && SCALAR_INT_MODE_P (mode))
7534         {
7535           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7536                                      XEXP (rhs, 1));
7537           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7538         }
7539       else if (GET_CODE (rhs) == MULT
7540                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7541         {
7542           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7543                                      simplify_gen_unary (NEG, mode,
7544                                                          XEXP (rhs, 1),
7545                                                          mode));
7546           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7547         }
7548       else
7549         {
7550           SUBST (XEXP (x, 0), lhs);
7551           SUBST (XEXP (x, 1), rhs);
7552           return x;
7553         }
7554       return gen_lowpart (mode, new_rtx);
7555
7556     case AND:
7557       /* If the second operand is not a constant, we can't do anything
7558          with it.  */
7559       if (!CONST_INT_P (XEXP (x, 1)))
7560         break;
7561
7562       /* If the constant is a power of two minus one and the first operand
7563          is a logical right shift, make an extraction.  */
7564       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7565           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7566         {
7567           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7568           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7569                                  0, in_code == COMPARE);
7570         }
7571
7572       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7573       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7574                && subreg_lowpart_p (XEXP (x, 0))
7575                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7576                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7577         {
7578           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7579                                          next_code);
7580           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7581                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7582                                  0, in_code == COMPARE);
7583         }
7584       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7585       else if ((GET_CODE (XEXP (x, 0)) == XOR
7586                 || GET_CODE (XEXP (x, 0)) == IOR)
7587                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7588                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7589                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7590         {
7591           /* Apply the distributive law, and then try to make extractions.  */
7592           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7593                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7594                                              XEXP (x, 1)),
7595                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7596                                              XEXP (x, 1)));
7597           new_rtx = make_compound_operation (new_rtx, in_code);
7598         }
7599
7600       /* If we are have (and (rotate X C) M) and C is larger than the number
7601          of bits in M, this is an extraction.  */
7602
7603       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7604                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7605                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7606                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7607         {
7608           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7609           new_rtx = make_extraction (mode, new_rtx,
7610                                  (GET_MODE_PRECISION (mode)
7611                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7612                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7613         }
7614
7615       /* On machines without logical shifts, if the operand of the AND is
7616          a logical shift and our mask turns off all the propagated sign
7617          bits, we can replace the logical shift with an arithmetic shift.  */
7618       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7619                && !have_insn_for (LSHIFTRT, mode)
7620                && have_insn_for (ASHIFTRT, mode)
7621                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7622                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7623                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7624                && mode_width <= HOST_BITS_PER_WIDE_INT)
7625         {
7626           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7627
7628           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7629           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7630             SUBST (XEXP (x, 0),
7631                    gen_rtx_ASHIFTRT (mode,
7632                                      make_compound_operation
7633                                      (XEXP (XEXP (x, 0), 0), next_code),
7634                                      XEXP (XEXP (x, 0), 1)));
7635         }
7636
7637       /* If the constant is one less than a power of two, this might be
7638          representable by an extraction even if no shift is present.
7639          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7640          we are in a COMPARE.  */
7641       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7642         new_rtx = make_extraction (mode,
7643                                make_compound_operation (XEXP (x, 0),
7644                                                         next_code),
7645                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7646
7647       /* If we are in a comparison and this is an AND with a power of two,
7648          convert this into the appropriate bit extract.  */
7649       else if (in_code == COMPARE
7650                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7651         new_rtx = make_extraction (mode,
7652                                make_compound_operation (XEXP (x, 0),
7653                                                         next_code),
7654                                i, NULL_RTX, 1, 1, 0, 1);
7655
7656       break;
7657
7658     case LSHIFTRT:
7659       /* If the sign bit is known to be zero, replace this with an
7660          arithmetic shift.  */
7661       if (have_insn_for (ASHIFTRT, mode)
7662           && ! have_insn_for (LSHIFTRT, mode)
7663           && mode_width <= HOST_BITS_PER_WIDE_INT
7664           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7665         {
7666           new_rtx = gen_rtx_ASHIFTRT (mode,
7667                                   make_compound_operation (XEXP (x, 0),
7668                                                            next_code),
7669                                   XEXP (x, 1));
7670           break;
7671         }
7672
7673       /* ... fall through ...  */
7674
7675     case ASHIFTRT:
7676       lhs = XEXP (x, 0);
7677       rhs = XEXP (x, 1);
7678
7679       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7680          this is a SIGN_EXTRACT.  */
7681       if (CONST_INT_P (rhs)
7682           && GET_CODE (lhs) == ASHIFT
7683           && CONST_INT_P (XEXP (lhs, 1))
7684           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7685           && INTVAL (XEXP (lhs, 1)) >= 0
7686           && INTVAL (rhs) < mode_width)
7687         {
7688           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7689           new_rtx = make_extraction (mode, new_rtx,
7690                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7691                                  NULL_RTX, mode_width - INTVAL (rhs),
7692                                  code == LSHIFTRT, 0, in_code == COMPARE);
7693           break;
7694         }
7695
7696       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7697          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7698          also do this for some cases of SIGN_EXTRACT, but it doesn't
7699          seem worth the effort; the case checked for occurs on Alpha.  */
7700
7701       if (!OBJECT_P (lhs)
7702           && ! (GET_CODE (lhs) == SUBREG
7703                 && (OBJECT_P (SUBREG_REG (lhs))))
7704           && CONST_INT_P (rhs)
7705           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7706           && INTVAL (rhs) < mode_width
7707           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7708         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7709                                0, NULL_RTX, mode_width - INTVAL (rhs),
7710                                code == LSHIFTRT, 0, in_code == COMPARE);
7711
7712       break;
7713
7714     case SUBREG:
7715       /* Call ourselves recursively on the inner expression.  If we are
7716          narrowing the object and it has a different RTL code from
7717          what it originally did, do this SUBREG as a force_to_mode.  */
7718       {
7719         rtx inner = SUBREG_REG (x), simplified;
7720         enum rtx_code subreg_code = in_code;
7721
7722         /* If in_code is COMPARE, it isn't always safe to pass it through
7723            to the recursive make_compound_operation call.  */
7724         if (subreg_code == COMPARE
7725             && (!subreg_lowpart_p (x)
7726                 || GET_CODE (inner) == SUBREG
7727                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7728                    is (const_int 0), rather than
7729                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7730                 || (GET_CODE (inner) == AND
7731                     && CONST_INT_P (XEXP (inner, 1))
7732                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7733                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7734                        >= GET_MODE_BITSIZE (mode))))
7735           subreg_code = SET;
7736
7737         tem = make_compound_operation (inner, subreg_code);
7738
7739         simplified
7740           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7741         if (simplified)
7742           tem = simplified;
7743
7744         if (GET_CODE (tem) != GET_CODE (inner)
7745             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7746             && subreg_lowpart_p (x))
7747           {
7748             rtx newer
7749               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7750
7751             /* If we have something other than a SUBREG, we might have
7752                done an expansion, so rerun ourselves.  */
7753             if (GET_CODE (newer) != SUBREG)
7754               newer = make_compound_operation (newer, in_code);
7755
7756             /* force_to_mode can expand compounds.  If it just re-expanded the
7757                compound, use gen_lowpart to convert to the desired mode.  */
7758             if (rtx_equal_p (newer, x)
7759                 /* Likewise if it re-expanded the compound only partially.
7760                    This happens for SUBREG of ZERO_EXTRACT if they extract
7761                    the same number of bits.  */
7762                 || (GET_CODE (newer) == SUBREG
7763                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7764                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7765                     && GET_CODE (inner) == AND
7766                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7767               return gen_lowpart (GET_MODE (x), tem);
7768
7769             return newer;
7770           }
7771
7772         if (simplified)
7773           return tem;
7774       }
7775       break;
7776
7777     default:
7778       break;
7779     }
7780
7781   if (new_rtx)
7782     {
7783       x = gen_lowpart (mode, new_rtx);
7784       code = GET_CODE (x);
7785     }
7786
7787   /* Now recursively process each operand of this operation.  We need to
7788      handle ZERO_EXTEND specially so that we don't lose track of the
7789      inner mode.  */
7790   if (GET_CODE (x) == ZERO_EXTEND)
7791     {
7792       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7793       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7794                                             new_rtx, GET_MODE (XEXP (x, 0)));
7795       if (tem)
7796         return tem;
7797       SUBST (XEXP (x, 0), new_rtx);
7798       return x;
7799     }
7800
7801   fmt = GET_RTX_FORMAT (code);
7802   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7803     if (fmt[i] == 'e')
7804       {
7805         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7806         SUBST (XEXP (x, i), new_rtx);
7807       }
7808     else if (fmt[i] == 'E')
7809       for (j = 0; j < XVECLEN (x, i); j++)
7810         {
7811           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7812           SUBST (XVECEXP (x, i, j), new_rtx);
7813         }
7814
7815  maybe_swap:
7816   /* If this is a commutative operation, the changes to the operands
7817      may have made it noncanonical.  */
7818   if (COMMUTATIVE_ARITH_P (x)
7819       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7820     {
7821       tem = XEXP (x, 0);
7822       SUBST (XEXP (x, 0), XEXP (x, 1));
7823       SUBST (XEXP (x, 1), tem);
7824     }
7825
7826   return x;
7827 }
7828 \f
7829 /* Given M see if it is a value that would select a field of bits
7830    within an item, but not the entire word.  Return -1 if not.
7831    Otherwise, return the starting position of the field, where 0 is the
7832    low-order bit.
7833
7834    *PLEN is set to the length of the field.  */
7835
7836 static int
7837 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7838 {
7839   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7840   int pos = m ? ctz_hwi (m) : -1;
7841   int len = 0;
7842
7843   if (pos >= 0)
7844     /* Now shift off the low-order zero bits and see if we have a
7845        power of two minus 1.  */
7846     len = exact_log2 ((m >> pos) + 1);
7847
7848   if (len <= 0)
7849     pos = -1;
7850
7851   *plen = len;
7852   return pos;
7853 }
7854 \f
7855 /* If X refers to a register that equals REG in value, replace these
7856    references with REG.  */
7857 static rtx
7858 canon_reg_for_combine (rtx x, rtx reg)
7859 {
7860   rtx op0, op1, op2;
7861   const char *fmt;
7862   int i;
7863   bool copied;
7864
7865   enum rtx_code code = GET_CODE (x);
7866   switch (GET_RTX_CLASS (code))
7867     {
7868     case RTX_UNARY:
7869       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7870       if (op0 != XEXP (x, 0))
7871         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7872                                    GET_MODE (reg));
7873       break;
7874
7875     case RTX_BIN_ARITH:
7876     case RTX_COMM_ARITH:
7877       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7878       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7879       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7880         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7881       break;
7882
7883     case RTX_COMPARE:
7884     case RTX_COMM_COMPARE:
7885       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7886       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7887       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7888         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7889                                         GET_MODE (op0), op0, op1);
7890       break;
7891
7892     case RTX_TERNARY:
7893     case RTX_BITFIELD_OPS:
7894       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7895       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7896       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7897       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7898         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7899                                      GET_MODE (op0), op0, op1, op2);
7900
7901     case RTX_OBJ:
7902       if (REG_P (x))
7903         {
7904           if (rtx_equal_p (get_last_value (reg), x)
7905               || rtx_equal_p (reg, get_last_value (x)))
7906             return reg;
7907           else
7908             break;
7909         }
7910
7911       /* fall through */
7912
7913     default:
7914       fmt = GET_RTX_FORMAT (code);
7915       copied = false;
7916       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7917         if (fmt[i] == 'e')
7918           {
7919             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7920             if (op != XEXP (x, i))
7921               {
7922                 if (!copied)
7923                   {
7924                     copied = true;
7925                     x = copy_rtx (x);
7926                   }
7927                 XEXP (x, i) = op;
7928               }
7929           }
7930         else if (fmt[i] == 'E')
7931           {
7932             int j;
7933             for (j = 0; j < XVECLEN (x, i); j++)
7934               {
7935                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7936                 if (op != XVECEXP (x, i, j))
7937                   {
7938                     if (!copied)
7939                       {
7940                         copied = true;
7941                         x = copy_rtx (x);
7942                       }
7943                     XVECEXP (x, i, j) = op;
7944                   }
7945               }
7946           }
7947
7948       break;
7949     }
7950
7951   return x;
7952 }
7953
7954 /* Return X converted to MODE.  If the value is already truncated to
7955    MODE we can just return a subreg even though in the general case we
7956    would need an explicit truncation.  */
7957
7958 static rtx
7959 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7960 {
7961   if (!CONST_INT_P (x)
7962       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7963       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7964       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7965     {
7966       /* Bit-cast X into an integer mode.  */
7967       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7968         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7969       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7970                               x, GET_MODE (x));
7971     }
7972
7973   return gen_lowpart (mode, x);
7974 }
7975
7976 /* See if X can be simplified knowing that we will only refer to it in
7977    MODE and will only refer to those bits that are nonzero in MASK.
7978    If other bits are being computed or if masking operations are done
7979    that select a superset of the bits in MASK, they can sometimes be
7980    ignored.
7981
7982    Return a possibly simplified expression, but always convert X to
7983    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7984
7985    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7986    are all off in X.  This is used when X will be complemented, by either
7987    NOT, NEG, or XOR.  */
7988
7989 static rtx
7990 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7991                int just_select)
7992 {
7993   enum rtx_code code = GET_CODE (x);
7994   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7995   enum machine_mode op_mode;
7996   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7997   rtx op0, op1, temp;
7998
7999   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8000      code below will do the wrong thing since the mode of such an
8001      expression is VOIDmode.
8002
8003      Also do nothing if X is a CLOBBER; this can happen if X was
8004      the return value from a call to gen_lowpart.  */
8005   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8006     return x;
8007
8008   /* We want to perform the operation is its present mode unless we know
8009      that the operation is valid in MODE, in which case we do the operation
8010      in MODE.  */
8011   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8012               && have_insn_for (code, mode))
8013              ? mode : GET_MODE (x));
8014
8015   /* It is not valid to do a right-shift in a narrower mode
8016      than the one it came in with.  */
8017   if ((code == LSHIFTRT || code == ASHIFTRT)
8018       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8019     op_mode = GET_MODE (x);
8020
8021   /* Truncate MASK to fit OP_MODE.  */
8022   if (op_mode)
8023     mask &= GET_MODE_MASK (op_mode);
8024
8025   /* When we have an arithmetic operation, or a shift whose count we
8026      do not know, we need to assume that all bits up to the highest-order
8027      bit in MASK will be needed.  This is how we form such a mask.  */
8028   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8029     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8030   else
8031     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8032                    - 1);
8033
8034   /* Determine what bits of X are guaranteed to be (non)zero.  */
8035   nonzero = nonzero_bits (x, mode);
8036
8037   /* If none of the bits in X are needed, return a zero.  */
8038   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8039     x = const0_rtx;
8040
8041   /* If X is a CONST_INT, return a new one.  Do this here since the
8042      test below will fail.  */
8043   if (CONST_INT_P (x))
8044     {
8045       if (SCALAR_INT_MODE_P (mode))
8046         return gen_int_mode (INTVAL (x) & mask, mode);
8047       else
8048         {
8049           x = GEN_INT (INTVAL (x) & mask);
8050           return gen_lowpart_common (mode, x);
8051         }
8052     }
8053
8054   /* If X is narrower than MODE and we want all the bits in X's mode, just
8055      get X in the proper mode.  */
8056   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8057       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8058     return gen_lowpart (mode, x);
8059
8060   /* We can ignore the effect of a SUBREG if it narrows the mode or
8061      if the constant masks to zero all the bits the mode doesn't have.  */
8062   if (GET_CODE (x) == SUBREG
8063       && subreg_lowpart_p (x)
8064       && ((GET_MODE_SIZE (GET_MODE (x))
8065            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8066           || (0 == (mask
8067                     & GET_MODE_MASK (GET_MODE (x))
8068                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8069     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8070
8071   /* The arithmetic simplifications here only work for scalar integer modes.  */
8072   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8073     return gen_lowpart_or_truncate (mode, x);
8074
8075   switch (code)
8076     {
8077     case CLOBBER:
8078       /* If X is a (clobber (const_int)), return it since we know we are
8079          generating something that won't match.  */
8080       return x;
8081
8082     case SIGN_EXTEND:
8083     case ZERO_EXTEND:
8084     case ZERO_EXTRACT:
8085     case SIGN_EXTRACT:
8086       x = expand_compound_operation (x);
8087       if (GET_CODE (x) != code)
8088         return force_to_mode (x, mode, mask, next_select);
8089       break;
8090
8091     case TRUNCATE:
8092       /* Similarly for a truncate.  */
8093       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8094
8095     case AND:
8096       /* If this is an AND with a constant, convert it into an AND
8097          whose constant is the AND of that constant with MASK.  If it
8098          remains an AND of MASK, delete it since it is redundant.  */
8099
8100       if (CONST_INT_P (XEXP (x, 1)))
8101         {
8102           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8103                                       mask & INTVAL (XEXP (x, 1)));
8104
8105           /* If X is still an AND, see if it is an AND with a mask that
8106              is just some low-order bits.  If so, and it is MASK, we don't
8107              need it.  */
8108
8109           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8110               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8111                   == mask))
8112             x = XEXP (x, 0);
8113
8114           /* If it remains an AND, try making another AND with the bits
8115              in the mode mask that aren't in MASK turned on.  If the
8116              constant in the AND is wide enough, this might make a
8117              cheaper constant.  */
8118
8119           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8120               && GET_MODE_MASK (GET_MODE (x)) != mask
8121               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8122             {
8123               unsigned HOST_WIDE_INT cval
8124                 = UINTVAL (XEXP (x, 1))
8125                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8126               int width = GET_MODE_PRECISION (GET_MODE (x));
8127               rtx y;
8128
8129               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8130                  number, sign extend it.  */
8131               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8132                   && (cval & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8133                 cval |= HOST_WIDE_INT_M1U << width;
8134
8135               y = simplify_gen_binary (AND, GET_MODE (x),
8136                                        XEXP (x, 0), GEN_INT (cval));
8137               if (set_src_cost (y, optimize_this_for_speed_p)
8138                   < set_src_cost (x, optimize_this_for_speed_p))
8139                 x = y;
8140             }
8141
8142           break;
8143         }
8144
8145       goto binop;
8146
8147     case PLUS:
8148       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8149          low-order bits (as in an alignment operation) and FOO is already
8150          aligned to that boundary, mask C1 to that boundary as well.
8151          This may eliminate that PLUS and, later, the AND.  */
8152
8153       {
8154         unsigned int width = GET_MODE_PRECISION (mode);
8155         unsigned HOST_WIDE_INT smask = mask;
8156
8157         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8158            number, sign extend it.  */
8159
8160         if (width < HOST_BITS_PER_WIDE_INT
8161             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8162           smask |= HOST_WIDE_INT_M1U << width;
8163
8164         if (CONST_INT_P (XEXP (x, 1))
8165             && exact_log2 (- smask) >= 0
8166             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8167             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8168           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8169                                                (INTVAL (XEXP (x, 1)) & smask)),
8170                                 mode, smask, next_select);
8171       }
8172
8173       /* ... fall through ...  */
8174
8175     case MULT:
8176       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8177          most significant bit in MASK since carries from those bits will
8178          affect the bits we are interested in.  */
8179       mask = fuller_mask;
8180       goto binop;
8181
8182     case MINUS:
8183       /* If X is (minus C Y) where C's least set bit is larger than any bit
8184          in the mask, then we may replace with (neg Y).  */
8185       if (CONST_INT_P (XEXP (x, 0))
8186           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8187                                         & -INTVAL (XEXP (x, 0))))
8188               > mask))
8189         {
8190           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8191                                   GET_MODE (x));
8192           return force_to_mode (x, mode, mask, next_select);
8193         }
8194
8195       /* Similarly, if C contains every bit in the fuller_mask, then we may
8196          replace with (not Y).  */
8197       if (CONST_INT_P (XEXP (x, 0))
8198           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8199         {
8200           x = simplify_gen_unary (NOT, GET_MODE (x),
8201                                   XEXP (x, 1), GET_MODE (x));
8202           return force_to_mode (x, mode, mask, next_select);
8203         }
8204
8205       mask = fuller_mask;
8206       goto binop;
8207
8208     case IOR:
8209     case XOR:
8210       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8211          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8212          operation which may be a bitfield extraction.  Ensure that the
8213          constant we form is not wider than the mode of X.  */
8214
8215       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8216           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8217           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8218           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8219           && CONST_INT_P (XEXP (x, 1))
8220           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8221                + floor_log2 (INTVAL (XEXP (x, 1))))
8222               < GET_MODE_PRECISION (GET_MODE (x)))
8223           && (UINTVAL (XEXP (x, 1))
8224               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8225         {
8226           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8227                           << INTVAL (XEXP (XEXP (x, 0), 1)));
8228           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8229                                       XEXP (XEXP (x, 0), 0), temp);
8230           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8231                                    XEXP (XEXP (x, 0), 1));
8232           return force_to_mode (x, mode, mask, next_select);
8233         }
8234
8235     binop:
8236       /* For most binary operations, just propagate into the operation and
8237          change the mode if we have an operation of that mode.  */
8238
8239       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8240       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8241
8242       /* If we ended up truncating both operands, truncate the result of the
8243          operation instead.  */
8244       if (GET_CODE (op0) == TRUNCATE
8245           && GET_CODE (op1) == TRUNCATE)
8246         {
8247           op0 = XEXP (op0, 0);
8248           op1 = XEXP (op1, 0);
8249         }
8250
8251       op0 = gen_lowpart_or_truncate (op_mode, op0);
8252       op1 = gen_lowpart_or_truncate (op_mode, op1);
8253
8254       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8255         x = simplify_gen_binary (code, op_mode, op0, op1);
8256       break;
8257
8258     case ASHIFT:
8259       /* For left shifts, do the same, but just for the first operand.
8260          However, we cannot do anything with shifts where we cannot
8261          guarantee that the counts are smaller than the size of the mode
8262          because such a count will have a different meaning in a
8263          wider mode.  */
8264
8265       if (! (CONST_INT_P (XEXP (x, 1))
8266              && INTVAL (XEXP (x, 1)) >= 0
8267              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8268           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8269                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8270                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8271         break;
8272
8273       /* If the shift count is a constant and we can do arithmetic in
8274          the mode of the shift, refine which bits we need.  Otherwise, use the
8275          conservative form of the mask.  */
8276       if (CONST_INT_P (XEXP (x, 1))
8277           && INTVAL (XEXP (x, 1)) >= 0
8278           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8279           && HWI_COMPUTABLE_MODE_P (op_mode))
8280         mask >>= INTVAL (XEXP (x, 1));
8281       else
8282         mask = fuller_mask;
8283
8284       op0 = gen_lowpart_or_truncate (op_mode,
8285                                      force_to_mode (XEXP (x, 0), op_mode,
8286                                                     mask, next_select));
8287
8288       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8289         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8290       break;
8291
8292     case LSHIFTRT:
8293       /* Here we can only do something if the shift count is a constant,
8294          this shift constant is valid for the host, and we can do arithmetic
8295          in OP_MODE.  */
8296
8297       if (CONST_INT_P (XEXP (x, 1))
8298           && INTVAL (XEXP (x, 1)) >= 0
8299           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8300           && HWI_COMPUTABLE_MODE_P (op_mode))
8301         {
8302           rtx inner = XEXP (x, 0);
8303           unsigned HOST_WIDE_INT inner_mask;
8304
8305           /* Select the mask of the bits we need for the shift operand.  */
8306           inner_mask = mask << INTVAL (XEXP (x, 1));
8307
8308           /* We can only change the mode of the shift if we can do arithmetic
8309              in the mode of the shift and INNER_MASK is no wider than the
8310              width of X's mode.  */
8311           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8312             op_mode = GET_MODE (x);
8313
8314           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8315
8316           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8317             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8318         }
8319
8320       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8321          shift and AND produces only copies of the sign bit (C2 is one less
8322          than a power of two), we can do this with just a shift.  */
8323
8324       if (GET_CODE (x) == LSHIFTRT
8325           && CONST_INT_P (XEXP (x, 1))
8326           /* The shift puts one of the sign bit copies in the least significant
8327              bit.  */
8328           && ((INTVAL (XEXP (x, 1))
8329                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8330               >= GET_MODE_PRECISION (GET_MODE (x)))
8331           && exact_log2 (mask + 1) >= 0
8332           /* Number of bits left after the shift must be more than the mask
8333              needs.  */
8334           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8335               <= GET_MODE_PRECISION (GET_MODE (x)))
8336           /* Must be more sign bit copies than the mask needs.  */
8337           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8338               >= exact_log2 (mask + 1)))
8339         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8340                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8341                                           - exact_log2 (mask + 1)));
8342
8343       goto shiftrt;
8344
8345     case ASHIFTRT:
8346       /* If we are just looking for the sign bit, we don't need this shift at
8347          all, even if it has a variable count.  */
8348       if (val_signbit_p (GET_MODE (x), mask))
8349         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8350
8351       /* If this is a shift by a constant, get a mask that contains those bits
8352          that are not copies of the sign bit.  We then have two cases:  If
8353          MASK only includes those bits, this can be a logical shift, which may
8354          allow simplifications.  If MASK is a single-bit field not within
8355          those bits, we are requesting a copy of the sign bit and hence can
8356          shift the sign bit to the appropriate location.  */
8357
8358       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8359           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8360         {
8361           int i;
8362
8363           /* If the considered data is wider than HOST_WIDE_INT, we can't
8364              represent a mask for all its bits in a single scalar.
8365              But we only care about the lower bits, so calculate these.  */
8366
8367           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8368             {
8369               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8370
8371               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8372                  is the number of bits a full-width mask would have set.
8373                  We need only shift if these are fewer than nonzero can
8374                  hold.  If not, we must keep all bits set in nonzero.  */
8375
8376               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8377                   < HOST_BITS_PER_WIDE_INT)
8378                 nonzero >>= INTVAL (XEXP (x, 1))
8379                             + HOST_BITS_PER_WIDE_INT
8380                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8381             }
8382           else
8383             {
8384               nonzero = GET_MODE_MASK (GET_MODE (x));
8385               nonzero >>= INTVAL (XEXP (x, 1));
8386             }
8387
8388           if ((mask & ~nonzero) == 0)
8389             {
8390               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8391                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8392               if (GET_CODE (x) != ASHIFTRT)
8393                 return force_to_mode (x, mode, mask, next_select);
8394             }
8395
8396           else if ((i = exact_log2 (mask)) >= 0)
8397             {
8398               x = simplify_shift_const
8399                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8400                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8401
8402               if (GET_CODE (x) != ASHIFTRT)
8403                 return force_to_mode (x, mode, mask, next_select);
8404             }
8405         }
8406
8407       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8408          even if the shift count isn't a constant.  */
8409       if (mask == 1)
8410         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8411                                  XEXP (x, 0), XEXP (x, 1));
8412
8413     shiftrt:
8414
8415       /* If this is a zero- or sign-extension operation that just affects bits
8416          we don't care about, remove it.  Be sure the call above returned
8417          something that is still a shift.  */
8418
8419       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8420           && CONST_INT_P (XEXP (x, 1))
8421           && INTVAL (XEXP (x, 1)) >= 0
8422           && (INTVAL (XEXP (x, 1))
8423               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8424           && GET_CODE (XEXP (x, 0)) == ASHIFT
8425           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8426         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8427                               next_select);
8428
8429       break;
8430
8431     case ROTATE:
8432     case ROTATERT:
8433       /* If the shift count is constant and we can do computations
8434          in the mode of X, compute where the bits we care about are.
8435          Otherwise, we can't do anything.  Don't change the mode of
8436          the shift or propagate MODE into the shift, though.  */
8437       if (CONST_INT_P (XEXP (x, 1))
8438           && INTVAL (XEXP (x, 1)) >= 0)
8439         {
8440           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8441                                             GET_MODE (x), GEN_INT (mask),
8442                                             XEXP (x, 1));
8443           if (temp && CONST_INT_P (temp))
8444             SUBST (XEXP (x, 0),
8445                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8446                                   INTVAL (temp), next_select));
8447         }
8448       break;
8449
8450     case NEG:
8451       /* If we just want the low-order bit, the NEG isn't needed since it
8452          won't change the low-order bit.  */
8453       if (mask == 1)
8454         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8455
8456       /* We need any bits less significant than the most significant bit in
8457          MASK since carries from those bits will affect the bits we are
8458          interested in.  */
8459       mask = fuller_mask;
8460       goto unop;
8461
8462     case NOT:
8463       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8464          same as the XOR case above.  Ensure that the constant we form is not
8465          wider than the mode of X.  */
8466
8467       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8468           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8469           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8470           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8471               < GET_MODE_PRECISION (GET_MODE (x)))
8472           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8473         {
8474           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8475                                GET_MODE (x));
8476           temp = simplify_gen_binary (XOR, GET_MODE (x),
8477                                       XEXP (XEXP (x, 0), 0), temp);
8478           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8479                                    temp, XEXP (XEXP (x, 0), 1));
8480
8481           return force_to_mode (x, mode, mask, next_select);
8482         }
8483
8484       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8485          use the full mask inside the NOT.  */
8486       mask = fuller_mask;
8487
8488     unop:
8489       op0 = gen_lowpart_or_truncate (op_mode,
8490                                      force_to_mode (XEXP (x, 0), mode, mask,
8491                                                     next_select));
8492       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8493         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8494       break;
8495
8496     case NE:
8497       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8498          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8499          which is equal to STORE_FLAG_VALUE.  */
8500       if ((mask & ~STORE_FLAG_VALUE) == 0
8501           && XEXP (x, 1) == const0_rtx
8502           && GET_MODE (XEXP (x, 0)) == mode
8503           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8504           && (nonzero_bits (XEXP (x, 0), mode)
8505               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8506         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8507
8508       break;
8509
8510     case IF_THEN_ELSE:
8511       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8512          written in a narrower mode.  We play it safe and do not do so.  */
8513
8514       SUBST (XEXP (x, 1),
8515              gen_lowpart_or_truncate (GET_MODE (x),
8516                                       force_to_mode (XEXP (x, 1), mode,
8517                                                      mask, next_select)));
8518       SUBST (XEXP (x, 2),
8519              gen_lowpart_or_truncate (GET_MODE (x),
8520                                       force_to_mode (XEXP (x, 2), mode,
8521                                                      mask, next_select)));
8522       break;
8523
8524     default:
8525       break;
8526     }
8527
8528   /* Ensure we return a value of the proper mode.  */
8529   return gen_lowpart_or_truncate (mode, x);
8530 }
8531 \f
8532 /* Return nonzero if X is an expression that has one of two values depending on
8533    whether some other value is zero or nonzero.  In that case, we return the
8534    value that is being tested, *PTRUE is set to the value if the rtx being
8535    returned has a nonzero value, and *PFALSE is set to the other alternative.
8536
8537    If we return zero, we set *PTRUE and *PFALSE to X.  */
8538
8539 static rtx
8540 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8541 {
8542   enum machine_mode mode = GET_MODE (x);
8543   enum rtx_code code = GET_CODE (x);
8544   rtx cond0, cond1, true0, true1, false0, false1;
8545   unsigned HOST_WIDE_INT nz;
8546
8547   /* If we are comparing a value against zero, we are done.  */
8548   if ((code == NE || code == EQ)
8549       && XEXP (x, 1) == const0_rtx)
8550     {
8551       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8552       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8553       return XEXP (x, 0);
8554     }
8555
8556   /* If this is a unary operation whose operand has one of two values, apply
8557      our opcode to compute those values.  */
8558   else if (UNARY_P (x)
8559            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8560     {
8561       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8562       *pfalse = simplify_gen_unary (code, mode, false0,
8563                                     GET_MODE (XEXP (x, 0)));
8564       return cond0;
8565     }
8566
8567   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8568      make can't possibly match and would suppress other optimizations.  */
8569   else if (code == COMPARE)
8570     ;
8571
8572   /* If this is a binary operation, see if either side has only one of two
8573      values.  If either one does or if both do and they are conditional on
8574      the same value, compute the new true and false values.  */
8575   else if (BINARY_P (x))
8576     {
8577       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8578       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8579
8580       if ((cond0 != 0 || cond1 != 0)
8581           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8582         {
8583           /* If if_then_else_cond returned zero, then true/false are the
8584              same rtl.  We must copy one of them to prevent invalid rtl
8585              sharing.  */
8586           if (cond0 == 0)
8587             true0 = copy_rtx (true0);
8588           else if (cond1 == 0)
8589             true1 = copy_rtx (true1);
8590
8591           if (COMPARISON_P (x))
8592             {
8593               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8594                                                 true0, true1);
8595               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8596                                                  false0, false1);
8597              }
8598           else
8599             {
8600               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8601               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8602             }
8603
8604           return cond0 ? cond0 : cond1;
8605         }
8606
8607       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8608          operands is zero when the other is nonzero, and vice-versa,
8609          and STORE_FLAG_VALUE is 1 or -1.  */
8610
8611       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8612           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8613               || code == UMAX)
8614           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8615         {
8616           rtx op0 = XEXP (XEXP (x, 0), 1);
8617           rtx op1 = XEXP (XEXP (x, 1), 1);
8618
8619           cond0 = XEXP (XEXP (x, 0), 0);
8620           cond1 = XEXP (XEXP (x, 1), 0);
8621
8622           if (COMPARISON_P (cond0)
8623               && COMPARISON_P (cond1)
8624               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8625                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8626                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8627                   || ((swap_condition (GET_CODE (cond0))
8628                        == reversed_comparison_code (cond1, NULL))
8629                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8630                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8631               && ! side_effects_p (x))
8632             {
8633               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8634               *pfalse = simplify_gen_binary (MULT, mode,
8635                                              (code == MINUS
8636                                               ? simplify_gen_unary (NEG, mode,
8637                                                                     op1, mode)
8638                                               : op1),
8639                                               const_true_rtx);
8640               return cond0;
8641             }
8642         }
8643
8644       /* Similarly for MULT, AND and UMIN, except that for these the result
8645          is always zero.  */
8646       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8647           && (code == MULT || code == AND || code == UMIN)
8648           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8649         {
8650           cond0 = XEXP (XEXP (x, 0), 0);
8651           cond1 = XEXP (XEXP (x, 1), 0);
8652
8653           if (COMPARISON_P (cond0)
8654               && COMPARISON_P (cond1)
8655               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8656                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8657                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8658                   || ((swap_condition (GET_CODE (cond0))
8659                        == reversed_comparison_code (cond1, NULL))
8660                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8661                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8662               && ! side_effects_p (x))
8663             {
8664               *ptrue = *pfalse = const0_rtx;
8665               return cond0;
8666             }
8667         }
8668     }
8669
8670   else if (code == IF_THEN_ELSE)
8671     {
8672       /* If we have IF_THEN_ELSE already, extract the condition and
8673          canonicalize it if it is NE or EQ.  */
8674       cond0 = XEXP (x, 0);
8675       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8676       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8677         return XEXP (cond0, 0);
8678       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8679         {
8680           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8681           return XEXP (cond0, 0);
8682         }
8683       else
8684         return cond0;
8685     }
8686
8687   /* If X is a SUBREG, we can narrow both the true and false values
8688      if the inner expression, if there is a condition.  */
8689   else if (code == SUBREG
8690            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8691                                                &true0, &false0)))
8692     {
8693       true0 = simplify_gen_subreg (mode, true0,
8694                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8695       false0 = simplify_gen_subreg (mode, false0,
8696                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8697       if (true0 && false0)
8698         {
8699           *ptrue = true0;
8700           *pfalse = false0;
8701           return cond0;
8702         }
8703     }
8704
8705   /* If X is a constant, this isn't special and will cause confusions
8706      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8707   else if (CONSTANT_P (x)
8708            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8709     ;
8710
8711   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8712      will be least confusing to the rest of the compiler.  */
8713   else if (mode == BImode)
8714     {
8715       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8716       return x;
8717     }
8718
8719   /* If X is known to be either 0 or -1, those are the true and
8720      false values when testing X.  */
8721   else if (x == constm1_rtx || x == const0_rtx
8722            || (mode != VOIDmode
8723                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8724     {
8725       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8726       return x;
8727     }
8728
8729   /* Likewise for 0 or a single bit.  */
8730   else if (HWI_COMPUTABLE_MODE_P (mode)
8731            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8732     {
8733       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8734       return x;
8735     }
8736
8737   /* Otherwise fail; show no condition with true and false values the same.  */
8738   *ptrue = *pfalse = x;
8739   return 0;
8740 }
8741 \f
8742 /* Return the value of expression X given the fact that condition COND
8743    is known to be true when applied to REG as its first operand and VAL
8744    as its second.  X is known to not be shared and so can be modified in
8745    place.
8746
8747    We only handle the simplest cases, and specifically those cases that
8748    arise with IF_THEN_ELSE expressions.  */
8749
8750 static rtx
8751 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8752 {
8753   enum rtx_code code = GET_CODE (x);
8754   rtx temp;
8755   const char *fmt;
8756   int i, j;
8757
8758   if (side_effects_p (x))
8759     return x;
8760
8761   /* If either operand of the condition is a floating point value,
8762      then we have to avoid collapsing an EQ comparison.  */
8763   if (cond == EQ
8764       && rtx_equal_p (x, reg)
8765       && ! FLOAT_MODE_P (GET_MODE (x))
8766       && ! FLOAT_MODE_P (GET_MODE (val)))
8767     return val;
8768
8769   if (cond == UNEQ && rtx_equal_p (x, reg))
8770     return val;
8771
8772   /* If X is (abs REG) and we know something about REG's relationship
8773      with zero, we may be able to simplify this.  */
8774
8775   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8776     switch (cond)
8777       {
8778       case GE:  case GT:  case EQ:
8779         return XEXP (x, 0);
8780       case LT:  case LE:
8781         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8782                                    XEXP (x, 0),
8783                                    GET_MODE (XEXP (x, 0)));
8784       default:
8785         break;
8786       }
8787
8788   /* The only other cases we handle are MIN, MAX, and comparisons if the
8789      operands are the same as REG and VAL.  */
8790
8791   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8792     {
8793       if (rtx_equal_p (XEXP (x, 0), val))
8794         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8795
8796       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8797         {
8798           if (COMPARISON_P (x))
8799             {
8800               if (comparison_dominates_p (cond, code))
8801                 return const_true_rtx;
8802
8803               code = reversed_comparison_code (x, NULL);
8804               if (code != UNKNOWN
8805                   && comparison_dominates_p (cond, code))
8806                 return const0_rtx;
8807               else
8808                 return x;
8809             }
8810           else if (code == SMAX || code == SMIN
8811                    || code == UMIN || code == UMAX)
8812             {
8813               int unsignedp = (code == UMIN || code == UMAX);
8814
8815               /* Do not reverse the condition when it is NE or EQ.
8816                  This is because we cannot conclude anything about
8817                  the value of 'SMAX (x, y)' when x is not equal to y,
8818                  but we can when x equals y.  */
8819               if ((code == SMAX || code == UMAX)
8820                   && ! (cond == EQ || cond == NE))
8821                 cond = reverse_condition (cond);
8822
8823               switch (cond)
8824                 {
8825                 case GE:   case GT:
8826                   return unsignedp ? x : XEXP (x, 1);
8827                 case LE:   case LT:
8828                   return unsignedp ? x : XEXP (x, 0);
8829                 case GEU:  case GTU:
8830                   return unsignedp ? XEXP (x, 1) : x;
8831                 case LEU:  case LTU:
8832                   return unsignedp ? XEXP (x, 0) : x;
8833                 default:
8834                   break;
8835                 }
8836             }
8837         }
8838     }
8839   else if (code == SUBREG)
8840     {
8841       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8842       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8843
8844       if (SUBREG_REG (x) != r)
8845         {
8846           /* We must simplify subreg here, before we lose track of the
8847              original inner_mode.  */
8848           new_rtx = simplify_subreg (GET_MODE (x), r,
8849                                  inner_mode, SUBREG_BYTE (x));
8850           if (new_rtx)
8851             return new_rtx;
8852           else
8853             SUBST (SUBREG_REG (x), r);
8854         }
8855
8856       return x;
8857     }
8858   /* We don't have to handle SIGN_EXTEND here, because even in the
8859      case of replacing something with a modeless CONST_INT, a
8860      CONST_INT is already (supposed to be) a valid sign extension for
8861      its narrower mode, which implies it's already properly
8862      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8863      story is different.  */
8864   else if (code == ZERO_EXTEND)
8865     {
8866       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8867       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8868
8869       if (XEXP (x, 0) != r)
8870         {
8871           /* We must simplify the zero_extend here, before we lose
8872              track of the original inner_mode.  */
8873           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8874                                           r, inner_mode);
8875           if (new_rtx)
8876             return new_rtx;
8877           else
8878             SUBST (XEXP (x, 0), r);
8879         }
8880
8881       return x;
8882     }
8883
8884   fmt = GET_RTX_FORMAT (code);
8885   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8886     {
8887       if (fmt[i] == 'e')
8888         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8889       else if (fmt[i] == 'E')
8890         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8891           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8892                                                 cond, reg, val));
8893     }
8894
8895   return x;
8896 }
8897 \f
8898 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8899    assignment as a field assignment.  */
8900
8901 static int
8902 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8903 {
8904   if (x == y || rtx_equal_p (x, y))
8905     return 1;
8906
8907   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8908     return 0;
8909
8910   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8911      Note that all SUBREGs of MEM are paradoxical; otherwise they
8912      would have been rewritten.  */
8913   if (MEM_P (x) && GET_CODE (y) == SUBREG
8914       && MEM_P (SUBREG_REG (y))
8915       && rtx_equal_p (SUBREG_REG (y),
8916                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8917     return 1;
8918
8919   if (MEM_P (y) && GET_CODE (x) == SUBREG
8920       && MEM_P (SUBREG_REG (x))
8921       && rtx_equal_p (SUBREG_REG (x),
8922                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8923     return 1;
8924
8925   /* We used to see if get_last_value of X and Y were the same but that's
8926      not correct.  In one direction, we'll cause the assignment to have
8927      the wrong destination and in the case, we'll import a register into this
8928      insn that might have already have been dead.   So fail if none of the
8929      above cases are true.  */
8930   return 0;
8931 }
8932 \f
8933 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8934    Return that assignment if so.
8935
8936    We only handle the most common cases.  */
8937
8938 static rtx
8939 make_field_assignment (rtx x)
8940 {
8941   rtx dest = SET_DEST (x);
8942   rtx src = SET_SRC (x);
8943   rtx assign;
8944   rtx rhs, lhs;
8945   HOST_WIDE_INT c1;
8946   HOST_WIDE_INT pos;
8947   unsigned HOST_WIDE_INT len;
8948   rtx other;
8949   enum machine_mode mode;
8950
8951   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8952      a clear of a one-bit field.  We will have changed it to
8953      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8954      for a SUBREG.  */
8955
8956   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8957       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8958       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8959       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8960     {
8961       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8962                                 1, 1, 1, 0);
8963       if (assign != 0)
8964         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8965       return x;
8966     }
8967
8968   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8969       && subreg_lowpart_p (XEXP (src, 0))
8970       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8971           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8972       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8973       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8974       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8975       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8976     {
8977       assign = make_extraction (VOIDmode, dest, 0,
8978                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8979                                 1, 1, 1, 0);
8980       if (assign != 0)
8981         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8982       return x;
8983     }
8984
8985   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8986      one-bit field.  */
8987   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8988       && XEXP (XEXP (src, 0), 0) == const1_rtx
8989       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8990     {
8991       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8992                                 1, 1, 1, 0);
8993       if (assign != 0)
8994         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8995       return x;
8996     }
8997
8998   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8999      SRC is an AND with all bits of that field set, then we can discard
9000      the AND.  */
9001   if (GET_CODE (dest) == ZERO_EXTRACT
9002       && CONST_INT_P (XEXP (dest, 1))
9003       && GET_CODE (src) == AND
9004       && CONST_INT_P (XEXP (src, 1)))
9005     {
9006       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9007       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9008       unsigned HOST_WIDE_INT ze_mask;
9009
9010       if (width >= HOST_BITS_PER_WIDE_INT)
9011         ze_mask = -1;
9012       else
9013         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9014
9015       /* Complete overlap.  We can remove the source AND.  */
9016       if ((and_mask & ze_mask) == ze_mask)
9017         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9018
9019       /* Partial overlap.  We can reduce the source AND.  */
9020       if ((and_mask & ze_mask) != and_mask)
9021         {
9022           mode = GET_MODE (src);
9023           src = gen_rtx_AND (mode, XEXP (src, 0),
9024                              gen_int_mode (and_mask & ze_mask, mode));
9025           return gen_rtx_SET (VOIDmode, dest, src);
9026         }
9027     }
9028
9029   /* The other case we handle is assignments into a constant-position
9030      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9031      a mask that has all one bits except for a group of zero bits and
9032      OTHER is known to have zeros where C1 has ones, this is such an
9033      assignment.  Compute the position and length from C1.  Shift OTHER
9034      to the appropriate position, force it to the required mode, and
9035      make the extraction.  Check for the AND in both operands.  */
9036
9037   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9038     return x;
9039
9040   rhs = expand_compound_operation (XEXP (src, 0));
9041   lhs = expand_compound_operation (XEXP (src, 1));
9042
9043   if (GET_CODE (rhs) == AND
9044       && CONST_INT_P (XEXP (rhs, 1))
9045       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9046     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9047   else if (GET_CODE (lhs) == AND
9048            && CONST_INT_P (XEXP (lhs, 1))
9049            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9050     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9051   else
9052     return x;
9053
9054   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9055   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9056       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9057       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9058     return x;
9059
9060   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9061   if (assign == 0)
9062     return x;
9063
9064   /* The mode to use for the source is the mode of the assignment, or of
9065      what is inside a possible STRICT_LOW_PART.  */
9066   mode = (GET_CODE (assign) == STRICT_LOW_PART
9067           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9068
9069   /* Shift OTHER right POS places and make it the source, restricting it
9070      to the proper length and mode.  */
9071
9072   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9073                                                      GET_MODE (src),
9074                                                      other, pos),
9075                                dest);
9076   src = force_to_mode (src, mode,
9077                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9078                        ? ~(unsigned HOST_WIDE_INT) 0
9079                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9080                        0);
9081
9082   /* If SRC is masked by an AND that does not make a difference in
9083      the value being stored, strip it.  */
9084   if (GET_CODE (assign) == ZERO_EXTRACT
9085       && CONST_INT_P (XEXP (assign, 1))
9086       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9087       && GET_CODE (src) == AND
9088       && CONST_INT_P (XEXP (src, 1))
9089       && UINTVAL (XEXP (src, 1))
9090          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9091     src = XEXP (src, 0);
9092
9093   return gen_rtx_SET (VOIDmode, assign, src);
9094 }
9095 \f
9096 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9097    if so.  */
9098
9099 static rtx
9100 apply_distributive_law (rtx x)
9101 {
9102   enum rtx_code code = GET_CODE (x);
9103   enum rtx_code inner_code;
9104   rtx lhs, rhs, other;
9105   rtx tem;
9106
9107   /* Distributivity is not true for floating point as it can change the
9108      value.  So we don't do it unless -funsafe-math-optimizations.  */
9109   if (FLOAT_MODE_P (GET_MODE (x))
9110       && ! flag_unsafe_math_optimizations)
9111     return x;
9112
9113   /* The outer operation can only be one of the following:  */
9114   if (code != IOR && code != AND && code != XOR
9115       && code != PLUS && code != MINUS)
9116     return x;
9117
9118   lhs = XEXP (x, 0);
9119   rhs = XEXP (x, 1);
9120
9121   /* If either operand is a primitive we can't do anything, so get out
9122      fast.  */
9123   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9124     return x;
9125
9126   lhs = expand_compound_operation (lhs);
9127   rhs = expand_compound_operation (rhs);
9128   inner_code = GET_CODE (lhs);
9129   if (inner_code != GET_CODE (rhs))
9130     return x;
9131
9132   /* See if the inner and outer operations distribute.  */
9133   switch (inner_code)
9134     {
9135     case LSHIFTRT:
9136     case ASHIFTRT:
9137     case AND:
9138     case IOR:
9139       /* These all distribute except over PLUS.  */
9140       if (code == PLUS || code == MINUS)
9141         return x;
9142       break;
9143
9144     case MULT:
9145       if (code != PLUS && code != MINUS)
9146         return x;
9147       break;
9148
9149     case ASHIFT:
9150       /* This is also a multiply, so it distributes over everything.  */
9151       break;
9152
9153     /* This used to handle SUBREG, but this turned out to be counter-
9154        productive, since (subreg (op ...)) usually is not handled by
9155        insn patterns, and this "optimization" therefore transformed
9156        recognizable patterns into unrecognizable ones.  Therefore the
9157        SUBREG case was removed from here.
9158
9159        It is possible that distributing SUBREG over arithmetic operations
9160        leads to an intermediate result than can then be optimized further,
9161        e.g. by moving the outer SUBREG to the other side of a SET as done
9162        in simplify_set.  This seems to have been the original intent of
9163        handling SUBREGs here.
9164
9165        However, with current GCC this does not appear to actually happen,
9166        at least on major platforms.  If some case is found where removing
9167        the SUBREG case here prevents follow-on optimizations, distributing
9168        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9169
9170     default:
9171       return x;
9172     }
9173
9174   /* Set LHS and RHS to the inner operands (A and B in the example
9175      above) and set OTHER to the common operand (C in the example).
9176      There is only one way to do this unless the inner operation is
9177      commutative.  */
9178   if (COMMUTATIVE_ARITH_P (lhs)
9179       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9180     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9181   else if (COMMUTATIVE_ARITH_P (lhs)
9182            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9183     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9184   else if (COMMUTATIVE_ARITH_P (lhs)
9185            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9186     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9187   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9188     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9189   else
9190     return x;
9191
9192   /* Form the new inner operation, seeing if it simplifies first.  */
9193   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9194
9195   /* There is one exception to the general way of distributing:
9196      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9197   if (code == XOR && inner_code == IOR)
9198     {
9199       inner_code = AND;
9200       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9201     }
9202
9203   /* We may be able to continuing distributing the result, so call
9204      ourselves recursively on the inner operation before forming the
9205      outer operation, which we return.  */
9206   return simplify_gen_binary (inner_code, GET_MODE (x),
9207                               apply_distributive_law (tem), other);
9208 }
9209
9210 /* See if X is of the form (* (+ A B) C), and if so convert to
9211    (+ (* A C) (* B C)) and try to simplify.
9212
9213    Most of the time, this results in no change.  However, if some of
9214    the operands are the same or inverses of each other, simplifications
9215    will result.
9216
9217    For example, (and (ior A B) (not B)) can occur as the result of
9218    expanding a bit field assignment.  When we apply the distributive
9219    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9220    which then simplifies to (and (A (not B))).
9221
9222    Note that no checks happen on the validity of applying the inverse
9223    distributive law.  This is pointless since we can do it in the
9224    few places where this routine is called.
9225
9226    N is the index of the term that is decomposed (the arithmetic operation,
9227    i.e. (+ A B) in the first example above).  !N is the index of the term that
9228    is distributed, i.e. of C in the first example above.  */
9229 static rtx
9230 distribute_and_simplify_rtx (rtx x, int n)
9231 {
9232   enum machine_mode mode;
9233   enum rtx_code outer_code, inner_code;
9234   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9235
9236   /* Distributivity is not true for floating point as it can change the
9237      value.  So we don't do it unless -funsafe-math-optimizations.  */
9238   if (FLOAT_MODE_P (GET_MODE (x))
9239       && ! flag_unsafe_math_optimizations)
9240     return NULL_RTX;
9241
9242   decomposed = XEXP (x, n);
9243   if (!ARITHMETIC_P (decomposed))
9244     return NULL_RTX;
9245
9246   mode = GET_MODE (x);
9247   outer_code = GET_CODE (x);
9248   distributed = XEXP (x, !n);
9249
9250   inner_code = GET_CODE (decomposed);
9251   inner_op0 = XEXP (decomposed, 0);
9252   inner_op1 = XEXP (decomposed, 1);
9253
9254   /* Special case (and (xor B C) (not A)), which is equivalent to
9255      (xor (ior A B) (ior A C))  */
9256   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9257     {
9258       distributed = XEXP (distributed, 0);
9259       outer_code = IOR;
9260     }
9261
9262   if (n == 0)
9263     {
9264       /* Distribute the second term.  */
9265       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9266       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9267     }
9268   else
9269     {
9270       /* Distribute the first term.  */
9271       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9272       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9273     }
9274
9275   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9276                                                      new_op0, new_op1));
9277   if (GET_CODE (tmp) != outer_code
9278       && (set_src_cost (tmp, optimize_this_for_speed_p)
9279           < set_src_cost (x, optimize_this_for_speed_p)))
9280     return tmp;
9281
9282   return NULL_RTX;
9283 }
9284 \f
9285 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9286    in MODE.  Return an equivalent form, if different from (and VAROP
9287    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9288
9289 static rtx
9290 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9291                           unsigned HOST_WIDE_INT constop)
9292 {
9293   unsigned HOST_WIDE_INT nonzero;
9294   unsigned HOST_WIDE_INT orig_constop;
9295   rtx orig_varop;
9296   int i;
9297
9298   orig_varop = varop;
9299   orig_constop = constop;
9300   if (GET_CODE (varop) == CLOBBER)
9301     return NULL_RTX;
9302
9303   /* Simplify VAROP knowing that we will be only looking at some of the
9304      bits in it.
9305
9306      Note by passing in CONSTOP, we guarantee that the bits not set in
9307      CONSTOP are not significant and will never be examined.  We must
9308      ensure that is the case by explicitly masking out those bits
9309      before returning.  */
9310   varop = force_to_mode (varop, mode, constop, 0);
9311
9312   /* If VAROP is a CLOBBER, we will fail so return it.  */
9313   if (GET_CODE (varop) == CLOBBER)
9314     return varop;
9315
9316   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9317      to VAROP and return the new constant.  */
9318   if (CONST_INT_P (varop))
9319     return gen_int_mode (INTVAL (varop) & constop, mode);
9320
9321   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9322      a call to nonzero_bits, here we don't care about bits outside
9323      MODE.  */
9324
9325   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9326
9327   /* Turn off all bits in the constant that are known to already be zero.
9328      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9329      which is tested below.  */
9330
9331   constop &= nonzero;
9332
9333   /* If we don't have any bits left, return zero.  */
9334   if (constop == 0)
9335     return const0_rtx;
9336
9337   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9338      a power of two, we can replace this with an ASHIFT.  */
9339   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9340       && (i = exact_log2 (constop)) >= 0)
9341     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9342
9343   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9344      or XOR, then try to apply the distributive law.  This may eliminate
9345      operations if either branch can be simplified because of the AND.
9346      It may also make some cases more complex, but those cases probably
9347      won't match a pattern either with or without this.  */
9348
9349   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9350     return
9351       gen_lowpart
9352         (mode,
9353          apply_distributive_law
9354          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9355                                simplify_and_const_int (NULL_RTX,
9356                                                        GET_MODE (varop),
9357                                                        XEXP (varop, 0),
9358                                                        constop),
9359                                simplify_and_const_int (NULL_RTX,
9360                                                        GET_MODE (varop),
9361                                                        XEXP (varop, 1),
9362                                                        constop))));
9363
9364   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9365      the AND and see if one of the operands simplifies to zero.  If so, we
9366      may eliminate it.  */
9367
9368   if (GET_CODE (varop) == PLUS
9369       && exact_log2 (constop + 1) >= 0)
9370     {
9371       rtx o0, o1;
9372
9373       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9374       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9375       if (o0 == const0_rtx)
9376         return o1;
9377       if (o1 == const0_rtx)
9378         return o0;
9379     }
9380
9381   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9382   varop = gen_lowpart (mode, varop);
9383   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9384     return NULL_RTX;
9385
9386   /* If we are only masking insignificant bits, return VAROP.  */
9387   if (constop == nonzero)
9388     return varop;
9389
9390   if (varop == orig_varop && constop == orig_constop)
9391     return NULL_RTX;
9392
9393   /* Otherwise, return an AND.  */
9394   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9395 }
9396
9397
9398 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9399    in MODE.
9400
9401    Return an equivalent form, if different from X.  Otherwise, return X.  If
9402    X is zero, we are to always construct the equivalent form.  */
9403
9404 static rtx
9405 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9406                         unsigned HOST_WIDE_INT constop)
9407 {
9408   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9409   if (tem)
9410     return tem;
9411
9412   if (!x)
9413     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9414                              gen_int_mode (constop, mode));
9415   if (GET_MODE (x) != mode)
9416     x = gen_lowpart (mode, x);
9417   return x;
9418 }
9419 \f
9420 /* Given a REG, X, compute which bits in X can be nonzero.
9421    We don't care about bits outside of those defined in MODE.
9422
9423    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9424    a shift, AND, or zero_extract, we can do better.  */
9425
9426 static rtx
9427 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9428                               const_rtx known_x ATTRIBUTE_UNUSED,
9429                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9430                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9431                               unsigned HOST_WIDE_INT *nonzero)
9432 {
9433   rtx tem;
9434   reg_stat_type *rsp;
9435
9436   /* If X is a register whose nonzero bits value is current, use it.
9437      Otherwise, if X is a register whose value we can find, use that
9438      value.  Otherwise, use the previously-computed global nonzero bits
9439      for this register.  */
9440
9441   rsp = &reg_stat[REGNO (x)];
9442   if (rsp->last_set_value != 0
9443       && (rsp->last_set_mode == mode
9444           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9445               && GET_MODE_CLASS (mode) == MODE_INT))
9446       && ((rsp->last_set_label >= label_tick_ebb_start
9447            && rsp->last_set_label < label_tick)
9448           || (rsp->last_set_label == label_tick
9449               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9450           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9451               && REG_N_SETS (REGNO (x)) == 1
9452               && !REGNO_REG_SET_P
9453                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9454     {
9455       *nonzero &= rsp->last_set_nonzero_bits;
9456       return NULL;
9457     }
9458
9459   tem = get_last_value (x);
9460
9461   if (tem)
9462     {
9463 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9464       /* If X is narrower than MODE and TEM is a non-negative
9465          constant that would appear negative in the mode of X,
9466          sign-extend it for use in reg_nonzero_bits because some
9467          machines (maybe most) will actually do the sign-extension
9468          and this is the conservative approach.
9469
9470          ??? For 2.5, try to tighten up the MD files in this regard
9471          instead of this kludge.  */
9472
9473       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9474           && CONST_INT_P (tem)
9475           && INTVAL (tem) > 0
9476           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9477         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9478 #endif
9479       return tem;
9480     }
9481   else if (nonzero_sign_valid && rsp->nonzero_bits)
9482     {
9483       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9484
9485       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9486         /* We don't know anything about the upper bits.  */
9487         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9488       *nonzero &= mask;
9489     }
9490
9491   return NULL;
9492 }
9493
9494 /* Return the number of bits at the high-order end of X that are known to
9495    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9496    VOIDmode, X will be used in its own mode.  The returned value  will always
9497    be between 1 and the number of bits in MODE.  */
9498
9499 static rtx
9500 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9501                                      const_rtx known_x ATTRIBUTE_UNUSED,
9502                                      enum machine_mode known_mode
9503                                      ATTRIBUTE_UNUSED,
9504                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9505                                      unsigned int *result)
9506 {
9507   rtx tem;
9508   reg_stat_type *rsp;
9509
9510   rsp = &reg_stat[REGNO (x)];
9511   if (rsp->last_set_value != 0
9512       && rsp->last_set_mode == mode
9513       && ((rsp->last_set_label >= label_tick_ebb_start
9514            && rsp->last_set_label < label_tick)
9515           || (rsp->last_set_label == label_tick
9516               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9517           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9518               && REG_N_SETS (REGNO (x)) == 1
9519               && !REGNO_REG_SET_P
9520                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9521     {
9522       *result = rsp->last_set_sign_bit_copies;
9523       return NULL;
9524     }
9525
9526   tem = get_last_value (x);
9527   if (tem != 0)
9528     return tem;
9529
9530   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9531       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9532     *result = rsp->sign_bit_copies;
9533
9534   return NULL;
9535 }
9536 \f
9537 /* Return the number of "extended" bits there are in X, when interpreted
9538    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9539    unsigned quantities, this is the number of high-order zero bits.
9540    For signed quantities, this is the number of copies of the sign bit
9541    minus 1.  In both case, this function returns the number of "spare"
9542    bits.  For example, if two quantities for which this function returns
9543    at least 1 are added, the addition is known not to overflow.
9544
9545    This function will always return 0 unless called during combine, which
9546    implies that it must be called from a define_split.  */
9547
9548 unsigned int
9549 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9550 {
9551   if (nonzero_sign_valid == 0)
9552     return 0;
9553
9554   return (unsignedp
9555           ? (HWI_COMPUTABLE_MODE_P (mode)
9556              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9557                                - floor_log2 (nonzero_bits (x, mode)))
9558              : 0)
9559           : num_sign_bit_copies (x, mode) - 1);
9560 }
9561
9562 /* This function is called from `simplify_shift_const' to merge two
9563    outer operations.  Specifically, we have already found that we need
9564    to perform operation *POP0 with constant *PCONST0 at the outermost
9565    position.  We would now like to also perform OP1 with constant CONST1
9566    (with *POP0 being done last).
9567
9568    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9569    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9570    complement the innermost operand, otherwise it is unchanged.
9571
9572    MODE is the mode in which the operation will be done.  No bits outside
9573    the width of this mode matter.  It is assumed that the width of this mode
9574    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9575
9576    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9577    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9578    result is simply *PCONST0.
9579
9580    If the resulting operation cannot be expressed as one operation, we
9581    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9582
9583 static int
9584 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9585 {
9586   enum rtx_code op0 = *pop0;
9587   HOST_WIDE_INT const0 = *pconst0;
9588
9589   const0 &= GET_MODE_MASK (mode);
9590   const1 &= GET_MODE_MASK (mode);
9591
9592   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9593   if (op0 == AND)
9594     const1 &= const0;
9595
9596   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9597      if OP0 is SET.  */
9598
9599   if (op1 == UNKNOWN || op0 == SET)
9600     return 1;
9601
9602   else if (op0 == UNKNOWN)
9603     op0 = op1, const0 = const1;
9604
9605   else if (op0 == op1)
9606     {
9607       switch (op0)
9608         {
9609         case AND:
9610           const0 &= const1;
9611           break;
9612         case IOR:
9613           const0 |= const1;
9614           break;
9615         case XOR:
9616           const0 ^= const1;
9617           break;
9618         case PLUS:
9619           const0 += const1;
9620           break;
9621         case NEG:
9622           op0 = UNKNOWN;
9623           break;
9624         default:
9625           break;
9626         }
9627     }
9628
9629   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9630   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9631     return 0;
9632
9633   /* If the two constants aren't the same, we can't do anything.  The
9634      remaining six cases can all be done.  */
9635   else if (const0 != const1)
9636     return 0;
9637
9638   else
9639     switch (op0)
9640       {
9641       case IOR:
9642         if (op1 == AND)
9643           /* (a & b) | b == b */
9644           op0 = SET;
9645         else /* op1 == XOR */
9646           /* (a ^ b) | b == a | b */
9647           {;}
9648         break;
9649
9650       case XOR:
9651         if (op1 == AND)
9652           /* (a & b) ^ b == (~a) & b */
9653           op0 = AND, *pcomp_p = 1;
9654         else /* op1 == IOR */
9655           /* (a | b) ^ b == a & ~b */
9656           op0 = AND, const0 = ~const0;
9657         break;
9658
9659       case AND:
9660         if (op1 == IOR)
9661           /* (a | b) & b == b */
9662         op0 = SET;
9663         else /* op1 == XOR */
9664           /* (a ^ b) & b) == (~a) & b */
9665           *pcomp_p = 1;
9666         break;
9667       default:
9668         break;
9669       }
9670
9671   /* Check for NO-OP cases.  */
9672   const0 &= GET_MODE_MASK (mode);
9673   if (const0 == 0
9674       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9675     op0 = UNKNOWN;
9676   else if (const0 == 0 && op0 == AND)
9677     op0 = SET;
9678   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9679            && op0 == AND)
9680     op0 = UNKNOWN;
9681
9682   *pop0 = op0;
9683
9684   /* ??? Slightly redundant with the above mask, but not entirely.
9685      Moving this above means we'd have to sign-extend the mode mask
9686      for the final test.  */
9687   if (op0 != UNKNOWN && op0 != NEG)
9688     *pconst0 = trunc_int_for_mode (const0, mode);
9689
9690   return 1;
9691 }
9692 \f
9693 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9694    the shift in.  The original shift operation CODE is performed on OP in
9695    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9696    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9697    result of the shift is subject to operation OUTER_CODE with operand
9698    OUTER_CONST.  */
9699
9700 static enum machine_mode
9701 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9702                       enum machine_mode orig_mode, enum machine_mode mode,
9703                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9704 {
9705   if (orig_mode == mode)
9706     return mode;
9707   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9708
9709   /* In general we can't perform in wider mode for right shift and rotate.  */
9710   switch (code)
9711     {
9712     case ASHIFTRT:
9713       /* We can still widen if the bits brought in from the left are identical
9714          to the sign bit of ORIG_MODE.  */
9715       if (num_sign_bit_copies (op, mode)
9716           > (unsigned) (GET_MODE_PRECISION (mode)
9717                         - GET_MODE_PRECISION (orig_mode)))
9718         return mode;
9719       return orig_mode;
9720
9721     case LSHIFTRT:
9722       /* Similarly here but with zero bits.  */
9723       if (HWI_COMPUTABLE_MODE_P (mode)
9724           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9725         return mode;
9726
9727       /* We can also widen if the bits brought in will be masked off.  This
9728          operation is performed in ORIG_MODE.  */
9729       if (outer_code == AND)
9730         {
9731           int care_bits = low_bitmask_len (orig_mode, outer_const);
9732
9733           if (care_bits >= 0
9734               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9735             return mode;
9736         }
9737       /* fall through */
9738
9739     case ROTATE:
9740       return orig_mode;
9741
9742     case ROTATERT:
9743       gcc_unreachable ();
9744
9745     default:
9746       return mode;
9747     }
9748 }
9749
9750 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9751    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9752    if we cannot simplify it.  Otherwise, return a simplified value.
9753
9754    The shift is normally computed in the widest mode we find in VAROP, as
9755    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9756    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9757
9758 static rtx
9759 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9760                         rtx varop, int orig_count)
9761 {
9762   enum rtx_code orig_code = code;
9763   rtx orig_varop = varop;
9764   int count;
9765   enum machine_mode mode = result_mode;
9766   enum machine_mode shift_mode, tmode;
9767   unsigned int mode_words
9768     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9769   /* We form (outer_op (code varop count) (outer_const)).  */
9770   enum rtx_code outer_op = UNKNOWN;
9771   HOST_WIDE_INT outer_const = 0;
9772   int complement_p = 0;
9773   rtx new_rtx, x;
9774
9775   /* Make sure and truncate the "natural" shift on the way in.  We don't
9776      want to do this inside the loop as it makes it more difficult to
9777      combine shifts.  */
9778   if (SHIFT_COUNT_TRUNCATED)
9779     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9780
9781   /* If we were given an invalid count, don't do anything except exactly
9782      what was requested.  */
9783
9784   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9785     return NULL_RTX;
9786
9787   count = orig_count;
9788
9789   /* Unless one of the branches of the `if' in this loop does a `continue',
9790      we will `break' the loop after the `if'.  */
9791
9792   while (count != 0)
9793     {
9794       /* If we have an operand of (clobber (const_int 0)), fail.  */
9795       if (GET_CODE (varop) == CLOBBER)
9796         return NULL_RTX;
9797
9798       /* Convert ROTATERT to ROTATE.  */
9799       if (code == ROTATERT)
9800         {
9801           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9802           code = ROTATE;
9803           if (VECTOR_MODE_P (result_mode))
9804             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9805           else
9806             count = bitsize - count;
9807         }
9808
9809       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9810                                          mode, outer_op, outer_const);
9811
9812       /* Handle cases where the count is greater than the size of the mode
9813          minus 1.  For ASHIFT, use the size minus one as the count (this can
9814          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9815          take the count modulo the size.  For other shifts, the result is
9816          zero.
9817
9818          Since these shifts are being produced by the compiler by combining
9819          multiple operations, each of which are defined, we know what the
9820          result is supposed to be.  */
9821
9822       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9823         {
9824           if (code == ASHIFTRT)
9825             count = GET_MODE_PRECISION (shift_mode) - 1;
9826           else if (code == ROTATE || code == ROTATERT)
9827             count %= GET_MODE_PRECISION (shift_mode);
9828           else
9829             {
9830               /* We can't simply return zero because there may be an
9831                  outer op.  */
9832               varop = const0_rtx;
9833               count = 0;
9834               break;
9835             }
9836         }
9837
9838       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9839          here would cause an infinite loop.  */
9840       if (complement_p)
9841         break;
9842
9843       /* An arithmetic right shift of a quantity known to be -1 or 0
9844          is a no-op.  */
9845       if (code == ASHIFTRT
9846           && (num_sign_bit_copies (varop, shift_mode)
9847               == GET_MODE_PRECISION (shift_mode)))
9848         {
9849           count = 0;
9850           break;
9851         }
9852
9853       /* If we are doing an arithmetic right shift and discarding all but
9854          the sign bit copies, this is equivalent to doing a shift by the
9855          bitsize minus one.  Convert it into that shift because it will often
9856          allow other simplifications.  */
9857
9858       if (code == ASHIFTRT
9859           && (count + num_sign_bit_copies (varop, shift_mode)
9860               >= GET_MODE_PRECISION (shift_mode)))
9861         count = GET_MODE_PRECISION (shift_mode) - 1;
9862
9863       /* We simplify the tests below and elsewhere by converting
9864          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9865          `make_compound_operation' will convert it to an ASHIFTRT for
9866          those machines (such as VAX) that don't have an LSHIFTRT.  */
9867       if (code == ASHIFTRT
9868           && val_signbit_known_clear_p (shift_mode,
9869                                         nonzero_bits (varop, shift_mode)))
9870         code = LSHIFTRT;
9871
9872       if (((code == LSHIFTRT
9873             && HWI_COMPUTABLE_MODE_P (shift_mode)
9874             && !(nonzero_bits (varop, shift_mode) >> count))
9875            || (code == ASHIFT
9876                && HWI_COMPUTABLE_MODE_P (shift_mode)
9877                && !((nonzero_bits (varop, shift_mode) << count)
9878                     & GET_MODE_MASK (shift_mode))))
9879           && !side_effects_p (varop))
9880         varop = const0_rtx;
9881
9882       switch (GET_CODE (varop))
9883         {
9884         case SIGN_EXTEND:
9885         case ZERO_EXTEND:
9886         case SIGN_EXTRACT:
9887         case ZERO_EXTRACT:
9888           new_rtx = expand_compound_operation (varop);
9889           if (new_rtx != varop)
9890             {
9891               varop = new_rtx;
9892               continue;
9893             }
9894           break;
9895
9896         case MEM:
9897           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9898              minus the width of a smaller mode, we can do this with a
9899              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9900           if ((code == ASHIFTRT || code == LSHIFTRT)
9901               && ! mode_dependent_address_p (XEXP (varop, 0),
9902                                              MEM_ADDR_SPACE (varop))
9903               && ! MEM_VOLATILE_P (varop)
9904               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9905                                          MODE_INT, 1)) != BLKmode)
9906             {
9907               new_rtx = adjust_address_nv (varop, tmode,
9908                                        BYTES_BIG_ENDIAN ? 0
9909                                        : count / BITS_PER_UNIT);
9910
9911               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9912                                      : ZERO_EXTEND, mode, new_rtx);
9913               count = 0;
9914               continue;
9915             }
9916           break;
9917
9918         case SUBREG:
9919           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9920              the same number of words as what we've seen so far.  Then store
9921              the widest mode in MODE.  */
9922           if (subreg_lowpart_p (varop)
9923               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9924                   > GET_MODE_SIZE (GET_MODE (varop)))
9925               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9926                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9927                  == mode_words
9928               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9929               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9930             {
9931               varop = SUBREG_REG (varop);
9932               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9933                 mode = GET_MODE (varop);
9934               continue;
9935             }
9936           break;
9937
9938         case MULT:
9939           /* Some machines use MULT instead of ASHIFT because MULT
9940              is cheaper.  But it is still better on those machines to
9941              merge two shifts into one.  */
9942           if (CONST_INT_P (XEXP (varop, 1))
9943               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9944             {
9945               varop
9946                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9947                                        XEXP (varop, 0),
9948                                        GEN_INT (exact_log2 (
9949                                                 UINTVAL (XEXP (varop, 1)))));
9950               continue;
9951             }
9952           break;
9953
9954         case UDIV:
9955           /* Similar, for when divides are cheaper.  */
9956           if (CONST_INT_P (XEXP (varop, 1))
9957               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9958             {
9959               varop
9960                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9961                                        XEXP (varop, 0),
9962                                        GEN_INT (exact_log2 (
9963                                                 UINTVAL (XEXP (varop, 1)))));
9964               continue;
9965             }
9966           break;
9967
9968         case ASHIFTRT:
9969           /* If we are extracting just the sign bit of an arithmetic
9970              right shift, that shift is not needed.  However, the sign
9971              bit of a wider mode may be different from what would be
9972              interpreted as the sign bit in a narrower mode, so, if
9973              the result is narrower, don't discard the shift.  */
9974           if (code == LSHIFTRT
9975               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9976               && (GET_MODE_BITSIZE (result_mode)
9977                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9978             {
9979               varop = XEXP (varop, 0);
9980               continue;
9981             }
9982
9983           /* ... fall through ...  */
9984
9985         case LSHIFTRT:
9986         case ASHIFT:
9987         case ROTATE:
9988           /* Here we have two nested shifts.  The result is usually the
9989              AND of a new shift with a mask.  We compute the result below.  */
9990           if (CONST_INT_P (XEXP (varop, 1))
9991               && INTVAL (XEXP (varop, 1)) >= 0
9992               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
9993               && HWI_COMPUTABLE_MODE_P (result_mode)
9994               && HWI_COMPUTABLE_MODE_P (mode)
9995               && !VECTOR_MODE_P (result_mode))
9996             {
9997               enum rtx_code first_code = GET_CODE (varop);
9998               unsigned int first_count = INTVAL (XEXP (varop, 1));
9999               unsigned HOST_WIDE_INT mask;
10000               rtx mask_rtx;
10001
10002               /* We have one common special case.  We can't do any merging if
10003                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10004                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10005                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10006                  we can convert it to
10007                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10008                  This simplifies certain SIGN_EXTEND operations.  */
10009               if (code == ASHIFT && first_code == ASHIFTRT
10010                   && count == (GET_MODE_PRECISION (result_mode)
10011                                - GET_MODE_PRECISION (GET_MODE (varop))))
10012                 {
10013                   /* C3 has the low-order C1 bits zero.  */
10014
10015                   mask = GET_MODE_MASK (mode)
10016                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10017
10018                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10019                                                   XEXP (varop, 0), mask);
10020                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10021                                                 varop, count);
10022                   count = first_count;
10023                   code = ASHIFTRT;
10024                   continue;
10025                 }
10026
10027               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10028                  than C1 high-order bits equal to the sign bit, we can convert
10029                  this to either an ASHIFT or an ASHIFTRT depending on the
10030                  two counts.
10031
10032                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10033
10034               if (code == ASHIFTRT && first_code == ASHIFT
10035                   && GET_MODE (varop) == shift_mode
10036                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10037                       > first_count))
10038                 {
10039                   varop = XEXP (varop, 0);
10040                   count -= first_count;
10041                   if (count < 0)
10042                     {
10043                       count = -count;
10044                       code = ASHIFT;
10045                     }
10046
10047                   continue;
10048                 }
10049
10050               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10051                  we can only do this if FIRST_CODE is also ASHIFTRT.
10052
10053                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10054                  ASHIFTRT.
10055
10056                  If the mode of this shift is not the mode of the outer shift,
10057                  we can't do this if either shift is a right shift or ROTATE.
10058
10059                  Finally, we can't do any of these if the mode is too wide
10060                  unless the codes are the same.
10061
10062                  Handle the case where the shift codes are the same
10063                  first.  */
10064
10065               if (code == first_code)
10066                 {
10067                   if (GET_MODE (varop) != result_mode
10068                       && (code == ASHIFTRT || code == LSHIFTRT
10069                           || code == ROTATE))
10070                     break;
10071
10072                   count += first_count;
10073                   varop = XEXP (varop, 0);
10074                   continue;
10075                 }
10076
10077               if (code == ASHIFTRT
10078                   || (code == ROTATE && first_code == ASHIFTRT)
10079                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10080                   || (GET_MODE (varop) != result_mode
10081                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10082                           || first_code == ROTATE
10083                           || code == ROTATE)))
10084                 break;
10085
10086               /* To compute the mask to apply after the shift, shift the
10087                  nonzero bits of the inner shift the same way the
10088                  outer shift will.  */
10089
10090               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10091
10092               mask_rtx
10093                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10094                                                    GEN_INT (count));
10095
10096               /* Give up if we can't compute an outer operation to use.  */
10097               if (mask_rtx == 0
10098                   || !CONST_INT_P (mask_rtx)
10099                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10100                                         INTVAL (mask_rtx),
10101                                         result_mode, &complement_p))
10102                 break;
10103
10104               /* If the shifts are in the same direction, we add the
10105                  counts.  Otherwise, we subtract them.  */
10106               if ((code == ASHIFTRT || code == LSHIFTRT)
10107                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10108                 count += first_count;
10109               else
10110                 count -= first_count;
10111
10112               /* If COUNT is positive, the new shift is usually CODE,
10113                  except for the two exceptions below, in which case it is
10114                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10115                  always be used  */
10116               if (count > 0
10117                   && ((first_code == ROTATE && code == ASHIFT)
10118                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10119                 code = first_code;
10120               else if (count < 0)
10121                 code = first_code, count = -count;
10122
10123               varop = XEXP (varop, 0);
10124               continue;
10125             }
10126
10127           /* If we have (A << B << C) for any shift, we can convert this to
10128              (A << C << B).  This wins if A is a constant.  Only try this if
10129              B is not a constant.  */
10130
10131           else if (GET_CODE (varop) == code
10132                    && CONST_INT_P (XEXP (varop, 0))
10133                    && !CONST_INT_P (XEXP (varop, 1)))
10134             {
10135               rtx new_rtx = simplify_const_binary_operation (code, mode,
10136                                                          XEXP (varop, 0),
10137                                                          GEN_INT (count));
10138               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10139               count = 0;
10140               continue;
10141             }
10142           break;
10143
10144         case NOT:
10145           if (VECTOR_MODE_P (mode))
10146             break;
10147
10148           /* Make this fit the case below.  */
10149           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10150           continue;
10151
10152         case IOR:
10153         case AND:
10154         case XOR:
10155           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10156              with C the size of VAROP - 1 and the shift is logical if
10157              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10158              we have an (le X 0) operation.   If we have an arithmetic shift
10159              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10160              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10161
10162           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10163               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10164               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10165               && (code == LSHIFTRT || code == ASHIFTRT)
10166               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10167               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10168             {
10169               count = 0;
10170               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10171                                   const0_rtx);
10172
10173               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10174                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10175
10176               continue;
10177             }
10178
10179           /* If we have (shift (logical)), move the logical to the outside
10180              to allow it to possibly combine with another logical and the
10181              shift to combine with another shift.  This also canonicalizes to
10182              what a ZERO_EXTRACT looks like.  Also, some machines have
10183              (and (shift)) insns.  */
10184
10185           if (CONST_INT_P (XEXP (varop, 1))
10186               /* We can't do this if we have (ashiftrt (xor))  and the
10187                  constant has its sign bit set in shift_mode.  */
10188               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10189                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10190                                               shift_mode))
10191               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10192                                                          XEXP (varop, 1),
10193                                                          GEN_INT (count))) != 0
10194               && CONST_INT_P (new_rtx)
10195               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10196                                   INTVAL (new_rtx), result_mode, &complement_p))
10197             {
10198               varop = XEXP (varop, 0);
10199               continue;
10200             }
10201
10202           /* If we can't do that, try to simplify the shift in each arm of the
10203              logical expression, make a new logical expression, and apply
10204              the inverse distributive law.  This also can't be done
10205              for some (ashiftrt (xor)).  */
10206           if (CONST_INT_P (XEXP (varop, 1))
10207              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10208                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10209                                              shift_mode)))
10210             {
10211               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10212                                               XEXP (varop, 0), count);
10213               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10214                                               XEXP (varop, 1), count);
10215
10216               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10217                                            lhs, rhs);
10218               varop = apply_distributive_law (varop);
10219
10220               count = 0;
10221               continue;
10222             }
10223           break;
10224
10225         case EQ:
10226           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10227              says that the sign bit can be tested, FOO has mode MODE, C is
10228              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10229              that may be nonzero.  */
10230           if (code == LSHIFTRT
10231               && XEXP (varop, 1) == const0_rtx
10232               && GET_MODE (XEXP (varop, 0)) == result_mode
10233               && count == (GET_MODE_PRECISION (result_mode) - 1)
10234               && HWI_COMPUTABLE_MODE_P (result_mode)
10235               && STORE_FLAG_VALUE == -1
10236               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10237               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10238                                   &complement_p))
10239             {
10240               varop = XEXP (varop, 0);
10241               count = 0;
10242               continue;
10243             }
10244           break;
10245
10246         case NEG:
10247           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10248              than the number of bits in the mode is equivalent to A.  */
10249           if (code == LSHIFTRT
10250               && count == (GET_MODE_PRECISION (result_mode) - 1)
10251               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10252             {
10253               varop = XEXP (varop, 0);
10254               count = 0;
10255               continue;
10256             }
10257
10258           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10259              NEG outside to allow shifts to combine.  */
10260           if (code == ASHIFT
10261               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10262                                   &complement_p))
10263             {
10264               varop = XEXP (varop, 0);
10265               continue;
10266             }
10267           break;
10268
10269         case PLUS:
10270           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10271              is one less than the number of bits in the mode is
10272              equivalent to (xor A 1).  */
10273           if (code == LSHIFTRT
10274               && count == (GET_MODE_PRECISION (result_mode) - 1)
10275               && XEXP (varop, 1) == constm1_rtx
10276               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10277               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10278                                   &complement_p))
10279             {
10280               count = 0;
10281               varop = XEXP (varop, 0);
10282               continue;
10283             }
10284
10285           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10286              that might be nonzero in BAR are those being shifted out and those
10287              bits are known zero in FOO, we can replace the PLUS with FOO.
10288              Similarly in the other operand order.  This code occurs when
10289              we are computing the size of a variable-size array.  */
10290
10291           if ((code == ASHIFTRT || code == LSHIFTRT)
10292               && count < HOST_BITS_PER_WIDE_INT
10293               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10294               && (nonzero_bits (XEXP (varop, 1), result_mode)
10295                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10296             {
10297               varop = XEXP (varop, 0);
10298               continue;
10299             }
10300           else if ((code == ASHIFTRT || code == LSHIFTRT)
10301                    && count < HOST_BITS_PER_WIDE_INT
10302                    && HWI_COMPUTABLE_MODE_P (result_mode)
10303                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10304                             >> count)
10305                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10306                             & nonzero_bits (XEXP (varop, 1),
10307                                                  result_mode)))
10308             {
10309               varop = XEXP (varop, 1);
10310               continue;
10311             }
10312
10313           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10314           if (code == ASHIFT
10315               && CONST_INT_P (XEXP (varop, 1))
10316               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10317                                                          XEXP (varop, 1),
10318                                                          GEN_INT (count))) != 0
10319               && CONST_INT_P (new_rtx)
10320               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10321                                   INTVAL (new_rtx), result_mode, &complement_p))
10322             {
10323               varop = XEXP (varop, 0);
10324               continue;
10325             }
10326
10327           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10328              signbit', and attempt to change the PLUS to an XOR and move it to
10329              the outer operation as is done above in the AND/IOR/XOR case
10330              leg for shift(logical). See details in logical handling above
10331              for reasoning in doing so.  */
10332           if (code == LSHIFTRT
10333               && CONST_INT_P (XEXP (varop, 1))
10334               && mode_signbit_p (result_mode, XEXP (varop, 1))
10335               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10336                                                          XEXP (varop, 1),
10337                                                          GEN_INT (count))) != 0
10338               && CONST_INT_P (new_rtx)
10339               && merge_outer_ops (&outer_op, &outer_const, XOR,
10340                                   INTVAL (new_rtx), result_mode, &complement_p))
10341             {
10342               varop = XEXP (varop, 0);
10343               continue;
10344             }
10345
10346           break;
10347
10348         case MINUS:
10349           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10350              with C the size of VAROP - 1 and the shift is logical if
10351              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10352              we have a (gt X 0) operation.  If the shift is arithmetic with
10353              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10354              we have a (neg (gt X 0)) operation.  */
10355
10356           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10357               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10358               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10359               && (code == LSHIFTRT || code == ASHIFTRT)
10360               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10361               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10362               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10363             {
10364               count = 0;
10365               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10366                                   const0_rtx);
10367
10368               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10369                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10370
10371               continue;
10372             }
10373           break;
10374
10375         case TRUNCATE:
10376           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10377              if the truncate does not affect the value.  */
10378           if (code == LSHIFTRT
10379               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10380               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10381               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10382                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10383                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10384             {
10385               rtx varop_inner = XEXP (varop, 0);
10386
10387               varop_inner
10388                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10389                                     XEXP (varop_inner, 0),
10390                                     GEN_INT
10391                                     (count + INTVAL (XEXP (varop_inner, 1))));
10392               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10393               count = 0;
10394               continue;
10395             }
10396           break;
10397
10398         default:
10399           break;
10400         }
10401
10402       break;
10403     }
10404
10405   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10406                                      outer_op, outer_const);
10407
10408   /* We have now finished analyzing the shift.  The result should be
10409      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10410      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10411      to the result of the shift.  OUTER_CONST is the relevant constant,
10412      but we must turn off all bits turned off in the shift.  */
10413
10414   if (outer_op == UNKNOWN
10415       && orig_code == code && orig_count == count
10416       && varop == orig_varop
10417       && shift_mode == GET_MODE (varop))
10418     return NULL_RTX;
10419
10420   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10421   varop = gen_lowpart (shift_mode, varop);
10422   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10423     return NULL_RTX;
10424
10425   /* If we have an outer operation and we just made a shift, it is
10426      possible that we could have simplified the shift were it not
10427      for the outer operation.  So try to do the simplification
10428      recursively.  */
10429
10430   if (outer_op != UNKNOWN)
10431     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10432   else
10433     x = NULL_RTX;
10434
10435   if (x == NULL_RTX)
10436     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10437
10438   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10439      turn off all the bits that the shift would have turned off.  */
10440   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10441     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10442                                 GET_MODE_MASK (result_mode) >> orig_count);
10443
10444   /* Do the remainder of the processing in RESULT_MODE.  */
10445   x = gen_lowpart_or_truncate (result_mode, x);
10446
10447   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10448      operation.  */
10449   if (complement_p)
10450     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10451
10452   if (outer_op != UNKNOWN)
10453     {
10454       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10455           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10456         outer_const = trunc_int_for_mode (outer_const, result_mode);
10457
10458       if (outer_op == AND)
10459         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10460       else if (outer_op == SET)
10461         {
10462           /* This means that we have determined that the result is
10463              equivalent to a constant.  This should be rare.  */
10464           if (!side_effects_p (x))
10465             x = GEN_INT (outer_const);
10466         }
10467       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10468         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10469       else
10470         x = simplify_gen_binary (outer_op, result_mode, x,
10471                                  GEN_INT (outer_const));
10472     }
10473
10474   return x;
10475 }
10476
10477 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10478    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10479    return X or, if it is NULL, synthesize the expression with
10480    simplify_gen_binary.  Otherwise, return a simplified value.
10481
10482    The shift is normally computed in the widest mode we find in VAROP, as
10483    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10484    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10485
10486 static rtx
10487 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10488                       rtx varop, int count)
10489 {
10490   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10491   if (tem)
10492     return tem;
10493
10494   if (!x)
10495     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10496   if (GET_MODE (x) != result_mode)
10497     x = gen_lowpart (result_mode, x);
10498   return x;
10499 }
10500
10501 \f
10502 /* Like recog, but we receive the address of a pointer to a new pattern.
10503    We try to match the rtx that the pointer points to.
10504    If that fails, we may try to modify or replace the pattern,
10505    storing the replacement into the same pointer object.
10506
10507    Modifications include deletion or addition of CLOBBERs.
10508
10509    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10510    the CLOBBERs are placed.
10511
10512    The value is the final insn code from the pattern ultimately matched,
10513    or -1.  */
10514
10515 static int
10516 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10517 {
10518   rtx pat = *pnewpat;
10519   rtx pat_without_clobbers;
10520   int insn_code_number;
10521   int num_clobbers_to_add = 0;
10522   int i;
10523   rtx notes = NULL_RTX;
10524   rtx old_notes, old_pat;
10525   int old_icode;
10526
10527   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10528      we use to indicate that something didn't match.  If we find such a
10529      thing, force rejection.  */
10530   if (GET_CODE (pat) == PARALLEL)
10531     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10532       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10533           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10534         return -1;
10535
10536   old_pat = PATTERN (insn);
10537   old_notes = REG_NOTES (insn);
10538   PATTERN (insn) = pat;
10539   REG_NOTES (insn) = NULL_RTX;
10540
10541   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10542   if (dump_file && (dump_flags & TDF_DETAILS))
10543     {
10544       if (insn_code_number < 0)
10545         fputs ("Failed to match this instruction:\n", dump_file);
10546       else
10547         fputs ("Successfully matched this instruction:\n", dump_file);
10548       print_rtl_single (dump_file, pat);
10549     }
10550
10551   /* If it isn't, there is the possibility that we previously had an insn
10552      that clobbered some register as a side effect, but the combined
10553      insn doesn't need to do that.  So try once more without the clobbers
10554      unless this represents an ASM insn.  */
10555
10556   if (insn_code_number < 0 && ! check_asm_operands (pat)
10557       && GET_CODE (pat) == PARALLEL)
10558     {
10559       int pos;
10560
10561       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10562         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10563           {
10564             if (i != pos)
10565               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10566             pos++;
10567           }
10568
10569       SUBST_INT (XVECLEN (pat, 0), pos);
10570
10571       if (pos == 1)
10572         pat = XVECEXP (pat, 0, 0);
10573
10574       PATTERN (insn) = pat;
10575       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10576       if (dump_file && (dump_flags & TDF_DETAILS))
10577         {
10578           if (insn_code_number < 0)
10579             fputs ("Failed to match this instruction:\n", dump_file);
10580           else
10581             fputs ("Successfully matched this instruction:\n", dump_file);
10582           print_rtl_single (dump_file, pat);
10583         }
10584     }
10585
10586   pat_without_clobbers = pat;
10587
10588   PATTERN (insn) = old_pat;
10589   REG_NOTES (insn) = old_notes;
10590
10591   /* Recognize all noop sets, these will be killed by followup pass.  */
10592   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10593     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10594
10595   /* If we had any clobbers to add, make a new pattern than contains
10596      them.  Then check to make sure that all of them are dead.  */
10597   if (num_clobbers_to_add)
10598     {
10599       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10600                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10601                                                   ? (XVECLEN (pat, 0)
10602                                                      + num_clobbers_to_add)
10603                                                   : num_clobbers_to_add + 1));
10604
10605       if (GET_CODE (pat) == PARALLEL)
10606         for (i = 0; i < XVECLEN (pat, 0); i++)
10607           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10608       else
10609         XVECEXP (newpat, 0, 0) = pat;
10610
10611       add_clobbers (newpat, insn_code_number);
10612
10613       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10614            i < XVECLEN (newpat, 0); i++)
10615         {
10616           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10617               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10618             return -1;
10619           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10620             {
10621               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10622               notes = alloc_reg_note (REG_UNUSED,
10623                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10624             }
10625         }
10626       pat = newpat;
10627     }
10628
10629   if (insn_code_number >= 0
10630       && insn_code_number != NOOP_MOVE_INSN_CODE)
10631     {
10632       old_pat = PATTERN (insn);
10633       old_notes = REG_NOTES (insn);
10634       old_icode = INSN_CODE (insn);
10635       PATTERN (insn) = pat;
10636       REG_NOTES (insn) = notes;
10637
10638       /* Allow targets to reject combined insn.  */
10639       if (!targetm.legitimate_combined_insn (insn))
10640         {
10641           if (dump_file && (dump_flags & TDF_DETAILS))
10642             fputs ("Instruction not appropriate for target.",
10643                    dump_file);
10644
10645           /* Callers expect recog_for_combine to strip
10646              clobbers from the pattern on failure.  */
10647           pat = pat_without_clobbers;
10648           notes = NULL_RTX;
10649
10650           insn_code_number = -1;
10651         }
10652
10653       PATTERN (insn) = old_pat;
10654       REG_NOTES (insn) = old_notes;
10655       INSN_CODE (insn) = old_icode;
10656     }
10657
10658   *pnewpat = pat;
10659   *pnotes = notes;
10660
10661   return insn_code_number;
10662 }
10663 \f
10664 /* Like gen_lowpart_general but for use by combine.  In combine it
10665    is not possible to create any new pseudoregs.  However, it is
10666    safe to create invalid memory addresses, because combine will
10667    try to recognize them and all they will do is make the combine
10668    attempt fail.
10669
10670    If for some reason this cannot do its job, an rtx
10671    (clobber (const_int 0)) is returned.
10672    An insn containing that will not be recognized.  */
10673
10674 static rtx
10675 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10676 {
10677   enum machine_mode imode = GET_MODE (x);
10678   unsigned int osize = GET_MODE_SIZE (omode);
10679   unsigned int isize = GET_MODE_SIZE (imode);
10680   rtx result;
10681
10682   if (omode == imode)
10683     return x;
10684
10685   /* We can only support MODE being wider than a word if X is a
10686      constant integer or has a mode the same size.  */
10687   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10688       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10689     goto fail;
10690
10691   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10692      won't know what to do.  So we will strip off the SUBREG here and
10693      process normally.  */
10694   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10695     {
10696       x = SUBREG_REG (x);
10697
10698       /* For use in case we fall down into the address adjustments
10699          further below, we need to adjust the known mode and size of
10700          x; imode and isize, since we just adjusted x.  */
10701       imode = GET_MODE (x);
10702
10703       if (imode == omode)
10704         return x;
10705
10706       isize = GET_MODE_SIZE (imode);
10707     }
10708
10709   result = gen_lowpart_common (omode, x);
10710
10711   if (result)
10712     return result;
10713
10714   if (MEM_P (x))
10715     {
10716       int offset = 0;
10717
10718       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10719          address.  */
10720       if (MEM_VOLATILE_P (x)
10721           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10722         goto fail;
10723
10724       /* If we want to refer to something bigger than the original memref,
10725          generate a paradoxical subreg instead.  That will force a reload
10726          of the original memref X.  */
10727       if (isize < osize)
10728         return gen_rtx_SUBREG (omode, x, 0);
10729
10730       if (WORDS_BIG_ENDIAN)
10731         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10732
10733       /* Adjust the address so that the address-after-the-data is
10734          unchanged.  */
10735       if (BYTES_BIG_ENDIAN)
10736         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10737
10738       return adjust_address_nv (x, omode, offset);
10739     }
10740
10741   /* If X is a comparison operator, rewrite it in a new mode.  This
10742      probably won't match, but may allow further simplifications.  */
10743   else if (COMPARISON_P (x))
10744     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10745
10746   /* If we couldn't simplify X any other way, just enclose it in a
10747      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10748      include an explicit SUBREG or we may simplify it further in combine.  */
10749   else
10750     {
10751       int offset = 0;
10752       rtx res;
10753
10754       offset = subreg_lowpart_offset (omode, imode);
10755       if (imode == VOIDmode)
10756         {
10757           imode = int_mode_for_mode (omode);
10758           x = gen_lowpart_common (imode, x);
10759           if (x == NULL)
10760             goto fail;
10761         }
10762       res = simplify_gen_subreg (omode, x, imode, offset);
10763       if (res)
10764         return res;
10765     }
10766
10767  fail:
10768   return gen_rtx_CLOBBER (omode, const0_rtx);
10769 }
10770 \f
10771 /* Try to simplify a comparison between OP0 and a constant OP1,
10772    where CODE is the comparison code that will be tested, into a
10773    (CODE OP0 const0_rtx) form.
10774
10775    The result is a possibly different comparison code to use.
10776    *POP1 may be updated.  */
10777
10778 static enum rtx_code
10779 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10780 {
10781   enum machine_mode mode = GET_MODE (op0);
10782   unsigned int mode_width = GET_MODE_PRECISION (mode);
10783   HOST_WIDE_INT const_op = INTVAL (*pop1);
10784
10785   /* Get the constant we are comparing against and turn off all bits
10786      not on in our mode.  */
10787   if (mode != VOIDmode)
10788     const_op = trunc_int_for_mode (const_op, mode);
10789
10790   /* If we are comparing against a constant power of two and the value
10791      being compared can only have that single bit nonzero (e.g., it was
10792      `and'ed with that bit), we can replace this with a comparison
10793      with zero.  */
10794   if (const_op
10795       && (code == EQ || code == NE || code == GE || code == GEU
10796           || code == LT || code == LTU)
10797       && mode_width <= HOST_BITS_PER_WIDE_INT
10798       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10799       && (nonzero_bits (op0, mode)
10800           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10801     {
10802       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10803       const_op = 0;
10804     }
10805
10806   /* Similarly, if we are comparing a value known to be either -1 or
10807      0 with -1, change it to the opposite comparison against zero.  */
10808   if (const_op == -1
10809       && (code == EQ || code == NE || code == GT || code == LE
10810           || code == GEU || code == LTU)
10811       && num_sign_bit_copies (op0, mode) == mode_width)
10812     {
10813       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10814       const_op = 0;
10815     }
10816
10817   /* Do some canonicalizations based on the comparison code.  We prefer
10818      comparisons against zero and then prefer equality comparisons.
10819      If we can reduce the size of a constant, we will do that too.  */
10820   switch (code)
10821     {
10822     case LT:
10823       /* < C is equivalent to <= (C - 1) */
10824       if (const_op > 0)
10825         {
10826           const_op -= 1;
10827           code = LE;
10828           /* ... fall through to LE case below.  */
10829         }
10830       else
10831         break;
10832
10833     case LE:
10834       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10835       if (const_op < 0)
10836         {
10837           const_op += 1;
10838           code = LT;
10839         }
10840
10841       /* If we are doing a <= 0 comparison on a value known to have
10842          a zero sign bit, we can replace this with == 0.  */
10843       else if (const_op == 0
10844                && mode_width <= HOST_BITS_PER_WIDE_INT
10845                && (nonzero_bits (op0, mode)
10846                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10847                == 0)
10848         code = EQ;
10849       break;
10850
10851     case GE:
10852       /* >= C is equivalent to > (C - 1).  */
10853       if (const_op > 0)
10854         {
10855           const_op -= 1;
10856           code = GT;
10857           /* ... fall through to GT below.  */
10858         }
10859       else
10860         break;
10861
10862     case GT:
10863       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10864       if (const_op < 0)
10865         {
10866           const_op += 1;
10867           code = GE;
10868         }
10869
10870       /* If we are doing a > 0 comparison on a value known to have
10871          a zero sign bit, we can replace this with != 0.  */
10872       else if (const_op == 0
10873                && mode_width <= HOST_BITS_PER_WIDE_INT
10874                && (nonzero_bits (op0, mode)
10875                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10876                == 0)
10877         code = NE;
10878       break;
10879
10880     case LTU:
10881       /* < C is equivalent to <= (C - 1).  */
10882       if (const_op > 0)
10883         {
10884           const_op -= 1;
10885           code = LEU;
10886           /* ... fall through ...  */
10887         }
10888       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10889       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10890                && (unsigned HOST_WIDE_INT) const_op
10891                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10892         {
10893           const_op = 0;
10894           code = GE;
10895           break;
10896         }
10897       else
10898         break;
10899
10900     case LEU:
10901       /* unsigned <= 0 is equivalent to == 0 */
10902       if (const_op == 0)
10903         code = EQ;
10904       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10905       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10906                && (unsigned HOST_WIDE_INT) const_op
10907                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10908         {
10909           const_op = 0;
10910           code = GE;
10911         }
10912       break;
10913
10914     case GEU:
10915       /* >= C is equivalent to > (C - 1).  */
10916       if (const_op > 1)
10917         {
10918           const_op -= 1;
10919           code = GTU;
10920           /* ... fall through ...  */
10921         }
10922
10923       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10924       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10925                && (unsigned HOST_WIDE_INT) const_op
10926                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10927         {
10928           const_op = 0;
10929           code = LT;
10930           break;
10931         }
10932       else
10933         break;
10934
10935     case GTU:
10936       /* unsigned > 0 is equivalent to != 0 */
10937       if (const_op == 0)
10938         code = NE;
10939       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10940       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10941                && (unsigned HOST_WIDE_INT) const_op
10942                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10943         {
10944           const_op = 0;
10945           code = LT;
10946         }
10947       break;
10948
10949     default:
10950       break;
10951     }
10952
10953   *pop1 = GEN_INT (const_op);
10954   return code;
10955 }
10956 \f
10957 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10958    comparison code that will be tested.
10959
10960    The result is a possibly different comparison code to use.  *POP0 and
10961    *POP1 may be updated.
10962
10963    It is possible that we might detect that a comparison is either always
10964    true or always false.  However, we do not perform general constant
10965    folding in combine, so this knowledge isn't useful.  Such tautologies
10966    should have been detected earlier.  Hence we ignore all such cases.  */
10967
10968 static enum rtx_code
10969 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10970 {
10971   rtx op0 = *pop0;
10972   rtx op1 = *pop1;
10973   rtx tem, tem1;
10974   int i;
10975   enum machine_mode mode, tmode;
10976
10977   /* Try a few ways of applying the same transformation to both operands.  */
10978   while (1)
10979     {
10980 #ifndef WORD_REGISTER_OPERATIONS
10981       /* The test below this one won't handle SIGN_EXTENDs on these machines,
10982          so check specially.  */
10983       if (code != GTU && code != GEU && code != LTU && code != LEU
10984           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10985           && GET_CODE (XEXP (op0, 0)) == ASHIFT
10986           && GET_CODE (XEXP (op1, 0)) == ASHIFT
10987           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10988           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10989           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10990               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10991           && CONST_INT_P (XEXP (op0, 1))
10992           && XEXP (op0, 1) == XEXP (op1, 1)
10993           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10994           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10995           && (INTVAL (XEXP (op0, 1))
10996               == (GET_MODE_PRECISION (GET_MODE (op0))
10997                   - (GET_MODE_PRECISION
10998                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10999         {
11000           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11001           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11002         }
11003 #endif
11004
11005       /* If both operands are the same constant shift, see if we can ignore the
11006          shift.  We can if the shift is a rotate or if the bits shifted out of
11007          this shift are known to be zero for both inputs and if the type of
11008          comparison is compatible with the shift.  */
11009       if (GET_CODE (op0) == GET_CODE (op1)
11010           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11011           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11012               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11013                   && (code != GT && code != LT && code != GE && code != LE))
11014               || (GET_CODE (op0) == ASHIFTRT
11015                   && (code != GTU && code != LTU
11016                       && code != GEU && code != LEU)))
11017           && CONST_INT_P (XEXP (op0, 1))
11018           && INTVAL (XEXP (op0, 1)) >= 0
11019           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11020           && XEXP (op0, 1) == XEXP (op1, 1))
11021         {
11022           enum machine_mode mode = GET_MODE (op0);
11023           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11024           int shift_count = INTVAL (XEXP (op0, 1));
11025
11026           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11027             mask &= (mask >> shift_count) << shift_count;
11028           else if (GET_CODE (op0) == ASHIFT)
11029             mask = (mask & (mask << shift_count)) >> shift_count;
11030
11031           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11032               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11033             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11034           else
11035             break;
11036         }
11037
11038       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11039          SUBREGs are of the same mode, and, in both cases, the AND would
11040          be redundant if the comparison was done in the narrower mode,
11041          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11042          and the operand's possibly nonzero bits are 0xffffff01; in that case
11043          if we only care about QImode, we don't need the AND).  This case
11044          occurs if the output mode of an scc insn is not SImode and
11045          STORE_FLAG_VALUE == 1 (e.g., the 386).
11046
11047          Similarly, check for a case where the AND's are ZERO_EXTEND
11048          operations from some narrower mode even though a SUBREG is not
11049          present.  */
11050
11051       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11052                && CONST_INT_P (XEXP (op0, 1))
11053                && CONST_INT_P (XEXP (op1, 1)))
11054         {
11055           rtx inner_op0 = XEXP (op0, 0);
11056           rtx inner_op1 = XEXP (op1, 0);
11057           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11058           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11059           int changed = 0;
11060
11061           if (paradoxical_subreg_p (inner_op0)
11062               && GET_CODE (inner_op1) == SUBREG
11063               && (GET_MODE (SUBREG_REG (inner_op0))
11064                   == GET_MODE (SUBREG_REG (inner_op1)))
11065               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11066                   <= HOST_BITS_PER_WIDE_INT)
11067               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11068                                              GET_MODE (SUBREG_REG (inner_op0)))))
11069               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11070                                              GET_MODE (SUBREG_REG (inner_op1))))))
11071             {
11072               op0 = SUBREG_REG (inner_op0);
11073               op1 = SUBREG_REG (inner_op1);
11074
11075               /* The resulting comparison is always unsigned since we masked
11076                  off the original sign bit.  */
11077               code = unsigned_condition (code);
11078
11079               changed = 1;
11080             }
11081
11082           else if (c0 == c1)
11083             for (tmode = GET_CLASS_NARROWEST_MODE
11084                  (GET_MODE_CLASS (GET_MODE (op0)));
11085                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11086               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11087                 {
11088                   op0 = gen_lowpart (tmode, inner_op0);
11089                   op1 = gen_lowpart (tmode, inner_op1);
11090                   code = unsigned_condition (code);
11091                   changed = 1;
11092                   break;
11093                 }
11094
11095           if (! changed)
11096             break;
11097         }
11098
11099       /* If both operands are NOT, we can strip off the outer operation
11100          and adjust the comparison code for swapped operands; similarly for
11101          NEG, except that this must be an equality comparison.  */
11102       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11103                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11104                    && (code == EQ || code == NE)))
11105         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11106
11107       else
11108         break;
11109     }
11110
11111   /* If the first operand is a constant, swap the operands and adjust the
11112      comparison code appropriately, but don't do this if the second operand
11113      is already a constant integer.  */
11114   if (swap_commutative_operands_p (op0, op1))
11115     {
11116       tem = op0, op0 = op1, op1 = tem;
11117       code = swap_condition (code);
11118     }
11119
11120   /* We now enter a loop during which we will try to simplify the comparison.
11121      For the most part, we only are concerned with comparisons with zero,
11122      but some things may really be comparisons with zero but not start
11123      out looking that way.  */
11124
11125   while (CONST_INT_P (op1))
11126     {
11127       enum machine_mode mode = GET_MODE (op0);
11128       unsigned int mode_width = GET_MODE_PRECISION (mode);
11129       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11130       int equality_comparison_p;
11131       int sign_bit_comparison_p;
11132       int unsigned_comparison_p;
11133       HOST_WIDE_INT const_op;
11134
11135       /* We only want to handle integral modes.  This catches VOIDmode,
11136          CCmode, and the floating-point modes.  An exception is that we
11137          can handle VOIDmode if OP0 is a COMPARE or a comparison
11138          operation.  */
11139
11140       if (GET_MODE_CLASS (mode) != MODE_INT
11141           && ! (mode == VOIDmode
11142                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11143         break;
11144
11145       /* Try to simplify the compare to constant, possibly changing the
11146          comparison op, and/or changing op1 to zero.  */
11147       code = simplify_compare_const (code, op0, &op1);
11148       const_op = INTVAL (op1);
11149
11150       /* Compute some predicates to simplify code below.  */
11151
11152       equality_comparison_p = (code == EQ || code == NE);
11153       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11154       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11155                                || code == GEU);
11156
11157       /* If this is a sign bit comparison and we can do arithmetic in
11158          MODE, say that we will only be needing the sign bit of OP0.  */
11159       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11160         op0 = force_to_mode (op0, mode,
11161                              (unsigned HOST_WIDE_INT) 1
11162                              << (GET_MODE_PRECISION (mode) - 1),
11163                              0);
11164
11165       /* Now try cases based on the opcode of OP0.  If none of the cases
11166          does a "continue", we exit this loop immediately after the
11167          switch.  */
11168
11169       switch (GET_CODE (op0))
11170         {
11171         case ZERO_EXTRACT:
11172           /* If we are extracting a single bit from a variable position in
11173              a constant that has only a single bit set and are comparing it
11174              with zero, we can convert this into an equality comparison
11175              between the position and the location of the single bit.  */
11176           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11177              have already reduced the shift count modulo the word size.  */
11178           if (!SHIFT_COUNT_TRUNCATED
11179               && CONST_INT_P (XEXP (op0, 0))
11180               && XEXP (op0, 1) == const1_rtx
11181               && equality_comparison_p && const_op == 0
11182               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11183             {
11184               if (BITS_BIG_ENDIAN)
11185                 i = BITS_PER_WORD - 1 - i;
11186
11187               op0 = XEXP (op0, 2);
11188               op1 = GEN_INT (i);
11189               const_op = i;
11190
11191               /* Result is nonzero iff shift count is equal to I.  */
11192               code = reverse_condition (code);
11193               continue;
11194             }
11195
11196           /* ... fall through ...  */
11197
11198         case SIGN_EXTRACT:
11199           tem = expand_compound_operation (op0);
11200           if (tem != op0)
11201             {
11202               op0 = tem;
11203               continue;
11204             }
11205           break;
11206
11207         case NOT:
11208           /* If testing for equality, we can take the NOT of the constant.  */
11209           if (equality_comparison_p
11210               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11211             {
11212               op0 = XEXP (op0, 0);
11213               op1 = tem;
11214               continue;
11215             }
11216
11217           /* If just looking at the sign bit, reverse the sense of the
11218              comparison.  */
11219           if (sign_bit_comparison_p)
11220             {
11221               op0 = XEXP (op0, 0);
11222               code = (code == GE ? LT : GE);
11223               continue;
11224             }
11225           break;
11226
11227         case NEG:
11228           /* If testing for equality, we can take the NEG of the constant.  */
11229           if (equality_comparison_p
11230               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11231             {
11232               op0 = XEXP (op0, 0);
11233               op1 = tem;
11234               continue;
11235             }
11236
11237           /* The remaining cases only apply to comparisons with zero.  */
11238           if (const_op != 0)
11239             break;
11240
11241           /* When X is ABS or is known positive,
11242              (neg X) is < 0 if and only if X != 0.  */
11243
11244           if (sign_bit_comparison_p
11245               && (GET_CODE (XEXP (op0, 0)) == ABS
11246                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11247                       && (nonzero_bits (XEXP (op0, 0), mode)
11248                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11249                          == 0)))
11250             {
11251               op0 = XEXP (op0, 0);
11252               code = (code == LT ? NE : EQ);
11253               continue;
11254             }
11255
11256           /* If we have NEG of something whose two high-order bits are the
11257              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11258           if (num_sign_bit_copies (op0, mode) >= 2)
11259             {
11260               op0 = XEXP (op0, 0);
11261               code = swap_condition (code);
11262               continue;
11263             }
11264           break;
11265
11266         case ROTATE:
11267           /* If we are testing equality and our count is a constant, we
11268              can perform the inverse operation on our RHS.  */
11269           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11270               && (tem = simplify_binary_operation (ROTATERT, mode,
11271                                                    op1, XEXP (op0, 1))) != 0)
11272             {
11273               op0 = XEXP (op0, 0);
11274               op1 = tem;
11275               continue;
11276             }
11277
11278           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11279              a particular bit.  Convert it to an AND of a constant of that
11280              bit.  This will be converted into a ZERO_EXTRACT.  */
11281           if (const_op == 0 && sign_bit_comparison_p
11282               && CONST_INT_P (XEXP (op0, 1))
11283               && mode_width <= HOST_BITS_PER_WIDE_INT)
11284             {
11285               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11286                                             ((unsigned HOST_WIDE_INT) 1
11287                                              << (mode_width - 1
11288                                                  - INTVAL (XEXP (op0, 1)))));
11289               code = (code == LT ? NE : EQ);
11290               continue;
11291             }
11292
11293           /* Fall through.  */
11294
11295         case ABS:
11296           /* ABS is ignorable inside an equality comparison with zero.  */
11297           if (const_op == 0 && equality_comparison_p)
11298             {
11299               op0 = XEXP (op0, 0);
11300               continue;
11301             }
11302           break;
11303
11304         case SIGN_EXTEND:
11305           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11306              (compare FOO CONST) if CONST fits in FOO's mode and we
11307              are either testing inequality or have an unsigned
11308              comparison with ZERO_EXTEND or a signed comparison with
11309              SIGN_EXTEND.  But don't do it if we don't have a compare
11310              insn of the given mode, since we'd have to revert it
11311              later on, and then we wouldn't know whether to sign- or
11312              zero-extend.  */
11313           mode = GET_MODE (XEXP (op0, 0));
11314           if (GET_MODE_CLASS (mode) == MODE_INT
11315               && ! unsigned_comparison_p
11316               && HWI_COMPUTABLE_MODE_P (mode)
11317               && trunc_int_for_mode (const_op, mode) == const_op
11318               && have_insn_for (COMPARE, mode))
11319             {
11320               op0 = XEXP (op0, 0);
11321               continue;
11322             }
11323           break;
11324
11325         case SUBREG:
11326           /* Check for the case where we are comparing A - C1 with C2, that is
11327
11328                (subreg:MODE (plus (A) (-C1))) op (C2)
11329
11330              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11331              comparison in the wider mode.  One of the following two conditions
11332              must be true in order for this to be valid:
11333
11334                1. The mode extension results in the same bit pattern being added
11335                   on both sides and the comparison is equality or unsigned.  As
11336                   C2 has been truncated to fit in MODE, the pattern can only be
11337                   all 0s or all 1s.
11338
11339                2. The mode extension results in the sign bit being copied on
11340                   each side.
11341
11342              The difficulty here is that we have predicates for A but not for
11343              (A - C1) so we need to check that C1 is within proper bounds so
11344              as to perturbate A as little as possible.  */
11345
11346           if (mode_width <= HOST_BITS_PER_WIDE_INT
11347               && subreg_lowpart_p (op0)
11348               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11349               && GET_CODE (SUBREG_REG (op0)) == PLUS
11350               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11351             {
11352               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11353               rtx a = XEXP (SUBREG_REG (op0), 0);
11354               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11355
11356               if ((c1 > 0
11357                    && (unsigned HOST_WIDE_INT) c1
11358                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11359                    && (equality_comparison_p || unsigned_comparison_p)
11360                    /* (A - C1) zero-extends if it is positive and sign-extends
11361                       if it is negative, C2 both zero- and sign-extends.  */
11362                    && ((0 == (nonzero_bits (a, inner_mode)
11363                               & ~GET_MODE_MASK (mode))
11364                         && const_op >= 0)
11365                        /* (A - C1) sign-extends if it is positive and 1-extends
11366                           if it is negative, C2 both sign- and 1-extends.  */
11367                        || (num_sign_bit_copies (a, inner_mode)
11368                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11369                                              - mode_width)
11370                            && const_op < 0)))
11371                   || ((unsigned HOST_WIDE_INT) c1
11372                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11373                       /* (A - C1) always sign-extends, like C2.  */
11374                       && num_sign_bit_copies (a, inner_mode)
11375                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11376                                            - (mode_width - 1))))
11377                 {
11378                   op0 = SUBREG_REG (op0);
11379                   continue;
11380                 }
11381             }
11382
11383           /* If the inner mode is narrower and we are extracting the low part,
11384              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11385           if (subreg_lowpart_p (op0)
11386               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11387             /* Fall through */ ;
11388           else
11389             break;
11390
11391           /* ... fall through ...  */
11392
11393         case ZERO_EXTEND:
11394           mode = GET_MODE (XEXP (op0, 0));
11395           if (GET_MODE_CLASS (mode) == MODE_INT
11396               && (unsigned_comparison_p || equality_comparison_p)
11397               && HWI_COMPUTABLE_MODE_P (mode)
11398               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11399               && const_op >= 0
11400               && have_insn_for (COMPARE, mode))
11401             {
11402               op0 = XEXP (op0, 0);
11403               continue;
11404             }
11405           break;
11406
11407         case PLUS:
11408           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11409              this for equality comparisons due to pathological cases involving
11410              overflows.  */
11411           if (equality_comparison_p
11412               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11413                                                         op1, XEXP (op0, 1))))
11414             {
11415               op0 = XEXP (op0, 0);
11416               op1 = tem;
11417               continue;
11418             }
11419
11420           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11421           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11422               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11423             {
11424               op0 = XEXP (XEXP (op0, 0), 0);
11425               code = (code == LT ? EQ : NE);
11426               continue;
11427             }
11428           break;
11429
11430         case MINUS:
11431           /* We used to optimize signed comparisons against zero, but that
11432              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11433              arrive here as equality comparisons, or (GEU, LTU) are
11434              optimized away.  No need to special-case them.  */
11435
11436           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11437              (eq B (minus A C)), whichever simplifies.  We can only do
11438              this for equality comparisons due to pathological cases involving
11439              overflows.  */
11440           if (equality_comparison_p
11441               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11442                                                         XEXP (op0, 1), op1)))
11443             {
11444               op0 = XEXP (op0, 0);
11445               op1 = tem;
11446               continue;
11447             }
11448
11449           if (equality_comparison_p
11450               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11451                                                         XEXP (op0, 0), op1)))
11452             {
11453               op0 = XEXP (op0, 1);
11454               op1 = tem;
11455               continue;
11456             }
11457
11458           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11459              of bits in X minus 1, is one iff X > 0.  */
11460           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11461               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11462               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11463               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11464             {
11465               op0 = XEXP (op0, 1);
11466               code = (code == GE ? LE : GT);
11467               continue;
11468             }
11469           break;
11470
11471         case XOR:
11472           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11473              if C is zero or B is a constant.  */
11474           if (equality_comparison_p
11475               && 0 != (tem = simplify_binary_operation (XOR, mode,
11476                                                         XEXP (op0, 1), op1)))
11477             {
11478               op0 = XEXP (op0, 0);
11479               op1 = tem;
11480               continue;
11481             }
11482           break;
11483
11484         case EQ:  case NE:
11485         case UNEQ:  case LTGT:
11486         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11487         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11488         case UNORDERED: case ORDERED:
11489           /* We can't do anything if OP0 is a condition code value, rather
11490              than an actual data value.  */
11491           if (const_op != 0
11492               || CC0_P (XEXP (op0, 0))
11493               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11494             break;
11495
11496           /* Get the two operands being compared.  */
11497           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11498             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11499           else
11500             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11501
11502           /* Check for the cases where we simply want the result of the
11503              earlier test or the opposite of that result.  */
11504           if (code == NE || code == EQ
11505               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11506                   && (code == LT || code == GE)))
11507             {
11508               enum rtx_code new_code;
11509               if (code == LT || code == NE)
11510                 new_code = GET_CODE (op0);
11511               else
11512                 new_code = reversed_comparison_code (op0, NULL);
11513
11514               if (new_code != UNKNOWN)
11515                 {
11516                   code = new_code;
11517                   op0 = tem;
11518                   op1 = tem1;
11519                   continue;
11520                 }
11521             }
11522           break;
11523
11524         case IOR:
11525           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11526              iff X <= 0.  */
11527           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11528               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11529               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11530             {
11531               op0 = XEXP (op0, 1);
11532               code = (code == GE ? GT : LE);
11533               continue;
11534             }
11535           break;
11536
11537         case AND:
11538           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11539              will be converted to a ZERO_EXTRACT later.  */
11540           if (const_op == 0 && equality_comparison_p
11541               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11542               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11543             {
11544               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11545                                       XEXP (XEXP (op0, 0), 1));
11546               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11547               continue;
11548             }
11549
11550           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11551              zero and X is a comparison and C1 and C2 describe only bits set
11552              in STORE_FLAG_VALUE, we can compare with X.  */
11553           if (const_op == 0 && equality_comparison_p
11554               && mode_width <= HOST_BITS_PER_WIDE_INT
11555               && CONST_INT_P (XEXP (op0, 1))
11556               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11557               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11558               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11559               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11560             {
11561               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11562                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11563               if ((~STORE_FLAG_VALUE & mask) == 0
11564                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11565                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11566                           && COMPARISON_P (tem))))
11567                 {
11568                   op0 = XEXP (XEXP (op0, 0), 0);
11569                   continue;
11570                 }
11571             }
11572
11573           /* If we are doing an equality comparison of an AND of a bit equal
11574              to the sign bit, replace this with a LT or GE comparison of
11575              the underlying value.  */
11576           if (equality_comparison_p
11577               && const_op == 0
11578               && CONST_INT_P (XEXP (op0, 1))
11579               && mode_width <= HOST_BITS_PER_WIDE_INT
11580               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11581                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11582             {
11583               op0 = XEXP (op0, 0);
11584               code = (code == EQ ? GE : LT);
11585               continue;
11586             }
11587
11588           /* If this AND operation is really a ZERO_EXTEND from a narrower
11589              mode, the constant fits within that mode, and this is either an
11590              equality or unsigned comparison, try to do this comparison in
11591              the narrower mode.
11592
11593              Note that in:
11594
11595              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11596              -> (ne:DI (reg:SI 4) (const_int 0))
11597
11598              unless TRULY_NOOP_TRUNCATION allows it or the register is
11599              known to hold a value of the required mode the
11600              transformation is invalid.  */
11601           if ((equality_comparison_p || unsigned_comparison_p)
11602               && CONST_INT_P (XEXP (op0, 1))
11603               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11604                                    & GET_MODE_MASK (mode))
11605                                   + 1)) >= 0
11606               && const_op >> i == 0
11607               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11608               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11609                   || (REG_P (XEXP (op0, 0))
11610                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11611             {
11612               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11613               continue;
11614             }
11615
11616           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11617              fits in both M1 and M2 and the SUBREG is either paradoxical
11618              or represents the low part, permute the SUBREG and the AND
11619              and try again.  */
11620           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11621             {
11622               unsigned HOST_WIDE_INT c1;
11623               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11624               /* Require an integral mode, to avoid creating something like
11625                  (AND:SF ...).  */
11626               if (SCALAR_INT_MODE_P (tmode)
11627                   /* It is unsafe to commute the AND into the SUBREG if the
11628                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11629                      not defined.  As originally written the upper bits
11630                      have a defined value due to the AND operation.
11631                      However, if we commute the AND inside the SUBREG then
11632                      they no longer have defined values and the meaning of
11633                      the code has been changed.  */
11634                   && (0
11635 #ifdef WORD_REGISTER_OPERATIONS
11636                       || (mode_width > GET_MODE_PRECISION (tmode)
11637                           && mode_width <= BITS_PER_WORD)
11638 #endif
11639                       || (mode_width <= GET_MODE_PRECISION (tmode)
11640                           && subreg_lowpart_p (XEXP (op0, 0))))
11641                   && CONST_INT_P (XEXP (op0, 1))
11642                   && mode_width <= HOST_BITS_PER_WIDE_INT
11643                   && HWI_COMPUTABLE_MODE_P (tmode)
11644                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11645                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11646                   && c1 != mask
11647                   && c1 != GET_MODE_MASK (tmode))
11648                 {
11649                   op0 = simplify_gen_binary (AND, tmode,
11650                                              SUBREG_REG (XEXP (op0, 0)),
11651                                              gen_int_mode (c1, tmode));
11652                   op0 = gen_lowpart (mode, op0);
11653                   continue;
11654                 }
11655             }
11656
11657           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11658           if (const_op == 0 && equality_comparison_p
11659               && XEXP (op0, 1) == const1_rtx
11660               && GET_CODE (XEXP (op0, 0)) == NOT)
11661             {
11662               op0 = simplify_and_const_int (NULL_RTX, mode,
11663                                             XEXP (XEXP (op0, 0), 0), 1);
11664               code = (code == NE ? EQ : NE);
11665               continue;
11666             }
11667
11668           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11669              (eq (and (lshiftrt X) 1) 0).
11670              Also handle the case where (not X) is expressed using xor.  */
11671           if (const_op == 0 && equality_comparison_p
11672               && XEXP (op0, 1) == const1_rtx
11673               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11674             {
11675               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11676               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11677
11678               if (GET_CODE (shift_op) == NOT
11679                   || (GET_CODE (shift_op) == XOR
11680                       && CONST_INT_P (XEXP (shift_op, 1))
11681                       && CONST_INT_P (shift_count)
11682                       && HWI_COMPUTABLE_MODE_P (mode)
11683                       && (UINTVAL (XEXP (shift_op, 1))
11684                           == (unsigned HOST_WIDE_INT) 1
11685                                << INTVAL (shift_count))))
11686                 {
11687                   op0
11688                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11689                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11690                   code = (code == NE ? EQ : NE);
11691                   continue;
11692                 }
11693             }
11694           break;
11695
11696         case ASHIFT:
11697           /* If we have (compare (ashift FOO N) (const_int C)) and
11698              the high order N bits of FOO (N+1 if an inequality comparison)
11699              are known to be zero, we can do this by comparing FOO with C
11700              shifted right N bits so long as the low-order N bits of C are
11701              zero.  */
11702           if (CONST_INT_P (XEXP (op0, 1))
11703               && INTVAL (XEXP (op0, 1)) >= 0
11704               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11705                   < HOST_BITS_PER_WIDE_INT)
11706               && (((unsigned HOST_WIDE_INT) const_op
11707                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11708                       - 1)) == 0)
11709               && mode_width <= HOST_BITS_PER_WIDE_INT
11710               && (nonzero_bits (XEXP (op0, 0), mode)
11711                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11712                                + ! equality_comparison_p))) == 0)
11713             {
11714               /* We must perform a logical shift, not an arithmetic one,
11715                  as we want the top N bits of C to be zero.  */
11716               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11717
11718               temp >>= INTVAL (XEXP (op0, 1));
11719               op1 = gen_int_mode (temp, mode);
11720               op0 = XEXP (op0, 0);
11721               continue;
11722             }
11723
11724           /* If we are doing a sign bit comparison, it means we are testing
11725              a particular bit.  Convert it to the appropriate AND.  */
11726           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11727               && mode_width <= HOST_BITS_PER_WIDE_INT)
11728             {
11729               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11730                                             ((unsigned HOST_WIDE_INT) 1
11731                                              << (mode_width - 1
11732                                                  - INTVAL (XEXP (op0, 1)))));
11733               code = (code == LT ? NE : EQ);
11734               continue;
11735             }
11736
11737           /* If this an equality comparison with zero and we are shifting
11738              the low bit to the sign bit, we can convert this to an AND of the
11739              low-order bit.  */
11740           if (const_op == 0 && equality_comparison_p
11741               && CONST_INT_P (XEXP (op0, 1))
11742               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11743             {
11744               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11745               continue;
11746             }
11747           break;
11748
11749         case ASHIFTRT:
11750           /* If this is an equality comparison with zero, we can do this
11751              as a logical shift, which might be much simpler.  */
11752           if (equality_comparison_p && const_op == 0
11753               && CONST_INT_P (XEXP (op0, 1)))
11754             {
11755               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11756                                           XEXP (op0, 0),
11757                                           INTVAL (XEXP (op0, 1)));
11758               continue;
11759             }
11760
11761           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11762              do the comparison in a narrower mode.  */
11763           if (! unsigned_comparison_p
11764               && CONST_INT_P (XEXP (op0, 1))
11765               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11766               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11767               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11768                                          MODE_INT, 1)) != BLKmode
11769               && (((unsigned HOST_WIDE_INT) const_op
11770                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11771                   <= GET_MODE_MASK (tmode)))
11772             {
11773               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11774               continue;
11775             }
11776
11777           /* Likewise if OP0 is a PLUS of a sign extension with a
11778              constant, which is usually represented with the PLUS
11779              between the shifts.  */
11780           if (! unsigned_comparison_p
11781               && CONST_INT_P (XEXP (op0, 1))
11782               && GET_CODE (XEXP (op0, 0)) == PLUS
11783               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11784               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11785               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11786               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11787                                          MODE_INT, 1)) != BLKmode
11788               && (((unsigned HOST_WIDE_INT) const_op
11789                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11790                   <= GET_MODE_MASK (tmode)))
11791             {
11792               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11793               rtx add_const = XEXP (XEXP (op0, 0), 1);
11794               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11795                                                    add_const, XEXP (op0, 1));
11796
11797               op0 = simplify_gen_binary (PLUS, tmode,
11798                                          gen_lowpart (tmode, inner),
11799                                          new_const);
11800               continue;
11801             }
11802
11803           /* ... fall through ...  */
11804         case LSHIFTRT:
11805           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11806              the low order N bits of FOO are known to be zero, we can do this
11807              by comparing FOO with C shifted left N bits so long as no
11808              overflow occurs.  Even if the low order N bits of FOO aren't known
11809              to be zero, if the comparison is >= or < we can use the same
11810              optimization and for > or <= by setting all the low
11811              order N bits in the comparison constant.  */
11812           if (CONST_INT_P (XEXP (op0, 1))
11813               && INTVAL (XEXP (op0, 1)) > 0
11814               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11815               && mode_width <= HOST_BITS_PER_WIDE_INT
11816               && (((unsigned HOST_WIDE_INT) const_op
11817                    + (GET_CODE (op0) != LSHIFTRT
11818                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11819                          + 1)
11820                       : 0))
11821                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11822             {
11823               unsigned HOST_WIDE_INT low_bits
11824                 = (nonzero_bits (XEXP (op0, 0), mode)
11825                    & (((unsigned HOST_WIDE_INT) 1
11826                        << INTVAL (XEXP (op0, 1))) - 1));
11827               if (low_bits == 0 || !equality_comparison_p)
11828                 {
11829                   /* If the shift was logical, then we must make the condition
11830                      unsigned.  */
11831                   if (GET_CODE (op0) == LSHIFTRT)
11832                     code = unsigned_condition (code);
11833
11834                   const_op <<= INTVAL (XEXP (op0, 1));
11835                   if (low_bits != 0
11836                       && (code == GT || code == GTU
11837                           || code == LE || code == LEU))
11838                     const_op
11839                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11840                   op1 = GEN_INT (const_op);
11841                   op0 = XEXP (op0, 0);
11842                   continue;
11843                 }
11844             }
11845
11846           /* If we are using this shift to extract just the sign bit, we
11847              can replace this with an LT or GE comparison.  */
11848           if (const_op == 0
11849               && (equality_comparison_p || sign_bit_comparison_p)
11850               && CONST_INT_P (XEXP (op0, 1))
11851               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11852             {
11853               op0 = XEXP (op0, 0);
11854               code = (code == NE || code == GT ? LT : GE);
11855               continue;
11856             }
11857           break;
11858
11859         default:
11860           break;
11861         }
11862
11863       break;
11864     }
11865
11866   /* Now make any compound operations involved in this comparison.  Then,
11867      check for an outmost SUBREG on OP0 that is not doing anything or is
11868      paradoxical.  The latter transformation must only be performed when
11869      it is known that the "extra" bits will be the same in op0 and op1 or
11870      that they don't matter.  There are three cases to consider:
11871
11872      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11873      care bits and we can assume they have any convenient value.  So
11874      making the transformation is safe.
11875
11876      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11877      In this case the upper bits of op0 are undefined.  We should not make
11878      the simplification in that case as we do not know the contents of
11879      those bits.
11880
11881      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11882      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11883      also be sure that they are the same as the upper bits of op1.
11884
11885      We can never remove a SUBREG for a non-equality comparison because
11886      the sign bit is in a different place in the underlying object.  */
11887
11888   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11889   op1 = make_compound_operation (op1, SET);
11890
11891   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11892       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11893       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11894       && (code == NE || code == EQ))
11895     {
11896       if (paradoxical_subreg_p (op0))
11897         {
11898           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11899              implemented.  */
11900           if (REG_P (SUBREG_REG (op0)))
11901             {
11902               op0 = SUBREG_REG (op0);
11903               op1 = gen_lowpart (GET_MODE (op0), op1);
11904             }
11905         }
11906       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11907                 <= HOST_BITS_PER_WIDE_INT)
11908                && (nonzero_bits (SUBREG_REG (op0),
11909                                  GET_MODE (SUBREG_REG (op0)))
11910                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11911         {
11912           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11913
11914           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11915                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11916             op0 = SUBREG_REG (op0), op1 = tem;
11917         }
11918     }
11919
11920   /* We now do the opposite procedure: Some machines don't have compare
11921      insns in all modes.  If OP0's mode is an integer mode smaller than a
11922      word and we can't do a compare in that mode, see if there is a larger
11923      mode for which we can do the compare.  There are a number of cases in
11924      which we can use the wider mode.  */
11925
11926   mode = GET_MODE (op0);
11927   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11928       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11929       && ! have_insn_for (COMPARE, mode))
11930     for (tmode = GET_MODE_WIDER_MODE (mode);
11931          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11932          tmode = GET_MODE_WIDER_MODE (tmode))
11933       if (have_insn_for (COMPARE, tmode))
11934         {
11935           int zero_extended;
11936
11937           /* If this is a test for negative, we can make an explicit
11938              test of the sign bit.  Test this first so we can use
11939              a paradoxical subreg to extend OP0.  */
11940
11941           if (op1 == const0_rtx && (code == LT || code == GE)
11942               && HWI_COMPUTABLE_MODE_P (mode))
11943             {
11944               op0 = simplify_gen_binary (AND, tmode,
11945                                          gen_lowpart (tmode, op0),
11946                                          GEN_INT ((unsigned HOST_WIDE_INT) 1
11947                                                   << (GET_MODE_BITSIZE (mode)
11948                                                       - 1)));
11949               code = (code == LT) ? NE : EQ;
11950               break;
11951             }
11952
11953           /* If the only nonzero bits in OP0 and OP1 are those in the
11954              narrower mode and this is an equality or unsigned comparison,
11955              we can use the wider mode.  Similarly for sign-extended
11956              values, in which case it is true for all comparisons.  */
11957           zero_extended = ((code == EQ || code == NE
11958                             || code == GEU || code == GTU
11959                             || code == LEU || code == LTU)
11960                            && (nonzero_bits (op0, tmode)
11961                                & ~GET_MODE_MASK (mode)) == 0
11962                            && ((CONST_INT_P (op1)
11963                                 || (nonzero_bits (op1, tmode)
11964                                     & ~GET_MODE_MASK (mode)) == 0)));
11965
11966           if (zero_extended
11967               || ((num_sign_bit_copies (op0, tmode)
11968                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11969                                      - GET_MODE_PRECISION (mode)))
11970                   && (num_sign_bit_copies (op1, tmode)
11971                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11972                                         - GET_MODE_PRECISION (mode)))))
11973             {
11974               /* If OP0 is an AND and we don't have an AND in MODE either,
11975                  make a new AND in the proper mode.  */
11976               if (GET_CODE (op0) == AND
11977                   && !have_insn_for (AND, mode))
11978                 op0 = simplify_gen_binary (AND, tmode,
11979                                            gen_lowpart (tmode,
11980                                                         XEXP (op0, 0)),
11981                                            gen_lowpart (tmode,
11982                                                         XEXP (op0, 1)));
11983               else
11984                 {
11985                   if (zero_extended)
11986                     {
11987                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11988                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11989                     }
11990                   else
11991                     {
11992                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11993                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11994                     }
11995                   break;
11996                 }
11997             }
11998         }
11999
12000   /* We may have changed the comparison operands.  Re-canonicalize.  */
12001   if (swap_commutative_operands_p (op0, op1))
12002     {
12003       tem = op0, op0 = op1, op1 = tem;
12004       code = swap_condition (code);
12005     }
12006
12007   /* If this machine only supports a subset of valid comparisons, see if we
12008      can convert an unsupported one into a supported one.  */
12009   target_canonicalize_comparison (&code, &op0, &op1, 0);
12010
12011   *pop0 = op0;
12012   *pop1 = op1;
12013
12014   return code;
12015 }
12016 \f
12017 /* Utility function for record_value_for_reg.  Count number of
12018    rtxs in X.  */
12019 static int
12020 count_rtxs (rtx x)
12021 {
12022   enum rtx_code code = GET_CODE (x);
12023   const char *fmt;
12024   int i, j, ret = 1;
12025
12026   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12027       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12028     {
12029       rtx x0 = XEXP (x, 0);
12030       rtx x1 = XEXP (x, 1);
12031
12032       if (x0 == x1)
12033         return 1 + 2 * count_rtxs (x0);
12034
12035       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12036            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12037           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12038         return 2 + 2 * count_rtxs (x0)
12039                + count_rtxs (x == XEXP (x1, 0)
12040                              ? XEXP (x1, 1) : XEXP (x1, 0));
12041
12042       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12043            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12044           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12045         return 2 + 2 * count_rtxs (x1)
12046                + count_rtxs (x == XEXP (x0, 0)
12047                              ? XEXP (x0, 1) : XEXP (x0, 0));
12048     }
12049
12050   fmt = GET_RTX_FORMAT (code);
12051   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12052     if (fmt[i] == 'e')
12053       ret += count_rtxs (XEXP (x, i));
12054     else if (fmt[i] == 'E')
12055       for (j = 0; j < XVECLEN (x, i); j++)
12056         ret += count_rtxs (XVECEXP (x, i, j));
12057
12058   return ret;
12059 }
12060 \f
12061 /* Utility function for following routine.  Called when X is part of a value
12062    being stored into last_set_value.  Sets last_set_table_tick
12063    for each register mentioned.  Similar to mention_regs in cse.c  */
12064
12065 static void
12066 update_table_tick (rtx x)
12067 {
12068   enum rtx_code code = GET_CODE (x);
12069   const char *fmt = GET_RTX_FORMAT (code);
12070   int i, j;
12071
12072   if (code == REG)
12073     {
12074       unsigned int regno = REGNO (x);
12075       unsigned int endregno = END_REGNO (x);
12076       unsigned int r;
12077
12078       for (r = regno; r < endregno; r++)
12079         {
12080           reg_stat_type *rsp = &reg_stat[r];
12081           rsp->last_set_table_tick = label_tick;
12082         }
12083
12084       return;
12085     }
12086
12087   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12088     if (fmt[i] == 'e')
12089       {
12090         /* Check for identical subexpressions.  If x contains
12091            identical subexpression we only have to traverse one of
12092            them.  */
12093         if (i == 0 && ARITHMETIC_P (x))
12094           {
12095             /* Note that at this point x1 has already been
12096                processed.  */
12097             rtx x0 = XEXP (x, 0);
12098             rtx x1 = XEXP (x, 1);
12099
12100             /* If x0 and x1 are identical then there is no need to
12101                process x0.  */
12102             if (x0 == x1)
12103               break;
12104
12105             /* If x0 is identical to a subexpression of x1 then while
12106                processing x1, x0 has already been processed.  Thus we
12107                are done with x.  */
12108             if (ARITHMETIC_P (x1)
12109                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12110               break;
12111
12112             /* If x1 is identical to a subexpression of x0 then we
12113                still have to process the rest of x0.  */
12114             if (ARITHMETIC_P (x0)
12115                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12116               {
12117                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12118                 break;
12119               }
12120           }
12121
12122         update_table_tick (XEXP (x, i));
12123       }
12124     else if (fmt[i] == 'E')
12125       for (j = 0; j < XVECLEN (x, i); j++)
12126         update_table_tick (XVECEXP (x, i, j));
12127 }
12128
12129 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12130    are saying that the register is clobbered and we no longer know its
12131    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12132    only permitted with VALUE also zero and is used to invalidate the
12133    register.  */
12134
12135 static void
12136 record_value_for_reg (rtx reg, rtx insn, rtx value)
12137 {
12138   unsigned int regno = REGNO (reg);
12139   unsigned int endregno = END_REGNO (reg);
12140   unsigned int i;
12141   reg_stat_type *rsp;
12142
12143   /* If VALUE contains REG and we have a previous value for REG, substitute
12144      the previous value.  */
12145   if (value && insn && reg_overlap_mentioned_p (reg, value))
12146     {
12147       rtx tem;
12148
12149       /* Set things up so get_last_value is allowed to see anything set up to
12150          our insn.  */
12151       subst_low_luid = DF_INSN_LUID (insn);
12152       tem = get_last_value (reg);
12153
12154       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12155          it isn't going to be useful and will take a lot of time to process,
12156          so just use the CLOBBER.  */
12157
12158       if (tem)
12159         {
12160           if (ARITHMETIC_P (tem)
12161               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12162               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12163             tem = XEXP (tem, 0);
12164           else if (count_occurrences (value, reg, 1) >= 2)
12165             {
12166               /* If there are two or more occurrences of REG in VALUE,
12167                  prevent the value from growing too much.  */
12168               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12169                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12170             }
12171
12172           value = replace_rtx (copy_rtx (value), reg, tem);
12173         }
12174     }
12175
12176   /* For each register modified, show we don't know its value, that
12177      we don't know about its bitwise content, that its value has been
12178      updated, and that we don't know the location of the death of the
12179      register.  */
12180   for (i = regno; i < endregno; i++)
12181     {
12182       rsp = &reg_stat[i];
12183
12184       if (insn)
12185         rsp->last_set = insn;
12186
12187       rsp->last_set_value = 0;
12188       rsp->last_set_mode = VOIDmode;
12189       rsp->last_set_nonzero_bits = 0;
12190       rsp->last_set_sign_bit_copies = 0;
12191       rsp->last_death = 0;
12192       rsp->truncated_to_mode = VOIDmode;
12193     }
12194
12195   /* Mark registers that are being referenced in this value.  */
12196   if (value)
12197     update_table_tick (value);
12198
12199   /* Now update the status of each register being set.
12200      If someone is using this register in this block, set this register
12201      to invalid since we will get confused between the two lives in this
12202      basic block.  This makes using this register always invalid.  In cse, we
12203      scan the table to invalidate all entries using this register, but this
12204      is too much work for us.  */
12205
12206   for (i = regno; i < endregno; i++)
12207     {
12208       rsp = &reg_stat[i];
12209       rsp->last_set_label = label_tick;
12210       if (!insn
12211           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12212         rsp->last_set_invalid = 1;
12213       else
12214         rsp->last_set_invalid = 0;
12215     }
12216
12217   /* The value being assigned might refer to X (like in "x++;").  In that
12218      case, we must replace it with (clobber (const_int 0)) to prevent
12219      infinite loops.  */
12220   rsp = &reg_stat[regno];
12221   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12222     {
12223       value = copy_rtx (value);
12224       if (!get_last_value_validate (&value, insn, label_tick, 1))
12225         value = 0;
12226     }
12227
12228   /* For the main register being modified, update the value, the mode, the
12229      nonzero bits, and the number of sign bit copies.  */
12230
12231   rsp->last_set_value = value;
12232
12233   if (value)
12234     {
12235       enum machine_mode mode = GET_MODE (reg);
12236       subst_low_luid = DF_INSN_LUID (insn);
12237       rsp->last_set_mode = mode;
12238       if (GET_MODE_CLASS (mode) == MODE_INT
12239           && HWI_COMPUTABLE_MODE_P (mode))
12240         mode = nonzero_bits_mode;
12241       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12242       rsp->last_set_sign_bit_copies
12243         = num_sign_bit_copies (value, GET_MODE (reg));
12244     }
12245 }
12246
12247 /* Called via note_stores from record_dead_and_set_regs to handle one
12248    SET or CLOBBER in an insn.  DATA is the instruction in which the
12249    set is occurring.  */
12250
12251 static void
12252 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12253 {
12254   rtx record_dead_insn = (rtx) data;
12255
12256   if (GET_CODE (dest) == SUBREG)
12257     dest = SUBREG_REG (dest);
12258
12259   if (!record_dead_insn)
12260     {
12261       if (REG_P (dest))
12262         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12263       return;
12264     }
12265
12266   if (REG_P (dest))
12267     {
12268       /* If we are setting the whole register, we know its value.  Otherwise
12269          show that we don't know the value.  We can handle SUBREG in
12270          some cases.  */
12271       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12272         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12273       else if (GET_CODE (setter) == SET
12274                && GET_CODE (SET_DEST (setter)) == SUBREG
12275                && SUBREG_REG (SET_DEST (setter)) == dest
12276                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12277                && subreg_lowpart_p (SET_DEST (setter)))
12278         record_value_for_reg (dest, record_dead_insn,
12279                               gen_lowpart (GET_MODE (dest),
12280                                                        SET_SRC (setter)));
12281       else
12282         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12283     }
12284   else if (MEM_P (dest)
12285            /* Ignore pushes, they clobber nothing.  */
12286            && ! push_operand (dest, GET_MODE (dest)))
12287     mem_last_set = DF_INSN_LUID (record_dead_insn);
12288 }
12289
12290 /* Update the records of when each REG was most recently set or killed
12291    for the things done by INSN.  This is the last thing done in processing
12292    INSN in the combiner loop.
12293
12294    We update reg_stat[], in particular fields last_set, last_set_value,
12295    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12296    last_death, and also the similar information mem_last_set (which insn
12297    most recently modified memory) and last_call_luid (which insn was the
12298    most recent subroutine call).  */
12299
12300 static void
12301 record_dead_and_set_regs (rtx insn)
12302 {
12303   rtx link;
12304   unsigned int i;
12305
12306   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12307     {
12308       if (REG_NOTE_KIND (link) == REG_DEAD
12309           && REG_P (XEXP (link, 0)))
12310         {
12311           unsigned int regno = REGNO (XEXP (link, 0));
12312           unsigned int endregno = END_REGNO (XEXP (link, 0));
12313
12314           for (i = regno; i < endregno; i++)
12315             {
12316               reg_stat_type *rsp;
12317
12318               rsp = &reg_stat[i];
12319               rsp->last_death = insn;
12320             }
12321         }
12322       else if (REG_NOTE_KIND (link) == REG_INC)
12323         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12324     }
12325
12326   if (CALL_P (insn))
12327     {
12328       hard_reg_set_iterator hrsi;
12329       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12330         {
12331           reg_stat_type *rsp;
12332
12333           rsp = &reg_stat[i];
12334           rsp->last_set_invalid = 1;
12335           rsp->last_set = insn;
12336           rsp->last_set_value = 0;
12337           rsp->last_set_mode = VOIDmode;
12338           rsp->last_set_nonzero_bits = 0;
12339           rsp->last_set_sign_bit_copies = 0;
12340           rsp->last_death = 0;
12341           rsp->truncated_to_mode = VOIDmode;
12342         }
12343
12344       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12345
12346       /* We can't combine into a call pattern.  Remember, though, that
12347          the return value register is set at this LUID.  We could
12348          still replace a register with the return value from the
12349          wrong subroutine call!  */
12350       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12351     }
12352   else
12353     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12354 }
12355
12356 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12357    register present in the SUBREG, so for each such SUBREG go back and
12358    adjust nonzero and sign bit information of the registers that are
12359    known to have some zero/sign bits set.
12360
12361    This is needed because when combine blows the SUBREGs away, the
12362    information on zero/sign bits is lost and further combines can be
12363    missed because of that.  */
12364
12365 static void
12366 record_promoted_value (rtx insn, rtx subreg)
12367 {
12368   struct insn_link *links;
12369   rtx set;
12370   unsigned int regno = REGNO (SUBREG_REG (subreg));
12371   enum machine_mode mode = GET_MODE (subreg);
12372
12373   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12374     return;
12375
12376   for (links = LOG_LINKS (insn); links;)
12377     {
12378       reg_stat_type *rsp;
12379
12380       insn = links->insn;
12381       set = single_set (insn);
12382
12383       if (! set || !REG_P (SET_DEST (set))
12384           || REGNO (SET_DEST (set)) != regno
12385           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12386         {
12387           links = links->next;
12388           continue;
12389         }
12390
12391       rsp = &reg_stat[regno];
12392       if (rsp->last_set == insn)
12393         {
12394           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12395             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12396         }
12397
12398       if (REG_P (SET_SRC (set)))
12399         {
12400           regno = REGNO (SET_SRC (set));
12401           links = LOG_LINKS (insn);
12402         }
12403       else
12404         break;
12405     }
12406 }
12407
12408 /* Check if X, a register, is known to contain a value already
12409    truncated to MODE.  In this case we can use a subreg to refer to
12410    the truncated value even though in the generic case we would need
12411    an explicit truncation.  */
12412
12413 static bool
12414 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12415 {
12416   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12417   enum machine_mode truncated = rsp->truncated_to_mode;
12418
12419   if (truncated == 0
12420       || rsp->truncation_label < label_tick_ebb_start)
12421     return false;
12422   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12423     return true;
12424   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12425     return true;
12426   return false;
12427 }
12428
12429 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12430    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12431    might be able to turn a truncate into a subreg using this information.
12432    Return -1 if traversing *P is complete or 0 otherwise.  */
12433
12434 static int
12435 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12436 {
12437   rtx x = *p;
12438   enum machine_mode truncated_mode;
12439   reg_stat_type *rsp;
12440
12441   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12442     {
12443       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12444       truncated_mode = GET_MODE (x);
12445
12446       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12447         return -1;
12448
12449       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12450         return -1;
12451
12452       x = SUBREG_REG (x);
12453     }
12454   /* ??? For hard-regs we now record everything.  We might be able to
12455      optimize this using last_set_mode.  */
12456   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12457     truncated_mode = GET_MODE (x);
12458   else
12459     return 0;
12460
12461   rsp = &reg_stat[REGNO (x)];
12462   if (rsp->truncated_to_mode == 0
12463       || rsp->truncation_label < label_tick_ebb_start
12464       || (GET_MODE_SIZE (truncated_mode)
12465           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12466     {
12467       rsp->truncated_to_mode = truncated_mode;
12468       rsp->truncation_label = label_tick;
12469     }
12470
12471   return -1;
12472 }
12473
12474 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12475    the modes they are used in.  This can help truning TRUNCATEs into
12476    SUBREGs.  */
12477
12478 static void
12479 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12480 {
12481   for_each_rtx (x, record_truncated_value, NULL);
12482 }
12483
12484 /* Scan X for promoted SUBREGs.  For each one found,
12485    note what it implies to the registers used in it.  */
12486
12487 static void
12488 check_promoted_subreg (rtx insn, rtx x)
12489 {
12490   if (GET_CODE (x) == SUBREG
12491       && SUBREG_PROMOTED_VAR_P (x)
12492       && REG_P (SUBREG_REG (x)))
12493     record_promoted_value (insn, x);
12494   else
12495     {
12496       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12497       int i, j;
12498
12499       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12500         switch (format[i])
12501           {
12502           case 'e':
12503             check_promoted_subreg (insn, XEXP (x, i));
12504             break;
12505           case 'V':
12506           case 'E':
12507             if (XVEC (x, i) != 0)
12508               for (j = 0; j < XVECLEN (x, i); j++)
12509                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12510             break;
12511           }
12512     }
12513 }
12514 \f
12515 /* Verify that all the registers and memory references mentioned in *LOC are
12516    still valid.  *LOC was part of a value set in INSN when label_tick was
12517    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12518    the invalid references with (clobber (const_int 0)) and return 1.  This
12519    replacement is useful because we often can get useful information about
12520    the form of a value (e.g., if it was produced by a shift that always
12521    produces -1 or 0) even though we don't know exactly what registers it
12522    was produced from.  */
12523
12524 static int
12525 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12526 {
12527   rtx x = *loc;
12528   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12529   int len = GET_RTX_LENGTH (GET_CODE (x));
12530   int i, j;
12531
12532   if (REG_P (x))
12533     {
12534       unsigned int regno = REGNO (x);
12535       unsigned int endregno = END_REGNO (x);
12536       unsigned int j;
12537
12538       for (j = regno; j < endregno; j++)
12539         {
12540           reg_stat_type *rsp = &reg_stat[j];
12541           if (rsp->last_set_invalid
12542               /* If this is a pseudo-register that was only set once and not
12543                  live at the beginning of the function, it is always valid.  */
12544               || (! (regno >= FIRST_PSEUDO_REGISTER
12545                      && REG_N_SETS (regno) == 1
12546                      && (!REGNO_REG_SET_P
12547                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12548                   && rsp->last_set_label > tick))
12549           {
12550             if (replace)
12551               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12552             return replace;
12553           }
12554         }
12555
12556       return 1;
12557     }
12558   /* If this is a memory reference, make sure that there were no stores after
12559      it that might have clobbered the value.  We don't have alias info, so we
12560      assume any store invalidates it.  Moreover, we only have local UIDs, so
12561      we also assume that there were stores in the intervening basic blocks.  */
12562   else if (MEM_P (x) && !MEM_READONLY_P (x)
12563            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12564     {
12565       if (replace)
12566         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12567       return replace;
12568     }
12569
12570   for (i = 0; i < len; i++)
12571     {
12572       if (fmt[i] == 'e')
12573         {
12574           /* Check for identical subexpressions.  If x contains
12575              identical subexpression we only have to traverse one of
12576              them.  */
12577           if (i == 1 && ARITHMETIC_P (x))
12578             {
12579               /* Note that at this point x0 has already been checked
12580                  and found valid.  */
12581               rtx x0 = XEXP (x, 0);
12582               rtx x1 = XEXP (x, 1);
12583
12584               /* If x0 and x1 are identical then x is also valid.  */
12585               if (x0 == x1)
12586                 return 1;
12587
12588               /* If x1 is identical to a subexpression of x0 then
12589                  while checking x0, x1 has already been checked.  Thus
12590                  it is valid and so as x.  */
12591               if (ARITHMETIC_P (x0)
12592                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12593                 return 1;
12594
12595               /* If x0 is identical to a subexpression of x1 then x is
12596                  valid iff the rest of x1 is valid.  */
12597               if (ARITHMETIC_P (x1)
12598                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12599                 return
12600                   get_last_value_validate (&XEXP (x1,
12601                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12602                                            insn, tick, replace);
12603             }
12604
12605           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12606                                        replace) == 0)
12607             return 0;
12608         }
12609       else if (fmt[i] == 'E')
12610         for (j = 0; j < XVECLEN (x, i); j++)
12611           if (get_last_value_validate (&XVECEXP (x, i, j),
12612                                        insn, tick, replace) == 0)
12613             return 0;
12614     }
12615
12616   /* If we haven't found a reason for it to be invalid, it is valid.  */
12617   return 1;
12618 }
12619
12620 /* Get the last value assigned to X, if known.  Some registers
12621    in the value may be replaced with (clobber (const_int 0)) if their value
12622    is known longer known reliably.  */
12623
12624 static rtx
12625 get_last_value (const_rtx x)
12626 {
12627   unsigned int regno;
12628   rtx value;
12629   reg_stat_type *rsp;
12630
12631   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12632      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12633      we cannot predict what values the "extra" bits might have.  */
12634   if (GET_CODE (x) == SUBREG
12635       && subreg_lowpart_p (x)
12636       && !paradoxical_subreg_p (x)
12637       && (value = get_last_value (SUBREG_REG (x))) != 0)
12638     return gen_lowpart (GET_MODE (x), value);
12639
12640   if (!REG_P (x))
12641     return 0;
12642
12643   regno = REGNO (x);
12644   rsp = &reg_stat[regno];
12645   value = rsp->last_set_value;
12646
12647   /* If we don't have a value, or if it isn't for this basic block and
12648      it's either a hard register, set more than once, or it's a live
12649      at the beginning of the function, return 0.
12650
12651      Because if it's not live at the beginning of the function then the reg
12652      is always set before being used (is never used without being set).
12653      And, if it's set only once, and it's always set before use, then all
12654      uses must have the same last value, even if it's not from this basic
12655      block.  */
12656
12657   if (value == 0
12658       || (rsp->last_set_label < label_tick_ebb_start
12659           && (regno < FIRST_PSEUDO_REGISTER
12660               || REG_N_SETS (regno) != 1
12661               || REGNO_REG_SET_P
12662                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12663     return 0;
12664
12665   /* If the value was set in a later insn than the ones we are processing,
12666      we can't use it even if the register was only set once.  */
12667   if (rsp->last_set_label == label_tick
12668       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12669     return 0;
12670
12671   /* If the value has all its registers valid, return it.  */
12672   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12673     return value;
12674
12675   /* Otherwise, make a copy and replace any invalid register with
12676      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12677
12678   value = copy_rtx (value);
12679   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12680     return value;
12681
12682   return 0;
12683 }
12684 \f
12685 /* Return nonzero if expression X refers to a REG or to memory
12686    that is set in an instruction more recent than FROM_LUID.  */
12687
12688 static int
12689 use_crosses_set_p (const_rtx x, int from_luid)
12690 {
12691   const char *fmt;
12692   int i;
12693   enum rtx_code code = GET_CODE (x);
12694
12695   if (code == REG)
12696     {
12697       unsigned int regno = REGNO (x);
12698       unsigned endreg = END_REGNO (x);
12699
12700 #ifdef PUSH_ROUNDING
12701       /* Don't allow uses of the stack pointer to be moved,
12702          because we don't know whether the move crosses a push insn.  */
12703       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12704         return 1;
12705 #endif
12706       for (; regno < endreg; regno++)
12707         {
12708           reg_stat_type *rsp = &reg_stat[regno];
12709           if (rsp->last_set
12710               && rsp->last_set_label == label_tick
12711               && DF_INSN_LUID (rsp->last_set) > from_luid)
12712             return 1;
12713         }
12714       return 0;
12715     }
12716
12717   if (code == MEM && mem_last_set > from_luid)
12718     return 1;
12719
12720   fmt = GET_RTX_FORMAT (code);
12721
12722   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12723     {
12724       if (fmt[i] == 'E')
12725         {
12726           int j;
12727           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12728             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12729               return 1;
12730         }
12731       else if (fmt[i] == 'e'
12732                && use_crosses_set_p (XEXP (x, i), from_luid))
12733         return 1;
12734     }
12735   return 0;
12736 }
12737 \f
12738 /* Define three variables used for communication between the following
12739    routines.  */
12740
12741 static unsigned int reg_dead_regno, reg_dead_endregno;
12742 static int reg_dead_flag;
12743
12744 /* Function called via note_stores from reg_dead_at_p.
12745
12746    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12747    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12748
12749 static void
12750 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12751 {
12752   unsigned int regno, endregno;
12753
12754   if (!REG_P (dest))
12755     return;
12756
12757   regno = REGNO (dest);
12758   endregno = END_REGNO (dest);
12759   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12760     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12761 }
12762
12763 /* Return nonzero if REG is known to be dead at INSN.
12764
12765    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12766    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12767    live.  Otherwise, see if it is live or dead at the start of the basic
12768    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12769    must be assumed to be always live.  */
12770
12771 static int
12772 reg_dead_at_p (rtx reg, rtx insn)
12773 {
12774   basic_block block;
12775   unsigned int i;
12776
12777   /* Set variables for reg_dead_at_p_1.  */
12778   reg_dead_regno = REGNO (reg);
12779   reg_dead_endregno = END_REGNO (reg);
12780
12781   reg_dead_flag = 0;
12782
12783   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12784      we allow the machine description to decide whether use-and-clobber
12785      patterns are OK.  */
12786   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12787     {
12788       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12789         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12790           return 0;
12791     }
12792
12793   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12794      beginning of basic block.  */
12795   block = BLOCK_FOR_INSN (insn);
12796   for (;;)
12797     {
12798       if (INSN_P (insn))
12799         {
12800           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12801           if (reg_dead_flag)
12802             return reg_dead_flag == 1 ? 1 : 0;
12803
12804           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12805             return 1;
12806         }
12807
12808       if (insn == BB_HEAD (block))
12809         break;
12810
12811       insn = PREV_INSN (insn);
12812     }
12813
12814   /* Look at live-in sets for the basic block that we were in.  */
12815   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12816     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12817       return 0;
12818
12819   return 1;
12820 }
12821 \f
12822 /* Note hard registers in X that are used.  */
12823
12824 static void
12825 mark_used_regs_combine (rtx x)
12826 {
12827   RTX_CODE code = GET_CODE (x);
12828   unsigned int regno;
12829   int i;
12830
12831   switch (code)
12832     {
12833     case LABEL_REF:
12834     case SYMBOL_REF:
12835     case CONST:
12836     CASE_CONST_ANY:
12837     case PC:
12838     case ADDR_VEC:
12839     case ADDR_DIFF_VEC:
12840     case ASM_INPUT:
12841 #ifdef HAVE_cc0
12842     /* CC0 must die in the insn after it is set, so we don't need to take
12843        special note of it here.  */
12844     case CC0:
12845 #endif
12846       return;
12847
12848     case CLOBBER:
12849       /* If we are clobbering a MEM, mark any hard registers inside the
12850          address as used.  */
12851       if (MEM_P (XEXP (x, 0)))
12852         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12853       return;
12854
12855     case REG:
12856       regno = REGNO (x);
12857       /* A hard reg in a wide mode may really be multiple registers.
12858          If so, mark all of them just like the first.  */
12859       if (regno < FIRST_PSEUDO_REGISTER)
12860         {
12861           /* None of this applies to the stack, frame or arg pointers.  */
12862           if (regno == STACK_POINTER_REGNUM
12863 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12864               || regno == HARD_FRAME_POINTER_REGNUM
12865 #endif
12866 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12867               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12868 #endif
12869               || regno == FRAME_POINTER_REGNUM)
12870             return;
12871
12872           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12873         }
12874       return;
12875
12876     case SET:
12877       {
12878         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12879            the address.  */
12880         rtx testreg = SET_DEST (x);
12881
12882         while (GET_CODE (testreg) == SUBREG
12883                || GET_CODE (testreg) == ZERO_EXTRACT
12884                || GET_CODE (testreg) == STRICT_LOW_PART)
12885           testreg = XEXP (testreg, 0);
12886
12887         if (MEM_P (testreg))
12888           mark_used_regs_combine (XEXP (testreg, 0));
12889
12890         mark_used_regs_combine (SET_SRC (x));
12891       }
12892       return;
12893
12894     default:
12895       break;
12896     }
12897
12898   /* Recursively scan the operands of this expression.  */
12899
12900   {
12901     const char *fmt = GET_RTX_FORMAT (code);
12902
12903     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12904       {
12905         if (fmt[i] == 'e')
12906           mark_used_regs_combine (XEXP (x, i));
12907         else if (fmt[i] == 'E')
12908           {
12909             int j;
12910
12911             for (j = 0; j < XVECLEN (x, i); j++)
12912               mark_used_regs_combine (XVECEXP (x, i, j));
12913           }
12914       }
12915   }
12916 }
12917 \f
12918 /* Remove register number REGNO from the dead registers list of INSN.
12919
12920    Return the note used to record the death, if there was one.  */
12921
12922 rtx
12923 remove_death (unsigned int regno, rtx insn)
12924 {
12925   rtx note = find_regno_note (insn, REG_DEAD, regno);
12926
12927   if (note)
12928     remove_note (insn, note);
12929
12930   return note;
12931 }
12932
12933 /* For each register (hardware or pseudo) used within expression X, if its
12934    death is in an instruction with luid between FROM_LUID (inclusive) and
12935    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12936    list headed by PNOTES.
12937
12938    That said, don't move registers killed by maybe_kill_insn.
12939
12940    This is done when X is being merged by combination into TO_INSN.  These
12941    notes will then be distributed as needed.  */
12942
12943 static void
12944 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12945              rtx *pnotes)
12946 {
12947   const char *fmt;
12948   int len, i;
12949   enum rtx_code code = GET_CODE (x);
12950
12951   if (code == REG)
12952     {
12953       unsigned int regno = REGNO (x);
12954       rtx where_dead = reg_stat[regno].last_death;
12955
12956       /* Don't move the register if it gets killed in between from and to.  */
12957       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12958           && ! reg_referenced_p (x, maybe_kill_insn))
12959         return;
12960
12961       if (where_dead
12962           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12963           && DF_INSN_LUID (where_dead) >= from_luid
12964           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12965         {
12966           rtx note = remove_death (regno, where_dead);
12967
12968           /* It is possible for the call above to return 0.  This can occur
12969              when last_death points to I2 or I1 that we combined with.
12970              In that case make a new note.
12971
12972              We must also check for the case where X is a hard register
12973              and NOTE is a death note for a range of hard registers
12974              including X.  In that case, we must put REG_DEAD notes for
12975              the remaining registers in place of NOTE.  */
12976
12977           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12978               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12979                   > GET_MODE_SIZE (GET_MODE (x))))
12980             {
12981               unsigned int deadregno = REGNO (XEXP (note, 0));
12982               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12983               unsigned int ourend = END_HARD_REGNO (x);
12984               unsigned int i;
12985
12986               for (i = deadregno; i < deadend; i++)
12987                 if (i < regno || i >= ourend)
12988                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12989             }
12990
12991           /* If we didn't find any note, or if we found a REG_DEAD note that
12992              covers only part of the given reg, and we have a multi-reg hard
12993              register, then to be safe we must check for REG_DEAD notes
12994              for each register other than the first.  They could have
12995              their own REG_DEAD notes lying around.  */
12996           else if ((note == 0
12997                     || (note != 0
12998                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12999                             < GET_MODE_SIZE (GET_MODE (x)))))
13000                    && regno < FIRST_PSEUDO_REGISTER
13001                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13002             {
13003               unsigned int ourend = END_HARD_REGNO (x);
13004               unsigned int i, offset;
13005               rtx oldnotes = 0;
13006
13007               if (note)
13008                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13009               else
13010                 offset = 1;
13011
13012               for (i = regno + offset; i < ourend; i++)
13013                 move_deaths (regno_reg_rtx[i],
13014                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13015             }
13016
13017           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13018             {
13019               XEXP (note, 1) = *pnotes;
13020               *pnotes = note;
13021             }
13022           else
13023             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13024         }
13025
13026       return;
13027     }
13028
13029   else if (GET_CODE (x) == SET)
13030     {
13031       rtx dest = SET_DEST (x);
13032
13033       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13034
13035       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13036          that accesses one word of a multi-word item, some
13037          piece of everything register in the expression is used by
13038          this insn, so remove any old death.  */
13039       /* ??? So why do we test for equality of the sizes?  */
13040
13041       if (GET_CODE (dest) == ZERO_EXTRACT
13042           || GET_CODE (dest) == STRICT_LOW_PART
13043           || (GET_CODE (dest) == SUBREG
13044               && (((GET_MODE_SIZE (GET_MODE (dest))
13045                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13046                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13047                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13048         {
13049           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13050           return;
13051         }
13052
13053       /* If this is some other SUBREG, we know it replaces the entire
13054          value, so use that as the destination.  */
13055       if (GET_CODE (dest) == SUBREG)
13056         dest = SUBREG_REG (dest);
13057
13058       /* If this is a MEM, adjust deaths of anything used in the address.
13059          For a REG (the only other possibility), the entire value is
13060          being replaced so the old value is not used in this insn.  */
13061
13062       if (MEM_P (dest))
13063         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13064                      to_insn, pnotes);
13065       return;
13066     }
13067
13068   else if (GET_CODE (x) == CLOBBER)
13069     return;
13070
13071   len = GET_RTX_LENGTH (code);
13072   fmt = GET_RTX_FORMAT (code);
13073
13074   for (i = 0; i < len; i++)
13075     {
13076       if (fmt[i] == 'E')
13077         {
13078           int j;
13079           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13080             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13081                          to_insn, pnotes);
13082         }
13083       else if (fmt[i] == 'e')
13084         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13085     }
13086 }
13087 \f
13088 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13089    pattern of an insn.  X must be a REG.  */
13090
13091 static int
13092 reg_bitfield_target_p (rtx x, rtx body)
13093 {
13094   int i;
13095
13096   if (GET_CODE (body) == SET)
13097     {
13098       rtx dest = SET_DEST (body);
13099       rtx target;
13100       unsigned int regno, tregno, endregno, endtregno;
13101
13102       if (GET_CODE (dest) == ZERO_EXTRACT)
13103         target = XEXP (dest, 0);
13104       else if (GET_CODE (dest) == STRICT_LOW_PART)
13105         target = SUBREG_REG (XEXP (dest, 0));
13106       else
13107         return 0;
13108
13109       if (GET_CODE (target) == SUBREG)
13110         target = SUBREG_REG (target);
13111
13112       if (!REG_P (target))
13113         return 0;
13114
13115       tregno = REGNO (target), regno = REGNO (x);
13116       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13117         return target == x;
13118
13119       endtregno = end_hard_regno (GET_MODE (target), tregno);
13120       endregno = end_hard_regno (GET_MODE (x), regno);
13121
13122       return endregno > tregno && regno < endtregno;
13123     }
13124
13125   else if (GET_CODE (body) == PARALLEL)
13126     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13127       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13128         return 1;
13129
13130   return 0;
13131 }
13132 \f
13133 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13134    as appropriate.  I3 and I2 are the insns resulting from the combination
13135    insns including FROM (I2 may be zero).
13136
13137    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13138    not need REG_DEAD notes because they are being substituted for.  This
13139    saves searching in the most common cases.
13140
13141    Each note in the list is either ignored or placed on some insns, depending
13142    on the type of note.  */
13143
13144 static void
13145 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13146                   rtx elim_i1, rtx elim_i0)
13147 {
13148   rtx note, next_note;
13149   rtx tem;
13150
13151   for (note = notes; note; note = next_note)
13152     {
13153       rtx place = 0, place2 = 0;
13154
13155       next_note = XEXP (note, 1);
13156       switch (REG_NOTE_KIND (note))
13157         {
13158         case REG_BR_PROB:
13159         case REG_BR_PRED:
13160           /* Doesn't matter much where we put this, as long as it's somewhere.
13161              It is preferable to keep these notes on branches, which is most
13162              likely to be i3.  */
13163           place = i3;
13164           break;
13165
13166         case REG_NON_LOCAL_GOTO:
13167           if (JUMP_P (i3))
13168             place = i3;
13169           else
13170             {
13171               gcc_assert (i2 && JUMP_P (i2));
13172               place = i2;
13173             }
13174           break;
13175
13176         case REG_EH_REGION:
13177           /* These notes must remain with the call or trapping instruction.  */
13178           if (CALL_P (i3))
13179             place = i3;
13180           else if (i2 && CALL_P (i2))
13181             place = i2;
13182           else
13183             {
13184               gcc_assert (cfun->can_throw_non_call_exceptions);
13185               if (may_trap_p (i3))
13186                 place = i3;
13187               else if (i2 && may_trap_p (i2))
13188                 place = i2;
13189               /* ??? Otherwise assume we've combined things such that we
13190                  can now prove that the instructions can't trap.  Drop the
13191                  note in this case.  */
13192             }
13193           break;
13194
13195         case REG_ARGS_SIZE:
13196           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13197              entire adjustment.  Assert i3 contains at least some adjust.  */
13198           if (!noop_move_p (i3))
13199             {
13200               int old_size, args_size = INTVAL (XEXP (note, 0));
13201               /* fixup_args_size_notes looks at REG_NORETURN note,
13202                  so ensure the note is placed there first.  */
13203               if (CALL_P (i3))
13204                 {
13205                   rtx *np;
13206                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13207                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13208                       {
13209                         rtx n = *np;
13210                         *np = XEXP (n, 1);
13211                         XEXP (n, 1) = REG_NOTES (i3);
13212                         REG_NOTES (i3) = n;
13213                         break;
13214                       }
13215                 }
13216               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13217               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13218                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13219               gcc_assert (old_size != args_size
13220                           || (CALL_P (i3)
13221                               && !ACCUMULATE_OUTGOING_ARGS
13222                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13223             }
13224           break;
13225
13226         case REG_NORETURN:
13227         case REG_SETJMP:
13228         case REG_TM:
13229           /* These notes must remain with the call.  It should not be
13230              possible for both I2 and I3 to be a call.  */
13231           if (CALL_P (i3))
13232             place = i3;
13233           else
13234             {
13235               gcc_assert (i2 && CALL_P (i2));
13236               place = i2;
13237             }
13238           break;
13239
13240         case REG_UNUSED:
13241           /* Any clobbers for i3 may still exist, and so we must process
13242              REG_UNUSED notes from that insn.
13243
13244              Any clobbers from i2 or i1 can only exist if they were added by
13245              recog_for_combine.  In that case, recog_for_combine created the
13246              necessary REG_UNUSED notes.  Trying to keep any original
13247              REG_UNUSED notes from these insns can cause incorrect output
13248              if it is for the same register as the original i3 dest.
13249              In that case, we will notice that the register is set in i3,
13250              and then add a REG_UNUSED note for the destination of i3, which
13251              is wrong.  However, it is possible to have REG_UNUSED notes from
13252              i2 or i1 for register which were both used and clobbered, so
13253              we keep notes from i2 or i1 if they will turn into REG_DEAD
13254              notes.  */
13255
13256           /* If this register is set or clobbered in I3, put the note there
13257              unless there is one already.  */
13258           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13259             {
13260               if (from_insn != i3)
13261                 break;
13262
13263               if (! (REG_P (XEXP (note, 0))
13264                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13265                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13266                 place = i3;
13267             }
13268           /* Otherwise, if this register is used by I3, then this register
13269              now dies here, so we must put a REG_DEAD note here unless there
13270              is one already.  */
13271           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13272                    && ! (REG_P (XEXP (note, 0))
13273                          ? find_regno_note (i3, REG_DEAD,
13274                                             REGNO (XEXP (note, 0)))
13275                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13276             {
13277               PUT_REG_NOTE_KIND (note, REG_DEAD);
13278               place = i3;
13279             }
13280           break;
13281
13282         case REG_EQUAL:
13283         case REG_EQUIV:
13284         case REG_NOALIAS:
13285           /* These notes say something about results of an insn.  We can
13286              only support them if they used to be on I3 in which case they
13287              remain on I3.  Otherwise they are ignored.
13288
13289              If the note refers to an expression that is not a constant, we
13290              must also ignore the note since we cannot tell whether the
13291              equivalence is still true.  It might be possible to do
13292              slightly better than this (we only have a problem if I2DEST
13293              or I1DEST is present in the expression), but it doesn't
13294              seem worth the trouble.  */
13295
13296           if (from_insn == i3
13297               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13298             place = i3;
13299           break;
13300
13301         case REG_INC:
13302           /* These notes say something about how a register is used.  They must
13303              be present on any use of the register in I2 or I3.  */
13304           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13305             place = i3;
13306
13307           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13308             {
13309               if (place)
13310                 place2 = i2;
13311               else
13312                 place = i2;
13313             }
13314           break;
13315
13316         case REG_LABEL_TARGET:
13317         case REG_LABEL_OPERAND:
13318           /* This can show up in several ways -- either directly in the
13319              pattern, or hidden off in the constant pool with (or without?)
13320              a REG_EQUAL note.  */
13321           /* ??? Ignore the without-reg_equal-note problem for now.  */
13322           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13323               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13324                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13325                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13326             place = i3;
13327
13328           if (i2
13329               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13330                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13331                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13332                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13333             {
13334               if (place)
13335                 place2 = i2;
13336               else
13337                 place = i2;
13338             }
13339
13340           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13341              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13342              there.  */
13343           if (place && JUMP_P (place)
13344               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13345               && (JUMP_LABEL (place) == NULL
13346                   || JUMP_LABEL (place) == XEXP (note, 0)))
13347             {
13348               rtx label = JUMP_LABEL (place);
13349
13350               if (!label)
13351                 JUMP_LABEL (place) = XEXP (note, 0);
13352               else if (LABEL_P (label))
13353                 LABEL_NUSES (label)--;
13354             }
13355
13356           if (place2 && JUMP_P (place2)
13357               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13358               && (JUMP_LABEL (place2) == NULL
13359                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13360             {
13361               rtx label = JUMP_LABEL (place2);
13362
13363               if (!label)
13364                 JUMP_LABEL (place2) = XEXP (note, 0);
13365               else if (LABEL_P (label))
13366                 LABEL_NUSES (label)--;
13367               place2 = 0;
13368             }
13369           break;
13370
13371         case REG_NONNEG:
13372           /* This note says something about the value of a register prior
13373              to the execution of an insn.  It is too much trouble to see
13374              if the note is still correct in all situations.  It is better
13375              to simply delete it.  */
13376           break;
13377
13378         case REG_DEAD:
13379           /* If we replaced the right hand side of FROM_INSN with a
13380              REG_EQUAL note, the original use of the dying register
13381              will not have been combined into I3 and I2.  In such cases,
13382              FROM_INSN is guaranteed to be the first of the combined
13383              instructions, so we simply need to search back before
13384              FROM_INSN for the previous use or set of this register,
13385              then alter the notes there appropriately.
13386
13387              If the register is used as an input in I3, it dies there.
13388              Similarly for I2, if it is nonzero and adjacent to I3.
13389
13390              If the register is not used as an input in either I3 or I2
13391              and it is not one of the registers we were supposed to eliminate,
13392              there are two possibilities.  We might have a non-adjacent I2
13393              or we might have somehow eliminated an additional register
13394              from a computation.  For example, we might have had A & B where
13395              we discover that B will always be zero.  In this case we will
13396              eliminate the reference to A.
13397
13398              In both cases, we must search to see if we can find a previous
13399              use of A and put the death note there.  */
13400
13401           if (from_insn
13402               && from_insn == i2mod
13403               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13404             tem = from_insn;
13405           else
13406             {
13407               if (from_insn
13408                   && CALL_P (from_insn)
13409                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13410                 place = from_insn;
13411               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13412                 place = i3;
13413               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13414                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13415                 place = i2;
13416               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13417                         && !(i2mod
13418                              && reg_overlap_mentioned_p (XEXP (note, 0),
13419                                                          i2mod_old_rhs)))
13420                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13421                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13422                 break;
13423               tem = i3;
13424             }
13425
13426           if (place == 0)
13427             {
13428               basic_block bb = this_basic_block;
13429
13430               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13431                 {
13432                   if (!NONDEBUG_INSN_P (tem))
13433                     {
13434                       if (tem == BB_HEAD (bb))
13435                         break;
13436                       continue;
13437                     }
13438
13439                   /* If the register is being set at TEM, see if that is all
13440                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13441                      into a REG_UNUSED note instead. Don't delete sets to
13442                      global register vars.  */
13443                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13444                        || !global_regs[REGNO (XEXP (note, 0))])
13445                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13446                     {
13447                       rtx set = single_set (tem);
13448                       rtx inner_dest = 0;
13449 #ifdef HAVE_cc0
13450                       rtx cc0_setter = NULL_RTX;
13451 #endif
13452
13453                       if (set != 0)
13454                         for (inner_dest = SET_DEST (set);
13455                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13456                               || GET_CODE (inner_dest) == SUBREG
13457                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13458                              inner_dest = XEXP (inner_dest, 0))
13459                           ;
13460
13461                       /* Verify that it was the set, and not a clobber that
13462                          modified the register.
13463
13464                          CC0 targets must be careful to maintain setter/user
13465                          pairs.  If we cannot delete the setter due to side
13466                          effects, mark the user with an UNUSED note instead
13467                          of deleting it.  */
13468
13469                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13470                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13471 #ifdef HAVE_cc0
13472                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13473                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13474                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13475 #endif
13476                           )
13477                         {
13478                           /* Move the notes and links of TEM elsewhere.
13479                              This might delete other dead insns recursively.
13480                              First set the pattern to something that won't use
13481                              any register.  */
13482                           rtx old_notes = REG_NOTES (tem);
13483
13484                           PATTERN (tem) = pc_rtx;
13485                           REG_NOTES (tem) = NULL;
13486
13487                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13488                                             NULL_RTX, NULL_RTX, NULL_RTX);
13489                           distribute_links (LOG_LINKS (tem));
13490
13491                           SET_INSN_DELETED (tem);
13492                           if (tem == i2)
13493                             i2 = NULL_RTX;
13494
13495 #ifdef HAVE_cc0
13496                           /* Delete the setter too.  */
13497                           if (cc0_setter)
13498                             {
13499                               PATTERN (cc0_setter) = pc_rtx;
13500                               old_notes = REG_NOTES (cc0_setter);
13501                               REG_NOTES (cc0_setter) = NULL;
13502
13503                               distribute_notes (old_notes, cc0_setter,
13504                                                 cc0_setter, NULL_RTX,
13505                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13506                               distribute_links (LOG_LINKS (cc0_setter));
13507
13508                               SET_INSN_DELETED (cc0_setter);
13509                               if (cc0_setter == i2)
13510                                 i2 = NULL_RTX;
13511                             }
13512 #endif
13513                         }
13514                       else
13515                         {
13516                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13517
13518                           /*  If there isn't already a REG_UNUSED note, put one
13519                               here.  Do not place a REG_DEAD note, even if
13520                               the register is also used here; that would not
13521                               match the algorithm used in lifetime analysis
13522                               and can cause the consistency check in the
13523                               scheduler to fail.  */
13524                           if (! find_regno_note (tem, REG_UNUSED,
13525                                                  REGNO (XEXP (note, 0))))
13526                             place = tem;
13527                           break;
13528                         }
13529                     }
13530                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13531                            || (CALL_P (tem)
13532                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13533                     {
13534                       place = tem;
13535
13536                       /* If we are doing a 3->2 combination, and we have a
13537                          register which formerly died in i3 and was not used
13538                          by i2, which now no longer dies in i3 and is used in
13539                          i2 but does not die in i2, and place is between i2
13540                          and i3, then we may need to move a link from place to
13541                          i2.  */
13542                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13543                           && from_insn
13544                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13545                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13546                         {
13547                           struct insn_link *links = LOG_LINKS (place);
13548                           LOG_LINKS (place) = NULL;
13549                           distribute_links (links);
13550                         }
13551                       break;
13552                     }
13553
13554                   if (tem == BB_HEAD (bb))
13555                     break;
13556                 }
13557
13558             }
13559
13560           /* If the register is set or already dead at PLACE, we needn't do
13561              anything with this note if it is still a REG_DEAD note.
13562              We check here if it is set at all, not if is it totally replaced,
13563              which is what `dead_or_set_p' checks, so also check for it being
13564              set partially.  */
13565
13566           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13567             {
13568               unsigned int regno = REGNO (XEXP (note, 0));
13569               reg_stat_type *rsp = &reg_stat[regno];
13570
13571               if (dead_or_set_p (place, XEXP (note, 0))
13572                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13573                 {
13574                   /* Unless the register previously died in PLACE, clear
13575                      last_death.  [I no longer understand why this is
13576                      being done.] */
13577                   if (rsp->last_death != place)
13578                     rsp->last_death = 0;
13579                   place = 0;
13580                 }
13581               else
13582                 rsp->last_death = place;
13583
13584               /* If this is a death note for a hard reg that is occupying
13585                  multiple registers, ensure that we are still using all
13586                  parts of the object.  If we find a piece of the object
13587                  that is unused, we must arrange for an appropriate REG_DEAD
13588                  note to be added for it.  However, we can't just emit a USE
13589                  and tag the note to it, since the register might actually
13590                  be dead; so we recourse, and the recursive call then finds
13591                  the previous insn that used this register.  */
13592
13593               if (place && regno < FIRST_PSEUDO_REGISTER
13594                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13595                 {
13596                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13597                   bool all_used = true;
13598                   unsigned int i;
13599
13600                   for (i = regno; i < endregno; i++)
13601                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13602                          && ! find_regno_fusage (place, USE, i))
13603                         || dead_or_set_regno_p (place, i))
13604                       {
13605                         all_used = false;
13606                         break;
13607                       }
13608
13609                   if (! all_used)
13610                     {
13611                       /* Put only REG_DEAD notes for pieces that are
13612                          not already dead or set.  */
13613
13614                       for (i = regno; i < endregno;
13615                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13616                         {
13617                           rtx piece = regno_reg_rtx[i];
13618                           basic_block bb = this_basic_block;
13619
13620                           if (! dead_or_set_p (place, piece)
13621                               && ! reg_bitfield_target_p (piece,
13622                                                           PATTERN (place)))
13623                             {
13624                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13625                                                              NULL_RTX);
13626
13627                               distribute_notes (new_note, place, place,
13628                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13629                                                 NULL_RTX);
13630                             }
13631                           else if (! refers_to_regno_p (i, i + 1,
13632                                                         PATTERN (place), 0)
13633                                    && ! find_regno_fusage (place, USE, i))
13634                             for (tem = PREV_INSN (place); ;
13635                                  tem = PREV_INSN (tem))
13636                               {
13637                                 if (!NONDEBUG_INSN_P (tem))
13638                                   {
13639                                     if (tem == BB_HEAD (bb))
13640                                       break;
13641                                     continue;
13642                                   }
13643                                 if (dead_or_set_p (tem, piece)
13644                                     || reg_bitfield_target_p (piece,
13645                                                               PATTERN (tem)))
13646                                   {
13647                                     add_reg_note (tem, REG_UNUSED, piece);
13648                                     break;
13649                                   }
13650                               }
13651                         }
13652
13653                       place = 0;
13654                     }
13655                 }
13656             }
13657           break;
13658
13659         default:
13660           /* Any other notes should not be present at this point in the
13661              compilation.  */
13662           gcc_unreachable ();
13663         }
13664
13665       if (place)
13666         {
13667           XEXP (note, 1) = REG_NOTES (place);
13668           REG_NOTES (place) = note;
13669         }
13670
13671       if (place2)
13672         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13673     }
13674 }
13675 \f
13676 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13677    I3, I2, and I1 to new locations.  This is also called to add a link
13678    pointing at I3 when I3's destination is changed.  */
13679
13680 static void
13681 distribute_links (struct insn_link *links)
13682 {
13683   struct insn_link *link, *next_link;
13684
13685   for (link = links; link; link = next_link)
13686     {
13687       rtx place = 0;
13688       rtx insn;
13689       rtx set, reg;
13690
13691       next_link = link->next;
13692
13693       /* If the insn that this link points to is a NOTE or isn't a single
13694          set, ignore it.  In the latter case, it isn't clear what we
13695          can do other than ignore the link, since we can't tell which
13696          register it was for.  Such links wouldn't be used by combine
13697          anyway.
13698
13699          It is not possible for the destination of the target of the link to
13700          have been changed by combine.  The only potential of this is if we
13701          replace I3, I2, and I1 by I3 and I2.  But in that case the
13702          destination of I2 also remains unchanged.  */
13703
13704       if (NOTE_P (link->insn)
13705           || (set = single_set (link->insn)) == 0)
13706         continue;
13707
13708       reg = SET_DEST (set);
13709       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13710              || GET_CODE (reg) == STRICT_LOW_PART)
13711         reg = XEXP (reg, 0);
13712
13713       /* A LOG_LINK is defined as being placed on the first insn that uses
13714          a register and points to the insn that sets the register.  Start
13715          searching at the next insn after the target of the link and stop
13716          when we reach a set of the register or the end of the basic block.
13717
13718          Note that this correctly handles the link that used to point from
13719          I3 to I2.  Also note that not much searching is typically done here
13720          since most links don't point very far away.  */
13721
13722       for (insn = NEXT_INSN (link->insn);
13723            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13724                      || BB_HEAD (this_basic_block->next_bb) != insn));
13725            insn = NEXT_INSN (insn))
13726         if (DEBUG_INSN_P (insn))
13727           continue;
13728         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13729           {
13730             if (reg_referenced_p (reg, PATTERN (insn)))
13731               place = insn;
13732             break;
13733           }
13734         else if (CALL_P (insn)
13735                  && find_reg_fusage (insn, USE, reg))
13736           {
13737             place = insn;
13738             break;
13739           }
13740         else if (INSN_P (insn) && reg_set_p (reg, insn))
13741           break;
13742
13743       /* If we found a place to put the link, place it there unless there
13744          is already a link to the same insn as LINK at that point.  */
13745
13746       if (place)
13747         {
13748           struct insn_link *link2;
13749
13750           FOR_EACH_LOG_LINK (link2, place)
13751             if (link2->insn == link->insn)
13752               break;
13753
13754           if (link2 == NULL)
13755             {
13756               link->next = LOG_LINKS (place);
13757               LOG_LINKS (place) = link;
13758
13759               /* Set added_links_insn to the earliest insn we added a
13760                  link to.  */
13761               if (added_links_insn == 0
13762                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13763                 added_links_insn = place;
13764             }
13765         }
13766     }
13767 }
13768 \f
13769 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13770    Check whether the expression pointer to by LOC is a register or
13771    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13772    Otherwise return zero.  */
13773
13774 static int
13775 unmentioned_reg_p_1 (rtx *loc, void *expr)
13776 {
13777   rtx x = *loc;
13778
13779   if (x != NULL_RTX
13780       && (REG_P (x) || MEM_P (x))
13781       && ! reg_mentioned_p (x, (rtx) expr))
13782     return 1;
13783   return 0;
13784 }
13785
13786 /* Check for any register or memory mentioned in EQUIV that is not
13787    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13788    of EXPR where some registers may have been replaced by constants.  */
13789
13790 static bool
13791 unmentioned_reg_p (rtx equiv, rtx expr)
13792 {
13793   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13794 }
13795 \f
13796 DEBUG_FUNCTION void
13797 dump_combine_stats (FILE *file)
13798 {
13799   fprintf
13800     (file,
13801      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13802      combine_attempts, combine_merges, combine_extras, combine_successes);
13803 }
13804
13805 void
13806 dump_combine_total_stats (FILE *file)
13807 {
13808   fprintf
13809     (file,
13810      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13811      total_attempts, total_merges, total_extras, total_successes);
13812 }
13813 \f
13814 static bool
13815 gate_handle_combine (void)
13816 {
13817   return (optimize > 0);
13818 }
13819
13820 /* Try combining insns through substitution.  */
13821 static unsigned int
13822 rest_of_handle_combine (void)
13823 {
13824   int rebuild_jump_labels_after_combine;
13825
13826   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13827   df_note_add_problem ();
13828   df_analyze ();
13829
13830   regstat_init_n_sets_and_refs ();
13831
13832   rebuild_jump_labels_after_combine
13833     = combine_instructions (get_insns (), max_reg_num ());
13834
13835   /* Combining insns may have turned an indirect jump into a
13836      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13837      instructions.  */
13838   if (rebuild_jump_labels_after_combine)
13839     {
13840       timevar_push (TV_JUMP);
13841       rebuild_jump_labels (get_insns ());
13842       cleanup_cfg (0);
13843       timevar_pop (TV_JUMP);
13844     }
13845
13846   regstat_free_n_sets_and_refs ();
13847   return 0;
13848 }
13849
13850 namespace {
13851
13852 const pass_data pass_data_combine =
13853 {
13854   RTL_PASS, /* type */
13855   "combine", /* name */
13856   OPTGROUP_NONE, /* optinfo_flags */
13857   true, /* has_gate */
13858   true, /* has_execute */
13859   TV_COMBINE, /* tv_id */
13860   PROP_cfglayout, /* properties_required */
13861   0, /* properties_provided */
13862   0, /* properties_destroyed */
13863   0, /* todo_flags_start */
13864   ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
13865 };
13866
13867 class pass_combine : public rtl_opt_pass
13868 {
13869 public:
13870   pass_combine(gcc::context *ctxt)
13871     : rtl_opt_pass(pass_data_combine, ctxt)
13872   {}
13873
13874   /* opt_pass methods: */
13875   bool gate () { return gate_handle_combine (); }
13876   unsigned int execute () { return rest_of_handle_combine (); }
13877
13878 }; // class pass_combine
13879
13880 } // anon namespace
13881
13882 rtl_opt_pass *
13883 make_pass_combine (gcc::context *ctxt)
13884 {
13885   return new pass_combine (ctxt);
13886 }