gcc/ChangeLog

   1 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
   2
   3         PR tree-optimization/113361
   4         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
   5         Fix up determination of the type for > limb_prec constants.
   6
   7 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
   8
   9         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
  10         Add web-link to the avr-gcc wiki.
  11
  12 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
  13
  14         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
  15         documentation for a version without argument, which is not supported.
  16
  17 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  18
  19         * config/arm/arm_neon.h
  20         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
  21         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
  22         (vld1_f16_x4, vld1_f32_x4): New.
  23         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
  24         (vld1_bf16_x4): New.
  25         (vld1q_types_x4): Updated to use vld1q_x4
  26         from arm_neon_builtins.def
  27         * config/arm/arm_neon_builtins.def
  28         (vld1_x4): Updated entries.
  29         (vld1q_x4): New entries, but comes from the old vld1_x4
  30         * config/arm/neon.md
  31         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
  32
  33 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  34
  35         * config/arm/arm_neon.h
  36         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
  37         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
  38         (vld1_f16_x3, vld1_f32_x3): New.
  39         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
  40         (vld1_bf16_x3): New.
  41         (vld1q_types_x3): Updated to use vld1q_x3 from
  42         arm_neon_builtins.def
  43         * config/arm/arm_neon_builtins.def
  44         (vld1_x3): Updated entries.
  45         (vld1q_x3): New entries, but comes from the old vld1_x2
  46         * config/arm/neon.md
  47         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
  48
  49 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  50
  51         * config/arm/arm_neon.h
  52         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
  53         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
  54         (vld1_f16_x2, vld1_f32_x2): New.
  55         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
  56         (vld1_bf16_x2): New.
  57         (vld1q_types_x2): Updated to use vld1q_x2 from
  58         arm_neon_builtins.def
  59         * config/arm/arm_neon_builtins.def
  60         (vld1_x2): Updated entries.
  61         (vld1q_x2): New entries, but comes from the old vld1_x2
  62         * config/arm/neon.md
  63         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
  64         neon_vld1_x2<mode>.
  65
  66 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  67
  68         * config/arm/arm_neon.h
  69         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
  70         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
  71         (vst1q_f16_x4, vst1q_f32_x4): New.
  72         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
  73         (vst1q_bf16_x4): New.
  74         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
  75         * config/arm/neon.md
  76         (neon_vst1q_x4<mode>): New.
  77         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
  78         * config/arm/unspecs.md
  79         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
  80
  81 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  82
  83         * config/arm/arm_neon.h
  84         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
  85         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
  86         (vst1q_f16_x3, vst1q_f32_x3): New.
  87         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
  88         (vst1q_bf16_x3): New.
  89         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
  90         * config/arm/neon.md
  91         (neon_vst1q_x3<mode>): New.
  92         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
  93         * config/arm/unspecs.md
  94         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
  95
  96 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  97
  98         * config/arm/arm_neon.h
  99         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
 100         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
 101         (vst1q_f16_x2, vst1q_f32_x2): New.
 102         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
 103         (vst1q_bf16_x2): New.
 104         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
 105         * config/arm/neon.md
 106         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 107         neon_vst1_x2<mode>.
 108         * config/arm/iterators.md
 109         (VMEMX2): New mode iterator.
 110         (VMEMX2_q): New mode attribute.
 111
 112 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 113
 114         * config/arm/arm_neon.h
 115         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
 116         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
 117         (vst1_f16_x4, vst1_f32_x4): New.
 118         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
 119         (vst1_bf16_x4): New.
 120         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
 121         * config/arm/neon.md (vst1_x4<mode>): New.
 122
 123 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 124
 125         * config/arm/arm_neon.h
 126         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
 127         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
 128         (vst1_f16_x3, vst1_f32_x3): New.
 129         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
 130         (vst1_bf16_x3): New.
 131         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
 132         * config/arm/neon.md (vst1_x3<mode>): New.
 133
 134 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 135
 136         * config/arm/arm_neon.h
 137         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
 138         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
 139         (vst1_f16_x2, vst1_f32_x2): New.
 140         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
 141         (vst1_bf16_x2): New.
 142         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
 143         * config/arm/neon.md (vst1_x2<mode>): New.
 144
 145 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 146
 147         * config/arm/arm_neon.h
 148         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
 149         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
 150         (vld1q_f16_x4, vld1q_f32_x4): New.
 151         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
 152         (vld1q_bf16_x4): New.
 153         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
 154         * config/arm/neon.md
 155         (neon_vld1_x4<mode>): New.
 156         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
 157         * config/arm/unspecs.md
 158         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
 159
 160 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 161
 162         * config/arm/arm_neon.h
 163         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
 164         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
 165         (vld1q_f16_x3, vld1q_f32_x3): New.
 166         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
 167         (vld1q_bf16_x3): New.
 168         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
 169         * config/arm/neon.md
 170         (neon_vld1_x3<mode>): New.
 171         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
 172         * config/arm/unspecs.md
 173         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
 174
 175 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 176
 177         * config/arm/arm_neon.h
 178         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
 179         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
 180         (vld1q_f16_x2, vld1q_f32_x2): New.
 181         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
 182         (vld1q_bf16_x2): New.
 183         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
 184         * config/arm/neon.md (vld1_x2<mode>): New.
 185
 186 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 187
 188         PR tree-optimization/113287
 189         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
 190
 191 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 192
 193         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
 194         * tree-vect-loop.cc (vect_transform_loop): Likewise.
 195
 196 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 197
 198         PR tree-optimization/113178
 199         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
 200         alternate exits.
 201
 202 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 203
 204         PR tree-optimization/113237
 205         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
 206         existing LCSSA variable for exit when all exits are early break.
 207
 208 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 209
 210         PR tree-optimization/113137
 211         PR tree-optimization/113136
 212         PR tree-optimization/113172
 213         PR tree-optimization/113178
 214         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 215         Maintain PHIs on inverted loops.
 216         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
 217         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
 218         latch.
 219         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
 220
 221 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 222
 223         PR tree-optimization/113135
 224         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
 225         dependency analysis.
 226
 227 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
 228
 229         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
 230         diagnostics class member name for abort of error.
 231
 232 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 233
 234         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
 235         format string to %s argument.
 236
 237 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
 238             Jakub Jelinek  <jakub@redhat.com>
 239
 240         PR middle-end/113182
 241         * varasm.cc (process_pending_assemble_externals,
 242         assemble_external_libcall): Use targetm.strip_name_encoding
 243         before calling get_identifier.
 244
 245 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         PR target/113196
 248         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
 249         New member variable.
 250         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
 251         Declare.
 252         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
 253         * config/aarch64/aarch64-simd.md
 254         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
 255         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
 256         zip2 for zero-extends to...
 257         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
 258         instruction.  Fix big-endian handling.
 259         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
 260         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
 261         zip1 for zero-extends to...
 262         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
 263         Fix big-endian handling.
 264         (*aarch64_zip1_uxtl): New pattern.
 265         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
 266         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
 267         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
 268         (aarch64_gen_shareable_zero): Use it.
 269         (aarch64_split_simd_shift_p): New function.
 270
 271 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 272
 273         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
 274         (function_beg_insn): New macro.
 275         * function.cc (expand_function_start): Initialize function_beg_insn.
 276
 277 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 278
 279         PR target/112989
 280         * config/aarch64/aarch64-sve-builtins.h
 281         (function_builder::m_overload_names): Replace with...
 282         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
 283         new global.
 284         (add_overloaded_function): Update accordingly, using get_identifier
 285         to get a GGC-friendly record of the name.
 286
 287 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 288
 289         PR target/112989
 290         * config/aarch64/aarch64-sve-builtins.def: Don't include
 291         aarch64-sve-builtins-sme.def.
 292         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
 293         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
 294         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
 295         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
 296         requires AARCH64_FL_SME2.
 297         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
 298         AARCH64_FL_SME adjustment here.
 299         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
 300         include SME intrinsics.
 301         (sme_function_groups): New array.
 302         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
 303         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
 304
 305 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 306
 307         PR target/113281
 308         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
 309         (struct cpu_vector_cost): Add regmove struct.
 310         (get_vector_costs): Export as global.
 311         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
 312         (costs::add_stmt_cost): Ditto.
 313         * config/riscv/riscv.cc (get_common_costs): Export global function.
 314
 315 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 316
 317         PR tree-optimization/113334
 318         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
 319         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
 320         to determine if number should be extended by all ones rather than zero
 321         extended.
 322
 323 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 324
 325         PR tree-optimization/113330
 326         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
 327         too large size.
 328
 329 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 330
 331         PR tree-optimization/113323
 332         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
 333         check for lhs being large/huge _BitInt not in m_names.
 334
 335 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 336
 337         PR tree-optimization/113316
 338         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
 339         uninitialized large/huge _BitInt arguments to calls.
 340
 341 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 342
 343         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
 344         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
 345         CEIL (TYPE_PRECISION (t), limb_prec).
 346         (bitint_large_huge::handle_cast): Likewise.
 347
 348 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
 349
 350         PR sanitizer/113284
 351         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
 352         Use assemble_function_label_final () for Power ELF V1 ABI.
 353         * output.h (assemble_function_label_final): New function.
 354         * varasm.cc (assemble_function_label_raw): Use
 355         assemble_function_label_final ().
 356         (assemble_function_label_final): New function.
 357
 358 2024-01-12  Richard Biener  <rguenther@suse.de>
 359
 360         PR middle-end/113344
 361         * match.pd ((double)float CMP (double)float -> float CMP float):
 362         Perform result type check only for vectors.
 363         * fold-const.cc (fold_binary_loc): Likewise.
 364
 365 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
 366
 367         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
 368         (usdot_prod<mode>): Ditto.
 369         (sdot_prod<mode>): Ditto.
 370         (udot_prod<mode>): Ditto.
 371
 372 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
 373
 374         PR target/113288
 375         * config/i386/i386-c.cc (ix86_target_macros_internal):
 376         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
 377
 378 2024-01-12  Richard Biener  <rguenther@suse.de>
 379
 380         PR target/112280
 381         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
 382         Do not generate code when d.testing_p.
 383
 384 2024-01-12  liuhongt  <hongtao.liu@intel.com>
 385
 386         PR target/113039
 387         * doc/invoke.texi (fcf-protection=): Update documents.
 388
 389 2024-01-12  Pan Li  <pan2.li@intel.com>
 390
 391         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
 392         comments of predicate func riscv_v_ext_mode_p.
 393
 394 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
 395
 396         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
 397                         Modify ABI-name length of vfloat16m8_t
 398
 399 2024-01-12  Li Wei  <liwei@loongson.cn>
 400
 401         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
 402         Adjust.
 403
 404 2024-01-12  Li Wei  <liwei@loongson.cn>
 405
 406         * config/loongarch/loongarch.md (add<mode>3): Removed.
 407         (*addsi3): New.
 408         (addsi3): Ditto.
 409         (adddi3): Ditto.
 410         (*addsi3_extended): Removed.
 411         (addsi3_extended): New.
 412
 413 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
 414
 415         * config/riscv/thead.md: Add limits for splits.
 416
 417 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
 418
 419         PR middle-end/113322
 420         * expr.cc (do_store_flag): Don't try single bit tests with
 421         comparison on vector types.
 422
 423 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
 424
 425         PR tree-optimization/113301
 426         * match.pd (`1/x`): Delay signed case until late.
 427
 428 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
 429
 430         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
 431         and -msp8 to...
 432         (AVR Internal Options): ...this new @subsubsection.
 433
 434 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
 435
 436         PR rtl-optimization/112918
 437         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
 438         (in_class_p): Restrict condition for narrowing class in case of
 439         allow_all_reload_class_changes_p.
 440         (process_alt_operands): Try to match operand without and with
 441         narrowing reg class.  Discourage narrowing the class.  Finish insn
 442         matching only if there is no class narrowing.
 443         (curr_insn_transform): Pass true to in_class_p for reg operand win.
 444
 445 2024-01-11  Richard Biener  <rguenther@suse.de>
 446
 447         PR tree-optimization/112505
 448         * tree-vect-loop.cc (vectorizable_induction): Reject
 449         bit-precision induction.
 450
 451 2024-01-11  Richard Biener  <rguenther@suse.de>
 452
 453         PR tree-optimization/113126
 454         * match.pd ((double)float CMP (double)float -> float CMP float):
 455         Make sure the boolean type is the same.
 456         * fold-const.cc (fold_binary_loc): Likewise.
 457
 458 2024-01-11  Richard Biener  <rguenther@suse.de>
 459
 460         PR tree-optimization/112636
 461         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
 462         estimate_numbers_of_iterations before querying
 463         get_max_loop_iterations_int.
 464         (pass_ch::execute): Initialize SCEV and loops appropriately.
 465
 466 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
 467
 468         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
 469         Reduced Tiny.
 470         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
 471         * doc/extend.texi (AVR Variable Attributes): Improve documentation
 472         of io, io_low and address attributes.
 473         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
 474         * doc/avr-mmcu.texi: Rebuild.
 475
 476 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
 477
 478         PR target/113233
 479         * config/loongarch/genopts/loongarch.opt.in: Mark options with
 480         the "Save" property.
 481         * config/loongarch/loongarch.opt: Same.
 482         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
 483         according to la_target.
 484         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
 485         RESTORE} for the la_target structure; Rename option conditions
 486         to have the same "la_" prefix.
 487         * config/loongarch/loongarch.h: Same.
 488
 489 2024-01-11  Pan Li  <pan2.li@intel.com>
 490
 491         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
 492         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
 493
 494 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
 495
 496         PR target/113077
 497         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
 498         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
 499         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
 500         synthesize these if needed.  Update caller ...
 501         (ldp_bb_info::fuse_pair): ... here.
 502         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
 503         and either insn is frame-related.
 504         (find_trailing_add): Punt on frame-related insns.
 505         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
 506         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
 507
 508 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
 509
 510         * config/mips/mips.cc (mips_start_function_definition):
 511         Add ATTRIBUTE_UNUSED.
 512
 513 2024-01-11  Richard Biener  <rguenther@suse.de>
 514
 515         PR middle-end/112740
 516         * expr.cc (store_constructor): Check the integer vector
 517         mask has a single bit per element before using sign-extension
 518         to expand an uniform vector.
 519
 520 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 521
 522         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
 523         preempt VLS on unknown NITERS loop.
 524
 525 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
 526
 527         * doc/invoke.texi: Add -mevex512.
 528
 529 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
 530
 531         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
 532         (*nor<mode>3): Likewise.
 533         (nor<mode>3): Likewise.
 534         (*negsi2_extended): New template.
 535         (*<optab>si3_internal): Likewise.
 536         (*one_cmplsi2_internal): Likewise.
 537         (*norsi3_internal): Likewise.
 538         (*<optab>nsi_internal): Likewise.
 539         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
 540         modified bit operation to make the optimization work.
 541
 542 2024-01-11  liuhongt  <hongtao.liu@intel.com>
 543
 544         PR target/104401
 545         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
 546
 547 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 548
 549         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
 550         (get_vector_costs): Ditto.
 551         (riscv_builtin_vectorization_cost): Ditto.
 552
 553 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 554
 555         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
 556
 557 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
 558
 559         PR jit/111396
 560         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
 561         ipa_free_size_summary.
 562         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
 563         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
 564         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
 565         * ipa-prop.h (ipa_prop_cc_finalize): New function.
 566         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
 567         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
 568         ipa_sra_cc_finalize): New functions.
 569         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
 570         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
 571         ipa_sra_cc_finalize
 572         Include ipa-utils.h.
 573
 574 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
 575
 576         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
 577         (th_int_get_save_adjustment): Likewise.
 578         (th_int_adjust_cfi_prologue): Likewise.
 579         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
 580         (TH_INT_INTERRUPT): New macro.
 581         (riscv_expand_prologue): Add the processing of XTheadInt.
 582         (riscv_expand_epilogue): Likewise.
 583         * config/riscv/riscv.h (BITSET_P): Moved to here.
 584         * config/riscv/riscv.md: New unspec.
 585         * config/riscv/thead.cc (th_int_get_mask): New function.
 586         (th_int_get_save_adjustment): Likewise.
 587         (th_int_adjust_cfi_prologue): Likewise.
 588         * config/riscv/thead.md (th_int_push): New pattern.
 589         (th_int_pop): new pattern.
 590
 591 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 592
 593         PR tree-optimization/112468
 594         * doc/sourcebuild.texi: Document ifn_copysign.
 595         * match.pd: Only apply transformation if target supports the IFN.
 596
 597 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
 598
 599         PR tree-optimization/112581
 600         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
 601         mark_ssa_maybe_undefs.
 602         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
 603         variables can not be reassociated.
 604         (init_range_entry): Check for uninitialized variables too.
 605         (init_reassoc): Call mark_ssa_maybe_undefs.
 606
 607 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
 608
 609         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
 610         Also handle sign extension.
 611
 612 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
 613
 614         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
 615         to 0.
 616         (-mlate-ldp-fusion): Likewise.
 617
 618 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 619
 620         PR tree-optimization/113287
 621         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
 622         instead of using BRANCH_EDGE to determine true edge.
 623
 624 2024-01-10  Richard Biener  <rguenther@suse.de>
 625
 626         PR tree-optimization/113078
 627         * tree-vect-loop.cc (check_reduction_path): Canonicalize
 628         .COND_SUB to .COND_ADD.
 629
 630 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 631
 632         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
 633         Handle prefix mappings before calling find_opt.
 634         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
 635         "-fno-"-prefixed command-line option.
 636         * opts-common.cc (get_option_prefix_remapping): New.
 637         * opts.h (get_option_prefix_remapping): New decl.
 638
 639 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 640
 641         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
 642         m_urlifier to pp_output_formatted_text.
 643         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
 644         (obstack_append_string): New overload, taking a length.
 645         (urlify_quoted_string): Pass in an obstack ptr, rather than using
 646         that of the pp's buffer.  Generalize to handle trailing text in
 647         the buffer beyond the run of quoted text.
 648         (class quoting_info): New.
 649         (on_begin_quote): New.
 650         (on_end_quote): New.
 651         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
 652         it to calls to on_begin_quote and on_end_quote.
 653         (struct auto_obstack): New.
 654         (quoting_info::handle_phase_3): New.
 655         (pp_output_formatted_text): Add urlifier param.  Use it if there
 656         is deferred urlification.  Delete m_quotes.
 657         (selftest::pp_printf_with_urlifier): Pass urlifier to
 658         pp_output_formatted_text.
 659         (selftest::test_urlification): Update results for the existing
 660         case of quoted text stradding chunks; add more such test cases.
 661         * pretty-print.h (class quoting_info): New forward decl.
 662         (chunk_info::m_quotes): New field.
 663         (pp_output_formatted_text): Add optional urlifier param.
 664
 665 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 666
 667         * pretty-print.cc (selftest::test_pp_format): Add selftest
 668         coverage for numbered args.
 669
 670 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 671
 672         PR tree-optimization/113144
 673         PR tree-optimization/113145
 674         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 675         Update all BB that the original exits dominated.
 676
 677 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
 678
 679         * dwarf2out.cc (modified_type_die): Extend the support of reverse
 680         storage order to enumeration types if -gstrict-dwarf is not passed.
 681         (gen_enumeration_type_die): Add REVERSE parameter and generate the
 682         DIE immediately after the existing one if it is true.
 683         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
 684         call to gen_enumeration_type_die.
 685         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
 686         first recursive call as well as the call to gen_tagged_type_die.
 687         (gen_type_die): Add REVERSE parameter and pass it in the call to
 688         gen_type_die_with_usage.
 689
 690 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
 691
 692         PR tree-optimization/113120
 693         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
 694         with root->size TYPE_PRECISION don't build anything new.
 695         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
 696         rather than build_nonstandard_integer_type.
 697
 698 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
 699
 700         * config/i386/i386.opt: Adjust document.
 701         * doc/invoke.texi: Add description for
 702         -mapx-inline-asm-use-gpr32.
 703
 704 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 705
 706         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
 707         (avg<v_double_trunc>3_floor): New pattern.
 708         (<u>avg<v_double_trunc>3_ceil): Remove.
 709         (avg<v_double_trunc>3_ceil): New pattern.
 710         (uavg<mode>3_floor): Ditto.
 711         (uavg<mode>3_ceil): Ditto.
 712         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
 713         (enum insn_type): Ditto.
 714         * config/riscv/riscv-v.cc: Ditto.
 715         * config/riscv/vector-iterators.md (ashiftrt): Remove.
 716         (ASHIFTRT): Ditto.
 717         * config/riscv/vector.md: Add VLS modes.
 718
 719 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 720
 721         PR target/111480
 722         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
 723         (vczlsbb_char): New int attribute.
 724         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
 725         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
 726         (*vctzlsbb_zext_<mode>): Rename to ...
 727         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
 728         cover vclzlsbb.
 729
 730 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 731
 732         PR target/112606
 733         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
 734         of the last argument from altivec_register_operand to any_operand.  If
 735         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
 736         otherwise if it doesn't satisfy altivec_register_operand, force it to
 737         REG using copy_to_mode_reg.
 738
 739 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 740
 741         PR middle-end/113100
 742         * builtins.cc (expand_builtin_stack_address): Guard stack point
 743         adjustment with SPARC_STACK_BOUNDARY_HACK.
 744
 745 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 746
 747         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
 748         argument string definitions.
 749         * config/loongarch/loongarch-str.h: Same.
 750         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
 751         as aliases to -mexplicit-relocs={always,none}
 752         * config/loongarch/loongarch.opt: Regenerate.
 753         * config/loongarch/loongarch.cc: Same.
 754
 755 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 756
 757         * config/loongarch/loongarch-def.h: Define constants with
 758         enums instead of Macros.
 759
 760 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 761
 762         * config/loongarch/genopts/loongarch-strings: Rename.
 763         * config/loongarch/genopts/loongarch.opt.in: Same.
 764         * config/loongarch/loongarch-cpu.cc: Same.
 765         * config/loongarch/loongarch-def.cc: Same.
 766         * config/loongarch/loongarch-def.h: Same.
 767         * config/loongarch/loongarch-opts.cc: Same.
 768         * config/loongarch/loongarch-opts.h: Same.
 769         * config/loongarch/loongarch-str.h: Same.
 770         * config/loongarch/loongarch.opt: Same.
 771
 772 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 773
 774         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
 775         variable with the common la_ prefix.
 776         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
 777         flags as saved using TargetVariable.
 778         * config/loongarch/loongarch.opt: Same.
 779         * config/loongarch/loongarch-def.h: Define evolution_set to
 780         mark changes to the -march default.
 781         * config/loongarch/loongarch-driver.cc: Same.
 782         * config/loongarch/loongarch-opts.cc: Same.
 783         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
 784         conditions around the la_target structure.
 785         * config/loongarch/loongarch.cc: Same.
 786         * config/loongarch/loongarch.md: Same.
 787         * config/loongarch/loongarch-builtins.cc: Same.
 788         * config/loongarch/loongarch-c.cc: Same.
 789         * config/loongarch/lasx.md: Same.
 790         * config/loongarch/lsx.md: Same.
 791         * config/loongarch/sync.md: Same.
 792
 793 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
 794
 795         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
 796         no less.
 797
 798 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
 799
 800         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
 801
 802 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 803
 804         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
 805         restart_loop.
 806         (vectorizable_live_operation): Likewise.
 807
 808 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 809
 810         PR tree-optimization/113199
 811         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
 812         BIT_FIELD_REF.
 813
 814 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
 815
 816         PR target/113270
 817         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
 818         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
 819         GTY(()) declaration before the definition, drop GTY(()) drom the
 820         definition.
 821
 822 2024-01-09  Richard Biener  <rguenther@suse.de>
 823
 824         PR tree-optimization/113026
 825         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
 826         redundant and wrong niter bound setting.  Move niter
 827         bound adjustment down.
 828
 829 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 830
 831         PR middle-end/113163
 832         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
 833         Reject non-linear inductions that aren't supported.
 834
 835 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
 836
 837         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
 838         left shift implementation strategies.
 839         (arc_shift_info): Type for each entry of the shift strategy table.
 840         (arc_shift_context_idx): Return a integer value for each code
 841         generation context, used as an index
 842         (arc_ashl_alg): Table indexed by context and shifted bit count.
 843         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
 844         left shift implementation.
 845         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
 846         provide accurate costs, when optimizing for speed or size.
 847
 848 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 849
 850         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
 851
 852 2024-01-09  Julian Brown  <julian@codesourcery.com>
 853
 854         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
 855         processed out before gimplification.
 856         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
 857         * tree.def (OMP_ARRAY_SECTION): New tree code.
 858
 859 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
 860
 861         PR tree-optimization/113210
 862         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
 863         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
 864         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
 865         minus 1.
 866
 867 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
 868
 869         PR rtl-optimization/113140
 870         * reorg.cc (fill_slots_from_thread): If we are to branch after the
 871         last instruction of the function, create an end label.
 872
 873 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
 874             Hongtao Liu  <hongtao.liu@intel.com>
 875
 876         PR target/112992
 877         * config/i386/i386-expand.cc
 878         (ix86_convert_const_wide_int_to_broadcast): Allow call to
 879         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
 880         (ix86_broadcast_from_constant): Revert recent change; Return a
 881         suitable MEMREF independently of mode/target combinations.
 882         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
 883         to decide whether expansion is possible/preferrable.  Only try
 884         forcing DImode constants to memory (and trying again) if calling
 885         ix86_expand_vector_init_duplicate fails with an DImode immediate
 886         constant.
 887         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
 888         V4SImode for suitable immediate constants.
 889         <case E_V4DImode>: Try using V8SImode for suitable constants.
 890         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
 891         <case E_V2HImode>: Likewise.
 892         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
 893         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
 894         <label widen>: Handle CONT_INTs via simplify_binary_operation.
 895         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
 896         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
 897         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
 898         (ix86_expand_vector_init): Move try using a broadcast for all_same
 899         with ix86_expand_vector_init_duplicate before using constant pool.
 900
 901 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 902
 903         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
 904
 905 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 906
 907         * config/arm/arm-cpus.in (cortex-m52): New cpu.
 908         * config/arm/arm-tables.opt: Regenerate.
 909         * config/arm/arm-tune.md: Regenerate.
 910
 911 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
 912
 913         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
 914         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
 915         (@vec_concatz<mode>): New insn pattern.
 916         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
 917         Handle VALS containing two vectors.
 918
 919 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 920
 921         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
 922         (vundefined): Ditto.
 923
 924 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
 925
 926         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
 927                                 Add new function_base for crypto vector.
 928         (class bitmanip): Ditto.
 929         (class b_reverse):Ditto.
 930         (class vwsll):   Ditto.
 931         (class clmul):   Ditto.
 932         (class vg_nhab):  Ditto.
 933         (class crypto_vv):Ditto.
 934         (class crypto_vi):Ditto.
 935         (class vaeskf2_vsm3c):Ditto.
 936         (class vsm3me): Ditto.
 937         (BASE): Add BASE declaration for crypto vector.
 938         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
 939         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
 940                                 Add crypto vector intrinsic definition.
 941         (vbrev): Ditto.
 942         (vclz): Ditto.
 943         (vctz): Ditto.
 944         (vwsll): Ditto.
 945         (vandn): Ditto.
 946         (vbrev8): Ditto.
 947         (vrev8): Ditto.
 948         (vrol): Ditto.
 949         (vror): Ditto.
 950         (vclmul): Ditto.
 951         (vclmulh): Ditto.
 952         (vghsh): Ditto.
 953         (vgmul): Ditto.
 954         (vaesef): Ditto.
 955         (vaesem): Ditto.
 956         (vaesdf): Ditto.
 957         (vaesdm): Ditto.
 958         (vaesz): Ditto.
 959         (vaeskf1): Ditto.
 960         (vaeskf2): Ditto.
 961         (vsha2ms): Ditto.
 962         (vsha2ch): Ditto.
 963         (vsha2cl): Ditto.
 964         (vsm4k): Ditto.
 965         (vsm4r): Ditto.
 966         (vsm3me): Ditto.
 967         (vsm3c): Ditto.
 968         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
 969                                 Add new function_shape for crypto vector.
 970         (struct crypto_vi_def): Ditto.
 971         (struct crypto_vv_no_op_type_def): Ditto.
 972         (SHAPE): Add SHAPE declaration of crypto vector.
 973         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
 974         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
 975                                 Add new data type for crypto vector.
 976         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 977         (vuint32mf2_t): Ditto.
 978         (vuint32m1_t): Ditto.
 979         (vuint32m2_t): Ditto.
 980         (vuint32m4_t): Ditto.
 981         (vuint32m8_t): Ditto.
 982         (vuint64m1_t): Ditto.
 983         (vuint64m2_t): Ditto.
 984         (vuint64m4_t): Ditto.
 985         (vuint64m8_t): Ditto.
 986         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
 987                                 Add new data struct for crypto vector.
 988         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 989         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
 990         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
 991
 992 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
 993
 994         PR sanitizer/113251
 995         * varasm.cc (assemble_function_label_raw): Do not call
 996         asan_function_start () without the current function.
 997
 998 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
 999
1000         PR target/113225
1001         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
1002         extern and kernel_helper attributed function decls.
1003
1004 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1005
1006         * btfout.cc (output_btf_strs): Changed.
1007
1008 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1009
1010         * config/gcn/mkoffload.cc (main): Handle gfx1100
1011         when setting the default XNACK.
1012
1013 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1014
1015         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
1016         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
1017         (ASM_SPEC): Handle gfx1100.
1018         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
1019         (enum gcn_isa): Add ISA_RDNA3.
1020         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
1021         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1022         * config/gcn/gcn.cc (gcn_option_override,
1023         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
1024         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
1025         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1026         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
1027         with gfx1100.
1028         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
1029         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
1030         __gfx1100__.
1031         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1032         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
1033         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
1034         (isa_has_combined_avgprs, main): Handle gfx1100.
1035         * config/gcn/t-omp-device (isa): Add gfx1100.
1036
1037 2024-01-08  Richard Biener  <rguenther@suse.de>
1038
1039         * doc/invoke.texi (-mmovbe): Clarify.
1040
1041 2024-01-08  Richard Biener  <rguenther@suse.de>
1042
1043         PR tree-optimization/113026
1044         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
1045         Avoid an epilog in more cases.
1046         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
1047         epilogues niter upper bounds and estimates.
1048
1049 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1050
1051         PR tree-optimization/113228
1052         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
1053
1054 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1055
1056         PR tree-optimization/113120
1057         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
1058         large _BitInt zero INTEGER_CST PHI argument.
1059
1060 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1061
1062         PR tree-optimization/113119
1063         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
1064         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
1065         is before REALPART_EXPR.
1066
1067 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
1068
1069         PR target/112952
1070         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
1071         range when diagnosing attribute "io" and "io_low" are out of range.
1072         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
1073         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
1074         in contexts other than static storage.
1075         (avr_asm_output_aligned_decl_common): Move output of decls with
1076         attribute "address", "io", and "io_low" to...
1077         (avr_output_addr_attrib): ...this new function.
1078         (avr_asm_asm_output_aligned_bss): Remove output for decls with
1079         attribute "address", "io", and "io_low".
1080         (avr_encode_section_info): Rectify handling of decls with attribute
1081         "address", "io", and "io_low".
1082
1083 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1084
1085         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
1086         (elf_flags): Remove XNACK from the default value.
1087         (main): Set a default XNACK according to the arch.
1088
1089 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1090
1091         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
1092         (process_asm): Don't count avgprs.
1093
1094 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
1095
1096         * config/i386/i386.opt: Add supported sub-features.
1097         * doc/extend.texi: Add description for target attribute.
1098
1099 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
1100
1101         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
1102
1103 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
1104             Uros Bizjak  <ubizjak@gmail.com>
1105
1106         PR target/113231
1107         * config/i386/i386-features.cc (compute_convert_gain): Include
1108         the overhead of explicit load and store (movd) instructions when
1109         converting non-store scalar operations with memory destinations.
1110         Various indentation whitespace fixes.
1111
1112 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
1113
1114         * config/arm/neon.md (cbranch<mode>4): New.
1115
1116 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1117
1118         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
1119
1120 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
1121
1122         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
1123
1124 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1125
1126         PR target/113248
1127         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
1128         Update the MAX_SEW.
1129
1130 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1131
1132         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
1133         (variable_vectorized_p): Teach loop invariant.
1134         (has_unexpected_spills_p): Ditto.
1135
1136 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1137
1138         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
1139         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
1140         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
1141
1142 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
1143
1144         PR target/113104
1145         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
1146         (aarch64-vect-compare-costs): ...this.
1147         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
1148         Replace with...
1149         (-param=aarch64-vect-compare-costs=): ...this new param.
1150         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
1151         Don't disable it when vectorizing for Advanced SIMD only.
1152         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
1153         whenever aarch64_vect_compare_costs is true.
1154
1155 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
1156
1157         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
1158         Modify the method of determining the memory offset of [x]vld/[x]vst.
1159         (lasx_mxst_<lasxfmt_f>): Likewise.
1160         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
1161         (loongarch_address_insns): Likewise.
1162         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
1163         (lsx_st_<lsxfmt_f>): Likewise.
1164         * config/loongarch/predicates.md (aq10b_operand): Likewise.
1165         (aq10h_operand): Likewise.
1166         (aq10w_operand): Likewise.
1167         (aq10d_operand): Likewise.
1168
1169 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
1170
1171         PR target/113217
1172         * config/aarch64/aarch64-ldp-fusion.cc
1173         (ldp_bb_info::try_fuse_pair): If the second access can throw,
1174         narrow the move range to exactly that insn.
1175
1176 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1177
1178         * asan.cc (asan_function_start): Drop switch_to_section ().
1179         (asan_emit_stack_protection): Set .LASANPC alignment.
1180         * config/i386/i386.cc: Use assemble_function_label_raw ()
1181         instead of ASM_OUTPUT_LABEL ().
1182         * config/s390/s390.cc (s390_asm_output_function_label):
1183         Likewise.
1184         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
1185         * final.cc (final_start_function_1): Drop
1186         asan_function_start ().
1187         * output.h (assemble_function_label_raw): New function.
1188         * varasm.cc (assemble_function_label_raw): Likewise.
1189
1190 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1191
1192         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
1193         Use ASM_OUTPUT_FUNCTION_LABEL ().
1194         * config/alpha/alpha.cc (alpha_start_function): Likewise.
1195         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1196         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
1197         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1198         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1199         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
1200         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1201         * config/ia64/ia64.cc (ia64_start_function): Likewise.
1202         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
1203         Likewise.
1204         * config/microblaze/microblaze.cc (microblaze_function_prologue):
1205         Likewise.
1206         * config/mips/mips.cc (mips_start_unique_function): Return the
1207         tree.
1208         (mips_start_function_definition): Use
1209         ASM_OUTPUT_FUNCTION_LABEL ().
1210         (mips_finish_stub): Pass the tree to
1211         mips_start_function_definition ().
1212         (mips16_build_function_stub): Likewise.
1213         (mips16_build_call_stub): Likewise.
1214         (mips_output_function_prologue): Likewise.
1215         * config/pa/pa.cc (pa_output_function_label): Use
1216         ASM_OUTPUT_FUNCTION_LABEL ().
1217         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
1218         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1219         Likewise.
1220         (rs6000_xcoff_declare_function_name): Likewise.
1221
1222 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1223
1224         PR tree-optimization/113201
1225         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
1226         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
1227
1228 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1229
1230         PR tree-optimization/90693
1231         * tree-ssa-math-opts.cc (match_single_bit_test): If
1232         tree_expr_nonzero_p (arg), remember it in the second argument to
1233         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
1234         arg ^ (arg - 1) > arg - 1.
1235         * internal-fn.cc (expand_POPCOUNT): If second argument to
1236         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
1237         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
1238
1239 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
1240
1241         * config/riscv/riscv-v.cc (expand_load_store):
1242         Remove `value`.
1243         (expand_cond_len_op): Ditto.
1244         (expand_gather_scatter): Ditto.
1245         (expand_lanes_load_store): Ditto.
1246         (expand_fold_extract_last): Ditto.
1247
1248 2024-01-05  Pan Li  <pan2.li@intel.com>
1249
1250         Revert:
1251         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
1252
1253         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1254                                 Add new function_base for crypto vector.
1255         (class bitmanip): Ditto.
1256         (class b_reverse):Ditto.
1257         (class vwsll):   Ditto.
1258         (class clmul):   Ditto.
1259         (class vg_nhab):  Ditto.
1260         (class crypto_vv):Ditto.
1261         (class crypto_vi):Ditto.
1262         (class vaeskf2_vsm3c):Ditto.
1263         (class vsm3me): Ditto.
1264         (BASE): Add BASE declaration for crypto vector.
1265         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1266         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1267                                 Add crypto vector intrinsic definition.
1268         (vbrev): Ditto.
1269         (vclz): Ditto.
1270         (vctz): Ditto.
1271         (vwsll): Ditto.
1272         (vandn): Ditto.
1273         (vbrev8): Ditto.
1274         (vrev8): Ditto.
1275         (vrol): Ditto.
1276         (vror): Ditto.
1277         (vclmul): Ditto.
1278         (vclmulh): Ditto.
1279         (vghsh): Ditto.
1280         (vgmul): Ditto.
1281         (vaesef): Ditto.
1282         (vaesem): Ditto.
1283         (vaesdf): Ditto.
1284         (vaesdm): Ditto.
1285         (vaesz): Ditto.
1286         (vaeskf1): Ditto.
1287         (vaeskf2): Ditto.
1288         (vsha2ms): Ditto.
1289         (vsha2ch): Ditto.
1290         (vsha2cl): Ditto.
1291         (vsm4k): Ditto.
1292         (vsm4r): Ditto.
1293         (vsm3me): Ditto.
1294         (vsm3c): Ditto.
1295         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1296                                 Add new function_shape for crypto vector.
1297         (struct crypto_vi_def): Ditto.
1298         (struct crypto_vv_no_op_type_def): Ditto.
1299         (SHAPE): Add SHAPE declaration of crypto vector.
1300         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1301         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1302                                 Add new data type for crypto vector.
1303         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1304         (vuint32mf2_t): Ditto.
1305         (vuint32m1_t): Ditto.
1306         (vuint32m2_t): Ditto.
1307         (vuint32m4_t): Ditto.
1308         (vuint32m8_t): Ditto.
1309         (vuint64m1_t): Ditto.
1310         (vuint64m2_t): Ditto.
1311         (vuint64m4_t): Ditto.
1312         (vuint64m8_t): Ditto.
1313         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1314                                 Add new data struct for crypto vector.
1315         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1316         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1317         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1318
1319 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
1320
1321         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1322                                 Add new function_base for crypto vector.
1323         (class bitmanip): Ditto.
1324         (class b_reverse):Ditto.
1325         (class vwsll):   Ditto.
1326         (class clmul):   Ditto.
1327         (class vg_nhab):  Ditto.
1328         (class crypto_vv):Ditto.
1329         (class crypto_vi):Ditto.
1330         (class vaeskf2_vsm3c):Ditto.
1331         (class vsm3me): Ditto.
1332         (BASE): Add BASE declaration for crypto vector.
1333         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1334         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1335                                 Add crypto vector intrinsic definition.
1336         (vbrev): Ditto.
1337         (vclz): Ditto.
1338         (vctz): Ditto.
1339         (vwsll): Ditto.
1340         (vandn): Ditto.
1341         (vbrev8): Ditto.
1342         (vrev8): Ditto.
1343         (vrol): Ditto.
1344         (vror): Ditto.
1345         (vclmul): Ditto.
1346         (vclmulh): Ditto.
1347         (vghsh): Ditto.
1348         (vgmul): Ditto.
1349         (vaesef): Ditto.
1350         (vaesem): Ditto.
1351         (vaesdf): Ditto.
1352         (vaesdm): Ditto.
1353         (vaesz): Ditto.
1354         (vaeskf1): Ditto.
1355         (vaeskf2): Ditto.
1356         (vsha2ms): Ditto.
1357         (vsha2ch): Ditto.
1358         (vsha2cl): Ditto.
1359         (vsm4k): Ditto.
1360         (vsm4r): Ditto.
1361         (vsm3me): Ditto.
1362         (vsm3c): Ditto.
1363         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1364                                 Add new function_shape for crypto vector.
1365         (struct crypto_vi_def): Ditto.
1366         (struct crypto_vv_no_op_type_def): Ditto.
1367         (SHAPE): Add SHAPE declaration of crypto vector.
1368         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1369         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1370                                 Add new data type for crypto vector.
1371         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1372         (vuint32mf2_t): Ditto.
1373         (vuint32m1_t): Ditto.
1374         (vuint32m2_t): Ditto.
1375         (vuint32m4_t): Ditto.
1376         (vuint32m8_t): Ditto.
1377         (vuint64m1_t): Ditto.
1378         (vuint64m2_t): Ditto.
1379         (vuint64m4_t): Ditto.
1380         (vuint64m8_t): Ditto.
1381         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1382                                 Add new data struct for crypto vector.
1383         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1384         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1385         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1386
1387 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1388
1389         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1390
1391 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
1392
1393         PR tree-optimization/113186
1394         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
1395         Match `^` with the `==` for 1bit integral types.
1396         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
1397         integral types.
1398
1399 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1400
1401         * toplev.cc (general_init): Pass lang_mask to urlifier.
1402
1403 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1404
1405         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
1406         param.
1407         (diagnostic_context::make_option_url): Update for lang_mask param.
1408         * gcc-urlifier.cc: Include "opts.h" and "options.h".
1409         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
1410         (gcc_urlifier::m_lang_mask): New field.
1411         (doc_urls): Make static.
1412         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
1413         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
1414         Look for an option by name before trying a binary search in
1415         doc_urls.
1416         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
1417         (gcc_urlifier::get_url_suffix_for_option): New.
1418         (make_gcc_urlifier): Add lang_mask param.
1419         (selftest::gcc_urlifier_cc_tests): Update for above changes.
1420         Verify that a URL is found for "-fpack-struct".
1421         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
1422         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
1423         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
1424         to make_gcc_urlifier.
1425         * opts-diagnostic.h (get_option_url): Add lang_mask param.
1426         * opts.cc (get_option_html_page): Remove special-casing for
1427         analyzer and LTO.
1428         (get_option_url_suffix): New.
1429         (get_option_url): Reimplement.
1430         (selftest::test_get_option_html_page): Rename to...
1431         (selftest::test_get_option_url_suffix): ...this and update for
1432         above changes.
1433         (selftest::opts_cc_tests): Update for renaming.
1434         * opts.h: Include "rich-location.h".
1435         (get_option_url_suffix): New decl.
1436
1437 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1438
1439         * Makefile.in (ALL_OPT_URL_FILES): New.
1440         (GCC_OBJS): Add options-urls.o.
1441         (OBJS): Likewise.
1442         (OBJS-libcommon): Likewise.
1443         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
1444         inputs to opt-gather.awk.
1445         (options-urls.cc): New Makefile target.
1446         * opt-functions.awk (url_suffix): New function.
1447         (lang_url_suffix): New function.
1448         * options-urls-cc-gen.awk: New file.
1449         * opts.h (get_opt_url_suffix): New decl.
1450
1451 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1452
1453         * params.opt.urls: New file, autogenerated by
1454         regenerate-opt-urls.py.
1455
1456 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1457
1458         * common.opt.urls: New file, autogenerated by
1459         regenerate-opt-urls.py.
1460         * config/aarch64/aarch64.opt.urls: Likewise.
1461         * config/alpha/alpha.opt.urls: Likewise.
1462         * config/alpha/elf.opt.urls: Likewise.
1463         * config/arc/arc-tables.opt.urls: Likewise.
1464         * config/arc/arc.opt.urls: Likewise.
1465         * config/arm/arm-tables.opt.urls: Likewise.
1466         * config/arm/arm.opt.urls: Likewise.
1467         * config/arm/vxworks.opt.urls: Likewise.
1468         * config/avr/avr.opt.urls: Likewise.
1469         * config/bpf/bpf.opt.urls: Likewise.
1470         * config/c6x/c6x-tables.opt.urls: Likewise.
1471         * config/c6x/c6x.opt.urls: Likewise.
1472         * config/cris/cris.opt.urls: Likewise.
1473         * config/cris/elf.opt.urls: Likewise.
1474         * config/csky/csky.opt.urls: Likewise.
1475         * config/csky/csky_tables.opt.urls: Likewise.
1476         * config/darwin.opt.urls: Likewise.
1477         * config/dragonfly.opt.urls: Likewise.
1478         * config/epiphany/epiphany.opt.urls: Likewise.
1479         * config/fr30/fr30.opt.urls: Likewise.
1480         * config/freebsd.opt.urls: Likewise.
1481         * config/frv/frv.opt.urls: Likewise.
1482         * config/ft32/ft32.opt.urls: Likewise.
1483         * config/fused-madd.opt.urls: Likewise.
1484         * config/g.opt.urls: Likewise.
1485         * config/gcn/gcn.opt.urls: Likewise.
1486         * config/gnu-user.opt.urls: Likewise.
1487         * config/h8300/h8300.opt.urls: Likewise.
1488         * config/hpux11.opt.urls: Likewise.
1489         * config/i386/cygming.opt.urls: Likewise.
1490         * config/i386/cygwin.opt.urls: Likewise.
1491         * config/i386/djgpp.opt.urls: Likewise.
1492         * config/i386/i386.opt.urls: Likewise.
1493         * config/i386/mingw-w64.opt.urls: Likewise.
1494         * config/i386/mingw.opt.urls: Likewise.
1495         * config/i386/nto.opt.urls: Likewise.
1496         * config/ia64/ia64.opt.urls: Likewise.
1497         * config/ia64/ilp32.opt.urls: Likewise.
1498         * config/ia64/vms.opt.urls: Likewise.
1499         * config/iq2000/iq2000.opt.urls: Likewise.
1500         * config/linux-android.opt.urls: Likewise.
1501         * config/linux.opt.urls: Likewise.
1502         * config/lm32/lm32.opt.urls: Likewise.
1503         * config/loongarch/loongarch.opt.urls: Likewise.
1504         * config/lynx.opt.urls: Likewise.
1505         * config/m32c/m32c.opt.urls: Likewise.
1506         * config/m32r/m32r.opt.urls: Likewise.
1507         * config/m68k/ieee.opt.urls: Likewise.
1508         * config/m68k/m68k-tables.opt.urls: Likewise.
1509         * config/m68k/m68k.opt.urls: Likewise.
1510         * config/m68k/uclinux.opt.urls: Likewise.
1511         * config/mcore/mcore.opt.urls: Likewise.
1512         * config/microblaze/microblaze.opt.urls: Likewise.
1513         * config/mips/mips-tables.opt.urls: Likewise.
1514         * config/mips/mips.opt.urls: Likewise.
1515         * config/mips/sde.opt.urls: Likewise.
1516         * config/mmix/mmix.opt.urls: Likewise.
1517         * config/mn10300/mn10300.opt.urls: Likewise.
1518         * config/moxie/moxie.opt.urls: Likewise.
1519         * config/msp430/msp430.opt.urls: Likewise.
1520         * config/nds32/nds32-elf.opt.urls: Likewise.
1521         * config/nds32/nds32-linux.opt.urls: Likewise.
1522         * config/nds32/nds32.opt.urls: Likewise.
1523         * config/netbsd-elf.opt.urls: Likewise.
1524         * config/netbsd.opt.urls: Likewise.
1525         * config/nios2/elf.opt.urls: Likewise.
1526         * config/nios2/nios2.opt.urls: Likewise.
1527         * config/nvptx/nvptx-gen.opt.urls: Likewise.
1528         * config/nvptx/nvptx.opt.urls: Likewise.
1529         * config/openbsd.opt.urls: Likewise.
1530         * config/or1k/elf.opt.urls: Likewise.
1531         * config/or1k/or1k.opt.urls: Likewise.
1532         * config/pa/pa-hpux.opt.urls: Likewise.
1533         * config/pa/pa-hpux1010.opt.urls: Likewise.
1534         * config/pa/pa-hpux1111.opt.urls: Likewise.
1535         * config/pa/pa-hpux1131.opt.urls: Likewise.
1536         * config/pa/pa.opt.urls: Likewise.
1537         * config/pa/pa64-hpux.opt.urls: Likewise.
1538         * config/pdp11/pdp11.opt.urls: Likewise.
1539         * config/pru/pru.opt.urls: Likewise.
1540         * config/riscv/riscv.opt.urls: Likewise.
1541         * config/rl78/rl78.opt.urls: Likewise.
1542         * config/rpath.opt.urls: Likewise.
1543         * config/rs6000/476.opt.urls: Likewise.
1544         * config/rs6000/aix64.opt.urls: Likewise.
1545         * config/rs6000/darwin.opt.urls: Likewise.
1546         * config/rs6000/linux64.opt.urls: Likewise.
1547         * config/rs6000/rs6000-tables.opt.urls: Likewise.
1548         * config/rs6000/rs6000.opt.urls: Likewise.
1549         * config/rs6000/sysv4.opt.urls: Likewise.
1550         * config/rtems.opt.urls: Likewise.
1551         * config/rx/elf.opt.urls: Likewise.
1552         * config/rx/rx.opt.urls: Likewise.
1553         * config/s390/s390.opt.urls: Likewise.
1554         * config/s390/tpf.opt.urls: Likewise.
1555         * config/sh/sh.opt.urls: Likewise.
1556         * config/sh/superh.opt.urls: Likewise.
1557         * config/sol2.opt.urls: Likewise.
1558         * config/sparc/long-double-switch.opt.urls: Likewise.
1559         * config/sparc/sparc.opt.urls: Likewise.
1560         * config/stormy16/stormy16.opt.urls: Likewise.
1561         * config/v850/v850.opt.urls: Likewise.
1562         * config/vax/elf.opt.urls: Likewise.
1563         * config/vax/vax.opt.urls: Likewise.
1564         * config/visium/visium.opt.urls: Likewise.
1565         * config/vms/vms.opt.urls: Likewise.
1566         * config/vxworks-smp.opt.urls: Likewise.
1567         * config/vxworks.opt.urls: Likewise.
1568         * config/xtensa/elf.opt.urls: Likewise.
1569         * config/xtensa/uclinux.opt.urls: Likewise.
1570         * config/xtensa/xtensa.opt.urls: Likewise.
1571         * config/bfin/bfin.opt.urls: New file.
1572
1573 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1574
1575         * Makefile.in (OPT_URLS_HTML_DEPS): New.
1576         (regenerate-opt-urls): New target.
1577         (regenerate-opt-urls-unit-test): New target.
1578         * doc/options.texi (Option properties): Add UrlSuffix and
1579         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
1580         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
1581         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
1582         and Makefile.in's OPT_URLS_HTML_DEPS.
1583         (Anatomy of a Target Back End): Add
1584         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
1585         * regenerate-opt-urls.py: New file.
1586
1587 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1588
1589         * diagnostic-format-sarif.cc
1590         (sarif_builder::make_logical_location_object): Convert to...
1591         (make_sarif_logical_location_object): ...this.
1592         (sarif_builder::set_any_logical_locs_arr): Update for above
1593         change.
1594         (sarif_builder::make_thread_flow_location_object): Call
1595         maybe_add_sarif_properties on each diagnostic_event.
1596         * diagnostic-format-sarif.h (class logical_location): New forward
1597         decl.
1598         (make_sarif_logical_location_object): New decl.
1599         * diagnostic-path.h (class sarif_object): New forward decl.
1600         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
1601
1602 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
1603             Patrick Lin  <patrick@andestech.com>
1604             Rufus Chen  <rufus@andestech.com>
1605             Monk Chiang  <monk.chiang@sifive.com>
1606
1607         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
1608         with Nan-boxing value.
1609         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
1610
1611 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
1612             Jeff Law  <jlaw@ventanamicro.com>
1613
1614         PR rtl-optimization/104914
1615         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
1616         a sign or zero extension is only required if the modified field
1617         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
1618         targets, don't refer to the temporarily incorrectly extended value
1619         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
1620
1621 2024-01-04  Pan Li  <pan2.li@intel.com>
1622
1623         Revert:
1624         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1625
1626         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1627
1628 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1629
1630         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1631
1632 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
1633
1634         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
1635         offset of fcsr.
1636
1637 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1638
1639         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
1640         (compute_nregs_for_mode): Refine LMUL.
1641         (max_number_of_live_regs): Ditto.
1642         (compute_estimated_lmul): Ditto.
1643         (has_unexpected_spills_p): Ditto.
1644
1645 2024-01-04  Li Wei  <liwei@loongson.cn>
1646
1647         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
1648         Remove useless forward declaration.
1649         (loongarch_is_even_extraction): Remove useless forward declaration.
1650         (loongarch_try_expand_lsx_vshuf_const): Removed.
1651         (loongarch_expand_vec_perm_const_1): Merged.
1652         (loongarch_is_double_duplicate): Removed.
1653         (loongarch_is_center_extraction): Ditto.
1654         (loongarch_is_reversing_permutation): Ditto.
1655         (loongarch_is_di_misalign_extract): Ditto.
1656         (loongarch_is_si_misalign_extract): Ditto.
1657         (loongarch_is_lasx_lowpart_extract): Ditto.
1658         (loongarch_is_op_reverse_perm): Ditto.
1659         (loongarch_is_single_op_perm): Ditto.
1660         (loongarch_is_divisible_perm): Ditto.
1661         (loongarch_is_triple_stride_extract): Ditto.
1662         (loongarch_expand_vec_perm_const_2): Merged.
1663         (loongarch_expand_vec_perm_const): New.
1664         (loongarch_vectorize_vec_perm_const): Adjust.
1665
1666 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
1667
1668         * omp-general.cc: Fix comment typos and misplaced/confusing
1669         comments.  Delete redundant include of omp-general.h.
1670
1671 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1672
1673         PR rtl-optimization/104914
1674         * config/mips/mips.md (insqisi_extended): New patterns.
1675         (inshisi_extended): Ditto.
1676
1677 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1678
1679         * config/mips/mips.cc (mips_insn_cost): New function.
1680
1681 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1682
1683         * config/mips/mips.md (perf_ratio): New attribute.
1684
1685 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1686
1687         PR target/113206
1688         PR target/113209
1689         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
1690         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
1691         blocks belong to infinite loop.
1692         (pre_vsetvl::emit_vsetvl): Remove fake edges.
1693         * config/riscv/t-riscv: Add a new include file.
1694
1695 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1696
1697         * config/riscv/vector.md: Fix indent.
1698
1699 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
1700
1701         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
1702         OMP_CLAUSE__SIMDUID_.
1703         * tree.cc (omp_clause_num_ops): Update position of entry for
1704         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
1705         (omp_clause_code_name): Likewise.
1706
1707 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
1708
1709         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
1710         printing of FUNC_MAP/IND_FUNC_MAP labels.
1711
1712 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
1713
1714         * gcc.cc (process_command): Update copyright notice dates.
1715         * gcov-dump.cc (print_version): Ditto.
1716         * gcov.cc (print_version): Ditto.
1717         * gcov-tool.cc (print_version): Ditto.
1718         * gengtype.cc (create_file): Ditto.
1719         * doc/cpp.texi: Bump @copying's copyright year.
1720         * doc/cppinternals.texi: Ditto.
1721         * doc/gcc.texi: Ditto.
1722         * doc/gccint.texi: Ditto.
1723         * doc/gcov.texi: Ditto.
1724         * doc/install.texi: Ditto.
1725         * doc/invoke.texi: Ditto.
1726
1727 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
1728
1729         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
1730         (fmin<mode>3): Likewise.
1731         (reduc_fmax_scal_<mode>3): New define_expand.
1732         (reduc_fmin_scal_<mode>3): Likewise.
1733
1734 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1735
1736         PR target/113112
1737         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
1738         (max_number_of_live_regs): Ditto.
1739         (has_unexpected_spills_p): Ditto.
1740
1741 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
1742             Jin Ma  <jinma@linux.alibaba.com>
1743             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
1744             Christoph Müllner  <christoph.muellner@vrull.eu>
1745
1746         * config/riscv/vector.md:
1747         Use vector_length_operand for vsetvl patterns.
1748
1749 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1750
1751         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
1752         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
1753
1754 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
1755
1756         * config/aarch64/aarch64-tuning-flags.def
1757         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
1758         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
1759         * config/aarch64/aarch64.cc
1760         (aarch64_override_options_internal): Set
1761         param_fully_pipelined_fma according to tuning option.
1762         * config/aarch64/tuning_models/ampere1.h: Add
1763         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
1764         * config/aarch64/tuning_models/ampere1a.h: Likewise.
1765         * config/aarch64/tuning_models/ampere1b.h: Likewise.
1766
1767 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
1768
1769         * config/riscv/vector-crypto.md: Modify copyright year.
1770
1771 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1772
1773         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
1774
1775 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
1776
1777         * config.in: Regenerate.
1778         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
1779         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
1780         Added TLS Le Relax support.
1781         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
1782         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
1783         * configure: Regenerate.
1784         * configure.ac: Check if binutils supports TLS le relax.
1785
1786 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
1787
1788         * config/riscv/iterators.md: Add rotate insn name.
1789         * config/riscv/riscv.md: Add new insns name for crypto vector.
1790         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
1791         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
1792         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
1793
1794 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1795
1796         PR target/113112
1797         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
1798         pointer type liveness count.
1799 \f
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