gcc/testsuite/gcc.target/i386/vect-div-1.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -fno-common -msse2" } */
   3
   4 unsigned short b[1024] = { 0 };
   5 int a[1024] = { 0 };
   6
   7 int
   8 f1 (int x)
   9 {
  10   int i;
  11   for (i = 0; i < 1024; i++)
  12     a[i] = (b[i] + 7) / 15;
  13 }
  14
  15 int
  16 f2 (int x)
  17 {
  18   int i;
  19   for (i = 0; i < 1024; i++)
  20     a[i] = (b[i] + 7) % 15;
  21 }
  22
  23 int
  24 f3 (int x)
  25 {
  26   int i;
  27   for (i = 0; i < 1024; i++)
  28     a[i] = (b[i] - 66000) / 15;
  29 }
  30
  31 int
  32 f4 (int x)
  33 {
  34   int i;
  35   for (i = 0; i < 1024; i++)
  36     a[i] = (b[i] - 66000) % 15;
  37 }
  38
  39 /* In f1 and f2, VRP can prove the first operand of division or modulo
  40    is always non-negative, so there is no need to do >> 31 shift
  41    etc. to check if it is.  And in f3 and f4, VRP can prove it is always
  42    negative.  */
  43 /* { dg-final { scan-assembler-not "psrad\[^\n\r\]*\\\$31" } } */