1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msse4 -mtune=generic" } */
4 /* We need SSE4 so the backend recognizes a { 0, 5, 2, 7 } constant
5 permutation as supported as the vectorizer wants to generate
7 vect__6.10_24 = vect__3.6_20 - vect__5.9_23;
8 vect__6.11_25 = vect__3.6_20 + vect__5.9_23;
9 _26 = VEC_PERM_EXPR <vect__6.10_24, vect__6.11_25, { 0, 5, 2, 7 }>;
11 See also the ??? comment about using and/andn/or in expand_vec_perm_blend
12 for non-SSE4 targets. */
14 void testf (float * __restrict__ p
, float * __restrict q
)
22 /* { dg-final { scan-assembler "addsubps" } } */