1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Changing spilled pseudos to stack memory or their equivalences;
41 o Allocation stack memory changes the address displacement and
42 new iteration is needed.
44 Here is block diagram of LRA passes:
46 ------------------------
47 --------------- | Undo inheritance for | ---------------
48 | Memory-memory | | spilled pseudos, | | New (and old) |
49 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
50 --------------- | the same hard regs, | | assignment |
51 Start | | and optional reloads | ---------------
52 | | ------------------------ ^
53 V | ---------------- |
54 ----------- V | Update virtual | |
55 | Remove |----> ------------>| register | |
56 | scratches | ^ | displacements | |
57 ----------- | ---------------- |
60 ---------------- No ------------ pseudos -------------------
61 | Spilled pseudo | change |Constraints:| or insns | Inheritance/split |
62 | to memory |<-------| RTL |--------->| transformations |
63 | substitution | | transfor- | | in EBB scope |
64 ---------------- | mations | -------------------
67 -------------------------
68 | Hard regs substitution, |
69 | devirtalization, and |------> Finish
70 | restoring scratches got |
72 -------------------------
74 To speed up the process:
75 o We process only insns affected by changes on previous
77 o We don't use DFA-infrastructure because it results in much slower
78 compiler speed than a special IR described below does;
79 o We use a special insn representation for quick access to insn
80 info which is always *synchronized* with the current RTL;
81 o Insn IR is minimized by memory. It is divided on three parts:
82 o one specific for each insn in RTL (only operand locations);
83 o one common for all insns in RTL with the same insn code
84 (different operand attributes from machine descriptions);
85 o one oriented for maintenance of live info (list of pseudos).
87 o all insns where the pseudo is referenced;
88 o live info (conflicting hard regs, live ranges, # of
90 o data used for assigning (preferred hard regs, costs etc).
92 This file contains LRA driver, LRA utility functions and data, and
93 code for dealing with scratches. */
97 #include "coretypes.h"
99 #include "hard-reg-set.h"
103 #include "insn-config.h"
104 #include "insn-codes.h"
107 #include "addresses.h"
110 #include "hash-set.h"
112 #include "machmode.h"
114 #include "function.h"
116 #include "basic-block.h"
118 #include "tree-pass.h"
125 /* Hard registers currently not available for allocation. It can
126 changed after some hard registers become not eliminable. */
127 HARD_REG_SET lra_no_alloc_regs
;
129 static int get_new_reg_value (void);
130 static void expand_reg_info (void);
131 static void invalidate_insn_recog_data (int);
132 static int get_insn_freq (rtx_insn
*);
133 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
136 /* Expand all regno related info needed for LRA. */
138 expand_reg_data (int old
)
142 ira_expand_reg_equiv ();
143 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
144 lra_change_class (i
, ALL_REGS
, " Set", true);
147 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
148 or of VOIDmode, use MD_MODE for the new reg. Initialize its
149 register class to RCLASS. Print message about assigning class
150 RCLASS containing new register name TITLE unless it is NULL. Use
151 attributes of ORIGINAL if it is a register. The created register
152 will have unique held value. */
154 lra_create_new_reg_with_unique_value (enum machine_mode md_mode
, rtx original
,
155 enum reg_class rclass
, const char *title
)
157 enum machine_mode mode
;
160 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
162 lra_assert (mode
!= VOIDmode
);
163 new_reg
= gen_reg_rtx (mode
);
164 if (original
== NULL_RTX
|| ! REG_P (original
))
166 if (lra_dump_file
!= NULL
)
167 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
171 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
172 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
173 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
174 REG_POINTER (new_reg
) = REG_POINTER (original
);
175 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
176 if (lra_dump_file
!= NULL
)
177 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
178 REGNO (new_reg
), REGNO (original
));
180 if (lra_dump_file
!= NULL
)
183 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
184 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
185 title
, REGNO (new_reg
));
186 fprintf (lra_dump_file
, "\n");
188 expand_reg_data (max_reg_num ());
189 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
193 /* Analogous to the previous function but also inherits value of
196 lra_create_new_reg (enum machine_mode md_mode
, rtx original
,
197 enum reg_class rclass
, const char *title
)
202 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
203 if (original
!= NULL_RTX
&& REG_P (original
))
204 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
208 /* Set up for REGNO unique hold value. */
210 lra_set_regno_unique_value (int regno
)
212 lra_reg_info
[regno
].val
= get_new_reg_value ();
215 /* Invalidate INSN related info used by LRA. The info should never be
218 lra_invalidate_insn_data (rtx_insn
*insn
)
220 lra_invalidate_insn_regno_info (insn
);
221 invalidate_insn_recog_data (INSN_UID (insn
));
224 /* Mark INSN deleted and invalidate the insn related info used by
227 lra_set_insn_deleted (rtx_insn
*insn
)
229 lra_invalidate_insn_data (insn
);
230 SET_INSN_DELETED (insn
);
233 /* Delete an unneeded INSN and any previous insns who sole purpose is
234 loading data that is dead in INSN. */
236 lra_delete_dead_insn (rtx_insn
*insn
)
238 rtx_insn
*prev
= prev_real_insn (insn
);
241 /* If the previous insn sets a register that dies in our insn,
243 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
244 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
245 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
246 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
247 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
248 lra_delete_dead_insn (prev
);
250 lra_set_insn_deleted (insn
);
253 /* Emit insn x = y + z. Return NULL if we failed to do it.
254 Otherwise, return the insn. We don't use gen_add3_insn as it might
257 emit_add3_insn (rtx x
, rtx y
, rtx z
)
261 last
= get_last_insn ();
263 if (have_addptr3_insn (x
, y
, z
))
265 rtx insn
= gen_addptr3_insn (x
, y
, z
);
267 /* If the target provides an "addptr" pattern it hopefully does
268 for a reason. So falling back to the normal add would be
270 lra_assert (insn
!= NULL_RTX
);
275 rtx_insn
*insn
= emit_insn (gen_rtx_SET (VOIDmode
, x
,
276 gen_rtx_PLUS (GET_MODE (y
), y
, z
)));
277 if (recog_memoized (insn
) < 0)
279 delete_insns_since (last
);
285 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
288 emit_add2_insn (rtx x
, rtx y
)
292 insn
= emit_add3_insn (x
, x
, y
);
293 if (insn
== NULL_RTX
)
295 insn
= gen_add2_insn (x
, y
);
296 if (insn
!= NULL_RTX
)
302 /* Target checks operands through operand predicates to recognize an
303 insn. We should have a special precaution to generate add insns
304 which are frequent results of elimination.
306 Emit insns for x = y + z. X can be used to store intermediate
307 values and should be not in Y and Z when we use X to store an
308 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
309 + disp] where base and index are registers, disp and scale are
310 constants. Y should contain base if it is present, Z should
311 contain disp if any. index[*scale] can be part of Y or Z. */
313 lra_emit_add (rtx x
, rtx y
, rtx z
)
317 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
320 rtx add3_insn
= emit_add3_insn (x
, y
, z
);
321 old
= max_reg_num ();
322 if (add3_insn
!= NULL
)
326 disp
= a2
= NULL_RTX
;
327 if (GET_CODE (y
) == PLUS
)
341 index_scale
= scale
= NULL_RTX
;
342 if (GET_CODE (a1
) == MULT
)
345 index
= XEXP (a1
, 0);
346 scale
= XEXP (a1
, 1);
349 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
352 index
= XEXP (a2
, 0);
353 scale
= XEXP (a2
, 1);
361 if (! (REG_P (base
) || GET_CODE (base
) == SUBREG
)
362 || (index
!= NULL_RTX
363 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
364 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
365 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
367 /* Probably we have no 3 op add. Last chance is to use 2-op
368 add insn. To succeed, don't move Z to X as an address
369 segment always comes in Y. Otherwise, we might fail when
370 adding the address segment to register. */
371 lra_assert (x
!= y
&& x
!= z
);
372 emit_move_insn (x
, y
);
373 rtx insn
= emit_add2_insn (x
, z
);
374 lra_assert (insn
!= NULL_RTX
);
378 if (index_scale
== NULL_RTX
)
380 if (disp
== NULL_RTX
)
382 /* Generate x = index_scale; x = x + base. */
383 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
384 emit_move_insn (x
, index_scale
);
385 rtx insn
= emit_add2_insn (x
, base
);
386 lra_assert (insn
!= NULL_RTX
);
388 else if (scale
== NULL_RTX
)
390 /* Try x = base + disp. */
391 lra_assert (base
!= NULL_RTX
);
392 last
= get_last_insn ();
393 rtx_insn
*move_insn
=
394 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
395 if (recog_memoized (move_insn
) < 0)
397 delete_insns_since (last
);
398 /* Generate x = disp; x = x + base. */
399 emit_move_insn (x
, disp
);
400 rtx add2_insn
= emit_add2_insn (x
, base
);
401 lra_assert (add2_insn
!= NULL_RTX
);
403 /* Generate x = x + index. */
404 if (index
!= NULL_RTX
)
406 rtx insn
= emit_add2_insn (x
, index
);
407 lra_assert (insn
!= NULL_RTX
);
412 /* Try x = index_scale; x = x + disp; x = x + base. */
413 last
= get_last_insn ();
414 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
416 if (recog_memoized (move_insn
) >= 0)
418 rtx insn
= emit_add2_insn (x
, disp
);
419 if (insn
!= NULL_RTX
)
421 insn
= emit_add2_insn (x
, disp
);
422 if (insn
!= NULL_RTX
)
428 delete_insns_since (last
);
429 /* Generate x = disp; x = x + base; x = x + index_scale. */
430 emit_move_insn (x
, disp
);
431 rtx insn
= emit_add2_insn (x
, base
);
432 lra_assert (insn
!= NULL_RTX
);
433 insn
= emit_add2_insn (x
, index_scale
);
434 lra_assert (insn
!= NULL_RTX
);
439 /* Functions emit_... can create pseudos -- so expand the pseudo
441 if (old
!= max_reg_num ())
442 expand_reg_data (old
);
445 /* The number of emitted reload insns so far. */
446 int lra_curr_reload_num
;
448 /* Emit x := y, processing special case when y = u + v or y = u + v *
449 scale + w through emit_add (Y can be an address which is base +
450 index reg * scale + displacement in general case). X may be used
451 as intermediate result therefore it should be not in Y. */
453 lra_emit_move (rtx x
, rtx y
)
457 if (GET_CODE (y
) != PLUS
)
459 if (rtx_equal_p (x
, y
))
461 old
= max_reg_num ();
462 emit_move_insn (x
, y
);
464 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
465 /* Function emit_move can create pseudos -- so expand the pseudo
467 if (old
!= max_reg_num ())
468 expand_reg_data (old
);
471 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
474 /* Update insn operands which are duplication of operands whose
475 numbers are in array of NOPS (with end marker -1). The insn is
476 represented by its LRA internal representation ID. */
478 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
481 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
483 for (i
= 0; i
< static_id
->n_dups
; i
++)
484 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
485 if (static_id
->dup_num
[i
] == nop
)
486 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
491 /* This page contains code dealing with info about registers in the
494 /* Pools for insn reg info. */
495 static alloc_pool insn_reg_pool
;
497 /* Initiate pool for insn reg info. */
499 init_insn_regs (void)
502 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg
), 100);
505 /* Create LRA insn related info about a reference to REGNO in INSN with
506 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
507 reference through subreg (SUBREG_P), flag that is early clobbered
508 in the insn (EARLY_CLOBBER), and reference to the next insn reg
510 static struct lra_insn_reg
*
511 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
512 enum machine_mode mode
,
513 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
515 struct lra_insn_reg
*ir
;
517 ir
= (struct lra_insn_reg
*) pool_alloc (insn_reg_pool
);
519 ir
->biggest_mode
= mode
;
520 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
521 && NONDEBUG_INSN_P (insn
))
522 lra_reg_info
[regno
].biggest_mode
= mode
;
523 ir
->subreg_p
= subreg_p
;
524 ir
->early_clobber
= early_clobber
;
530 /* Free insn reg info IR. */
532 free_insn_reg (struct lra_insn_reg
*ir
)
534 pool_free (insn_reg_pool
, ir
);
537 /* Free insn reg info list IR. */
539 free_insn_regs (struct lra_insn_reg
*ir
)
541 struct lra_insn_reg
*next_ir
;
543 for (; ir
!= NULL
; ir
= next_ir
)
550 /* Finish pool for insn reg info. */
552 finish_insn_regs (void)
554 free_alloc_pool (insn_reg_pool
);
559 /* This page contains code dealing LRA insn info (or in other words
560 LRA internal insn representation). */
562 /* Map INSN_CODE -> the static insn data. This info is valid during
563 all translation unit. */
564 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
566 /* Debug insns are represented as a special insn with one input
567 operand which is RTL expression in var_location. */
569 /* The following data are used as static insn operand data for all
570 debug insns. If structure lra_operand_data is changed, the
571 initializer should be changed too. */
572 static struct lra_operand_data debug_operand_data
=
574 NULL
, /* alternative */
575 VOIDmode
, /* We are not interesting in the operand mode. */
580 /* The following data are used as static insn data for all debug
581 insns. If structure lra_static_insn_data is changed, the
582 initializer should be changed too. */
583 static struct lra_static_insn_data debug_insn_static_data
=
586 0, /* Duplication operands #. */
587 -1, /* Commutative operand #. */
588 1, /* Operands #. There is only one operand which is debug RTL
590 0, /* Duplications #. */
591 0, /* Alternatives #. We are not interesting in alternatives
592 because we does not proceed debug_insns for reloads. */
593 NULL
, /* Hard registers referenced in machine description. */
594 NULL
/* Descriptions of operands in alternatives. */
597 /* Called once per compiler work to initialize some LRA data related
600 init_insn_code_data_once (void)
602 memset (insn_code_data
, 0, sizeof (insn_code_data
));
605 /* Called once per compiler work to finalize some LRA data related to
608 finish_insn_code_data_once (void)
612 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
614 if (insn_code_data
[i
] != NULL
)
615 free (insn_code_data
[i
]);
619 /* Return static insn data, allocate and setup if necessary. Although
620 dup_num is static data (it depends only on icode), to set it up we
621 need to extract insn first. So recog_data should be valid for
622 normal insn (ICODE >= 0) before the call. */
623 static struct lra_static_insn_data
*
624 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
626 struct lra_static_insn_data
*data
;
629 lra_assert (icode
< LAST_INSN_CODE
);
630 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
632 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
633 n_bytes
= sizeof (struct lra_static_insn_data
)
634 + sizeof (struct lra_operand_data
) * nop
635 + sizeof (int) * ndup
;
636 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
637 data
->operand_alternative
= NULL
;
638 data
->n_operands
= nop
;
640 data
->n_alternatives
= nalt
;
641 data
->operand
= ((struct lra_operand_data
*)
642 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
643 data
->dup_num
= ((int *) ((char *) data
->operand
644 + sizeof (struct lra_operand_data
) * nop
));
649 insn_code_data
[icode
] = data
;
650 for (i
= 0; i
< nop
; i
++)
652 data
->operand
[i
].constraint
653 = insn_data
[icode
].operand
[i
].constraint
;
654 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
655 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
656 data
->operand
[i
].is_operator
657 = insn_data
[icode
].operand
[i
].is_operator
;
658 data
->operand
[i
].type
659 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
660 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
662 data
->operand
[i
].is_address
= false;
664 for (i
= 0; i
< ndup
; i
++)
665 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
670 /* The current length of the following array. */
671 int lra_insn_recog_data_len
;
673 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
674 lra_insn_recog_data_t
*lra_insn_recog_data
;
676 /* Initialize LRA data about insns. */
678 init_insn_recog_data (void)
680 lra_insn_recog_data_len
= 0;
681 lra_insn_recog_data
= NULL
;
685 /* Expand, if necessary, LRA data about insns. */
687 check_and_expand_insn_recog_data (int index
)
691 if (lra_insn_recog_data_len
> index
)
693 old
= lra_insn_recog_data_len
;
694 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
695 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
697 lra_insn_recog_data_len
);
698 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
699 lra_insn_recog_data
[i
] = NULL
;
702 /* Finish LRA DATA about insn. */
704 free_insn_recog_data (lra_insn_recog_data_t data
)
706 if (data
->operand_loc
!= NULL
)
707 free (data
->operand_loc
);
708 if (data
->dup_loc
!= NULL
)
709 free (data
->dup_loc
);
710 if (data
->arg_hard_regs
!= NULL
)
711 free (data
->arg_hard_regs
);
712 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
714 if (data
->insn_static_data
->operand_alternative
!= NULL
)
715 free (const_cast <operand_alternative
*>
716 (data
->insn_static_data
->operand_alternative
));
717 free_insn_regs (data
->insn_static_data
->hard_regs
);
718 free (data
->insn_static_data
);
720 free_insn_regs (data
->regs
);
725 /* Finish LRA data about all insns. */
727 finish_insn_recog_data (void)
730 lra_insn_recog_data_t data
;
732 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
733 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
734 free_insn_recog_data (data
);
736 free (lra_insn_recog_data
);
739 /* Setup info about operands in alternatives of LRA DATA of insn. */
741 setup_operand_alternative (lra_insn_recog_data_t data
,
742 const operand_alternative
*op_alt
)
745 int icode
= data
->icode
;
746 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
748 static_data
->commutative
= -1;
749 nop
= static_data
->n_operands
;
750 nalt
= static_data
->n_alternatives
;
751 static_data
->operand_alternative
= op_alt
;
752 for (i
= 0; i
< nop
; i
++)
754 static_data
->operand
[i
].early_clobber
= false;
755 static_data
->operand
[i
].is_address
= false;
756 if (static_data
->operand
[i
].constraint
[0] == '%')
758 /* We currently only support one commutative pair of operands. */
759 if (static_data
->commutative
< 0)
760 static_data
->commutative
= i
;
762 lra_assert (icode
< 0); /* Asm */
763 /* The last operand should not be marked commutative. */
764 lra_assert (i
!= nop
- 1);
767 for (j
= 0; j
< nalt
; j
++)
768 for (i
= 0; i
< nop
; i
++, op_alt
++)
770 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
771 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
775 /* Recursively process X and collect info about registers, which are
776 not the insn operands, in X with TYPE (in/out/inout) and flag that
777 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
778 to LIST. X is a part of insn given by DATA. Return the result
780 static struct lra_insn_reg
*
781 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
782 struct lra_insn_reg
*list
,
783 enum op_type type
, bool early_clobber
)
785 int i
, j
, regno
, last
;
787 enum machine_mode mode
;
788 struct lra_insn_reg
*curr
;
790 enum rtx_code code
= GET_CODE (op
);
791 const char *fmt
= GET_RTX_FORMAT (code
);
793 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
794 if (x
== data
->operand_loc
[i
])
795 /* It is an operand loc. Stop here. */
797 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
798 if (x
== data
->dup_loc
[i
])
799 /* It is a dup loc. Stop here. */
801 mode
= GET_MODE (op
);
805 op
= SUBREG_REG (op
);
806 code
= GET_CODE (op
);
807 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
809 mode
= GET_MODE (op
);
810 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
816 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
818 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
821 if (! TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
822 || TEST_HARD_REG_BIT (eliminable_regset
, regno
))
824 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
825 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
826 && curr
->biggest_mode
== mode
)
828 if (curr
->type
!= type
)
829 curr
->type
= OP_INOUT
;
830 if (curr
->early_clobber
!= early_clobber
)
831 curr
->early_clobber
= true;
836 /* This is a new hard regno or the info can not be
837 integrated into the found structure. */
841 /* This clobber is to inform popping floating
843 && ! (FIRST_STACK_REG
<= regno
844 && regno
<= LAST_STACK_REG
));
846 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
847 early_clobber
, list
);
855 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
856 list
, OP_OUT
, false);
857 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
861 /* We treat clobber of non-operand hard registers as early
862 clobber (the behavior is expected from asm). */
863 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
866 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
867 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
868 list
, OP_INOUT
, false);
870 case PRE_MODIFY
: case POST_MODIFY
:
871 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
872 list
, OP_INOUT
, false);
873 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
877 fmt
= GET_RTX_FORMAT (code
);
878 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
881 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
883 else if (fmt
[i
] == 'E')
884 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
885 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
892 /* Set up and return info about INSN. Set up the info if it is not set up
894 lra_insn_recog_data_t
895 lra_set_insn_recog_data (rtx_insn
*insn
)
897 lra_insn_recog_data_t data
;
900 unsigned int uid
= INSN_UID (insn
);
901 struct lra_static_insn_data
*insn_static_data
;
903 check_and_expand_insn_recog_data (uid
);
904 if (DEBUG_INSN_P (insn
))
908 icode
= INSN_CODE (insn
);
910 /* It might be a new simple insn which is not recognized yet. */
911 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
913 data
= XNEW (struct lra_insn_recog_data
);
914 lra_insn_recog_data
[uid
] = data
;
916 data
->used_insn_alternative
= -1;
919 if (DEBUG_INSN_P (insn
))
921 data
->insn_static_data
= &debug_insn_static_data
;
922 data
->dup_loc
= NULL
;
923 data
->arg_hard_regs
= NULL
;
924 data
->enabled_alternatives
= ALL_ALTERNATIVES
;
925 data
->operand_loc
= XNEWVEC (rtx
*, 1);
926 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
932 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
933 const char *constraints
[MAX_RECOG_OPERANDS
];
935 nop
= asm_noperands (PATTERN (insn
));
936 data
->operand_loc
= data
->dup_loc
= NULL
;
940 /* It is a special insn like USE or CLOBBER. We should
941 recognize any regular insn otherwise LRA can do nothing
943 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
944 || GET_CODE (PATTERN (insn
)) == CLOBBER
945 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
946 data
->insn_static_data
= insn_static_data
947 = get_static_insn_data (-1, 0, 0, nalt
);
951 /* expand_asm_operands makes sure there aren't too many
953 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
955 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
956 /* Now get the operand values and constraints out of the
958 decode_asm_operands (PATTERN (insn
), NULL
,
960 constraints
, operand_mode
, NULL
);
963 const char *p
= recog_data
.constraints
[0];
965 for (p
= constraints
[0]; *p
; p
++)
968 data
->insn_static_data
= insn_static_data
969 = get_static_insn_data (-1, nop
, 0, nalt
);
970 for (i
= 0; i
< nop
; i
++)
972 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
973 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
974 insn_static_data
->operand
[i
].strict_low
= false;
975 insn_static_data
->operand
[i
].is_operator
= false;
976 insn_static_data
->operand
[i
].is_address
= false;
979 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
980 insn_static_data
->operand
[i
].type
981 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
982 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
984 data
->enabled_alternatives
= ALL_ALTERNATIVES
;
987 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
989 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
990 setup_operand_alternative (data
, op_alt
);
996 data
->insn_static_data
= insn_static_data
997 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
998 insn_data
[icode
].n_dups
,
999 insn_data
[icode
].n_alternatives
);
1000 n
= insn_static_data
->n_operands
;
1005 locs
= XNEWVEC (rtx
*, n
);
1006 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1008 data
->operand_loc
= locs
;
1009 n
= insn_static_data
->n_dups
;
1014 locs
= XNEWVEC (rtx
*, n
);
1015 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1017 data
->dup_loc
= locs
;
1018 data
->enabled_alternatives
= get_enabled_alternatives (insn
);
1019 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1020 if (!insn_static_data
->operand_alternative
)
1021 setup_operand_alternative (data
, op_alt
);
1022 else if (op_alt
!= insn_static_data
->operand_alternative
)
1023 insn_static_data
->operand_alternative
= op_alt
;
1025 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1026 insn_static_data
->hard_regs
= NULL
;
1028 insn_static_data
->hard_regs
1029 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1030 NULL
, OP_IN
, false);
1031 data
->arg_hard_regs
= NULL
;
1035 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1038 /* Finding implicit hard register usage. We believe it will be
1039 not changed whatever transformations are used. Call insns
1040 are such example. */
1041 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1043 link
= XEXP (link
, 1))
1044 if (GET_CODE (XEXP (link
, 0)) == USE
1045 && REG_P (XEXP (XEXP (link
, 0), 0)))
1047 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1048 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1049 /* It is an argument register. */
1050 for (i
= (hard_regno_nregs
1051 [regno
][GET_MODE (XEXP (XEXP (link
, 0), 0))]) - 1;
1054 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1056 if (n_hard_regs
!= 0)
1058 arg_hard_regs
[n_hard_regs
++] = -1;
1059 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1060 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1061 sizeof (int) * n_hard_regs
);
1064 /* Some output operand can be recognized only from the context not
1065 from the constraints which are empty in this case. Call insn may
1066 contain a hard register in set destination with empty constraint
1067 and extract_insn treats them as an input. */
1068 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1072 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1074 /* ??? Should we treat 'X' the same way. It looks to me that
1075 'X' means anything and empty constraint means we do not
1077 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1078 || operand
->is_operator
)
1080 pat
= PATTERN (insn
);
1081 if (GET_CODE (pat
) == SET
)
1083 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1086 else if (GET_CODE (pat
) == PARALLEL
)
1088 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1090 set
= XVECEXP (PATTERN (insn
), 0, j
);
1091 if (GET_CODE (set
) == SET
1092 && &SET_DEST (set
) == data
->operand_loc
[i
])
1100 operand
->type
= OP_OUT
;
1105 /* Return info about insn give by UID. The info should be already set
1107 static lra_insn_recog_data_t
1108 get_insn_recog_data_by_uid (int uid
)
1110 lra_insn_recog_data_t data
;
1112 data
= lra_insn_recog_data
[uid
];
1113 lra_assert (data
!= NULL
);
1117 /* Invalidate all info about insn given by its UID. */
1119 invalidate_insn_recog_data (int uid
)
1121 lra_insn_recog_data_t data
;
1123 data
= lra_insn_recog_data
[uid
];
1124 lra_assert (data
!= NULL
);
1125 free_insn_recog_data (data
);
1126 lra_insn_recog_data
[uid
] = NULL
;
1129 /* Update all the insn info about INSN. It is usually called when
1130 something in the insn was changed. Return the updated info. */
1131 lra_insn_recog_data_t
1132 lra_update_insn_recog_data (rtx_insn
*insn
)
1134 lra_insn_recog_data_t data
;
1136 unsigned int uid
= INSN_UID (insn
);
1137 struct lra_static_insn_data
*insn_static_data
;
1138 HOST_WIDE_INT sp_offset
= 0;
1140 check_and_expand_insn_recog_data (uid
);
1141 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1142 && data
->icode
!= INSN_CODE (insn
))
1144 sp_offset
= data
->sp_offset
;
1145 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1146 invalidate_insn_recog_data (uid
);
1151 data
= lra_get_insn_recog_data (insn
);
1152 /* Initiate or restore SP offset. */
1153 data
->sp_offset
= sp_offset
;
1156 insn_static_data
= data
->insn_static_data
;
1157 data
->used_insn_alternative
= -1;
1158 if (DEBUG_INSN_P (insn
))
1160 if (data
->icode
< 0)
1163 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1164 const char *constraints
[MAX_RECOG_OPERANDS
];
1166 nop
= asm_noperands (PATTERN (insn
));
1169 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1170 /* Now get the operand values and constraints out of the
1172 decode_asm_operands (PATTERN (insn
), NULL
,
1174 constraints
, operand_mode
, NULL
);
1175 #ifdef ENABLE_CHECKING
1179 for (i
= 0; i
< nop
; i
++)
1181 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1182 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1183 && ! insn_static_data
->operand
[i
].is_operator
);
1187 #ifdef ENABLE_CHECKING
1191 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1193 (insn_static_data
->operand
[i
].type
1194 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1195 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1202 insn_extract (insn
);
1203 n
= insn_static_data
->n_operands
;
1205 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1206 n
= insn_static_data
->n_dups
;
1208 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1209 #if HAVE_ATTR_enabled
1210 #ifdef ENABLE_CHECKING
1213 alternative_mask enabled
;
1215 n
= insn_static_data
->n_alternatives
;
1216 enabled
= data
->enabled_alternatives
;
1217 lra_assert (n
>= 0);
1218 /* Cache the insn to prevent extract_insn call from
1219 get_attr_enabled. */
1220 recog_data
.insn
= insn
;
1221 for (i
= 0; i
< n
; i
++)
1223 which_alternative
= i
;
1224 lra_assert (TEST_BIT (enabled
, i
)
1225 == (bool) get_attr_enabled (insn
));
1234 /* Set up that INSN is using alternative ALT now. */
1236 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1238 lra_insn_recog_data_t data
;
1240 data
= lra_get_insn_recog_data (insn
);
1241 data
->used_insn_alternative
= alt
;
1244 /* Set up that insn with UID is using alternative ALT now. The insn
1245 info should be already set up. */
1247 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1249 lra_insn_recog_data_t data
;
1251 check_and_expand_insn_recog_data (uid
);
1252 data
= lra_insn_recog_data
[uid
];
1253 lra_assert (data
!= NULL
);
1254 data
->used_insn_alternative
= alt
;
1259 /* This page contains code dealing with common register info and
1262 /* The size of the following array. */
1263 static int reg_info_size
;
1264 /* Common info about each register. */
1265 struct lra_reg
*lra_reg_info
;
1267 /* Last register value. */
1268 static int last_reg_value
;
1270 /* Return new register value. */
1272 get_new_reg_value (void)
1274 return ++last_reg_value
;
1277 /* Pools for copies. */
1278 static alloc_pool copy_pool
;
1280 /* Vec referring to pseudo copies. */
1281 static vec
<lra_copy_t
> copy_vec
;
1283 /* Initialize I-th element of lra_reg_info. */
1285 initialize_lra_reg_info_element (int i
)
1287 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1289 lra_reg_info
[i
].no_stack_p
= false;
1291 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1292 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1293 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1294 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1295 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1296 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1297 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1298 lra_reg_info
[i
].live_ranges
= NULL
;
1299 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1300 lra_reg_info
[i
].last_reload
= 0;
1301 lra_reg_info
[i
].restore_regno
= -1;
1302 lra_reg_info
[i
].val
= get_new_reg_value ();
1303 lra_reg_info
[i
].offset
= 0;
1304 lra_reg_info
[i
].copies
= NULL
;
1307 /* Initialize common reg info and copies. */
1309 init_reg_info (void)
1314 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1315 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1316 for (i
= 0; i
< reg_info_size
; i
++)
1317 initialize_lra_reg_info_element (i
);
1319 = create_alloc_pool ("lra copies", sizeof (struct lra_copy
), 100);
1320 copy_vec
.create (100);
1324 /* Finish common reg info and copies. */
1326 finish_reg_info (void)
1330 for (i
= 0; i
< reg_info_size
; i
++)
1331 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1332 free (lra_reg_info
);
1334 free_alloc_pool (copy_pool
);
1335 copy_vec
.release ();
1338 /* Expand common reg info if it is necessary. */
1340 expand_reg_info (void)
1342 int i
, old
= reg_info_size
;
1344 if (reg_info_size
> max_reg_num ())
1346 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1347 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1348 for (i
= old
; i
< reg_info_size
; i
++)
1349 initialize_lra_reg_info_element (i
);
1352 /* Free all copies. */
1354 lra_free_copies (void)
1358 while (copy_vec
.length () != 0)
1360 cp
= copy_vec
.pop ();
1361 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1362 pool_free (copy_pool
, cp
);
1366 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1367 frequency is FREQ. */
1369 lra_create_copy (int regno1
, int regno2
, int freq
)
1374 lra_assert (regno1
!= regno2
);
1375 regno1_dest_p
= true;
1376 if (regno1
> regno2
)
1380 regno1_dest_p
= false;
1384 cp
= (lra_copy_t
) pool_alloc (copy_pool
);
1385 copy_vec
.safe_push (cp
);
1386 cp
->regno1_dest_p
= regno1_dest_p
;
1388 cp
->regno1
= regno1
;
1389 cp
->regno2
= regno2
;
1390 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1391 lra_reg_info
[regno1
].copies
= cp
;
1392 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1393 lra_reg_info
[regno2
].copies
= cp
;
1394 if (lra_dump_file
!= NULL
)
1395 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1396 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1399 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1402 lra_get_copy (int n
)
1404 if (n
>= (int) copy_vec
.length ())
1411 /* This page contains code dealing with info about registers in
1414 /* Process X of insn UID recursively and add info (operand type is
1415 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1416 about registers in X to the insn DATA. */
1418 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1419 enum op_type type
, bool early_clobber
)
1423 enum machine_mode mode
;
1426 struct lra_insn_reg
*curr
;
1428 code
= GET_CODE (x
);
1429 mode
= GET_MODE (x
);
1431 if (GET_CODE (x
) == SUBREG
)
1434 code
= GET_CODE (x
);
1435 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1437 mode
= GET_MODE (x
);
1438 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1445 if (regno
< FIRST_PSEUDO_REGISTER
1446 && TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
1447 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
1450 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1452 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1453 early_clobber
, data
->regs
);
1458 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1459 if (curr
->regno
== regno
)
1461 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1462 /* The info can not be integrated into the found
1464 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1465 subreg_p
, early_clobber
,
1469 if (curr
->type
!= type
)
1470 curr
->type
= OP_INOUT
;
1471 if (curr
->early_clobber
!= early_clobber
)
1472 curr
->early_clobber
= true;
1483 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1484 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1487 /* We treat clobber of non-operand hard registers as early
1488 clobber (the behavior is expected from asm). */
1489 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1491 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1492 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1494 case PRE_MODIFY
: case POST_MODIFY
:
1495 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1496 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1499 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1500 /* Some targets place small structures in registers for return
1501 values of functions, and those registers are wrapped in
1502 PARALLEL that we may see as the destination of a SET. Here
1505 (call_insn 13 12 14 2 (set (parallel:BLK [
1506 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1508 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1509 (const_int 8 [0x8]))
1511 (call (mem:QI (symbol_ref:DI (... */
1513 fmt
= GET_RTX_FORMAT (code
);
1514 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1517 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1518 else if (fmt
[i
] == 'E')
1520 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1521 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1528 /* Return execution frequency of INSN. */
1530 get_insn_freq (rtx_insn
*insn
)
1532 basic_block bb
= BLOCK_FOR_INSN (insn
);
1534 gcc_checking_assert (bb
!= NULL
);
1535 return REG_FREQ_FROM_BB (bb
);
1538 /* Invalidate all reg info of INSN with DATA and execution frequency
1539 FREQ. Update common info about the invalidated registers. */
1541 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1547 struct lra_insn_reg
*ir
, *next_ir
;
1549 uid
= INSN_UID (insn
);
1550 debug_p
= DEBUG_INSN_P (insn
);
1551 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1556 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1557 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1559 lra_reg_info
[i
].nrefs
--;
1560 lra_reg_info
[i
].freq
-= freq
;
1561 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1567 /* Invalidate all reg info of INSN. Update common info about the
1568 invalidated registers. */
1570 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1572 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1573 get_insn_freq (insn
));
1576 /* Update common reg info from reg info of insn given by its DATA and
1577 execution frequency FREQ. */
1579 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1582 struct lra_insn_reg
*ir
;
1584 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1585 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1587 lra_reg_info
[i
].nrefs
++;
1588 lra_reg_info
[i
].freq
+= freq
;
1592 /* Set up insn reg info of INSN. Update common reg info from reg info
1595 lra_update_insn_regno_info (rtx_insn
*insn
)
1598 lra_insn_recog_data_t data
;
1599 struct lra_static_insn_data
*static_data
;
1602 if (! INSN_P (insn
))
1604 data
= lra_get_insn_recog_data (insn
);
1605 static_data
= data
->insn_static_data
;
1606 freq
= get_insn_freq (insn
);
1607 invalidate_insn_data_regno_info (data
, insn
, freq
);
1608 uid
= INSN_UID (insn
);
1609 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1610 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1611 static_data
->operand
[i
].type
,
1612 static_data
->operand
[i
].early_clobber
);
1613 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1614 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1615 code
== USE
? OP_IN
: OP_OUT
, false);
1616 if (NONDEBUG_INSN_P (insn
))
1617 setup_insn_reg_info (data
, freq
);
1620 /* Return reg info of insn given by it UID. */
1621 struct lra_insn_reg
*
1622 lra_get_insn_regs (int uid
)
1624 lra_insn_recog_data_t data
;
1626 data
= get_insn_recog_data_by_uid (uid
);
1632 /* This page contains code dealing with stack of the insns which
1633 should be processed by the next constraint pass. */
1635 /* Bitmap used to put an insn on the stack only in one exemplar. */
1636 static sbitmap lra_constraint_insn_stack_bitmap
;
1638 /* The stack itself. */
1639 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1641 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1642 info for INSN, otherwise only update it if INSN is not already on the
1645 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1647 unsigned int uid
= INSN_UID (insn
);
1649 lra_update_insn_regno_info (insn
);
1650 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1651 lra_constraint_insn_stack_bitmap
=
1652 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1653 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1655 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1656 if (! always_update
)
1657 lra_update_insn_regno_info (insn
);
1658 lra_constraint_insn_stack
.safe_push (insn
);
1661 /* Put INSN on the stack. */
1663 lra_push_insn (rtx_insn
*insn
)
1665 lra_push_insn_1 (insn
, false);
1668 /* Put INSN on the stack and update its reg info. */
1670 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1672 lra_push_insn_1 (insn
, true);
1675 /* Put insn with UID on the stack. */
1677 lra_push_insn_by_uid (unsigned int uid
)
1679 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1682 /* Take the last-inserted insns off the stack and return it. */
1686 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1687 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1691 /* Return the current size of the insn stack. */
1693 lra_insn_stack_length (void)
1695 return lra_constraint_insn_stack
.length ();
1698 /* Push insns FROM to TO (excluding it) going in reverse order. */
1700 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1704 if (from
== NULL_RTX
)
1706 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1708 lra_push_insn (insn
);
1711 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1712 taken from the next BB insn after LAST or zero if there in such
1715 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1717 rtx_insn
*before
= next_nonnote_insn_bb (last
);
1718 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1719 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1721 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1722 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1725 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1726 insns onto the stack. Print about emitting the insns with
1729 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1734 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1736 if (lra_dump_file
!= NULL
)
1738 dump_insn_slim (lra_dump_file
, insn
);
1739 if (before
!= NULL_RTX
)
1741 fprintf (lra_dump_file
," %s before:\n", title
);
1742 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1744 if (after
!= NULL_RTX
)
1746 fprintf (lra_dump_file
, " %s after:\n", title
);
1747 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1749 fprintf (lra_dump_file
, "\n");
1751 if (before
!= NULL_RTX
)
1753 emit_insn_before (before
, insn
);
1754 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1755 setup_sp_offset (before
, PREV_INSN (insn
));
1757 if (after
!= NULL_RTX
)
1759 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1761 emit_insn_after (after
, insn
);
1762 push_insns (last
, insn
);
1763 setup_sp_offset (after
, last
);
1769 /* This page contains code dealing with scratches (changing them onto
1770 pseudos and restoring them from the pseudos).
1772 We change scratches into pseudos at the beginning of LRA to
1773 simplify dealing with them (conflicts, hard register assignments).
1775 If the pseudo denoting scratch was spilled it means that we do need
1776 a hard register for it. Such pseudos are transformed back to
1777 scratches at the end of LRA. */
1779 /* Description of location of a former scratch operand. */
1782 rtx_insn
*insn
; /* Insn where the scratch was. */
1783 int nop
; /* Number of the operand which was a scratch. */
1786 typedef struct sloc
*sloc_t
;
1788 /* Locations of the former scratches. */
1789 static vec
<sloc_t
> scratches
;
1791 /* Bitmap of scratch regnos. */
1792 static bitmap_head scratch_bitmap
;
1794 /* Bitmap of scratch operands. */
1795 static bitmap_head scratch_operand_bitmap
;
1797 /* Return true if pseudo REGNO is made of SCRATCH. */
1799 lra_former_scratch_p (int regno
)
1801 return bitmap_bit_p (&scratch_bitmap
, regno
);
1804 /* Return true if the operand NOP of INSN is a former scratch. */
1806 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
1808 return bitmap_bit_p (&scratch_operand_bitmap
,
1809 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1812 /* Change scratches onto pseudos and save their location. */
1814 remove_scratches (void)
1817 bool insn_changed_p
;
1822 lra_insn_recog_data_t id
;
1823 struct lra_static_insn_data
*static_id
;
1825 scratches
.create (get_max_uid ());
1826 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1827 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1828 FOR_EACH_BB_FN (bb
, cfun
)
1829 FOR_BB_INSNS (bb
, insn
)
1832 id
= lra_get_insn_recog_data (insn
);
1833 static_id
= id
->insn_static_data
;
1834 insn_changed_p
= false;
1835 for (i
= 0; i
< static_id
->n_operands
; i
++)
1836 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1837 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1839 insn_changed_p
= true;
1840 *id
->operand_loc
[i
] = reg
1841 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1842 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1843 add_reg_note (insn
, REG_UNUSED
, reg
);
1844 lra_update_dup (id
, i
);
1845 loc
= XNEW (struct sloc
);
1848 scratches
.safe_push (loc
);
1849 bitmap_set_bit (&scratch_bitmap
, REGNO (*id
->operand_loc
[i
]));
1850 bitmap_set_bit (&scratch_operand_bitmap
,
1851 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ i
);
1852 if (lra_dump_file
!= NULL
)
1853 fprintf (lra_dump_file
,
1854 "Removing SCRATCH in insn #%u (nop %d)\n",
1855 INSN_UID (insn
), i
);
1858 /* Because we might use DF right after caller-saves sub-pass
1859 we need to keep DF info up to date. */
1860 df_insn_rescan (insn
);
1864 /* Changes pseudos created by function remove_scratches onto scratches. */
1866 restore_scratches (void)
1871 rtx_insn
*last
= NULL
;
1872 lra_insn_recog_data_t id
= NULL
;
1874 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1876 if (last
!= loc
->insn
)
1879 id
= lra_get_insn_recog_data (last
);
1881 if (REG_P (*id
->operand_loc
[loc
->nop
])
1882 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
1883 >= FIRST_PSEUDO_REGISTER
)
1884 && lra_get_regno_hard_regno (regno
) < 0)
1886 /* It should be only case when scratch register with chosen
1887 constraint 'X' did not get memory or hard register. */
1888 lra_assert (lra_former_scratch_p (regno
));
1889 *id
->operand_loc
[loc
->nop
]
1890 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
1891 lra_update_dup (id
, loc
->nop
);
1892 if (lra_dump_file
!= NULL
)
1893 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
1894 INSN_UID (loc
->insn
), loc
->nop
);
1897 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1899 scratches
.release ();
1900 bitmap_clear (&scratch_bitmap
);
1901 bitmap_clear (&scratch_operand_bitmap
);
1906 #ifdef ENABLE_CHECKING
1908 /* Function checks RTL for correctness. If FINAL_P is true, it is
1909 done at the end of LRA and the check is more rigorous. */
1911 check_rtl (bool final_p
)
1916 lra_assert (! final_p
|| reload_completed
);
1917 FOR_EACH_BB_FN (bb
, cfun
)
1918 FOR_BB_INSNS (bb
, insn
)
1919 if (NONDEBUG_INSN_P (insn
)
1920 && GET_CODE (PATTERN (insn
)) != USE
1921 && GET_CODE (PATTERN (insn
)) != CLOBBER
1922 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
1926 extract_insn (insn
);
1927 lra_assert (constrain_operands (1));
1930 /* LRA code is based on assumption that all addresses can be
1931 correctly decomposed. LRA can generate reloads for
1932 decomposable addresses. The decomposition code checks the
1933 correctness of the addresses. So we don't need to check
1934 the addresses here. Don't call insn_invalid_p here, it can
1935 change the code at this stage. */
1936 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
1937 fatal_insn_not_found (insn
);
1940 #endif /* #ifdef ENABLE_CHECKING */
1942 /* Determine if the current function has an exception receiver block
1943 that reaches the exit block via non-exceptional edges */
1945 has_nonexceptional_receiver (void)
1949 basic_block
*tos
, *worklist
, bb
;
1951 /* If we're not optimizing, then just err on the safe side. */
1955 /* First determine which blocks can reach exit via normal paths. */
1956 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
1958 FOR_EACH_BB_FN (bb
, cfun
)
1959 bb
->flags
&= ~BB_REACHABLE
;
1961 /* Place the exit block on our worklist. */
1962 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
1963 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
1965 /* Iterate: find everything reachable from what we've already seen. */
1966 while (tos
!= worklist
)
1970 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
1971 if (e
->flags
& EDGE_ABNORMAL
)
1978 basic_block src
= e
->src
;
1980 if (!(src
->flags
& BB_REACHABLE
))
1982 src
->flags
|= BB_REACHABLE
;
1988 /* No exceptional block reached exit unexceptionally. */
1994 /* Process recursively X of INSN and add REG_INC notes if necessary. */
1996 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
1998 enum rtx_code code
= GET_CODE (x
);
2002 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2004 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2008 /* Scan all X sub-expressions. */
2009 fmt
= GET_RTX_FORMAT (code
);
2010 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2013 add_auto_inc_notes (insn
, XEXP (x
, i
));
2014 else if (fmt
[i
] == 'E')
2015 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2016 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2022 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2023 We change pseudos by hard registers without notification of DF and
2024 that can make the notes obsolete. DF-infrastructure does not deal
2025 with REG_INC notes -- so we should regenerate them here. */
2027 update_inc_notes (void)
2033 FOR_EACH_BB_FN (bb
, cfun
)
2034 FOR_BB_INSNS (bb
, insn
)
2035 if (NONDEBUG_INSN_P (insn
))
2037 pnote
= ®_NOTES (insn
);
2040 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2041 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2042 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2043 *pnote
= XEXP (*pnote
, 1);
2045 pnote
= &XEXP (*pnote
, 1);
2048 add_auto_inc_notes (insn
, PATTERN (insn
));
2053 /* Set to 1 while in lra. */
2054 int lra_in_progress
;
2056 /* Start of pseudo regnos before the LRA. */
2057 int lra_new_regno_start
;
2059 /* Start of reload pseudo regnos before the new spill pass. */
2060 int lra_constraint_new_regno_start
;
2062 /* Inheritance pseudo regnos before the new spill pass. */
2063 bitmap_head lra_inheritance_pseudos
;
2065 /* Split regnos before the new spill pass. */
2066 bitmap_head lra_split_regs
;
2068 /* Reload pseudo regnos before the new assignmnet pass which still can
2069 be spilled after the assinment pass as memory is also accepted in
2070 insns for the reload pseudos. */
2071 bitmap_head lra_optional_reload_pseudos
;
2073 /* Pseudo regnos used for subreg reloads before the new assignment
2074 pass. Such pseudos still can be spilled after the assinment
2076 bitmap_head lra_subreg_reload_pseudos
;
2078 /* First UID of insns generated before a new spill pass. */
2079 int lra_constraint_new_insn_uid_start
;
2081 /* File used for output of LRA debug information. */
2082 FILE *lra_dump_file
;
2084 /* True if we should try spill into registers of different classes
2085 instead of memory. */
2086 bool lra_reg_spill_p
;
2088 /* Set up value LRA_REG_SPILL_P. */
2090 setup_reg_spill_flag (void)
2094 if (targetm
.spill_class
!= NULL
)
2095 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2096 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2097 if (targetm
.spill_class ((enum reg_class
) cl
,
2098 (enum machine_mode
) mode
) != NO_REGS
)
2100 lra_reg_spill_p
= true;
2103 lra_reg_spill_p
= false;
2106 /* True if the current function is too big to use regular algorithms
2107 in LRA. In other words, we should use simpler and faster algorithms
2108 in LRA. It also means we should not worry about generation code
2109 for caller saves. The value is set up in IRA. */
2112 /* Major LRA entry function. F is a file should be used to dump LRA
2118 bool live_p
, scratch_p
, inserted_p
;
2122 timevar_push (TV_LRA
);
2124 /* Make sure that the last insn is a note. Some subsequent passes
2126 emit_note (NOTE_INSN_DELETED
);
2128 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2133 init_insn_recog_data ();
2135 #ifdef ENABLE_CHECKING
2136 /* Some quick check on RTL generated by previous passes. */
2140 lra_in_progress
= 1;
2142 /* The enable attributes can change their values as LRA starts
2143 although it is a bad practice. To prevent reuse of the outdated
2144 values, clear them. */
2147 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2148 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2149 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2151 setup_reg_spill_flag ();
2153 /* Function remove_scratches can creates new pseudos for clobbers --
2154 so set up lra_constraint_new_regno_start before its call to
2155 permit changing reg classes for pseudos created by this
2157 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2158 remove_scratches ();
2159 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2161 /* A function that has a non-local label that can reach the exit
2162 block via non-exceptional paths must save all call-saved
2164 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2165 crtl
->saves_all_registers
= 1;
2167 if (crtl
->saves_all_registers
)
2168 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2169 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2170 df_set_regs_ever_live (i
, true);
2172 /* We don't DF from now and avoid its using because it is to
2173 expensive when a lot of RTL changes are made. */
2174 df_set_flags (DF_NO_INSN_RESCAN
);
2175 lra_constraint_insn_stack
.create (get_max_uid ());
2176 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2177 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2178 lra_live_ranges_init ();
2179 lra_constraints_init ();
2180 lra_curr_reload_num
= 0;
2181 push_insns (get_last_insn (), NULL
);
2182 /* It is needed for the 1st coalescing. */
2183 lra_constraint_new_insn_uid_start
= get_max_uid ();
2184 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2185 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2186 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2187 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2189 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2190 /* If we have a stack frame, we must align it now. The stack size
2191 may be a part of the offset computation for register
2193 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2199 /* We should try to assign hard registers to scratches even
2200 if there were no RTL transformations in
2202 if (! lra_constraints (lra_constraint_iter
== 0)
2203 && (lra_constraint_iter
> 1
2204 || (! scratch_p
&& ! caller_save_needed
)))
2206 /* Constraint transformations may result in that eliminable
2207 hard regs become uneliminable and pseudos which use them
2208 should be spilled. It is better to do it before pseudo
2211 For example, rs6000 can make
2212 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2213 to use a constant pool. */
2214 lra_eliminate (false, false);
2215 /* Do inheritance only for regular algorithms. */
2218 if (flag_use_caller_save
)
2221 lra_clear_live_ranges ();
2222 /* As a side-effect of lra_create_live_ranges, we calculate
2223 actual_call_used_reg_set, which is needed during
2225 lra_create_live_ranges (true);
2230 lra_clear_live_ranges ();
2231 /* We need live ranges for lra_assign -- so build them. */
2232 lra_create_live_ranges (true);
2234 /* If we don't spill non-reload and non-inheritance pseudos,
2235 there is no sense to run memory-memory move coalescing.
2236 If inheritance pseudos were spilled, the memory-memory
2237 moves involving them will be removed by pass undoing
2243 bool spill_p
= !lra_assign ();
2245 if (lra_undo_inheritance ())
2251 lra_create_live_ranges (true);
2254 if (lra_coalesce ())
2258 lra_clear_live_ranges ();
2261 /* Don't clear optional reloads bitmap until all constraints are
2262 satisfied as we need to differ them from regular reloads. */
2263 bitmap_clear (&lra_optional_reload_pseudos
);
2264 bitmap_clear (&lra_subreg_reload_pseudos
);
2265 bitmap_clear (&lra_inheritance_pseudos
);
2266 bitmap_clear (&lra_split_regs
);
2267 if (! lra_need_for_spills_p ())
2271 /* We need full live info for spilling pseudos into
2272 registers instead of memory. */
2273 lra_create_live_ranges (lra_reg_spill_p
);
2277 /* Assignment of stack slots changes elimination offsets for
2278 some eliminations. So update the offsets here. */
2279 lra_eliminate (false, false);
2280 lra_constraint_new_regno_start
= max_reg_num ();
2281 lra_constraint_new_insn_uid_start
= get_max_uid ();
2282 lra_assignment_iter_after_spill
= 0;
2284 restore_scratches ();
2285 lra_eliminate (true, false);
2286 lra_final_code_change ();
2287 lra_in_progress
= 0;
2289 lra_clear_live_ranges ();
2290 lra_live_ranges_finish ();
2291 lra_constraints_finish ();
2293 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2294 lra_constraint_insn_stack
.release ();
2295 finish_insn_recog_data ();
2296 regstat_free_n_sets_and_refs ();
2298 reload_completed
= 1;
2299 update_inc_notes ();
2301 inserted_p
= fixup_abnormal_edges ();
2303 /* We've possibly turned single trapping insn into multiple ones. */
2304 if (cfun
->can_throw_non_call_exceptions
)
2307 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2308 bitmap_ones (blocks
);
2309 find_many_sub_basic_blocks (blocks
);
2310 sbitmap_free (blocks
);
2314 commit_edge_insertions ();
2316 /* Replacing pseudos with their memory equivalents might have
2317 created shared rtx. Subsequent passes would get confused
2318 by this, so unshare everything here. */
2319 unshare_all_rtl_again (get_insns ());
2321 #ifdef ENABLE_CHECKING
2325 timevar_pop (TV_LRA
);
2328 /* Called once per compiler to initialize LRA data once. */
2330 lra_init_once (void)
2332 init_insn_code_data_once ();
2335 /* Called once per compiler to finish LRA data which are initialize
2338 lra_finish_once (void)
2340 finish_insn_code_data_once ();