| blob | 1afd8a10156e35df5688daca87db803b203b7d98 |
1 /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ------------------------------------------------------------------------ */
23 #define IN_TARGET_CODE 1
54 /* This file should be included last. */
57 /* ------------------------------------------------------------------------ */
59 /* This file is divided into five parts:
61 PART 1: Auxiliary static variable definitions and
62 target hook static variable definitions.
64 PART 2: Auxiliary static function definitions.
66 PART 3: Implement target hook stuff definitions.
68 PART 4: Implemet extern function definitions,
69 the prototype is in nds32-protos.h.
71 PART 5: Initialize target hook structure and definitions. */
73 /* ------------------------------------------------------------------------ */
75 /* PART 1: Auxiliary static variable definitions and
76 target hook static variable definitions. */
78 /* Define intrinsic register names.
79 Please refer to nds32_intrinsic.h file, the index is corresponding to
80 'enum nds32_intrinsic_registers' data type values.
81 NOTE that the base value starting from 1024. */
83 {
237 "$ITB"
238 };
240 /* Define instrinsic cctl names. */
242 {
266 "L1I_IX_WWD"
267 };
270 {
276 "CLWR"
277 };
279 /* Defining register allocation order for performance.
280 We want to allocate callee-saved registers after others.
281 It may be used by nds32_adjust_reg_alloc_order(). */
283 {
288 };
290 /* Defining target-specific uses of __attribute__. */
292 {
293 /* Syntax: { name, min_len, max_len, decl_required, type_required,
294 function_type_required, affects_type_identity, handler,
295 exclude } */
297 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
299 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */
301 /* Argument is user's interrupt numbers. The vector number is always 0. */
304 /* The attributes describing isr nested type. */
309 /* The attributes describing isr register save scheme. */
313 /* The attributes used by reset attribute. */
317 /* The attribute telling no prologue/epilogue. */
320 /* The attribute is used to tell this function to be ROM patch. */
323 /* FOR BACKWARD COMPATIBILITY,
324 this attribute also tells no prologue/epilogue. */
327 /* The last attribute spec is set to be NULL. */
329 };
332 /* ------------------------------------------------------------------------ */
334 /* PART 2: Auxiliary static function definitions. */
336 /* Function to save and restore machine-specific function data. */
339 {
343 /* Initially assume this function does not use __builtin_eh_return. */
346 /* Initially assume this function needs prologue/epilogue. */
349 /* Initially assume this function does NOT use fp_as_gp optimization. */
352 /* Initially this function is not under strictly aligned situation. */
355 /* Initially this function has no naked and no_prologue attributes. */
360 }
362 /* Function to compute stack frame size and
363 store into cfun->machine structure. */
364 static void
366 {
371 /* Because nds32_compute_stack_frame() will be called from different place,
372 everytime we enter this function, we have to assume this function
373 needs prologue/epilogue. */
376 /* We need to mark whether this function has naked and no_prologue
377 attribute so that we can distinguish the difference if users applies
378 -mret-in-naked-func option. */
386 /* If __builtin_eh_return is used, we better have frame pointer needed
387 so that we can easily locate the stack slot of return address. */
389 {
392 /* We need to mark eh data registers that need to be saved
393 in the stack. */
403 }
404 else
405 {
406 /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we
407 do not need to handle __builtin_eh_return case in this function. */
413 }
415 /* Get variadic arguments size to prepare pretend arguments and
416 we will push them into stack at prologue by ourself. */
419 {
421 = NDS32_GPR_ARG_FIRST_REGNUM
422 + NDS32_MAX_GPR_REGS_FOR_ARGS
426 }
427 else
428 {
431 }
433 /* Important: We need to make sure that varargs area is 8-byte alignment. */
436 {
439 }
441 /* Get local variables, incoming variables, and temporary variables size.
442 Note that we need to make sure it is 8-byte alignment because
443 there may be no padding bytes if we are using LRA. */
446 /* Get outgoing arguments size. */
449 /* If $fp value is required to be saved on stack, it needs 4 bytes space.
450 Check whether $fp is ever live. */
453 /* If $gp value is required to be saved on stack, it needs 4 bytes space.
454 Check whether we are using PIC code genration. */
458 /* If $lp value is required to be saved on stack, it needs 4 bytes space.
459 Check whether $lp is ever live. */
463 /* Initially there is no padding bytes. */
466 /* Calculate the bytes of saving callee-saved registers on stack. */
474 /* Currently, there is no need to check $r28~$r31
475 because we will save them in another way. */
477 {
479 {
480 /* Mark the first required callee-saved register
481 (only need to set it once).
482 If first regno == SP_REGNUM, we can tell that
483 it is the first time to be here. */
486 /* Mark the last required callee-saved register. */
488 }
489 }
491 /* Recording fpu callee-saved register. */
493 {
495 {
497 {
498 /* Mark the first required callee-saved register. */
500 {
501 /* Make first callee-saved number is even,
502 bacause we use doubleword access, and this way
503 promise 8-byte alignemt. */
506 else
508 }
510 }
511 }
513 /* Make last callee-saved register number is odd,
514 we hope callee-saved register is even. */
518 }
520 /* Check if this function can omit prologue/epilogue code fragment.
521 If there is 'no_prologue'/'naked' attribute in this function,
522 we can set 'naked_p' flag to indicate that
523 we do not have to generate prologue/epilogue.
524 Or, if all the following conditions succeed,
525 we can set this function 'naked_p' as well:
526 condition 1: first_regno == last_regno == SP_REGNUM,
527 which means we do not have to save
528 any callee-saved registers.
529 condition 2: Both $lp and $fp are NOT live in this function,
530 which means we do not need to save them and there
531 is no outgoing size.
532 condition 3: There is no local_size, which means
533 we do not need to adjust $sp. */
544 {
545 /* Set this function 'naked_p' and other functions can check this flag.
546 Note that in nds32 port, the 'naked_p = 1' JUST means there is no
547 callee-saved, local size, and outgoing size.
548 The varargs space and ret instruction may still present in
549 the prologue/epilogue expanding. */
552 /* No need to save $fp, $gp, and $lp.
553 We should set these value to be zero
554 so that nds32_initial_elimination_offset() can work properly. */
559 /* If stack usage computation is required,
560 we need to provide the static stack size. */
564 /* No need to do following adjustment, return immediately. */
566 }
570 /* Adjustment for v3push instructions:
571 If we are using v3push (push25/pop25) instructions,
572 we need to make sure Rb is $r6 and Re is
573 located on $r6, $r8, $r10, or $r14.
574 Some results above will be discarded and recomputed.
575 Note that it is only available under V3/V3M ISA and we
576 DO NOT setup following stuff for isr or variadic function. */
578 {
579 /* Recompute:
580 cfun->machine->fp_size
581 cfun->machine->gp_size
582 cfun->machine->lp_size
583 cfun->machine->callee_saved_first_gpr_regno
584 cfun->machine->callee_saved_last_gpr_regno */
586 /* For v3push instructions, $fp, $gp, and $lp are always saved. */
591 /* Remember to set Rb = $r6. */
595 {
596 /* Re = $r6 */
598 }
600 {
601 /* Re = $r8 */
603 }
605 {
606 /* Re = $r10 */
608 }
610 {
611 /* Re = $r14 */
613 }
615 {
616 /* If last_regno is SP_REGNUM, which means
617 it is never changed, so set it to Re = $r6. */
619 }
620 else
621 {
622 /* The program flow should not go here. */
624 }
625 }
635 {
646 {
647 /* $r14 is last callee save register. */
650 {
652 }
654 {
659 }
660 }
661 }
663 /* We have correctly set callee_saved_first_gpr_regno
664 and callee_saved_last_gpr_regno.
665 Initially, the callee_saved_gpr_regs_size is supposed to be 0.
666 As long as callee_saved_last_gpr_regno is not SP_REGNUM,
667 we can update callee_saved_gpr_regs_size with new size. */
669 {
670 /* Compute pushed size of callee-saved registers. */
675 }
678 {
679 /* Compute size of callee svaed floating-point registers. */
681 {
686 }
687 }
689 /* Important: We need to make sure that
690 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size)
691 is 8-byte alignment.
692 If it is not, calculate the padding bytes. */
698 {
701 }
703 /* If stack usage computation is required,
704 we need to provide the static stack size. */
706 {
707 current_function_static_stack_size
711 }
712 }
714 /* Function to create a parallel rtx pattern
715 which presents stack push multiple behavior.
716 The overall concept are:
717 "push registers to memory",
718 "adjust stack pointer". */
719 static void
723 {
730 rtx reg;
731 rtx mem;
732 rtx push_rtx;
733 rtx adjust_sp_rtx;
734 rtx parallel_insn;
735 rtx dwarf;
737 /* We need to provide a customized rtx which contains
738 necessary information for data analysis,
739 so we create a parallel rtx like this:
740 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
741 (reg:SI Rb))
742 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
743 (reg:SI Rb+1))
744 ...
745 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
746 (reg:SI Re))
747 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
748 (reg:SI FP_REGNUM))
749 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
750 (reg:SI GP_REGNUM))
751 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
752 (reg:SI LP_REGNUM))
753 (set (reg:SI SP_REGNUM)
754 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
756 /* Calculate the number of registers that will be pushed. */
759 extra_count++;
761 extra_count++;
763 extra_count++;
764 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
767 else
770 /* In addition to used registers,
771 we need one more space for (set sp sp-x) rtx. */
776 /* Initialize offset and start to create push behavior. */
779 /* Create (set mem regX) from Rb, Rb+1 up to Re. */
781 {
782 /* Rb and Re may be SP_REGNUM.
783 We need to break this loop immediately. */
789 stack_pointer_rtx,
790 offset));
795 par_index++;
796 }
798 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
800 {
803 stack_pointer_rtx,
804 offset));
809 par_index++;
810 }
812 {
815 stack_pointer_rtx,
816 offset));
821 par_index++;
822 }
824 {
827 stack_pointer_rtx,
828 offset));
833 par_index++;
834 }
836 /* Create (set sp sp-x). */
838 /* We need to re-calculate the offset value again for adjustment. */
840 adjust_sp_rtx
848 /* The insn rtx 'parallel_insn' will change frame layout.
849 We need to use RTX_FRAME_RELATED_P so that GCC is able to
850 generate CFI (Call Frame Information) stuff. */
853 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG
854 since we will not restore those register at epilogue. */
856 {
860 }
861 }
863 /* Function to create a parallel rtx pattern
864 which presents stack pop multiple behavior.
865 The overall concept are:
866 "pop registers from memory",
867 "adjust stack pointer". */
868 static void
871 {
878 rtx reg;
879 rtx mem;
880 rtx pop_rtx;
881 rtx adjust_sp_rtx;
882 rtx parallel_insn;
885 /* We need to provide a customized rtx which contains
886 necessary information for data analysis,
887 so we create a parallel rtx like this:
888 (parallel [(set (reg:SI Rb)
889 (mem (reg:SI SP_REGNUM)))
890 (set (reg:SI Rb+1)
891 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
892 ...
893 (set (reg:SI Re)
894 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
895 (set (reg:SI FP_REGNUM)
896 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
897 (set (reg:SI GP_REGNUM)
898 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
899 (set (reg:SI LP_REGNUM)
900 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
901 (set (reg:SI SP_REGNUM)
902 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
904 /* Calculate the number of registers that will be poped. */
907 extra_count++;
909 extra_count++;
911 extra_count++;
912 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
915 else
918 /* In addition to used registers,
919 we need one more space for (set sp sp+x) rtx. */
924 /* Initialize offset and start to create pop behavior. */
927 /* Create (set regX mem) from Rb, Rb+1 up to Re. */
929 {
930 /* Rb and Re may be SP_REGNUM.
931 We need to break this loop immediately. */
937 stack_pointer_rtx,
938 offset));
943 par_index++;
946 }
948 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
950 {
953 stack_pointer_rtx,
954 offset));
959 par_index++;
962 }
964 {
967 stack_pointer_rtx,
968 offset));
973 par_index++;
976 }
978 {
981 stack_pointer_rtx,
982 offset));
987 par_index++;
990 }
992 /* Create (set sp sp+x). */
994 /* The offset value is already in place. No need to re-calculate it. */
995 adjust_sp_rtx
1000 /* Tell gcc we adjust SP in this insn. */
1005 /* The insn rtx 'parallel_insn' will change frame layout.
1006 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1007 generate CFI (Call Frame Information) stuff. */
1010 /* Add CFI info by manual. */
1012 }
1014 /* Function to create a parallel rtx pattern
1015 which presents stack v3push behavior.
1016 The overall concept are:
1017 "push registers to memory",
1018 "adjust stack pointer". */
1019 static void
1023 {
1029 rtx reg;
1030 rtx mem;
1031 rtx push_rtx;
1032 rtx adjust_sp_rtx;
1033 rtx parallel_insn;
1035 /* We need to provide a customized rtx which contains
1036 necessary information for data analysis,
1037 so we create a parallel rtx like this:
1038 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
1039 (reg:SI Rb))
1040 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
1041 (reg:SI Rb+1))
1042 ...
1043 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
1044 (reg:SI Re))
1045 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
1046 (reg:SI FP_REGNUM))
1047 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
1048 (reg:SI GP_REGNUM))
1049 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
1050 (reg:SI LP_REGNUM))
1051 (set (reg:SI SP_REGNUM)
1052 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
1054 /* Calculate the number of registers that will be pushed.
1055 Since $fp, $gp, and $lp is always pushed with v3push instruction,
1056 we need to count these three registers.
1057 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1058 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1061 /* In addition to used registers,
1062 we need one more space for (set sp sp-x-imm8u) rtx. */
1067 /* Initialize offset and start to create push behavior. */
1070 /* Create (set mem regX) from Rb, Rb+1 up to Re.
1071 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1072 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1074 {
1077 stack_pointer_rtx,
1078 offset));
1083 par_index++;
1084 }
1086 /* Create (set mem fp). */
1089 stack_pointer_rtx,
1090 offset));
1095 par_index++;
1096 /* Create (set mem gp). */
1099 stack_pointer_rtx,
1100 offset));
1105 par_index++;
1106 /* Create (set mem lp). */
1109 stack_pointer_rtx,
1110 offset));
1115 par_index++;
1117 /* Create (set sp sp-x-imm8u). */
1119 /* We need to re-calculate the offset value again for adjustment. */
1121 adjust_sp_rtx
1124 stack_pointer_rtx,
1131 /* The insn rtx 'parallel_insn' will change frame layout.
1132 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1133 generate CFI (Call Frame Information) stuff. */
1135 }
1137 /* Function to create a parallel rtx pattern
1138 which presents stack v3pop behavior.
1139 The overall concept are:
1140 "pop registers from memory",
1141 "adjust stack pointer". */
1142 static void
1146 {
1152 rtx reg;
1153 rtx mem;
1154 rtx pop_rtx;
1155 rtx adjust_sp_rtx;
1156 rtx parallel_insn;
1159 /* We need to provide a customized rtx which contains
1160 necessary information for data analysis,
1161 so we create a parallel rtx like this:
1162 (parallel [(set (reg:SI Rb)
1163 (mem (reg:SI SP_REGNUM)))
1164 (set (reg:SI Rb+1)
1165 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
1166 ...
1167 (set (reg:SI Re)
1168 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
1169 (set (reg:SI FP_REGNUM)
1170 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
1171 (set (reg:SI GP_REGNUM)
1172 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
1173 (set (reg:SI LP_REGNUM)
1174 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
1175 (set (reg:SI SP_REGNUM)
1176 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
1178 /* Calculate the number of registers that will be poped.
1179 Since $fp, $gp, and $lp is always poped with v3pop instruction,
1180 we need to count these three registers.
1181 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1182 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1185 /* In addition to used registers,
1186 we need one more space for (set sp sp+x+imm8u) rtx. */
1191 /* Initialize offset and start to create pop behavior. */
1194 /* Create (set regX mem) from Rb, Rb+1 up to Re.
1195 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1196 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1198 {
1201 stack_pointer_rtx,
1202 offset));
1207 par_index++;
1210 }
1212 /* Create (set fp mem). */
1215 stack_pointer_rtx,
1216 offset));
1221 par_index++;
1224 /* Create (set gp mem). */
1227 stack_pointer_rtx,
1228 offset));
1233 par_index++;
1236 /* Create (set lp mem ). */
1239 stack_pointer_rtx,
1240 offset));
1245 par_index++;
1248 /* Create (set sp sp+x+imm8u). */
1250 /* The offset value is already in place. No need to re-calculate it. */
1251 adjust_sp_rtx
1254 stack_pointer_rtx,
1259 {
1260 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp)
1261 (const_int 0))
1262 mean reset frame pointer to $sp and reset to offset 0. */
1264 const0_rtx);
1266 }
1267 else
1268 {
1269 /* Tell gcc we adjust SP in this insn. */
1272 }
1276 /* The insn rtx 'parallel_insn' will change frame layout.
1277 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1278 generate CFI (Call Frame Information) stuff. */
1281 /* Add CFI info by manual. */
1283 }
1285 static void
1287 {
1290 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1294 /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */
1299 /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */
1304 /* add5.pc $gp */
1307 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1309 }
1311 /* Function that may creates more instructions
1312 for large value on adjusting stack pointer.
1314 In nds32 target, 'addi' can be used for stack pointer
1315 adjustment in prologue/epilogue stage.
1316 However, sometimes there are too many local variables so that
1317 the adjustment value is not able to be fit in the 'addi' instruction.
1318 One solution is to move value into a register
1319 and then use 'add' instruction.
1320 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */
1321 static void
1323 {
1324 rtx tmp_reg;
1325 rtx frame_adjust_insn;
1332 {
1333 /* The value is not able to fit in single addi instruction.
1334 Create more instructions of moving value into a register
1335 and then add stack pointer with it. */
1337 /* $r15 is going to be temporary register to hold the value. */
1340 /* Create one more instruction to move value
1341 into the temporary register. */
1344 /* Create new 'add' rtx. */
1346 from_reg,
1347 tmp_reg);
1348 /* Emit rtx into insn list and receive its transformed insn rtx. */
1351 /* Because (tmp_reg <- full_value) may be split into two
1352 rtl patterns, we can not set its RTX_FRAME_RELATED_P.
1353 We need to construct another (sp <- sp + full_value)
1354 and then insert it into sp_adjust_insn's reg note to
1355 represent a frame related expression.
1356 GCC knows how to refer it and output debug information. */
1358 rtx plus_rtx;
1359 rtx set_rtx;
1364 }
1365 else
1366 {
1367 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
1369 from_reg,
1370 adjust_value_rtx);
1371 /* Emit rtx into instructions list and receive INSN rtx form. */
1373 }
1375 /* The insn rtx 'sp_adjust_insn' will change frame layout.
1376 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1377 generate CFI (Call Frame Information) stuff. */
1379 }
1381 /* Return true if MODE/TYPE need double word alignment. */
1382 static bool
1384 {
1387 /* Pick up the alignment according to the mode or type. */
1391 }
1393 /* Return true if FUNC is a naked function. */
1394 bool
1396 {
1397 /* FOR BACKWARD COMPATIBILITY,
1398 we need to support 'no_prologue' attribute as well. */
1399 tree t_naked;
1400 tree t_no_prologue;
1405 /* We have to use lookup_attribute() to check attributes.
1406 Because attr_naked_p and attr_no_prologue_p are set in
1407 nds32_compute_stack_frame() and the function has not been
1408 invoked yet. */
1413 }
1415 /* Function that determine whether a load postincrement is a good thing to use
1416 for a given mode. */
1417 bool
1419 {
1421 }
1423 /* Function that check if 'X' is a valid address register.
1424 The variable 'STRICT' is very important to
1425 make decision for register number.
1427 STRICT : true
1428 => We are in reload pass or after reload pass.
1429 The register number should be strictly limited in general registers.
1431 STRICT : false
1432 => Before reload pass, we are free to use any register number. */
1433 static bool
1435 {
1445 else
1447 }
1449 /* Function that check if 'INDEX' is valid to be a index rtx for address.
1451 OUTER_MODE : Machine mode of outer address rtx.
1452 INDEX : Check if this rtx is valid to be a index for address.
1453 STRICT : If it is true, we are in reload pass or after reload pass. */
1454 static bool
1456 rtx index,
1458 {
1460 rtx op0;
1461 rtx op1;
1464 {
1467 /* If we are in reload pass or after reload pass,
1468 we need to limit it to general register. */
1471 else
1475 /* The alignment of the integer value is determined by 'outer_mode'. */
1477 {
1479 /* Further check if the value is legal for the 'outer_mode'. */
1485 /* Further check if the value is legal for the 'outer_mode'. */
1487 {
1488 /* If it is not under strictly aligned situation,
1489 we can return true without checking alignment. */
1492 /* Make sure address is half word alignment. */
1495 }
1499 /* Further check if the value is legal for the 'outer_mode'. */
1501 {
1503 {
1506 }
1508 /* If it is not under strictly aligned situation,
1509 we can return true without checking alignment. */
1512 /* Make sure address is word alignment. */
1515 }
1520 SImode)))
1521 {
1523 {
1526 }
1528 /* If it is not under strictly aligned situation,
1529 we can return true without checking alignment. */
1532 /* Make sure address is word alignment.
1533 Currently we do not have 64-bit load/store yet,
1534 so we will use two 32-bit load/store instructions to do
1535 memory access and they are single word alignment. */
1538 }
1543 }
1552 {
1556 /* We only allow (mult reg const_int_1), (mult reg const_int_2),
1557 (mult reg const_int_4) or (mult reg const_int_8). */
1563 /* Limit it in general registers if we are
1564 in reload pass or after reload pass. */
1567 else
1569 }
1578 {
1580 /* op1 is already the sv value for use to do left shift. */
1583 /* We only allow (ashift reg const_int_0)
1584 or (ashift reg const_int_1) or (ashift reg const_int_2) or
1585 (ashift reg const_int_3). */
1590 /* Limit it in general registers if we are
1591 in reload pass or after reload pass. */
1594 else
1596 }
1602 }
1603 }
1605 static void
1610 {
1614 {
1618 pass_pos /* po_op */
1619 };
1622 }
1624 /* This function is called from nds32_option_override ().
1625 All new passes should be registered here. */
1626 static void
1628 {
1630 make_pass_nds32_fp_as_gp,
1631 PASS_POS_INSERT_BEFORE,
1635 make_pass_nds32_relax_opt,
1636 PASS_POS_INSERT_AFTER,
1638 }
1640 /* ------------------------------------------------------------------------ */
1642 /* PART 3: Implement target hook stuff definitions. */
1643 \f
1645 /* Computing the Length of an Insn.
1646 Modifies the length assigned to instruction INSN.
1647 LEN is the initially computed length of the insn. */
1648 int
1650 {
1653 {
1656 {
1658 {
1662 }
1663 /* We need insert a nop after a noretun function call
1664 to prevent software breakpoint corrupt the next function. */
1666 {
1669 else
1671 }
1672 }
1677 }
1678 }
1680 /* Storage Layout. */
1682 /* This function will be called just before expansion into rtl. */
1683 static void
1685 {
1686 /* We need to set strictly aligned situation.
1687 After that, the memory address checking in nds32_legitimate_address_p()
1688 will take alignment offset into consideration so that it will not create
1689 unaligned [base + offset] access during the rtl optimization. */
1691 }
1693 \f
1694 /* Register Usage. */
1696 static void
1698 {
1702 {
1705 {
1712 else
1714 }
1715 }
1717 {
1720 regno++)
1722 }
1723 }
1725 \f
1726 /* Register Classes. */
1728 static unsigned char
1730 machine_mode mode)
1731 {
1732 /* Return the maximum number of consecutive registers
1733 needed to represent "mode" in a register of "rclass". */
1735 }
1737 static int
1739 {
1740 /* Encourage to use r0-r7 for LRA when optimize for size. */
1742 {
1749 else
1751 }
1752 else
1753 {
1756 else
1758 }
1759 }
1761 static bool
1763 machine_mode to,
1764 reg_class_t rclass)
1765 {
1766 /* Don't spill double-precision register to two singal-precision
1767 registers */
1770 {
1772 }
1775 }
1777 \f
1778 /* Stack Layout and Calling Conventions. */
1780 /* There are three kinds of pointer concepts using in GCC compiler:
1782 frame pointer: A pointer to the first location of local variables.
1783 stack pointer: A pointer to the top of a stack frame.
1784 argument pointer: A pointer to the incoming arguments.
1786 In nds32 target calling convention, we are using 8-byte alignment.
1787 Besides, we would like to have each stack frame of a function includes:
1789 [Block A]
1790 1. previous hard frame pointer
1791 2. return address
1792 3. callee-saved registers
1793 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
1794 and save it at
1795 cfun->machine->callee_saved_area_padding_bytes)
1797 [Block B]
1798 1. local variables
1799 2. spilling location
1800 3. <padding bytes> (it will be calculated by GCC itself)
1801 4. incoming arguments
1802 5. <padding bytes> (it will be calculated by GCC itself)
1804 [Block C]
1805 1. <padding bytes> (it will be calculated by GCC itself)
1806 2. outgoing arguments
1808 We 'wrap' these blocks together with
1809 hard frame pointer ($r28) and stack pointer ($r31).
1810 By applying the basic frame/stack/argument pointers concept,
1811 the layout of a stack frame shoule be like this:
1813 | |
1814 old stack pointer -> ----
1815 | | \
1816 | | saved arguments for
1817 | | vararg functions
1818 | | /
1819 hard frame pointer -> --
1820 & argument pointer | | \
1821 | | previous hardware frame pointer
1822 | | return address
1823 | | callee-saved registers
1824 | | /
1825 frame pointer -> --
1826 | | \
1827 | | local variables
1828 | | and incoming arguments
1829 | | /
1830 --
1831 | | \
1832 | | outgoing
1833 | | arguments
1834 | | /
1835 stack pointer -> ----
1837 $SFP and $AP are used to represent frame pointer and arguments pointer,
1838 which will be both eliminated as hard frame pointer. */
1840 /* -- Eliminating Frame Pointer and Arg Pointer. */
1842 static bool
1844 {
1858 }
1860 /* -- Passing Arguments in Registers. */
1862 static rtx
1865 {
1869 /* The last time this hook is called,
1870 it is called with MODE == VOIDmode. */
1874 /* For nameless arguments, we need to take care it individually. */
1876 {
1877 /* If we are under hard float abi, we have arguments passed on the
1878 stack and all situation can be handled by GCC itself. */
1883 {
1884 /* If we still have enough registers to pass argument, pick up
1885 next available register number. */
1886 regno
1889 }
1891 /* No register available, return NULL_RTX.
1892 The compiler will use stack to pass argument instead. */
1894 }
1896 /* The following is to handle named argument.
1897 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT
1898 are different. */
1900 {
1901 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR
1902 to pass argument. We have to further check TYPE and MODE so
1903 that we can determine which kind of register we shall use. */
1905 /* Note that we need to pass argument entirely in registers under
1906 hard float abi. */
1909 {
1910 /* Pick up the next available FPR register number. */
1911 regno
1914 }
1917 {
1918 /* Pick up the next available GPR register number. */
1919 regno
1922 }
1923 }
1924 else
1925 {
1926 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass
1927 argument. Since we allow to pass argument partially in registers,
1928 we can just return it if there are still registers available. */
1930 {
1931 /* Pick up the next available register number. */
1932 regno
1935 }
1937 }
1939 /* No register available, return NULL_RTX.
1940 The compiler will use stack to pass argument instead. */
1942 }
1944 static bool
1946 {
1947 /* Return true if a type must be passed in memory.
1948 If it is NOT using hard float abi, small aggregates can be
1949 passed in a register even we are calling a variadic function.
1950 So there is no need to take padding into consideration. */
1953 else
1955 }
1957 static int
1960 {
1961 /* Returns the number of bytes at the beginning of an argument that
1962 must be put in registers. The value must be zero for arguments that are
1963 passed entirely in registers or that are entirely pushed on the stack.
1964 Besides, TARGET_FUNCTION_ARG for these arguments should return the
1965 first register to be used by the caller for this argument. */
1972 /* Under hard float abi, we better have argument entirely passed in
1973 registers or pushed on the stack so that we can reduce the complexity
1974 of dealing with cum->gpr_offset and cum->fpr_offset. */
1978 /* If we have already runned out of argument registers, return zero
1979 so that the argument will be entirely pushed on the stack. */
1984 /* Calculate how many registers do we need for this argument. */
1987 /* Calculate how many argument registers have left for passing argument.
1988 Note that we should count it from next available register number. */
1989 remaining_reg_count
1990 = NDS32_MAX_GPR_REGS_FOR_ARGS
1994 /* Note that we have to return the nubmer of bytes, not registers count. */
1999 }
2001 static void
2004 {
2008 {
2009 /* We need to further check TYPE and MODE so that we can determine
2010 which kind of register we shall advance. */
2012 /* Under hard float abi, we may advance FPR registers. */
2014 {
2015 cum->fpr_offset
2017 - NDS32_FPR_ARG_FIRST_REGNUM
2019 }
2020 else
2021 {
2022 cum->gpr_offset
2024 - NDS32_GPR_ARG_FIRST_REGNUM
2026 }
2027 }
2028 else
2029 {
2030 /* If this nameless argument is NOT under TARGET_HARD_FLOAT,
2031 we can advance next register as well so that caller is
2032 able to pass arguments in registers and callee must be
2033 in charge of pushing all of them into stack. */
2035 {
2036 cum->gpr_offset
2038 - NDS32_GPR_ARG_FIRST_REGNUM
2040 }
2041 }
2042 }
2044 static unsigned int
2046 {
2048 ? NDS32_DOUBLE_WORD_ALIGNMENT
2050 }
2052 bool
2054 {
2060 }
2062 /* -- How Scalar Function Values Are Returned. */
2064 static rtx
2066 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
2068 {
2069 machine_mode mode;
2080 else
2082 }
2084 static rtx
2086 const_rtx fun ATTRIBUTE_UNUSED)
2087 {
2092 }
2094 static bool
2096 {
2098 || (TARGET_HARD_FLOAT
2103 }
2105 /* -- How Large Values Are Returned. */
2107 static bool
2109 const_tree fntype ATTRIBUTE_UNUSED)
2110 {
2111 /* Note that int_size_in_bytes can return -1 if the size can vary
2112 or is larger than an integer. */
2115 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers,
2116 the return value is supposed to be in memory. We need to be aware of
2117 that the size may be -1. */
2122 /* If it is BLKmode and the total size cannot be hold within two registers,
2123 the return value is supposed to be in memory. We need to be aware of
2124 that the size may be -1. */
2129 /* For other cases, having result in memory is unnecessary. */
2131 }
2133 /* -- Function Entry and Exit. */
2135 /* The content produced from this function
2136 will be placed before prologue body. */
2137 static void
2139 {
2142 tree attrs;
2143 tree name;
2145 /* All stack frame information is supposed to be
2146 already computed when expanding prologue.
2147 The result is in cfun->machine.
2148 DO NOT call nds32_compute_stack_frame() here
2149 because it may corrupt the essential information. */
2157 /* Use df_regs_ever_live_p() to detect if the register
2158 is ever used in the current function. */
2161 {
2164 }
2167 /* Display the attributes of this function. */
2169 /* Get the attributes tree list.
2170 Note that GCC builds attributes list with reverse order. */
2173 /* If there is no any attribute, print out "None". */
2177 /* If there are some attributes, try if we need to
2178 construct isr vector information. */
2182 /* Display all attributes of this function. */
2184 {
2188 /* Pick up the next attribute. */
2190 }
2192 }
2194 /* After rtl prologue has been expanded, this function is used. */
2195 static void
2197 {
2199 }
2201 /* Before rtl epilogue has been expanded, this function is used. */
2202 static void
2204 {
2206 }
2208 /* The content produced from this function
2209 will be placed after epilogue body. */
2210 static void
2212 {
2214 }
2216 static void
2218 HOST_WIDE_INT delta,
2219 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2220 tree function)
2221 {
2224 /* Make sure unwind info is emitted for the thunk if needed. */
2232 {
2242 else
2243 {
2248 }
2249 }
2252 {
2254 {
2257 }
2259 {
2262 }
2263 else
2264 {
2267 delta);
2270 delta);
2272 }
2273 }
2276 {
2285 }
2286 else
2287 {
2291 }
2294 }
2296 /* -- Permitting tail calls. */
2298 /* Return true if it is ok to do sibling call optimization. */
2299 static bool
2301 tree exp ATTRIBUTE_UNUSED)
2302 {
2303 /* The DECL is NULL if it is an indirect call. */
2305 /* 1. Do not apply sibling call if -mv3push is enabled,
2306 because pop25 instruction also represents return behavior.
2307 2. If this function is a variadic function, do not apply sibling call
2308 because the stack layout may be a mess.
2309 3. We don't want to apply sibling call optimization for indirect
2310 sibcall because the pop behavior in epilogue may pollute the
2311 content of caller-saved regsiter when the register is used for
2312 indirect sibcall.
2313 4. In pic mode, it may use some registers for PLT call. */
2316 && decl
2318 }
2320 /* Determine whether we need to enable warning for function return check. */
2321 static bool
2323 {
2324 /* Naked functions are implemented entirely in assembly, including the
2325 return sequence, so suppress warnings about this. */
2327 }
2329 \f
2330 /* Implementing the Varargs Macros. */
2332 static void
2334 machine_mode mode,
2335 tree type,
2338 {
2344 /* If we are under hard float abi, we do not need to set *pretend_args_size.
2345 So that all nameless arguments are pushed by caller and all situation
2346 can be handled by GCC itself. */
2350 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
2351 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
2352 However, for nameless(anonymous) arguments, we should push them on the
2353 stack so that all the nameless arguments appear to have been passed
2354 consecutively in the memory for accessing. Hence, we need to check and
2355 exclude the registers that are used for named arguments. */
2359 /* The MODE and TYPE describe the last argument.
2360 We need those information to determine the remaining registers
2361 for varargs. */
2362 total_args_regs
2364 num_of_used_regs
2372 }
2374 static bool
2376 {
2377 /* If this hook returns true, the named argument of FUNCTION_ARG is always
2378 true for named arguments, and false for unnamed arguments. */
2380 }
2382 \f
2383 /* Trampolines for Nested Functions. */
2385 static void
2387 {
2389 {
2390 /* Trampoline is not supported on reduced-set registers yet. */
2392 }
2393 else
2394 {
2405 }
2407 /* Preserve space ($pc + 16) for saving chain_value,
2408 nds32_trampoline_init will fill the value in this slot. */
2412 /* Preserve space ($pc + 20) for saving nested function address,
2413 nds32_trampoline_init will fill the value in this slot. */
2416 }
2418 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2419 static void
2421 {
2424 /* Nested function address. */
2425 rtx fnaddr;
2426 /* The memory rtx that is going to
2427 be filled with chain_value. */
2428 rtx chain_value_mem;
2429 /* The memory rtx that is going to
2430 be filled with nested function address. */
2431 rtx nested_func_mem;
2433 /* Start address of trampoline code in stack, for doing cache sync. */
2434 rtx sync_cache_addr;
2435 /* Temporary register for sync instruction. */
2436 rtx tmp_reg;
2437 /* Instruction-cache sync instruction,
2438 requesting an argument as starting address. */
2439 rtx isync_insn;
2440 /* For convenience reason of doing comparison. */
2443 /* Trampoline is not supported on reduced-set registers yet. */
2447 /* STEP 1: Copy trampoline code template into stack,
2448 fill up essential data into stack. */
2450 /* Extract nested function address rtx. */
2453 /* m_tramp is memory rtx that is going to be filled with trampoline code.
2454 We have nds32_asm_trampoline_template() to emit template pattern. */
2458 /* After copying trampoline code into stack,
2459 fill chain_value into stack. */
2462 /* After copying trampoline code int stack,
2463 fill nested function address into stack. */
2467 /* STEP 2: Sync instruction-cache. */
2469 /* We have successfully filled trampoline code into stack.
2470 However, in order to execute code in stack correctly,
2471 we must sync instruction cache. */
2476 /* Because nds32_cache_block_size is in bytes,
2477 we get trampoline alignment in bytes for convenient comparison. */
2482 {
2483 /* Under this condition, the starting address of trampoline
2484 must be aligned to the starting address of each cache block
2485 and we do not have to worry about cross-boundary issue. */
2489 i++)
2490 {
2495 }
2496 }
2498 {
2499 /* The starting address of trampoline code
2500 may not be aligned to the cache block,
2501 so the trampoline code may be across two cache block.
2502 We need to sync the last element, which is 4-byte size,
2503 of trampoline template. */
2507 i++)
2508 {
2513 }
2515 /* The last element of trampoline template is 4-byte size. */
2520 }
2521 else
2522 {
2523 /* This is the simplest case.
2524 Because TRAMPOLINE_SIZE is less than or
2525 equal to nds32_cache_block_size,
2526 we can just sync start address and
2527 the last element of trampoline code. */
2529 /* Sync starting address of tampoline code. */
2532 /* Sync the last element, which is 4-byte size,
2533 of trampoline template. */
2538 }
2540 /* Set instruction serialization barrier
2541 to guarantee the correct operations. */
2543 }
2545 \f
2546 /* Addressing Modes. */
2548 static bool
2550 {
2552 {
2553 /* When using floating-point instructions,
2554 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
2560 /* Allow [post_modify] addressing mode, when using FPU instructions. */
2563 {
2566 {
2573 {
2575 {
2576 /* If it is not under strictly aligned situation,
2577 we can return true without checking alignment. */
2580 /* Make sure address is word alignment.
2581 Currently we do not have 64-bit load/store yet,
2582 so we will use two 32-bit load/store instructions to do
2583 memory access and they are single word alignment. */
2586 }
2587 }
2588 }
2589 }
2590 }
2592 /* For (mem:DI addr) or (mem:DF addr) case,
2593 we only allow 'addr' to be [reg], [symbol_ref],
2594 [const], or [reg + const_int] pattern. */
2596 {
2597 /* Allow [Reg + const_int] addressing mode. */
2599 {
2608 }
2610 /* Allow [post_inc] and [post_dec] addressing mode. */
2612 {
2615 }
2617 /* Now check [reg], [symbol_ref], and [const]. */
2622 }
2624 /* Check if 'x' is a valid address. */
2626 {
2628 /* (mem (reg A)) => [Ra] */
2632 /* (mem (symbol_ref A)) => [symbol_ref] */
2640 /* If -mcmodel=large, the 'symbol_ref' is not a valid address
2641 during or after LRA/reload phase. */
2643 && (reload_completed
2644 || reload_in_progress
2647 /* If -mcmodel=medium and the symbol references to rodata section,
2648 the 'symbol_ref' is not a valid address during or after
2649 LRA/reload phase. */
2653 && (reload_completed
2654 || reload_in_progress
2661 /* (mem (const (...)))
2662 => [ + const_addr ], where const_addr = symbol_ref + const_int */
2664 {
2671 {
2672 /* Now we see the [ + const_addr ] pattern, but we need
2673 some further checking. */
2678 /* If -mcmodel=large, the 'const_addr' is not a valid address
2679 during or after LRA/reload phase. */
2681 && (reload_completed
2682 || reload_in_progress
2685 /* If -mcmodel=medium and the symbol references to rodata section,
2686 the 'const_addr' is not a valid address during or after
2687 LRA/reload phase. */
2690 && (reload_completed
2691 || reload_in_progress
2695 /* At this point we can make sure 'const_addr' is a
2696 valid address. */
2698 }
2699 }
2704 /* (mem (post_modify (reg) (plus (reg) (reg))))
2705 => [Ra], Rb */
2706 /* (mem (post_modify (reg) (plus (reg) (const_int))))
2707 => [Ra], const_int */
2710 {
2719 else
2721 }
2727 /* (mem (post_inc reg)) => [Ra], 1/2/4 */
2728 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
2729 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
2730 We only need to deal with register Ra. */
2733 else
2737 /* (mem (plus reg const_int))
2738 => [Ra + imm] */
2739 /* (mem (plus reg reg))
2740 => [Ra + Rb] */
2741 /* (mem (plus (mult reg const_int) reg))
2742 => [Ra + Rb << sv] */
2749 else
2753 /* (mem (lo_sum (reg) (symbol_ref))) */
2754 /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */
2755 /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */
2756 /* The LO_SUM is a valid address if and only if we would like to
2757 generate 32-bit full address memory access with any of following
2758 circumstance:
2759 1. -mcmodel=large.
2760 2. -mcmodel=medium and the symbol_ref references to rodata. */
2761 {
2773 {
2779 }
2780 else
2794 else
2796 }
2800 }
2801 }
2803 static rtx
2805 rtx oldx ATTRIBUTE_UNUSED,
2806 machine_mode mode ATTRIBUTE_UNUSED)
2807 {
2816 }
2818 static bool
2820 {
2822 {
2832 {
2836 }
2839 {
2841 {
2853 }
2854 }
2857 /* TLS symbols need a call to resolve in
2858 precompute_register_parameters. */
2864 }
2867 }
2869 /* Reorgnize the UNSPEC CONST and return its direct symbol. */
2870 static rtx
2872 {
2876 {
2879 /* Handle for GOTOFF. */
2884 {
2886 {
2900 }
2901 }
2902 }
2904 }
2906 static machine_mode
2908 {
2913 {
2920 }
2921 }
2923 static bool
2925 {
2927 {
2931 /* All symbols have to be accessed through gp-relative in PIC mode. */
2932 /* We don't want to force symbol as constant pool in .text section,
2933 because we use the gp-relatived instruction to load in small
2934 or medium model. */
2937 || TARGET_CMODEL_SMALL
2948 }
2950 }
2952 \f
2953 /* Condition Code Status. */
2955 /* -- Representation of condition codes using registers. */
2957 static void
2962 {
2963 /* When the instruction combination pass tries to combine a comparison insn
2964 with its previous insns, it also transforms the operator in order to
2965 minimize its constant field. For example, it tries to transform a
2966 comparison insn from
2967 (set (reg:SI 54)
2968 (ltu:SI (reg:SI 52)
2969 (const_int 10 [0xa])))
2970 to
2971 (set (reg:SI 54)
2972 (leu:SI (reg:SI 52)
2973 (const_int 9 [0x9])))
2975 However, the nds32 target only provides instructions supporting the LTU
2976 operation directly, and the implementation of the pattern "cbranchsi4"
2977 only expands the LTU form. In order to handle the non-LTU operations
2978 generated from passes other than the RTL expansion pass, we have to
2979 implement this hook to revert those changes. Since we only expand the LTU
2980 operator in the RTL expansion pass, we might only need to handle the LEU
2981 case, unless we find other optimization passes perform more aggressive
2982 transformations. */
2985 {
2988 }
2989 }
2991 \f
2992 /* Describing Relative Costs of Operations. */
2994 static int
2996 reg_class_t from,
2997 reg_class_t to)
2998 {
2999 /* In garywolf cpu, FPR to GPR is chaper than other cpu. */
3001 {
3003 {
3004 /* DPR to GPR. */
3007 /* GPR to DPR. */
3010 }
3011 else
3012 {
3016 }
3017 }
3024 else
3026 }
3028 static int
3030 reg_class_t rclass ATTRIBUTE_UNUSED,
3032 {
3034 }
3036 /* This target hook describes the relative costs of RTL expressions.
3037 Return 'true' when all subexpressions of x have been processed.
3038 Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
3039 Refer to gcc/rtlanal.c for more information. */
3040 static bool
3042 machine_mode mode,
3047 {
3049 }
3051 static int
3053 machine_mode mode,
3054 addr_space_t as,
3056 {
3058 }
3060 \f
3061 /* Dividing the Output into Sections (Texts, Data, . . . ). */
3063 /* If references to a symbol or a constant must be treated differently
3064 depending on something about the variable or function named by the symbol
3065 (such as what section it is in), we use this hook to store flags
3066 in symbol_ref rtx. */
3067 static void
3069 {
3072 /* For the memory rtx, if it references to rodata section, we can store
3073 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the
3074 nds32_legitimate_address_p() can determine how to treat such symbol_ref
3075 based on -mcmodel=X and this information. */
3077 {
3081 {
3082 /* For (mem (symbol_ref X)) case. */
3084 }
3087 {
3088 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */
3095 }
3096 }
3097 }
3099 \f
3100 /* Defining the Output Assembler Language. */
3102 /* -- The Overall Framework of an Assembler File. */
3104 static void
3106 {
3112 /* Tell assembler which ABI we are using. */
3116 else
3119 /* Tell assembler that this asm code is generated by compiler. */
3125 else
3127 /* Give assembler the size of each vector for interrupt handler. */
3132 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
3133 the compiler may produce 'la $fp,_FP_BASE_' instruction
3134 at prologue for fp-as-gp optimization.
3135 We should emit weak reference of _FP_BASE_ to avoid undefined reference
3136 in case user does not pass '--relax' option to linker. */
3138 {
3142 }
3154 {
3194 }
3255 else
3261 nds32_cache_block_size);
3266 }
3268 static void
3270 {
3274 }
3276 static bool
3278 {
3280 {
3282 {
3320 }
3322 }
3323 else
3325 }
3327 /* -- Output and Generation of Labels. */
3329 static void
3331 {
3335 }
3337 /* -- Output of Assembler Instructions. */
3339 static void
3341 {
3343 HOST_WIDE_INT one_position;
3344 HOST_WIDE_INT zero_position;
3353 {
3355 /* Do nothing special. */
3359 /* Use exact_log2() to search the 0-bit position. */
3365 /* No need to handle following process, so return immediately. */
3374 /* No need to handle following process, so return immediately. */
3385 /* No need to handle following process, so return immediately. */
3389 /* Use exact_log2() to search the 1-bit position. */
3395 /* No need to handle following process, so return immediately. */
3399 /* X is supposed to be REG rtx. */
3401 /* Claim that we are going to pick LSB part of X. */
3406 /* X is supposed to be REG rtx. */
3408 /* Claim that we are going to pick MSB part of X. */
3413 /* 'x' is supposed to be CONST_INT, get the value. */
3416 /* According to the Andes architecture,
3417 the system/user register index range is 0 ~ 1023.
3418 In order to avoid conflict between user-specified-integer value
3419 and enum-specified-register value,
3420 the 'enum nds32_intrinsic_registers' value
3421 in nds32_intrinsic.h starts from 1024. */
3423 {
3424 /* If user gives integer value directly (0~1023),
3425 we just print out the value. */
3427 }
3431 {
3432 /* The enum index value for array size is out of range. */
3434 }
3435 else
3436 {
3437 /* If user applies normal way with __NDS32_REG_XXX__ enum data,
3438 we can print out register name. Remember to substract 1024. */
3441 }
3443 /* No need to handle following process, so return immediately. */
3447 /* Note the cctl divide to 5 group and share the same name table. */
3454 /* Note the cctl divide to 5 group and share the same name table. */
3461 /* Note the cctl divide to 5 group and share the same name table. */
3468 /* Note the cctl divide to 5 group and share the same name table. */
3475 /* Note the cctl divide to 5 group and share the same name table. */
3486 /* Unknown flag. */
3489 }
3492 {
3506 /* Print a Double-precision register name. */
3509 {
3512 {
3515 }
3518 }
3520 /* Print LSB or MSB part of register pair if the
3521 constraint modifier 'L' or 'H' is specified. */
3524 {
3527 {
3528 /* If we would like to print out LSB register under big-endian,
3529 or print out MSB register under little-endian, we need to
3530 increase register number. */
3532 regno++;
3535 }
3536 }
3538 /* Forbid using static chain register ($r16)
3539 on reduced-set registers configuration. */
3544 /* Normal cases, print out register name. */
3554 {
3563 }
3564 else
3590 /* This is a special case for inline assembly using memory address 'p'.
3591 The inline assembly code is expected to use pesudo instruction
3592 for the operand. EX: la */
3597 /* Generally, output_addr_const () is able to handle most cases.
3598 We want to see what CODE could appear,
3599 so we use gcc_unreachable() to stop it. */
3603 }
3604 }
3606 static void
3608 machine_mode mode ATTRIBUTE_UNUSED,
3609 rtx x)
3610 {
3614 {
3617 /* [ + symbol_ref] */
3618 /* [ + const_addr], where const_addr = symbol_ref + const_int */
3625 /* This is a special case for inline assembly using memory operand 'm'.
3626 The inline assembly code is expected to use pesudo instruction
3627 for the operand. EX: [ls].[bhw] */
3635 /* Forbid using static chain register ($r16)
3636 on reduced-set registers configuration. */
3641 /* [Ra] */
3649 /* Checking op0, forbid using static chain register ($r16)
3650 on reduced-set registers configuration. */
3655 /* Checking op1, forbid using static chain register ($r16)
3656 on reduced-set registers configuration. */
3663 {
3664 /* [Ra + imm] */
3667 }
3669 {
3670 /* [Ra + Rb] */
3673 }
3675 {
3676 /* [Ra + Rb << sv]
3677 From observation, the pattern looks like:
3678 (plus:SI (mult:SI (reg:SI 58)
3679 (const_int 4 [0x4]))
3680 (reg/f:SI 57)) */
3683 /* We need to set sv to output shift value. */
3692 else
3698 sv);
3699 }
3701 {
3702 /* [Ra + Rb << sv]
3703 In normal, ASHIFT can be converted to MULT like above case.
3704 But when the address rtx does not go through canonicalize_address
3705 defined in fwprop, we'll need this case. */
3712 sv);
3713 }
3714 else
3715 {
3716 /* The control flow is not supposed to be here. */
3719 }
3724 /* (post_modify (regA) (plus (regA) (regB)))
3725 (post_modify (regA) (plus (regA) (const_int)))
3726 We would like to extract
3727 regA and regB (or const_int) from plus rtx. */
3731 /* Checking op0, forbid using static chain register ($r16)
3732 on reduced-set registers configuration. */
3737 /* Checking op1, forbid using static chain register ($r16)
3738 on reduced-set registers configuration. */
3745 {
3746 /* [Ra], Rb */
3749 }
3751 {
3752 /* [Ra], imm */
3755 }
3756 else
3757 {
3758 /* The control flow is not supposed to be here. */
3761 }
3769 /* Checking op0, forbid using static chain register ($r16)
3770 on reduced-set registers configuration. */
3777 {
3778 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
3779 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
3780 We only need to deal with register Ra. */
3782 }
3783 else
3784 {
3785 /* The control flow is not supposed to be here. */
3788 }
3793 /* Generally, output_addr_const () is able to handle most cases.
3794 We want to see what CODE could appear,
3795 so we use gcc_unreachable() to stop it. */
3799 }
3800 }
3802 /* -- Assembler Commands for Exception Regions. */
3804 static rtx
3806 {
3808 rtx dwarf_single;
3809 machine_mode mode;
3815 /* We need to adjust dwarf register information for floating-point registers
3816 rather than using default register number mapping. */
3819 {
3821 {
3822 /* By default, GCC maps increasing register numbers to increasing
3823 memory locations, but paired FPRs in NDS32 target are always
3824 big-endian, i.e.:
3826 fd0 : fs0 fs1
3827 (MSB) (LSB)
3829 We must return parallel rtx to represent such layout. */
3834 }
3836 {
3844 }
3846 {
3847 /* Create new dwarf information with adjusted register number. */
3850 }
3851 else
3852 {
3853 /* We should not be here. */
3855 }
3856 }
3859 }
3861 /* Map internal gcc register numbers to DWARF2 register numbers. */
3863 unsigned int
3865 {
3866 /* The nds32 port in GDB maintains a mapping between dwarf register
3867 number and displayed register name. For backward compatibility to
3868 previous toolchain, currently our gdb still has four registers
3869 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler
3870 does not count those four registers in its register number table.
3871 So we have to add 4 on its register number and then create new
3872 dwarf information. Hopefully we can discard such workaround
3873 in the future. */
3878 }
3880 \f
3881 /* Defining target-specific uses of __attribute__. */
3883 /* Add some checking after merging attributes. */
3884 static tree
3886 {
3887 tree combined_attrs;
3889 /* Create combined attributes. */
3893 /* Since newdecl is acutally a duplicate of olddecl,
3894 we can take olddecl for some operations. */
3896 {
3897 /* Check isr-specific attributes conflict. */
3899 }
3902 }
3904 /* Add some checking when inserting attributes. */
3905 static void
3907 {
3908 /* A "indirect_call" function attribute implies "noinline" and "noclone"
3909 for elf toolchain to support ROM patch mechanism. */
3912 {
3924 }
3926 /* For function declaration, we need to check isr-specific attributes:
3927 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
3928 2. Check valid integer value for interrupt/exception.
3929 3. Check valid integer value for reset.
3930 4. Check valid function for nmi/warm. */
3932 {
3933 tree func_attrs;
3936 /* Pick up function attributes. */
3939 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */
3942 /* Now we are starting to check valid id value
3943 for interrupt/exception/reset.
3944 Note that we ONLY check its validity here.
3945 To construct isr vector information, it is still performed
3946 by nds32_construct_isr_vectors_information(). */
3952 {
3953 /* Deal with interrupt/exception. */
3954 tree id_list;
3957 /* The way to handle interrupt or exception is the same,
3958 we just need to take care of actual vector number.
3959 For interrupt(0..63), the actual vector number is (9..72).
3960 For exception(1..8), the actual vector number is (1..8). */
3964 /* Prepare id list so that we can traverse id value. */
3967 /* 2. Check valid integer value for interrupt/exception. */
3969 {
3970 tree id;
3972 /* Pick up each vector id value. */
3974 /* Issue error if it is not a valid integer value. */
3980 /* Advance to next id. */
3982 }
3983 }
3985 {
3986 /* Deal with reset. */
3987 tree id_list;
3988 tree id;
3993 /* Prepare id_list and identify id value so that
3994 we can check if total number of vectors is valid. */
3998 /* The maximum numbers for user's interrupt is 64. */
4002 /* 3. Check valid integer value for reset. */
4008 /* 4. Check valid function for nmi/warm. */
4013 {
4014 tree nmi_func_list;
4015 tree nmi_func;
4020 /* Issue error if it is not a valid nmi function. */
4023 }
4026 {
4027 tree warm_func_list;
4028 tree warm_func;
4033 /* Issue error if it is not a valid warm function. */
4036 }
4037 }
4038 else
4039 {
4040 /* No interrupt, exception, or reset attribute is set. */
4042 }
4043 }
4044 }
4046 static bool
4048 tree pop_target ATTRIBUTE_UNUSED)
4049 {
4050 /* Currently, we do not parse any pragma target by ourself,
4051 so just simply return false. */
4053 }
4055 static void
4057 {
4058 /* After all the command options have been parsed,
4059 we shall deal with some flags for changing compiler settings. */
4061 /* At first, we check if we have to strictly
4062 set some flags based on ISA family. */
4064 {
4065 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
4067 }
4069 {
4070 /* Under V3 ISA, currently nothing should be strictly set. */
4071 }
4073 {
4074 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
4076 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
4078 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
4080 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
4085 }
4087 /* See if we are using reduced-set registers:
4088 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
4089 If so, we must forbid using $r11~$r14, $r16~$r27. */
4091 {
4094 /* Prevent register allocator from
4095 choosing it as doing register allocation. */
4100 }
4102 /* See if user explicitly would like to use fp-as-gp optimization.
4103 If so, we must prevent $fp from being allocated
4104 during register allocation. */
4109 {
4110 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */
4112 }
4115 {
4119 else
4122 }
4127 }
4129 \f
4130 /* Miscellaneous Parameters. */
4137 {
4139 {
4142 }
4144 }
4146 static void
4148 {
4150 }
4152 static tree
4154 {
4155 /* Implement in nds32-intrinsic.c. */
4157 }
4159 static rtx
4161 rtx target,
4162 rtx subtarget,
4163 machine_mode mode,
4165 {
4167 }
4170 /* ------------------------------------------------------------------------ */
4172 /* PART 4: Implemet extern function definitions,
4173 the prototype is in nds32-protos.h. */
4174 \f
4175 /* Run-time Target Specification. */
4177 void
4179 {
4180 #define builtin_define(TXT) cpp_define (pfile, TXT)
4181 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
4187 else
4207 {
4209 {
4228 }
4229 }
4233 else
4263 else
4266 #undef builtin_define
4267 #undef builtin_assert
4268 }
4270 \f
4271 /* Defining Data Structures for Per-function Information. */
4273 void
4275 {
4276 /* Arrange to initialize and mark the machine per-function status. */
4278 }
4280 \f
4281 /* Register Usage. */
4283 /* -- Order of Allocation of Registers. */
4285 void
4287 {
4290 /* Copy the default register allocation order, which is designed
4291 to optimize for code size. */
4294 /* Adjust few register allocation order when optimizing for speed. */
4296 {
4299 }
4300 }
4302 /* -- How Values Fit in Registers. */
4304 static unsigned
4306 machine_mode mode)
4307 {
4309 }
4311 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4313 static bool
4315 {
4320 {
4329 }
4331 /* Restrict double-word quantities to even register pairs. */
4337 }
4339 /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to
4340 tie QI/HI/SI modes together. */
4342 static bool
4344 {
4352 {
4356 else
4358 }
4361 }
4362 \f
4363 /* Register Classes. */
4365 enum reg_class
4367 {
4368 /* Refer to nds32.h for more register class details. */
4383 {
4384 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't
4385 know how to allocate register for $SFP and $AP, just tell IRA they
4386 are GENERAL_REGS, and ARM do this hack too. */
4388 }
4391 else
4393 }
4395 \f
4396 /* Stack Layout and Calling Conventions. */
4398 /* -- Basic Stack Layout. */
4400 rtx
4402 {
4404 {
4405 /* If -mv3push is specified, we push $fp, $gp, and $lp into stack.
4406 We can access dynamic chain address from stack by [$fp - 12]. */
4408 }
4409 else
4410 {
4411 /* For general case we push $fp and $lp into stack at prologue.
4412 We can access dynamic chain address from stack by [$fp - 8]. */
4414 }
4415 }
4417 rtx
4419 rtx frameaddr)
4420 {
4422 rtx addr;
4425 {
4426 /* In nds32 ABI design, we can expect that $lp is always available
4427 from stack by [$fp - 4] location. */
4433 }
4435 /* If count == 0, it means we are at current frame,
4436 the return address is $r30 ($lp). */
4438 }
4440 /* -- Eliminating Frame Pointer and Arg Pointer. */
4442 HOST_WIDE_INT
4444 {
4445 HOST_WIDE_INT offset;
4447 /* Compute and setup stack frame size.
4448 The result will be in cfun->machine. */
4451 /* Remember to consider
4452 cfun->machine->callee_saved_area_gpr_padding_bytes and
4453 cfun->machine->eh_return_data_regs_size
4454 when calculating offset. */
4456 {
4466 }
4469 {
4471 }
4474 {
4476 }
4479 {
4487 }
4488 else
4489 {
4491 }
4494 }
4496 /* -- Passing Arguments in Registers. */
4498 void
4500 tree fntype ATTRIBUTE_UNUSED,
4501 rtx libname ATTRIBUTE_UNUSED,
4502 tree fndecl ATTRIBUTE_UNUSED,
4504 {
4505 /* Initial available registers. The values are offset against
4506 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM
4507 for passing arguments. */
4510 }
4512 /* -- Function Entry and Exit. */
4514 /* Function for normal multiple push prologue. */
4515 void
4517 {
4522 /* Compute and setup stack frame size.
4523 The result will be in cfun->machine. */
4526 /* Check frame_pointer_needed again to prevent fp is need after reload. */
4530 /* If this is a variadic function, first we need to push argument
4531 registers that hold the unnamed argument value. */
4533 {
4536 /* No need to push $fp, $gp, or $lp. */
4539 /* We may also need to adjust stack pointer for padding bytes
4540 because varargs may cause $sp not 8-byte aligned. */
4542 {
4543 /* Generate sp adjustment instruction. */
4547 stack_pointer_rtx,
4549 }
4550 }
4552 /* If the function is 'naked',
4553 we do not have to generate prologue code fragment. */
4557 /* Get callee_first_regno and callee_last_regno. */
4561 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4562 to be saved, we don't have to create multiple push instruction.
4563 Otherwise, a multiple push instruction is needed. */
4568 {
4569 /* Create multiple push instruction rtx. */
4574 }
4576 /* Save eh data registers. */
4578 {
4582 /* No need to push $fp, $gp, or $lp.
4583 Also, this is not variadic arguments push. */
4585 }
4587 /* Check frame_pointer_needed to see
4588 if we shall emit fp adjustment instruction. */
4590 {
4591 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
4592 + (4 * callee-saved-registers)
4593 + (4 * exception-handling-data-registers)
4594 Note: No need to adjust
4595 cfun->machine->callee_saved_area_gpr_padding_bytes,
4596 because, at this point, stack pointer is just
4597 at the position after push instruction. */
4605 stack_pointer_rtx,
4606 fp_adjust);
4607 }
4609 /* Save fpu registers. */
4611 {
4612 /* When $sp moved to bottom of stack, we need to check whether
4613 the range of offset in the FPU instruction. */
4618 /* Check FPU instruction offset imm14s. */
4620 {
4624 /* Save fpu registers, need to allocate stack space
4625 for fpu callee registers. And now $sp position
4626 on callee saved fpr registers. */
4628 stack_pointer_rtx,
4631 /* Emit fpu store instruction, using [$sp + offset] store
4632 fpu registers. */
4635 /* Adjust $sp = $sp - local_size - out_args_size. */
4639 /* Allocate stack space for local size and out args size. */
4641 stack_pointer_rtx,
4643 }
4644 else
4645 {
4646 /* Offset range in Is14, so $sp moved to bottom of stack. */
4648 /* Adjust $sp = $sp - local_size - out_args_size
4649 - callee_saved_area_gpr_padding_bytes
4650 - callee_saved_fpr_regs_size. */
4657 stack_pointer_rtx,
4660 /* Emit fpu store instruction, using [$sp + offset] store
4661 fpu registers. */
4665 }
4666 }
4667 else
4668 {
4669 /* Adjust $sp = $sp - local_size - out_args_size
4670 - callee_saved_area_gpr_padding_bytes. */
4675 /* sp_adjust value may be out of range of the addi instruction,
4676 create alternative add behavior with TA_REGNUM if necessary,
4677 using NEGATIVE value to tell that we are decreasing address. */
4679 stack_pointer_rtx,
4681 }
4683 /* Emit gp setup instructions for -fpic. */
4687 /* Prevent the instruction scheduler from
4688 moving instructions across the boundary. */
4690 }
4692 /* Function for normal multiple pop epilogue. */
4693 void
4695 {
4699 /* Compute and setup stack frame size.
4700 The result will be in cfun->machine. */
4703 /* Prevent the instruction scheduler from
4704 moving instructions across the boundary. */
4707 /* If the function is 'naked', we do not have to generate
4708 epilogue code fragment BUT 'ret' instruction.
4709 However, if this function is also a variadic function,
4710 we need to create adjust stack pointer before 'ret' instruction. */
4712 {
4713 /* If this is a variadic function, we do not have to restore argument
4714 registers but need to adjust stack pointer back to previous stack
4715 frame location before return. */
4717 {
4718 /* Generate sp adjustment instruction.
4719 We need to consider padding bytes here. */
4724 stack_pointer_rtx,
4725 sp_adjust);
4726 }
4728 /* Generate return instruction by using 'return_internal' pattern.
4729 Make sure this instruction is after gen_blockage(). */
4731 {
4732 /* We need to further check attributes to determine whether
4733 there should be return instruction at epilogue.
4734 If the attribute naked exists but -mno-ret-in-naked-func
4735 is issued, there is NO need to generate return instruction. */
4740 }
4742 }
4745 {
4746 /* Restore fpu registers. */
4748 {
4751 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4752 - (4 * callee-saved-registers)
4753 - (4 * exception-handling-data-registers)
4754 - (4 * callee-saved-gpr-registers padding byte)
4755 - (4 * callee-saved-fpr-registers)
4756 Note: we want to adjust stack pointer
4757 to the position for callee-saved fpr register,
4758 And restore fpu register use .bi instruction to adjust $sp
4759 from callee-saved fpr register to pop instruction. */
4769 hard_frame_pointer_rtx,
4772 /* Emit fpu load instruction, using .bi instruction
4773 load fpu registers. */
4775 }
4776 else
4777 {
4778 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4779 - (4 * callee-saved-registers)
4780 - (4 * exception-handling-data-registers)
4781 Note: No need to adjust
4782 cfun->machine->callee_saved_area_gpr_padding_bytes,
4783 because we want to adjust stack pointer
4784 to the position for pop instruction. */
4792 hard_frame_pointer_rtx,
4794 }
4795 }
4796 else
4797 {
4798 /* Restore fpu registers. */
4800 {
4803 /* Adjust $sp = $sp + local_size + out_args_size. */
4808 stack_pointer_rtx,
4809 sp_adjust);
4811 /* Emit fpu load instruction, using .bi instruction
4812 load fpu registers, and adjust $sp from callee-saved fpr register
4813 to callee-saved gpr register. */
4815 }
4816 else
4817 {
4818 /* If frame pointer is NOT needed,
4819 we cannot calculate the sp adjustment from frame pointer.
4820 Instead, we calculate the adjustment by local_size,
4821 out_args_size, and callee_saved_area_gpr_padding_bytes.
4822 Notice that such sp adjustment value may be out of range,
4823 so we have to deal with it as well. */
4825 /* Adjust $sp = $sp + local_size + out_args_size
4826 + callee_saved_area_gpr_padding_bytes. */
4832 stack_pointer_rtx,
4833 sp_adjust);
4834 }
4835 }
4837 /* Restore eh data registers. */
4839 {
4843 /* No need to pop $fp, $gp, or $lp. */
4845 }
4847 /* Get callee_first_regno and callee_last_regno. */
4851 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4852 to be saved, we don't have to create multiple pop instruction.
4853 Otherwise, a multiple pop instruction is needed. */
4858 {
4859 /* Create multiple pop instruction rtx. */
4863 }
4865 /* If this is a variadic function, we do not have to restore argument
4866 registers but need to adjust stack pointer back to previous stack
4867 frame location before return. */
4869 {
4870 /* Generate sp adjustment instruction.
4871 We need to consider padding bytes here. */
4876 stack_pointer_rtx,
4877 sp_adjust);
4878 }
4880 /* If this function uses __builtin_eh_return, make stack adjustment
4881 for exception handler. */
4883 {
4884 /* We need to unwind the stack by the offset computed by
4885 EH_RETURN_STACKADJ_RTX. However, at this point the CFA is
4886 based on SP. Ideally we would update the SP and define the
4887 CFA along the lines of:
4889 SP = SP + EH_RETURN_STACKADJ_RTX
4890 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX)
4892 However the dwarf emitter only understands a constant
4893 register offset.
4895 The solution chosen here is to use the otherwise $ta ($r15)
4896 as a temporary register to hold the current SP value. The
4897 CFA is described using $ta then SP is modified. */
4899 rtx ta_reg;
4900 rtx insn;
4909 stack_pointer_rtx,
4910 EH_RETURN_STACKADJ_RTX));
4912 /* Ensure the assignment to $ta does not get optimized away. */
4914 }
4916 /* Generate return instruction. */
4919 }
4921 /* Function for v3push prologue. */
4922 void
4924 {
4930 /* Compute and setup stack frame size.
4931 The result will be in cfun->machine. */
4937 /* Check frame_pointer_needed again to prevent fp is need after reload. */
4941 /* If the function is 'naked',
4942 we do not have to generate prologue code fragment. */
4946 /* Get callee_first_regno and callee_last_regno. */
4950 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
4951 where imm8u has to be 8-byte alignment. */
4959 {
4960 /* We can use 'push25 Re,imm8u'. */
4962 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
4963 the pattern 'stack_v3push' is implemented in nds32.md. */
4966 /* Save fpu registers. */
4968 {
4969 /* Calculate fpr position. */
4972 /* Emit fpu store instruction, using [$sp + offset] store
4973 fpu registers. */
4975 }
4977 /* Check frame_pointer_needed to see
4978 if we shall emit fp adjustment instruction. */
4980 {
4981 /* adjust $fp = $sp + 4 ($fp size)
4982 + 4 ($gp size)
4983 + 4 ($lp size)
4984 + (4 * n) (callee-saved registers)
4985 + sp_adjust ('push25 Re,imm8u')
4986 Note: Since we use 'push25 Re,imm8u',
4987 the position of stack pointer is further
4988 changed after push instruction.
4989 Hence, we need to take sp_adjust value
4990 into consideration. */
4998 stack_pointer_rtx,
4999 fp_adjust);
5000 }
5001 }
5002 else
5003 {
5005 {
5006 /* Calculate fpr space. */
5010 /* We have to use 'push25 Re, fpr_space', to pre-allocate
5011 callee saved fpr registers space. */
5014 }
5015 else
5016 {
5017 /* We have to use 'push25 Re,0' and
5018 expand one more instruction to adjust $sp later. */
5020 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
5021 the pattern 'stack_v3push' is implemented in nds32.md. */
5023 }
5025 /* Check frame_pointer_needed to see
5026 if we shall emit fp adjustment instruction. */
5028 {
5029 /* adjust $fp = $sp + 4 ($fp size)
5030 + 4 ($gp size)
5031 + 4 ($lp size)
5032 + (4 * n) (callee-saved registers)
5033 Note: Since we use 'push25 Re,0',
5034 the stack pointer is just at the position
5035 after push instruction.
5036 No need to take sp_adjust into consideration. */
5043 {
5044 /* We use 'push25 Re, fpr_space', the $sp is
5045 on callee saved fpr position, so need to consider
5046 fpr space. */
5048 }
5051 stack_pointer_rtx,
5052 fp_adjust);
5053 }
5056 {
5057 /* We use 'push25 Re, fpr_space',
5058 the $sp is on callee saved fpr position,
5059 no need to consider fpr space. */
5061 }
5063 /* Because we use 'push25 Re,0',
5064 we need to expand one more instruction to adjust $sp.
5065 using NEGATIVE value to tell that we are decreasing address. */
5067 stack_pointer_rtx,
5069 }
5071 /* Emit gp setup instructions for -fpic. */
5075 /* Prevent the instruction scheduler from
5076 moving instructions across the boundary. */
5078 }
5080 /* Function for v3pop epilogue. */
5081 void
5083 {
5087 /* Compute and setup stack frame size.
5088 The result will be in cfun->machine. */
5091 /* Prevent the instruction scheduler from
5092 moving instructions across the boundary. */
5095 /* If the function is 'naked', we do not have to generate
5096 epilogue code fragment BUT 'ret' instruction. */
5098 {
5099 /* Generate return instruction by using 'return_internal' pattern.
5100 Make sure this instruction is after gen_blockage().
5101 First we need to check this is a function without sibling call. */
5103 {
5104 /* We need to further check attributes to determine whether
5105 there should be return instruction at epilogue.
5106 If the attribute naked exists but -mno-ret-in-naked-func
5107 is issued, there is NO need to generate return instruction. */
5112 }
5114 }
5116 /* Get callee_first_regno and callee_last_regno. */
5120 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
5121 where imm8u has to be 8-byte alignment. */
5127 /* We have to consider alloca issue as well.
5128 If the function does call alloca(), the stack pointer is not fixed.
5129 In that case, we cannot use 'pop25 Re,imm8u' directly.
5130 We have to caculate stack pointer from frame pointer
5131 and then use 'pop25 Re,0'.
5132 Of course, the frame_pointer_needed should be nonzero
5133 if the function calls alloca(). */
5137 {
5138 /* Restore fpu registers. */
5140 {
5143 /* Emit fpu load instruction, using [$sp + offset] restore
5144 fpu registers. */
5146 }
5148 /* We can use 'pop25 Re,imm8u'. */
5150 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5151 the pattern 'stack_v3pop' is implementad in nds32.md. */
5153 }
5154 else
5155 {
5156 /* We have to use 'pop25 Re,0', and prior to it,
5157 we must expand one more instruction to adjust $sp. */
5160 {
5161 /* adjust $sp = $fp - 4 ($fp size)
5162 - 4 ($gp size)
5163 - 4 ($lp size)
5164 - (4 * n) (callee-saved registers)
5165 Note: No need to adjust
5166 cfun->machine->callee_saved_area_gpr_padding_bytes,
5167 because we want to adjust stack pointer
5168 to the position for pop instruction. */
5174 /* Restore fpu registers. */
5176 {
5177 /* Set $sp to callee saved fpr position, we need to restore
5178 fpr registers. */
5179 sp_adjust = sp_adjust
5184 hard_frame_pointer_rtx,
5187 /* Emit fpu load instruction, using [$sp + offset] restore
5188 fpu registers. */
5190 }
5191 else
5192 {
5194 hard_frame_pointer_rtx,
5196 }
5197 }
5198 else
5199 {
5200 /* If frame pointer is NOT needed,
5201 we cannot calculate the sp adjustment from frame pointer.
5202 Instead, we calculate the adjustment by local_size,
5203 out_args_size, and callee_saved_area_padding_bytes.
5204 Notice that such sp adjustment value may be out of range,
5205 so we have to deal with it as well. */
5207 /* Adjust $sp = $sp + local_size + out_args_size
5208 + callee_saved_area_gpr_padding_bytes
5209 + callee_saved_fpr_regs_size. */
5215 /* Restore fpu registers. */
5217 {
5218 /* Set $sp to callee saved fpr position, we need to restore
5219 fpr registers. */
5220 sp_adjust = sp_adjust
5225 stack_pointer_rtx,
5226 sp_adjust);
5228 /* Emit fpu load instruction, using [$sp + offset] restore
5229 fpu registers. */
5231 }
5232 else
5233 {
5234 /* sp_adjust value may be out of range of the addi instruction,
5235 create alternative add behavior with TA_REGNUM if necessary,
5236 using POSITIVE value to tell that we are increasing
5237 address. */
5239 stack_pointer_rtx,
5240 sp_adjust);
5241 }
5242 }
5245 {
5246 /* We have fpr need to restore, so $sp is set on callee saved fpr
5247 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */
5251 }
5252 else
5253 {
5254 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5255 the pattern 'stack_v3pop' is implementad in nds32.md. */
5257 }
5258 }
5259 /* Generate return instruction. */
5261 }
5263 /* Return nonzero if this function is known to have a null epilogue.
5264 This allows the optimizer to omit jumps to jumps if no stack
5265 was created. */
5266 int
5268 {
5271 /* Prior to reloading, we can't tell how many registers must be saved.
5272 Thus we can not determine whether this function has null epilogue. */
5276 /* If attribute 'naked' appears but -mno-ret-in-naked-func is used,
5277 we cannot use return instruction. */
5289 && NDS32_V3PUSH_AVAILABLE_P
5290 && !(TARGET_HARD_FLOAT
5294 /* If no stack was created, two conditions must be satisfied:
5295 1. This is a naked function.
5296 So there is no callee-saved, local size, or outgoing size.
5297 2. This is NOT a variadic function.
5298 So there is no pushing arguement registers into the stack. */
5300 }
5302 scalar_int_mode
5304 rtx body ATTRIBUTE_UNUSED)
5305 {
5308 else
5309 {
5310 /* The jump table maybe need to 2 byte alignment,
5311 so reserved 1 byte for check max_offset. */
5314 else
5316 }
5317 }
5319 /* ------------------------------------------------------------------------ */
5321 /* Return alignment for the label. */
5322 int
5324 {
5332 /* Always align to 4 byte when first instruction after label is jump
5333 instruction since length for that might changed, so let's always align
5334 it for make sure we don't lose any perfomance here. */
5339 else
5341 }
5343 /* Return alignment for data. */
5344 unsigned int
5347 {
5353 else
5355 }
5357 /* Return alignment for constant value. */
5358 static HOST_WIDE_INT
5360 HOST_WIDE_INT basic_align)
5361 {
5362 /* Make string literal and constant for constructor to word align. */
5370 else
5372 }
5374 /* Return alignment for local variable. */
5375 unsigned int
5378 {
5380 /* Make local array, struct and union at least align to word for make
5381 sure it can unroll memcpy when initialize by constant. */
5383 {
5392 }
5396 else
5398 }
5400 bool
5402 {
5404 /* Do split at split2 if -O0 or schedule 2 not enable. */
5408 /* Split double word load store after copy propgation. */
5418 }
5420 static bool
5422 const_rtx x ATTRIBUTE_UNUSED)
5423 {
5427 else
5429 }
5431 /* ------------------------------------------------------------------------ */
5433 /* PART 5: Initialize target hook structure and definitions. */
5434 \f
5435 /* Controlling the Compilation Driver. */
5437 \f
5438 /* Run-time Target Specification. */
5440 \f
5441 /* Defining Data Structures for Per-function Information. */
5443 \f
5444 /* Storage Layout. */
5446 #undef TARGET_PROMOTE_FUNCTION_MODE
5447 #define TARGET_PROMOTE_FUNCTION_MODE \
5448 default_promote_function_mode_always_promote
5450 #undef TARGET_EXPAND_TO_RTL_HOOK
5451 #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook
5453 #undef TARGET_CONSTANT_ALIGNMENT
5454 #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment
5456 \f
5457 /* Layout of Source Language Data Types. */
5459 \f
5460 /* Register Usage. */
5462 /* -- Basic Characteristics of Registers. */
5464 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5465 #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage
5467 /* -- Order of Allocation of Registers. */
5469 /* -- How Values Fit in Registers. */
5471 #undef TARGET_HARD_REGNO_NREGS
5472 #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs
5474 #undef TARGET_HARD_REGNO_MODE_OK
5475 #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
5477 #undef TARGET_MODES_TIEABLE_P
5478 #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p
5480 /* -- Handling Leaf Functions. */
5482 /* -- Registers That Form a Stack. */
5484 \f
5485 /* Register Classes. */
5487 #undef TARGET_CLASS_MAX_NREGS
5488 #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
5490 #undef TARGET_REGISTER_PRIORITY
5491 #define TARGET_REGISTER_PRIORITY nds32_register_priority
5493 #undef TARGET_CAN_CHANGE_MODE_CLASS
5494 #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class
5496 \f
5497 /* Obsolete Macros for Defining Constraints. */
5499 \f
5500 /* Stack Layout and Calling Conventions. */
5502 /* -- Basic Stack Layout. */
5504 /* -- Exception Handling Support. */
5506 /* -- Specifying How Stack Checking is Done. */
5508 /* -- Registers That Address the Stack Frame. */
5510 /* -- Eliminating Frame Pointer and Arg Pointer. */
5512 #undef TARGET_CAN_ELIMINATE
5513 #define TARGET_CAN_ELIMINATE nds32_can_eliminate
5515 /* -- Passing Function Arguments on the Stack. */
5517 /* -- Passing Arguments in Registers. */
5519 #undef TARGET_FUNCTION_ARG
5520 #define TARGET_FUNCTION_ARG nds32_function_arg
5522 #undef TARGET_MUST_PASS_IN_STACK
5523 #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack
5525 #undef TARGET_ARG_PARTIAL_BYTES
5526 #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes
5528 #undef TARGET_FUNCTION_ARG_ADVANCE
5529 #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
5531 #undef TARGET_FUNCTION_ARG_BOUNDARY
5532 #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
5534 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5535 #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p
5537 /* -- How Scalar Function Values Are Returned. */
5539 #undef TARGET_FUNCTION_VALUE
5540 #define TARGET_FUNCTION_VALUE nds32_function_value
5542 #undef TARGET_LIBCALL_VALUE
5543 #define TARGET_LIBCALL_VALUE nds32_libcall_value
5545 #undef TARGET_FUNCTION_VALUE_REGNO_P
5546 #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
5548 /* -- How Large Values Are Returned. */
5550 #undef TARGET_RETURN_IN_MEMORY
5551 #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory
5553 /* -- Caller-Saves Register Allocation. */
5555 /* -- Function Entry and Exit. */
5557 #undef TARGET_ASM_FUNCTION_PROLOGUE
5558 #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
5560 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
5561 #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
5563 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
5564 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
5566 #undef TARGET_ASM_FUNCTION_EPILOGUE
5567 #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
5569 #undef TARGET_ASM_OUTPUT_MI_THUNK
5570 #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
5572 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5573 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
5575 /* -- Generating Code for Profiling. */
5577 /* -- Permitting tail calls. */
5579 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5580 #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall
5582 #undef TARGET_WARN_FUNC_RETURN
5583 #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
5585 /* Stack smashing protection. */
5587 \f
5588 /* Implementing the Varargs Macros. */
5590 #undef TARGET_SETUP_INCOMING_VARARGS
5591 #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
5593 #undef TARGET_STRICT_ARGUMENT_NAMING
5594 #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
5596 \f
5597 /* Trampolines for Nested Functions. */
5599 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5600 #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
5602 #undef TARGET_TRAMPOLINE_INIT
5603 #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
5605 \f
5606 /* Implicit Calls to Library Routines. */
5608 \f
5609 /* Addressing Modes. */
5611 #undef TARGET_LEGITIMATE_ADDRESS_P
5612 #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
5614 #undef TARGET_LEGITIMIZE_ADDRESS
5615 #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address
5617 #undef TARGET_LEGITIMATE_CONSTANT_P
5618 #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p
5620 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
5621 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode
5623 #undef TARGET_CANNOT_FORCE_CONST_MEM
5624 #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem
5626 #undef TARGET_DELEGITIMIZE_ADDRESS
5627 #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address
5629 \f
5630 /* Anchored Addresses. */
5632 \f
5633 /* Condition Code Status. */
5635 /* -- Representation of condition codes using (cc0). */
5637 /* -- Representation of condition codes using registers. */
5639 #undef TARGET_CANONICALIZE_COMPARISON
5640 #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison
5642 /* -- Macros to control conditional execution. */
5644 \f
5645 /* Describing Relative Costs of Operations. */
5647 #undef TARGET_REGISTER_MOVE_COST
5648 #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
5650 #undef TARGET_MEMORY_MOVE_COST
5651 #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
5653 #undef TARGET_RTX_COSTS
5654 #define TARGET_RTX_COSTS nds32_rtx_costs
5656 #undef TARGET_ADDRESS_COST
5657 #define TARGET_ADDRESS_COST nds32_address_cost
5659 \f
5660 /* Adjusting the Instruction Scheduler. */
5662 \f
5663 /* Dividing the Output into Sections (Texts, Data, . . . ). */
5665 #undef TARGET_ENCODE_SECTION_INFO
5666 #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info
5668 \f
5669 /* Position Independent Code. */
5671 \f
5672 /* Defining the Output Assembler Language. */
5674 /* -- The Overall Framework of an Assembler File. */
5676 #undef TARGET_ASM_FILE_START
5677 #define TARGET_ASM_FILE_START nds32_asm_file_start
5678 #undef TARGET_ASM_FILE_END
5679 #define TARGET_ASM_FILE_END nds32_asm_file_end
5681 /* -- Output of Data. */
5683 #undef TARGET_ASM_ALIGNED_HI_OP
5686 #undef TARGET_ASM_ALIGNED_SI_OP
5689 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
5690 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra
5692 /* -- Output of Uninitialized Variables. */
5694 /* -- Output and Generation of Labels. */
5696 #undef TARGET_ASM_GLOBALIZE_LABEL
5697 #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
5699 /* -- How Initialization Functions Are Handled. */
5701 /* -- Macros Controlling Initialization Routines. */
5703 /* -- Output of Assembler Instructions. */
5705 #undef TARGET_PRINT_OPERAND
5706 #define TARGET_PRINT_OPERAND nds32_print_operand
5707 #undef TARGET_PRINT_OPERAND_ADDRESS
5708 #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
5710 /* -- Output of Dispatch Tables. */
5712 /* -- Assembler Commands for Exception Regions. */
5714 #undef TARGET_DWARF_REGISTER_SPAN
5715 #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span
5717 /* -- Assembler Commands for Alignment. */
5719 \f
5720 /* Controlling Debugging Information Format. */
5722 /* -- Macros Affecting All Debugging Formats. */
5724 /* -- Specific Options for DBX Output. */
5726 /* -- Open-Ended Hooks for DBX Format. */
5728 /* -- File Names in DBX Format. */
5730 /* -- Macros for DWARF Output. */
5732 /* -- Macros for VMS Debug Format. */
5734 \f
5735 /* Cross Compilation and Floating Point. */
5737 \f
5738 /* Mode Switching Instructions. */
5740 \f
5741 /* Defining target-specific uses of __attribute__. */
5743 #undef TARGET_ATTRIBUTE_TABLE
5744 #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
5746 #undef TARGET_MERGE_DECL_ATTRIBUTES
5747 #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
5749 #undef TARGET_INSERT_ATTRIBUTES
5750 #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
5752 #undef TARGET_OPTION_PRAGMA_PARSE
5753 #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
5755 #undef TARGET_OPTION_OVERRIDE
5756 #define TARGET_OPTION_OVERRIDE nds32_option_override
5758 \f
5759 /* Emulating TLS. */
5761 \f
5762 /* Defining coprocessor specifics for MIPS targets. */
5764 \f
5765 /* Parameters for Precompiled Header Validity Checking. */
5767 \f
5768 /* C++ ABI parameters. */
5770 \f
5771 /* Adding support for named address spaces. */
5773 \f
5774 /* Miscellaneous Parameters. */
5776 #undef TARGET_MD_ASM_ADJUST
5777 #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust
5779 #undef TARGET_INIT_BUILTINS
5780 #define TARGET_INIT_BUILTINS nds32_init_builtins
5782 #undef TARGET_BUILTIN_DECL
5783 #define TARGET_BUILTIN_DECL nds32_builtin_decl
5785 #undef TARGET_EXPAND_BUILTIN
5786 #define TARGET_EXPAND_BUILTIN nds32_expand_builtin
5789 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5790 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p
5792 \f
5793 /* ------------------------------------------------------------------------ */
5795 /* Initialize the GCC target structure. */
5799 /* ------------------------------------------------------------------------ */