1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern tree lookup_name
PARAMS ((tree
));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
90 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
91 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
93 int coprocessor_operand
PARAMS ((rtx
,
95 int coprocessor2_operand
PARAMS ((rtx
,
97 static int m16_check_op
PARAMS ((rtx
, int, int, int));
98 static void block_move_loop
PARAMS ((rtx
, rtx
,
102 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
103 static void mips_arg_info
PARAMS ((const CUMULATIVE_ARGS
*,
106 struct mips_arg_info
*));
107 static rtx mips_add_large_offset_to_sp
PARAMS ((HOST_WIDE_INT
));
108 static void mips_annotate_frame_insn
PARAMS ((rtx
, rtx
));
109 static rtx mips_frame_set
PARAMS ((enum machine_mode
,
111 static void mips_emit_frame_related_store
PARAMS ((rtx
, rtx
,
113 static void save_restore_insns
PARAMS ((int, rtx
, long));
114 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
115 static void mips16_fp_args
PARAMS ((FILE *, int, int));
116 static void build_mips16_function_stub
PARAMS ((FILE *));
117 static void mips16_optimize_gp
PARAMS ((rtx
));
118 static rtx add_constant
PARAMS ((struct constant
**,
121 static void dump_constants
PARAMS ((struct constant
*,
123 static rtx mips_find_symbol
PARAMS ((rtx
));
124 static void abort_with_insn
PARAMS ((rtx
, const char *))
126 static int symbolic_expression_p
PARAMS ((rtx
));
127 static void mips_add_gc_roots
PARAMS ((void));
128 static bool mips_assemble_integer
PARAMS ((rtx
, unsigned int, int));
129 static void mips_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
130 static void mips_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
131 static enum processor_type mips_parse_cpu
PARAMS ((const char *));
132 static void copy_file_data
PARAMS ((FILE *, FILE *));
134 static void iris6_asm_named_section_1
PARAMS ((const char *,
137 static void iris6_asm_named_section
PARAMS ((const char *,
139 static int iris_section_align_entry_eq
PARAMS ((const PTR
, const PTR
));
140 static hashval_t iris_section_align_entry_hash
PARAMS ((const PTR
));
141 static int iris6_section_align_1
PARAMS ((void **, void *));
143 static int mips_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
144 static int mips_issue_rate
PARAMS ((void));
146 static void mips_init_machine_status
PARAMS ((struct function
*));
147 static void mips_free_machine_status
PARAMS ((struct function
*));
148 static void mips_mark_machine_status
PARAMS ((struct function
*));
150 struct machine_function
{
151 /* Pseudo-reg holding the address of the current function when
152 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
153 used by mips_finalize_pic if it was created. */
154 rtx embedded_pic_fnaddr_rtx
;
156 /* Pseudo-reg holding the value of $28 in a mips16 function which
157 refers to GP relative global variables. */
158 rtx mips16_gp_pseudo_rtx
;
161 /* Information about a single argument. */
164 /* True if the argument is a record or union type. */
167 /* True if the argument is passed in a floating-point register, or
168 would have been if we hadn't run out of registers. */
171 /* The argument's size, in bytes. */
172 unsigned int num_bytes
;
174 /* The number of words passed in registers, rounded up. */
175 unsigned int reg_words
;
177 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
178 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
180 unsigned int reg_offset
;
182 /* The number of words that must be passed on the stack, rounded up. */
183 unsigned int stack_words
;
185 /* The offset from the start of the stack overflow area of the argument's
186 first stack word. Only meaningful when STACK_WORDS is non-zero. */
187 unsigned int stack_offset
;
190 /* Global variables for machine-dependent things. */
192 /* Threshold for data being put into the small data/bss area, instead
193 of the normal data area (references to the small data/bss area take
194 1 instruction, and use the global pointer, references to the normal
195 data area takes 2 instructions). */
196 int mips_section_threshold
= -1;
198 /* Count the number of .file directives, so that .loc is up to date. */
199 int num_source_filenames
= 0;
201 /* Count the number of sdb related labels are generated (to find block
202 start and end boundaries). */
203 int sdb_label_count
= 0;
205 /* Next label # for each statement for Silicon Graphics IRIS systems. */
208 /* Non-zero if inside of a function, because the stupid MIPS asm can't
209 handle .files inside of functions. */
210 int inside_function
= 0;
212 /* Files to separate the text and the data output, so that all of the data
213 can be emitted before the text, which will mean that the assembler will
214 generate smaller code, based on the global pointer. */
215 FILE *asm_out_data_file
;
216 FILE *asm_out_text_file
;
218 /* Linked list of all externals that are to be emitted when optimizing
219 for the global pointer if they haven't been declared by the end of
220 the program with an appropriate .comm or initialization. */
224 struct extern_list
*next
; /* next external */
225 const char *name
; /* name of the external */
226 int size
; /* size in bytes */
229 /* Name of the file containing the current function. */
230 const char *current_function_file
= "";
232 /* Warning given that Mips ECOFF can't support changing files
233 within a function. */
234 int file_in_function_warning
= FALSE
;
236 /* Whether to suppress issuing .loc's because the user attempted
237 to change the filename within a function. */
238 int ignore_line_number
= FALSE
;
240 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
246 /* The next branch instruction is a branch likely, not branch normal. */
247 int mips_branch_likely
;
249 /* Count of delay slots and how many are filled. */
250 int dslots_load_total
;
251 int dslots_load_filled
;
252 int dslots_jump_total
;
253 int dslots_jump_filled
;
255 /* # of nops needed by previous insn */
256 int dslots_number_nops
;
258 /* Number of 1/2/3 word references to data items (ie, not jal's). */
261 /* registers to check for load delay */
262 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
264 /* Cached operands, and operator to compare for use in set/branch/trap
265 on condition codes. */
268 /* what type of branch to use */
269 enum cmp_type branch_type
;
271 /* Number of previously seen half-pic pointers and references. */
272 static int prev_half_pic_ptrs
= 0;
273 static int prev_half_pic_refs
= 0;
275 /* The target cpu for code generation. */
276 enum processor_type mips_arch
;
278 /* The target cpu for optimization and scheduling. */
279 enum processor_type mips_tune
;
281 /* which instruction set architecture to use. */
284 /* which abi to use. */
287 /* Strings to hold which cpu and instruction set architecture to use. */
288 const char *mips_cpu_string
; /* for -mcpu=<xxx> */
289 const char *mips_arch_string
; /* for -march=<xxx> */
290 const char *mips_tune_string
; /* for -mtune=<xxx> */
291 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
292 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
294 /* Whether we are generating mips16 code. This is a synonym for
295 TARGET_MIPS16, and exists for use as an attribute. */
298 /* This variable is set by -mno-mips16. We only care whether
299 -mno-mips16 appears or not, and using a string in this fashion is
300 just a way to avoid using up another bit in target_flags. */
301 const char *mips_no_mips16_string
;
303 /* This is only used to determine if an type size setting option was
304 explicitly specified (-mlong64, -mint64, -mlong32). The specs
305 set this option if such an option is used. */
306 const char *mips_explicit_type_size_string
;
308 /* Whether we are generating mips16 hard float code. In mips16 mode
309 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
310 -msoft-float was not specified by the user, which means that we
311 should arrange to call mips32 hard floating point code. */
312 int mips16_hard_float
;
314 /* This variable is set by -mentry. We only care whether -mentry
315 appears or not, and using a string in this fashion is just a way to
316 avoid using up another bit in target_flags. */
317 const char *mips_entry_string
;
319 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
321 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
324 /* If TRUE, we split addresses into their high and low parts in the RTL. */
325 int mips_split_addresses
;
327 /* Generating calls to position independent functions? */
328 enum mips_abicalls_type mips_abicalls
;
330 /* High and low marks for floating point values which we will accept
331 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
332 initialized in override_options. */
333 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
335 /* Mode used for saving/restoring general purpose registers. */
336 static enum machine_mode gpr_mode
;
338 /* Array giving truth value on whether or not a given hard register
339 can support a given mode. */
340 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
342 /* Current frame information calculated by compute_frame_size. */
343 struct mips_frame_info current_frame_info
;
345 /* Zero structure to initialize current_frame_info. */
346 struct mips_frame_info zero_frame_info
;
348 /* The length of all strings seen when compiling for the mips16. This
349 is used to tell how many strings are in the constant pool, so that
350 we can see if we may have an overflow. This is reset each time the
351 constant pool is output. */
352 int mips_string_length
;
354 /* In mips16 mode, we build a list of all the string constants we see
355 in a particular function. */
357 struct string_constant
359 struct string_constant
*next
;
363 static struct string_constant
*string_constants
;
365 /* List of all MIPS punctuation characters used by print_operand. */
366 char mips_print_operand_punct
[256];
368 /* Map GCC register number to debugger register number. */
369 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
371 /* Buffer to use to enclose a load/store operation with %{ %} to
372 turn on .set volatile. */
373 static char volatile_buffer
[60];
375 /* Hardware names for the registers. If -mrnames is used, this
376 will be overwritten with mips_sw_reg_names. */
378 char mips_reg_names
[][8] =
380 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
381 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
382 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
383 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
384 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
385 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
386 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
387 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
388 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
389 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
390 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
391 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
392 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
393 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
394 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
395 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
396 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
397 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
398 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
399 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
400 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
401 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
404 /* Mips software names for the registers, used to overwrite the
405 mips_reg_names array. */
407 char mips_sw_reg_names
[][8] =
409 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
410 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
411 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
412 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
413 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
414 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
415 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
416 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
417 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
418 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
419 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
420 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
421 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
422 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
423 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
424 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
425 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
426 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
427 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
428 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
429 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
430 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
433 /* Map hard register number to register class */
434 const enum reg_class mips_regno_to_class
[] =
436 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
437 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
438 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
439 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
440 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
441 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
442 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
443 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
444 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
445 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
446 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
447 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
448 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
449 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
450 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
451 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
452 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
453 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
454 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
,
455 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
456 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
457 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
458 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
459 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
460 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
461 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
462 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
463 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
464 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
465 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
466 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
467 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
468 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
469 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
470 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
471 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
472 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
473 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
474 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
475 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
476 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
477 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
478 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
479 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
482 /* Map register constraint character to register class. */
483 enum reg_class mips_char_to_class
[256] =
485 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
486 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
487 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
488 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
489 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
490 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
491 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
492 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
493 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
494 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
495 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
496 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
497 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
498 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
499 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
500 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
501 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
502 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
503 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
504 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
505 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
506 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
507 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
508 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
509 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
510 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
511 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
512 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
513 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
514 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
515 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
516 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
517 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
518 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
519 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
520 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
521 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
522 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
523 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
524 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
525 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
526 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
527 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
528 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
529 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
530 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
531 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
532 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
533 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
534 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
535 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
536 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
537 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
538 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
539 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
540 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
541 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
542 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
543 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
544 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
545 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
546 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
547 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
548 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
551 /* Initialize the GCC target structure. */
552 #undef TARGET_ASM_ALIGNED_HI_OP
553 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
554 #undef TARGET_ASM_ALIGNED_SI_OP
555 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
556 #undef TARGET_ASM_INTEGER
557 #define TARGET_ASM_INTEGER mips_assemble_integer
559 #if TARGET_IRIX5 && !TARGET_IRIX6
560 #undef TARGET_ASM_UNALIGNED_HI_OP
561 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
562 #undef TARGET_ASM_UNALIGNED_SI_OP
563 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
566 #undef TARGET_ASM_FUNCTION_PROLOGUE
567 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
568 #undef TARGET_ASM_FUNCTION_EPILOGUE
569 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
571 #undef TARGET_SCHED_ADJUST_COST
572 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
574 #undef TARGET_SCHED_ISSUE_RATE
575 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
577 struct gcc_target targetm
= TARGET_INITIALIZER
;
579 /* Return truth value of whether OP can be used as an operands
580 where a register or 16 bit unsigned integer is needed. */
583 uns_arith_operand (op
, mode
)
585 enum machine_mode mode
;
587 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
590 return register_operand (op
, mode
);
593 /* Return truth value of whether OP can be used as an operands
594 where a 16 bit integer is needed */
597 arith_operand (op
, mode
)
599 enum machine_mode mode
;
601 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
604 /* On the mips16, a GP relative value is a signed 16 bit offset. */
605 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
608 return register_operand (op
, mode
);
611 /* Return truth value of whether OP can be used as an operand in a two
612 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
615 arith32_operand (op
, mode
)
617 enum machine_mode mode
;
619 if (GET_CODE (op
) == CONST_INT
)
622 return register_operand (op
, mode
);
625 /* Return truth value of whether OP is an integer which fits in 16 bits. */
630 enum machine_mode mode ATTRIBUTE_UNUSED
;
632 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
635 /* Return truth value of whether OP is a 32 bit integer which is too big to
636 be loaded with one instruction. */
641 enum machine_mode mode ATTRIBUTE_UNUSED
;
645 if (GET_CODE (op
) != CONST_INT
)
650 /* ior reg,$r0,value */
651 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
654 /* subu reg,$r0,value */
655 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
658 /* lui reg,value>>16 */
659 if ((value
& 0x0000ffff) == 0)
665 /* Return truth value of whether OP is a register or the constant 0.
666 In mips16 mode, we only accept a register, since the mips16 does
670 reg_or_0_operand (op
, mode
)
672 enum machine_mode mode
;
674 switch (GET_CODE (op
))
679 return INTVAL (op
) == 0;
684 return op
== CONST0_RTX (mode
);
688 return register_operand (op
, mode
);
697 /* Return truth value of whether OP is a register or the constant 0,
698 even in mips16 mode. */
701 true_reg_or_0_operand (op
, mode
)
703 enum machine_mode mode
;
705 switch (GET_CODE (op
))
708 return INTVAL (op
) == 0;
711 return op
== CONST0_RTX (mode
);
715 return register_operand (op
, mode
);
724 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
727 mips_const_double_ok (op
, mode
)
729 enum machine_mode mode
;
733 if (GET_CODE (op
) != CONST_DOUBLE
)
736 if (mode
== VOIDmode
)
739 if (mode
!= SFmode
&& mode
!= DFmode
)
742 if (op
== CONST0_RTX (mode
))
745 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
746 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
749 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
751 if (REAL_VALUE_ISNAN (d
))
754 if (REAL_VALUE_NEGATIVE (d
))
755 d
= REAL_VALUE_NEGATE (d
);
759 if (REAL_VALUES_LESS (d
, dfhigh
)
760 && REAL_VALUES_LESS (dflow
, d
))
765 if (REAL_VALUES_LESS (d
, sfhigh
)
766 && REAL_VALUES_LESS (sflow
, d
))
773 /* Accept the floating point constant 1 in the appropriate mode. */
776 const_float_1_operand (op
, mode
)
778 enum machine_mode mode
;
781 static REAL_VALUE_TYPE onedf
;
782 static REAL_VALUE_TYPE onesf
;
783 static int one_initialized
;
785 if (GET_CODE (op
) != CONST_DOUBLE
786 || mode
!= GET_MODE (op
)
787 || (mode
!= DFmode
&& mode
!= SFmode
))
790 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
792 /* We only initialize these values if we need them, since we will
793 never get called unless mips_isa >= 4. */
794 if (! one_initialized
)
796 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
797 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
802 return REAL_VALUES_EQUAL (d
, onedf
);
804 return REAL_VALUES_EQUAL (d
, onesf
);
807 /* Return true if a memory load or store of REG plus OFFSET in MODE
808 can be represented in a single word on the mips16. */
811 mips16_simple_memory_operand (reg
, offset
, mode
)
814 enum machine_mode mode
;
821 /* We can't tell, because we don't know how the value will
822 eventually be accessed. Returning 0 here does no great
823 harm; it just prevents some possible instruction scheduling. */
827 size
= GET_MODE_SIZE (mode
);
829 if (INTVAL (offset
) % size
!= 0)
831 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
835 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < (HOST_WIDE_INT
)(off
* size
))
840 /* Return truth value if a memory operand fits in a single instruction
841 (ie, register + small offset). */
844 simple_memory_operand (op
, mode
)
846 enum machine_mode mode
;
848 rtx addr
, plus0
, plus1
;
850 /* Eliminate non-memory operations */
851 if (GET_CODE (op
) != MEM
)
854 /* dword operations really put out 2 instructions, so eliminate them. */
855 /* ??? This isn't strictly correct. It is OK to accept multiword modes
856 here, since the length attributes are being set correctly, but only
857 if the address is offsettable. LO_SUM is not offsettable. */
858 if (GET_MODE_SIZE (GET_MODE (op
)) > (unsigned) UNITS_PER_WORD
)
861 /* Decode the address now. */
863 switch (GET_CODE (addr
))
872 return SMALL_INT (addr
);
875 plus0
= XEXP (addr
, 0);
876 plus1
= XEXP (addr
, 1);
877 if (GET_CODE (plus0
) == REG
878 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
880 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
883 else if (GET_CODE (plus1
) == REG
884 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
886 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
893 /* We used to allow small symbol refs here (ie, stuff in .sdata
894 or .sbss), but this causes some bugs in G++. Also, it won't
895 interfere if the MIPS linker rewrites the store instruction
896 because the function is PIC. */
898 case LABEL_REF
: /* never gp relative */
902 /* If -G 0, we can never have a GP relative memory operation.
903 Also, save some time if not optimizing. */
908 rtx offset
= const0_rtx
;
909 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
910 if (GET_CODE (op
) != SYMBOL_REF
)
913 /* let's be paranoid.... */
914 if (! SMALL_INT (offset
))
921 return SYMBOL_REF_FLAG (addr
);
924 /* This SYMBOL_REF case is for the mips16. If the above case is
925 reenabled, this one should be merged in. */
927 /* References to the constant pool on the mips16 use a small
928 offset if the function is small. The only time we care about
929 getting this right is during delayed branch scheduling, so
930 don't need to check until then. The machine_dependent_reorg
931 function will set the total length of the instructions used
932 in the function in current_frame_info. If that is small
933 enough, we know for sure that this is a small offset. It
934 would be better if we could take into account the location of
935 the instruction within the function, but we can't, because we
936 don't know where we are. */
938 && CONSTANT_POOL_ADDRESS_P (addr
)
939 && current_frame_info
.insns_len
> 0)
943 size
= current_frame_info
.insns_len
+ get_pool_size ();
944 if (GET_MODE_SIZE (mode
) == 4)
945 return size
< 4 * 0x100;
946 else if (GET_MODE_SIZE (mode
) == 8)
947 return size
< 8 * 0x20;
961 /* Return nonzero for a memory address that can be used to load or store
965 double_memory_operand (op
, mode
)
967 enum machine_mode mode
;
969 if (GET_CODE (op
) != MEM
970 || ! memory_operand (op
, mode
))
972 /* During reload, we accept a pseudo register if it has an
973 appropriate memory address. If we don't do this, we will
974 wind up reloading into a register, and then reloading that
975 register from memory, when we could just reload directly from
977 if (reload_in_progress
978 && GET_CODE (op
) == REG
979 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
980 && reg_renumber
[REGNO (op
)] < 0
981 && reg_equiv_mem
[REGNO (op
)] != 0
982 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
985 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
986 the same test performed for 'm' in find_reloads. */
988 if (reload_in_progress
990 && (GET_CODE (op
) == MEM
991 || (GET_CODE (op
) == REG
992 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
993 && reg_renumber
[REGNO (op
)] < 0)))
996 if (reload_in_progress
998 && GET_CODE (op
) == MEM
)
1002 addr
= XEXP (op
, 0);
1004 /* During reload on the mips16, we accept a large offset
1005 from the frame pointer or the stack pointer. This large
1006 address will get reloaded anyhow. */
1007 if (GET_CODE (addr
) == PLUS
1008 && GET_CODE (XEXP (addr
, 0)) == REG
1009 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1010 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1011 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1012 && ! SMALL_INT (XEXP (addr
, 1)))
1013 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1014 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1017 /* Similarly, we accept a case where the memory address is
1018 itself on the stack, and will be reloaded. */
1019 if (GET_CODE (addr
) == MEM
)
1023 maddr
= XEXP (addr
, 0);
1024 if (GET_CODE (maddr
) == PLUS
1025 && GET_CODE (XEXP (maddr
, 0)) == REG
1026 && (REGNO (XEXP (maddr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1027 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
1028 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
1029 && ! SMALL_INT (XEXP (maddr
, 1)))
1030 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
1031 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
1035 /* We also accept the same case when we have a 16 bit signed
1036 offset mixed in as well. The large address will get
1037 reloaded, and the 16 bit offset will be OK. */
1038 if (GET_CODE (addr
) == PLUS
1039 && GET_CODE (XEXP (addr
, 0)) == MEM
1040 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
1041 && SMALL_INT (XEXP (addr
, 1)))
1043 addr
= XEXP (XEXP (addr
, 0), 0);
1044 if (GET_CODE (addr
) == PLUS
1045 && GET_CODE (XEXP (addr
, 0)) == REG
1046 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1047 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1048 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1049 && ! SMALL_INT (XEXP (addr
, 1)))
1050 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1051 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1061 /* In this case we can use an instruction like sd. */
1065 /* Make sure that 4 added to the address is a valid memory address.
1066 This essentially just checks for overflow in an added constant. */
1068 if (CONSTANT_ADDRESS_P (XEXP (op
, 0)))
1071 op
= adjust_address_nv (op
, GET_MODE_CLASS (mode
) == MODE_INT
1072 ? SImode
: SFmode
, 4);
1073 return memory_address_p (GET_MODE (op
), XEXP (op
, 0));
1076 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1079 equality_op (op
, mode
)
1081 enum machine_mode mode
;
1083 if (mode
!= GET_MODE (op
))
1086 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
1089 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1094 enum machine_mode mode
;
1096 if (mode
!= GET_MODE (op
))
1099 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
1102 /* Return nonzero if the code is a relational operation suitable for a
1103 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1104 We need this in the insn that expands `trap_if' in order to prevent
1105 combine from erroneously altering the condition. */
1108 trap_cmp_op (op
, mode
)
1110 enum machine_mode mode
;
1112 if (mode
!= GET_MODE (op
))
1115 switch (GET_CODE (op
))
1130 /* Return nonzero if the operand is either the PC or a label_ref. */
1133 pc_or_label_operand (op
, mode
)
1135 enum machine_mode mode ATTRIBUTE_UNUSED
;
1140 if (GET_CODE (op
) == LABEL_REF
)
1146 /* Test for a valid operand for a call instruction.
1147 Don't allow the arg pointer register or virtual regs
1148 since they may change into reg + const, which the patterns
1149 can't handle yet. */
1152 call_insn_operand (op
, mode
)
1154 enum machine_mode mode ATTRIBUTE_UNUSED
;
1156 return (CONSTANT_ADDRESS_P (op
)
1157 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
1158 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1159 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
1162 /* Return nonzero if OPERAND is valid as a source operand for a move
1166 move_operand (op
, mode
)
1168 enum machine_mode mode
;
1170 /* Accept any general operand after reload has started; doing so
1171 avoids losing if reload does an in-place replacement of a register
1172 with a SYMBOL_REF or CONST. */
1173 return (general_operand (op
, mode
)
1174 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1175 || reload_in_progress
|| reload_completed
)
1177 && GET_CODE (op
) == SYMBOL_REF
1178 && ! mips16_constant (op
, mode
, 1, 0)));
1181 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1182 This accepts not only general_operand, but also sign extended
1183 constants and registers. We need to accept sign extended constants
1184 in case a sign extended register which is used in an expression,
1185 and is equivalent to a constant, is spilled. */
1188 movdi_operand (op
, mode
)
1190 enum machine_mode mode
;
1194 && GET_CODE (op
) == SIGN_EXTEND
1195 && GET_MODE (op
) == DImode
1196 && (GET_MODE (XEXP (op
, 0)) == SImode
1197 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
1198 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
1199 && (register_operand (XEXP (op
, 0), SImode
)
1200 || immediate_operand (XEXP (op
, 0), SImode
)))
1203 return (general_operand (op
, mode
)
1205 && GET_CODE (op
) == SYMBOL_REF
1206 && ! mips16_constant (op
, mode
, 1, 0)));
1209 /* Like register_operand, but when in 64 bit mode also accept a sign
1210 extend of a 32 bit register, since the value is known to be already
1214 se_register_operand (op
, mode
)
1216 enum machine_mode mode
;
1220 && GET_CODE (op
) == SIGN_EXTEND
1221 && GET_MODE (op
) == DImode
1222 && GET_MODE (XEXP (op
, 0)) == SImode
1223 && register_operand (XEXP (op
, 0), SImode
))
1226 return register_operand (op
, mode
);
1229 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1230 extend of a 32 bit register, since the value is known to be already
1234 se_reg_or_0_operand (op
, mode
)
1236 enum machine_mode mode
;
1240 && GET_CODE (op
) == SIGN_EXTEND
1241 && GET_MODE (op
) == DImode
1242 && GET_MODE (XEXP (op
, 0)) == SImode
1243 && register_operand (XEXP (op
, 0), SImode
))
1246 return reg_or_0_operand (op
, mode
);
1249 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1250 extend of a 32 bit register, since the value is known to be already
1254 se_uns_arith_operand (op
, mode
)
1256 enum machine_mode mode
;
1260 && GET_CODE (op
) == SIGN_EXTEND
1261 && GET_MODE (op
) == DImode
1262 && GET_MODE (XEXP (op
, 0)) == SImode
1263 && register_operand (XEXP (op
, 0), SImode
))
1266 return uns_arith_operand (op
, mode
);
1269 /* Like arith_operand, but when in 64 bit mode also accept a sign
1270 extend of a 32 bit register, since the value is known to be already
1274 se_arith_operand (op
, mode
)
1276 enum machine_mode mode
;
1280 && GET_CODE (op
) == SIGN_EXTEND
1281 && GET_MODE (op
) == DImode
1282 && GET_MODE (XEXP (op
, 0)) == SImode
1283 && register_operand (XEXP (op
, 0), SImode
))
1286 return arith_operand (op
, mode
);
1289 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1290 extend of a 32 bit register, since the value is known to be already
1294 se_nonmemory_operand (op
, mode
)
1296 enum machine_mode mode
;
1300 && GET_CODE (op
) == SIGN_EXTEND
1301 && GET_MODE (op
) == DImode
1302 && GET_MODE (XEXP (op
, 0)) == SImode
1303 && register_operand (XEXP (op
, 0), SImode
))
1306 return nonmemory_operand (op
, mode
);
1309 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1310 sign extend of a 32 bit register, since the value is known to be
1311 already sign extended. */
1314 se_nonimmediate_operand (op
, mode
)
1316 enum machine_mode mode
;
1320 && GET_CODE (op
) == SIGN_EXTEND
1321 && GET_MODE (op
) == DImode
1322 && GET_MODE (XEXP (op
, 0)) == SImode
1323 && register_operand (XEXP (op
, 0), SImode
))
1326 return nonimmediate_operand (op
, mode
);
1329 /* Accept any operand that can appear in a mips16 constant table
1330 instruction. We can't use any of the standard operand functions
1331 because for these instructions we accept values that are not
1332 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1335 consttable_operand (op
, mode
)
1337 enum machine_mode mode ATTRIBUTE_UNUSED
;
1339 return CONSTANT_P (op
);
1342 /* Coprocessor operand; return true if rtx is a REG and refers to a
1346 coprocessor_operand (op
, mode
)
1348 enum machine_mode mode ATTRIBUTE_UNUSED
;
1350 return (GET_CODE (op
) == REG
1351 && COP0_REG_FIRST
<= REGNO (op
)
1352 && REGNO (op
) <= COP3_REG_LAST
);
1356 coprocessor2_operand (op
, mode
)
1358 enum machine_mode mode ATTRIBUTE_UNUSED
;
1360 return (GET_CODE (op
) == REG
1361 && COP2_REG_FIRST
<= REGNO (op
)
1362 && REGNO (op
) <= COP2_REG_LAST
);
1365 /* Return nonzero if we split the address into high and low parts. */
1367 /* ??? We should also handle reg+array somewhere. We get four
1368 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1369 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1370 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1371 out of the address, then we have 4 instructions to combine. Perhaps
1372 add a 3->2 define_split for combine. */
1374 /* ??? We could also split a CONST_INT here if it is a large_int().
1375 However, it doesn't seem to be very useful to have %hi(constant).
1376 We would be better off by doing the masking ourselves and then putting
1377 the explicit high part of the constant in the RTL. This will give better
1378 optimization. Also, %hi(constant) needs assembler changes to work.
1379 There is already a define_split that does this. */
1382 mips_check_split (address
, mode
)
1384 enum machine_mode mode
;
1386 /* ??? This is the same check used in simple_memory_operand.
1387 We use it here because LO_SUM is not offsettable. */
1388 if (GET_MODE_SIZE (mode
) > (unsigned) UNITS_PER_WORD
)
1391 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1392 || (GET_CODE (address
) == CONST
1393 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1394 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1395 || GET_CODE (address
) == LABEL_REF
)
1401 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1404 mips_reg_mode_ok_for_base_p (reg
, mode
, strict
)
1406 enum machine_mode mode
;
1410 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg
), mode
)
1411 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg
), mode
));
1414 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1415 returns a nonzero value if XINSN is a legitimate address for a
1416 memory operand of the indicated MODE. STRICT is non-zero if this
1417 function is called during reload. */
1420 mips_legitimate_address_p (mode
, xinsn
, strict
)
1421 enum machine_mode mode
;
1425 if (TARGET_DEBUG_B_MODE
)
1427 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1428 strict
? "" : "not ");
1429 GO_DEBUG_RTX (xinsn
);
1432 /* Check for constant before stripping off SUBREG, so that we don't
1433 accept (subreg (const_int)) which will fail to reload. */
1434 if (CONSTANT_ADDRESS_P (xinsn
)
1435 && ! (mips_split_addresses
&& mips_check_split (xinsn
, mode
))
1436 && (! TARGET_MIPS16
|| mips16_constant (xinsn
, mode
, 1, 0)))
1439 while (GET_CODE (xinsn
) == SUBREG
)
1440 xinsn
= SUBREG_REG (xinsn
);
1442 /* The mips16 can only use the stack pointer as a base register when
1443 loading SImode or DImode values. */
1444 if (GET_CODE (xinsn
) == REG
1445 && mips_reg_mode_ok_for_base_p (xinsn
, mode
, strict
))
1448 if (GET_CODE (xinsn
) == LO_SUM
&& mips_split_addresses
)
1450 register rtx xlow0
= XEXP (xinsn
, 0);
1451 register rtx xlow1
= XEXP (xinsn
, 1);
1453 while (GET_CODE (xlow0
) == SUBREG
)
1454 xlow0
= SUBREG_REG (xlow0
);
1455 if (GET_CODE (xlow0
) == REG
1456 && mips_reg_mode_ok_for_base_p (xlow0
, mode
, strict
)
1457 && mips_check_split (xlow1
, mode
))
1461 if (GET_CODE (xinsn
) == PLUS
)
1463 register rtx xplus0
= XEXP (xinsn
, 0);
1464 register rtx xplus1
= XEXP (xinsn
, 1);
1465 register enum rtx_code code0
;
1466 register enum rtx_code code1
;
1468 while (GET_CODE (xplus0
) == SUBREG
)
1469 xplus0
= SUBREG_REG (xplus0
);
1470 code0
= GET_CODE (xplus0
);
1472 while (GET_CODE (xplus1
) == SUBREG
)
1473 xplus1
= SUBREG_REG (xplus1
);
1474 code1
= GET_CODE (xplus1
);
1476 /* The mips16 can only use the stack pointer as a base register
1477 when loading SImode or DImode values. */
1479 && mips_reg_mode_ok_for_base_p (xplus0
, mode
, strict
))
1481 if (code1
== CONST_INT
&& SMALL_INT (xplus1
))
1484 /* On the mips16, we represent GP relative offsets in RTL.
1485 These are 16 bit signed values, and can serve as register
1488 && mips16_gp_offset_p (xplus1
))
1491 /* For some code sequences, you actually get better code by
1492 pretending that the MIPS supports an address mode of a
1493 constant address + a register, even though the real
1494 machine doesn't support it. This is because the
1495 assembler can use $r1 to load just the high 16 bits, add
1496 in the register, and fold the low 16 bits into the memory
1497 reference, whereas the compiler generates a 4 instruction
1498 sequence. On the other hand, CSE is not as effective.
1499 It would be a win to generate the lui directly, but the
1500 MIPS assembler does not have syntax to generate the
1501 appropriate relocation. */
1503 /* Also accept CONST_INT addresses here, so no else. */
1504 /* Reject combining an embedded PIC text segment reference
1505 with a register. That requires an additional
1507 /* ??? Reject combining an address with a register for the MIPS
1508 64 bit ABI, because the SGI assembler can not handle this. */
1509 if (!TARGET_DEBUG_A_MODE
1510 && (mips_abi
== ABI_32
1511 || mips_abi
== ABI_O64
1512 || mips_abi
== ABI_EABI
)
1513 && CONSTANT_ADDRESS_P (xplus1
)
1514 && ! mips_split_addresses
1515 && (!TARGET_EMBEDDED_PIC
1517 || GET_CODE (XEXP (xplus1
, 0)) != MINUS
)
1518 /* When assembling for machines with 64 bit registers,
1519 the assembler will sign-extend the constant "foo"
1520 in "la x, foo(x)" yielding the wrong result for:
1521 (set (blah:DI) (plus x y)). */
1523 || (code1
== CONST_INT
1524 && trunc_int_for_mode (INTVAL (xplus1
),
1525 SImode
) == INTVAL (xplus1
)))
1531 if (TARGET_DEBUG_B_MODE
)
1532 GO_PRINTF ("Not a legitimate address\n");
1534 /* The address was not legitimate. */
1539 /* We need a lot of little routines to check constant values on the
1540 mips16. These are used to figure out how long the instruction will
1541 be. It would be much better to do this using constraints, but
1542 there aren't nearly enough letters available. */
1545 m16_check_op (op
, low
, high
, mask
)
1551 return (GET_CODE (op
) == CONST_INT
1552 && INTVAL (op
) >= low
1553 && INTVAL (op
) <= high
1554 && (INTVAL (op
) & mask
) == 0);
1558 m16_uimm3_b (op
, mode
)
1560 enum machine_mode mode ATTRIBUTE_UNUSED
;
1562 return m16_check_op (op
, 0x1, 0x8, 0);
1566 m16_simm4_1 (op
, mode
)
1568 enum machine_mode mode ATTRIBUTE_UNUSED
;
1570 return m16_check_op (op
, - 0x8, 0x7, 0);
1574 m16_nsimm4_1 (op
, mode
)
1576 enum machine_mode mode ATTRIBUTE_UNUSED
;
1578 return m16_check_op (op
, - 0x7, 0x8, 0);
1582 m16_simm5_1 (op
, mode
)
1584 enum machine_mode mode ATTRIBUTE_UNUSED
;
1586 return m16_check_op (op
, - 0x10, 0xf, 0);
1590 m16_nsimm5_1 (op
, mode
)
1592 enum machine_mode mode ATTRIBUTE_UNUSED
;
1594 return m16_check_op (op
, - 0xf, 0x10, 0);
1598 m16_uimm5_4 (op
, mode
)
1600 enum machine_mode mode ATTRIBUTE_UNUSED
;
1602 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1606 m16_nuimm5_4 (op
, mode
)
1608 enum machine_mode mode ATTRIBUTE_UNUSED
;
1610 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1614 m16_simm8_1 (op
, mode
)
1616 enum machine_mode mode ATTRIBUTE_UNUSED
;
1618 return m16_check_op (op
, - 0x80, 0x7f, 0);
1622 m16_nsimm8_1 (op
, mode
)
1624 enum machine_mode mode ATTRIBUTE_UNUSED
;
1626 return m16_check_op (op
, - 0x7f, 0x80, 0);
1630 m16_uimm8_1 (op
, mode
)
1632 enum machine_mode mode ATTRIBUTE_UNUSED
;
1634 return m16_check_op (op
, 0x0, 0xff, 0);
1638 m16_nuimm8_1 (op
, mode
)
1640 enum machine_mode mode ATTRIBUTE_UNUSED
;
1642 return m16_check_op (op
, - 0xff, 0x0, 0);
1646 m16_uimm8_m1_1 (op
, mode
)
1648 enum machine_mode mode ATTRIBUTE_UNUSED
;
1650 return m16_check_op (op
, - 0x1, 0xfe, 0);
1654 m16_uimm8_4 (op
, mode
)
1656 enum machine_mode mode ATTRIBUTE_UNUSED
;
1658 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1662 m16_nuimm8_4 (op
, mode
)
1664 enum machine_mode mode ATTRIBUTE_UNUSED
;
1666 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1670 m16_simm8_8 (op
, mode
)
1672 enum machine_mode mode ATTRIBUTE_UNUSED
;
1674 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1678 m16_nsimm8_8 (op
, mode
)
1680 enum machine_mode mode ATTRIBUTE_UNUSED
;
1682 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1685 /* References to the string table on the mips16 only use a small
1686 offset if the function is small. See the comment in the SYMBOL_REF
1687 case in simple_memory_operand. We can't check for LABEL_REF here,
1688 because the offset is always large if the label is before the
1689 referencing instruction. */
1692 m16_usym8_4 (op
, mode
)
1694 enum machine_mode mode ATTRIBUTE_UNUSED
;
1696 if (GET_CODE (op
) == SYMBOL_REF
1697 && SYMBOL_REF_FLAG (op
)
1698 && current_frame_info
.insns_len
> 0
1699 && XSTR (op
, 0)[0] == '*'
1700 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1701 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1702 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1705 struct string_constant
*l
;
1707 /* Make sure this symbol is on thelist of string constants to be
1708 output for this function. It is possible that it has already
1709 been output, in which case this requires a large offset. */
1710 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1711 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1719 m16_usym5_4 (op
, mode
)
1721 enum machine_mode mode ATTRIBUTE_UNUSED
;
1723 if (GET_CODE (op
) == SYMBOL_REF
1724 && SYMBOL_REF_FLAG (op
)
1725 && current_frame_info
.insns_len
> 0
1726 && XSTR (op
, 0)[0] == '*'
1727 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1728 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1729 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1732 struct string_constant
*l
;
1734 /* Make sure this symbol is on thelist of string constants to be
1735 output for this function. It is possible that it has already
1736 been output, in which case this requires a large offset. */
1737 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1738 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1745 /* Returns an operand string for the given instruction's delay slot,
1746 after updating filled delay slot statistics.
1748 We assume that operands[0] is the target register that is set.
1750 In order to check the next insn, most of this functionality is moved
1751 to FINAL_PRESCAN_INSN, and we just set the global variables that
1754 /* ??? This function no longer does anything useful, because final_prescan_insn
1755 now will never emit a nop. */
1758 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1759 const char *ret
; /* normal string to return */
1760 enum delay_type type
; /* type of delay */
1761 rtx operands
[]; /* operands to use */
1762 rtx cur_insn
; /* current insn */
1764 register rtx set_reg
;
1765 register enum machine_mode mode
;
1766 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1767 register int num_nops
;
1769 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1772 else if (type
== DELAY_HILO
)
1778 /* Make sure that we don't put nop's after labels. */
1779 next_insn
= NEXT_INSN (cur_insn
);
1780 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1781 next_insn
= NEXT_INSN (next_insn
);
1783 dslots_load_total
+= num_nops
;
1784 if (TARGET_DEBUG_F_MODE
1786 || type
== DELAY_NONE
1790 || GET_CODE (next_insn
) == CODE_LABEL
1791 || (set_reg
= operands
[0]) == 0)
1793 dslots_number_nops
= 0;
1801 set_reg
= operands
[0];
1805 while (GET_CODE (set_reg
) == SUBREG
)
1806 set_reg
= SUBREG_REG (set_reg
);
1808 mode
= GET_MODE (set_reg
);
1809 dslots_number_nops
= num_nops
;
1810 mips_load_reg
= set_reg
;
1811 if (GET_MODE_SIZE (mode
)
1812 > (unsigned) (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1813 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1817 if (type
== DELAY_HILO
)
1819 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1820 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1832 /* Determine whether a memory reference takes one (based off of the GP
1833 pointer), two (normal), or three (label + reg) instructions, and bump the
1834 appropriate counter for -mstats. */
1837 mips_count_memory_refs (op
, num
)
1843 rtx addr
, plus0
, plus1
;
1844 enum rtx_code code0
, code1
;
1847 if (TARGET_DEBUG_B_MODE
)
1849 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1853 /* Skip MEM if passed, otherwise handle movsi of address. */
1854 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1856 /* Loop, going through the address RTL. */
1860 switch (GET_CODE (addr
))
1868 plus0
= XEXP (addr
, 0);
1869 plus1
= XEXP (addr
, 1);
1870 code0
= GET_CODE (plus0
);
1871 code1
= GET_CODE (plus1
);
1881 if (code0
== CONST_INT
)
1896 if (code1
== CONST_INT
)
1903 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1910 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1920 n_words
= 2; /* always 2 words */
1924 addr
= XEXP (addr
, 0);
1929 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1941 n_words
+= additional
;
1945 num_refs
[n_words
-1] += num
;
1949 /* Return a pseudo that points to the address of the current function.
1950 The first time it is called for a function, an initializer for the
1951 pseudo is emitted in the beginning of the function. */
1954 embedded_pic_fnaddr_reg ()
1956 if (cfun
->machine
->embedded_pic_fnaddr_rtx
== NULL
)
1960 cfun
->machine
->embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1962 /* Output code at function start to initialize the pseudo-reg. */
1963 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1964 inline functions, because it is called after RTL for the function
1965 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1966 does not get copied, and ends up not matching the rest of the RTL.
1967 This solution works, but means that we get unnecessary code to
1968 initialize this value every time a function is inlined into another
1971 emit_insn (gen_get_fnaddr (cfun
->machine
->embedded_pic_fnaddr_rtx
,
1972 XEXP (DECL_RTL (current_function_decl
), 0)));
1973 seq
= gen_sequence ();
1975 push_topmost_sequence ();
1976 emit_insn_after (seq
, get_insns ());
1977 pop_topmost_sequence ();
1980 return cfun
->machine
->embedded_pic_fnaddr_rtx
;
1983 /* Return RTL for the offset from the current function to the argument.
1984 X is the symbol whose offset from the current function we want. */
1987 embedded_pic_offset (x
)
1990 /* Make sure it is emitted. */
1991 embedded_pic_fnaddr_reg ();
1994 gen_rtx_CONST (Pmode
,
1995 gen_rtx_MINUS (Pmode
, x
,
1996 XEXP (DECL_RTL (current_function_decl
), 0)));
1999 /* Return the appropriate instructions to move one operand to another. */
2002 mips_move_1word (operands
, insn
, unsignedp
)
2007 const char *ret
= 0;
2008 rtx op0
= operands
[0];
2009 rtx op1
= operands
[1];
2010 enum rtx_code code0
= GET_CODE (op0
);
2011 enum rtx_code code1
= GET_CODE (op1
);
2012 enum machine_mode mode
= GET_MODE (op0
);
2013 int subreg_offset0
= 0;
2014 int subreg_offset1
= 0;
2015 enum delay_type delay
= DELAY_NONE
;
2017 while (code0
== SUBREG
)
2019 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2020 GET_MODE (SUBREG_REG (op0
)),
2023 op0
= SUBREG_REG (op0
);
2024 code0
= GET_CODE (op0
);
2027 while (code1
== SUBREG
)
2029 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2030 GET_MODE (SUBREG_REG (op1
)),
2033 op1
= SUBREG_REG (op1
);
2034 code1
= GET_CODE (op1
);
2037 /* For our purposes, a condition code mode is the same as SImode. */
2043 int regno0
= REGNO (op0
) + subreg_offset0
;
2047 int regno1
= REGNO (op1
) + subreg_offset1
;
2049 /* Just in case, don't do anything for assigning a register
2050 to itself, unless we are filling a delay slot. */
2051 if (regno0
== regno1
&& set_nomacro
== 0)
2054 else if (GP_REG_P (regno0
))
2056 if (GP_REG_P (regno1
))
2057 ret
= "move\t%0,%1";
2059 else if (MD_REG_P (regno1
))
2062 if (regno1
!= HILO_REGNUM
)
2068 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
2069 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
2074 if (FP_REG_P (regno1
))
2075 ret
= "mfc1\t%0,%1";
2076 else if (ALL_COP_REG_P (regno1
))
2078 static char retval
[] = "mfc_\t%0,%1";
2080 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2083 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2084 ret
= "cfc1\t%0,$31";
2088 else if (FP_REG_P (regno0
))
2090 if (GP_REG_P (regno1
))
2093 ret
= "mtc1\t%1,%0";
2096 if (FP_REG_P (regno1
))
2097 ret
= "mov.s\t%0,%1";
2100 else if (MD_REG_P (regno0
))
2102 if (GP_REG_P (regno1
))
2105 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
2110 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2112 if (GP_REG_P (regno1
))
2115 ret
= "ctc1\t%0,$31";
2118 else if (ALL_COP_REG_P (regno0
))
2120 if (GP_REG_P (regno1
))
2122 static char retval
[] = "mtc_\t%1,%0";
2123 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2126 abort_with_insn (insn
,
2127 "mtc0 not supported; it disturbs virtual address translation");
2135 else if (code1
== MEM
)
2140 mips_count_memory_refs (op1
, 1);
2142 if (GP_REG_P (regno0
))
2144 /* For loads, use the mode of the memory item, instead of the
2145 target, so zero/sign extend can use this code as well. */
2146 switch (GET_MODE (op1
))
2155 ret
= ((unsignedp
&& TARGET_64BIT
)
2160 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
2163 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
2168 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
2171 else if (ALL_COP_REG_P (regno0
))
2173 static char retval
[] = "lwc_\t%0,%1";
2174 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2177 abort_with_insn (insn
,
2178 "loads from memory to COP0 are illegal");
2184 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
2186 size_t i
= strlen (ret
);
2187 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2190 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2191 ret
= volatile_buffer
;
2195 else if (code1
== CONST_INT
2196 || (code1
== CONST_DOUBLE
2197 && GET_MODE (op1
) == VOIDmode
))
2199 if (code1
== CONST_DOUBLE
)
2201 /* This can happen when storing constants into long long
2202 bitfields. Just store the least significant word of
2204 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2207 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2209 if (GP_REG_P (regno0
))
2210 ret
= "move\t%0,%z1";
2212 else if (FP_REG_P (regno0
))
2215 ret
= "mtc1\t%z1,%0";
2218 else if (MD_REG_P (regno0
))
2225 else if (GP_REG_P (regno0
))
2227 /* Don't use X format, because that will give out of
2228 range numbers for 64 bit host and 32 bit target. */
2229 if (! TARGET_MIPS16
)
2230 ret
= "li\t%0,%1\t\t\t# %X1";
2233 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2235 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2236 ret
= "li\t%0,%n1\n\tneg\t%0";
2241 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
2243 if (op1
== CONST0_RTX (SFmode
))
2245 if (GP_REG_P (regno0
))
2246 ret
= "move\t%0,%.";
2248 else if (FP_REG_P (regno0
))
2251 ret
= "mtc1\t%.,%0";
2258 ret
= "li.s\t%0,%1";
2262 else if (code1
== LABEL_REF
)
2265 mips_count_memory_refs (op1
, 1);
2270 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2272 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
2274 rtx offset
= const0_rtx
;
2276 if (GET_CODE (op1
) == CONST
)
2277 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
2279 if (GET_CODE (op1
) == SYMBOL_REF
)
2281 operands
[2] = HALF_PIC_PTR (op1
);
2284 mips_count_memory_refs (operands
[2], 1);
2286 if (INTVAL (offset
) == 0)
2289 ret
= (unsignedp
&& TARGET_64BIT
2295 dslots_load_total
++;
2296 operands
[3] = offset
;
2297 if (unsignedp
&& TARGET_64BIT
)
2298 ret
= (SMALL_INT (offset
)
2299 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2300 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2302 ret
= (SMALL_INT (offset
)
2303 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2304 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2308 else if (TARGET_MIPS16
2310 && GET_CODE (XEXP (op1
, 0)) == REG
2311 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2313 /* This case arises on the mips16; see
2314 mips16_gp_pseudo_reg. */
2315 ret
= "move\t%0,%+";
2317 else if (TARGET_MIPS16
2318 && code1
== SYMBOL_REF
2319 && SYMBOL_REF_FLAG (op1
)
2320 && (XSTR (op1
, 0)[0] != '*'
2321 || strncmp (XSTR (op1
, 0) + 1,
2323 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2325 /* This can occur when reloading the address of a GP
2326 relative symbol on the mips16. */
2327 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2332 mips_count_memory_refs (op1
, 1);
2338 else if (code1
== PLUS
)
2340 rtx add_op0
= XEXP (op1
, 0);
2341 rtx add_op1
= XEXP (op1
, 1);
2343 if (GET_CODE (XEXP (op1
, 1)) == REG
2344 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
2345 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
2347 operands
[2] = add_op0
;
2348 operands
[3] = add_op1
;
2349 ret
= "add%:\t%0,%2,%3";
2352 else if (code1
== HIGH
)
2354 operands
[1] = XEXP (op1
, 0);
2355 ret
= "lui\t%0,%%hi(%1)";
2359 else if (code0
== MEM
)
2362 mips_count_memory_refs (op0
, 1);
2366 int regno1
= REGNO (op1
) + subreg_offset1
;
2368 if (GP_REG_P (regno1
))
2372 case SFmode
: ret
= "sw\t%1,%0"; break;
2373 case SImode
: ret
= "sw\t%1,%0"; break;
2374 case HImode
: ret
= "sh\t%1,%0"; break;
2375 case QImode
: ret
= "sb\t%1,%0"; break;
2380 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2382 else if (ALL_COP_REG_P (regno1
))
2384 static char retval
[] = "swc_\t%1,%0";
2386 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2391 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2395 case SFmode
: ret
= "sw\t%z1,%0"; break;
2396 case SImode
: ret
= "sw\t%z1,%0"; break;
2397 case HImode
: ret
= "sh\t%z1,%0"; break;
2398 case QImode
: ret
= "sb\t%z1,%0"; break;
2403 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2407 case SFmode
: ret
= "sw\t%.,%0"; break;
2408 case SImode
: ret
= "sw\t%.,%0"; break;
2409 case HImode
: ret
= "sh\t%.,%0"; break;
2410 case QImode
: ret
= "sb\t%.,%0"; break;
2415 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2417 size_t i
= strlen (ret
);
2419 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2422 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2423 ret
= volatile_buffer
;
2429 abort_with_insn (insn
, "bad move");
2433 if (delay
!= DELAY_NONE
)
2434 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2440 /* Return the appropriate instructions to move 2 words */
2443 mips_move_2words (operands
, insn
)
2447 const char *ret
= 0;
2448 rtx op0
= operands
[0];
2449 rtx op1
= operands
[1];
2450 enum rtx_code code0
= GET_CODE (operands
[0]);
2451 enum rtx_code code1
= GET_CODE (operands
[1]);
2452 int subreg_offset0
= 0;
2453 int subreg_offset1
= 0;
2454 enum delay_type delay
= DELAY_NONE
;
2456 while (code0
== SUBREG
)
2458 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2459 GET_MODE (SUBREG_REG (op0
)),
2462 op0
= SUBREG_REG (op0
);
2463 code0
= GET_CODE (op0
);
2466 if (code1
== SIGN_EXTEND
)
2468 op1
= XEXP (op1
, 0);
2469 code1
= GET_CODE (op1
);
2472 while (code1
== SUBREG
)
2474 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2475 GET_MODE (SUBREG_REG (op1
)),
2478 op1
= SUBREG_REG (op1
);
2479 code1
= GET_CODE (op1
);
2483 if (GET_CODE (operands
[1]) == SIGN_EXTEND
2485 && code1
!= CONST_INT
2486 /* The following three can happen as the result of a questionable
2488 && code1
!= LABEL_REF
2489 && code1
!= SYMBOL_REF
2495 int regno0
= REGNO (op0
) + subreg_offset0
;
2499 int regno1
= REGNO (op1
) + subreg_offset1
;
2501 /* Just in case, don't do anything for assigning a register
2502 to itself, unless we are filling a delay slot. */
2503 if (regno0
== regno1
&& set_nomacro
== 0)
2506 else if (FP_REG_P (regno0
))
2508 if (FP_REG_P (regno1
))
2509 ret
= "mov.d\t%0,%1";
2517 abort_with_insn (insn
, "bad move");
2519 #ifdef TARGET_FP_CALL_32
2520 if (FP_CALL_GP_REG_P (regno1
))
2521 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2524 ret
= "dmtc1\t%1,%0";
2527 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2531 else if (FP_REG_P (regno1
))
2537 abort_with_insn (insn
, "bad move");
2539 #ifdef TARGET_FP_CALL_32
2540 if (FP_CALL_GP_REG_P (regno0
))
2541 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2544 ret
= "dmfc1\t%0,%1";
2547 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2550 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2555 if (regno0
!= HILO_REGNUM
)
2557 else if (regno1
== 0)
2558 ret
= "mtlo\t%.\n\tmthi\t%.";
2561 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2564 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2569 if (regno1
!= HILO_REGNUM
)
2573 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2575 else if (GP_REG_P (regno0
) && ALL_COP_REG_P (regno1
)
2578 static char retval
[] = "dmfc_\t%0,%1";
2581 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2584 else if (ALL_COP_REG_P (regno0
) && GP_REG_P (regno1
)
2587 static char retval
[] = "dmtc_\t%1,%0";
2588 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2591 abort_with_insn (insn
,
2592 "dmtc0 not supported; it disturbs virtual address translation");
2597 else if (TARGET_64BIT
)
2598 ret
= "move\t%0,%1";
2600 else if (regno0
!= (regno1
+1))
2601 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2604 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2607 else if (code1
== CONST_DOUBLE
)
2609 /* Move zero from $0 unless !TARGET_64BIT and recipient
2610 is 64-bit fp reg, in which case generate a constant. */
2611 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2612 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2614 if (GET_MODE (op1
) == DFmode
)
2618 #ifdef TARGET_FP_CALL_32
2619 if (FP_CALL_GP_REG_P (regno0
))
2621 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2623 split_double (op1
, operands
+ 2, operands
+ 3);
2624 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2627 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2631 /* GNU as emits 64-bit code for li.d if the ISA is 3
2632 or higher. For !TARGET_64BIT && gp registers we
2633 need to avoid this by using two li instructions
2635 if (ISA_HAS_64BIT_REGS
2637 && ! FP_REG_P (regno0
))
2639 split_double (op1
, operands
+ 2, operands
+ 3);
2640 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2643 ret
= "li.d\t%0,%1";
2646 else if (TARGET_64BIT
)
2648 if (! TARGET_MIPS16
)
2654 split_double (op1
, operands
+ 2, operands
+ 3);
2655 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2661 if (GP_REG_P (regno0
))
2663 #ifdef TARGET_FP_CALL_32
2664 && ! FP_CALL_GP_REG_P (regno0
)
2667 : "move\t%0,%.\n\tmove\t%D0,%.");
2669 else if (FP_REG_P (regno0
))
2674 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2679 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2681 if (GP_REG_P (regno0
))
2684 : "move\t%0,%.\n\tmove\t%D0,%.");
2686 else if (FP_REG_P (regno0
))
2693 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2695 else if (MD_REG_P (regno0
))
2698 ret
= (regno0
== HILO_REGNUM
2699 ? "mtlo\t%.\n\tmthi\t%."
2704 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2705 && GP_REG_P (regno0
))
2711 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2713 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2714 ret
= "li\t%0,%n1\n\tneg\t%0";
2716 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2717 ret
= "li\t%0,%1\t\t# %X1";
2718 else if (HOST_BITS_PER_WIDE_INT
< 64)
2719 /* We can't use 'X' for negative numbers, because then we won't
2720 get the right value for the upper 32 bits. */
2721 ret
= (INTVAL (op1
) < 0
2722 ? "dli\t%0,%1\t\t\t# %X1"
2723 : "dli\t%0,%X1\t\t# %1");
2725 /* We must use 'X', because otherwise LONG_MIN will print as
2726 a number that the assembler won't accept. */
2727 ret
= "dli\t%0,%X1\t\t# %1";
2729 else if (HOST_BITS_PER_WIDE_INT
< 64)
2731 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2734 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2735 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2736 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2738 operands
[2] = GEN_INT (1);
2739 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2743 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2747 /* We use multiple shifts here, to avoid warnings about out
2748 of range shifts on 32 bit hosts. */
2749 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2751 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2754 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2755 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2756 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2758 operands
[2] = GEN_INT (1);
2759 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2763 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2767 else if (code1
== MEM
)
2772 mips_count_memory_refs (op1
, 2);
2774 if (FP_REG_P (regno0
))
2777 else if (ALL_COP_REG_P (regno0
) && TARGET_64BIT
)
2779 static char retval
[] = "ldc_\t%0,%1";
2780 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2783 abort_with_insn (insn
,
2784 "loads from memory to COP0 are illegal");
2790 else if (TARGET_64BIT
)
2793 #ifdef TARGET_FP_CALL_32
2794 if (FP_CALL_GP_REG_P (regno0
))
2795 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2796 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2797 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2803 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2804 ret
= (reg_mentioned_p (op0
, op1
)
2805 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2806 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2808 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2810 size_t i
= strlen (ret
);
2812 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2815 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2816 ret
= volatile_buffer
;
2820 else if (code1
== LABEL_REF
)
2823 mips_count_memory_refs (op1
, 2);
2825 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2826 /* We deliberately remove the 'a' from '%1', so that we don't
2827 have to add SIGN_EXTEND support to print_operand_address.
2828 print_operand will just call print_operand_address in this
2829 case, so there is no problem. */
2832 ret
= "dla\t%0,%a1";
2834 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2838 && GET_CODE (XEXP (op1
, 0)) == REG
2839 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2841 /* This case arises on the mips16; see
2842 mips16_gp_pseudo_reg. */
2843 ret
= "move\t%0,%+";
2845 else if (TARGET_MIPS16
2846 && code1
== SYMBOL_REF
2847 && SYMBOL_REF_FLAG (op1
)
2848 && (XSTR (op1
, 0)[0] != '*'
2849 || strncmp (XSTR (op1
, 0) + 1,
2851 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2853 /* This can occur when reloading the address of a GP
2854 relative symbol on the mips16. */
2855 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2860 mips_count_memory_refs (op1
, 2);
2862 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2863 /* We deliberately remove the 'a' from '%1', so that we don't
2864 have to add SIGN_EXTEND support to print_operand_address.
2865 print_operand will just call print_operand_address in this
2866 case, so there is no problem. */
2869 ret
= "dla\t%0,%a1";
2874 else if (code0
== MEM
)
2878 int regno1
= REGNO (op1
) + subreg_offset1
;
2880 if (FP_REG_P (regno1
))
2883 else if (ALL_COP_REG_P (regno1
) && TARGET_64BIT
)
2885 static char retval
[] = "sdc_\t%1,%0";
2887 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2890 else if (TARGET_64BIT
)
2893 #ifdef TARGET_FP_CALL_32
2894 if (FP_CALL_GP_REG_P (regno1
))
2895 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2901 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2902 ret
= "sw\t%1,%0\n\tsw\t%D1,%D0";
2905 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2906 || (code1
== CONST_DOUBLE
2907 && op1
== CONST0_RTX (GET_MODE (op1
))))
2909 || double_memory_operand (op0
, GET_MODE (op0
))))
2914 ret
= "sw\t%.,%0\n\tsw\t%.,%D0";
2918 mips_count_memory_refs (op0
, 2);
2920 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2922 size_t i
= strlen (ret
);
2924 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2927 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2928 ret
= volatile_buffer
;
2934 abort_with_insn (insn
, "bad move");
2938 if (delay
!= DELAY_NONE
)
2939 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2944 /* Provide the costs of an addressing mode that contains ADDR.
2945 If ADDR is not a valid address, its cost is irrelevant. */
2948 mips_address_cost (addr
)
2951 switch (GET_CODE (addr
))
2961 rtx offset
= const0_rtx
;
2962 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
2963 if (GET_CODE (addr
) == LABEL_REF
)
2966 if (GET_CODE (addr
) != SYMBOL_REF
)
2969 if (! SMALL_INT (offset
))
2973 /* ... fall through ... */
2976 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
2980 register rtx plus0
= XEXP (addr
, 0);
2981 register rtx plus1
= XEXP (addr
, 1);
2983 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
2984 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
2986 if (GET_CODE (plus0
) != REG
)
2989 switch (GET_CODE (plus1
))
2992 return SMALL_INT (plus1
) ? 1 : 2;
2999 return mips_address_cost (plus1
) + 1;
3013 /* Return nonzero if X is an address which needs a temporary register when
3014 reloaded while generating PIC code. */
3017 pic_address_needs_scratch (x
)
3020 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3021 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3022 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3023 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3024 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3030 /* Make normal rtx_code into something we can index from an array */
3032 static enum internal_test
3033 map_test_to_internal_test (test_code
)
3034 enum rtx_code test_code
;
3036 enum internal_test test
= ITEST_MAX
;
3040 case EQ
: test
= ITEST_EQ
; break;
3041 case NE
: test
= ITEST_NE
; break;
3042 case GT
: test
= ITEST_GT
; break;
3043 case GE
: test
= ITEST_GE
; break;
3044 case LT
: test
= ITEST_LT
; break;
3045 case LE
: test
= ITEST_LE
; break;
3046 case GTU
: test
= ITEST_GTU
; break;
3047 case GEU
: test
= ITEST_GEU
; break;
3048 case LTU
: test
= ITEST_LTU
; break;
3049 case LEU
: test
= ITEST_LEU
; break;
3057 /* Generate the code to compare two integer values. The return value is:
3058 (reg:SI xx) The pseudo register the comparison is in
3059 0 No register, generate a simple branch.
3061 ??? This is called with result nonzero by the Scond patterns in
3062 mips.md. These patterns are called with a target in the mode of
3063 the Scond instruction pattern. Since this must be a constant, we
3064 must use SImode. This means that if RESULT is non-zero, it will
3065 always be an SImode register, even if TARGET_64BIT is true. We
3066 cope with this by calling convert_move rather than emit_move_insn.
3067 This will sometimes lead to an unnecessary extension of the result;
3079 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
3080 enum rtx_code test_code
; /* relational test (EQ, etc) */
3081 rtx result
; /* result to store comp. or 0 if branch */
3082 rtx cmp0
; /* first operand to compare */
3083 rtx cmp1
; /* second operand to compare */
3084 int *p_invert
; /* NULL or ptr to hold whether branch needs */
3085 /* to reverse its test */
3089 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
3090 int const_low
; /* low bound of constant we can accept */
3091 int const_high
; /* high bound of constant we can accept */
3092 int const_add
; /* constant to add (convert LE -> LT) */
3093 int reverse_regs
; /* reverse registers in test */
3094 int invert_const
; /* != 0 if invert value if cmp1 is constant */
3095 int invert_reg
; /* != 0 if invert value if cmp1 is register */
3096 int unsignedp
; /* != 0 for unsigned comparisons. */
3099 static const struct cmp_info info
[ (int)ITEST_MAX
] = {
3101 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3102 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3103 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3104 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3105 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3106 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3107 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3108 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3109 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3110 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3113 enum internal_test test
;
3114 enum machine_mode mode
;
3115 const struct cmp_info
*p_info
;
3122 test
= map_test_to_internal_test (test_code
);
3123 if (test
== ITEST_MAX
)
3126 p_info
= &info
[(int) test
];
3127 eqne_p
= (p_info
->test_code
== XOR
);
3129 mode
= GET_MODE (cmp0
);
3130 if (mode
== VOIDmode
)
3131 mode
= GET_MODE (cmp1
);
3133 /* Eliminate simple branches */
3134 branch_p
= (result
== 0);
3137 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
3139 /* Comparisons against zero are simple branches */
3140 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
3141 && (! TARGET_MIPS16
|| eqne_p
))
3144 /* Test for beq/bne. */
3145 if (eqne_p
&& ! TARGET_MIPS16
)
3149 /* allocate a pseudo to calculate the value in. */
3150 result
= gen_reg_rtx (mode
);
3153 /* Make sure we can handle any constants given to us. */
3154 if (GET_CODE (cmp0
) == CONST_INT
)
3155 cmp0
= force_reg (mode
, cmp0
);
3157 if (GET_CODE (cmp1
) == CONST_INT
)
3159 HOST_WIDE_INT value
= INTVAL (cmp1
);
3161 if (value
< p_info
->const_low
3162 || value
> p_info
->const_high
3163 /* ??? Why? And why wasn't the similar code below modified too? */
3165 && HOST_BITS_PER_WIDE_INT
< 64
3166 && p_info
->const_add
!= 0
3167 && ((p_info
->unsignedp
3168 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
3169 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
3170 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
3171 != (p_info
->const_add
> 0))))
3172 cmp1
= force_reg (mode
, cmp1
);
3175 /* See if we need to invert the result. */
3176 invert
= (GET_CODE (cmp1
) == CONST_INT
3177 ? p_info
->invert_const
: p_info
->invert_reg
);
3179 if (p_invert
!= (int *)0)
3185 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3186 Comparison between two registers, may involve switching operands. */
3187 if (GET_CODE (cmp1
) == CONST_INT
)
3189 if (p_info
->const_add
!= 0)
3191 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
3193 /* If modification of cmp1 caused overflow,
3194 we would get the wrong answer if we follow the usual path;
3195 thus, x > 0xffffffffU would turn into x > 0U. */
3196 if ((p_info
->unsignedp
3197 ? (unsigned HOST_WIDE_INT
) new >
3198 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
3199 : new > INTVAL (cmp1
))
3200 != (p_info
->const_add
> 0))
3202 /* This test is always true, but if INVERT is true then
3203 the result of the test needs to be inverted so 0 should
3204 be returned instead. */
3205 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
3209 cmp1
= GEN_INT (new);
3213 else if (p_info
->reverse_regs
)
3220 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
3224 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
3225 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
3228 if (test
== ITEST_NE
)
3230 if (! TARGET_MIPS16
)
3232 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
3233 if (p_invert
!= NULL
)
3239 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3240 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
3245 else if (test
== ITEST_EQ
)
3247 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3248 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
3256 if (! TARGET_MIPS16
)
3260 /* The value is in $24. Copy it to another register, so
3261 that reload doesn't think it needs to store the $24 and
3262 the input to the XOR in the same location. */
3263 reg2
= gen_reg_rtx (mode
);
3264 emit_move_insn (reg2
, reg
);
3266 one
= force_reg (mode
, const1_rtx
);
3268 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
3274 /* Emit the common code for doing conditional branches.
3275 operand[0] is the label to jump to.
3276 The comparison operands are saved away by cmp{si,di,sf,df}. */
3279 gen_conditional_branch (operands
, test_code
)
3281 enum rtx_code test_code
;
3283 enum cmp_type type
= branch_type
;
3284 rtx cmp0
= branch_cmp
[0];
3285 rtx cmp1
= branch_cmp
[1];
3286 enum machine_mode mode
;
3295 mode
= type
== CMP_SI
? SImode
: DImode
;
3297 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
3305 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
3306 /* We don't want to build a comparison against a non-zero
3308 cmp1
= force_reg (mode
, cmp1
);
3315 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
3317 reg
= gen_reg_rtx (CCmode
);
3319 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3320 0 in the instruction built below. The MIPS FPU handles
3321 inequality testing by testing for equality and looking for a
3323 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3324 gen_rtx (test_code
== NE
? EQ
: test_code
,
3325 CCmode
, cmp0
, cmp1
)));
3327 test_code
= test_code
== NE
? EQ
: NE
;
3335 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
3338 /* Generate the branch. */
3340 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
3349 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3350 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3351 gen_rtx (test_code
, mode
,
3356 /* Emit the common code for conditional moves. OPERANDS is the array
3357 of operands passed to the conditional move defined_expand. */
3360 gen_conditional_move (operands
)
3363 rtx op0
= branch_cmp
[0];
3364 rtx op1
= branch_cmp
[1];
3365 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3366 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
3367 enum rtx_code move_code
= NE
;
3368 enum machine_mode op_mode
= GET_MODE (operands
[0]);
3369 enum machine_mode cmp_mode
;
3372 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3391 op0
= force_reg (mode
, branch_cmp
[1]);
3392 op1
= branch_cmp
[0];
3396 op0
= force_reg (mode
, branch_cmp
[1]);
3397 op1
= branch_cmp
[0];
3408 op0
= force_reg (mode
, branch_cmp
[1]);
3409 op1
= branch_cmp
[0];
3413 op0
= force_reg (mode
, branch_cmp
[1]);
3414 op1
= branch_cmp
[0];
3421 else if (cmp_code
== NE
)
3422 cmp_code
= EQ
, move_code
= EQ
;
3424 if (mode
== SImode
|| mode
== DImode
)
3426 else if (mode
== SFmode
|| mode
== DFmode
)
3431 cmp_reg
= gen_reg_rtx (cmp_mode
);
3432 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
3433 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
3435 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
3436 gen_rtx_IF_THEN_ELSE (op_mode
,
3437 gen_rtx (move_code
, VOIDmode
,
3439 CONST0_RTX (SImode
)),
3440 operands
[2], operands
[3])));
3443 /* Emit the common code for conditional moves. OPERANDS is the array
3444 of operands passed to the conditional move defined_expand. */
3447 mips_gen_conditional_trap (operands
)
3451 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3452 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3454 /* MIPS conditional trap machine instructions don't have GT or LE
3455 flavors, so we must invert the comparison and convert to LT and
3456 GE, respectively. */
3459 case GT
: cmp_code
= LT
; break;
3460 case LE
: cmp_code
= GE
; break;
3461 case GTU
: cmp_code
= LTU
; break;
3462 case LEU
: cmp_code
= GEU
; break;
3465 if (cmp_code
== GET_CODE (operands
[0]))
3467 op0
= force_reg (mode
, branch_cmp
[0]);
3468 op1
= branch_cmp
[1];
3472 op0
= force_reg (mode
, branch_cmp
[1]);
3473 op1
= branch_cmp
[0];
3475 if (GET_CODE (op1
) == CONST_INT
&& ! SMALL_INT (op1
))
3476 op1
= force_reg (mode
, op1
);
3478 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3479 gen_rtx (cmp_code
, GET_MODE (operands
[0]), op0
, op1
),
3483 /* Write a loop to move a constant number of bytes.
3484 Generate load/stores as follows:
3490 temp<last> = src[MAX_MOVE_REGS-1];
3494 dest[MAX_MOVE_REGS-1] = temp<last>;
3495 src += MAX_MOVE_REGS;
3496 dest += MAX_MOVE_REGS;
3497 } while (src != final);
3499 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3500 registers are needed.
3502 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3503 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3504 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3506 #define MAX_MOVE_REGS 4
3507 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3510 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3511 rtx dest_reg
; /* register holding destination address */
3512 rtx src_reg
; /* register holding source address */
3513 unsigned int bytes
; /* # bytes to move */
3514 int align
; /* alignment */
3515 rtx orig_dest
; /* original dest */
3516 rtx orig_src
; /* original source for making a reg note */
3518 rtx dest_mem
= replace_equiv_address (orig_dest
, dest_reg
);
3519 rtx src_mem
= replace_equiv_address (orig_src
, src_reg
);
3520 rtx align_rtx
= GEN_INT (align
);
3526 if (bytes
< (unsigned)2 * MAX_MOVE_BYTES
)
3529 leftover
= bytes
% MAX_MOVE_BYTES
;
3532 label
= gen_label_rtx ();
3533 final_src
= gen_reg_rtx (Pmode
);
3534 bytes_rtx
= GEN_INT (bytes
);
3538 if (Pmode
== DImode
)
3540 emit_insn (gen_movdi (final_src
, bytes_rtx
));
3541 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
3545 emit_insn (gen_movsi (final_src
, bytes_rtx
));
3546 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
3551 if (Pmode
== DImode
)
3552 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
3554 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
3559 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
3560 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
3562 if (Pmode
== DImode
)
3564 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
3565 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
3566 emit_insn (gen_cmpdi (src_reg
, final_src
));
3570 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
3571 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
3572 emit_insn (gen_cmpsi (src_reg
, final_src
));
3575 emit_jump_insn (gen_bne (label
));
3578 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
3582 /* Use a library function to move some bytes. */
3585 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
3590 /* We want to pass the size as Pmode, which will normally be SImode
3591 but will be DImode if we are using 64 bit longs and pointers. */
3592 if (GET_MODE (bytes_rtx
) != VOIDmode
3593 && GET_MODE (bytes_rtx
) != (unsigned) Pmode
)
3594 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
3596 #ifdef TARGET_MEM_FUNCTIONS
3597 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
3598 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
3599 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
3600 TREE_UNSIGNED (sizetype
)),
3601 TYPE_MODE (sizetype
));
3603 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
3604 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
3605 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
3606 TREE_UNSIGNED (integer_type_node
)),
3607 TYPE_MODE (integer_type_node
));
3611 /* Expand string/block move operations.
3613 operands[0] is the pointer to the destination.
3614 operands[1] is the pointer to the source.
3615 operands[2] is the number of bytes to move.
3616 operands[3] is the alignment. */
3619 expand_block_move (operands
)
3622 rtx bytes_rtx
= operands
[2];
3623 rtx align_rtx
= operands
[3];
3624 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
3625 unsigned HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
3626 unsigned int align
= INTVAL (align_rtx
);
3627 rtx orig_src
= operands
[1];
3628 rtx orig_dest
= operands
[0];
3632 if (constp
&& bytes
== 0)
3635 if (align
> (unsigned) UNITS_PER_WORD
)
3636 align
= UNITS_PER_WORD
;
3638 /* Move the address into scratch registers. */
3639 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
3640 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
3643 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3645 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
3646 && align
== (unsigned) UNITS_PER_WORD
)
3647 move_by_pieces (orig_dest
, orig_src
, bytes
, align
* BITS_PER_WORD
);
3649 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
)
3650 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3652 replace_equiv_address (orig_src
,
3654 bytes_rtx
, align_rtx
));
3656 else if (constp
&& align
>= (unsigned) UNITS_PER_WORD
&& optimize
)
3657 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
3659 else if (constp
&& optimize
)
3661 /* If the alignment is not word aligned, generate a test at
3662 runtime, to see whether things wound up aligned, and we
3663 can use the faster lw/sw instead ulw/usw. */
3665 rtx temp
= gen_reg_rtx (Pmode
);
3666 rtx aligned_label
= gen_label_rtx ();
3667 rtx join_label
= gen_label_rtx ();
3668 int leftover
= bytes
% MAX_MOVE_BYTES
;
3672 if (Pmode
== DImode
)
3674 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
3675 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3676 emit_insn (gen_cmpdi (temp
, const0_rtx
));
3680 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
3681 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3682 emit_insn (gen_cmpsi (temp
, const0_rtx
));
3685 emit_jump_insn (gen_beq (aligned_label
));
3687 /* Unaligned loop. */
3688 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
3689 emit_jump_insn (gen_jump (join_label
));
3693 emit_label (aligned_label
);
3694 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
3696 emit_label (join_label
);
3698 /* Bytes at the end of the loop. */
3700 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3702 replace_equiv_address (orig_src
,
3709 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3712 /* Emit load/stores for a small constant block_move.
3714 operands[0] is the memory address of the destination.
3715 operands[1] is the memory address of the source.
3716 operands[2] is the number of bytes to move.
3717 operands[3] is the alignment.
3718 operands[4] is a temp register.
3719 operands[5] is a temp register.
3721 operands[3+num_regs] is the last temp register.
3723 The block move type can be one of the following:
3724 BLOCK_MOVE_NORMAL Do all of the block move.
3725 BLOCK_MOVE_NOT_LAST Do all but the last store.
3726 BLOCK_MOVE_LAST Do just the last store. */
3729 output_block_move (insn
, operands
, num_regs
, move_type
)
3733 enum block_move_type move_type
;
3735 rtx dest_reg
= XEXP (operands
[0], 0);
3736 rtx src_reg
= XEXP (operands
[1], 0);
3737 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
3738 int align
= INTVAL (operands
[3]);
3741 int use_lwl_lwr
= 0;
3742 int last_operand
= num_regs
+ 4;
3748 const char *load
; /* load insn without nop */
3749 const char *load_nop
; /* load insn with trailing nop */
3750 const char *store
; /* store insn */
3751 const char *final
; /* if last_store used: NULL or swr */
3752 const char *last_store
; /* last store instruction */
3753 int offset
; /* current offset */
3754 enum machine_mode mode
; /* mode to use on (MEM) */
3757 /* ??? Detect a bug in GCC, where it can give us a register
3758 the same as one of the addressing registers and reduce
3759 the number of registers available. */
3760 for (i
= 4; i
< last_operand
&& safe_regs
< (int) ARRAY_SIZE (xoperands
); i
++)
3761 if (! reg_mentioned_p (operands
[i
], operands
[0])
3762 && ! reg_mentioned_p (operands
[i
], operands
[1]))
3763 xoperands
[safe_regs
++] = operands
[i
];
3765 if (safe_regs
< last_operand
)
3767 xoperands
[0] = operands
[0];
3768 xoperands
[1] = operands
[1];
3769 xoperands
[2] = operands
[2];
3770 xoperands
[3] = operands
[3];
3771 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
3774 /* If we are given global or static addresses, and we would be
3775 emitting a few instructions, try to save time by using a
3776 temporary register for the pointer. */
3777 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3778 an ldl/ldr instruction pair. We play it safe, and always move
3779 constant addresses into registers when generating N32/N64 code, just
3780 in case we might emit an unaligned load instruction. */
3781 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
3782 || mips_abi
== ABI_MEABI
3783 || mips_abi
== ABI_N32
3784 || mips_abi
== ABI_64
))
3786 if (CONSTANT_P (src_reg
))
3789 mips_count_memory_refs (operands
[1], 1);
3791 src_reg
= operands
[3 + num_regs
--];
3792 if (move_type
!= BLOCK_MOVE_LAST
)
3794 xoperands
[1] = operands
[1];
3795 xoperands
[0] = src_reg
;
3796 if (Pmode
== DImode
)
3797 output_asm_insn ("dla\t%0,%1", xoperands
);
3799 output_asm_insn ("la\t%0,%1", xoperands
);
3803 if (CONSTANT_P (dest_reg
))
3806 mips_count_memory_refs (operands
[0], 1);
3808 dest_reg
= operands
[3 + num_regs
--];
3809 if (move_type
!= BLOCK_MOVE_LAST
)
3811 xoperands
[1] = operands
[0];
3812 xoperands
[0] = dest_reg
;
3813 if (Pmode
== DImode
)
3814 output_asm_insn ("dla\t%0,%1", xoperands
);
3816 output_asm_insn ("la\t%0,%1", xoperands
);
3821 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3822 are not offsettable, however, offsettable_address_p says they are
3823 offsettable. I think this is a bug in offsettable_address_p.
3824 For expediency, we fix this by just loading the address into a register
3825 if we happen to get one. */
3827 if (GET_CODE (src_reg
) == LO_SUM
)
3829 src_reg
= operands
[3 + num_regs
--];
3830 if (move_type
!= BLOCK_MOVE_LAST
)
3832 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
3833 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3834 xoperands
[0] = src_reg
;
3835 if (Pmode
== DImode
)
3836 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3838 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3842 if (GET_CODE (dest_reg
) == LO_SUM
)
3844 dest_reg
= operands
[3 + num_regs
--];
3845 if (move_type
!= BLOCK_MOVE_LAST
)
3847 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
3848 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
3849 xoperands
[0] = dest_reg
;
3850 if (Pmode
== DImode
)
3851 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3853 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3857 if (num_regs
> (int) ARRAY_SIZE (load_store
))
3858 num_regs
= ARRAY_SIZE (load_store
);
3860 else if (num_regs
< 1)
3861 abort_with_insn (insn
,
3862 "cannot do block move, not enough scratch registers");
3866 load_store
[num
].offset
= offset
;
3868 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
3870 load_store
[num
].load
= "ld\t%0,%1";
3871 load_store
[num
].load_nop
= "ld\t%0,%1%#";
3872 load_store
[num
].store
= "sd\t%0,%1";
3873 load_store
[num
].last_store
= "sd\t%0,%1";
3874 load_store
[num
].final
= 0;
3875 load_store
[num
].mode
= DImode
;
3880 /* ??? Fails because of a MIPS assembler bug? */
3881 else if (TARGET_64BIT
&& bytes
>= 8 && ! TARGET_MIPS16
)
3883 if (BYTES_BIG_ENDIAN
)
3885 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
3886 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
3887 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
3888 load_store
[num
].last_store
= "sdr\t%0,%2";
3889 load_store
[num
].final
= "sdl\t%0,%1";
3893 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
3894 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
3895 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
3896 load_store
[num
].last_store
= "sdr\t%0,%1";
3897 load_store
[num
].final
= "sdl\t%0,%2";
3900 load_store
[num
].mode
= DImode
;
3906 else if (bytes
>= 4 && align
>= 4)
3908 load_store
[num
].load
= "lw\t%0,%1";
3909 load_store
[num
].load_nop
= "lw\t%0,%1%#";
3910 load_store
[num
].store
= "sw\t%0,%1";
3911 load_store
[num
].last_store
= "sw\t%0,%1";
3912 load_store
[num
].final
= 0;
3913 load_store
[num
].mode
= SImode
;
3918 else if (bytes
>= 4 && ! TARGET_MIPS16
)
3920 if (BYTES_BIG_ENDIAN
)
3922 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
3923 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3924 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
3925 load_store
[num
].last_store
= "swr\t%0,%2";
3926 load_store
[num
].final
= "swl\t%0,%1";
3930 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
3931 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3932 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
3933 load_store
[num
].last_store
= "swr\t%0,%1";
3934 load_store
[num
].final
= "swl\t%0,%2";
3937 load_store
[num
].mode
= SImode
;
3943 else if (bytes
>= 2 && align
>= 2)
3945 load_store
[num
].load
= "lh\t%0,%1";
3946 load_store
[num
].load_nop
= "lh\t%0,%1%#";
3947 load_store
[num
].store
= "sh\t%0,%1";
3948 load_store
[num
].last_store
= "sh\t%0,%1";
3949 load_store
[num
].final
= 0;
3950 load_store
[num
].mode
= HImode
;
3956 load_store
[num
].load
= "lb\t%0,%1";
3957 load_store
[num
].load_nop
= "lb\t%0,%1%#";
3958 load_store
[num
].store
= "sb\t%0,%1";
3959 load_store
[num
].last_store
= "sb\t%0,%1";
3960 load_store
[num
].final
= 0;
3961 load_store
[num
].mode
= QImode
;
3966 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3968 dslots_load_total
++;
3969 dslots_load_filled
++;
3971 if (CONSTANT_P (src_reg
))
3972 mips_count_memory_refs (src_reg
, 1);
3974 if (CONSTANT_P (dest_reg
))
3975 mips_count_memory_refs (dest_reg
, 1);
3978 /* Emit load/stores now if we have run out of registers or are
3979 at the end of the move. */
3981 if (++num
== num_regs
|| bytes
== 0)
3983 /* If only load/store, we need a NOP after the load. */
3986 load_store
[0].load
= load_store
[0].load_nop
;
3987 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3988 dslots_load_filled
--;
3991 if (move_type
!= BLOCK_MOVE_LAST
)
3993 for (i
= 0; i
< num
; i
++)
3997 if (!operands
[i
+ 4])
4000 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
4001 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
4002 REGNO (operands
[i
+ 4]));
4004 offset
= load_store
[i
].offset
;
4005 xoperands
[0] = operands
[i
+ 4];
4006 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4007 plus_constant (src_reg
, offset
));
4012 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4014 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4015 plus_constant (src_reg
,
4020 output_asm_insn (load_store
[i
].load
, xoperands
);
4024 for (i
= 0; i
< num
; i
++)
4026 int last_p
= (i
== num
-1 && bytes
== 0);
4027 int offset
= load_store
[i
].offset
;
4029 xoperands
[0] = operands
[i
+ 4];
4030 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4031 plus_constant (dest_reg
, offset
));
4036 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4037 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4038 plus_constant (dest_reg
,
4043 if (move_type
== BLOCK_MOVE_NORMAL
)
4044 output_asm_insn (load_store
[i
].store
, xoperands
);
4046 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
4049 output_asm_insn (load_store
[i
].store
, xoperands
);
4051 else if (load_store
[i
].final
!= 0)
4052 output_asm_insn (load_store
[i
].final
, xoperands
);
4056 output_asm_insn (load_store
[i
].last_store
, xoperands
);
4059 num
= 0; /* reset load_store */
4067 /* Argument support functions. */
4069 /* Initialize CUMULATIVE_ARGS for a function. */
4072 init_cumulative_args (cum
, fntype
, libname
)
4073 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
4074 tree fntype
; /* tree ptr for function decl */
4075 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
4077 static CUMULATIVE_ARGS zero_cum
;
4078 tree param
, next_param
;
4080 if (TARGET_DEBUG_E_MODE
)
4083 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
4086 fputc ('\n', stderr
);
4090 tree ret_type
= TREE_TYPE (fntype
);
4091 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
4092 tree_code_name
[(int)TREE_CODE (fntype
)],
4093 tree_code_name
[(int)TREE_CODE (ret_type
)]);
4098 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4100 /* Determine if this function has variable arguments. This is
4101 indicated by the last argument being 'void_type_mode' if there
4102 are no variable arguments. The standard MIPS calling sequence
4103 passes all arguments in the general purpose registers in this case. */
4105 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
4106 param
!= 0; param
= next_param
)
4108 next_param
= TREE_CHAIN (param
);
4109 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
4110 cum
->gp_reg_found
= 1;
4115 mips_arg_info (cum
, mode
, type
, named
, info
)
4116 const CUMULATIVE_ARGS
*cum
;
4117 enum machine_mode mode
;
4120 struct mips_arg_info
*info
;
4123 unsigned int num_words
, max_regs
;
4125 info
->struct_p
= (type
!= 0
4126 && (TREE_CODE (type
) == RECORD_TYPE
4127 || TREE_CODE (type
) == UNION_TYPE
4128 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
4130 /* Decide whether this argument should go in a floating-point register,
4131 assuming one is free. Later code checks for availablity. */
4133 info
->fpr_p
= false;
4134 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4135 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
4141 info
->fpr_p
= (!cum
->gp_reg_found
&& cum
->arg_number
< 2);
4149 /* The MIPS eabi says only structures containing doubles get
4150 passed in a fp register, so force a structure containing
4151 a float to be passed in the integer registers. */
4152 info
->fpr_p
= (named
&& !(mode
== SFmode
&& info
->struct_p
));
4156 info
->fpr_p
= named
;
4161 /* Now decide whether the argument must go in an even-numbered register. */
4166 /* Under the O64 ABI, the second float argument goes in $f13 if it
4167 is a double, but $f14 if it is a single. Otherwise, on a
4168 32-bit double-float machine, each FP argument must start in a
4169 new register pair. */
4170 even_reg_p
= ((mips_abi
== ABI_O64
&& mode
== SFmode
) || FP_INC
> 1);
4172 else if (!TARGET_64BIT
)
4174 if (GET_MODE_CLASS (mode
) == MODE_INT
4175 || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4176 even_reg_p
= (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
);
4178 else if (type
!= NULL_TREE
&& TYPE_ALIGN (type
) > BITS_PER_WORD
)
4182 /* Set REG_OFFSET to the register count we're interested in.
4183 The EABI allocates the floating-point registers separately,
4184 but the other ABIs allocate them like integer registers. */
4185 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4190 info
->reg_offset
+= info
->reg_offset
& 1;
4192 /* The alignment applied to registers is also applied to stack arguments. */
4193 info
->stack_offset
= cum
->stack_words
;
4195 info
->stack_offset
+= info
->stack_offset
& 1;
4197 if (mode
== BLKmode
)
4198 info
->num_bytes
= int_size_in_bytes (type
);
4200 info
->num_bytes
= GET_MODE_SIZE (mode
);
4202 num_words
= (info
->num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4203 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4205 /* Partition the argument between registers and stack. */
4206 info
->reg_words
= MIN (num_words
, max_regs
);
4207 info
->stack_words
= num_words
- info
->reg_words
;
4211 /* Advance the argument to the next argument position. */
4214 function_arg_advance (cum
, mode
, type
, named
)
4215 CUMULATIVE_ARGS
*cum
; /* current arg information */
4216 enum machine_mode mode
; /* current arg mode */
4217 tree type
; /* type of the argument or 0 if lib support */
4218 int named
; /* whether or not the argument was named */
4220 struct mips_arg_info info
;
4222 mips_arg_info (cum
, mode
, type
, named
, &info
);
4224 /* The following is a hack in order to pass 1 byte structures
4225 the same way that the MIPS compiler does (namely by passing
4226 the structure in the high byte or half word of the register).
4227 This also makes varargs work. If we have such a structure,
4228 we save the adjustment RTL, and the call define expands will
4229 emit them. For the VOIDmode argument (argument after the
4230 last real argument), pass back a parallel vector holding each
4231 of the adjustments. */
4233 /* ??? This scheme requires everything smaller than the word size to
4234 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4235 that would mean every int needs to be shifted left, which is very
4236 inefficient. Let's not carry this compatibility to the 64 bit
4237 calling convention for now. */
4240 && info
.reg_words
== 1
4241 && info
.num_bytes
< UNITS_PER_WORD
4243 && mips_abi
!= ABI_EABI
4244 && mips_abi
!= ABI_MEABI
)
4246 rtx amount
= GEN_INT (BITS_PER_WORD
- info
.num_bytes
* BITS_PER_UNIT
);
4247 rtx reg
= gen_rtx_REG (word_mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4250 cum
->adjust
[cum
->num_adjusts
++] = gen_ashldi3 (reg
, reg
, amount
);
4252 cum
->adjust
[cum
->num_adjusts
++] = gen_ashlsi3 (reg
, reg
, amount
);
4256 cum
->gp_reg_found
= true;
4258 /* See the comment above the cumulative args structure in mips.h
4259 for an explanation of what this code does. It assumes the O32
4260 ABI, which passes at most 2 arguments in float registers. */
4261 if (cum
->arg_number
< 2 && info
.fpr_p
)
4262 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
4264 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4265 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4266 else if (info
.reg_words
> 0)
4267 cum
->num_fprs
+= FP_INC
;
4269 if (info
.stack_words
> 0)
4270 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4275 /* Return an RTL expression containing the register for the given mode,
4276 or 0 if the argument is to be passed on the stack. */
4279 function_arg (cum
, mode
, type
, named
)
4280 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4281 enum machine_mode mode
; /* current arg mode */
4282 tree type
; /* type of the argument or 0 if lib support */
4283 int named
; /* != 0 for normal args, == 0 for ... args */
4285 struct mips_arg_info info
;
4287 /* We will be called with a mode of VOIDmode after the last argument
4288 has been seen. Whatever we return will be passed to the call
4289 insn. If we need any shifts for small structures, return them in
4290 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4291 mode. Otherwise, if we need a mips16 fp_code, return a REG
4292 with the code stored as the mode. */
4293 if (mode
== VOIDmode
)
4295 if (cum
->num_adjusts
> 0)
4296 return gen_rtx_PARALLEL ((enum machine_mode
) cum
->fp_code
,
4297 gen_rtvec_v (cum
->num_adjusts
,
4298 (rtx
*) cum
->adjust
));
4300 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4301 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4307 mips_arg_info (cum
, mode
, type
, named
, &info
);
4309 /* Return straight away if the whole argument is passed on the stack. */
4310 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4314 && TREE_CODE (type
) == RECORD_TYPE
4315 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4316 && TYPE_SIZE_UNIT (type
)
4317 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
4321 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4322 structure contains a double in its entirety, then that 64 bit
4323 chunk is passed in a floating point register. */
4326 /* First check to see if there is any such field. */
4327 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4328 if (TREE_CODE (field
) == FIELD_DECL
4329 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4330 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4331 && host_integerp (bit_position (field
), 0)
4332 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4337 /* Now handle the special case by returning a PARALLEL
4338 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4339 chunks are passed in registers. */
4341 HOST_WIDE_INT bitpos
;
4344 /* assign_parms checks the mode of ENTRY_PARM, so we must
4345 use the actual mode here. */
4346 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4349 field
= TYPE_FIELDS (type
);
4350 for (i
= 0; i
< info
.reg_words
; i
++)
4354 for (; field
; field
= TREE_CHAIN (field
))
4355 if (TREE_CODE (field
) == FIELD_DECL
4356 && int_bit_position (field
) >= bitpos
)
4360 && int_bit_position (field
) == bitpos
4361 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4362 && !TARGET_SOFT_FLOAT
4363 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4364 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4366 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4369 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4370 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4372 bitpos
+= BITS_PER_WORD
;
4378 if (mips_abi
== ABI_MEABI
&& info
.fpr_p
&& !cum
->prototype
)
4380 /* To make K&R varargs work we need to pass floating
4381 point arguments in both integer and FP registers. */
4382 return gen_rtx_PARALLEL
4385 gen_rtx_EXPR_LIST (VOIDmode
,
4390 gen_rtx_EXPR_LIST (VOIDmode
,
4398 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
4400 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4404 function_arg_partial_nregs (cum
, mode
, type
, named
)
4405 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4406 enum machine_mode mode
; /* current arg mode */
4407 tree type
; /* type of the argument or 0 if lib support */
4408 int named
; /* != 0 for normal args, == 0 for ... args */
4410 struct mips_arg_info info
;
4412 mips_arg_info (cum
, mode
, type
, named
, &info
);
4413 return info
.stack_words
> 0 ? info
.reg_words
: 0;
4417 mips_setup_incoming_varargs (cum
, mode
, type
, no_rtl
)
4418 const CUMULATIVE_ARGS
*cum
;
4419 enum machine_mode mode
;
4423 CUMULATIVE_ARGS local_cum
;
4424 int gp_saved
, fp_saved
;
4426 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4429 /* The caller has advanced CUM up to, but not beyond, the last named
4430 argument. Advance a local copy of CUM past the last "real" named
4431 argument, to find out how many registers are left over.
4433 For K&R varargs, the last named argument is a dummy word-sized one,
4434 so CUM already contains the information we need. For stdarg, it is
4435 a real argument (such as the format in printf()) and we need to
4438 if (!current_function_varargs
)
4439 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4441 /* Found out how many registers we need to save. */
4442 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4443 fp_saved
= (EABI_FLOAT_VARARGS_P
4444 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4453 ptr
= virtual_incoming_args_rtx
;
4454 if (mips_abi
== ABI_EABI
)
4455 ptr
= plus_constant (ptr
, -gp_saved
* UNITS_PER_WORD
);
4456 mem
= gen_rtx_MEM (BLKmode
, ptr
);
4458 /* va_arg is an array access in this case, which causes
4459 it to get MEM_IN_STRUCT_P set. We must set it here
4460 so that the insn scheduler won't assume that these
4461 stores can't possibly overlap with the va_arg loads. */
4462 if (mips_abi
!= ABI_EABI
&& BYTES_BIG_ENDIAN
)
4463 MEM_SET_IN_STRUCT_P (mem
, 1);
4465 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
, mem
,
4466 gp_saved
, gp_saved
* UNITS_PER_WORD
);
4470 /* We can't use move_block_from_reg, because it will use
4472 enum machine_mode mode
;
4475 /* Set OFF to the offset from virtual_incoming_args_rtx of
4476 the first float register. The FP save area lies below
4477 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4478 off
= -gp_saved
* UNITS_PER_WORD
;
4479 off
&= ~(UNITS_PER_FPVALUE
- 1);
4480 off
-= fp_saved
* UNITS_PER_FPREG
;
4482 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4484 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
4486 rtx ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4487 emit_move_insn (gen_rtx_MEM (mode
, ptr
),
4488 gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4489 off
+= UNITS_PER_FPVALUE
;
4493 return (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_FPREG
);
4496 /* Create the va_list data type.
4497 We keep 3 pointers, and two offsets.
4498 Two pointers are to the overflow area, which starts at the CFA.
4499 One of these is constant, for addressing into the GPR save area below it.
4500 The other is advanced up the stack through the overflow region.
4501 The third pointer is to the GPR save area. Since the FPR save area
4502 is just below it, we can address FPR slots off this pointer.
4503 We also keep two one-byte offsets, which are to be subtracted from the
4504 constant pointers to yield addresses in the GPR and FPR save areas.
4505 These are downcounted as float or non-float arguments are used,
4506 and when they get to zero, the argument must be obtained from the
4508 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4509 pointer is enough. It's started at the GPR save area, and is
4511 Note that the GPR save area is not constant size, due to optimization
4512 in the prologue. Hence, we can't use a design with two pointers
4513 and two offsets, although we could have designed this with two pointers
4514 and three offsets. */
4518 mips_build_va_list ()
4520 if (EABI_FLOAT_VARARGS_P
)
4522 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, record
;
4524 record
= make_node (RECORD_TYPE
);
4526 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4528 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4530 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4532 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4533 unsigned_char_type_node
);
4534 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4535 unsigned_char_type_node
);
4538 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4539 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4540 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4541 DECL_FIELD_CONTEXT (f_goff
) = record
;
4542 DECL_FIELD_CONTEXT (f_foff
) = record
;
4544 TYPE_FIELDS (record
) = f_ovfl
;
4545 TREE_CHAIN (f_ovfl
) = f_gtop
;
4546 TREE_CHAIN (f_gtop
) = f_ftop
;
4547 TREE_CHAIN (f_ftop
) = f_goff
;
4548 TREE_CHAIN (f_goff
) = f_foff
;
4550 layout_type (record
);
4554 return ptr_type_node
;
4557 /* Implement va_start. stdarg_p is 0 if implementing
4558 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4559 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4560 (It doesn't have "...", so it inherits the pointers of its caller.) */
4563 mips_va_start (stdarg_p
, valist
, nextarg
)
4568 const CUMULATIVE_ARGS
*cum
= ¤t_function_args_info
;
4570 if (mips_abi
== ABI_EABI
)
4572 int gpr_save_area_size
;
4575 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4577 if (EABI_FLOAT_VARARGS_P
)
4579 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4580 tree ovfl
, gtop
, ftop
, goff
, foff
;
4583 int fpr_save_area_size
;
4585 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4586 f_gtop
= TREE_CHAIN (f_ovfl
);
4587 f_ftop
= TREE_CHAIN (f_gtop
);
4588 f_goff
= TREE_CHAIN (f_ftop
);
4589 f_foff
= TREE_CHAIN (f_goff
);
4591 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4592 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4593 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4594 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4595 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4597 /* Emit code to initialize OVFL, which points to the next varargs
4598 stack argument. CUM->STACK_WORDS gives the number of stack
4599 words used by named arguments. */
4600 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4601 if (cum
->stack_words
> 0)
4602 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4603 build_int_2 (cum
->stack_words
* UNITS_PER_WORD
, 0));
4604 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4605 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4607 /* Emit code to initialize GTOP, the top of the GPR save area. */
4608 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4609 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
4610 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4612 /* Emit code to initialize FTOP, the top of the FPR save area.
4613 This address is gpr_save_area_bytes below GTOP, rounded
4614 down to the next fp-aligned boundary. */
4615 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4616 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4617 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4619 t
= build (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4620 build_int_2 (-fpr_offset
, -1));
4621 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
4622 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4624 /* Emit code to initialize GOFF, the offset from GTOP of the
4625 next GPR argument. */
4626 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
4627 build_int_2 (gpr_save_area_size
, 0));
4628 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4630 /* Likewise emit code to initialize FOFF, the offset from FTOP
4631 of the next FPR argument. */
4633 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4634 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
4635 build_int_2 (fpr_save_area_size
, 0));
4636 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4640 /* Everything is in the GPR save area, or in the overflow
4641 area which is contiguous with it. */
4643 int offset
= -gpr_save_area_size
;
4644 if (gpr_save_area_size
== 0)
4645 offset
= (stdarg_p
? 0 : -UNITS_PER_WORD
);
4646 nextarg
= plus_constant (nextarg
, offset
);
4647 std_expand_builtin_va_start (1, valist
, nextarg
);
4659 /* ??? This had been conditional on
4660 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4661 and both iris5.h and iris6.h define _MIPS_SIM. */
4662 if (mips_abi
== ABI_N32
4663 || mips_abi
== ABI_64
4664 || mips_abi
== ABI_MEABI
)
4665 ofs
= (cum
->num_gprs
< MAX_ARGS_IN_REGISTERS
4669 ofs
= -UNITS_PER_WORD
;
4672 nextarg
= plus_constant (nextarg
, ofs
);
4673 std_expand_builtin_va_start (1, valist
, nextarg
);
4677 /* Implement va_arg. */
4680 mips_va_arg (valist
, type
)
4683 HOST_WIDE_INT size
, rsize
;
4687 size
= int_size_in_bytes (type
);
4688 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4690 if (mips_abi
== ABI_EABI
)
4696 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4700 size
= POINTER_SIZE
/ BITS_PER_UNIT
;
4701 rsize
= UNITS_PER_WORD
;
4704 addr_rtx
= gen_reg_rtx (Pmode
);
4706 if (!EABI_FLOAT_VARARGS_P
)
4708 /* Case of all args in a merged stack. No need to check bounds,
4709 just advance valist along the stack. */
4714 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
4716 /* Align the pointer using: ap = (ap + align - 1) & -align,
4717 where align is 2 * UNITS_PER_WORD. */
4718 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
4719 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
4720 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4721 build_int_2 (-2 * UNITS_PER_WORD
, -1));
4722 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
4723 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4726 /* Emit code to set addr_rtx to the valist, and postincrement
4727 the valist by the size of the argument, rounded up to the
4729 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
,
4731 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4733 emit_move_insn (addr_rtx
, r
);
4735 /* Flush the POSTINCREMENT. */
4740 /* Not a simple merged stack. */
4742 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4743 tree ovfl
, top
, off
;
4744 rtx lab_over
= NULL_RTX
, lab_false
;
4745 HOST_WIDE_INT osize
;
4747 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4748 f_gtop
= TREE_CHAIN (f_ovfl
);
4749 f_ftop
= TREE_CHAIN (f_gtop
);
4750 f_goff
= TREE_CHAIN (f_ftop
);
4751 f_foff
= TREE_CHAIN (f_goff
);
4753 /* We maintain separate pointers and offsets for floating-point
4754 and integer arguments, but we need similar code in both cases.
4757 TOP be the top of the register save area;
4758 OFF be the offset from TOP of the next register;
4759 ADDR_RTX be the address of the argument; and
4760 RSIZE be the number of bytes used to store the argument
4761 when it's in the register save area
4762 OSIZE be the number of bytes used to store it when it's
4763 in the stack overflow area
4764 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4766 The code we want is:
4768 1: off &= -rsize; // round down
4771 4: addr_rtx = top - off;
4776 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4777 10: addr_rtx = ovfl + PADDING;
4781 [1] and [9] can sometimes be optimized away. */
4783 lab_false
= gen_label_rtx ();
4784 lab_over
= gen_label_rtx ();
4786 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4788 if (TREE_CODE (type
) == REAL_TYPE
)
4790 top
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4791 off
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4793 /* When floating-point registers are saved to the stack,
4794 each one will take up UNITS_PER_FPVALUE bytes, regardless
4795 of the float's precision. */
4796 rsize
= UNITS_PER_FPVALUE
;
4800 top
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4801 off
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4802 if (rsize
> UNITS_PER_WORD
)
4804 /* [1] Emit code for: off &= -rsize. */
4805 t
= build (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4806 build_int_2 (-rsize
, -1));
4807 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4808 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4811 /* Every overflow argument must take up at least UNITS_PER_WORD
4812 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4813 than that, such as in the combination -mgp64 -msingle-float
4814 -fshort-double. Doubles passed in registers will then take
4815 up UNITS_PER_FPVALUE bytes, but those passed on the stack
4816 take up UNITS_PER_WORD bytes. */
4817 osize
= MAX (rsize
, UNITS_PER_WORD
);
4819 /* [2] Emit code to branch if off == 0. */
4820 r
= expand_expr (off
, NULL_RTX
, TYPE_MODE (TREE_TYPE (off
)),
4822 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
4825 /* [4] Emit code for: addr_rtx = top - off. */
4826 t
= build (MINUS_EXPR
, TREE_TYPE (top
), top
, off
);
4827 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4829 emit_move_insn (addr_rtx
, r
);
4831 /* [5] Emit code for: off -= rsize. */
4832 t
= build (MINUS_EXPR
, TREE_TYPE (off
), off
, build_int_2 (rsize
, 0));
4833 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4834 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4836 /* [7] Emit code to jump over the else clause, then the label
4839 emit_jump (lab_over
);
4841 emit_label (lab_false
);
4843 if (osize
> UNITS_PER_WORD
)
4845 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4846 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4847 build_int_2 (osize
- 1, 0));
4848 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
,
4849 build_int_2 (-osize
, -1));
4850 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4851 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4854 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4855 post-increment ovfl by osize. On big-endian machines,
4856 the argument has OSIZE - RSIZE bytes of leading padding. */
4857 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4859 if (BYTES_BIG_ENDIAN
&& osize
> rsize
)
4860 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
,
4861 build_int_2 (osize
- rsize
, 0));
4862 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4864 emit_move_insn (addr_rtx
, r
);
4867 emit_label (lab_over
);
4871 addr_rtx
= force_reg (Pmode
, addr_rtx
);
4872 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4873 set_mem_alias_set (r
, get_varargs_alias_set ());
4874 emit_move_insn (addr_rtx
, r
);
4878 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4879 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4888 /* ??? The original va-mips.h did always align, despite the fact
4889 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4890 increment mechanism. */
4894 else if (TYPE_ALIGN (type
) > 32)
4899 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4900 build_int_2 (align
- 1, 0));
4901 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
4902 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4903 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4905 /* Everything past the alignment is standard. */
4906 return std_expand_builtin_va_arg (valist
, type
);
4910 /* Abort after printing out a specific insn. */
4913 abort_with_insn (insn
, reason
)
4922 /* Set up the threshold for data to go into the small data area, instead
4923 of the normal data area, and detect any conflicts in the switches. */
4928 register int i
, start
;
4930 register enum machine_mode mode
;
4931 register enum processor_type mips_cpu
;
4933 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4935 if (mips_section_threshold
<= 0)
4936 target_flags
&= ~MASK_GPOPT
;
4938 target_flags
|= MASK_GPOPT
;
4940 /* If both single-float and soft-float are set, then clear the one that
4941 was set by TARGET_DEFAULT, leaving the one that was set by the
4942 user. We assume here that the specs prevent both being set by the
4944 #ifdef TARGET_DEFAULT
4945 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
4946 target_flags
&= ~((TARGET_DEFAULT
) & (MASK_SOFT_FLOAT
| MASK_SINGLE_FLOAT
));
4949 /* Get the architectural level. */
4950 if (mips_isa_string
== 0)
4951 mips_isa
= MIPS_ISA_DEFAULT
;
4953 else if (mips_isa_string
!= 0
4954 && mips_arch_string
!= 0)
4955 warning ("The -march option is incompatible to -mipsN and therefore ignored.");
4957 else if (ISDIGIT (*mips_isa_string
))
4959 mips_isa
= atoi (mips_isa_string
);
4962 /* -mno-mips16 overrides -mips16. */
4963 if (mips_no_mips16_string
== NULL
)
4965 target_flags
|= MASK_MIPS16
;
4969 mips_isa
= MIPS_ISA_DEFAULT
;
4973 mips_isa
= MIPS_ISA_DEFAULT
;
4976 else if (mips_isa
< 1
4981 error ("-mips%d not supported", mips_isa
);
4988 error ("bad value (%s) for -mips switch", mips_isa_string
);
4992 #ifdef MIPS_ABI_DEFAULT
4993 /* Get the ABI to use. */
4994 if (mips_abi_string
== (char *) 0)
4995 mips_abi
= MIPS_ABI_DEFAULT
;
4996 else if (! strcmp (mips_abi_string
, "32"))
4998 else if (! strcmp (mips_abi_string
, "o64"))
5000 else if (! strcmp (mips_abi_string
, "n32"))
5002 else if (! strcmp (mips_abi_string
, "64"))
5004 else if (! strcmp (mips_abi_string
, "eabi"))
5005 mips_abi
= ABI_EABI
;
5006 else if (! strcmp (mips_abi_string
, "meabi"))
5007 mips_abi
= ABI_MEABI
;
5009 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
5011 /* A specified ISA defaults the ABI if it was not specified. */
5012 if (mips_abi_string
== 0 && mips_isa_string
5013 && mips_abi
!= ABI_EABI
5014 && mips_abi
!= ABI_O64
5015 && mips_abi
!= ABI_MEABI
)
5021 if (! ISA_HAS_64BIT_REGS
)
5023 else if (mips_abi
!= ABI_N32
)
5028 #ifdef MIPS_CPU_STRING_DEFAULT
5029 /* A specified ABI defaults the ISA if it was not specified. */
5030 else if (mips_isa_string
== 0 && mips_abi_string
5031 && mips_abi
!= ABI_EABI
&& mips_abi
!= ABI_O64
)
5033 if (mips_abi
== ABI_32
)
5035 else if (mips_abi
== ABI_N32
)
5042 /* If both ABI and ISA were specified, check for conflicts. */
5043 else if (mips_isa_string
&& mips_abi_string
)
5045 if (! ISA_HAS_64BIT_REGS
&& (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
5046 || mips_abi
== ABI_O64
))
5047 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
5050 /* Override TARGET_DEFAULT if necessary. */
5051 if (mips_abi
== ABI_32
)
5052 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
5054 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
5055 then set the type sizes. In the EABI in 64 bit mode, longs and
5056 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
5057 if (mips_explicit_type_size_string
== NULL
5058 && ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
5059 || mips_abi
== ABI_64
))
5060 target_flags
|= MASK_LONG64
;
5063 if (mips_abi_string
)
5064 error ("this target does not support the -mabi switch");
5067 #ifdef MIPS_CPU_STRING_DEFAULT
5068 /* ??? There is a minor inconsistency here. If the user specifies an ISA
5069 greater than that supported by the default processor, then the user gets
5070 an error. Normally, the compiler will just default to the base level cpu
5071 for the indicated isa. */
5072 if (mips_arch_string
== 0)
5073 mips_arch_string
= MIPS_CPU_STRING_DEFAULT
;
5074 if (mips_tune_string
== 0)
5075 mips_tune_string
= MIPS_CPU_STRING_DEFAULT
;
5078 /* Identify the processor type. */
5080 if (mips_cpu_string
!= 0)
5082 mips_cpu
= mips_parse_cpu (mips_cpu_string
);
5083 if (mips_cpu
== PROCESSOR_DEFAULT
)
5085 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
5086 mips_cpu_string
= "default";
5088 mips_arch
= mips_cpu
;
5089 mips_tune
= mips_cpu
;
5092 if (mips_arch_string
== 0
5093 || ! strcmp (mips_arch_string
, "default")
5094 || ! strcmp (mips_arch_string
, "DEFAULT"))
5099 mips_arch_string
= "3000";
5100 mips_arch
= PROCESSOR_R3000
;
5103 mips_arch_string
= "6000";
5104 mips_arch
= PROCESSOR_R6000
;
5107 mips_arch_string
= "4000";
5108 mips_arch
= PROCESSOR_R4000
;
5111 mips_arch_string
= "8000";
5112 mips_arch
= PROCESSOR_R8000
;
5115 mips_arch_string
= "4kc";
5116 mips_arch
= PROCESSOR_R4KC
;
5119 mips_arch_string
= "5kc";
5120 mips_arch
= PROCESSOR_R5KC
;
5126 mips_arch
= mips_parse_cpu (mips_arch_string
);
5127 if (mips_arch
== PROCESSOR_DEFAULT
)
5129 error ("bad value (%s) for -march= switch", mips_arch_string
);
5130 mips_arch_string
= "default";
5133 if (mips_tune_string
== 0
5134 || ! strcmp (mips_tune_string
, "default")
5135 || ! strcmp (mips_tune_string
, "DEFAULT"))
5137 if (mips_arch
!= PROCESSOR_DEFAULT
)
5138 mips_tune
= mips_arch
;
5143 mips_tune_string
= "3000";
5144 mips_tune
= PROCESSOR_R3000
;
5147 mips_tune_string
= "6000";
5148 mips_tune
= PROCESSOR_R6000
;
5151 mips_tune_string
= "4000";
5152 mips_tune
= PROCESSOR_R4000
;
5155 mips_tune_string
= "8000";
5156 mips_tune
= PROCESSOR_R8000
;
5159 mips_tune_string
= "4kc";
5160 mips_tune
= PROCESSOR_R4KC
;
5163 mips_tune_string
= "5kc";
5164 mips_tune
= PROCESSOR_R5KC
;
5171 mips_tune
= mips_parse_cpu (mips_tune_string
);
5172 if (mips_tune
== PROCESSOR_DEFAULT
)
5174 error ("bad value (%s) for -mtune= switch", mips_tune_string
);
5175 mips_tune_string
= "default";
5179 /* make sure sizes of ints/longs/etc. are ok */
5180 if (! ISA_HAS_64BIT_REGS
)
5184 error ("-mips%d does not support 64 bit fp registers", mips_isa
);
5185 target_flags
&= ~ MASK_FLOAT64
;
5188 else if (TARGET_64BIT
)
5190 error ("-mips%d does not support 64 bit gp registers", mips_isa
);
5191 target_flags
&= ~MASK_64BIT
;
5195 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5196 flag_pcc_struct_return
= 0;
5198 /* Tell halfpic.c that we have half-pic code if we do. */
5199 if (TARGET_HALF_PIC
)
5202 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5203 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5204 /* ??? -non_shared turns off pic code generation, but this is not
5206 if (TARGET_ABICALLS
)
5208 mips_abicalls
= MIPS_ABICALLS_YES
;
5210 if (mips_section_threshold
> 0)
5211 warning ("-G is incompatible with PIC code which is the default");
5214 mips_abicalls
= MIPS_ABICALLS_NO
;
5216 /* -membedded-pic is a form of PIC code suitable for embedded
5217 systems. All calls are made using PC relative addressing, and
5218 all data is addressed using the $gp register. This requires gas,
5219 which does most of the work, and GNU ld, which automatically
5220 expands PC relative calls which are out of range into a longer
5221 instruction sequence. All gcc really does differently is
5222 generate a different sequence for a switch. */
5223 if (TARGET_EMBEDDED_PIC
)
5226 if (TARGET_ABICALLS
)
5227 warning ("-membedded-pic and -mabicalls are incompatible");
5230 warning ("-G and -membedded-pic are incompatible");
5232 /* Setting mips_section_threshold is not required, because gas
5233 will force everything to be GP addressable anyhow, but
5234 setting it will cause gcc to make better estimates of the
5235 number of instructions required to access a particular data
5237 mips_section_threshold
= 0x7fffffff;
5240 /* This optimization requires a linker that can support a R_MIPS_LO16
5241 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5242 GNU ld has this support, but not all other MIPS linkers do, so we enable
5243 this optimization only if the user requests it, or if GNU ld is the
5244 standard linker for this configuration. */
5245 /* ??? This does not work when target addresses are DImode.
5246 This is because we are missing DImode high/lo_sum patterns. */
5247 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
5249 mips_split_addresses
= 1;
5251 mips_split_addresses
= 0;
5253 /* -mrnames says to use the MIPS software convention for register
5254 names instead of the hardware names (ie, $a0 instead of $4).
5255 We do this by switching the names in mips_reg_names, which the
5256 reg_names points into via the REGISTER_NAMES macro. */
5258 if (TARGET_NAME_REGS
)
5259 memcpy (mips_reg_names
, mips_sw_reg_names
, sizeof (mips_reg_names
));
5261 /* When compiling for the mips16, we can not use floating point. We
5262 record the original hard float value in mips16_hard_float. */
5265 if (TARGET_SOFT_FLOAT
)
5266 mips16_hard_float
= 0;
5268 mips16_hard_float
= 1;
5269 target_flags
|= MASK_SOFT_FLOAT
;
5271 /* Don't run the scheduler before reload, since it tends to
5272 increase register pressure. */
5273 flag_schedule_insns
= 0;
5276 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5277 to avoid using up another bit in target_flags. */
5278 if (mips_entry_string
!= NULL
)
5280 if (*mips_entry_string
!= '\0')
5281 error ("invalid option `entry%s'", mips_entry_string
);
5283 if (! TARGET_MIPS16
)
5284 warning ("-mentry is only meaningful with -mips-16");
5289 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5290 attributes can access it. */
5296 /* Initialize the high and low values for legitimate floating point
5297 constants. Rather than trying to get the accuracy down to the
5298 last bit, just use approximate ranges. */
5299 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
5300 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
5301 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
5302 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
5304 mips_print_operand_punct
['?'] = 1;
5305 mips_print_operand_punct
['#'] = 1;
5306 mips_print_operand_punct
['&'] = 1;
5307 mips_print_operand_punct
['!'] = 1;
5308 mips_print_operand_punct
['*'] = 1;
5309 mips_print_operand_punct
['@'] = 1;
5310 mips_print_operand_punct
['.'] = 1;
5311 mips_print_operand_punct
['('] = 1;
5312 mips_print_operand_punct
[')'] = 1;
5313 mips_print_operand_punct
['['] = 1;
5314 mips_print_operand_punct
[']'] = 1;
5315 mips_print_operand_punct
['<'] = 1;
5316 mips_print_operand_punct
['>'] = 1;
5317 mips_print_operand_punct
['{'] = 1;
5318 mips_print_operand_punct
['}'] = 1;
5319 mips_print_operand_punct
['^'] = 1;
5320 mips_print_operand_punct
['$'] = 1;
5321 mips_print_operand_punct
['+'] = 1;
5322 mips_print_operand_punct
['~'] = 1;
5324 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
5325 mips_char_to_class
['e'] = M16_NA_REGS
;
5326 mips_char_to_class
['t'] = T_REG
;
5327 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
5328 mips_char_to_class
['h'] = HI_REG
;
5329 mips_char_to_class
['l'] = LO_REG
;
5330 mips_char_to_class
['a'] = HILO_REG
;
5331 mips_char_to_class
['x'] = MD_REGS
;
5332 mips_char_to_class
['b'] = ALL_REGS
;
5333 mips_char_to_class
['y'] = GR_REGS
;
5334 mips_char_to_class
['z'] = ST_REGS
;
5335 mips_char_to_class
['B'] = COP0_REGS
;
5336 mips_char_to_class
['C'] = COP2_REGS
;
5337 mips_char_to_class
['D'] = COP3_REGS
;
5339 /* Set up array to map GCC register number to debug register number.
5340 Ignore the special purpose register numbers. */
5342 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5343 mips_dbx_regno
[i
] = -1;
5345 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
5346 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
5347 mips_dbx_regno
[i
] = i
+ start
;
5349 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
5350 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
5351 mips_dbx_regno
[i
] = i
+ start
;
5353 /* Set up array giving whether a given register can hold a given mode.
5354 At present, restrict ints from being in FP registers, because reload
5355 is a little enthusiastic about storing extra values in FP registers,
5356 and this is not good for things like OS kernels. Also, due to the
5357 mandatory delay, it is as fast to load from cached memory as to move
5358 from the FP register. */
5360 for (mode
= VOIDmode
;
5361 mode
!= MAX_MACHINE_MODE
;
5362 mode
= (enum machine_mode
) ((int)mode
+ 1))
5364 register int size
= GET_MODE_SIZE (mode
);
5365 register enum mode_class
class = GET_MODE_CLASS (mode
);
5367 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5374 temp
= (regno
== FPSW_REGNUM
);
5376 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5377 || FP_REG_P (regno
));
5380 else if (GP_REG_P (regno
))
5381 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5383 else if (FP_REG_P (regno
))
5384 temp
= (((regno
% FP_INC
) == 0
5385 /* I think this change is OK regardless of abi, but
5386 I'm being cautions untill I can test this more.
5387 HARD_REGNO_MODE_OK is about whether or not you
5388 can move to and from a register without changing
5389 the value, not about whether math works on the
5391 || (mips_abi
== ABI_MEABI
&& size
<= 4))
5392 && (class == MODE_FLOAT
5393 || class == MODE_COMPLEX_FLOAT
5394 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
5395 && size
<= UNITS_PER_FPVALUE
);
5397 else if (MD_REG_P (regno
))
5398 temp
= (class == MODE_INT
5399 && (size
<= UNITS_PER_WORD
5400 || (regno
== MD_REG_FIRST
5401 && size
== 2 * UNITS_PER_WORD
)));
5403 else if (ALL_COP_REG_P (regno
))
5404 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
5408 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5412 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5413 initialized yet, so we can't use that here. */
5414 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5416 /* Provide default values for align_* for 64-bit targets. */
5417 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5419 if (align_loops
== 0)
5421 if (align_jumps
== 0)
5423 if (align_functions
== 0)
5424 align_functions
= 8;
5427 /* Register global variables with the garbage collector. */
5428 mips_add_gc_roots ();
5430 /* Functions to allocate, mark and deallocate machine-dependent
5432 init_machine_status
= &mips_init_machine_status
;
5433 free_machine_status
= &mips_free_machine_status
;
5434 mark_machine_status
= &mips_mark_machine_status
;
5437 /* Allocate a chunk of memory for per-function machine-dependent data. */
5439 mips_init_machine_status (fn
)
5440 struct function
*fn
;
5442 fn
->machine
= ((struct machine_function
*)
5443 xcalloc (1, sizeof (struct machine_function
)));
5446 /* Release the chunk of memory for per-function machine-dependent data. */
5448 mips_free_machine_status (fn
)
5449 struct function
*fn
;
5455 /* Mark per-function machine-dependent data. */
5457 mips_mark_machine_status (fn
)
5458 struct function
*fn
;
5462 ggc_mark_rtx (fn
->machine
->embedded_pic_fnaddr_rtx
);
5463 ggc_mark_rtx (fn
->machine
->mips16_gp_pseudo_rtx
);
5467 /* On the mips16, we want to allocate $24 (T_REG) before other
5468 registers for instructions for which it is possible. This helps
5469 avoid shuffling registers around in order to set up for an xor,
5470 encouraging the compiler to use a cmp instead. */
5473 mips_order_regs_for_local_alloc ()
5477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5478 reg_alloc_order
[i
] = i
;
5482 /* It really doesn't matter where we put register 0, since it is
5483 a fixed register anyhow. */
5484 reg_alloc_order
[0] = 24;
5485 reg_alloc_order
[24] = 0;
5490 /* The MIPS debug format wants all automatic variables and arguments
5491 to be in terms of the virtual frame pointer (stack pointer before
5492 any adjustment in the function), while the MIPS 3.0 linker wants
5493 the frame pointer to be the stack pointer after the initial
5494 adjustment. So, we do the adjustment here. The arg pointer (which
5495 is eliminated) points to the virtual frame pointer, while the frame
5496 pointer (which may be eliminated) points to the stack pointer after
5497 the initial adjustments. */
5500 mips_debugger_offset (addr
, offset
)
5502 HOST_WIDE_INT offset
;
5504 rtx offset2
= const0_rtx
;
5505 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5508 offset
= INTVAL (offset2
);
5510 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5511 || reg
== hard_frame_pointer_rtx
)
5513 HOST_WIDE_INT frame_size
= (!current_frame_info
.initialized
)
5514 ? compute_frame_size (get_frame_size ())
5515 : current_frame_info
.total_size
;
5517 /* MIPS16 frame is smaller */
5518 if (frame_pointer_needed
&& TARGET_MIPS16
)
5519 frame_size
-= current_function_outgoing_args_size
;
5521 offset
= offset
- frame_size
;
5524 /* sdbout_parms does not want this to crash for unrecognized cases. */
5526 else if (reg
!= arg_pointer_rtx
)
5527 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer");
5533 /* A C compound statement to output to stdio stream STREAM the
5534 assembler syntax for an instruction operand X. X is an RTL
5537 CODE is a value that can be used to specify one of several ways
5538 of printing the operand. It is used when identical operands
5539 must be printed differently depending on the context. CODE
5540 comes from the `%' specification that was used to request
5541 printing of the operand. If the specification was just `%DIGIT'
5542 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5543 is the ASCII code for LTR.
5545 If X is a register, this macro should print the register's name.
5546 The names can be found in an array `reg_names' whose type is
5547 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5549 When the machine description has a specification `%PUNCT' (a `%'
5550 followed by a punctuation character), this macro is called with
5551 a null pointer for X and the punctuation character for CODE.
5553 The MIPS specific codes are:
5555 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5556 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5557 'd' output integer constant in decimal,
5558 'z' if the operand is 0, use $0 instead of normal operand.
5559 'D' print second part of double-word register or memory operand.
5560 'L' print low-order register of double-word register operand.
5561 'M' print high-order register of double-word register operand.
5562 'C' print part of opcode for a branch condition.
5563 'F' print part of opcode for a floating-point branch condition.
5564 'N' print part of opcode for a branch condition, inverted.
5565 'W' print part of opcode for a floating-point branch condition, inverted.
5566 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5567 'B' print 'z' for EQ, 'n' for NE
5568 'b' print 'n' for EQ, 'z' for NE
5569 'T' print 'f' for EQ, 't' for NE
5570 't' print 't' for EQ, 'f' for NE
5571 'Z' print register and a comma, but print nothing for $fcc0
5572 '(' Turn on .set noreorder
5573 ')' Turn on .set reorder
5574 '[' Turn on .set noat
5576 '<' Turn on .set nomacro
5577 '>' Turn on .set macro
5578 '{' Turn on .set volatile (not GAS)
5579 '}' Turn on .set novolatile (not GAS)
5580 '&' Turn on .set noreorder if filling delay slots
5581 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5582 '!' Turn on .set nomacro if filling delay slots
5583 '#' Print nop if in a .set noreorder section.
5584 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5585 '@' Print the name of the assembler temporary register (at or $1).
5586 '.' Print the name of the register with a hard-wired zero (zero or $0).
5587 '^' Print the name of the pic call-through register (t9 or $25).
5588 '$' Print the name of the stack pointer register (sp or $29).
5589 '+' Print the name of the gp register (gp or $28).
5590 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5593 print_operand (file
, op
, letter
)
5594 FILE *file
; /* file to write to */
5595 rtx op
; /* operand to print */
5596 int letter
; /* %<letter> or 0 */
5598 register enum rtx_code code
;
5600 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5605 if (mips_branch_likely
)
5610 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5614 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5618 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5622 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5626 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
5630 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5631 fputs (".set\tnoreorder\n\t", file
);
5635 if (final_sequence
!= 0)
5637 if (set_noreorder
++ == 0)
5638 fputs (".set\tnoreorder\n\t", file
);
5640 if (set_nomacro
++ == 0)
5641 fputs (".set\tnomacro\n\t", file
);
5646 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5647 fputs ("\n\t.set\tnomacro", file
);
5651 if (set_noreorder
!= 0)
5652 fputs ("\n\tnop", file
);
5653 else if (TARGET_STATS
)
5654 fputs ("\n\t#nop", file
);
5659 if (set_noreorder
++ == 0)
5660 fputs (".set\tnoreorder\n\t", file
);
5664 if (set_noreorder
== 0)
5665 error ("internal error: %%) found without a %%( in assembler pattern");
5667 else if (--set_noreorder
== 0)
5668 fputs ("\n\t.set\treorder", file
);
5673 if (set_noat
++ == 0)
5674 fputs (".set\tnoat\n\t", file
);
5679 error ("internal error: %%] found without a %%[ in assembler pattern");
5680 else if (--set_noat
== 0)
5681 fputs ("\n\t.set\tat", file
);
5686 if (set_nomacro
++ == 0)
5687 fputs (".set\tnomacro\n\t", file
);
5691 if (set_nomacro
== 0)
5692 error ("internal error: %%> found without a %%< in assembler pattern");
5693 else if (--set_nomacro
== 0)
5694 fputs ("\n\t.set\tmacro", file
);
5699 if (set_volatile
++ == 0)
5700 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
5704 if (set_volatile
== 0)
5705 error ("internal error: %%} found without a %%{ in assembler pattern");
5706 else if (--set_volatile
== 0)
5707 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
5713 if (align_labels_log
> 0)
5714 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5719 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5728 error ("PRINT_OPERAND null pointer");
5732 code
= GET_CODE (op
);
5734 if (code
== SIGN_EXTEND
)
5735 op
= XEXP (op
, 0), code
= GET_CODE (op
);
5740 case EQ
: fputs ("eq", file
); break;
5741 case NE
: fputs ("ne", file
); break;
5742 case GT
: fputs ("gt", file
); break;
5743 case GE
: fputs ("ge", file
); break;
5744 case LT
: fputs ("lt", file
); break;
5745 case LE
: fputs ("le", file
); break;
5746 case GTU
: fputs ("gtu", file
); break;
5747 case GEU
: fputs ("geu", file
); break;
5748 case LTU
: fputs ("ltu", file
); break;
5749 case LEU
: fputs ("leu", file
); break;
5751 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
5754 else if (letter
== 'N')
5757 case EQ
: fputs ("ne", file
); break;
5758 case NE
: fputs ("eq", file
); break;
5759 case GT
: fputs ("le", file
); break;
5760 case GE
: fputs ("lt", file
); break;
5761 case LT
: fputs ("ge", file
); break;
5762 case LE
: fputs ("gt", file
); break;
5763 case GTU
: fputs ("leu", file
); break;
5764 case GEU
: fputs ("ltu", file
); break;
5765 case LTU
: fputs ("geu", file
); break;
5766 case LEU
: fputs ("gtu", file
); break;
5768 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
5771 else if (letter
== 'F')
5774 case EQ
: fputs ("c1f", file
); break;
5775 case NE
: fputs ("c1t", file
); break;
5777 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
5780 else if (letter
== 'W')
5783 case EQ
: fputs ("c1t", file
); break;
5784 case NE
: fputs ("c1f", file
); break;
5786 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
5789 else if (letter
== 'S')
5793 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
5794 assemble_name (file
, buffer
);
5797 else if (letter
== 'Z')
5799 register int regnum
;
5804 regnum
= REGNO (op
);
5805 if (! ST_REG_P (regnum
))
5808 if (regnum
!= ST_REG_FIRST
)
5809 fprintf (file
, "%s,", reg_names
[regnum
]);
5812 else if (code
== REG
|| code
== SUBREG
)
5814 register int regnum
;
5817 regnum
= REGNO (op
);
5819 regnum
= true_regnum (op
);
5821 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5822 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5826 fprintf (file
, "%s", reg_names
[regnum
]);
5829 else if (code
== MEM
)
5832 output_address (plus_constant (XEXP (op
, 0), 4));
5834 output_address (XEXP (op
, 0));
5837 else if (code
== CONST_DOUBLE
5838 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
5843 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
5844 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
5848 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5849 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5851 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5852 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5854 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5855 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5857 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
5858 fputs (reg_names
[GP_REG_FIRST
], file
);
5860 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5861 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5863 else if (letter
== 'B')
5864 fputs (code
== EQ
? "z" : "n", file
);
5865 else if (letter
== 'b')
5866 fputs (code
== EQ
? "n" : "z", file
);
5867 else if (letter
== 'T')
5868 fputs (code
== EQ
? "f" : "t", file
);
5869 else if (letter
== 't')
5870 fputs (code
== EQ
? "t" : "f", file
);
5872 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
5874 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5875 print_operand (file
, XEXP (op
, 0), letter
);
5878 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
5880 fputs ("%gprel(", file
);
5881 mips16_output_gp_offset (file
, op
);
5886 output_addr_const (file
, op
);
5889 /* A C compound statement to output to stdio stream STREAM the
5890 assembler syntax for an instruction operand that is a memory
5891 reference whose address is ADDR. ADDR is an RTL expression.
5893 On some machines, the syntax for a symbolic address depends on
5894 the section that the address refers to. On these machines,
5895 define the macro `ENCODE_SECTION_INFO' to store the information
5896 into the `symbol_ref', and then check for it here. */
5899 print_operand_address (file
, addr
)
5904 error ("PRINT_OPERAND_ADDRESS, null pointer");
5907 switch (GET_CODE (addr
))
5910 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
5911 abort_with_insn (addr
, "arg pointer not eliminated");
5913 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
5918 register rtx arg0
= XEXP (addr
, 0);
5919 register rtx arg1
= XEXP (addr
, 1);
5921 if (! mips_split_addresses
)
5922 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5924 if (GET_CODE (arg0
) != REG
)
5925 abort_with_insn (addr
,
5926 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5928 fprintf (file
, "%%lo(");
5929 print_operand_address (file
, arg1
);
5930 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
5936 register rtx reg
= 0;
5937 register rtx offset
= 0;
5938 register rtx arg0
= XEXP (addr
, 0);
5939 register rtx arg1
= XEXP (addr
, 1);
5941 if (GET_CODE (arg0
) == REG
)
5945 if (GET_CODE (offset
) == REG
)
5946 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
5949 else if (GET_CODE (arg1
) == REG
)
5950 reg
= arg1
, offset
= arg0
;
5951 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
5953 output_addr_const (file
, addr
);
5957 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
5959 if (! CONSTANT_P (offset
))
5960 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5962 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
5963 abort_with_insn (addr
, "arg pointer not eliminated");
5966 && GET_CODE (offset
) == CONST
5967 && mips16_gp_offset_p (offset
))
5969 fputs ("%gprel(", file
);
5970 mips16_output_gp_offset (file
, offset
);
5974 output_addr_const (file
, offset
);
5975 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
5983 output_addr_const (file
, addr
);
5987 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5992 /* Target hook for assembling integer objects. It appears that the Irix
5993 6 assembler can't handle 64-bit decimal integers, so avoid printing
5994 such an integer here. */
5997 mips_assemble_integer (x
, size
, aligned_p
)
6002 if ((TARGET_64BIT
|| TARGET_GAS
) && size
== 8 && aligned_p
)
6004 fputs ("\t.dword\t", asm_out_file
);
6005 if (HOST_BITS_PER_WIDE_INT
< 64 || GET_CODE (x
) != CONST_INT
)
6006 output_addr_const (asm_out_file
, x
);
6008 print_operand (asm_out_file
, x
, 'X');
6009 fputc ('\n', asm_out_file
);
6012 return default_assemble_integer (x
, size
, aligned_p
);
6015 /* If optimizing for the global pointer, keep track of all of the externs, so
6016 that at the end of the file, we can emit the appropriate .extern
6017 declaration for them, before writing out the text section. We assume all
6018 names passed to us are in the permanent obstack, so they will be valid at
6019 the end of the compilation.
6021 If we have -G 0, or the extern size is unknown, or the object is in a user
6022 specified section that is not .sbss/.sdata, don't bother emitting the
6023 .externs. In the case of user specified sections this behaviour is
6024 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6027 mips_output_external (file
, decl
, name
)
6028 FILE *file ATTRIBUTE_UNUSED
;
6032 register struct extern_list
*p
;
6037 && TREE_CODE (decl
) != FUNCTION_DECL
6038 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
6039 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
6040 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
6041 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
6043 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6044 p
->next
= extern_head
;
6050 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6051 if (TREE_CODE (decl
) == FUNCTION_DECL
6052 /* ??? Don't include alloca, since gcc will always expand it
6053 inline. If we don't do this, the C++ library fails to build. */
6054 && strcmp (name
, "alloca")
6055 /* ??? Don't include __builtin_next_arg, because then gcc will not
6056 bootstrap under Irix 5.1. */
6057 && strcmp (name
, "__builtin_next_arg"))
6059 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6060 p
->next
= extern_head
;
6070 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6072 mips_output_external_libcall (file
, name
)
6073 FILE *file ATTRIBUTE_UNUSED
;
6076 register struct extern_list
*p
;
6078 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6079 p
->next
= extern_head
;
6088 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6089 for .file's that start within a function. If we are smuggling stabs, try to
6090 put out a MIPS ECOFF file and a stab. */
6093 mips_output_filename (stream
, name
)
6097 static int first_time
= 1;
6098 char ltext_label_name
[100];
6104 current_function_file
= name
;
6105 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6106 /* This tells mips-tfile that stabs will follow. */
6107 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
6108 fprintf (stream
, "\t#@stabs\n");
6111 else if (write_symbols
== DBX_DEBUG
)
6113 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
6114 fprintf (stream
, "%s", ASM_STABS_OP
);
6115 output_quoted_string (stream
, name
);
6116 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
6119 else if (name
!= current_function_file
6120 && strcmp (name
, current_function_file
) != 0)
6122 if (inside_function
&& !TARGET_GAS
)
6124 if (!file_in_function_warning
)
6126 file_in_function_warning
= 1;
6127 ignore_line_number
= 1;
6128 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6134 current_function_file
= name
;
6135 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6140 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6141 as well as a .loc, since it is possible that MIPS ECOFF might not be
6142 able to represent the location for inlines that come from a different
6146 mips_output_lineno (stream
, line
)
6150 if (write_symbols
== DBX_DEBUG
)
6153 fprintf (stream
, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6154 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
6155 LOCAL_LABEL_PREFIX
, sym_lineno
);
6159 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
6160 (ignore_line_number
) ? "#" : "",
6161 num_source_filenames
, line
);
6163 LABEL_AFTER_LOC (stream
);
6167 /* Output an ASCII string, in a space-saving way. */
6170 mips_output_ascii (stream
, string_param
, len
)
6172 const char *string_param
;
6177 register const unsigned char *string
=
6178 (const unsigned char *)string_param
;
6180 fprintf (stream
, "\t.ascii\t\"");
6181 for (i
= 0; i
< len
; i
++)
6183 register int c
= string
[i
];
6189 putc ('\\', stream
);
6194 case TARGET_NEWLINE
:
6195 fputs ("\\n", stream
);
6197 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
6198 || c
== TARGET_TAB
))
6199 cur_pos
= 32767; /* break right here */
6205 fputs ("\\t", stream
);
6210 fputs ("\\f", stream
);
6215 fputs ("\\b", stream
);
6220 fputs ("\\r", stream
);
6225 if (c
>= ' ' && c
< 0177)
6232 fprintf (stream
, "\\%03o", c
);
6237 if (cur_pos
> 72 && i
+1 < len
)
6240 fprintf (stream
, "\"\n\t.ascii\t\"");
6243 fprintf (stream
, "\"\n");
6246 /* If defined, a C statement to be executed just prior to the output of
6247 assembler code for INSN, to modify the extracted operands so they will be
6250 Here the argument OPVEC is the vector containing the operands extracted
6251 from INSN, and NOPERANDS is the number of elements of the vector which
6252 contain meaningful data for this insn. The contents of this vector are
6253 what will be used to convert the insn template into assembler code, so you
6254 can change the assembler output by changing the contents of the vector.
6256 We use it to check if the current insn needs a nop in front of it because
6257 of load delays, and also to update the delay slot statistics. */
6259 /* ??? There is no real need for this function, because it never actually
6260 emits a NOP anymore. */
6263 final_prescan_insn (insn
, opvec
, noperands
)
6265 rtx opvec
[] ATTRIBUTE_UNUSED
;
6266 int noperands ATTRIBUTE_UNUSED
;
6268 if (dslots_number_nops
> 0)
6270 rtx pattern
= PATTERN (insn
);
6271 int length
= get_attr_length (insn
);
6273 /* Do we need to emit a NOP? */
6275 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
6276 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
6277 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
6278 || (mips_load_reg4
!= 0
6279 && reg_mentioned_p (mips_load_reg4
, pattern
)))
6280 fputs ("\t#nop\n", asm_out_file
);
6283 dslots_load_filled
++;
6285 while (--dslots_number_nops
> 0)
6286 fputs ("\t#nop\n", asm_out_file
);
6295 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
6296 dslots_jump_total
++;
6299 /* Output at beginning of assembler file.
6301 If we are optimizing to use the global pointer, create a temporary file to
6302 hold all of the text stuff, and write it out to the end. This is needed
6303 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6304 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6305 processed, it generates a two instruction sequence. */
6308 mips_asm_file_start (stream
)
6311 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
6313 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6314 inside of a .set noreorder section jumps to a label outside of the .set
6315 noreorder section. Revision 2.20 just set nobopt silently rather than
6318 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
6319 fprintf (stream
, "\t.set\tnobopt\n");
6323 #if defined(OBJECT_FORMAT_ELF)
6324 /* Generate a special section to describe the ABI switches used to
6325 produce the resultant binary. This used to be done by the assembler
6326 setting bits in the ELF header's flags field, but we have run out of
6327 bits. GDB needs this information in order to be able to correctly
6328 debug these binaries. See the function mips_gdbarch_init() in
6330 const char * abi_string
= NULL
;
6334 case ABI_32
: abi_string
= "abi32"; break;
6335 case ABI_N32
: abi_string
= "abiN32"; break;
6336 case ABI_64
: abi_string
= "abi64"; break;
6337 case ABI_O64
: abi_string
= "abiO64"; break;
6338 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
6339 case ABI_MEABI
:abi_string
= TARGET_64BIT
? "meabi64" : "meabi32"; break;
6343 /* Note - we use fprintf directly rather than called named_section()
6344 because in this way we can avoid creating an allocated section. We
6345 do not want this section to take up any space in the running
6347 fprintf (stream
, "\t.section .mdebug.%s\n", abi_string
);
6349 /* Restore the default section. */
6350 fprintf (stream
, "\t.previous\n");
6356 /* Generate the pseudo ops that System V.4 wants. */
6357 #ifndef ABICALLS_ASM_OP
6358 #define ABICALLS_ASM_OP "\t.abicalls"
6360 if (TARGET_ABICALLS
)
6361 /* ??? but do not want this (or want pic0) if -non-shared? */
6362 fprintf (stream
, "%s\n", ABICALLS_ASM_OP
);
6365 fprintf (stream
, "\t.set\tmips16\n");
6367 /* This code exists so that we can put all externs before all symbol
6368 references. This is necessary for the MIPS assembler's global pointer
6369 optimizations to work. */
6370 if (TARGET_FILE_SWITCHING
)
6372 asm_out_data_file
= stream
;
6373 asm_out_text_file
= tmpfile ();
6376 asm_out_data_file
= asm_out_text_file
= stream
;
6378 if (flag_verbose_asm
)
6379 fprintf (stream
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6381 mips_section_threshold
, mips_arch_string
, mips_isa
);
6384 /* If we are optimizing the global pointer, emit the text section now and any
6385 small externs which did not have .comm, etc that are needed. Also, give a
6386 warning if the data area is more than 32K and -pic because 3 instructions
6387 are needed to reference the data pointers. */
6390 mips_asm_file_end (file
)
6394 struct extern_list
*p
;
6398 HALF_PIC_FINISH (file
);
6405 for (p
= extern_head
; p
!= 0; p
= p
->next
)
6407 name_tree
= get_identifier (p
->name
);
6409 /* Positively ensure only one .extern for any given symbol. */
6410 if (! TREE_ASM_WRITTEN (name_tree
))
6412 TREE_ASM_WRITTEN (name_tree
) = 1;
6413 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6415 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
6419 fputs ("\t.extern\t", file
);
6420 assemble_name (file
, p
->name
);
6421 fprintf (file
, ", %d\n", p
->size
);
6427 if (TARGET_FILE_SWITCHING
)
6429 fprintf (file
, "\n\t.text\n");
6430 copy_file_data (file
, asm_out_text_file
);
6435 copy_file_data (to
, from
)
6442 fatal_io_error ("can't rewind temp file");
6444 while ((len
= fread (buffer
, 1, sizeof (buffer
), from
)) > 0)
6445 if (fwrite (buffer
, 1, len
, to
) != len
)
6446 fatal_io_error ("can't write to output file");
6449 fatal_io_error ("can't read from temp file");
6452 fatal_io_error ("can't close temp file");
6455 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6456 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6459 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
6462 const char *init_string
;
6463 const char *final_string
;
6466 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
6467 assemble_name (stream
, name
);
6468 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
6472 tree name_tree
= get_identifier (name
);
6473 TREE_ASM_WRITTEN (name_tree
) = 1;
6477 /* Return the bytes needed to compute the frame pointer from the current
6480 Mips stack frames look like:
6482 Before call After call
6483 +-----------------------+ +-----------------------+
6486 | caller's temps. | | caller's temps. |
6488 +-----------------------+ +-----------------------+
6490 | arguments on stack. | | arguments on stack. |
6492 +-----------------------+ +-----------------------+
6493 | 4 words to save | | 4 words to save |
6494 | arguments passed | | arguments passed |
6495 | in registers, even | | in registers, even |
6496 SP->| if not passed. | VFP->| if not passed. |
6497 +-----------------------+ +-----------------------+
6499 | fp register save |
6501 +-----------------------+
6503 | gp register save |
6505 +-----------------------+
6509 +-----------------------+
6511 | alloca allocations |
6513 +-----------------------+
6515 | GP save for V.4 abi |
6517 +-----------------------+
6519 | arguments on stack |
6521 +-----------------------+
6523 | arguments passed |
6524 | in registers, even |
6525 low SP->| if not passed. |
6526 memory +-----------------------+
6531 compute_frame_size (size
)
6532 HOST_WIDE_INT size
; /* # of var. bytes allocated */
6535 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6536 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6537 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6538 HOST_WIDE_INT extra_size
; /* # extra bytes */
6539 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6540 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6541 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6542 long mask
; /* mask of saved gp registers */
6543 long fmask
; /* mask of saved fp registers */
6550 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
6551 var_size
= MIPS_STACK_ALIGN (size
);
6552 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
6554 /* The MIPS 3.0 linker does not like functions that dynamically
6555 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6556 looks like we are trying to create a second frame pointer to the
6557 function, so allocate some stack space to make it happy. */
6559 if (args_size
== 0 && current_function_calls_alloca
)
6560 args_size
= 4 * UNITS_PER_WORD
;
6562 total_size
= var_size
+ args_size
+ extra_size
;
6563 return_type
= DECL_RESULT (current_function_decl
);
6565 /* Calculate space needed for gp registers. */
6566 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6568 /* $18 is a special case on the mips16. It may be used to call
6569 a function which returns a floating point value, but it is
6570 marked in call_used_regs. $31 is also a special case. When
6571 not using -mentry, it will be used to copy a return value
6572 into the floating point registers if the return value is
6574 if (MUST_SAVE_REGISTER (regno
)
6576 && regno
== GP_REG_FIRST
+ 18
6577 && regs_ever_live
[regno
])
6579 && regno
== GP_REG_FIRST
+ 31
6580 && mips16_hard_float
6582 && ! aggregate_value_p (return_type
)
6583 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6584 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
))
6586 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6587 mask
|= 1L << (regno
- GP_REG_FIRST
);
6589 /* The entry and exit pseudo instructions can not save $17
6590 without also saving $16. */
6592 && regno
== GP_REG_FIRST
+ 17
6593 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
6595 gp_reg_size
+= UNITS_PER_WORD
;
6601 /* We need to restore these for the handler. */
6602 if (current_function_calls_eh_return
)
6607 regno
= EH_RETURN_DATA_REGNO (i
);
6608 if (regno
== INVALID_REGNUM
)
6610 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6611 mask
|= 1L << (regno
- GP_REG_FIRST
);
6615 /* This loop must iterate over the same space as its companion in
6616 save_restore_insns. */
6617 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6618 regno
>= FP_REG_FIRST
;
6621 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6623 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
6624 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
6628 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6629 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6631 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6632 for leaf routines (total_size == extra_size) to save the gp reg.
6633 The gp reg is callee saved in the 64 bit ABI, so all routines must
6634 save the gp reg. This is not a leaf routine if -p, because of the
6636 if (total_size
== extra_size
6637 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
6638 && ! current_function_profile
)
6639 total_size
= extra_size
= 0;
6640 else if (TARGET_ABICALLS
)
6642 /* Add the context-pointer to the saved registers. */
6643 gp_reg_size
+= UNITS_PER_WORD
;
6644 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
6645 total_size
-= gp_reg_rounded
;
6646 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6647 total_size
+= gp_reg_rounded
;
6650 /* Add in space reserved on the stack by the callee for storing arguments
6651 passed in registers. */
6652 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6653 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
6655 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6656 if (mips_entry
&& total_size
> 0 && total_size
< 32)
6659 /* Save other computed information. */
6660 current_frame_info
.total_size
= total_size
;
6661 current_frame_info
.var_size
= var_size
;
6662 current_frame_info
.args_size
= args_size
;
6663 current_frame_info
.extra_size
= extra_size
;
6664 current_frame_info
.gp_reg_size
= gp_reg_size
;
6665 current_frame_info
.fp_reg_size
= fp_reg_size
;
6666 current_frame_info
.mask
= mask
;
6667 current_frame_info
.fmask
= fmask
;
6668 current_frame_info
.initialized
= reload_completed
;
6669 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6670 current_frame_info
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
6674 unsigned long offset
;
6676 /* When using mips_entry, the registers are always saved at the
6677 top of the stack. */
6679 offset
= (args_size
+ extra_size
+ var_size
6680 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6682 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
6684 current_frame_info
.gp_sp_offset
= offset
;
6685 current_frame_info
.gp_save_offset
= offset
- total_size
;
6689 current_frame_info
.gp_sp_offset
= 0;
6690 current_frame_info
.gp_save_offset
= 0;
6695 unsigned long offset
= (args_size
+ extra_size
+ var_size
6696 + gp_reg_rounded
+ fp_reg_size
6697 - FP_INC
* UNITS_PER_FPREG
);
6698 current_frame_info
.fp_sp_offset
= offset
;
6699 current_frame_info
.fp_save_offset
= offset
- total_size
;
6703 current_frame_info
.fp_sp_offset
= 0;
6704 current_frame_info
.fp_save_offset
= 0;
6707 /* Ok, we're done. */
6711 /* Common code to emit the insns (or to write the instructions to a file)
6712 to save/restore registers.
6714 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6715 is not modified within save_restore_insns. */
6717 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6719 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6720 and return an rtl expression for the register.
6722 This function is a subroutine of save_restore_insns. It is used when
6723 OFFSET is too large to add in a single instruction. */
6726 mips_add_large_offset_to_sp (offset
)
6727 HOST_WIDE_INT offset
;
6729 rtx reg
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6730 rtx offset_rtx
= GEN_INT (offset
);
6732 emit_move_insn (reg
, offset_rtx
);
6733 if (Pmode
== DImode
)
6734 emit_insn (gen_adddi3 (reg
, reg
, stack_pointer_rtx
));
6736 emit_insn (gen_addsi3 (reg
, reg
, stack_pointer_rtx
));
6740 /* Make INSN frame related and note that it performs the frame-related
6741 operation DWARF_PATTERN. */
6744 mips_annotate_frame_insn (insn
, dwarf_pattern
)
6745 rtx insn
, dwarf_pattern
;
6747 RTX_FRAME_RELATED_P (insn
) = 1;
6748 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6753 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6754 The expression should only be used to store single registers. */
6757 mips_frame_set (mode
, regno
, offset
)
6758 enum machine_mode mode
;
6762 rtx address
= plus_constant (stack_pointer_rtx
, offset
);
6763 rtx set
= gen_rtx_SET (mode
,
6764 gen_rtx_MEM (mode
, address
),
6765 gen_rtx_REG (mode
, regno
));
6766 RTX_FRAME_RELATED_P (set
) = 1;
6771 /* Emit a move instruction that stores REG in MEM. Make the instruction
6772 frame related and note that it stores REG at (SP + OFFSET). This
6773 function may be asked to store an FPR pair. */
6776 mips_emit_frame_related_store (mem
, reg
, offset
)
6779 HOST_WIDE_INT offset
;
6783 if (GET_MODE (reg
) == DFmode
&& ! TARGET_FLOAT64
)
6785 /* Two registers are being stored, so the frame-related expression
6786 must be a PARALLEL rtx with one SET for each register. The
6787 higher numbered register is stored in the lower address on
6788 big-endian targets. */
6789 int regno1
= TARGET_BIG_ENDIAN
? REGNO (reg
) + 1 : REGNO (reg
);
6790 int regno2
= TARGET_BIG_ENDIAN
? REGNO (reg
) : REGNO (reg
) + 1;
6791 rtx set1
= mips_frame_set (SFmode
, regno1
, offset
);
6792 rtx set2
= mips_frame_set (SFmode
, regno2
, offset
+ UNITS_PER_FPREG
);
6793 dwarf_expr
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set1
, set2
));
6796 dwarf_expr
= mips_frame_set (GET_MODE (reg
), REGNO (reg
), offset
);
6798 mips_annotate_frame_insn (emit_move_insn (mem
, reg
), dwarf_expr
);
6802 save_restore_insns (store_p
, large_reg
, large_offset
)
6803 int store_p
; /* true if this is prologue */
6804 rtx large_reg
; /* register holding large offset constant or NULL */
6805 long large_offset
; /* large constant offset value */
6807 long mask
= current_frame_info
.mask
;
6808 long fmask
= current_frame_info
.fmask
;
6809 long real_mask
= mask
;
6812 HOST_WIDE_INT base_offset
;
6813 HOST_WIDE_INT gp_offset
;
6814 HOST_WIDE_INT fp_offset
;
6815 HOST_WIDE_INT end_offset
;
6818 if (frame_pointer_needed
6819 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
6822 /* Do not restore GP under certain conditions. */
6825 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
6826 mask
&= ~(1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
));
6828 if (mask
== 0 && fmask
== 0)
6831 /* Save registers starting from high to low. The debuggers prefer at least
6832 the return register be stored at func+4, and also it allows us not to
6833 need a nop in the epilog if at least one register is reloaded in
6834 addition to return address. */
6836 /* Save GP registers if needed. */
6839 /* Pick which pointer to use as a base register. For small frames, just
6840 use the stack pointer. Otherwise, use a temporary register. Save 2
6841 cycles if the save area is near the end of a large frame, by reusing
6842 the constant created in the prologue/epilogue to adjust the stack
6845 gp_offset
= current_frame_info
.gp_sp_offset
;
6847 = gp_offset
- (current_frame_info
.gp_reg_size
6848 - GET_MODE_SIZE (gpr_mode
));
6850 if (gp_offset
< 0 || end_offset
< 0)
6852 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6853 (long) gp_offset
, (long) end_offset
);
6855 /* If we see a large frame in mips16 mode, we save the registers
6856 before adjusting the stack pointer, and load them afterward. */
6857 else if (TARGET_MIPS16
&& large_offset
> 32767)
6858 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
6860 else if (gp_offset
< 32768)
6861 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6863 else if (large_reg
!= 0
6864 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
6865 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6867 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6868 base_offset
= large_offset
;
6869 if (Pmode
== DImode
)
6870 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6871 stack_pointer_rtx
));
6873 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6874 stack_pointer_rtx
));
6878 base_offset
= gp_offset
;
6879 base_reg_rtx
= mips_add_large_offset_to_sp (base_offset
);
6882 /* When we restore the registers in MIPS16 mode, then if we are
6883 using a frame pointer, and this is not a large frame, the
6884 current stack pointer will be offset by
6885 current_function_outgoing_args_size. Doing it this way lets
6886 us avoid offsetting the frame pointer before copying it into
6887 the stack pointer; there is no instruction to set the stack
6888 pointer to the sum of a register and a constant. */
6891 && frame_pointer_needed
6892 && large_offset
<= 32767)
6893 base_offset
+= current_function_outgoing_args_size
;
6895 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6897 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
6901 = gen_rtx (MEM
, gpr_mode
,
6902 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6903 GEN_INT (gp_offset
- base_offset
)));
6905 if (! current_function_calls_eh_return
)
6906 RTX_UNCHANGING_P (mem_rtx
) = 1;
6908 /* The mips16 does not have an instruction to load
6909 $31, so we load $7 instead, and work things out
6910 in mips_expand_epilogue. */
6911 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
6912 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
6913 /* The mips16 sometimes needs to save $18. */
6914 else if (TARGET_MIPS16
6915 && regno
!= GP_REG_FIRST
+ 31
6916 && ! M16_REG_P (regno
))
6919 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
6922 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
6923 emit_move_insn (reg_rtx
,
6924 gen_rtx (REG
, gpr_mode
, regno
));
6928 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
6931 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, gp_offset
);
6934 emit_move_insn (reg_rtx
, mem_rtx
);
6936 && regno
!= GP_REG_FIRST
+ 31
6937 && ! M16_REG_P (regno
))
6938 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
6942 /* If the restore is being supressed, still take into account
6943 the offset at which it is stored. */
6944 if (BITSET_P (real_mask
, regno
- GP_REG_FIRST
))
6945 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
6949 base_reg_rtx
= 0, base_offset
= 0;
6951 /* Save floating point registers if needed. */
6954 /* Pick which pointer to use as a base register. */
6955 fp_offset
= current_frame_info
.fp_sp_offset
;
6956 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
6957 - UNITS_PER_FPVALUE
);
6959 if (fp_offset
< 0 || end_offset
< 0)
6961 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
6962 (long) fp_offset
, (long) end_offset
);
6964 else if (fp_offset
< 32768)
6965 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6967 else if (base_reg_rtx
!= 0
6968 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
6969 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
6970 ; /* already set up for gp registers above */
6972 else if (large_reg
!= 0
6973 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
6974 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6976 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6977 base_offset
= large_offset
;
6978 if (Pmode
== DImode
)
6979 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6980 stack_pointer_rtx
));
6982 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6983 stack_pointer_rtx
));
6987 base_offset
= fp_offset
;
6988 base_reg_rtx
= mips_add_large_offset_to_sp (fp_offset
);
6991 /* This loop must iterate over the same space as its companion in
6992 compute_frame_size. */
6993 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6994 regno
>= FP_REG_FIRST
;
6996 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
6998 enum machine_mode sz
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6999 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
7000 rtx mem_rtx
= gen_rtx (MEM
, sz
,
7001 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
7004 if (! current_function_calls_eh_return
)
7005 RTX_UNCHANGING_P (mem_rtx
) = 1;
7008 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, fp_offset
);
7010 emit_move_insn (reg_rtx
, mem_rtx
);
7012 fp_offset
-= UNITS_PER_FPVALUE
;
7017 /* Set up the stack and frame (if desired) for the function. */
7020 mips_output_function_prologue (file
, size
)
7022 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7024 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7027 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7029 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
7031 #ifdef SDB_DEBUGGING_INFO
7032 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
7033 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
7036 /* In mips16 mode, we may need to generate a 32 bit to handle
7037 floating point arguments. The linker will arrange for any 32 bit
7038 functions to call this stub, which will then jump to the 16 bit
7040 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
7041 && current_function_args_info
.fp_code
!= 0)
7042 build_mips16_function_stub (file
);
7044 inside_function
= 1;
7046 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7047 /* Get the function name the same way that toplev.c does before calling
7048 assemble_start_function. This is needed so that the name used here
7049 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7050 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7052 if (!flag_inhibit_size_directive
)
7054 fputs ("\t.ent\t", file
);
7055 assemble_name (file
, fnname
);
7059 assemble_name (file
, fnname
);
7060 fputs (":\n", file
);
7063 if (!flag_inhibit_size_directive
)
7065 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7067 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7068 (reg_names
[(frame_pointer_needed
)
7069 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
7070 ((frame_pointer_needed
&& TARGET_MIPS16
)
7071 ? ((long) tsize
- current_function_outgoing_args_size
)
7073 reg_names
[GP_REG_FIRST
+ 31],
7074 current_frame_info
.var_size
,
7075 current_frame_info
.num_gp
,
7076 current_frame_info
.num_fp
,
7077 current_function_outgoing_args_size
,
7078 current_frame_info
.extra_size
);
7080 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7081 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7082 current_frame_info
.mask
,
7083 current_frame_info
.gp_save_offset
,
7084 current_frame_info
.fmask
,
7085 current_frame_info
.fp_save_offset
);
7088 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7089 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7092 if (mips_entry
&& ! mips_can_use_return_insn ())
7094 int save16
= BITSET_P (current_frame_info
.mask
, 16);
7095 int save17
= BITSET_P (current_frame_info
.mask
, 17);
7096 int save31
= BITSET_P (current_frame_info
.mask
, 31);
7100 /* Look through the initial insns to see if any of them store
7101 the function parameters into the incoming parameter storage
7102 area. If they do, we delete the insn, and save the register
7103 using the entry pseudo-instruction instead. We don't try to
7104 look past a label, jump, or call. */
7105 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
7107 rtx note
, set
, src
, dest
, base
, offset
;
7110 if (GET_CODE (insn
) == CODE_LABEL
7111 || GET_CODE (insn
) == JUMP_INSN
7112 || GET_CODE (insn
) == CALL_INSN
)
7114 if (GET_CODE (insn
) != INSN
)
7116 set
= PATTERN (insn
);
7117 if (GET_CODE (set
) != SET
)
7120 /* An insn storing a function parameter will still have a
7121 REG_EQUIV note on it mentioning the argument pointer. */
7122 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
7123 if (note
== NULL_RTX
)
7125 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
7128 src
= SET_SRC (set
);
7129 if (GET_CODE (src
) != REG
7130 || REGNO (src
) < GP_REG_FIRST
+ 4
7131 || REGNO (src
) > GP_REG_FIRST
+ 7)
7134 dest
= SET_DEST (set
);
7135 if (GET_CODE (dest
) != MEM
)
7137 if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned) UNITS_PER_WORD
)
7139 else if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned)2 * UNITS_PER_WORD
7140 && REGNO (src
) < GP_REG_FIRST
+ 7)
7144 offset
= const0_rtx
;
7145 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
7146 if (GET_CODE (base
) != REG
7147 || GET_CODE (offset
) != CONST_INT
)
7149 if (REGNO (base
) == (unsigned) STACK_POINTER_REGNUM
7150 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
7152 else if (REGNO (base
) == (unsigned) HARD_FRAME_POINTER_REGNUM
7155 + (REGNO (src
) - 4) * UNITS_PER_WORD
7156 - current_function_outgoing_args_size
)))
7161 /* This insn stores a parameter onto the stack, in the same
7162 location where the entry pseudo-instruction will put it.
7163 Delete the insn, and arrange to tell the entry
7164 instruction to save the register. */
7165 PUT_CODE (insn
, NOTE
);
7166 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7167 NOTE_SOURCE_FILE (insn
) = 0;
7169 hireg
= (REGNO (src
)
7170 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
7172 if (hireg
> savearg
)
7176 /* If this is a varargs function, we need to save all the
7177 registers onto the stack anyhow. */
7178 if (current_function_stdarg
|| current_function_varargs
)
7179 savearg
= GP_REG_FIRST
+ 7;
7181 fprintf (file
, "\tentry\t");
7184 if (savearg
== GP_REG_FIRST
+ 4)
7185 fprintf (file
, "%s", reg_names
[savearg
]);
7187 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
7188 reg_names
[savearg
]);
7190 if (save16
|| save17
)
7193 fprintf (file
, ",");
7194 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
7196 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
7200 if (savearg
> 0 || save16
|| save17
)
7201 fprintf (file
, ",");
7202 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
7204 fprintf (file
, "\n");
7207 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7209 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7211 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7212 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
7215 fprintf (file
, "\t%s\t%s,%s,%ld\n",
7216 (Pmode
== DImode
? "dsubu" : "subu"),
7217 sp_str
, sp_str
, (long) tsize
);
7218 fprintf (file
, "\t.cprestore %ld\n", current_frame_info
.args_size
);
7221 if (dwarf2out_do_frame ())
7222 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
7226 /* Expand the prologue into a bunch of separate insns. */
7229 mips_expand_prologue ()
7232 HOST_WIDE_INT tsize
;
7234 int last_arg_is_vararg_marker
= 0;
7235 tree fndecl
= current_function_decl
;
7236 tree fntype
= TREE_TYPE (fndecl
);
7237 tree fnargs
= DECL_ARGUMENTS (fndecl
);
7242 CUMULATIVE_ARGS args_so_far
;
7243 rtx reg_18_save
= NULL_RTX
;
7244 int store_args_on_stack
= (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
7245 && (! mips_entry
|| mips_can_use_return_insn ());
7247 /* If struct value address is treated as the first argument, make it so. */
7248 if (aggregate_value_p (DECL_RESULT (fndecl
))
7249 && ! current_function_returns_pcc_struct
7250 && struct_value_incoming_rtx
== 0)
7252 tree type
= build_pointer_type (fntype
);
7253 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
7255 DECL_ARG_TYPE (function_result_decl
) = type
;
7256 TREE_CHAIN (function_result_decl
) = fnargs
;
7257 fnargs
= function_result_decl
;
7260 /* For arguments passed in registers, find the register number
7261 of the first argument in the variable part of the argument list,
7262 otherwise GP_ARG_LAST+1. Note also if the last argument is
7263 the varargs special argument, and treat it as part of the
7266 This is only needed if store_args_on_stack is true. */
7268 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
7269 regno
= GP_ARG_FIRST
;
7271 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
7273 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
7274 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
7277 if (TREE_ADDRESSABLE (passed_type
))
7279 passed_type
= build_pointer_type (passed_type
);
7280 passed_mode
= Pmode
;
7283 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
7285 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
7286 next_arg
= TREE_CHAIN (cur_arg
);
7288 if (entry_parm
&& store_args_on_stack
)
7291 && DECL_NAME (cur_arg
)
7292 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7293 "__builtin_va_alist"))
7294 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7297 last_arg_is_vararg_marker
= 1;
7298 if (GET_CODE (entry_parm
) == REG
)
7299 regno
= REGNO (entry_parm
);
7301 regno
= GP_ARG_LAST
+ 1;
7308 if (GET_CODE (entry_parm
) != REG
)
7311 /* passed in a register, so will get homed automatically */
7312 if (GET_MODE (entry_parm
) == BLKmode
)
7313 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
7315 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
7317 regno
= REGNO (entry_parm
) + words
- 1;
7322 regno
= GP_ARG_LAST
+1;
7327 /* In order to pass small structures by value in registers compatibly with
7328 the MIPS compiler, we need to shift the value into the high part of the
7329 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7330 adjustments to be made as the next_arg_reg variable, so we split up the
7331 insns, and emit them separately. */
7333 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
7334 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
7336 rtvec adjust
= XVEC (next_arg_reg
, 0);
7337 int num
= GET_NUM_ELEM (adjust
);
7339 for (i
= 0; i
< num
; i
++)
7343 pattern
= RTVEC_ELT (adjust
, i
);
7344 if (GET_CODE (pattern
) != SET
7345 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
7346 abort_with_insn (pattern
, "insn is not a shift");
7347 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
7349 insn
= emit_insn (pattern
);
7351 /* Global life information isn't valid at this point, so we
7352 can't check whether these shifts are actually used. Mark
7353 them MAYBE_DEAD so that flow2 will remove them, and not
7354 complain about dead code in the prologue. */
7355 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, NULL_RTX
,
7360 tsize
= compute_frame_size (get_frame_size ());
7362 /* If this function is a varargs function, store any registers that
7363 would normally hold arguments ($4 - $7) on the stack. */
7364 if (store_args_on_stack
7365 && ((TYPE_ARG_TYPES (fntype
) != 0
7366 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
7368 || last_arg_is_vararg_marker
))
7370 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
7371 rtx ptr
= stack_pointer_rtx
;
7373 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7374 if (TARGET_ABICALLS
)
7377 for (; regno
<= GP_ARG_LAST
; regno
++)
7380 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
7381 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
7382 gen_rtx (REG
, gpr_mode
, regno
));
7384 offset
+= GET_MODE_SIZE (gpr_mode
);
7388 /* If we are using the entry pseudo instruction, it will
7389 automatically subtract 32 from the stack pointer, so we don't
7390 need to. The entry pseudo instruction is emitted by
7391 function_prologue. */
7392 if (mips_entry
&& ! mips_can_use_return_insn ())
7394 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
7398 /* If we are using a frame pointer with a small stack frame,
7399 we need to initialize it here since it won't be done
7401 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7403 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7404 if (Pmode
== DImode
)
7405 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7409 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7413 else if (Pmode
== DImode
)
7414 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7415 stack_pointer_rtx
));
7417 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7418 stack_pointer_rtx
));
7420 RTX_FRAME_RELATED_P (insn
) = 1;
7423 /* We may need to save $18, if it is used to call a function
7424 which may return a floating point value. Set up a sequence
7425 of instructions to do so. Later on we emit them at the right
7427 if (TARGET_MIPS16
&& BITSET_P (current_frame_info
.mask
, 18))
7429 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
7430 long gp_offset
, base_offset
;
7432 gp_offset
= current_frame_info
.gp_sp_offset
;
7433 if (BITSET_P (current_frame_info
.mask
, 16))
7434 gp_offset
-= UNITS_PER_WORD
;
7435 if (BITSET_P (current_frame_info
.mask
, 17))
7436 gp_offset
-= UNITS_PER_WORD
;
7437 if (BITSET_P (current_frame_info
.mask
, 31))
7438 gp_offset
-= UNITS_PER_WORD
;
7440 base_offset
= tsize
;
7444 emit_move_insn (reg_rtx
,
7445 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
7446 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
7447 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
7451 reg_18_save
= gen_sequence ();
7460 if (reg_18_save
!= NULL_RTX
)
7461 emit_insn (reg_18_save
);
7467 rtx tsize_rtx
= GEN_INT (tsize
);
7469 /* If we are doing svr4-abi, sp move is done by
7470 function_prologue. In mips16 mode with a large frame, we
7471 save the registers before adjusting the stack. */
7472 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7473 && (!TARGET_MIPS16
|| tsize
<= 32767))
7475 rtx adjustment_rtx
, insn
, dwarf_pattern
;
7479 adjustment_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
7480 emit_move_insn (adjustment_rtx
, tsize_rtx
);
7483 adjustment_rtx
= tsize_rtx
;
7485 if (Pmode
== DImode
)
7486 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7489 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7492 dwarf_pattern
= gen_rtx_SET (Pmode
, stack_pointer_rtx
,
7493 plus_constant (stack_pointer_rtx
,
7496 mips_annotate_frame_insn (insn
, dwarf_pattern
);
7500 save_restore_insns (1, tmp_rtx
, tsize
);
7501 else if (reg_18_save
!= NULL_RTX
)
7502 emit_insn (reg_18_save
);
7504 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7510 if (!frame_pointer_needed
)
7513 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
7514 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7515 emit_move_insn (reg_rtx
, tsize_rtx
);
7516 if (Pmode
== DImode
)
7517 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
7518 hard_frame_pointer_rtx
,
7521 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
7522 hard_frame_pointer_rtx
,
7524 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
7527 if (frame_pointer_needed
)
7531 /* On the mips16, we encourage the use of unextended
7532 instructions when using the frame pointer by pointing the
7533 frame pointer ahead of the argument space allocated on
7535 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7539 /* In this case, we have already copied the stack
7540 pointer into the frame pointer, above. We need only
7541 adjust for the outgoing argument size. */
7542 if (current_function_outgoing_args_size
!= 0)
7544 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7545 if (Pmode
== DImode
)
7546 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7547 hard_frame_pointer_rtx
,
7550 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7551 hard_frame_pointer_rtx
,
7555 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7557 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7558 if (Pmode
== DImode
)
7559 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7563 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7567 else if (Pmode
== DImode
)
7568 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7569 stack_pointer_rtx
));
7571 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7572 stack_pointer_rtx
));
7575 RTX_FRAME_RELATED_P (insn
) = 1;
7578 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7579 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
7580 gen_rtx_REG (DImode
, 25)));
7583 /* If we are profiling, make sure no instructions are scheduled before
7584 the call to mcount. */
7586 if (current_function_profile
)
7587 emit_insn (gen_blockage ());
7590 /* Do any necessary cleanup after a function to restore stack, frame,
7593 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7594 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7597 mips_output_function_epilogue (file
, size
)
7598 FILE *file ATTRIBUTE_UNUSED
;
7599 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7601 const char *fnname
= ""; /* FIXME: Correct initialisation? */
7603 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7604 /* Get the function name the same way that toplev.c does before calling
7605 assemble_start_function. This is needed so that the name used here
7606 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7607 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7609 if (!flag_inhibit_size_directive
)
7611 fputs ("\t.end\t", file
);
7612 assemble_name (file
, fnname
);
7619 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
7620 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
7621 int num_regs
= num_gp_regs
+ num_fp_regs
;
7622 const char *name
= fnname
;
7627 dslots_load_total
+= num_regs
;
7630 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7631 name
, frame_pointer_needed
? 'y' : 'n',
7632 (current_frame_info
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
7633 current_function_calls_alloca
? 'y' : 'n',
7634 current_function_calls_setjmp
? 'y' : 'n',
7635 current_frame_info
.total_size
,
7636 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
7637 dslots_load_total
, dslots_load_filled
,
7638 dslots_jump_total
, dslots_jump_filled
,
7639 num_refs
[0], num_refs
[1], num_refs
[2]);
7641 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
7644 " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
7645 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
7648 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
7651 " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
7652 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
7655 fputc ('\n', stderr
);
7658 /* Reset state info for each function. */
7659 inside_function
= 0;
7660 ignore_line_number
= 0;
7661 dslots_load_total
= 0;
7662 dslots_jump_total
= 0;
7663 dslots_load_filled
= 0;
7664 dslots_jump_filled
= 0;
7670 current_frame_info
= zero_frame_info
;
7672 while (string_constants
!= NULL
)
7674 struct string_constant
*next
;
7676 next
= string_constants
->next
;
7677 free (string_constants
);
7678 string_constants
= next
;
7681 /* Restore the output file if optimizing the GP (optimizing the GP causes
7682 the text to be diverted to a tempfile, so that data decls come before
7683 references to the data). */
7684 if (TARGET_FILE_SWITCHING
)
7686 asm_out_file
= asm_out_data_file
;
7691 /* Expand the epilogue into a bunch of separate insns. */
7694 mips_expand_epilogue ()
7696 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7697 rtx tsize_rtx
= GEN_INT (tsize
);
7698 rtx tmp_rtx
= (rtx
)0;
7700 if (mips_can_use_return_insn ())
7702 emit_insn (gen_return ());
7706 if (mips_entry
&& ! mips_can_use_return_insn ())
7709 if (tsize
> 32767 && ! TARGET_MIPS16
)
7711 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
7712 emit_move_insn (tmp_rtx
, tsize_rtx
);
7713 tsize_rtx
= tmp_rtx
;
7718 long orig_tsize
= tsize
;
7720 if (frame_pointer_needed
)
7722 emit_insn (gen_blockage ());
7724 /* On the mips16, the frame pointer is offset from the stack
7725 pointer by current_function_outgoing_args_size. We
7726 account for that by changing tsize. Note that this can
7727 actually make tsize negative. */
7730 tsize
-= current_function_outgoing_args_size
;
7732 /* If we have a large frame, it's easier to add to $6
7733 than to $sp, since the mips16 has no instruction to
7734 add a register to $sp. */
7735 if (orig_tsize
> 32767)
7737 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7739 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
7740 if (Pmode
== DImode
)
7741 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7742 hard_frame_pointer_rtx
,
7745 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7746 hard_frame_pointer_rtx
,
7751 if (tsize
&& tsize
!= orig_tsize
)
7752 tsize_rtx
= GEN_INT (tsize
);
7755 if (Pmode
== DImode
)
7756 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7758 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7761 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7762 are going to restore it, then we must emit a blockage insn to
7763 prevent the scheduler from moving the restore out of the epilogue. */
7764 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
7765 && (current_frame_info
.mask
7766 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
7767 emit_insn (gen_blockage ());
7769 save_restore_insns (0, tmp_rtx
, orig_tsize
);
7771 /* In mips16 mode with a large frame, we adjust the stack
7772 pointer before restoring the registers. In this case, we
7773 should always be using a frame pointer, so everything should
7774 have been handled above. */
7775 if (tsize
> 32767 && TARGET_MIPS16
)
7778 if (current_function_calls_eh_return
)
7780 rtx eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7781 if (Pmode
== DImode
)
7782 emit_insn (gen_adddi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7784 emit_insn (gen_addsi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7788 emit_insn (gen_blockage ());
7790 if (tsize
!= 0 || current_function_calls_eh_return
)
7794 if (Pmode
== DImode
)
7795 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7798 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7803 /* We need to work around not being able to add a register
7804 to the stack pointer directly. Use register $6 as an
7805 intermediate step. */
7807 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7809 if (Pmode
== DImode
)
7811 emit_insn (gen_movdi (g6_rtx
, stack_pointer_rtx
));
7812 emit_insn (gen_adddi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7813 emit_insn (gen_movdi (stack_pointer_rtx
, g6_rtx
));
7817 emit_insn (gen_movsi (g6_rtx
, stack_pointer_rtx
));
7818 emit_insn (gen_addsi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7819 emit_insn (gen_movsi (stack_pointer_rtx
, g6_rtx
));
7826 /* The mips16 loads the return address into $7, not $31. */
7827 if (TARGET_MIPS16
&& (current_frame_info
.mask
& RA_MASK
) != 0)
7828 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7829 GP_REG_FIRST
+ 7)));
7831 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7832 GP_REG_FIRST
+ 31)));
7835 /* Return nonzero if this function is known to have a null epilogue.
7836 This allows the optimizer to omit jumps to jumps if no stack
7840 mips_can_use_return_insn ()
7844 if (! reload_completed
)
7847 if (regs_ever_live
[31] || current_function_profile
)
7850 return_type
= DECL_RESULT (current_function_decl
);
7852 /* In mips16 mode, a function which returns a floating point value
7853 needs to arrange to copy the return value into the floating point
7856 && mips16_hard_float
7857 && ! aggregate_value_p (return_type
)
7858 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
7859 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
7862 if (current_frame_info
.initialized
)
7863 return current_frame_info
.total_size
== 0;
7865 return compute_frame_size (get_frame_size ()) == 0;
7868 /* Returns non-zero if X contains a SYMBOL_REF. */
7871 symbolic_expression_p (x
)
7874 if (GET_CODE (x
) == SYMBOL_REF
)
7877 if (GET_CODE (x
) == CONST
)
7878 return symbolic_expression_p (XEXP (x
, 0));
7880 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
7881 return symbolic_expression_p (XEXP (x
, 0));
7883 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
7884 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
7885 return (symbolic_expression_p (XEXP (x
, 0))
7886 || symbolic_expression_p (XEXP (x
, 1)));
7891 /* Choose the section to use for the constant rtx expression X that has
7895 mips_select_rtx_section (mode
, x
)
7896 enum machine_mode mode
;
7897 rtx x ATTRIBUTE_UNUSED
;
7901 /* In mips16 mode, the constant table always goes in the same section
7902 as the function, so that constants can be loaded using PC relative
7904 function_section (current_function_decl
);
7906 else if (TARGET_EMBEDDED_DATA
)
7908 /* For embedded applications, always put constants in read-only data,
7909 in order to reduce RAM usage. */
7910 READONLY_DATA_SECTION ();
7914 /* For hosted applications, always put constants in small data if
7915 possible, as this gives the best performance. */
7917 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
7918 && mips_section_threshold
> 0)
7919 SMALL_DATA_SECTION ();
7920 else if (flag_pic
&& symbolic_expression_p (x
))
7921 /* Any expression involving a SYMBOL_REF might need a run-time
7922 relocation. (The symbol might be defined in a shared
7923 library loaded at an unexpected base address.) So, we must
7924 put such expressions in the data segment (which is
7925 writable), rather than the text segment (which is
7929 READONLY_DATA_SECTION ();
7933 /* Choose the section to use for DECL. RELOC is true if its value contains
7934 any relocatable expression.
7936 Some of the logic used here needs to be replicated in
7937 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7938 are done correctly. Specifically, at least all symbols assigned
7939 here to rom (.text and/or .rodata) must not be referenced via
7940 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7942 If you need to make a change here, you probably should check
7943 ENCODE_SECTION_INFO to see if it needs a similar change. */
7946 mips_select_section (decl
, reloc
)
7950 int size
= int_size_in_bytes (TREE_TYPE (decl
));
7952 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
7953 && TREE_CODE (decl
) == STRING_CST
7954 && !flag_writable_strings
)
7955 /* For embedded position independent code, put constant strings in the
7956 text section, because the data section is limited to 64K in size.
7957 For mips16 code, put strings in the text section so that a PC
7958 relative load instruction can be used to get their address. */
7960 else if (TARGET_EMBEDDED_DATA
)
7962 /* For embedded applications, always put an object in read-only data
7963 if possible, in order to reduce RAM usage. */
7965 if (((TREE_CODE (decl
) == VAR_DECL
7966 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7967 && DECL_INITIAL (decl
)
7968 && (DECL_INITIAL (decl
) == error_mark_node
7969 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7970 /* Deal with calls from output_constant_def_contents. */
7971 || (TREE_CODE (decl
) != VAR_DECL
7972 && (TREE_CODE (decl
) != STRING_CST
7973 || !flag_writable_strings
)))
7974 && ! (flag_pic
&& reloc
))
7975 READONLY_DATA_SECTION ();
7976 else if (size
> 0 && size
<= mips_section_threshold
)
7977 SMALL_DATA_SECTION ();
7983 /* For hosted applications, always put an object in small data if
7984 possible, as this gives the best performance. */
7986 if (size
> 0 && size
<= mips_section_threshold
)
7987 SMALL_DATA_SECTION ();
7988 else if (((TREE_CODE (decl
) == VAR_DECL
7989 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7990 && DECL_INITIAL (decl
)
7991 && (DECL_INITIAL (decl
) == error_mark_node
7992 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7993 /* Deal with calls from output_constant_def_contents. */
7994 || (TREE_CODE (decl
) != VAR_DECL
7995 && (TREE_CODE (decl
) != STRING_CST
7996 || !flag_writable_strings
)))
7997 && ! (flag_pic
&& reloc
))
7998 READONLY_DATA_SECTION ();
8004 /* Return register to use for a function return value with VALTYPE for
8005 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8008 mips_function_value (valtype
, func
, mode
)
8010 tree func ATTRIBUTE_UNUSED
;
8011 enum machine_mode mode
;
8013 int reg
= GP_RETURN
;
8014 enum mode_class mclass
;
8019 mode
= TYPE_MODE (valtype
);
8020 unsignedp
= TREE_UNSIGNED (valtype
);
8022 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8023 the mode just as PROMOTE_MODE does. */
8024 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
8026 mclass
= GET_MODE_CLASS (mode
);
8028 if (mclass
== MODE_FLOAT
&& GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
8031 else if (mclass
== MODE_COMPLEX_FLOAT
8032 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
* 2)
8034 enum machine_mode cmode
= GET_MODE_INNER (mode
);
8036 return gen_rtx_PARALLEL
8039 gen_rtx_EXPR_LIST (VOIDmode
,
8040 gen_rtx_REG (cmode
, FP_RETURN
),
8042 gen_rtx_EXPR_LIST (VOIDmode
,
8043 gen_rtx_REG (cmode
, FP_RETURN
+ FP_INC
),
8044 GEN_INT (GET_MODE_SIZE (cmode
)))));
8047 else if (valtype
&& TREE_CODE (valtype
) == RECORD_TYPE
8048 && mips_abi
!= ABI_32
8049 && mips_abi
!= ABI_O64
8050 && mips_abi
!= ABI_EABI
)
8052 /* A struct with only one or two floating point fields is returned in
8053 the floating point registers. */
8054 tree field
, fields
[2];
8057 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
8058 field
= TREE_CHAIN (field
))
8060 if (TREE_CODE (field
) != FIELD_DECL
)
8063 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
8066 fields
[i
++] = field
;
8069 /* Must check i, so that we reject structures with no elements. */
8074 /* The structure has DImode, but we don't allow DImode values
8075 in FP registers, so we use a PARALLEL even though it isn't
8076 strictly necessary. */
8077 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
8079 return gen_rtx_PARALLEL
8082 gen_rtx_EXPR_LIST (VOIDmode
,
8083 gen_rtx_REG (field_mode
,
8090 enum machine_mode first_mode
8091 = TYPE_MODE (TREE_TYPE (fields
[0]));
8092 enum machine_mode second_mode
8093 = TYPE_MODE (TREE_TYPE (fields
[1]));
8094 HOST_WIDE_INT first_offset
= int_byte_position (fields
[0]);
8095 HOST_WIDE_INT second_offset
= int_byte_position (fields
[1]);
8097 return gen_rtx_PARALLEL
8100 gen_rtx_EXPR_LIST (VOIDmode
,
8101 gen_rtx_REG (first_mode
,
8103 GEN_INT (first_offset
)),
8104 gen_rtx_EXPR_LIST (VOIDmode
,
8105 gen_rtx_REG (second_mode
,
8107 GEN_INT (second_offset
))));
8112 return gen_rtx_REG (mode
, reg
);
8115 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8116 nonzero when an argument must be passed by reference. */
8119 function_arg_pass_by_reference (cum
, mode
, type
, named
)
8120 const CUMULATIVE_ARGS
*cum
;
8121 enum machine_mode mode
;
8123 int named ATTRIBUTE_UNUSED
;
8127 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
8130 /* We must pass by reference if we would be both passing in registers
8131 and the stack. This is because any subsequent partial arg would be
8132 handled incorrectly in this case.
8134 ??? This is really a kludge. We should either fix GCC so that such
8135 a situation causes an abort and then do something in the MIPS port
8136 to prevent it, or add code to function.c to properly handle the case. */
8137 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8138 here hopefully is not relevant to mips_va_arg. */
8139 if (cum
&& MUST_PASS_IN_STACK (mode
, type
)
8140 && mips_abi
!= ABI_MEABI
8141 && FUNCTION_ARG (*cum
, mode
, type
, named
) != 0)
8144 /* Otherwise, we only do this if EABI is selected. */
8145 if (mips_abi
!= ABI_EABI
)
8148 /* ??? How should SCmode be handled? */
8149 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
8152 size
= int_size_in_bytes (type
);
8153 return size
== -1 || size
> UNITS_PER_WORD
;
8156 /* This function returns the register class required for a secondary
8157 register when copying between one of the registers in CLASS, and X,
8158 using MODE. If IN_P is nonzero, the copy is going from X to the
8159 register, otherwise the register is the source. A return value of
8160 NO_REGS means that no secondary register is required. */
8163 mips_secondary_reload_class (class, mode
, x
, in_p
)
8164 enum reg_class
class;
8165 enum machine_mode mode
;
8169 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
8173 if (GET_CODE (x
) == SIGN_EXTEND
)
8179 /* We may be called with reg_renumber NULL from regclass.
8180 ??? This is probably a bug. */
8182 regno
= true_regnum (x
);
8185 while (GET_CODE (x
) == SUBREG
)
8187 off
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
8188 GET_MODE (SUBREG_REG (x
)),
8194 if (GET_CODE (x
) == REG
)
8195 regno
= REGNO (x
) + off
;
8199 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
8200 regno
= true_regnum (x
);
8202 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
8204 /* We always require a general register when copying anything to
8205 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8206 to a general register, or when copying from register 0. */
8207 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
8210 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8211 ? NO_REGS
: gr_regs
);
8212 else if (regno
== HILO_REGNUM
)
8215 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8216 ? NO_REGS
: gr_regs
);
8218 /* Copying from HI or LO to anywhere other than a general register
8219 requires a general register. */
8220 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
8222 if (TARGET_MIPS16
&& in_p
)
8224 /* We can't really copy to HI or LO at all in mips16 mode. */
8227 return gp_reg_p
? NO_REGS
: gr_regs
;
8229 if (MD_REG_P (regno
))
8231 if (TARGET_MIPS16
&& ! in_p
)
8233 /* We can't really copy to HI or LO at all in mips16 mode. */
8236 return class == gr_regs
? NO_REGS
: gr_regs
;
8239 /* We can only copy a value to a condition code register from a
8240 floating point register, and even then we require a scratch
8241 floating point register. We can only copy a value out of a
8242 condition code register into a general register. */
8243 if (class == ST_REGS
)
8247 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8249 if (ST_REG_P (regno
))
8253 return class == GR_REGS
? NO_REGS
: GR_REGS
;
8256 /* In mips16 mode, going between memory and anything but M16_REGS
8257 requires an M16_REG. */
8260 if (class != M16_REGS
&& class != M16_NA_REGS
)
8268 /* The stack pointer isn't a valid operand to an add instruction,
8269 so we need to load it into M16_REGS first. This can happen as
8270 a result of register elimination and form_sum converting
8271 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8272 need an extra register if the dest is the same as the other
8273 register. In that case, we can't fix the problem by loading SP
8274 into the dest first. */
8275 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
8276 && GET_CODE (XEXP (x
, 1)) == REG
8277 && (XEXP (x
, 0) == stack_pointer_rtx
8278 || XEXP (x
, 1) == stack_pointer_rtx
))
8279 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
8281 if (class == M16_REGS
|| class == M16_NA_REGS
)
8290 /* This function returns the maximum number of consecutive registers
8291 needed to represent mode MODE in registers of class CLASS. */
8294 mips_class_max_nregs (class, mode
)
8295 enum reg_class
class;
8296 enum machine_mode mode
;
8298 if (class == FP_REGS
)
8301 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8304 /* For each mips16 function which refers to GP relative symbols, we
8305 use a pseudo register, initialized at the start of the function, to
8306 hold the $gp value. */
8309 mips16_gp_pseudo_reg ()
8311 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
8316 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
8317 RTX_UNCHANGING_P (cfun
->machine
->mips16_gp_pseudo_rtx
) = 1;
8319 /* We want to initialize this to a value which gcc will believe
8321 const_gp
= gen_rtx (CONST
, Pmode
,
8322 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
8325 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
8327 insn
= gen_sequence ();
8330 push_topmost_sequence ();
8331 /* We need to emit the initialization after the FUNCTION_BEG
8332 note, so that it will be integrated. */
8333 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
8334 if (GET_CODE (scan
) == NOTE
8335 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
8337 if (scan
== NULL_RTX
)
8338 scan
= get_insns ();
8339 insn
= emit_insn_after (insn
, scan
);
8340 pop_topmost_sequence ();
8343 return cfun
->machine
->mips16_gp_pseudo_rtx
;
8346 /* Return an RTX which represents the signed 16 bit offset from the
8347 $gp register for the given symbol. This is only used on the
8351 mips16_gp_offset (sym
)
8356 if (GET_CODE (sym
) != SYMBOL_REF
8357 || ! SYMBOL_REF_FLAG (sym
))
8360 /* We use a special identifier to represent the value of the gp
8362 gp
= get_identifier ("__mips16_gp_value");
8364 return gen_rtx (CONST
, Pmode
,
8365 gen_rtx (MINUS
, Pmode
, sym
,
8366 gen_rtx (SYMBOL_REF
, Pmode
,
8367 IDENTIFIER_POINTER (gp
))));
8370 /* Return nonzero if the given RTX represents a signed 16 bit offset
8371 from the $gp register. */
8374 mips16_gp_offset_p (x
)
8377 if (GET_CODE (x
) == CONST
)
8380 /* It's OK to add a small integer value to a gp offset. */
8381 if (GET_CODE (x
) == PLUS
)
8383 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8384 && SMALL_INT (XEXP (x
, 1)))
8385 return mips16_gp_offset_p (XEXP (x
, 0));
8386 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
8387 && SMALL_INT (XEXP (x
, 0)))
8388 return mips16_gp_offset_p (XEXP (x
, 1));
8392 /* Make sure it is in the form SYM - __mips16_gp_value. */
8393 return (GET_CODE (x
) == MINUS
8394 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
8395 && SYMBOL_REF_FLAG (XEXP (x
, 0))
8396 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8397 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
8400 /* Output a GP offset. We don't want to print the subtraction of
8401 __mips16_gp_value; it is implicitly represented by the %gprel which
8402 should have been printed by the caller. */
8405 mips16_output_gp_offset (file
, x
)
8409 if (GET_CODE (x
) == CONST
)
8412 if (GET_CODE (x
) == PLUS
)
8414 mips16_output_gp_offset (file
, XEXP (x
, 0));
8416 mips16_output_gp_offset (file
, XEXP (x
, 1));
8420 if (GET_CODE (x
) == MINUS
8421 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8422 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
8424 mips16_output_gp_offset (file
, XEXP (x
, 0));
8428 output_addr_const (file
, x
);
8431 /* Return nonzero if a constant should not be output until after the
8432 function. This is true of most string constants, so that we can
8433 use a more efficient PC relative reference. However, a static
8434 inline function may never call assemble_function_end to write out
8435 the constant pool, so don't try to postpone the constant in that
8438 ??? It's really a bug that a static inline function can put stuff
8439 in the constant pool even if the function itself is not output.
8441 We record which string constants we've seen, so that we know which
8442 ones might use the more efficient reference. */
8445 mips16_constant_after_function_p (x
)
8448 if (TREE_CODE (x
) == STRING_CST
8449 && ! flag_writable_strings
8450 && current_function_decl
!= 0
8451 && ! DECL_DEFER_OUTPUT (current_function_decl
)
8452 && ! (DECL_INLINE (current_function_decl
)
8453 && ((! TREE_PUBLIC (current_function_decl
)
8454 && ! TREE_ADDRESSABLE (current_function_decl
)
8455 && ! flag_keep_inline_functions
)
8456 || DECL_EXTERNAL (current_function_decl
))))
8458 struct string_constant
*n
;
8460 n
= (struct string_constant
*) xmalloc (sizeof *n
);
8461 n
->label
= XSTR (XEXP (TREE_CST_RTL (x
), 0), 0);
8462 n
->next
= string_constants
;
8463 string_constants
= n
;
8471 /* Validate a constant for the mips16. This rejects general symbolic
8472 addresses, which must be loaded from memory. If ADDR is nonzero,
8473 this should reject anything which is not a legal address. If
8474 ADDEND is nonzero, this is being added to something else. */
8477 mips16_constant (x
, mode
, addr
, addend
)
8479 enum machine_mode mode
;
8483 while (GET_CODE (x
) == CONST
)
8486 switch (GET_CODE (x
))
8492 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
8493 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
8496 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8498 if (CONSTANT_POOL_ADDRESS_P (x
))
8501 /* If we aren't looking for a memory address, we can accept a GP
8502 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8503 knows how to handle this. We can always accept a string
8504 constant, which is the other case in which SYMBOL_REF_FLAG
8508 && SYMBOL_REF_FLAG (x
)
8509 && mode
== (enum machine_mode
) Pmode
)
8512 /* We can accept a string constant, which will have
8513 SYMBOL_REF_FLAG set but must be recognized by name to
8514 distinguish from a GP accessible symbol. The name of a
8515 string constant will have been generated by
8516 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8517 if (SYMBOL_REF_FLAG (x
))
8519 const char *name
= XSTR (x
, 0);
8521 return (name
[0] == '*'
8522 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
8523 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
8529 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8534 if (addr
&& ! addend
)
8536 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
8539 /* We need to treat $gp as a legitimate constant, because
8540 mips16_gp_pseudo_reg assumes that. */
8541 return REGNO (x
) == GP_REG_FIRST
+ 28;
8545 /* Write out code to move floating point arguments in or out of
8546 general registers. Output the instructions to FILE. FP_CODE is
8547 the code describing which arguments are present (see the comment at
8548 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8549 we are copying from the floating point registers. */
8552 mips16_fp_args (file
, fp_code
, from_fp_p
)
8561 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8562 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8569 gparg
= GP_ARG_FIRST
;
8570 fparg
= FP_ARG_FIRST
;
8571 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8575 if ((fparg
& 1) != 0)
8577 fprintf (file
, "\t%s\t%s,%s\n", s
,
8578 reg_names
[gparg
], reg_names
[fparg
]);
8580 else if ((f
& 3) == 2)
8583 fprintf (file
, "\td%s\t%s,%s\n", s
,
8584 reg_names
[gparg
], reg_names
[fparg
]);
8587 if ((fparg
& 1) != 0)
8589 if (TARGET_BIG_ENDIAN
)
8590 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8591 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
8592 reg_names
[gparg
+ 1], reg_names
[fparg
]);
8594 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8595 reg_names
[gparg
], reg_names
[fparg
], s
,
8596 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
8609 /* Build a mips16 function stub. This is used for functions which
8610 take aruments in the floating point registers. It is 32 bit code
8611 that moves the floating point args into the general registers, and
8612 then jumps to the 16 bit code. */
8615 build_mips16_function_stub (file
)
8619 char *secname
, *stubname
;
8620 tree stubid
, stubdecl
;
8624 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8625 secname
= (char *) alloca (strlen (fnname
) + 20);
8626 sprintf (secname
, ".mips16.fn.%s", fnname
);
8627 stubname
= (char *) alloca (strlen (fnname
) + 20);
8628 sprintf (stubname
, "__fn_stub_%s", fnname
);
8629 stubid
= get_identifier (stubname
);
8630 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8631 build_function_type (void_type_node
, NULL_TREE
));
8632 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8634 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
8636 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
8638 fprintf (file
, "%s%s",
8639 need_comma
? ", " : "",
8640 (f
& 3) == 1 ? "float" : "double");
8643 fprintf (file
, ")\n");
8645 fprintf (file
, "\t.set\tnomips16\n");
8646 function_section (stubdecl
);
8647 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
8649 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8650 within a .ent, and we can not emit another .ent. */
8651 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8652 fputs ("\t.ent\t", file
);
8653 assemble_name (file
, stubname
);
8657 assemble_name (file
, stubname
);
8658 fputs (":\n", file
);
8660 /* We don't want the assembler to insert any nops here. */
8661 fprintf (file
, "\t.set\tnoreorder\n");
8663 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
8665 fprintf (asm_out_file
, "\t.set\tnoat\n");
8666 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
8667 assemble_name (file
, fnname
);
8668 fprintf (file
, "\n");
8669 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8670 fprintf (asm_out_file
, "\t.set\tat\n");
8672 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8673 with one of the mfc1 instructions, because the result is not
8674 available for one instruction, so if the very first instruction
8675 in the function refers to the register, it will see the wrong
8677 fprintf (file
, "\tnop\n");
8679 fprintf (file
, "\t.set\treorder\n");
8681 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8682 fputs ("\t.end\t", file
);
8683 assemble_name (file
, stubname
);
8687 fprintf (file
, "\t.set\tmips16\n");
8689 function_section (current_function_decl
);
8692 /* We keep a list of functions for which we have already built stubs
8693 in build_mips16_call_stub. */
8697 struct mips16_stub
*next
;
8702 static struct mips16_stub
*mips16_stubs
;
8704 /* Build a call stub for a mips16 call. A stub is needed if we are
8705 passing any floating point values which should go into the floating
8706 point registers. If we are, and the call turns out to be to a 32
8707 bit function, the stub will be used to move the values into the
8708 floating point registers before calling the 32 bit function. The
8709 linker will magically adjust the function call to either the 16 bit
8710 function or the 32 bit stub, depending upon where the function call
8711 is actually defined.
8713 Similarly, we need a stub if the return value might come back in a
8714 floating point register.
8716 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8717 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8718 is the code built by function_arg. This function returns a nonzero
8719 value if it builds the call instruction itself. */
8722 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
8731 char *secname
, *stubname
;
8732 struct mips16_stub
*l
;
8733 tree stubid
, stubdecl
;
8737 /* We don't need to do anything if we aren't in mips16 mode, or if
8738 we were invoked with the -msoft-float option. */
8739 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8742 /* Figure out whether the value might come back in a floating point
8744 fpret
= (retval
!= 0
8745 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8746 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
8748 /* We don't need to do anything if there were no floating point
8749 arguments and the value will not be returned in a floating point
8751 if (fp_code
== 0 && ! fpret
)
8754 if (GET_CODE (fnmem
) != MEM
)
8756 fn
= XEXP (fnmem
, 0);
8758 /* We don't need to do anything if this is a call to a special
8759 mips16 support function. */
8760 if (GET_CODE (fn
) == SYMBOL_REF
8761 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8764 /* This code will only work for o32 and o64 abis. The other ABI's
8765 require more sophisticated support. */
8766 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8769 /* We can only handle SFmode and DFmode floating point return
8771 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
8774 /* If we're calling via a function pointer, then we must always call
8775 via a stub. There are magic stubs provided in libgcc.a for each
8776 of the required cases. Each of them expects the function address
8777 to arrive in register $2. */
8779 if (GET_CODE (fn
) != SYMBOL_REF
)
8783 rtx stub_fn
, stub_mem
, insn
;
8785 /* ??? If this code is modified to support other ABI's, we need
8786 to handle PARALLEL return values here. */
8788 sprintf (buf
, "__mips16_call_stub_%s%d",
8790 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
8793 id
= get_identifier (buf
);
8794 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
8795 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
8797 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
8799 if (retval
== NULL_RTX
)
8800 insn
= gen_call_internal0 (stub_mem
, arg_size
,
8801 gen_rtx (REG
, SImode
,
8802 GP_REG_FIRST
+ 31));
8804 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
8805 gen_rtx (REG
, SImode
,
8806 GP_REG_FIRST
+ 31));
8807 insn
= emit_call_insn (insn
);
8809 /* Put the register usage information on the CALL. */
8810 if (GET_CODE (insn
) != CALL_INSN
)
8812 CALL_INSN_FUNCTION_USAGE (insn
) =
8813 gen_rtx (EXPR_LIST
, VOIDmode
,
8814 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
8815 CALL_INSN_FUNCTION_USAGE (insn
));
8817 /* If we are handling a floating point return value, we need to
8818 save $18 in the function prologue. Putting a note on the
8819 call will mean that regs_ever_live[$18] will be true if the
8820 call is not eliminated, and we can check that in the prologue
8823 CALL_INSN_FUNCTION_USAGE (insn
) =
8824 gen_rtx (EXPR_LIST
, VOIDmode
,
8825 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8826 CALL_INSN_FUNCTION_USAGE (insn
));
8828 /* Return 1 to tell the caller that we've generated the call
8833 /* We know the function we are going to call. If we have already
8834 built a stub, we don't need to do anything further. */
8836 fnname
= XSTR (fn
, 0);
8837 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8838 if (strcmp (l
->name
, fnname
) == 0)
8843 /* Build a special purpose stub. When the linker sees a
8844 function call in mips16 code, it will check where the target
8845 is defined. If the target is a 32 bit call, the linker will
8846 search for the section defined here. It can tell which
8847 symbol this section is associated with by looking at the
8848 relocation information (the name is unreliable, since this
8849 might be a static function). If such a section is found, the
8850 linker will redirect the call to the start of the magic
8853 If the function does not return a floating point value, the
8854 special stub section is named
8857 If the function does return a floating point value, the stub
8859 .mips16.call.fp.FNNAME
8862 secname
= (char *) alloca (strlen (fnname
) + 40);
8863 sprintf (secname
, ".mips16.call.%s%s",
8866 stubname
= (char *) alloca (strlen (fnname
) + 20);
8867 sprintf (stubname
, "__call_stub_%s%s",
8870 stubid
= get_identifier (stubname
);
8871 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8872 build_function_type (void_type_node
, NULL_TREE
));
8873 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8875 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8877 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8881 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8883 fprintf (asm_out_file
, "%s%s",
8884 need_comma
? ", " : "",
8885 (f
& 3) == 1 ? "float" : "double");
8888 fprintf (asm_out_file
, ")\n");
8890 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8891 assemble_start_function (stubdecl
, stubname
);
8893 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8894 fputs ("\t.ent\t", asm_out_file
);
8895 assemble_name (asm_out_file
, stubname
);
8896 fputs ("\n", asm_out_file
);
8898 assemble_name (asm_out_file
, stubname
);
8899 fputs (":\n", asm_out_file
);
8902 /* We build the stub code by hand. That's the only way we can
8903 do it, since we can't generate 32 bit code during a 16 bit
8906 /* We don't want the assembler to insert any nops here. */
8907 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
8909 mips16_fp_args (asm_out_file
, fp_code
, 0);
8913 fprintf (asm_out_file
, "\t.set\tnoat\n");
8914 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
8916 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8917 fprintf (asm_out_file
, "\t.set\tat\n");
8918 /* Unfortunately, we can't fill the jump delay slot. We
8919 can't fill with one of the mtc1 instructions, because the
8920 result is not available for one instruction, so if the
8921 very first instruction in the function refers to the
8922 register, it will see the wrong value. */
8923 fprintf (asm_out_file
, "\tnop\n");
8927 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
8928 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
8929 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
8930 /* As above, we can't fill the delay slot. */
8931 fprintf (asm_out_file
, "\tnop\n");
8932 if (GET_MODE (retval
) == SFmode
)
8933 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8934 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
8937 if (TARGET_BIG_ENDIAN
)
8939 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8940 reg_names
[GP_REG_FIRST
+ 2],
8941 reg_names
[FP_REG_FIRST
+ 1]);
8942 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8943 reg_names
[GP_REG_FIRST
+ 3],
8944 reg_names
[FP_REG_FIRST
+ 0]);
8948 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8949 reg_names
[GP_REG_FIRST
+ 2],
8950 reg_names
[FP_REG_FIRST
+ 0]);
8951 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8952 reg_names
[GP_REG_FIRST
+ 3],
8953 reg_names
[FP_REG_FIRST
+ 1]);
8956 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
8957 /* As above, we can't fill the delay slot. */
8958 fprintf (asm_out_file
, "\tnop\n");
8961 fprintf (asm_out_file
, "\t.set\treorder\n");
8963 #ifdef ASM_DECLARE_FUNCTION_SIZE
8964 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
8967 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8968 fputs ("\t.end\t", asm_out_file
);
8969 assemble_name (asm_out_file
, stubname
);
8970 fputs ("\n", asm_out_file
);
8973 fprintf (asm_out_file
, "\t.set\tmips16\n");
8975 /* Record this stub. */
8976 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
8977 l
->name
= xstrdup (fnname
);
8979 l
->next
= mips16_stubs
;
8983 /* If we expect a floating point return value, but we've built a
8984 stub which does not expect one, then we're in trouble. We can't
8985 use the existing stub, because it won't handle the floating point
8986 value. We can't build a new stub, because the linker won't know
8987 which stub to use for the various calls in this object file.
8988 Fortunately, this case is illegal, since it means that a function
8989 was declared in two different ways in a single compilation. */
8990 if (fpret
&& ! l
->fpret
)
8991 error ("can not handle inconsistent calls to `%s'", fnname
);
8993 /* If we are calling a stub which handles a floating point return
8994 value, we need to arrange to save $18 in the prologue. We do
8995 this by marking the function call as using the register. The
8996 prologue will later see that it is used, and emit code to save
9003 if (retval
== NULL_RTX
)
9004 insn
= gen_call_internal0 (fnmem
, arg_size
,
9005 gen_rtx (REG
, SImode
,
9006 GP_REG_FIRST
+ 31));
9008 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
9009 gen_rtx (REG
, SImode
,
9010 GP_REG_FIRST
+ 31));
9011 insn
= emit_call_insn (insn
);
9013 if (GET_CODE (insn
) != CALL_INSN
)
9016 CALL_INSN_FUNCTION_USAGE (insn
) =
9017 gen_rtx (EXPR_LIST
, VOIDmode
,
9018 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9019 CALL_INSN_FUNCTION_USAGE (insn
));
9021 /* Return 1 to tell the caller that we've generated the call
9026 /* Return 0 to let the caller generate the call insn. */
9030 /* This function looks through the code for a function, and tries to
9031 optimize the usage of the $gp register. We arrange to copy $gp
9032 into a pseudo-register, and then let gcc's normal reload handling
9033 deal with the pseudo-register. Unfortunately, if reload choose to
9034 put the pseudo-register into a call-clobbered register, it will
9035 emit saves and restores for that register around any function
9036 calls. We don't need the saves, and it's faster to copy $gp than
9037 to do an actual restore. ??? This still means that we waste a
9040 This is an optimization, and the code which gcc has actually
9041 generated is correct, so we do not need to catch all cases. */
9044 mips16_optimize_gp (first
)
9047 rtx gpcopy
, slot
, insn
;
9049 /* Look through the instructions. Set GPCOPY to the register which
9050 holds a copy of $gp. Set SLOT to the stack slot where it is
9051 saved. If we find an instruction which sets GPCOPY to anything
9052 other than $gp or SLOT, then we can't use it. If we find an
9053 instruction which sets SLOT to anything other than GPCOPY, we
9058 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9062 if (! INSN_P (insn
))
9065 set
= PATTERN (insn
);
9067 /* We know that all references to memory will be inside a SET,
9068 because there is no other way to access memory on the mips16.
9069 We don't have to worry about a PARALLEL here, because the
9070 mips.md file will never generate them for memory references. */
9071 if (GET_CODE (set
) != SET
)
9074 if (gpcopy
== NULL_RTX
9075 && GET_CODE (SET_SRC (set
)) == CONST
9076 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
9077 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
9078 && GET_CODE (SET_DEST (set
)) == REG
9079 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9080 gpcopy
= SET_DEST (set
);
9081 else if (slot
== NULL_RTX
9082 && gpcopy
!= NULL_RTX
9083 && GET_CODE (SET_DEST (set
)) == MEM
9084 && GET_CODE (SET_SRC (set
)) == REG
9085 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
9086 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9090 offset
= const0_rtx
;
9091 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9092 if (GET_CODE (base
) == REG
9093 && (REGNO (base
) == STACK_POINTER_REGNUM
9094 || REGNO (base
) == FRAME_POINTER_REGNUM
))
9095 slot
= SET_DEST (set
);
9097 else if (gpcopy
!= NULL_RTX
9098 && (GET_CODE (SET_DEST (set
)) == REG
9099 || GET_CODE (SET_DEST (set
)) == SUBREG
)
9100 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
9101 && (GET_CODE (SET_DEST (set
)) != REG
9102 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
9103 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
9104 || ((GET_CODE (SET_SRC (set
)) != CONST
9105 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
9106 || (REGNO (XEXP (SET_SRC (set
), 0))
9107 != GP_REG_FIRST
+ 28))
9108 && ! rtx_equal_p (SET_SRC (set
), slot
))))
9110 else if (slot
!= NULL_RTX
9111 && GET_CODE (SET_DEST (set
)) == MEM
9112 && rtx_equal_p (SET_DEST (set
), slot
)
9113 && (GET_CODE (SET_SRC (set
)) != REG
9114 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
9118 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9119 different optimization. Any time we find a copy of $28 into a
9120 register, followed by an add of a symbol_ref to that register, we
9121 convert it to load the value from the constant table instead.
9122 The copy and add will take six bytes, just as the load and
9123 constant table entry will take six bytes. However, it is
9124 possible that the constant table entry will be shared.
9126 This could be a peephole optimization, but I don't know if the
9127 peephole code can call force_const_mem.
9129 Using the same register for the copy of $28 and the add of the
9130 symbol_ref is actually pretty likely, since the add instruction
9131 requires the destination and the first addend to be the same
9134 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
9138 /* This optimization is only reasonable if the constant table
9139 entries are only 4 bytes. */
9140 if (Pmode
!= SImode
)
9143 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
9150 next
= NEXT_INSN (next
);
9152 while (next
!= NULL_RTX
9153 && (GET_CODE (next
) == NOTE
9154 || (GET_CODE (next
) == INSN
9155 && (GET_CODE (PATTERN (next
)) == USE
9156 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
9158 if (next
== NULL_RTX
)
9161 if (! INSN_P (insn
))
9164 if (! INSN_P (next
))
9167 set1
= PATTERN (insn
);
9168 if (GET_CODE (set1
) != SET
)
9170 set2
= PATTERN (next
);
9171 if (GET_CODE (set2
) != SET
)
9174 if (GET_CODE (SET_DEST (set1
)) == REG
9175 && GET_CODE (SET_SRC (set1
)) == CONST
9176 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
9177 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
9178 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
9179 && GET_CODE (SET_SRC (set2
)) == PLUS
9180 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
9181 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
9182 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
9186 /* We've found a case we can change to load from the
9189 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
9190 if (GET_CODE (sym
) != SYMBOL_REF
)
9192 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
9193 force_const_mem (Pmode
, sym
)),
9196 PUT_CODE (insn
, NOTE
);
9197 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9198 NOTE_SOURCE_FILE (insn
) = 0;
9200 PUT_CODE (next
, NOTE
);
9201 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
9202 NOTE_SOURCE_FILE (next
) = 0;
9209 /* We can safely remove all assignments to SLOT from GPCOPY, and
9210 replace all assignments from SLOT to GPCOPY with assignments from
9213 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9217 if (! INSN_P (insn
))
9220 set
= PATTERN (insn
);
9221 if (GET_CODE (set
) != SET
9222 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
)
9225 if (GET_CODE (SET_DEST (set
)) == MEM
9226 && rtx_equal_p (SET_DEST (set
), slot
)
9227 && GET_CODE (SET_SRC (set
)) == REG
9228 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
9230 PUT_CODE (insn
, NOTE
);
9231 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9232 NOTE_SOURCE_FILE (insn
) = 0;
9234 else if (GET_CODE (SET_DEST (set
)) == REG
9235 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
9236 && GET_CODE (SET_SRC (set
)) == MEM
9237 && rtx_equal_p (SET_SRC (set
), slot
))
9239 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
9240 gen_rtx (CONST
, Pmode
,
9241 gen_rtx (REG
, Pmode
,
9242 GP_REG_FIRST
+ 28))),
9244 PUT_CODE (insn
, NOTE
);
9245 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9246 NOTE_SOURCE_FILE (insn
) = 0;
9251 /* We keep a list of constants we which we have to add to internal
9252 constant tables in the middle of large functions. */
9256 struct constant
*next
;
9259 enum machine_mode mode
;
9262 /* Add a constant to the list in *PCONSTANTS. */
9265 add_constant (pconstants
, val
, mode
)
9266 struct constant
**pconstants
;
9268 enum machine_mode mode
;
9272 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
9273 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
9276 c
= (struct constant
*) xmalloc (sizeof *c
);
9279 c
->label
= gen_label_rtx ();
9280 c
->next
= *pconstants
;
9285 /* Dump out the constants in CONSTANTS after INSN. */
9288 dump_constants (constants
, insn
)
9289 struct constant
*constants
;
9300 struct constant
*next
;
9302 switch (GET_MODE_SIZE (c
->mode
))
9309 insn
= emit_insn_after (gen_align_2 (), insn
);
9314 insn
= emit_insn_after (gen_align_4 (), insn
);
9319 insn
= emit_insn_after (gen_align_8 (), insn
);
9324 insn
= emit_label_after (c
->label
, insn
);
9329 r
= gen_consttable_qi (c
->value
);
9332 r
= gen_consttable_hi (c
->value
);
9335 r
= gen_consttable_si (c
->value
);
9338 r
= gen_consttable_sf (c
->value
);
9341 r
= gen_consttable_di (c
->value
);
9344 r
= gen_consttable_df (c
->value
);
9350 insn
= emit_insn_after (r
, insn
);
9357 emit_barrier_after (insn
);
9360 /* Find the symbol in an address expression. */
9363 mips_find_symbol (addr
)
9366 if (GET_CODE (addr
) == MEM
)
9367 addr
= XEXP (addr
, 0);
9368 while (GET_CODE (addr
) == CONST
)
9369 addr
= XEXP (addr
, 0);
9370 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
9372 if (GET_CODE (addr
) == PLUS
)
9376 l1
= mips_find_symbol (XEXP (addr
, 0));
9377 l2
= mips_find_symbol (XEXP (addr
, 1));
9378 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
9380 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
9386 /* Exported to toplev.c.
9388 Do a final pass over the function, just before delayed branch
9392 machine_dependent_reorg (first
)
9395 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
9397 struct constant
*constants
;
9399 if (! TARGET_MIPS16
)
9402 /* If $gp is used, try to remove stores, and replace loads with
9405 mips16_optimize_gp (first
);
9407 /* Scan the function looking for PC relative loads which may be out
9408 of range. All such loads will either be from the constant table,
9409 or be getting the address of a constant string. If the size of
9410 the function plus the size of the constant table is less than
9411 0x8000, then all loads are in range. */
9414 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9416 insns_len
+= get_attr_length (insn
);
9418 /* ??? We put switch tables in .text, but we don't define
9419 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9420 compute their lengths correctly. */
9421 if (GET_CODE (insn
) == JUMP_INSN
)
9425 body
= PATTERN (insn
);
9426 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9427 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9428 * GET_MODE_SIZE (GET_MODE (body
)));
9429 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9433 /* Store the original value of insns_len in current_frame_info, so
9434 that simple_memory_operand can look at it. */
9435 current_frame_info
.insns_len
= insns_len
;
9437 pool_size
= get_pool_size ();
9438 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
9441 /* Loop over the insns and figure out what the maximum internal pool
9443 max_internal_pool_size
= 0;
9444 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9446 if (GET_CODE (insn
) == INSN
9447 && GET_CODE (PATTERN (insn
)) == SET
)
9451 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9452 if (src
== NULL_RTX
)
9454 if (CONSTANT_POOL_ADDRESS_P (src
))
9455 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
9456 else if (SYMBOL_REF_FLAG (src
))
9457 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
9463 first_constant_ref
= -1;
9465 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9467 if (GET_CODE (insn
) == INSN
9468 && GET_CODE (PATTERN (insn
)) == SET
)
9471 enum machine_mode mode
= VOIDmode
;
9474 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9475 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
9477 /* ??? This is very conservative, which means that we
9478 will generate too many copies of the constant table.
9479 The only solution would seem to be some form of
9481 if (((insns_len
- addr
)
9482 + max_internal_pool_size
9483 + get_pool_offset (src
))
9486 val
= get_pool_constant (src
);
9487 mode
= get_pool_mode (src
);
9489 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
9491 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
9493 /* Including all of mips_string_length is conservative,
9494 and so is including all of max_internal_pool_size. */
9495 if (((insns_len
- addr
)
9496 + max_internal_pool_size
9498 + mips_string_length
)
9504 max_internal_pool_size
-= Pmode
;
9507 if (val
!= NULL_RTX
)
9511 /* This PC relative load is out of range. ??? In the
9512 case of a string constant, we are only guessing that
9513 it is range, since we don't know the offset of a
9514 particular string constant. */
9516 lab
= add_constant (&constants
, val
, mode
);
9517 newsrc
= gen_rtx (MEM
, mode
,
9518 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
9519 RTX_UNCHANGING_P (newsrc
) = 1;
9520 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
9521 SET_DEST (PATTERN (insn
)),
9523 INSN_CODE (insn
) = -1;
9525 if (first_constant_ref
< 0)
9526 first_constant_ref
= addr
;
9530 addr
+= get_attr_length (insn
);
9532 /* ??? We put switch tables in .text, but we don't define
9533 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9534 compute their lengths correctly. */
9535 if (GET_CODE (insn
) == JUMP_INSN
)
9539 body
= PATTERN (insn
);
9540 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9541 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9542 * GET_MODE_SIZE (GET_MODE (body
)));
9543 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9546 if (GET_CODE (insn
) == BARRIER
)
9548 /* Output any constants we have accumulated. Note that we
9549 don't need to change ADDR, since its only use is
9550 subtraction from INSNS_LEN, and both would be changed by
9552 ??? If the instructions up to the next barrier reuse a
9553 constant, it would often be better to continue
9555 if (constants
!= NULL
)
9556 dump_constants (constants
, insn
);
9558 first_constant_ref
= -1;
9561 if (constants
!= NULL
9562 && (NEXT_INSN (insn
) == NULL
9563 || (first_constant_ref
>= 0
9564 && (((addr
- first_constant_ref
)
9565 + 2 /* for alignment */
9566 + 2 /* for a short jump insn */
9570 /* If we haven't had a barrier within 0x8000 bytes of a
9571 constant reference or we are at the end of the function,
9572 emit a barrier now. */
9574 rtx label
, jump
, barrier
;
9576 label
= gen_label_rtx ();
9577 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
9578 JUMP_LABEL (jump
) = label
;
9579 LABEL_NUSES (label
) = 1;
9580 barrier
= emit_barrier_after (jump
);
9581 emit_label_after (label
, barrier
);
9582 first_constant_ref
= -1;
9586 /* ??? If we output all references to a constant in internal
9587 constants table, we don't need to output the constant in the real
9588 constant table, but we have no way to prevent that. */
9591 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9593 extend_operator (x
, mode
)
9595 enum machine_mode mode ATTRIBUTE_UNUSED
;
9597 enum rtx_code code
= GET_CODE (x
);
9598 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
9601 /* Accept any operator that can be used to shift the high half of the
9602 input value to the lower half, suitable for truncation. The
9603 remainder (the lower half of the input, and the upper half of the
9604 output) will be discarded. */
9606 highpart_shift_operator (x
, mode
)
9608 enum machine_mode mode ATTRIBUTE_UNUSED
;
9610 enum rtx_code code
= GET_CODE (x
);
9611 return (code
== LSHIFTRT
9617 /* Return a number assessing the cost of moving a register in class
9618 FROM to class TO. The classes are expressed using the enumeration
9619 values such as `GENERAL_REGS'. A value of 2 is the default; other
9620 values are interpreted relative to that.
9622 It is not required that the cost always equal 2 when FROM is the
9623 same as TO; on some machines it is expensive to move between
9624 registers if they are not general registers.
9626 If reload sees an insn consisting of a single `set' between two
9627 hard registers, and if `REGISTER_MOVE_COST' applied to their
9628 classes returns a value of 2, reload does not check to ensure that
9629 the constraints of the insn are met. Setting a cost of other than
9630 2 will allow reload to verify that the constraints are met. You
9631 should do this if the `movM' pattern's constraints do not allow
9634 ??? We make make the cost of moving from HI/LO/HILO/MD into general
9635 registers the same as for one of moving general registers to
9636 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
9637 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
9638 isn't clear if it is wise. And it might not work in all cases. We
9639 could solve the DImode LO reg problem by using a multiply, just
9640 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9641 problem by using divide instructions. divu puts the remainder in
9642 the HI reg, so doing a divide by -1 will move the value in the HI
9643 reg for all values except -1. We could handle that case by using a
9644 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9645 a compare/branch to test the input value to see which instruction
9646 we need to use. This gets pretty messy, but it is feasible. */
9649 mips_register_move_cost (mode
, to
, from
)
9650 enum machine_mode mode ATTRIBUTE_UNUSED
;
9651 enum reg_class to
, from
;
9653 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
9655 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
9657 else if (GR_REG_CLASS_P (from
))
9661 else if (to
== M16_NA_REGS
)
9663 else if (GR_REG_CLASS_P (to
))
9670 else if (to
== FP_REGS
)
9672 else if (to
== HI_REG
|| to
== LO_REG
|| to
== MD_REGS
9680 else if (COP_REG_CLASS_P (to
))
9684 } /* GR_REG_CLASS_P (from) */
9685 else if (from
== FP_REGS
)
9687 if (GR_REG_CLASS_P (to
))
9689 else if (to
== FP_REGS
)
9691 else if (to
== ST_REGS
)
9693 } /* from == FP_REGS */
9694 else if (from
== HI_REG
|| from
== LO_REG
|| from
== MD_REGS
9695 || from
== HILO_REG
)
9697 if (GR_REG_CLASS_P (to
))
9704 } /* from == HI_REG, etc. */
9705 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
9707 else if (COP_REG_CLASS_P (from
))
9710 } /* COP_REG_CLASS_P (from) */
9717 /* Return the length of INSN. LENGTH is the initial length computed by
9718 attributes in the machine-description file. */
9721 mips_adjust_insn_length (insn
, length
)
9725 /* A unconditional jump has an unfilled delay slot if it is not part
9726 of a sequence. A conditional jump normally has a delay slot, but
9727 does not on MIPS16. */
9728 if (simplejump_p (insn
)
9729 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
9730 || GET_CODE (insn
) == CALL_INSN
)))
9733 /* All MIPS16 instructions are a measly two bytes. */
9740 /* Output assembly instructions to peform a conditional branch.
9742 INSN is the branch instruction. OPERANDS[0] is the condition.
9743 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9744 of the first operand to the condition. If TWO_OPERANDS_P is
9745 non-zero the comparison takes two operands; OPERANDS[3] will be the
9748 If INVERTED_P is non-zero we are to branch if the condition does
9749 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9751 LENGTH is the length (in bytes) of the sequence we are to generate.
9752 That tells us whether to generate a simple conditional branch, or a
9753 reversed conditional branch around a `jr' instruction. */
9755 mips_output_conditional_branch (insn
,
9768 static char buffer
[200];
9769 /* The kind of comparison we are doing. */
9770 enum rtx_code code
= GET_CODE (operands
[0]);
9771 /* Non-zero if the opcode for the comparison needs a `z' indicating
9772 that it is a comparision against zero. */
9774 /* A string to use in the assembly output to represent the first
9776 const char *op1
= "%z2";
9777 /* A string to use in the assembly output to represent the second
9778 operand. Use the hard-wired zero register if there's no second
9780 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
9781 /* The operand-printing string for the comparison. */
9782 const char *const comp
= (float_p
? "%F0" : "%C0");
9783 /* The operand-printing string for the inverted comparison. */
9784 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
9786 /* The MIPS processors (for levels of the ISA at least two), have
9787 "likely" variants of each branch instruction. These instructions
9788 annul the instruction in the delay slot if the branch is not
9790 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9792 if (!two_operands_p
)
9794 /* To compute whether than A > B, for example, we normally
9795 subtract B from A and then look at the sign bit. But, if we
9796 are doing an unsigned comparison, and B is zero, we don't
9797 have to do the subtraction. Instead, we can just check to
9798 see if A is non-zero. Thus, we change the CODE here to
9799 reflect the simpler comparison operation. */
9811 /* A condition which will always be true. */
9817 /* A condition which will always be false. */
9823 /* Not a special case. */
9828 /* Relative comparisons are always done against zero. But
9829 equality comparisons are done between two operands, and therefore
9830 do not require a `z' in the assembly language output. */
9831 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
9832 /* For comparisons against zero, the zero is not provided
9837 /* Begin by terminating the buffer. That way we can always use
9838 strcat to add to it. */
9845 /* Just a simple conditional branch. */
9847 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
9848 inverted_p
? inverted_comp
: comp
);
9850 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
9851 inverted_p
? inverted_comp
: comp
,
9852 need_z_p
? "z" : "",
9860 /* Generate a reversed conditional branch around ` j'
9875 rtx target
= gen_label_rtx ();
9877 output_asm_insn ("%(%<", 0);
9878 orig_target
= operands
[1];
9879 operands
[1] = target
;
9880 /* Generate the reversed comparison. This takes four
9883 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
9884 inverted_p
? comp
: inverted_comp
);
9886 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
9887 inverted_p
? comp
: inverted_comp
,
9888 need_z_p
? "z" : "",
9891 output_asm_insn (buffer
, operands
);
9892 operands
[1] = orig_target
;
9894 output_asm_insn ("nop\n\tj\t%1", operands
);
9897 output_asm_insn ("nop", 0);
9900 /* Output delay slot instruction. */
9901 rtx insn
= final_sequence
;
9902 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
9904 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
9906 output_asm_insn ("%>%)", 0);
9907 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
9908 CODE_LABEL_NUMBER (target
));
9912 /* We do not currently use this code. It handles jumps to
9913 arbitrary locations, using `jr', even across a 256MB boundary.
9914 We could add a -mhuge switch, and then use this code instead of
9915 the `j' alternative above when -mhuge was used. */
9920 /* Generate a reversed conditional branch around a `jr'
9934 Not pretty, but allows a conditional branch anywhere in the
9935 32-bit address space. If the original branch is annulled,
9936 then the instruction in the delay slot should be executed
9937 only if the branch is taken. The la instruction is really
9938 a macro which will usually take eight bytes, but sometimes
9939 takes only four, if the instruction to which we're jumping
9940 gets its own entry in the global pointer table, which will
9941 happen if its a case label. The assembler will then
9942 generate only a four-byte sequence, rather than eight, and
9943 there seems to be no way to tell it not to. Thus, we can't
9944 just use a `.+x' addressing form; we don't know what value
9947 So, we resort to using the explicit relocation syntax
9948 available in the assembler and do:
9950 lw $at,%got_page(target)($gp)
9951 daddiu $at,$at,%got_ofst(target)
9953 That way, this always takes up eight bytes, and we can use
9954 the `.+x' form. Of course, these explicit machinations
9955 with relocation will not work with old assemblers. Then
9956 again, neither do out-of-range branches, so we haven't lost
9959 /* The target of the reversed branch. */
9960 const char *const target
9961 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
9962 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
9963 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
9966 strcpy (buffer
, "%(%<%[");
9967 c
= strchr (buffer
, '\0');
9968 /* Generate the reversed comparision. This takes four
9971 sprintf (c
, "%%*b%s\t%%Z2%s",
9972 inverted_p
? comp
: inverted_comp
,
9975 sprintf (c
, "%%*b%s%s\t%s%s,%s",
9976 inverted_p
? comp
: inverted_comp
,
9977 need_z_p
? "z" : "",
9981 c
= strchr (buffer
, '\0');
9982 /* Generate the load-address, and jump. This takes twelve
9983 bytes, for a total of 16. */
9985 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9992 /* The delay slot was unfilled. Since we're inside
9993 .noreorder, the assembler will not fill in the NOP for
9994 us, so we must do it ourselves. */
9995 strcat (buffer
, "\n\tnop");
9996 strcat (buffer
, "%]%>%)");
10009 /* Called to register all of our global variables with the garbage
10013 mips_add_gc_roots ()
10015 ggc_add_rtx_root (&mips_load_reg
, 1);
10016 ggc_add_rtx_root (&mips_load_reg2
, 1);
10017 ggc_add_rtx_root (&mips_load_reg3
, 1);
10018 ggc_add_rtx_root (&mips_load_reg4
, 1);
10019 ggc_add_rtx_root (branch_cmp
, ARRAY_SIZE (branch_cmp
));
10022 static enum processor_type
10023 mips_parse_cpu (cpu_string
)
10024 const char *cpu_string
;
10026 const char *p
= cpu_string
;
10028 enum processor_type cpu
;
10029 int warn_upper_case
= 0;
10031 /* We need to cope with the various "vr" prefixes for the NEC 4300
10032 and 4100 processors. */
10033 if (*p
== 'v' || *p
== 'V')
10036 warn_upper_case
= 1;
10040 if (*p
== 'r' || *p
== 'R')
10043 warn_upper_case
= 1;
10047 if (warn_upper_case
)
10048 warning ("the cpu name must be lower case");
10050 /* Since there is no difference between a R2000 and R3000 in
10051 terms of the scheduler, we collapse them into just an R3000. */
10053 cpu
= PROCESSOR_DEFAULT
;
10057 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
10058 cpu
= PROCESSOR_R3000
;
10059 else if (!strcmp (p
, "20kc") || !strcmp (p
, "20Kc") )
10060 cpu
= PROCESSOR_R20KC
;
10064 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
10065 cpu
= PROCESSOR_R3000
;
10066 else if (!strcmp (p
, "3900"))
10067 cpu
= PROCESSOR_R3900
;
10071 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
10072 cpu
= PROCESSOR_R4000
;
10073 /* The vr4100 is a non-FP ISA III processor with some extra
10075 else if (!strcmp (p
, "4100"))
10076 cpu
= PROCESSOR_R4100
;
10077 /* The vr4300 is a standard ISA III processor, but with a different
10079 else if (!strcmp (p
, "4300"))
10080 cpu
= PROCESSOR_R4300
;
10081 /* The r4400 is exactly the same as the r4000 from the compiler's
10083 else if (!strcmp (p
, "4400"))
10084 cpu
= PROCESSOR_R4000
;
10085 else if (!strcmp (p
, "4600"))
10086 cpu
= PROCESSOR_R4600
;
10087 else if (!strcmp (p
, "4650"))
10088 cpu
= PROCESSOR_R4650
;
10089 /* The 4kc and 4kp processor cores are the same for
10090 scheduling purposes; they both implement the MIPS32
10091 ISA and only differ in their memory management
10093 else if (!strcmp (p
, "4kc") || !strcmp (p
, "4Kc")
10094 || !strcmp (p
, "4kp") || !strcmp (p
, "4Kp") )
10095 cpu
= PROCESSOR_R4KC
;
10099 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
10100 cpu
= PROCESSOR_R5000
;
10101 else if (!strcmp (p
, "5kc") || !strcmp (p
, "5Kc") )
10102 cpu
= PROCESSOR_R5KC
;
10106 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
10107 cpu
= PROCESSOR_R6000
;
10111 if (!strcmp (p
, "8000"))
10112 cpu
= PROCESSOR_R8000
;
10116 if (!strcmp (p
, "orion"))
10117 cpu
= PROCESSOR_R4600
;
10122 && cpu
!= PROCESSOR_R4300
10123 && cpu
!= PROCESSOR_R4100
10124 && cpu
!= PROCESSOR_R5000
)
10125 cpu
= PROCESSOR_DEFAULT
;
10130 /* Adjust the cost of INSN based on the relationship between INSN that
10131 is dependent on DEP_INSN through the dependence LINK. The default
10132 is to make no adjustment to COST.
10134 On the MIPS, ignore the cost of anti- and output-dependencies. */
10136 mips_adjust_cost (insn
, link
, dep
, cost
)
10137 rtx insn ATTRIBUTE_UNUSED
;
10139 rtx dep ATTRIBUTE_UNUSED
;
10142 if (REG_NOTE_KIND (link
) != 0)
10143 return 0; /* Anti or output dependence. */
10147 /* Cover function for UNIQUE_SECTION. */
10150 mips_unique_section (decl
, reloc
)
10154 int len
, size
, sec
;
10155 const char *name
, *prefix
;
10157 static const char *const prefixes
[4][2] = {
10158 { ".text.", ".gnu.linkonce.t." },
10159 { ".rodata.", ".gnu.linkonce.r." },
10160 { ".data.", ".gnu.linkonce.d." },
10161 { ".sdata.", ".gnu.linkonce.s." }
10164 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10165 size
= int_size_in_bytes (TREE_TYPE (decl
));
10166 STRIP_NAME_ENCODING (name
, name
);
10168 /* Determine the base section we are interested in:
10169 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10170 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10172 else if (DECL_INITIAL (decl
) == 0
10173 || DECL_INITIAL (decl
) == error_mark_node
)
10175 else if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
10176 && TREE_CODE (decl
) == STRING_CST
10177 && !flag_writable_strings
)
10179 /* For embedded position independent code, put constant
10180 strings in the text section, because the data section
10181 is limited to 64K in size. For mips16 code, put
10182 strings in the text section so that a PC relative load
10183 instruction can be used to get their address. */
10186 else if (TARGET_EMBEDDED_DATA
)
10188 /* For embedded applications, always put an object in
10189 read-only data if possible, in order to reduce RAM
10192 if (DECL_READONLY_SECTION (decl
, reloc
))
10194 else if (size
> 0 && size
<= mips_section_threshold
)
10201 /* For hosted applications, always put an object in
10202 small data if possible, as this gives the best
10205 if (size
> 0 && size
<= mips_section_threshold
)
10207 else if (DECL_READONLY_SECTION (decl
, reloc
))
10213 prefix
= prefixes
[sec
][DECL_ONE_ONLY (decl
)];
10214 len
= strlen (name
) + strlen (prefix
);
10215 string
= alloca (len
+ 1);
10216 sprintf (string
, "%s%s", prefix
, name
);
10218 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
10222 mips_hard_regno_nregs (regno
, mode
)
10224 enum machine_mode mode
;
10226 if (! FP_REG_P (regno
))
10227 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
10229 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
10233 mips_return_in_memory (type
)
10236 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10237 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10238 structures are returned in a register. Objects with varying size
10239 must still be returned in memory, of course. */
10241 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
10242 return (TYPE_MODE (type
) == BLKmode
);
10244 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
10245 || (int_size_in_bytes (type
) == -1));
10255 case PROCESSOR_R3000
:
10268 #ifdef TARGET_IRIX6
10269 /* Output assembly to switch to section NAME with attribute FLAGS. */
10272 iris6_asm_named_section_1 (name
, flags
, align
)
10274 unsigned int flags
;
10275 unsigned int align
;
10277 unsigned int sh_type
, sh_flags
, sh_entsize
;
10280 if (!(flags
& SECTION_DEBUG
))
10281 sh_flags
|= 2; /* SHF_ALLOC */
10282 if (flags
& SECTION_WRITE
)
10283 sh_flags
|= 1; /* SHF_WRITE */
10284 if (flags
& SECTION_CODE
)
10285 sh_flags
|= 4; /* SHF_EXECINSTR */
10286 if (flags
& SECTION_SMALL
)
10287 sh_flags
|= 0x10000000; /* SHF_MIPS_GPREL */
10288 if (strcmp (name
, ".debug_frame") == 0)
10289 sh_flags
|= 0x08000000; /* SHF_MIPS_NOSTRIP */
10290 if (flags
& SECTION_DEBUG
)
10291 sh_type
= 0x7000001e; /* SHT_MIPS_DWARF */
10292 else if (flags
& SECTION_BSS
)
10293 sh_type
= 8; /* SHT_NOBITS */
10295 sh_type
= 1; /* SHT_PROGBITS */
10297 if (flags
& SECTION_CODE
)
10302 fprintf (asm_out_file
, "\t.section %s,%#x,%#x,%u,%u\n",
10303 name
, sh_type
, sh_flags
, sh_entsize
, align
);
10307 iris6_asm_named_section (name
, flags
)
10309 unsigned int flags
;
10311 if (TARGET_FILE_SWITCHING
&& (flags
& SECTION_CODE
))
10312 asm_out_file
= asm_out_text_file
;
10313 iris6_asm_named_section_1 (name
, flags
, 0);
10316 /* In addition to emitting a .align directive, record the maximum
10317 alignment requested for the current section. */
10319 struct iris_section_align_entry
10323 unsigned int flags
;
10326 static htab_t iris_section_align_htab
;
10327 static FILE *iris_orig_asm_out_file
;
10330 iris_section_align_entry_eq (p1
, p2
)
10334 const struct iris_section_align_entry
*old
= p1
;
10335 const char *new = p2
;
10337 return strcmp (old
->name
, new) == 0;
10341 iris_section_align_entry_hash (p
)
10344 const struct iris_section_align_entry
*old
= p
;
10345 return htab_hash_string (old
->name
);
10349 iris6_asm_output_align (file
, log
)
10353 const char *section
= current_section_name ();
10354 struct iris_section_align_entry
**slot
, *entry
;
10359 slot
= (struct iris_section_align_entry
**)
10360 htab_find_slot_with_hash (iris_section_align_htab
, section
,
10361 htab_hash_string (section
), INSERT
);
10365 entry
= (struct iris_section_align_entry
*)
10366 xmalloc (sizeof (struct iris_section_align_entry
));
10368 entry
->name
= section
;
10370 entry
->flags
= current_section_flags ();
10372 else if (entry
->log
< log
)
10375 fprintf (file
, "\t.align\t%u\n", log
);
10378 /* The Iris assembler does not record alignment from .align directives,
10379 but takes it from the first .section directive seen. Play yet more
10380 file switching games so that we can emit a .section directive at the
10381 beginning of the file with the proper alignment attached. */
10384 iris6_asm_file_start (stream
)
10387 mips_asm_file_start (stream
);
10389 iris_orig_asm_out_file
= asm_out_file
;
10390 stream
= tmpfile ();
10391 asm_out_file
= stream
;
10392 asm_out_data_file
= stream
;
10393 if (! TARGET_FILE_SWITCHING
)
10394 asm_out_text_file
= stream
;
10396 iris_section_align_htab
= htab_create (31, iris_section_align_entry_hash
,
10397 iris_section_align_entry_eq
, NULL
);
10401 iris6_section_align_1 (slot
, data
)
10403 void *data ATTRIBUTE_UNUSED
;
10405 const struct iris_section_align_entry
*entry
10406 = *(const struct iris_section_align_entry
**) slot
;
10408 iris6_asm_named_section_1 (entry
->name
, entry
->flags
, 1 << entry
->log
);
10413 iris6_asm_file_end (stream
)
10416 /* Emit section directives with the proper alignment at the top of the
10417 real output file. */
10418 asm_out_file
= iris_orig_asm_out_file
;
10419 htab_traverse (iris_section_align_htab
, iris6_section_align_1
, NULL
);
10421 /* Copy the data emitted to the temp file to the real output file. */
10422 copy_file_data (asm_out_file
, stream
);
10424 mips_asm_file_end (stream
);
10426 #endif /* TARGET_IRIX6 */