RISC-V: Support FP l/ll round and rint HF mode autovec
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / autovec / vls / math-lrintf16-rv64-0.c
blob21ef441131b22b5cd4acc68cb83cfa081eaff64d
1 /* { dg-do compile } */
2 /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
4 #include "def.h"
6 DEF_OP_V_CVT (lrintf16, 1, _Float16, long, __builtin_lrintf16)
7 DEF_OP_V_CVT (lrintf16, 2, _Float16, long, __builtin_lrintf16)
8 DEF_OP_V_CVT (lrintf16, 4, _Float16, long, __builtin_lrintf16)
9 DEF_OP_V_CVT (lrintf16, 8, _Float16, long, __builtin_lrintf16)
10 DEF_OP_V_CVT (lrintf16, 16, _Float16, long, __builtin_lrintf16)
11 DEF_OP_V_CVT (lrintf16, 32, _Float16, long, __builtin_lrintf16)
12 DEF_OP_V_CVT (lrintf16, 64, _Float16, long, __builtin_lrintf16)
13 DEF_OP_V_CVT (lrintf16, 128, _Float16, long, __builtin_lrintf16)
14 DEF_OP_V_CVT (lrintf16, 256, _Float16, long, __builtin_lrintf16)
15 DEF_OP_V_CVT (lrintf16, 512, _Float16, long, __builtin_lrintf16)
17 /* { dg-final { scan-assembler-not {csrr} } } */
18 /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
19 /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
20 /* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
21 /* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
22 /* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
23 /* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
24 /* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
25 /* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
26 /* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
27 /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 9 } } */
28 /* { dg-final { scan-assembler-times {vfwcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 9 } } */