1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((unsigned int *,
344 static void init_reg_last_arrays
PARAMS ((void));
345 static void setup_incoming_promotions
PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
347 static int cant_combine_insn_p
PARAMS ((rtx
));
348 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
349 static int sets_function_arg_p
PARAMS ((rtx
));
350 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
351 static int contains_muldiv
PARAMS ((rtx
));
352 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
353 static void undo_all
PARAMS ((void));
354 static void undo_commit
PARAMS ((void));
355 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
356 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
357 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
358 static rtx simplify_if_then_else
PARAMS ((rtx
));
359 static rtx simplify_set
PARAMS ((rtx
));
360 static rtx simplify_logical
PARAMS ((rtx
, int));
361 static rtx expand_compound_operation
PARAMS ((rtx
));
362 static rtx expand_field_assignment
PARAMS ((rtx
));
363 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
364 rtx
, unsigned HOST_WIDE_INT
, int,
366 static rtx extract_left_shift
PARAMS ((rtx
, int));
367 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
368 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
369 unsigned HOST_WIDE_INT
*));
370 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
371 unsigned HOST_WIDE_INT
, rtx
, int));
372 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
373 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
374 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
375 static rtx make_field_assignment
PARAMS ((rtx
));
376 static rtx apply_distributive_law
PARAMS ((rtx
));
377 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
378 unsigned HOST_WIDE_INT
));
379 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
380 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
381 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
382 enum rtx_code
, HOST_WIDE_INT
,
383 enum machine_mode
, int *));
384 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
386 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
387 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
388 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
390 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
391 static void update_table_tick
PARAMS ((rtx
));
392 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
393 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
394 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
395 static void record_dead_and_set_regs
PARAMS ((rtx
));
396 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
397 static rtx get_last_value
PARAMS ((rtx
));
398 static int use_crosses_set_p
PARAMS ((rtx
, int));
399 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
400 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
401 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
402 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
403 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
404 static void distribute_links
PARAMS ((rtx
));
405 static void mark_used_regs_combine
PARAMS ((rtx
));
406 static int insn_cuid
PARAMS ((rtx
));
407 static void record_promoted_value
PARAMS ((rtx
, rtx
));
408 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
409 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into
, newval
)
424 if (oldval
== newval
)
428 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
430 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
434 buf
->old_contents
.r
= oldval
;
437 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into
, newval
)
448 unsigned int *into
, newval
;
451 unsigned int oldval
= *into
;
453 if (oldval
== newval
)
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.i
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f
, nregs
)
481 register rtx insn
, next
;
486 register rtx links
, nextlinks
;
488 int new_direct_jump_p
= 0;
490 combine_attempts
= 0;
493 combine_successes
= 0;
495 combine_max_regno
= nregs
;
497 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
498 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
500 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
502 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
503 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
506 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
509 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs
* sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
522 if (INSN_UID (insn
) > i
)
525 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
528 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid
= 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn
= NULL_RTX
;
552 setup_incoming_promotions ();
554 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
555 sbitmap_zero (refresh_blocks
);
558 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
560 uid_cuid
[INSN_UID (insn
)] = ++i
;
566 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
568 record_dead_and_set_regs (insn
);
571 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
572 if (REG_NOTE_KIND (links
) == REG_INC
)
573 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
578 if (GET_CODE (insn
) == CODE_LABEL
)
582 nonzero_sign_valid
= 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block
= -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block
+ 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
602 if (GET_CODE (insn
) == CODE_LABEL
)
605 else if (INSN_P (insn
))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn
, PATTERN (insn
));
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0),
615 NULL_RTX
, &new_direct_jump_p
)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
622 rtx link
= XEXP (links
, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in persuing this chain any further. */
626 if (GET_CODE (link
) == NOTE
)
629 for (nextlinks
= LOG_LINKS (link
);
631 nextlinks
= XEXP (nextlinks
, 1))
632 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 &new_direct_jump_p
)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn
) == JUMP_INSN
647 && (prev
= prev_nonnote_insn (insn
)) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
)))
651 if ((next
= try_combine (insn
, prev
,
652 NULL_RTX
, &new_direct_jump_p
)) != 0)
655 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, prev
,
659 &new_direct_jump_p
)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn
) == INSN
665 && (prev
= prev_nonnote_insn (insn
)) != 0
666 && GET_CODE (prev
) == INSN
667 && sets_cc0_p (PATTERN (prev
))
668 && GET_CODE (PATTERN (insn
)) == SET
669 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
671 if ((next
= try_combine (insn
, prev
,
672 NULL_RTX
, &new_direct_jump_p
)) != 0)
675 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
676 nextlinks
= XEXP (nextlinks
, 1))
677 if ((next
= try_combine (insn
, prev
,
679 &new_direct_jump_p
)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
687 if (GET_CODE (XEXP (links
, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
689 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
690 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && (next
= try_combine (insn
, XEXP (links
, 0),
694 prev
, &new_direct_jump_p
)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 for (nextlinks
= XEXP (links
, 1); nextlinks
;
702 nextlinks
= XEXP (nextlinks
, 1))
703 if ((next
= try_combine (insn
, XEXP (links
, 0),
705 &new_direct_jump_p
)) != 0)
708 if (GET_CODE (insn
) != NOTE
)
709 record_dead_and_set_regs (insn
);
716 delete_noop_moves (f
);
720 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
725 sbitmap_free (refresh_blocks
);
726 free (reg_nonzero_bits
);
727 free (reg_sign_bit_copies
);
728 free (reg_last_death
);
730 free (reg_last_set_value
);
731 free (reg_last_set_table_tick
);
732 free (reg_last_set_label
);
733 free (reg_last_set_invalid
);
734 free (reg_last_set_mode
);
735 free (reg_last_set_nonzero_bits
);
736 free (reg_last_set_sign_bit_copies
);
740 struct undo
*undo
, *next
;
741 for (undo
= undobuf
.frees
; undo
; undo
= next
)
749 total_attempts
+= combine_attempts
;
750 total_merges
+= combine_merges
;
751 total_extras
+= combine_extras
;
752 total_successes
+= combine_successes
;
754 nonzero_sign_valid
= 0;
756 /* Make recognizer allow volatile MEMs again. */
759 return new_direct_jump_p
;
762 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
765 init_reg_last_arrays ()
767 unsigned int nregs
= combine_max_regno
;
769 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
770 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
771 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
772 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
773 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
774 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
775 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
776 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
777 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
780 /* Set up any promoted values for incoming argument registers. */
783 setup_incoming_promotions ()
785 #ifdef PROMOTE_FUNCTION_ARGS
788 enum machine_mode mode
;
790 rtx first
= get_insns ();
792 #ifndef OUTGOING_REGNO
793 #define OUTGOING_REGNO(N) N
795 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
796 /* Check whether this register can hold an incoming pointer
797 argument. FUNCTION_ARG_REGNO_P tests outgoing register
798 numbers, so translate if necessary due to register windows. */
799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
800 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
803 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
806 gen_rtx_CLOBBER (mode
, const0_rtx
)));
811 /* Called via note_stores. If X is a pseudo that is narrower than
812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
814 If we are setting only a portion of X and we can't figure out what
815 portion, assume all bits will be used since we don't know what will
818 Similarly, set how many bits of X are known to be copies of the sign bit
819 at all locations in the function. This is the smallest number implied
823 set_nonzero_bits_and_sign_copies (x
, set
, data
)
826 void *data ATTRIBUTE_UNUSED
;
830 if (GET_CODE (x
) == REG
831 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
832 /* If this register is undefined at the start of the file, we can't
833 say what its contents were. */
834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
835 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
837 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
839 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
840 reg_sign_bit_copies
[REGNO (x
)] = 1;
844 /* If this is a complex assignment, see if we can convert it into a
845 simple assignment. */
846 set
= expand_field_assignment (set
);
848 /* If this is a simple assignment, or we have a paradoxical SUBREG,
849 set what we know about X. */
851 if (SET_DEST (set
) == x
852 || (GET_CODE (SET_DEST (set
)) == SUBREG
853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
855 && SUBREG_REG (SET_DEST (set
)) == x
))
857 rtx src
= SET_SRC (set
);
859 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
860 /* If X is narrower than a word and SRC is a non-negative
861 constant that would appear negative in the mode of X,
862 sign-extend it for use in reg_nonzero_bits because some
863 machines (maybe most) will actually do the sign-extension
864 and this is the conservative approach.
866 ??? For 2.5, try to tighten up the MD files in this regard
867 instead of this kludge. */
869 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
870 && GET_CODE (src
) == CONST_INT
872 && 0 != (INTVAL (src
)
874 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
875 src
= GEN_INT (INTVAL (src
)
876 | ((HOST_WIDE_INT
) (-1)
877 << GET_MODE_BITSIZE (GET_MODE (x
))));
880 reg_nonzero_bits
[REGNO (x
)]
881 |= nonzero_bits (src
, nonzero_bits_mode
);
882 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
883 if (reg_sign_bit_copies
[REGNO (x
)] == 0
884 || reg_sign_bit_copies
[REGNO (x
)] > num
)
885 reg_sign_bit_copies
[REGNO (x
)] = num
;
889 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
890 reg_sign_bit_copies
[REGNO (x
)] = 1;
895 /* See if INSN can be combined into I3. PRED and SUCC are optionally
896 insns that were previously combined into I3 or that will be combined
897 into the merger of INSN and I3.
899 Return 0 if the combination is not allowed for any reason.
901 If the combination is allowed, *PDEST will be set to the single
902 destination of INSN and *PSRC to the single source, and this function
906 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
909 rtx pred ATTRIBUTE_UNUSED
;
914 rtx set
= 0, src
, dest
;
919 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
920 && next_active_insn (succ
) == i3
)
921 : next_active_insn (insn
) == i3
);
923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
924 or a PARALLEL consisting of such a SET and CLOBBERs.
926 If INSN has CLOBBER parallel parts, ignore them for our processing.
927 By definition, these happen during the execution of the insn. When it
928 is merged with another insn, all bets are off. If they are, in fact,
929 needed and aren't also supplied in I3, they may be added by
930 recog_for_combine. Otherwise, it won't match.
932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
935 Get the source and destination of INSN. If more than one, can't
938 if (GET_CODE (PATTERN (insn
)) == SET
)
939 set
= PATTERN (insn
);
940 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
941 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
943 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
945 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
947 switch (GET_CODE (elt
))
949 /* This is important to combine floating point insns
952 /* Combining an isolated USE doesn't make sense.
953 We depend here on combinable_i3_pat to reject them. */
954 /* The code below this loop only verifies that the inputs of
955 the SET in INSN do not change. We call reg_set_between_p
956 to verify that the REG in the USE does not change betweeen
958 If the USE in INSN was for a pseudo register, the matching
959 insn pattern will likely match any register; combining this
960 with any other USE would only be safe if we knew that the
961 used registers have identical values, or if there was
962 something to tell them apart, e.g. different modes. For
963 now, we forgo such compilcated tests and simply disallow
964 combining of USES of pseudo registers with any other USE. */
965 if (GET_CODE (XEXP (elt
, 0)) == REG
966 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
968 rtx i3pat
= PATTERN (i3
);
969 int i
= XVECLEN (i3pat
, 0) - 1;
970 unsigned int regno
= REGNO (XEXP (elt
, 0));
974 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
976 if (GET_CODE (i3elt
) == USE
977 && GET_CODE (XEXP (i3elt
, 0)) == REG
978 && (REGNO (XEXP (i3elt
, 0)) == regno
979 ? reg_set_between_p (XEXP (elt
, 0),
980 PREV_INSN (insn
), i3
)
981 : regno
>= FIRST_PSEUDO_REGISTER
))
988 /* We can ignore CLOBBERs. */
993 /* Ignore SETs whose result isn't used but not those that
994 have side-effects. */
995 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
996 && ! side_effects_p (elt
))
999 /* If we have already found a SET, this is a second one and
1000 so we cannot combine with this insn. */
1008 /* Anything else means we can't combine. */
1014 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1015 so don't do anything with it. */
1016 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1025 set
= expand_field_assignment (set
);
1026 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1028 /* Don't eliminate a store in the stack pointer. */
1029 if (dest
== stack_pointer_rtx
1030 /* If we couldn't eliminate a field assignment, we can't combine. */
1031 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1032 /* Don't combine with an insn that sets a register to itself if it has
1033 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1034 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1035 /* Can't merge an ASM_OPERANDS. */
1036 || GET_CODE (src
) == ASM_OPERANDS
1037 /* Can't merge a function call. */
1038 || GET_CODE (src
) == CALL
1039 /* Don't eliminate a function call argument. */
1040 || (GET_CODE (i3
) == CALL_INSN
1041 && (find_reg_fusage (i3
, USE
, dest
)
1042 || (GET_CODE (dest
) == REG
1043 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1044 && global_regs
[REGNO (dest
)])))
1045 /* Don't substitute into an incremented register. */
1046 || FIND_REG_INC_NOTE (i3
, dest
)
1047 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1049 /* Don't combine the end of a libcall into anything. */
1050 /* ??? This gives worse code, and appears to be unnecessary, since no
1051 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1052 use REG_RETVAL notes for noconflict blocks, but other code here
1053 makes sure that those insns don't disappear. */
1054 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1056 /* Make sure that DEST is not used after SUCC but before I3. */
1057 || (succ
&& ! all_adjacent
1058 && reg_used_between_p (dest
, succ
, i3
))
1059 /* Make sure that the value that is to be substituted for the register
1060 does not use any registers whose values alter in between. However,
1061 If the insns are adjacent, a use can't cross a set even though we
1062 think it might (this can happen for a sequence of insns each setting
1063 the same destination; reg_last_set of that register might point to
1064 a NOTE). If INSN has a REG_EQUIV note, the register is always
1065 equivalent to the memory so the substitution is valid even if there
1066 are intervening stores. Also, don't move a volatile asm or
1067 UNSPEC_VOLATILE across any other insns. */
1069 && (((GET_CODE (src
) != MEM
1070 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1071 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1072 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1073 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1074 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1075 better register allocation by not doing the combine. */
1076 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1077 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1078 /* Don't combine across a CALL_INSN, because that would possibly
1079 change whether the life span of some REGs crosses calls or not,
1080 and it is a pain to update that information.
1081 Exception: if source is a constant, moving it later can't hurt.
1082 Accept that special case, because it helps -fforce-addr a lot. */
1083 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1086 /* DEST must either be a REG or CC0. */
1087 if (GET_CODE (dest
) == REG
)
1089 /* If register alignment is being enforced for multi-word items in all
1090 cases except for parameters, it is possible to have a register copy
1091 insn referencing a hard register that is not allowed to contain the
1092 mode being copied and which would not be valid as an operand of most
1093 insns. Eliminate this problem by not combining with such an insn.
1095 Also, on some machines we don't want to extend the life of a hard
1098 if (GET_CODE (src
) == REG
1099 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1100 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1101 /* Don't extend the life of a hard register unless it is
1102 user variable (if we have few registers) or it can't
1103 fit into the desired register (meaning something special
1105 Also avoid substituting a return register into I3, because
1106 reload can't handle a conflict with constraints of other
1108 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1109 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1112 else if (GET_CODE (dest
) != CC0
)
1115 /* Don't substitute for a register intended as a clobberable operand.
1116 Similarly, don't substitute an expression containing a register that
1117 will be clobbered in I3. */
1118 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1119 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1120 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1121 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1123 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1126 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1127 or not), reject, unless nothing volatile comes between it and I3 */
1129 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1131 /* Make sure succ doesn't contain a volatile reference. */
1132 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1135 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1136 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1140 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1141 to be an explicit register variable, and was chosen for a reason. */
1143 if (GET_CODE (src
) == ASM_OPERANDS
1144 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1147 /* If there are any volatile insns between INSN and I3, reject, because
1148 they might affect machine state. */
1150 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1151 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1154 /* If INSN or I2 contains an autoincrement or autodecrement,
1155 make sure that register is not used between there and I3,
1156 and not already used in I3 either.
1157 Also insist that I3 not be a jump; if it were one
1158 and the incremented register were spilled, we would lose. */
1161 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1162 if (REG_NOTE_KIND (link
) == REG_INC
1163 && (GET_CODE (i3
) == JUMP_INSN
1164 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1165 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1170 /* Don't combine an insn that follows a CC0-setting insn.
1171 An insn that uses CC0 must not be separated from the one that sets it.
1172 We do, however, allow I2 to follow a CC0-setting insn if that insn
1173 is passed as I1; in that case it will be deleted also.
1174 We also allow combining in this case if all the insns are adjacent
1175 because that would leave the two CC0 insns adjacent as well.
1176 It would be more logical to test whether CC0 occurs inside I1 or I2,
1177 but that would be much slower, and this ought to be equivalent. */
1179 p
= prev_nonnote_insn (insn
);
1180 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1185 /* If we get here, we have passed all the tests and the combination is
1194 /* Check if PAT is an insn - or a part of it - used to set up an
1195 argument for a function in a hard register. */
1198 sets_function_arg_p (pat
)
1204 switch (GET_CODE (pat
))
1207 return sets_function_arg_p (PATTERN (pat
));
1210 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1211 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1217 inner_dest
= SET_DEST (pat
);
1218 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1219 || GET_CODE (inner_dest
) == SUBREG
1220 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1221 inner_dest
= XEXP (inner_dest
, 0);
1223 return (GET_CODE (inner_dest
) == REG
1224 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1225 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1234 /* LOC is the location within I3 that contains its pattern or the component
1235 of a PARALLEL of the pattern. We validate that it is valid for combining.
1237 One problem is if I3 modifies its output, as opposed to replacing it
1238 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1239 so would produce an insn that is not equivalent to the original insns.
1243 (set (reg:DI 101) (reg:DI 100))
1244 (set (subreg:SI (reg:DI 101) 0) <foo>)
1246 This is NOT equivalent to:
1248 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1249 (set (reg:DI 101) (reg:DI 100))])
1251 Not only does this modify 100 (in which case it might still be valid
1252 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1254 We can also run into a problem if I2 sets a register that I1
1255 uses and I1 gets directly substituted into I3 (not via I2). In that
1256 case, we would be getting the wrong value of I2DEST into I3, so we
1257 must reject the combination. This case occurs when I2 and I1 both
1258 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1259 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1260 of a SET must prevent combination from occurring.
1262 Before doing the above check, we first try to expand a field assignment
1263 into a set of logical operations.
1265 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1266 we place a register that is both set and used within I3. If more than one
1267 such register is detected, we fail.
1269 Return 1 if the combination is valid, zero otherwise. */
1272 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1278 rtx
*pi3dest_killed
;
1282 if (GET_CODE (x
) == SET
)
1284 rtx set
= expand_field_assignment (x
);
1285 rtx dest
= SET_DEST (set
);
1286 rtx src
= SET_SRC (set
);
1287 rtx inner_dest
= dest
;
1290 rtx inner_src
= src
;
1295 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1296 || GET_CODE (inner_dest
) == SUBREG
1297 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1298 inner_dest
= XEXP (inner_dest
, 0);
1300 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1303 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1304 || GET_CODE (inner_src
) == SUBREG
1305 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1306 inner_src
= XEXP (inner_src
, 0);
1308 /* If it is better that two different modes keep two different pseudos,
1309 avoid combining them. This avoids producing the following pattern
1311 (set (subreg:SI (reg/v:QI 21) 0)
1312 (lshiftrt:SI (reg/v:SI 20)
1314 If that were made, reload could not handle the pair of
1315 reg 20/21, since it would try to get any GENERAL_REGS
1316 but some of them don't handle QImode. */
1318 if (rtx_equal_p (inner_src
, i2dest
)
1319 && GET_CODE (inner_dest
) == REG
1320 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1324 /* Check for the case where I3 modifies its output, as
1326 if ((inner_dest
!= dest
1327 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1328 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1330 /* This is the same test done in can_combine_p except we can't test
1331 all_adjacent; we don't have to, since this instruction will stay
1332 in place, thus we are not considering increasing the lifetime of
1335 Also, if this insn sets a function argument, combining it with
1336 something that might need a spill could clobber a previous
1337 function argument; the all_adjacent test in can_combine_p also
1338 checks this; here, we do a more specific test for this case. */
1340 || (GET_CODE (inner_dest
) == REG
1341 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1342 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1343 GET_MODE (inner_dest
))))
1344 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1347 /* If DEST is used in I3, it is being killed in this insn,
1348 so record that for later.
1349 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1350 STACK_POINTER_REGNUM, since these are always considered to be
1351 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1352 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1353 && reg_referenced_p (dest
, PATTERN (i3
))
1354 && REGNO (dest
) != FRAME_POINTER_REGNUM
1355 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1356 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1358 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1359 && (REGNO (dest
) != ARG_POINTER_REGNUM
1360 || ! fixed_regs
[REGNO (dest
)])
1362 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1364 if (*pi3dest_killed
)
1367 *pi3dest_killed
= dest
;
1371 else if (GET_CODE (x
) == PARALLEL
)
1375 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1376 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1377 i1_not_in_src
, pi3dest_killed
))
1384 /* Return 1 if X is an arithmetic expression that contains a multiplication
1385 and division. We don't count multiplications by powers of two here. */
1391 switch (GET_CODE (x
))
1393 case MOD
: case DIV
: case UMOD
: case UDIV
:
1397 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1398 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1400 switch (GET_RTX_CLASS (GET_CODE (x
)))
1402 case 'c': case '<': case '2':
1403 return contains_muldiv (XEXP (x
, 0))
1404 || contains_muldiv (XEXP (x
, 1));
1407 return contains_muldiv (XEXP (x
, 0));
1415 /* Determine whether INSN can be used in a combination. Return nonzero if
1416 not. This is used in try_combine to detect early some cases where we
1417 can't perform combinations. */
1420 cant_combine_insn_p (insn
)
1426 /* If this isn't really an insn, we can't do anything.
1427 This can occur when flow deletes an insn that it has merged into an
1428 auto-increment address. */
1429 if (! INSN_P (insn
))
1432 /* Never combine loads and stores involving hard regs. The register
1433 allocator can usually handle such reg-reg moves by tying. If we allow
1434 the combiner to make substitutions of hard regs, we risk aborting in
1435 reload on machines that have SMALL_REGISTER_CLASSES.
1436 As an exception, we allow combinations involving fixed regs; these are
1437 not available to the register allocator so there's no risk involved. */
1439 set
= single_set (insn
);
1442 src
= SET_SRC (set
);
1443 dest
= SET_DEST (set
);
1444 if (GET_CODE (src
) == SUBREG
)
1445 src
= SUBREG_REG (src
);
1446 if (GET_CODE (dest
) == SUBREG
)
1447 dest
= SUBREG_REG (dest
);
1448 if (REG_P (src
) && REG_P (dest
)
1449 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1450 && ! fixed_regs
[REGNO (src
)])
1451 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1452 && ! fixed_regs
[REGNO (dest
)])))
1458 /* Try to combine the insns I1 and I2 into I3.
1459 Here I1 and I2 appear earlier than I3.
1460 I1 can be zero; then we combine just I2 into I3.
1462 If we are combining three insns and the resulting insn is not recognized,
1463 try splitting it into two insns. If that happens, I2 and I3 are retained
1464 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1467 Return 0 if the combination does not work. Then nothing is changed.
1468 If we did the combination, return the insn at which combine should
1471 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1472 new direct jump instruction. */
1475 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1476 register rtx i3
, i2
, i1
;
1477 register int *new_direct_jump_p
;
1479 /* New patterns for I3 and I2, respectively. */
1480 rtx newpat
, newi2pat
= 0;
1481 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1482 int added_sets_1
, added_sets_2
;
1483 /* Total number of SETs to put into I3. */
1485 /* Nonzero is I2's body now appears in I3. */
1487 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1488 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1489 /* Contains I3 if the destination of I3 is used in its source, which means
1490 that the old life of I3 is being killed. If that usage is placed into
1491 I2 and not in I3, a REG_DEAD note must be made. */
1492 rtx i3dest_killed
= 0;
1493 /* SET_DEST and SET_SRC of I2 and I1. */
1494 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1495 /* PATTERN (I2), or a copy of it in certain cases. */
1497 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1498 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1499 int i1_feeds_i3
= 0;
1500 /* Notes that must be added to REG_NOTES in I3 and I2. */
1501 rtx new_i3_notes
, new_i2_notes
;
1502 /* Notes that we substituted I3 into I2 instead of the normal case. */
1503 int i3_subst_into_i2
= 0;
1504 /* Notes that I1, I2 or I3 is a MULT operation. */
1512 /* Exit early if one of the insns involved can't be used for
1514 if (cant_combine_insn_p (i3
)
1515 || cant_combine_insn_p (i2
)
1516 || (i1
&& cant_combine_insn_p (i1
))
1517 /* We also can't do anything if I3 has a
1518 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1521 /* ??? This gives worse code, and appears to be unnecessary, since no
1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1523 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1529 undobuf
.other_insn
= 0;
1531 /* Reset the hard register usage information. */
1532 CLEAR_HARD_REG_SET (newpat_used_regs
);
1534 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1535 code below, set I1 to be the earlier of the two insns. */
1536 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1537 temp
= i1
, i1
= i2
, i2
= temp
;
1539 added_links_insn
= 0;
1541 /* First check for one important special-case that the code below will
1542 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1543 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1544 we may be able to replace that destination with the destination of I3.
1545 This occurs in the common code where we compute both a quotient and
1546 remainder into a structure, in which case we want to do the computation
1547 directly into the structure to avoid register-register copies.
1549 Note that this case handles both multiple sets in I2 and also
1550 cases where I2 has a number of CLOBBER or PARALLELs.
1552 We make very conservative checks below and only try to handle the
1553 most common cases of this. For example, we only handle the case
1554 where I2 and I3 are adjacent to avoid making difficult register
1557 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1558 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1559 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1560 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1561 && GET_CODE (PATTERN (i2
)) == PARALLEL
1562 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1563 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1564 below would need to check what is inside (and reg_overlap_mentioned_p
1565 doesn't support those codes anyway). Don't allow those destinations;
1566 the resulting insn isn't likely to be recognized anyway. */
1567 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1568 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1569 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1570 SET_DEST (PATTERN (i3
)))
1571 && next_real_insn (i2
) == i3
)
1573 rtx p2
= PATTERN (i2
);
1575 /* Make sure that the destination of I3,
1576 which we are going to substitute into one output of I2,
1577 is not used within another output of I2. We must avoid making this:
1578 (parallel [(set (mem (reg 69)) ...)
1579 (set (reg 69) ...)])
1580 which is not well-defined as to order of actions.
1581 (Besides, reload can't handle output reloads for this.)
1583 The problem can also happen if the dest of I3 is a memory ref,
1584 if another dest in I2 is an indirect memory ref. */
1585 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1586 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1587 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1588 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1589 SET_DEST (XVECEXP (p2
, 0, i
))))
1592 if (i
== XVECLEN (p2
, 0))
1593 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1594 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1595 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1596 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1601 subst_low_cuid
= INSN_CUID (i2
);
1603 added_sets_2
= added_sets_1
= 0;
1604 i2dest
= SET_SRC (PATTERN (i3
));
1606 /* Replace the dest in I2 with our dest and make the resulting
1607 insn the new pattern for I3. Then skip to where we
1608 validate the pattern. Everything was set up above. */
1609 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1610 SET_DEST (PATTERN (i3
)));
1613 i3_subst_into_i2
= 1;
1614 goto validate_replacement
;
1618 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1619 one of those words to another constant, merge them by making a new
1622 && (temp
= single_set (i2
)) != 0
1623 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1624 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1625 && GET_CODE (SET_DEST (temp
)) == REG
1626 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1627 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1628 && GET_CODE (PATTERN (i3
)) == SET
1629 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1630 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1633 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1635 HOST_WIDE_INT lo
, hi
;
1637 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1638 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1641 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1642 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1645 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1647 /* We don't handle the case of the target word being wider
1648 than a host wide int. */
1649 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1652 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1653 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1655 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1656 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1657 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1659 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1660 >> (HOST_BITS_PER_WIDE_INT
- 1));
1662 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1663 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1664 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1665 (INTVAL (SET_SRC (PATTERN (i3
)))));
1667 hi
= lo
< 0 ? -1 : 0;
1670 /* We don't handle the case of the higher word not fitting
1671 entirely in either hi or lo. */
1676 subst_low_cuid
= INSN_CUID (i2
);
1677 added_sets_2
= added_sets_1
= 0;
1678 i2dest
= SET_DEST (temp
);
1680 SUBST (SET_SRC (temp
),
1681 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1683 newpat
= PATTERN (i2
);
1684 goto validate_replacement
;
1688 /* If we have no I1 and I2 looks like:
1689 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1691 make up a dummy I1 that is
1694 (set (reg:CC X) (compare:CC Y (const_int 0)))
1696 (We can ignore any trailing CLOBBERs.)
1698 This undoes a previous combination and allows us to match a branch-and-
1701 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1702 && XVECLEN (PATTERN (i2
), 0) >= 2
1703 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1704 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1706 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1707 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1708 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1709 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1710 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1711 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1713 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1714 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1719 /* We make I1 with the same INSN_UID as I2. This gives it
1720 the same INSN_CUID for value tracking. Our fake I1 will
1721 never appear in the insn stream so giving it the same INSN_UID
1722 as I2 will not cause a problem. */
1724 subst_prev_insn
= i1
1725 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1726 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1729 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1730 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1731 SET_DEST (PATTERN (i1
)));
1736 /* Verify that I2 and I1 are valid for combining. */
1737 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1738 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1744 /* Record whether I2DEST is used in I2SRC and similarly for the other
1745 cases. Knowing this will help in register status updating below. */
1746 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1747 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1748 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1750 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1752 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1754 /* Ensure that I3's pattern can be the destination of combines. */
1755 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1756 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1763 /* See if any of the insns is a MULT operation. Unless one is, we will
1764 reject a combination that is, since it must be slower. Be conservative
1766 if (GET_CODE (i2src
) == MULT
1767 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1768 || (GET_CODE (PATTERN (i3
)) == SET
1769 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1772 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1773 We used to do this EXCEPT in one case: I3 has a post-inc in an
1774 output operand. However, that exception can give rise to insns like
1776 which is a famous insn on the PDP-11 where the value of r3 used as the
1777 source was model-dependent. Avoid this sort of thing. */
1780 if (!(GET_CODE (PATTERN (i3
)) == SET
1781 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1782 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1783 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1784 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1785 /* It's not the exception. */
1788 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1789 if (REG_NOTE_KIND (link
) == REG_INC
1790 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1792 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1799 /* See if the SETs in I1 or I2 need to be kept around in the merged
1800 instruction: whenever the value set there is still needed past I3.
1801 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1803 For the SET in I1, we have two cases: If I1 and I2 independently
1804 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1805 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1806 in I1 needs to be kept around unless I1DEST dies or is set in either
1807 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1808 I1DEST. If so, we know I1 feeds into I2. */
1810 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1813 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1814 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1816 /* If the set in I2 needs to be kept around, we must make a copy of
1817 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1818 PATTERN (I2), we are only substituting for the original I1DEST, not into
1819 an already-substituted copy. This also prevents making self-referential
1820 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1823 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1824 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1828 i2pat
= copy_rtx (i2pat
);
1832 /* Substitute in the latest insn for the regs set by the earlier ones. */
1834 maxreg
= max_reg_num ();
1838 /* It is possible that the source of I2 or I1 may be performing an
1839 unneeded operation, such as a ZERO_EXTEND of something that is known
1840 to have the high part zero. Handle that case by letting subst look at
1841 the innermost one of them.
1843 Another way to do this would be to have a function that tries to
1844 simplify a single insn instead of merging two or more insns. We don't
1845 do this because of the potential of infinite loops and because
1846 of the potential extra memory required. However, doing it the way
1847 we are is a bit of a kludge and doesn't catch all cases.
1849 But only do this if -fexpensive-optimizations since it slows things down
1850 and doesn't usually win. */
1852 if (flag_expensive_optimizations
)
1854 /* Pass pc_rtx so no substitutions are done, just simplifications.
1855 The cases that we are interested in here do not involve the few
1856 cases were is_replaced is checked. */
1859 subst_low_cuid
= INSN_CUID (i1
);
1860 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1864 subst_low_cuid
= INSN_CUID (i2
);
1865 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1870 /* Many machines that don't use CC0 have insns that can both perform an
1871 arithmetic operation and set the condition code. These operations will
1872 be represented as a PARALLEL with the first element of the vector
1873 being a COMPARE of an arithmetic operation with the constant zero.
1874 The second element of the vector will set some pseudo to the result
1875 of the same arithmetic operation. If we simplify the COMPARE, we won't
1876 match such a pattern and so will generate an extra insn. Here we test
1877 for this case, where both the comparison and the operation result are
1878 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1879 I2SRC. Later we will make the PARALLEL that contains I2. */
1881 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1882 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1883 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1884 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1886 #ifdef EXTRA_CC_MODES
1888 enum machine_mode compare_mode
;
1891 newpat
= PATTERN (i3
);
1892 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1896 #ifdef EXTRA_CC_MODES
1897 /* See if a COMPARE with the operand we substituted in should be done
1898 with the mode that is currently being used. If not, do the same
1899 processing we do in `subst' for a SET; namely, if the destination
1900 is used only once, try to replace it with a register of the proper
1901 mode and also replace the COMPARE. */
1902 if (undobuf
.other_insn
== 0
1903 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1904 &undobuf
.other_insn
))
1905 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1907 != GET_MODE (SET_DEST (newpat
))))
1909 unsigned int regno
= REGNO (SET_DEST (newpat
));
1910 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1912 if (regno
< FIRST_PSEUDO_REGISTER
1913 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1914 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1916 if (regno
>= FIRST_PSEUDO_REGISTER
)
1917 SUBST (regno_reg_rtx
[regno
], new_dest
);
1919 SUBST (SET_DEST (newpat
), new_dest
);
1920 SUBST (XEXP (*cc_use
, 0), new_dest
);
1921 SUBST (SET_SRC (newpat
),
1922 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1925 undobuf
.other_insn
= 0;
1932 n_occurrences
= 0; /* `subst' counts here */
1934 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1935 need to make a unique copy of I2SRC each time we substitute it
1936 to avoid self-referential rtl. */
1938 subst_low_cuid
= INSN_CUID (i2
);
1939 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1940 ! i1_feeds_i3
&& i1dest_in_i1src
);
1942 /* Record whether i2's body now appears within i3's body. */
1943 i2_is_used
= n_occurrences
;
1946 /* If we already got a failure, don't try to do more. Otherwise,
1947 try to substitute in I1 if we have it. */
1949 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1951 /* Before we can do this substitution, we must redo the test done
1952 above (see detailed comments there) that ensures that I1DEST
1953 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1955 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1963 subst_low_cuid
= INSN_CUID (i1
);
1964 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1967 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1968 to count all the ways that I2SRC and I1SRC can be used. */
1969 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1970 && i2_is_used
+ added_sets_2
> 1)
1971 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1972 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1974 /* Fail if we tried to make a new register (we used to abort, but there's
1975 really no reason to). */
1976 || max_reg_num () != maxreg
1977 /* Fail if we couldn't do something and have a CLOBBER. */
1978 || GET_CODE (newpat
) == CLOBBER
1979 /* Fail if this new pattern is a MULT and we didn't have one before
1980 at the outer level. */
1981 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1988 /* If the actions of the earlier insns must be kept
1989 in addition to substituting them into the latest one,
1990 we must make a new PARALLEL for the latest insn
1991 to hold additional the SETs. */
1993 if (added_sets_1
|| added_sets_2
)
1997 if (GET_CODE (newpat
) == PARALLEL
)
1999 rtvec old
= XVEC (newpat
, 0);
2000 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2001 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2002 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2003 sizeof (old
->elem
[0]) * old
->num_elem
);
2008 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2009 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2010 XVECEXP (newpat
, 0, 0) = old
;
2014 XVECEXP (newpat
, 0, --total_sets
)
2015 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2016 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2020 /* If there is no I1, use I2's body as is. We used to also not do
2021 the subst call below if I2 was substituted into I3,
2022 but that could lose a simplification. */
2024 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2026 /* See comment where i2pat is assigned. */
2027 XVECEXP (newpat
, 0, --total_sets
)
2028 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2032 /* We come here when we are replacing a destination in I2 with the
2033 destination of I3. */
2034 validate_replacement
:
2036 /* Note which hard regs this insn has as inputs. */
2037 mark_used_regs_combine (newpat
);
2039 /* Is the result of combination a valid instruction? */
2040 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2042 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2043 the second SET's destination is a register that is unused. In that case,
2044 we just need the first SET. This can occur when simplifying a divmod
2045 insn. We *must* test for this case here because the code below that
2046 splits two independent SETs doesn't handle this case correctly when it
2047 updates the register status. Also check the case where the first
2048 SET's destination is unused. That would not cause incorrect code, but
2049 does cause an unneeded insn to remain. */
2051 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2052 && XVECLEN (newpat
, 0) == 2
2053 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2056 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2058 && asm_noperands (newpat
) < 0)
2060 newpat
= XVECEXP (newpat
, 0, 0);
2061 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2064 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2065 && XVECLEN (newpat
, 0) == 2
2066 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2067 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2068 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2069 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2070 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2071 && asm_noperands (newpat
) < 0)
2073 newpat
= XVECEXP (newpat
, 0, 1);
2074 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2077 /* If we were combining three insns and the result is a simple SET
2078 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2079 insns. There are two ways to do this. It can be split using a
2080 machine-specific method (like when you have an addition of a large
2081 constant) or by combine in the function find_split_point. */
2083 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2084 && asm_noperands (newpat
) < 0)
2086 rtx m_split
, *split
;
2087 rtx ni2dest
= i2dest
;
2089 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2090 use I2DEST as a scratch register will help. In the latter case,
2091 convert I2DEST to the mode of the source of NEWPAT if we can. */
2093 m_split
= split_insns (newpat
, i3
);
2095 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2096 inputs of NEWPAT. */
2098 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2099 possible to try that as a scratch reg. This would require adding
2100 more code to make it work though. */
2102 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2104 /* If I2DEST is a hard register or the only use of a pseudo,
2105 we can change its mode. */
2106 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2107 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2108 && GET_CODE (i2dest
) == REG
2109 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2110 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2111 && ! REG_USERVAR_P (i2dest
))))
2112 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2115 m_split
= split_insns (gen_rtx_PARALLEL
2117 gen_rtvec (2, newpat
,
2118 gen_rtx_CLOBBER (VOIDmode
,
2121 /* If the split with the mode-changed register didn't work, try
2122 the original register. */
2123 if (! m_split
&& ni2dest
!= i2dest
)
2126 m_split
= split_insns (gen_rtx_PARALLEL
2128 gen_rtvec (2, newpat
,
2129 gen_rtx_CLOBBER (VOIDmode
,
2135 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2137 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2138 if (insn_code_number
>= 0)
2141 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2142 && XVECLEN (m_split
, 0) == 2
2143 && (next_real_insn (i2
) == i3
2144 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2148 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2149 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2151 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2152 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2154 /* In case we changed the mode of I2DEST, replace it in the
2155 pseudo-register table here. We can't do it above in case this
2156 code doesn't get executed and we do a split the other way. */
2158 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2159 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2161 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2163 /* If I2 or I3 has multiple SETs, we won't know how to track
2164 register status, so don't use these insns. If I2's destination
2165 is used between I2 and I3, we also can't use these insns. */
2167 if (i2_code_number
>= 0 && i2set
&& i3set
2168 && (next_real_insn (i2
) == i3
2169 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2170 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2172 if (insn_code_number
>= 0)
2175 /* It is possible that both insns now set the destination of I3.
2176 If so, we must show an extra use of it. */
2178 if (insn_code_number
>= 0)
2180 rtx new_i3_dest
= SET_DEST (i3set
);
2181 rtx new_i2_dest
= SET_DEST (i2set
);
2183 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2184 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2185 || GET_CODE (new_i3_dest
) == SUBREG
)
2186 new_i3_dest
= XEXP (new_i3_dest
, 0);
2188 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2189 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2190 || GET_CODE (new_i2_dest
) == SUBREG
)
2191 new_i2_dest
= XEXP (new_i2_dest
, 0);
2193 if (GET_CODE (new_i3_dest
) == REG
2194 && GET_CODE (new_i2_dest
) == REG
2195 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2196 REG_N_SETS (REGNO (new_i2_dest
))++;
2200 /* If we can split it and use I2DEST, go ahead and see if that
2201 helps things be recognized. Verify that none of the registers
2202 are set between I2 and I3. */
2203 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2205 && GET_CODE (i2dest
) == REG
2207 /* We need I2DEST in the proper mode. If it is a hard register
2208 or the only use of a pseudo, we can change its mode. */
2209 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2210 || GET_MODE (*split
) == VOIDmode
2211 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2212 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2213 && ! REG_USERVAR_P (i2dest
)))
2214 && (next_real_insn (i2
) == i3
2215 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2216 /* We can't overwrite I2DEST if its value is still used by
2218 && ! reg_referenced_p (i2dest
, newpat
))
2220 rtx newdest
= i2dest
;
2221 enum rtx_code split_code
= GET_CODE (*split
);
2222 enum machine_mode split_mode
= GET_MODE (*split
);
2224 /* Get NEWDEST as a register in the proper mode. We have already
2225 validated that we can do this. */
2226 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2228 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2230 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2231 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2234 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2235 an ASHIFT. This can occur if it was inside a PLUS and hence
2236 appeared to be a memory address. This is a kludge. */
2237 if (split_code
== MULT
2238 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2239 && INTVAL (XEXP (*split
, 1)) > 0
2240 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2242 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2243 XEXP (*split
, 0), GEN_INT (i
)));
2244 /* Update split_code because we may not have a multiply
2246 split_code
= GET_CODE (*split
);
2249 #ifdef INSN_SCHEDULING
2250 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2251 be written as a ZERO_EXTEND. */
2252 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2253 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2254 SUBREG_REG (*split
)));
2257 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2258 SUBST (*split
, newdest
);
2259 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2261 /* If the split point was a MULT and we didn't have one before,
2262 don't use one now. */
2263 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2264 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2268 /* Check for a case where we loaded from memory in a narrow mode and
2269 then sign extended it, but we need both registers. In that case,
2270 we have a PARALLEL with both loads from the same memory location.
2271 We can split this into a load from memory followed by a register-register
2272 copy. This saves at least one insn, more if register allocation can
2275 We cannot do this if the destination of the second assignment is
2276 a register that we have already assumed is zero-extended. Similarly
2277 for a SUBREG of such a register. */
2279 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2280 && GET_CODE (newpat
) == PARALLEL
2281 && XVECLEN (newpat
, 0) == 2
2282 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2283 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2284 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2285 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2286 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2287 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2289 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2290 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2291 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2292 (GET_CODE (temp
) == REG
2293 && reg_nonzero_bits
[REGNO (temp
)] != 0
2294 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2295 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2296 && (reg_nonzero_bits
[REGNO (temp
)]
2297 != GET_MODE_MASK (word_mode
))))
2298 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2299 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2300 (GET_CODE (temp
) == REG
2301 && reg_nonzero_bits
[REGNO (temp
)] != 0
2302 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2304 && (reg_nonzero_bits
[REGNO (temp
)]
2305 != GET_MODE_MASK (word_mode
)))))
2306 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2307 SET_SRC (XVECEXP (newpat
, 0, 1)))
2308 && ! find_reg_note (i3
, REG_UNUSED
,
2309 SET_DEST (XVECEXP (newpat
, 0, 0))))
2313 newi2pat
= XVECEXP (newpat
, 0, 0);
2314 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2315 newpat
= XVECEXP (newpat
, 0, 1);
2316 SUBST (SET_SRC (newpat
),
2317 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2318 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2320 if (i2_code_number
>= 0)
2321 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2323 if (insn_code_number
>= 0)
2328 /* If we will be able to accept this, we have made a change to the
2329 destination of I3. This can invalidate a LOG_LINKS pointing
2330 to I3. No other part of combine.c makes such a transformation.
2332 The new I3 will have a destination that was previously the
2333 destination of I1 or I2 and which was used in i2 or I3. Call
2334 distribute_links to make a LOG_LINK from the next use of
2335 that destination. */
2337 PATTERN (i3
) = newpat
;
2338 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2340 /* I3 now uses what used to be its destination and which is
2341 now I2's destination. That means we need a LOG_LINK from
2342 I3 to I2. But we used to have one, so we still will.
2344 However, some later insn might be using I2's dest and have
2345 a LOG_LINK pointing at I3. We must remove this link.
2346 The simplest way to remove the link is to point it at I1,
2347 which we know will be a NOTE. */
2349 for (insn
= NEXT_INSN (i3
);
2350 insn
&& (this_basic_block
== n_basic_blocks
- 1
2351 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2352 insn
= NEXT_INSN (insn
))
2354 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2356 for (link
= LOG_LINKS (insn
); link
;
2357 link
= XEXP (link
, 1))
2358 if (XEXP (link
, 0) == i3
)
2359 XEXP (link
, 0) = i1
;
2367 /* Similarly, check for a case where we have a PARALLEL of two independent
2368 SETs but we started with three insns. In this case, we can do the sets
2369 as two separate insns. This case occurs when some SET allows two
2370 other insns to combine, but the destination of that SET is still live. */
2372 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2373 && GET_CODE (newpat
) == PARALLEL
2374 && XVECLEN (newpat
, 0) == 2
2375 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2376 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2378 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2379 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2381 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2383 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2384 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2387 XVECEXP (newpat
, 0, 0))
2388 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2389 XVECEXP (newpat
, 0, 1))
2390 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2391 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2393 /* Normally, it doesn't matter which of the two is done first,
2394 but it does if one references cc0. In that case, it has to
2397 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2399 newi2pat
= XVECEXP (newpat
, 0, 0);
2400 newpat
= XVECEXP (newpat
, 0, 1);
2405 newi2pat
= XVECEXP (newpat
, 0, 1);
2406 newpat
= XVECEXP (newpat
, 0, 0);
2409 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2411 if (i2_code_number
>= 0)
2412 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2415 /* If it still isn't recognized, fail and change things back the way they
2417 if ((insn_code_number
< 0
2418 /* Is the result a reasonable ASM_OPERANDS? */
2419 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2425 /* If we had to change another insn, make sure it is valid also. */
2426 if (undobuf
.other_insn
)
2428 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2429 rtx new_other_notes
;
2432 CLEAR_HARD_REG_SET (newpat_used_regs
);
2434 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2437 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2443 PATTERN (undobuf
.other_insn
) = other_pat
;
2445 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2446 are still valid. Then add any non-duplicate notes added by
2447 recog_for_combine. */
2448 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2450 next
= XEXP (note
, 1);
2452 if (REG_NOTE_KIND (note
) == REG_UNUSED
2453 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2455 if (GET_CODE (XEXP (note
, 0)) == REG
)
2456 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2458 remove_note (undobuf
.other_insn
, note
);
2462 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2463 if (GET_CODE (XEXP (note
, 0)) == REG
)
2464 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2466 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2467 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2470 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2471 they are adjacent to each other or not. */
2473 rtx p
= prev_nonnote_insn (i3
);
2474 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2475 && sets_cc0_p (newi2pat
))
2483 /* We now know that we can do this combination. Merge the insns and
2484 update the status of registers and LOG_LINKS. */
2487 rtx i3notes
, i2notes
, i1notes
= 0;
2488 rtx i3links
, i2links
, i1links
= 0;
2491 /* Compute which registers we expect to eliminate. newi2pat may be setting
2492 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2493 same as i3dest, in which case newi2pat may be setting i1dest. */
2494 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2495 || i2dest_in_i2src
|| i2dest_in_i1src
2497 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2498 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2501 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2503 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2504 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2506 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2508 /* Ensure that we do not have something that should not be shared but
2509 occurs multiple times in the new insns. Check this by first
2510 resetting all the `used' flags and then copying anything is shared. */
2512 reset_used_flags (i3notes
);
2513 reset_used_flags (i2notes
);
2514 reset_used_flags (i1notes
);
2515 reset_used_flags (newpat
);
2516 reset_used_flags (newi2pat
);
2517 if (undobuf
.other_insn
)
2518 reset_used_flags (PATTERN (undobuf
.other_insn
));
2520 i3notes
= copy_rtx_if_shared (i3notes
);
2521 i2notes
= copy_rtx_if_shared (i2notes
);
2522 i1notes
= copy_rtx_if_shared (i1notes
);
2523 newpat
= copy_rtx_if_shared (newpat
);
2524 newi2pat
= copy_rtx_if_shared (newi2pat
);
2525 if (undobuf
.other_insn
)
2526 reset_used_flags (PATTERN (undobuf
.other_insn
));
2528 INSN_CODE (i3
) = insn_code_number
;
2529 PATTERN (i3
) = newpat
;
2530 if (undobuf
.other_insn
)
2531 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2533 /* We had one special case above where I2 had more than one set and
2534 we replaced a destination of one of those sets with the destination
2535 of I3. In that case, we have to update LOG_LINKS of insns later
2536 in this basic block. Note that this (expensive) case is rare.
2538 Also, in this case, we must pretend that all REG_NOTEs for I2
2539 actually came from I3, so that REG_UNUSED notes from I2 will be
2540 properly handled. */
2542 if (i3_subst_into_i2
)
2544 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2545 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2546 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2547 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2548 && ! find_reg_note (i2
, REG_UNUSED
,
2549 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2550 for (temp
= NEXT_INSN (i2
);
2551 temp
&& (this_basic_block
== n_basic_blocks
- 1
2552 || BLOCK_HEAD (this_basic_block
) != temp
);
2553 temp
= NEXT_INSN (temp
))
2554 if (temp
!= i3
&& INSN_P (temp
))
2555 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2556 if (XEXP (link
, 0) == i2
)
2557 XEXP (link
, 0) = i3
;
2562 while (XEXP (link
, 1))
2563 link
= XEXP (link
, 1);
2564 XEXP (link
, 1) = i2notes
;
2578 INSN_CODE (i2
) = i2_code_number
;
2579 PATTERN (i2
) = newi2pat
;
2583 PUT_CODE (i2
, NOTE
);
2584 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2585 NOTE_SOURCE_FILE (i2
) = 0;
2592 PUT_CODE (i1
, NOTE
);
2593 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2594 NOTE_SOURCE_FILE (i1
) = 0;
2597 /* Get death notes for everything that is now used in either I3 or
2598 I2 and used to die in a previous insn. If we built two new
2599 patterns, move from I1 to I2 then I2 to I3 so that we get the
2600 proper movement on registers that I2 modifies. */
2604 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2605 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2608 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2611 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2613 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2616 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2619 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2622 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2625 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2626 know these are REG_UNUSED and want them to go to the desired insn,
2627 so we always pass it as i3. We have not counted the notes in
2628 reg_n_deaths yet, so we need to do so now. */
2630 if (newi2pat
&& new_i2_notes
)
2632 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2633 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2634 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2636 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2641 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2642 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2643 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2645 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2648 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2649 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2650 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2651 in that case, it might delete I2. Similarly for I2 and I1.
2652 Show an additional death due to the REG_DEAD note we make here. If
2653 we discard it in distribute_notes, we will decrement it again. */
2657 if (GET_CODE (i3dest_killed
) == REG
)
2658 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2660 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2661 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2663 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2665 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2667 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2671 if (i2dest_in_i2src
)
2673 if (GET_CODE (i2dest
) == REG
)
2674 REG_N_DEATHS (REGNO (i2dest
))++;
2676 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2677 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2678 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2680 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2681 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2682 NULL_RTX
, NULL_RTX
);
2685 if (i1dest_in_i1src
)
2687 if (GET_CODE (i1dest
) == REG
)
2688 REG_N_DEATHS (REGNO (i1dest
))++;
2690 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2691 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2692 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2695 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2696 NULL_RTX
, NULL_RTX
);
2699 distribute_links (i3links
);
2700 distribute_links (i2links
);
2701 distribute_links (i1links
);
2703 if (GET_CODE (i2dest
) == REG
)
2706 rtx i2_insn
= 0, i2_val
= 0, set
;
2708 /* The insn that used to set this register doesn't exist, and
2709 this life of the register may not exist either. See if one of
2710 I3's links points to an insn that sets I2DEST. If it does,
2711 that is now the last known value for I2DEST. If we don't update
2712 this and I2 set the register to a value that depended on its old
2713 contents, we will get confused. If this insn is used, thing
2714 will be set correctly in combine_instructions. */
2716 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2717 if ((set
= single_set (XEXP (link
, 0))) != 0
2718 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2719 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2721 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2723 /* If the reg formerly set in I2 died only once and that was in I3,
2724 zero its use count so it won't make `reload' do any work. */
2726 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2727 && ! i2dest_in_i2src
)
2729 regno
= REGNO (i2dest
);
2730 REG_N_SETS (regno
)--;
2734 if (i1
&& GET_CODE (i1dest
) == REG
)
2737 rtx i1_insn
= 0, i1_val
= 0, set
;
2739 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2740 if ((set
= single_set (XEXP (link
, 0))) != 0
2741 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2742 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2744 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2746 regno
= REGNO (i1dest
);
2747 if (! added_sets_1
&& ! i1dest_in_i1src
)
2748 REG_N_SETS (regno
)--;
2751 /* Update reg_nonzero_bits et al for any changes that may have been made
2752 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2753 important. Because newi2pat can affect nonzero_bits of newpat */
2755 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2756 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2758 /* Set new_direct_jump_p if a new return or simple jump instruction
2761 If I3 is now an unconditional jump, ensure that it has a
2762 BARRIER following it since it may have initially been a
2763 conditional jump. It may also be the last nonnote insn. */
2765 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2767 *new_direct_jump_p
= 1;
2769 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2770 || GET_CODE (temp
) != BARRIER
)
2771 emit_barrier_after (i3
);
2773 /* An NOOP jump does not need barrier, but it does need cleaning up
2775 if (GET_CODE (newpat
) == SET
2776 && SET_SRC (newpat
) == pc_rtx
2777 && SET_DEST (newpat
) == pc_rtx
)
2778 *new_direct_jump_p
= 1;
2781 combine_successes
++;
2784 /* Clear this here, so that subsequent get_last_value calls are not
2786 subst_prev_insn
= NULL_RTX
;
2788 if (added_links_insn
2789 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2790 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2791 return added_links_insn
;
2793 return newi2pat
? i2
: i3
;
2796 /* Undo all the modifications recorded in undobuf. */
2801 struct undo
*undo
, *next
;
2803 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2807 *undo
->where
.i
= undo
->old_contents
.i
;
2809 *undo
->where
.r
= undo
->old_contents
.r
;
2811 undo
->next
= undobuf
.frees
;
2812 undobuf
.frees
= undo
;
2817 /* Clear this here, so that subsequent get_last_value calls are not
2819 subst_prev_insn
= NULL_RTX
;
2822 /* We've committed to accepting the changes we made. Move all
2823 of the undos to the free list. */
2828 struct undo
*undo
, *next
;
2830 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2833 undo
->next
= undobuf
.frees
;
2834 undobuf
.frees
= undo
;
2840 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2841 where we have an arithmetic expression and return that point. LOC will
2844 try_combine will call this function to see if an insn can be split into
2848 find_split_point (loc
, insn
)
2853 enum rtx_code code
= GET_CODE (x
);
2855 unsigned HOST_WIDE_INT len
= 0;
2856 HOST_WIDE_INT pos
= 0;
2858 rtx inner
= NULL_RTX
;
2860 /* First special-case some codes. */
2864 #ifdef INSN_SCHEDULING
2865 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2867 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2870 return find_split_point (&SUBREG_REG (x
), insn
);
2874 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2875 using LO_SUM and HIGH. */
2876 if (GET_CODE (XEXP (x
, 0)) == CONST
2877 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2880 gen_rtx_LO_SUM (Pmode
,
2881 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2883 return &XEXP (XEXP (x
, 0), 0);
2887 /* If we have a PLUS whose second operand is a constant and the
2888 address is not valid, perhaps will can split it up using
2889 the machine-specific way to split large constants. We use
2890 the first pseudo-reg (one of the virtual regs) as a placeholder;
2891 it will not remain in the result. */
2892 if (GET_CODE (XEXP (x
, 0)) == PLUS
2893 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2894 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2896 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2897 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2900 /* This should have produced two insns, each of which sets our
2901 placeholder. If the source of the second is a valid address,
2902 we can make put both sources together and make a split point
2905 if (seq
&& XVECLEN (seq
, 0) == 2
2906 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2907 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2908 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2909 && ! reg_mentioned_p (reg
,
2910 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2911 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2912 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2913 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2914 && memory_address_p (GET_MODE (x
),
2915 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2917 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2918 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2920 /* Replace the placeholder in SRC2 with SRC1. If we can
2921 find where in SRC2 it was placed, that can become our
2922 split point and we can replace this address with SRC2.
2923 Just try two obvious places. */
2925 src2
= replace_rtx (src2
, reg
, src1
);
2927 if (XEXP (src2
, 0) == src1
)
2928 split
= &XEXP (src2
, 0);
2929 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2930 && XEXP (XEXP (src2
, 0), 0) == src1
)
2931 split
= &XEXP (XEXP (src2
, 0), 0);
2935 SUBST (XEXP (x
, 0), src2
);
2940 /* If that didn't work, perhaps the first operand is complex and
2941 needs to be computed separately, so make a split point there.
2942 This will occur on machines that just support REG + CONST
2943 and have a constant moved through some previous computation. */
2945 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2946 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2947 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2949 return &XEXP (XEXP (x
, 0), 0);
2955 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2956 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2957 we need to put the operand into a register. So split at that
2960 if (SET_DEST (x
) == cc0_rtx
2961 && GET_CODE (SET_SRC (x
)) != COMPARE
2962 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2963 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2964 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2965 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2966 return &SET_SRC (x
);
2969 /* See if we can split SET_SRC as it stands. */
2970 split
= find_split_point (&SET_SRC (x
), insn
);
2971 if (split
&& split
!= &SET_SRC (x
))
2974 /* See if we can split SET_DEST as it stands. */
2975 split
= find_split_point (&SET_DEST (x
), insn
);
2976 if (split
&& split
!= &SET_DEST (x
))
2979 /* See if this is a bitfield assignment with everything constant. If
2980 so, this is an IOR of an AND, so split it into that. */
2981 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2982 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2983 <= HOST_BITS_PER_WIDE_INT
)
2984 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2985 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2986 && GET_CODE (SET_SRC (x
)) == CONST_INT
2987 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2988 + INTVAL (XEXP (SET_DEST (x
), 2)))
2989 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2990 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2992 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2993 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2994 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2995 rtx dest
= XEXP (SET_DEST (x
), 0);
2996 enum machine_mode mode
= GET_MODE (dest
);
2997 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2999 if (BITS_BIG_ENDIAN
)
3000 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3004 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3007 gen_binary (IOR
, mode
,
3008 gen_binary (AND
, mode
, dest
,
3009 GEN_INT (~(mask
<< pos
)
3010 & GET_MODE_MASK (mode
))),
3011 GEN_INT (src
<< pos
)));
3013 SUBST (SET_DEST (x
), dest
);
3015 split
= find_split_point (&SET_SRC (x
), insn
);
3016 if (split
&& split
!= &SET_SRC (x
))
3020 /* Otherwise, see if this is an operation that we can split into two.
3021 If so, try to split that. */
3022 code
= GET_CODE (SET_SRC (x
));
3027 /* If we are AND'ing with a large constant that is only a single
3028 bit and the result is only being used in a context where we
3029 need to know if it is zero or non-zero, replace it with a bit
3030 extraction. This will avoid the large constant, which might
3031 have taken more than one insn to make. If the constant were
3032 not a valid argument to the AND but took only one insn to make,
3033 this is no worse, but if it took more than one insn, it will
3036 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3037 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3038 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3039 && GET_CODE (SET_DEST (x
)) == REG
3040 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3041 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3042 && XEXP (*split
, 0) == SET_DEST (x
)
3043 && XEXP (*split
, 1) == const0_rtx
)
3045 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3046 XEXP (SET_SRC (x
), 0),
3047 pos
, NULL_RTX
, 1, 1, 0, 0);
3048 if (extraction
!= 0)
3050 SUBST (SET_SRC (x
), extraction
);
3051 return find_split_point (loc
, insn
);
3057 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3058 is known to be on, this can be converted into a NEG of a shift. */
3059 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3060 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3061 && 1 <= (pos
= exact_log2
3062 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3063 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3065 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3069 gen_rtx_LSHIFTRT (mode
,
3070 XEXP (SET_SRC (x
), 0),
3073 split
= find_split_point (&SET_SRC (x
), insn
);
3074 if (split
&& split
!= &SET_SRC (x
))
3080 inner
= XEXP (SET_SRC (x
), 0);
3082 /* We can't optimize if either mode is a partial integer
3083 mode as we don't know how many bits are significant
3085 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3086 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3090 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3096 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3097 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3099 inner
= XEXP (SET_SRC (x
), 0);
3100 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3101 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3103 if (BITS_BIG_ENDIAN
)
3104 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3105 unsignedp
= (code
== ZERO_EXTRACT
);
3113 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3115 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3117 /* For unsigned, we have a choice of a shift followed by an
3118 AND or two shifts. Use two shifts for field sizes where the
3119 constant might be too large. We assume here that we can
3120 always at least get 8-bit constants in an AND insn, which is
3121 true for every current RISC. */
3123 if (unsignedp
&& len
<= 8)
3128 (mode
, gen_lowpart_for_combine (mode
, inner
),
3130 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3132 split
= find_split_point (&SET_SRC (x
), insn
);
3133 if (split
&& split
!= &SET_SRC (x
))
3140 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3141 gen_rtx_ASHIFT (mode
,
3142 gen_lowpart_for_combine (mode
, inner
),
3143 GEN_INT (GET_MODE_BITSIZE (mode
)
3145 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3147 split
= find_split_point (&SET_SRC (x
), insn
);
3148 if (split
&& split
!= &SET_SRC (x
))
3153 /* See if this is a simple operation with a constant as the second
3154 operand. It might be that this constant is out of range and hence
3155 could be used as a split point. */
3156 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3157 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3158 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3159 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3160 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3161 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3162 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3164 return &XEXP (SET_SRC (x
), 1);
3166 /* Finally, see if this is a simple operation with its first operand
3167 not in a register. The operation might require this operand in a
3168 register, so return it as a split point. We can always do this
3169 because if the first operand were another operation, we would have
3170 already found it as a split point. */
3171 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3172 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3173 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3174 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3175 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3176 return &XEXP (SET_SRC (x
), 0);
3182 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3183 it is better to write this as (not (ior A B)) so we can split it.
3184 Similarly for IOR. */
3185 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3188 gen_rtx_NOT (GET_MODE (x
),
3189 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3191 XEXP (XEXP (x
, 0), 0),
3192 XEXP (XEXP (x
, 1), 0))));
3193 return find_split_point (loc
, insn
);
3196 /* Many RISC machines have a large set of logical insns. If the
3197 second operand is a NOT, put it first so we will try to split the
3198 other operand first. */
3199 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3201 rtx tem
= XEXP (x
, 0);
3202 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3203 SUBST (XEXP (x
, 1), tem
);
3211 /* Otherwise, select our actions depending on our rtx class. */
3212 switch (GET_RTX_CLASS (code
))
3214 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3216 split
= find_split_point (&XEXP (x
, 2), insn
);
3219 /* ... fall through ... */
3223 split
= find_split_point (&XEXP (x
, 1), insn
);
3226 /* ... fall through ... */
3228 /* Some machines have (and (shift ...) ...) insns. If X is not
3229 an AND, but XEXP (X, 0) is, use it as our split point. */
3230 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3231 return &XEXP (x
, 0);
3233 split
= find_split_point (&XEXP (x
, 0), insn
);
3239 /* Otherwise, we don't have a split point. */
3243 /* Throughout X, replace FROM with TO, and return the result.
3244 The result is TO if X is FROM;
3245 otherwise the result is X, but its contents may have been modified.
3246 If they were modified, a record was made in undobuf so that
3247 undo_all will (among other things) return X to its original state.
3249 If the number of changes necessary is too much to record to undo,
3250 the excess changes are not made, so the result is invalid.
3251 The changes already made can still be undone.
3252 undobuf.num_undo is incremented for such changes, so by testing that
3253 the caller can tell whether the result is valid.
3255 `n_occurrences' is incremented each time FROM is replaced.
3257 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3259 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3260 by copying if `n_occurrences' is non-zero. */
3263 subst (x
, from
, to
, in_dest
, unique_copy
)
3264 register rtx x
, from
, to
;
3268 register enum rtx_code code
= GET_CODE (x
);
3269 enum machine_mode op0_mode
= VOIDmode
;
3270 register const char *fmt
;
3271 register int len
, i
;
3274 /* Two expressions are equal if they are identical copies of a shared
3275 RTX or if they are both registers with the same register number
3278 #define COMBINE_RTX_EQUAL_P(X,Y) \
3280 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3281 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3283 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3286 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3289 /* If X and FROM are the same register but different modes, they will
3290 not have been seen as equal above. However, flow.c will make a
3291 LOG_LINKS entry for that case. If we do nothing, we will try to
3292 rerecognize our original insn and, when it succeeds, we will
3293 delete the feeding insn, which is incorrect.
3295 So force this insn not to match in this (rare) case. */
3296 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3297 && REGNO (x
) == REGNO (from
))
3298 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3300 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3301 of which may contain things that can be combined. */
3302 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3305 /* It is possible to have a subexpression appear twice in the insn.
3306 Suppose that FROM is a register that appears within TO.
3307 Then, after that subexpression has been scanned once by `subst',
3308 the second time it is scanned, TO may be found. If we were
3309 to scan TO here, we would find FROM within it and create a
3310 self-referent rtl structure which is completely wrong. */
3311 if (COMBINE_RTX_EQUAL_P (x
, to
))
3314 /* Parallel asm_operands need special attention because all of the
3315 inputs are shared across the arms. Furthermore, unsharing the
3316 rtl results in recognition failures. Failure to handle this case
3317 specially can result in circular rtl.
3319 Solve this by doing a normal pass across the first entry of the
3320 parallel, and only processing the SET_DESTs of the subsequent
3323 if (code
== PARALLEL
3324 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3325 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3327 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3329 /* If this substitution failed, this whole thing fails. */
3330 if (GET_CODE (new) == CLOBBER
3331 && XEXP (new, 0) == const0_rtx
)
3334 SUBST (XVECEXP (x
, 0, 0), new);
3336 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3338 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3340 if (GET_CODE (dest
) != REG
3341 && GET_CODE (dest
) != CC0
3342 && GET_CODE (dest
) != PC
)
3344 new = subst (dest
, from
, to
, 0, unique_copy
);
3346 /* If this substitution failed, this whole thing fails. */
3347 if (GET_CODE (new) == CLOBBER
3348 && XEXP (new, 0) == const0_rtx
)
3351 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3357 len
= GET_RTX_LENGTH (code
);
3358 fmt
= GET_RTX_FORMAT (code
);
3360 /* We don't need to process a SET_DEST that is a register, CC0,
3361 or PC, so set up to skip this common case. All other cases
3362 where we want to suppress replacing something inside a
3363 SET_SRC are handled via the IN_DEST operand. */
3365 && (GET_CODE (SET_DEST (x
)) == REG
3366 || GET_CODE (SET_DEST (x
)) == CC0
3367 || GET_CODE (SET_DEST (x
)) == PC
))
3370 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3373 op0_mode
= GET_MODE (XEXP (x
, 0));
3375 for (i
= 0; i
< len
; i
++)
3380 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3382 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3384 new = (unique_copy
&& n_occurrences
3385 ? copy_rtx (to
) : to
);
3390 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3393 /* If this substitution failed, this whole thing
3395 if (GET_CODE (new) == CLOBBER
3396 && XEXP (new, 0) == const0_rtx
)
3400 SUBST (XVECEXP (x
, i
, j
), new);
3403 else if (fmt
[i
] == 'e')
3405 /* If this is a register being set, ignore it. */
3408 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3409 || code
== ZERO_EXTRACT
)
3411 && GET_CODE (new) == REG
)
3414 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3416 /* In general, don't install a subreg involving two
3417 modes not tieable. It can worsen register
3418 allocation, and can even make invalid reload
3419 insns, since the reg inside may need to be copied
3420 from in the outside mode, and that may be invalid
3421 if it is an fp reg copied in integer mode.
3423 We allow two exceptions to this: It is valid if
3424 it is inside another SUBREG and the mode of that
3425 SUBREG and the mode of the inside of TO is
3426 tieable and it is valid if X is a SET that copies
3429 if (GET_CODE (to
) == SUBREG
3430 && ! MODES_TIEABLE_P (GET_MODE (to
),
3431 GET_MODE (SUBREG_REG (to
)))
3432 && ! (code
== SUBREG
3433 && MODES_TIEABLE_P (GET_MODE (x
),
3434 GET_MODE (SUBREG_REG (to
))))
3436 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3439 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3441 #ifdef CLASS_CANNOT_CHANGE_MODE
3443 && GET_CODE (to
) == REG
3444 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3445 && (TEST_HARD_REG_BIT
3446 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3448 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3450 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3453 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3457 /* If we are in a SET_DEST, suppress most cases unless we
3458 have gone inside a MEM, in which case we want to
3459 simplify the address. We assume here that things that
3460 are actually part of the destination have their inner
3461 parts in the first expression. This is true for SUBREG,
3462 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3463 things aside from REG and MEM that should appear in a
3465 new = subst (XEXP (x
, i
), from
, to
,
3467 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3468 || code
== ZERO_EXTRACT
))
3470 && i
== 0), unique_copy
);
3472 /* If we found that we will have to reject this combination,
3473 indicate that by returning the CLOBBER ourselves, rather than
3474 an expression containing it. This will speed things up as
3475 well as prevent accidents where two CLOBBERs are considered
3476 to be equal, thus producing an incorrect simplification. */
3478 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3481 SUBST (XEXP (x
, i
), new);
3486 /* Try to simplify X. If the simplification changed the code, it is likely
3487 that further simplification will help, so loop, but limit the number
3488 of repetitions that will be performed. */
3490 for (i
= 0; i
< 4; i
++)
3492 /* If X is sufficiently simple, don't bother trying to do anything
3494 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3495 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3497 if (GET_CODE (x
) == code
)
3500 code
= GET_CODE (x
);
3502 /* We no longer know the original mode of operand 0 since we
3503 have changed the form of X) */
3504 op0_mode
= VOIDmode
;
3510 /* Simplify X, a piece of RTL. We just operate on the expression at the
3511 outer level; call `subst' to simplify recursively. Return the new
3514 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3515 will be the iteration even if an expression with a code different from
3516 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3519 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3521 enum machine_mode op0_mode
;
3525 enum rtx_code code
= GET_CODE (x
);
3526 enum machine_mode mode
= GET_MODE (x
);
3531 /* If this is a commutative operation, put a constant last and a complex
3532 expression first. We don't need to do this for comparisons here. */
3533 if (GET_RTX_CLASS (code
) == 'c'
3534 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3537 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3538 SUBST (XEXP (x
, 1), temp
);
3541 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3542 sign extension of a PLUS with a constant, reverse the order of the sign
3543 extension and the addition. Note that this not the same as the original
3544 code, but overflow is undefined for signed values. Also note that the
3545 PLUS will have been partially moved "inside" the sign-extension, so that
3546 the first operand of X will really look like:
3547 (ashiftrt (plus (ashift A C4) C5) C4).
3549 (plus (ashiftrt (ashift A C4) C2) C4)
3550 and replace the first operand of X with that expression. Later parts
3551 of this function may simplify the expression further.
3553 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3554 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3555 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3557 We do this to simplify address expressions. */
3559 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3560 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3561 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3562 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3563 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3564 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3565 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3566 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3567 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3568 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3569 XEXP (XEXP (x
, 0), 1))) != 0)
3572 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3573 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3574 INTVAL (XEXP (XEXP (x
, 0), 1)));
3576 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3577 INTVAL (XEXP (XEXP (x
, 0), 1)));
3579 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3582 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3583 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3584 things. Check for cases where both arms are testing the same
3587 Don't do anything if all operands are very simple. */
3589 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3590 || GET_RTX_CLASS (code
) == '<')
3591 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3592 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3593 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3595 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3596 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3597 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3599 || (GET_RTX_CLASS (code
) == '1'
3600 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3601 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3602 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3605 rtx cond
, true_rtx
, false_rtx
;
3607 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3609 /* If everything is a comparison, what we have is highly unlikely
3610 to be simpler, so don't use it. */
3611 && ! (GET_RTX_CLASS (code
) == '<'
3612 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3613 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3615 rtx cop1
= const0_rtx
;
3616 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3618 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3621 /* Simplify the alternative arms; this may collapse the true and
3622 false arms to store-flag values. */
3623 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3624 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3626 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3627 is unlikely to be simpler. */
3628 if (general_operand (true_rtx
, VOIDmode
)
3629 && general_operand (false_rtx
, VOIDmode
))
3631 /* Restarting if we generate a store-flag expression will cause
3632 us to loop. Just drop through in this case. */
3634 /* If the result values are STORE_FLAG_VALUE and zero, we can
3635 just make the comparison operation. */
3636 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3637 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3638 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3639 && reverse_condition (cond_code
) != UNKNOWN
)
3640 x
= gen_binary (reverse_condition (cond_code
),
3643 /* Likewise, we can make the negate of a comparison operation
3644 if the result values are - STORE_FLAG_VALUE and zero. */
3645 else if (GET_CODE (true_rtx
) == CONST_INT
3646 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3647 && false_rtx
== const0_rtx
)
3648 x
= simplify_gen_unary (NEG
, mode
,
3649 gen_binary (cond_code
, mode
, cond
,
3652 else if (GET_CODE (false_rtx
) == CONST_INT
3653 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3654 && true_rtx
== const0_rtx
)
3655 x
= simplify_gen_unary (NEG
, mode
,
3656 gen_binary (reverse_condition
3661 return gen_rtx_IF_THEN_ELSE (mode
,
3662 gen_binary (cond_code
, VOIDmode
,
3664 true_rtx
, false_rtx
);
3666 code
= GET_CODE (x
);
3667 op0_mode
= VOIDmode
;
3672 /* Try to fold this expression in case we have constants that weren't
3675 switch (GET_RTX_CLASS (code
))
3678 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3682 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3683 if (cmp_mode
== VOIDmode
)
3685 cmp_mode
= GET_MODE (XEXP (x
, 1));
3686 if (cmp_mode
== VOIDmode
)
3687 cmp_mode
= op0_mode
;
3689 temp
= simplify_relational_operation (code
, cmp_mode
,
3690 XEXP (x
, 0), XEXP (x
, 1));
3692 #ifdef FLOAT_STORE_FLAG_VALUE
3693 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3695 if (temp
== const0_rtx
)
3696 temp
= CONST0_RTX (mode
);
3698 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3704 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3708 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3709 XEXP (x
, 1), XEXP (x
, 2));
3716 code
= GET_CODE (temp
);
3717 op0_mode
= VOIDmode
;
3718 mode
= GET_MODE (temp
);
3721 /* First see if we can apply the inverse distributive law. */
3722 if (code
== PLUS
|| code
== MINUS
3723 || code
== AND
|| code
== IOR
|| code
== XOR
)
3725 x
= apply_distributive_law (x
);
3726 code
= GET_CODE (x
);
3727 op0_mode
= VOIDmode
;
3730 /* If CODE is an associative operation not otherwise handled, see if we
3731 can associate some operands. This can win if they are constants or
3732 if they are logically related (i.e. (a & b) & a). */
3733 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3734 || code
== AND
|| code
== IOR
|| code
== XOR
3735 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3736 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3737 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3739 if (GET_CODE (XEXP (x
, 0)) == code
)
3741 rtx other
= XEXP (XEXP (x
, 0), 0);
3742 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3743 rtx inner_op1
= XEXP (x
, 1);
3746 /* Make sure we pass the constant operand if any as the second
3747 one if this is a commutative operation. */
3748 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3750 rtx tem
= inner_op0
;
3751 inner_op0
= inner_op1
;
3754 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3755 : code
== DIV
? MULT
3757 mode
, inner_op0
, inner_op1
);
3759 /* For commutative operations, try the other pair if that one
3761 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3763 other
= XEXP (XEXP (x
, 0), 1);
3764 inner
= simplify_binary_operation (code
, mode
,
3765 XEXP (XEXP (x
, 0), 0),
3770 return gen_binary (code
, mode
, other
, inner
);
3774 /* A little bit of algebraic simplification here. */
3778 /* Ensure that our address has any ASHIFTs converted to MULT in case
3779 address-recognizing predicates are called later. */
3780 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3781 SUBST (XEXP (x
, 0), temp
);
3785 if (op0_mode
== VOIDmode
)
3786 op0_mode
= GET_MODE (SUBREG_REG (x
));
3788 /* simplify_subreg can't use gen_lowpart_for_combine. */
3789 if (CONSTANT_P (SUBREG_REG (x
))
3790 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
))
3791 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3795 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3801 /* Note that we cannot do any narrowing for non-constants since
3802 we might have been counting on using the fact that some bits were
3803 zero. We now do this in the SET. */
3808 /* (not (plus X -1)) can become (neg X). */
3809 if (GET_CODE (XEXP (x
, 0)) == PLUS
3810 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3811 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3813 /* Similarly, (not (neg X)) is (plus X -1). */
3814 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3815 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3817 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3818 if (GET_CODE (XEXP (x
, 0)) == XOR
3819 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3820 && (temp
= simplify_unary_operation (NOT
, mode
,
3821 XEXP (XEXP (x
, 0), 1),
3823 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3825 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3826 other than 1, but that is not valid. We could do a similar
3827 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3828 but this doesn't seem common enough to bother with. */
3829 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3830 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3831 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3833 XEXP (XEXP (x
, 0), 1));
3835 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3836 && subreg_lowpart_p (XEXP (x
, 0))
3837 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3838 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3839 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3840 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3842 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3844 x
= gen_rtx_ROTATE (inner_mode
,
3845 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3847 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3848 return gen_lowpart_for_combine (mode
, x
);
3851 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3852 reversing the comparison code if valid. */
3853 if (STORE_FLAG_VALUE
== -1
3854 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3855 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3856 XEXP (XEXP (x
, 0), 1))))
3859 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3860 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3861 perform the above simplification. */
3863 if (STORE_FLAG_VALUE
== -1
3864 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3865 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3866 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3867 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3869 /* Apply De Morgan's laws to reduce number of patterns for machines
3870 with negating logical insns (and-not, nand, etc.). If result has
3871 only one NOT, put it first, since that is how the patterns are
3874 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3876 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3877 enum machine_mode op_mode
;
3879 op_mode
= GET_MODE (in1
);
3880 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3882 op_mode
= GET_MODE (in2
);
3883 if (op_mode
== VOIDmode
)
3885 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3887 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3890 in2
= in1
; in1
= tem
;
3893 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3899 /* (neg (plus X 1)) can become (not X). */
3900 if (GET_CODE (XEXP (x
, 0)) == PLUS
3901 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3902 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3904 /* Similarly, (neg (not X)) is (plus X 1). */
3905 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3906 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3908 /* (neg (minus X Y)) can become (minus Y X). */
3909 if (GET_CODE (XEXP (x
, 0)) == MINUS
3910 && (! FLOAT_MODE_P (mode
)
3911 /* x-y != -(y-x) with IEEE floating point. */
3912 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3913 || flag_unsafe_math_optimizations
))
3914 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3915 XEXP (XEXP (x
, 0), 0));
3917 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3918 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3919 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3920 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3922 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3923 if we can then eliminate the NEG (e.g.,
3924 if the operand is a constant). */
3926 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3928 temp
= simplify_unary_operation (NEG
, mode
,
3929 XEXP (XEXP (x
, 0), 0), mode
);
3931 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3934 temp
= expand_compound_operation (XEXP (x
, 0));
3936 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3937 replaced by (lshiftrt X C). This will convert
3938 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3940 if (GET_CODE (temp
) == ASHIFTRT
3941 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3942 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3943 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3944 INTVAL (XEXP (temp
, 1)));
3946 /* If X has only a single bit that might be nonzero, say, bit I, convert
3947 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3948 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3949 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3950 or a SUBREG of one since we'd be making the expression more
3951 complex if it was just a register. */
3953 if (GET_CODE (temp
) != REG
3954 && ! (GET_CODE (temp
) == SUBREG
3955 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3956 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3958 rtx temp1
= simplify_shift_const
3959 (NULL_RTX
, ASHIFTRT
, mode
,
3960 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3961 GET_MODE_BITSIZE (mode
) - 1 - i
),
3962 GET_MODE_BITSIZE (mode
) - 1 - i
);
3964 /* If all we did was surround TEMP with the two shifts, we
3965 haven't improved anything, so don't use it. Otherwise,
3966 we are better off with TEMP1. */
3967 if (GET_CODE (temp1
) != ASHIFTRT
3968 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3969 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3975 /* We can't handle truncation to a partial integer mode here
3976 because we don't know the real bitsize of the partial
3978 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3981 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3982 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3983 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3985 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3986 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3988 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3989 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3990 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3991 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3992 return XEXP (XEXP (x
, 0), 0);
3994 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3995 (OP:SI foo:SI) if OP is NEG or ABS. */
3996 if ((GET_CODE (XEXP (x
, 0)) == ABS
3997 || GET_CODE (XEXP (x
, 0)) == NEG
)
3998 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3999 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4000 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4001 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4002 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4004 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4006 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4007 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4008 && subreg_lowpart_p (XEXP (x
, 0)))
4009 return SUBREG_REG (XEXP (x
, 0));
4011 /* If we know that the value is already truncated, we can
4012 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4013 is nonzero for the corresponding modes. But don't do this
4014 for an (LSHIFTRT (MULT ...)) since this will cause problems
4015 with the umulXi3_highpart patterns. */
4016 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4017 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4018 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4019 >= GET_MODE_BITSIZE (mode
) + 1
4020 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4021 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4022 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4024 /* A truncate of a comparison can be replaced with a subreg if
4025 STORE_FLAG_VALUE permits. This is like the previous test,
4026 but it works even if the comparison is done in a mode larger
4027 than HOST_BITS_PER_WIDE_INT. */
4028 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4029 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4030 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4031 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4033 /* Similarly, a truncate of a register whose value is a
4034 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4036 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4037 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4038 && (temp
= get_last_value (XEXP (x
, 0)))
4039 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4040 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4044 case FLOAT_TRUNCATE
:
4045 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4046 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4047 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4048 return XEXP (XEXP (x
, 0), 0);
4050 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4051 (OP:SF foo:SF) if OP is NEG or ABS. */
4052 if ((GET_CODE (XEXP (x
, 0)) == ABS
4053 || GET_CODE (XEXP (x
, 0)) == NEG
)
4054 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4055 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4056 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4057 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4059 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4060 is (float_truncate:SF x). */
4061 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4062 && subreg_lowpart_p (XEXP (x
, 0))
4063 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4064 return SUBREG_REG (XEXP (x
, 0));
4069 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4070 using cc0, in which case we want to leave it as a COMPARE
4071 so we can distinguish it from a register-register-copy. */
4072 if (XEXP (x
, 1) == const0_rtx
)
4075 /* In IEEE floating point, x-0 is not the same as x. */
4076 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4077 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4078 || flag_unsafe_math_optimizations
)
4079 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4085 /* (const (const X)) can become (const X). Do it this way rather than
4086 returning the inner CONST since CONST can be shared with a
4088 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4089 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4094 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4095 can add in an offset. find_split_point will split this address up
4096 again if it doesn't match. */
4097 if (GET_CODE (XEXP (x
, 0)) == HIGH
4098 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4104 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4105 outermost. That's because that's the way indexed addresses are
4106 supposed to appear. This code used to check many more cases, but
4107 they are now checked elsewhere. */
4108 if (GET_CODE (XEXP (x
, 0)) == PLUS
4109 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4110 return gen_binary (PLUS
, mode
,
4111 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4113 XEXP (XEXP (x
, 0), 1));
4115 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4116 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4117 bit-field and can be replaced by either a sign_extend or a
4118 sign_extract. The `and' may be a zero_extend and the two
4119 <c>, -<c> constants may be reversed. */
4120 if (GET_CODE (XEXP (x
, 0)) == XOR
4121 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4122 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4123 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4124 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4125 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4126 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4127 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4128 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4129 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4130 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4131 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4132 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4133 == (unsigned int) i
+ 1))))
4134 return simplify_shift_const
4135 (NULL_RTX
, ASHIFTRT
, mode
,
4136 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4137 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4138 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4139 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4141 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4142 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4143 is 1. This produces better code than the alternative immediately
4145 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4146 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4147 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4148 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4149 XEXP (XEXP (x
, 0), 0),
4150 XEXP (XEXP (x
, 0), 1))))
4152 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4154 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4155 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4156 the bitsize of the mode - 1. This allows simplification of
4157 "a = (b & 8) == 0;" */
4158 if (XEXP (x
, 1) == constm1_rtx
4159 && GET_CODE (XEXP (x
, 0)) != REG
4160 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4161 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4162 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4163 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4164 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4165 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4166 GET_MODE_BITSIZE (mode
) - 1),
4167 GET_MODE_BITSIZE (mode
) - 1);
4169 /* If we are adding two things that have no bits in common, convert
4170 the addition into an IOR. This will often be further simplified,
4171 for example in cases like ((a & 1) + (a & 2)), which can
4174 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4175 && (nonzero_bits (XEXP (x
, 0), mode
)
4176 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4178 /* Try to simplify the expression further. */
4179 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4180 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4182 /* If we could, great. If not, do not go ahead with the IOR
4183 replacement, since PLUS appears in many special purpose
4184 address arithmetic instructions. */
4185 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4191 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4192 by reversing the comparison code if valid. */
4193 if (STORE_FLAG_VALUE
== 1
4194 && XEXP (x
, 0) == const1_rtx
4195 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4196 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4197 XEXP (XEXP (x
, 1), 0),
4198 XEXP (XEXP (x
, 1), 1))))
4201 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4202 (and <foo> (const_int pow2-1)) */
4203 if (GET_CODE (XEXP (x
, 1)) == AND
4204 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4205 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4206 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4207 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4208 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4210 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4212 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4213 return gen_binary (MINUS
, mode
,
4214 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4215 XEXP (XEXP (x
, 1), 0)),
4216 XEXP (XEXP (x
, 1), 1));
4220 /* If we have (mult (plus A B) C), apply the distributive law and then
4221 the inverse distributive law to see if things simplify. This
4222 occurs mostly in addresses, often when unrolling loops. */
4224 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4226 x
= apply_distributive_law
4227 (gen_binary (PLUS
, mode
,
4228 gen_binary (MULT
, mode
,
4229 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4230 gen_binary (MULT
, mode
,
4231 XEXP (XEXP (x
, 0), 1),
4232 copy_rtx (XEXP (x
, 1)))));
4234 if (GET_CODE (x
) != MULT
)
4237 /* Try simplify a*(b/c) as (a*b)/c. */
4238 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4239 && GET_CODE (XEXP (x
, 0)) == DIV
)
4241 rtx tem
= simplify_binary_operation (MULT
, mode
,
4242 XEXP (XEXP (x
, 0), 0),
4245 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4250 /* If this is a divide by a power of two, treat it as a shift if
4251 its first operand is a shift. */
4252 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4253 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4254 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4255 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4256 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4257 || GET_CODE (XEXP (x
, 0)) == ROTATE
4258 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4259 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4263 case GT
: case GTU
: case GE
: case GEU
:
4264 case LT
: case LTU
: case LE
: case LEU
:
4265 case UNEQ
: case LTGT
:
4266 case UNGT
: case UNGE
:
4267 case UNLT
: case UNLE
:
4268 case UNORDERED
: case ORDERED
:
4269 /* If the first operand is a condition code, we can't do anything
4271 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4272 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4274 && XEXP (x
, 0) != cc0_rtx
4278 rtx op0
= XEXP (x
, 0);
4279 rtx op1
= XEXP (x
, 1);
4280 enum rtx_code new_code
;
4282 if (GET_CODE (op0
) == COMPARE
)
4283 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4285 /* Simplify our comparison, if possible. */
4286 new_code
= simplify_comparison (code
, &op0
, &op1
);
4288 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4289 if only the low-order bit is possibly nonzero in X (such as when
4290 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4291 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4292 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4295 Remove any ZERO_EXTRACT we made when thinking this was a
4296 comparison. It may now be simpler to use, e.g., an AND. If a
4297 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4298 the call to make_compound_operation in the SET case. */
4300 if (STORE_FLAG_VALUE
== 1
4301 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4302 && op1
== const0_rtx
4303 && mode
== GET_MODE (op0
)
4304 && nonzero_bits (op0
, mode
) == 1)
4305 return gen_lowpart_for_combine (mode
,
4306 expand_compound_operation (op0
));
4308 else if (STORE_FLAG_VALUE
== 1
4309 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4310 && op1
== const0_rtx
4311 && mode
== GET_MODE (op0
)
4312 && (num_sign_bit_copies (op0
, mode
)
4313 == GET_MODE_BITSIZE (mode
)))
4315 op0
= expand_compound_operation (op0
);
4316 return simplify_gen_unary (NEG
, mode
,
4317 gen_lowpart_for_combine (mode
, op0
),
4321 else if (STORE_FLAG_VALUE
== 1
4322 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4323 && op1
== const0_rtx
4324 && mode
== GET_MODE (op0
)
4325 && nonzero_bits (op0
, mode
) == 1)
4327 op0
= expand_compound_operation (op0
);
4328 return gen_binary (XOR
, mode
,
4329 gen_lowpart_for_combine (mode
, op0
),
4333 else if (STORE_FLAG_VALUE
== 1
4334 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4335 && op1
== const0_rtx
4336 && mode
== GET_MODE (op0
)
4337 && (num_sign_bit_copies (op0
, mode
)
4338 == GET_MODE_BITSIZE (mode
)))
4340 op0
= expand_compound_operation (op0
);
4341 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4344 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4346 if (STORE_FLAG_VALUE
== -1
4347 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4348 && op1
== const0_rtx
4349 && (num_sign_bit_copies (op0
, mode
)
4350 == GET_MODE_BITSIZE (mode
)))
4351 return gen_lowpart_for_combine (mode
,
4352 expand_compound_operation (op0
));
4354 else if (STORE_FLAG_VALUE
== -1
4355 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4356 && op1
== const0_rtx
4357 && mode
== GET_MODE (op0
)
4358 && nonzero_bits (op0
, mode
) == 1)
4360 op0
= expand_compound_operation (op0
);
4361 return simplify_gen_unary (NEG
, mode
,
4362 gen_lowpart_for_combine (mode
, op0
),
4366 else if (STORE_FLAG_VALUE
== -1
4367 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4368 && op1
== const0_rtx
4369 && mode
== GET_MODE (op0
)
4370 && (num_sign_bit_copies (op0
, mode
)
4371 == GET_MODE_BITSIZE (mode
)))
4373 op0
= expand_compound_operation (op0
);
4374 return simplify_gen_unary (NOT
, mode
,
4375 gen_lowpart_for_combine (mode
, op0
),
4379 /* If X is 0/1, (eq X 0) is X-1. */
4380 else if (STORE_FLAG_VALUE
== -1
4381 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4382 && op1
== const0_rtx
4383 && mode
== GET_MODE (op0
)
4384 && nonzero_bits (op0
, mode
) == 1)
4386 op0
= expand_compound_operation (op0
);
4387 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4390 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4391 one bit that might be nonzero, we can convert (ne x 0) to
4392 (ashift x c) where C puts the bit in the sign bit. Remove any
4393 AND with STORE_FLAG_VALUE when we are done, since we are only
4394 going to test the sign bit. */
4395 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4396 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4397 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4398 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4399 && op1
== const0_rtx
4400 && mode
== GET_MODE (op0
)
4401 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4403 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4404 expand_compound_operation (op0
),
4405 GET_MODE_BITSIZE (mode
) - 1 - i
);
4406 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4412 /* If the code changed, return a whole new comparison. */
4413 if (new_code
!= code
)
4414 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4416 /* Otherwise, keep this operation, but maybe change its operands.
4417 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4418 SUBST (XEXP (x
, 0), op0
);
4419 SUBST (XEXP (x
, 1), op1
);
4424 return simplify_if_then_else (x
);
4430 /* If we are processing SET_DEST, we are done. */
4434 return expand_compound_operation (x
);
4437 return simplify_set (x
);
4442 return simplify_logical (x
, last
);
4445 /* (abs (neg <foo>)) -> (abs <foo>) */
4446 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4447 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4449 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4451 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4454 /* If operand is something known to be positive, ignore the ABS. */
4455 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4456 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4457 <= HOST_BITS_PER_WIDE_INT
)
4458 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4459 & ((HOST_WIDE_INT
) 1
4460 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4464 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4465 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4466 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4471 /* (ffs (*_extend <X>)) = (ffs <X>) */
4472 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4473 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4474 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4478 /* (float (sign_extend <X>)) = (float <X>). */
4479 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4480 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4488 /* If this is a shift by a constant amount, simplify it. */
4489 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4490 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4491 INTVAL (XEXP (x
, 1)));
4493 #ifdef SHIFT_COUNT_TRUNCATED
4494 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4496 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4498 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4507 rtx op0
= XEXP (x
, 0);
4508 rtx op1
= XEXP (x
, 1);
4511 if (GET_CODE (op1
) != PARALLEL
)
4513 len
= XVECLEN (op1
, 0);
4515 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4516 && GET_CODE (op0
) == VEC_CONCAT
)
4518 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4520 /* Try to find the element in the VEC_CONCAT. */
4523 if (GET_MODE (op0
) == GET_MODE (x
))
4525 if (GET_CODE (op0
) == VEC_CONCAT
)
4527 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4528 if (op0_size
< offset
)
4529 op0
= XEXP (op0
, 0);
4533 op0
= XEXP (op0
, 1);
4551 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4554 simplify_if_then_else (x
)
4557 enum machine_mode mode
= GET_MODE (x
);
4558 rtx cond
= XEXP (x
, 0);
4559 rtx true_rtx
= XEXP (x
, 1);
4560 rtx false_rtx
= XEXP (x
, 2);
4561 enum rtx_code true_code
= GET_CODE (cond
);
4562 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4565 enum rtx_code false_code
;
4568 /* Simplify storing of the truth value. */
4569 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4570 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4572 /* Also when the truth value has to be reversed. */
4574 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4575 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4579 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4580 in it is being compared against certain values. Get the true and false
4581 comparisons and see if that says anything about the value of each arm. */
4584 && ((false_code
= combine_reversed_comparison_code (cond
))
4586 && GET_CODE (XEXP (cond
, 0)) == REG
)
4589 rtx from
= XEXP (cond
, 0);
4590 rtx true_val
= XEXP (cond
, 1);
4591 rtx false_val
= true_val
;
4594 /* If FALSE_CODE is EQ, swap the codes and arms. */
4596 if (false_code
== EQ
)
4598 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4599 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4602 /* If we are comparing against zero and the expression being tested has
4603 only a single bit that might be nonzero, that is its value when it is
4604 not equal to zero. Similarly if it is known to be -1 or 0. */
4606 if (true_code
== EQ
&& true_val
== const0_rtx
4607 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4608 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4609 else if (true_code
== EQ
&& true_val
== const0_rtx
4610 && (num_sign_bit_copies (from
, GET_MODE (from
))
4611 == GET_MODE_BITSIZE (GET_MODE (from
))))
4612 false_code
= EQ
, false_val
= constm1_rtx
;
4614 /* Now simplify an arm if we know the value of the register in the
4615 branch and it is used in the arm. Be careful due to the potential
4616 of locally-shared RTL. */
4618 if (reg_mentioned_p (from
, true_rtx
))
4619 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4621 pc_rtx
, pc_rtx
, 0, 0);
4622 if (reg_mentioned_p (from
, false_rtx
))
4623 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4625 pc_rtx
, pc_rtx
, 0, 0);
4627 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4628 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4630 true_rtx
= XEXP (x
, 1);
4631 false_rtx
= XEXP (x
, 2);
4632 true_code
= GET_CODE (cond
);
4635 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4636 reversed, do so to avoid needing two sets of patterns for
4637 subtract-and-branch insns. Similarly if we have a constant in the true
4638 arm, the false arm is the same as the first operand of the comparison, or
4639 the false arm is more complicated than the true arm. */
4642 && combine_reversed_comparison_code (cond
) != UNKNOWN
4643 && (true_rtx
== pc_rtx
4644 || (CONSTANT_P (true_rtx
)
4645 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4646 || true_rtx
== const0_rtx
4647 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4648 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4649 || (GET_CODE (true_rtx
) == SUBREG
4650 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4651 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4652 || reg_mentioned_p (true_rtx
, false_rtx
)
4653 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4655 true_code
= reversed_comparison_code (cond
, NULL
);
4657 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4660 SUBST (XEXP (x
, 1), false_rtx
);
4661 SUBST (XEXP (x
, 2), true_rtx
);
4663 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4666 /* It is possible that the conditional has been simplified out. */
4667 true_code
= GET_CODE (cond
);
4668 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4671 /* If the two arms are identical, we don't need the comparison. */
4673 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4676 /* Convert a == b ? b : a to "a". */
4677 if (true_code
== EQ
&& ! side_effects_p (cond
)
4678 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4679 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4680 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4682 else if (true_code
== NE
&& ! side_effects_p (cond
)
4683 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4684 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4685 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4688 /* Look for cases where we have (abs x) or (neg (abs X)). */
4690 if (GET_MODE_CLASS (mode
) == MODE_INT
4691 && GET_CODE (false_rtx
) == NEG
4692 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4694 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4695 && ! side_effects_p (true_rtx
))
4700 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4704 simplify_gen_unary (NEG
, mode
,
4705 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4711 /* Look for MIN or MAX. */
4713 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4715 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4716 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4717 && ! side_effects_p (cond
))
4722 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4725 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4728 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4731 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4736 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4737 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4738 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4739 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4740 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4741 neither 1 or -1, but it isn't worth checking for. */
4743 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4744 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4746 rtx t
= make_compound_operation (true_rtx
, SET
);
4747 rtx f
= make_compound_operation (false_rtx
, SET
);
4748 rtx cond_op0
= XEXP (cond
, 0);
4749 rtx cond_op1
= XEXP (cond
, 1);
4750 enum rtx_code op
= NIL
, extend_op
= NIL
;
4751 enum machine_mode m
= mode
;
4752 rtx z
= 0, c1
= NULL_RTX
;
4754 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4755 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4756 || GET_CODE (t
) == ASHIFT
4757 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4758 && rtx_equal_p (XEXP (t
, 0), f
))
4759 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4761 /* If an identity-zero op is commutative, check whether there
4762 would be a match if we swapped the operands. */
4763 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4764 || GET_CODE (t
) == XOR
)
4765 && rtx_equal_p (XEXP (t
, 1), f
))
4766 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4767 else if (GET_CODE (t
) == SIGN_EXTEND
4768 && (GET_CODE (XEXP (t
, 0)) == PLUS
4769 || GET_CODE (XEXP (t
, 0)) == MINUS
4770 || GET_CODE (XEXP (t
, 0)) == IOR
4771 || GET_CODE (XEXP (t
, 0)) == XOR
4772 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4773 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4774 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4775 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4776 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4777 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4778 && (num_sign_bit_copies (f
, GET_MODE (f
))
4779 > (GET_MODE_BITSIZE (mode
)
4780 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4782 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4783 extend_op
= SIGN_EXTEND
;
4784 m
= GET_MODE (XEXP (t
, 0));
4786 else if (GET_CODE (t
) == SIGN_EXTEND
4787 && (GET_CODE (XEXP (t
, 0)) == PLUS
4788 || GET_CODE (XEXP (t
, 0)) == IOR
4789 || GET_CODE (XEXP (t
, 0)) == XOR
)
4790 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4791 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4792 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4793 && (num_sign_bit_copies (f
, GET_MODE (f
))
4794 > (GET_MODE_BITSIZE (mode
)
4795 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4797 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4798 extend_op
= SIGN_EXTEND
;
4799 m
= GET_MODE (XEXP (t
, 0));
4801 else if (GET_CODE (t
) == ZERO_EXTEND
4802 && (GET_CODE (XEXP (t
, 0)) == PLUS
4803 || GET_CODE (XEXP (t
, 0)) == MINUS
4804 || GET_CODE (XEXP (t
, 0)) == IOR
4805 || GET_CODE (XEXP (t
, 0)) == XOR
4806 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4807 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4808 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4809 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4810 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4811 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4812 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4813 && ((nonzero_bits (f
, GET_MODE (f
))
4814 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4817 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4818 extend_op
= ZERO_EXTEND
;
4819 m
= GET_MODE (XEXP (t
, 0));
4821 else if (GET_CODE (t
) == ZERO_EXTEND
4822 && (GET_CODE (XEXP (t
, 0)) == PLUS
4823 || GET_CODE (XEXP (t
, 0)) == IOR
4824 || GET_CODE (XEXP (t
, 0)) == XOR
)
4825 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4826 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4827 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4828 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4829 && ((nonzero_bits (f
, GET_MODE (f
))
4830 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4833 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4834 extend_op
= ZERO_EXTEND
;
4835 m
= GET_MODE (XEXP (t
, 0));
4840 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4841 pc_rtx
, pc_rtx
, 0, 0);
4842 temp
= gen_binary (MULT
, m
, temp
,
4843 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4844 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4845 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4847 if (extend_op
!= NIL
)
4848 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4854 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4855 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4856 negation of a single bit, we can convert this operation to a shift. We
4857 can actually do this more generally, but it doesn't seem worth it. */
4859 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4860 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4861 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4862 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4863 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4864 == GET_MODE_BITSIZE (mode
))
4865 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4867 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4868 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4873 /* Simplify X, a SET expression. Return the new expression. */
4879 rtx src
= SET_SRC (x
);
4880 rtx dest
= SET_DEST (x
);
4881 enum machine_mode mode
4882 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4886 /* (set (pc) (return)) gets written as (return). */
4887 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4890 /* Now that we know for sure which bits of SRC we are using, see if we can
4891 simplify the expression for the object knowing that we only need the
4894 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4896 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4897 SUBST (SET_SRC (x
), src
);
4900 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4901 the comparison result and try to simplify it unless we already have used
4902 undobuf.other_insn. */
4903 if ((GET_CODE (src
) == COMPARE
4908 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4909 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4910 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4911 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4913 enum rtx_code old_code
= GET_CODE (*cc_use
);
4914 enum rtx_code new_code
;
4916 int other_changed
= 0;
4917 enum machine_mode compare_mode
= GET_MODE (dest
);
4919 if (GET_CODE (src
) == COMPARE
)
4920 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4922 op0
= src
, op1
= const0_rtx
;
4924 /* Simplify our comparison, if possible. */
4925 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4927 #ifdef EXTRA_CC_MODES
4928 /* If this machine has CC modes other than CCmode, check to see if we
4929 need to use a different CC mode here. */
4930 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4931 #endif /* EXTRA_CC_MODES */
4933 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4934 /* If the mode changed, we have to change SET_DEST, the mode in the
4935 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4936 a hard register, just build new versions with the proper mode. If it
4937 is a pseudo, we lose unless it is only time we set the pseudo, in
4938 which case we can safely change its mode. */
4939 if (compare_mode
!= GET_MODE (dest
))
4941 unsigned int regno
= REGNO (dest
);
4942 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4944 if (regno
< FIRST_PSEUDO_REGISTER
4945 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4947 if (regno
>= FIRST_PSEUDO_REGISTER
)
4948 SUBST (regno_reg_rtx
[regno
], new_dest
);
4950 SUBST (SET_DEST (x
), new_dest
);
4951 SUBST (XEXP (*cc_use
, 0), new_dest
);
4959 /* If the code changed, we have to build a new comparison in
4960 undobuf.other_insn. */
4961 if (new_code
!= old_code
)
4963 unsigned HOST_WIDE_INT mask
;
4965 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
4968 /* If the only change we made was to change an EQ into an NE or
4969 vice versa, OP0 has only one bit that might be nonzero, and OP1
4970 is zero, check if changing the user of the condition code will
4971 produce a valid insn. If it won't, we can keep the original code
4972 in that insn by surrounding our operation with an XOR. */
4974 if (((old_code
== NE
&& new_code
== EQ
)
4975 || (old_code
== EQ
&& new_code
== NE
))
4976 && ! other_changed
&& op1
== const0_rtx
4977 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4978 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4980 rtx pat
= PATTERN (other_insn
), note
= 0;
4982 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4983 && ! check_asm_operands (pat
)))
4985 PUT_CODE (*cc_use
, old_code
);
4988 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4996 undobuf
.other_insn
= other_insn
;
4999 /* If we are now comparing against zero, change our source if
5000 needed. If we do not use cc0, we always have a COMPARE. */
5001 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5003 SUBST (SET_SRC (x
), op0
);
5009 /* Otherwise, if we didn't previously have a COMPARE in the
5010 correct mode, we need one. */
5011 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5013 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5018 /* Otherwise, update the COMPARE if needed. */
5019 SUBST (XEXP (src
, 0), op0
);
5020 SUBST (XEXP (src
, 1), op1
);
5025 /* Get SET_SRC in a form where we have placed back any
5026 compound expressions. Then do the checks below. */
5027 src
= make_compound_operation (src
, SET
);
5028 SUBST (SET_SRC (x
), src
);
5031 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5032 and X being a REG or (subreg (reg)), we may be able to convert this to
5033 (set (subreg:m2 x) (op)).
5035 We can always do this if M1 is narrower than M2 because that means that
5036 we only care about the low bits of the result.
5038 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5039 perform a narrower operation than requested since the high-order bits will
5040 be undefined. On machine where it is defined, this transformation is safe
5041 as long as M1 and M2 have the same number of words. */
5043 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5044 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5045 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5047 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5048 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5049 #ifndef WORD_REGISTER_OPERATIONS
5050 && (GET_MODE_SIZE (GET_MODE (src
))
5051 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5053 #ifdef CLASS_CANNOT_CHANGE_MODE
5054 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5055 && (TEST_HARD_REG_BIT
5056 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5058 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5059 GET_MODE (SUBREG_REG (src
))))
5061 && (GET_CODE (dest
) == REG
5062 || (GET_CODE (dest
) == SUBREG
5063 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5065 SUBST (SET_DEST (x
),
5066 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5068 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5070 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5073 #ifdef LOAD_EXTEND_OP
5074 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5075 would require a paradoxical subreg. Replace the subreg with a
5076 zero_extend to avoid the reload that would otherwise be required. */
5078 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5079 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5080 && SUBREG_BYTE (src
) == 0
5081 && (GET_MODE_SIZE (GET_MODE (src
))
5082 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5083 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5086 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5087 GET_MODE (src
), SUBREG_REG (src
)));
5093 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5094 are comparing an item known to be 0 or -1 against 0, use a logical
5095 operation instead. Check for one of the arms being an IOR of the other
5096 arm with some value. We compute three terms to be IOR'ed together. In
5097 practice, at most two will be nonzero. Then we do the IOR's. */
5099 if (GET_CODE (dest
) != PC
5100 && GET_CODE (src
) == IF_THEN_ELSE
5101 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5102 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5103 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5104 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5105 #ifdef HAVE_conditional_move
5106 && ! can_conditionally_move_p (GET_MODE (src
))
5108 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5109 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5110 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5111 && ! side_effects_p (src
))
5113 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5114 ? XEXP (src
, 1) : XEXP (src
, 2));
5115 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5116 ? XEXP (src
, 2) : XEXP (src
, 1));
5117 rtx term1
= const0_rtx
, term2
, term3
;
5119 if (GET_CODE (true_rtx
) == IOR
5120 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5121 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5122 else if (GET_CODE (true_rtx
) == IOR
5123 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5124 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5125 else if (GET_CODE (false_rtx
) == IOR
5126 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5127 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5128 else if (GET_CODE (false_rtx
) == IOR
5129 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5130 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5132 term2
= gen_binary (AND
, GET_MODE (src
),
5133 XEXP (XEXP (src
, 0), 0), true_rtx
);
5134 term3
= gen_binary (AND
, GET_MODE (src
),
5135 simplify_gen_unary (NOT
, GET_MODE (src
),
5136 XEXP (XEXP (src
, 0), 0),
5141 gen_binary (IOR
, GET_MODE (src
),
5142 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5148 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5149 whole thing fail. */
5150 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5152 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5155 /* Convert this into a field assignment operation, if possible. */
5156 return make_field_assignment (x
);
5159 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5160 result. LAST is nonzero if this is the last retry. */
5163 simplify_logical (x
, last
)
5167 enum machine_mode mode
= GET_MODE (x
);
5168 rtx op0
= XEXP (x
, 0);
5169 rtx op1
= XEXP (x
, 1);
5172 switch (GET_CODE (x
))
5175 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5176 insn (and may simplify more). */
5177 if (GET_CODE (op0
) == XOR
5178 && rtx_equal_p (XEXP (op0
, 0), op1
)
5179 && ! side_effects_p (op1
))
5180 x
= gen_binary (AND
, mode
,
5181 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5184 if (GET_CODE (op0
) == XOR
5185 && rtx_equal_p (XEXP (op0
, 1), op1
)
5186 && ! side_effects_p (op1
))
5187 x
= gen_binary (AND
, mode
,
5188 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5191 /* Similarly for (~(A ^ B)) & A. */
5192 if (GET_CODE (op0
) == NOT
5193 && GET_CODE (XEXP (op0
, 0)) == XOR
5194 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5195 && ! side_effects_p (op1
))
5196 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5198 if (GET_CODE (op0
) == NOT
5199 && GET_CODE (XEXP (op0
, 0)) == XOR
5200 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5201 && ! side_effects_p (op1
))
5202 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5204 /* We can call simplify_and_const_int only if we don't lose
5205 any (sign) bits when converting INTVAL (op1) to
5206 "unsigned HOST_WIDE_INT". */
5207 if (GET_CODE (op1
) == CONST_INT
5208 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5209 || INTVAL (op1
) > 0))
5211 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5213 /* If we have (ior (and (X C1) C2)) and the next restart would be
5214 the last, simplify this by making C1 as small as possible
5217 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5218 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5219 && GET_CODE (op1
) == CONST_INT
)
5220 return gen_binary (IOR
, mode
,
5221 gen_binary (AND
, mode
, XEXP (op0
, 0),
5222 GEN_INT (INTVAL (XEXP (op0
, 1))
5223 & ~INTVAL (op1
))), op1
);
5225 if (GET_CODE (x
) != AND
)
5228 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5229 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5230 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5233 /* Convert (A | B) & A to A. */
5234 if (GET_CODE (op0
) == IOR
5235 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5236 || rtx_equal_p (XEXP (op0
, 1), op1
))
5237 && ! side_effects_p (XEXP (op0
, 0))
5238 && ! side_effects_p (XEXP (op0
, 1)))
5241 /* In the following group of tests (and those in case IOR below),
5242 we start with some combination of logical operations and apply
5243 the distributive law followed by the inverse distributive law.
5244 Most of the time, this results in no change. However, if some of
5245 the operands are the same or inverses of each other, simplifications
5248 For example, (and (ior A B) (not B)) can occur as the result of
5249 expanding a bit field assignment. When we apply the distributive
5250 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5251 which then simplifies to (and (A (not B))).
5253 If we have (and (ior A B) C), apply the distributive law and then
5254 the inverse distributive law to see if things simplify. */
5256 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5258 x
= apply_distributive_law
5259 (gen_binary (GET_CODE (op0
), mode
,
5260 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5261 gen_binary (AND
, mode
, XEXP (op0
, 1),
5263 if (GET_CODE (x
) != AND
)
5267 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5268 return apply_distributive_law
5269 (gen_binary (GET_CODE (op1
), mode
,
5270 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5271 gen_binary (AND
, mode
, XEXP (op1
, 1),
5274 /* Similarly, taking advantage of the fact that
5275 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5277 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5278 return apply_distributive_law
5279 (gen_binary (XOR
, mode
,
5280 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5281 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5284 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5285 return apply_distributive_law
5286 (gen_binary (XOR
, mode
,
5287 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5288 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5292 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5293 if (GET_CODE (op1
) == CONST_INT
5294 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5295 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5298 /* Convert (A & B) | A to A. */
5299 if (GET_CODE (op0
) == AND
5300 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5301 || rtx_equal_p (XEXP (op0
, 1), op1
))
5302 && ! side_effects_p (XEXP (op0
, 0))
5303 && ! side_effects_p (XEXP (op0
, 1)))
5306 /* If we have (ior (and A B) C), apply the distributive law and then
5307 the inverse distributive law to see if things simplify. */
5309 if (GET_CODE (op0
) == AND
)
5311 x
= apply_distributive_law
5312 (gen_binary (AND
, mode
,
5313 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5314 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5317 if (GET_CODE (x
) != IOR
)
5321 if (GET_CODE (op1
) == AND
)
5323 x
= apply_distributive_law
5324 (gen_binary (AND
, mode
,
5325 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5326 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5329 if (GET_CODE (x
) != IOR
)
5333 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5334 mode size to (rotate A CX). */
5336 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5337 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5338 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5339 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5340 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5341 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5342 == GET_MODE_BITSIZE (mode
)))
5343 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5344 (GET_CODE (op0
) == ASHIFT
5345 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5347 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5348 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5349 does not affect any of the bits in OP1, it can really be done
5350 as a PLUS and we can associate. We do this by seeing if OP1
5351 can be safely shifted left C bits. */
5352 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5353 && GET_CODE (XEXP (op0
, 0)) == PLUS
5354 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5355 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5356 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5358 int count
= INTVAL (XEXP (op0
, 1));
5359 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5361 if (mask
>> count
== INTVAL (op1
)
5362 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5364 SUBST (XEXP (XEXP (op0
, 0), 1),
5365 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5372 /* If we are XORing two things that have no bits in common,
5373 convert them into an IOR. This helps to detect rotation encoded
5374 using those methods and possibly other simplifications. */
5376 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5377 && (nonzero_bits (op0
, mode
)
5378 & nonzero_bits (op1
, mode
)) == 0)
5379 return (gen_binary (IOR
, mode
, op0
, op1
));
5381 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5382 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5385 int num_negated
= 0;
5387 if (GET_CODE (op0
) == NOT
)
5388 num_negated
++, op0
= XEXP (op0
, 0);
5389 if (GET_CODE (op1
) == NOT
)
5390 num_negated
++, op1
= XEXP (op1
, 0);
5392 if (num_negated
== 2)
5394 SUBST (XEXP (x
, 0), op0
);
5395 SUBST (XEXP (x
, 1), op1
);
5397 else if (num_negated
== 1)
5399 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5403 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5404 correspond to a machine insn or result in further simplifications
5405 if B is a constant. */
5407 if (GET_CODE (op0
) == AND
5408 && rtx_equal_p (XEXP (op0
, 1), op1
)
5409 && ! side_effects_p (op1
))
5410 return gen_binary (AND
, mode
,
5411 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5414 else if (GET_CODE (op0
) == AND
5415 && rtx_equal_p (XEXP (op0
, 0), op1
)
5416 && ! side_effects_p (op1
))
5417 return gen_binary (AND
, mode
,
5418 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5421 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5422 comparison if STORE_FLAG_VALUE is 1. */
5423 if (STORE_FLAG_VALUE
== 1
5424 && op1
== const1_rtx
5425 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5426 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5430 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5431 is (lt foo (const_int 0)), so we can perform the above
5432 simplification if STORE_FLAG_VALUE is 1. */
5434 if (STORE_FLAG_VALUE
== 1
5435 && op1
== const1_rtx
5436 && GET_CODE (op0
) == LSHIFTRT
5437 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5438 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5439 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5441 /* (xor (comparison foo bar) (const_int sign-bit))
5442 when STORE_FLAG_VALUE is the sign bit. */
5443 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5444 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5445 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5446 && op1
== const_true_rtx
5447 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5448 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5461 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5462 operations" because they can be replaced with two more basic operations.
5463 ZERO_EXTEND is also considered "compound" because it can be replaced with
5464 an AND operation, which is simpler, though only one operation.
5466 The function expand_compound_operation is called with an rtx expression
5467 and will convert it to the appropriate shifts and AND operations,
5468 simplifying at each stage.
5470 The function make_compound_operation is called to convert an expression
5471 consisting of shifts and ANDs into the equivalent compound expression.
5472 It is the inverse of this function, loosely speaking. */
5475 expand_compound_operation (x
)
5478 unsigned HOST_WIDE_INT pos
= 0, len
;
5480 unsigned int modewidth
;
5483 switch (GET_CODE (x
))
5488 /* We can't necessarily use a const_int for a multiword mode;
5489 it depends on implicitly extending the value.
5490 Since we don't know the right way to extend it,
5491 we can't tell whether the implicit way is right.
5493 Even for a mode that is no wider than a const_int,
5494 we can't win, because we need to sign extend one of its bits through
5495 the rest of it, and we don't know which bit. */
5496 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5499 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5500 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5501 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5502 reloaded. If not for that, MEM's would very rarely be safe.
5504 Reject MODEs bigger than a word, because we might not be able
5505 to reference a two-register group starting with an arbitrary register
5506 (and currently gen_lowpart might crash for a SUBREG). */
5508 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5511 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5512 /* If the inner object has VOIDmode (the only way this can happen
5513 is if it is a ASM_OPERANDS), we can't do anything since we don't
5514 know how much masking to do. */
5523 /* If the operand is a CLOBBER, just return it. */
5524 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5527 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5528 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5529 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5532 len
= INTVAL (XEXP (x
, 1));
5533 pos
= INTVAL (XEXP (x
, 2));
5535 /* If this goes outside the object being extracted, replace the object
5536 with a (use (mem ...)) construct that only combine understands
5537 and is used only for this purpose. */
5538 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5539 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5541 if (BITS_BIG_ENDIAN
)
5542 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5549 /* Convert sign extension to zero extension, if we know that the high
5550 bit is not set, as this is easier to optimize. It will be converted
5551 back to cheaper alternative in make_extraction. */
5552 if (GET_CODE (x
) == SIGN_EXTEND
5553 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5554 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5555 & ~(((unsigned HOST_WIDE_INT
)
5556 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5560 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5561 return expand_compound_operation (temp
);
5564 /* We can optimize some special cases of ZERO_EXTEND. */
5565 if (GET_CODE (x
) == ZERO_EXTEND
)
5567 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5568 know that the last value didn't have any inappropriate bits
5570 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5571 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5572 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5573 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5574 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5575 return XEXP (XEXP (x
, 0), 0);
5577 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5578 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5579 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5580 && subreg_lowpart_p (XEXP (x
, 0))
5581 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5582 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5583 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5584 return SUBREG_REG (XEXP (x
, 0));
5586 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5587 is a comparison and STORE_FLAG_VALUE permits. This is like
5588 the first case, but it works even when GET_MODE (x) is larger
5589 than HOST_WIDE_INT. */
5590 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5591 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5592 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5593 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5594 <= HOST_BITS_PER_WIDE_INT
)
5595 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5596 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5597 return XEXP (XEXP (x
, 0), 0);
5599 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5600 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5601 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5602 && subreg_lowpart_p (XEXP (x
, 0))
5603 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5604 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5605 <= HOST_BITS_PER_WIDE_INT
)
5606 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5607 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5608 return SUBREG_REG (XEXP (x
, 0));
5612 /* If we reach here, we want to return a pair of shifts. The inner
5613 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5614 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5615 logical depending on the value of UNSIGNEDP.
5617 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5618 converted into an AND of a shift.
5620 We must check for the case where the left shift would have a negative
5621 count. This can happen in a case like (x >> 31) & 255 on machines
5622 that can't shift by a constant. On those machines, we would first
5623 combine the shift with the AND to produce a variable-position
5624 extraction. Then the constant of 31 would be substituted in to produce
5625 a such a position. */
5627 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5628 if (modewidth
+ len
>= pos
)
5629 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5631 simplify_shift_const (NULL_RTX
, ASHIFT
,
5634 modewidth
- pos
- len
),
5637 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5638 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5639 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5642 ((HOST_WIDE_INT
) 1 << len
) - 1);
5644 /* Any other cases we can't handle. */
5647 /* If we couldn't do this for some reason, return the original
5649 if (GET_CODE (tem
) == CLOBBER
)
5655 /* X is a SET which contains an assignment of one object into
5656 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5657 or certain SUBREGS). If possible, convert it into a series of
5660 We half-heartedly support variable positions, but do not at all
5661 support variable lengths. */
5664 expand_field_assignment (x
)
5668 rtx pos
; /* Always counts from low bit. */
5671 enum machine_mode compute_mode
;
5673 /* Loop until we find something we can't simplify. */
5676 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5677 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5679 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5681 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5682 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5683 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5685 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5686 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5688 inner
= XEXP (SET_DEST (x
), 0);
5689 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5690 pos
= XEXP (SET_DEST (x
), 2);
5692 /* If the position is constant and spans the width of INNER,
5693 surround INNER with a USE to indicate this. */
5694 if (GET_CODE (pos
) == CONST_INT
5695 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5696 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5698 if (BITS_BIG_ENDIAN
)
5700 if (GET_CODE (pos
) == CONST_INT
)
5701 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5703 else if (GET_CODE (pos
) == MINUS
5704 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5705 && (INTVAL (XEXP (pos
, 1))
5706 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5707 /* If position is ADJUST - X, new position is X. */
5708 pos
= XEXP (pos
, 0);
5710 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5711 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5717 /* A SUBREG between two modes that occupy the same numbers of words
5718 can be done by moving the SUBREG to the source. */
5719 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5720 /* We need SUBREGs to compute nonzero_bits properly. */
5721 && nonzero_sign_valid
5722 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5723 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5724 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5725 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5727 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5728 gen_lowpart_for_combine
5729 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5736 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5737 inner
= SUBREG_REG (inner
);
5739 compute_mode
= GET_MODE (inner
);
5741 /* Don't attempt bitwise arithmetic on non-integral modes. */
5742 if (! INTEGRAL_MODE_P (compute_mode
))
5744 enum machine_mode imode
;
5746 /* Something is probably seriously wrong if this matches. */
5747 if (! FLOAT_MODE_P (compute_mode
))
5750 /* Try to find an integral mode to pun with. */
5751 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5752 if (imode
== BLKmode
)
5755 compute_mode
= imode
;
5756 inner
= gen_lowpart_for_combine (imode
, inner
);
5759 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5760 if (len
< HOST_BITS_PER_WIDE_INT
)
5761 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5765 /* Now compute the equivalent expression. Make a copy of INNER
5766 for the SET_DEST in case it is a MEM into which we will substitute;
5767 we don't want shared RTL in that case. */
5769 (VOIDmode
, copy_rtx (inner
),
5770 gen_binary (IOR
, compute_mode
,
5771 gen_binary (AND
, compute_mode
,
5772 simplify_gen_unary (NOT
, compute_mode
,
5778 gen_binary (ASHIFT
, compute_mode
,
5779 gen_binary (AND
, compute_mode
,
5780 gen_lowpart_for_combine
5781 (compute_mode
, SET_SRC (x
)),
5789 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5790 it is an RTX that represents a variable starting position; otherwise,
5791 POS is the (constant) starting bit position (counted from the LSB).
5793 INNER may be a USE. This will occur when we started with a bitfield
5794 that went outside the boundary of the object in memory, which is
5795 allowed on most machines. To isolate this case, we produce a USE
5796 whose mode is wide enough and surround the MEM with it. The only
5797 code that understands the USE is this routine. If it is not removed,
5798 it will cause the resulting insn not to match.
5800 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5803 IN_DEST is non-zero if this is a reference in the destination of a
5804 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5805 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5808 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5809 ZERO_EXTRACT should be built even for bits starting at bit 0.
5811 MODE is the desired mode of the result (if IN_DEST == 0).
5813 The result is an RTX for the extraction or NULL_RTX if the target
5817 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5818 unsignedp
, in_dest
, in_compare
)
5819 enum machine_mode mode
;
5823 unsigned HOST_WIDE_INT len
;
5825 int in_dest
, in_compare
;
5827 /* This mode describes the size of the storage area
5828 to fetch the overall value from. Within that, we
5829 ignore the POS lowest bits, etc. */
5830 enum machine_mode is_mode
= GET_MODE (inner
);
5831 enum machine_mode inner_mode
;
5832 enum machine_mode wanted_inner_mode
= byte_mode
;
5833 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5834 enum machine_mode pos_mode
= word_mode
;
5835 enum machine_mode extraction_mode
= word_mode
;
5836 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5839 rtx orig_pos_rtx
= pos_rtx
;
5840 HOST_WIDE_INT orig_pos
;
5842 /* Get some information about INNER and get the innermost object. */
5843 if (GET_CODE (inner
) == USE
)
5844 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5845 /* We don't need to adjust the position because we set up the USE
5846 to pretend that it was a full-word object. */
5847 spans_byte
= 1, inner
= XEXP (inner
, 0);
5848 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5850 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5851 consider just the QI as the memory to extract from.
5852 The subreg adds or removes high bits; its mode is
5853 irrelevant to the meaning of this extraction,
5854 since POS and LEN count from the lsb. */
5855 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5856 is_mode
= GET_MODE (SUBREG_REG (inner
));
5857 inner
= SUBREG_REG (inner
);
5860 inner_mode
= GET_MODE (inner
);
5862 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5863 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5865 /* See if this can be done without an extraction. We never can if the
5866 width of the field is not the same as that of some integer mode. For
5867 registers, we can only avoid the extraction if the position is at the
5868 low-order bit and this is either not in the destination or we have the
5869 appropriate STRICT_LOW_PART operation available.
5871 For MEM, we can avoid an extract if the field starts on an appropriate
5872 boundary and we can change the mode of the memory reference. However,
5873 we cannot directly access the MEM if we have a USE and the underlying
5874 MEM is not TMODE. This combination means that MEM was being used in a
5875 context where bits outside its mode were being referenced; that is only
5876 valid in bit-field insns. */
5878 if (tmode
!= BLKmode
5879 && ! (spans_byte
&& inner_mode
!= tmode
)
5880 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5881 && GET_CODE (inner
) != MEM
5883 || (GET_CODE (inner
) == REG
5884 && have_insn_for (STRICT_LOW_PART
, tmode
))))
5885 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5887 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5888 : BITS_PER_UNIT
)) == 0
5889 /* We can't do this if we are widening INNER_MODE (it
5890 may not be aligned, for one thing). */
5891 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5892 && (inner_mode
== tmode
5893 || (! mode_dependent_address_p (XEXP (inner
, 0))
5894 && ! MEM_VOLATILE_P (inner
))))))
5896 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5897 field. If the original and current mode are the same, we need not
5898 adjust the offset. Otherwise, we do if bytes big endian.
5900 If INNER is not a MEM, get a piece consisting of just the field
5901 of interest (in this case POS % BITS_PER_WORD must be 0). */
5903 if (GET_CODE (inner
) == MEM
)
5905 HOST_WIDE_INT offset
;
5907 /* POS counts from lsb, but make OFFSET count in memory order. */
5908 if (BYTES_BIG_ENDIAN
)
5909 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5911 offset
= pos
/ BITS_PER_UNIT
;
5913 new = adjust_address_nv (inner
, tmode
, offset
);
5915 else if (GET_CODE (inner
) == REG
)
5917 /* We can't call gen_lowpart_for_combine here since we always want
5918 a SUBREG and it would sometimes return a new hard register. */
5919 if (tmode
!= inner_mode
)
5921 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
5923 if (WORDS_BIG_ENDIAN
5924 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
5925 final_word
= ((GET_MODE_SIZE (inner_mode
)
5926 - GET_MODE_SIZE (tmode
))
5927 / UNITS_PER_WORD
) - final_word
;
5929 final_word
*= UNITS_PER_WORD
;
5930 if (BYTES_BIG_ENDIAN
&&
5931 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
5932 final_word
+= (GET_MODE_SIZE (inner_mode
)
5933 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
5935 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
5941 new = force_to_mode (inner
, tmode
,
5942 len
>= HOST_BITS_PER_WIDE_INT
5943 ? ~(unsigned HOST_WIDE_INT
) 0
5944 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5947 /* If this extraction is going into the destination of a SET,
5948 make a STRICT_LOW_PART unless we made a MEM. */
5951 return (GET_CODE (new) == MEM
? new
5952 : (GET_CODE (new) != SUBREG
5953 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5954 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
5959 /* If we know that no extraneous bits are set, and that the high
5960 bit is not set, convert the extraction to the cheaper of
5961 sign and zero extension, that are equivalent in these cases. */
5962 if (flag_expensive_optimizations
5963 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5964 && ((nonzero_bits (new, tmode
)
5965 & ~(((unsigned HOST_WIDE_INT
)
5966 GET_MODE_MASK (tmode
))
5970 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5971 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5973 /* Prefer ZERO_EXTENSION, since it gives more information to
5975 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
5980 /* Otherwise, sign- or zero-extend unless we already are in the
5983 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5987 /* Unless this is a COMPARE or we have a funny memory reference,
5988 don't do anything with zero-extending field extracts starting at
5989 the low-order bit since they are simple AND operations. */
5990 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5991 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5994 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5995 we would be spanning bytes or if the position is not a constant and the
5996 length is not 1. In all other cases, we would only be going outside
5997 our object in cases when an original shift would have been
5999 if (! spans_byte
&& GET_CODE (inner
) == MEM
6000 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6001 || (pos_rtx
!= 0 && len
!= 1)))
6004 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6005 and the mode for the result. */
6006 if (in_dest
&& mode_for_extraction(EP_insv
, -1) != MAX_MACHINE_MODE
)
6008 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6009 pos_mode
= mode_for_extraction (EP_insv
, 2);
6010 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6013 if (! in_dest
&& unsignedp
6014 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6016 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6017 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6018 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6021 if (! in_dest
&& ! unsignedp
6022 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6024 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6025 pos_mode
= mode_for_extraction (EP_extv
, 3);
6026 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6029 /* Never narrow an object, since that might not be safe. */
6031 if (mode
!= VOIDmode
6032 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6033 extraction_mode
= mode
;
6035 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6036 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6037 pos_mode
= GET_MODE (pos_rtx
);
6039 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6040 if we have to change the mode of memory and cannot, the desired mode is
6042 if (GET_CODE (inner
) != MEM
)
6043 wanted_inner_mode
= wanted_inner_reg_mode
;
6044 else if (inner_mode
!= wanted_inner_mode
6045 && (mode_dependent_address_p (XEXP (inner
, 0))
6046 || MEM_VOLATILE_P (inner
)))
6047 wanted_inner_mode
= extraction_mode
;
6051 if (BITS_BIG_ENDIAN
)
6053 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6054 BITS_BIG_ENDIAN style. If position is constant, compute new
6055 position. Otherwise, build subtraction.
6056 Note that POS is relative to the mode of the original argument.
6057 If it's a MEM we need to recompute POS relative to that.
6058 However, if we're extracting from (or inserting into) a register,
6059 we want to recompute POS relative to wanted_inner_mode. */
6060 int width
= (GET_CODE (inner
) == MEM
6061 ? GET_MODE_BITSIZE (is_mode
)
6062 : GET_MODE_BITSIZE (wanted_inner_mode
));
6065 pos
= width
- len
- pos
;
6068 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6069 /* POS may be less than 0 now, but we check for that below.
6070 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6073 /* If INNER has a wider mode, make it smaller. If this is a constant
6074 extract, try to adjust the byte to point to the byte containing
6076 if (wanted_inner_mode
!= VOIDmode
6077 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6078 && ((GET_CODE (inner
) == MEM
6079 && (inner_mode
== wanted_inner_mode
6080 || (! mode_dependent_address_p (XEXP (inner
, 0))
6081 && ! MEM_VOLATILE_P (inner
))))))
6085 /* The computations below will be correct if the machine is big
6086 endian in both bits and bytes or little endian in bits and bytes.
6087 If it is mixed, we must adjust. */
6089 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6090 adjust OFFSET to compensate. */
6091 if (BYTES_BIG_ENDIAN
6093 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6094 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6096 /* If this is a constant position, we can move to the desired byte. */
6099 offset
+= pos
/ BITS_PER_UNIT
;
6100 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6103 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6105 && is_mode
!= wanted_inner_mode
)
6106 offset
= (GET_MODE_SIZE (is_mode
)
6107 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6109 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6110 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6113 /* If INNER is not memory, we can always get it into the proper mode. If we
6114 are changing its mode, POS must be a constant and smaller than the size
6116 else if (GET_CODE (inner
) != MEM
)
6118 if (GET_MODE (inner
) != wanted_inner_mode
6120 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6123 inner
= force_to_mode (inner
, wanted_inner_mode
,
6125 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6126 ? ~(unsigned HOST_WIDE_INT
) 0
6127 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6132 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6133 have to zero extend. Otherwise, we can just use a SUBREG. */
6135 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6137 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6139 /* If we know that no extraneous bits are set, and that the high
6140 bit is not set, convert extraction to cheaper one - eighter
6141 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6143 if (flag_expensive_optimizations
6144 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6145 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6146 & ~(((unsigned HOST_WIDE_INT
)
6147 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6151 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6153 /* Prefer ZERO_EXTENSION, since it gives more information to
6155 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6160 else if (pos_rtx
!= 0
6161 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6162 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6164 /* Make POS_RTX unless we already have it and it is correct. If we don't
6165 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6167 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6168 pos_rtx
= orig_pos_rtx
;
6170 else if (pos_rtx
== 0)
6171 pos_rtx
= GEN_INT (pos
);
6173 /* Make the required operation. See if we can use existing rtx. */
6174 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6175 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6177 new = gen_lowpart_for_combine (mode
, new);
6182 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6183 with any other operations in X. Return X without that shift if so. */
6186 extract_left_shift (x
, count
)
6190 enum rtx_code code
= GET_CODE (x
);
6191 enum machine_mode mode
= GET_MODE (x
);
6197 /* This is the shift itself. If it is wide enough, we will return
6198 either the value being shifted if the shift count is equal to
6199 COUNT or a shift for the difference. */
6200 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6201 && INTVAL (XEXP (x
, 1)) >= count
)
6202 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6203 INTVAL (XEXP (x
, 1)) - count
);
6207 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6208 return simplify_gen_unary (code
, mode
, tem
, mode
);
6212 case PLUS
: case IOR
: case XOR
: case AND
:
6213 /* If we can safely shift this constant and we find the inner shift,
6214 make a new operation. */
6215 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6216 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6217 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6218 return gen_binary (code
, mode
, tem
,
6219 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6230 /* Look at the expression rooted at X. Look for expressions
6231 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6232 Form these expressions.
6234 Return the new rtx, usually just X.
6236 Also, for machines like the VAX that don't have logical shift insns,
6237 try to convert logical to arithmetic shift operations in cases where
6238 they are equivalent. This undoes the canonicalizations to logical
6239 shifts done elsewhere.
6241 We try, as much as possible, to re-use rtl expressions to save memory.
6243 IN_CODE says what kind of expression we are processing. Normally, it is
6244 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6245 being kludges), it is MEM. When processing the arguments of a comparison
6246 or a COMPARE against zero, it is COMPARE. */
6249 make_compound_operation (x
, in_code
)
6251 enum rtx_code in_code
;
6253 enum rtx_code code
= GET_CODE (x
);
6254 enum machine_mode mode
= GET_MODE (x
);
6255 int mode_width
= GET_MODE_BITSIZE (mode
);
6257 enum rtx_code next_code
;
6263 /* Select the code to be used in recursive calls. Once we are inside an
6264 address, we stay there. If we have a comparison, set to COMPARE,
6265 but once inside, go back to our default of SET. */
6267 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6268 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6269 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6270 : in_code
== COMPARE
? SET
: in_code
);
6272 /* Process depending on the code of this operation. If NEW is set
6273 non-zero, it will be returned. */
6278 /* Convert shifts by constants into multiplications if inside
6280 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6281 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6282 && INTVAL (XEXP (x
, 1)) >= 0)
6284 new = make_compound_operation (XEXP (x
, 0), next_code
);
6285 new = gen_rtx_MULT (mode
, new,
6286 GEN_INT ((HOST_WIDE_INT
) 1
6287 << INTVAL (XEXP (x
, 1))));
6292 /* If the second operand is not a constant, we can't do anything
6294 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6297 /* If the constant is a power of two minus one and the first operand
6298 is a logical right shift, make an extraction. */
6299 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6300 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6302 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6303 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6304 0, in_code
== COMPARE
);
6307 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6308 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6309 && subreg_lowpart_p (XEXP (x
, 0))
6310 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6311 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6313 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6315 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6316 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6317 0, in_code
== COMPARE
);
6319 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6320 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6321 || GET_CODE (XEXP (x
, 0)) == IOR
)
6322 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6323 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6324 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6326 /* Apply the distributive law, and then try to make extractions. */
6327 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6328 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6330 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6332 new = make_compound_operation (new, in_code
);
6335 /* If we are have (and (rotate X C) M) and C is larger than the number
6336 of bits in M, this is an extraction. */
6338 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6339 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6340 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6341 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6343 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6344 new = make_extraction (mode
, new,
6345 (GET_MODE_BITSIZE (mode
)
6346 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6347 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6350 /* On machines without logical shifts, if the operand of the AND is
6351 a logical shift and our mask turns off all the propagated sign
6352 bits, we can replace the logical shift with an arithmetic shift. */
6353 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6354 && !have_insn_for (LSHIFTRT
, mode
)
6355 && have_insn_for (ASHIFTRT
, mode
)
6356 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6357 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6358 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6359 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6361 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6363 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6364 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6366 gen_rtx_ASHIFTRT (mode
,
6367 make_compound_operation
6368 (XEXP (XEXP (x
, 0), 0), next_code
),
6369 XEXP (XEXP (x
, 0), 1)));
6372 /* If the constant is one less than a power of two, this might be
6373 representable by an extraction even if no shift is present.
6374 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6375 we are in a COMPARE. */
6376 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6377 new = make_extraction (mode
,
6378 make_compound_operation (XEXP (x
, 0),
6380 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6382 /* If we are in a comparison and this is an AND with a power of two,
6383 convert this into the appropriate bit extract. */
6384 else if (in_code
== COMPARE
6385 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6386 new = make_extraction (mode
,
6387 make_compound_operation (XEXP (x
, 0),
6389 i
, NULL_RTX
, 1, 1, 0, 1);
6394 /* If the sign bit is known to be zero, replace this with an
6395 arithmetic shift. */
6396 if (have_insn_for (ASHIFTRT
, mode
)
6397 && ! have_insn_for (LSHIFTRT
, mode
)
6398 && mode_width
<= HOST_BITS_PER_WIDE_INT
6399 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6401 new = gen_rtx_ASHIFTRT (mode
,
6402 make_compound_operation (XEXP (x
, 0),
6408 /* ... fall through ... */
6414 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6415 this is a SIGN_EXTRACT. */
6416 if (GET_CODE (rhs
) == CONST_INT
6417 && GET_CODE (lhs
) == ASHIFT
6418 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6419 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6421 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6422 new = make_extraction (mode
, new,
6423 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6424 NULL_RTX
, mode_width
- INTVAL (rhs
),
6425 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6429 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6430 If so, try to merge the shifts into a SIGN_EXTEND. We could
6431 also do this for some cases of SIGN_EXTRACT, but it doesn't
6432 seem worth the effort; the case checked for occurs on Alpha. */
6434 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6435 && ! (GET_CODE (lhs
) == SUBREG
6436 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6437 && GET_CODE (rhs
) == CONST_INT
6438 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6439 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6440 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6441 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6442 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6447 /* Call ourselves recursively on the inner expression. If we are
6448 narrowing the object and it has a different RTL code from
6449 what it originally did, do this SUBREG as a force_to_mode. */
6451 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6452 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6453 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6454 && subreg_lowpart_p (x
))
6456 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6459 /* If we have something other than a SUBREG, we might have
6460 done an expansion, so rerun outselves. */
6461 if (GET_CODE (newer
) != SUBREG
)
6462 newer
= make_compound_operation (newer
, in_code
);
6467 /* If this is a paradoxical subreg, and the new code is a sign or
6468 zero extension, omit the subreg and widen the extension. If it
6469 is a regular subreg, we can still get rid of the subreg by not
6470 widening so much, or in fact removing the extension entirely. */
6471 if ((GET_CODE (tem
) == SIGN_EXTEND
6472 || GET_CODE (tem
) == ZERO_EXTEND
)
6473 && subreg_lowpart_p (x
))
6475 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6476 || (GET_MODE_SIZE (mode
) >
6477 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6478 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6480 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6491 x
= gen_lowpart_for_combine (mode
, new);
6492 code
= GET_CODE (x
);
6495 /* Now recursively process each operand of this operation. */
6496 fmt
= GET_RTX_FORMAT (code
);
6497 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6500 new = make_compound_operation (XEXP (x
, i
), next_code
);
6501 SUBST (XEXP (x
, i
), new);
6507 /* Given M see if it is a value that would select a field of bits
6508 within an item, but not the entire word. Return -1 if not.
6509 Otherwise, return the starting position of the field, where 0 is the
6512 *PLEN is set to the length of the field. */
6515 get_pos_from_mask (m
, plen
)
6516 unsigned HOST_WIDE_INT m
;
6517 unsigned HOST_WIDE_INT
*plen
;
6519 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6520 int pos
= exact_log2 (m
& -m
);
6526 /* Now shift off the low-order zero bits and see if we have a power of
6528 len
= exact_log2 ((m
>> pos
) + 1);
6537 /* See if X can be simplified knowing that we will only refer to it in
6538 MODE and will only refer to those bits that are nonzero in MASK.
6539 If other bits are being computed or if masking operations are done
6540 that select a superset of the bits in MASK, they can sometimes be
6543 Return a possibly simplified expression, but always convert X to
6544 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6546 Also, if REG is non-zero and X is a register equal in value to REG,
6549 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6550 are all off in X. This is used when X will be complemented, by either
6551 NOT, NEG, or XOR. */
6554 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6556 enum machine_mode mode
;
6557 unsigned HOST_WIDE_INT mask
;
6561 enum rtx_code code
= GET_CODE (x
);
6562 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6563 enum machine_mode op_mode
;
6564 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6567 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6568 code below will do the wrong thing since the mode of such an
6569 expression is VOIDmode.
6571 Also do nothing if X is a CLOBBER; this can happen if X was
6572 the return value from a call to gen_lowpart_for_combine. */
6573 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6576 /* We want to perform the operation is its present mode unless we know
6577 that the operation is valid in MODE, in which case we do the operation
6579 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6580 && have_insn_for (code
, mode
))
6581 ? mode
: GET_MODE (x
));
6583 /* It is not valid to do a right-shift in a narrower mode
6584 than the one it came in with. */
6585 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6586 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6587 op_mode
= GET_MODE (x
);
6589 /* Truncate MASK to fit OP_MODE. */
6591 mask
&= GET_MODE_MASK (op_mode
);
6593 /* When we have an arithmetic operation, or a shift whose count we
6594 do not know, we need to assume that all bit the up to the highest-order
6595 bit in MASK will be needed. This is how we form such a mask. */
6597 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6598 ? GET_MODE_MASK (op_mode
)
6599 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6602 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6604 /* Determine what bits of X are guaranteed to be (non)zero. */
6605 nonzero
= nonzero_bits (x
, mode
);
6607 /* If none of the bits in X are needed, return a zero. */
6608 if (! just_select
&& (nonzero
& mask
) == 0)
6611 /* If X is a CONST_INT, return a new one. Do this here since the
6612 test below will fail. */
6613 if (GET_CODE (x
) == CONST_INT
)
6615 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6616 int width
= GET_MODE_BITSIZE (mode
);
6618 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6619 number, sign extend it. */
6620 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6621 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6622 cval
|= (HOST_WIDE_INT
) -1 << width
;
6624 return GEN_INT (cval
);
6627 /* If X is narrower than MODE and we want all the bits in X's mode, just
6628 get X in the proper mode. */
6629 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6630 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6631 return gen_lowpart_for_combine (mode
, x
);
6633 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6634 MASK are already known to be zero in X, we need not do anything. */
6635 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6641 /* If X is a (clobber (const_int)), return it since we know we are
6642 generating something that won't match. */
6646 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6647 spanned the boundary of the MEM. If we are now masking so it is
6648 within that boundary, we don't need the USE any more. */
6649 if (! BITS_BIG_ENDIAN
6650 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6651 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6658 x
= expand_compound_operation (x
);
6659 if (GET_CODE (x
) != code
)
6660 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6664 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6665 || rtx_equal_p (reg
, get_last_value (x
))))
6670 if (subreg_lowpart_p (x
)
6671 /* We can ignore the effect of this SUBREG if it narrows the mode or
6672 if the constant masks to zero all the bits the mode doesn't
6674 && ((GET_MODE_SIZE (GET_MODE (x
))
6675 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6677 & GET_MODE_MASK (GET_MODE (x
))
6678 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6679 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6683 /* If this is an AND with a constant, convert it into an AND
6684 whose constant is the AND of that constant with MASK. If it
6685 remains an AND of MASK, delete it since it is redundant. */
6687 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6689 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6690 mask
& INTVAL (XEXP (x
, 1)));
6692 /* If X is still an AND, see if it is an AND with a mask that
6693 is just some low-order bits. If so, and it is MASK, we don't
6696 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6697 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6700 /* If it remains an AND, try making another AND with the bits
6701 in the mode mask that aren't in MASK turned on. If the
6702 constant in the AND is wide enough, this might make a
6703 cheaper constant. */
6705 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6706 && GET_MODE_MASK (GET_MODE (x
)) != mask
6707 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6709 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6710 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6711 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6714 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6715 number, sign extend it. */
6716 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6717 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6718 cval
|= (HOST_WIDE_INT
) -1 << width
;
6720 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6721 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6731 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6732 low-order bits (as in an alignment operation) and FOO is already
6733 aligned to that boundary, mask C1 to that boundary as well.
6734 This may eliminate that PLUS and, later, the AND. */
6737 unsigned int width
= GET_MODE_BITSIZE (mode
);
6738 unsigned HOST_WIDE_INT smask
= mask
;
6740 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6741 number, sign extend it. */
6743 if (width
< HOST_BITS_PER_WIDE_INT
6744 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6745 smask
|= (HOST_WIDE_INT
) -1 << width
;
6747 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6748 && exact_log2 (- smask
) >= 0)
6752 && (XEXP (x
, 0) == stack_pointer_rtx
6753 || XEXP (x
, 0) == frame_pointer_rtx
))
6755 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6756 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6758 sp_mask
&= ~(sp_alignment
- 1);
6759 if ((sp_mask
& ~smask
) == 0
6760 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6761 return force_to_mode (plus_constant (XEXP (x
, 0),
6762 ((INTVAL (XEXP (x
, 1)) -
6763 STACK_BIAS
) & smask
)
6765 mode
, smask
, reg
, next_select
);
6768 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6769 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6770 return force_to_mode (plus_constant (XEXP (x
, 0),
6771 (INTVAL (XEXP (x
, 1))
6773 mode
, smask
, reg
, next_select
);
6777 /* ... fall through ... */
6780 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6781 most significant bit in MASK since carries from those bits will
6782 affect the bits we are interested in. */
6787 /* If X is (minus C Y) where C's least set bit is larger than any bit
6788 in the mask, then we may replace with (neg Y). */
6789 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6790 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6791 & -INTVAL (XEXP (x
, 0))))
6794 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6796 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6799 /* Similarly, if C contains every bit in the mask, then we may
6800 replace with (not Y). */
6801 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6802 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6803 == INTVAL (XEXP (x
, 0))))
6805 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6806 XEXP (x
, 1), GET_MODE (x
));
6807 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6815 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6816 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6817 operation which may be a bitfield extraction. Ensure that the
6818 constant we form is not wider than the mode of X. */
6820 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6821 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6822 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6823 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6824 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6825 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6826 + floor_log2 (INTVAL (XEXP (x
, 1))))
6827 < GET_MODE_BITSIZE (GET_MODE (x
)))
6828 && (INTVAL (XEXP (x
, 1))
6829 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6831 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6832 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6833 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6834 XEXP (XEXP (x
, 0), 0), temp
);
6835 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6836 XEXP (XEXP (x
, 0), 1));
6837 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6841 /* For most binary operations, just propagate into the operation and
6842 change the mode if we have an operation of that mode. */
6844 op0
= gen_lowpart_for_combine (op_mode
,
6845 force_to_mode (XEXP (x
, 0), mode
, mask
,
6847 op1
= gen_lowpart_for_combine (op_mode
,
6848 force_to_mode (XEXP (x
, 1), mode
, mask
,
6851 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6852 MASK since OP1 might have been sign-extended but we never want
6853 to turn on extra bits, since combine might have previously relied
6854 on them being off. */
6855 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6856 && (INTVAL (op1
) & mask
) != 0)
6857 op1
= GEN_INT (INTVAL (op1
) & mask
);
6859 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6860 x
= gen_binary (code
, op_mode
, op0
, op1
);
6864 /* For left shifts, do the same, but just for the first operand.
6865 However, we cannot do anything with shifts where we cannot
6866 guarantee that the counts are smaller than the size of the mode
6867 because such a count will have a different meaning in a
6870 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6871 && INTVAL (XEXP (x
, 1)) >= 0
6872 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6873 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6874 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6875 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6878 /* If the shift count is a constant and we can do arithmetic in
6879 the mode of the shift, refine which bits we need. Otherwise, use the
6880 conservative form of the mask. */
6881 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6882 && INTVAL (XEXP (x
, 1)) >= 0
6883 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6884 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6885 mask
>>= INTVAL (XEXP (x
, 1));
6889 op0
= gen_lowpart_for_combine (op_mode
,
6890 force_to_mode (XEXP (x
, 0), op_mode
,
6891 mask
, reg
, next_select
));
6893 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6894 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6898 /* Here we can only do something if the shift count is a constant,
6899 this shift constant is valid for the host, and we can do arithmetic
6902 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6903 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6904 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6906 rtx inner
= XEXP (x
, 0);
6907 unsigned HOST_WIDE_INT inner_mask
;
6909 /* Select the mask of the bits we need for the shift operand. */
6910 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6912 /* We can only change the mode of the shift if we can do arithmetic
6913 in the mode of the shift and INNER_MASK is no wider than the
6914 width of OP_MODE. */
6915 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6916 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
6917 op_mode
= GET_MODE (x
);
6919 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6921 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6922 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6925 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6926 shift and AND produces only copies of the sign bit (C2 is one less
6927 than a power of two), we can do this with just a shift. */
6929 if (GET_CODE (x
) == LSHIFTRT
6930 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6931 /* The shift puts one of the sign bit copies in the least significant
6933 && ((INTVAL (XEXP (x
, 1))
6934 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6935 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6936 && exact_log2 (mask
+ 1) >= 0
6937 /* Number of bits left after the shift must be more than the mask
6939 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
6940 <= GET_MODE_BITSIZE (GET_MODE (x
)))
6941 /* Must be more sign bit copies than the mask needs. */
6942 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6943 >= exact_log2 (mask
+ 1)))
6944 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6945 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6946 - exact_log2 (mask
+ 1)));
6951 /* If we are just looking for the sign bit, we don't need this shift at
6952 all, even if it has a variable count. */
6953 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6954 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6955 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6956 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6958 /* If this is a shift by a constant, get a mask that contains those bits
6959 that are not copies of the sign bit. We then have two cases: If
6960 MASK only includes those bits, this can be a logical shift, which may
6961 allow simplifications. If MASK is a single-bit field not within
6962 those bits, we are requesting a copy of the sign bit and hence can
6963 shift the sign bit to the appropriate location. */
6965 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6966 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6970 /* If the considered data is wider then HOST_WIDE_INT, we can't
6971 represent a mask for all its bits in a single scalar.
6972 But we only care about the lower bits, so calculate these. */
6974 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6976 nonzero
= ~(HOST_WIDE_INT
) 0;
6978 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6979 is the number of bits a full-width mask would have set.
6980 We need only shift if these are fewer than nonzero can
6981 hold. If not, we must keep all bits set in nonzero. */
6983 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6984 < HOST_BITS_PER_WIDE_INT
)
6985 nonzero
>>= INTVAL (XEXP (x
, 1))
6986 + HOST_BITS_PER_WIDE_INT
6987 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6991 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6992 nonzero
>>= INTVAL (XEXP (x
, 1));
6995 if ((mask
& ~nonzero
) == 0
6996 || (i
= exact_log2 (mask
)) >= 0)
6998 x
= simplify_shift_const
6999 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7000 i
< 0 ? INTVAL (XEXP (x
, 1))
7001 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7003 if (GET_CODE (x
) != ASHIFTRT
)
7004 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7008 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7009 even if the shift count isn't a constant. */
7011 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7015 /* If this is a zero- or sign-extension operation that just affects bits
7016 we don't care about, remove it. Be sure the call above returned
7017 something that is still a shift. */
7019 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7020 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7021 && INTVAL (XEXP (x
, 1)) >= 0
7022 && (INTVAL (XEXP (x
, 1))
7023 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7024 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7025 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7026 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7027 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7034 /* If the shift count is constant and we can do computations
7035 in the mode of X, compute where the bits we care about are.
7036 Otherwise, we can't do anything. Don't change the mode of
7037 the shift or propagate MODE into the shift, though. */
7038 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7039 && INTVAL (XEXP (x
, 1)) >= 0)
7041 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7042 GET_MODE (x
), GEN_INT (mask
),
7044 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7046 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7047 INTVAL (temp
), reg
, next_select
));
7052 /* If we just want the low-order bit, the NEG isn't needed since it
7053 won't change the low-order bit. */
7055 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7057 /* We need any bits less significant than the most significant bit in
7058 MASK since carries from those bits will affect the bits we are
7064 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7065 same as the XOR case above. Ensure that the constant we form is not
7066 wider than the mode of X. */
7068 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7069 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7070 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7071 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7072 < GET_MODE_BITSIZE (GET_MODE (x
)))
7073 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7075 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7076 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7077 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7079 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7082 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7083 use the full mask inside the NOT. */
7087 op0
= gen_lowpart_for_combine (op_mode
,
7088 force_to_mode (XEXP (x
, 0), mode
, mask
,
7090 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7091 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7095 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7096 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7097 which is equal to STORE_FLAG_VALUE. */
7098 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7099 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7100 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7101 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7106 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7107 written in a narrower mode. We play it safe and do not do so. */
7110 gen_lowpart_for_combine (GET_MODE (x
),
7111 force_to_mode (XEXP (x
, 1), mode
,
7112 mask
, reg
, next_select
)));
7114 gen_lowpart_for_combine (GET_MODE (x
),
7115 force_to_mode (XEXP (x
, 2), mode
,
7116 mask
, reg
,next_select
)));
7123 /* Ensure we return a value of the proper mode. */
7124 return gen_lowpart_for_combine (mode
, x
);
7127 /* Return nonzero if X is an expression that has one of two values depending on
7128 whether some other value is zero or nonzero. In that case, we return the
7129 value that is being tested, *PTRUE is set to the value if the rtx being
7130 returned has a nonzero value, and *PFALSE is set to the other alternative.
7132 If we return zero, we set *PTRUE and *PFALSE to X. */
7135 if_then_else_cond (x
, ptrue
, pfalse
)
7137 rtx
*ptrue
, *pfalse
;
7139 enum machine_mode mode
= GET_MODE (x
);
7140 enum rtx_code code
= GET_CODE (x
);
7141 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7142 unsigned HOST_WIDE_INT nz
;
7144 /* If we are comparing a value against zero, we are done. */
7145 if ((code
== NE
|| code
== EQ
)
7146 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7148 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7149 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7153 /* If this is a unary operation whose operand has one of two values, apply
7154 our opcode to compute those values. */
7155 else if (GET_RTX_CLASS (code
) == '1'
7156 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7158 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7159 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7160 GET_MODE (XEXP (x
, 0)));
7164 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7165 make can't possibly match and would suppress other optimizations. */
7166 else if (code
== COMPARE
)
7169 /* If this is a binary operation, see if either side has only one of two
7170 values. If either one does or if both do and they are conditional on
7171 the same value, compute the new true and false values. */
7172 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7173 || GET_RTX_CLASS (code
) == '<')
7175 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7176 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7178 if ((cond0
!= 0 || cond1
!= 0)
7179 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7181 /* If if_then_else_cond returned zero, then true/false are the
7182 same rtl. We must copy one of them to prevent invalid rtl
7185 true0
= copy_rtx (true0
);
7186 else if (cond1
== 0)
7187 true1
= copy_rtx (true1
);
7189 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7190 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7191 return cond0
? cond0
: cond1
;
7194 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7195 operands is zero when the other is non-zero, and vice-versa,
7196 and STORE_FLAG_VALUE is 1 or -1. */
7198 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7199 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7201 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7203 rtx op0
= XEXP (XEXP (x
, 0), 1);
7204 rtx op1
= XEXP (XEXP (x
, 1), 1);
7206 cond0
= XEXP (XEXP (x
, 0), 0);
7207 cond1
= XEXP (XEXP (x
, 1), 0);
7209 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7210 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7211 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7212 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7213 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7214 || ((swap_condition (GET_CODE (cond0
))
7215 == combine_reversed_comparison_code (cond1
))
7216 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7217 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7218 && ! side_effects_p (x
))
7220 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7221 *pfalse
= gen_binary (MULT
, mode
,
7223 ? simplify_gen_unary (NEG
, mode
, op1
,
7231 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7233 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7234 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7235 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7237 cond0
= XEXP (XEXP (x
, 0), 0);
7238 cond1
= XEXP (XEXP (x
, 1), 0);
7240 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7241 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7242 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7243 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7244 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7245 || ((swap_condition (GET_CODE (cond0
))
7246 == combine_reversed_comparison_code (cond1
))
7247 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7248 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7249 && ! side_effects_p (x
))
7251 *ptrue
= *pfalse
= const0_rtx
;
7257 else if (code
== IF_THEN_ELSE
)
7259 /* If we have IF_THEN_ELSE already, extract the condition and
7260 canonicalize it if it is NE or EQ. */
7261 cond0
= XEXP (x
, 0);
7262 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7263 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7264 return XEXP (cond0
, 0);
7265 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7267 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7268 return XEXP (cond0
, 0);
7274 /* If X is a SUBREG, we can narrow both the true and false values
7275 if the inner expression, if there is a condition. */
7276 else if (code
== SUBREG
7277 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7280 *ptrue
= simplify_gen_subreg (mode
, true0
,
7281 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7282 *pfalse
= simplify_gen_subreg (mode
, false0
,
7283 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7288 /* If X is a constant, this isn't special and will cause confusions
7289 if we treat it as such. Likewise if it is equivalent to a constant. */
7290 else if (CONSTANT_P (x
)
7291 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7294 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7295 will be least confusing to the rest of the compiler. */
7296 else if (mode
== BImode
)
7298 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7302 /* If X is known to be either 0 or -1, those are the true and
7303 false values when testing X. */
7304 else if (x
== constm1_rtx
|| x
== const0_rtx
7305 || (mode
!= VOIDmode
7306 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7308 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7312 /* Likewise for 0 or a single bit. */
7313 else if (mode
!= VOIDmode
7314 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7315 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7317 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7321 /* Otherwise fail; show no condition with true and false values the same. */
7322 *ptrue
= *pfalse
= x
;
7326 /* Return the value of expression X given the fact that condition COND
7327 is known to be true when applied to REG as its first operand and VAL
7328 as its second. X is known to not be shared and so can be modified in
7331 We only handle the simplest cases, and specifically those cases that
7332 arise with IF_THEN_ELSE expressions. */
7335 known_cond (x
, cond
, reg
, val
)
7340 enum rtx_code code
= GET_CODE (x
);
7345 if (side_effects_p (x
))
7348 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7350 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7353 /* If X is (abs REG) and we know something about REG's relationship
7354 with zero, we may be able to simplify this. */
7356 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7359 case GE
: case GT
: case EQ
:
7362 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7364 GET_MODE (XEXP (x
, 0)));
7369 /* The only other cases we handle are MIN, MAX, and comparisons if the
7370 operands are the same as REG and VAL. */
7372 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7374 if (rtx_equal_p (XEXP (x
, 0), val
))
7375 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7377 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7379 if (GET_RTX_CLASS (code
) == '<')
7381 if (comparison_dominates_p (cond
, code
))
7382 return const_true_rtx
;
7384 code
= combine_reversed_comparison_code (x
);
7386 && comparison_dominates_p (cond
, code
))
7391 else if (code
== SMAX
|| code
== SMIN
7392 || code
== UMIN
|| code
== UMAX
)
7394 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7396 /* Do not reverse the condition when it is NE or EQ.
7397 This is because we cannot conclude anything about
7398 the value of 'SMAX (x, y)' when x is not equal to y,
7399 but we can when x equals y. */
7400 if ((code
== SMAX
|| code
== UMAX
)
7401 && ! (cond
== EQ
|| cond
== NE
))
7402 cond
= reverse_condition (cond
);
7407 return unsignedp
? x
: XEXP (x
, 1);
7409 return unsignedp
? x
: XEXP (x
, 0);
7411 return unsignedp
? XEXP (x
, 1) : x
;
7413 return unsignedp
? XEXP (x
, 0) : x
;
7421 fmt
= GET_RTX_FORMAT (code
);
7422 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7425 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7426 else if (fmt
[i
] == 'E')
7427 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7428 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7435 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7436 assignment as a field assignment. */
7439 rtx_equal_for_field_assignment_p (x
, y
)
7443 if (x
== y
|| rtx_equal_p (x
, y
))
7446 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7449 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7450 Note that all SUBREGs of MEM are paradoxical; otherwise they
7451 would have been rewritten. */
7452 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7453 && GET_CODE (SUBREG_REG (y
)) == MEM
7454 && rtx_equal_p (SUBREG_REG (y
),
7455 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7458 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7459 && GET_CODE (SUBREG_REG (x
)) == MEM
7460 && rtx_equal_p (SUBREG_REG (x
),
7461 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7464 /* We used to see if get_last_value of X and Y were the same but that's
7465 not correct. In one direction, we'll cause the assignment to have
7466 the wrong destination and in the case, we'll import a register into this
7467 insn that might have already have been dead. So fail if none of the
7468 above cases are true. */
7472 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7473 Return that assignment if so.
7475 We only handle the most common cases. */
7478 make_field_assignment (x
)
7481 rtx dest
= SET_DEST (x
);
7482 rtx src
= SET_SRC (x
);
7487 unsigned HOST_WIDE_INT len
;
7489 enum machine_mode mode
;
7491 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7492 a clear of a one-bit field. We will have changed it to
7493 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7496 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7497 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7498 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7499 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7501 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7504 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7508 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7509 && subreg_lowpart_p (XEXP (src
, 0))
7510 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7511 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7512 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7513 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7514 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7516 assign
= make_extraction (VOIDmode
, dest
, 0,
7517 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7520 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7524 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7526 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7527 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7528 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7530 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7533 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7537 /* The other case we handle is assignments into a constant-position
7538 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7539 a mask that has all one bits except for a group of zero bits and
7540 OTHER is known to have zeros where C1 has ones, this is such an
7541 assignment. Compute the position and length from C1. Shift OTHER
7542 to the appropriate position, force it to the required mode, and
7543 make the extraction. Check for the AND in both operands. */
7545 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7548 rhs
= expand_compound_operation (XEXP (src
, 0));
7549 lhs
= expand_compound_operation (XEXP (src
, 1));
7551 if (GET_CODE (rhs
) == AND
7552 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7553 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7554 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7555 else if (GET_CODE (lhs
) == AND
7556 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7557 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7558 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7562 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7563 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7564 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7565 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7568 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7572 /* The mode to use for the source is the mode of the assignment, or of
7573 what is inside a possible STRICT_LOW_PART. */
7574 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7575 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7577 /* Shift OTHER right POS places and make it the source, restricting it
7578 to the proper length and mode. */
7580 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7581 GET_MODE (src
), other
, pos
),
7583 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7584 ? ~(unsigned HOST_WIDE_INT
) 0
7585 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7588 return gen_rtx_SET (VOIDmode
, assign
, src
);
7591 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7595 apply_distributive_law (x
)
7598 enum rtx_code code
= GET_CODE (x
);
7599 rtx lhs
, rhs
, other
;
7601 enum rtx_code inner_code
;
7603 /* Distributivity is not true for floating point.
7604 It can change the value. So don't do it.
7605 -- rms and moshier@world.std.com. */
7606 if (FLOAT_MODE_P (GET_MODE (x
)))
7609 /* The outer operation can only be one of the following: */
7610 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7611 && code
!= PLUS
&& code
!= MINUS
)
7614 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7616 /* If either operand is a primitive we can't do anything, so get out
7618 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7619 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7622 lhs
= expand_compound_operation (lhs
);
7623 rhs
= expand_compound_operation (rhs
);
7624 inner_code
= GET_CODE (lhs
);
7625 if (inner_code
!= GET_CODE (rhs
))
7628 /* See if the inner and outer operations distribute. */
7635 /* These all distribute except over PLUS. */
7636 if (code
== PLUS
|| code
== MINUS
)
7641 if (code
!= PLUS
&& code
!= MINUS
)
7646 /* This is also a multiply, so it distributes over everything. */
7650 /* Non-paradoxical SUBREGs distributes over all operations, provided
7651 the inner modes and byte offsets are the same, this is an extraction
7652 of a low-order part, we don't convert an fp operation to int or
7653 vice versa, and we would not be converting a single-word
7654 operation into a multi-word operation. The latter test is not
7655 required, but it prevents generating unneeded multi-word operations.
7656 Some of the previous tests are redundant given the latter test, but
7657 are retained because they are required for correctness.
7659 We produce the result slightly differently in this case. */
7661 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7662 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7663 || ! subreg_lowpart_p (lhs
)
7664 || (GET_MODE_CLASS (GET_MODE (lhs
))
7665 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7666 || (GET_MODE_SIZE (GET_MODE (lhs
))
7667 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7668 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7671 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7672 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7673 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7679 /* Set LHS and RHS to the inner operands (A and B in the example
7680 above) and set OTHER to the common operand (C in the example).
7681 These is only one way to do this unless the inner operation is
7683 if (GET_RTX_CLASS (inner_code
) == 'c'
7684 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7685 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7686 else if (GET_RTX_CLASS (inner_code
) == 'c'
7687 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7688 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7689 else if (GET_RTX_CLASS (inner_code
) == 'c'
7690 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7691 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7692 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7693 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7697 /* Form the new inner operation, seeing if it simplifies first. */
7698 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7700 /* There is one exception to the general way of distributing:
7701 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7702 if (code
== XOR
&& inner_code
== IOR
)
7705 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7708 /* We may be able to continuing distributing the result, so call
7709 ourselves recursively on the inner operation before forming the
7710 outer operation, which we return. */
7711 return gen_binary (inner_code
, GET_MODE (x
),
7712 apply_distributive_law (tem
), other
);
7715 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7718 Return an equivalent form, if different from X. Otherwise, return X. If
7719 X is zero, we are to always construct the equivalent form. */
7722 simplify_and_const_int (x
, mode
, varop
, constop
)
7724 enum machine_mode mode
;
7726 unsigned HOST_WIDE_INT constop
;
7728 unsigned HOST_WIDE_INT nonzero
;
7731 /* Simplify VAROP knowing that we will be only looking at some of the
7733 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7735 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7736 CONST_INT, we are done. */
7737 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7740 /* See what bits may be nonzero in VAROP. Unlike the general case of
7741 a call to nonzero_bits, here we don't care about bits outside
7744 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7745 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7747 /* Turn off all bits in the constant that are known to already be zero.
7748 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7749 which is tested below. */
7753 /* If we don't have any bits left, return zero. */
7757 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7758 a power of two, we can replace this with a ASHIFT. */
7759 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7760 && (i
= exact_log2 (constop
)) >= 0)
7761 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7763 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7764 or XOR, then try to apply the distributive law. This may eliminate
7765 operations if either branch can be simplified because of the AND.
7766 It may also make some cases more complex, but those cases probably
7767 won't match a pattern either with or without this. */
7769 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7771 gen_lowpart_for_combine
7773 apply_distributive_law
7774 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7775 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7776 XEXP (varop
, 0), constop
),
7777 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7778 XEXP (varop
, 1), constop
))));
7780 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7781 if we already had one (just check for the simplest cases). */
7782 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7783 && GET_MODE (XEXP (x
, 0)) == mode
7784 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7785 varop
= XEXP (x
, 0);
7787 varop
= gen_lowpart_for_combine (mode
, varop
);
7789 /* If we can't make the SUBREG, try to return what we were given. */
7790 if (GET_CODE (varop
) == CLOBBER
)
7791 return x
? x
: varop
;
7793 /* If we are only masking insignificant bits, return VAROP. */
7794 if (constop
== nonzero
)
7797 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7798 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7799 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7803 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7804 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7805 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7807 SUBST (XEXP (x
, 0), varop
);
7813 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7814 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7815 is less useful. We can't allow both, because that results in exponential
7816 run time recursion. There is a nullstone testcase that triggered
7817 this. This macro avoids accidental uses of num_sign_bit_copies. */
7818 #define num_sign_bit_copies()
7820 /* Given an expression, X, compute which bits in X can be non-zero.
7821 We don't care about bits outside of those defined in MODE.
7823 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7824 a shift, AND, or zero_extract, we can do better. */
7826 static unsigned HOST_WIDE_INT
7827 nonzero_bits (x
, mode
)
7829 enum machine_mode mode
;
7831 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7832 unsigned HOST_WIDE_INT inner_nz
;
7834 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7837 /* For floating-point values, assume all bits are needed. */
7838 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7841 /* If X is wider than MODE, use its mode instead. */
7842 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7844 mode
= GET_MODE (x
);
7845 nonzero
= GET_MODE_MASK (mode
);
7846 mode_width
= GET_MODE_BITSIZE (mode
);
7849 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7850 /* Our only callers in this case look for single bit values. So
7851 just return the mode mask. Those tests will then be false. */
7854 #ifndef WORD_REGISTER_OPERATIONS
7855 /* If MODE is wider than X, but both are a single word for both the host
7856 and target machines, we can compute this from which bits of the
7857 object might be nonzero in its own mode, taking into account the fact
7858 that on many CISC machines, accessing an object in a wider mode
7859 causes the high-order bits to become undefined. So they are
7860 not known to be zero. */
7862 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7863 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7864 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7865 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7867 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7868 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
7873 code
= GET_CODE (x
);
7877 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7878 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7879 all the bits above ptr_mode are known to be zero. */
7880 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7882 nonzero
&= GET_MODE_MASK (ptr_mode
);
7885 #ifdef STACK_BOUNDARY
7886 /* If this is the stack pointer, we may know something about its
7887 alignment. If PUSH_ROUNDING is defined, it is possible for the
7888 stack to be momentarily aligned only to that amount, so we pick
7889 the least alignment. */
7891 /* We can't check for arg_pointer_rtx here, because it is not
7892 guaranteed to have as much alignment as the stack pointer.
7893 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7894 alignment but the argument pointer has only 64 bit alignment. */
7896 if ((x
== frame_pointer_rtx
7897 || x
== stack_pointer_rtx
7898 || x
== hard_frame_pointer_rtx
7899 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7900 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7906 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7908 #ifdef PUSH_ROUNDING
7909 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
7910 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7913 /* We must return here, otherwise we may get a worse result from
7914 one of the choices below. There is nothing useful below as
7915 far as the stack pointer is concerned. */
7916 return nonzero
&= ~(sp_alignment
- 1);
7920 /* If X is a register whose nonzero bits value is current, use it.
7921 Otherwise, if X is a register whose value we can find, use that
7922 value. Otherwise, use the previously-computed global nonzero bits
7923 for this register. */
7925 if (reg_last_set_value
[REGNO (x
)] != 0
7926 && reg_last_set_mode
[REGNO (x
)] == mode
7927 && (reg_last_set_label
[REGNO (x
)] == label_tick
7928 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7929 && REG_N_SETS (REGNO (x
)) == 1
7930 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7932 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7933 return reg_last_set_nonzero_bits
[REGNO (x
)];
7935 tem
= get_last_value (x
);
7939 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7940 /* If X is narrower than MODE and TEM is a non-negative
7941 constant that would appear negative in the mode of X,
7942 sign-extend it for use in reg_nonzero_bits because some
7943 machines (maybe most) will actually do the sign-extension
7944 and this is the conservative approach.
7946 ??? For 2.5, try to tighten up the MD files in this regard
7947 instead of this kludge. */
7949 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7950 && GET_CODE (tem
) == CONST_INT
7952 && 0 != (INTVAL (tem
)
7953 & ((HOST_WIDE_INT
) 1
7954 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7955 tem
= GEN_INT (INTVAL (tem
)
7956 | ((HOST_WIDE_INT
) (-1)
7957 << GET_MODE_BITSIZE (GET_MODE (x
))));
7959 return nonzero_bits (tem
, mode
);
7961 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7962 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7967 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7968 /* If X is negative in MODE, sign-extend the value. */
7969 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7970 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7971 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7977 #ifdef LOAD_EXTEND_OP
7978 /* In many, if not most, RISC machines, reading a byte from memory
7979 zeros the rest of the register. Noticing that fact saves a lot
7980 of extra zero-extends. */
7981 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7982 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7987 case UNEQ
: case LTGT
:
7988 case GT
: case GTU
: case UNGT
:
7989 case LT
: case LTU
: case UNLT
:
7990 case GE
: case GEU
: case UNGE
:
7991 case LE
: case LEU
: case UNLE
:
7992 case UNORDERED
: case ORDERED
:
7994 /* If this produces an integer result, we know which bits are set.
7995 Code here used to clear bits outside the mode of X, but that is
7998 if (GET_MODE_CLASS (mode
) == MODE_INT
7999 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8000 nonzero
= STORE_FLAG_VALUE
;
8005 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8006 and num_sign_bit_copies. */
8007 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8008 == GET_MODE_BITSIZE (GET_MODE (x
)))
8012 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8013 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8018 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8019 and num_sign_bit_copies. */
8020 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8021 == GET_MODE_BITSIZE (GET_MODE (x
)))
8027 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8031 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8032 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8033 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8037 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8038 Otherwise, show all the bits in the outer mode but not the inner
8040 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8041 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8043 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8045 & (((HOST_WIDE_INT
) 1
8046 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8047 inner_nz
|= (GET_MODE_MASK (mode
)
8048 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8051 nonzero
&= inner_nz
;
8055 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8056 & nonzero_bits (XEXP (x
, 1), mode
));
8060 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8061 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8062 | nonzero_bits (XEXP (x
, 1), mode
));
8065 case PLUS
: case MINUS
:
8067 case DIV
: case UDIV
:
8068 case MOD
: case UMOD
:
8069 /* We can apply the rules of arithmetic to compute the number of
8070 high- and low-order zero bits of these operations. We start by
8071 computing the width (position of the highest-order non-zero bit)
8072 and the number of low-order zero bits for each value. */
8074 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8075 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8076 int width0
= floor_log2 (nz0
) + 1;
8077 int width1
= floor_log2 (nz1
) + 1;
8078 int low0
= floor_log2 (nz0
& -nz0
);
8079 int low1
= floor_log2 (nz1
& -nz1
);
8080 HOST_WIDE_INT op0_maybe_minusp
8081 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8082 HOST_WIDE_INT op1_maybe_minusp
8083 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8084 unsigned int result_width
= mode_width
;
8092 && (XEXP (x
, 0) == stack_pointer_rtx
8093 || XEXP (x
, 0) == frame_pointer_rtx
)
8094 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8096 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8098 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8099 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8100 width0
= floor_log2 (nz0
) + 1;
8101 width1
= floor_log2 (nz1
) + 1;
8102 low0
= floor_log2 (nz0
& -nz0
);
8103 low1
= floor_log2 (nz1
& -nz1
);
8106 result_width
= MAX (width0
, width1
) + 1;
8107 result_low
= MIN (low0
, low1
);
8110 result_low
= MIN (low0
, low1
);
8113 result_width
= width0
+ width1
;
8114 result_low
= low0
+ low1
;
8119 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8120 result_width
= width0
;
8125 result_width
= width0
;
8130 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8131 result_width
= MIN (width0
, width1
);
8132 result_low
= MIN (low0
, low1
);
8137 result_width
= MIN (width0
, width1
);
8138 result_low
= MIN (low0
, low1
);
8144 if (result_width
< mode_width
)
8145 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8148 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8150 #ifdef POINTERS_EXTEND_UNSIGNED
8151 /* If pointers extend unsigned and this is an addition or subtraction
8152 to a pointer in Pmode, all the bits above ptr_mode are known to be
8154 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8155 && (code
== PLUS
|| code
== MINUS
)
8156 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8157 nonzero
&= GET_MODE_MASK (ptr_mode
);
8163 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8164 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8165 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8169 /* If this is a SUBREG formed for a promoted variable that has
8170 been zero-extended, we know that at least the high-order bits
8171 are zero, though others might be too. */
8173 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8174 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8175 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8177 /* If the inner mode is a single word for both the host and target
8178 machines, we can compute this from which bits of the inner
8179 object might be nonzero. */
8180 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8181 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8182 <= HOST_BITS_PER_WIDE_INT
))
8184 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8186 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8187 /* If this is a typical RISC machine, we only have to worry
8188 about the way loads are extended. */
8189 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8191 & (((unsigned HOST_WIDE_INT
) 1
8192 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8194 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8197 /* On many CISC machines, accessing an object in a wider mode
8198 causes the high-order bits to become undefined. So they are
8199 not known to be zero. */
8200 if (GET_MODE_SIZE (GET_MODE (x
))
8201 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8202 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8203 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8212 /* The nonzero bits are in two classes: any bits within MODE
8213 that aren't in GET_MODE (x) are always significant. The rest of the
8214 nonzero bits are those that are significant in the operand of
8215 the shift when shifted the appropriate number of bits. This
8216 shows that high-order bits are cleared by the right shift and
8217 low-order bits by left shifts. */
8218 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8219 && INTVAL (XEXP (x
, 1)) >= 0
8220 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8222 enum machine_mode inner_mode
= GET_MODE (x
);
8223 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8224 int count
= INTVAL (XEXP (x
, 1));
8225 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8226 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8227 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8228 unsigned HOST_WIDE_INT outer
= 0;
8230 if (mode_width
> width
)
8231 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8233 if (code
== LSHIFTRT
)
8235 else if (code
== ASHIFTRT
)
8239 /* If the sign bit may have been nonzero before the shift, we
8240 need to mark all the places it could have been copied to
8241 by the shift as possibly nonzero. */
8242 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8243 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8245 else if (code
== ASHIFT
)
8248 inner
= ((inner
<< (count
% width
)
8249 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8251 nonzero
&= (outer
| inner
);
8256 /* This is at most the number of bits in the mode. */
8257 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8261 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8262 | nonzero_bits (XEXP (x
, 2), mode
));
8272 /* See the macro definition above. */
8273 #undef num_sign_bit_copies
8275 /* Return the number of bits at the high-order end of X that are known to
8276 be equal to the sign bit. X will be used in mode MODE; if MODE is
8277 VOIDmode, X will be used in its own mode. The returned value will always
8278 be between 1 and the number of bits in MODE. */
8281 num_sign_bit_copies (x
, mode
)
8283 enum machine_mode mode
;
8285 enum rtx_code code
= GET_CODE (x
);
8286 unsigned int bitwidth
;
8287 int num0
, num1
, result
;
8288 unsigned HOST_WIDE_INT nonzero
;
8291 /* If we weren't given a mode, use the mode of X. If the mode is still
8292 VOIDmode, we don't know anything. Likewise if one of the modes is
8295 if (mode
== VOIDmode
)
8296 mode
= GET_MODE (x
);
8298 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8301 bitwidth
= GET_MODE_BITSIZE (mode
);
8303 /* For a smaller object, just ignore the high bits. */
8304 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8306 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8308 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8311 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8313 #ifndef WORD_REGISTER_OPERATIONS
8314 /* If this machine does not do all register operations on the entire
8315 register and MODE is wider than the mode of X, we can say nothing
8316 at all about the high-order bits. */
8319 /* Likewise on machines that do, if the mode of the object is smaller
8320 than a word and loads of that size don't sign extend, we can say
8321 nothing about the high order bits. */
8322 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8323 #ifdef LOAD_EXTEND_OP
8324 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8335 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8336 /* If pointers extend signed and this is a pointer in Pmode, say that
8337 all the bits above ptr_mode are known to be sign bit copies. */
8338 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8340 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8343 if (reg_last_set_value
[REGNO (x
)] != 0
8344 && reg_last_set_mode
[REGNO (x
)] == mode
8345 && (reg_last_set_label
[REGNO (x
)] == label_tick
8346 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8347 && REG_N_SETS (REGNO (x
)) == 1
8348 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8350 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8351 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8353 tem
= get_last_value (x
);
8355 return num_sign_bit_copies (tem
, mode
);
8357 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8358 return reg_sign_bit_copies
[REGNO (x
)];
8362 #ifdef LOAD_EXTEND_OP
8363 /* Some RISC machines sign-extend all loads of smaller than a word. */
8364 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8365 return MAX (1, ((int) bitwidth
8366 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8371 /* If the constant is negative, take its 1's complement and remask.
8372 Then see how many zero bits we have. */
8373 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8374 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8375 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8376 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8378 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8381 /* If this is a SUBREG for a promoted object that is sign-extended
8382 and we are looking at it in a wider mode, we know that at least the
8383 high-order bits are known to be sign bit copies. */
8385 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8387 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8388 return MAX ((int) bitwidth
8389 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8393 /* For a smaller object, just ignore the high bits. */
8394 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8396 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8397 return MAX (1, (num0
8398 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8402 #ifdef WORD_REGISTER_OPERATIONS
8403 #ifdef LOAD_EXTEND_OP
8404 /* For paradoxical SUBREGs on machines where all register operations
8405 affect the entire register, just look inside. Note that we are
8406 passing MODE to the recursive call, so the number of sign bit copies
8407 will remain relative to that mode, not the inner mode. */
8409 /* This works only if loads sign extend. Otherwise, if we get a
8410 reload for the inner part, it may be loaded from the stack, and
8411 then we lose all sign bit copies that existed before the store
8414 if ((GET_MODE_SIZE (GET_MODE (x
))
8415 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8416 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8417 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8423 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8424 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8428 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8429 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8432 /* For a smaller object, just ignore the high bits. */
8433 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8434 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8438 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8440 case ROTATE
: case ROTATERT
:
8441 /* If we are rotating left by a number of bits less than the number
8442 of sign bit copies, we can just subtract that amount from the
8444 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8445 && INTVAL (XEXP (x
, 1)) >= 0
8446 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8448 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8449 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8450 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8455 /* In general, this subtracts one sign bit copy. But if the value
8456 is known to be positive, the number of sign bit copies is the
8457 same as that of the input. Finally, if the input has just one bit
8458 that might be nonzero, all the bits are copies of the sign bit. */
8459 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8460 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8461 return num0
> 1 ? num0
- 1 : 1;
8463 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8468 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8473 case IOR
: case AND
: case XOR
:
8474 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8475 /* Logical operations will preserve the number of sign-bit copies.
8476 MIN and MAX operations always return one of the operands. */
8477 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8478 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8479 return MIN (num0
, num1
);
8481 case PLUS
: case MINUS
:
8482 /* For addition and subtraction, we can have a 1-bit carry. However,
8483 if we are subtracting 1 from a positive number, there will not
8484 be such a carry. Furthermore, if the positive number is known to
8485 be 0 or 1, we know the result is either -1 or 0. */
8487 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8488 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8490 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8491 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8492 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8493 : bitwidth
- floor_log2 (nonzero
) - 1);
8496 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8497 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8498 result
= MAX (1, MIN (num0
, num1
) - 1);
8500 #ifdef POINTERS_EXTEND_UNSIGNED
8501 /* If pointers extend signed and this is an addition or subtraction
8502 to a pointer in Pmode, all the bits above ptr_mode are known to be
8504 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8505 && (code
== PLUS
|| code
== MINUS
)
8506 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8507 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8508 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8514 /* The number of bits of the product is the sum of the number of
8515 bits of both terms. However, unless one of the terms if known
8516 to be positive, we must allow for an additional bit since negating
8517 a negative number can remove one sign bit copy. */
8519 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8520 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8522 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8524 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8525 || (((nonzero_bits (XEXP (x
, 0), mode
)
8526 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8527 && ((nonzero_bits (XEXP (x
, 1), mode
)
8528 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8531 return MAX (1, result
);
8534 /* The result must be <= the first operand. If the first operand
8535 has the high bit set, we know nothing about the number of sign
8537 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8539 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8540 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8543 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8546 /* The result must be <= the scond operand. */
8547 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8550 /* Similar to unsigned division, except that we have to worry about
8551 the case where the divisor is negative, in which case we have
8553 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8555 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8556 || (nonzero_bits (XEXP (x
, 1), mode
)
8557 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8563 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8565 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8566 || (nonzero_bits (XEXP (x
, 1), mode
)
8567 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8573 /* Shifts by a constant add to the number of bits equal to the
8575 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8576 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8577 && INTVAL (XEXP (x
, 1)) > 0)
8578 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8583 /* Left shifts destroy copies. */
8584 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8585 || INTVAL (XEXP (x
, 1)) < 0
8586 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8589 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8590 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8593 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8594 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8595 return MIN (num0
, num1
);
8597 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8598 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8599 case GEU
: case GTU
: case LEU
: case LTU
:
8600 case UNORDERED
: case ORDERED
:
8601 /* If the constant is negative, take its 1's complement and remask.
8602 Then see how many zero bits we have. */
8603 nonzero
= STORE_FLAG_VALUE
;
8604 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8605 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8606 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8608 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8615 /* If we haven't been able to figure it out by one of the above rules,
8616 see if some of the high-order bits are known to be zero. If so,
8617 count those bits and return one less than that amount. If we can't
8618 safely compute the mask for this mode, always return BITWIDTH. */
8620 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8623 nonzero
= nonzero_bits (x
, mode
);
8624 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8625 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8628 /* Return the number of "extended" bits there are in X, when interpreted
8629 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8630 unsigned quantities, this is the number of high-order zero bits.
8631 For signed quantities, this is the number of copies of the sign bit
8632 minus 1. In both case, this function returns the number of "spare"
8633 bits. For example, if two quantities for which this function returns
8634 at least 1 are added, the addition is known not to overflow.
8636 This function will always return 0 unless called during combine, which
8637 implies that it must be called from a define_split. */
8640 extended_count (x
, mode
, unsignedp
)
8642 enum machine_mode mode
;
8645 if (nonzero_sign_valid
== 0)
8649 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8650 ? (GET_MODE_BITSIZE (mode
) - 1
8651 - floor_log2 (nonzero_bits (x
, mode
)))
8653 : num_sign_bit_copies (x
, mode
) - 1);
8656 /* This function is called from `simplify_shift_const' to merge two
8657 outer operations. Specifically, we have already found that we need
8658 to perform operation *POP0 with constant *PCONST0 at the outermost
8659 position. We would now like to also perform OP1 with constant CONST1
8660 (with *POP0 being done last).
8662 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8663 the resulting operation. *PCOMP_P is set to 1 if we would need to
8664 complement the innermost operand, otherwise it is unchanged.
8666 MODE is the mode in which the operation will be done. No bits outside
8667 the width of this mode matter. It is assumed that the width of this mode
8668 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8670 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8671 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8672 result is simply *PCONST0.
8674 If the resulting operation cannot be expressed as one operation, we
8675 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8678 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8679 enum rtx_code
*pop0
;
8680 HOST_WIDE_INT
*pconst0
;
8682 HOST_WIDE_INT const1
;
8683 enum machine_mode mode
;
8686 enum rtx_code op0
= *pop0
;
8687 HOST_WIDE_INT const0
= *pconst0
;
8689 const0
&= GET_MODE_MASK (mode
);
8690 const1
&= GET_MODE_MASK (mode
);
8692 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8696 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8699 if (op1
== NIL
|| op0
== SET
)
8702 else if (op0
== NIL
)
8703 op0
= op1
, const0
= const1
;
8705 else if (op0
== op1
)
8729 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8730 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8733 /* If the two constants aren't the same, we can't do anything. The
8734 remaining six cases can all be done. */
8735 else if (const0
!= const1
)
8743 /* (a & b) | b == b */
8745 else /* op1 == XOR */
8746 /* (a ^ b) | b == a | b */
8752 /* (a & b) ^ b == (~a) & b */
8753 op0
= AND
, *pcomp_p
= 1;
8754 else /* op1 == IOR */
8755 /* (a | b) ^ b == a & ~b */
8756 op0
= AND
, *pconst0
= ~const0
;
8761 /* (a | b) & b == b */
8763 else /* op1 == XOR */
8764 /* (a ^ b) & b) == (~a) & b */
8771 /* Check for NO-OP cases. */
8772 const0
&= GET_MODE_MASK (mode
);
8774 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8776 else if (const0
== 0 && op0
== AND
)
8778 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8782 /* ??? Slightly redundant with the above mask, but not entirely.
8783 Moving this above means we'd have to sign-extend the mode mask
8784 for the final test. */
8785 const0
= trunc_int_for_mode (const0
, mode
);
8793 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8794 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8795 that we started with.
8797 The shift is normally computed in the widest mode we find in VAROP, as
8798 long as it isn't a different number of words than RESULT_MODE. Exceptions
8799 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8802 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8805 enum machine_mode result_mode
;
8809 enum rtx_code orig_code
= code
;
8810 int orig_count
= input_count
;
8813 enum machine_mode mode
= result_mode
;
8814 enum machine_mode shift_mode
, tmode
;
8815 unsigned int mode_words
8816 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8817 /* We form (outer_op (code varop count) (outer_const)). */
8818 enum rtx_code outer_op
= NIL
;
8819 HOST_WIDE_INT outer_const
= 0;
8821 int complement_p
= 0;
8824 /* If we were given an invalid count, don't do anything except exactly
8825 what was requested. */
8827 if (input_count
< 0 || input_count
>= (int) GET_MODE_BITSIZE (mode
))
8832 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8835 count
= input_count
;
8837 /* Make sure and truncate the "natural" shift on the way in. We don't
8838 want to do this inside the loop as it makes it more difficult to
8840 #ifdef SHIFT_COUNT_TRUNCATED
8841 if (SHIFT_COUNT_TRUNCATED
)
8842 count
%= GET_MODE_BITSIZE (mode
);
8845 /* Unless one of the branches of the `if' in this loop does a `continue',
8846 we will `break' the loop after the `if'. */
8850 /* If we have an operand of (clobber (const_int 0)), just return that
8852 if (GET_CODE (varop
) == CLOBBER
)
8855 /* If we discovered we had to complement VAROP, leave. Making a NOT
8856 here would cause an infinite loop. */
8860 /* Convert ROTATERT to ROTATE. */
8861 if (code
== ROTATERT
)
8862 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8864 /* We need to determine what mode we will do the shift in. If the
8865 shift is a right shift or a ROTATE, we must always do it in the mode
8866 it was originally done in. Otherwise, we can do it in MODE, the
8867 widest mode encountered. */
8869 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8870 ? result_mode
: mode
);
8872 /* Handle cases where the count is greater than the size of the mode
8873 minus 1. For ASHIFT, use the size minus one as the count (this can
8874 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8875 take the count modulo the size. For other shifts, the result is
8878 Since these shifts are being produced by the compiler by combining
8879 multiple operations, each of which are defined, we know what the
8880 result is supposed to be. */
8882 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8884 if (code
== ASHIFTRT
)
8885 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8886 else if (code
== ROTATE
|| code
== ROTATERT
)
8887 count
%= GET_MODE_BITSIZE (shift_mode
);
8890 /* We can't simply return zero because there may be an
8898 /* An arithmetic right shift of a quantity known to be -1 or 0
8900 if (code
== ASHIFTRT
8901 && (num_sign_bit_copies (varop
, shift_mode
)
8902 == GET_MODE_BITSIZE (shift_mode
)))
8908 /* If we are doing an arithmetic right shift and discarding all but
8909 the sign bit copies, this is equivalent to doing a shift by the
8910 bitsize minus one. Convert it into that shift because it will often
8911 allow other simplifications. */
8913 if (code
== ASHIFTRT
8914 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8915 >= GET_MODE_BITSIZE (shift_mode
)))
8916 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8918 /* We simplify the tests below and elsewhere by converting
8919 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8920 `make_compound_operation' will convert it to a ASHIFTRT for
8921 those machines (such as VAX) that don't have a LSHIFTRT. */
8922 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8924 && ((nonzero_bits (varop
, shift_mode
)
8925 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8929 switch (GET_CODE (varop
))
8935 new = expand_compound_operation (varop
);
8944 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8945 minus the width of a smaller mode, we can do this with a
8946 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8947 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8948 && ! mode_dependent_address_p (XEXP (varop
, 0))
8949 && ! MEM_VOLATILE_P (varop
)
8950 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8951 MODE_INT
, 1)) != BLKmode
)
8953 new = adjust_address_nv (varop
, tmode
,
8954 BYTES_BIG_ENDIAN
? 0
8955 : count
/ BITS_PER_UNIT
);
8957 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8958 : ZERO_EXTEND
, mode
, new);
8965 /* Similar to the case above, except that we can only do this if
8966 the resulting mode is the same as that of the underlying
8967 MEM and adjust the address depending on the *bits* endianness
8968 because of the way that bit-field extract insns are defined. */
8969 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8970 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8971 MODE_INT
, 1)) != BLKmode
8972 && tmode
== GET_MODE (XEXP (varop
, 0)))
8974 if (BITS_BIG_ENDIAN
)
8975 new = XEXP (varop
, 0);
8978 new = copy_rtx (XEXP (varop
, 0));
8979 SUBST (XEXP (new, 0),
8980 plus_constant (XEXP (new, 0),
8981 count
/ BITS_PER_UNIT
));
8984 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8985 : ZERO_EXTEND
, mode
, new);
8992 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8993 the same number of words as what we've seen so far. Then store
8994 the widest mode in MODE. */
8995 if (subreg_lowpart_p (varop
)
8996 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8997 > GET_MODE_SIZE (GET_MODE (varop
)))
8998 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8999 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9002 varop
= SUBREG_REG (varop
);
9003 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9004 mode
= GET_MODE (varop
);
9010 /* Some machines use MULT instead of ASHIFT because MULT
9011 is cheaper. But it is still better on those machines to
9012 merge two shifts into one. */
9013 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9014 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9017 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9018 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9024 /* Similar, for when divides are cheaper. */
9025 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9026 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9029 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9030 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9036 /* If we are extracting just the sign bit of an arithmetic
9037 right shift, that shift is not needed. However, the sign
9038 bit of a wider mode may be different from what would be
9039 interpreted as the sign bit in a narrower mode, so, if
9040 the result is narrower, don't discard the shift. */
9041 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9042 && (GET_MODE_BITSIZE (result_mode
)
9043 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9045 varop
= XEXP (varop
, 0);
9049 /* ... fall through ... */
9054 /* Here we have two nested shifts. The result is usually the
9055 AND of a new shift with a mask. We compute the result below. */
9056 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9057 && INTVAL (XEXP (varop
, 1)) >= 0
9058 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9059 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9060 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9062 enum rtx_code first_code
= GET_CODE (varop
);
9063 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9064 unsigned HOST_WIDE_INT mask
;
9067 /* We have one common special case. We can't do any merging if
9068 the inner code is an ASHIFTRT of a smaller mode. However, if
9069 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9070 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9071 we can convert it to
9072 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9073 This simplifies certain SIGN_EXTEND operations. */
9074 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9075 && (GET_MODE_BITSIZE (result_mode
)
9076 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9078 /* C3 has the low-order C1 bits zero. */
9080 mask
= (GET_MODE_MASK (mode
)
9081 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9083 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9084 XEXP (varop
, 0), mask
);
9085 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9087 count
= first_count
;
9092 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9093 than C1 high-order bits equal to the sign bit, we can convert
9094 this to either an ASHIFT or a ASHIFTRT depending on the
9097 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9099 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9100 && GET_MODE (varop
) == shift_mode
9101 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9104 varop
= XEXP (varop
, 0);
9106 signed_count
= count
- first_count
;
9107 if (signed_count
< 0)
9108 count
= -signed_count
, code
= ASHIFT
;
9110 count
= signed_count
;
9115 /* There are some cases we can't do. If CODE is ASHIFTRT,
9116 we can only do this if FIRST_CODE is also ASHIFTRT.
9118 We can't do the case when CODE is ROTATE and FIRST_CODE is
9121 If the mode of this shift is not the mode of the outer shift,
9122 we can't do this if either shift is a right shift or ROTATE.
9124 Finally, we can't do any of these if the mode is too wide
9125 unless the codes are the same.
9127 Handle the case where the shift codes are the same
9130 if (code
== first_code
)
9132 if (GET_MODE (varop
) != result_mode
9133 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9137 count
+= first_count
;
9138 varop
= XEXP (varop
, 0);
9142 if (code
== ASHIFTRT
9143 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9144 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9145 || (GET_MODE (varop
) != result_mode
9146 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9147 || first_code
== ROTATE
9148 || code
== ROTATE
)))
9151 /* To compute the mask to apply after the shift, shift the
9152 nonzero bits of the inner shift the same way the
9153 outer shift will. */
9155 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9158 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9161 /* Give up if we can't compute an outer operation to use. */
9163 || GET_CODE (mask_rtx
) != CONST_INT
9164 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9166 result_mode
, &complement_p
))
9169 /* If the shifts are in the same direction, we add the
9170 counts. Otherwise, we subtract them. */
9171 signed_count
= count
;
9172 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9173 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9174 signed_count
+= first_count
;
9176 signed_count
-= first_count
;
9178 /* If COUNT is positive, the new shift is usually CODE,
9179 except for the two exceptions below, in which case it is
9180 FIRST_CODE. If the count is negative, FIRST_CODE should
9182 if (signed_count
> 0
9183 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9184 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9185 code
= first_code
, count
= signed_count
;
9186 else if (signed_count
< 0)
9187 code
= first_code
, count
= -signed_count
;
9189 count
= signed_count
;
9191 varop
= XEXP (varop
, 0);
9195 /* If we have (A << B << C) for any shift, we can convert this to
9196 (A << C << B). This wins if A is a constant. Only try this if
9197 B is not a constant. */
9199 else if (GET_CODE (varop
) == code
9200 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9202 = simplify_binary_operation (code
, mode
,
9206 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9213 /* Make this fit the case below. */
9214 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9215 GEN_INT (GET_MODE_MASK (mode
)));
9221 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9222 with C the size of VAROP - 1 and the shift is logical if
9223 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9224 we have an (le X 0) operation. If we have an arithmetic shift
9225 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9226 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9228 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9229 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9230 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9231 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9232 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9233 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9236 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9239 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9240 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9245 /* If we have (shift (logical)), move the logical to the outside
9246 to allow it to possibly combine with another logical and the
9247 shift to combine with another shift. This also canonicalizes to
9248 what a ZERO_EXTRACT looks like. Also, some machines have
9249 (and (shift)) insns. */
9251 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9252 && (new = simplify_binary_operation (code
, result_mode
,
9254 GEN_INT (count
))) != 0
9255 && GET_CODE (new) == CONST_INT
9256 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9257 INTVAL (new), result_mode
, &complement_p
))
9259 varop
= XEXP (varop
, 0);
9263 /* If we can't do that, try to simplify the shift in each arm of the
9264 logical expression, make a new logical expression, and apply
9265 the inverse distributive law. */
9267 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9268 XEXP (varop
, 0), count
);
9269 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9270 XEXP (varop
, 1), count
);
9272 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9273 varop
= apply_distributive_law (varop
);
9280 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9281 says that the sign bit can be tested, FOO has mode MODE, C is
9282 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9283 that may be nonzero. */
9284 if (code
== LSHIFTRT
9285 && XEXP (varop
, 1) == const0_rtx
9286 && GET_MODE (XEXP (varop
, 0)) == result_mode
9287 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9288 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9289 && ((STORE_FLAG_VALUE
9290 & ((HOST_WIDE_INT
) 1
9291 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9292 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9293 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9294 (HOST_WIDE_INT
) 1, result_mode
,
9297 varop
= XEXP (varop
, 0);
9304 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9305 than the number of bits in the mode is equivalent to A. */
9306 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9307 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9309 varop
= XEXP (varop
, 0);
9314 /* NEG commutes with ASHIFT since it is multiplication. Move the
9315 NEG outside to allow shifts to combine. */
9317 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9318 (HOST_WIDE_INT
) 0, result_mode
,
9321 varop
= XEXP (varop
, 0);
9327 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9328 is one less than the number of bits in the mode is
9329 equivalent to (xor A 1). */
9330 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9331 && XEXP (varop
, 1) == constm1_rtx
9332 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9333 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9334 (HOST_WIDE_INT
) 1, result_mode
,
9338 varop
= XEXP (varop
, 0);
9342 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9343 that might be nonzero in BAR are those being shifted out and those
9344 bits are known zero in FOO, we can replace the PLUS with FOO.
9345 Similarly in the other operand order. This code occurs when
9346 we are computing the size of a variable-size array. */
9348 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9349 && count
< HOST_BITS_PER_WIDE_INT
9350 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9351 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9352 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9354 varop
= XEXP (varop
, 0);
9357 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9358 && count
< HOST_BITS_PER_WIDE_INT
9359 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9360 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9362 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9363 & nonzero_bits (XEXP (varop
, 1),
9366 varop
= XEXP (varop
, 1);
9370 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9372 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9373 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9375 GEN_INT (count
))) != 0
9376 && GET_CODE (new) == CONST_INT
9377 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9378 INTVAL (new), result_mode
, &complement_p
))
9380 varop
= XEXP (varop
, 0);
9386 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9387 with C the size of VAROP - 1 and the shift is logical if
9388 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9389 we have a (gt X 0) operation. If the shift is arithmetic with
9390 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9391 we have a (neg (gt X 0)) operation. */
9393 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9394 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9395 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9396 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9397 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9398 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9399 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9402 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9405 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9406 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9413 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9414 if the truncate does not affect the value. */
9415 if (code
== LSHIFTRT
9416 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9417 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9418 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9419 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9420 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9422 rtx varop_inner
= XEXP (varop
, 0);
9425 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9426 XEXP (varop_inner
, 0),
9428 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9429 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9442 /* We need to determine what mode to do the shift in. If the shift is
9443 a right shift or ROTATE, we must always do it in the mode it was
9444 originally done in. Otherwise, we can do it in MODE, the widest mode
9445 encountered. The code we care about is that of the shift that will
9446 actually be done, not the shift that was originally requested. */
9448 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9449 ? result_mode
: mode
);
9451 /* We have now finished analyzing the shift. The result should be
9452 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9453 OUTER_OP is non-NIL, it is an operation that needs to be applied
9454 to the result of the shift. OUTER_CONST is the relevant constant,
9455 but we must turn off all bits turned off in the shift.
9457 If we were passed a value for X, see if we can use any pieces of
9458 it. If not, make new rtx. */
9460 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9461 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9462 && INTVAL (XEXP (x
, 1)) == count
)
9463 const_rtx
= XEXP (x
, 1);
9465 const_rtx
= GEN_INT (count
);
9467 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9468 && GET_MODE (XEXP (x
, 0)) == shift_mode
9469 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9470 varop
= XEXP (x
, 0);
9471 else if (GET_MODE (varop
) != shift_mode
)
9472 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9474 /* If we can't make the SUBREG, try to return what we were given. */
9475 if (GET_CODE (varop
) == CLOBBER
)
9476 return x
? x
: varop
;
9478 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9483 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9484 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9486 SUBST (XEXP (x
, 0), varop
);
9487 SUBST (XEXP (x
, 1), const_rtx
);
9490 /* If we have an outer operation and we just made a shift, it is
9491 possible that we could have simplified the shift were it not
9492 for the outer operation. So try to do the simplification
9495 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9496 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9497 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9498 INTVAL (XEXP (x
, 1)));
9500 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9501 turn off all the bits that the shift would have turned off. */
9502 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9503 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9504 GET_MODE_MASK (result_mode
) >> orig_count
);
9506 /* Do the remainder of the processing in RESULT_MODE. */
9507 x
= gen_lowpart_for_combine (result_mode
, x
);
9509 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9512 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9514 if (outer_op
!= NIL
)
9516 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9517 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9519 if (outer_op
== AND
)
9520 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9521 else if (outer_op
== SET
)
9522 /* This means that we have determined that the result is
9523 equivalent to a constant. This should be rare. */
9524 x
= GEN_INT (outer_const
);
9525 else if (GET_RTX_CLASS (outer_op
) == '1')
9526 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9528 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9534 /* Like recog, but we receive the address of a pointer to a new pattern.
9535 We try to match the rtx that the pointer points to.
9536 If that fails, we may try to modify or replace the pattern,
9537 storing the replacement into the same pointer object.
9539 Modifications include deletion or addition of CLOBBERs.
9541 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9542 the CLOBBERs are placed.
9544 The value is the final insn code from the pattern ultimately matched,
9548 recog_for_combine (pnewpat
, insn
, pnotes
)
9553 register rtx pat
= *pnewpat
;
9554 int insn_code_number
;
9555 int num_clobbers_to_add
= 0;
9560 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9561 we use to indicate that something didn't match. If we find such a
9562 thing, force rejection. */
9563 if (GET_CODE (pat
) == PARALLEL
)
9564 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9565 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9566 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9569 /* Remove the old notes prior to trying to recognize the new pattern. */
9570 old_notes
= REG_NOTES (insn
);
9571 REG_NOTES (insn
) = 0;
9573 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9575 /* If it isn't, there is the possibility that we previously had an insn
9576 that clobbered some register as a side effect, but the combined
9577 insn doesn't need to do that. So try once more without the clobbers
9578 unless this represents an ASM insn. */
9580 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9581 && GET_CODE (pat
) == PARALLEL
)
9585 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9586 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9589 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9593 SUBST_INT (XVECLEN (pat
, 0), pos
);
9596 pat
= XVECEXP (pat
, 0, 0);
9598 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9601 /* Recognize all noop sets, these will be killed by followup pass. */
9602 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9603 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9605 REG_NOTES (insn
) = old_notes
;
9607 /* If we had any clobbers to add, make a new pattern than contains
9608 them. Then check to make sure that all of them are dead. */
9609 if (num_clobbers_to_add
)
9611 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9612 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9614 + num_clobbers_to_add
)
9615 : num_clobbers_to_add
+ 1));
9617 if (GET_CODE (pat
) == PARALLEL
)
9618 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9619 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9621 XVECEXP (newpat
, 0, 0) = pat
;
9623 add_clobbers (newpat
, insn_code_number
);
9625 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9626 i
< XVECLEN (newpat
, 0); i
++)
9628 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9629 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9631 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9632 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9640 return insn_code_number
;
9643 /* Like gen_lowpart but for use by combine. In combine it is not possible
9644 to create any new pseudoregs. However, it is safe to create
9645 invalid memory addresses, because combine will try to recognize
9646 them and all they will do is make the combine attempt fail.
9648 If for some reason this cannot do its job, an rtx
9649 (clobber (const_int 0)) is returned.
9650 An insn containing that will not be recognized. */
9655 gen_lowpart_for_combine (mode
, x
)
9656 enum machine_mode mode
;
9661 if (GET_MODE (x
) == mode
)
9664 /* We can only support MODE being wider than a word if X is a
9665 constant integer or has a mode the same size. */
9667 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9668 && ! ((GET_MODE (x
) == VOIDmode
9669 && (GET_CODE (x
) == CONST_INT
9670 || GET_CODE (x
) == CONST_DOUBLE
))
9671 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9672 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9674 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9675 won't know what to do. So we will strip off the SUBREG here and
9676 process normally. */
9677 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9680 if (GET_MODE (x
) == mode
)
9684 result
= gen_lowpart_common (mode
, x
);
9685 #ifdef CLASS_CANNOT_CHANGE_MODE
9687 && GET_CODE (result
) == SUBREG
9688 && GET_CODE (SUBREG_REG (result
)) == REG
9689 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9690 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9691 GET_MODE (SUBREG_REG (result
))))
9692 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9698 if (GET_CODE (x
) == MEM
)
9700 register int offset
= 0;
9702 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9704 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9705 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9707 /* If we want to refer to something bigger than the original memref,
9708 generate a perverse subreg instead. That will force a reload
9709 of the original memref X. */
9710 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9711 return gen_rtx_SUBREG (mode
, x
, 0);
9713 if (WORDS_BIG_ENDIAN
)
9714 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9715 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9717 if (BYTES_BIG_ENDIAN
)
9719 /* Adjust the address so that the address-after-the-data is
9721 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9722 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9725 return adjust_address_nv (x
, mode
, offset
);
9728 /* If X is a comparison operator, rewrite it in a new mode. This
9729 probably won't match, but may allow further simplifications. */
9730 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9731 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9733 /* If we couldn't simplify X any other way, just enclose it in a
9734 SUBREG. Normally, this SUBREG won't match, but some patterns may
9735 include an explicit SUBREG or we may simplify it further in combine. */
9741 offset
= subreg_lowpart_offset (mode
, GET_MODE (x
));
9742 res
= simplify_gen_subreg (mode
, x
, GET_MODE (x
), offset
);
9745 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9749 /* These routines make binary and unary operations by first seeing if they
9750 fold; if not, a new expression is allocated. */
9753 gen_binary (code
, mode
, op0
, op1
)
9755 enum machine_mode mode
;
9761 if (GET_RTX_CLASS (code
) == 'c'
9762 && swap_commutative_operands_p (op0
, op1
))
9763 tem
= op0
, op0
= op1
, op1
= tem
;
9765 if (GET_RTX_CLASS (code
) == '<')
9767 enum machine_mode op_mode
= GET_MODE (op0
);
9769 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9770 just (REL_OP X Y). */
9771 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9773 op1
= XEXP (op0
, 1);
9774 op0
= XEXP (op0
, 0);
9775 op_mode
= GET_MODE (op0
);
9778 if (op_mode
== VOIDmode
)
9779 op_mode
= GET_MODE (op1
);
9780 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9783 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9788 /* Put complex operands first and constants second. */
9789 if (GET_RTX_CLASS (code
) == 'c'
9790 && swap_commutative_operands_p (op0
, op1
))
9791 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9793 /* If we are turning off bits already known off in OP0, we need not do
9795 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9796 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9797 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9800 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9803 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9804 comparison code that will be tested.
9806 The result is a possibly different comparison code to use. *POP0 and
9807 *POP1 may be updated.
9809 It is possible that we might detect that a comparison is either always
9810 true or always false. However, we do not perform general constant
9811 folding in combine, so this knowledge isn't useful. Such tautologies
9812 should have been detected earlier. Hence we ignore all such cases. */
9814 static enum rtx_code
9815 simplify_comparison (code
, pop0
, pop1
)
9824 enum machine_mode mode
, tmode
;
9826 /* Try a few ways of applying the same transformation to both operands. */
9829 #ifndef WORD_REGISTER_OPERATIONS
9830 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9831 so check specially. */
9832 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9833 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9834 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9835 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9836 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9837 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9838 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9839 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9840 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9841 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9842 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9843 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9844 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9845 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9846 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9847 && (INTVAL (XEXP (op0
, 1))
9848 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9850 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9852 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9853 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9857 /* If both operands are the same constant shift, see if we can ignore the
9858 shift. We can if the shift is a rotate or if the bits shifted out of
9859 this shift are known to be zero for both inputs and if the type of
9860 comparison is compatible with the shift. */
9861 if (GET_CODE (op0
) == GET_CODE (op1
)
9862 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9863 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9864 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9865 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9866 || (GET_CODE (op0
) == ASHIFTRT
9867 && (code
!= GTU
&& code
!= LTU
9868 && code
!= GEU
&& code
!= LEU
)))
9869 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9870 && INTVAL (XEXP (op0
, 1)) >= 0
9871 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9872 && XEXP (op0
, 1) == XEXP (op1
, 1))
9874 enum machine_mode mode
= GET_MODE (op0
);
9875 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9876 int shift_count
= INTVAL (XEXP (op0
, 1));
9878 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9879 mask
&= (mask
>> shift_count
) << shift_count
;
9880 else if (GET_CODE (op0
) == ASHIFT
)
9881 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9883 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9884 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9885 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9890 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9891 SUBREGs are of the same mode, and, in both cases, the AND would
9892 be redundant if the comparison was done in the narrower mode,
9893 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9894 and the operand's possibly nonzero bits are 0xffffff01; in that case
9895 if we only care about QImode, we don't need the AND). This case
9896 occurs if the output mode of an scc insn is not SImode and
9897 STORE_FLAG_VALUE == 1 (e.g., the 386).
9899 Similarly, check for a case where the AND's are ZERO_EXTEND
9900 operations from some narrower mode even though a SUBREG is not
9903 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9904 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9905 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9907 rtx inner_op0
= XEXP (op0
, 0);
9908 rtx inner_op1
= XEXP (op1
, 0);
9909 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9910 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9913 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9914 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9915 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9916 && (GET_MODE (SUBREG_REG (inner_op0
))
9917 == GET_MODE (SUBREG_REG (inner_op1
)))
9918 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9919 <= HOST_BITS_PER_WIDE_INT
)
9920 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9921 GET_MODE (SUBREG_REG (inner_op0
)))))
9922 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9923 GET_MODE (SUBREG_REG (inner_op1
))))))
9925 op0
= SUBREG_REG (inner_op0
);
9926 op1
= SUBREG_REG (inner_op1
);
9928 /* The resulting comparison is always unsigned since we masked
9929 off the original sign bit. */
9930 code
= unsigned_condition (code
);
9936 for (tmode
= GET_CLASS_NARROWEST_MODE
9937 (GET_MODE_CLASS (GET_MODE (op0
)));
9938 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9939 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9941 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9942 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9943 code
= unsigned_condition (code
);
9952 /* If both operands are NOT, we can strip off the outer operation
9953 and adjust the comparison code for swapped operands; similarly for
9954 NEG, except that this must be an equality comparison. */
9955 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9956 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9957 && (code
== EQ
|| code
== NE
)))
9958 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9964 /* If the first operand is a constant, swap the operands and adjust the
9965 comparison code appropriately, but don't do this if the second operand
9966 is already a constant integer. */
9967 if (swap_commutative_operands_p (op0
, op1
))
9969 tem
= op0
, op0
= op1
, op1
= tem
;
9970 code
= swap_condition (code
);
9973 /* We now enter a loop during which we will try to simplify the comparison.
9974 For the most part, we only are concerned with comparisons with zero,
9975 but some things may really be comparisons with zero but not start
9976 out looking that way. */
9978 while (GET_CODE (op1
) == CONST_INT
)
9980 enum machine_mode mode
= GET_MODE (op0
);
9981 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9982 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9983 int equality_comparison_p
;
9984 int sign_bit_comparison_p
;
9985 int unsigned_comparison_p
;
9986 HOST_WIDE_INT const_op
;
9988 /* We only want to handle integral modes. This catches VOIDmode,
9989 CCmode, and the floating-point modes. An exception is that we
9990 can handle VOIDmode if OP0 is a COMPARE or a comparison
9993 if (GET_MODE_CLASS (mode
) != MODE_INT
9994 && ! (mode
== VOIDmode
9995 && (GET_CODE (op0
) == COMPARE
9996 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9999 /* Get the constant we are comparing against and turn off all bits
10000 not on in our mode. */
10001 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10002 op1
= GEN_INT (const_op
);
10004 /* If we are comparing against a constant power of two and the value
10005 being compared can only have that single bit nonzero (e.g., it was
10006 `and'ed with that bit), we can replace this with a comparison
10009 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10010 || code
== LT
|| code
== LTU
)
10011 && mode_width
<= HOST_BITS_PER_WIDE_INT
10012 && exact_log2 (const_op
) >= 0
10013 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10015 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10016 op1
= const0_rtx
, const_op
= 0;
10019 /* Similarly, if we are comparing a value known to be either -1 or
10020 0 with -1, change it to the opposite comparison against zero. */
10023 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10024 || code
== GEU
|| code
== LTU
)
10025 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10027 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10028 op1
= const0_rtx
, const_op
= 0;
10031 /* Do some canonicalizations based on the comparison code. We prefer
10032 comparisons against zero and then prefer equality comparisons.
10033 If we can reduce the size of a constant, we will do that too. */
10038 /* < C is equivalent to <= (C - 1) */
10042 op1
= GEN_INT (const_op
);
10044 /* ... fall through to LE case below. */
10050 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10054 op1
= GEN_INT (const_op
);
10058 /* If we are doing a <= 0 comparison on a value known to have
10059 a zero sign bit, we can replace this with == 0. */
10060 else if (const_op
== 0
10061 && mode_width
<= HOST_BITS_PER_WIDE_INT
10062 && (nonzero_bits (op0
, mode
)
10063 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10068 /* >= C is equivalent to > (C - 1). */
10072 op1
= GEN_INT (const_op
);
10074 /* ... fall through to GT below. */
10080 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10084 op1
= GEN_INT (const_op
);
10088 /* If we are doing a > 0 comparison on a value known to have
10089 a zero sign bit, we can replace this with != 0. */
10090 else if (const_op
== 0
10091 && mode_width
<= HOST_BITS_PER_WIDE_INT
10092 && (nonzero_bits (op0
, mode
)
10093 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10098 /* < C is equivalent to <= (C - 1). */
10102 op1
= GEN_INT (const_op
);
10104 /* ... fall through ... */
10107 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10108 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10109 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10111 const_op
= 0, op1
= const0_rtx
;
10119 /* unsigned <= 0 is equivalent to == 0 */
10123 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10124 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10125 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10127 const_op
= 0, op1
= const0_rtx
;
10133 /* >= C is equivalent to < (C - 1). */
10137 op1
= GEN_INT (const_op
);
10139 /* ... fall through ... */
10142 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10143 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10144 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10146 const_op
= 0, op1
= const0_rtx
;
10154 /* unsigned > 0 is equivalent to != 0 */
10158 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10159 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10160 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10162 const_op
= 0, op1
= const0_rtx
;
10171 /* Compute some predicates to simplify code below. */
10173 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10174 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10175 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10178 /* If this is a sign bit comparison and we can do arithmetic in
10179 MODE, say that we will only be needing the sign bit of OP0. */
10180 if (sign_bit_comparison_p
10181 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10182 op0
= force_to_mode (op0
, mode
,
10184 << (GET_MODE_BITSIZE (mode
) - 1)),
10187 /* Now try cases based on the opcode of OP0. If none of the cases
10188 does a "continue", we exit this loop immediately after the
10191 switch (GET_CODE (op0
))
10194 /* If we are extracting a single bit from a variable position in
10195 a constant that has only a single bit set and are comparing it
10196 with zero, we can convert this into an equality comparison
10197 between the position and the location of the single bit. */
10199 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10200 && XEXP (op0
, 1) == const1_rtx
10201 && equality_comparison_p
&& const_op
== 0
10202 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10204 if (BITS_BIG_ENDIAN
)
10206 enum machine_mode new_mode
10207 = mode_for_extraction (EP_extzv
, 1);
10208 if (new_mode
== MAX_MACHINE_MODE
)
10209 i
= BITS_PER_WORD
- 1 - i
;
10213 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10217 op0
= XEXP (op0
, 2);
10221 /* Result is nonzero iff shift count is equal to I. */
10222 code
= reverse_condition (code
);
10226 /* ... fall through ... */
10229 tem
= expand_compound_operation (op0
);
10238 /* If testing for equality, we can take the NOT of the constant. */
10239 if (equality_comparison_p
10240 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10242 op0
= XEXP (op0
, 0);
10247 /* If just looking at the sign bit, reverse the sense of the
10249 if (sign_bit_comparison_p
)
10251 op0
= XEXP (op0
, 0);
10252 code
= (code
== GE
? LT
: GE
);
10258 /* If testing for equality, we can take the NEG of the constant. */
10259 if (equality_comparison_p
10260 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10262 op0
= XEXP (op0
, 0);
10267 /* The remaining cases only apply to comparisons with zero. */
10271 /* When X is ABS or is known positive,
10272 (neg X) is < 0 if and only if X != 0. */
10274 if (sign_bit_comparison_p
10275 && (GET_CODE (XEXP (op0
, 0)) == ABS
10276 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10277 && (nonzero_bits (XEXP (op0
, 0), mode
)
10278 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10280 op0
= XEXP (op0
, 0);
10281 code
= (code
== LT
? NE
: EQ
);
10285 /* If we have NEG of something whose two high-order bits are the
10286 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10287 if (num_sign_bit_copies (op0
, mode
) >= 2)
10289 op0
= XEXP (op0
, 0);
10290 code
= swap_condition (code
);
10296 /* If we are testing equality and our count is a constant, we
10297 can perform the inverse operation on our RHS. */
10298 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10299 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10300 op1
, XEXP (op0
, 1))) != 0)
10302 op0
= XEXP (op0
, 0);
10307 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10308 a particular bit. Convert it to an AND of a constant of that
10309 bit. This will be converted into a ZERO_EXTRACT. */
10310 if (const_op
== 0 && sign_bit_comparison_p
10311 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10312 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10314 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10317 - INTVAL (XEXP (op0
, 1)))));
10318 code
= (code
== LT
? NE
: EQ
);
10322 /* Fall through. */
10325 /* ABS is ignorable inside an equality comparison with zero. */
10326 if (const_op
== 0 && equality_comparison_p
)
10328 op0
= XEXP (op0
, 0);
10334 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10335 to (compare FOO CONST) if CONST fits in FOO's mode and we
10336 are either testing inequality or have an unsigned comparison
10337 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10338 if (! unsigned_comparison_p
10339 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10340 <= HOST_BITS_PER_WIDE_INT
)
10341 && ((unsigned HOST_WIDE_INT
) const_op
10342 < (((unsigned HOST_WIDE_INT
) 1
10343 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10345 op0
= XEXP (op0
, 0);
10351 /* Check for the case where we are comparing A - C1 with C2,
10352 both constants are smaller than 1/2 the maximum positive
10353 value in MODE, and the comparison is equality or unsigned.
10354 In that case, if A is either zero-extended to MODE or has
10355 sufficient sign bits so that the high-order bit in MODE
10356 is a copy of the sign in the inner mode, we can prove that it is
10357 safe to do the operation in the wider mode. This simplifies
10358 many range checks. */
10360 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10361 && subreg_lowpart_p (op0
)
10362 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10363 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10364 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10365 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10366 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10367 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10368 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10369 GET_MODE (SUBREG_REG (op0
)))
10370 & ~GET_MODE_MASK (mode
))
10371 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10372 GET_MODE (SUBREG_REG (op0
)))
10373 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10374 - GET_MODE_BITSIZE (mode
)))))
10376 op0
= SUBREG_REG (op0
);
10380 /* If the inner mode is narrower and we are extracting the low part,
10381 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10382 if (subreg_lowpart_p (op0
)
10383 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10384 /* Fall through */ ;
10388 /* ... fall through ... */
10391 if ((unsigned_comparison_p
|| equality_comparison_p
)
10392 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10393 <= HOST_BITS_PER_WIDE_INT
)
10394 && ((unsigned HOST_WIDE_INT
) const_op
10395 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10397 op0
= XEXP (op0
, 0);
10403 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10404 this for equality comparisons due to pathological cases involving
10406 if (equality_comparison_p
10407 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10408 op1
, XEXP (op0
, 1))))
10410 op0
= XEXP (op0
, 0);
10415 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10416 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10417 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10419 op0
= XEXP (XEXP (op0
, 0), 0);
10420 code
= (code
== LT
? EQ
: NE
);
10426 /* We used to optimize signed comparisons against zero, but that
10427 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10428 arrive here as equality comparisons, or (GEU, LTU) are
10429 optimized away. No need to special-case them. */
10431 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10432 (eq B (minus A C)), whichever simplifies. We can only do
10433 this for equality comparisons due to pathological cases involving
10435 if (equality_comparison_p
10436 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10437 XEXP (op0
, 1), op1
)))
10439 op0
= XEXP (op0
, 0);
10444 if (equality_comparison_p
10445 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10446 XEXP (op0
, 0), op1
)))
10448 op0
= XEXP (op0
, 1);
10453 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10454 of bits in X minus 1, is one iff X > 0. */
10455 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10456 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10457 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10458 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10460 op0
= XEXP (op0
, 1);
10461 code
= (code
== GE
? LE
: GT
);
10467 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10468 if C is zero or B is a constant. */
10469 if (equality_comparison_p
10470 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10471 XEXP (op0
, 1), op1
)))
10473 op0
= XEXP (op0
, 0);
10480 case UNEQ
: case LTGT
:
10481 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10482 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10483 case UNORDERED
: case ORDERED
:
10484 /* We can't do anything if OP0 is a condition code value, rather
10485 than an actual data value. */
10488 || XEXP (op0
, 0) == cc0_rtx
10490 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10493 /* Get the two operands being compared. */
10494 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10495 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10497 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10499 /* Check for the cases where we simply want the result of the
10500 earlier test or the opposite of that result. */
10501 if (code
== NE
|| code
== EQ
10502 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10503 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10504 && (STORE_FLAG_VALUE
10505 & (((HOST_WIDE_INT
) 1
10506 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10507 && (code
== LT
|| code
== GE
)))
10509 enum rtx_code new_code
;
10510 if (code
== LT
|| code
== NE
)
10511 new_code
= GET_CODE (op0
);
10513 new_code
= combine_reversed_comparison_code (op0
);
10515 if (new_code
!= UNKNOWN
)
10526 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10528 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10529 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10530 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10532 op0
= XEXP (op0
, 1);
10533 code
= (code
== GE
? GT
: LE
);
10539 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10540 will be converted to a ZERO_EXTRACT later. */
10541 if (const_op
== 0 && equality_comparison_p
10542 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10543 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10545 op0
= simplify_and_const_int
10546 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10548 XEXP (XEXP (op0
, 0), 1)),
10549 (HOST_WIDE_INT
) 1);
10553 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10554 zero and X is a comparison and C1 and C2 describe only bits set
10555 in STORE_FLAG_VALUE, we can compare with X. */
10556 if (const_op
== 0 && equality_comparison_p
10557 && mode_width
<= HOST_BITS_PER_WIDE_INT
10558 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10559 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10560 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10561 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10562 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10564 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10565 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10566 if ((~STORE_FLAG_VALUE
& mask
) == 0
10567 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10568 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10569 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10571 op0
= XEXP (XEXP (op0
, 0), 0);
10576 /* If we are doing an equality comparison of an AND of a bit equal
10577 to the sign bit, replace this with a LT or GE comparison of
10578 the underlying value. */
10579 if (equality_comparison_p
10581 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10582 && mode_width
<= HOST_BITS_PER_WIDE_INT
10583 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10584 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10586 op0
= XEXP (op0
, 0);
10587 code
= (code
== EQ
? GE
: LT
);
10591 /* If this AND operation is really a ZERO_EXTEND from a narrower
10592 mode, the constant fits within that mode, and this is either an
10593 equality or unsigned comparison, try to do this comparison in
10594 the narrower mode. */
10595 if ((equality_comparison_p
|| unsigned_comparison_p
)
10596 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10597 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10598 & GET_MODE_MASK (mode
))
10600 && const_op
>> i
== 0
10601 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10603 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10607 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10608 in both M1 and M2 and the SUBREG is either paradoxical or
10609 represents the low part, permute the SUBREG and the AND and
10611 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10613 #ifdef WORD_REGISTER_OPERATIONS
10615 > (GET_MODE_BITSIZE
10616 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10617 && mode_width
<= BITS_PER_WORD
)
10620 <= (GET_MODE_BITSIZE
10621 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10622 && subreg_lowpart_p (XEXP (op0
, 0))))
10623 #ifndef WORD_REGISTER_OPERATIONS
10624 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10625 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10626 As originally written the upper bits have a defined value
10627 due to the AND operation. However, if we commute the AND
10628 inside the SUBREG then they no longer have defined values
10629 and the meaning of the code has been changed. */
10630 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10631 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10633 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10634 && mode_width
<= HOST_BITS_PER_WIDE_INT
10635 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10636 <= HOST_BITS_PER_WIDE_INT
)
10637 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10638 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10639 & INTVAL (XEXP (op0
, 1)))
10640 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10641 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10642 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10646 = gen_lowpart_for_combine
10648 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10649 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10653 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10654 (eq (and (lshiftrt X) 1) 0). */
10655 if (const_op
== 0 && equality_comparison_p
10656 && XEXP (op0
, 1) == const1_rtx
10657 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10658 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10660 op0
= simplify_and_const_int
10662 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10663 XEXP (XEXP (op0
, 0), 1)),
10664 (HOST_WIDE_INT
) 1);
10665 code
= (code
== NE
? EQ
: NE
);
10671 /* If we have (compare (ashift FOO N) (const_int C)) and
10672 the high order N bits of FOO (N+1 if an inequality comparison)
10673 are known to be zero, we can do this by comparing FOO with C
10674 shifted right N bits so long as the low-order N bits of C are
10676 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10677 && INTVAL (XEXP (op0
, 1)) >= 0
10678 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10679 < HOST_BITS_PER_WIDE_INT
)
10681 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10682 && mode_width
<= HOST_BITS_PER_WIDE_INT
10683 && (nonzero_bits (XEXP (op0
, 0), mode
)
10684 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10685 + ! equality_comparison_p
))) == 0)
10687 /* We must perform a logical shift, not an arithmetic one,
10688 as we want the top N bits of C to be zero. */
10689 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10691 temp
>>= INTVAL (XEXP (op0
, 1));
10692 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10693 op0
= XEXP (op0
, 0);
10697 /* If we are doing a sign bit comparison, it means we are testing
10698 a particular bit. Convert it to the appropriate AND. */
10699 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10700 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10702 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10705 - INTVAL (XEXP (op0
, 1)))));
10706 code
= (code
== LT
? NE
: EQ
);
10710 /* If this an equality comparison with zero and we are shifting
10711 the low bit to the sign bit, we can convert this to an AND of the
10713 if (const_op
== 0 && equality_comparison_p
10714 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10715 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10717 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10718 (HOST_WIDE_INT
) 1);
10724 /* If this is an equality comparison with zero, we can do this
10725 as a logical shift, which might be much simpler. */
10726 if (equality_comparison_p
&& const_op
== 0
10727 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10729 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10731 INTVAL (XEXP (op0
, 1)));
10735 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10736 do the comparison in a narrower mode. */
10737 if (! unsigned_comparison_p
10738 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10739 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10740 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10741 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10742 MODE_INT
, 1)) != BLKmode
10743 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10744 || ((unsigned HOST_WIDE_INT
) -const_op
10745 <= GET_MODE_MASK (tmode
))))
10747 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10751 /* Likewise if OP0 is a PLUS of a sign extension with a
10752 constant, which is usually represented with the PLUS
10753 between the shifts. */
10754 if (! unsigned_comparison_p
10755 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10756 && GET_CODE (XEXP (op0
, 0)) == PLUS
10757 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10758 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10759 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10760 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10761 MODE_INT
, 1)) != BLKmode
10762 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10763 || ((unsigned HOST_WIDE_INT
) -const_op
10764 <= GET_MODE_MASK (tmode
))))
10766 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10767 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10768 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10771 op0
= gen_binary (PLUS
, tmode
,
10772 gen_lowpart_for_combine (tmode
, inner
),
10777 /* ... fall through ... */
10779 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10780 the low order N bits of FOO are known to be zero, we can do this
10781 by comparing FOO with C shifted left N bits so long as no
10782 overflow occurs. */
10783 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10784 && INTVAL (XEXP (op0
, 1)) >= 0
10785 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10786 && mode_width
<= HOST_BITS_PER_WIDE_INT
10787 && (nonzero_bits (XEXP (op0
, 0), mode
)
10788 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10790 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10793 const_op
<<= INTVAL (XEXP (op0
, 1));
10794 op1
= GEN_INT (const_op
);
10795 op0
= XEXP (op0
, 0);
10799 /* If we are using this shift to extract just the sign bit, we
10800 can replace this with an LT or GE comparison. */
10802 && (equality_comparison_p
|| sign_bit_comparison_p
)
10803 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10804 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10806 op0
= XEXP (op0
, 0);
10807 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10819 /* Now make any compound operations involved in this comparison. Then,
10820 check for an outmost SUBREG on OP0 that is not doing anything or is
10821 paradoxical. The latter case can only occur when it is known that the
10822 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10823 We can never remove a SUBREG for a non-equality comparison because the
10824 sign bit is in a different place in the underlying object. */
10826 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10827 op1
= make_compound_operation (op1
, SET
);
10829 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10830 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10831 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10832 && (code
== NE
|| code
== EQ
)
10833 && ((GET_MODE_SIZE (GET_MODE (op0
))
10834 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10836 op0
= SUBREG_REG (op0
);
10837 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10840 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10841 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10842 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10843 && (code
== NE
|| code
== EQ
)
10844 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10845 <= HOST_BITS_PER_WIDE_INT
)
10846 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10847 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
10848 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10850 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10851 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
10852 op0
= SUBREG_REG (op0
), op1
= tem
;
10854 /* We now do the opposite procedure: Some machines don't have compare
10855 insns in all modes. If OP0's mode is an integer mode smaller than a
10856 word and we can't do a compare in that mode, see if there is a larger
10857 mode for which we can do the compare. There are a number of cases in
10858 which we can use the wider mode. */
10860 mode
= GET_MODE (op0
);
10861 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10862 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10863 && ! have_insn_for (COMPARE
, mode
))
10864 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10866 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10867 tmode
= GET_MODE_WIDER_MODE (tmode
))
10868 if (have_insn_for (COMPARE
, tmode
))
10870 /* If the only nonzero bits in OP0 and OP1 are those in the
10871 narrower mode and this is an equality or unsigned comparison,
10872 we can use the wider mode. Similarly for sign-extended
10873 values, in which case it is true for all comparisons. */
10874 if (((code
== EQ
|| code
== NE
10875 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10876 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
10877 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
10878 || ((num_sign_bit_copies (op0
, tmode
)
10879 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10880 && (num_sign_bit_copies (op1
, tmode
)
10881 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10883 /* If OP0 is an AND and we don't have an AND in MODE either,
10884 make a new AND in the proper mode. */
10885 if (GET_CODE (op0
) == AND
10886 && !have_insn_for (AND
, mode
))
10887 op0
= gen_binary (AND
, tmode
,
10888 gen_lowpart_for_combine (tmode
,
10890 gen_lowpart_for_combine (tmode
,
10893 op0
= gen_lowpart_for_combine (tmode
, op0
);
10894 op1
= gen_lowpart_for_combine (tmode
, op1
);
10898 /* If this is a test for negative, we can make an explicit
10899 test of the sign bit. */
10901 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10902 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10904 op0
= gen_binary (AND
, tmode
,
10905 gen_lowpart_for_combine (tmode
, op0
),
10906 GEN_INT ((HOST_WIDE_INT
) 1
10907 << (GET_MODE_BITSIZE (mode
) - 1)));
10908 code
= (code
== LT
) ? NE
: EQ
;
10913 #ifdef CANONICALIZE_COMPARISON
10914 /* If this machine only supports a subset of valid comparisons, see if we
10915 can convert an unsupported one into a supported one. */
10916 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10925 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10926 searching backward. */
10927 static enum rtx_code
10928 combine_reversed_comparison_code (exp
)
10931 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10934 if (code1
!= UNKNOWN
10935 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10937 /* Otherwise try and find where the condition codes were last set and
10939 x
= get_last_value (XEXP (exp
, 0));
10940 if (!x
|| GET_CODE (x
) != COMPARE
)
10942 return reversed_comparison_code_parts (GET_CODE (exp
),
10943 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10945 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10946 Return NULL_RTX in case we fail to do the reversal. */
10948 reversed_comparison (exp
, mode
, op0
, op1
)
10950 enum machine_mode mode
;
10952 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10953 if (reversed_code
== UNKNOWN
)
10956 return gen_binary (reversed_code
, mode
, op0
, op1
);
10959 /* Utility function for following routine. Called when X is part of a value
10960 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10961 for each register mentioned. Similar to mention_regs in cse.c */
10964 update_table_tick (x
)
10967 register enum rtx_code code
= GET_CODE (x
);
10968 register const char *fmt
= GET_RTX_FORMAT (code
);
10973 unsigned int regno
= REGNO (x
);
10974 unsigned int endregno
10975 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10976 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10979 for (r
= regno
; r
< endregno
; r
++)
10980 reg_last_set_table_tick
[r
] = label_tick
;
10985 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10986 /* Note that we can't have an "E" in values stored; see
10987 get_last_value_validate. */
10989 update_table_tick (XEXP (x
, i
));
10992 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10993 are saying that the register is clobbered and we no longer know its
10994 value. If INSN is zero, don't update reg_last_set; this is only permitted
10995 with VALUE also zero and is used to invalidate the register. */
10998 record_value_for_reg (reg
, insn
, value
)
11003 unsigned int regno
= REGNO (reg
);
11004 unsigned int endregno
11005 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11006 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11009 /* If VALUE contains REG and we have a previous value for REG, substitute
11010 the previous value. */
11011 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11015 /* Set things up so get_last_value is allowed to see anything set up to
11017 subst_low_cuid
= INSN_CUID (insn
);
11018 tem
= get_last_value (reg
);
11020 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11021 it isn't going to be useful and will take a lot of time to process,
11022 so just use the CLOBBER. */
11026 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11027 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11028 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11029 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11030 tem
= XEXP (tem
, 0);
11032 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11036 /* For each register modified, show we don't know its value, that
11037 we don't know about its bitwise content, that its value has been
11038 updated, and that we don't know the location of the death of the
11040 for (i
= regno
; i
< endregno
; i
++)
11043 reg_last_set
[i
] = insn
;
11045 reg_last_set_value
[i
] = 0;
11046 reg_last_set_mode
[i
] = 0;
11047 reg_last_set_nonzero_bits
[i
] = 0;
11048 reg_last_set_sign_bit_copies
[i
] = 0;
11049 reg_last_death
[i
] = 0;
11052 /* Mark registers that are being referenced in this value. */
11054 update_table_tick (value
);
11056 /* Now update the status of each register being set.
11057 If someone is using this register in this block, set this register
11058 to invalid since we will get confused between the two lives in this
11059 basic block. This makes using this register always invalid. In cse, we
11060 scan the table to invalidate all entries using this register, but this
11061 is too much work for us. */
11063 for (i
= regno
; i
< endregno
; i
++)
11065 reg_last_set_label
[i
] = label_tick
;
11066 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11067 reg_last_set_invalid
[i
] = 1;
11069 reg_last_set_invalid
[i
] = 0;
11072 /* The value being assigned might refer to X (like in "x++;"). In that
11073 case, we must replace it with (clobber (const_int 0)) to prevent
11075 if (value
&& ! get_last_value_validate (&value
, insn
,
11076 reg_last_set_label
[regno
], 0))
11078 value
= copy_rtx (value
);
11079 if (! get_last_value_validate (&value
, insn
,
11080 reg_last_set_label
[regno
], 1))
11084 /* For the main register being modified, update the value, the mode, the
11085 nonzero bits, and the number of sign bit copies. */
11087 reg_last_set_value
[regno
] = value
;
11091 subst_low_cuid
= INSN_CUID (insn
);
11092 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11093 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11094 reg_last_set_sign_bit_copies
[regno
]
11095 = num_sign_bit_copies (value
, GET_MODE (reg
));
11099 /* Called via note_stores from record_dead_and_set_regs to handle one
11100 SET or CLOBBER in an insn. DATA is the instruction in which the
11101 set is occurring. */
11104 record_dead_and_set_regs_1 (dest
, setter
, data
)
11108 rtx record_dead_insn
= (rtx
) data
;
11110 if (GET_CODE (dest
) == SUBREG
)
11111 dest
= SUBREG_REG (dest
);
11113 if (GET_CODE (dest
) == REG
)
11115 /* If we are setting the whole register, we know its value. Otherwise
11116 show that we don't know the value. We can handle SUBREG in
11118 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11119 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11120 else if (GET_CODE (setter
) == SET
11121 && GET_CODE (SET_DEST (setter
)) == SUBREG
11122 && SUBREG_REG (SET_DEST (setter
)) == dest
11123 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11124 && subreg_lowpart_p (SET_DEST (setter
)))
11125 record_value_for_reg (dest
, record_dead_insn
,
11126 gen_lowpart_for_combine (GET_MODE (dest
),
11127 SET_SRC (setter
)));
11129 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11131 else if (GET_CODE (dest
) == MEM
11132 /* Ignore pushes, they clobber nothing. */
11133 && ! push_operand (dest
, GET_MODE (dest
)))
11134 mem_last_set
= INSN_CUID (record_dead_insn
);
11137 /* Update the records of when each REG was most recently set or killed
11138 for the things done by INSN. This is the last thing done in processing
11139 INSN in the combiner loop.
11141 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11142 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11143 and also the similar information mem_last_set (which insn most recently
11144 modified memory) and last_call_cuid (which insn was the most recent
11145 subroutine call). */
11148 record_dead_and_set_regs (insn
)
11154 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11156 if (REG_NOTE_KIND (link
) == REG_DEAD
11157 && GET_CODE (XEXP (link
, 0)) == REG
)
11159 unsigned int regno
= REGNO (XEXP (link
, 0));
11160 unsigned int endregno
11161 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11162 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11165 for (i
= regno
; i
< endregno
; i
++)
11166 reg_last_death
[i
] = insn
;
11168 else if (REG_NOTE_KIND (link
) == REG_INC
)
11169 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11172 if (GET_CODE (insn
) == CALL_INSN
)
11174 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11175 if (call_used_regs
[i
])
11177 reg_last_set_value
[i
] = 0;
11178 reg_last_set_mode
[i
] = 0;
11179 reg_last_set_nonzero_bits
[i
] = 0;
11180 reg_last_set_sign_bit_copies
[i
] = 0;
11181 reg_last_death
[i
] = 0;
11184 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11187 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11190 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11191 register present in the SUBREG, so for each such SUBREG go back and
11192 adjust nonzero and sign bit information of the registers that are
11193 known to have some zero/sign bits set.
11195 This is needed because when combine blows the SUBREGs away, the
11196 information on zero/sign bits is lost and further combines can be
11197 missed because of that. */
11200 record_promoted_value (insn
, subreg
)
11205 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11206 enum machine_mode mode
= GET_MODE (subreg
);
11208 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11211 for (links
= LOG_LINKS (insn
); links
;)
11213 insn
= XEXP (links
, 0);
11214 set
= single_set (insn
);
11216 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11217 || REGNO (SET_DEST (set
)) != regno
11218 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11220 links
= XEXP (links
, 1);
11224 if (reg_last_set
[regno
] == insn
)
11226 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11227 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11230 if (GET_CODE (SET_SRC (set
)) == REG
)
11232 regno
= REGNO (SET_SRC (set
));
11233 links
= LOG_LINKS (insn
);
11240 /* Scan X for promoted SUBREGs. For each one found,
11241 note what it implies to the registers used in it. */
11244 check_promoted_subreg (insn
, x
)
11248 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11249 && GET_CODE (SUBREG_REG (x
)) == REG
)
11250 record_promoted_value (insn
, x
);
11253 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11256 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11260 check_promoted_subreg (insn
, XEXP (x
, i
));
11264 if (XVEC (x
, i
) != 0)
11265 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11266 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11272 /* Utility routine for the following function. Verify that all the registers
11273 mentioned in *LOC are valid when *LOC was part of a value set when
11274 label_tick == TICK. Return 0 if some are not.
11276 If REPLACE is non-zero, replace the invalid reference with
11277 (clobber (const_int 0)) and return 1. This replacement is useful because
11278 we often can get useful information about the form of a value (e.g., if
11279 it was produced by a shift that always produces -1 or 0) even though
11280 we don't know exactly what registers it was produced from. */
11283 get_last_value_validate (loc
, insn
, tick
, replace
)
11290 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11291 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11294 if (GET_CODE (x
) == REG
)
11296 unsigned int regno
= REGNO (x
);
11297 unsigned int endregno
11298 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11299 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11302 for (j
= regno
; j
< endregno
; j
++)
11303 if (reg_last_set_invalid
[j
]
11304 /* If this is a pseudo-register that was only set once and not
11305 live at the beginning of the function, it is always valid. */
11306 || (! (regno
>= FIRST_PSEUDO_REGISTER
11307 && REG_N_SETS (regno
) == 1
11308 && (! REGNO_REG_SET_P
11309 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11310 && reg_last_set_label
[j
] > tick
))
11313 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11319 /* If this is a memory reference, make sure that there were
11320 no stores after it that might have clobbered the value. We don't
11321 have alias info, so we assume any store invalidates it. */
11322 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11323 && INSN_CUID (insn
) <= mem_last_set
)
11326 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11330 for (i
= 0; i
< len
; i
++)
11332 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11333 /* Don't bother with these. They shouldn't occur anyway. */
11337 /* If we haven't found a reason for it to be invalid, it is valid. */
11341 /* Get the last value assigned to X, if known. Some registers
11342 in the value may be replaced with (clobber (const_int 0)) if their value
11343 is known longer known reliably. */
11349 unsigned int regno
;
11352 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11353 then convert it to the desired mode. If this is a paradoxical SUBREG,
11354 we cannot predict what values the "extra" bits might have. */
11355 if (GET_CODE (x
) == SUBREG
11356 && subreg_lowpart_p (x
)
11357 && (GET_MODE_SIZE (GET_MODE (x
))
11358 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11359 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11360 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11362 if (GET_CODE (x
) != REG
)
11366 value
= reg_last_set_value
[regno
];
11368 /* If we don't have a value, or if it isn't for this basic block and
11369 it's either a hard register, set more than once, or it's a live
11370 at the beginning of the function, return 0.
11372 Because if it's not live at the beginnning of the function then the reg
11373 is always set before being used (is never used without being set).
11374 And, if it's set only once, and it's always set before use, then all
11375 uses must have the same last value, even if it's not from this basic
11379 || (reg_last_set_label
[regno
] != label_tick
11380 && (regno
< FIRST_PSEUDO_REGISTER
11381 || REG_N_SETS (regno
) != 1
11382 || (REGNO_REG_SET_P
11383 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11386 /* If the value was set in a later insn than the ones we are processing,
11387 we can't use it even if the register was only set once. */
11388 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11391 /* If the value has all its registers valid, return it. */
11392 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11393 reg_last_set_label
[regno
], 0))
11396 /* Otherwise, make a copy and replace any invalid register with
11397 (clobber (const_int 0)). If that fails for some reason, return 0. */
11399 value
= copy_rtx (value
);
11400 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11401 reg_last_set_label
[regno
], 1))
11407 /* Return nonzero if expression X refers to a REG or to memory
11408 that is set in an instruction more recent than FROM_CUID. */
11411 use_crosses_set_p (x
, from_cuid
)
11415 register const char *fmt
;
11417 register enum rtx_code code
= GET_CODE (x
);
11421 unsigned int regno
= REGNO (x
);
11422 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11423 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11425 #ifdef PUSH_ROUNDING
11426 /* Don't allow uses of the stack pointer to be moved,
11427 because we don't know whether the move crosses a push insn. */
11428 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11431 for (; regno
< endreg
; regno
++)
11432 if (reg_last_set
[regno
]
11433 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11438 if (code
== MEM
&& mem_last_set
> from_cuid
)
11441 fmt
= GET_RTX_FORMAT (code
);
11443 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11448 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11449 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11452 else if (fmt
[i
] == 'e'
11453 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11459 /* Define three variables used for communication between the following
11462 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11463 static int reg_dead_flag
;
11465 /* Function called via note_stores from reg_dead_at_p.
11467 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11468 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11471 reg_dead_at_p_1 (dest
, x
, data
)
11474 void *data ATTRIBUTE_UNUSED
;
11476 unsigned int regno
, endregno
;
11478 if (GET_CODE (dest
) != REG
)
11481 regno
= REGNO (dest
);
11482 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11483 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11485 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11486 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11489 /* Return non-zero if REG is known to be dead at INSN.
11491 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11492 referencing REG, it is dead. If we hit a SET referencing REG, it is
11493 live. Otherwise, see if it is live or dead at the start of the basic
11494 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11495 must be assumed to be always live. */
11498 reg_dead_at_p (reg
, insn
)
11505 /* Set variables for reg_dead_at_p_1. */
11506 reg_dead_regno
= REGNO (reg
);
11507 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11508 ? HARD_REGNO_NREGS (reg_dead_regno
,
11514 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11515 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11517 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11518 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11522 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11523 beginning of function. */
11524 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11525 insn
= prev_nonnote_insn (insn
))
11527 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11529 return reg_dead_flag
== 1 ? 1 : 0;
11531 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11535 /* Get the basic block number that we were in. */
11540 for (block
= 0; block
< n_basic_blocks
; block
++)
11541 if (insn
== BLOCK_HEAD (block
))
11544 if (block
== n_basic_blocks
)
11548 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11549 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11555 /* Note hard registers in X that are used. This code is similar to
11556 that in flow.c, but much simpler since we don't care about pseudos. */
11559 mark_used_regs_combine (x
)
11562 RTX_CODE code
= GET_CODE (x
);
11563 unsigned int regno
;
11575 case ADDR_DIFF_VEC
:
11578 /* CC0 must die in the insn after it is set, so we don't need to take
11579 special note of it here. */
11585 /* If we are clobbering a MEM, mark any hard registers inside the
11586 address as used. */
11587 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11588 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11593 /* A hard reg in a wide mode may really be multiple registers.
11594 If so, mark all of them just like the first. */
11595 if (regno
< FIRST_PSEUDO_REGISTER
)
11597 unsigned int endregno
, r
;
11599 /* None of this applies to the stack, frame or arg pointers */
11600 if (regno
== STACK_POINTER_REGNUM
11601 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11602 || regno
== HARD_FRAME_POINTER_REGNUM
11604 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11605 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11607 || regno
== FRAME_POINTER_REGNUM
)
11610 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11611 for (r
= regno
; r
< endregno
; r
++)
11612 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11618 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11620 register rtx testreg
= SET_DEST (x
);
11622 while (GET_CODE (testreg
) == SUBREG
11623 || GET_CODE (testreg
) == ZERO_EXTRACT
11624 || GET_CODE (testreg
) == SIGN_EXTRACT
11625 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11626 testreg
= XEXP (testreg
, 0);
11628 if (GET_CODE (testreg
) == MEM
)
11629 mark_used_regs_combine (XEXP (testreg
, 0));
11631 mark_used_regs_combine (SET_SRC (x
));
11639 /* Recursively scan the operands of this expression. */
11642 register const char *fmt
= GET_RTX_FORMAT (code
);
11644 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11647 mark_used_regs_combine (XEXP (x
, i
));
11648 else if (fmt
[i
] == 'E')
11652 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11653 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11659 /* Remove register number REGNO from the dead registers list of INSN.
11661 Return the note used to record the death, if there was one. */
11664 remove_death (regno
, insn
)
11665 unsigned int regno
;
11668 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11672 REG_N_DEATHS (regno
)--;
11673 remove_note (insn
, note
);
11679 /* For each register (hardware or pseudo) used within expression X, if its
11680 death is in an instruction with cuid between FROM_CUID (inclusive) and
11681 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11682 list headed by PNOTES.
11684 That said, don't move registers killed by maybe_kill_insn.
11686 This is done when X is being merged by combination into TO_INSN. These
11687 notes will then be distributed as needed. */
11690 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11692 rtx maybe_kill_insn
;
11697 register const char *fmt
;
11698 register int len
, i
;
11699 register enum rtx_code code
= GET_CODE (x
);
11703 unsigned int regno
= REGNO (x
);
11704 register rtx where_dead
= reg_last_death
[regno
];
11705 register rtx before_dead
, after_dead
;
11707 /* Don't move the register if it gets killed in between from and to */
11708 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11709 && ! reg_referenced_p (x
, maybe_kill_insn
))
11712 /* WHERE_DEAD could be a USE insn made by combine, so first we
11713 make sure that we have insns with valid INSN_CUID values. */
11714 before_dead
= where_dead
;
11715 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11716 before_dead
= PREV_INSN (before_dead
);
11718 after_dead
= where_dead
;
11719 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11720 after_dead
= NEXT_INSN (after_dead
);
11722 if (before_dead
&& after_dead
11723 && INSN_CUID (before_dead
) >= from_cuid
11724 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11725 || (where_dead
!= after_dead
11726 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11728 rtx note
= remove_death (regno
, where_dead
);
11730 /* It is possible for the call above to return 0. This can occur
11731 when reg_last_death points to I2 or I1 that we combined with.
11732 In that case make a new note.
11734 We must also check for the case where X is a hard register
11735 and NOTE is a death note for a range of hard registers
11736 including X. In that case, we must put REG_DEAD notes for
11737 the remaining registers in place of NOTE. */
11739 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11740 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11741 > GET_MODE_SIZE (GET_MODE (x
))))
11743 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11744 unsigned int deadend
11745 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11746 GET_MODE (XEXP (note
, 0))));
11747 unsigned int ourend
11748 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11751 for (i
= deadregno
; i
< deadend
; i
++)
11752 if (i
< regno
|| i
>= ourend
)
11753 REG_NOTES (where_dead
)
11754 = gen_rtx_EXPR_LIST (REG_DEAD
,
11755 gen_rtx_REG (reg_raw_mode
[i
], i
),
11756 REG_NOTES (where_dead
));
11759 /* If we didn't find any note, or if we found a REG_DEAD note that
11760 covers only part of the given reg, and we have a multi-reg hard
11761 register, then to be safe we must check for REG_DEAD notes
11762 for each register other than the first. They could have
11763 their own REG_DEAD notes lying around. */
11764 else if ((note
== 0
11766 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11767 < GET_MODE_SIZE (GET_MODE (x
)))))
11768 && regno
< FIRST_PSEUDO_REGISTER
11769 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11771 unsigned int ourend
11772 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11773 unsigned int i
, offset
;
11777 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11781 for (i
= regno
+ offset
; i
< ourend
; i
++)
11782 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11783 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11786 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11788 XEXP (note
, 1) = *pnotes
;
11792 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11794 REG_N_DEATHS (regno
)++;
11800 else if (GET_CODE (x
) == SET
)
11802 rtx dest
= SET_DEST (x
);
11804 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11806 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11807 that accesses one word of a multi-word item, some
11808 piece of everything register in the expression is used by
11809 this insn, so remove any old death. */
11810 /* ??? So why do we test for equality of the sizes? */
11812 if (GET_CODE (dest
) == ZERO_EXTRACT
11813 || GET_CODE (dest
) == STRICT_LOW_PART
11814 || (GET_CODE (dest
) == SUBREG
11815 && (((GET_MODE_SIZE (GET_MODE (dest
))
11816 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11817 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11818 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11820 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11824 /* If this is some other SUBREG, we know it replaces the entire
11825 value, so use that as the destination. */
11826 if (GET_CODE (dest
) == SUBREG
)
11827 dest
= SUBREG_REG (dest
);
11829 /* If this is a MEM, adjust deaths of anything used in the address.
11830 For a REG (the only other possibility), the entire value is
11831 being replaced so the old value is not used in this insn. */
11833 if (GET_CODE (dest
) == MEM
)
11834 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11839 else if (GET_CODE (x
) == CLOBBER
)
11842 len
= GET_RTX_LENGTH (code
);
11843 fmt
= GET_RTX_FORMAT (code
);
11845 for (i
= 0; i
< len
; i
++)
11850 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11851 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11854 else if (fmt
[i
] == 'e')
11855 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11859 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11860 pattern of an insn. X must be a REG. */
11863 reg_bitfield_target_p (x
, body
)
11869 if (GET_CODE (body
) == SET
)
11871 rtx dest
= SET_DEST (body
);
11873 unsigned int regno
, tregno
, endregno
, endtregno
;
11875 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11876 target
= XEXP (dest
, 0);
11877 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11878 target
= SUBREG_REG (XEXP (dest
, 0));
11882 if (GET_CODE (target
) == SUBREG
)
11883 target
= SUBREG_REG (target
);
11885 if (GET_CODE (target
) != REG
)
11888 tregno
= REGNO (target
), regno
= REGNO (x
);
11889 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11890 return target
== x
;
11892 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11893 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11895 return endregno
> tregno
&& regno
< endtregno
;
11898 else if (GET_CODE (body
) == PARALLEL
)
11899 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11900 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11906 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11907 as appropriate. I3 and I2 are the insns resulting from the combination
11908 insns including FROM (I2 may be zero).
11910 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11911 not need REG_DEAD notes because they are being substituted for. This
11912 saves searching in the most common cases.
11914 Each note in the list is either ignored or placed on some insns, depending
11915 on the type of note. */
11918 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11922 rtx elim_i2
, elim_i1
;
11924 rtx note
, next_note
;
11927 for (note
= notes
; note
; note
= next_note
)
11929 rtx place
= 0, place2
= 0;
11931 /* If this NOTE references a pseudo register, ensure it references
11932 the latest copy of that register. */
11933 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11934 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11935 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11937 next_note
= XEXP (note
, 1);
11938 switch (REG_NOTE_KIND (note
))
11942 case REG_EXEC_COUNT
:
11943 /* Doesn't matter much where we put this, as long as it's somewhere.
11944 It is preferable to keep these notes on branches, which is most
11945 likely to be i3. */
11949 case REG_NON_LOCAL_GOTO
:
11950 if (GET_CODE (i3
) == JUMP_INSN
)
11952 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11958 case REG_EH_REGION
:
11959 /* These notes must remain with the call or trapping instruction. */
11960 if (GET_CODE (i3
) == CALL_INSN
)
11962 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11964 else if (flag_non_call_exceptions
)
11966 if (may_trap_p (i3
))
11968 else if (i2
&& may_trap_p (i2
))
11970 /* ??? Otherwise assume we've combined things such that we
11971 can now prove that the instructions can't trap. Drop the
11972 note in this case. */
11980 /* These notes must remain with the call. It should not be
11981 possible for both I2 and I3 to be a call. */
11982 if (GET_CODE (i3
) == CALL_INSN
)
11984 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11991 /* Any clobbers for i3 may still exist, and so we must process
11992 REG_UNUSED notes from that insn.
11994 Any clobbers from i2 or i1 can only exist if they were added by
11995 recog_for_combine. In that case, recog_for_combine created the
11996 necessary REG_UNUSED notes. Trying to keep any original
11997 REG_UNUSED notes from these insns can cause incorrect output
11998 if it is for the same register as the original i3 dest.
11999 In that case, we will notice that the register is set in i3,
12000 and then add a REG_UNUSED note for the destination of i3, which
12001 is wrong. However, it is possible to have REG_UNUSED notes from
12002 i2 or i1 for register which were both used and clobbered, so
12003 we keep notes from i2 or i1 if they will turn into REG_DEAD
12006 /* If this register is set or clobbered in I3, put the note there
12007 unless there is one already. */
12008 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12010 if (from_insn
!= i3
)
12013 if (! (GET_CODE (XEXP (note
, 0)) == REG
12014 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12015 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12018 /* Otherwise, if this register is used by I3, then this register
12019 now dies here, so we must put a REG_DEAD note here unless there
12021 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12022 && ! (GET_CODE (XEXP (note
, 0)) == REG
12023 ? find_regno_note (i3
, REG_DEAD
,
12024 REGNO (XEXP (note
, 0)))
12025 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12027 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12035 /* These notes say something about results of an insn. We can
12036 only support them if they used to be on I3 in which case they
12037 remain on I3. Otherwise they are ignored.
12039 If the note refers to an expression that is not a constant, we
12040 must also ignore the note since we cannot tell whether the
12041 equivalence is still true. It might be possible to do
12042 slightly better than this (we only have a problem if I2DEST
12043 or I1DEST is present in the expression), but it doesn't
12044 seem worth the trouble. */
12046 if (from_insn
== i3
12047 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12052 case REG_NO_CONFLICT
:
12053 /* These notes say something about how a register is used. They must
12054 be present on any use of the register in I2 or I3. */
12055 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12058 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12068 /* This can show up in several ways -- either directly in the
12069 pattern, or hidden off in the constant pool with (or without?)
12070 a REG_EQUAL note. */
12071 /* ??? Ignore the without-reg_equal-note problem for now. */
12072 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12073 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12074 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12075 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12079 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12080 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12081 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12082 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12093 /* These notes say something about the value of a register prior
12094 to the execution of an insn. It is too much trouble to see
12095 if the note is still correct in all situations. It is better
12096 to simply delete it. */
12100 /* If the insn previously containing this note still exists,
12101 put it back where it was. Otherwise move it to the previous
12102 insn. Adjust the corresponding REG_LIBCALL note. */
12103 if (GET_CODE (from_insn
) != NOTE
)
12107 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12108 place
= prev_real_insn (from_insn
);
12110 XEXP (tem
, 0) = place
;
12111 /* If we're deleting the last remaining instruction of a
12112 libcall sequence, don't add the notes. */
12113 else if (XEXP (note
, 0) == from_insn
)
12119 /* This is handled similarly to REG_RETVAL. */
12120 if (GET_CODE (from_insn
) != NOTE
)
12124 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12125 place
= next_real_insn (from_insn
);
12127 XEXP (tem
, 0) = place
;
12128 /* If we're deleting the last remaining instruction of a
12129 libcall sequence, don't add the notes. */
12130 else if (XEXP (note
, 0) == from_insn
)
12136 /* If the register is used as an input in I3, it dies there.
12137 Similarly for I2, if it is non-zero and adjacent to I3.
12139 If the register is not used as an input in either I3 or I2
12140 and it is not one of the registers we were supposed to eliminate,
12141 there are two possibilities. We might have a non-adjacent I2
12142 or we might have somehow eliminated an additional register
12143 from a computation. For example, we might have had A & B where
12144 we discover that B will always be zero. In this case we will
12145 eliminate the reference to A.
12147 In both cases, we must search to see if we can find a previous
12148 use of A and put the death note there. */
12151 && GET_CODE (from_insn
) == CALL_INSN
12152 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12154 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12156 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12157 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12160 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12161 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12166 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12168 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12170 if (! INSN_P (tem
))
12172 if (tem
== bb
->head
)
12177 /* If the register is being set at TEM, see if that is all
12178 TEM is doing. If so, delete TEM. Otherwise, make this
12179 into a REG_UNUSED note instead. */
12180 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12182 rtx set
= single_set (tem
);
12183 rtx inner_dest
= 0;
12185 rtx cc0_setter
= NULL_RTX
;
12189 for (inner_dest
= SET_DEST (set
);
12190 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12191 || GET_CODE (inner_dest
) == SUBREG
12192 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12193 inner_dest
= XEXP (inner_dest
, 0))
12196 /* Verify that it was the set, and not a clobber that
12197 modified the register.
12199 CC0 targets must be careful to maintain setter/user
12200 pairs. If we cannot delete the setter due to side
12201 effects, mark the user with an UNUSED note instead
12204 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12205 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12207 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12208 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12209 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12213 /* Move the notes and links of TEM elsewhere.
12214 This might delete other dead insns recursively.
12215 First set the pattern to something that won't use
12218 PATTERN (tem
) = pc_rtx
;
12220 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12221 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12222 distribute_links (LOG_LINKS (tem
));
12224 PUT_CODE (tem
, NOTE
);
12225 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12226 NOTE_SOURCE_FILE (tem
) = 0;
12229 /* Delete the setter too. */
12232 PATTERN (cc0_setter
) = pc_rtx
;
12234 distribute_notes (REG_NOTES (cc0_setter
),
12235 cc0_setter
, cc0_setter
,
12236 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12237 distribute_links (LOG_LINKS (cc0_setter
));
12239 PUT_CODE (cc0_setter
, NOTE
);
12240 NOTE_LINE_NUMBER (cc0_setter
)
12241 = NOTE_INSN_DELETED
;
12242 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12246 /* If the register is both set and used here, put the
12247 REG_DEAD note here, but place a REG_UNUSED note
12248 here too unless there already is one. */
12249 else if (reg_referenced_p (XEXP (note
, 0),
12254 if (! find_regno_note (tem
, REG_UNUSED
,
12255 REGNO (XEXP (note
, 0))))
12257 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12262 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12264 /* If there isn't already a REG_UNUSED note, put one
12266 if (! find_regno_note (tem
, REG_UNUSED
,
12267 REGNO (XEXP (note
, 0))))
12272 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12273 || (GET_CODE (tem
) == CALL_INSN
12274 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12278 /* If we are doing a 3->2 combination, and we have a
12279 register which formerly died in i3 and was not used
12280 by i2, which now no longer dies in i3 and is used in
12281 i2 but does not die in i2, and place is between i2
12282 and i3, then we may need to move a link from place to
12284 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12285 && INSN_CUID (place
) > INSN_CUID (i2
)
12287 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12288 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12290 rtx links
= LOG_LINKS (place
);
12291 LOG_LINKS (place
) = 0;
12292 distribute_links (links
);
12297 if (tem
== bb
->head
)
12301 /* We haven't found an insn for the death note and it
12302 is still a REG_DEAD note, but we have hit the beginning
12303 of the block. If the existing life info says the reg
12304 was dead, there's nothing left to do. Otherwise, we'll
12305 need to do a global life update after combine. */
12306 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12307 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12308 REGNO (XEXP (note
, 0))))
12310 SET_BIT (refresh_blocks
, this_basic_block
);
12315 /* If the register is set or already dead at PLACE, we needn't do
12316 anything with this note if it is still a REG_DEAD note.
12317 We can here if it is set at all, not if is it totally replace,
12318 which is what `dead_or_set_p' checks, so also check for it being
12321 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12323 unsigned int regno
= REGNO (XEXP (note
, 0));
12325 /* Similarly, if the instruction on which we want to place
12326 the note is a noop, we'll need do a global live update
12327 after we remove them in delete_noop_moves. */
12328 if (noop_move_p (place
))
12330 SET_BIT (refresh_blocks
, this_basic_block
);
12334 if (dead_or_set_p (place
, XEXP (note
, 0))
12335 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12337 /* Unless the register previously died in PLACE, clear
12338 reg_last_death. [I no longer understand why this is
12340 if (reg_last_death
[regno
] != place
)
12341 reg_last_death
[regno
] = 0;
12345 reg_last_death
[regno
] = place
;
12347 /* If this is a death note for a hard reg that is occupying
12348 multiple registers, ensure that we are still using all
12349 parts of the object. If we find a piece of the object
12350 that is unused, we must arrange for an appropriate REG_DEAD
12351 note to be added for it. However, we can't just emit a USE
12352 and tag the note to it, since the register might actually
12353 be dead; so we recourse, and the recursive call then finds
12354 the previous insn that used this register. */
12356 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12357 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12359 unsigned int endregno
12360 = regno
+ HARD_REGNO_NREGS (regno
,
12361 GET_MODE (XEXP (note
, 0)));
12365 for (i
= regno
; i
< endregno
; i
++)
12366 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12367 && ! find_regno_fusage (place
, USE
, i
))
12368 || dead_or_set_regno_p (place
, i
))
12373 /* Put only REG_DEAD notes for pieces that are
12374 not already dead or set. */
12376 for (i
= regno
; i
< endregno
;
12377 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12379 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12380 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12382 if (! dead_or_set_p (place
, piece
)
12383 && ! reg_bitfield_target_p (piece
,
12387 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12389 distribute_notes (new_note
, place
, place
,
12390 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12392 else if (! refers_to_regno_p (i
, i
+ 1,
12393 PATTERN (place
), 0)
12394 && ! find_regno_fusage (place
, USE
, i
))
12395 for (tem
= PREV_INSN (place
); ;
12396 tem
= PREV_INSN (tem
))
12398 if (! INSN_P (tem
))
12400 if (tem
== bb
->head
)
12402 SET_BIT (refresh_blocks
,
12409 if (dead_or_set_p (tem
, piece
)
12410 || reg_bitfield_target_p (piece
,
12414 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12429 /* Any other notes should not be present at this point in the
12436 XEXP (note
, 1) = REG_NOTES (place
);
12437 REG_NOTES (place
) = note
;
12439 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12440 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12441 && GET_CODE (XEXP (note
, 0)) == REG
)
12442 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12446 if ((REG_NOTE_KIND (note
) == REG_DEAD
12447 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12448 && GET_CODE (XEXP (note
, 0)) == REG
)
12449 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12451 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12452 REG_NOTE_KIND (note
),
12454 REG_NOTES (place2
));
12459 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12460 I3, I2, and I1 to new locations. This is also called in one case to
12461 add a link pointing at I3 when I3's destination is changed. */
12464 distribute_links (links
)
12467 rtx link
, next_link
;
12469 for (link
= links
; link
; link
= next_link
)
12475 next_link
= XEXP (link
, 1);
12477 /* If the insn that this link points to is a NOTE or isn't a single
12478 set, ignore it. In the latter case, it isn't clear what we
12479 can do other than ignore the link, since we can't tell which
12480 register it was for. Such links wouldn't be used by combine
12483 It is not possible for the destination of the target of the link to
12484 have been changed by combine. The only potential of this is if we
12485 replace I3, I2, and I1 by I3 and I2. But in that case the
12486 destination of I2 also remains unchanged. */
12488 if (GET_CODE (XEXP (link
, 0)) == NOTE
12489 || (set
= single_set (XEXP (link
, 0))) == 0)
12492 reg
= SET_DEST (set
);
12493 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12494 || GET_CODE (reg
) == SIGN_EXTRACT
12495 || GET_CODE (reg
) == STRICT_LOW_PART
)
12496 reg
= XEXP (reg
, 0);
12498 /* A LOG_LINK is defined as being placed on the first insn that uses
12499 a register and points to the insn that sets the register. Start
12500 searching at the next insn after the target of the link and stop
12501 when we reach a set of the register or the end of the basic block.
12503 Note that this correctly handles the link that used to point from
12504 I3 to I2. Also note that not much searching is typically done here
12505 since most links don't point very far away. */
12507 for (insn
= NEXT_INSN (XEXP (link
, 0));
12508 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12509 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12510 insn
= NEXT_INSN (insn
))
12511 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12513 if (reg_referenced_p (reg
, PATTERN (insn
)))
12517 else if (GET_CODE (insn
) == CALL_INSN
12518 && find_reg_fusage (insn
, USE
, reg
))
12524 /* If we found a place to put the link, place it there unless there
12525 is already a link to the same insn as LINK at that point. */
12531 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12532 if (XEXP (link2
, 0) == XEXP (link
, 0))
12537 XEXP (link
, 1) = LOG_LINKS (place
);
12538 LOG_LINKS (place
) = link
;
12540 /* Set added_links_insn to the earliest insn we added a
12542 if (added_links_insn
== 0
12543 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12544 added_links_insn
= place
;
12550 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12556 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12557 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12558 insn
= NEXT_INSN (insn
);
12560 if (INSN_UID (insn
) > max_uid_cuid
)
12563 return INSN_CUID (insn
);
12567 dump_combine_stats (file
)
12572 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12573 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12577 dump_combine_total_stats (file
)
12582 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12583 total_attempts
, total_merges
, total_extras
, total_successes
);