| blob | 7ba634af532a6f5ec210b71a0bd4adc890bf044e |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
330 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
331 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
333 #define FOR_EACH_LOG_LINK(L, INSN) \
334 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
336 /* Links for LOG_LINKS are allocated from this obstack. */
340 /* Allocate a link. */
344 {
352 }
354 /* Incremented for each basic block. */
358 /* Reset to label_tick for each extended basic block in scanning order. */
362 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
363 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
367 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
368 be safely used. It is zero while computing them and after combine has
369 completed. This former test prevents propagating values based on
370 previously set values, which can be incorrect if a variable is modified
371 in a loop. */
375 \f
376 /* Record one modification to rtl structure
377 to be undone by storing old_contents into *where. */
381 struct undo
382 {
387 };
389 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
390 num_undo says how many are currently recorded.
392 other_insn is nonzero if we have modified some other insn in the process
393 of working on subst_insn. It must be verified too. */
395 struct undobuf
396 {
400 };
404 /* Number of times the pseudo being substituted for
405 was found and replaced. */
410 machine_mode,
414 machine_mode,
486 \f
488 /* It is not safe to use ordinary gen_lowpart in combine.
489 See comments in gen_lowpart_for_combine. */
490 #undef RTL_HOOKS_GEN_LOWPART
491 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
493 /* Our implementation of gen_lowpart never emits a new pseudo. */
494 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
497 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
500 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
503 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
508 \f
509 /* Convenience wrapper for the canonicalize_comparison target hook.
510 Target hooks cannot use enum rtx_code. */
514 {
518 }
520 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 PATTERN can not be split. Otherwise, it returns an insn sequence.
522 This is a wrapper around split_insns which ensures that the
523 reg_stat vector is made larger if the splitter creates a new
524 register. */
528 {
537 }
539 /* This is used by find_single_use to locate an rtx in LOC that
540 contains exactly one use of DEST, which is typically either a REG
541 or CC0. It returns a pointer to the innermost rtx expression
542 containing DEST. Appearances of DEST that are being used to
543 totally replace it are not counted. */
547 {
556 {
560 CASE_CONST_ANY:
565 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
566 of a REG that occupies all of the REG, the insn uses DEST if
567 it is mentioned in the destination or the source. Otherwise, we
568 need just check the source. */
588 }
590 /* If it wasn't one of the common cases above, check each expression and
591 vector of this code. Look for a unique usage of DEST. */
595 {
597 {
602 else
608 /* Duplicate usage. */
610 }
612 {
616 {
622 else
629 }
630 }
631 }
634 }
637 /* See if DEST, produced in INSN, is used only a single time in the
638 sequel. If so, return a pointer to the innermost rtx expression in which
639 it is used.
641 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
643 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
644 care about REG_DEAD notes or LOG_LINKS.
646 Otherwise, we find the single use by finding an insn that has a
647 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
648 only referenced once in that insn, we know that it must be the first
649 and last insn referencing DEST. */
653 {
654 basic_block bb;
660 {
670 }
680 {
686 {
691 }
692 }
695 }
696 \f
697 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
698 insn. The substitution can be undone by undo_all. If INTO is already
699 set to NEWVAL, do not record this change. Because computing NEWVAL might
700 also call SUBST, we have to compute it before we put anything into
701 the undo table. */
703 static void
705 {
712 /* We'd like to catch as many invalid transformations here as
713 possible. Unfortunately, there are way too many mode changes
714 that are perfectly valid, so we'd waste too much effort for
715 little gain doing the checks here. Focus on catching invalid
716 transformations involving integer constants. */
719 {
720 /* Sanity check that we're replacing oldval with a CONST_INT
721 that is a valid sign-extension for the original mode. */
725 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
726 CONST_INT is not valid, because after the replacement, the
727 original mode would be gone. Unfortunately, we can't tell
728 when do_SUBST is called to replace the operand thereof, so we
729 perform this test on oldval instead, checking whether an
730 invalid replacement took place before we got here. */
735 }
739 else
748 }
750 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
752 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
753 for the value of a HOST_WIDE_INT value (including CONST_INT) is
754 not safe. */
756 static void
758 {
767 else
776 }
778 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
780 /* Similar to SUBST, but just substitute the mode. This is used when
781 changing the mode of a pseudo-register, so that any other
782 references to the entry in the regno_reg_rtx array will change as
783 well. */
785 static void
787 {
796 else
805 }
807 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
809 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
811 static void
813 {
822 else
831 }
833 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
834 \f
835 /* Subroutine of try_combine. Determine whether the replacement patterns
836 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
837 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
838 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
839 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
840 of all the instructions can be estimated and the replacements are more
841 expensive than the original sequence. */
843 static bool
846 {
851 /* Lookup the original insn_rtx_costs. */
856 {
859 {
863 }
864 else
865 {
869 }
870 }
871 else
872 {
875 }
877 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
878 correct that. */
883 /* Calculate the replacement insn_rtx_costs. */
886 {
890 }
891 else
892 {
895 }
898 {
904 {
907 }
908 else
910 }
912 /* Disallow this combination if both new_cost and old_cost are greater than
913 zero, and new_cost is greater than old cost. */
917 {
936 else
938 }
943 /* Update the uid_insn_cost array with the replacement costs. */
947 {
951 }
954 }
957 /* Delete any insns that copy a register to itself. */
959 static void
961 {
963 basic_block bb;
966 {
968 {
971 {
976 }
977 }
978 }
979 }
981 \f
982 /* Return false if we do not want to (or cannot) combine DEF. */
983 static bool
985 {
986 /* Do not consider if it is pre/post modification in MEM. */
992 /* Do not combine frame pointer adjustments. */
995 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1003 }
1005 /* Return false if we do not want to (or cannot) combine USE. */
1006 static bool
1008 {
1009 /* Do not consider the usage of the stack pointer by function call. */
1014 }
1016 /* Fill in log links field for all insns. */
1018 static void
1020 {
1021 basic_block bb;
1028 /* Pass through each block from the end, recording the uses of each
1029 register and establishing log links when def is encountered.
1030 Note that we do not clear next_use array in order to save time,
1031 so we have to test whether the use is in the same basic block as def.
1033 There are a few cases below when we do not consider the definition or
1034 usage -- these are taken from original flow.c did. Don't ask me why it is
1035 done this way; I don't know and if it works, I don't want to know. */
1038 {
1040 {
1044 /* Log links are created only once. */
1048 {
1064 /* flow.c claimed:
1066 We don't build a LOG_LINK for hard registers contained
1067 in ASM_OPERANDs. If these registers get replaced,
1068 we might wind up changing the semantics of the insn,
1069 even if reload can make what appear to be valid
1070 assignments later. */
1075 /* Don't add duplicate links between instructions. */
1084 }
1089 }
1090 }
1093 }
1095 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1096 true if we found a LOG_LINK that proves that A feeds B. This only works
1097 if there are no instructions between A and B which could have a link
1098 depending on A, since in that case we would not record a link for B.
1099 We also check the implicit dependency created by a cc0 setter/user
1100 pair. */
1102 static bool
1104 {
1112 }
1113 \f
1114 /* Main entry point for combiner. F is the first insn of the function.
1115 NREGS is the first unused pseudo-reg number.
1117 Return nonzero if the combiner has turned an indirect jump
1118 instruction into a direct jump. */
1119 static int
1121 {
1126 basic_block last_bb;
1146 /* Allocate array for insn info. */
1154 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1155 problems when, for example, we have j <<= 1 in a loop. */
1160 /* Scan all SETs and see if we can deduce anything about what
1161 bits are known to be zero for some registers and how many copies
1162 of the sign bit are known to exist for those registers.
1164 Also set any known values so that we can use it while searching
1165 for what bits are known to be set. */
1168 /* Allow the entry block and the first block to fall into the same EBB.
1169 Conceptually the incoming promotions are assigned to the entry block. */
1174 {
1179 label_tick++;
1187 {
1188 rtx links;
1194 insn);
1201 insn);
1203 /* Record the current insn_rtx_cost of this instruction. */
1206 optimize_this_for_speed_p);
1210 }
1211 }
1215 /* Now scan all the insns in forward order. */
1223 {
1229 label_tick++;
1239 {
1253 /* See if we know about function return values before this
1254 insn based upon SUBREG flags. */
1257 /* See if we can find hardregs and subreg of pseudos in
1258 narrower modes. This could help turning TRUNCATEs
1259 into SUBREGs. */
1262 /* Try this insn with each insn it links back to. */
1268 {
1271 }
1273 /* Try each sequence of three linked insns ending with this one. */
1277 {
1280 /* If the linked insn has been replaced by a note, then there
1281 is no point in pursuing this chain any further. */
1289 {
1292 }
1293 }
1295 /* Try to combine a jump insn that uses CC0
1296 with a preceding insn that sets CC0, and maybe with its
1297 logical predecessor as well.
1298 This is how we make decrement-and-branch insns.
1299 We need this special code because data flow connections
1300 via CC0 do not get entered in LOG_LINKS. */
1307 {
1318 }
1320 /* Do the same for an insn that explicitly references CC0. */
1327 {
1338 }
1340 /* Finally, see if any of the insns that this insn links to
1341 explicitly references CC0. If so, try this insn, that insn,
1342 and its predecessor if it sets CC0. */
1344 {
1356 }
1358 /* Try combining an insn with two different insns whose results it
1359 uses. */
1369 {
1372 }
1374 /* Try four-instruction combinations. */
1377 {
1381 /* If the linked insn has been replaced by a note, then there
1382 is no point in pursuing this chain any further. */
1387 {
1391 /* I0 -> I1 -> I2 -> I3. */
1397 {
1400 }
1401 /* I0, I1 -> I2, I2 -> I3. */
1408 {
1411 }
1412 }
1415 {
1419 /* I0 -> I2; I1, I2 -> I3. */
1425 {
1428 }
1429 /* I0 -> I1; I1, I2 -> I3. */
1435 {
1438 }
1439 }
1440 }
1442 /* Try this insn with each REG_EQUAL note it links back to. */
1444 {
1450 /* Avoid using a register that may already been marked
1451 dead by an earlier instruction. */
1459 {
1460 /* Temporarily replace the set's source with the
1461 contents of the REG_EQUAL note. The insn will
1462 be deleted or recognized by try_combine. */
1473 last_combined_insn);
1476 {
1479 }
1482 }
1483 }
1488 retry:
1489 ;
1490 }
1491 }
1498 /* Clean up. */
1504 {
1507 {
1510 }
1512 }
1522 /* Make recognizer allow volatile MEMs again. */
1526 }
1528 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1530 static void
1532 {
1538 }
1539 \f
1540 /* Set up any promoted values for incoming argument registers. */
1542 static void
1544 {
1545 tree arg;
1550 {
1555 /* Only continue if the incoming argument is in a register. */
1559 /* Determine, if possible, whether all call sites of the current
1560 function lie within the current compilation unit. (This does
1561 take into account the exporting of a function via taking its
1562 address, and so forth.) */
1565 /* The mode and signedness of the argument before any promotions happen
1566 (equal to the mode of the pseudo holding it at that stage). */
1570 /* The mode and signedness of the argument after any source language and
1571 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1575 /* The mode and signedness of the argument as it is actually passed,
1576 see assign_parm_setup_reg in function.c. */
1580 /* The mode of the register in which the argument is being passed. */
1583 /* Eliminate sign extensions in the callee when:
1584 (a) A mode promotion has occurred; */
1587 /* (b) The mode of the register is the same as the mode of
1588 the argument as it is passed; */
1591 /* (c) There's no language level extension; */
1593 ;
1594 /* (c.1) All callers are from the current compilation unit. If that's
1595 the case we don't have to rely on an ABI, we only have to know
1596 what we're generating right now, and we know that we will do the
1597 mode1 to mode2 promotion with the given sign. */
1600 /* (c.2) The combination of the two promotions is useful. This is
1601 true when the signs match, or if the first promotion is unsigned.
1602 In the later case, (sign_extend (zero_extend x)) is the same as
1603 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1609 /* Record that the value was promoted from mode1 to mode3,
1610 so that any sign extension at the head of the current
1611 function may be eliminated. */
1615 }
1616 }
1618 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1619 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1620 because some machines (maybe most) will actually do the sign-extension and
1621 this is the conservative approach.
1623 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1624 kludge. */
1626 static rtx
1628 {
1636 }
1638 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1639 and SET. */
1641 static void
1643 rtx x)
1644 {
1654 {
1658 }
1660 /* Don't call nonzero_bits if it cannot change anything. */
1662 {
1667 }
1669 /* Don't call num_sign_bit_copies if it cannot change anything. */
1671 {
1674 {
1678 }
1681 }
1682 }
1684 /* Called via note_stores. If X is a pseudo that is narrower than
1685 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1687 If we are setting only a portion of X and we can't figure out what
1688 portion, assume all bits will be used since we don't know what will
1689 be happening.
1691 Similarly, set how many bits of X are known to be copies of the sign bit
1692 at all locations in the function. This is the smallest number implied
1693 by any set of X. */
1695 static void
1697 {
1702 /* If this register is undefined at the start of the file, we can't
1703 say what its contents were. */
1704 && ! REGNO_REG_SET_P
1707 {
1711 {
1715 }
1717 /* If this register is being initialized using itself, and the
1718 register is uninitialized in this basic block, and there are
1719 no LOG_LINKS which set the register, then part of the
1720 register is uninitialized. In that case we can't assume
1721 anything about the number of nonzero bits.
1723 ??? We could do better if we checked this in
1724 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1725 could avoid making assumptions about the insn which initially
1726 sets the register, while still using the information in other
1727 insns. We would have to be careful to check every insn
1728 involved in the combination. */
1734 {
1741 {
1745 }
1746 }
1748 /* If this is a complex assignment, see if we can convert it into a
1749 simple assignment. */
1752 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1753 set what we know about X. */
1759 else
1760 {
1763 }
1764 }
1765 }
1766 \f
1767 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1768 optionally insns that were previously combined into I3 or that will be
1769 combined into the merger of INSN and I3. The order is PRED, PRED2,
1770 INSN, SUCC, SUCC2, I3.
1772 Return 0 if the combination is not allowed for any reason.
1774 If the combination is allowed, *PDEST will be set to the single
1775 destination of INSN and *PSRC to the single source, and this function
1776 will return 1. */
1778 static int
1782 {
1787 rtx link;
1792 {
1794 {
1799 }
1804 }
1808 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1809 or a PARALLEL consisting of such a SET and CLOBBERs.
1811 If INSN has CLOBBER parallel parts, ignore them for our processing.
1812 By definition, these happen during the execution of the insn. When it
1813 is merged with another insn, all bets are off. If they are, in fact,
1814 needed and aren't also supplied in I3, they may be added by
1815 recog_for_combine. Otherwise, it won't match.
1817 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1818 note.
1820 Get the source and destination of INSN. If more than one, can't
1821 combine. */
1827 {
1829 {
1833 {
1834 /* This is important to combine floating point insns
1835 for the SH4 port. */
1837 /* Combining an isolated USE doesn't make sense.
1838 We depend here on combinable_i3pat to reject them. */
1839 /* The code below this loop only verifies that the inputs of
1840 the SET in INSN do not change. We call reg_set_between_p
1841 to verify that the REG in the USE does not change between
1842 I3 and INSN.
1843 If the USE in INSN was for a pseudo register, the matching
1844 insn pattern will likely match any register; combining this
1845 with any other USE would only be safe if we knew that the
1846 used registers have identical values, or if there was
1847 something to tell them apart, e.g. different modes. For
1848 now, we forgo such complicated tests and simply disallow
1849 combining of USES of pseudo registers with any other USE. */
1852 {
1857 do
1858 {
1868 }
1870 }
1873 /* We can ignore CLOBBERs. */
1878 /* Ignore SETs whose result isn't used but not those that
1879 have side-effects. */
1885 /* If we have already found a SET, this is a second one and
1886 so we cannot combine with this insn. */
1894 /* Anything else means we can't combine. */
1896 }
1897 }
1900 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1901 so don't do anything with it. */
1904 }
1905 else
1911 /* The simplification in expand_field_assignment may call back to
1912 get_last_value, so set safe guard here. */
1918 /* Do not eliminate user-specified register if it is in an
1919 asm input because we may break the register asm usage defined
1920 in GCC manual if allow to do so.
1921 Be aware that this may cover more cases than we expect but this
1922 should be harmless. */
1927 /* Don't eliminate a store in the stack pointer. */
1929 /* Don't combine with an insn that sets a register to itself if it has
1930 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1932 /* Can't merge an ASM_OPERANDS. */
1934 /* Can't merge a function call. */
1936 /* Don't eliminate a function call argument. */
1942 /* Don't substitute into an incremented register. */
1946 /* Don't substitute into a non-local goto, this confuses CFG. */
1948 /* Make sure that DEST is not used after SUCC but before I3. */
1949 || (!all_adjacent
1950 && ((succ2
1954 /* Make sure that the value that is to be substituted for the register
1955 does not use any registers whose values alter in between. However,
1956 If the insns are adjacent, a use can't cross a set even though we
1957 think it might (this can happen for a sequence of insns each setting
1958 the same destination; last_set of that register might point to
1959 a NOTE). If INSN has a REG_EQUIV note, the register is always
1960 equivalent to the memory so the substitution is valid even if there
1961 are intervening stores. Also, don't move a volatile asm or
1962 UNSPEC_VOLATILE across any other insns. */
1963 || (! all_adjacent
1969 /* Don't combine across a CALL_INSN, because that would possibly
1970 change whether the life span of some REGs crosses calls or not,
1971 and it is a pain to update that information.
1972 Exception: if source is a constant, moving it later can't hurt.
1973 Accept that as a special case. */
1977 /* DEST must either be a REG or CC0. */
1979 {
1980 /* If register alignment is being enforced for multi-word items in all
1981 cases except for parameters, it is possible to have a register copy
1982 insn referencing a hard register that is not allowed to contain the
1983 mode being copied and which would not be valid as an operand of most
1984 insns. Eliminate this problem by not combining with such an insn.
1986 Also, on some machines we don't want to extend the life of a hard
1987 register. */
1992 /* Don't extend the life of a hard register unless it is
1993 user variable (if we have few registers) or it can't
1994 fit into the desired register (meaning something special
1995 is going on).
1996 Also avoid substituting a return register into I3, because
1997 reload can't handle a conflict with constraints of other
1998 inputs. */
2002 }
2010 {
2013 /* If the clobber represents an earlyclobber operand, we must not
2014 substitute an expression containing the clobbered register.
2015 As we do not analyze the constraint strings here, we have to
2016 make the conservative assumption. However, if the register is
2017 a fixed hard reg, the clobber cannot represent any operand;
2018 we leave it up to the machine description to either accept or
2019 reject use-and-clobber patterns. */
2025 }
2027 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2028 or not), reject, unless nothing volatile comes between it and I3 */
2031 {
2032 /* Make sure neither succ nor succ2 contains a volatile reference. */
2037 /* We'll check insns between INSN and I3 below. */
2038 }
2040 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2041 to be an explicit register variable, and was chosen for a reason. */
2047 /* If INSN contains volatile references (specifically volatile MEMs),
2048 we cannot combine across any other volatile references.
2049 Even if INSN doesn't contain volatile references, any intervening
2050 volatile insn might affect machine state. */
2053 ? volatile_refs_p
2060 /* If INSN contains an autoincrement or autodecrement, make sure that
2061 register is not used between there and I3, and not already used in
2062 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2063 Also insist that I3 not be a jump; if it were one
2064 and the incremented register were spilled, we would lose. */
2082 /* Don't combine an insn that follows a CC0-setting insn.
2083 An insn that uses CC0 must not be separated from the one that sets it.
2084 We do, however, allow I2 to follow a CC0-setting insn if that insn
2085 is passed as I1; in that case it will be deleted also.
2086 We also allow combining in this case if all the insns are adjacent
2087 because that would leave the two CC0 insns adjacent as well.
2088 It would be more logical to test whether CC0 occurs inside I1 or I2,
2089 but that would be much slower, and this ought to be equivalent. */
2092 {
2097 }
2099 /* If we get here, we have passed all the tests and the combination is
2100 to be allowed. */
2106 }
2107 \f
2108 /* LOC is the location within I3 that contains its pattern or the component
2109 of a PARALLEL of the pattern. We validate that it is valid for combining.
2111 One problem is if I3 modifies its output, as opposed to replacing it
2112 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2113 doing so would produce an insn that is not equivalent to the original insns.
2115 Consider:
2117 (set (reg:DI 101) (reg:DI 100))
2118 (set (subreg:SI (reg:DI 101) 0) <foo>)
2120 This is NOT equivalent to:
2122 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2123 (set (reg:DI 101) (reg:DI 100))])
2125 Not only does this modify 100 (in which case it might still be valid
2126 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2128 We can also run into a problem if I2 sets a register that I1
2129 uses and I1 gets directly substituted into I3 (not via I2). In that
2130 case, we would be getting the wrong value of I2DEST into I3, so we
2131 must reject the combination. This case occurs when I2 and I1 both
2132 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2133 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2134 of a SET must prevent combination from occurring. The same situation
2135 can occur for I0, in which case I0_NOT_IN_SRC is set.
2137 Before doing the above check, we first try to expand a field assignment
2138 into a set of logical operations.
2140 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2141 we place a register that is both set and used within I3. If more than one
2142 such register is detected, we fail.
2144 Return 1 if the combination is valid, zero otherwise. */
2146 static int
2149 {
2153 {
2158 rtx subdest;
2165 /* Check for the case where I3 modifies its output, as discussed
2166 above. We don't want to prevent pseudos from being combined
2167 into the address of a MEM, so only prevent the combination if
2168 i1 or i2 set the same MEM. */
2178 /* This is the same test done in can_combine_p except we can't test
2179 all_adjacent; we don't have to, since this instruction will stay
2180 in place, thus we are not considering increasing the lifetime of
2181 INNER_DEST.
2183 Also, if this insn sets a function argument, combining it with
2184 something that might need a spill could clobber a previous
2185 function argument; the all_adjacent test in can_combine_p also
2186 checks this; here, we do a more specific test for this case. */
2196 /* If DEST is used in I3, it is being killed in this insn, so
2197 record that for later. We have to consider paradoxical
2198 subregs here, since they kill the whole register, but we
2199 ignore partial subregs, STRICT_LOW_PART, etc.
2200 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2201 STACK_POINTER_REGNUM, since these are always considered to be
2202 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2212 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2218 {
2223 }
2224 }
2227 {
2234 }
2237 }
2238 \f
2239 /* Return 1 if X is an arithmetic expression that contains a multiplication
2240 and division. We don't count multiplications by powers of two here. */
2242 static int
2244 {
2246 {
2262 }
2263 }
2264 \f
2265 /* Determine whether INSN can be used in a combination. Return nonzero if
2266 not. This is used in try_combine to detect early some cases where we
2267 can't perform combinations. */
2269 static int
2271 {
2272 rtx set;
2275 /* If this isn't really an insn, we can't do anything.
2276 This can occur when flow deletes an insn that it has merged into an
2277 auto-increment address. */
2281 /* Never combine loads and stores involving hard regs that are likely
2282 to be spilled. The register allocator can usually handle such
2283 reg-reg moves by tying. If we allow the combiner to make
2284 substitutions of likely-spilled regs, reload might die.
2285 As an exception, we allow combinations involving fixed regs; these are
2286 not available to the register allocator so there's no risk involved. */
2307 }
2309 struct likely_spilled_retval_info
2310 {
2313 };
2315 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2316 hard registers that are known to be written to / clobbered in full. */
2317 static void
2319 {
2336 else
2339 }
2341 /* Return nonzero iff part of the return value is live during INSN, and
2342 it is likely spilled. This can happen when more than one insn is needed
2343 to copy the return value, e.g. when we consider to combine into the
2344 second copy insn for a complex value. */
2346 static int
2348 {
2350 rtx reg;
2353 /* We assume here that no machine mode needs more than
2354 32 hard registers when the value overlaps with a register
2355 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2370 /* Disregard parts of the return value that are set later. */
2379 /* Check if any of the (probably) live return value registers is
2380 likely spilled. */
2381 nregs --;
2382 do
2383 {
2389 }
2391 /* Adjust INSN after we made a change to its destination.
2393 Changing the destination can invalidate notes that say something about
2394 the results of the insn and a LOG_LINK pointing to the insn. */
2396 static void
2398 {
2399 /* For notes, be conservative and simply remove them. */
2402 /* The new insn will have a destination that was previously the destination
2403 of an insn just above it. Call distribute_links to make a LOG_LINK from
2404 the next use of that destination. */
2420 }
2422 /* Return TRUE if combine can reuse reg X in mode MODE.
2423 ADDED_SETS is nonzero if the original set is still required. */
2424 static bool
2426 {
2433 /* Allow hard registers if the new mode is legal, and occupies no more
2434 registers than the old mode. */
2439 /* Or a pseudo that is only used once. */
2442 && !added_sets
2444 }
2447 /* Check whether X, the destination of a set, refers to part of
2448 the register specified by REG. */
2450 static bool
2452 {
2453 /* Check that reg is an integer mode register. */
2464 }
2466 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2467 Note that the INSN should be deleted *after* removing dead edges, so
2468 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2469 but not for a (set (pc) (label_ref FOO)). */
2471 static void
2473 {
2481 {
2486 /* Remove barriers from the footer if there are any. */
2489 {
2492 else
2496 }
2499 }
2500 }
2502 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2503 by an arbitrary number of CLOBBERs. */
2504 static bool
2506 {
2525 }
2527 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2528 CLOBBERs), can be split into individual SETs in that order, without
2529 changing semantics. */
2530 static bool
2532 {
2540 {
2549 }
2552 }
2554 /* Try to combine the insns I0, I1 and I2 into I3.
2555 Here I0, I1 and I2 appear earlier than I3.
2556 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2557 I3.
2559 If we are combining more than two insns and the resulting insn is not
2560 recognized, try splitting it into two insns. If that happens, I2 and I3
2561 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2562 Otherwise, I0, I1 and I2 are pseudo-deleted.
2564 Return 0 if the combination does not work. Then nothing is changed.
2565 If we did the combination, return the insn at which combine should
2566 resume scanning.
2568 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2569 new direct jump instruction.
2571 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2572 been I3 passed to an earlier try_combine within the same basic
2573 block. */
2578 {
2579 /* New patterns for I3 and I2, respectively. */
2583 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2584 dead. */
2586 /* Total number of SETs to put into I3. */
2588 /* Nonzero if I2's or I1's body now appears in I3. */
2590 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2592 /* Contains I3 if the destination of I3 is used in its source, which means
2593 that the old life of I3 is being killed. If that usage is placed into
2594 I2 and not in I3, a REG_DEAD note must be made. */
2596 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2598 /* Copy of SET_SRC of I1 and I0, if needed. */
2600 /* Set if I2DEST was reused as a scratch register. */
2602 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2604 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2609 /* Notes that must be added to REG_NOTES in I3 and I2. */
2611 /* Notes that we substituted I3 into I2 instead of the normal case. */
2613 /* Notes that I1, I2 or I3 is a MULT operation. */
2620 rtx temp_expr;
2623 rtx new_other_notes;
2626 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2627 never be). */
2631 /* Only try four-insn combinations when there's high likelihood of
2632 success. Look for simple insns, such as loads of constants or
2633 binary operations involving a constant. */
2635 {
2645 {
2648 rtx src;
2653 {
2656 }
2658 ngood++;
2661 nshift++;
2662 }
2664 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2665 are likely manipulating its value. Ideally we'll be able to combine
2666 all four insns into a bitfield insertion of some kind.
2668 Note the source in I0 might be inside a sign/zero extension and the
2669 memory modes in I0 and I3 might be different. So extract the address
2670 from the destination of I3 and search for it in the source of I0.
2672 In the event that there's a match but the source/dest do not actually
2673 refer to the same memory, the worst that happens is we try some
2674 combinations that we wouldn't have otherwise. */
2676 /* Ensure the source of SET0 is a MEM, possibly buried inside
2677 an extension. */
2683 /* Ensure the destination of SET3 is a MEM. */
2685 /* Would it be better to extract the base address for the MEM
2686 in SET3 and look for that? I don't have cases where it matters
2687 but I could envision such cases. */
2693 }
2695 /* Exit early if one of the insns involved can't be used for
2696 combinations. */
2707 combine_attempts++;
2710 /* Reset the hard register usage information. */
2714 {
2721 else
2724 }
2726 /* If multiple insns feed into one of I2 or I3, they can be in any
2727 order. To simplify the code below, reorder them in sequence. */
2737 /* First check for one important special case that the code below will
2738 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2739 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2740 we may be able to replace that destination with the destination of I3.
2741 This occurs in the common code where we compute both a quotient and
2742 remainder into a structure, in which case we want to do the computation
2743 directly into the structure to avoid register-register copies.
2745 Note that this case handles both multiple sets in I2 and also cases
2746 where I2 has a number of CLOBBERs inside the PARALLEL.
2748 We make very conservative checks below and only try to handle the
2749 most common cases of this. For example, we only handle the case
2750 where I2 and I3 are adjacent to avoid making difficult register
2751 usage tests. */
2759 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2760 below would need to check what is inside (and reg_overlap_mentioned_p
2761 doesn't support those codes anyway). Don't allow those destinations;
2762 the resulting insn isn't likely to be recognized anyway. */
2768 {
2771 /* Make sure that the destination of I3,
2772 which we are going to substitute into one output of I2,
2773 is not used within another output of I2. We must avoid making this:
2774 (parallel [(set (mem (reg 69)) ...)
2775 (set (reg 69) ...)])
2776 which is not well-defined as to order of actions.
2777 (Besides, reload can't handle output reloads for this.)
2779 The problem can also happen if the dest of I3 is a memory ref,
2780 if another dest in I2 is an indirect memory ref. */
2788 /* Make sure this PARALLEL is not an asm. We do not allow combining
2789 that usually (see can_combine_p), so do not here either. */
2799 {
2800 combine_merges++;
2810 /* Replace the dest in I2 with our dest and make the resulting
2811 insn the new pattern for I3. Then skip to where we validate
2812 the pattern. Everything was set up above. */
2817 }
2818 }
2820 /* If I2 is setting a pseudo to a constant and I3 is setting some
2821 sub-part of it to another constant, merge them by making a new
2822 constant. */
2829 {
2835 {
2838 {
2844 }
2845 }
2846 else
2847 {
2852 }
2855 {
2856 /* If this is the low part, we're done. */
2858 ;
2859 /* Handle the case where inner is twice the size of outer. */
2863 /* Otherwise give up for now. */
2864 else
2866 }
2869 {
2873 wide_int o
2878 combine_merges++;
2885 /* Replace the source in I2 with the new constant and make the
2886 resulting insn the new pattern for I3. Then skip to where we
2887 validate the pattern. Everything was set up above. */
2893 /* The dest of I3 has been replaced with the dest of I2. */
2896 }
2897 }
2899 /* If we have no I1 and I2 looks like:
2900 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2901 (set Y OP)])
2902 make up a dummy I1 that is
2903 (set Y OP)
2904 and change I2 to be
2905 (set (reg:CC X) (compare:CC Y (const_int 0)))
2907 (We can ignore any trailing CLOBBERs.)
2909 This undoes a previous combination and allows us to match a branch-and-
2910 decrement insn. */
2922 {
2923 /* We make I1 with the same INSN_UID as I2. This gives it
2924 the same DF_INSN_LUID for value tracking. Our fake I1 will
2925 never appear in the insn stream so giving it the same INSN_UID
2926 as I2 will not cause a problem. */
2939 }
2941 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2942 make those two SETs separate I1 and I2 insns, and make an I0 that is
2943 the original I1. */
2949 {
2950 /* If there is no I1, there is no I0 either. */
2953 /* We make I1 with the same INSN_UID as I2. This gives it
2954 the same DF_INSN_LUID for value tracking. Our fake I1 will
2955 never appear in the insn stream so giving it the same INSN_UID
2956 as I2 will not cause a problem. */
2964 }
2966 /* Verify that I2 and I1 are valid for combining. */
2972 {
2975 }
2977 /* Record whether I2DEST is used in I2SRC and similarly for the other
2978 cases. Knowing this will help in register status updating below. */
2989 /* For the earlier insns, determine which of the subsequent ones they
2990 feed. */
2997 /* Ensure that I3's pattern can be the destination of combines. */
3003 {
3006 }
3008 /* See if any of the insns is a MULT operation. Unless one is, we will
3009 reject a combination that is, since it must be slower. Be conservative
3010 here. */
3018 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3019 We used to do this EXCEPT in one case: I3 has a post-inc in an
3020 output operand. However, that exception can give rise to insns like
3021 mov r3,(r3)+
3022 which is a famous insn on the PDP-11 where the value of r3 used as the
3023 source was model-dependent. Avoid this sort of thing. */
3025 #if 0
3031 /* It's not the exception. */
3032 #endif
3034 {
3035 rtx link;
3041 {
3044 }
3045 }
3047 /* See if the SETs in I1 or I2 need to be kept around in the merged
3048 instruction: whenever the value set there is still needed past I3.
3049 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3051 For the SET in I1, we have two cases: if I1 and I2 independently feed
3052 into I3, the set in I1 needs to be kept around unless I1DEST dies
3053 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3054 in I1 needs to be kept around unless I1DEST dies or is set in either
3055 I2 or I3. The same considerations apply to I0. */
3062 else
3070 else
3073 /* We are about to copy insns for the case where they need to be kept
3074 around. Check that they can be copied in the merged instruction. */
3080 {
3083 }
3085 /* If the set in I2 needs to be kept around, we must make a copy of
3086 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3087 PATTERN (I2), we are only substituting for the original I1DEST, not into
3088 an already-substituted copy. This also prevents making self-referential
3089 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3090 I2DEST. */
3093 {
3096 else
3098 }
3101 {
3104 else
3106 }
3109 {
3112 else
3114 }
3116 combine_merges++;
3118 /* Substitute in the latest insn for the regs set by the earlier ones. */
3124 /* Many machines that don't use CC0 have insns that can both perform an
3125 arithmetic operation and set the condition code. These operations will
3126 be represented as a PARALLEL with the first element of the vector
3127 being a COMPARE of an arithmetic operation with the constant zero.
3128 The second element of the vector will set some pseudo to the result
3129 of the same arithmetic operation. If we simplify the COMPARE, we won't
3130 match such a pattern and so will generate an extra insn. Here we test
3131 for this case, where both the comparison and the operation result are
3132 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3133 I2SRC. Later we will make the PARALLEL that contains I2. */
3139 {
3140 rtx newpat_dest;
3154 {
3159 }
3161 /* Do the rest only if op1 is const0_rtx, which may be the
3162 result of simplification. */
3164 {
3165 /* If a single use of the CC is found, prepare to modify it
3166 when SELECT_CC_MODE returns a new CC-class mode, or when
3167 the above simplify_compare_const() returned a new comparison
3168 operator. undobuf.other_insn is assigned the CC use insn
3169 when modifying it. */
3171 {
3172 #ifdef SELECT_CC_MODE
3173 machine_mode new_mode
3178 {
3183 else
3184 {
3187 }
3188 }
3189 #endif
3190 /* Cases for modifying the CC-using comparison. */
3192 /* ??? Do we need to verify the zero rtx? */
3194 {
3195 /* Replace cc_use_loc with entire new RTX. */
3200 }
3202 {
3203 /* Just replace the CC reg with a new mode. */
3206 }
3207 }
3209 /* Now we modify the current newpat:
3210 First, SET_DEST(newpat) is updated if the CC mode has been
3211 altered. For targets without SELECT_CC_MODE, this should be
3212 optimized away. */
3215 /* This is always done to propagate i2src into newpat. */
3218 /* Create new version of i2pat if needed; the below PARALLEL
3219 creation needs this to work correctly. */
3223 }
3224 }
3227 {
3228 /* It is possible that the source of I2 or I1 may be performing
3229 an unneeded operation, such as a ZERO_EXTEND of something
3230 that is known to have the high part zero. Handle that case
3231 by letting subst look at the inner insns.
3233 Another way to do this would be to have a function that tries
3234 to simplify a single insn instead of merging two or more
3235 insns. We don't do this because of the potential of infinite
3236 loops and because of the potential extra memory required.
3237 However, doing it the way we are is a bit of a kludge and
3238 doesn't catch all cases.
3240 But only do this if -fexpensive-optimizations since it slows
3241 things down and doesn't usually win.
3243 This is not done in the COMPARE case above because the
3244 unmodified I2PAT is used in the PARALLEL and so a pattern
3245 with a modified I2SRC would not match. */
3248 {
3249 /* Pass pc_rtx so no substitutions are done, just
3250 simplifications. */
3252 {
3255 }
3259 }
3264 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3265 copy of I2SRC each time we substitute it, in order to avoid creating
3266 self-referential RTL when we will be substituting I1SRC for I1DEST
3267 later. Likewise if I0 feeds into I2, either directly or indirectly
3268 through I1, and I0DEST is in I0SRC. */
3275 /* Record whether I2's body now appears within I3's body. */
3277 }
3279 /* If we already got a failure, don't try to do more. Otherwise, try to
3280 substitute I1 if we have it. */
3283 {
3284 /* Check that an autoincrement side-effect on I1 has not been lost.
3285 This happens if I1DEST is mentioned in I2 and dies there, and
3286 has disappeared from the new pattern. */
3288 && i1_feeds_i2_n
3291 /* Before we can do this substitution, we must redo the test done
3292 above (see detailed comments there) that ensures I1DEST isn't
3293 mentioned in any SETs in NEWPAT that are field assignments. */
3296 {
3299 }
3304 /* If the following substitution will modify I1SRC, make a copy of it
3305 for the case where it is substituted for I1DEST in I2PAT later. */
3309 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3310 copy of I1SRC each time we substitute it, in order to avoid creating
3311 self-referential RTL when we will be substituting I0SRC for I0DEST
3312 later. */
3317 /* Record whether I1's body now appears within I3's body. */
3319 }
3321 /* Likewise for I0 if we have it. */
3324 {
3331 {
3334 }
3336 /* If the following substitution will modify I0SRC, make a copy of it
3337 for the case where it is substituted for I0DEST in I1PAT later. */
3340 /* And a copy for I0DEST in I2PAT substitution. */
3349 }
3351 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3352 to count all the ways that I2SRC and I1SRC can be used. */
3363 /* Fail if we tried to make a new register. */
3365 /* Fail if we couldn't do something and have a CLOBBER. */
3367 /* Fail if this new pattern is a MULT and we didn't have one before
3368 at the outer level. */
3371 {
3374 }
3376 /* If the actions of the earlier insns must be kept
3377 in addition to substituting them into the latest one,
3378 we must make a new PARALLEL for the latest insn
3379 to hold additional the SETs. */
3382 {
3384 combine_extras++;
3387 {
3393 }
3394 else
3395 {
3400 }
3406 {
3412 }
3414 {
3423 }
3424 }
3426 validate_replacement:
3428 /* Note which hard regs this insn has as inputs. */
3431 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3432 consider splitting this pattern, we might need these clobbers. */
3435 {
3441 }
3443 /* We have recognized nothing yet. */
3446 /* See if this is a PARALLEL of two SETs where one SET's destination is
3447 a register that is unused and this isn't marked as an instruction that
3448 might trap in an EH region. In that case, we just need the other SET.
3449 We prefer this over the PARALLEL.
3451 This can occur when simplifying a divmod insn. We *must* test for this
3452 case here because the code below that splits two independent SETs doesn't
3453 handle this case correctly when it updates the register status.
3455 It's pointless doing this if we originally had two sets, one from
3456 i3, and one from i2. Combining then splitting the parallel results
3457 in the original i2 again plus an invalid insn (which we delete).
3458 The net effect is only to move instructions around, which makes
3459 debug info less accurate. */
3464 {
3475 {
3478 }
3487 {
3493 }
3497 }
3499 /* Is the result of combination a valid instruction? */
3503 /* If we were combining three insns and the result is a simple SET
3504 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3505 insns. There are two ways to do this. It can be split using a
3506 machine-specific method (like when you have an addition of a large
3507 constant) or by combine in the function find_split_point. */
3511 {
3515 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3516 use I2DEST as a scratch register will help. In the latter case,
3517 convert I2DEST to the mode of the source of NEWPAT if we can. */
3521 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3522 inputs of NEWPAT. */
3524 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3525 possible to try that as a scratch reg. This would require adding
3526 more code to make it work though. */
3529 {
3532 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3533 (temporarily, until we are committed to this instruction
3534 combination) does not work: for example, any call to nonzero_bits
3535 on the register (from a splitter in the MD file, for example)
3536 will get the old information, which is invalid.
3538 Since nowadays we can create registers during combine just fine,
3539 we should just create a new one here, not reuse i2dest. */
3541 /* First try to split using the original register as a
3542 scratch register. */
3546 i2dest)));
3549 /* If that didn't work, try changing the mode of I2DEST if
3550 we can. */
3555 {
3557 rtx ni2dest;
3561 else
3562 {
3565 }
3567 parallel = (gen_rtx_PARALLEL
3571 ni2dest))));
3576 {
3584 }
3585 }
3588 }
3590 /* If recog_for_combine has discarded clobbers, try to use them
3591 again for the split. */
3593 {
3596 }
3599 {
3604 }
3608 {
3618 /* If I2 or I3 has multiple SETs, we won't know how to track
3619 register status, so don't use these insns. If I2's destination
3620 is used between I2 and I3, we also can't use these insns. */
3630 /* It is possible that both insns now set the destination of I3.
3631 If so, we must show an extra use of it. */
3634 {
3653 }
3654 }
3656 /* If we can split it and use I2DEST, go ahead and see if that
3657 helps things be recognized. Verify that none of the registers
3658 are set between I2 and I3. */
3662 /* We need I2DEST in the proper mode. If it is a hard register
3663 or the only use of a pseudo, we can change its mode.
3664 Make sure we don't change a hard register to have a mode that
3665 isn't valid for it, or change the number of registers. */
3672 /* We can't overwrite I2DEST if its value is still used by
3673 NEWPAT. */
3675 {
3684 /* *SPLIT may be part of I2SRC, so make sure we have the
3685 original expression around for later debug processing.
3686 We should not need I2SRC any more in other cases. */
3689 else
3692 /* Get NEWDEST as a register in the proper mode. We have already
3693 validated that we can do this. */
3695 {
3698 else
3699 {
3702 }
3703 }
3705 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3706 an ASHIFT. This can occur if it was inside a PLUS and hence
3707 appeared to be a memory address. This is a kludge. */
3712 {
3715 /* Update split_code because we may not have a multiply
3716 anymore. */
3718 }
3720 /* Similarly for (plus (mult FOO (const_int pow2))). */
3726 {
3730 /* Update split_code because we may not have a multiply
3731 anymore. */
3733 }
3735 #ifdef INSN_SCHEDULING
3736 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3737 be written as a ZERO_EXTEND. */
3739 {
3740 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3741 what it really is. */
3746 else
3749 }
3750 #endif
3752 /* Attempt to split binary operators using arithmetic identities. */
3756 {
3763 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3765 {
3770 }
3771 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3778 {
3784 /* Split both "((X op Y) op X) op Y" and
3785 "((X op Y) op Y) op X" as "T op T" where T is
3786 "X op Y". */
3789 {
3794 }
3795 /* Split "((X op X) op Y) op Y)" as "T op T" where
3796 T is "X op Y". */
3798 {
3804 }
3805 }
3806 }
3809 {
3812 }
3816 /* recog_for_combine might have added CLOBBERs to newi2pat.
3817 Make sure NEWPAT does not depend on the clobbered regs. */
3821 {
3824 {
3827 }
3828 }
3830 /* If the split point was a MULT and we didn't have one before,
3831 don't use one now. */
3834 }
3835 }
3837 /* Check for a case where we loaded from memory in a narrow mode and
3838 then sign extended it, but we need both registers. In that case,
3839 we have a PARALLEL with both loads from the same memory location.
3840 We can split this into a load from memory followed by a register-register
3841 copy. This saves at least one insn, more if register allocation can
3842 eliminate the copy.
3844 We cannot do this if the destination of the first assignment is a
3845 condition code register or cc0. We eliminate this case by making sure
3846 the SET_DEST and SET_SRC have the same mode.
3848 We cannot do this if the destination of the second assignment is
3849 a register that we have already assumed is zero-extended. Similarly
3850 for a SUBREG of such a register. */
3885 {
3886 rtx ni2dest;
3900 }
3902 /* Similarly, check for a case where we have a PARALLEL of two independent
3903 SETs but we started with three insns. In this case, we can do the sets
3904 as two separate insns. This case occurs when some SET allows two
3905 other insns to combine, but the destination of that SET is still live.
3907 Also do this if we started with two insns and (at least) one of the
3908 resulting sets is a noop; this noop will be deleted later. */
3927 {
3931 /* Normally, it doesn't matter which of the two is done first,
3932 but the one that references cc0 can't be the second, and
3933 one which uses any regs/memory set in between i2 and i3 can't
3934 be first. The PARALLEL might also have been pre-existing in i3,
3935 so we need to make sure that we won't wrongly hoist a SET to i2
3936 that would conflict with a death note present in there. */
3944 /* If I3 is a jump, ensure that set0 is a jump so that
3945 we do not create invalid RTL. */
3947 )
3948 {
3951 }
3959 /* If I3 is a jump, ensure that set1 is a jump so that
3960 we do not create invalid RTL. */
3962 )
3963 {
3966 }
3967 else
3968 {
3971 }
3976 {
3977 /* recog_for_combine might have added CLOBBERs to newi2pat.
3978 Make sure NEWPAT does not depend on the clobbered regs. */
3980 {
3983 {
3986 {
3989 }
3990 }
3991 }
3994 }
3995 }
3997 /* If it still isn't recognized, fail and change things back the way they
3998 were. */
4000 /* Is the result a reasonable ASM_OPERANDS? */
4002 {
4005 }
4007 /* If we had to change another insn, make sure it is valid also. */
4009 {
4017 {
4020 }
4021 }
4023 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4024 they are adjacent to each other or not. */
4026 {
4030 {
4033 }
4034 }
4036 /* Only allow this combination if insn_rtx_costs reports that the
4037 replacement instructions are cheaper than the originals. */
4039 {
4042 }
4045 {
4050 {
4055 /* Temporarily revert mode back. */
4059 {
4060 /* If we used i2dest as a scratch register with a
4061 different mode, substitute it for the original
4062 i2src while its original mode is temporarily
4063 restored, and then clear i2scratch so that we don't
4064 do it again later. */
4066 this_basic_block);
4068 /* Put back the new mode. */
4070 }
4071 else
4072 {
4077 {
4080 }
4081 else
4082 {
4089 }
4091 /* We're dealing with a reg that changed mode but not
4092 meaning, so we want to turn it into a subreg for
4093 the new mode. However, because of REG sharing and
4094 because its mode had already changed, we have to do
4095 it in two steps. First, replace any debug uses of
4096 reg, with its original mode temporarily restored,
4097 with this copy we have created; then, replace the
4098 copy with the SUBREG of the original shared reg,
4099 once again changed to the new mode. */
4101 this_basic_block);
4105 this_basic_block);
4106 }
4107 }
4108 }
4110 /* If we will be able to accept this, we have made a
4111 change to the destination of I3. This requires us to
4112 do a few adjustments. */
4115 {
4118 }
4120 /* We now know that we can do this combination. Merge the insns and
4121 update the status of registers and LOG_LINKS. */
4124 {
4129 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4130 ensure that they are still valid. Then add any non-duplicate
4131 notes added by recog_for_combine. */
4133 {
4143 }
4147 NULL_RTX);
4148 }
4151 {
4154 rtx ni2dest;
4156 /* I3 now uses what used to be its destination and which is now
4157 I2's destination. This requires us to do a few adjustments. */
4161 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4162 so we still will.
4164 However, some later insn might be using I2's dest and have
4165 a LOG_LINK pointing at I3. We must remove this link.
4166 The simplest way to remove the link is to point it at I1,
4167 which we know will be a NOTE. */
4169 /* newi2pat is usually a SET here; however, recog_for_combine might
4170 have added some clobbers. */
4173 else
4180 {
4182 {
4188 }
4189 }
4190 }
4192 {
4197 /* Compute which registers we expect to eliminate. newi2pat may be setting
4198 either i3dest or i2dest, so we must check it. */
4201 || !i2dest_killed
4203 /* For i1, we need to compute both local elimination and global
4204 elimination information with respect to newi2pat because i1dest
4205 may be the same as i3dest, in which case newi2pat may be setting
4206 i1dest. Global information is used when distributing REG_DEAD
4207 note for i2 and i3, in which case it does matter if newi2pat sets
4208 i1dest or not.
4210 Local information is used when distributing REG_DEAD note for i1,
4211 in which case it doesn't matter if newi2pat sets i1dest or not.
4212 See PR62151, if we have four insns combination:
4213 i0: r0 <- i0src
4214 i1: r1 <- i1src (using r0)
4215 REG_DEAD (r0)
4216 i2: r0 <- i2src (using r1)
4217 i3: r3 <- i3src (using r0)
4218 ix: using r0
4219 From i1's point of view, r0 is eliminated, no matter if it is set
4220 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4221 should be discarded.
4223 Note local information only affects cases in forms like "I1->I2->I3",
4224 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4225 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4226 i0dest anyway. */
4228 || !i1dest_killed
4233 /* Same case as i1. */
4240 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4241 clear them. */
4249 /* Ensure that we do not have something that should not be shared but
4250 occurs multiple times in the new insns. Check this by first
4251 resetting all the `used' flags and then copying anything is shared. */
4275 {
4282 {
4283 /* I2SRC must still be meaningful at this point. Some splitting
4284 operations can invalidate I2SRC, but those operations do not
4285 apply to calls. */
4288 }
4296 }
4301 /* We had one special case above where I2 had more than one set and
4302 we replaced a destination of one of those sets with the destination
4303 of I3. In that case, we have to update LOG_LINKS of insns later
4304 in this basic block. Note that this (expensive) case is rare.
4306 Also, in this case, we must pretend that all REG_NOTEs for I2
4307 actually came from I3, so that REG_UNUSED notes from I2 will be
4308 properly handled. */
4311 {
4320 temp_insn
4330 {
4335 }
4336 else
4339 }
4347 {
4350 this_basic_block);
4353 }
4354 else
4355 {
4358 this_basic_block);
4360 }
4363 {
4368 this_basic_block);
4370 }
4373 {
4378 this_basic_block);
4380 }
4382 /* Get death notes for everything that is now used in either I3 or
4383 I2 and used to die in a previous insn. If we built two new
4384 patterns, move from I1 to I2 then I2 to I3 so that we get the
4385 proper movement on registers that I2 modifies. */
4391 else
4397 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4414 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4415 know these are REG_UNUSED and want them to go to the desired insn,
4416 so we always pass it as i3. */
4420 NULL_RTX);
4424 NULL_RTX);
4426 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4427 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4428 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4429 in that case, it might delete I2. Similarly for I2 and I1.
4430 Show an additional death due to the REG_DEAD note we make here. If
4431 we discard it in distribute_notes, we will decrement it again. */
4434 {
4439 else
4442 }
4445 {
4450 else
4453 }
4456 {
4461 else
4464 }
4467 {
4472 else
4475 }
4483 {
4488 /* The insn that used to set this register doesn't exist, and
4489 this life of the register may not exist either. See if one of
4490 I3's links points to an insn that sets I2DEST. If it does,
4491 that is now the last known value for I2DEST. If we don't update
4492 this and I2 set the register to a value that depended on its old
4493 contents, we will get confused. If this insn is used, thing
4494 will be set correctly in combine_instructions. */
4502 /* If the reg formerly set in I2 died only once and that was in I3,
4503 zero its use count so it won't make `reload' do any work. */
4506 && ! i2dest_in_i2src
4509 }
4512 {
4525 && ! i1dest_in_i1src
4528 }
4531 {
4544 && ! i0dest_in_i0src
4547 }
4549 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4550 been made to this insn. The order is important, because newi2pat
4551 can affect nonzero_bits of newpat. */
4555 }
4558 {
4560 {
4563 }
4565 }
4568 {
4570 {
4573 }
4575 }
4578 {
4580 {
4583 }
4585 }
4588 {
4590 {
4593 }
4595 }
4598 {
4600 {
4603 }
4605 }
4607 /* Set new_direct_jump_p if a new return or simple jump instruction
4608 has been created. Adjust the CFG accordingly. */
4610 {
4614 }
4619 {
4622 }
4626 {
4632 }
4637 {
4643 }
4645 /* A noop might also need cleaning up of CFG, if it comes from the
4646 simplification of a jump. */
4651 {
4654 }
4661 {
4664 }
4666 combine_successes++;
4673 else
4675 }
4676 \f
4677 /* Get a marker for undoing to the current state. */
4681 {
4683 }
4685 /* Undo the modifications up to the marker. */
4687 static void
4689 {
4693 {
4698 {
4713 }
4717 }
4720 }
4722 /* Undo all the modifications recorded in undobuf. */
4724 static void
4726 {
4728 }
4730 /* We've committed to accepting the changes we made. Move all
4731 of the undos to the free list. */
4733 static void
4735 {
4739 {
4743 }
4745 }
4746 \f
4747 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4748 where we have an arithmetic expression and return that point. LOC will
4749 be inside INSN.
4751 try_combine will call this function to see if an insn can be split into
4752 two insns. */
4756 {
4765 /* First special-case some codes. */
4767 {
4769 #ifdef INSN_SCHEDULING
4770 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4771 point. */
4774 #endif
4778 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4779 using LO_SUM and HIGH. */
4782 {
4790 }
4792 /* If we have a PLUS whose second operand is a constant and the
4793 address is not valid, perhaps will can split it up using
4794 the machine-specific way to split large constants. We use
4795 the first pseudo-reg (one of the virtual regs) as a placeholder;
4796 it will not remain in the result. */
4801 {
4804 subst_insn);
4806 /* This should have produced two insns, each of which sets our
4807 placeholder. If the source of the second is a valid address,
4808 we can make put both sources together and make a split point
4809 in the middle. */
4822 && memory_address_addr_space_p
4825 {
4829 /* Replace the placeholder in SRC2 with SRC1. If we can
4830 find where in SRC2 it was placed, that can become our
4831 split point and we can replace this address with SRC2.
4832 Just try two obvious places. */
4843 {
4846 }
4847 }
4849 /* If that didn't work, perhaps the first operand is complex and
4850 needs to be computed separately, so make a split point there.
4851 This will occur on machines that just support REG + CONST
4852 and have a constant moved through some previous computation. */
4858 }
4860 /* If we have a PLUS whose first operand is complex, try computing it
4861 separately by making a split there. */
4872 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4873 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4874 we need to put the operand into a register. So split at that
4875 point. */
4885 /* See if we can split SET_SRC as it stands. */
4890 /* See if we can split SET_DEST as it stands. */
4895 /* See if this is a bitfield assignment with everything constant. If
4896 so, this is an IOR of an AND, so split it into that. */
4906 {
4912 unsigned HOST_WIDE_INT mask
4914 rtx or_mask;
4923 else
4924 {
4930 or_mask));
4931 }
4938 }
4940 /* Otherwise, see if this is an operation that we can split into two.
4941 If so, try to split that. */
4945 {
4947 /* If we are AND'ing with a large constant that is only a single
4948 bit and the result is only being used in a context where we
4949 need to know if it is zero or nonzero, replace it with a bit
4950 extraction. This will avoid the large constant, which might
4951 have taken more than one insn to make. If the constant were
4952 not a valid argument to the AND but took only one insn to make,
4953 this is no worse, but if it took more than one insn, it will
4954 be better. */
4964 {
4969 {
4972 }
4973 }
4977 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4978 is known to be on, this can be converted into a NEG of a shift. */
4984 {
4996 }
5002 /* We can't optimize if either mode is a partial integer
5003 mode as we don't know how many bits are significant
5004 in those modes. */
5018 {
5026 }
5031 }
5035 {
5038 /* For unsigned, we have a choice of a shift followed by an
5039 AND or two shifts. Use two shifts for field sizes where the
5040 constant might be too large. We assume here that we can
5041 always at least get 8-bit constants in an AND insn, which is
5042 true for every current RISC. */
5045 {
5046 unsigned HOST_WIDE_INT mask
5050 gen_rtx_LSHIFTRT
5058 }
5059 else
5060 {
5062 gen_rtx_fmt_ee
5073 }
5074 }
5076 /* See if this is a simple operation with a constant as the second
5077 operand. It might be that this constant is out of range and hence
5078 could be used as a split point. */
5086 /* Finally, see if this is a simple operation with its first operand
5087 not in a register. The operation might require this operand in a
5088 register, so return it as a split point. We can always do this
5089 because if the first operand were another operation, we would have
5090 already found it as a split point. */
5099 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5100 it is better to write this as (not (ior A B)) so we can split it.
5101 Similarly for IOR. */
5103 {
5111 }
5113 /* Many RISC machines have a large set of logical insns. If the
5114 second operand is a NOT, put it first so we will try to split the
5115 other operand first. */
5117 {
5121 }
5126 /* Canonicalization can produce (minus A (mult B C)), where C is a
5127 constant. It may be better to try splitting (plus (mult B -C) A)
5128 instead if this isn't a multiply by a power of two. */
5132 {
5140 mode)),
5143 }
5145 /* Split at a multiply-accumulate instruction. However if this is
5146 the SET_SRC, we likely do not have such an instruction and it's
5147 worthless to try this split. */
5156 }
5158 /* Otherwise, select our actions depending on our rtx class. */
5160 {
5166 /* fall through */
5174 /* fall through */
5176 /* Some machines have (and (shift ...) ...) insns. If X is not
5177 an AND, but XEXP (X, 0) is, use it as our split point. */
5187 /* Otherwise, we don't have a split point. */
5189 }
5190 }
5191 \f
5192 /* Throughout X, replace FROM with TO, and return the result.
5193 The result is TO if X is FROM;
5194 otherwise the result is X, but its contents may have been modified.
5195 If they were modified, a record was made in undobuf so that
5196 undo_all will (among other things) return X to its original state.
5198 If the number of changes necessary is too much to record to undo,
5199 the excess changes are not made, so the result is invalid.
5200 The changes already made can still be undone.
5201 undobuf.num_undo is incremented for such changes, so by testing that
5202 the caller can tell whether the result is valid.
5204 `n_occurrences' is incremented each time FROM is replaced.
5206 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5208 IN_COND is nonzero if we are at the top level of a condition.
5210 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5211 by copying if `n_occurrences' is nonzero. */
5213 static rtx
5215 {
5220 rtx new_rtx;
5222 /* Two expressions are equal if they are identical copies of a shared
5223 RTX or if they are both registers with the same register number
5224 and mode. */
5226 #define COMBINE_RTX_EQUAL_P(X,Y) \
5227 ((X) == (Y) \
5228 || (REG_P (X) && REG_P (Y) \
5229 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5231 /* Do not substitute into clobbers of regs -- this will never result in
5232 valid RTL. */
5237 {
5238 n_occurrences++;
5240 }
5242 /* If X and FROM are the same register but different modes, they
5243 will not have been seen as equal above. However, the log links code
5244 will make a LOG_LINKS entry for that case. If we do nothing, we
5245 will try to rerecognize our original insn and, when it succeeds,
5246 we will delete the feeding insn, which is incorrect.
5248 So force this insn not to match in this (rare) case. */
5253 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5254 of which may contain things that can be combined. */
5258 /* It is possible to have a subexpression appear twice in the insn.
5259 Suppose that FROM is a register that appears within TO.
5260 Then, after that subexpression has been scanned once by `subst',
5261 the second time it is scanned, TO may be found. If we were
5262 to scan TO here, we would find FROM within it and create a
5263 self-referent rtl structure which is completely wrong. */
5267 /* Parallel asm_operands need special attention because all of the
5268 inputs are shared across the arms. Furthermore, unsharing the
5269 rtl results in recognition failures. Failure to handle this case
5270 specially can result in circular rtl.
5272 Solve this by doing a normal pass across the first entry of the
5273 parallel, and only processing the SET_DESTs of the subsequent
5274 entries. Ug. */
5279 {
5282 /* If this substitution failed, this whole thing fails. */
5290 {
5296 {
5299 /* If this substitution failed, this whole thing fails. */
5305 }
5306 }
5307 }
5308 else
5309 {
5313 /* We don't need to process a SET_DEST that is a register, CC0,
5314 or PC, so set up to skip this common case. All other cases
5315 where we want to suppress replacing something inside a
5316 SET_SRC are handled via the IN_DEST operand. */
5323 /* Trying to simplify the operands of a widening MULT is not likely
5324 to create RTL matching a machine insn. */
5336 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5337 constant. */
5342 {
5344 {
5347 {
5349 {
5352 n_occurrences++;
5353 }
5354 else
5355 {
5357 unique_copy);
5359 /* If this substitution failed, this whole thing
5360 fails. */
5364 }
5367 }
5368 }
5370 {
5371 /* If this is a register being set, ignore it. */
5378 ;
5381 {
5382 /* In general, don't install a subreg involving two
5383 modes not tieable. It can worsen register
5384 allocation, and can even make invalid reload
5385 insns, since the reg inside may need to be copied
5386 from in the outside mode, and that may be invalid
5387 if it is an fp reg copied in integer mode.
5389 We allow two exceptions to this: It is valid if
5390 it is inside another SUBREG and the mode of that
5391 SUBREG and the mode of the inside of TO is
5392 tieable and it is valid if X is a SET that copies
5393 FROM to CC0. */
5401 && (!HAVE_cc0
5416 n_occurrences++;
5417 }
5418 else
5419 /* If we are in a SET_DEST, suppress most cases unless we
5420 have gone inside a MEM, in which case we want to
5421 simplify the address. We assume here that things that
5422 are actually part of the destination have their inner
5423 parts in the first expression. This is true for SUBREG,
5424 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5425 things aside from REG and MEM that should appear in a
5426 SET_DEST. */
5428 (((in_dest
5434 unique_copy);
5436 /* If we found that we will have to reject this combination,
5437 indicate that by returning the CLOBBER ourselves, rather than
5438 an expression containing it. This will speed things up as
5439 well as prevent accidents where two CLOBBERs are considered
5440 to be equal, thus producing an incorrect simplification. */
5446 {
5454 }
5457 {
5461 }
5462 else
5464 }
5465 }
5466 }
5468 /* Check if we are loading something from the constant pool via float
5469 extension; in this case we would undo compress_float_constant
5470 optimization and degenerate constant load to an immediate value. */
5474 {
5478 }
5480 /* Try to simplify X. If the simplification changed the code, it is likely
5481 that further simplification will help, so loop, but limit the number
5482 of repetitions that will be performed. */
5485 {
5486 /* If X is sufficiently simple, don't bother trying to do anything
5487 with it. */
5496 /* We no longer know the original mode of operand 0 since we
5497 have changed the form of X) */
5499 }
5502 }
5503 \f
5504 /* If X is a commutative operation whose operands are not in the canonical
5505 order, use substitutions to swap them. */
5507 static void
5509 {
5512 {
5516 }
5517 }
5519 /* Simplify X, a piece of RTL. We just operate on the expression at the
5520 outer level; call `subst' to simplify recursively. Return the new
5521 expression.
5523 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5524 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5525 of a condition. */
5527 static rtx
5530 {
5533 rtx temp;
5536 /* If this is a commutative operation, put a constant last and a complex
5537 expression first. We don't need to do this for comparisons here. */
5540 /* Try to fold this expression in case we have constants that weren't
5541 present before. */
5544 {
5552 {
5555 {
5559 }
5562 }
5575 }
5578 {
5583 }
5585 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5586 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5587 things. Check for cases where both arms are testing the same
5588 condition.
5590 Don't do anything if all operands are very simple. */
5603 {
5607 /* If the operation is an AND wrapped in a SIGN_EXTEND or ZERO_EXTEND with
5608 either operand being just a constant single bit value, do nothing since
5609 IF_THEN_ELSE is likely to increase the expression's complexity. */
5620 /* If everything is a comparison, what we have is highly unlikely
5621 to be simpler, so don't use it. */
5624 {
5631 /* Simplify the alternative arms; this may collapse the true and
5632 false arms to store-flag values. Be careful to use copy_rtx
5633 here since true_rtx or false_rtx might share RTL with x as a
5634 result of the if_then_else_cond call above. */
5638 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5639 is unlikely to be simpler. */
5642 {
5645 /* Restarting if we generate a store-flag expression will cause
5646 us to loop. Just drop through in this case. */
5648 /* If the result values are STORE_FLAG_VALUE and zero, we can
5649 just make the comparison operation. */
5660 /* Likewise, we can make the negate of a comparison operation
5661 if the result values are - STORE_FLAG_VALUE and zero. */
5669 mode);
5680 mode);
5681 else
5684 mode,
5685 VOIDmode,
5686 cond,
5687 cop1),
5692 }
5693 }
5694 }
5696 /* First see if we can apply the inverse distributive law. */
5699 {
5703 }
5705 /* If CODE is an associative operation not otherwise handled, see if we
5706 can associate some operands. This can win if they are constants or
5707 if they are logically related (i.e. (a & b) & a). */
5713 {
5715 {
5719 rtx inner;
5721 /* Make sure we pass the constant operand if any as the second
5722 one if this is a commutative operation. */
5730 /* For commutative operations, try the other pair if that one
5731 didn't simplify. */
5733 {
5738 }
5742 }
5743 }
5745 /* A little bit of algebraic simplification here. */
5747 {
5749 /* Ensure that our address has any ASHIFTs converted to MULT in case
5750 address-recognizing predicates are called later. */
5759 /* See if this can be moved to simplify_subreg. */
5762 /* Don't call gen_lowpart if the inner mode
5763 is VOIDmode and we cannot simplify it, as SUBREG without
5764 inner mode is invalid. */
5771 {
5772 rtx temp;
5778 /* If op is known to have all lower bits zero, the result is zero. */
5788 }
5790 /* Don't change the mode of the MEM if that would change the meaning
5791 of the address. */
5798 /* Note that we cannot do any narrowing for non-constants since
5799 we might have been counting on using the fact that some bits were
5800 zero. We now do this in the SET. */
5807 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5808 replaced by (lshiftrt X C). This will convert
5809 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5817 /* If X has only a single bit that might be nonzero, say, bit I, convert
5818 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5819 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5820 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5821 or a SUBREG of one since we'd be making the expression more
5822 complex if it was just a register. */
5828 {
5829 rtx temp1 = simplify_shift_const
5835 /* If all we did was surround TEMP with the two shifts, we
5836 haven't improved anything, so don't use it. Otherwise,
5837 we are better off with TEMP1. */
5842 }
5846 /* We can't handle truncation to a partial integer mode here
5847 because we don't know the real bitsize of the partial
5848 integer mode. */
5857 /* We can truncate a constant value and return it. */
5861 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5862 whose value is a comparison can be replaced with a subreg if
5863 STORE_FLAG_VALUE permits. */
5872 /* (const (const X)) can become (const X). Do it this way rather than
5873 returning the inner CONST since CONST can be shared with a
5874 REG_EQUAL note. */
5880 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5881 can add in an offset. find_split_point will split this address up
5882 again if it doesn't match. */
5889 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5890 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5891 bit-field and can be replaced by either a sign_extend or a
5892 sign_extract. The `and' may be a zero_extend and the two
5893 <c>, -<c> constants may be reversed. */
5908 return simplify_shift_const
5915 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5916 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5917 the bitsize of the mode - 1. This allows simplification of
5918 "a = (b & 8) == 0;" */
5930 /* If we are adding two things that have no bits in common, convert
5931 the addition into an IOR. This will often be further simplified,
5932 for example in cases like ((a & 1) + (a & 2)), which can
5933 become a & 3. */
5938 {
5939 /* Try to simplify the expression further. */
5943 /* If we could, great. If not, do not go ahead with the IOR
5944 replacement, since PLUS appears in many special purpose
5945 address arithmetic instructions. */
5953 }
5955 /* Canonicalize x + x into x << 1. */
5964 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5965 (and <foo> (const_int pow2-1)) */
5975 /* If we have (mult (plus A B) C), apply the distributive law and then
5976 the inverse distributive law to see if things simplify. This
5977 occurs mostly in addresses, often when unrolling loops. */
5980 {
5984 }
5986 /* Try simplify a*(b/c) as (a*b)/c. */
5989 {
5995 }
5999 /* If this is a divide by a power of two, treat it as a shift if
6000 its first operand is a shift. */
6018 /* If the first operand is a condition code, we can't do anything
6019 with it. */
6023 {
6031 /* Simplify our comparison, if possible. */
6034 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6035 if only the low-order bit is possibly nonzero in X (such as when
6036 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6037 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6038 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6039 (plus X 1).
6041 Remove any ZERO_EXTRACT we made when thinking this was a
6042 comparison. It may now be simpler to use, e.g., an AND. If a
6043 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6044 the call to make_compound_operation in the SET case.
6046 Don't apply these optimizations if the caller would
6047 prefer a comparison rather than a value.
6048 E.g., for the condition in an IF_THEN_ELSE most targets need
6049 an explicit comparison. */
6052 ;
6068 {
6072 mode);
6073 }
6080 {
6084 const1_rtx);
6085 }
6093 {
6096 }
6098 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6099 those above. */
6101 ;
6117 {
6121 mode);
6122 }
6130 {
6134 mode);
6135 }
6137 /* If X is 0/1, (eq X 0) is X-1. */
6143 {
6146 }
6148 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6149 one bit that might be nonzero, we can convert (ne x 0) to
6150 (ashift x c) where C puts the bit in the sign bit. Remove any
6151 AND with STORE_FLAG_VALUE when we are done, since we are only
6152 going to test the sign bit. */
6159 {
6165 else
6167 }
6169 /* If the code changed, return a whole new comparison.
6170 We also need to avoid using SUBST in cases where
6171 simplify_comparison has widened a comparison with a CONST_INT,
6172 since in that case the wider CONST_INT may fail the sanity
6173 checks in do_SUBST. */
6180 /* Otherwise, keep this operation, but maybe change its operands.
6181 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6184 }
6194 /* If we are processing SET_DEST, we are done. */
6212 /* If this is a shift by a constant amount, simplify it. */
6220 (HOST_WIDE_INT_1U
6228 }
6231 }
6232 \f
6233 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6235 static rtx
6237 {
6244 rtx temp;
6247 rtx reversed;
6249 /* Simplify storing of the truth value. */
6254 /* Also when the truth value has to be reversed. */
6260 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6261 in it is being compared against certain values. Get the true and false
6262 comparisons and see if that says anything about the value of each arm. */
6268 {
6269 HOST_WIDE_INT nzb;
6275 /* If FALSE_CODE is EQ, swap the codes and arms. */
6278 {
6281 }
6283 /* If we are comparing against zero and the expression being tested has
6284 only a single bit that might be nonzero, that is its value when it is
6285 not equal to zero. Similarly if it is known to be -1 or 0. */
6289 {
6292 }
6296 {
6299 }
6301 /* Now simplify an arm if we know the value of the register in the
6302 branch and it is used in the arm. Be careful due to the potential
6303 of locally-shared RTL. */
6320 }
6322 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6323 reversed, do so to avoid needing two sets of patterns for
6324 subtract-and-branch insns. Similarly if we have a constant in the true
6325 arm, the false arm is the same as the first operand of the comparison, or
6326 the false arm is more complicated than the true arm. */
6339 {
6348 /* It is possible that the conditional has been simplified out. */
6351 }
6353 /* If the two arms are identical, we don't need the comparison. */
6358 /* Convert a == b ? b : a to "a". */
6370 /* Look for cases where we have (abs x) or (neg (abs X)). */
6373 && comparison_p
6380 {
6386 return
6389 mode);
6392 }
6394 /* Look for MIN or MAX. */
6397 && comparison_p
6402 {
6417 }
6419 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6420 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6421 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6422 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6423 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6424 neither 1 or -1, but it isn't worth checking for. */
6427 && comparison_p
6430 {
6446 /* If an identity-zero op is commutative, check whether there
6447 would be a match if we swapped the operands. */
6467 {
6471 }
6483 {
6487 }
6503 {
6507 }
6519 {
6523 }
6526 {
6532 const_true_rtx));
6540 }
6541 }
6543 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6544 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6545 negation of a single bit, we can convert this operation to a shift. We
6546 can actually do this more generally, but it doesn't seem worth it. */
6555 return
6559 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6560 non-zero bit in A is C1. */
6567 {
6574 }
6577 }
6578 \f
6579 /* Simplify X, a SET expression. Return the new expression. */
6581 static rtx
6583 {
6586 machine_mode mode
6591 /* (set (pc) (return)) gets written as (return). */
6595 /* Now that we know for sure which bits of SRC we are using, see if we can
6596 simplify the expression for the object knowing that we only need the
6597 low-order bits. */
6600 {
6603 }
6605 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6606 the comparison result and try to simplify it unless we already have used
6607 undobuf.other_insn. */
6615 {
6624 {
6627 {
6630 }
6631 }
6632 else
6640 {
6644 }
6645 else
6646 {
6651 /* Attempt to simplify CC user. */
6653 {
6657 }
6659 /* Convert X into a no-op move. */
6663 }
6665 /* Simplify our comparison, if possible. */
6668 #ifdef SELECT_CC_MODE
6669 /* If this machine has CC modes other than CCmode, check to see if we
6670 need to use a different CC mode here. */
6679 else
6682 /* If the mode changed, we have to change SET_DEST, the mode in the
6683 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6684 a hard register, just build new versions with the proper mode. If it
6685 is a pseudo, we lose unless it is only time we set the pseudo, in
6686 which case we can safely change its mode. */
6688 {
6690 {
6692 rtx new_dest;
6696 else
6697 {
6700 }
6707 }
6708 }
6711 /* If the code changed, we have to build a new comparison in
6712 undobuf.other_insn. */
6714 {
6723 /* If the only change we made was to change an EQ into an NE or
6724 vice versa, OP0 has only one bit that might be nonzero, and OP1
6725 is zero, check if changing the user of the condition code will
6726 produce a valid insn. If it won't, we can keep the original code
6727 in that insn by surrounding our operation with an XOR. */
6734 {
6739 {
6746 }
6747 }
6748 }
6753 /* Don't generate a compare of a CC with 0, just use that CC. */
6755 {
6758 }
6759 /* Otherwise, if we didn't previously have the same COMPARE we
6760 want, create it from scratch. */
6763 {
6766 }
6767 }
6768 else
6769 {
6770 /* Get SET_SRC in a form where we have placed back any
6771 compound expressions. Then do the checks below. */
6774 }
6776 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6777 and X being a REG or (subreg (reg)), we may be able to convert this to
6778 (set (subreg:m2 x) (op)).
6780 We can always do this if M1 is narrower than M2 because that means that
6781 we only care about the low bits of the result.
6783 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6784 perform a narrower operation than requested since the high-order bits will
6785 be undefined. On machine where it is defined, this transformation is safe
6786 as long as M1 and M2 have the same number of words. */
6794 && (WORD_REGISTER_OPERATIONS
6797 #ifdef CANNOT_CHANGE_MODE_CLASS
6802 #endif
6806 {
6809 dest));
6813 }
6815 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6816 in SRC. */
6822 {
6826 /* Here we make sure that we don't have a sign bit on. */
6829 {
6832 }
6833 }
6835 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6836 would require a paradoxical subreg. Replace the subreg with a
6837 zero_extend to avoid the reload that would otherwise be required. */
6843 {
6848 }
6850 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6851 are comparing an item known to be 0 or -1 against 0, use a logical
6852 operation instead. Check for one of the arms being an IOR of the other
6853 arm with some value. We compute three terms to be IOR'ed together. In
6854 practice, at most two will be nonzero. Then we do the IOR's. */
6862 && (!HAVE_conditional_move
6868 {
6894 false_rtx);
6900 term3));
6903 }
6905 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6906 whole thing fail. */
6911 else
6912 /* Convert this into a field assignment operation, if possible. */
6914 }
6915 \f
6916 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6917 result. */
6919 static rtx
6921 {
6927 {
6929 /* We can call simplify_and_const_int only if we don't lose
6930 any (sign) bits when converting INTVAL (op1) to
6931 "unsigned HOST_WIDE_INT". */
6935 {
6942 }
6944 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6945 apply the distributive law and then the inverse distributive
6946 law to see if things simplify. */
6948 {
6952 }
6954 {
6958 }
6962 /* If we have (ior (and A B) C), apply the distributive law and then
6963 the inverse distributive law to see if things simplify. */
6966 {
6970 }
6973 {
6977 }
6982 }
6985 }
6986 \f
6987 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6988 operations" because they can be replaced with two more basic operations.
6989 ZERO_EXTEND is also considered "compound" because it can be replaced with
6990 an AND operation, which is simpler, though only one operation.
6992 The function expand_compound_operation is called with an rtx expression
6993 and will convert it to the appropriate shifts and AND operations,
6994 simplifying at each stage.
6996 The function make_compound_operation is called to convert an expression
6997 consisting of shifts and ANDs into the equivalent compound expression.
6998 It is the inverse of this function, loosely speaking. */
7000 static rtx
7002 {
7006 rtx tem;
7009 {
7012 /* FALLTHRU */
7014 /* We can't necessarily use a const_int for a multiword mode;
7015 it depends on implicitly extending the value.
7016 Since we don't know the right way to extend it,
7017 we can't tell whether the implicit way is right.
7019 Even for a mode that is no wider than a const_int,
7020 we can't win, because we need to sign extend one of its bits through
7021 the rest of it, and we don't know which bit. */
7025 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7026 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7027 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7028 reloaded. If not for that, MEM's would very rarely be safe.
7030 Reject MODEs bigger than a word, because we might not be able
7031 to reference a two-register group starting with an arbitrary register
7032 (and currently gen_lowpart might crash for a SUBREG). */
7037 /* Reject MODEs that aren't scalar integers because turning vector
7038 or complex modes into shifts causes problems. */
7044 /* If the inner object has VOIDmode (the only way this can happen
7045 is if it is an ASM_OPERANDS), we can't do anything since we don't
7046 know how much masking to do. */
7055 /* fall through */
7058 /* If the operand is a CLOBBER, just return it. */
7067 /* Reject MODEs that aren't scalar integers because turning vector
7068 or complex modes into shifts causes problems. */
7076 /* This should stay within the object being extracted, fail otherwise. */
7087 }
7088 /* Convert sign extension to zero extension, if we know that the high
7089 bit is not set, as this is easier to optimize. It will be converted
7090 back to cheaper alternative in make_extraction. */
7098 {
7103 /* Make sure this is a profitable operation. */
7110 else
7112 }
7114 /* We can optimize some special cases of ZERO_EXTEND. */
7116 {
7117 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7118 know that the last value didn't have any inappropriate bits
7119 set. */
7127 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7136 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7137 is a comparison and STORE_FLAG_VALUE permits. This is like
7138 the first case, but it works even when GET_MODE (x) is larger
7139 than HOST_WIDE_INT. */
7148 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7158 }
7160 /* If we reach here, we want to return a pair of shifts. The inner
7161 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7162 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7163 logical depending on the value of UNSIGNEDP.
7165 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7166 converted into an AND of a shift.
7168 We must check for the case where the left shift would have a negative
7169 count. This can happen in a case like (x >> 31) & 255 on machines
7170 that can't shift by a constant. On those machines, we would first
7171 combine the shift with the AND to produce a variable-position
7172 extraction. Then the constant of 31 would be substituted in
7173 to produce such a position. */
7177 {
7186 }
7193 else
7194 /* Any other cases we can't handle. */
7197 /* If we couldn't do this for some reason, return the original
7198 expression. */
7203 }
7204 \f
7205 /* X is a SET which contains an assignment of one object into
7206 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7207 or certain SUBREGS). If possible, convert it into a series of
7208 logical operations.
7210 We half-heartedly support variable positions, but do not at all
7211 support variable lengths. */
7213 static const_rtx
7215 {
7216 rtx inner;
7220 machine_mode compute_mode;
7222 /* Loop until we find something we can't simplify. */
7224 {
7227 {
7231 }
7234 {
7239 /* A constant position should stay within the width of INNER. */
7245 {
7253 /* If position is ADJUST - X, new position is X. */
7255 else
7256 {
7261 pos);
7262 }
7263 }
7264 }
7266 /* A SUBREG between two modes that occupy the same numbers of words
7267 can be done by moving the SUBREG to the source. */
7269 /* We need SUBREGs to compute nonzero_bits properly. */
7270 && nonzero_sign_valid
7275 {
7277 gen_lowpart
7281 }
7282 else
7290 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7292 {
7293 machine_mode imode;
7295 /* Don't do anything for vector or complex integral types. */
7299 /* Try to find an integral mode to pun with. */
7306 }
7308 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7312 /* Don't try to compute in too wide unsupported modes. */
7316 /* Now compute the equivalent expression. Make a copy of INNER
7317 for the SET_DEST in case it is a MEM into which we will substitute;
7318 we don't want shared RTL in that case. */
7320 compute_mode);
7324 compute_mode,
7326 compute_mode),
7327 inner);
7332 mask),
7333 pos);
7338 }
7341 }
7342 \f
7343 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7344 it is an RTX that represents the (variable) starting position; otherwise,
7345 POS is the (constant) starting bit position. Both are counted from the LSB.
7347 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7349 IN_DEST is nonzero if this is a reference in the destination of a SET.
7350 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7351 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7352 be used.
7354 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7355 ZERO_EXTRACT should be built even for bits starting at bit 0.
7357 MODE is the desired mode of the result (if IN_DEST == 0).
7359 The result is an RTX for the extraction or NULL_RTX if the target
7360 can't handle it. */
7362 static rtx
7366 {
7367 /* This mode describes the size of the storage area
7368 to fetch the overall value from. Within that, we
7369 ignore the POS lowest bits, etc. */
7371 machine_mode inner_mode;
7372 machine_mode wanted_inner_mode;
7379 HOST_WIDE_INT orig_pos;
7385 {
7386 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7387 consider just the QI as the memory to extract from.
7388 The subreg adds or removes high bits; its mode is
7389 irrelevant to the meaning of this extraction,
7390 since POS and LEN count from the lsb. */
7394 }
7399 {
7400 /* We're extracting the least significant bits of an rtx
7401 (ashift X (const_int C)), where LEN > C. Extract the
7402 least significant (LEN - C) bits of X, giving an rtx
7403 whose mode is MODE, then shift it left C times. */
7409 }
7415 /* See if this can be done without an extraction. We never can if the
7416 width of the field is not the same as that of some integer mode. For
7417 registers, we can only avoid the extraction if the position is at the
7418 low-order bit and this is either not in the destination or we have the
7419 appropriate STRICT_LOW_PART operation available.
7421 For MEM, we can avoid an extract if the field starts on an appropriate
7422 boundary and we can change the mode of the memory reference. */
7432 && (! in_dest
7436 && (pos
7439 /* We can't do this if we are widening INNER_MODE (it
7440 may not be aligned, for one thing). */
7446 {
7447 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7448 field. If the original and current mode are the same, we need not
7449 adjust the offset. Otherwise, we do if bytes big endian.
7451 If INNER is not a MEM, get a piece consisting of just the field
7452 of interest (in this case POS % BITS_PER_WORD must be 0). */
7455 {
7456 HOST_WIDE_INT offset;
7458 /* POS counts from lsb, but make OFFSET count in memory order. */
7461 else
7465 }
7467 {
7469 {
7470 /* We can't call gen_lowpart in a DEST since we
7471 always want a SUBREG (see below) and it would sometimes
7472 return a new hard register. */
7474 {
7489 /* Avoid creating invalid subregs, for example when
7490 simplifying (x>>32)&255. */
7495 }
7496 else
7498 }
7499 else
7501 }
7502 else
7504 len >= HOST_BITS_PER_WIDE_INT
7505 ? HOST_WIDE_INT_M1U
7508 /* If this extraction is going into the destination of a SET,
7509 make a STRICT_LOW_PART unless we made a MEM. */
7524 /* If we know that no extraneous bits are set, and that the high
7525 bit is not set, convert the extraction to the cheaper of
7526 sign and zero extension, that are equivalent in these cases. */
7532 {
7536 /* Prefer ZERO_EXTENSION, since it gives more information to
7537 backends. */
7542 }
7544 /* Otherwise, sign- or zero-extend unless we already are in the
7545 proper mode. */
7549 }
7551 /* Unless this is a COMPARE or we have a funny memory reference,
7552 don't do anything with zero-extending field extracts starting at
7553 the low-order bit since they are simple AND operations. */
7558 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7559 if the position is not a constant and the length is not 1. In all
7560 other cases, we would only be going outside our object in cases when
7561 an original shift would have been undefined. */
7570 /* If INNER is not from memory, we want it to have the mode of a register
7571 extraction pattern's structure operand, or word_mode if there is no
7572 such pattern. The same applies to extraction_mode and pos_mode
7573 and their respective operands.
7575 For memory, assume that the desired extraction_mode and pos_mode
7576 are the same as for a register operation, since at present we don't
7577 have named patterns for aligned memory structures. */
7581 {
7585 }
7587 /* Never narrow an object, since that might not be safe. */
7595 else
7596 {
7597 /* Be careful not to go beyond the extracted object and maintain the
7598 natural alignment of the memory. */
7602 {
7605 }
7606 }
7611 {
7612 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7613 BITS_BIG_ENDIAN style. If position is constant, compute new
7614 position. Otherwise, build subtraction.
7615 Note that POS is relative to the mode of the original argument.
7616 If it's a MEM we need to recompute POS relative to that.
7617 However, if we're extracting from (or inserting into) a register,
7618 we want to recompute POS relative to wanted_inner_mode. */
7625 else
7626 pos_rtx
7629 pos_rtx);
7630 /* POS may be less than 0 now, but we check for that below.
7631 Note that it can only be less than 0 if !MEM_P (inner). */
7632 }
7634 /* If INNER has a wider mode, and this is a constant extraction, try to
7635 make it smaller and adjust the byte to point to the byte containing
7636 the value. */
7639 && ! pos_rtx
7644 {
7647 /* The computations below will be correct if the machine is big
7648 endian in both bits and bytes or little endian in bits and bytes.
7649 If it is mixed, we must adjust. */
7651 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7652 adjust OFFSET to compensate. */
7657 /* We can now move to the desired byte. */
7668 }
7670 /* If INNER is not memory, get it into the proper mode. If we are changing
7671 its mode, POS must be a constant and smaller than the size of the new
7672 mode. */
7674 {
7675 /* On the LHS, don't create paradoxical subregs implicitely truncating
7676 the register unless TRULY_NOOP_TRUNCATION. */
7679 wanted_inner_mode))
7691 pos_rtx
7693 ? HOST_WIDE_INT_M1U
7697 }
7699 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7700 have to zero extend. Otherwise, we can just use a SUBREG. */
7703 {
7707 /* If we know that no extraneous bits are set, and that the high
7708 bit is not set, convert extraction to cheaper one - either
7709 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7710 cases. */
7718 {
7722 /* Prefer ZERO_EXTENSION, since it gives more information to
7723 backends. */
7727 }
7729 }
7731 /* Make POS_RTX unless we already have it and it is correct. If we don't
7732 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7733 be a CONST_INT. */
7740 /* Make the required operation. See if we can use existing rtx. */
7747 }
7748 \f
7749 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7750 with any other operations in X. Return X without that shift if so. */
7752 static rtx
7754 {
7757 rtx tem;
7760 {
7762 /* This is the shift itself. If it is wide enough, we will return
7763 either the value being shifted if the shift count is equal to
7764 COUNT or a shift for the difference. */
7778 /* If we can safely shift this constant and we find the inner shift,
7779 make a new operation. */
7784 {
7788 }
7793 }
7796 }
7797 \f
7798 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7799 level of the expression and MODE is its mode. IN_CODE is as for
7800 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7801 that should be used when recursing on operands of *X_PTR.
7803 There are two possible actions:
7805 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7806 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7808 - Return a new rtx, which the caller returns directly. */
7810 static rtx
7814 {
7822 rtx tem;
7826 {
7829 }
7831 /* Process depending on the code of this operation. If NEW is set
7832 nonzero, it will be returned. */
7835 {
7837 /* Convert shifts by constants into multiplications if inside
7838 an address. */
7842 {
7848 {
7851 }
7854 }
7863 {
7867 }
7870 {
7874 mode));
7876 }
7877 else
7878 {
7881 }
7891 {
7895 }
7898 {
7902 mode));
7904 }
7905 else
7906 {
7910 }
7913 /* If the second operand is not a constant, we can't do anything
7914 with it. */
7918 /* If the constant is a power of two minus one and the first operand
7919 is a logical right shift, make an extraction. */
7922 {
7926 }
7928 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7933 {
7942 {
7943 /* If we narrowed the mode when dropping the subreg, then
7944 we must zero-extend to keep the semantics of the AND. */
7946 ;
7950 else
7952 }
7954 /* If that didn't give anything, see if the AND simplifies on
7955 its own. */
7957 {
7961 }
7962 }
7963 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7969 {
7970 /* Apply the distributive law, and then try to make extractions. */
7977 }
7979 /* If we are have (and (rotate X C) M) and C is larger than the number
7980 of bits in M, this is an extraction. */
7986 {
7992 }
7994 /* On machines without logical shifts, if the operand of the AND is
7995 a logical shift and our mask turns off all the propagated sign
7996 bits, we can replace the logical shift with an arithmetic shift. */
8004 {
8011 make_compound_operation
8014 }
8016 /* If the constant is one less than a power of two, this might be
8017 representable by an extraction even if no shift is present.
8018 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8019 we are in a COMPARE. */
8023 next_code),
8026 /* If we are in a comparison and this is an AND with a power of two,
8027 convert this into the appropriate bit extract. */
8033 next_code),
8036 /* If the one operand is a paradoxical subreg of a register or memory and
8037 the constant (limited to the smaller mode) has only zero bits where
8038 the sub expression has known zero bits, this can be expressed as
8039 a zero_extend. */
8041 {
8042 rtx sub;
8048 {
8052 /* original AND constant with all the known zero bits set */
8055 {
8060 }
8061 }
8062 }
8067 /* If the sign bit is known to be zero, replace this with an
8068 arithmetic shift. */
8073 {
8076 next_code),
8079 }
8081 /* fall through */
8087 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8088 this is a SIGN_EXTRACT. */
8095 {
8102 }
8104 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8105 If so, try to merge the shifts into a SIGN_EXTEND. We could
8106 also do this for some cases of SIGN_EXTRACT, but it doesn't
8107 seem worth the effort; the case checked for occurs on Alpha. */
8124 /* Call ourselves recursively on the inner expression. If we are
8125 narrowing the object and it has a different RTL code from
8126 what it originally did, do this SUBREG as a force_to_mode. */
8127 {
8131 /* If the SUBREG is masking of a logical right shift,
8132 make an extraction. */
8139 {
8148 }
8150 /* If in_code is COMPARE, it isn't always safe to pass it through
8151 to the recursive make_compound_operation call. */
8155 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8156 is (const_int 0), rather than
8157 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8167 simplified
8175 {
8176 rtx newer
8179 /* If we have something other than a SUBREG, we might have
8180 done an expansion, so rerun ourselves. */
8184 /* force_to_mode can expand compounds. If it just re-expanded the
8185 compound, use gen_lowpart to convert to the desired mode. */
8187 /* Likewise if it re-expanded the compound only partially.
8188 This happens for SUBREG of ZERO_EXTRACT if they extract
8189 the same number of bits. */
8198 }
8202 }
8207 }
8213 }
8215 /* Look at the expression rooted at X. Look for expressions
8216 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8217 Form these expressions.
8219 Return the new rtx, usually just X.
8221 Also, for machines like the VAX that don't have logical shift insns,
8222 try to convert logical to arithmetic shift operations in cases where
8223 they are equivalent. This undoes the canonicalizations to logical
8224 shifts done elsewhere.
8226 We try, as much as possible, to re-use rtl expressions to save memory.
8228 IN_CODE says what kind of expression we are processing. Normally, it is
8229 SET. In a memory address it is MEM. When processing the arguments of
8230 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8231 precisely it is an equality comparison against zero. */
8233 rtx
8235 {
8242 /* Select the code to be used in recursive calls. Once we are inside an
8243 address, we stay there. If we have a comparison, set to COMPARE,
8244 but once inside, go back to our default of SET. */
8252 {
8258 }
8260 /* Now recursively process each operand of this operation. We need to
8261 handle ZERO_EXTEND specially so that we don't lose track of the
8262 inner mode. */
8264 {
8272 }
8277 {
8280 }
8283 {
8286 }
8290 }
8291 \f
8292 /* Given M see if it is a value that would select a field of bits
8293 within an item, but not the entire word. Return -1 if not.
8294 Otherwise, return the starting position of the field, where 0 is the
8295 low-order bit.
8297 *PLEN is set to the length of the field. */
8299 static int
8301 {
8302 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8307 /* Now shift off the low-order zero bits and see if we have a
8308 power of two minus 1. */
8316 }
8317 \f
8318 /* If X refers to a register that equals REG in value, replace these
8319 references with REG. */
8320 static rtx
8322 {
8330 {
8363 /* FALLTHRU */
8367 {
8371 else
8373 }
8375 /* fall through */
8382 {
8385 {
8387 {
8390 }
8392 }
8393 }
8395 {
8398 {
8401 {
8403 {
8406 }
8408 }
8409 }
8410 }
8413 }
8416 }
8418 /* Return X converted to MODE. If the value is already truncated to
8419 MODE we can just return a subreg even though in the general case we
8420 would need an explicit truncation. */
8422 static rtx
8424 {
8429 {
8430 /* Bit-cast X into an integer mode. */
8435 }
8438 }
8440 /* See if X can be simplified knowing that we will only refer to it in
8441 MODE and will only refer to those bits that are nonzero in MASK.
8442 If other bits are being computed or if masking operations are done
8443 that select a superset of the bits in MASK, they can sometimes be
8444 ignored.
8446 Return a possibly simplified expression, but always convert X to
8447 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8449 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8450 are all off in X. This is used when X will be complemented, by either
8451 NOT, NEG, or XOR. */
8453 static rtx
8456 {
8459 machine_mode op_mode;
8463 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8464 code below will do the wrong thing since the mode of such an
8465 expression is VOIDmode.
8467 Also do nothing if X is a CLOBBER; this can happen if X was
8468 the return value from a call to gen_lowpart. */
8472 /* We want to perform the operation in its present mode unless we know
8473 that the operation is valid in MODE, in which case we do the operation
8474 in MODE. */
8479 /* It is not valid to do a right-shift in a narrower mode
8480 than the one it came in with. */
8485 /* Truncate MASK to fit OP_MODE. */
8489 /* When we have an arithmetic operation, or a shift whose count we
8490 do not know, we need to assume that all bits up to the highest-order
8491 bit in MASK will be needed. This is how we form such a mask. */
8494 else
8498 /* Determine what bits of X are guaranteed to be (non)zero. */
8501 /* If none of the bits in X are needed, return a zero. */
8505 /* If X is a CONST_INT, return a new one. Do this here since the
8506 test below will fail. */
8508 {
8511 else
8512 {
8515 }
8516 }
8518 /* If X is narrower than MODE and we want all the bits in X's mode, just
8519 get X in the proper mode. */
8524 /* We can ignore the effect of a SUBREG if it narrows the mode or
8525 if the constant masks to zero all the bits the mode doesn't have. */
8535 /* The arithmetic simplifications here only work for scalar integer modes. */
8540 {
8542 /* If X is a (clobber (const_int)), return it since we know we are
8543 generating something that won't match. */
8556 /* Similarly for a truncate. */
8560 /* If this is an AND with a constant, convert it into an AND
8561 whose constant is the AND of that constant with MASK. If it
8562 remains an AND of MASK, delete it since it is redundant. */
8565 {
8569 /* If X is still an AND, see if it is an AND with a mask that
8570 is just some low-order bits. If so, and it is MASK, we don't
8571 need it. */
8578 /* If it remains an AND, try making another AND with the bits
8579 in the mode mask that aren't in MASK turned on. If the
8580 constant in the AND is wide enough, this might make a
8581 cheaper constant. */
8586 {
8587 unsigned HOST_WIDE_INT cval
8590 rtx y;
8597 }
8600 }
8605 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8606 low-order bits (as in an alignment operation) and FOO is already
8607 aligned to that boundary, mask C1 to that boundary as well.
8608 This may eliminate that PLUS and, later, the AND. */
8610 {
8614 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8615 number, sign extend it. */
8628 }
8630 /* fall through */
8633 /* Substituting into the operands of a widening MULT is not likely to
8634 create RTL matching a machine insn. */
8644 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8645 most significant bit in MASK since carries from those bits will
8646 affect the bits we are interested in. */
8651 /* If X is (minus C Y) where C's least set bit is larger than any bit
8652 in the mask, then we may replace with (neg Y). */
8655 {
8659 }
8661 /* Similarly, if C contains every bit in the fuller_mask, then we may
8662 replace with (not Y). */
8665 {
8669 }
8676 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8677 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8678 operation which may be a bitfield extraction. Ensure that the
8679 constant we form is not wider than the mode of X. */
8691 {
8700 }
8702 binop:
8703 /* For most binary operations, just propagate into the operation and
8704 change the mode if we have an operation of that mode. */
8709 /* If we ended up truncating both operands, truncate the result of the
8710 operation instead. */
8713 {
8716 }
8726 /* For left shifts, do the same, but just for the first operand.
8727 However, we cannot do anything with shifts where we cannot
8728 guarantee that the counts are smaller than the size of the mode
8729 because such a count will have a different meaning in a
8730 wider mode. */
8740 /* If the shift count is a constant and we can do arithmetic in
8741 the mode of the shift, refine which bits we need. Otherwise, use the
8742 conservative form of the mask. */
8748 else
8760 /* Here we can only do something if the shift count is a constant,
8761 this shift constant is valid for the host, and we can do arithmetic
8762 in OP_MODE. */
8768 {
8772 /* Select the mask of the bits we need for the shift operand. */
8775 /* We can only change the mode of the shift if we can do arithmetic
8776 in the mode of the shift and INNER_MASK is no wider than the
8777 width of X's mode. */
8785 }
8787 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8788 shift and AND produces only copies of the sign bit (C2 is one less
8789 than a power of two), we can do this with just a shift. */
8793 /* The shift puts one of the sign bit copies in the least significant
8794 bit. */
8799 /* Number of bits left after the shift must be more than the mask
8800 needs. */
8803 /* Must be more sign bit copies than the mask needs. */
8813 /* If we are just looking for the sign bit, we don't need this shift at
8814 all, even if it has a variable count. */
8818 /* If this is a shift by a constant, get a mask that contains those bits
8819 that are not copies of the sign bit. We then have two cases: If
8820 MASK only includes those bits, this can be a logical shift, which may
8821 allow simplifications. If MASK is a single-bit field not within
8822 those bits, we are requesting a copy of the sign bit and hence can
8823 shift the sign bit to the appropriate location. */
8827 {
8830 /* If the considered data is wider than HOST_WIDE_INT, we can't
8831 represent a mask for all its bits in a single scalar.
8832 But we only care about the lower bits, so calculate these. */
8835 {
8838 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8839 is the number of bits a full-width mask would have set.
8840 We need only shift if these are fewer than nonzero can
8841 hold. If not, we must keep all bits set in nonzero. */
8846 + HOST_BITS_PER_WIDE_INT
8848 }
8849 else
8850 {
8853 }
8856 {
8861 }
8864 {
8865 x = simplify_shift_const
8871 }
8872 }
8874 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8875 even if the shift count isn't a constant. */
8880 shiftrt:
8882 /* If this is a zero- or sign-extension operation that just affects bits
8883 we don't care about, remove it. Be sure the call above returned
8884 something that is still a shift. */
8894 next_select);
8900 /* If the shift count is constant and we can do computations
8901 in the mode of X, compute where the bits we care about are.
8902 Otherwise, we can't do anything. Don't change the mode of
8903 the shift or propagate MODE into the shift, though. */
8906 {
8916 }
8920 /* If we just want the low-order bit, the NEG isn't needed since it
8921 won't change the low-order bit. */
8925 /* We need any bits less significant than the most significant bit in
8926 MASK since carries from those bits will affect the bits we are
8927 interested in. */
8932 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8933 same as the XOR case above. Ensure that the constant we form is not
8934 wider than the mode of X. */
8942 {
8951 }
8953 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8954 use the full mask inside the NOT. */
8957 unop:
8960 next_select));
8966 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8967 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8968 which is equal to STORE_FLAG_VALUE. */
8980 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8981 written in a narrower mode. We play it safe and do not do so. */
8997 }
8999 /* Ensure we return a value of the proper mode. */
9001 }
9002 \f
9003 /* Return nonzero if X is an expression that has one of two values depending on
9004 whether some other value is zero or nonzero. In that case, we return the
9005 value that is being tested, *PTRUE is set to the value if the rtx being
9006 returned has a nonzero value, and *PFALSE is set to the other alternative.
9008 If we return zero, we set *PTRUE and *PFALSE to X. */
9010 static rtx
9012 {
9018 /* If we are comparing a value against zero, we are done. */
9021 {
9025 }
9027 /* If this is a unary operation whose operand has one of two values, apply
9028 our opcode to compute those values. */
9031 {
9036 }
9038 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9039 make can't possibly match and would suppress other optimizations. */
9041 ;
9043 /* If this is a binary operation, see if either side has only one of two
9044 values. If either one does or if both do and they are conditional on
9045 the same value, compute the new true and false values. */
9047 {
9053 {
9054 /* If if_then_else_cond returned zero, then true/false are the
9055 same rtl. We must copy one of them to prevent invalid rtl
9056 sharing. */
9063 {
9068 }
9069 else
9070 {
9073 }
9076 }
9078 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9079 operands is zero when the other is nonzero, and vice-versa,
9080 and STORE_FLAG_VALUE is 1 or -1. */
9086 {
9103 {
9110 const_true_rtx);
9112 }
9113 }
9115 /* Similarly for MULT, AND and UMIN, except that for these the result
9116 is always zero. */
9120 {
9134 {
9137 }
9138 }
9139 }
9142 {
9143 /* If we have IF_THEN_ELSE already, extract the condition and
9144 canonicalize it if it is NE or EQ. */
9150 {
9153 }
9154 else
9156 }
9158 /* If X is a SUBREG, we can narrow both the true and false values
9159 if the inner expression, if there is a condition. */
9163 {
9169 {
9173 }
9174 }
9176 /* If X is a constant, this isn't special and will cause confusions
9177 if we treat it as such. Likewise if it is equivalent to a constant. */
9180 ;
9182 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9183 will be least confusing to the rest of the compiler. */
9185 {
9188 }
9190 /* If X is known to be either 0 or -1, those are the true and
9191 false values when testing X. */
9195 {
9198 }
9200 /* Likewise for 0 or a single bit. */
9203 {
9206 }
9208 /* Otherwise fail; show no condition with true and false values the same. */
9211 }
9212 \f
9213 /* Return the value of expression X given the fact that condition COND
9214 is known to be true when applied to REG as its first operand and VAL
9215 as its second. X is known to not be shared and so can be modified in
9216 place.
9218 We only handle the simplest cases, and specifically those cases that
9219 arise with IF_THEN_ELSE expressions. */
9221 static rtx
9223 {
9231 /* If either operand of the condition is a floating point value,
9232 then we have to avoid collapsing an EQ comparison. */
9242 /* If X is (abs REG) and we know something about REG's relationship
9243 with zero, we may be able to simplify this. */
9247 {
9256 }
9258 /* The only other cases we handle are MIN, MAX, and comparisons if the
9259 operands are the same as REG and VAL. */
9262 {
9264 {
9267 }
9270 {
9272 {
9280 else
9282 }
9285 {
9288 /* Do not reverse the condition when it is NE or EQ.
9289 This is because we cannot conclude anything about
9290 the value of 'SMAX (x, y)' when x is not equal to y,
9291 but we can when x equals y. */
9297 {
9308 }
9309 }
9310 }
9311 }
9313 {
9318 {
9319 /* We must simplify subreg here, before we lose track of the
9320 original inner_mode. */
9325 else
9327 }
9330 }
9331 /* We don't have to handle SIGN_EXTEND here, because even in the
9332 case of replacing something with a modeless CONST_INT, a
9333 CONST_INT is already (supposed to be) a valid sign extension for
9334 its narrower mode, which implies it's already properly
9335 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9336 story is different. */
9338 {
9343 {
9344 /* We must simplify the zero_extend here, before we lose
9345 track of the original inner_mode. */
9350 else
9352 }
9355 }
9359 {
9366 }
9369 }
9370 \f
9371 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9372 assignment as a field assignment. */
9374 static int
9376 {
9378 {
9383 /* For big endian, adjust the memory offset. */
9388 else
9390 }
9398 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9399 Note that all SUBREGs of MEM are paradoxical; otherwise they
9400 would have been rewritten. */
9413 /* We used to see if get_last_value of X and Y were the same but that's
9414 not correct. In one direction, we'll cause the assignment to have
9415 the wrong destination and in the case, we'll import a register into this
9416 insn that might have already have been dead. So fail if none of the
9417 above cases are true. */
9419 }
9420 \f
9421 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9422 Return that assignment if so.
9424 We only handle the most common cases. */
9426 static rtx
9428 {
9431 rtx assign;
9433 HOST_WIDE_INT c1;
9434 HOST_WIDE_INT pos;
9436 rtx other;
9437 machine_mode mode;
9439 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9440 a clear of a one-bit field. We will have changed it to
9441 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9442 for a SUBREG. */
9448 {
9454 }
9464 {
9471 }
9473 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9474 one-bit field. */
9478 {
9484 }
9486 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9487 SRC is an AND with all bits of that field set, then we can discard
9488 the AND. */
9493 {
9500 else
9503 /* Complete overlap. We can remove the source AND. */
9507 /* Partial overlap. We can reduce the source AND. */
9509 {
9514 }
9515 }
9517 /* The other case we handle is assignments into a constant-position
9518 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9519 a mask that has all one bits except for a group of zero bits and
9520 OTHER is known to have zeros where C1 has ones, this is such an
9521 assignment. Compute the position and length from C1. Shift OTHER
9522 to the appropriate position, force it to the required mode, and
9523 make the extraction. Check for the AND in both operands. */
9525 /* One or more SUBREGs might obscure the constant-position field
9526 assignment. The first one we are likely to encounter is an outer
9527 narrowing SUBREG, which we can just strip for the purposes of
9528 identifying the constant-field assignment. */
9542 /* The second SUBREG that might get in the way is a paradoxical
9543 SUBREG around the first operand of the AND. We want to
9544 pretend the operand is as wide as the destination here. We
9545 do this by adjusting the MEM to wider mode for the sole
9546 purpose of the call to rtx_equal_for_field_assignment_p. Also
9547 note this trick only works for MEMs. */
9559 /* The second SUBREG that might get in the way is a paradoxical
9560 SUBREG around the first operand of the AND. We want to
9561 pretend the operand is as wide as the destination here. We
9562 do this by adjusting the MEM to wider mode for the sole
9563 purpose of the call to rtx_equal_for_field_assignment_p. Also
9564 note this trick only works for MEMs. */
9572 else
9585 /* The mode to use for the source is the mode of the assignment, or of
9586 what is inside a possible STRICT_LOW_PART. */
9590 /* Shift OTHER right POS places and make it the source, restricting it
9591 to the proper length and mode. */
9596 dest);
9599 ? HOST_WIDE_INT_M1U
9603 /* If SRC is masked by an AND that does not make a difference in
9604 the value being stored, strip it. */
9615 }
9616 \f
9617 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9618 if so. */
9620 static rtx
9622 {
9626 rtx tem;
9628 /* Distributivity is not true for floating point as it can change the
9629 value. So we don't do it unless -funsafe-math-optimizations. */
9634 /* The outer operation can only be one of the following: */
9642 /* If either operand is a primitive we can't do anything, so get out
9643 fast. */
9653 /* See if the inner and outer operations distribute. */
9655 {
9660 /* These all distribute except over PLUS. */
9671 /* This is also a multiply, so it distributes over everything. */
9674 /* This used to handle SUBREG, but this turned out to be counter-
9675 productive, since (subreg (op ...)) usually is not handled by
9676 insn patterns, and this "optimization" therefore transformed
9677 recognizable patterns into unrecognizable ones. Therefore the
9678 SUBREG case was removed from here.
9680 It is possible that distributing SUBREG over arithmetic operations
9681 leads to an intermediate result than can then be optimized further,
9682 e.g. by moving the outer SUBREG to the other side of a SET as done
9683 in simplify_set. This seems to have been the original intent of
9684 handling SUBREGs here.
9686 However, with current GCC this does not appear to actually happen,
9687 at least on major platforms. If some case is found where removing
9688 the SUBREG case here prevents follow-on optimizations, distributing
9689 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9693 }
9695 /* Set LHS and RHS to the inner operands (A and B in the example
9696 above) and set OTHER to the common operand (C in the example).
9697 There is only one way to do this unless the inner operation is
9698 commutative. */
9710 else
9713 /* Form the new inner operation, seeing if it simplifies first. */
9716 /* There is one exception to the general way of distributing:
9717 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9719 {
9722 }
9724 /* We may be able to continuing distributing the result, so call
9725 ourselves recursively on the inner operation before forming the
9726 outer operation, which we return. */
9729 }
9731 /* See if X is of the form (* (+ A B) C), and if so convert to
9732 (+ (* A C) (* B C)) and try to simplify.
9734 Most of the time, this results in no change. However, if some of
9735 the operands are the same or inverses of each other, simplifications
9736 will result.
9738 For example, (and (ior A B) (not B)) can occur as the result of
9739 expanding a bit field assignment. When we apply the distributive
9740 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9741 which then simplifies to (and (A (not B))).
9743 Note that no checks happen on the validity of applying the inverse
9744 distributive law. This is pointless since we can do it in the
9745 few places where this routine is called.
9747 N is the index of the term that is decomposed (the arithmetic operation,
9748 i.e. (+ A B) in the first example above). !N is the index of the term that
9749 is distributed, i.e. of C in the first example above. */
9750 static rtx
9752 {
9753 machine_mode mode;
9757 /* Distributivity is not true for floating point as it can change the
9758 value. So we don't do it unless -funsafe-math-optimizations. */
9775 /* Special case (and (xor B C) (not A)), which is equivalent to
9776 (xor (ior A B) (ior A C)) */
9778 {
9781 }
9784 {
9785 /* Distribute the second term. */
9788 }
9789 else
9790 {
9791 /* Distribute the first term. */
9794 }
9804 }
9805 \f
9806 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9807 in MODE. Return an equivalent form, if different from (and VAROP
9808 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9810 static rtx
9813 {
9816 rtx orig_varop;
9824 /* Simplify VAROP knowing that we will be only looking at some of the
9825 bits in it.
9827 Note by passing in CONSTOP, we guarantee that the bits not set in
9828 CONSTOP are not significant and will never be examined. We must
9829 ensure that is the case by explicitly masking out those bits
9830 before returning. */
9833 /* If VAROP is a CLOBBER, we will fail so return it. */
9837 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9838 to VAROP and return the new constant. */
9842 /* See what bits may be nonzero in VAROP. Unlike the general case of
9843 a call to nonzero_bits, here we don't care about bits outside
9844 MODE. */
9848 /* Turn off all bits in the constant that are known to already be zero.
9849 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9850 which is tested below. */
9854 /* If we don't have any bits left, return zero. */
9858 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9859 a power of two, we can replace this with an ASHIFT. */
9864 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9865 or XOR, then try to apply the distributive law. This may eliminate
9866 operations if either branch can be simplified because of the AND.
9867 It may also make some cases more complex, but those cases probably
9868 won't match a pattern either with or without this. */
9871 return
9872 gen_lowpart
9874 apply_distributive_law
9879 constop),
9883 constop))));
9885 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9886 the AND and see if one of the operands simplifies to zero. If so, we
9887 may eliminate it. */
9891 {
9900 }
9902 /* Make a SUBREG if necessary. If we can't make it, fail. */
9907 /* If we are only masking insignificant bits, return VAROP. */
9914 /* Otherwise, return an AND. */
9916 }
9919 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9920 in MODE.
9922 Return an equivalent form, if different from X. Otherwise, return X. If
9923 X is zero, we are to always construct the equivalent form. */
9925 static rtx
9928 {
9939 }
9940 \f
9941 /* Given a REG, X, compute which bits in X can be nonzero.
9942 We don't care about bits outside of those defined in MODE.
9944 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9945 a shift, AND, or zero_extract, we can do better. */
9947 static rtx
9949 const_rtx known_x ATTRIBUTE_UNUSED,
9950 machine_mode known_mode ATTRIBUTE_UNUSED,
9953 {
9954 rtx tem;
9957 /* If X is a register whose nonzero bits value is current, use it.
9958 Otherwise, if X is a register whose value we can find, use that
9959 value. Otherwise, use the previously-computed global nonzero bits
9960 for this register. */
9974 && !REGNO_REG_SET_P
9977 {
9978 /* Note that, even if the precision of last_set_mode is lower than that
9979 of mode, record_value_for_reg invoked nonzero_bits on the register
9980 with nonzero_bits_mode (because last_set_mode is necessarily integral
9981 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9982 are all valid, hence in mode too since nonzero_bits_mode is defined
9983 to the largest HWI_COMPUTABLE_MODE_P mode. */
9986 }
9990 {
9996 }
9999 {
10003 /* We don't know anything about the upper bits. */
10007 }
10010 }
10012 /* Return the number of bits at the high-order end of X that are known to
10013 be equal to the sign bit. X will be used in mode MODE; if MODE is
10014 VOIDmode, X will be used in its own mode. The returned value will always
10015 be between 1 and the number of bits in MODE. */
10017 static rtx
10019 const_rtx known_x ATTRIBUTE_UNUSED,
10020 machine_mode known_mode
10021 ATTRIBUTE_UNUSED,
10024 {
10025 rtx tem;
10038 && !REGNO_REG_SET_P
10041 {
10044 }
10055 }
10056 \f
10057 /* Return the number of "extended" bits there are in X, when interpreted
10058 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10059 unsigned quantities, this is the number of high-order zero bits.
10060 For signed quantities, this is the number of copies of the sign bit
10061 minus 1. In both case, this function returns the number of "spare"
10062 bits. For example, if two quantities for which this function returns
10063 at least 1 are added, the addition is known not to overflow.
10065 This function will always return 0 unless called during combine, which
10066 implies that it must be called from a define_split. */
10068 unsigned int
10070 {
10080 }
10082 /* This function is called from `simplify_shift_const' to merge two
10083 outer operations. Specifically, we have already found that we need
10084 to perform operation *POP0 with constant *PCONST0 at the outermost
10085 position. We would now like to also perform OP1 with constant CONST1
10086 (with *POP0 being done last).
10088 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10089 the resulting operation. *PCOMP_P is set to 1 if we would need to
10090 complement the innermost operand, otherwise it is unchanged.
10092 MODE is the mode in which the operation will be done. No bits outside
10093 the width of this mode matter. It is assumed that the width of this mode
10094 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10096 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10097 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10098 result is simply *PCONST0.
10100 If the resulting operation cannot be expressed as one operation, we
10101 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10103 static int
10104 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10105 {
10112 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10116 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10117 if OP0 is SET. */
10126 {
10128 {
10146 }
10147 }
10149 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10153 /* If the two constants aren't the same, we can't do anything. The
10154 remaining six cases can all be done. */
10158 else
10160 {
10163 /* (a & b) | b == b */
10166 /* (a ^ b) | b == a | b */
10167 {;}
10172 /* (a & b) ^ b == (~a) & b */
10175 /* (a | b) ^ b == a & ~b */
10181 /* (a | b) & b == b */
10184 /* (a ^ b) & b) == (~a) & b */
10189 }
10191 /* Check for NO-OP cases. */
10204 /* ??? Slightly redundant with the above mask, but not entirely.
10205 Moving this above means we'd have to sign-extend the mode mask
10206 for the final test. */
10211 }
10212 \f
10213 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10214 the shift in. The original shift operation CODE is performed on OP in
10215 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10216 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10217 result of the shift is subject to operation OUTER_CODE with operand
10218 OUTER_CONST. */
10220 static machine_mode
10224 {
10229 /* In general we can't perform in wider mode for right shift and rotate. */
10231 {
10233 /* We can still widen if the bits brought in from the left are identical
10234 to the sign bit of ORIG_MODE. */
10242 /* Similarly here but with zero bits. */
10247 /* We can also widen if the bits brought in will be masked off. This
10248 operation is performed in ORIG_MODE. */
10250 {
10256 }
10257 /* fall through */
10267 }
10268 }
10270 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10271 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10272 if we cannot simplify it. Otherwise, return a simplified value.
10274 The shift is normally computed in the widest mode we find in VAROP, as
10275 long as it isn't a different number of words than RESULT_MODE. Exceptions
10276 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10278 static rtx
10281 {
10287 unsigned int mode_words
10289 /* We form (outer_op (code varop count) (outer_const)). */
10295 /* Make sure and truncate the "natural" shift on the way in. We don't
10296 want to do this inside the loop as it makes it more difficult to
10297 combine shifts. */
10301 /* If we were given an invalid count, don't do anything except exactly
10302 what was requested. */
10309 /* Unless one of the branches of the `if' in this loop does a `continue',
10310 we will `break' the loop after the `if'. */
10313 {
10314 /* If we have an operand of (clobber (const_int 0)), fail. */
10318 /* Convert ROTATERT to ROTATE. */
10320 {
10324 }
10330 /* Handle cases where the count is greater than the size of the mode
10331 minus 1. For ASHIFT, use the size minus one as the count (this can
10332 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10333 take the count modulo the size. For other shifts, the result is
10334 zero.
10336 Since these shifts are being produced by the compiler by combining
10337 multiple operations, each of which are defined, we know what the
10338 result is supposed to be. */
10341 {
10346 else
10347 {
10348 /* We can't simply return zero because there may be an
10349 outer op. */
10353 }
10354 }
10356 /* If we discovered we had to complement VAROP, leave. Making a NOT
10357 here would cause an infinite loop. */
10362 {
10363 /* An arithmetic right shift of a quantity known to be -1 or 0
10364 is a no-op. */
10368 {
10371 }
10373 /* If we are doing an arithmetic right shift and discarding all but
10374 the sign bit copies, this is equivalent to doing a shift by the
10375 bitsize minus one. Convert it into that shift because it will
10376 often allow other simplifications. */
10383 /* We simplify the tests below and elsewhere by converting
10384 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10385 `make_compound_operation' will convert it to an ASHIFTRT for
10386 those machines (such as VAX) that don't have an LSHIFTRT. */
10391 shift_unit_mode)))
10403 }
10406 {
10413 {
10416 }
10420 /* The following rules apply only to scalars. */
10424 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10425 minus the width of a smaller mode, we can do this with a
10426 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10433 {
10442 }
10446 /* The following rules apply only to scalars. */
10450 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10451 the same number of words as what we've seen so far. Then store
10452 the widest mode in MODE. */
10458 == mode_words
10461 {
10466 }
10470 /* Some machines use MULT instead of ASHIFT because MULT
10471 is cheaper. But it is still better on those machines to
10472 merge two shifts into one. */
10475 {
10476 varop
10482 }
10486 /* Similar, for when divides are cheaper. */
10489 {
10490 varop
10496 }
10500 /* If we are extracting just the sign bit of an arithmetic
10501 right shift, that shift is not needed. However, the sign
10502 bit of a wider mode may be different from what would be
10503 interpreted as the sign bit in a narrower mode, so, if
10504 the result is narrower, don't discard the shift. */
10509 {
10512 }
10514 /* fall through */
10519 /* The following rules apply only to scalars. */
10523 /* Here we have two nested shifts. The result is usually the
10524 AND of a new shift with a mask. We compute the result below. */
10530 {
10534 rtx mask_rtx;
10536 /* We have one common special case. We can't do any merging if
10537 the inner code is an ASHIFTRT of a smaller mode. However, if
10538 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10539 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10540 we can convert it to
10541 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10542 This simplifies certain SIGN_EXTEND operations. */
10546 {
10547 /* C3 has the low-order C1 bits zero. */
10559 }
10561 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10562 than C1 high-order bits equal to the sign bit, we can convert
10563 this to either an ASHIFT or an ASHIFTRT depending on the
10564 two counts.
10566 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10572 {
10576 {
10579 }
10582 }
10584 /* There are some cases we can't do. If CODE is ASHIFTRT,
10585 we can only do this if FIRST_CODE is also ASHIFTRT.
10587 We can't do the case when CODE is ROTATE and FIRST_CODE is
10588 ASHIFTRT.
10590 If the mode of this shift is not the mode of the outer shift,
10591 we can't do this if either shift is a right shift or ROTATE.
10593 Finally, we can't do any of these if the mode is too wide
10594 unless the codes are the same.
10596 Handle the case where the shift codes are the same
10597 first. */
10600 {
10609 }
10620 /* To compute the mask to apply after the shift, shift the
10621 nonzero bits of the inner shift the same way the
10622 outer shift will. */
10625 result_mode);
10627 mask_rtx
10631 /* Give up if we can't compute an outer operation to use. */
10639 /* If the shifts are in the same direction, we add the
10640 counts. Otherwise, we subtract them. */
10644 else
10647 /* If COUNT is positive, the new shift is usually CODE,
10648 except for the two exceptions below, in which case it is
10649 FIRST_CODE. If the count is negative, FIRST_CODE should
10650 always be used */
10660 }
10662 /* If we have (A << B << C) for any shift, we can convert this to
10663 (A << C << B). This wins if A is a constant. Only try this if
10664 B is not a constant. */
10669 {
10670 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10671 sure the result will be masked. See PR70222. */
10679 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10680 up outer sign extension (often left and right shift) is
10681 hardly more efficient than the original. See PR70429. */
10691 }
10695 /* The following rules apply only to scalars. */
10699 /* Make this fit the case below. */
10706 /* The following rules apply only to scalars. */
10710 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10711 with C the size of VAROP - 1 and the shift is logical if
10712 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10713 we have an (le X 0) operation. If we have an arithmetic shift
10714 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10715 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10723 {
10726 const0_rtx);
10732 }
10734 /* If we have (shift (logical)), move the logical to the outside
10735 to allow it to possibly combine with another logical and the
10736 shift to combine with another shift. This also canonicalizes to
10737 what a ZERO_EXTRACT looks like. Also, some machines have
10738 (and (shift)) insns. */
10741 /* We can't do this if we have (ashiftrt (xor)) and the
10742 constant has its sign bit set in shift_mode with shift_mode
10743 wider than result_mode. */
10747 shift_mode))
10755 {
10758 }
10760 /* If we can't do that, try to simplify the shift in each arm of the
10761 logical expression, make a new logical expression, and apply
10762 the inverse distributive law. This also can't be done for
10763 (ashiftrt (xor)) where we've widened the shift and the constant
10764 changes the sign bit. */
10769 shift_mode)))
10770 {
10782 }
10786 /* The following rules apply only to scalars. */
10790 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10791 says that the sign bit can be tested, FOO has mode MODE, C is
10792 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10793 that may be nonzero. */
10803 {
10807 }
10811 /* The following rules apply only to scalars. */
10815 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10816 than the number of bits in the mode is equivalent to A. */
10820 {
10824 }
10826 /* NEG commutes with ASHIFT since it is multiplication. Move the
10827 NEG outside to allow shifts to combine. */
10831 {
10834 }
10838 /* The following rules apply only to scalars. */
10842 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10843 is one less than the number of bits in the mode is
10844 equivalent to (xor A 1). */
10851 {
10855 }
10857 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10858 that might be nonzero in BAR are those being shifted out and those
10859 bits are known zero in FOO, we can replace the PLUS with FOO.
10860 Similarly in the other operand order. This code occurs when
10861 we are computing the size of a variable-size array. */
10868 {
10871 }
10879 result_mode)))
10880 {
10883 }
10885 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10895 {
10898 }
10900 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10901 signbit', and attempt to change the PLUS to an XOR and move it to
10902 the outer operation as is done above in the AND/IOR/XOR case
10903 leg for shift(logical). See details in logical handling above
10904 for reasoning in doing so. */
10915 {
10918 }
10923 /* The following rules apply only to scalars. */
10927 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10928 with C the size of VAROP - 1 and the shift is logical if
10929 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10930 we have a (gt X 0) operation. If the shift is arithmetic with
10931 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10932 we have a (neg (gt X 0)) operation. */
10941 {
10944 const0_rtx);
10950 }
10954 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10955 if the truncate does not affect the value. */
10962 {
10965 varop_inner
10968 GEN_INT
10973 }
10978 }
10981 }
10986 /* We have now finished analyzing the shift. The result should be
10987 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10988 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10989 to the result of the shift. OUTER_CONST is the relevant constant,
10990 but we must turn off all bits turned off in the shift. */
10998 /* Make a SUBREG if necessary. If we can't make it, fail. */
11003 /* If we have an outer operation and we just made a shift, it is
11004 possible that we could have simplified the shift were it not
11005 for the outer operation. So try to do the simplification
11006 recursively. */
11010 else
11016 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11017 turn off all the bits that the shift would have turned off. */
11022 /* Do the remainder of the processing in RESULT_MODE. */
11025 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11026 operation. */
11031 {
11039 {
11040 /* This means that we have determined that the result is
11041 equivalent to a constant. This should be rare. */
11044 }
11047 else
11050 }
11053 }
11055 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11056 The result of the shift is RESULT_MODE. If we cannot simplify it,
11057 return X or, if it is NULL, synthesize the expression with
11058 simplify_gen_binary. Otherwise, return a simplified value.
11060 The shift is normally computed in the widest mode we find in VAROP, as
11061 long as it isn't a different number of words than RESULT_MODE. Exceptions
11062 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11064 static rtx
11067 {
11077 }
11079 \f
11080 /* A subroutine of recog_for_combine. See there for arguments and
11081 return value. */
11083 static int
11085 {
11087 rtx pat_without_clobbers;
11095 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11096 we use to indicate that something didn't match. If we find such a
11097 thing, force rejection. */
11111 {
11114 else
11117 }
11119 /* If it isn't, there is the possibility that we previously had an insn
11120 that clobbered some register as a side effect, but the combined
11121 insn doesn't need to do that. So try once more without the clobbers
11122 unless this represents an ASM insn. */
11126 {
11131 {
11134 pos++;
11135 }
11145 {
11148 else
11151 }
11152 }
11159 /* Recognize all noop sets, these will be killed by followup pass. */
11163 /* If we had any clobbers to add, make a new pattern than contains
11164 them. Then check to make sure that all of them are dead. */
11166 {
11176 else
11183 {
11188 {
11192 }
11193 }
11195 }
11199 {
11206 /* Allow targets to reject combined insn. */
11208 {
11211 dump_file);
11213 /* Callers expect recog_for_combine to strip
11214 clobbers from the pattern on failure. */
11219 }
11224 }
11230 }
11232 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11233 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11234 Return whether anything was so changed. */
11236 static bool
11238 {
11244 {
11253 {
11262 else
11264 }
11271 {
11276 }
11282 {
11285 }
11286 else
11294 }
11305 {
11320 else
11328 }
11331 }
11333 /* Like recog, but we receive the address of a pointer to a new pattern.
11334 We try to match the rtx that the pointer points to.
11335 If that fails, we may try to modify or replace the pattern,
11336 storing the replacement into the same pointer object.
11338 Modifications include deletion or addition of CLOBBERs. If the
11339 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11340 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11341 (and undo if that fails).
11343 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11344 the CLOBBERs are placed.
11346 The value is the final insn code from the pattern ultimately matched,
11347 or -1. */
11349 static int
11351 {
11363 {
11366 {
11370 }
11371 }
11374 {
11379 }
11382 }
11383 \f
11384 /* Like gen_lowpart_general but for use by combine. In combine it
11385 is not possible to create any new pseudoregs. However, it is
11386 safe to create invalid memory addresses, because combine will
11387 try to recognize them and all they will do is make the combine
11388 attempt fail.
11390 If for some reason this cannot do its job, an rtx
11391 (clobber (const_int 0)) is returned.
11392 An insn containing that will not be recognized. */
11394 static rtx
11396 {
11400 rtx result;
11405 /* We can only support MODE being wider than a word if X is a
11406 constant integer or has a mode the same size. */
11411 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11412 won't know what to do. So we will strip off the SUBREG here and
11413 process normally. */
11415 {
11418 /* For use in case we fall down into the address adjustments
11419 further below, we need to adjust the known mode and size of
11420 x; imode and isize, since we just adjusted x. */
11427 }
11435 {
11438 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11439 address. */
11444 /* If we want to refer to something bigger than the original memref,
11445 generate a paradoxical subreg instead. That will force a reload
11446 of the original memref X. */
11453 /* Adjust the address so that the address-after-the-data is
11454 unchanged. */
11459 }
11461 /* If X is a comparison operator, rewrite it in a new mode. This
11462 probably won't match, but may allow further simplifications. */
11466 /* If we couldn't simplify X any other way, just enclose it in a
11467 SUBREG. Normally, this SUBREG won't match, but some patterns may
11468 include an explicit SUBREG or we may simplify it further in combine. */
11469 else
11470 {
11471 rtx res;
11474 {
11479 }
11483 }
11485 fail:
11487 }
11488 \f
11489 /* Try to simplify a comparison between OP0 and a constant OP1,
11490 where CODE is the comparison code that will be tested, into a
11491 (CODE OP0 const0_rtx) form.
11493 The result is a possibly different comparison code to use.
11494 *POP1 may be updated. */
11496 static enum rtx_code
11499 {
11503 /* Get the constant we are comparing against and turn off all bits
11504 not on in our mode. */
11508 /* If we are comparing against a constant power of two and the value
11509 being compared can only have that single bit nonzero (e.g., it was
11510 `and'ed with that bit), we can replace this with a comparison
11511 with zero. */
11519 {
11522 }
11524 /* Similarly, if we are comparing a value known to be either -1 or
11525 0 with -1, change it to the opposite comparison against zero. */
11530 {
11533 }
11535 /* Do some canonicalizations based on the comparison code. We prefer
11536 comparisons against zero and then prefer equality comparisons.
11537 If we can reduce the size of a constant, we will do that too. */
11539 {
11541 /* < C is equivalent to <= (C - 1) */
11543 {
11546 /* ... fall through to LE case below. */
11548 }
11549 else
11553 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11555 {
11558 }
11560 /* If we are doing a <= 0 comparison on a value known to have
11561 a zero sign bit, we can replace this with == 0. */
11571 /* >= C is equivalent to > (C - 1). */
11573 {
11576 /* ... fall through to GT below. */
11578 }
11579 else
11583 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11585 {
11588 }
11590 /* If we are doing a > 0 comparison on a value known to have
11591 a zero sign bit, we can replace this with != 0. */
11601 /* < C is equivalent to <= (C - 1). */
11603 {
11606 /* ... fall through ... */
11607 }
11608 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11612 {
11616 }
11617 else
11621 /* unsigned <= 0 is equivalent to == 0 */
11624 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11628 {
11631 }
11635 /* >= C is equivalent to > (C - 1). */
11637 {
11640 /* ... fall through ... */
11641 }
11643 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11647 {
11651 }
11652 else
11656 /* unsigned > 0 is equivalent to != 0 */
11659 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11663 {
11666 }
11671 }
11675 }
11676 \f
11677 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11678 comparison code that will be tested.
11680 The result is a possibly different comparison code to use. *POP0 and
11681 *POP1 may be updated.
11683 It is possible that we might detect that a comparison is either always
11684 true or always false. However, we do not perform general constant
11685 folding in combine, so this knowledge isn't useful. Such tautologies
11686 should have been detected earlier. Hence we ignore all such cases. */
11688 static enum rtx_code
11690 {
11697 /* Try a few ways of applying the same transformation to both operands. */
11699 {
11700 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11701 so check specially. */
11717 - (GET_MODE_PRECISION
11719 {
11722 }
11724 /* If both operands are the same constant shift, see if we can ignore the
11725 shift. We can if the shift is a rotate or if the bits shifted out of
11726 this shift are known to be zero for both inputs and if the type of
11727 comparison is compatible with the shift. */
11740 {
11753 else
11755 }
11757 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11758 SUBREGs are of the same mode, and, in both cases, the AND would
11759 be redundant if the comparison was done in the narrower mode,
11760 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11761 and the operand's possibly nonzero bits are 0xffffff01; in that case
11762 if we only care about QImode, we don't need the AND). This case
11763 occurs if the output mode of an scc insn is not SImode and
11764 STORE_FLAG_VALUE == 1 (e.g., the 386).
11766 Similarly, check for a case where the AND's are ZERO_EXTEND
11767 operations from some narrower mode even though a SUBREG is not
11768 present. */
11773 {
11790 {
11794 /* The resulting comparison is always unsigned since we masked
11795 off the original sign bit. */
11799 }
11806 {
11812 }
11816 }
11818 /* If both operands are NOT, we can strip off the outer operation
11819 and adjust the comparison code for swapped operands; similarly for
11820 NEG, except that this must be an equality comparison. */
11826 else
11828 }
11830 /* If the first operand is a constant, swap the operands and adjust the
11831 comparison code appropriately, but don't do this if the second operand
11832 is already a constant integer. */
11834 {
11837 }
11839 /* We now enter a loop during which we will try to simplify the comparison.
11840 For the most part, we only are concerned with comparisons with zero,
11841 but some things may really be comparisons with zero but not start
11842 out looking that way. */
11845 {
11852 HOST_WIDE_INT const_op;
11854 /* We only want to handle integral modes. This catches VOIDmode,
11855 CCmode, and the floating-point modes. An exception is that we
11856 can handle VOIDmode if OP0 is a COMPARE or a comparison
11857 operation. */
11864 /* Try to simplify the compare to constant, possibly changing the
11865 comparison op, and/or changing op1 to zero. */
11869 /* Compute some predicates to simplify code below. */
11876 /* If this is a sign bit comparison and we can do arithmetic in
11877 MODE, say that we will only be needing the sign bit of OP0. */
11880 HOST_WIDE_INT_1U
11884 /* Now try cases based on the opcode of OP0. If none of the cases
11885 does a "continue", we exit this loop immediately after the
11886 switch. */
11889 {
11891 /* If we are extracting a single bit from a variable position in
11892 a constant that has only a single bit set and are comparing it
11893 with zero, we can convert this into an equality comparison
11894 between the position and the location of the single bit. */
11895 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11896 have already reduced the shift count modulo the word size. */
11902 {
11910 /* Result is nonzero iff shift count is equal to I. */
11913 }
11915 /* fall through */
11920 {
11923 }
11927 /* If testing for equality, we can take the NOT of the constant. */
11930 {
11934 }
11936 /* If just looking at the sign bit, reverse the sense of the
11937 comparison. */
11939 {
11943 }
11947 /* If testing for equality, we can take the NEG of the constant. */
11950 {
11954 }
11956 /* The remaining cases only apply to comparisons with zero. */
11960 /* When X is ABS or is known positive,
11961 (neg X) is < 0 if and only if X != 0. */
11969 {
11973 }
11975 /* If we have NEG of something whose two high-order bits are the
11976 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11978 {
11982 }
11986 /* If we are testing equality and our count is a constant, we
11987 can perform the inverse operation on our RHS. */
11991 {
11995 }
11997 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11998 a particular bit. Convert it to an AND of a constant of that
11999 bit. This will be converted into a ZERO_EXTRACT. */
12003 {
12005 (HOST_WIDE_INT_1U
12010 }
12012 /* Fall through. */
12015 /* ABS is ignorable inside an equality comparison with zero. */
12017 {
12020 }
12024 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12025 (compare FOO CONST) if CONST fits in FOO's mode and we
12026 are either testing inequality or have an unsigned
12027 comparison with ZERO_EXTEND or a signed comparison with
12028 SIGN_EXTEND. But don't do it if we don't have a compare
12029 insn of the given mode, since we'd have to revert it
12030 later on, and then we wouldn't know whether to sign- or
12031 zero-extend. */
12034 && ! unsigned_comparison_p
12038 {
12041 }
12045 /* Check for the case where we are comparing A - C1 with C2, that is
12047 (subreg:MODE (plus (A) (-C1))) op (C2)
12049 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12050 comparison in the wider mode. One of the following two conditions
12051 must be true in order for this to be valid:
12053 1. The mode extension results in the same bit pattern being added
12054 on both sides and the comparison is equality or unsigned. As
12055 C2 has been truncated to fit in MODE, the pattern can only be
12056 all 0s or all 1s.
12058 2. The mode extension results in the sign bit being copied on
12059 each side.
12061 The difficulty here is that we have predicates for A but not for
12062 (A - C1) so we need to check that C1 is within proper bounds so
12063 as to perturbate A as little as possible. */
12070 {
12079 /* (A - C1) zero-extends if it is positive and sign-extends
12080 if it is negative, C2 both zero- and sign-extends. */
12084 /* (A - C1) sign-extends if it is positive and 1-extends
12085 if it is negative, C2 both sign- and 1-extends. */
12092 /* (A - C1) always sign-extends, like C2. */
12096 {
12099 }
12100 }
12102 /* If the inner mode is narrower and we are extracting the low part,
12103 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12106 ;
12117 {
12118 /* Remove outer subregs that don't do anything. */
12123 {
12127 }
12129 }
12130 else
12133 /* FALLTHROUGH */
12143 {
12146 }
12150 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12151 this for equality comparisons due to pathological cases involving
12152 overflows. */
12156 {
12160 }
12162 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12165 {
12169 }
12173 /* We used to optimize signed comparisons against zero, but that
12174 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12175 arrive here as equality comparisons, or (GEU, LTU) are
12176 optimized away. No need to special-case them. */
12178 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12179 (eq B (minus A C)), whichever simplifies. We can only do
12180 this for equality comparisons due to pathological cases involving
12181 overflows. */
12185 {
12189 }
12194 {
12198 }
12200 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12201 of bits in X minus 1, is one iff X > 0. */
12206 {
12210 }
12214 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12215 if C is zero or B is a constant. */
12219 {
12223 }
12231 /* We can't do anything if OP0 is a condition code value, rather
12232 than an actual data value. */
12238 /* Get the two operands being compared. */
12241 else
12244 /* Check for the cases where we simply want the result of the
12245 earlier test or the opposite of that result. */
12249 {
12253 else
12257 {
12262 }
12263 }
12267 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12268 iff X <= 0. */
12272 {
12276 }
12280 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12281 will be converted to a ZERO_EXTRACT later. */
12285 {
12290 }
12292 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12293 zero and X is a comparison and C1 and C2 describe only bits set
12294 in STORE_FLAG_VALUE, we can compare with X. */
12302 {
12309 {
12312 }
12313 }
12315 /* If we are doing an equality comparison of an AND of a bit equal
12316 to the sign bit, replace this with a LT or GE comparison of
12317 the underlying value. */
12324 {
12328 }
12330 /* If this AND operation is really a ZERO_EXTEND from a narrower
12331 mode, the constant fits within that mode, and this is either an
12332 equality or unsigned comparison, try to do this comparison in
12333 the narrower mode.
12335 Note that in:
12337 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12338 -> (ne:DI (reg:SI 4) (const_int 0))
12340 unless TRULY_NOOP_TRUNCATION allows it or the register is
12341 known to hold a value of the required mode the
12342 transformation is invalid. */
12350 {
12353 }
12355 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12356 fits in both M1 and M2 and the SUBREG is either paradoxical
12357 or represents the low part, permute the SUBREG and the AND
12358 and try again. */
12361 {
12364 /* Require an integral mode, to avoid creating something like
12365 (AND:SF ...). */
12367 /* It is unsafe to commute the AND into the SUBREG if the
12368 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12369 not defined. As originally written the upper bits
12370 have a defined value due to the AND operation.
12371 However, if we commute the AND inside the SUBREG then
12372 they no longer have defined values and the meaning of
12373 the code has been changed.
12374 Also C1 should not change value in the smaller mode,
12375 see PR67028 (a positive C1 can become negative in the
12376 smaller mode, so that the AND does no longer mask the
12377 upper bits). */
12378 && ((WORD_REGISTER_OPERATIONS
12390 {
12396 }
12397 }
12399 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12403 {
12408 }
12410 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12411 (eq (and (lshiftrt X) 1) 0).
12412 Also handle the case where (not X) is expressed using xor. */
12416 {
12426 == HOST_WIDE_INT_1U
12428 {
12429 op0
12434 }
12435 }
12439 /* If we have (compare (ashift FOO N) (const_int C)) and
12440 the high order N bits of FOO (N+1 if an inequality comparison)
12441 are known to be zero, we can do this by comparing FOO with C
12442 shifted right N bits so long as the low-order N bits of C are
12443 zero. */
12455 {
12456 /* We must perform a logical shift, not an arithmetic one,
12457 as we want the top N bits of C to be zero. */
12464 }
12466 /* If we are doing a sign bit comparison, it means we are testing
12467 a particular bit. Convert it to the appropriate AND. */
12470 {
12472 (HOST_WIDE_INT_1U
12477 }
12479 /* If this an equality comparison with zero and we are shifting
12480 the low bit to the sign bit, we can convert this to an AND of the
12481 low-order bit. */
12485 {
12488 }
12492 /* If this is an equality comparison with zero, we can do this
12493 as a logical shift, which might be much simpler. */
12496 {
12501 }
12503 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12504 do the comparison in a narrower mode. */
12514 {
12517 }
12519 /* Likewise if OP0 is a PLUS of a sign extension with a
12520 constant, which is usually represented with the PLUS
12521 between the shifts. */
12533 {
12541 new_const);
12543 }
12545 /* FALLTHROUGH */
12547 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12548 the low order N bits of FOO are known to be zero, we can do this
12549 by comparing FOO with C shifted left N bits so long as no
12550 overflow occurs. Even if the low order N bits of FOO aren't known
12551 to be zero, if the comparison is >= or < we can use the same
12552 optimization and for > or <= by setting all the low
12553 order N bits in the comparison constant. */
12564 {
12565 unsigned HOST_WIDE_INT low_bits
12567 & ((HOST_WIDE_INT_1U
12570 {
12571 /* If the shift was logical, then we must make the condition
12572 unsigned. */
12581 const_op
12586 }
12587 }
12589 /* If we are using this shift to extract just the sign bit, we
12590 can replace this with an LT or GE comparison. */
12595 {
12599 }
12604 }
12607 }
12609 /* Now make any compound operations involved in this comparison. Then,
12610 check for an outmost SUBREG on OP0 that is not doing anything or is
12611 paradoxical. The latter transformation must only be performed when
12612 it is known that the "extra" bits will be the same in op0 and op1 or
12613 that they don't matter. There are three cases to consider:
12615 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12616 care bits and we can assume they have any convenient value. So
12617 making the transformation is safe.
12619 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12620 In this case the upper bits of op0 are undefined. We should not make
12621 the simplification in that case as we do not know the contents of
12622 those bits.
12624 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12625 In that case we know those bits are zeros or ones. We must also be
12626 sure that they are the same as the upper bits of op1.
12628 We can never remove a SUBREG for a non-equality comparison because
12629 the sign bit is in a different place in the underlying object. */
12642 {
12644 {
12645 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12646 implemented. */
12648 {
12651 }
12652 }
12658 {
12664 }
12665 }
12667 /* We now do the opposite procedure: Some machines don't have compare
12668 insns in all modes. If OP0's mode is an integer mode smaller than a
12669 word and we can't do a compare in that mode, see if there is a larger
12670 mode for which we can do the compare. There are a number of cases in
12671 which we can use the wider mode. */
12681 {
12684 /* If this is a test for negative, we can make an explicit
12685 test of the sign bit. Test this first so we can use
12686 a paradoxical subreg to extend OP0. */
12690 {
12691 unsigned HOST_WIDE_INT sign
12698 }
12700 /* If the only nonzero bits in OP0 and OP1 are those in the
12701 narrower mode and this is an equality or unsigned comparison,
12702 we can use the wider mode. Similarly for sign-extended
12703 values, in which case it is true for all comparisons. */
12720 {
12721 /* If OP0 is an AND and we don't have an AND in MODE either,
12722 make a new AND in the proper mode. */
12730 else
12731 {
12733 {
12736 }
12737 else
12738 {
12741 }
12743 }
12744 }
12745 }
12747 /* We may have changed the comparison operands. Re-canonicalize. */
12749 {
12752 }
12754 /* If this machine only supports a subset of valid comparisons, see if we
12755 can convert an unsupported one into a supported one. */
12762 }
12763 \f
12764 /* Utility function for record_value_for_reg. Count number of
12765 rtxs in X. */
12766 static int
12768 {
12775 {
12795 }
12806 }
12807 \f
12808 /* Utility function for following routine. Called when X is part of a value
12809 being stored into last_set_value. Sets last_set_table_tick
12810 for each register mentioned. Similar to mention_regs in cse.c */
12812 static void
12814 {
12820 {
12826 {
12829 }
12832 }
12836 {
12837 /* Check for identical subexpressions. If x contains
12838 identical subexpression we only have to traverse one of
12839 them. */
12841 {
12842 /* Note that at this point x1 has already been
12843 processed. */
12847 /* If x0 and x1 are identical then there is no need to
12848 process x0. */
12852 /* If x0 is identical to a subexpression of x1 then while
12853 processing x1, x0 has already been processed. Thus we
12854 are done with x. */
12859 /* If x1 is identical to a subexpression of x0 then we
12860 still have to process the rest of x0. */
12863 {
12866 }
12867 }
12870 }
12874 }
12876 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12877 are saying that the register is clobbered and we no longer know its
12878 value. If INSN is zero, don't update reg_stat[].last_set; this is
12879 only permitted with VALUE also zero and is used to invalidate the
12880 register. */
12882 static void
12884 {
12890 /* If VALUE contains REG and we have a previous value for REG, substitute
12891 the previous value. */
12893 {
12894 rtx tem;
12896 /* Set things up so get_last_value is allowed to see anything set up to
12897 our insn. */
12901 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12902 it isn't going to be useful and will take a lot of time to process,
12903 so just use the CLOBBER. */
12906 {
12912 {
12913 /* If there are two or more occurrences of REG in VALUE,
12914 prevent the value from growing too much. */
12917 }
12920 }
12921 }
12923 /* For each register modified, show we don't know its value, that
12924 we don't know about its bitwise content, that its value has been
12925 updated, and that we don't know the location of the death of the
12926 register. */
12928 {
12940 }
12942 /* Mark registers that are being referenced in this value. */
12946 /* Now update the status of each register being set.
12947 If someone is using this register in this block, set this register
12948 to invalid since we will get confused between the two lives in this
12949 basic block. This makes using this register always invalid. In cse, we
12950 scan the table to invalidate all entries using this register, but this
12951 is too much work for us. */
12954 {
12960 else
12962 }
12964 /* The value being assigned might refer to X (like in "x++;"). In that
12965 case, we must replace it with (clobber (const_int 0)) to prevent
12966 infinite loops. */
12969 {
12973 }
12975 /* For the main register being modified, update the value, the mode, the
12976 nonzero bits, and the number of sign bit copies. */
12981 {
12989 rsp->last_set_sign_bit_copies
12991 }
12992 }
12994 /* Called via note_stores from record_dead_and_set_regs to handle one
12995 SET or CLOBBER in an insn. DATA is the instruction in which the
12996 set is occurring. */
12998 static void
13000 {
13007 {
13011 }
13014 {
13015 /* If we are setting the whole register, we know its value. Otherwise
13016 show that we don't know the value. We can handle SUBREG in
13017 some cases. */
13028 else
13030 }
13032 /* Ignore pushes, they clobber nothing. */
13035 }
13037 /* Update the records of when each REG was most recently set or killed
13038 for the things done by INSN. This is the last thing done in processing
13039 INSN in the combiner loop.
13041 We update reg_stat[], in particular fields last_set, last_set_value,
13042 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13043 last_death, and also the similar information mem_last_set (which insn
13044 most recently modified memory) and last_call_luid (which insn was the
13045 most recent subroutine call). */
13047 static void
13049 {
13050 rtx link;
13054 {
13057 {
13062 {
13067 }
13068 }
13071 }
13074 {
13075 hard_reg_set_iterator hrsi;
13077 {
13089 }
13093 /* We can't combine into a call pattern. Remember, though, that
13094 the return value register is set at this LUID. We could
13095 still replace a register with the return value from the
13096 wrong subroutine call! */
13098 }
13099 else
13101 }
13103 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13104 register present in the SUBREG, so for each such SUBREG go back and
13105 adjust nonzero and sign bit information of the registers that are
13106 known to have some zero/sign bits set.
13108 This is needed because when combine blows the SUBREGs away, the
13109 information on zero/sign bits is lost and further combines can be
13110 missed because of that. */
13112 static void
13114 {
13116 rtx set;
13124 {
13133 {
13136 }
13140 {
13143 }
13146 {
13149 }
13150 else
13152 }
13153 }
13155 /* Check if X, a register, is known to contain a value already
13156 truncated to MODE. In this case we can use a subreg to refer to
13157 the truncated value even though in the generic case we would need
13158 an explicit truncation. */
13160 static bool
13162 {
13174 }
13176 /* If X is a hard reg or a subreg record the mode that the register is
13177 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13178 to turn a truncate into a subreg using this information. Return true
13179 if traversing X is complete. */
13181 static bool
13183 {
13184 machine_mode truncated_mode;
13188 {
13199 }
13200 /* ??? For hard-regs we now record everything. We might be able to
13201 optimize this using last_set_mode. */
13204 else
13212 {
13215 }
13218 }
13220 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13221 the modes they are used in. This can help truning TRUNCATEs into
13222 SUBREGs. */
13224 static void
13226 {
13231 }
13233 /* Scan X for promoted SUBREGs. For each one found,
13234 note what it implies to the registers used in it. */
13236 static void
13238 {
13243 else
13244 {
13250 {
13260 }
13261 }
13262 }
13263 \f
13264 /* Verify that all the registers and memory references mentioned in *LOC are
13265 still valid. *LOC was part of a value set in INSN when label_tick was
13266 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13267 the invalid references with (clobber (const_int 0)) and return 1. This
13268 replacement is useful because we often can get useful information about
13269 the form of a value (e.g., if it was produced by a shift that always
13270 produces -1 or 0) even though we don't know exactly what registers it
13271 was produced from. */
13273 static int
13275 {
13282 {
13288 {
13291 /* If this is a pseudo-register that was only set once and not
13292 live at the beginning of the function, it is always valid. */
13296 && (!REGNO_REG_SET_P
13298 regno)))
13300 {
13304 }
13305 }
13308 }
13309 /* If this is a memory reference, make sure that there were no stores after
13310 it that might have clobbered the value. We don't have alias info, so we
13311 assume any store invalidates it. Moreover, we only have local UIDs, so
13312 we also assume that there were stores in the intervening basic blocks. */
13315 {
13319 }
13322 {
13324 {
13325 /* Check for identical subexpressions. If x contains
13326 identical subexpression we only have to traverse one of
13327 them. */
13329 {
13330 /* Note that at this point x0 has already been checked
13331 and found valid. */
13335 /* If x0 and x1 are identical then x is also valid. */
13339 /* If x1 is identical to a subexpression of x0 then
13340 while checking x0, x1 has already been checked. Thus
13341 it is valid and so as x. */
13346 /* If x0 is identical to a subexpression of x1 then x is
13347 valid iff the rest of x1 is valid. */
13350 return
13354 }
13359 }
13365 }
13367 /* If we haven't found a reason for it to be invalid, it is valid. */
13369 }
13371 /* Get the last value assigned to X, if known. Some registers
13372 in the value may be replaced with (clobber (const_int 0)) if their value
13373 is known longer known reliably. */
13375 static rtx
13377 {
13379 rtx value;
13382 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13383 then convert it to the desired mode. If this is a paradoxical SUBREG,
13384 we cannot predict what values the "extra" bits might have. */
13398 /* If we don't have a value, or if it isn't for this basic block and
13399 it's either a hard register, set more than once, or it's a live
13400 at the beginning of the function, return 0.
13402 Because if it's not live at the beginning of the function then the reg
13403 is always set before being used (is never used without being set).
13404 And, if it's set only once, and it's always set before use, then all
13405 uses must have the same last value, even if it's not from this basic
13406 block. */
13413 || REGNO_REG_SET_P
13417 /* If the value was set in a later insn than the ones we are processing,
13418 we can't use it even if the register was only set once. */
13423 /* If fewer bits were set than what we are asked for now, we cannot use
13424 the value. */
13429 /* If the value has all its registers valid, return it. */
13433 /* Otherwise, make a copy and replace any invalid register with
13434 (clobber (const_int 0)). If that fails for some reason, return 0. */
13441 }
13442 \f
13443 /* Return nonzero if expression X refers to a REG or to memory
13444 that is set in an instruction more recent than FROM_LUID. */
13446 static int
13448 {
13454 {
13458 #ifdef PUSH_ROUNDING
13459 /* Don't allow uses of the stack pointer to be moved,
13460 because we don't know whether the move crosses a push insn. */
13463 #endif
13465 {
13471 }
13473 }
13481 {
13483 {
13488 }
13492 }
13494 }
13495 \f
13496 /* Define three variables used for communication between the following
13497 routines. */
13502 /* Function called via note_stores from reg_dead_at_p.
13504 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13505 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13507 static void
13509 {
13519 }
13521 /* Return nonzero if REG is known to be dead at INSN.
13523 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13524 referencing REG, it is dead. If we hit a SET referencing REG, it is
13525 live. Otherwise, see if it is live or dead at the start of the basic
13526 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13527 must be assumed to be always live. */
13529 static int
13531 {
13532 basic_block block;
13535 /* Set variables for reg_dead_at_p_1. */
13541 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13542 we allow the machine description to decide whether use-and-clobber
13543 patterns are OK. */
13545 {
13549 }
13551 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13552 beginning of basic block. */
13555 {
13557 {
13567 }
13573 }
13575 /* Look at live-in sets for the basic block that we were in. */
13581 }
13582 \f
13583 /* Note hard registers in X that are used. */
13585 static void
13587 {
13593 {
13597 CASE_CONST_ANY:
13602 /* CC0 must die in the insn after it is set, so we don't need to take
13603 special note of it here. */
13608 /* If we are clobbering a MEM, mark any hard registers inside the
13609 address as used. */
13616 /* A hard reg in a wide mode may really be multiple registers.
13617 If so, mark all of them just like the first. */
13619 {
13620 /* None of this applies to the stack, frame or arg pointers. */
13622 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13630 }
13634 {
13635 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13636 the address. */
13648 }
13653 }
13655 /* Recursively scan the operands of this expression. */
13657 {
13661 {
13665 {
13670 }
13671 }
13672 }
13673 }
13674 \f
13675 /* Remove register number REGNO from the dead registers list of INSN.
13677 Return the note used to record the death, if there was one. */
13679 rtx
13681 {
13688 }
13690 /* For each register (hardware or pseudo) used within expression X, if its
13691 death is in an instruction with luid between FROM_LUID (inclusive) and
13692 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13693 list headed by PNOTES.
13695 That said, don't move registers killed by maybe_kill_insn.
13697 This is done when X is being merged by combination into TO_INSN. These
13698 notes will then be distributed as needed. */
13700 static void
13703 {
13709 {
13713 /* Don't move the register if it gets killed in between from and to. */
13722 {
13725 /* It is possible for the call above to return 0. This can occur
13726 when last_death points to I2 or I1 that we combined with.
13727 In that case make a new note.
13729 We must also check for the case where X is a hard register
13730 and NOTE is a death note for a range of hard registers
13731 including X. In that case, we must put REG_DEAD notes for
13732 the remaining registers in place of NOTE. */
13737 {
13746 }
13748 /* If we didn't find any note, or if we found a REG_DEAD note that
13749 covers only part of the given reg, and we have a multi-reg hard
13750 register, then to be safe we must check for REG_DEAD notes
13751 for each register other than the first. They could have
13752 their own REG_DEAD notes lying around. */
13759 {
13766 else
13772 }
13775 {
13778 }
13779 else
13781 }
13784 }
13787 {
13792 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13793 that accesses one word of a multi-word item, some
13794 piece of everything register in the expression is used by
13795 this insn, so remove any old death. */
13796 /* ??? So why do we test for equality of the sizes? */
13805 {
13808 }
13810 /* If this is some other SUBREG, we know it replaces the entire
13811 value, so use that as the destination. */
13815 /* If this is a MEM, adjust deaths of anything used in the address.
13816 For a REG (the only other possibility), the entire value is
13817 being replaced so the old value is not used in this insn. */
13823 }
13832 {
13834 {
13839 }
13842 }
13843 }
13844 \f
13845 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13846 pattern of an insn. X must be a REG. */
13848 static int
13850 {
13854 {
13856 rtx target;
13863 else
13880 }
13888 }
13889 \f
13890 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13891 as appropriate. I3 and I2 are the insns resulting from the combination
13892 insns including FROM (I2 may be zero).
13894 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13895 not need REG_DEAD notes because they are being substituted for. This
13896 saves searching in the most common cases.
13898 Each note in the list is either ignored or placed on some insns, depending
13899 on the type of note. */
13901 static void
13904 {
13906 rtx tem_note;
13910 {
13915 {
13918 /* Doesn't matter much where we put this, as long as it's somewhere.
13919 It is preferable to keep these notes on branches, which is most
13920 likely to be i3. */
13927 else
13928 {
13931 }
13935 /* These notes must remain with the call or trapping instruction. */
13940 else
13941 {
13947 /* ??? Otherwise assume we've combined things such that we
13948 can now prove that the instructions can't trap. Drop the
13949 note in this case. */
13950 }
13954 /* ??? How to distribute between i3-i1. Assume i3 contains the
13955 entire adjustment. Assert i3 contains at least some adjust. */
13957 {
13959 /* fixup_args_size_notes looks at REG_NORETURN note,
13960 so ensure the note is placed there first. */
13962 {
13966 {
13972 }
13973 }
13975 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13976 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13979 && !ACCUMULATE_OUTGOING_ARGS
13981 }
13988 /* These notes must remain with the call. It should not be
13989 possible for both I2 and I3 to be a call. */
13992 else
13993 {
13996 }
14000 /* Any clobbers for i3 may still exist, and so we must process
14001 REG_UNUSED notes from that insn.
14003 Any clobbers from i2 or i1 can only exist if they were added by
14004 recog_for_combine. In that case, recog_for_combine created the
14005 necessary REG_UNUSED notes. Trying to keep any original
14006 REG_UNUSED notes from these insns can cause incorrect output
14007 if it is for the same register as the original i3 dest.
14008 In that case, we will notice that the register is set in i3,
14009 and then add a REG_UNUSED note for the destination of i3, which
14010 is wrong. However, it is possible to have REG_UNUSED notes from
14011 i2 or i1 for register which were both used and clobbered, so
14012 we keep notes from i2 or i1 if they will turn into REG_DEAD
14013 notes. */
14015 /* If this register is set or clobbered in I3, put the note there
14016 unless there is one already. */
14018 {
14026 }
14027 /* Otherwise, if this register is used by I3, then this register
14028 now dies here, so we must put a REG_DEAD note here unless there
14029 is one already. */
14035 {
14038 }
14044 /* These notes say something about results of an insn. We can
14045 only support them if they used to be on I3 in which case they
14046 remain on I3. Otherwise they are ignored.
14048 If the note refers to an expression that is not a constant, we
14049 must also ignore the note since we cannot tell whether the
14050 equivalence is still true. It might be possible to do
14051 slightly better than this (we only have a problem if I2DEST
14052 or I1DEST is present in the expression), but it doesn't
14053 seem worth the trouble. */
14061 /* These notes say something about how a register is used. They must
14062 be present on any use of the register in I2 or I3. */
14067 {
14070 else
14072 }
14077 /* This can show up in several ways -- either directly in the
14078 pattern, or hidden off in the constant pool with (or without?)
14079 a REG_EQUAL note. */
14080 /* ??? Ignore the without-reg_equal-note problem for now. */
14092 {
14095 else
14097 }
14099 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14100 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14101 there. */
14106 {
14113 }
14119 {
14127 }
14131 /* This note says something about the value of a register prior
14132 to the execution of an insn. It is too much trouble to see
14133 if the note is still correct in all situations. It is better
14134 to simply delete it. */
14138 /* If we replaced the right hand side of FROM_INSN with a
14139 REG_EQUAL note, the original use of the dying register
14140 will not have been combined into I3 and I2. In such cases,
14141 FROM_INSN is guaranteed to be the first of the combined
14142 instructions, so we simply need to search back before
14143 FROM_INSN for the previous use or set of this register,
14144 then alter the notes there appropriately.
14146 If the register is used as an input in I3, it dies there.
14147 Similarly for I2, if it is nonzero and adjacent to I3.
14149 If the register is not used as an input in either I3 or I2
14150 and it is not one of the registers we were supposed to eliminate,
14151 there are two possibilities. We might have a non-adjacent I2
14152 or we might have somehow eliminated an additional register
14153 from a computation. For example, we might have had A & B where
14154 we discover that B will always be zero. In this case we will
14155 eliminate the reference to A.
14157 In both cases, we must search to see if we can find a previous
14158 use of A and put the death note there. */
14164 else
14165 {
14176 && !(i2mod
14178 i2mod_old_rhs)))
14183 /* If the new I2 sets the same register that is marked dead
14184 in the note, we do not know where to put the note.
14185 Give up. */
14188 }
14191 {
14195 {
14197 {
14201 }
14203 /* If the register is being set at TEM_INSN, see if that is all
14204 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14205 into a REG_UNUSED note instead. Don't delete sets to
14206 global register vars. */
14210 {
14221 ;
14223 /* Verify that it was the set, and not a clobber that
14224 modified the register.
14226 CC0 targets must be careful to maintain setter/user
14227 pairs. If we cannot delete the setter due to side
14228 effects, mark the user with an UNUSED note instead
14229 of deleting it. */
14233 && (!HAVE_cc0
14237 {
14238 /* Move the notes and links of TEM_INSN elsewhere.
14239 This might delete other dead insns recursively.
14240 First set the pattern to something that won't use
14241 any register. */
14255 /* Delete the setter too. */
14257 {
14270 }
14271 }
14272 else
14273 {
14276 /* If there isn't already a REG_UNUSED note, put one
14277 here. Do not place a REG_DEAD note, even if
14278 the register is also used here; that would not
14279 match the algorithm used in lifetime analysis
14280 and can cause the consistency check in the
14281 scheduler to fail. */
14286 }
14287 }
14291 {
14294 /* If we are doing a 3->2 combination, and we have a
14295 register which formerly died in i3 and was not used
14296 by i2, which now no longer dies in i3 and is used in
14297 i2 but does not die in i2, and place is between i2
14298 and i3, then we may need to move a link from place to
14299 i2. */
14301 && from_insn
14304 {
14308 }
14310 }
14314 }
14316 }
14318 /* If the register is set or already dead at PLACE, we needn't do
14319 anything with this note if it is still a REG_DEAD note.
14320 We check here if it is set at all, not if is it totally replaced,
14321 which is what `dead_or_set_p' checks, so also check for it being
14322 set partially. */
14325 {
14331 {
14332 /* Unless the register previously died in PLACE, clear
14333 last_death. [I no longer understand why this is
14334 being done.] */
14338 }
14339 else
14342 /* If this is a death note for a hard reg that is occupying
14343 multiple registers, ensure that we are still using all
14344 parts of the object. If we find a piece of the object
14345 that is unused, we must arrange for an appropriate REG_DEAD
14346 note to be added for it. However, we can't just emit a USE
14347 and tag the note to it, since the register might actually
14348 be dead; so we recourse, and the recursive call then finds
14349 the previous insn that used this register. */
14352 {
14361 {
14364 }
14367 {
14368 /* Put only REG_DEAD notes for pieces that are
14369 not already dead or set. */
14373 {
14380 {
14382 NULL_RTX);
14386 NULL_RTX);
14387 }
14392 {
14394 {
14398 }
14402 {
14405 }
14406 }
14407 }
14410 }
14411 }
14412 }
14416 /* Any other notes should not be present at this point in the
14417 compilation. */
14419 }
14422 {
14425 }
14429 }
14430 }
14431 \f
14432 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14433 I3, I2, and I1 to new locations. This is also called to add a link
14434 pointing at I3 when I3's destination is changed. */
14436 static void
14438 {
14442 {
14449 /* If the insn that this link points to is a NOTE, ignore it. */
14458 {
14461 {
14477 }
14480 }
14481 else
14491 /* A LOG_LINK is defined as being placed on the first insn that uses
14492 a register and points to the insn that sets the register. Start
14493 searching at the next insn after the target of the link and stop
14494 when we reach a set of the register or the end of the basic block.
14496 Note that this correctly handles the link that used to point from
14497 I3 to I2. Also note that not much searching is typically done here
14498 since most links don't point very far away. */
14507 {
14511 }
14514 {
14517 }
14521 /* If we found a place to put the link, place it there unless there
14522 is already a link to the same insn as LINK at that point. */
14525 {
14533 {
14537 /* Set added_links_insn to the earliest insn we added a
14538 link to. */
14542 }
14543 }
14544 }
14545 }
14546 \f
14547 /* Check for any register or memory mentioned in EQUIV that is not
14548 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14549 of EXPR where some registers may have been replaced by constants. */
14551 static bool
14553 {
14556 {
14561 }
14563 }
14564 \f
14565 DEBUG_FUNCTION void
14567 {
14568 fprintf
14570 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14572 }
14574 void
14576 {
14577 fprintf
14579 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14581 }
14582 \f
14583 /* Try combining insns through substitution. */
14584 static unsigned int
14586 {
14596 rebuild_jump_labels_after_combine
14599 /* Combining insns may have turned an indirect jump into a
14600 direct jump. Rebuild the JUMP_LABEL fields of jumping
14601 instructions. */
14603 {
14610 }
14614 }
14619 {
14629 };
14632 {
14636 {}
14638 /* opt_pass methods: */
14641 {
14643 }
14649 rtl_opt_pass *
14651 {
14653 }