| blob | 4e4078f3377497b25dae39b063fb66e03362c68a |
1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
29 #ifndef RS6000_OPTS_H
31 #endif
33 /* Definitions for the object file format. These are set at
34 compile-time. */
36 #define OBJECT_XCOFF 1
37 #define OBJECT_ELF 2
38 #define OBJECT_PEF 3
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
46 #ifndef TARGET_AIX
47 #define TARGET_AIX 0
48 #endif
50 #ifndef TARGET_AIX_OS
51 #define TARGET_AIX_OS 0
52 #endif
54 /* Control whether function entry points use a "dot" symbol when
55 ABI_AIX. */
56 #define DOT_SYMBOLS 1
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
61 #endif
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
66 #else
67 #define PPC405_ERRATUM77 0
68 #endif
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
72 #endif
74 #ifdef HAVE_AS_POPCNTB
76 #else
78 #endif
80 #ifdef HAVE_AS_DFP
82 #else
84 #endif
86 #ifdef HAVE_AS_POPCNTD
88 #else
90 #endif
92 #ifdef HAVE_AS_POWER8
94 #else
95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
96 #endif
98 #ifdef HAVE_AS_POWER9
100 #else
101 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC
102 #endif
104 #ifdef HAVE_AS_DCI
106 #else
108 #endif
110 /* Common ASM definitions used by ASM_SPEC among the various targets for
111 handling -mcpu=xxx switches. There is a parallel list in driver-powerpcspe.c to
112 provide the default assembler options if the user uses -mcpu=native, so if
113 you make changes here, make them also there. */
114 #define ASM_CPU_SPEC \
115 "%{!mcpu*: \
116 %{mpowerpc64*: -mppc64} \
117 %{!mpowerpc64*: %(asm_default)}} \
118 %{mcpu=native: %(asm_cpu_native)} \
119 %{mcpu=cell: -mcell} \
120 %{mcpu=power3: -mppc64} \
121 %{mcpu=power4: -mpower4} \
122 %{mcpu=power5: %(asm_cpu_power5)} \
123 %{mcpu=power5+: %(asm_cpu_power5)} \
124 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
125 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
126 %{mcpu=power7: %(asm_cpu_power7)} \
127 %{mcpu=power8: %(asm_cpu_power8)} \
128 %{mcpu=power9: %(asm_cpu_power9)} \
129 %{mcpu=a2: -ma2} \
130 %{mcpu=powerpc: -mppc} \
131 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
132 %{mcpu=rs64a: -mppc64} \
133 %{mcpu=401: -mppc} \
134 %{mcpu=403: -m403} \
135 %{mcpu=405: -m405} \
136 %{mcpu=405fp: -m405} \
137 %{mcpu=440: -m440} \
138 %{mcpu=440fp: -m440} \
139 %{mcpu=464: -m440} \
140 %{mcpu=464fp: -m440} \
141 %{mcpu=476: %(asm_cpu_476)} \
142 %{mcpu=476fp: %(asm_cpu_476)} \
143 %{mcpu=505: -mppc} \
144 %{mcpu=601: -m601} \
145 %{mcpu=602: -mppc} \
146 %{mcpu=603: -mppc} \
147 %{mcpu=603e: -mppc} \
148 %{mcpu=ec603e: -mppc} \
149 %{mcpu=604: -mppc} \
150 %{mcpu=604e: -mppc} \
151 %{mcpu=620: -mppc64} \
152 %{mcpu=630: -mppc64} \
153 %{mcpu=740: -mppc} \
154 %{mcpu=750: -mppc} \
155 %{mcpu=G3: -mppc} \
156 %{mcpu=7400: -mppc -maltivec} \
157 %{mcpu=7450: -mppc -maltivec} \
158 %{mcpu=G4: -mppc -maltivec} \
159 %{mcpu=801: -mppc} \
160 %{mcpu=821: -mppc} \
161 %{mcpu=823: -mppc} \
162 %{mcpu=860: -mppc} \
163 %{mcpu=970: -mpower4 -maltivec} \
164 %{mcpu=G5: -mpower4 -maltivec} \
165 %{mcpu=8540: -me500} \
166 %{mcpu=8548: -me500} \
167 %{mcpu=e300c2: -me300} \
168 %{mcpu=e300c3: -me300} \
169 %{mcpu=e500mc: -me500mc} \
170 %{mcpu=e500mc64: -me500mc64} \
171 %{mcpu=e5500: -me5500} \
172 %{mcpu=e6500: -me6500} \
173 %{maltivec: -maltivec} \
174 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
175 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
176 -many"
182 /* This macro defines names of additional specifications to put in the specs
183 that can be used in various specifications like CC1_SPEC. Its definition
184 is an initializer with a subgrouping for each command option.
186 Each subgrouping contains a string constant, that defines the
187 specification name, and a string constant that used by the GCC driver
188 program.
190 Do not define this macro if it does not need to do anything. */
192 #define SUBTARGET_EXTRA_SPECS
194 #define EXTRA_SPECS \
206 SUBTARGET_EXTRA_SPECS
208 /* -mcpu=native handling only makes sense with compiler running on
209 an PowerPC chip. If changing this condition, also change
210 the condition in driver-powerpcspe.c. */
211 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
212 /* In driver-powerpcspe.c. */
214 #define EXTRA_SPEC_FUNCTIONS \
216 #define HAVE_LOCAL_CPU_DETECT
219 #else
221 #endif
223 #ifndef CC1_CPU_SPEC
224 #ifdef HAVE_LOCAL_CPU_DETECT
225 #define CC1_CPU_SPEC \
226 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
227 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
228 #else
230 #endif
231 #endif
233 /* Architecture type. */
235 /* Define TARGET_MFCRF if the target assembler does not support the
236 optional field operand for mfcr. */
238 #ifndef HAVE_AS_MFCRF
239 #undef TARGET_MFCRF
240 #define TARGET_MFCRF 0
241 #endif
243 /* Define TARGET_POPCNTB if the target assembler does not support the
244 popcount byte instruction. */
246 #ifndef HAVE_AS_POPCNTB
247 #undef TARGET_POPCNTB
248 #define TARGET_POPCNTB 0
249 #endif
251 /* Define TARGET_FPRND if the target assembler does not support the
252 fp rounding instructions. */
254 #ifndef HAVE_AS_FPRND
255 #undef TARGET_FPRND
256 #define TARGET_FPRND 0
257 #endif
259 /* Define TARGET_CMPB if the target assembler does not support the
260 cmpb instruction. */
262 #ifndef HAVE_AS_CMPB
263 #undef TARGET_CMPB
264 #define TARGET_CMPB 0
265 #endif
267 /* Define TARGET_MFPGPR if the target assembler does not support the
268 mffpr and mftgpr instructions. */
270 #ifndef HAVE_AS_MFPGPR
271 #undef TARGET_MFPGPR
272 #define TARGET_MFPGPR 0
273 #endif
275 /* Define TARGET_DFP if the target assembler does not support decimal
276 floating point instructions. */
277 #ifndef HAVE_AS_DFP
278 #undef TARGET_DFP
279 #define TARGET_DFP 0
280 #endif
282 /* Define TARGET_POPCNTD if the target assembler does not support the
283 popcount word and double word instructions. */
285 #ifndef HAVE_AS_POPCNTD
286 #undef TARGET_POPCNTD
287 #define TARGET_POPCNTD 0
288 #endif
290 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
291 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
292 instructions. */
294 #ifndef HAVE_AS_POWER8
295 #undef TARGET_DIRECT_MOVE
296 #undef TARGET_CRYPTO
297 #undef TARGET_HTM
298 #undef TARGET_P8_VECTOR
299 #define TARGET_DIRECT_MOVE 0
300 #define TARGET_CRYPTO 0
301 #define TARGET_HTM 0
302 #define TARGET_P8_VECTOR 0
303 #endif
305 /* Define the ISA 3.0 flags as 0 if the target assembler does not support
306 Power9 instructions. Allow -mpower9-fusion, since it does not add new
307 instructions. Allow -misel, since it predates ISA 3.0 and does
308 not require any Power9 features. */
310 #ifndef HAVE_AS_POWER9
311 #undef TARGET_FLOAT128_HW
312 #undef TARGET_MODULO
313 #undef TARGET_P9_VECTOR
314 #undef TARGET_P9_MINMAX
315 #undef TARGET_P9_DFORM_SCALAR
316 #undef TARGET_P9_DFORM_VECTOR
317 #undef TARGET_P9_MISC
318 #define TARGET_FLOAT128_HW 0
319 #define TARGET_MODULO 0
320 #define TARGET_P9_VECTOR 0
321 #define TARGET_P9_MINMAX 0
322 #define TARGET_P9_DFORM_SCALAR 0
323 #define TARGET_P9_DFORM_VECTOR 0
324 #define TARGET_P9_MISC 0
325 #endif
327 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
328 not, generate the lwsync code as an integer constant. */
329 #ifdef HAVE_AS_LWSYNC
330 #define TARGET_LWSYNC_INSTRUCTION 1
331 #else
332 #define TARGET_LWSYNC_INSTRUCTION 0
333 #endif
335 /* Define TARGET_TLS_MARKERS if the target assembler does not support
336 arg markers for __tls_get_addr calls. */
337 #ifndef HAVE_AS_TLS_MARKERS
338 #undef TARGET_TLS_MARKERS
339 #define TARGET_TLS_MARKERS 0
340 #else
341 #define TARGET_TLS_MARKERS tls_markers
342 #endif
344 #ifndef TARGET_SECURE_PLT
345 #define TARGET_SECURE_PLT 0
346 #endif
348 #ifndef TARGET_CMODEL
349 #define TARGET_CMODEL CMODEL_SMALL
350 #endif
352 #define TARGET_32BIT (! TARGET_64BIT)
354 #ifndef HAVE_AS_TLS
355 #define HAVE_AS_TLS 0
356 #endif
358 #ifndef TARGET_LINK_STACK
359 #define TARGET_LINK_STACK 0
360 #endif
362 #ifndef SET_TARGET_LINK_STACK
363 #define SET_TARGET_LINK_STACK(X) do { } while (0)
364 #endif
366 #ifndef TARGET_FLOAT128_ENABLE_TYPE
367 #define TARGET_FLOAT128_ENABLE_TYPE 0
368 #endif
370 /* Return 1 for a symbol ref for a thread-local storage symbol. */
371 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
372 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
374 #ifdef IN_LIBGCC2
375 /* For libgcc2 we make sure this is a compile time constant */
376 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
377 #undef TARGET_POWERPC64
378 #define TARGET_POWERPC64 1
379 #else
380 #undef TARGET_POWERPC64
381 #define TARGET_POWERPC64 0
382 #endif
383 #else
384 /* The option machinery will define this. */
385 #endif
387 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
389 /* FPU operations supported.
390 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
391 also test TARGET_HARD_FLOAT. */
392 #define TARGET_SINGLE_FLOAT 1
393 #define TARGET_DOUBLE_FLOAT 1
394 #define TARGET_SINGLE_FPU 0
395 #define TARGET_SIMPLE_FPU 0
396 #define TARGET_XILINX_FPU 0
398 /* Recast the processor type to the cpu attribute. */
399 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
401 /* Define generic processor types based upon current deployment. */
402 #define PROCESSOR_COMMON PROCESSOR_PPC601
403 #define PROCESSOR_POWERPC PROCESSOR_PPC604
404 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
406 /* Define the default processor. This is overridden by other tm.h files. */
407 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
408 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
410 /* Specify the dialect of assembler to use. Only new mnemonics are supported
411 starting with GCC 4.8, i.e. just one dialect, but for backwards
412 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
413 defined. */
414 #define ASSEMBLER_DIALECT 1
416 /* Debug support */
424 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
425 | MASK_DEBUG_ARG \
426 | MASK_DEBUG_REG \
427 | MASK_DEBUG_ADDR \
428 | MASK_DEBUG_COST \
429 | MASK_DEBUG_TARGET \
430 | MASK_DEBUG_BUILTIN)
432 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
433 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
434 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
435 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
436 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
437 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
438 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
440 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
441 long double format that uses a pair of doubles, or IEEE 128-bit floating
442 point. KFmode was added as a way to represent IEEE 128-bit floating point,
443 even if the default for long double is the IBM long double format.
444 Similarly IFmode is the IBM long double format even if the default is IEEE
445 128-bit. Don't allow IFmode if -msoft-float. */
446 #define FLOAT128_IEEE_P(MODE) \
447 ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
448 || ((MODE) == KFmode) || ((MODE) == KCmode))
450 #define FLOAT128_IBM_P(MODE) \
451 ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
452 || (TARGET_HARD_FLOAT && TARGET_FPRS \
453 && ((MODE) == IFmode || (MODE) == ICmode)))
455 /* Helper macros to say whether a 128-bit floating point type can go in a
456 single vector register, or whether it needs paired scalar values. */
457 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
459 #define FLOAT128_2REG_P(MODE) \
460 (FLOAT128_IBM_P (MODE) \
461 || ((MODE) == TDmode) \
462 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
464 /* Return true for floating point that does not use a vector register. */
465 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
466 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
468 /* Describe the vector unit used for arithmetic operations. */
471 #define VECTOR_UNIT_NONE_P(MODE) \
472 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
474 #define VECTOR_UNIT_VSX_P(MODE) \
475 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
477 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
478 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
480 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
481 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
483 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
484 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
485 (int)VECTOR_VSX, \
486 (int)VECTOR_P8_VECTOR))
488 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
489 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
490 compatible, so allow it as well, rather than changing all of the uses of the
491 macro. */
492 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
493 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
494 (int)VECTOR_ALTIVEC, \
495 (int)VECTOR_P8_VECTOR))
497 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
498 same unit as the vector unit we are using, but we may want to migrate to
499 using VSX style loads even for types handled by altivec. */
502 #define VECTOR_MEM_NONE_P(MODE) \
503 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
505 #define VECTOR_MEM_VSX_P(MODE) \
506 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
508 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
509 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
511 #define VECTOR_MEM_ALTIVEC_P(MODE) \
512 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
514 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
515 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
516 (int)VECTOR_VSX, \
517 (int)VECTOR_P8_VECTOR))
519 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
520 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
521 (int)VECTOR_ALTIVEC, \
522 (int)VECTOR_P8_VECTOR))
524 /* Return the alignment of a given vector type, which is set based on the
525 vector unit use. VSX for instance can load 32 or 64 bit aligned words
526 without problems, while Altivec requires 128-bit aligned vectors. */
529 #define VECTOR_ALIGN(MODE) \
530 ((rs6000_vector_align[(MODE)] != 0) \
531 ? rs6000_vector_align[(MODE)] \
532 : (int)GET_MODE_BITSIZE ((MODE)))
534 /* Determine the element order to use for vector instructions. By
535 default we use big-endian element order when targeting big-endian,
536 and little-endian element order when targeting little-endian. For
537 programs being ported from BE Power to LE Power, it can sometimes
538 be useful to use big-endian element order when targeting little-endian.
539 This is set via -maltivec=be, for example. */
540 #define VECTOR_ELT_ORDER_BIG \
541 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
543 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
544 with scalar instructions. */
545 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
547 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
548 with the ISA 3.0 MFVSRLD instructions. */
549 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
551 /* Alignment options for fields in structures for sub-targets following
552 AIX-like ABI.
553 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
554 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
556 Override the macro definitions when compiling libobjc to avoid undefined
557 reference to rs6000_alignment_flags due to library's use of GCC alignment
558 macros which use the macros below. */
560 #ifndef IN_TARGET_LIBS
561 #define MASK_ALIGN_POWER 0x00000000
562 #define MASK_ALIGN_NATURAL 0x00000001
563 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
564 #else
565 #define TARGET_ALIGN_NATURAL 0
566 #endif
568 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
569 #define TARGET_IEEEQUAD rs6000_ieeequad
570 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
571 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
573 #define TARGET_SPE_ABI 0
574 #define TARGET_SPE 0
575 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
576 #define TARGET_FPRS 1
577 #define TARGET_E500_SINGLE 0
578 #define TARGET_E500_DOUBLE 0
579 #define CHECK_E500_OPTIONS do { } while (0)
581 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
582 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
583 XILINX. */
584 #define TARGET_FCFID (TARGET_POWERPC64 \
589 || TARGET_XILINX_FPU)
591 #define TARGET_FCTIDZ TARGET_FCFID
592 #define TARGET_STFIWX TARGET_PPC_GFXOPT
593 #define TARGET_LFIWAX TARGET_CMPB
594 #define TARGET_LFIWZX TARGET_POPCNTD
595 #define TARGET_FCFIDS TARGET_POPCNTD
596 #define TARGET_FCFIDU TARGET_POPCNTD
597 #define TARGET_FCFIDUS TARGET_POPCNTD
598 #define TARGET_FCTIDUZ TARGET_POPCNTD
599 #define TARGET_FCTIWUZ TARGET_POPCNTD
600 #define TARGET_CTZ TARGET_MODULO
601 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
602 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
604 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
605 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
606 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
607 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
608 && TARGET_POWERPC64)
609 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
610 && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
613 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
614 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
615 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
617 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
618 loads are slow. */
619 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
621 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
622 in power7, so conditionalize them on p8 features. TImode syncs need quad
623 memory support. */
624 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
625 || TARGET_QUAD_MEMORY_ATOMIC \
626 || TARGET_DIRECT_MOVE)
628 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
630 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
631 to allocate the SDmode stack slot to get the value into the proper location
632 in the register. */
633 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
635 /* ISA 3.0 has new min/max functions that don't need fast math that are being
636 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
637 answers if the arguments are not in the normal range. */
638 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \
639 && (TARGET_P9_MINMAX || !flag_trapping_math))
641 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
642 && (TARGET_P9_MINMAX || !flag_trapping_math))
644 /* In switching from using target_flags to using rs6000_isa_flags, the options
645 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
646 OPTION_MASK_<xxx> back into MASK_<xxx>. */
647 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
648 #define MASK_CMPB OPTION_MASK_CMPB
649 #define MASK_CRYPTO OPTION_MASK_CRYPTO
650 #define MASK_DFP OPTION_MASK_DFP
651 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
652 #define MASK_DLMZB OPTION_MASK_DLMZB
653 #define MASK_EABI OPTION_MASK_EABI
654 #define MASK_FLOAT128_TYPE OPTION_MASK_FLOAT128_TYPE
655 #define MASK_FPRND OPTION_MASK_FPRND
656 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
657 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
658 #define MASK_HTM OPTION_MASK_HTM
659 #define MASK_ISEL OPTION_MASK_ISEL
660 #define MASK_MFCRF OPTION_MASK_MFCRF
661 #define MASK_MFPGPR OPTION_MASK_MFPGPR
662 #define MASK_MULHW OPTION_MASK_MULHW
663 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
664 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
665 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
666 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
667 #define MASK_P9_MISC OPTION_MASK_P9_MISC
668 #define MASK_POPCNTB OPTION_MASK_POPCNTB
669 #define MASK_POPCNTD OPTION_MASK_POPCNTD
670 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
671 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
672 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
673 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
674 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
675 #define MASK_STRING OPTION_MASK_STRING
676 #define MASK_UPDATE OPTION_MASK_UPDATE
677 #define MASK_VSX OPTION_MASK_VSX
678 #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
680 #ifndef IN_LIBGCC2
681 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
682 #endif
684 #ifdef TARGET_64BIT
685 #define MASK_64BIT OPTION_MASK_64BIT
686 #endif
688 #ifdef TARGET_LITTLE_ENDIAN
689 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
690 #endif
692 #ifdef TARGET_REGNAMES
693 #define MASK_REGNAMES OPTION_MASK_REGNAMES
694 #endif
696 #ifdef TARGET_PROTOTYPE
697 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
698 #endif
700 #ifdef TARGET_MODULO
701 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
702 #endif
705 /* For power systems, we want to enable Altivec and VSX builtins even if the
706 user did not use -maltivec or -mvsx to allow the builtins to be used inside
707 of #pragma GCC target or the target attribute to change the code level for a
708 given system. The SPE and Paired builtins are only enabled if you configure
709 the compiler for those builtins, and those machines don't support altivec or
710 VSX. */
712 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
713 && ((TARGET_POWERPC64 \
718 || TARGET_ALTIVEC \
719 || TARGET_VSX \
720 || TARGET_HARD_FLOAT)))
722 /* E500 cores only support plain "sync", not lwsync. */
723 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
724 || rs6000_cpu == PROCESSOR_PPC8548)
727 /* Whether SF/DF operations are supported on the E500. */
728 #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
729 && !TARGET_FPRS)
731 #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
732 && !TARGET_FPRS && TARGET_E500_DOUBLE)
734 /* Whether SF/DF operations are supported by the normal floating point unit
735 (or the vector/scalar unit). */
736 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
737 && TARGET_SINGLE_FLOAT)
739 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
740 && TARGET_DOUBLE_FLOAT)
742 /* Whether SF/DF operations are supported by any hardware. */
743 #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
744 #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
746 /* Which machine supports the various reciprocal estimate instructions. */
747 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
748 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
750 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
751 && TARGET_DOUBLE_FLOAT \
752 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
754 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
755 && TARGET_PPC_GFXOPT && TARGET_FPRS \
756 && TARGET_SINGLE_FLOAT)
758 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
759 && TARGET_DOUBLE_FLOAT \
760 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
762 /* Conditions to allow TOC fusion for loading/storing integers. */
763 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
764 && TARGET_TOC_FUSION \
765 && (TARGET_CMODEL != CMODEL_SMALL) \
766 && TARGET_POWERPC64)
768 /* Conditions to allow TOC fusion for loading/storing floating point. */
769 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
770 && TARGET_TOC_FUSION \
771 && (TARGET_CMODEL != CMODEL_SMALL) \
772 && TARGET_POWERPC64 \
773 && TARGET_HARD_FLOAT \
774 && TARGET_FPRS \
775 && TARGET_SINGLE_FLOAT \
776 && TARGET_DOUBLE_FLOAT)
778 /* Macro to say whether we can do optimizations where we need to do parts of
779 the calculation in 64-bit GPRs and then is transfered to the vector
780 registers. Do not allow -maltivec=be for these optimizations, because it
781 adds to the complexity of the code. */
782 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
783 && TARGET_P8_VECTOR \
784 && TARGET_POWERPC64 \
785 && TARGET_UPPER_REGS_DI \
786 && (rs6000_altivec_element_order != 2))
788 /* Whether the various reciprocal divide/square root estimate instructions
789 exist, and whether we should automatically generate code for the instruction
790 by default. */
798 #define RS6000_RECIP_HAVE_RE_P(MODE) \
799 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
801 #define RS6000_RECIP_AUTO_RE_P(MODE) \
802 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
804 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
805 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
807 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
808 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
810 /* The default CPU for TARGET_OPTION_OVERRIDE. */
811 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
813 /* Target pragma. */
814 #define REGISTER_TARGET_PRAGMAS() do { \
816 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
817 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
818 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
819 } while (0)
821 /* Target #defines. */
822 #define TARGET_CPU_CPP_BUILTINS() \
823 rs6000_cpu_cpp_builtins (pfile)
825 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
826 we're compiling for. Some configurations may need to override it. */
827 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
828 do \
829 { \
830 if (BYTES_BIG_ENDIAN) \
831 { \
835 } \
836 else \
837 { \
841 } \
842 } \
843 while (0)
844 \f
845 /* Target machine storage layout. */
847 /* Define this macro if it is advisable to hold scalars in registers
848 in a wider mode than that declared by the program. In such cases,
849 the value is constrained to be within the bounds of the declared
850 type, but kept valid in the wider mode. The signedness of the
851 extension may differ from that of the type. */
853 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
854 if (GET_MODE_CLASS (MODE) == MODE_INT \
855 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
856 (MODE) = TARGET_32BIT ? SImode : DImode;
858 /* Define this if most significant bit is lowest numbered
859 in instructions that operate on numbered bit-fields. */
860 /* That is true on RS/6000. */
861 #define BITS_BIG_ENDIAN 1
863 /* Define this if most significant byte of a word is the lowest numbered. */
864 /* That is true on RS/6000. */
865 #define BYTES_BIG_ENDIAN 1
867 /* Define this if most significant word of a multiword number is lowest
868 numbered.
870 For RS/6000 we can decide arbitrarily since there are no machine
871 instructions for them. Might as well be consistent with bits and bytes. */
872 #define WORDS_BIG_ENDIAN 1
874 /* This says that for the IBM long double the larger magnitude double
875 comes first. It's really a two element double array, and arrays
876 don't index differently between little- and big-endian. */
877 #define LONG_DOUBLE_LARGE_FIRST 1
879 #define MAX_BITS_PER_WORD 64
881 /* Width of a word, in units (bytes). */
882 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
883 #ifdef IN_LIBGCC2
884 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
885 #else
886 #define MIN_UNITS_PER_WORD 4
887 #endif
888 #define UNITS_PER_FP_WORD 8
889 #define UNITS_PER_ALTIVEC_WORD 16
890 #define UNITS_PER_VSX_WORD 16
891 #define UNITS_PER_SPE_WORD 8
892 #define UNITS_PER_PAIRED_WORD 8
894 /* Type used for ptrdiff_t, as a string used in a declaration. */
897 /* Type used for size_t, as a string used in a declaration. */
900 /* Type used for wchar_t, as a string used in a declaration. */
903 /* Width of wchar_t in bits. */
904 #define WCHAR_TYPE_SIZE 16
906 /* A C expression for the size in bits of the type `short' on the
907 target machine. If you don't define this, the default is half a
908 word. (If this would be less than one storage unit, it is
909 rounded up to one unit.) */
910 #define SHORT_TYPE_SIZE 16
912 /* A C expression for the size in bits of the type `int' on the
913 target machine. If you don't define this, the default is one
914 word. */
915 #define INT_TYPE_SIZE 32
917 /* A C expression for the size in bits of the type `long' on the
918 target machine. If you don't define this, the default is one
919 word. */
920 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
922 /* A C expression for the size in bits of the type `long long' on the
923 target machine. If you don't define this, the default is two
924 words. */
925 #define LONG_LONG_TYPE_SIZE 64
927 /* A C expression for the size in bits of the type `float' on the
928 target machine. If you don't define this, the default is one
929 word. */
930 #define FLOAT_TYPE_SIZE 32
932 /* A C expression for the size in bits of the type `double' on the
933 target machine. If you don't define this, the default is two
934 words. */
935 #define DOUBLE_TYPE_SIZE 64
937 /* A C expression for the size in bits of the type `long double' on
938 the target machine. If you don't define this, the default is two
939 words. */
940 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
942 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
943 #define WIDEST_HARDWARE_FP_SIZE 64
945 /* Width in bits of a pointer.
946 See also the macro `Pmode' defined below. */
948 #define POINTER_SIZE rs6000_pointer_size
950 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
951 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
953 /* Boundary (in *bits*) on which stack pointer should be aligned. */
954 #define STACK_BOUNDARY \
955 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
956 ? 64 : 128)
958 /* Allocation boundary (in *bits*) for the code of a function. */
959 #define FUNCTION_BOUNDARY 32
961 /* No data type wants to be aligned rounder than this. */
962 #define BIGGEST_ALIGNMENT 128
964 /* Alignment of field after `int : 0' in a structure. */
965 #define EMPTY_FIELD_BOUNDARY 32
967 /* Every structure's size must be a multiple of this. */
968 #define STRUCTURE_SIZE_BOUNDARY 8
970 /* A bit-field declared as `int' forces `int' alignment for the struct. */
971 #define PCC_BITFIELD_TYPE_MATTERS 1
975 /* A C expression to compute the alignment for a variables in the
976 local store. TYPE is the data type, and ALIGN is the alignment
977 that the object would ordinarily have. */
978 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
979 rs6000_data_alignment (TYPE, ALIGN, align_both)
981 /* Make strings word-aligned so strcpy from constants will be faster. */
982 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
983 (TREE_CODE (EXP) == STRING_CST \
984 && (STRICT_ALIGNMENT || !optimize_size) \
985 && (ALIGN) < BITS_PER_WORD \
986 ? BITS_PER_WORD \
987 : (ALIGN))
989 /* Make arrays of chars word-aligned for the same reasons. */
990 #define DATA_ALIGNMENT(TYPE, ALIGN) \
991 rs6000_data_alignment (TYPE, ALIGN, align_opt)
993 /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
994 64 bits. */
995 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
996 rs6000_data_alignment (TYPE, ALIGN, align_abi)
998 /* Nonzero if move instructions will actually fail to work
999 when given unaligned data. */
1000 #define STRICT_ALIGNMENT 0
1002 /* Define this macro to be the value 1 if unaligned accesses have a cost
1003 many times greater than aligned accesses, for example if they are
1004 emulated in a trap handler. */
1005 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
1006 memory instructions trap on unaligned accesses; VSX memory instructions are
1007 aligned to 4 or 8 bytes. */
1008 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
1009 (STRICT_ALIGNMENT \
1010 || (!TARGET_EFFICIENT_UNALIGNED_VSX \
1011 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) && (ALIGN) < 32) \
1012 || ((VECTOR_MODE_P (MODE) || FLOAT128_VECTOR_P (MODE)) \
1013 && (int) (ALIGN) < VECTOR_ALIGN (MODE)))))
1015 \f
1016 /* Standard register usage. */
1018 /* Number of actual hardware registers.
1019 The hardware registers are assigned numbers for the compiler
1020 from 0 to just below FIRST_PSEUDO_REGISTER.
1021 All registers that the compiler knows about must be given numbers,
1022 even those that are not normally considered general registers.
1024 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
1025 a count register, a link register, and 8 condition register fields,
1026 which we view here as separate registers. AltiVec adds 32 vector
1027 registers and a VRsave register.
1029 In addition, the difference between the frame and argument pointers is
1030 a function of the number of registers saved, so we need to have a
1031 register for AP that will later be eliminated in favor of SP or FP.
1032 This is a normal register, but it is fixed.
1034 We also create a pseudo register for float/int conversions, that will
1035 really represent the memory location used. It is represented here as
1036 a register, in order to work around problems in allocating stack storage
1037 in inline functions.
1039 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
1040 pointer, which is eventually eliminated in favor of SP or FP.
1042 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
1044 #define FIRST_PSEUDO_REGISTER 149
1046 /* This must be included for pre gcc 3.0 glibc compatibility. */
1047 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
1049 /* True if register is an SPE High register. */
1050 #define SPE_HIGH_REGNO_P(N) \
1051 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
1053 /* SPE high registers added as hard regs.
1054 The sfp register and 3 HTM registers
1055 aren't included in DWARF_FRAME_REGISTERS. */
1056 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
1058 /* The SPE has an additional 32 synthetic registers, with DWARF debug
1059 info numbering for these registers starting at 1200. While eh_frame
1060 register numbering need not be the same as the debug info numbering,
1061 we choose to number these regs for eh_frame at 1200 too.
1063 We must map them here to avoid huge unwinder tables mostly consisting
1064 of unused space. */
1065 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
1066 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
1068 /* Use standard DWARF numbering for DWARF debugging information. */
1069 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
1071 /* Use gcc hard register numbering for eh_frame. */
1072 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
1074 /* Map register numbers held in the call frame info that gcc has
1075 collected using DWARF_FRAME_REGNUM to those that should be output in
1076 .debug_frame and .eh_frame. */
1077 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
1078 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
1080 /* 1 for registers that have pervasive standard uses
1081 and are not available for the register allocator.
1083 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
1084 as a local register; for all other OS's r2 is the TOC pointer.
1086 On System V implementations, r13 is fixed and not available for use. */
1088 #define FIXED_REGISTERS \
1089 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
1090 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1091 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1092 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1093 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
1095 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1096 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1097 1, 1 \
1098 , 1, 1, 1, 1, 1, 1, \
1100 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1102 }
1104 /* 1 for registers not available across function calls.
1105 These must include the FIXED_REGISTERS and also any
1106 registers that can be used without being saved.
1107 The latter must include the registers where values are returned
1108 and the register where structure-value addresses are passed.
1109 Aside from that, you can include as many other registers as you like. */
1111 #define CALL_USED_REGISTERS \
1112 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1114 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1115 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1116 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1118 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1120 1, 1 \
1121 , 1, 1, 1, 1, 1, 1, \
1123 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1124 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1125 }
1127 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
1128 the entire set of `FIXED_REGISTERS' be included.
1129 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
1130 This macro is optional. If not specified, it defaults to the value
1131 of `CALL_USED_REGISTERS'. */
1133 #define CALL_REALLY_USED_REGISTERS \
1134 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1135 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1136 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1138 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1142 0, 0 \
1143 , 0, 0, 0, 0, 0, 0, \
1145 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1147 }
1149 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1151 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1152 #define FIRST_SAVED_FP_REGNO (14+32)
1153 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1155 /* List the order in which to allocate registers. Each register must be
1156 listed once, even those in FIXED_REGISTERS.
1158 We allocate in the following order:
1159 fp0 (not saved or used for anything)
1160 fp13 - fp2 (not saved; incoming fp arg registers)
1161 fp1 (not saved; return value)
1162 fp31 - fp14 (saved; order given to save least number)
1163 cr7, cr5 (not saved or special)
1164 cr6 (not saved, but used for vector operations)
1165 cr1 (not saved, but used for FP operations)
1166 cr0 (not saved, but used for arithmetic operations)
1167 cr4, cr3, cr2 (saved)
1168 r9 (not saved; best for TImode)
1169 r10, r8-r4 (not saved; highest first for less conflict with params)
1170 r3 (not saved; return value register)
1171 r11 (not saved; later alloc to help shrink-wrap)
1172 r0 (not saved; cannot be base reg)
1173 r31 - r13 (saved; order given to save least number)
1174 r12 (not saved; if used for DImode or DFmode would use r13)
1175 ctr (not saved; when we have the choice ctr is better)
1176 lr (saved)
1177 r1, r2, ap, ca (fixed)
1178 v0 - v1 (not saved or used for anything)
1179 v13 - v3 (not saved; incoming vector arg registers)
1180 v2 (not saved; incoming vector arg reg; return value)
1181 v19 - v14 (not saved or used for anything)
1182 v31 - v20 (saved; order given to save least number)
1183 vrsave, vscr (fixed)
1184 spe_acc, spefscr (fixed)
1185 sfp (fixed)
1186 tfhar (fixed)
1187 tfiar (fixed)
1188 texasr (fixed)
1189 */
1191 #if FIXED_R2 == 1
1192 #define MAYBE_R2_AVAILABLE
1193 #define MAYBE_R2_FIXED 2,
1194 #else
1195 #define MAYBE_R2_AVAILABLE 2,
1196 #define MAYBE_R2_FIXED
1197 #endif
1199 #if FIXED_R13 == 1
1200 #define EARLY_R12 12,
1201 #define LATE_R12
1202 #else
1203 #define EARLY_R12
1204 #define LATE_R12 12,
1205 #endif
1207 #define REG_ALLOC_ORDER \
1208 {32, \
1211 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1212 33, \
1213 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1214 50, 49, 48, 47, 46, \
1215 75, 73, 74, 69, 68, 72, 71, 70, \
1216 MAYBE_R2_AVAILABLE \
1217 9, 10, 8, 7, 6, 5, 4, \
1218 3, EARLY_R12 11, 0, \
1219 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1220 18, 17, 16, 15, 14, 13, LATE_R12 \
1221 66, 65, \
1222 1, MAYBE_R2_FIXED 67, 76, \
1224 77, 78, \
1225 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1226 79, \
1227 96, 95, 94, 93, 92, 91, \
1228 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1229 109, 110, \
1230 111, 112, 113, 114, 115, 116, \
1231 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
1232 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
1233 141, 142, 143, 144, 145, 146, 147, 148 \
1234 }
1236 /* True if register is floating-point. */
1237 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1239 /* True if register is a condition register. */
1240 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1242 /* True if register is a condition register, but not cr0. */
1243 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1245 /* True if register is an integer register. */
1246 #define INT_REGNO_P(N) \
1247 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1249 /* SPE SIMD registers are just the GPRs. */
1250 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1252 /* PAIRED SIMD registers are just the FPRs. */
1253 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1255 /* True if register is the CA register. */
1256 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1258 /* True if register is an AltiVec register. */
1259 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1261 /* True if register is a VSX register. */
1262 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1264 /* Alternate name for any vector register supporting floating point, no matter
1265 which instruction set(s) are available. */
1266 #define VFLOAT_REGNO_P(N) \
1267 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1269 /* Alternate name for any vector register supporting integer, no matter which
1270 instruction set(s) are available. */
1271 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1273 /* Alternate name for any vector register supporting logical operations, no
1274 matter which instruction set(s) are available. Allow GPRs as well as the
1275 vector registers. */
1276 #define VLOGICAL_REGNO_P(N) \
1277 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1278 || (TARGET_VSX && FP_REGNO_P (N))) \
1280 /* Return number of consecutive hard regs needed starting at reg REGNO
1281 to hold something of mode MODE. */
1283 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1285 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1286 enough space to account for vectors in FP regs. However, TFmode/TDmode
1287 should not use VSX instructions to do a caller save. */
1288 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1289 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1290 ? (MODE) \
1291 : TARGET_VSX \
1292 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1293 && FP_REGNO_P (REGNO) \
1294 ? V2DFmode \
1295 : TARGET_E500_DOUBLE && (MODE) == SImode \
1296 ? SImode \
1297 : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \
1298 ? DFmode \
1299 : !TARGET_E500_DOUBLE && FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1300 ? DFmode \
1301 : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \
1302 ? DImode \
1303 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1305 #define VSX_VECTOR_MODE(MODE) \
1306 ((MODE) == V4SFmode \
1307 || (MODE) == V2DFmode) \
1309 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1310 really a vector, but we want to treat it as a vector for moves, and
1311 such. */
1313 #define ALTIVEC_VECTOR_MODE(MODE) \
1314 ((MODE) == V16QImode \
1315 || (MODE) == V8HImode \
1316 || (MODE) == V4SFmode \
1317 || (MODE) == V4SImode \
1318 || FLOAT128_VECTOR_P (MODE))
1320 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1321 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1322 || (MODE) == V2DImode || (MODE) == V1TImode)
1324 #define SPE_VECTOR_MODE(MODE) \
1325 ((MODE) == V4HImode \
1326 || (MODE) == V2SFmode \
1327 || (MODE) == V1DImode \
1328 || (MODE) == V2SImode)
1330 #define PAIRED_VECTOR_MODE(MODE) \
1331 ((MODE) == V2SFmode)
1333 /* Value is TRUE if hard register REGNO can hold a value of
1334 machine-mode MODE. */
1335 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1336 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1338 /* Value is 1 if it is a good idea to tie two pseudo registers
1339 when one has mode MODE1 and one has mode MODE2.
1340 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1341 for any hard reg, then this must be 0 for correct output.
1343 PTImode cannot tie with other modes because PTImode is restricted to even
1344 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
1345 57744).
1347 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
1348 128-bit floating point on VSX systems ties with other vectors. */
1349 #define MODES_TIEABLE_P(MODE1, MODE2) \
1350 ((MODE1) == PTImode \
1351 ? (MODE2) == PTImode \
1352 : (MODE2) == PTImode \
1353 ? 0 \
1354 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1355 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1356 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1357 ? 0 \
1358 : SCALAR_FLOAT_MODE_P (MODE1) \
1359 ? SCALAR_FLOAT_MODE_P (MODE2) \
1360 : SCALAR_FLOAT_MODE_P (MODE2) \
1361 ? 0 \
1362 : GET_MODE_CLASS (MODE1) == MODE_CC \
1363 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1364 : GET_MODE_CLASS (MODE2) == MODE_CC \
1365 ? 0 \
1366 : SPE_VECTOR_MODE (MODE1) \
1367 ? SPE_VECTOR_MODE (MODE2) \
1368 : SPE_VECTOR_MODE (MODE2) \
1369 ? 0 \
1370 : 1)
1372 /* Post-reload, we can't use any new AltiVec registers, as we already
1373 emitted the vrsave mask. */
1375 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1376 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1378 /* Specify the cost of a branch insn; roughly the number of extra insns that
1379 should be added to avoid a branch.
1381 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1382 unscheduled conditional branch. */
1384 #define BRANCH_COST(speed_p, predictable_p) 3
1386 /* Override BRANCH_COST heuristic which empirically produces worse
1387 performance for removing short circuiting from the logical ops. */
1389 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1391 /* A fixed register used at epilogue generation to address SPE registers
1392 with negative offsets. The 64-bit load/store instructions on the SPE
1393 only take positive offsets (and small ones at that), so we need to
1394 reserve a register for consing up negative offsets. */
1396 #define FIXED_SCRATCH 0
1398 /* Specify the registers used for certain standard purposes.
1399 The values of these macros are register numbers. */
1401 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1402 /* #define PC_REGNUM */
1404 /* Register to use for pushing function arguments. */
1405 #define STACK_POINTER_REGNUM 1
1407 /* Base register for access to local variables of the function. */
1408 #define HARD_FRAME_POINTER_REGNUM 31
1410 /* Base register for access to local variables of the function. */
1411 #define FRAME_POINTER_REGNUM 113
1413 /* Base register for access to arguments of the function. */
1414 #define ARG_POINTER_REGNUM 67
1416 /* Place to put static chain when calling a function that requires it. */
1417 #define STATIC_CHAIN_REGNUM 11
1419 /* Base register for access to thread local storage variables. */
1420 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1422 \f
1423 /* Define the classes of registers for register constraints in the
1424 machine description. Also define ranges of constants.
1426 One of the classes must always be named ALL_REGS and include all hard regs.
1427 If there is more than one class, another class must be named NO_REGS
1428 and contain no registers.
1430 The name GENERAL_REGS must be the name of a class (or an alias for
1431 another name such as ALL_REGS). This is the class of registers
1432 that is allowed by "g" or "r" in a register constraint.
1433 Also, registers outside this class are allocated only when
1434 instructions express preferences for them.
1436 The classes must be numbered in nondecreasing order; that is,
1437 a larger-numbered class must never be contained completely
1438 in a smaller-numbered class.
1440 For any two classes, it is very desirable that there be another
1441 class that represents their union. */
1443 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1444 condition registers, plus three special registers, CTR, and the link
1445 register. AltiVec adds a vector register class. VSX registers overlap the
1446 FPR registers and the Altivec registers.
1448 However, r0 is special in that it cannot be used as a base register.
1449 So make a class for registers valid as base registers.
1451 Also, cr0 is the only condition code register that can be used in
1452 arithmetic insns, so make a separate class for it. */
1454 enum reg_class
1455 {
1456 NO_REGS,
1457 BASE_REGS,
1458 GENERAL_REGS,
1459 FLOAT_REGS,
1460 ALTIVEC_REGS,
1461 VSX_REGS,
1462 VRSAVE_REGS,
1463 VSCR_REGS,
1464 SPE_ACC_REGS,
1465 SPEFSCR_REGS,
1466 SPR_REGS,
1467 NON_SPECIAL_REGS,
1468 LINK_REGS,
1469 CTR_REGS,
1470 LINK_OR_CTR_REGS,
1471 SPECIAL_REGS,
1472 SPEC_OR_GEN_REGS,
1473 CR0_REGS,
1474 CR_REGS,
1475 NON_FLOAT_REGS,
1476 CA_REGS,
1477 SPE_HIGH_REGS,
1478 ALL_REGS,
1479 LIM_REG_CLASSES
1480 };
1482 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1484 /* Give names of register classes as strings for dump file. */
1486 #define REG_CLASS_NAMES \
1487 { \
1511 }
1513 /* Define which registers fit in which classes.
1514 This is an initializer for a vector of HARD_REG_SET
1515 of length N_REG_CLASSES. */
1517 #define REG_CLASS_CONTENTS \
1518 { \
1520 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1522 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1524 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1526 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
1528 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
1530 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
1532 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
1534 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
1536 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
1538 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
1540 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
1542 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
1544 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
1546 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
1548 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
1550 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
1552 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
1554 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
1556 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
1558 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
1560 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
1562 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
1564 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
1565 }
1567 /* The same information, inverted:
1568 Return the class number of the smallest class containing
1569 reg number REGNO. This could be a conditional expression
1570 or could index an array. */
1574 #define REGNO_REG_CLASS(REGNO) \
1575 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1576 rs6000_regno_regclass[(REGNO)])
1578 /* Register classes for various constraints that are based on the target
1579 switches. */
1613 RS6000_CONSTRAINT_MAX
1614 };
1618 /* The class value for index registers, and the one for base regs. */
1619 #define INDEX_REG_CLASS GENERAL_REGS
1620 #define BASE_REG_CLASS BASE_REGS
1622 /* Return whether a given register class can hold VSX objects. */
1623 #define VSX_REG_CLASS_P(CLASS) \
1624 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1626 /* Return whether a given register class targets general purpose registers. */
1627 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1629 /* Given an rtx X being reloaded into a reg required to be
1630 in class CLASS, return the class of reg to actually use.
1631 In general this is just CLASS; but on some machines
1632 in some cases it is preferable to use a more restrictive class.
1634 On the RS/6000, we have to return NO_REGS when we want to reload a
1635 floating-point CONST_DOUBLE to force it to be copied to memory.
1637 We also don't want to reload integer values into floating-point
1638 registers if we can at all help it. In fact, this can
1639 cause reload to die, if it tries to generate a reload of CTR
1640 into a FP register and discovers it doesn't have the memory location
1641 required.
1643 ??? Would it be a good idea to have reload do the converse, that is
1644 try to reload floating modes into FP registers if possible?
1645 */
1647 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1648 rs6000_preferred_reload_class_ptr (X, CLASS)
1650 /* Return the register class of a scratch register needed to copy IN into
1651 or out of a register in CLASS in MODE. If it can be done directly,
1652 NO_REGS is returned. */
1654 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1655 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1657 /* If we are copying between FP or AltiVec registers and anything
1658 else, we need a memory location. The exception is when we are
1659 targeting ppc64 and the move to/from fpr to gpr instructions
1660 are available.*/
1662 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1663 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1665 /* For cpus that cannot load/store SDmode values from the 64-bit
1666 FP registers without using a full 64-bit load/store, we need
1667 to allocate a full 64-bit stack slot for them. */
1669 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1670 rs6000_secondary_memory_needed_rtx (MODE)
1672 /* Specify the mode to be used for memory when a secondary memory
1673 location is needed. For cpus that cannot load/store SDmode values
1674 from the 64-bit FP registers without using a full 64-bit
1675 load/store, we need a wider mode. */
1676 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1677 rs6000_secondary_memory_needed_mode (MODE)
1679 /* Return the maximum number of consecutive registers
1680 needed to represent mode MODE in a register of class CLASS.
1682 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1683 a single reg is enough for two words, unless we have VSX, where the FP
1684 registers can hold 128 bits. */
1685 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1687 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1689 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1690 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1692 /* Stack layout; function entry, exit and calling. */
1694 /* Define this if pushing a word on the stack
1695 makes the stack pointer a smaller address. */
1696 #define STACK_GROWS_DOWNWARD 1
1698 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1699 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1701 /* Define this to nonzero if the nominal address of the stack frame
1702 is at the high-address end of the local variables;
1703 that is, each additional local variable allocated
1704 goes at a more negative offset in the frame.
1706 On the RS/6000, we grow upwards, from the area after the outgoing
1707 arguments. */
1708 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1709 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1711 /* Size of the fixed area on the stack */
1712 #define RS6000_SAVE_AREA \
1713 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1714 << (TARGET_64BIT ? 1 : 0))
1716 /* Stack offset for toc save slot. */
1717 #define RS6000_TOC_SAVE_SLOT \
1718 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1720 /* Align an address */
1721 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1723 /* Offset within stack frame to start allocating local variables at.
1724 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1725 first local allocated. Otherwise, it is the offset to the BEGINNING
1726 of the first local allocated.
1728 On the RS/6000, the frame pointer is the same as the stack pointer,
1729 except for dynamic allocations. So we start after the fixed area and
1730 outgoing parameter area.
1732 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1733 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1734 sizes of the fixed area and the parameter area must be a multiple of
1735 STACK_BOUNDARY. */
1737 #define STARTING_FRAME_OFFSET \
1738 (FRAME_GROWS_DOWNWARD \
1739 ? 0 \
1740 : (cfun->calls_alloca \
1741 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1742 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1743 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1744 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1745 + RS6000_SAVE_AREA)))
1747 /* Offset from the stack pointer register to an item dynamically
1748 allocated on the stack, e.g., by `alloca'.
1750 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1751 length of the outgoing arguments. The default is correct for most
1752 machines. See `function.c' for details.
1754 This value must be a multiple of STACK_BOUNDARY (hard coded in
1755 `emit-rtl.c'). */
1756 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1757 RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \
1758 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1760 /* If we generate an insn to push BYTES bytes,
1761 this says how many the stack pointer really advances by.
1762 On RS/6000, don't define this because there are no push insns. */
1763 /* #define PUSH_ROUNDING(BYTES) */
1765 /* Offset of first parameter from the argument pointer register value.
1766 On the RS/6000, we define the argument pointer to the start of the fixed
1767 area. */
1768 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1770 /* Offset from the argument pointer register value to the top of
1771 stack. This is different from FIRST_PARM_OFFSET because of the
1772 register save area. */
1773 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1775 /* Define this if stack space is still allocated for a parameter passed
1776 in a register. The value is the number of bytes allocated to this
1777 area. */
1778 #define REG_PARM_STACK_SPACE(FNDECL) \
1779 rs6000_reg_parm_stack_space ((FNDECL), false)
1781 /* Define this macro if space guaranteed when compiling a function body
1782 is different to space required when making a call, a situation that
1783 can arise with K&R style function definitions. */
1784 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1785 rs6000_reg_parm_stack_space ((FNDECL), true)
1787 /* Define this if the above stack space is to be considered part of the
1788 space allocated by the caller. */
1789 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1791 /* This is the difference between the logical top of stack and the actual sp.
1793 For the RS/6000, sp points past the fixed area. */
1794 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1796 /* Define this if the maximum size of all the outgoing args is to be
1797 accumulated and pushed during the prologue. The amount can be
1798 found in the variable crtl->outgoing_args_size. */
1799 #define ACCUMULATE_OUTGOING_ARGS 1
1801 /* Define how to find the value returned by a library function
1802 assuming the value has mode MODE. */
1804 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1806 /* DRAFT_V4_STRUCT_RET defaults off. */
1807 #define DRAFT_V4_STRUCT_RET 0
1809 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1810 #define DEFAULT_PCC_STRUCT_RETURN 0
1812 /* Mode of stack savearea.
1813 FUNCTION is VOIDmode because calling convention maintains SP.
1814 BLOCK needs Pmode for SP.
1815 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1816 #define STACK_SAVEAREA_MODE(LEVEL) \
1817 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1818 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1820 /* Minimum and maximum general purpose registers used to hold arguments. */
1821 #define GP_ARG_MIN_REG 3
1822 #define GP_ARG_MAX_REG 10
1823 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1825 /* Minimum and maximum floating point registers used to hold arguments. */
1826 #define FP_ARG_MIN_REG 33
1827 #define FP_ARG_AIX_MAX_REG 45
1828 #define FP_ARG_V4_MAX_REG 40
1829 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1830 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1831 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1833 /* Minimum and maximum AltiVec registers used to hold arguments. */
1834 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1835 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1836 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1838 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1839 #define AGGR_ARG_NUM_REG 8
1841 /* Return registers */
1842 #define GP_ARG_RETURN GP_ARG_MIN_REG
1843 #define FP_ARG_RETURN FP_ARG_MIN_REG
1844 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1845 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1846 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1847 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1848 ? (ALTIVEC_ARG_RETURN \
1849 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1850 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1852 /* Flags for the call/call_value rtl operations set up by function_arg */
1854 /* Bits in 0x00000001 are unused. */
1860 /* We don't have prologue and epilogue functions to save/restore
1861 everything for most ABIs. */
1862 #define WORLD_SAVE_P(INFO) 0
1864 /* 1 if N is a possible register number for a function value
1865 as seen by the caller.
1867 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1868 #define FUNCTION_VALUE_REGNO_P(N) \
1869 ((N) == GP_ARG_RETURN \
1870 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1871 && TARGET_HARD_FLOAT && TARGET_FPRS) \
1872 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1873 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1875 /* 1 if N is a possible register number for function argument passing.
1876 On RS/6000, these are r3-r10 and fp1-fp13.
1877 On AltiVec, v2 - v13 are used for passing vectors. */
1878 #define FUNCTION_ARG_REGNO_P(N) \
1879 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1880 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1881 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1882 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1883 && TARGET_HARD_FLOAT && TARGET_FPRS))
1884 \f
1885 /* Define a data type for recording info about an argument list
1886 during the scan of that argument list. This data type should
1887 hold all necessary information about the function itself
1888 and about the args processed so far, enough to enable macros
1889 such as FUNCTION_ARG to determine where the next arg should go.
1891 On the RS/6000, this is a structure. The first element is the number of
1892 total argument words, the second is used to store the next
1893 floating-point register number, and the third says how many more args we
1894 have prototype types for.
1896 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1897 the next available GP register, `fregno' is the next available FP
1898 register, and `words' is the number of words used on the stack.
1900 The varargs/stdarg support requires that this structure's size
1901 be a multiple of sizeof(int). */
1904 {
1916 GPR space (darwin64) */
1922 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1923 for a call to a function whose data type is FNTYPE.
1924 For a library call, FNTYPE is 0. */
1926 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1927 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1928 N_NAMED_ARGS, FNDECL, VOIDmode)
1930 /* Similar, but when scanning the definition of a procedure. We always
1931 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1933 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1934 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1935 1000, current_function_decl, VOIDmode)
1937 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1939 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1940 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1941 0, NULL_TREE, MODE)
1943 /* If defined, a C expression which determines whether, and in which
1944 direction, to pad out an argument with extra space. The value
1945 should be of type `enum direction': either `upward' to pad above
1946 the argument, `downward' to pad below, or `none' to inhibit
1947 padding. */
1949 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1951 #define PAD_VARARGS_DOWN \
1952 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1954 /* Output assembler code to FILE to increment profiler label # LABELNO
1955 for profiling a function entry. */
1957 #define FUNCTION_PROFILER(FILE, LABELNO) \
1958 output_function_profiler ((FILE), (LABELNO));
1960 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1961 the stack pointer does not matter. No definition is equivalent to
1962 always zero.
1964 On the RS/6000, this is nonzero because we can restore the stack from
1965 its backpointer, which we maintain. */
1966 #define EXIT_IGNORE_STACK 1
1968 /* Define this macro as a C expression that is nonzero for registers
1969 that are used by the epilogue or the return' pattern. The stack
1970 and frame pointer registers are already be assumed to be used as
1971 needed. */
1973 #define EPILOGUE_USES(REGNO) \
1974 ((reload_completed && (REGNO) == LR_REGNO) \
1975 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1976 || (crtl->calls_eh_return \
1977 && TARGET_AIX \
1978 && (REGNO) == 2))
1980 \f
1981 /* Length in units of the trampoline for entering a nested function. */
1983 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1984 \f
1985 /* Definitions for __builtin_return_address and __builtin_frame_address.
1986 __builtin_return_address (0) should give link register (LR_REGNO), enable
1987 this. */
1988 /* This should be uncommented, so that the link register is used, but
1989 currently this would result in unmatched insns and spilling fixed
1990 registers so we'll leave it for another day. When these problems are
1991 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1992 (mrs) */
1993 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1995 /* Number of bytes into the frame return addresses can be found. See
1996 rs6000_stack_info in powerpcspe.c for more information on how the different
1997 abi's store the return address. */
1998 #define RETURN_ADDRESS_OFFSET \
1999 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
2001 /* The current return address is in link register (65). The return address
2002 of anything farther back is accessed normally at an offset of 8 from the
2003 frame pointer. */
2004 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2005 (rs6000_return_addr (COUNT, FRAME))
2007 \f
2008 /* Definitions for register eliminations.
2010 We have two registers that can be eliminated on the RS/6000. First, the
2011 frame pointer register can often be eliminated in favor of the stack
2012 pointer register. Secondly, the argument pointer register can always be
2013 eliminated; it is replaced with either the stack or frame pointer.
2015 In addition, we use the elimination mechanism to see if r30 is needed
2016 Initially we assume that it isn't. If it is, we spill it. This is done
2017 by making it an eliminable register. We replace it with itself so that
2018 if it isn't needed, then existing uses won't be modified. */
2020 /* This is an array of structures. Each structure initializes one pair
2021 of eliminable registers. The "from" register number is given first,
2022 followed by "to". Eliminations of the same "from" register are listed
2023 in order of preference. */
2024 #define ELIMINABLE_REGS \
2025 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2026 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2027 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
2028 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2029 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
2030 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
2032 /* Define the offset between two registers, one to be eliminated, and the other
2033 its replacement, at the start of a routine. */
2034 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2035 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
2036 \f
2037 /* Addressing modes, and classification of registers for them. */
2039 #define HAVE_PRE_DECREMENT 1
2040 #define HAVE_PRE_INCREMENT 1
2041 #define HAVE_PRE_MODIFY_DISP 1
2042 #define HAVE_PRE_MODIFY_REG 1
2044 /* Macros to check register numbers against specific register classes. */
2046 /* These assume that REGNO is a hard or pseudo reg number.
2047 They give nonzero only if REGNO is a hard reg of the suitable class
2048 or a pseudo reg currently allocated to a suitable hard reg.
2049 Since they use reg_renumber, they are safe only once reg_renumber
2050 has been allocated, which happens in reginfo.c during register
2051 allocation. */
2053 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2054 ((REGNO) < FIRST_PSEUDO_REGISTER \
2055 ? (REGNO) <= 31 || (REGNO) == 67 \
2056 || (REGNO) == FRAME_POINTER_REGNUM \
2057 : (reg_renumber[REGNO] >= 0 \
2058 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
2059 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
2061 #define REGNO_OK_FOR_BASE_P(REGNO) \
2062 ((REGNO) < FIRST_PSEUDO_REGISTER \
2063 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
2064 || (REGNO) == FRAME_POINTER_REGNUM \
2065 : (reg_renumber[REGNO] > 0 \
2066 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
2067 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
2069 /* Nonzero if X is a hard reg that can be used as an index
2070 or if it is a pseudo reg in the non-strict case. */
2071 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2072 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
2073 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
2075 /* Nonzero if X is a hard reg that can be used as a base reg
2076 or if it is a pseudo reg in the non-strict case. */
2077 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2078 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
2079 || REGNO_OK_FOR_BASE_P (REGNO (X)))
2081 \f
2082 /* Maximum number of registers that can appear in a valid memory address. */
2084 #define MAX_REGS_PER_ADDRESS 2
2086 /* Recognize any constant value that is a valid address. */
2088 #define CONSTANT_ADDRESS_P(X) \
2089 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2090 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2091 || GET_CODE (X) == HIGH)
2093 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
2094 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
2095 && EASY_VECTOR_15((n) >> 1) \
2096 && ((n) & 1) == 0)
2098 #define EASY_VECTOR_MSB(n,mode) \
2099 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
2100 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
2102 \f
2103 /* Try a machine-dependent way of reloading an illegitimate address
2104 operand. If we find one, push the reload and jump to WIN. This
2105 macro is used in only one place: `find_reloads_address' in reload.c.
2107 Implemented on rs6000 by rs6000_legitimize_reload_address.
2108 Note that (X) is evaluated twice; this is safe in current usage. */
2110 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2111 do { \
2112 int win; \
2113 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
2114 (int)(TYPE), (IND_LEVELS), &win); \
2115 if ( win ) \
2116 goto WIN; \
2117 } while (0)
2119 #define FIND_BASE_TERM rs6000_find_base_term
2120 \f
2121 /* The register number of the register used to address a table of
2122 static data addresses in memory. In some cases this register is
2123 defined by a processor's "application binary interface" (ABI).
2124 When this macro is defined, RTL is generated for this register
2125 once, as with the stack pointer and frame pointer registers. If
2126 this macro is not defined, it is up to the machine-dependent files
2127 to allocate such a register (if necessary). */
2129 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2130 #define PIC_OFFSET_TABLE_REGNUM \
2131 (TARGET_TOC ? TOC_REGISTER \
2132 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
2133 : INVALID_REGNUM)
2135 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2137 /* Define this macro if the register defined by
2138 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2139 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2141 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2143 /* A C expression that is nonzero if X is a legitimate immediate
2144 operand on the target machine when generating position independent
2145 code. You can assume that X satisfies `CONSTANT_P', so you need
2146 not check this. You can also assume FLAG_PIC is true, so you need
2147 not check it either. You need not define this macro if all
2148 constants (including `SYMBOL_REF') can be immediate operands when
2149 generating position independent code. */
2151 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2152 \f
2153 /* Define this if some processing needs to be done immediately before
2154 emitting code for an insn. */
2156 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
2157 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
2159 /* Specify the machine mode that this machine uses
2160 for the index in the tablejump instruction. */
2161 #define CASE_VECTOR_MODE SImode
2163 /* Define as C expression which evaluates to nonzero if the tablejump
2164 instruction expects the table to contain offsets from the address of the
2165 table.
2166 Do not define this if the table should contain absolute addresses. */
2167 #define CASE_VECTOR_PC_RELATIVE 1
2169 /* Define this as 1 if `char' should by default be signed; else as 0. */
2170 #define DEFAULT_SIGNED_CHAR 0
2172 /* An integer expression for the size in bits of the largest integer machine
2173 mode that should actually be used. */
2175 /* Allow pairs of registers to be used, which is the intent of the default. */
2176 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
2178 /* Max number of bytes we can move from memory to memory
2179 in one reasonably fast instruction. */
2180 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2181 #define MAX_MOVE_MAX 8
2183 /* Nonzero if access to memory by bytes is no faster than for words.
2184 Also nonzero if doing byte operations (specifically shifts) in registers
2185 is undesirable. */
2186 #define SLOW_BYTE_ACCESS 1
2188 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2189 will either zero-extend or sign-extend. The value of this macro should
2190 be the code that says which one of the two operations is implicitly
2191 done, UNKNOWN if none. */
2192 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2194 /* Define if loading short immediate values into registers sign extends. */
2195 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
2196 \f
2197 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2198 is done just by pretending it is already truncated. */
2199 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2201 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2202 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2203 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
2205 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
2206 zero. The hardware instructions added in Power9 and the sequences using
2207 popcount return 32 or 64. */
2208 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2209 (TARGET_CTZ || TARGET_POPCNTD \
2210 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
2211 : ((VALUE) = -1, 2))
2213 /* Specify the machine mode that pointers have.
2214 After generation of rtl, the compiler makes no further distinction
2215 between pointers and any other objects of this machine mode. */
2217 #define Pmode rs6000_pmode
2219 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2220 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2222 /* Mode of a function address in a call instruction (for indexing purposes).
2223 Doesn't matter on RS/6000. */
2224 #define FUNCTION_MODE SImode
2226 /* Define this if addresses of constant functions
2227 shouldn't be put through pseudo regs where they can be cse'd.
2228 Desirable on machines where ordinary constants are expensive
2229 but a CALL with constant address is cheap. */
2230 #define NO_FUNCTION_CSE 1
2232 /* Define this to be nonzero if shift instructions ignore all but the low-order
2233 few bits.
2235 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2236 have been dropped from the PowerPC architecture. */
2237 #define SHIFT_COUNT_TRUNCATED 0
2239 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2240 should be adjusted to reflect any required changes. This macro is used when
2241 there is some systematic length adjustment required that would be difficult
2242 to express in the length attribute. */
2244 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2246 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2247 COMPARE, return the mode to be used for the comparison. For
2248 floating-point, CCFPmode should be used. CCUNSmode should be used
2249 for unsigned comparisons. CCEQmode should be used when we are
2250 doing an inequality comparison on the result of a
2251 comparison. CCmode should be used in all other cases. */
2253 #define SELECT_CC_MODE(OP,X,Y) \
2254 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2255 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2256 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2257 ? CCEQmode : CCmode))
2259 /* Can the condition code MODE be safely reversed? This is safe in
2260 all cases on this port, because at present it doesn't use the
2261 trapping FP comparisons (fcmpo). */
2262 #define REVERSIBLE_CC_MODE(MODE) 1
2264 /* Given a condition code and a mode, return the inverse condition. */
2265 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2267 \f
2268 /* Control the assembler format that we output. */
2270 /* A C string constant describing how to begin a comment in the target
2271 assembler language. The compiler assumes that the comment will end at
2272 the end of the line. */
2275 /* Flag to say the TOC is initialized */
2278 /* Macro to output a special constant pool entry. Go to WIN if we output
2279 it. Otherwise, it is written the usual way.
2281 On the RS/6000, toc entries are handled this way. */
2283 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2284 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2285 { \
2286 output_toc (FILE, X, LABELNO, MODE); \
2287 goto WIN; \
2288 } \
2289 }
2291 #ifdef HAVE_GAS_WEAK
2292 #define RS6000_WEAK 1
2293 #else
2294 #define RS6000_WEAK 0
2295 #endif
2297 #if RS6000_WEAK
2298 /* Used in lieu of ASM_WEAKEN_LABEL. */
2299 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2300 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
2301 #endif
2303 #if HAVE_GAS_WEAKREF
2304 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2305 do \
2306 { \
2308 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2310 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2311 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2312 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2313 { \
2315 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2317 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2318 } \
2320 } while (0)
2321 #endif
2323 /* This implements the `alias' attribute. */
2324 #undef ASM_OUTPUT_DEF_FROM_DECLS
2325 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2326 do \
2327 { \
2328 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2329 const char *name = IDENTIFIER_POINTER (TARGET); \
2330 if (TREE_CODE (DECL) == FUNCTION_DECL \
2331 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2332 { \
2333 if (TREE_PUBLIC (DECL)) \
2334 { \
2335 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2336 { \
2338 RS6000_OUTPUT_BASENAME (FILE, alias); \
2340 } \
2341 } \
2342 else if (TARGET_XCOFF) \
2343 { \
2344 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2345 { \
2347 RS6000_OUTPUT_BASENAME (FILE, alias); \
2350 RS6000_OUTPUT_BASENAME (FILE, alias); \
2352 } \
2353 } \
2355 RS6000_OUTPUT_BASENAME (FILE, alias); \
2357 RS6000_OUTPUT_BASENAME (FILE, name); \
2359 } \
2360 ASM_OUTPUT_DEF (FILE, alias, name); \
2361 } \
2362 while (0)
2364 #define TARGET_ASM_FILE_START rs6000_file_start
2366 /* Output to assembler file text saying following lines
2367 may contain character constants, extra white space, comments, etc. */
2371 /* Output to assembler file text saying following lines
2372 no longer contain unusual constructs. */
2376 /* How to refer to registers in assembler output.
2377 This sequence is indexed by compiler's hard-register-number (see above). */
2381 #define REGISTER_NAMES \
2382 { \
2415 \
2448 \
2453 \
2462 \
2464 \
2505 \
2538 }
2540 /* Table of additional register names to use in user input. */
2542 #define ADDITIONAL_REGISTER_NAMES \
2603 }
2605 /* This is how to output an element of a case-vector that is relative. */
2607 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2608 do { char buf[100]; \
2611 assemble_name (FILE, buf); \
2614 assemble_name (FILE, buf); \
2616 } while (0)
2618 /* This is how to output an assembler line
2619 that says to advance the location counter
2620 to a multiple of 2**LOG bytes. */
2622 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2623 if ((LOG) != 0) \
2626 /* How to align the given loop. */
2627 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2629 /* Alignment guaranteed by __builtin_malloc. */
2630 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2631 However, specifying the stronger guarantee currently leads to
2632 a regression in SPEC CPU2006 437.leslie3d. The stronger
2633 guarantee should be implemented here once that's fixed. */
2634 #define MALLOC_ABI_ALIGNMENT (64)
2636 /* Pick up the return address upon entry to a procedure. Used for
2637 dwarf2 unwind information. This also enables the table driven
2638 mechanism. */
2640 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2641 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2643 /* Describe how we implement __builtin_eh_return. */
2644 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2645 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2647 /* Print operand X (an rtx) in assembler syntax to file FILE.
2648 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2649 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2651 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2653 /* Define which CODE values are valid. */
2657 /* Print a memory address as an operand to reference that memory location. */
2659 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2661 /* For switching between functions with different target attributes. */
2662 #define SWITCHABLE_TARGET 1
2664 /* uncomment for disabling the corresponding default options */
2665 /* #define MACHINE_no_sched_interblock */
2666 /* #define MACHINE_no_sched_speculative */
2667 /* #define MACHINE_no_sched_speculative_load */
2669 /* General flags. */
2672 /* Classification of the builtin functions as to which switches enable the
2673 builtin, and what attributes it should have. We used to use the target
2674 flags macros, but we've run out of bits, so we now map the options into new
2675 settings used here. */
2677 /* Builtin attributes. */
2690 modifies global state. */
2692 state/mem and does
2693 not modify global state. */
2697 /* Miscellaneous information. */
2704 /* Convenience macros to document the instruction type. */
2708 /* Builtin targets. For now, we reuse the masks for those options that are in
2709 target flags, and pick three random bits for SPE, paired and ldbl128 which
2710 aren't in target_flags. */
2734 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2735 | RS6000_BTM_VSX \
2736 | RS6000_BTM_P8_VECTOR \
2737 | RS6000_BTM_P9_VECTOR \
2738 | RS6000_BTM_P9_MISC \
2739 | RS6000_BTM_MODULO \
2740 | RS6000_BTM_CRYPTO \
2741 | RS6000_BTM_FRE \
2742 | RS6000_BTM_FRES \
2743 | RS6000_BTM_FRSQRTE \
2744 | RS6000_BTM_FRSQRTES \
2745 | RS6000_BTM_HTM \
2746 | RS6000_BTM_POPCNTD \
2747 | RS6000_BTM_CELL \
2748 | RS6000_BTM_DFP \
2749 | RS6000_BTM_HARD_FLOAT \
2750 | RS6000_BTM_LDBL128 \
2751 | RS6000_BTM_FLOAT128)
2753 /* Define builtin enum index. */
2755 #undef RS6000_BUILTIN_0
2756 #undef RS6000_BUILTIN_1
2757 #undef RS6000_BUILTIN_2
2758 #undef RS6000_BUILTIN_3
2759 #undef RS6000_BUILTIN_A
2760 #undef RS6000_BUILTIN_D
2761 #undef RS6000_BUILTIN_E
2762 #undef RS6000_BUILTIN_H
2763 #undef RS6000_BUILTIN_P
2764 #undef RS6000_BUILTIN_Q
2765 #undef RS6000_BUILTIN_S
2766 #undef RS6000_BUILTIN_X
2768 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2769 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2770 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2771 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2772 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2773 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2774 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2775 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2776 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2777 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2778 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2779 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2781 enum rs6000_builtins
2782 {
2785 RS6000_BUILTIN_COUNT
2786 };
2788 #undef RS6000_BUILTIN_0
2789 #undef RS6000_BUILTIN_1
2790 #undef RS6000_BUILTIN_2
2791 #undef RS6000_BUILTIN_3
2792 #undef RS6000_BUILTIN_A
2793 #undef RS6000_BUILTIN_D
2794 #undef RS6000_BUILTIN_E
2795 #undef RS6000_BUILTIN_H
2796 #undef RS6000_BUILTIN_P
2797 #undef RS6000_BUILTIN_Q
2798 #undef RS6000_BUILTIN_S
2799 #undef RS6000_BUILTIN_X
2801 enum rs6000_builtin_type_index
2802 {
2803 RS6000_BTI_NOT_OPAQUE,
2804 RS6000_BTI_opaque_V2SI,
2805 RS6000_BTI_opaque_V2SF,
2806 RS6000_BTI_opaque_p_V2SI,
2807 RS6000_BTI_opaque_V4SI,
2808 RS6000_BTI_V16QI,
2809 RS6000_BTI_V1TI,
2810 RS6000_BTI_V2SI,
2811 RS6000_BTI_V2SF,
2812 RS6000_BTI_V2DI,
2813 RS6000_BTI_V2DF,
2814 RS6000_BTI_V4HI,
2815 RS6000_BTI_V4SI,
2816 RS6000_BTI_V4SF,
2817 RS6000_BTI_V8HI,
2818 RS6000_BTI_unsigned_V16QI,
2819 RS6000_BTI_unsigned_V1TI,
2820 RS6000_BTI_unsigned_V8HI,
2821 RS6000_BTI_unsigned_V4SI,
2822 RS6000_BTI_unsigned_V2DI,
2856 RS6000_BTI_MAX
2857 };
2860 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2861 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2862 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2863 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2864 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2865 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2866 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2867 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2868 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2869 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2870 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2871 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2872 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2873 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2874 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2875 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2876 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2877 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2878 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2879 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2880 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2881 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2882 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2883 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2884 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2885 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2886 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2887 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2888 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2890 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2891 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2892 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2893 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2894 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2895 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2896 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2897 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2898 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2899 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2900 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2901 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2902 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2903 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2904 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2905 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2906 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2907 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2908 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2909 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2910 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2911 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2912 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2917 #define TARGET_SUPPORTS_WIDE_INT 1
2919 #if (GCC_VERSION >= 3000)
2920 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2921 #endif