| blob | ba48b28d1d54af52a0921e9f180af863b11e24ca |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement HARD_REGNO_NREGS. */
1072 int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement HARD_REGNO_MODE_OK. */
1088 int
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1109 return
1111 else
1113 }
1116 }
1118 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1119 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1120 clobbers the top 64 bits when restoring the bottom 64 bits. */
1122 static bool
1124 {
1126 }
1128 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1129 machine_mode
1131 machine_mode mode)
1132 {
1133 /* Handle modes that fit within single registers. */
1135 {
1138 else
1140 }
1141 /* Fall back to generic for multi-reg and very large modes. */
1142 else
1144 }
1146 /* Return true if calls to DECL should be treated as
1147 long-calls (ie called via a register). */
1148 static bool
1150 {
1152 }
1154 /* Return true if calls to symbol-ref SYM should be treated as
1155 long-calls (ie called via a register). */
1156 bool
1158 {
1160 }
1162 /* Return true if calls to symbol-ref SYM should not go through
1163 plt stubs. */
1165 bool
1167 {
1171 && decl
1172 && (!flag_plt
1178 }
1180 /* Return true if the offsets to a zero/sign-extract operation
1181 represent an expression that matches an extend operation. The
1182 operands represent the paramters from
1184 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1185 bool
1187 rtx extract_imm)
1188 {
1205 }
1207 /* Emit an insn that's a simple single-set. Both the operands must be
1208 known to be valid. */
1211 {
1213 }
1215 /* X and Y are two things to compare using CODE. Emit the compare insn and
1216 return the rtx for register 0 in the proper mode. */
1217 rtx
1219 {
1225 }
1227 /* Build the SYMBOL_REF for __tls_get_addr. */
1231 rtx
1233 {
1237 }
1239 /* Return the TLS model to use for ADDR. */
1241 static enum tls_model
1243 {
1248 {
1252 }
1257 }
1259 /* We'll allow lo_sum's in addresses in our legitimate addresses
1260 so that combine would take care of combining addresses where
1261 necessary, but for generation purposes, we'll generate the address
1262 as :
1263 RTL Absolute
1264 tmp = hi (symbol_ref); adrp x1, foo
1265 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1266 nop
1268 PIC TLS
1269 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1270 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1271 bl __tls_get_addr
1272 nop
1274 Load TLS symbol, depending on TLS mechanism and TLS access model.
1276 Global Dynamic - Traditional TLS:
1277 adrp tmp, :tlsgd:imm
1278 add dest, tmp, #:tlsgd_lo12:imm
1279 bl __tls_get_addr
1281 Global Dynamic - TLS Descriptors:
1282 adrp dest, :tlsdesc:imm
1283 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1284 add dest, dest, #:tlsdesc_lo12:imm
1285 blr tmp
1286 mrs tp, tpidr_el0
1287 add dest, dest, tp
1289 Initial Exec:
1290 mrs tp, tpidr_el0
1291 adrp tmp, :gottprel:imm
1292 ldr dest, [tmp, #:gottprel_lo12:imm]
1293 add dest, dest, tp
1295 Local Exec:
1296 mrs tp, tpidr_el0
1297 add t0, tp, #:tprel_hi12:imm, lsl #12
1298 add t0, t0, #:tprel_lo12_nc:imm
1299 */
1301 static void
1304 {
1306 {
1308 {
1309 /* In ILP32, the mode of dest can be either SImode or DImode. */
1321 }
1328 {
1331 rtx insn;
1332 rtx mem;
1334 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1335 here before rtl expand. Tree IVOPT will generate rtl pattern to
1336 decide rtx costs, in which case pic_offset_table_rtx is not
1337 initialized. For that case no need to generate the first adrp
1338 instruction as the final cost for global variable access is
1339 one instruction. */
1341 {
1342 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1343 using the page base as GOT base, the first page may be wasted,
1344 in the worst scenario, there is only 28K space for GOT).
1346 The generate instruction sequence for accessing global variable
1347 is:
1349 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1351 Only one instruction needed. But we must initialize
1352 pic_offset_table_rtx properly. We generate initialize insn for
1353 every global access, and allow CSE to remove all redundant.
1355 The final instruction sequences will look like the following
1356 for multiply global variables access.
1358 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1360 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1361 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1362 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1363 ... */
1372 }
1375 {
1378 else
1382 }
1383 else
1384 {
1389 }
1391 /* The operand is expected to be MEM. Whenever the related insn
1392 pattern changed, above code which calculate mem should be
1393 updated. */
1399 }
1402 {
1403 /* In ILP32, the mode of dest can be either SImode or DImode,
1404 while the got entry is always of SImode size. The mode of
1405 dest depends on how dest is used: if dest is assigned to a
1406 pointer (e.g. in the memory), it has SImode; it may have
1407 DImode if dest is dereferenced to access the memeory.
1408 This is why we have to handle three different ldr_got_small
1409 patterns here (two patterns for ILP32). */
1411 rtx insn;
1412 rtx mem;
1421 {
1424 else
1428 }
1429 else
1430 {
1435 }
1442 }
1445 {
1453 else
1461 }
1464 {
1467 rtx tp;
1471 /* In ILP32, the got entry is always of SImode size. Unlike
1472 small GOT, the dest is fixed at reg 0. */
1475 else
1485 }
1488 {
1489 /* In ILP32, the mode of dest can be either SImode or DImode,
1490 while the got entry is always of SImode size. The mode of
1491 dest depends on how dest is used: if dest is assigned to a
1492 pointer (e.g. in the memory), it has SImode; it may have
1493 DImode if dest is dereferenced to access the memeory.
1494 This is why we have to handle three different tlsie_small
1495 patterns here (two patterns for ILP32). */
1501 {
1504 else
1505 {
1508 }
1509 }
1510 else
1511 {
1514 }
1519 }
1525 {
1533 {
1556 }
1560 }
1567 {
1572 {
1575 else
1576 {
1579 }
1580 }
1581 else
1582 {
1585 }
1589 }
1593 }
1594 }
1596 /* Emit a move from SRC to DEST. Assume that the move expanders can
1597 handle all moves if !can_create_pseudo_p (). The distinction is
1598 important because, unlike emit_move_insn, the move expanders know
1599 how to force Pmode objects into the constant pool even when the
1600 constant pool address is not itself legitimate. */
1601 static rtx
1603 {
1607 }
1609 /* Split a 128-bit move operation into two 64-bit move operations,
1610 taking care to handle partial overlap of register to register
1611 copies. Special cases are needed when moving between GP regs and
1612 FP regs. SRC can be a register, constant or memory; DST a register
1613 or memory. If either operand is memory it must not have any side
1614 effects. */
1615 void
1617 {
1628 {
1632 /* Handle FP <-> GP regs. */
1634 {
1639 {
1642 }
1643 else
1644 {
1647 }
1649 }
1651 {
1656 {
1659 }
1660 else
1661 {
1664 }
1666 }
1667 }
1674 /* At most one pairing may overlap. */
1676 {
1679 }
1680 else
1681 {
1684 }
1685 }
1687 bool
1689 {
1692 }
1694 /* Split a complex SIMD combine. */
1696 void
1698 {
1710 {
1734 }
1738 }
1740 /* Split a complex SIMD move. */
1742 void
1744 {
1751 {
1757 {
1781 }
1785 }
1786 }
1788 bool
1791 {
1795 }
1798 static rtx
1800 {
1803 else
1804 {
1807 }
1808 }
1811 static rtx
1813 {
1815 {
1816 rtx high;
1817 /* Load the full offset into a register. This
1818 might be improvable in the future. */
1824 }
1826 }
1828 static int
1830 machine_mode mode)
1831 {
1840 {
1844 }
1846 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1847 (with XXXX non-zero). In that case check to see if the move can be done in
1848 a smaller mode. */
1853 {
1857 /* Check if we have to emit a second instruction by checking to see
1858 if any of the upper 32 bits of the original DI mode value is set. */
1869 }
1872 {
1874 {
1879 else
1882 }
1884 }
1886 /* Remaining cases are all for DImode. */
1895 {
1896 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1897 For a 64-bit bitmask try whether changing 16 bits to all ones or
1898 zeroes creates a valid bitmask. To check any repeated bitmask,
1899 try using 16 bits from the other 32-bit half of val. */
1902 {
1913 }
1915 {
1917 {
1921 }
1923 }
1924 }
1926 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1927 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1928 otherwise skip zero bits. */
1940 {
1946 num_insns ++;
1947 }
1950 }
1953 void
1955 {
1960 /* Check on what type of symbol it is. */
1964 {
1968 /* If we have (const (plus symbol offset)), separate out the offset
1969 before we start classifying the symbol. */
1974 {
1978 {
1984 }
1989 /* If we aren't generating PC relative literals, then
1990 we need to expand the literal pool access carefully.
1991 This is something that needs to be done in a number
1992 of places, so could well live as a separate function. */
1994 {
2001 }
2018 {
2024 }
2025 /* FALLTHRU */
2038 }
2039 }
2042 {
2045 else
2046 {
2050 }
2053 }
2056 }
2058 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2059 temporary value if necessary. FRAME_RELATED_P should be true if
2060 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2061 to the generated instructions. If SCRATCHREG is known to hold
2062 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2063 immediate again.
2065 Since this function may be used to adjust the stack pointer, we must
2066 ensure that it cannot cause transient stack deallocation (for example
2067 by first incrementing SP and then decrementing when adjusting by a
2068 large immediate). */
2070 static void
2074 {
2082 /* Single instruction adjustment. */
2084 {
2088 }
2090 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2091 Only do this if mdelta is not a 16-bit move as adjusting using a move
2092 is better. */
2094 {
2103 }
2105 /* Emit a move immediate if required and an addition/subtraction. */
2112 {
2116 }
2117 }
2121 HOST_WIDE_INT delta)
2122 {
2124 }
2128 {
2131 }
2135 {
2138 }
2140 static bool
2142 tree exp ATTRIBUTE_UNUSED)
2143 {
2144 /* Currently, always true. */
2146 }
2148 /* Implement TARGET_PASS_BY_REFERENCE. */
2150 static bool
2152 machine_mode mode,
2153 const_tree type,
2155 {
2156 HOST_WIDE_INT size;
2157 machine_mode dummymode;
2160 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2164 /* Aggregates are passed by reference based on their size. */
2166 {
2168 }
2170 /* Variable sized arguments are always returned by reference. */
2174 /* Can this be a candidate to be passed in fp/simd register(s)? */
2177 NULL))
2180 /* Arguments which are variable sized or larger than 2 registers are
2181 passed by reference unless they are a homogenous floating point
2182 aggregate. */
2184 }
2186 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2187 static bool
2189 {
2190 machine_mode dummy_mode;
2193 /* Never happens in little-endian mode. */
2197 /* Only composite types smaller than or equal to 16 bytes can
2198 be potentially returned in registers. */
2204 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2205 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2206 is always passed/returned in the least significant bits of fp/simd
2207 register(s). */
2213 }
2215 /* Implement TARGET_FUNCTION_VALUE.
2216 Define how to find the value returned by a function. */
2218 static rtx
2221 {
2222 machine_mode mode;
2225 machine_mode ag_mode;
2232 {
2236 {
2239 }
2240 }
2244 {
2246 {
2249 }
2250 else
2251 {
2253 rtx par;
2257 {
2262 }
2264 }
2265 }
2266 else
2268 }
2270 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2271 Return true if REGNO is the number of a hard register in which the values
2272 of called function may come back. */
2274 static bool
2276 {
2277 /* Maximum of 16 bytes can be returned in the general registers. Examples
2278 of 16-byte return values are: 128-bit integers and 16-byte small
2279 structures (excluding homogeneous floating-point aggregates). */
2283 /* Up to four fp/simd registers can return a function value, e.g. a
2284 homogeneous floating-point aggregate having four members. */
2289 }
2291 /* Implement TARGET_RETURN_IN_MEMORY.
2293 If the type T of the result of a function is such that
2294 void func (T arg)
2295 would require that arg be passed as a value in a register (or set of
2296 registers) according to the parameter passing rules, then the result
2297 is returned in the same registers as would be used for such an
2298 argument. */
2300 static bool
2302 {
2303 HOST_WIDE_INT size;
2304 machine_mode ag_mode;
2310 /* Simple scalar types always returned in registers. */
2314 type,
2317 NULL))
2320 /* Types larger than 2 registers returned in memory. */
2323 }
2325 static bool
2328 {
2331 type,
2333 nregs,
2334 NULL);
2335 }
2337 /* Given MODE and TYPE of a function argument, return the alignment in
2338 bits. The idea is to suppress any stronger alignment requested by
2339 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2340 This is a helper function for local use only. */
2342 static unsigned int
2344 {
2365 }
2367 /* Layout a function argument according to the AAPCS64 rules. The rule
2368 numbers refer to the rule numbers in the AAPCS64. */
2370 static void
2372 const_tree type,
2374 {
2378 HOST_WIDE_INT size;
2380 /* We need to do this once per argument. */
2386 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2387 size
2389 UNITS_PER_WORD);
2393 mode,
2394 type,
2397 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2398 The following code thus handles passing by SIMD/FP registers first. */
2402 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2403 and homogenous short-vector aggregates (HVA). */
2405 {
2410 {
2413 {
2416 }
2417 else
2418 {
2419 rtx par;
2423 {
2426 tmp = gen_rtx_EXPR_LIST
2430 }
2432 }
2434 }
2435 else
2436 {
2437 /* C.3 NSRN is set to 8. */
2440 }
2441 }
2446 /* C6 - C9. though the sign and zero extension semantics are
2447 handled elsewhere. This is the case where the argument fits
2448 entirely general registers. */
2450 {
2454 /* C.8 if the argument has an alignment of 16 then the NGRN is
2455 rounded up to the next even number. */
2458 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2459 comparison is there because for > 16 * BITS_PER_UNIT
2460 alignment nregs should be > 2 and therefore it should be
2461 passed by reference rather than value. */
2463 {
2466 }
2468 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2469 A reg is still generated for it, but the caller should be smart
2470 enough not to use it. */
2473 else
2474 {
2475 rtx par;
2480 {
2485 }
2487 }
2491 }
2493 /* C.11 */
2496 /* The argument is passed on stack; record the needed number of words for
2497 this argument and align the total size if necessary. */
2498 on_stack:
2505 }
2507 /* Implement TARGET_FUNCTION_ARG. */
2509 static rtx
2512 {
2521 }
2523 void
2525 const_tree fntype ATTRIBUTE_UNUSED,
2526 rtx libname ATTRIBUTE_UNUSED,
2527 const_tree fndecl ATTRIBUTE_UNUSED,
2529 {
2543 {
2550 }
2552 }
2554 static void
2556 machine_mode mode,
2557 const_tree type,
2559 {
2562 {
2572 }
2573 }
2575 bool
2577 {
2580 }
2582 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2583 PARM_BOUNDARY bits of alignment, but will be given anything up
2584 to STACK_BOUNDARY bits if the type requires it. This makes sure
2585 that both before and after the layout of each argument, the Next
2586 Stacked Argument Address (NSAA) will have a minimum alignment of
2587 8 bytes. */
2589 static unsigned int
2591 {
2594 }
2596 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2598 Return true if an argument passed on the stack should be padded upwards,
2599 i.e. if the least-significant byte of the stack slot has useful data.
2601 Small aggregate types are placed in the lowest memory address.
2603 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2605 bool
2607 {
2608 /* On little-endian targets, the least significant byte of every stack
2609 argument is passed at the lowest byte address of the stack slot. */
2613 /* Otherwise, integral, floating-point and pointer types are padded downward:
2614 the least significant byte of a stack argument is passed at the highest
2615 byte address of the stack slot. */
2622 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2624 }
2626 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2628 It specifies padding for the last (may also be the only)
2629 element of a block move between registers and memory. If
2630 assuming the block is in the memory, padding upward means that
2631 the last element is padded after its highest significant byte,
2632 while in downward padding, the last element is padded at the
2633 its least significant byte side.
2635 Small aggregates and small complex types are always padded
2636 upwards.
2638 We don't need to worry about homogeneous floating-point or
2639 short-vector aggregates; their move is not affected by the
2640 padding direction determined here. Regardless of endianness,
2641 each element of such an aggregate is put in the least
2642 significant bits of a fp/simd register.
2644 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2645 register has useful data, and return the opposite if the most
2646 significant byte does. */
2648 bool
2651 {
2653 /* Small composite types are always padded upward. */
2655 {
2660 }
2662 /* Otherwise, use the default padding. */
2664 }
2666 static scalar_int_mode
2668 {
2670 }
2672 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2674 /* We use the 12-bit shifted immediate arithmetic instructions so values
2675 must be multiple of (1 << 12), i.e. 4096. */
2676 #define ARITH_FACTOR 4096
2678 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2679 #error Cannot use simple address calculation for stack probing
2680 #endif
2682 /* The pair of scratch registers used for stack probing. */
2683 #define PROBE_STACK_FIRST_REG 9
2684 #define PROBE_STACK_SECOND_REG 10
2686 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2687 inclusive. These are offsets from the current stack pointer. */
2689 static void
2691 {
2694 /* See the same assertion on PROBE_INTERVAL above. */
2697 /* See if we have a constant small number of probes to generate. If so,
2698 that's the easy case. */
2700 {
2707 }
2709 /* The run-time loop is made up of 8 insns in the generic case while the
2710 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2712 {
2717 stack_pointer_rtx,
2721 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2722 it exceeds SIZE. If only two probes are needed, this will not
2723 generate any code. Then probe at FIRST + SIZE. */
2725 {
2729 }
2733 {
2738 }
2739 else
2741 }
2743 /* Otherwise, do the same as above, but in a loop. Note that we must be
2744 extra careful with variables wrapping around because we might be at
2745 the very top (or the very bottom) of the address space and we have
2746 to be able to handle this case properly; in particular, we use an
2747 equality test for the loop condition. */
2748 else
2749 {
2752 /* Step 1: round SIZE to the previous multiple of the interval. */
2757 /* Step 2: compute initial and final value of the loop counter. */
2759 /* TEST_ADDR = SP + FIRST. */
2763 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2766 {
2770 }
2771 else
2772 {
2775 }
2777 /* Step 3: the loop
2779 do
2780 {
2781 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2782 probe at TEST_ADDR
2783 }
2784 while (TEST_ADDR != LAST_ADDR)
2786 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2787 until it is equal to ROUNDED_SIZE. */
2792 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2793 that SIZE is equal to ROUNDED_SIZE. */
2796 {
2800 {
2805 }
2806 else
2808 }
2809 }
2811 /* Make sure nothing is scheduled before we are done. */
2813 }
2815 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2816 absolute addresses. */
2820 {
2827 /* Loop. */
2830 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2835 /* Probe at TEST_ADDR. */
2838 /* Test if TEST_ADDR == LAST_ADDR. */
2842 /* Branch. */
2848 }
2850 static bool
2852 {
2853 /* In aarch64_override_options_after_change
2854 flag_omit_leaf_frame_pointer turns off the frame pointer by
2855 default. Turn it back on now if we've not got a leaf
2856 function. */
2861 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2866 }
2868 /* Mark the registers that need to be saved by the callee and calculate
2869 the size of the callee-saved registers area and frame record (both FP
2870 and LR may be omitted). */
2871 static void
2873 {
2880 #define SLOT_NOT_REQUIRED (-2)
2881 #define SLOT_REQUIRED (-1)
2886 /* First mark all the registers that really need to be saved... */
2893 /* ... that includes the eh data registers (if needed)... */
2899 /* ... and any callee saved register that dataflow says is live. */
2909 {
2912 }
2915 {
2916 /* FP and LR are placed in the linkage record. */
2922 }
2924 /* Now assign stack slots for them. */
2927 {
2934 }
2942 {
2943 /* If there is an alignment gap between integer and fp callee-saves,
2944 allocate the last fp register to it if possible. */
2946 {
2949 }
2958 }
2964 HOST_WIDE_INT varargs_and_saved_regs_size
2991 {
2992 /* Simple, small frame with no outgoing arguments:
2993 stp reg1, reg2, [sp, -frame_size]!
2994 stp reg3, reg4, [sp, 16] */
2996 }
3001 {
3002 /* Frame with small outgoing arguments:
3003 sub sp, sp, frame_size
3004 stp reg1, reg2, [sp, outgoing_args_size]
3005 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3009 }
3011 {
3012 /* Frame with large outgoing arguments but a small local area:
3013 stp reg1, reg2, [sp, -hard_fp_offset]!
3014 stp reg3, reg4, [sp, 16]
3015 sub sp, sp, outgoing_args_size */
3019 }
3022 {
3023 /* Frame with large local area and outgoing arguments (this pushes the
3024 callee-saves first, followed by the locals and outgoing area):
3025 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3026 stp reg3, reg4, [sp, 16]
3027 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3033 }
3034 else
3035 {
3036 /* Frame with large local area and outgoing arguments using frame pointer:
3037 sub sp, sp, hard_fp_offset
3038 stp x29, x30, [sp, 0]
3039 add x29, sp, 0
3040 stp reg3, reg4, [sp, 16]
3041 sub sp, sp, outgoing_args_size */
3045 }
3048 }
3050 /* Return true if the register REGNO is saved on entry to
3051 the current function. */
3053 static bool
3055 {
3057 }
3059 /* Return the next register up from REGNO up to LIMIT for the callee
3060 to save. */
3062 static unsigned
3064 {
3066 regno ++;
3068 }
3070 /* Push the register number REGNO of mode MODE to the stack with write-back
3071 adjusting the stack by ADJUSTMENT. */
3073 static void
3075 HOST_WIDE_INT adjustment)
3076 {
3087 }
3089 /* Generate and return an instruction to store the pair of registers
3090 REG and REG2 of mode MODE to location BASE with write-back adjusting
3091 the stack location BASE by ADJUSTMENT. */
3093 static rtx
3095 HOST_WIDE_INT adjustment)
3096 {
3098 {
3109 }
3110 }
3112 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3113 stack pointer by ADJUSTMENT. */
3115 static void
3117 {
3132 }
3134 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3135 adjusting it by ADJUSTMENT afterwards. */
3137 static rtx
3139 HOST_WIDE_INT adjustment)
3140 {
3142 {
3151 }
3152 }
3154 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3155 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3156 into CFI_OPS. */
3158 static void
3161 {
3168 {
3172 }
3173 else
3174 {
3179 }
3180 }
3182 /* Generate and return a store pair instruction of mode MODE to store
3183 register REG1 to MEM1 and register REG2 to MEM2. */
3185 static rtx
3187 rtx reg2)
3188 {
3190 {
3199 }
3200 }
3202 /* Generate and regurn a load pair isntruction of mode MODE to load register
3203 REG1 from MEM1 and register REG2 from MEM2. */
3205 static rtx
3207 rtx mem2)
3208 {
3210 {
3219 }
3220 }
3222 /* Return TRUE if return address signing should be enabled for the current
3223 function, otherwise return FALSE. */
3225 bool
3227 {
3228 /* This function should only be called after frame laid out. */
3231 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3232 if it's LR is pushed onto stack. */
3236 }
3238 /* Emit code to save the callee-saved registers from register number START
3239 to LIMIT to the stack at the location starting at offset START_OFFSET,
3240 skipping any write-back candidates if SKIP_WB is true. */
3242 static void
3245 {
3253 {
3255 HOST_WIDE_INT offset;
3268 offset));
3277 {
3279 rtx mem2;
3283 offset));
3285 reg2));
3287 /* The first part of a frame-related parallel insn is
3288 always assumed to be relevant to the frame
3289 calculations; subsequent parts, are only
3290 frame-related if explicitly marked. */
3293 }
3294 else
3298 }
3299 }
3301 /* Emit code to restore the callee registers of mode MODE from register
3302 number START up to and including LIMIT. Restore from the stack offset
3303 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3304 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3306 static void
3310 {
3314 HOST_WIDE_INT offset;
3319 {
3340 {
3342 rtx mem2;
3350 }
3351 else
3354 }
3355 }
3359 HOST_WIDE_INT offset)
3360 {
3362 }
3366 {
3370 }
3372 bool
3374 {
3378 }
3380 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3382 static sbitmap
3384 {
3390 /* The registers we need saved to the frame. */
3393 {
3398 /* Check that we can access the stack slot of the register with one
3399 direct load with no adjustments needed. */
3402 }
3404 /* Don't mess with the hard frame pointer. */
3410 /* If aarch64_layout_frame has chosen registers to store/restore with
3411 writeback don't interfere with them to avoid having to output explicit
3412 stack adjustment instructions. */
3422 }
3424 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3426 static sbitmap
3428 {
3436 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3445 }
3447 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3448 Nothing to do for aarch64. */
3450 static void
3452 {
3453 }
3455 /* Return the next set bit in BMP from START onwards. Return the total number
3456 of bits in BMP if no set bit is found at or after START. */
3458 static unsigned int
3460 {
3471 }
3473 /* Do the work for aarch64_emit_prologue_components and
3474 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3475 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3476 for these components or the epilogue sequence. That is, it determines
3477 whether we should emit stores or loads and what kind of CFA notes to attach
3478 to the insns. Otherwise the logic for the two sequences is very
3479 similar. */
3481 static void
3483 {
3485 ? HARD_FRAME_POINTER_REGNUM
3493 {
3494 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3495 so DFmode for the vector registers is enough. */
3507 /* No more registers to handle after REGNO.
3508 Emit a single save/restore and exit. */
3510 {
3515 else
3518 }
3521 /* The next register is not of the same class or its offset is not
3522 mergeable with the current one into a pair. */
3527 {
3532 else
3537 }
3539 /* REGNO2 can be saved/restored in a pair with REGNO. */
3551 else
3556 {
3559 }
3560 else
3561 {
3564 }
3567 }
3568 }
3570 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3572 static void
3574 {
3576 }
3578 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3580 static void
3582 {
3584 }
3586 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3588 static void
3590 {
3594 }
3596 /* AArch64 stack frames generated by this compiler look like:
3598 +-------------------------------+
3599 | |
3600 | incoming stack arguments |
3601 | |
3602 +-------------------------------+
3603 | | <-- incoming stack pointer (aligned)
3604 | callee-allocated save area |
3605 | for register varargs |
3606 | |
3607 +-------------------------------+
3608 | local variables | <-- frame_pointer_rtx
3609 | |
3610 +-------------------------------+
3611 | padding0 | \
3612 +-------------------------------+ |
3613 | callee-saved registers | | frame.saved_regs_size
3614 +-------------------------------+ |
3615 | LR' | |
3616 +-------------------------------+ |
3617 | FP' | / <- hard_frame_pointer_rtx (aligned)
3618 +-------------------------------+
3619 | dynamic allocation |
3620 +-------------------------------+
3621 | padding |
3622 +-------------------------------+
3623 | outgoing stack arguments | <-- arg_pointer
3624 | |
3625 +-------------------------------+
3626 | | <-- stack_pointer_rtx (aligned)
3628 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3629 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3630 unchanged. */
3632 /* Generate the prologue instructions for entry into a function.
3633 Establish the stack frame by decreasing the stack pointer with a
3634 properly calculated size and, if necessary, create a frame record
3635 filled with the values of LR and previous frame pointer. The
3636 current FP is also set up if it is in use. */
3638 void
3640 {
3652 /* Sign return address for functions. */
3654 {
3658 }
3664 {
3666 {
3670 }
3673 }
3681 {
3686 stack_pointer_rtx,
3690 }
3697 }
3699 /* Return TRUE if we can use a simple_return insn.
3701 This function checks whether the callee saved stack is empty, which
3702 means no restore actions are need. The pro_and_epilogue will use
3703 this to check whether shrink-wrapping opt is feasible. */
3705 bool
3707 {
3717 }
3719 /* Generate the epilogue instructions for returning from a function.
3720 This is almost exactly the reverse of the prolog sequence, except
3721 that we need to insert barriers to avoid scheduling loads that read
3722 from a deallocated stack, and we optimize the unwind records by
3723 emitting them all together if possible. */
3724 void
3726 {
3738 /* We need to add memory barrier to prevent read from deallocated stack. */
3742 /* Emit a barrier to prevent loads from a deallocated stack. */
3745 {
3748 }
3750 /* Restore the stack pointer from the frame pointer if it may not
3751 be the same as the stack pointer. */
3753 {
3755 hard_frame_pointer_rtx,
3757 /* If writeback is used when restoring callee-saves, the CFA
3758 is restored on the instruction doing the writeback. */
3760 }
3761 else
3776 {
3777 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3783 }
3788 {
3789 /* Emit delayed restores and reset the CFA to be SP. */
3794 }
3796 /* We prefer to emit the combined return/authenticate instruction RETAA,
3797 however there are three cases in which we must instead emit an explicit
3798 authentication instruction.
3800 1) Sibcalls don't return in a normal way, so if we're about to call one
3801 we must authenticate.
3803 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3804 generating code for !TARGET_ARMV8_3 we can't use it and must
3805 explicitly authenticate.
3807 3) On an eh_return path we make extra stack adjustments to update the
3808 canonical frame address to be the exception handler's CFA. We want
3809 to authenticate using the CFA of the function which calls eh_return.
3810 */
3813 {
3817 }
3819 /* Stack adjustment for exception handler. */
3821 {
3822 /* We need to unwind the stack by the offset computed by
3823 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3824 to be SP; letting the CFA move during this adjustment
3825 is just as correct as retaining the CFA from the body
3826 of the function. Therefore, do nothing special. */
3828 }
3833 }
3835 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3836 normally or return to a previous frame after unwinding.
3838 An EH return uses a single shared return sequence. The epilogue is
3839 exactly like a normal epilogue except that it has an extra input
3840 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3841 that must be applied after the frame has been destroyed. An extra label
3842 is inserted before the epilogue which initializes this register to zero,
3843 and this is the entry point for a normal return.
3845 An actual EH return updates the return address, initializes the stack
3846 adjustment and jumps directly into the epilogue (bypassing the zeroing
3847 of the adjustment). Since the return address is typically saved on the
3848 stack when a function makes a call, the saved LR must be updated outside
3849 the epilogue.
3851 This poses problems as the store is generated well before the epilogue,
3852 so the offset of LR is not known yet. Also optimizations will remove the
3853 store as it appears dead, even after the epilogue is generated (as the
3854 base or offset for loading LR is different in many cases).
3856 To avoid these problems this implementation forces the frame pointer
3857 in eh_return functions so that the location of LR is fixed and known early.
3858 It also marks the store volatile, so no optimization is permitted to
3859 remove the store. */
3860 rtx
3862 {
3866 /* Mark the store volatile, so no optimization is permitted to remove it. */
3869 }
3871 /* Output code to add DELTA to the first argument, and then jump
3872 to FUNCTION. Used for C++ multiple inheritance. */
3873 static void
3875 HOST_WIDE_INT delta,
3876 HOST_WIDE_INT vcall_offset,
3877 tree function)
3878 {
3879 /* The this pointer is always in x0. Note that this differs from
3880 Arm where the this pointer maybe bumped to r1 if r0 is required
3881 to return a pointer to an aggregate. On AArch64 a result value
3882 pointer will be in x8. */
3892 else
3893 {
3902 {
3906 else
3908 }
3912 else
3919 else
3920 {
3922 Pmode);
3924 }
3928 else
3934 }
3936 /* Generate a tail call to the target function. */
3938 {
3941 }
3953 /* Stop pretending to be a post-reload pass. */
3955 }
3957 static bool
3959 {
3964 {
3968 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3969 TLS offsets, not real symbol references. */
3972 }
3974 }
3977 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3978 a left shift of 0 or 12 bits. */
3979 bool
3981 {
3984 );
3985 }
3988 /* Return true if val is an immediate that can be loaded into a
3989 register by a MOVZ instruction. */
3990 static bool
3992 {
3994 {
3998 }
3999 else
4000 {
4001 /* Ignore sign extension. */
4003 }
4006 }
4008 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4011 {
4017 };
4020 /* Return true if val is a valid bitmask immediate. */
4022 bool
4024 {
4028 /* Check for a single sequence of one bits and return quickly if so.
4029 The special cases of all ones and all zeroes returns false. */
4036 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4040 /* Invert if the immediate doesn't start with a zero bit - this means we
4041 only need to search for sequences of one bits. */
4045 /* Find the first set bit and set tmp to val with the first sequence of one
4046 bits removed. Return success if there is a single sequence of ones. */
4053 /* Find the next set bit and compute the difference in bit position. */
4058 /* Check the bit position difference is a power of 2, and that the first
4059 sequence of one bits fits within 'bits' bits. */
4063 /* Check the sequence of one bits is repeated 64/bits times. */
4065 }
4067 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4068 Assumed precondition: VAL_IN Is not zero. */
4070 unsigned HOST_WIDE_INT
4072 {
4079 }
4081 /* Create constant where bits outside of lowest bit set to highest bit set
4082 are set to 1. */
4084 unsigned HOST_WIDE_INT
4086 {
4088 }
4090 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4092 bool
4094 {
4104 }
4106 /* Return true if val is an immediate that can be loaded into a
4107 register in a single instruction. */
4108 bool
4110 {
4114 }
4116 static bool
4118 {
4126 {
4130 else
4131 /* Avoid generating a 64-bit relocation in ILP32; leave
4132 to aarch64_expand_mov_immediate to handle it properly. */
4134 }
4137 }
4139 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4140 The expansion for a table switch is quite expensive due to the number
4141 of instructions, the table lookup and hard to predict indirect jump.
4142 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4143 set, otherwise use tables for > 16 cases as a tradeoff between size and
4144 performance. When optimizing for size, use the default setting. */
4146 static unsigned int
4148 {
4149 /* Use the specified limit for the number of cases before using jump
4150 tables at higher optimization levels. */
4154 else
4156 }
4158 /* Return true if register REGNO is a valid index register.
4159 STRICT_P is true if REG_OK_STRICT is in effect. */
4161 bool
4163 {
4165 {
4173 }
4175 }
4177 /* Return true if register REGNO is a valid base register for mode MODE.
4178 STRICT_P is true if REG_OK_STRICT is in effect. */
4180 bool
4182 {
4184 {
4192 }
4194 /* The fake registers will be eliminated to either the stack or
4195 hard frame pointer, both of which are usually valid base registers.
4196 Reload deals with the cases where the eliminated form isn't valid. */
4201 }
4203 /* Return true if X is a valid base register for mode MODE.
4204 STRICT_P is true if REG_OK_STRICT is in effect. */
4206 static bool
4208 {
4215 }
4217 /* Return true if address offset is a valid index. If it is, fill in INFO
4218 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4220 static bool
4223 {
4225 rtx index;
4228 /* (reg:P) */
4231 {
4235 }
4236 /* (sign_extend:DI (reg:SI)) */
4241 {
4246 }
4247 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4254 {
4259 }
4260 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4267 {
4272 }
4273 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4280 {
4288 }
4289 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4290 (const_int 0xffffffff<<shift)) */
4297 {
4303 }
4304 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4311 {
4319 }
4320 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4321 (const_int 0xffffffff<<shift)) */
4328 {
4334 }
4335 /* (mult:P (reg:P) (const_int scale)) */
4340 {
4344 }
4345 /* (ashift:P (reg:P) (const_int shift)) */
4350 {
4354 }
4355 else
4368 {
4373 }
4376 }
4378 /* Return true if MODE is one of the modes for which we
4379 support LDP/STP operations. */
4381 static bool
4383 {
4388 }
4390 /* Return true if REGNO is a virtual pointer register, or an eliminable
4391 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4392 include stack_pointer or hard_frame_pointer. */
4393 static bool
4395 {
4400 }
4402 /* Return true if X is a valid address for machine mode MODE. If it is,
4403 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4404 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4406 static bool
4410 {
4414 /* On BE, we use load/store pair for all large int mode load/stores.
4415 TI/TFmode may also use a load/store pair. */
4419 || (BYTES_BIG_ENDIAN
4423 !load_store_pair_p
4427 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4428 REG addressing. */
4434 {
4450 {
4456 }
4461 {
4468 /* TImode and TFmode values are allowed in both pairs of X
4469 registers and individual Q registers. The available
4470 address modes are:
4471 X,X: 7-bit signed scaled offset
4472 Q: 9-bit signed offset
4473 We conservatively require an offset representable in either mode.
4474 When performing the check for pairs of X registers i.e. LDP/STP
4475 pass down DImode since that is the natural size of the LDP/STP
4476 instruction memory accesses. */
4482 /* A 7bit offset check because OImode will emit a ldp/stp
4483 instruction (only big endian will get here).
4484 For ldp/stp instructions, the offset is scaled for the size of a
4485 single element of the pair. */
4489 /* Three 9/12 bit offsets checks because CImode will emit three
4490 ldr/str instructions (only big endian will get here). */
4497 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4498 instructions (only big endian will get here). */
4507 else
4510 }
4513 {
4514 /* Look for base + (scaled/extended) index register. */
4517 {
4520 }
4523 {
4526 }
4527 }
4548 {
4549 HOST_WIDE_INT offset;
4553 /* TImode and TFmode values are allowed in both pairs of X
4554 registers and individual Q registers. The available
4555 address modes are:
4556 X,X: 7-bit signed scaled offset
4557 Q: 9-bit signed offset
4558 We conservatively require an offset representable in either mode.
4559 */
4567 else
4569 }
4575 /* load literal: pc-relative constant pool entry. Only supported
4576 for SI mode or larger. */
4580 {
4588 }
4597 {
4602 {
4603 /* The symbol and offset must be aligned to the access size. */
4610 {
4614 }
4620 else
4629 }
4630 }
4635 }
4636 }
4638 /* Return true if the address X is valid for a PRFM instruction.
4639 STRICT_P is true if we should do strict checking with
4640 aarch64_classify_address. */
4642 bool
4644 {
4647 /* PRFM accepts the same addresses as DImode... */
4652 /* ... except writeback forms. */
4654 }
4656 bool
4658 {
4659 rtx offset;
4663 }
4665 /* Classify the base of symbolic expression X. */
4667 enum aarch64_symbol_type
4669 {
4670 rtx offset;
4674 }
4677 /* Return TRUE if X is a legitimate address for accessing memory in
4678 mode MODE. */
4679 static bool
4681 {
4685 }
4687 /* Return TRUE if X is a legitimate address for accessing memory in
4688 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4689 pair operation. */
4690 bool
4693 {
4697 }
4699 /* Split an out-of-range address displacement into a base and offset.
4700 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4701 to increase opportunities for sharing the base address of different sizes.
4702 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4703 static bool
4705 {
4716 }
4718 /* Return the binary representation of floating point constant VALUE in INTVAL.
4719 If the value cannot be converted, return false without setting INTVAL.
4720 The conversion is done in the given MODE. */
4721 bool
4723 {
4725 /* We make a general exception for 0. */
4727 {
4730 }
4736 /* Only support up to DF mode. */
4748 {
4752 }
4753 else
4758 }
4760 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4761 single MOV(+MOVK) followed by an FMOV. */
4762 bool
4764 {
4769 /* Determine whether it's cheaper to write float constants as
4770 mov/movk pairs over ldr/adrp pairs. */
4776 {
4778 ? SImode
4783 }
4786 }
4788 /* Return TRUE if rtx X is immediate constant 0.0 */
4789 bool
4791 {
4798 }
4800 /* Return TRUE if rtx X is immediate constant that fits in a single
4801 MOVI immediate operation. */
4802 bool
4804 {
4813 {
4817 /* We make a general exception for 0. */
4822 }
4825 {
4828 }
4829 else
4832 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4833 a 128 bit vector mode. */
4840 }
4843 /* Return the fixed registers used for condition codes. */
4845 static bool
4847 {
4851 }
4853 /* This function is used by the call expanders of the machine description.
4854 RESULT is the register in which the result is returned. It's NULL for
4855 "call" and "sibcall".
4856 MEM is the location of the function call.
4857 SIBCALL indicates whether this function call is normal call or sibling call.
4858 It will generate different pattern accordingly. */
4860 void
4862 {
4864 rtvec vec;
4865 machine_mode mode;
4872 /* Decide if we should generate indirect calls by loading the
4873 address of the callee into a register before performing
4874 the branch-and-link. */
4888 else
4895 }
4897 /* Emit call insn with PAT and do aarch64-specific handling. */
4899 void
4901 {
4907 }
4909 machine_mode
4911 {
4912 /* All floating point compares return CCFP if it is an equality
4913 comparison, and CCFPE otherwise. */
4915 {
4917 {
4938 }
4939 }
4941 /* Equality comparisons of short modes against zero can be performed
4942 using the TST instruction with the appropriate bitmask. */
4948 /* Similarly, comparisons of zero_extends from shorter modes can
4949 be performed using an ANDS with an immediate mask. */
4965 /* A compare with a shifted operand. Because of canonicalization,
4966 the comparison will have to be swapped when we emit the assembly
4967 code. */
4975 /* Similarly for a negated operand, but we can only do this for
4976 equalities. */
4983 /* A test for unsigned overflow. */
4990 /* For everything else, return CCmode. */
4992 }
4994 static int
4997 int
4999 {
5006 }
5008 static int
5010 {
5012 {
5016 {
5030 }
5035 {
5047 }
5052 {
5064 }
5069 {
5075 }
5080 {
5084 }
5089 {
5093 }
5098 }
5101 }
5103 bool
5105 HOST_WIDE_INT minval,
5106 HOST_WIDE_INT maxval)
5107 {
5108 HOST_WIDE_INT firstval;
5125 }
5127 bool
5129 {
5131 }
5134 /* N Z C V. */
5135 #define AARCH64_CC_V 1
5136 #define AARCH64_CC_C (1 << 1)
5137 #define AARCH64_CC_Z (1 << 2)
5138 #define AARCH64_CC_N (1 << 3)
5140 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5142 {
5159 };
5161 /* Print operand X to file F in a target specific manner according to CODE.
5162 The acceptable formatting commands given by CODE are:
5163 'c': An integer or symbol address without a preceding #
5164 sign.
5165 'e': Print the sign/zero-extend size as a character 8->b,
5166 16->h, 32->w.
5167 'p': Prints N such that 2^N == X (X must be power of 2 and
5168 const int).
5169 'P': Print the number of non-zero bits in X (a const_int).
5170 'H': Print the higher numbered register of a pair (TImode)
5171 of regs.
5172 'm': Print a condition (eq, ne, etc).
5173 'M': Same as 'm', but invert condition.
5174 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5175 'S/T/U/V': Print a FP/SIMD register name for a register list.
5176 The register printed is the FP/SIMD register name
5177 of X + 0/1/2/3 for S/T/U/V.
5178 'R': Print a scalar FP/SIMD register name + 1.
5179 'X': Print bottom 16 bits of integer constant in hex.
5180 'w/x': Print a general register name or the zero register
5181 (32-bit or 64-bit).
5182 '0': Print a normal operand, if it's a general register,
5183 then we assume DImode.
5184 'k': Print NZCV for conditional compare instructions.
5185 'A': Output address constant representing the first
5186 argument of X, specifying a relocation offset
5187 if appropriate.
5188 'L': Output constant address specified by X
5189 with a relocation offset if appropriate.
5190 'G': Prints address of X, specifying a PC relative
5191 relocation mode if appropriate. */
5193 static void
5195 {
5197 {
5200 {
5212 {
5215 }
5216 /* Fall through. */
5220 }
5224 {
5229 {
5232 }
5235 {
5248 }
5249 }
5253 {
5257 {
5260 }
5263 }
5268 {
5271 }
5278 {
5281 }
5288 {
5290 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5292 {
5296 }
5299 {
5302 }
5309 }
5318 {
5319 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5321 }
5330 {
5331 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5333 }
5339 {
5340 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5342 }
5348 {
5351 }
5359 {
5362 }
5365 {
5368 }
5371 {
5374 }
5376 /* Fall through */
5380 {
5383 }
5386 {
5393 /* Check all memory references are Pmode - even with ILP32. */
5409 {
5412 HOST_WIDE_INT_MIN,
5413 HOST_WIDE_INT_MAX));
5415 }
5417 {
5419 }
5420 else
5425 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5426 be getting CONST_DOUBLEs holding integers. */
5429 {
5432 }
5434 {
5435 #define buf_size 20
5443 #undef buf_size
5444 }
5450 }
5458 {
5485 }
5491 {
5526 }
5532 {
5538 }
5543 {
5544 HOST_WIDE_INT cond_code;
5547 {
5550 }
5555 }
5561 }
5562 }
5564 static void
5566 {
5571 {
5575 else
5584 else
5593 else
5602 else
5609 {
5636 }
5647 }
5650 }
5652 bool
5654 {
5661 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5662 referencing instruction, but they are constant offsets, not
5663 symbols. */
5669 {
5671 {
5677 }
5680 }
5683 }
5685 /* Implement REGNO_REG_CLASS. */
5687 enum reg_class
5689 {
5704 }
5706 static rtx
5708 {
5709 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5710 where mask is selected by alignment and size of the offset.
5711 We try to pick as large a range for the offset as possible to
5712 maximize the chance of a CSE. However, for aligned addresses
5713 we limit the range to 4k so that structures with different sized
5714 elements are likely to use the same base. We need to be careful
5715 not to split a CONST for some forms of address expression, otherwise
5716 it will generate sub-optimal code. */
5719 {
5725 {
5729 /* Force any scaling into a temp for CSE. */
5733 /* Let the pointer register be in op0. */
5737 /* If the pointer is virtual or frame related, then we know that
5738 virtual register instantiation or register elimination is going
5739 to apply a second constant. We want the two constants folded
5740 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5742 {
5746 }
5748 /* Otherwise, in order to encourage CSE (and thence loop strength
5749 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5753 }
5755 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5756 HOST_WIDE_INT base_offset;
5759 /* For offsets aren't a multiple of the access size, the limit is
5760 -256...255. */
5762 {
5765 /* BLKmode typically uses LDP of X-registers. */
5768 }
5769 /* Small negative offsets are supported. */
5774 /* Use 12-bit offset by access size. */
5775 else
5779 {
5783 }
5784 }
5787 }
5789 /* Return the reload icode required for a constant pool in mode. */
5790 static enum insn_code
5792 {
5794 {
5830 }
5833 }
5834 static reg_class_t
5836 reg_class_t rclass,
5837 machine_mode mode,
5839 {
5841 /* If we have to disable direct literal pool loads and stores because the
5842 function is too big, then we need a scratch register. */
5847 {
5850 }
5852 /* Without the TARGET_SIMD instructions we cannot move a Q register
5853 to a Q register directly. We need a scratch. */
5857 {
5863 }
5865 /* A TFmode or TImode memory access should be handled via an FP_REGS
5866 because AArch64 has richer addressing modes for LDR/STR instructions
5867 than LDP/STP instructions. */
5876 }
5878 static bool
5880 {
5881 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5882 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5885 {
5897 }
5898 else
5899 {
5900 /* If we decided that we didn't need a leaf frame pointer but then used
5901 LR in the function, then we'll want a frame pointer after all, so
5902 prevent this elimination to ensure a frame pointer is used. */
5904 && flag_omit_leaf_frame_pointer
5907 }
5910 }
5912 HOST_WIDE_INT
5914 {
5918 {
5925 }
5928 {
5932 }
5935 }
5937 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5938 previous frame. */
5940 rtx
5942 {
5946 }
5949 static void
5951 {
5953 {
5956 }
5957 else
5958 {
5961 }
5966 }
5968 static void
5970 {
5974 /* Don't need to copy the trailing D-words, we fill those in below. */
5986 /* XXX We should really define a "clear_cache" pattern and use
5987 gen_clear_cache(). */
5992 ptr_mode);
5993 }
5995 static unsigned char
5997 {
5999 {
6006 return
6018 }
6020 }
6022 static reg_class_t
6024 {
6029 {
6035 }
6037 /* Register eliminiation can result in a request for
6038 SP+constant->FP_REGS. We cannot support such operations which
6039 use SP as source and an FP_REG as destination, so reject out
6040 right now. */
6042 {
6045 /* Look through a possible SUBREG introduced by ILP32. */
6051 POINTER_REGS));
6053 }
6056 }
6058 void
6060 {
6062 }
6064 static void
6066 {
6069 else
6070 {
6072 /* While priority is known to be in range [0, 65535], so 18 bytes
6073 would be enough, the compiler might not know that. To avoid
6074 -Wformat-truncation false positive, use a larger size. */
6081 }
6082 }
6084 static void
6086 {
6089 else
6090 {
6092 /* While priority is known to be in range [0, 65535], so 18 bytes
6093 would be enough, the compiler might not know that. To avoid
6094 -Wformat-truncation false positive, use a larger size. */
6101 }
6102 }
6106 {
6112 {
6113 {
6116 },
6117 {
6120 },
6121 {
6124 },
6125 /* We assume that DImode is only generated when not optimizing and
6126 that we don't really need 64-bit address offsets. That would
6127 imply an object file with 8GB of code in a single function! */
6128 {
6131 }
6132 };
6140 /* Need to implement table size reduction, by chaning the code below. */
6150 }
6153 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6154 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6155 operator. */
6157 int
6159 {
6161 {
6164 {
6168 }
6169 }
6171 }
6173 /* Constant pools are per function only when PC relative
6174 literal loads are true or we are in the large memory
6175 model. */
6179 {
6182 }
6184 static bool
6186 {
6187 /* Fixme:: In an ideal world this would work similar
6188 to the logic in aarch64_select_rtx_section but this
6189 breaks bootstrap in gcc go. For now we workaround
6190 this by returning false here. */
6192 }
6194 /* Select appropriate section for constants depending
6195 on where we place literal pools. */
6199 rtx x,
6201 {
6206 }
6208 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6209 void
6211 HOST_WIDE_INT offset)
6212 {
6213 /* When using per-function literal pools, we must ensure that any code
6214 section is aligned to the minimal instruction length, lest we get
6215 errors from the assembler re "unaligned instructions". */
6218 }
6220 /* Costs. */
6222 /* Helper function for rtx cost calculation. Strip a shift expression
6223 from X. Returns the inner operand if successful, or the original
6224 expression on failure. */
6225 static rtx
6227 {
6230 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6231 we can convert both to ROR during final output. */
6246 }
6248 /* Helper function for rtx cost calculation. Strip an extend
6249 expression from X. Returns the inner operand if successful, or the
6250 original expression on failure. We deal with a number of possible
6251 canonicalization variations here. If STRIP_SHIFT is true, then
6252 we can strip off a shift also. */
6253 static rtx
6255 {
6258 /* Zero and sign extraction of a widened value. */
6266 /* It can also be represented (for zero-extend) as an AND with an
6267 immediate. */
6276 /* Now handle extended register, as this may also have an optional
6277 left shift by 1..4. */
6292 }
6294 /* Return true iff CODE is a shift supported in combination
6295 with arithmetic instructions. */
6297 static bool
6299 {
6301 }
6304 /* Return true iff X is a cheap shift without a sign extend. */
6306 static bool
6308 {
6334 }
6336 /* Helper function for rtx cost calculation. Calculate the cost of
6337 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6338 Return the calculated cost of the expression, recursing manually in to
6339 operands where needed. */
6341 static int
6343 {
6359 /* Integer multiply/fma. */
6361 {
6362 /* The multiply will be canonicalized as a shift, cost it as such. */
6366 {
6370 {
6372 {
6373 /* If the shift is considered cheap,
6374 then don't add any cost. */
6376 ;
6378 /* ARITH + shift-by-register. */
6381 /* ARITH + extended register. We don't have a cost field
6382 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6384 else
6385 /* ARITH + shift-by-immediate. */
6387 }
6388 else
6389 /* LSL (immediate). */
6392 }
6393 /* Strip extends as we will have costed them in the case above. */
6400 }
6402 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6403 compound and let the below cases handle it. After all, MNEG is a
6404 special-case alias of MSUB. */
6406 {
6409 }
6411 /* Integer multiplies or FMAs have zero/sign extending variants. */
6416 {
6421 {
6423 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6425 else
6426 /* MUL/SMULL/UMULL. */
6428 }
6431 }
6433 /* This is either an integer multiply or a MADD. In both cases
6434 we want to recurse and cost the operands. */
6439 {
6441 /* MADD/MSUB. */
6443 else
6444 /* MUL. */
6446 }
6449 }
6450 else
6451 {
6453 {
6454 /* Floating-point FMA/FMUL can also support negations of the
6455 operands, unless the rounding mode is upward or downward in
6456 which case FNMUL is different than FMUL with operand negation. */
6460 {
6465 }
6468 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6470 else
6471 /* FMUL/FNMUL. */
6473 }
6478 }
6479 }
6481 static int
6483 machine_mode mode,
6484 addr_space_t as ATTRIBUTE_UNUSED,
6486 {
6494 {
6496 {
6497 /* This is a CONST or SYMBOL ref which will be split
6498 in a different way depending on the code model in use.
6499 Cost it through the generic infrastructure. */
6501 /* Divide through by the cost of one instruction to
6502 bring it to the same units as the address costs. */
6504 /* The cost is then the cost of preparing the address,
6505 followed by an immediate (possibly 0) offset. */
6507 }
6508 else
6509 {
6510 /* This is most likely a jump table from a case
6511 statement. */
6513 }
6514 }
6517 {
6529 else
6548 }
6552 {
6553 /* For the sake of calculating the cost of the shifted register
6554 component, we can treat same sized modes in the same way. */
6556 {
6569 /* We can't tell, or this is a 128-bit vector. */
6573 }
6574 }
6577 }
6579 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6580 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6581 to be taken. */
6583 int
6585 {
6586 /* When optimizing for speed, use the cost of unpredictable branches. */
6592 else
6594 }
6596 /* Return true if the RTX X in mode MODE is a zero or sign extract
6597 usable in an ADD or SUB (extended register) instruction. */
6598 static bool
6600 {
6601 /* Catch add with a sign extract.
6602 This is add_<optab><mode>_multp2. */
6605 {
6616 op1))
6617 {
6619 }
6620 }
6621 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6622 No shift. */
6628 }
6630 static bool
6632 {
6634 {
6646 }
6647 }
6649 /* Return true iff X is an rtx that will match an extr instruction
6650 i.e. as described in the *extr<mode>5_insn family of patterns.
6651 OP0 and OP1 will be set to the operands of the shifts involved
6652 on success and will be NULL_RTX otherwise. */
6654 static bool
6656 {
6671 {
6672 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6684 {
6688 }
6689 }
6692 }
6694 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6695 storing it in *COST. Result is true if the total cost of the operation
6696 has now been calculated. */
6697 static bool
6699 {
6700 rtx inner;
6701 rtx comparator;
6705 {
6709 }
6710 else
6711 {
6715 }
6718 {
6719 /* Conditional branch. */
6722 else
6723 {
6725 {
6727 {
6728 /* TBZ/TBNZ/CBZ/CBNZ. */
6730 /* TBZ/TBNZ. */
6733 else
6734 /* CBZ/CBNZ. */
6738 }
6739 }
6741 {
6742 /* TBZ/TBNZ. */
6745 }
6746 }
6747 }
6749 {
6750 /* CCMP. */
6752 {
6753 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6757 {
6764 else
6766 }
6768 }
6770 /* It's a conditional operation based on the status flags,
6771 so it must be some flavor of CSEL. */
6773 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6779 {
6780 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6783 }
6788 }
6790 /* We don't know what this is, cost all operands. */
6792 }
6794 /* Check whether X is a bitfield operation of the form shift + extend that
6795 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6796 operand to which the bitfield operation is applied. Otherwise return
6797 NULL_RTX. */
6799 static rtx
6801 {
6815 {
6833 }
6836 }
6838 /* Return true if the mask and a shift amount from an RTX of the form
6839 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6840 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6842 bool
6844 {
6849 }
6851 /* Calculate the cost of calculating X, storing it in *COST. Result
6852 is true if the total cost of the operation has now been calculated. */
6853 static bool
6856 {
6861 scalar_int_mode int_mode;
6863 /* By default, assume that everything has equivalent cost to the
6864 cheapest instruction. Any additional costs are applied as a delta
6865 above this default. */
6869 {
6871 /* The cost depends entirely on the operands to SET. */
6877 {
6880 {
6894 }
6903 /* Fall through. */
6905 /* The cost is one per vector-register copied. */
6907 {
6911 }
6912 /* const0_rtx is in general free, but we will use an
6913 instruction to set a register to 0. */
6915 {
6916 /* The cost is 1 per register copied. */
6920 }
6921 else
6922 /* Cost is just the cost of the RHS of the set. */
6928 /* Bit-field insertion. Strip any redundant widening of
6929 the RHS to meet the width of the target. */
6940 {
6941 /* MOV immediate is assumed to always be cheap. */
6943 }
6944 else
6945 {
6946 /* BFM. */
6950 }
6955 /* We can't make sense of this, assume default cost. */
6958 }
6962 /* If an instruction can incorporate a constant within the
6963 instruction, the instruction's expression avoids calling
6964 rtx_cost() on the constant. If rtx_cost() is called on a
6965 constant, then it is usually because the constant must be
6966 moved into a register by one or more instructions.
6968 The exception is constant 0, which can be expressed
6969 as XZR/WZR and is therefore free. The exception to this is
6970 if we have (set (reg) (const0_rtx)) in which case we must cost
6971 the move. However, we can catch that when we cost the SET, so
6972 we don't need to consider that here. */
6975 else
6976 {
6977 /* To an approximation, building any other constant is
6978 proportionally expensive to the number of instructions
6979 required to build that constant. This is true whether we
6980 are compiling for SPEED or otherwise. */
6983 }
6988 /* First determine number of instructions to do the move
6989 as an integer constant. */
6993 {
6999 ? SImode
7005 }
7008 {
7009 /* mov[df,sf]_aarch64. */
7011 /* FMOV (scalar immediate). */
7014 {
7015 /* This will be a load from memory. */
7018 else
7020 }
7021 else
7022 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7023 or MOV v0.s[0], wzr - neither of which are modeled by the
7024 cost tables. Just use the default cost. */
7025 {
7026 }
7027 }
7033 {
7034 /* For loads we want the base cost of a load, plus an
7035 approximation for the additional cost of the addressing
7036 mode. */
7050 }
7058 {
7060 {
7061 /* FNEG. */
7063 }
7065 }
7068 {
7071 {
7072 /* CSETM. */
7075 }
7077 /* Cost this as SUB wzr, X. */
7081 }
7084 {
7085 /* Support (neg(fma...)) as a single instruction only if
7086 sign of zeros is unimportant. This matches the decision
7087 making in aarch64.md. */
7089 {
7090 /* FNMADD. */
7093 }
7095 {
7096 /* FNMUL. */
7099 }
7101 /* FNEG. */
7104 }
7111 {
7114 else
7116 }
7126 {
7130 }
7133 {
7134 /* TODO: A write to the CC flags possibly costs extra, this
7135 needs encoding in the cost tables. */
7138 /* ANDS. */
7140 {
7143 }
7146 {
7147 /* ADDS (and CMN alias). */
7150 }
7153 {
7154 /* SUBS. */
7157 }
7162 {
7163 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7164 Handle it here directly rather than going to cost_logic
7165 since we know the immediate generated for the TST is valid
7166 so we can avoid creating an intermediate rtx for it only
7167 for costing purposes. */
7174 }
7177 {
7178 /* CMN. */
7185 }
7187 /* CMP.
7189 Compare can freely swap the order of operands, and
7190 canonicalization puts the more complex operation first.
7191 But the integer MINUS logic expects the shift/extend
7192 operation in op1. */
7195 {
7198 }
7200 }
7203 {
7204 /* FCMP. */
7209 {
7211 /* FCMP supports constant 0.0 for no extra cost. */
7213 }
7215 }
7218 {
7219 /* Vector compare. */
7224 {
7225 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7226 cost. */
7228 }
7230 }
7234 {
7238 cost_minus:
7241 /* Detect valid immediates. */
7247 {
7249 /* SUB(S) (immediate). */
7252 }
7254 /* Look for SUB (extended register). */
7256 {
7264 }
7268 /* Cost this as an FMA-alike operation. */
7272 {
7275 speed);
7277 }
7282 {
7284 {
7285 /* Vector SUB. */
7287 }
7289 {
7290 /* SUB(S). */
7292 }
7294 {
7295 /* FSUB. */
7297 }
7298 }
7300 }
7303 {
7304 rtx new_op0;
7309 cost_plus:
7312 {
7313 /* CSINC. */
7317 }
7322 {
7326 /* ADD (immediate). */
7329 }
7333 /* Look for ADD (extended register). */
7335 {
7343 }
7345 /* Strip any extend, leave shifts behind as we will
7346 cost them through mult_cost. */
7351 {
7353 speed);
7355 }
7360 {
7362 {
7363 /* Vector ADD. */
7365 }
7367 {
7368 /* ADD. */
7370 }
7372 {
7373 /* FADD. */
7375 }
7376 }
7378 }
7384 {
7387 else
7389 }
7394 {
7398 {
7401 else
7403 }
7405 }
7408 {
7415 }
7416 /* Fall through. */
7419 cost_logic:
7424 {
7428 }
7436 {
7437 /* This is a UBFM/SBFM. */
7442 }
7445 {
7447 {
7448 /* We have a mask + shift version of a UBFIZ
7449 i.e. the *andim_ashift<mode>_bfiz pattern. */
7453 {
7460 }
7462 {
7463 /* We possibly get the immediate for free, this is not
7464 modelled. */
7471 }
7472 }
7473 else
7474 {
7477 /* Handle ORN, EON, or BIC. */
7483 /* If we had a shift on op0 then this is a logical-shift-
7484 by-register/immediate operation. Otherwise, this is just
7485 a logical operation. */
7487 {
7489 {
7490 /* Shift by immediate. */
7493 else
7495 }
7496 else
7498 }
7500 /* In both cases we want to cost both operands. */
7507 }
7508 }
7516 {
7517 /* Vector NOT. */
7520 }
7522 /* MVN-shifted-reg. */
7524 {
7531 }
7532 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7533 Handle the second form here taking care that 'a' in the above can
7534 be a shift. */
7536 {
7545 {
7548 else
7550 }
7553 }
7554 /* MVN. */
7563 /* If a value is written in SI mode, then zero extended to DI
7564 mode, the operation will in general be free as a write to
7565 a 'w' register implicitly zeroes the upper bits of an 'x'
7566 register. However, if this is
7568 (set (reg) (zero_extend (reg)))
7570 we must cost the explicit register move. */
7574 {
7577 /* If OP_COST is non-zero, then the cost of the zero extend
7578 is effectively the cost of the inner operation. Otherwise
7579 we have a MOV instruction and we take the cost from the MOV
7580 itself. This is true independently of whether we are
7581 optimizing for space or time. */
7586 }
7588 {
7589 /* All loads can zero extend to any size for free. */
7592 }
7596 {
7601 }
7604 {
7606 {
7607 /* UMOV. */
7609 }
7610 else
7611 {
7612 /* We generate an AND instead of UXTB/UXTH. */
7614 }
7615 }
7620 {
7621 /* LDRSH. */
7623 {
7630 }
7632 }
7636 {
7641 }
7644 {
7647 else
7649 }
7657 {
7659 {
7661 {
7662 /* Vector shift (immediate). */
7664 }
7665 else
7666 {
7667 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7668 aliases. */
7670 }
7671 }
7673 /* We can incorporate zero/sign extend for free. */
7680 }
7681 else
7682 {
7684 {
7686 /* Vector shift (register). */
7688 }
7689 else
7690 {
7692 /* LSLV. */
7698 {
7700 /* We already demanded XEXP (op1, 0) to be REG_P, so
7701 don't recurse into it. */
7703 }
7704 }
7706 }
7716 {
7717 /* ASR (immediate) and friends. */
7719 {
7722 else
7724 }
7728 }
7729 else
7730 {
7732 {
7734 /* Vector shift (register). */
7736 }
7737 else
7738 {
7740 /* ASR (register) and friends. */
7746 {
7748 /* We already demanded XEXP (op1, 0) to be REG_P, so
7749 don't recurse into it. */
7751 }
7752 }
7754 }
7760 {
7761 /* LDR. */
7764 }
7767 {
7768 /* ADRP, followed by ADD. */
7772 }
7775 {
7776 /* ADR. */
7779 }
7782 {
7783 /* One extra load instruction, after accessing the GOT. */
7787 }
7792 /* ADRP/ADD (immediate). */
7799 /* UBFX/SBFX. */
7801 {
7804 else
7806 }
7808 /* We can trust that the immediates used will be correct (there
7809 are no by-register forms), so we need only cost op0. */
7815 /* aarch64_rtx_mult_cost always handles recursion to its
7816 operands. */
7820 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7821 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7822 an unconditional negate. This case should only ever be reached through
7823 the set_smod_pow2_cheap check in expmed.c. */
7827 {
7828 /* We expand to 4 instructions. Reset the baseline. */
7836 }
7838 /* Fall-through. */
7841 {
7842 /* Slighly prefer UMOD over SMOD. */
7849 }
7856 {
7860 /* There is no integer SQRT, so only DIV and UDIV can get
7861 here. */
7863 /* Slighly prefer UDIV over SDIV. */
7865 else
7867 }
7893 {
7896 else
7898 }
7900 /* FMSUB, FNMADD, and FNMSUB are free. */
7907 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7908 and the by-element operand as operand 0. */
7912 /* Catch vector-by-element operations. The by-element operand can
7913 either be (vec_duplicate (vec_select (x))) or just
7914 (vec_select (x)), depending on whether we are multiplying by
7915 a vector or a scalar.
7917 Canonicalization is not very good in these cases, FMA4 will put the
7918 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7929 /* If the remaining parameters are not registers,
7930 get the cost to put them into registers. */
7944 {
7946 {
7947 /*Vector truncate. */
7949 }
7950 else
7952 }
7957 {
7959 {
7960 /*Vector conversion. */
7962 }
7963 else
7965 }
7971 /* Strip the rounding part. They will all be implemented
7972 by the fcvt* family of instructions anyway. */
7974 {
7983 }
7986 {
7989 else
7991 }
7993 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7994 fixed-point fcvt. */
7999 {
8003 }
8010 {
8011 /* ABS (vector). */
8014 }
8016 {
8019 /* FABD, which is analogous to FADD. */
8021 {
8028 }
8029 /* Simple FABS is analogous to FNEG. */
8032 }
8033 else
8034 {
8035 /* Integer ABS will either be split to
8036 two arithmetic instructions, or will be an ABS
8037 (scalar), which we don't model. */
8041 }
8047 {
8050 else
8051 {
8052 /* FMAXNM/FMINNM/FMAX/FMIN.
8053 TODO: This may not be accurate for all implementations, but
8054 we do not model this in the cost tables. */
8056 }
8057 }
8061 /* The floating point round to integer frint* instructions. */
8063 {
8068 }
8071 {
8076 }
8081 /* Decompose <su>muldi3_highpart. */
8083 mode == DImode
8084 /* (lshiftrt:TI */
8087 /* (mult:TI */
8089 /* (ANY_EXTEND:TI (reg:DI))
8090 (ANY_EXTEND:TI (reg:DI))) */
8097 /* (const_int 64) */
8100 {
8101 /* UMULH/SMULH. */
8109 }
8111 /* Fall through. */
8114 }
8122 }
8124 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8125 calculated for X. This cost is stored in *COST. Returns true
8126 if the total cost of X was calculated. */
8127 static bool
8130 {
8135 {
8140 }
8143 }
8145 static int
8148 {
8154 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8161 /* Moving between GPR and stack cost is the same as GP2GP. */
8166 /* To/From the stack register, we move via the gprs. */
8172 {
8173 /* 128-bit operations on general registers require 2 instructions. */
8181 /* When AdvSIMD instructions are disabled it is not possible to move
8182 a 128-bit value directly between Q registers. This is handled in
8183 secondary reload. A general register is used as a scratch to move
8184 the upper DI value and the lower DI value is moved directly,
8185 hence the cost is the sum of three moves. */
8190 }
8200 }
8202 static int
8204 reg_class_t rclass ATTRIBUTE_UNUSED,
8206 {
8208 }
8210 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8211 to optimize 1.0/sqrt. */
8213 static bool
8215 {
8217 && flag_unsafe_math_optimizations
8221 }
8223 /* Function to decide when to use the approximate reciprocal square root
8224 builtin. */
8226 static tree
8228 {
8234 }
8238 /* Select reciprocal square root initial estimate insn depending on machine
8239 mode. */
8241 static rsqrte_type
8243 {
8245 {
8252 }
8253 }
8257 /* Select reciprocal square root series step insn depending on machine mode. */
8259 static rsqrts_type
8261 {
8263 {
8270 }
8271 }
8273 /* Emit instruction sequence to compute either the approximate square root
8274 or its approximate reciprocal, depending on the flag RECP, and return
8275 whether the sequence was emitted or not. */
8277 bool
8279 {
8283 {
8286 }
8288 machine_mode mmsk
8292 {
8299 || flag_trapping_math
8300 || !flag_unsafe_math_optimizations
8303 }
8304 else
8305 /* Caller assumes we cannot fail. */
8311 /* When calculating the approximate square root, compare the
8312 argument with 0.0 and create a mask. */
8318 /* Estimate the approximate reciprocal square root. */
8322 /* Iterate over the series twice for SF and thrice for DF. */
8325 /* Optionally iterate over the series once less for faster performance
8326 while sacrificing the accuracy. */
8329 iterations--;
8331 /* Iterate over the series to calculate the approximate reciprocal square
8332 root. */
8335 {
8343 }
8346 {
8347 /* Qualify the approximate reciprocal square root when the argument is
8348 0.0 by squashing the intermediary result to 0.0. */
8354 /* Calculate the approximate square root. */
8356 }
8358 /* Finalize the approximation. */
8362 }
8366 /* Select reciprocal initial estimate insn depending on machine mode. */
8368 static recpe_type
8370 {
8372 {
8379 }
8380 }
8384 /* Select reciprocal series step insn depending on machine mode. */
8386 static recps_type
8388 {
8390 {
8397 }
8398 }
8400 /* Emit the instruction sequence to compute the approximation for the division
8401 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8403 bool
8405 {
8416 || flag_trapping_math
8417 || !flag_unsafe_math_optimizations
8422 /* Estimate the approximate reciprocal. */
8426 /* Iterate over the series twice for SF and thrice for DF. */
8429 /* Optionally iterate over the series once less for faster performance,
8430 while sacrificing the accuracy. */
8432 iterations--;
8434 /* Iterate over the series to calculate the approximate reciprocal. */
8437 {
8442 }
8445 {
8446 /* As the approximate reciprocal of DEN is already calculated, only
8447 calculate the approximate division when NUM is not 1.0. */
8450 }
8452 /* Finalize the approximation. */
8455 }
8457 /* Return the number of instructions that can be issued per cycle. */
8458 static int
8460 {
8462 }
8464 static int
8466 {
8470 }
8473 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8474 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8475 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8477 static int
8480 {
8482 }
8485 /* Vectorizer cost model target hooks. */
8487 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8488 static int
8490 tree vectype,
8492 {
8501 {
8550 }
8551 }
8553 /* Implement targetm.vectorize.add_stmt_cost. */
8554 static unsigned
8558 {
8563 {
8568 /* Statements in an inner loop relative to the loop being
8569 vectorized are weighted more heavily. The value here is
8570 arbitrary and could potentially be improved with analysis. */
8576 }
8579 }
8583 /* Parse the TO_PARSE string and put the architecture struct that it
8584 selects into RES and the architectural features into ISA_FLAGS.
8585 Return an aarch64_parse_opt_result describing the parse result.
8586 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8588 static enum aarch64_parse_opt_result
8591 {
8603 else
8610 /* Loop through the list of supported ARCHes to find a match. */
8612 {
8614 {
8618 {
8619 /* TO_PARSE string contains at least one extension. */
8620 enum aarch64_parse_opt_result ext_res
8625 }
8626 /* Extension parsing was successful. Confirm the result
8627 arch and ISA flags. */
8631 }
8632 }
8634 /* ARCH name not found in list. */
8636 }
8638 /* Parse the TO_PARSE string and put the result tuning in RES and the
8639 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8640 describing the parse result. If there is an error parsing, RES and
8641 ISA_FLAGS are left unchanged. */
8643 static enum aarch64_parse_opt_result
8646 {
8658 else
8665 /* Loop through the list of supported CPUs to find a match. */
8667 {
8669 {
8674 {
8675 /* TO_PARSE string contains at least one extension. */
8676 enum aarch64_parse_opt_result ext_res
8681 }
8682 /* Extension parsing was successfull. Confirm the result
8683 cpu and ISA flags. */
8687 }
8688 }
8690 /* CPU name not found in list. */
8692 }
8694 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8695 Return an aarch64_parse_opt_result describing the parse result.
8696 If the parsing fails the RES does not change. */
8698 static enum aarch64_parse_opt_result
8700 {
8706 /* Loop through the list of supported CPUs to find a match. */
8708 {
8710 {
8713 }
8714 }
8716 /* CPU name not found in list. */
8718 }
8720 /* Parse TOKEN, which has length LENGTH to see if it is an option
8721 described in FLAG. If it is, return the index bit for that fusion type.
8722 If not, error (printing OPTION_NAME) and return zero. */
8724 static unsigned int
8729 {
8731 {
8735 }
8739 }
8741 /* Parse OPTION which is a comma-separated list of flags to enable.
8742 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8743 default state we inherit from the CPU tuning structures. OPTION_NAME
8744 gives the top-level option we are parsing in the -moverride string,
8745 for use in error messages. */
8747 static unsigned int
8752 {
8759 {
8762 token_length,
8763 flags,
8764 option_name);
8765 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8766 in the token stream, reset the supported operations. So:
8768 adrp+add.cmp+branch.none.adrp+add
8770 would have the result of turning on only adrp+add fusion. */
8776 }
8778 /* We ended with a comma, print something. */
8780 {
8783 }
8785 /* We still have one more token to parse. */
8788 token_length,
8789 flags,
8790 option_name);
8796 }
8798 /* Support for overriding instruction fusion. */
8800 static void
8803 {
8805 aarch64_fusible_pairs,
8808 }
8810 /* Support for overriding other tuning flags. */
8812 static void
8815 {
8816 tune->extra_tuning_flags
8818 aarch64_tuning_flags,
8821 }
8823 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8824 we understand. If it is, extract the option string and handoff to
8825 the appropriate function. */
8827 void
8831 {
8837 {
8840 }
8842 /* Get the length of the option name. */
8844 /* Skip the '=' to get to the option string. */
8845 option_part++;
8848 {
8850 {
8853 }
8854 }
8858 }
8860 /* A checking mechanism for the implementation of the tls size. */
8862 static void
8864 {
8869 {
8871 /* Both the default and maximum TLS size allowed under tiny is 1M which
8872 needs two instructions to address, so we clamp the size to 24. */
8877 /* The maximum TLS size allowed under small is 4G. */
8882 /* The maximum TLS size allowed under large is 16E.
8883 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8889 }
8892 }
8894 /* Parse STRING looking for options in the format:
8895 string :: option:string
8896 option :: name=substring
8897 name :: {a-z}
8898 substring :: defined by option. */
8900 static void
8903 {
8914 {
8916 /* Make this substring look like a string. */
8920 }
8922 /* One last option to parse. */
8925 }
8928 static void
8930 {
8931 /* The logic here is that if we are disabling all frame pointer generation
8932 then we do not need to disable leaf frame pointer generation as a
8933 separate operation. But if we are *only* disabling leaf frame pointer
8934 generation then we set flag_omit_frame_pointer to true, but in
8935 aarch64_frame_pointer_required we return false only for leaf functions.
8937 PR 70044: We have to be careful about being called multiple times for the
8938 same function. Once we have decided to set flag_omit_frame_pointer just
8939 so that we can omit leaf frame pointers, we must then not interpret a
8940 second call as meaning that all frame pointer generation should be
8941 omitted. We do this by setting flag_omit_frame_pointer to a special,
8942 non-zero value. */
8951 /* If not optimizing for size, set the default
8952 alignment to what the target wants. */
8954 {
8961 }
8963 /* We default to no pc-relative literal loads. */
8967 /* If -mpc-relative-literal-loads is set on the command line, this
8968 implies that the user asked for PC relative literal loads. */
8972 /* This is PR70113. When building the Linux kernel with
8973 CONFIG_ARM64_ERRATUM_843419, support for relocations
8974 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8975 removed from the kernel to avoid loading objects with possibly
8976 offending sequences. Without -mpc-relative-literal-loads we would
8977 generate such relocations, preventing the kernel build from
8978 succeeding. */
8983 /* In the tiny memory model it makes no sense to disallow PC relative
8984 literal pool loads. */
8989 /* When enabling the lower precision Newton series for the square root, also
8990 enable it for the reciprocal square root, since the latter is an
8991 intermediary step for the former. */
8994 }
8996 /* 'Unpack' up the internal tuning structs and update the options
8997 in OPTS. The caller must have set up selected_tune and selected_arch
8998 as all the other target-specific codegen decisions are
8999 derived from them. */
9001 void
9003 {
9006 /* Make a copy of the tuning parameters attached to the core, which
9007 we may later overwrite. */
9015 /* This target defaults to strict volatile bitfields. */
9024 {
9036 }
9038 /* We don't mind passing in global_options_set here as we don't use
9039 the *options_set structs anyway. */
9041 queue_depth,
9045 /* Set up parameters to be used in prefetching algorithm. Do not
9046 override the defaults unless we are tuning for a core we have
9047 researched values for. */
9069 /* Enable sw prefetching at specified optimization level for
9070 CPUS that have prefetch. Lower optimization level threshold by 1
9071 when profiling is enabled. */
9079 }
9081 /* Print a hint with a suggestion for a core or architecture name that
9082 most closely resembles what the user passed in STR. ARCH is true if
9083 the user is asking for an architecture name. ARCH is false if the user
9084 is asking for a core name. */
9086 static void
9088 {
9099 }
9101 /* Print a hint with a suggestion for a core name that most closely resembles
9102 what the user passed in STR. */
9106 {
9108 }
9110 /* Print a hint with a suggestion for an architecture name that most closely
9111 resembles what the user passed in STR. */
9115 {
9117 }
9119 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9120 specified in STR and throw errors if appropriate. Put the results if
9121 they are valid in RES and ISA_FLAGS. Return whether the option is
9122 valid. */
9124 static bool
9127 {
9128 enum aarch64_parse_opt_result parse_res
9135 {
9148 }
9151 }
9153 /* Validate a command-line -march option. Parse the arch and extensions
9154 (if any) specified in STR and throw errors if appropriate. Put the
9155 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9156 option is valid. */
9158 static bool
9161 {
9162 enum aarch64_parse_opt_result parse_res
9169 {
9182 }
9185 }
9187 /* Validate a command-line -mtune option. Parse the cpu
9188 specified in STR and throw errors if appropriate. Put the
9189 result, if it is valid, in RES. Return whether the option is
9190 valid. */
9192 static bool
9194 {
9195 enum aarch64_parse_opt_result parse_res
9202 {
9212 }
9214 }
9216 /* Return the CPU corresponding to the enum CPU.
9217 If it doesn't specify a cpu, return the default. */
9221 {
9225 /* The & 0x3f is to extract the bottom 6 bits that encode the
9226 default cpu as selected by the --with-cpu GCC configure option
9227 in config.gcc.
9228 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9229 flags mechanism should be reworked to make it more sane. */
9231 }
9233 /* Return the architecture corresponding to the enum ARCH.
9234 If it doesn't specify a valid architecture, return the default. */
9238 {
9245 }
9247 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9248 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9249 tuning structs. In particular it must set selected_tune and
9250 aarch64_isa_flags that define the available ISA features and tuning
9251 decisions. It must also set selected_arch as this will be used to
9252 output the .arch asm tags for each function. */
9254 static void
9256 {
9269 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9270 If either of -march or -mtune is given, they override their
9271 respective component of -mcpu. */
9283 /* If the user did not specify a processor, choose the default
9284 one for them. This will be the CPU set during configuration using
9285 --with-cpu, otherwise it is "generic". */
9287 {
9289 {
9293 }
9294 else
9295 {
9296 /* Get default configure-time CPU. */
9299 }
9303 }
9304 /* If both -mcpu and -march are specified check that they are architecturally
9305 compatible, warn if they're not and prefer the -march ISA flags. */
9307 {
9309 {
9313 }
9318 }
9319 else
9320 {
9321 /* -mcpu but no -march. */
9328 }
9330 /* Set the arch as well as we will need it when outputing
9331 the .arch directive in assembly. */
9333 {
9336 }
9341 #ifndef HAVE_AS_MABI_OPTION
9342 /* The compiler may have been configured with 2.23.* binutils, which does
9343 not have support for ILP32. */
9346 #endif
9351 /* Make sure we properly set up the explicit options. */
9362 /* Save these options as the default ones in case we push and pop them later
9363 while processing functions with potential target attributes. */
9364 target_option_default_node = target_option_current_node
9366 }
9368 /* Implement targetm.override_options_after_change. */
9370 static void
9372 {
9374 }
9378 {
9382 }
9384 void
9386 {
9388 }
9390 /* A checking mechanism for the implementation of the various code models. */
9391 static void
9393 {
9395 {
9397 {
9402 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9404 ? AARCH64_CMODEL_SMALL_PIC
9406 #else
9408 #endif
9416 }
9417 }
9418 else
9420 }
9422 /* Implement TARGET_OPTION_SAVE. */
9424 static void
9426 {
9428 }
9430 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9431 using the information saved in PTR. */
9433 static void
9435 {
9443 }
9445 /* Implement TARGET_OPTION_PRINT. */
9447 static void
9449 {
9460 }
9464 void
9466 {
9468 }
9470 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9471 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9472 make sure optab availability predicates are recomputed when necessary. */
9474 void
9476 {
9481 else
9483 }
9485 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9486 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9487 of the function, if such exists. This function may be called multiple
9488 times on a single function so use aarch64_previous_fndecl to avoid
9489 setting up identical state. */
9491 static void
9493 {
9497 tree old_tree = (aarch64_previous_fndecl
9503 /* If current function has no attributes but the previous one did,
9504 use the default node. */
9508 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9509 the default have been handled by aarch64_save_restore_target_globals from
9510 aarch64_pragma_target_parse. */
9516 /* First set the target options. */
9520 }
9522 /* Enum describing the various ways we can handle attributes.
9523 In many cases we can reuse the generic option handling machinery. */
9525 enum aarch64_attr_opt_type
9526 {
9530 aarch64_attr_custom /* Attribute requires a custom handling function. */
9531 };
9533 /* All the information needed to handle a target attribute.
9534 NAME is the name of the attribute.
9535 ATTR_TYPE specifies the type of behavior of the attribute as described
9536 in the definition of enum aarch64_attr_opt_type.
9537 ALLOW_NEG is true if the attribute supports a "no-" form.
9538 HANDLER is the function that takes the attribute string and whether
9539 it is a pragma or attribute and handles the option. It is needed only
9540 when the ATTR_TYPE is aarch64_attr_custom.
9541 OPT_NUM is the enum specifying the option that the attribute modifies.
9542 This is needed for attributes that mirror the behavior of a command-line
9543 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9544 aarch64_attr_enum. */
9546 struct aarch64_attribute_info
9547 {
9553 };
9555 /* Handle the ARCH_STR argument to the arch= target attribute.
9556 PRAGMA_OR_ATTR is used in potential error messages. */
9558 static bool
9560 {
9562 enum aarch64_parse_opt_result parse_res
9566 {
9571 }
9574 {
9588 }
9591 }
9593 /* Handle the argument CPU_STR to the cpu= target attribute.
9594 PRAGMA_OR_ATTR is used in potential error messages. */
9596 static bool
9598 {
9600 enum aarch64_parse_opt_result parse_res
9604 {
9612 }
9615 {
9629 }
9632 }
9634 /* Handle the argument STR to the tune= target attribute.
9635 PRAGMA_OR_ATTR is used in potential error messages. */
9637 static bool
9639 {
9641 enum aarch64_parse_opt_result parse_res
9645 {
9650 }
9653 {
9660 }
9663 }
9665 /* Parse an architecture extensions target attribute string specified in STR.
9666 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9667 if successful. Update aarch64_isa_flags to reflect the ISA features
9668 modified.
9669 PRAGMA_OR_ATTR is used in potential error messages. */
9671 static bool
9673 {
9677 /* We allow "+nothing" in the beginning to clear out all architectural
9678 features if the user wants to handpick specific features. */
9680 {
9683 }
9688 {
9691 }
9694 {
9707 }
9710 }
9712 /* The target attributes that we support. On top of these we also support just
9713 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9714 handled explicitly in aarch64_process_one_target_attr. */
9717 {
9719 OPT_mgeneral_regs_only },
9721 OPT_mfix_cortex_a53_835769 },
9723 OPT_mfix_cortex_a53_843419 },
9727 OPT_momit_leaf_frame_pointer },
9730 OPT_march_ },
9733 OPT_mtune_ },
9735 OPT_msign_return_address_ },
9737 };
9739 /* Parse ARG_STR which contains the definition of one target attribute.
9740 Show appropriate errors if any or return true if the attribute is valid.
9741 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9742 we're processing a target attribute or pragma. */
9744 static bool
9746 {
9752 {
9755 }
9760 /* Skip leading whitespace. */
9762 str_to_check++;
9764 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9765 It is easier to detect and handle it explicitly here rather than going
9766 through the machinery for the rest of the target attributes in this
9767 function. */
9772 {
9775 }
9778 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9779 and point ARG to "foo". */
9781 {
9783 arg++;
9784 }
9788 {
9789 /* If the names don't match up, or the user has given an argument
9790 to an attribute that doesn't accept one, or didn't give an argument
9791 to an attribute that expects one, fail to match. */
9800 {
9804 }
9806 /* If the name matches but the attribute does not allow "no-" versions
9807 then we can't match. */
9809 {
9813 }
9816 {
9817 /* Has a custom handler registered.
9818 For example, cpu=, arch=, tune=. */
9825 /* Either set or unset a boolean option. */
9827 {
9835 }
9836 /* Set or unset a bit in the target_flags. aarch64_handle_option
9837 should know what mask to apply given the option number. */
9839 {
9841 /* We only need to specify the option number.
9842 aarch64_handle_option will know which mask to apply. */
9848 }
9849 /* Use the option setting machinery to set an option to an enum. */
9851 {
9858 {
9861 global_dc);
9862 }
9863 else
9864 {
9867 }
9869 }
9872 }
9873 }
9875 /* If we reached here we either have found an attribute and validated
9876 it or didn't match any. If we matched an attribute but its arguments
9877 were malformed we will have returned false already. */
9879 }
9881 /* Count how many times the character C appears in
9882 NULL-terminated string STR. */
9884 static unsigned int
9886 {
9889 {
9891 res++;
9893 str++;
9894 }
9897 }
9899 /* Parse the tree in ARGS that contains the target attribute information
9900 and update the global target options space. PRAGMA_OR_ATTR is a string
9901 to be used in error messages, specifying whether this is processing
9902 a target attribute or a target pragma. */
9904 bool
9906 {
9908 {
9909 do
9910 {
9913 {
9916 }
9921 }
9924 {
9927 }
9934 {
9937 }
9939 /* Used to catch empty spaces between commas i.e.
9940 attribute ((target ("attr1,,attr2"))). */
9943 /* Handle multiple target attributes separated by ','. */
9948 {
9949 num_attrs++;
9951 {
9954 }
9957 }
9960 {
9964 }
9967 }
9969 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9970 process attribute ((target ("..."))). */
9972 static bool
9974 {
9977 tree old_optimize;
9981 /* If what we're processing is the current pragma string then the
9982 target option node is already stored in target_option_current_node
9983 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9984 having to re-parse the string. This is especially useful to keep
9985 arm_neon.h compile times down since that header contains a lot
9986 of intrinsics enclosed in pragmas. */
9988 {
9991 }
9997 /* If the function changed the optimization levels as well as setting
9998 target options, start with the optimizations specified. */
10003 /* Save the current target options to restore at the end. */
10006 /* If fndecl already has some target attributes applied to it, unpack
10007 them so that we add this attribute on top of them, rather than
10008 overwriting them. */
10010 {
10016 }
10017 else
10024 /* Set up any additional state. */
10026 {
10028 /* Initialize SIMD builtins if we haven't already.
10029 Set current_target_pragma to NULL for the duration so that
10030 the builtin initialization code doesn't try to tag the functions
10031 being built with the attributes specified by any current pragma, thus
10032 going into an infinite recursion. */
10034 {
10039 }
10041 }
10042 else
10048 {
10053 }
10061 }
10063 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10064 tri-bool options (yes, no, don't care) and the default value is
10065 DEF, determine whether to reject inlining. */
10067 static bool
10070 {
10071 /* If the callee doesn't care, always allow inlining. */
10075 /* If the caller doesn't care, always allow inlining. */
10079 /* Otherwise, allow inlining if either the callee and caller values
10080 agree, or if the callee is using the default value. */
10082 }
10084 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10085 to inline CALLEE into CALLER based on target-specific info.
10086 Make sure that the caller and callee have compatible architectural
10087 features. Then go through the other possible target attributes
10088 and see if they can block inlining. Try not to reject always_inline
10089 callees unless they are incompatible architecturally. */
10091 static bool
10093 {
10097 /* If callee has no option attributes, then it is ok to inline. */
10108 /* Callee's ISA flags should be a subset of the caller's. */
10113 /* Allow non-strict aligned functions inlining into strict
10114 aligned ones. */
10124 /* If the architectural features match up and the callee is always_inline
10125 then the other attributes don't matter. */
10137 /* Honour explicit requests to workaround errata. */
10150 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10151 caller and calle and they don't match up, reject inlining. */
10158 /* If the callee has specific tuning overrides, respect them. */
10163 /* If the user specified tuning override strings for the
10164 caller and callee and they don't match up, reject inlining.
10165 We just do a string compare here, we don't analyze the meaning
10166 of the string, as it would be too costly for little gain. */
10174 }
10176 /* Return true if SYMBOL_REF X binds locally. */
10178 static bool
10180 {
10184 }
10186 /* Return true if SYMBOL_REF X is thread local */
10187 static bool
10189 {
10197 }
10199 /* Classify a TLS symbol into one of the TLS kinds. */
10200 enum aarch64_symbol_type
10202 {
10206 {
10213 {
10219 }
10230 else
10239 }
10240 }
10242 /* Return the method that should be used to access SYMBOL_REF or
10243 LABEL_REF X. */
10245 enum aarch64_symbol_type
10247 {
10249 {
10251 {
10266 }
10267 }
10270 {
10275 {
10277 /* When we retrieve symbol + offset address, we have to make sure
10278 the offset does not cause overflow of the final address. But
10279 we have no way of knowing the address of symbol at compile time
10280 so we can't accurately say if the distance between the PC and
10281 symbol + offset is outside the addressible range of +/-1M in the
10282 TINY code model. So we rely on images not being greater than
10283 1M and cap the offset at 1M and anything beyond 1M will have to
10284 be loaded using an alternative mechanism. Furthermore if the
10285 symbol is a weak reference to something that isn't known to
10286 resolve to a symbol in this module, then force to memory. */
10294 /* Same reasoning as the tiny code model, but the offset cap here is
10295 4G. */
10316 /* This is alright even in PIC code as the constant
10317 pool reference is always PC relative and within
10318 the same translation unit. */
10321 else
10326 }
10327 }
10329 /* By default push everything into the constant pool. */
10331 }
10333 bool
10335 {
10337 }
10339 bool
10341 {
10349 }
10351 /* Return true if X holds either a quarter-precision or
10352 floating-point +0.0 constant. */
10353 static bool
10355 {
10359 /* This call determines which constants can be used in mov<mode>
10360 as integer moves instead of constant loads. */
10365 }
10367 static bool
10369 {
10370 /* Do not allow vector struct mode constants. We could support
10371 0 and -1 easily, but they need support in aarch64-simd.md. */
10375 /* For these cases we never want to use a literal load.
10376 As such we have to prevent the compiler from forcing these
10377 to memory. */
10390 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10391 so spilling them is better than rematerialization. */
10396 }
10398 rtx
10400 {
10406 /* Can return in any reg. */
10409 }
10411 /* On AAPCS systems, this is the "struct __va_list". */
10414 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10415 Return the type to use as __builtin_va_list.
10417 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10419 struct __va_list
10420 {
10421 void *__stack;
10422 void *__gr_top;
10423 void *__vr_top;
10424 int __gr_offs;
10425 int __vr_offs;
10426 }; */
10428 static tree
10430 {
10431 tree va_list_name;
10434 /* Create the type. */
10436 /* Give it the required name. */
10438 TYPE_DECL,
10440 va_list_type);
10445 /* Create the fields. */
10448 ptr_type_node);
10451 ptr_type_node);
10454 ptr_type_node);
10457 integer_type_node);
10460 integer_type_node);
10462 /* Tell tree-stdarg pass about our internal offset fields.
10463 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10464 purpose to identify whether the code is updating va_list internal
10465 offset fields through irregular way. */
10487 /* Compute its layout. */
10491 }
10493 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10494 static void
10496 {
10500 tree t;
10514 {
10517 }
10526 NULL_TREE);
10528 NULL_TREE);
10530 NULL_TREE);
10532 NULL_TREE);
10534 NULL_TREE);
10536 /* Emit code to initialize STACK, which points to the next varargs stack
10537 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10538 by named arguments. STACK is 8-byte aligned. */
10545 /* Emit code to initialize GRTOP, the top of the GR save area.
10546 virtual_incoming_args_rtx should have been 16 byte aligned. */
10551 /* Emit code to initialize VRTOP, the top of the VR save area.
10552 This address is gr_save_area_bytes below GRTOP, rounded
10553 down to the next 16-byte boundary. */
10563 /* Emit code to initialize GROFF, the offset from GRTOP of the
10564 next GPR argument. */
10569 /* Likewise emit code to initialize VROFF, the offset from FTOP
10570 of the next VR argument. */
10574 }
10576 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10578 static tree
10581 {
10582 tree addr;
10588 machine_mode mode;
10615 type,
10619 {
10620 /* TYPE passed in fp/simd registers. */
10632 {
10635 }
10638 {
10640 }
10641 }
10642 else
10643 {
10644 /* TYPE passed in general registers. */
10657 {
10659 }
10660 }
10662 /* Get a local temporary for the field value. */
10665 /* Emit code to branch if off >= 0. */
10671 {
10672 /* Emit: offs = (offs + 15) & -16. */
10678 }
10679 else
10682 /* Update ap.__[g|v]r_offs */
10687 /* String up. */
10691 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10696 /* String up: make sure the assignment happens before the use. */
10700 /* Prepare the trees handling the argument that is passed on the stack;
10701 the top level node will store in ON_STACK. */
10704 {
10705 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10713 }
10714 else
10716 /* Advance ap.__stack */
10724 /* String up roundup and advance. */
10727 /* String up with arg */
10729 /* Big-endianness related address adjustment. */
10732 {
10736 }
10741 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10751 {
10752 /* type ha; // treat as "struct {ftype field[n];}"
10753 ... [computing offs]
10754 for (i = 0; i <nregs; ++i, offs += 16)
10755 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10756 return ha; */
10760 /* Declare a local variable. */
10764 /* Establish the base type. */
10766 {
10785 {
10789 }
10793 }
10795 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10803 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10805 {
10815 }
10819 }
10829 }
10831 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10833 static void
10837 {
10839 CUMULATIVE_ARGS local_cum;
10843 /* The caller has advanced CUM up to, but not beyond, the last named
10844 argument. Advance a local copy of CUM past the last "real" named
10845 argument, to find out how many registers are left over. */
10849 /* Found out how many registers we need to save.
10850 Honor tree-stdvar analysis results. */
10859 {
10862 }
10865 {
10867 {
10870 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10878 }
10880 {
10881 /* We can't use move_block_from_reg, because it will use
10882 the wrong mode, storing D regs only. */
10886 /* Set OFF to the offset from virtual_incoming_args_rtx of
10887 the first vector register. The VR save area lies below
10888 the GR one, and is aligned to 16 bytes. */
10895 {
10903 }
10904 }
10905 }
10907 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10908 any complication of having crtl->args.pretend_args_size changed. */
10913 }
10915 static void
10917 {
10920 {
10922 {
10925 }
10926 }
10927 }
10929 /* Walk down the type tree of TYPE counting consecutive base elements.
10930 If *MODEP is VOIDmode, then set it to the first valid floating point
10931 type. If a non-floating point type is found, or if a floating point
10932 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10933 otherwise return the count in the sub-tree. */
10934 static int
10936 {
10937 machine_mode mode;
10938 HOST_WIDE_INT size;
10941 {
10971 /* Use V2SImode and V4SImode as representatives of all 64-bit
10972 and 128-bit vector types. */
10975 {
10984 }
10989 /* Vector modes are considered to be opaque: two vectors are
10990 equivalent for the purposes of being homogeneous aggregates
10991 if they are the same size. */
10998 {
11002 /* Can't handle incomplete types nor sizes that are not
11003 fixed. */
11010 || !index
11021 /* There must be no padding. */
11026 }
11029 {
11032 tree field;
11034 /* Can't handle incomplete types nor sizes that are not
11035 fixed. */
11041 {
11049 }
11051 /* There must be no padding. */
11056 }
11060 {
11061 /* These aren't very interesting except in a degenerate case. */
11064 tree field;
11066 /* Can't handle incomplete types nor sizes that are not
11067 fixed. */
11073 {
11081 }
11083 /* There must be no padding. */
11088 }
11092 }
11095 }
11097 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11098 type as described in AAPCS64 \S 4.1.2.
11100 See the comment above aarch64_composite_type_p for the notes on MODE. */
11102 static bool
11104 machine_mode mode)
11105 {
11115 }
11117 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11118 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11119 array types. The C99 floating-point complex types are also considered
11120 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11121 types, which are GCC extensions and out of the scope of AAPCS64, are
11122 treated as composite types here as well.
11124 Note that MODE itself is not sufficient in determining whether a type
11125 is such a composite type or not. This is because
11126 stor-layout.c:compute_record_mode may have already changed the MODE
11127 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11128 structure with only one field may have its MODE set to the mode of the
11129 field. Also an integer mode whose size matches the size of the
11130 RECORD_TYPE type may be used to substitute the original mode
11131 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11132 solely relied on. */
11134 static bool
11136 machine_mode mode)
11137 {
11150 }
11152 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11153 shall be passed or returned in simd/fp register(s) (providing these
11154 parameter passing registers are available).
11156 Upon successful return, *COUNT returns the number of needed registers,
11157 *BASE_MODE returns the mode of the individual register and when IS_HAF
11158 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11159 floating-point aggregate or a homogeneous short-vector aggregate. */
11161 static bool
11163 const_tree type,
11167 {
11175 {
11178 }
11180 {
11184 }
11186 {
11190 {
11193 }
11194 else
11196 }
11197 else
11202 }
11204 /* Implement TARGET_STRUCT_VALUE_RTX. */
11206 static rtx
11209 {
11211 }
11213 /* Implements target hook vector_mode_supported_p. */
11214 static bool
11216 {
11228 }
11230 /* Return appropriate SIMD container
11231 for MODE within a vector of WIDTH bits. */
11232 static machine_mode
11234 {
11237 {
11240 {
11257 }
11258 else
11260 {
11273 }
11274 }
11276 }
11278 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11279 static machine_mode
11281 {
11283 }
11285 /* Return the bitmask of possible vector sizes for the vectorizer
11286 to iterate over. */
11287 static unsigned int
11289 {
11291 }
11293 /* Implement TARGET_MANGLE_TYPE. */
11297 {
11298 /* The AArch64 ABI documents say that "__va_list" has to be
11299 managled as if it is in the "std" namespace. */
11303 /* Half-precision float. */
11307 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11308 builtin types. */
11312 /* Use the default mangling. */
11314 }
11316 /* Find the first rtx_insn before insn that will generate an assembly
11317 instruction. */
11321 {
11325 do
11326 {
11328 }
11332 }
11334 static bool
11336 {
11338 /* A number of these may be AArch32 only. */
11343 };
11346 {
11349 }
11352 }
11354 /* Check if there is a register dependency between a load and the insn
11355 for which we hold recog_data. */
11357 static bool
11359 {
11360 rtx load_reg;
11370 {
11376 }
11378 }
11381 /* When working around the Cortex-A53 erratum 835769,
11382 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11383 instruction and has a preceding memory instruction such that a NOP
11384 should be inserted between them. */
11386 bool
11388 {
11391 rtx body;
11404 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11405 Restore recog state to INSN to avoid state corruption. */
11413 /* If the previous insn is a memory op and there is no dependency between
11414 it and the DImode madd, emit a NOP between them. If body is NULL then we
11415 have a complex memory operation, probably a load/store pair.
11416 Be conservative for now and emit a NOP. */
11423 }
11426 /* Implement FINAL_PRESCAN_INSN. */
11428 void
11430 {
11433 }
11436 /* Return the equivalent letter for size. */
11437 static char
11439 {
11441 {
11447 }
11448 }
11450 /* Return true iff x is a uniform vector of floating-point
11451 constants, and the constant can be represented in
11452 quarter-precision form. Note, as aarch64_float_const_representable
11453 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11454 static bool
11456 {
11457 rtx elt;
11461 }
11463 /* Return true for valid and false for invalid. */
11464 bool
11467 {
11468 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11469 matches = 1; \
11470 for (i = 0; i < idx; i += (STRIDE)) \
11471 if (!(TEST)) \
11472 matches = 0; \
11473 if (matches) \
11474 { \
11475 immtype = (CLASS); \
11476 elsize = (ELSIZE); \
11477 eshift = (SHIFT); \
11478 emvn = (NEG); \
11479 break; \
11480 }
11490 {
11496 {
11498 scalar_float_mode elt_mode
11505 }
11508 }
11510 /* Splat vector constant out into a byte vector. */
11512 {
11513 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11514 it must be laid out in the vector register in reverse order. */
11522 {
11525 }
11527 }
11529 /* Sanity check. */
11532 do
11533 {
11582 }
11589 {
11599 /* Un-invert bytes of recognized vector, if necessary. */
11605 {
11606 /* FIXME: Broken on 32-bit H_W_I hosts. */
11615 }
11616 else
11617 {
11621 /* Construct 'abcdefgh' because the assembler cannot handle
11622 generic constants. */
11627 }
11628 }
11631 #undef CHECK
11632 }
11634 /* Check of immediate shift constants are within range. */
11635 bool
11637 {
11641 else
11643 }
11645 /* Return true if X is a uniform vector where all elements
11646 are either the floating-point constant 0.0 or the
11647 integer constant 0. */
11648 bool
11650 {
11652 }
11655 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11656 operation of width WIDTH at bit position POS. */
11658 rtx
11660 {
11664 unsigned HOST_WIDE_INT mask
11667 }
11669 bool
11671 {
11684 }
11686 /* Return a const_int vector of VAL. */
11687 rtx
11689 {
11700 }
11702 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11704 bool
11706 {
11707 machine_mode vmode;
11713 }
11715 /* Construct and return a PARALLEL RTX vector with elements numbering the
11716 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11717 the vector - from the perspective of the architecture. This does not
11718 line up with GCC's perspective on lane numbers, so we end up with
11719 different masks depending on our target endian-ness. The diagram
11720 below may help. We must draw the distinction when building masks
11721 which select one half of the vector. An instruction selecting
11722 architectural low-lanes for a big-endian target, must be described using
11723 a mask selecting GCC high-lanes.
11725 Big-Endian Little-Endian
11727 GCC 0 1 2 3 3 2 1 0
11728 | x | x | x | x | | x | x | x | x |
11729 Architecture 3 2 1 0 3 2 1 0
11731 Low Mask: { 2, 3 } { 0, 1 }
11732 High Mask: { 0, 1 } { 2, 3 }
11733 */
11735 rtx
11737 {
11743 rtx t1;
11748 else
11756 }
11758 /* Check OP for validity as a PARALLEL RTX vector with elements
11759 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11760 from the perspective of the architecture. See the diagram above
11761 aarch64_simd_vect_par_cnst_half for more details. */
11763 bool
11766 {
11779 {
11786 }
11788 }
11790 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11791 HIGH (exclusive). */
11792 void
11794 const_tree exp)
11795 {
11796 HOST_WIDE_INT lane;
11801 {
11804 else
11806 }
11807 }
11809 /* Return TRUE if OP is a valid vector addressing mode. */
11810 bool
11812 {
11815 }
11817 /* Emit a register copy from operand to operand, taking care not to
11818 early-clobber source registers in the process.
11820 COUNT is the number of components into which the copy needs to be
11821 decomposed. */
11822 void
11825 {
11835 else
11839 }
11841 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11842 one of VSTRUCT modes: OI, CI, or XI. */
11843 int
11845 {
11847 }
11849 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11850 alignment of a vector to 128 bits. */
11851 static HOST_WIDE_INT
11853 {
11856 }
11858 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11859 static bool
11861 {
11865 /* We guarantee alignment for vectors up to 128-bits. */
11870 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11872 }
11874 /* Return true if the vector misalignment factor is supported by the
11875 target. */
11876 static bool
11880 {
11882 {
11883 /* Return if movmisalign pattern is not supported for this mode. */
11888 {
11889 /* Misalignment factor is unknown at compile time but we know
11890 it's word aligned. */
11892 {
11897 }
11899 }
11900 }
11902 is_packed);
11903 }
11905 /* If VALS is a vector constant that can be loaded into a register
11906 using DUP, generate instructions to do so and return an RTX to
11907 assign to the register. Otherwise return NULL_RTX. */
11908 static rtx
11910 {
11913 rtx x;
11918 /* We can load this constant by using DUP and a constant in a
11919 single ARM register. This will be cheaper than a vector
11920 load. */
11923 }
11926 /* Generate code to load VALS, which is a PARALLEL containing only
11927 constants (for vec_init) or CONST_VECTOR, efficiently into a
11928 register. Returns an RTX to copy into the register, or NULL_RTX
11929 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11930 static rtx
11932 {
11934 rtx const_dup;
11943 {
11944 /* A CONST_VECTOR must contain only CONST_INTs and
11945 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11946 Only store valid constants in a CONST_VECTOR. */
11948 {
11951 n_const++;
11952 }
11955 }
11956 else
11961 /* Load using MOVI/MVNI. */
11964 /* Loaded using DUP. */
11967 /* Load from constant pool. We can not take advantage of single-cycle
11968 LD1 because we need a PC-relative addressing mode. */
11970 else
11971 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11972 We can not construct an initializer. */
11974 }
11976 /* Expand a vector initialisation sequence, such that TARGET is
11977 initialised to contain VALS. */
11979 void
11981 {
11984 /* The number of vector elements. */
11986 /* The number of vector elements which are not constant. */
11989 /* The first element of vals. */
11993 /* Count the number of variable elements to initialise. */
11995 {
11999 else
12003 }
12005 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12006 how best to handle this. */
12008 {
12011 {
12014 }
12015 }
12017 /* Splat a single non-constant element if we can. */
12019 {
12023 }
12028 /* If there are only variable elements, try to optimize
12029 the insertion using dup for the most common element
12030 followed by insertions. */
12032 /* The algorithm will fill matches[*][0] with the earliest matching element,
12033 and matches[X][1] with the count of duplicate elements (if X is the
12034 earliest element which has duplicates). */
12037 {
12040 {
12042 {
12044 {
12048 }
12049 }
12050 }
12055 {
12058 }
12060 /* Create a duplicate of the most common element. */
12064 /* Insert the rest. */
12066 {
12072 }
12074 }
12076 /* Initialise a vector which is part-variable. We want to first try
12077 to build those lanes which are constant in the most efficient way we
12078 can. */
12080 {
12083 /* Load constant part of vector. We really don't care what goes into the
12084 parts we will overwrite, but we're more likely to be able to load the
12085 constant efficiently if it has fewer, larger, repeating parts
12086 (see aarch64_simd_valid_immediate). */
12088 {
12094 {
12095 /* Look in the copied vector, as more elements are const. */
12098 {
12101 }
12102 }
12104 }
12106 }
12108 /* Insert the variable lanes directly. */
12110 {
12116 }
12117 }
12119 static unsigned HOST_WIDE_INT
12121 {
12122 return
12123 (!SHIFT_COUNT_TRUNCATED
12126 }
12128 /* Select a format to encode pointers in exception handling data. */
12129 int
12131 {
12134 {
12140 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12141 for everything. */
12145 /* No assumptions here. 8-byte relocs required. */
12148 }
12150 }
12152 /* The last .arch and .tune assembly strings that we printed. */
12156 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12157 by the function fndecl. */
12159 void
12161 tree fndecl)
12162 {
12168 else
12179 /* Only update the assembler .arch string if it is distinct from the last
12180 such string we printed. */
12183 {
12186 }
12188 /* Print the cpu name we're tuning for in the comments, might be
12189 useful to readers of the generated asm. Do it only when it changes
12190 from function to function and verbose assembly is requested. */
12195 {
12199 }
12201 /* Don't forget the type directive for ELF. */
12204 }
12206 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12208 static void
12210 {
12227 }
12229 /* Emit load exclusive. */
12231 static void
12234 {
12238 {
12245 }
12248 }
12250 /* Emit store exclusive. */
12252 static void
12255 {
12259 {
12266 }
12269 }
12271 /* Mark the previous jump instruction as unlikely. */
12273 static void
12275 {
12278 }
12280 /* Expand a compare and swap pattern. */
12282 void
12284 {
12289 gen_cas_fn gen;
12291 {
12292 gen_aarch64_compare_and_swapqi,
12293 gen_aarch64_compare_and_swaphi,
12294 gen_aarch64_compare_and_swapsi,
12295 gen_aarch64_compare_and_swapdi
12296 };
12298 {
12299 gen_aarch64_compare_and_swapqi_lse,
12300 gen_aarch64_compare_and_swaphi_lse,
12301 gen_aarch64_compare_and_swapsi_lse,
12302 gen_aarch64_compare_and_swapdi_lse
12303 };
12316 /* Normally the succ memory model must be stronger than fail, but in the
12317 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12318 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12325 {
12328 /* For short modes, we're going to perform the comparison in SImode,
12329 so do the zero-extension now. */
12333 /* Fall through. */
12337 /* Force the value into a register if needed. */
12344 }
12347 {
12354 }
12357 else
12368 }
12370 /* Test whether the target supports using a atomic load-operate instruction.
12371 CODE is the operation and AFTER is TRUE if the data in memory after the
12372 operation should be returned and FALSE if the data before the operation
12373 should be returned. Returns FALSE if the operation isn't supported by the
12374 architecture. */
12376 bool
12378 {
12383 {
12393 }
12394 }
12396 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12397 sequence implementing an atomic operation. */
12399 static void
12401 {
12408 {
12410 }
12411 }
12413 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12414 for the data in memory. EXPECTED is the value expected to be in memory.
12415 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12416 is the memory ordering to use. */
12418 void
12421 rtx model)
12422 {
12424 machine_mode mode;
12429 {
12436 }
12438 /* Move the expected value into the CAS destination register. */
12441 /* Emit the CAS. */
12444 /* Compare the expected value with the value loaded by the CAS, to establish
12445 whether the swap was made. */
12447 }
12449 /* Split a compare and swap pattern. */
12451 void
12453 {
12455 machine_mode mode;
12460 rtx model_rtx;
12472 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12473 loop:
12474 .label1:
12475 LD[A]XR rval, [mem]
12476 CBNZ rval, .label2
12477 ST[L]XR scratch, newval, [mem]
12478 CBNZ scratch, .label1
12479 .label2:
12480 CMP rval, 0. */
12485 {
12488 }
12491 /* The initial load can be relaxed for a __sync operation since a final
12492 barrier will be emitted to stop code hoisting. */
12496 else
12500 {
12505 }
12506 else
12507 {
12513 }
12518 {
12523 }
12524 else
12525 {
12529 }
12532 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12533 to set the condition flags. If this is not used it will be removed by
12534 later passes. */
12536 {
12540 }
12541 /* Emit any final barrier needed for a __sync operation. */
12544 }
12546 /* Emit a BIC instruction. */
12548 static void
12550 {
12555 {
12560 }
12563 }
12565 /* Emit an atomic swap. */
12567 static void
12570 {
12574 {
12581 }
12584 }
12586 /* Operations supported by aarch64_emit_atomic_load_op. */
12588 enum aarch64_atomic_load_op_code
12589 {
12593 AARCH64_LDOP_BIC /* A & ~B */
12594 };
12596 /* Emit an atomic load-operate. */
12598 static void
12602 {
12605 {
12606 gen_aarch64_atomic_loadaddqi,
12607 gen_aarch64_atomic_loadaddhi,
12608 gen_aarch64_atomic_loadaddsi,
12609 gen_aarch64_atomic_loadadddi
12610 };
12612 {
12613 gen_aarch64_atomic_loadeorqi,
12614 gen_aarch64_atomic_loadeorhi,
12615 gen_aarch64_atomic_loadeorsi,
12616 gen_aarch64_atomic_loadeordi
12617 };
12619 {
12620 gen_aarch64_atomic_loadsetqi,
12621 gen_aarch64_atomic_loadsethi,
12622 gen_aarch64_atomic_loadsetsi,
12623 gen_aarch64_atomic_loadsetdi
12624 };
12626 {
12627 gen_aarch64_atomic_loadclrqi,
12628 gen_aarch64_atomic_loadclrhi,
12629 gen_aarch64_atomic_loadclrsi,
12630 gen_aarch64_atomic_loadclrdi
12631 };
12632 aarch64_atomic_load_op_fn gen;
12636 {
12643 }
12646 {
12653 }
12656 }
12658 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12659 location to store the data read from memory. OUT_RESULT is the location to
12660 store the result of the operation. MEM is the memory location to read and
12661 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12662 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12663 be NULL. */
12665 void
12668 {
12672 aarch64_atomic_load_op_code ldop_code;
12673 rtx src;
12674 rtx x;
12682 /* Make sure the value is in a register, putting it into a destination
12683 register if it needs to be manipulated. */
12686 {
12689 }
12690 else
12694 /* Preprocess the data for the operation as necessary. If the operation is
12695 a SET then emit a swap instruction and finish. */
12697 {
12703 /* Negate the value and treat it as a PLUS. */
12704 {
12705 rtx neg_src;
12707 /* Resize the value if necessary. */
12716 }
12717 /* Fall-through. */
12731 {
12732 rtx not_src;
12734 /* Resize the value if necessary. */
12743 }
12748 /* The operation can't be done with atomic instructions. */
12750 }
12754 /* If necessary, calculate the data in memory after the update by redoing the
12755 operation from values in registers. */
12760 {
12764 }
12769 {
12785 }
12790 }
12792 /* Split an atomic operation. */
12794 void
12797 {
12803 rtx x;
12805 /* Split the atomic operation into a sequence. */
12813 else
12817 /* The initial load can be relaxed for a __sync operation since a final
12818 barrier will be emitted to stop code hoisting. */
12822 else
12826 {
12840 {
12843 }
12844 /* Fall through. */
12850 }
12860 /* Emit any final barrier needed for a __sync operation. */
12863 }
12865 static void
12867 {
12868 /* Half-precision float operations. The compiler handles all operations
12869 with NULL libfuncs by converting to SFmode. */
12871 /* Conversions. */
12875 /* Arithmetic. */
12882 /* Comparisons. */
12890 }
12892 /* Target hook for c_mode_for_suffix. */
12893 static machine_mode
12895 {
12900 }
12902 /* We can only represent floating point constants which will fit in
12903 "quarter-precision" values. These values are characterised by
12904 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12905 by:
12907 (-1)^s * (n/16) * 2^r
12909 Where:
12910 's' is the sign bit.
12911 'n' is an integer in the range 16 <= n <= 31.
12912 'r' is an integer in the range -3 <= r <= 4. */
12914 /* Return true iff X can be represented by a quarter-precision
12915 floating point immediate operand X. Note, we cannot represent 0.0. */
12916 bool
12918 {
12919 /* This represents our current view of how many bits
12920 make up the mantissa. */
12930 /* We don't support HFmode constants yet. */
12936 /* We cannot represent infinities, NaNs or +/-zero. We won't
12937 know if we have +zero until we analyse the mantissa, but we
12938 can reject the other invalid values. */
12943 /* Extract exponent. */
12947 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12948 highest (sign) bit, with a fixed binary point at bit point_pos.
12949 m1 holds the low part of the mantissa, m2 the high part.
12950 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12951 bits for the mantissa, this can fail (low bits will be lost). */
12955 /* If the low part of the mantissa has bits set we cannot represent
12956 the value. */
12959 /* We have rejected the lower HOST_WIDE_INT, so update our
12960 understanding of how many bits lie in the mantissa and
12961 look only at the high HOST_WIDE_INT. */
12965 /* We can only represent values with a mantissa of the form 1.xxxx. */
12970 /* Having filtered unrepresentable values, we may now remove all
12971 but the highest 5 bits. */
12974 /* We cannot represent the value 0.0, so reject it. This is handled
12975 elsewhere. */
12979 /* Then, as bit 4 is always set, we can mask it off, leaving
12980 the mantissa in the range [0, 15]. */
12984 /* GCC internally does not use IEEE754-like encoding (where normalized
12985 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12986 Our mantissa values are shifted 4 places to the left relative to
12987 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12988 by 5 places to correct for GCC's representation. */
12992 }
12996 machine_mode mode,
12998 {
13008 /* This will return true to show const_vector is legal for use as either
13009 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
13010 also update INFO to show how the immediate should be generated. */
13019 {
13021 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13022 move immediate path. */
13025 else
13026 {
13035 else
13039 }
13040 }
13053 else
13057 }
13061 {
13063 /* If a floating point number was passed and we desire to use it in an
13064 integer mode do the conversion to integer. */
13066 {
13071 }
13073 machine_mode vmode;
13074 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13075 a 128 bit vector mode. */
13082 }
13084 /* Split operands into moves from op[1] + op[2] into op[0]. */
13086 void
13088 {
13099 {
13100 /* No-op move. Can't split to nothing; emit something. */
13103 }
13105 /* Preserve register attributes for variable tracking. */
13110 /* Special case of reversed high/low parts. */
13113 {
13117 }
13119 {
13120 /* Try to avoid unnecessary moves if part of the result
13121 is in the right place already. */
13126 }
13127 else
13128 {
13133 }
13134 }
13136 /* vec_perm support. */
13138 #define MAX_VECT_LEN 16
13140 struct expand_vec_perm_d
13141 {
13144 machine_mode vmode;
13148 };
13150 /* Generate a variable permutation. */
13152 static void
13154 {
13165 {
13167 {
13168 /* Expand the argument to a V16QI mode by duplicating it. */
13172 }
13173 else
13174 {
13176 }
13177 }
13178 else
13179 {
13180 rtx pair;
13183 {
13187 }
13188 else
13189 {
13193 }
13194 }
13195 }
13197 void
13199 {
13203 rtx mask;
13205 /* The TBL instruction does not use a modulo index, so we must take care
13206 of that ourselves. */
13211 /* For big-endian, we also need to reverse the index within the vector
13212 (but not which vector). */
13214 {
13215 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13220 }
13222 }
13224 /* Recognize patterns suitable for the TRN instructions. */
13225 static bool
13227 {
13236 /* Note that these are little-endian tests.
13237 We correct for big-endian later. */
13242 else
13247 {
13252 }
13254 /* Success! */
13261 {
13264 }
13268 {
13270 {
13285 }
13286 }
13287 else
13288 {
13290 {
13305 }
13306 }
13310 }
13312 /* Recognize patterns suitable for the UZP instructions. */
13313 static bool
13315 {
13324 /* Note that these are little-endian tests.
13325 We correct for big-endian later. */
13330 else
13335 {
13339 }
13341 /* Success! */
13348 {
13351 }
13355 {
13357 {
13372 }
13373 }
13374 else
13375 {
13377 {
13392 }
13393 }
13397 }
13399 /* Recognize patterns suitable for the ZIP instructions. */
13400 static bool
13402 {
13411 /* Note that these are little-endian tests.
13412 We correct for big-endian later. */
13415 /* Do Nothing. */
13416 ;
13419 else
13424 {
13431 }
13433 /* Success! */
13440 {
13443 }
13447 {
13449 {
13464 }
13465 }
13466 else
13467 {
13469 {
13484 }
13485 }
13489 }
13491 /* Recognize patterns for the EXT insn. */
13493 static bool
13495 {
13498 rtx offset;
13502 /* Check if the extracted indices are increasing by one. */
13504 {
13507 {
13508 /* We'll pass the same vector in twice, so allow indices to wrap. */
13510 }
13513 }
13516 {
13531 }
13533 /* Success! */
13537 /* The case where (location == 0) is a no-op for both big- and little-endian,
13538 and is removed by the mid-end at optimization levels -O1 and higher. */
13541 {
13542 /* After setup, we want the high elements of the first vector (stored
13543 at the LSB end of the register), and the low elements of the second
13544 vector (stored at the MSB end of the register). So swap. */
13546 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13548 }
13553 }
13555 /* Recognize patterns for the REV insns. */
13557 static bool
13559 {
13568 {
13571 {
13576 }
13580 {
13587 }
13591 {
13604 }
13608 }
13612 {
13613 /* This is guaranteed to be true as the value of diff
13614 is 7, 3, 1 and we should have enough elements in the
13615 queue to generate this. Getting a vector mask with a
13616 value of diff other than these values implies that
13617 something is wrong by the time we get here. */
13621 }
13623 /* Success! */
13629 }
13631 static bool
13633 {
13636 rtx in0;
13639 rtx lane;
13643 {
13646 }
13648 /* The generic preparation in aarch64_expand_vec_perm_const_1
13649 swaps the operand order and the permute indices if it finds
13650 d->perm[0] to be in the second operand. Thus, we can always
13651 use d->op0 and need not do any extra arithmetic to get the
13652 correct lane number. */
13657 {
13672 }
13676 }
13678 static bool
13680 {
13688 /* Generic code will try constant permutation twice. Once with the
13689 original mode and again with the elements lowered to QImode.
13690 So wait and don't do the selector expansion ourselves. */
13695 {
13698 /* If big-endian and two vectors we end up with a weird mixed-endian
13699 mode on NEON. Reverse the index within each word but not the word
13700 itself. */
13703 }
13709 }
13711 static bool
13713 {
13714 /* The pattern matching functions above are written to look for a small
13715 number to begin the sequence (0, 1, N/2). If we begin with an index
13716 from the second operand, we can swap the operands. */
13718 {
13726 }
13729 {
13743 }
13745 }
13747 /* Expand a vec_perm_const pattern. */
13749 bool
13751 {
13765 {
13770 }
13773 {
13782 /* The elements of PERM do not suggest that only the first operand
13783 is used, but both operands are identical. Allow easier matching
13784 of the permutation by folding the permutation into the single
13785 input vector. */
13786 /* Fall Through. */
13798 }
13801 }
13803 static bool
13806 {
13816 /* Calculate whether all elements are in one vector. */
13818 {
13822 }
13824 /* If all elements are from the second vector, reindex as if from the
13825 first vector. */
13830 /* Check whether the mask can be applied to a single vector. */
13843 }
13845 rtx
13847 {
13848 /* We have to reverse each vector because we dont have
13849 a permuted load that can reverse-load according to ABI rules. */
13850 rtx mask;
13864 }
13866 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13867 However due to issues with register allocation it is preferable to avoid
13868 tieing integer scalar and FP scalar modes. Executing integer operations
13869 in general registers is better than treating them as scalar vector
13870 operations. This reduces latency and avoids redundant int<->FP moves.
13871 So tie modes if they are either the same class, or vector modes with
13872 other vector modes, vector structs or any scalar mode.
13873 */
13875 bool
13877 {
13881 /* We specifically want to allow elements of "structure" modes to
13882 be tieable to the structure. This more general condition allows
13883 other rarer situations too. */
13887 /* Also allow any scalar modes with vectors. */
13893 }
13895 /* Return a new RTX holding the result of moving POINTER forward by
13896 AMOUNT bytes. */
13898 static rtx
13900 {
13905 }
13907 /* Return a new RTX holding the result of moving POINTER forward by the
13908 size of the mode it points to. */
13910 static rtx
13912 {
13916 }
13918 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13919 MODE bytes. */
13921 static void
13923 machine_mode mode)
13924 {
13927 /* "Cast" the pointers to the correct mode. */
13930 /* Emit the memcpy. */
13933 /* Move the pointers forward. */
13936 }
13938 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13939 we succeed, otherwise return false. */
13941 bool
13943 {
13947 rtx base;
13950 /* When optimizing for size, give a better estimate of the length of a
13951 memcpy call, but use the default otherwise. */
13954 /* We can't do anything smart if the amount to copy is not constant. */
13960 /* Try to keep the number of instructions low. For cases below 16 bytes we
13961 need to make at most two moves. For cases above 16 bytes it will be one
13962 move for each 16 byte chunk, then at most two additional moves. */
13972 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13973 1-byte chunk. */
13975 {
13977 {
13980 }
13986 }
13988 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13989 4-byte chunk, partially overlapping with the previously copied chunk. */
13991 {
13995 {
14001 }
14003 }
14005 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14006 them, then (if applicable) an 8-byte chunk. */
14008 {
14010 {
14013 }
14014 else
14015 {
14018 }
14019 }
14021 /* Finish the final bytes of the copy. We can always do this in one
14022 instruction. We either copy the exact amount we need, or partially
14023 overlap with the previous chunk we copied and copy 8-bytes. */
14032 else
14033 {
14035 {
14039 }
14040 else
14041 {
14047 }
14048 }
14051 }
14053 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14054 SImode stores. Handle the case when the constant has identical
14055 bottom and top halves. This is beneficial when the two stores can be
14056 merged into an STP and we avoid synthesising potentially expensive
14057 immediates twice. Return true if such a split is possible. */
14059 bool
14061 {
14070 unsigned int orig_cost
14072 unsigned int lo_cost
14075 /* We want to transform:
14076 MOV x1, 49370
14077 MOVK x1, 0x140, lsl 16
14078 MOVK x1, 0xc0da, lsl 32
14079 MOVK x1, 0x140, lsl 48
14080 STR x1, [x0]
14081 into:
14082 MOV w1, 49370
14083 MOVK w1, 0x140, lsl 16
14084 STP w1, w1, [x0]
14085 So we want to perform this only when we save two instructions
14086 or more. When optimizing for size, however, accept any code size
14087 savings we can. */
14102 /* Don't emit an explicit store pair as this may not be always profitable.
14103 Let the sched-fusion logic decide whether to merge them. */
14108 }
14110 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14112 static unsigned HOST_WIDE_INT
14114 {
14116 }
14118 static bool
14123 {
14124 /* STORE_BY_PIECES can be used when copying a constant string, but
14125 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14126 For now we always fail this and let the move_by_pieces code copy
14127 the string from read-only memory. */
14132 }
14134 static rtx
14137 {
14141 insn_code icode;
14152 {
14180 }
14185 {
14188 }
14197 {
14200 }
14206 }
14208 static rtx
14211 {
14215 insn_code icode;
14227 {
14255 }
14260 {
14263 }
14271 {
14276 }
14287 {
14290 }
14296 }
14298 #undef TARGET_GEN_CCMP_FIRST
14299 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14301 #undef TARGET_GEN_CCMP_NEXT
14302 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14304 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14305 instruction fusion of some sort. */
14307 static bool
14309 {
14311 }
14314 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14315 should be kept together during scheduling. */
14317 static bool
14319 {
14320 rtx set_dest;
14323 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14330 {
14331 /* We are trying to match:
14332 prev (mov) == (set (reg r0) (const_int imm16))
14333 curr (movk) == (set (zero_extract (reg r0)
14334 (const_int 16)
14335 (const_int 16))
14336 (const_int imm16_1)) */
14348 {
14350 }
14351 }
14354 {
14356 /* We're trying to match:
14357 prev (adrp) == (set (reg r1)
14358 (high (symbol_ref ("SYM"))))
14359 curr (add) == (set (reg r0)
14360 (lo_sum (reg r1)
14361 (symbol_ref ("SYM"))))
14362 Note that r0 need not necessarily be the same as r1, especially
14363 during pre-regalloc scheduling. */
14367 {
14375 }
14376 }
14379 {
14381 /* We're trying to match:
14382 prev (movk) == (set (zero_extract (reg r0)
14383 (const_int 16)
14384 (const_int 32))
14385 (const_int imm16_1))
14386 curr (movk) == (set (zero_extract (reg r0)
14387 (const_int 16)
14388 (const_int 48))
14389 (const_int imm16_2)) */
14405 }
14407 {
14408 /* We're trying to match:
14409 prev (adrp) == (set (reg r0)
14410 (high (symbol_ref ("SYM"))))
14411 curr (ldr) == (set (reg r1)
14412 (mem (lo_sum (reg r0)
14413 (symbol_ref ("SYM")))))
14414 or
14415 curr (ldr) == (set (reg r1)
14416 (zero_extend (mem
14417 (lo_sum (reg r0)
14418 (symbol_ref ("SYM")))))) */
14421 {
14434 }
14435 }
14443 {
14447 rtx cc_reg_1;
14452 && prev
14454 {
14455 /* FIXME: this misses some which is considered simple arthematic
14456 instructions for ThunderX. Simple shifts are missed here. */
14462 }
14463 }
14466 && curr_set
14469 {
14470 /* We're trying to match:
14471 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14472 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14473 (const_int 0))
14474 (label_ref ("SYM"))
14475 (pc)) */
14482 {
14483 /* Fuse ALU operations followed by conditional branch instruction. */
14485 {
14506 }
14507 }
14508 }
14511 }
14513 /* Return true iff the instruction fusion described by OP is enabled. */
14515 bool
14517 {
14519 }
14521 /* If MEM is in the form of [base+offset], extract the two parts
14522 of address and set to BASE and OFFSET, otherwise return false
14523 after clearing BASE and OFFSET. */
14525 bool
14527 {
14528 rtx addr;
14535 {
14539 }
14543 {
14547 }
14553 }
14555 /* Types for scheduling fusion. */
14556 enum sched_fusion_type
14557 {
14559 SCHED_FUSION_LD_SIGN_EXTEND,
14560 SCHED_FUSION_LD_ZERO_EXTEND,
14561 SCHED_FUSION_LD,
14562 SCHED_FUSION_ST,
14563 SCHED_FUSION_NUM
14564 };
14566 /* If INSN is a load or store of address in the form of [base+offset],
14567 extract the two parts and set to BASE and OFFSET. Return scheduling
14568 fusion type this INSN is. */
14570 static enum sched_fusion_type
14572 {
14590 {
14595 }
14597 {
14602 }
14607 {
14610 }
14611 else
14618 }
14620 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14622 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14623 and PRI are only calculated for these instructions. For other instruction,
14624 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14625 type instruction fusion can be added by returning different priorities.
14627 It's important that irrelevant instructions get the largest FUSION_PRI. */
14629 static void
14632 {
14642 {
14646 }
14648 /* Set FUSION_PRI according to fusion type and base register. */
14651 /* Calculate PRI. */
14654 /* INSN with smaller offset goes first. */
14658 else
14663 }
14665 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14666 Adjust priority of sha1h instructions so they are scheduled before
14667 other SHA1 instructions. */
14669 static int
14671 {
14675 {
14680 }
14683 }
14685 /* Given OPERANDS of consecutive load/store, check if we can merge
14686 them into ldp/stp. LOAD is true if they are load instructions.
14687 MODE is the mode of memory operands. */
14689 bool
14691 machine_mode mode)
14692 {
14698 {
14706 }
14707 else
14708 {
14713 }
14715 /* The mems cannot be volatile. */
14719 /* If we have SImode and slow unaligned ldp,
14720 check the alignment to be at least 8 byte. */
14724 && !optimize_size
14728 /* Check if the addresses are in the form of [base+offset]. */
14736 /* Check if the bases are same. */
14743 /* Check if the offsets are consecutive. */
14747 /* Check if the addresses are clobbered by load. */
14749 {
14753 /* In increasing order, the last load can clobber the address. */
14756 }
14760 else
14765 else
14768 /* Check if the registers are of same class. */
14773 }
14775 /* Given OPERANDS of consecutive load/store, check if we can merge
14776 them into ldp/stp by adjusting the offset. LOAD is true if they
14777 are load instructions. MODE is the mode of memory operands.
14779 Given below consecutive stores:
14781 str w1, [xb, 0x100]
14782 str w1, [xb, 0x104]
14783 str w1, [xb, 0x108]
14784 str w1, [xb, 0x10c]
14786 Though the offsets are out of the range supported by stp, we can
14787 still pair them after adjusting the offset, like:
14789 add scratch, xb, 0x100
14790 stp w1, w1, [scratch]
14791 stp w1, w1, [scratch, 0x8]
14793 The peephole patterns detecting this opportunity should guarantee
14794 the scratch register is avaliable. */
14796 bool
14798 machine_mode mode)
14799 {
14806 {
14819 }
14820 else
14821 {
14830 }
14831 /* Skip if memory operand is by itslef valid for ldp/stp. */
14835 /* The mems cannot be volatile. */
14840 /* Check if the addresses are in the form of [base+offset]. */
14854 /* Check if the bases are same. */
14865 /* Check if the offsets are consecutive. */
14874 /* Check if the addresses are clobbered by load. */
14876 {
14882 /* In increasing order, the last load can clobber the address. */
14885 }
14887 /* If we have SImode and slow unaligned ldp,
14888 check the alignment to be at least 8 byte. */
14892 && !optimize_size
14898 else
14903 else
14908 else
14913 else
14916 /* Check if the registers are of same class. */
14921 }
14923 /* Given OPERANDS of consecutive load/store, this function pairs them
14924 into ldp/stp after adjusting the offset. It depends on the fact
14925 that addresses of load/store instructions are in increasing order.
14926 MODE is the mode of memory operands. CODE is the rtl operator
14927 which should be applied to all memory operands, it's SIGN_EXTEND,
14928 ZERO_EXTEND or UNKNOWN. */
14930 bool
14933 {
14939 {
14944 }
14945 else
14946 {
14952 }
14957 /* Adjust offset thus it can fit in ldp/stp instruction. */
14965 /* Further adjust to make sure all offsets are OK. */
14967 {
14970 }
14972 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14977 {
14980 }
14982 /* Create new memory references. */
14986 /* Check if the adjusted address is OK for ldp/stp. */
15005 {
15010 }
15012 {
15017 }
15020 {
15025 }
15026 else
15027 {
15032 }
15034 /* Emit adjusting instruction. */
15036 /* Emit ldp/stp instructions. */
15044 }
15046 /* Return 1 if pseudo register should be created and used to hold
15047 GOT address for PIC code. */
15049 bool
15051 {
15053 }
15055 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15057 static int
15059 {
15061 {
15068 }
15071 }
15074 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15075 return the log2 of that value. Otherwise return -1. */
15077 int
15079 {
15094 }
15096 /* If X is a vector of equal CONST_DOUBLE values and that value is
15097 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15099 int
15101 {
15117 }
15119 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15120 to float.
15122 __fp16 always promotes through this hook.
15123 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15124 through the generic excess precision logic rather than here. */
15126 static tree
15128 {
15134 }
15136 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15138 static bool
15140 optimization_type opt_type)
15141 {
15143 {
15149 }
15150 }
15152 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15153 if MODE is HFmode, and punt to the generic implementation otherwise. */
15155 static bool
15157 {
15161 }
15163 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15164 if MODE is HFmode, and punt to the generic implementation otherwise. */
15166 static bool
15168 {
15172 }
15174 /* Set the value of FLT_EVAL_METHOD.
15175 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15177 0: evaluate all operations and constants, whose semantic type has at
15178 most the range and precision of type float, to the range and
15179 precision of float; evaluate all other operations and constants to
15180 the range and precision of the semantic type;
15182 N, where _FloatN is a supported interchange floating type
15183 evaluate all operations and constants, whose semantic type has at
15184 most the range and precision of _FloatN type, to the range and
15185 precision of the _FloatN type; evaluate all other operations and
15186 constants to the range and precision of the semantic type;
15188 If we have the ARMv8.2-A extensions then we support _Float16 in native
15189 precision, so we should set this to 16. Otherwise, we support the type,
15190 but want to evaluate expressions in float precision, so set this to
15191 0. */
15193 static enum flt_eval_method
15195 {
15197 {
15200 /* We can calculate either in 16-bit range and precision or
15201 32-bit range and precision. Make that decision based on whether
15202 we have native support for the ARMv8.2-A 16-bit floating-point
15203 instructions or not. */
15205 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15211 }
15213 }
15215 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15216 scheduled for speculative execution. Reject the long-running division
15217 and square-root instructions. */
15219 static bool
15221 {
15223 {
15241 }
15242 }
15244 /* Target-specific selftests. */
15246 #if CHECKING_P
15250 /* Selftest for the RTL loader.
15251 Verify that the RTL loader copes with a dump from
15252 print_rtx_function. This is essentially just a test that class
15253 function_reader can handle a real dump, but it also verifies
15254 that lookup_reg_by_dump_name correctly handles hard regs.
15255 The presence of hard reg names in the dump means that the test is
15256 target-specific, hence it is in this file. */
15258 static void
15260 {
15272 /* Verify crtl->return_rtx. */
15276 }
15278 /* Run all target-specific selftests. */
15280 static void
15282 {
15284 }
15290 #undef TARGET_ADDRESS_COST
15291 #define TARGET_ADDRESS_COST aarch64_address_cost
15293 /* This hook will determines whether unnamed bitfields affect the alignment
15294 of the containing structure. The hook returns true if the structure
15295 should inherit the alignment requirements of an unnamed bitfield's
15296 type. */
15297 #undef TARGET_ALIGN_ANON_BITFIELD
15298 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15300 #undef TARGET_ASM_ALIGNED_DI_OP
15303 #undef TARGET_ASM_ALIGNED_HI_OP
15306 #undef TARGET_ASM_ALIGNED_SI_OP
15309 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15310 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15311 hook_bool_const_tree_hwi_hwi_const_tree_true
15313 #undef TARGET_ASM_FILE_START
15314 #define TARGET_ASM_FILE_START aarch64_start_file
15316 #undef TARGET_ASM_OUTPUT_MI_THUNK
15317 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15319 #undef TARGET_ASM_SELECT_RTX_SECTION
15320 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15322 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15323 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15325 #undef TARGET_BUILD_BUILTIN_VA_LIST
15326 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15328 #undef TARGET_CALLEE_COPIES
15329 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15331 #undef TARGET_CAN_ELIMINATE
15332 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15334 #undef TARGET_CAN_INLINE_P
15335 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15337 #undef TARGET_CANNOT_FORCE_CONST_MEM
15338 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15340 #undef TARGET_CASE_VALUES_THRESHOLD
15341 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15343 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15344 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15346 /* Only the least significant bit is used for initialization guard
15347 variables. */
15348 #undef TARGET_CXX_GUARD_MASK_BIT
15349 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15351 #undef TARGET_C_MODE_FOR_SUFFIX
15352 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15354 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15355 #undef TARGET_DEFAULT_TARGET_FLAGS
15356 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15357 #endif
15359 #undef TARGET_CLASS_MAX_NREGS
15360 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15362 #undef TARGET_BUILTIN_DECL
15363 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15365 #undef TARGET_BUILTIN_RECIPROCAL
15366 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15368 #undef TARGET_C_EXCESS_PRECISION
15369 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15371 #undef TARGET_EXPAND_BUILTIN
15372 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15374 #undef TARGET_EXPAND_BUILTIN_VA_START
15375 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15377 #undef TARGET_FOLD_BUILTIN
15378 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15380 #undef TARGET_FUNCTION_ARG
15381 #define TARGET_FUNCTION_ARG aarch64_function_arg
15383 #undef TARGET_FUNCTION_ARG_ADVANCE
15384 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15386 #undef TARGET_FUNCTION_ARG_BOUNDARY
15387 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15389 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15390 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15392 #undef TARGET_FUNCTION_VALUE
15393 #define TARGET_FUNCTION_VALUE aarch64_function_value
15395 #undef TARGET_FUNCTION_VALUE_REGNO_P
15396 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15398 #undef TARGET_FRAME_POINTER_REQUIRED
15399 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15401 #undef TARGET_GIMPLE_FOLD_BUILTIN
15402 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15404 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15405 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15407 #undef TARGET_INIT_BUILTINS
15408 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15410 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15411 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15412 aarch64_ira_change_pseudo_allocno_class
15414 #undef TARGET_LEGITIMATE_ADDRESS_P
15415 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15417 #undef TARGET_LEGITIMATE_CONSTANT_P
15418 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15420 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15421 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15422 aarch64_legitimize_address_displacement
15424 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15425 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15427 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15428 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15429 aarch64_libgcc_floating_mode_supported_p
15431 #undef TARGET_MANGLE_TYPE
15432 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15434 #undef TARGET_MEMORY_MOVE_COST
15435 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15437 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15438 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15440 #undef TARGET_MUST_PASS_IN_STACK
15441 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15443 /* This target hook should return true if accesses to volatile bitfields
15444 should use the narrowest mode possible. It should return false if these
15445 accesses should use the bitfield container type. */
15446 #undef TARGET_NARROW_VOLATILE_BITFIELD
15447 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15449 #undef TARGET_OPTION_OVERRIDE
15450 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15452 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15453 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15454 aarch64_override_options_after_change
15456 #undef TARGET_OPTION_SAVE
15457 #define TARGET_OPTION_SAVE aarch64_option_save
15459 #undef TARGET_OPTION_RESTORE
15460 #define TARGET_OPTION_RESTORE aarch64_option_restore
15462 #undef TARGET_OPTION_PRINT
15463 #define TARGET_OPTION_PRINT aarch64_option_print
15465 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15466 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15468 #undef TARGET_SET_CURRENT_FUNCTION
15469 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15471 #undef TARGET_PASS_BY_REFERENCE
15472 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15474 #undef TARGET_PREFERRED_RELOAD_CLASS
15475 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15477 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15478 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15480 #undef TARGET_PROMOTED_TYPE
15481 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15483 #undef TARGET_SECONDARY_RELOAD
15484 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15486 #undef TARGET_SHIFT_TRUNCATION_MASK
15487 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15489 #undef TARGET_SETUP_INCOMING_VARARGS
15490 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15492 #undef TARGET_STRUCT_VALUE_RTX
15493 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15495 #undef TARGET_REGISTER_MOVE_COST
15496 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15498 #undef TARGET_RETURN_IN_MEMORY
15499 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15501 #undef TARGET_RETURN_IN_MSB
15502 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15504 #undef TARGET_RTX_COSTS
15505 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15507 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15508 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15510 #undef TARGET_SCHED_ISSUE_RATE
15511 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15513 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15514 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15515 aarch64_sched_first_cycle_multipass_dfa_lookahead
15517 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15518 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15519 aarch64_first_cycle_multipass_dfa_lookahead_guard
15521 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15522 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15523 aarch64_get_separate_components
15525 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15526 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15527 aarch64_components_for_bb
15529 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15530 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15531 aarch64_disqualify_components
15533 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15534 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15535 aarch64_emit_prologue_components
15537 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15538 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15539 aarch64_emit_epilogue_components
15541 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15542 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15543 aarch64_set_handled_components
15545 #undef TARGET_TRAMPOLINE_INIT
15546 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15548 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15549 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15551 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15552 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15554 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15555 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15556 aarch64_builtin_support_vector_misalignment
15558 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15559 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15561 #undef TARGET_VECTORIZE_ADD_STMT_COST
15562 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15564 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15565 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15566 aarch64_builtin_vectorization_cost
15568 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15569 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15571 #undef TARGET_VECTORIZE_BUILTINS
15572 #define TARGET_VECTORIZE_BUILTINS
15574 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15575 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15576 aarch64_builtin_vectorized_function
15578 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15579 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15580 aarch64_autovectorize_vector_sizes
15582 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15583 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15584 aarch64_atomic_assign_expand_fenv
15586 /* Section anchor support. */
15588 #undef TARGET_MIN_ANCHOR_OFFSET
15589 #define TARGET_MIN_ANCHOR_OFFSET -256
15591 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15592 byte offset; we can do much more for larger data types, but have no way
15593 to determine the size of the access. We assume accesses are aligned. */
15594 #undef TARGET_MAX_ANCHOR_OFFSET
15595 #define TARGET_MAX_ANCHOR_OFFSET 4095
15597 #undef TARGET_VECTOR_ALIGNMENT
15598 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15600 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15601 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15602 aarch64_simd_vector_alignment_reachable
15604 /* vec_perm support. */
15606 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15607 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15608 aarch64_vectorize_vec_perm_const_ok
15610 #undef TARGET_INIT_LIBFUNCS
15611 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15613 #undef TARGET_FIXED_CONDITION_CODE_REGS
15614 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15616 #undef TARGET_FLAGS_REGNUM
15617 #define TARGET_FLAGS_REGNUM CC_REGNUM
15619 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15620 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15622 #undef TARGET_ASAN_SHADOW_OFFSET
15623 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15625 #undef TARGET_LEGITIMIZE_ADDRESS
15626 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15628 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15629 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15630 aarch64_use_by_pieces_infrastructure_p
15632 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15633 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15635 #undef TARGET_CAN_USE_DOLOOP_P
15636 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15638 #undef TARGET_SCHED_ADJUST_PRIORITY
15639 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15641 #undef TARGET_SCHED_MACRO_FUSION_P
15642 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15644 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15645 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15647 #undef TARGET_SCHED_FUSION_PRIORITY
15648 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15650 #undef TARGET_UNSPEC_MAY_TRAP_P
15651 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15653 #undef TARGET_USE_PSEUDO_PIC_REG
15654 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15656 #undef TARGET_PRINT_OPERAND
15657 #define TARGET_PRINT_OPERAND aarch64_print_operand
15659 #undef TARGET_PRINT_OPERAND_ADDRESS
15660 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15662 #undef TARGET_OPTAB_SUPPORTED_P
15663 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15665 #undef TARGET_OMIT_STRUCT_RETURN_REG
15666 #define TARGET_OMIT_STRUCT_RETURN_REG true
15668 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15669 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15670 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15672 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15673 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15674 aarch64_hard_regno_call_part_clobbered
15676 #if CHECKING_P
15677 #undef TARGET_RUN_TARGET_SELFTESTS
15678 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests