1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "print-tree.h"
30 #include "stringpool.h"
31 #include "stor-layout.h"
36 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
40 #include "insn-attr.h"
52 #include "diagnostic-core.h"
54 #include "dominance.h"
60 #include "cfgcleanup.h"
61 #include "basic-block.h"
64 #include "target-def.h"
66 #include "langhooks.h"
67 #include "insn-codes.h"
69 #include "hash-table.h"
70 #include "tree-ssa-alias.h"
71 #include "internal-fn.h"
72 #include "gimple-fold.h"
74 #include "gimple-expr.h"
82 #include "tree-pass.h"
87 /* Define the specific costs for a given cpu. */
89 struct processor_costs
92 const int m
; /* cost of an M instruction. */
93 const int mghi
; /* cost of an MGHI instruction. */
94 const int mh
; /* cost of an MH instruction. */
95 const int mhi
; /* cost of an MHI instruction. */
96 const int ml
; /* cost of an ML instruction. */
97 const int mr
; /* cost of an MR instruction. */
98 const int ms
; /* cost of an MS instruction. */
99 const int msg
; /* cost of an MSG instruction. */
100 const int msgf
; /* cost of an MSGF instruction. */
101 const int msgfr
; /* cost of an MSGFR instruction. */
102 const int msgr
; /* cost of an MSGR instruction. */
103 const int msr
; /* cost of an MSR instruction. */
104 const int mult_df
; /* cost of multiplication in DFmode. */
107 const int sqxbr
; /* cost of square root in TFmode. */
108 const int sqdbr
; /* cost of square root in DFmode. */
109 const int sqebr
; /* cost of square root in SFmode. */
110 /* multiply and add */
111 const int madbr
; /* cost of multiply and add in DFmode. */
112 const int maebr
; /* cost of multiply and add in SFmode. */
124 const struct processor_costs
*s390_cost
;
127 struct processor_costs z900_cost
=
129 COSTS_N_INSNS (5), /* M */
130 COSTS_N_INSNS (10), /* MGHI */
131 COSTS_N_INSNS (5), /* MH */
132 COSTS_N_INSNS (4), /* MHI */
133 COSTS_N_INSNS (5), /* ML */
134 COSTS_N_INSNS (5), /* MR */
135 COSTS_N_INSNS (4), /* MS */
136 COSTS_N_INSNS (15), /* MSG */
137 COSTS_N_INSNS (7), /* MSGF */
138 COSTS_N_INSNS (7), /* MSGFR */
139 COSTS_N_INSNS (10), /* MSGR */
140 COSTS_N_INSNS (4), /* MSR */
141 COSTS_N_INSNS (7), /* multiplication in DFmode */
142 COSTS_N_INSNS (13), /* MXBR */
143 COSTS_N_INSNS (136), /* SQXBR */
144 COSTS_N_INSNS (44), /* SQDBR */
145 COSTS_N_INSNS (35), /* SQEBR */
146 COSTS_N_INSNS (18), /* MADBR */
147 COSTS_N_INSNS (13), /* MAEBR */
148 COSTS_N_INSNS (134), /* DXBR */
149 COSTS_N_INSNS (30), /* DDBR */
150 COSTS_N_INSNS (27), /* DEBR */
151 COSTS_N_INSNS (220), /* DLGR */
152 COSTS_N_INSNS (34), /* DLR */
153 COSTS_N_INSNS (34), /* DR */
154 COSTS_N_INSNS (32), /* DSGFR */
155 COSTS_N_INSNS (32), /* DSGR */
159 struct processor_costs z990_cost
=
161 COSTS_N_INSNS (4), /* M */
162 COSTS_N_INSNS (2), /* MGHI */
163 COSTS_N_INSNS (2), /* MH */
164 COSTS_N_INSNS (2), /* MHI */
165 COSTS_N_INSNS (4), /* ML */
166 COSTS_N_INSNS (4), /* MR */
167 COSTS_N_INSNS (5), /* MS */
168 COSTS_N_INSNS (6), /* MSG */
169 COSTS_N_INSNS (4), /* MSGF */
170 COSTS_N_INSNS (4), /* MSGFR */
171 COSTS_N_INSNS (4), /* MSGR */
172 COSTS_N_INSNS (4), /* MSR */
173 COSTS_N_INSNS (1), /* multiplication in DFmode */
174 COSTS_N_INSNS (28), /* MXBR */
175 COSTS_N_INSNS (130), /* SQXBR */
176 COSTS_N_INSNS (66), /* SQDBR */
177 COSTS_N_INSNS (38), /* SQEBR */
178 COSTS_N_INSNS (1), /* MADBR */
179 COSTS_N_INSNS (1), /* MAEBR */
180 COSTS_N_INSNS (60), /* DXBR */
181 COSTS_N_INSNS (40), /* DDBR */
182 COSTS_N_INSNS (26), /* DEBR */
183 COSTS_N_INSNS (176), /* DLGR */
184 COSTS_N_INSNS (31), /* DLR */
185 COSTS_N_INSNS (31), /* DR */
186 COSTS_N_INSNS (31), /* DSGFR */
187 COSTS_N_INSNS (31), /* DSGR */
191 struct processor_costs z9_109_cost
=
193 COSTS_N_INSNS (4), /* M */
194 COSTS_N_INSNS (2), /* MGHI */
195 COSTS_N_INSNS (2), /* MH */
196 COSTS_N_INSNS (2), /* MHI */
197 COSTS_N_INSNS (4), /* ML */
198 COSTS_N_INSNS (4), /* MR */
199 COSTS_N_INSNS (5), /* MS */
200 COSTS_N_INSNS (6), /* MSG */
201 COSTS_N_INSNS (4), /* MSGF */
202 COSTS_N_INSNS (4), /* MSGFR */
203 COSTS_N_INSNS (4), /* MSGR */
204 COSTS_N_INSNS (4), /* MSR */
205 COSTS_N_INSNS (1), /* multiplication in DFmode */
206 COSTS_N_INSNS (28), /* MXBR */
207 COSTS_N_INSNS (130), /* SQXBR */
208 COSTS_N_INSNS (66), /* SQDBR */
209 COSTS_N_INSNS (38), /* SQEBR */
210 COSTS_N_INSNS (1), /* MADBR */
211 COSTS_N_INSNS (1), /* MAEBR */
212 COSTS_N_INSNS (60), /* DXBR */
213 COSTS_N_INSNS (40), /* DDBR */
214 COSTS_N_INSNS (26), /* DEBR */
215 COSTS_N_INSNS (30), /* DLGR */
216 COSTS_N_INSNS (23), /* DLR */
217 COSTS_N_INSNS (23), /* DR */
218 COSTS_N_INSNS (24), /* DSGFR */
219 COSTS_N_INSNS (24), /* DSGR */
223 struct processor_costs z10_cost
=
225 COSTS_N_INSNS (10), /* M */
226 COSTS_N_INSNS (10), /* MGHI */
227 COSTS_N_INSNS (10), /* MH */
228 COSTS_N_INSNS (10), /* MHI */
229 COSTS_N_INSNS (10), /* ML */
230 COSTS_N_INSNS (10), /* MR */
231 COSTS_N_INSNS (10), /* MS */
232 COSTS_N_INSNS (10), /* MSG */
233 COSTS_N_INSNS (10), /* MSGF */
234 COSTS_N_INSNS (10), /* MSGFR */
235 COSTS_N_INSNS (10), /* MSGR */
236 COSTS_N_INSNS (10), /* MSR */
237 COSTS_N_INSNS (1) , /* multiplication in DFmode */
238 COSTS_N_INSNS (50), /* MXBR */
239 COSTS_N_INSNS (120), /* SQXBR */
240 COSTS_N_INSNS (52), /* SQDBR */
241 COSTS_N_INSNS (38), /* SQEBR */
242 COSTS_N_INSNS (1), /* MADBR */
243 COSTS_N_INSNS (1), /* MAEBR */
244 COSTS_N_INSNS (111), /* DXBR */
245 COSTS_N_INSNS (39), /* DDBR */
246 COSTS_N_INSNS (32), /* DEBR */
247 COSTS_N_INSNS (160), /* DLGR */
248 COSTS_N_INSNS (71), /* DLR */
249 COSTS_N_INSNS (71), /* DR */
250 COSTS_N_INSNS (71), /* DSGFR */
251 COSTS_N_INSNS (71), /* DSGR */
255 struct processor_costs z196_cost
=
257 COSTS_N_INSNS (7), /* M */
258 COSTS_N_INSNS (5), /* MGHI */
259 COSTS_N_INSNS (5), /* MH */
260 COSTS_N_INSNS (5), /* MHI */
261 COSTS_N_INSNS (7), /* ML */
262 COSTS_N_INSNS (7), /* MR */
263 COSTS_N_INSNS (6), /* MS */
264 COSTS_N_INSNS (8), /* MSG */
265 COSTS_N_INSNS (6), /* MSGF */
266 COSTS_N_INSNS (6), /* MSGFR */
267 COSTS_N_INSNS (8), /* MSGR */
268 COSTS_N_INSNS (6), /* MSR */
269 COSTS_N_INSNS (1) , /* multiplication in DFmode */
270 COSTS_N_INSNS (40), /* MXBR B+40 */
271 COSTS_N_INSNS (100), /* SQXBR B+100 */
272 COSTS_N_INSNS (42), /* SQDBR B+42 */
273 COSTS_N_INSNS (28), /* SQEBR B+28 */
274 COSTS_N_INSNS (1), /* MADBR B */
275 COSTS_N_INSNS (1), /* MAEBR B */
276 COSTS_N_INSNS (101), /* DXBR B+101 */
277 COSTS_N_INSNS (29), /* DDBR */
278 COSTS_N_INSNS (22), /* DEBR */
279 COSTS_N_INSNS (160), /* DLGR cracked */
280 COSTS_N_INSNS (160), /* DLR cracked */
281 COSTS_N_INSNS (160), /* DR expanded */
282 COSTS_N_INSNS (160), /* DSGFR cracked */
283 COSTS_N_INSNS (160), /* DSGR cracked */
287 struct processor_costs zEC12_cost
=
289 COSTS_N_INSNS (7), /* M */
290 COSTS_N_INSNS (5), /* MGHI */
291 COSTS_N_INSNS (5), /* MH */
292 COSTS_N_INSNS (5), /* MHI */
293 COSTS_N_INSNS (7), /* ML */
294 COSTS_N_INSNS (7), /* MR */
295 COSTS_N_INSNS (6), /* MS */
296 COSTS_N_INSNS (8), /* MSG */
297 COSTS_N_INSNS (6), /* MSGF */
298 COSTS_N_INSNS (6), /* MSGFR */
299 COSTS_N_INSNS (8), /* MSGR */
300 COSTS_N_INSNS (6), /* MSR */
301 COSTS_N_INSNS (1) , /* multiplication in DFmode */
302 COSTS_N_INSNS (40), /* MXBR B+40 */
303 COSTS_N_INSNS (100), /* SQXBR B+100 */
304 COSTS_N_INSNS (42), /* SQDBR B+42 */
305 COSTS_N_INSNS (28), /* SQEBR B+28 */
306 COSTS_N_INSNS (1), /* MADBR B */
307 COSTS_N_INSNS (1), /* MAEBR B */
308 COSTS_N_INSNS (131), /* DXBR B+131 */
309 COSTS_N_INSNS (29), /* DDBR */
310 COSTS_N_INSNS (22), /* DEBR */
311 COSTS_N_INSNS (160), /* DLGR cracked */
312 COSTS_N_INSNS (160), /* DLR cracked */
313 COSTS_N_INSNS (160), /* DR expanded */
314 COSTS_N_INSNS (160), /* DSGFR cracked */
315 COSTS_N_INSNS (160), /* DSGR cracked */
318 extern int reload_completed
;
320 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
321 static rtx_insn
*last_scheduled_insn
;
323 /* Structure used to hold the components of a S/390 memory
324 address. A legitimate address on S/390 is of the general
326 base + index + displacement
327 where any of the components is optional.
329 base and index are registers of the class ADDR_REGS,
330 displacement is an unsigned 12-bit immediate constant. */
341 /* The following structure is embedded in the machine
342 specific part of struct function. */
344 struct GTY (()) s390_frame_layout
346 /* Offset within stack frame. */
347 HOST_WIDE_INT gprs_offset
;
348 HOST_WIDE_INT f0_offset
;
349 HOST_WIDE_INT f4_offset
;
350 HOST_WIDE_INT f8_offset
;
351 HOST_WIDE_INT backchain_offset
;
353 /* Number of first and last gpr where slots in the register
354 save area are reserved for. */
355 int first_save_gpr_slot
;
356 int last_save_gpr_slot
;
358 /* Location (FP register number) where GPRs (r0-r15) should
360 0 - does not need to be saved at all
362 signed char gpr_save_slots
[16];
364 /* Number of first and last gpr to be saved, restored. */
366 int first_restore_gpr
;
368 int last_restore_gpr
;
370 /* Bits standing for floating point registers. Set, if the
371 respective register has to be saved. Starting with reg 16 (f0)
372 at the rightmost bit.
373 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
374 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
375 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
376 unsigned int fpr_bitmap
;
378 /* Number of floating point registers f8-f15 which must be saved. */
381 /* Set if return address needs to be saved.
382 This flag is set by s390_return_addr_rtx if it could not use
383 the initial value of r14 and therefore depends on r14 saved
385 bool save_return_addr_p
;
387 /* Size of stack frame. */
388 HOST_WIDE_INT frame_size
;
391 /* Define the structure for the machine field in struct function. */
393 struct GTY(()) machine_function
395 struct s390_frame_layout frame_layout
;
397 /* Literal pool base register. */
400 /* True if we may need to perform branch splitting. */
401 bool split_branches_pending_p
;
403 bool has_landing_pad_p
;
405 /* True if the current function may contain a tbegin clobbering
410 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
412 #define cfun_frame_layout (cfun->machine->frame_layout)
413 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
414 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
415 ? cfun_frame_layout.fpr_bitmap & 0x0f \
416 : cfun_frame_layout.fpr_bitmap & 0x03))
417 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
418 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
419 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
420 (1 << (REGNO - FPR0_REGNUM)))
421 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
422 (1 << (REGNO - FPR0_REGNUM))))
423 #define cfun_gpr_save_slot(REGNO) \
424 cfun->machine->frame_layout.gpr_save_slots[REGNO]
426 /* Number of GPRs and FPRs used for argument passing. */
427 #define GP_ARG_NUM_REG 5
428 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
430 /* A couple of shortcuts. */
431 #define CONST_OK_FOR_J(x) \
432 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
433 #define CONST_OK_FOR_K(x) \
434 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
435 #define CONST_OK_FOR_Os(x) \
436 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
437 #define CONST_OK_FOR_Op(x) \
438 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
439 #define CONST_OK_FOR_On(x) \
440 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
442 #define REGNO_PAIR_OK(REGNO, MODE) \
443 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
445 /* That's the read ahead of the dynamic branch prediction unit in
446 bytes on a z10 (or higher) CPU. */
447 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
449 static const int s390_hotpatch_trampoline_halfwords_default
= 12;
450 static const int s390_hotpatch_trampoline_halfwords_max
= 1000000;
451 static int s390_hotpatch_trampoline_halfwords
= -1;
453 /* Return the argument of the given hotpatch attribute or the default value if
454 no argument is present. */
457 get_hotpatch_attribute (tree hotpatch_attr
)
461 args
= TREE_VALUE (hotpatch_attr
);
464 TREE_INT_CST_LOW (TREE_VALUE (args
)):
465 s390_hotpatch_trampoline_halfwords_default
;
468 /* Check whether the hotpatch attribute is applied to a function and, if it has
469 an argument, the argument is valid. */
472 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
473 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
475 if (TREE_CODE (*node
) != FUNCTION_DECL
)
477 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
479 *no_add_attrs
= true;
483 tree expr
= TREE_VALUE (args
);
485 if (TREE_CODE (expr
) != INTEGER_CST
486 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
487 || wi::gtu_p (expr
, s390_hotpatch_trampoline_halfwords_max
))
489 error ("requested %qE attribute is not a non-negative integer"
490 " constant or too large (max. %d)", name
,
491 s390_hotpatch_trampoline_halfwords_max
);
492 *no_add_attrs
= true;
499 static const struct attribute_spec s390_attribute_table
[] = {
500 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute
, false
503 { NULL
, 0, 0, false, false, false, NULL
, false }
506 /* Return the alignment for LABEL. We default to the -falign-labels
507 value except for the literal pool base label. */
509 s390_label_align (rtx label
)
511 rtx_insn
*prev_insn
= prev_active_insn (label
);
514 if (prev_insn
== NULL_RTX
)
517 set
= single_set (prev_insn
);
524 /* Don't align literal pool base labels. */
525 if (GET_CODE (src
) == UNSPEC
526 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
530 return align_labels_log
;
534 s390_libgcc_cmp_return_mode (void)
536 return TARGET_64BIT
? DImode
: SImode
;
540 s390_libgcc_shift_count_mode (void)
542 return TARGET_64BIT
? DImode
: SImode
;
546 s390_unwind_word_mode (void)
548 return TARGET_64BIT
? DImode
: SImode
;
551 /* Return true if the back end supports mode MODE. */
553 s390_scalar_mode_supported_p (machine_mode mode
)
555 /* In contrast to the default implementation reject TImode constants on 31bit
556 TARGET_ZARCH for ABI compliance. */
557 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
560 if (DECIMAL_FLOAT_MODE_P (mode
))
561 return default_decimal_float_supported_p ();
563 return default_scalar_mode_supported_p (mode
);
566 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
569 s390_set_has_landing_pad_p (bool value
)
571 cfun
->machine
->has_landing_pad_p
= value
;
574 /* If two condition code modes are compatible, return a condition code
575 mode which is compatible with both. Otherwise, return
579 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
587 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
588 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
609 /* Return true if SET either doesn't set the CC register, or else
610 the source and destination have matching CC modes and that
611 CC mode is at least as constrained as REQ_MODE. */
614 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
616 machine_mode set_mode
;
618 gcc_assert (GET_CODE (set
) == SET
);
620 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
623 set_mode
= GET_MODE (SET_DEST (set
));
637 if (req_mode
!= set_mode
)
642 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
643 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
649 if (req_mode
!= CCAmode
)
657 return (GET_MODE (SET_SRC (set
)) == set_mode
);
660 /* Return true if every SET in INSN that sets the CC register
661 has source and destination with matching CC modes and that
662 CC mode is at least as constrained as REQ_MODE.
663 If REQ_MODE is VOIDmode, always return false. */
666 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
670 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
671 if (req_mode
== VOIDmode
)
674 if (GET_CODE (PATTERN (insn
)) == SET
)
675 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
677 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
678 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
680 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
681 if (GET_CODE (set
) == SET
)
682 if (!s390_match_ccmode_set (set
, req_mode
))
689 /* If a test-under-mask instruction can be used to implement
690 (compare (and ... OP1) OP2), return the CC mode required
691 to do that. Otherwise, return VOIDmode.
692 MIXED is true if the instruction can distinguish between
693 CC1 and CC2 for mixed selected bits (TMxx), it is false
694 if the instruction cannot (TM). */
697 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
701 /* ??? Fixme: should work on CONST_DOUBLE as well. */
702 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
705 /* Selected bits all zero: CC0.
706 e.g.: int a; if ((a & (16 + 128)) == 0) */
707 if (INTVAL (op2
) == 0)
710 /* Selected bits all one: CC3.
711 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
712 if (INTVAL (op2
) == INTVAL (op1
))
715 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
717 if ((a & (16 + 128)) == 16) -> CCT1
718 if ((a & (16 + 128)) == 128) -> CCT2 */
721 bit1
= exact_log2 (INTVAL (op2
));
722 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
723 if (bit0
!= -1 && bit1
!= -1)
724 return bit0
> bit1
? CCT1mode
: CCT2mode
;
730 /* Given a comparison code OP (EQ, NE, etc.) and the operands
731 OP0 and OP1 of a COMPARE, return the mode to be used for the
735 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
741 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
742 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
744 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
745 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
747 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
748 || GET_CODE (op1
) == NEG
)
749 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
752 if (GET_CODE (op0
) == AND
)
754 /* Check whether we can potentially do it via TM. */
756 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
757 if (ccmode
!= VOIDmode
)
759 /* Relax CCTmode to CCZmode to allow fall-back to AND
760 if that turns out to be beneficial. */
761 return ccmode
== CCTmode
? CCZmode
: ccmode
;
765 if (register_operand (op0
, HImode
)
766 && GET_CODE (op1
) == CONST_INT
767 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
769 if (register_operand (op0
, QImode
)
770 && GET_CODE (op1
) == CONST_INT
771 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
780 /* The only overflow condition of NEG and ABS happens when
781 -INT_MAX is used as parameter, which stays negative. So
782 we have an overflow from a positive value to a negative.
783 Using CCAP mode the resulting cc can be used for comparisons. */
784 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
785 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
788 /* If constants are involved in an add instruction it is possible to use
789 the resulting cc for comparisons with zero. Knowing the sign of the
790 constant the overflow behavior gets predictable. e.g.:
791 int a, b; if ((b = a + c) > 0)
792 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
793 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
794 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
795 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
796 /* Avoid INT32_MIN on 32 bit. */
797 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
799 if (INTVAL (XEXP((op0
), 1)) < 0)
813 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
814 && GET_CODE (op1
) != CONST_INT
)
820 if (GET_CODE (op0
) == PLUS
821 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
824 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
825 && GET_CODE (op1
) != CONST_INT
)
831 if (GET_CODE (op0
) == MINUS
832 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
835 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
836 && GET_CODE (op1
) != CONST_INT
)
845 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
846 that we can implement more efficiently. */
849 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
850 bool op0_preserve_value
)
852 if (op0_preserve_value
)
855 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
856 if ((*code
== EQ
|| *code
== NE
)
857 && *op1
== const0_rtx
858 && GET_CODE (*op0
) == ZERO_EXTRACT
859 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
860 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
861 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
863 rtx inner
= XEXP (*op0
, 0);
864 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
865 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
866 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
868 if (len
> 0 && len
< modesize
869 && pos
>= 0 && pos
+ len
<= modesize
870 && modesize
<= HOST_BITS_PER_WIDE_INT
)
872 unsigned HOST_WIDE_INT block
;
873 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
874 block
<<= modesize
- pos
- len
;
876 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
877 gen_int_mode (block
, GET_MODE (inner
)));
881 /* Narrow AND of memory against immediate to enable TM. */
882 if ((*code
== EQ
|| *code
== NE
)
883 && *op1
== const0_rtx
884 && GET_CODE (*op0
) == AND
885 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
886 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
888 rtx inner
= XEXP (*op0
, 0);
889 rtx mask
= XEXP (*op0
, 1);
891 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
892 if (GET_CODE (inner
) == SUBREG
893 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
894 && (GET_MODE_SIZE (GET_MODE (inner
))
895 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
897 & GET_MODE_MASK (GET_MODE (inner
))
898 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
900 inner
= SUBREG_REG (inner
);
902 /* Do not change volatile MEMs. */
903 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
905 int part
= s390_single_part (XEXP (*op0
, 1),
906 GET_MODE (inner
), QImode
, 0);
909 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
910 inner
= adjust_address_nv (inner
, QImode
, part
);
911 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
916 /* Narrow comparisons against 0xffff to HImode if possible. */
917 if ((*code
== EQ
|| *code
== NE
)
918 && GET_CODE (*op1
) == CONST_INT
919 && INTVAL (*op1
) == 0xffff
920 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
921 && (nonzero_bits (*op0
, GET_MODE (*op0
))
922 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
924 *op0
= gen_lowpart (HImode
, *op0
);
928 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
929 if (GET_CODE (*op0
) == UNSPEC
930 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
931 && XVECLEN (*op0
, 0) == 1
932 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
933 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
934 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
935 && *op1
== const0_rtx
)
937 enum rtx_code new_code
= UNKNOWN
;
940 case EQ
: new_code
= EQ
; break;
941 case NE
: new_code
= NE
; break;
942 case LT
: new_code
= GTU
; break;
943 case GT
: new_code
= LTU
; break;
944 case LE
: new_code
= GEU
; break;
945 case GE
: new_code
= LEU
; break;
949 if (new_code
!= UNKNOWN
)
951 *op0
= XVECEXP (*op0
, 0, 0);
956 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
957 if (GET_CODE (*op0
) == UNSPEC
958 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
959 && XVECLEN (*op0
, 0) == 1
960 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
961 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
962 && CONST_INT_P (*op1
))
964 enum rtx_code new_code
= UNKNOWN
;
965 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
971 case EQ
: new_code
= EQ
; break;
972 case NE
: new_code
= NE
; break;
979 if (new_code
!= UNKNOWN
)
981 /* For CCRAWmode put the required cc mask into the second
983 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
984 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
985 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
986 *op0
= XVECEXP (*op0
, 0, 0);
991 /* Simplify cascaded EQ, NE with const0_rtx. */
992 if ((*code
== NE
|| *code
== EQ
)
993 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
994 && GET_MODE (*op0
) == SImode
995 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
996 && REG_P (XEXP (*op0
, 0))
997 && XEXP (*op0
, 1) == const0_rtx
998 && *op1
== const0_rtx
)
1000 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1001 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1005 *op0
= XEXP (*op0
, 0);
1008 /* Prefer register over memory as first operand. */
1009 if (MEM_P (*op0
) && REG_P (*op1
))
1011 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1012 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1016 /* Emit a compare instruction suitable to implement the comparison
1017 OP0 CODE OP1. Return the correct condition RTL to be placed in
1018 the IF_THEN_ELSE of the conditional branch testing the result. */
1021 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1023 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1026 /* Do not output a redundant compare instruction if a compare_and_swap
1027 pattern already computed the result and the machine modes are compatible. */
1028 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1030 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1036 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1037 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1040 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1043 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1045 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1046 conditional branch testing the result. */
1049 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1050 rtx cmp
, rtx new_rtx
)
1052 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
, new_rtx
));
1053 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
),
1057 /* Emit a jump instruction to TARGET and return it. If COND is
1058 NULL_RTX, emit an unconditional jump, else a conditional jump under
1062 s390_emit_jump (rtx target
, rtx cond
)
1066 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1068 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1070 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
1071 return emit_jump_insn (insn
);
1074 /* Return branch condition mask to implement a branch
1075 specified by CODE. Return -1 for invalid comparisons. */
1078 s390_branch_condition_mask (rtx code
)
1080 const int CC0
= 1 << 3;
1081 const int CC1
= 1 << 2;
1082 const int CC2
= 1 << 1;
1083 const int CC3
= 1 << 0;
1085 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1086 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1087 gcc_assert (XEXP (code
, 1) == const0_rtx
1088 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1089 && CONST_INT_P (XEXP (code
, 1))));
1092 switch (GET_MODE (XEXP (code
, 0)))
1096 switch (GET_CODE (code
))
1098 case EQ
: return CC0
;
1099 case NE
: return CC1
| CC2
| CC3
;
1105 switch (GET_CODE (code
))
1107 case EQ
: return CC1
;
1108 case NE
: return CC0
| CC2
| CC3
;
1114 switch (GET_CODE (code
))
1116 case EQ
: return CC2
;
1117 case NE
: return CC0
| CC1
| CC3
;
1123 switch (GET_CODE (code
))
1125 case EQ
: return CC3
;
1126 case NE
: return CC0
| CC1
| CC2
;
1132 switch (GET_CODE (code
))
1134 case EQ
: return CC0
| CC2
;
1135 case NE
: return CC1
| CC3
;
1141 switch (GET_CODE (code
))
1143 case LTU
: return CC2
| CC3
; /* carry */
1144 case GEU
: return CC0
| CC1
; /* no carry */
1150 switch (GET_CODE (code
))
1152 case GTU
: return CC0
| CC1
; /* borrow */
1153 case LEU
: return CC2
| CC3
; /* no borrow */
1159 switch (GET_CODE (code
))
1161 case EQ
: return CC0
| CC2
;
1162 case NE
: return CC1
| CC3
;
1163 case LTU
: return CC1
;
1164 case GTU
: return CC3
;
1165 case LEU
: return CC1
| CC2
;
1166 case GEU
: return CC2
| CC3
;
1171 switch (GET_CODE (code
))
1173 case EQ
: return CC0
;
1174 case NE
: return CC1
| CC2
| CC3
;
1175 case LTU
: return CC1
;
1176 case GTU
: return CC2
;
1177 case LEU
: return CC0
| CC1
;
1178 case GEU
: return CC0
| CC2
;
1184 switch (GET_CODE (code
))
1186 case EQ
: return CC0
;
1187 case NE
: return CC2
| CC1
| CC3
;
1188 case LTU
: return CC2
;
1189 case GTU
: return CC1
;
1190 case LEU
: return CC0
| CC2
;
1191 case GEU
: return CC0
| CC1
;
1197 switch (GET_CODE (code
))
1199 case EQ
: return CC0
;
1200 case NE
: return CC1
| CC2
| CC3
;
1201 case LT
: return CC1
| CC3
;
1202 case GT
: return CC2
;
1203 case LE
: return CC0
| CC1
| CC3
;
1204 case GE
: return CC0
| CC2
;
1210 switch (GET_CODE (code
))
1212 case EQ
: return CC0
;
1213 case NE
: return CC1
| CC2
| CC3
;
1214 case LT
: return CC1
;
1215 case GT
: return CC2
| CC3
;
1216 case LE
: return CC0
| CC1
;
1217 case GE
: return CC0
| CC2
| CC3
;
1223 switch (GET_CODE (code
))
1225 case EQ
: return CC0
;
1226 case NE
: return CC1
| CC2
| CC3
;
1227 case LT
: return CC1
;
1228 case GT
: return CC2
;
1229 case LE
: return CC0
| CC1
;
1230 case GE
: return CC0
| CC2
;
1231 case UNORDERED
: return CC3
;
1232 case ORDERED
: return CC0
| CC1
| CC2
;
1233 case UNEQ
: return CC0
| CC3
;
1234 case UNLT
: return CC1
| CC3
;
1235 case UNGT
: return CC2
| CC3
;
1236 case UNLE
: return CC0
| CC1
| CC3
;
1237 case UNGE
: return CC0
| CC2
| CC3
;
1238 case LTGT
: return CC1
| CC2
;
1244 switch (GET_CODE (code
))
1246 case EQ
: return CC0
;
1247 case NE
: return CC2
| CC1
| CC3
;
1248 case LT
: return CC2
;
1249 case GT
: return CC1
;
1250 case LE
: return CC0
| CC2
;
1251 case GE
: return CC0
| CC1
;
1252 case UNORDERED
: return CC3
;
1253 case ORDERED
: return CC0
| CC2
| CC1
;
1254 case UNEQ
: return CC0
| CC3
;
1255 case UNLT
: return CC2
| CC3
;
1256 case UNGT
: return CC1
| CC3
;
1257 case UNLE
: return CC0
| CC2
| CC3
;
1258 case UNGE
: return CC0
| CC1
| CC3
;
1259 case LTGT
: return CC2
| CC1
;
1265 switch (GET_CODE (code
))
1268 return INTVAL (XEXP (code
, 1));
1270 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
1281 /* Return branch condition mask to implement a compare and branch
1282 specified by CODE. Return -1 for invalid comparisons. */
1285 s390_compare_and_branch_condition_mask (rtx code
)
1287 const int CC0
= 1 << 3;
1288 const int CC1
= 1 << 2;
1289 const int CC2
= 1 << 1;
1291 switch (GET_CODE (code
))
1315 /* If INV is false, return assembler mnemonic string to implement
1316 a branch specified by CODE. If INV is true, return mnemonic
1317 for the corresponding inverted branch. */
1320 s390_branch_condition_mnemonic (rtx code
, int inv
)
1324 static const char *const mnemonic
[16] =
1326 NULL
, "o", "h", "nle",
1327 "l", "nhe", "lh", "ne",
1328 "e", "nlh", "he", "nl",
1329 "le", "nh", "no", NULL
1332 if (GET_CODE (XEXP (code
, 0)) == REG
1333 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1334 && (XEXP (code
, 1) == const0_rtx
1335 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1336 && CONST_INT_P (XEXP (code
, 1)))))
1337 mask
= s390_branch_condition_mask (code
);
1339 mask
= s390_compare_and_branch_condition_mask (code
);
1341 gcc_assert (mask
>= 0);
1346 gcc_assert (mask
>= 1 && mask
<= 14);
1348 return mnemonic
[mask
];
1351 /* Return the part of op which has a value different from def.
1352 The size of the part is determined by mode.
1353 Use this function only if you already know that op really
1354 contains such a part. */
1356 unsigned HOST_WIDE_INT
1357 s390_extract_part (rtx op
, machine_mode mode
, int def
)
1359 unsigned HOST_WIDE_INT value
= 0;
1360 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1361 int part_bits
= GET_MODE_BITSIZE (mode
);
1362 unsigned HOST_WIDE_INT part_mask
1363 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1366 for (i
= 0; i
< max_parts
; i
++)
1369 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1371 value
>>= part_bits
;
1373 if ((value
& part_mask
) != (def
& part_mask
))
1374 return value
& part_mask
;
1380 /* If OP is an integer constant of mode MODE with exactly one
1381 part of mode PART_MODE unequal to DEF, return the number of that
1382 part. Otherwise, return -1. */
1385 s390_single_part (rtx op
,
1387 machine_mode part_mode
,
1390 unsigned HOST_WIDE_INT value
= 0;
1391 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1392 unsigned HOST_WIDE_INT part_mask
1393 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1396 if (GET_CODE (op
) != CONST_INT
)
1399 for (i
= 0; i
< n_parts
; i
++)
1402 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1404 value
>>= GET_MODE_BITSIZE (part_mode
);
1406 if ((value
& part_mask
) != (def
& part_mask
))
1414 return part
== -1 ? -1 : n_parts
- 1 - part
;
1417 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1418 bits and no other bits are set in IN. POS and LENGTH can be used
1419 to obtain the start position and the length of the bitfield.
1421 POS gives the position of the first bit of the bitfield counting
1422 from the lowest order bit starting with zero. In order to use this
1423 value for S/390 instructions this has to be converted to "bits big
1427 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1428 int *pos
, int *length
)
1433 unsigned HOST_WIDE_INT mask
= 1ULL;
1434 bool contiguous
= false;
1436 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1460 /* Calculate a mask for all bits beyond the contiguous bits. */
1461 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1466 if (tmp_length
+ tmp_pos
- 1 > size
)
1470 *length
= tmp_length
;
1478 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1479 equivalent to a shift followed by the AND. In particular, CONTIG
1480 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1481 for ROTL indicate a rotate to the right. */
1484 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
1489 ok
= s390_contiguous_bitmask_p (contig
, bitsize
, &pos
, &len
);
1492 return ((rotl
>= 0 && rotl
<= pos
)
1493 || (rotl
< 0 && -rotl
<= bitsize
- len
- pos
));
1496 /* Check whether we can (and want to) split a double-word
1497 move in mode MODE from SRC to DST into two single-word
1498 moves, moving the subword FIRST_SUBWORD first. */
1501 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
1503 /* Floating point registers cannot be split. */
1504 if (FP_REG_P (src
) || FP_REG_P (dst
))
1507 /* We don't need to split if operands are directly accessible. */
1508 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1511 /* Non-offsettable memory references cannot be split. */
1512 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1513 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1516 /* Moving the first subword must not clobber a register
1517 needed to move the second subword. */
1518 if (register_operand (dst
, mode
))
1520 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1521 if (reg_overlap_mentioned_p (subreg
, src
))
1528 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1529 and [MEM2, MEM2 + SIZE] do overlap and false
1533 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1535 rtx addr1
, addr2
, addr_delta
;
1536 HOST_WIDE_INT delta
;
1538 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1544 addr1
= XEXP (mem1
, 0);
1545 addr2
= XEXP (mem2
, 0);
1547 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1549 /* This overlapping check is used by peepholes merging memory block operations.
1550 Overlapping operations would otherwise be recognized by the S/390 hardware
1551 and would fall back to a slower implementation. Allowing overlapping
1552 operations would lead to slow code but not to wrong code. Therefore we are
1553 somewhat optimistic if we cannot prove that the memory blocks are
1555 That's why we return false here although this may accept operations on
1556 overlapping memory areas. */
1557 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1560 delta
= INTVAL (addr_delta
);
1563 || (delta
> 0 && delta
< size
)
1564 || (delta
< 0 && -delta
< size
))
1570 /* Check whether the address of memory reference MEM2 equals exactly
1571 the address of memory reference MEM1 plus DELTA. Return true if
1572 we can prove this to be the case, false otherwise. */
1575 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1577 rtx addr1
, addr2
, addr_delta
;
1579 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1582 addr1
= XEXP (mem1
, 0);
1583 addr2
= XEXP (mem2
, 0);
1585 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1586 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1592 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1595 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
1598 machine_mode wmode
= mode
;
1599 rtx dst
= operands
[0];
1600 rtx src1
= operands
[1];
1601 rtx src2
= operands
[2];
1604 /* If we cannot handle the operation directly, use a temp register. */
1605 if (!s390_logical_operator_ok_p (operands
))
1606 dst
= gen_reg_rtx (mode
);
1608 /* QImode and HImode patterns make sense only if we have a destination
1609 in memory. Otherwise perform the operation in SImode. */
1610 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1613 /* Widen operands if required. */
1616 if (GET_CODE (dst
) == SUBREG
1617 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1619 else if (REG_P (dst
))
1620 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1622 dst
= gen_reg_rtx (wmode
);
1624 if (GET_CODE (src1
) == SUBREG
1625 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1627 else if (GET_MODE (src1
) != VOIDmode
)
1628 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1630 if (GET_CODE (src2
) == SUBREG
1631 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1633 else if (GET_MODE (src2
) != VOIDmode
)
1634 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1637 /* Emit the instruction. */
1638 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1639 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1640 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1642 /* Fix up the destination if needed. */
1643 if (dst
!= operands
[0])
1644 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1647 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1650 s390_logical_operator_ok_p (rtx
*operands
)
1652 /* If the destination operand is in memory, it needs to coincide
1653 with one of the source operands. After reload, it has to be
1654 the first source operand. */
1655 if (GET_CODE (operands
[0]) == MEM
)
1656 return rtx_equal_p (operands
[0], operands
[1])
1657 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1662 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1663 operand IMMOP to switch from SS to SI type instructions. */
1666 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1668 int def
= code
== AND
? -1 : 0;
1672 gcc_assert (GET_CODE (*memop
) == MEM
);
1673 gcc_assert (!MEM_VOLATILE_P (*memop
));
1675 mask
= s390_extract_part (*immop
, QImode
, def
);
1676 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1677 gcc_assert (part
>= 0);
1679 *memop
= adjust_address (*memop
, QImode
, part
);
1680 *immop
= gen_int_mode (mask
, QImode
);
1684 /* How to allocate a 'struct machine_function'. */
1686 static struct machine_function
*
1687 s390_init_machine_status (void)
1689 return ggc_cleared_alloc
<machine_function
> ();
1692 /* Map for smallest class containing reg regno. */
1694 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1695 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1696 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1697 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1698 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1699 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1700 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1701 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1702 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1703 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1704 ACCESS_REGS
, ACCESS_REGS
1707 /* Return attribute type of insn. */
1709 static enum attr_type
1710 s390_safe_attr_type (rtx_insn
*insn
)
1712 if (recog_memoized (insn
) >= 0)
1713 return get_attr_type (insn
);
1718 /* Return true if DISP is a valid short displacement. */
1721 s390_short_displacement (rtx disp
)
1723 /* No displacement is OK. */
1727 /* Without the long displacement facility we don't need to
1728 distingiush between long and short displacement. */
1729 if (!TARGET_LONG_DISPLACEMENT
)
1732 /* Integer displacement in range. */
1733 if (GET_CODE (disp
) == CONST_INT
)
1734 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1736 /* GOT offset is not OK, the GOT can be large. */
1737 if (GET_CODE (disp
) == CONST
1738 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1739 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1740 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1743 /* All other symbolic constants are literal pool references,
1744 which are OK as the literal pool must be small. */
1745 if (GET_CODE (disp
) == CONST
)
1751 /* Decompose a RTL expression ADDR for a memory address into
1752 its components, returned in OUT.
1754 Returns false if ADDR is not a valid memory address, true
1755 otherwise. If OUT is NULL, don't return the components,
1756 but check for validity only.
1758 Note: Only addresses in canonical form are recognized.
1759 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1760 canonical form so that they will be recognized. */
1763 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1765 HOST_WIDE_INT offset
= 0;
1766 rtx base
= NULL_RTX
;
1767 rtx indx
= NULL_RTX
;
1768 rtx disp
= NULL_RTX
;
1770 bool pointer
= false;
1771 bool base_ptr
= false;
1772 bool indx_ptr
= false;
1773 bool literal_pool
= false;
1775 /* We may need to substitute the literal pool base register into the address
1776 below. However, at this point we do not know which register is going to
1777 be used as base, so we substitute the arg pointer register. This is going
1778 to be treated as holding a pointer below -- it shouldn't be used for any
1780 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1782 /* Decompose address into base + index + displacement. */
1784 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1787 else if (GET_CODE (addr
) == PLUS
)
1789 rtx op0
= XEXP (addr
, 0);
1790 rtx op1
= XEXP (addr
, 1);
1791 enum rtx_code code0
= GET_CODE (op0
);
1792 enum rtx_code code1
= GET_CODE (op1
);
1794 if (code0
== REG
|| code0
== UNSPEC
)
1796 if (code1
== REG
|| code1
== UNSPEC
)
1798 indx
= op0
; /* index + base */
1804 base
= op0
; /* base + displacement */
1809 else if (code0
== PLUS
)
1811 indx
= XEXP (op0
, 0); /* index + base + disp */
1812 base
= XEXP (op0
, 1);
1823 disp
= addr
; /* displacement */
1825 /* Extract integer part of displacement. */
1829 if (GET_CODE (disp
) == CONST_INT
)
1831 offset
= INTVAL (disp
);
1834 else if (GET_CODE (disp
) == CONST
1835 && GET_CODE (XEXP (disp
, 0)) == PLUS
1836 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1838 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1839 disp
= XEXP (XEXP (disp
, 0), 0);
1843 /* Strip off CONST here to avoid special case tests later. */
1844 if (disp
&& GET_CODE (disp
) == CONST
)
1845 disp
= XEXP (disp
, 0);
1847 /* We can convert literal pool addresses to
1848 displacements by basing them off the base register. */
1849 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1851 /* Either base or index must be free to hold the base register. */
1853 base
= fake_pool_base
, literal_pool
= true;
1855 indx
= fake_pool_base
, literal_pool
= true;
1859 /* Mark up the displacement. */
1860 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1861 UNSPEC_LTREL_OFFSET
);
1864 /* Validate base register. */
1867 if (GET_CODE (base
) == UNSPEC
)
1868 switch (XINT (base
, 1))
1872 disp
= gen_rtx_UNSPEC (Pmode
,
1873 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1874 UNSPEC_LTREL_OFFSET
);
1878 base
= XVECEXP (base
, 0, 1);
1881 case UNSPEC_LTREL_BASE
:
1882 if (XVECLEN (base
, 0) == 1)
1883 base
= fake_pool_base
, literal_pool
= true;
1885 base
= XVECEXP (base
, 0, 1);
1893 || (GET_MODE (base
) != SImode
1894 && GET_MODE (base
) != Pmode
))
1897 if (REGNO (base
) == STACK_POINTER_REGNUM
1898 || REGNO (base
) == FRAME_POINTER_REGNUM
1899 || ((reload_completed
|| reload_in_progress
)
1900 && frame_pointer_needed
1901 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1902 || REGNO (base
) == ARG_POINTER_REGNUM
1904 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1905 pointer
= base_ptr
= true;
1907 if ((reload_completed
|| reload_in_progress
)
1908 && base
== cfun
->machine
->base_reg
)
1909 pointer
= base_ptr
= literal_pool
= true;
1912 /* Validate index register. */
1915 if (GET_CODE (indx
) == UNSPEC
)
1916 switch (XINT (indx
, 1))
1920 disp
= gen_rtx_UNSPEC (Pmode
,
1921 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1922 UNSPEC_LTREL_OFFSET
);
1926 indx
= XVECEXP (indx
, 0, 1);
1929 case UNSPEC_LTREL_BASE
:
1930 if (XVECLEN (indx
, 0) == 1)
1931 indx
= fake_pool_base
, literal_pool
= true;
1933 indx
= XVECEXP (indx
, 0, 1);
1941 || (GET_MODE (indx
) != SImode
1942 && GET_MODE (indx
) != Pmode
))
1945 if (REGNO (indx
) == STACK_POINTER_REGNUM
1946 || REGNO (indx
) == FRAME_POINTER_REGNUM
1947 || ((reload_completed
|| reload_in_progress
)
1948 && frame_pointer_needed
1949 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1950 || REGNO (indx
) == ARG_POINTER_REGNUM
1952 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1953 pointer
= indx_ptr
= true;
1955 if ((reload_completed
|| reload_in_progress
)
1956 && indx
== cfun
->machine
->base_reg
)
1957 pointer
= indx_ptr
= literal_pool
= true;
1960 /* Prefer to use pointer as base, not index. */
1961 if (base
&& indx
&& !base_ptr
1962 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1969 /* Validate displacement. */
1972 /* If virtual registers are involved, the displacement will change later
1973 anyway as the virtual registers get eliminated. This could make a
1974 valid displacement invalid, but it is more likely to make an invalid
1975 displacement valid, because we sometimes access the register save area
1976 via negative offsets to one of those registers.
1977 Thus we don't check the displacement for validity here. If after
1978 elimination the displacement turns out to be invalid after all,
1979 this is fixed up by reload in any case. */
1980 /* LRA maintains always displacements up to date and we need to
1981 know the displacement is right during all LRA not only at the
1982 final elimination. */
1984 || (base
!= arg_pointer_rtx
1985 && indx
!= arg_pointer_rtx
1986 && base
!= return_address_pointer_rtx
1987 && indx
!= return_address_pointer_rtx
1988 && base
!= frame_pointer_rtx
1989 && indx
!= frame_pointer_rtx
1990 && base
!= virtual_stack_vars_rtx
1991 && indx
!= virtual_stack_vars_rtx
))
1992 if (!DISP_IN_RANGE (offset
))
1997 /* All the special cases are pointers. */
2000 /* In the small-PIC case, the linker converts @GOT
2001 and @GOTNTPOFF offsets to possible displacements. */
2002 if (GET_CODE (disp
) == UNSPEC
2003 && (XINT (disp
, 1) == UNSPEC_GOT
2004 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2010 /* Accept pool label offsets. */
2011 else if (GET_CODE (disp
) == UNSPEC
2012 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2015 /* Accept literal pool references. */
2016 else if (GET_CODE (disp
) == UNSPEC
2017 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2019 /* In case CSE pulled a non literal pool reference out of
2020 the pool we have to reject the address. This is
2021 especially important when loading the GOT pointer on non
2022 zarch CPUs. In this case the literal pool contains an lt
2023 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2024 will most likely exceed the displacement. */
2025 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2026 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2029 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2032 /* If we have an offset, make sure it does not
2033 exceed the size of the constant pool entry. */
2034 rtx sym
= XVECEXP (disp
, 0, 0);
2035 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2038 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2053 out
->disp
= orig_disp
;
2054 out
->pointer
= pointer
;
2055 out
->literal_pool
= literal_pool
;
2061 /* Decompose a RTL expression OP for a shift count into its components,
2062 and return the base register in BASE and the offset in OFFSET.
2064 Return true if OP is a valid shift count, false if not. */
2067 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2069 HOST_WIDE_INT off
= 0;
2071 /* We can have an integer constant, an address register,
2072 or a sum of the two. */
2073 if (GET_CODE (op
) == CONST_INT
)
2078 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2080 off
= INTVAL (XEXP (op
, 1));
2083 while (op
&& GET_CODE (op
) == SUBREG
)
2084 op
= SUBREG_REG (op
);
2086 if (op
&& GET_CODE (op
) != REG
)
2098 /* Return true if CODE is a valid address without index. */
2101 s390_legitimate_address_without_index_p (rtx op
)
2103 struct s390_address addr
;
2105 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2114 /* Return TRUE if ADDR is an operand valid for a load/store relative
2115 instruction. Be aware that the alignment of the operand needs to
2116 be checked separately.
2117 Valid addresses are single references or a sum of a reference and a
2118 constant integer. Return these parts in SYMREF and ADDEND. You can
2119 pass NULL in REF and/or ADDEND if you are not interested in these
2120 values. Literal pool references are *not* considered symbol
2124 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2126 HOST_WIDE_INT tmpaddend
= 0;
2128 if (GET_CODE (addr
) == CONST
)
2129 addr
= XEXP (addr
, 0);
2131 if (GET_CODE (addr
) == PLUS
)
2133 if (!CONST_INT_P (XEXP (addr
, 1)))
2136 tmpaddend
= INTVAL (XEXP (addr
, 1));
2137 addr
= XEXP (addr
, 0);
2140 if ((GET_CODE (addr
) == SYMBOL_REF
&& !CONSTANT_POOL_ADDRESS_P (addr
))
2141 || (GET_CODE (addr
) == UNSPEC
2142 && (XINT (addr
, 1) == UNSPEC_GOTENT
2143 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
2148 *addend
= tmpaddend
;
2155 /* Return true if the address in OP is valid for constraint letter C
2156 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2157 pool MEMs should be accepted. Only the Q, R, S, T constraint
2158 letters are allowed for C. */
2161 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2163 struct s390_address addr
;
2164 bool decomposed
= false;
2166 /* This check makes sure that no symbolic address (except literal
2167 pool references) are accepted by the R or T constraints. */
2168 if (s390_loadrelative_operand_p (op
, NULL
, NULL
))
2171 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2174 if (!s390_decompose_address (op
, &addr
))
2176 if (addr
.literal_pool
)
2183 case 'Q': /* no index short displacement */
2184 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2188 if (!s390_short_displacement (addr
.disp
))
2192 case 'R': /* with index short displacement */
2193 if (TARGET_LONG_DISPLACEMENT
)
2195 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2197 if (!s390_short_displacement (addr
.disp
))
2200 /* Any invalid address here will be fixed up by reload,
2201 so accept it for the most generic constraint. */
2204 case 'S': /* no index long displacement */
2205 if (!TARGET_LONG_DISPLACEMENT
)
2207 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2211 if (s390_short_displacement (addr
.disp
))
2215 case 'T': /* with index long displacement */
2216 if (!TARGET_LONG_DISPLACEMENT
)
2218 /* Any invalid address here will be fixed up by reload,
2219 so accept it for the most generic constraint. */
2220 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2221 && s390_short_displacement (addr
.disp
))
2231 /* Evaluates constraint strings described by the regular expression
2232 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2233 the constraint given in STR, or 0 else. */
2236 s390_mem_constraint (const char *str
, rtx op
)
2243 /* Check for offsettable variants of memory constraints. */
2244 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2246 if ((reload_completed
|| reload_in_progress
)
2247 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2249 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2251 /* Check for non-literal-pool variants of memory constraints. */
2254 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2259 if (GET_CODE (op
) != MEM
)
2261 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2263 return (s390_check_qrst_address ('Q', op
, true)
2264 || s390_check_qrst_address ('R', op
, true));
2266 return (s390_check_qrst_address ('S', op
, true)
2267 || s390_check_qrst_address ('T', op
, true));
2269 /* Simply check for the basic form of a shift count. Reload will
2270 take care of making sure we have a proper base register. */
2271 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2275 return s390_check_qrst_address (str
[1], op
, true);
2283 /* Evaluates constraint strings starting with letter O. Input
2284 parameter C is the second letter following the "O" in the constraint
2285 string. Returns 1 if VALUE meets the respective constraint and 0
2289 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2297 return trunc_int_for_mode (value
, SImode
) == value
;
2301 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2304 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2312 /* Evaluates constraint strings starting with letter N. Parameter STR
2313 contains the letters following letter "N" in the constraint string.
2314 Returns true if VALUE matches the constraint. */
2317 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2319 machine_mode mode
, part_mode
;
2321 int part
, part_goal
;
2327 part_goal
= str
[0] - '0';
2371 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2374 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2377 if (part_goal
!= -1 && part_goal
!= part
)
2384 /* Returns true if the input parameter VALUE is a float zero. */
2387 s390_float_const_zero_p (rtx value
)
2389 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2390 && value
== CONST0_RTX (GET_MODE (value
)));
2393 /* Implement TARGET_REGISTER_MOVE_COST. */
2396 s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2397 reg_class_t from
, reg_class_t to
)
2399 /* On s390, copy between fprs and gprs is expensive as long as no
2400 ldgr/lgdr can be used. */
2401 if ((!TARGET_Z10
|| GET_MODE_SIZE (mode
) != 8)
2402 && ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2403 && reg_classes_intersect_p (to
, FP_REGS
))
2404 || (reg_classes_intersect_p (from
, FP_REGS
)
2405 && reg_classes_intersect_p (to
, GENERAL_REGS
))))
2411 /* Implement TARGET_MEMORY_MOVE_COST. */
2414 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2415 reg_class_t rclass ATTRIBUTE_UNUSED
,
2416 bool in ATTRIBUTE_UNUSED
)
2421 /* Compute a (partial) cost for rtx X. Return true if the complete
2422 cost has been computed, and false if subexpressions should be
2423 scanned. In either case, *TOTAL contains the cost result.
2424 CODE contains GET_CODE (x), OUTER_CODE contains the code
2425 of the superexpression of x. */
2428 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2429 int *total
, bool speed ATTRIBUTE_UNUSED
)
2452 *total
= COSTS_N_INSNS (1);
2457 *total
= COSTS_N_INSNS (1);
2461 switch (GET_MODE (x
))
2465 rtx left
= XEXP (x
, 0);
2466 rtx right
= XEXP (x
, 1);
2467 if (GET_CODE (right
) == CONST_INT
2468 && CONST_OK_FOR_K (INTVAL (right
)))
2469 *total
= s390_cost
->mhi
;
2470 else if (GET_CODE (left
) == SIGN_EXTEND
)
2471 *total
= s390_cost
->mh
;
2473 *total
= s390_cost
->ms
; /* msr, ms, msy */
2478 rtx left
= XEXP (x
, 0);
2479 rtx right
= XEXP (x
, 1);
2482 if (GET_CODE (right
) == CONST_INT
2483 && CONST_OK_FOR_K (INTVAL (right
)))
2484 *total
= s390_cost
->mghi
;
2485 else if (GET_CODE (left
) == SIGN_EXTEND
)
2486 *total
= s390_cost
->msgf
;
2488 *total
= s390_cost
->msg
; /* msgr, msg */
2490 else /* TARGET_31BIT */
2492 if (GET_CODE (left
) == SIGN_EXTEND
2493 && GET_CODE (right
) == SIGN_EXTEND
)
2494 /* mulsidi case: mr, m */
2495 *total
= s390_cost
->m
;
2496 else if (GET_CODE (left
) == ZERO_EXTEND
2497 && GET_CODE (right
) == ZERO_EXTEND
2498 && TARGET_CPU_ZARCH
)
2499 /* umulsidi case: ml, mlr */
2500 *total
= s390_cost
->ml
;
2502 /* Complex calculation is required. */
2503 *total
= COSTS_N_INSNS (40);
2509 *total
= s390_cost
->mult_df
;
2512 *total
= s390_cost
->mxbr
;
2520 switch (GET_MODE (x
))
2523 *total
= s390_cost
->madbr
;
2526 *total
= s390_cost
->maebr
;
2531 /* Negate in the third argument is free: FMSUB. */
2532 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2534 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
2535 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
2536 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
2543 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2544 *total
= s390_cost
->dlgr
;
2545 else if (GET_MODE (x
) == DImode
)
2547 rtx right
= XEXP (x
, 1);
2548 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2549 *total
= s390_cost
->dlr
;
2550 else /* 64 by 64 bit division */
2551 *total
= s390_cost
->dlgr
;
2553 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2554 *total
= s390_cost
->dlr
;
2559 if (GET_MODE (x
) == DImode
)
2561 rtx right
= XEXP (x
, 1);
2562 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2564 *total
= s390_cost
->dsgfr
;
2566 *total
= s390_cost
->dr
;
2567 else /* 64 by 64 bit division */
2568 *total
= s390_cost
->dsgr
;
2570 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2571 *total
= s390_cost
->dlr
;
2572 else if (GET_MODE (x
) == SFmode
)
2574 *total
= s390_cost
->debr
;
2576 else if (GET_MODE (x
) == DFmode
)
2578 *total
= s390_cost
->ddbr
;
2580 else if (GET_MODE (x
) == TFmode
)
2582 *total
= s390_cost
->dxbr
;
2587 if (GET_MODE (x
) == SFmode
)
2588 *total
= s390_cost
->sqebr
;
2589 else if (GET_MODE (x
) == DFmode
)
2590 *total
= s390_cost
->sqdbr
;
2592 *total
= s390_cost
->sqxbr
;
2597 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2598 || outer_code
== PLUS
|| outer_code
== MINUS
2599 || outer_code
== COMPARE
)
2604 *total
= COSTS_N_INSNS (1);
2605 if (GET_CODE (XEXP (x
, 0)) == AND
2606 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2607 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2609 rtx op0
= XEXP (XEXP (x
, 0), 0);
2610 rtx op1
= XEXP (XEXP (x
, 0), 1);
2611 rtx op2
= XEXP (x
, 1);
2613 if (memory_operand (op0
, GET_MODE (op0
))
2614 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2616 if (register_operand (op0
, GET_MODE (op0
))
2617 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2627 /* Return the cost of an address rtx ADDR. */
2630 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
2631 addr_space_t as ATTRIBUTE_UNUSED
,
2632 bool speed ATTRIBUTE_UNUSED
)
2634 struct s390_address ad
;
2635 if (!s390_decompose_address (addr
, &ad
))
2638 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2641 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2642 otherwise return 0. */
2645 tls_symbolic_operand (rtx op
)
2647 if (GET_CODE (op
) != SYMBOL_REF
)
2649 return SYMBOL_REF_TLS_MODEL (op
);
2652 /* Split DImode access register reference REG (on 64-bit) into its constituent
2653 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2654 gen_highpart cannot be used as they assume all registers are word-sized,
2655 while our access registers have only half that size. */
2658 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2660 gcc_assert (TARGET_64BIT
);
2661 gcc_assert (ACCESS_REG_P (reg
));
2662 gcc_assert (GET_MODE (reg
) == DImode
);
2663 gcc_assert (!(REGNO (reg
) & 1));
2665 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2666 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2669 /* Return true if OP contains a symbol reference */
2672 symbolic_reference_mentioned_p (rtx op
)
2677 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2680 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2681 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2687 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2688 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2692 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2699 /* Return true if OP contains a reference to a thread-local symbol. */
2702 tls_symbolic_reference_mentioned_p (rtx op
)
2707 if (GET_CODE (op
) == SYMBOL_REF
)
2708 return tls_symbolic_operand (op
);
2710 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2711 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2717 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2718 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2722 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2730 /* Return true if OP is a legitimate general operand when
2731 generating PIC code. It is given that flag_pic is on
2732 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2735 legitimate_pic_operand_p (rtx op
)
2737 /* Accept all non-symbolic constants. */
2738 if (!SYMBOLIC_CONST (op
))
2741 /* Reject everything else; must be handled
2742 via emit_symbolic_move. */
2746 /* Returns true if the constant value OP is a legitimate general operand.
2747 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2750 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
2752 /* Accept all non-symbolic constants. */
2753 if (!SYMBOLIC_CONST (op
))
2756 /* Accept immediate LARL operands. */
2757 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
2760 /* Thread-local symbols are never legal constants. This is
2761 so that emit_call knows that computing such addresses
2762 might require a function call. */
2763 if (TLS_SYMBOLIC_CONST (op
))
2766 /* In the PIC case, symbolic constants must *not* be
2767 forced into the literal pool. We accept them here,
2768 so that they will be handled by emit_symbolic_move. */
2772 /* All remaining non-PIC symbolic constants are
2773 forced into the literal pool. */
2777 /* Determine if it's legal to put X into the constant pool. This
2778 is not possible if X contains the address of a symbol that is
2779 not constant (TLS) or not known at final link time (PIC). */
2782 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
2784 switch (GET_CODE (x
))
2788 /* Accept all non-symbolic constants. */
2792 /* Labels are OK iff we are non-PIC. */
2793 return flag_pic
!= 0;
2796 /* 'Naked' TLS symbol references are never OK,
2797 non-TLS symbols are OK iff we are non-PIC. */
2798 if (tls_symbolic_operand (x
))
2801 return flag_pic
!= 0;
2804 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2807 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2808 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2811 switch (XINT (x
, 1))
2813 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2814 case UNSPEC_LTREL_OFFSET
:
2822 case UNSPEC_GOTNTPOFF
:
2823 case UNSPEC_INDNTPOFF
:
2826 /* If the literal pool shares the code section, be put
2827 execute template placeholders into the pool as well. */
2829 return TARGET_CPU_ZARCH
;
2841 /* Returns true if the constant value OP is a legitimate general
2842 operand during and after reload. The difference to
2843 legitimate_constant_p is that this function will not accept
2844 a constant that would need to be forced to the literal pool
2845 before it can be used as operand.
2846 This function accepts all constants which can be loaded directly
2850 legitimate_reload_constant_p (rtx op
)
2852 /* Accept la(y) operands. */
2853 if (GET_CODE (op
) == CONST_INT
2854 && DISP_IN_RANGE (INTVAL (op
)))
2857 /* Accept l(g)hi/l(g)fi operands. */
2858 if (GET_CODE (op
) == CONST_INT
2859 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2862 /* Accept lliXX operands. */
2864 && GET_CODE (op
) == CONST_INT
2865 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2866 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2870 && GET_CODE (op
) == CONST_INT
2871 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2872 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2875 /* Accept larl operands. */
2876 if (TARGET_CPU_ZARCH
2877 && larl_operand (op
, VOIDmode
))
2880 /* Accept floating-point zero operands that fit into a single GPR. */
2881 if (GET_CODE (op
) == CONST_DOUBLE
2882 && s390_float_const_zero_p (op
)
2883 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2886 /* Accept double-word operands that can be split. */
2887 if (GET_CODE (op
) == CONST_INT
2888 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2890 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2891 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2892 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2893 return legitimate_reload_constant_p (hi
)
2894 && legitimate_reload_constant_p (lo
);
2897 /* Everything else cannot be handled without reload. */
2901 /* Returns true if the constant value OP is a legitimate fp operand
2902 during and after reload.
2903 This function accepts all constants which can be loaded directly
2907 legitimate_reload_fp_constant_p (rtx op
)
2909 /* Accept floating-point zero operands if the load zero instruction
2910 can be used. Prior to z196 the load fp zero instruction caused a
2911 performance penalty if the result is used as BFP number. */
2913 && GET_CODE (op
) == CONST_DOUBLE
2914 && s390_float_const_zero_p (op
))
2920 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2921 return the class of reg to actually use. */
2924 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2926 switch (GET_CODE (op
))
2928 /* Constants we cannot reload into general registers
2929 must be forced into the literal pool. */
2932 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2933 && legitimate_reload_constant_p (op
))
2934 return GENERAL_REGS
;
2935 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2936 && legitimate_reload_constant_p (op
))
2938 else if (reg_class_subset_p (FP_REGS
, rclass
)
2939 && legitimate_reload_fp_constant_p (op
))
2943 /* If a symbolic constant or a PLUS is reloaded,
2944 it is most likely being used as an address, so
2945 prefer ADDR_REGS. If 'class' is not a superset
2946 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2948 /* Symrefs cannot be pushed into the literal pool with -fPIC
2949 so we *MUST NOT* return NO_REGS for these cases
2950 (s390_cannot_force_const_mem will return true).
2952 On the other hand we MUST return NO_REGS for symrefs with
2953 invalid addend which might have been pushed to the literal
2954 pool (no -fPIC). Usually we would expect them to be
2955 handled via secondary reload but this does not happen if
2956 they are used as literal pool slot replacement in reload
2957 inheritance (see emit_input_reload_insns). */
2958 if (TARGET_CPU_ZARCH
2959 && GET_CODE (XEXP (op
, 0)) == PLUS
2960 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
2961 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
2963 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
2971 if (!legitimate_reload_constant_p (op
))
2975 /* load address will be used. */
2976 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2988 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2989 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2993 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2995 HOST_WIDE_INT addend
;
2998 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3001 if (addend
& (alignment
- 1))
3004 if (GET_CODE (symref
) == SYMBOL_REF
3005 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
))
3008 if (GET_CODE (symref
) == UNSPEC
3009 && alignment
<= UNITS_PER_LONG
)
3015 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3016 operand SCRATCH is used to reload the even part of the address and
3020 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3022 HOST_WIDE_INT addend
;
3025 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3029 /* Easy case. The addend is even so larl will do fine. */
3030 emit_move_insn (reg
, addr
);
3033 /* We can leave the scratch register untouched if the target
3034 register is a valid base register. */
3035 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3036 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3039 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3040 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3043 emit_move_insn (scratch
,
3044 gen_rtx_CONST (Pmode
,
3045 gen_rtx_PLUS (Pmode
, symref
,
3046 GEN_INT (addend
- 1))));
3048 emit_move_insn (scratch
, symref
);
3050 /* Increment the address using la in order to avoid clobbering cc. */
3051 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3055 /* Generate what is necessary to move between REG and MEM using
3056 SCRATCH. The direction is given by TOMEM. */
3059 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3061 /* Reload might have pulled a constant out of the literal pool.
3062 Force it back in. */
3063 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3064 || GET_CODE (mem
) == CONST
)
3065 mem
= force_const_mem (GET_MODE (reg
), mem
);
3067 gcc_assert (MEM_P (mem
));
3069 /* For a load from memory we can leave the scratch register
3070 untouched if the target register is a valid base register. */
3072 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3073 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3074 && GET_MODE (reg
) == GET_MODE (scratch
))
3077 /* Load address into scratch register. Since we can't have a
3078 secondary reload for a secondary reload we have to cover the case
3079 where larl would need a secondary reload here as well. */
3080 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3082 /* Now we can use a standard load/store to do the move. */
3084 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3086 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3089 /* Inform reload about cases where moving X with a mode MODE to a register in
3090 RCLASS requires an extra scratch or immediate register. Return the class
3091 needed for the immediate register. */
3094 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3095 machine_mode mode
, secondary_reload_info
*sri
)
3097 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3099 /* Intermediate register needed. */
3100 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3101 return GENERAL_REGS
;
3105 HOST_WIDE_INT offset
;
3108 /* On z10 several optimizer steps may generate larl operands with
3111 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
3113 && !SYMBOL_REF_ALIGN1_P (symref
)
3114 && (offset
& 1) == 1)
3115 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3116 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3118 /* On z10 we need a scratch register when moving QI, TI or floating
3119 point mode values from or to a memory location with a SYMBOL_REF
3120 or if the symref addend of a SI or DI move is not aligned to the
3121 width of the access. */
3123 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
3124 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3125 || (!TARGET_ZARCH
&& mode
== DImode
)
3126 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3127 && (!s390_check_symref_alignment (XEXP (x
, 0),
3128 GET_MODE_SIZE (mode
))))))
3130 #define __SECONDARY_RELOAD_CASE(M,m) \
3133 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3134 CODE_FOR_reload##m##di_tomem_z10; \
3136 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3137 CODE_FOR_reload##m##si_tomem_z10; \
3140 switch (GET_MODE (x
))
3142 __SECONDARY_RELOAD_CASE (QI
, qi
);
3143 __SECONDARY_RELOAD_CASE (HI
, hi
);
3144 __SECONDARY_RELOAD_CASE (SI
, si
);
3145 __SECONDARY_RELOAD_CASE (DI
, di
);
3146 __SECONDARY_RELOAD_CASE (TI
, ti
);
3147 __SECONDARY_RELOAD_CASE (SF
, sf
);
3148 __SECONDARY_RELOAD_CASE (DF
, df
);
3149 __SECONDARY_RELOAD_CASE (TF
, tf
);
3150 __SECONDARY_RELOAD_CASE (SD
, sd
);
3151 __SECONDARY_RELOAD_CASE (DD
, dd
);
3152 __SECONDARY_RELOAD_CASE (TD
, td
);
3157 #undef __SECONDARY_RELOAD_CASE
3161 /* We need a scratch register when loading a PLUS expression which
3162 is not a legitimate operand of the LOAD ADDRESS instruction. */
3163 /* LRA can deal with transformation of plus op very well -- so we
3164 don't need to prompt LRA in this case. */
3165 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
3166 sri
->icode
= (TARGET_64BIT
?
3167 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3169 /* Performing a multiword move from or to memory we have to make sure the
3170 second chunk in memory is addressable without causing a displacement
3171 overflow. If that would be the case we calculate the address in
3172 a scratch register. */
3174 && GET_CODE (XEXP (x
, 0)) == PLUS
3175 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3176 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3177 + GET_MODE_SIZE (mode
) - 1))
3179 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3180 in a s_operand address since we may fallback to lm/stm. So we only
3181 have to care about overflows in the b+i+d case. */
3182 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3183 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3184 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3185 /* For FP_REGS no lm/stm is available so this check is triggered
3186 for displacement overflows in b+i+d and b+d like addresses. */
3187 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3188 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3191 sri
->icode
= (TARGET_64BIT
?
3192 CODE_FOR_reloaddi_nonoffmem_in
:
3193 CODE_FOR_reloadsi_nonoffmem_in
);
3195 sri
->icode
= (TARGET_64BIT
?
3196 CODE_FOR_reloaddi_nonoffmem_out
:
3197 CODE_FOR_reloadsi_nonoffmem_out
);
3201 /* A scratch address register is needed when a symbolic constant is
3202 copied to r0 compiling with -fPIC. In other cases the target
3203 register might be used as temporary (see legitimize_pic_address). */
3204 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3205 sri
->icode
= (TARGET_64BIT
?
3206 CODE_FOR_reloaddi_PIC_addr
:
3207 CODE_FOR_reloadsi_PIC_addr
);
3209 /* Either scratch or no register needed. */
3213 /* Generate code to load SRC, which is PLUS that is not a
3214 legitimate operand for the LA instruction, into TARGET.
3215 SCRATCH may be used as scratch register. */
3218 s390_expand_plus_operand (rtx target
, rtx src
,
3222 struct s390_address ad
;
3224 /* src must be a PLUS; get its two operands. */
3225 gcc_assert (GET_CODE (src
) == PLUS
);
3226 gcc_assert (GET_MODE (src
) == Pmode
);
3228 /* Check if any of the two operands is already scheduled
3229 for replacement by reload. This can happen e.g. when
3230 float registers occur in an address. */
3231 sum1
= find_replacement (&XEXP (src
, 0));
3232 sum2
= find_replacement (&XEXP (src
, 1));
3233 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3235 /* If the address is already strictly valid, there's nothing to do. */
3236 if (!s390_decompose_address (src
, &ad
)
3237 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3238 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3240 /* Otherwise, one of the operands cannot be an address register;
3241 we reload its value into the scratch register. */
3242 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3244 emit_move_insn (scratch
, sum1
);
3247 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3249 emit_move_insn (scratch
, sum2
);
3253 /* According to the way these invalid addresses are generated
3254 in reload.c, it should never happen (at least on s390) that
3255 *neither* of the PLUS components, after find_replacements
3256 was applied, is an address register. */
3257 if (sum1
== scratch
&& sum2
== scratch
)
3263 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3266 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3267 is only ever performed on addresses, so we can mark the
3268 sum as legitimate for LA in any case. */
3269 s390_load_address (target
, src
);
3273 /* Return true if ADDR is a valid memory address.
3274 STRICT specifies whether strict register checking applies. */
3277 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
3279 struct s390_address ad
;
3282 && larl_operand (addr
, VOIDmode
)
3283 && (mode
== VOIDmode
3284 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3287 if (!s390_decompose_address (addr
, &ad
))
3292 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3295 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3301 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3302 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3306 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3307 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3313 /* Return true if OP is a valid operand for the LA instruction.
3314 In 31-bit, we need to prove that the result is used as an
3315 address, as LA performs only a 31-bit addition. */
3318 legitimate_la_operand_p (rtx op
)
3320 struct s390_address addr
;
3321 if (!s390_decompose_address (op
, &addr
))
3324 return (TARGET_64BIT
|| addr
.pointer
);
3327 /* Return true if it is valid *and* preferable to use LA to
3328 compute the sum of OP1 and OP2. */
3331 preferred_la_operand_p (rtx op1
, rtx op2
)
3333 struct s390_address addr
;
3335 if (op2
!= const0_rtx
)
3336 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3338 if (!s390_decompose_address (op1
, &addr
))
3340 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3342 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3345 /* Avoid LA instructions with index register on z196; it is
3346 preferable to use regular add instructions when possible.
3347 Starting with zEC12 the la with index register is "uncracked"
3349 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3352 if (!TARGET_64BIT
&& !addr
.pointer
)
3358 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3359 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3365 /* Emit a forced load-address operation to load SRC into DST.
3366 This will use the LOAD ADDRESS instruction even in situations
3367 where legitimate_la_operand_p (SRC) returns false. */
3370 s390_load_address (rtx dst
, rtx src
)
3373 emit_move_insn (dst
, src
);
3375 emit_insn (gen_force_la_31 (dst
, src
));
3378 /* Return a legitimate reference for ORIG (an address) using the
3379 register REG. If REG is 0, a new pseudo is generated.
3381 There are two types of references that must be handled:
3383 1. Global data references must load the address from the GOT, via
3384 the PIC reg. An insn is emitted to do this load, and the reg is
3387 2. Static data references, constant pool addresses, and code labels
3388 compute the address as an offset from the GOT, whose base is in
3389 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3390 differentiate them from global data objects. The returned
3391 address is the PIC reg + an unspec constant.
3393 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3394 reg also appears in the address. */
3397 legitimize_pic_address (rtx orig
, rtx reg
)
3400 rtx addend
= const0_rtx
;
3403 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3405 if (GET_CODE (addr
) == CONST
)
3406 addr
= XEXP (addr
, 0);
3408 if (GET_CODE (addr
) == PLUS
)
3410 addend
= XEXP (addr
, 1);
3411 addr
= XEXP (addr
, 0);
3414 if ((GET_CODE (addr
) == LABEL_REF
3415 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
))
3416 || (GET_CODE (addr
) == UNSPEC
&&
3417 (XINT (addr
, 1) == UNSPEC_GOTENT
3418 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
3419 && GET_CODE (addend
) == CONST_INT
)
3421 /* This can be locally addressed. */
3423 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3424 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
3425 gen_rtx_CONST (Pmode
, addr
) : addr
);
3427 if (TARGET_CPU_ZARCH
3428 && larl_operand (const_addr
, VOIDmode
)
3429 && INTVAL (addend
) < (HOST_WIDE_INT
)1 << 31
3430 && INTVAL (addend
) >= -((HOST_WIDE_INT
)1 << 31))
3432 if (INTVAL (addend
) & 1)
3434 /* LARL can't handle odd offsets, so emit a pair of LARL
3436 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3438 if (!DISP_IN_RANGE (INTVAL (addend
)))
3440 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
3441 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
3442 addr
= gen_rtx_CONST (Pmode
, addr
);
3443 addend
= const1_rtx
;
3446 emit_move_insn (temp
, addr
);
3447 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
3451 s390_load_address (reg
, new_rtx
);
3457 /* If the offset is even, we can just use LARL. This
3458 will happen automatically. */
3463 /* No larl - Access local symbols relative to the GOT. */
3465 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3467 if (reload_in_progress
|| reload_completed
)
3468 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3470 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3471 if (addend
!= const0_rtx
)
3472 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
3473 addr
= gen_rtx_CONST (Pmode
, addr
);
3474 addr
= force_const_mem (Pmode
, addr
);
3475 emit_move_insn (temp
, addr
);
3477 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3480 s390_load_address (reg
, new_rtx
);
3485 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
3487 /* A non-local symbol reference without addend.
3489 The symbol ref is wrapped into an UNSPEC to make sure the
3490 proper operand modifier (@GOT or @GOTENT) will be emitted.
3491 This will tell the linker to put the symbol into the GOT.
3493 Additionally the code dereferencing the GOT slot is emitted here.
3495 An addend to the symref needs to be added afterwards.
3496 legitimize_pic_address calls itself recursively to handle
3497 that case. So no need to do it here. */
3500 reg
= gen_reg_rtx (Pmode
);
3504 /* Use load relative if possible.
3505 lgrl <target>, sym@GOTENT */
3506 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3507 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3508 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
3510 emit_move_insn (reg
, new_rtx
);
3513 else if (flag_pic
== 1)
3515 /* Assume GOT offset is a valid displacement operand (< 4k
3516 or < 512k with z990). This is handled the same way in
3517 both 31- and 64-bit code (@GOT).
3518 lg <target>, sym@GOT(r12) */
3520 if (reload_in_progress
|| reload_completed
)
3521 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3523 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3524 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3525 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3526 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3527 emit_move_insn (reg
, new_rtx
);
3530 else if (TARGET_CPU_ZARCH
)
3532 /* If the GOT offset might be >= 4k, we determine the position
3533 of the GOT entry via a PC-relative LARL (@GOTENT).
3534 larl temp, sym@GOTENT
3535 lg <target>, 0(temp) */
3537 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3539 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3540 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3542 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3543 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3544 emit_move_insn (temp
, new_rtx
);
3546 new_rtx
= gen_const_mem (Pmode
, temp
);
3547 emit_move_insn (reg
, new_rtx
);
3553 /* If the GOT offset might be >= 4k, we have to load it
3554 from the literal pool (@GOT).
3556 lg temp, lit-litbase(r13)
3557 lg <target>, 0(temp)
3558 lit: .long sym@GOT */
3560 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3562 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3563 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3565 if (reload_in_progress
|| reload_completed
)
3566 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3568 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3569 addr
= gen_rtx_CONST (Pmode
, addr
);
3570 addr
= force_const_mem (Pmode
, addr
);
3571 emit_move_insn (temp
, addr
);
3573 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3574 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3575 emit_move_insn (reg
, new_rtx
);
3579 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
3581 gcc_assert (XVECLEN (addr
, 0) == 1);
3582 switch (XINT (addr
, 1))
3584 /* These address symbols (or PLT slots) relative to the GOT
3585 (not GOT slots!). In general this will exceed the
3586 displacement range so these value belong into the literal
3590 new_rtx
= force_const_mem (Pmode
, orig
);
3593 /* For -fPIC the GOT size might exceed the displacement
3594 range so make sure the value is in the literal pool. */
3597 new_rtx
= force_const_mem (Pmode
, orig
);
3600 /* For @GOTENT larl is used. This is handled like local
3606 /* @PLT is OK as is on 64-bit, must be converted to
3607 GOT-relative @PLTOFF on 31-bit. */
3609 if (!TARGET_CPU_ZARCH
)
3611 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3613 if (reload_in_progress
|| reload_completed
)
3614 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3616 addr
= XVECEXP (addr
, 0, 0);
3617 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3619 if (addend
!= const0_rtx
)
3620 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
3621 addr
= gen_rtx_CONST (Pmode
, addr
);
3622 addr
= force_const_mem (Pmode
, addr
);
3623 emit_move_insn (temp
, addr
);
3625 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3628 s390_load_address (reg
, new_rtx
);
3633 /* On 64 bit larl can be used. This case is handled like
3634 local symbol refs. */
3638 /* Everything else cannot happen. */
3643 else if (addend
!= const0_rtx
)
3645 /* Otherwise, compute the sum. */
3647 rtx base
= legitimize_pic_address (addr
, reg
);
3648 new_rtx
= legitimize_pic_address (addend
,
3649 base
== reg
? NULL_RTX
: reg
);
3650 if (GET_CODE (new_rtx
) == CONST_INT
)
3651 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
3654 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3656 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3657 new_rtx
= XEXP (new_rtx
, 1);
3659 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3662 if (GET_CODE (new_rtx
) == CONST
)
3663 new_rtx
= XEXP (new_rtx
, 0);
3664 new_rtx
= force_operand (new_rtx
, 0);
3670 /* Load the thread pointer into a register. */
3673 s390_get_thread_pointer (void)
3675 rtx tp
= gen_reg_rtx (Pmode
);
3677 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3678 mark_reg_pointer (tp
, BITS_PER_WORD
);
3683 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3684 in s390_tls_symbol which always refers to __tls_get_offset.
3685 The returned offset is written to RESULT_REG and an USE rtx is
3686 generated for TLS_CALL. */
3688 static GTY(()) rtx s390_tls_symbol
;
3691 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3696 emit_insn (s390_load_got ());
3698 if (!s390_tls_symbol
)
3699 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3701 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3702 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3704 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3705 RTL_CONST_CALL_P (insn
) = 1;
3708 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3709 this (thread-local) address. REG may be used as temporary. */
3712 legitimize_tls_address (rtx addr
, rtx reg
)
3714 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3716 if (GET_CODE (addr
) == SYMBOL_REF
)
3717 switch (tls_symbolic_operand (addr
))
3719 case TLS_MODEL_GLOBAL_DYNAMIC
:
3721 r2
= gen_rtx_REG (Pmode
, 2);
3722 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3723 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3724 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3725 emit_move_insn (r2
, new_rtx
);
3726 s390_emit_tls_call_insn (r2
, tls_call
);
3727 insn
= get_insns ();
3730 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3731 temp
= gen_reg_rtx (Pmode
);
3732 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3734 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3737 s390_load_address (reg
, new_rtx
);
3742 case TLS_MODEL_LOCAL_DYNAMIC
:
3744 r2
= gen_rtx_REG (Pmode
, 2);
3745 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3746 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3747 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3748 emit_move_insn (r2
, new_rtx
);
3749 s390_emit_tls_call_insn (r2
, tls_call
);
3750 insn
= get_insns ();
3753 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3754 temp
= gen_reg_rtx (Pmode
);
3755 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3757 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3758 base
= gen_reg_rtx (Pmode
);
3759 s390_load_address (base
, new_rtx
);
3761 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3762 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3763 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3764 temp
= gen_reg_rtx (Pmode
);
3765 emit_move_insn (temp
, new_rtx
);
3767 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3770 s390_load_address (reg
, new_rtx
);
3775 case TLS_MODEL_INITIAL_EXEC
:
3778 /* Assume GOT offset < 4k. This is handled the same way
3779 in both 31- and 64-bit code. */
3781 if (reload_in_progress
|| reload_completed
)
3782 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3784 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3785 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3786 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3787 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3788 temp
= gen_reg_rtx (Pmode
);
3789 emit_move_insn (temp
, new_rtx
);
3791 else if (TARGET_CPU_ZARCH
)
3793 /* If the GOT offset might be >= 4k, we determine the position
3794 of the GOT entry via a PC-relative LARL. */
3796 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3797 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3798 temp
= gen_reg_rtx (Pmode
);
3799 emit_move_insn (temp
, new_rtx
);
3801 new_rtx
= gen_const_mem (Pmode
, temp
);
3802 temp
= gen_reg_rtx (Pmode
);
3803 emit_move_insn (temp
, new_rtx
);
3807 /* If the GOT offset might be >= 4k, we have to load it
3808 from the literal pool. */
3810 if (reload_in_progress
|| reload_completed
)
3811 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3813 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3814 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3815 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3816 temp
= gen_reg_rtx (Pmode
);
3817 emit_move_insn (temp
, new_rtx
);
3819 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3820 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3822 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3823 temp
= gen_reg_rtx (Pmode
);
3824 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3828 /* In position-dependent code, load the absolute address of
3829 the GOT entry from the literal pool. */
3831 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3832 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3833 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3834 temp
= gen_reg_rtx (Pmode
);
3835 emit_move_insn (temp
, new_rtx
);
3838 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3839 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3840 temp
= gen_reg_rtx (Pmode
);
3841 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3844 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3847 s390_load_address (reg
, new_rtx
);
3852 case TLS_MODEL_LOCAL_EXEC
:
3853 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3854 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3855 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3856 temp
= gen_reg_rtx (Pmode
);
3857 emit_move_insn (temp
, new_rtx
);
3859 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3862 s390_load_address (reg
, new_rtx
);
3871 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3873 switch (XINT (XEXP (addr
, 0), 1))
3875 case UNSPEC_INDNTPOFF
:
3876 gcc_assert (TARGET_CPU_ZARCH
);
3885 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3886 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3888 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3889 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3890 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3892 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3893 new_rtx
= plus_constant (Pmode
, new_rtx
,
3894 INTVAL (XEXP (XEXP (addr
, 0), 1)));
3895 new_rtx
= force_operand (new_rtx
, 0);
3899 gcc_unreachable (); /* for now ... */
3904 /* Emit insns making the address in operands[1] valid for a standard
3905 move to operands[0]. operands[1] is replaced by an address which
3906 should be used instead of the former RTX to emit the move
3910 emit_symbolic_move (rtx
*operands
)
3912 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3914 if (GET_CODE (operands
[0]) == MEM
)
3915 operands
[1] = force_reg (Pmode
, operands
[1]);
3916 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3917 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3919 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3922 /* Try machine-dependent ways of modifying an illegitimate address X
3923 to be legitimate. If we find one, return the new, valid address.
3925 OLDX is the address as it was before break_out_memory_refs was called.
3926 In some cases it is useful to look at this to decide what needs to be done.
3928 MODE is the mode of the operand pointed to by X.
3930 When -fpic is used, special handling is needed for symbolic references.
3931 See comments by legitimize_pic_address for details. */
3934 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3935 machine_mode mode ATTRIBUTE_UNUSED
)
3937 rtx constant_term
= const0_rtx
;
3939 if (TLS_SYMBOLIC_CONST (x
))
3941 x
= legitimize_tls_address (x
, 0);
3943 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3946 else if (GET_CODE (x
) == PLUS
3947 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3948 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3954 if (SYMBOLIC_CONST (x
)
3955 || (GET_CODE (x
) == PLUS
3956 && (SYMBOLIC_CONST (XEXP (x
, 0))
3957 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3958 x
= legitimize_pic_address (x
, 0);
3960 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3964 x
= eliminate_constant_term (x
, &constant_term
);
3966 /* Optimize loading of large displacements by splitting them
3967 into the multiple of 4K and the rest; this allows the
3968 former to be CSE'd if possible.
3970 Don't do this if the displacement is added to a register
3971 pointing into the stack frame, as the offsets will
3972 change later anyway. */
3974 if (GET_CODE (constant_term
) == CONST_INT
3975 && !TARGET_LONG_DISPLACEMENT
3976 && !DISP_IN_RANGE (INTVAL (constant_term
))
3977 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3979 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3980 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3982 rtx temp
= gen_reg_rtx (Pmode
);
3983 rtx val
= force_operand (GEN_INT (upper
), temp
);
3985 emit_move_insn (temp
, val
);
3987 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3988 constant_term
= GEN_INT (lower
);
3991 if (GET_CODE (x
) == PLUS
)
3993 if (GET_CODE (XEXP (x
, 0)) == REG
)
3995 rtx temp
= gen_reg_rtx (Pmode
);
3996 rtx val
= force_operand (XEXP (x
, 1), temp
);
3998 emit_move_insn (temp
, val
);
4000 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
4003 else if (GET_CODE (XEXP (x
, 1)) == REG
)
4005 rtx temp
= gen_reg_rtx (Pmode
);
4006 rtx val
= force_operand (XEXP (x
, 0), temp
);
4008 emit_move_insn (temp
, val
);
4010 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4014 if (constant_term
!= const0_rtx
)
4015 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4020 /* Try a machine-dependent way of reloading an illegitimate address AD
4021 operand. If we find one, push the reload and return the new address.
4023 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4024 and TYPE is the reload type of the current reload. */
4027 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
4028 int opnum
, int type
)
4030 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
4033 if (GET_CODE (ad
) == PLUS
)
4035 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
4036 XEXP (ad
, 0), XEXP (ad
, 1));
4041 if (GET_CODE (ad
) == PLUS
4042 && GET_CODE (XEXP (ad
, 0)) == REG
4043 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4044 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4046 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4047 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4048 rtx cst
, tem
, new_rtx
;
4050 cst
= GEN_INT (upper
);
4051 if (!legitimate_reload_constant_p (cst
))
4052 cst
= force_const_mem (Pmode
, cst
);
4054 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4055 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4057 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4058 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4059 opnum
, (enum reload_type
) type
);
4066 /* Emit code to move LEN bytes from DST to SRC. */
4069 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4071 /* When tuning for z10 or higher we rely on the Glibc functions to
4072 do the right thing. Only for constant lengths below 64k we will
4073 generate inline code. */
4074 if (s390_tune
>= PROCESSOR_2097_Z10
4075 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4078 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4080 if (INTVAL (len
) > 0)
4081 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4084 else if (TARGET_MVCLE
)
4086 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4091 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4092 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4093 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4094 rtx_code_label
*end_label
= gen_label_rtx ();
4097 mode
= GET_MODE (len
);
4098 if (mode
== VOIDmode
)
4101 dst_addr
= gen_reg_rtx (Pmode
);
4102 src_addr
= gen_reg_rtx (Pmode
);
4103 count
= gen_reg_rtx (mode
);
4104 blocks
= gen_reg_rtx (mode
);
4106 convert_move (count
, len
, 1);
4107 emit_cmp_and_jump_insns (count
, const0_rtx
,
4108 EQ
, NULL_RTX
, mode
, 1, end_label
);
4110 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4111 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4112 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4113 src
= change_address (src
, VOIDmode
, src_addr
);
4115 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4118 emit_move_insn (count
, temp
);
4120 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4123 emit_move_insn (blocks
, temp
);
4125 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4126 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4128 emit_label (loop_start_label
);
4131 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4135 /* Issue a read prefetch for the +3 cache line. */
4136 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4137 const0_rtx
, const0_rtx
);
4138 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4139 emit_insn (prefetch
);
4141 /* Issue a write prefetch for the +3 cache line. */
4142 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4143 const1_rtx
, const0_rtx
);
4144 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4145 emit_insn (prefetch
);
4148 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4149 s390_load_address (dst_addr
,
4150 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4151 s390_load_address (src_addr
,
4152 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4154 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4157 emit_move_insn (blocks
, temp
);
4159 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4160 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4162 emit_jump (loop_start_label
);
4163 emit_label (loop_end_label
);
4165 emit_insn (gen_movmem_short (dst
, src
,
4166 convert_to_mode (Pmode
, count
, 1)));
4167 emit_label (end_label
);
4172 /* Emit code to set LEN bytes at DST to VAL.
4173 Make use of clrmem if VAL is zero. */
4176 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4178 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4181 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4183 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4185 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4186 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4189 /* Initialize memory by storing the first byte. */
4190 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4192 if (INTVAL (len
) > 1)
4194 /* Initiate 1 byte overlap move.
4195 The first byte of DST is propagated through DSTP1.
4196 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4197 DST is set to size 1 so the rest of the memory location
4198 does not count as source operand. */
4199 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4200 set_mem_size (dst
, 1);
4202 emit_insn (gen_movmem_short (dstp1
, dst
,
4203 GEN_INT (INTVAL (len
) - 2)));
4208 else if (TARGET_MVCLE
)
4210 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4211 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4216 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4217 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4218 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4219 rtx_code_label
*end_label
= gen_label_rtx ();
4222 mode
= GET_MODE (len
);
4223 if (mode
== VOIDmode
)
4226 dst_addr
= gen_reg_rtx (Pmode
);
4227 count
= gen_reg_rtx (mode
);
4228 blocks
= gen_reg_rtx (mode
);
4230 convert_move (count
, len
, 1);
4231 emit_cmp_and_jump_insns (count
, const0_rtx
,
4232 EQ
, NULL_RTX
, mode
, 1, end_label
);
4234 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4235 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4237 if (val
== const0_rtx
)
4238 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4242 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4243 set_mem_size (dst
, 1);
4245 /* Initialize memory by storing the first byte. */
4246 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4248 /* If count is 1 we are done. */
4249 emit_cmp_and_jump_insns (count
, const1_rtx
,
4250 EQ
, NULL_RTX
, mode
, 1, end_label
);
4252 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4256 emit_move_insn (count
, temp
);
4258 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4261 emit_move_insn (blocks
, temp
);
4263 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4264 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4266 emit_label (loop_start_label
);
4269 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4271 /* Issue a write prefetch for the +4 cache line. */
4272 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4274 const1_rtx
, const0_rtx
);
4275 emit_insn (prefetch
);
4276 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4279 if (val
== const0_rtx
)
4280 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4282 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4283 s390_load_address (dst_addr
,
4284 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4286 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4289 emit_move_insn (blocks
, temp
);
4291 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4292 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4294 emit_jump (loop_start_label
);
4295 emit_label (loop_end_label
);
4297 if (val
== const0_rtx
)
4298 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4300 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4301 emit_label (end_label
);
4305 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4306 and return the result in TARGET. */
4309 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4311 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4314 /* When tuning for z10 or higher we rely on the Glibc functions to
4315 do the right thing. Only for constant lengths below 64k we will
4316 generate inline code. */
4317 if (s390_tune
>= PROCESSOR_2097_Z10
4318 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4321 /* As the result of CMPINT is inverted compared to what we need,
4322 we have to swap the operands. */
4323 tmp
= op0
; op0
= op1
; op1
= tmp
;
4325 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4327 if (INTVAL (len
) > 0)
4329 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4330 emit_insn (gen_cmpint (target
, ccreg
));
4333 emit_move_insn (target
, const0_rtx
);
4335 else if (TARGET_MVCLE
)
4337 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4338 emit_insn (gen_cmpint (target
, ccreg
));
4342 rtx addr0
, addr1
, count
, blocks
, temp
;
4343 rtx_code_label
*loop_start_label
= gen_label_rtx ();
4344 rtx_code_label
*loop_end_label
= gen_label_rtx ();
4345 rtx_code_label
*end_label
= gen_label_rtx ();
4348 mode
= GET_MODE (len
);
4349 if (mode
== VOIDmode
)
4352 addr0
= gen_reg_rtx (Pmode
);
4353 addr1
= gen_reg_rtx (Pmode
);
4354 count
= gen_reg_rtx (mode
);
4355 blocks
= gen_reg_rtx (mode
);
4357 convert_move (count
, len
, 1);
4358 emit_cmp_and_jump_insns (count
, const0_rtx
,
4359 EQ
, NULL_RTX
, mode
, 1, end_label
);
4361 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4362 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4363 op0
= change_address (op0
, VOIDmode
, addr0
);
4364 op1
= change_address (op1
, VOIDmode
, addr1
);
4366 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4369 emit_move_insn (count
, temp
);
4371 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4374 emit_move_insn (blocks
, temp
);
4376 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4377 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4379 emit_label (loop_start_label
);
4382 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4386 /* Issue a read prefetch for the +2 cache line of operand 1. */
4387 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4388 const0_rtx
, const0_rtx
);
4389 emit_insn (prefetch
);
4390 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4392 /* Issue a read prefetch for the +2 cache line of operand 2. */
4393 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4394 const0_rtx
, const0_rtx
);
4395 emit_insn (prefetch
);
4396 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4399 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4400 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4401 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4402 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4403 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4404 emit_jump_insn (temp
);
4406 s390_load_address (addr0
,
4407 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4408 s390_load_address (addr1
,
4409 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4411 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4414 emit_move_insn (blocks
, temp
);
4416 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4417 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4419 emit_jump (loop_start_label
);
4420 emit_label (loop_end_label
);
4422 emit_insn (gen_cmpmem_short (op0
, op1
,
4423 convert_to_mode (Pmode
, count
, 1)));
4424 emit_label (end_label
);
4426 emit_insn (gen_cmpint (target
, ccreg
));
4432 /* Expand conditional increment or decrement using alc/slb instructions.
4433 Should generate code setting DST to either SRC or SRC + INCREMENT,
4434 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4435 Returns true if successful, false otherwise.
4437 That makes it possible to implement some if-constructs without jumps e.g.:
4438 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4439 unsigned int a, b, c;
4440 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4441 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4442 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4443 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4445 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4446 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4447 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4448 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4449 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4452 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4453 rtx dst
, rtx src
, rtx increment
)
4455 machine_mode cmp_mode
;
4456 machine_mode cc_mode
;
4462 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4463 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4465 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4466 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4471 /* Try ADD LOGICAL WITH CARRY. */
4472 if (increment
== const1_rtx
)
4474 /* Determine CC mode to use. */
4475 if (cmp_code
== EQ
|| cmp_code
== NE
)
4477 if (cmp_op1
!= const0_rtx
)
4479 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4480 NULL_RTX
, 0, OPTAB_WIDEN
);
4481 cmp_op1
= const0_rtx
;
4484 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4487 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4492 cmp_code
= swap_condition (cmp_code
);
4509 /* Emit comparison instruction pattern. */
4510 if (!register_operand (cmp_op0
, cmp_mode
))
4511 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4513 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4514 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4515 /* We use insn_invalid_p here to add clobbers if required. */
4516 ret
= insn_invalid_p (emit_insn (insn
), false);
4519 /* Emit ALC instruction pattern. */
4520 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4521 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4524 if (src
!= const0_rtx
)
4526 if (!register_operand (src
, GET_MODE (dst
)))
4527 src
= force_reg (GET_MODE (dst
), src
);
4529 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4530 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4533 p
= rtvec_alloc (2);
4535 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4537 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4543 /* Try SUBTRACT LOGICAL WITH BORROW. */
4544 if (increment
== constm1_rtx
)
4546 /* Determine CC mode to use. */
4547 if (cmp_code
== EQ
|| cmp_code
== NE
)
4549 if (cmp_op1
!= const0_rtx
)
4551 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4552 NULL_RTX
, 0, OPTAB_WIDEN
);
4553 cmp_op1
= const0_rtx
;
4556 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4559 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4564 cmp_code
= swap_condition (cmp_code
);
4581 /* Emit comparison instruction pattern. */
4582 if (!register_operand (cmp_op0
, cmp_mode
))
4583 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4585 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4586 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4587 /* We use insn_invalid_p here to add clobbers if required. */
4588 ret
= insn_invalid_p (emit_insn (insn
), false);
4591 /* Emit SLB instruction pattern. */
4592 if (!register_operand (src
, GET_MODE (dst
)))
4593 src
= force_reg (GET_MODE (dst
), src
);
4595 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4596 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4597 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4598 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4600 p
= rtvec_alloc (2);
4602 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4604 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4605 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4613 /* Expand code for the insv template. Return true if successful. */
4616 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4618 int bitsize
= INTVAL (op1
);
4619 int bitpos
= INTVAL (op2
);
4620 machine_mode mode
= GET_MODE (dest
);
4622 int smode_bsize
, mode_bsize
;
4625 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
4628 /* Generate INSERT IMMEDIATE (IILL et al). */
4629 /* (set (ze (reg)) (const_int)). */
4631 && register_operand (dest
, word_mode
)
4632 && (bitpos
% 16) == 0
4633 && (bitsize
% 16) == 0
4634 && const_int_operand (src
, VOIDmode
))
4636 HOST_WIDE_INT val
= INTVAL (src
);
4637 int regpos
= bitpos
+ bitsize
;
4639 while (regpos
> bitpos
)
4641 machine_mode putmode
;
4644 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4649 putsize
= GET_MODE_BITSIZE (putmode
);
4651 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4654 gen_int_mode (val
, putmode
));
4657 gcc_assert (regpos
== bitpos
);
4661 smode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4662 smode_bsize
= GET_MODE_BITSIZE (smode
);
4663 mode_bsize
= GET_MODE_BITSIZE (mode
);
4665 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4667 && (bitsize
% BITS_PER_UNIT
) == 0
4669 && (register_operand (src
, word_mode
)
4670 || const_int_operand (src
, VOIDmode
)))
4672 /* Emit standard pattern if possible. */
4673 if (smode_bsize
== bitsize
)
4675 emit_move_insn (adjust_address (dest
, smode
, 0),
4676 gen_lowpart (smode
, src
));
4680 /* (set (ze (mem)) (const_int)). */
4681 else if (const_int_operand (src
, VOIDmode
))
4683 int size
= bitsize
/ BITS_PER_UNIT
;
4684 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
4686 UNITS_PER_WORD
- size
);
4688 dest
= adjust_address (dest
, BLKmode
, 0);
4689 set_mem_size (dest
, size
);
4690 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4694 /* (set (ze (mem)) (reg)). */
4695 else if (register_operand (src
, word_mode
))
4698 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4702 /* Emit st,stcmh sequence. */
4703 int stcmh_width
= bitsize
- 32;
4704 int size
= stcmh_width
/ BITS_PER_UNIT
;
4706 emit_move_insn (adjust_address (dest
, SImode
, size
),
4707 gen_lowpart (SImode
, src
));
4708 set_mem_size (dest
, size
);
4709 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4710 GEN_INT (stcmh_width
),
4712 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
4718 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4719 if ((bitpos
% BITS_PER_UNIT
) == 0
4720 && (bitsize
% BITS_PER_UNIT
) == 0
4721 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
4723 && (mode
== DImode
|| mode
== SImode
)
4724 && register_operand (dest
, mode
))
4726 /* Emit a strict_low_part pattern if possible. */
4727 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
4729 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
4730 op
= gen_rtx_SET (VOIDmode
, op
, gen_lowpart (smode
, src
));
4731 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4732 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4736 /* ??? There are more powerful versions of ICM that are not
4737 completely represented in the md file. */
4740 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4741 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
4743 machine_mode mode_s
= GET_MODE (src
);
4745 if (mode_s
== VOIDmode
)
4747 /* Assume const_int etc already in the proper mode. */
4748 src
= force_reg (mode
, src
);
4750 else if (mode_s
!= mode
)
4752 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
4753 src
= force_reg (mode_s
, src
);
4754 src
= gen_lowpart (mode
, src
);
4757 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
4758 op
= gen_rtx_SET (VOIDmode
, op
, src
);
4762 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4763 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
4773 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4774 register that holds VAL of mode MODE shifted by COUNT bits. */
4777 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
4779 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4780 NULL_RTX
, 1, OPTAB_DIRECT
);
4781 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4782 NULL_RTX
, 1, OPTAB_DIRECT
);
4785 /* Structure to hold the initial parameters for a compare_and_swap operation
4786 in HImode and QImode. */
4788 struct alignment_context
4790 rtx memsi
; /* SI aligned memory location. */
4791 rtx shift
; /* Bit offset with regard to lsb. */
4792 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4793 rtx modemaski
; /* ~modemask */
4794 bool aligned
; /* True if memory is aligned, false else. */
4797 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4798 structure AC for transparent simplifying, if the memory alignment is known
4799 to be at least 32bit. MEM is the memory location for the actual operation
4800 and MODE its mode. */
4803 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4806 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4807 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4810 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4813 /* Alignment is unknown. */
4814 rtx byteoffset
, addr
, align
;
4816 /* Force the address into a register. */
4817 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4819 /* Align it to SImode. */
4820 align
= expand_simple_binop (Pmode
, AND
, addr
,
4821 GEN_INT (-GET_MODE_SIZE (SImode
)),
4822 NULL_RTX
, 1, OPTAB_DIRECT
);
4824 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4825 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4826 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4827 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4829 /* Calculate shiftcount. */
4830 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4831 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4832 NULL_RTX
, 1, OPTAB_DIRECT
);
4833 /* As we already have some offset, evaluate the remaining distance. */
4834 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4835 NULL_RTX
, 1, OPTAB_DIRECT
);
4838 /* Shift is the byte count, but we need the bitcount. */
4839 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
4840 NULL_RTX
, 1, OPTAB_DIRECT
);
4842 /* Calculate masks. */
4843 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4844 GEN_INT (GET_MODE_MASK (mode
)),
4845 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
4846 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
4850 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4851 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4852 perform the merge in SEQ2. */
4855 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
4856 machine_mode mode
, rtx val
, rtx ins
)
4863 tmp
= copy_to_mode_reg (SImode
, val
);
4864 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
4868 *seq2
= get_insns ();
4875 /* Failed to use insv. Generate a two part shift and mask. */
4877 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
4878 *seq1
= get_insns ();
4882 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
4883 *seq2
= get_insns ();
4889 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4890 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4891 value to set if CMP == MEM. */
4894 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
4895 rtx cmp
, rtx new_rtx
, bool is_weak
)
4897 struct alignment_context ac
;
4898 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
4899 rtx res
= gen_reg_rtx (SImode
);
4900 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
4902 gcc_assert (MEM_P (mem
));
4904 init_alignment_context (&ac
, mem
, mode
);
4906 /* Load full word. Subsequent loads are performed by CS. */
4907 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4908 NULL_RTX
, 1, OPTAB_DIRECT
);
4910 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4911 possible, we try to use insv to make this happen efficiently. If
4912 that fails we'll generate code both inside and outside the loop. */
4913 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
4914 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
4921 /* Start CS loop. */
4924 /* Begin assuming success. */
4925 emit_move_insn (btarget
, const1_rtx
);
4927 csloop
= gen_label_rtx ();
4928 csend
= gen_label_rtx ();
4929 emit_label (csloop
);
4932 /* val = "<mem>00..0<mem>"
4933 * cmp = "00..0<cmp>00..0"
4934 * new = "00..0<new>00..0"
4940 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
);
4942 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
4947 /* Jump to end if we're done (likely?). */
4948 s390_emit_jump (csend
, cc
);
4950 /* Check for changes outside mode, and loop internal if so.
4951 Arrange the moves so that the compare is adjacent to the
4952 branch so that we can generate CRJ. */
4953 tmp
= copy_to_reg (val
);
4954 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
4956 cc
= s390_emit_compare (NE
, val
, tmp
);
4957 s390_emit_jump (csloop
, cc
);
4960 emit_move_insn (btarget
, const0_rtx
);
4964 /* Return the correct part of the bitfield. */
4965 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4966 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4969 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4970 and VAL the value to play with. If AFTER is true then store the value
4971 MEM holds after the operation, if AFTER is false then store the value MEM
4972 holds before the operation. If TARGET is zero then discard that value, else
4973 store it to TARGET. */
4976 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
4977 rtx target
, rtx mem
, rtx val
, bool after
)
4979 struct alignment_context ac
;
4981 rtx new_rtx
= gen_reg_rtx (SImode
);
4982 rtx orig
= gen_reg_rtx (SImode
);
4983 rtx_code_label
*csloop
= gen_label_rtx ();
4985 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4986 gcc_assert (MEM_P (mem
));
4988 init_alignment_context (&ac
, mem
, mode
);
4990 /* Shift val to the correct bit positions.
4991 Preserve "icm", but prevent "ex icm". */
4992 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4993 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4995 /* Further preparation insns. */
4996 if (code
== PLUS
|| code
== MINUS
)
4997 emit_move_insn (orig
, val
);
4998 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4999 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
5000 NULL_RTX
, 1, OPTAB_DIRECT
);
5002 /* Load full word. Subsequent loads are performed by CS. */
5003 cmp
= force_reg (SImode
, ac
.memsi
);
5005 /* Start CS loop. */
5006 emit_label (csloop
);
5007 emit_move_insn (new_rtx
, cmp
);
5009 /* Patch new with val at correct position. */
5014 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
5015 NULL_RTX
, 1, OPTAB_DIRECT
);
5016 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
5017 NULL_RTX
, 1, OPTAB_DIRECT
);
5020 if (ac
.aligned
&& MEM_P (val
))
5021 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
5025 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
5026 NULL_RTX
, 1, OPTAB_DIRECT
);
5027 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
5028 NULL_RTX
, 1, OPTAB_DIRECT
);
5034 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
5035 NULL_RTX
, 1, OPTAB_DIRECT
);
5037 case MULT
: /* NAND */
5038 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
5039 NULL_RTX
, 1, OPTAB_DIRECT
);
5040 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
5041 NULL_RTX
, 1, OPTAB_DIRECT
);
5047 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
5048 ac
.memsi
, cmp
, new_rtx
));
5050 /* Return the correct part of the bitfield. */
5052 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
5053 after
? new_rtx
: cmp
, ac
.shift
,
5054 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
5057 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5058 We need to emit DTP-relative relocations. */
5060 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
5063 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5068 fputs ("\t.long\t", file
);
5071 fputs ("\t.quad\t", file
);
5076 output_addr_const (file
, x
);
5077 fputs ("@DTPOFF", file
);
5080 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5081 /* Implement TARGET_MANGLE_TYPE. */
5084 s390_mangle_type (const_tree type
)
5086 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
5087 && TARGET_LONG_DOUBLE_128
)
5090 /* For all other types, use normal C++ mangling. */
5095 /* In the name of slightly smaller debug output, and to cater to
5096 general assembler lossage, recognize various UNSPEC sequences
5097 and turn them back into a direct symbol reference. */
5100 s390_delegitimize_address (rtx orig_x
)
5104 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5107 /* Extract the symbol ref from:
5108 (plus:SI (reg:SI 12 %r12)
5109 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5110 UNSPEC_GOTOFF/PLTOFF)))
5112 (plus:SI (reg:SI 12 %r12)
5113 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5114 UNSPEC_GOTOFF/PLTOFF)
5115 (const_int 4 [0x4])))) */
5116 if (GET_CODE (x
) == PLUS
5117 && REG_P (XEXP (x
, 0))
5118 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
5119 && GET_CODE (XEXP (x
, 1)) == CONST
)
5121 HOST_WIDE_INT offset
= 0;
5123 /* The const operand. */
5124 y
= XEXP (XEXP (x
, 1), 0);
5126 if (GET_CODE (y
) == PLUS
5127 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
5129 offset
= INTVAL (XEXP (y
, 1));
5133 if (GET_CODE (y
) == UNSPEC
5134 && (XINT (y
, 1) == UNSPEC_GOTOFF
5135 || XINT (y
, 1) == UNSPEC_PLTOFF
))
5136 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
5139 if (GET_CODE (x
) != MEM
)
5143 if (GET_CODE (x
) == PLUS
5144 && GET_CODE (XEXP (x
, 1)) == CONST
5145 && GET_CODE (XEXP (x
, 0)) == REG
5146 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5148 y
= XEXP (XEXP (x
, 1), 0);
5149 if (GET_CODE (y
) == UNSPEC
5150 && XINT (y
, 1) == UNSPEC_GOT
)
5151 y
= XVECEXP (y
, 0, 0);
5155 else if (GET_CODE (x
) == CONST
)
5157 /* Extract the symbol ref from:
5158 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5159 UNSPEC_PLT/GOTENT))) */
5162 if (GET_CODE (y
) == UNSPEC
5163 && (XINT (y
, 1) == UNSPEC_GOTENT
5164 || XINT (y
, 1) == UNSPEC_PLT
))
5165 y
= XVECEXP (y
, 0, 0);
5172 if (GET_MODE (orig_x
) != Pmode
)
5174 if (GET_MODE (orig_x
) == BLKmode
)
5176 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
5183 /* Output operand OP to stdio stream FILE.
5184 OP is an address (register + offset) which is not used to address data;
5185 instead the rightmost bits are interpreted as the value. */
5188 print_shift_count_operand (FILE *file
, rtx op
)
5190 HOST_WIDE_INT offset
;
5193 /* Extract base register and offset. */
5194 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5200 gcc_assert (GET_CODE (base
) == REG
);
5201 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5202 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5205 /* Offsets are constricted to twelve bits. */
5206 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5208 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5211 /* Returns -1 if the function should not be made hotpatchable. Otherwise it
5212 returns a number >= 0 that is the desired size of the hotpatch trampoline
5215 static int s390_function_num_hotpatch_trampoline_halfwords (tree decl
,
5220 if (DECL_DECLARED_INLINE_P (decl
)
5221 || DECL_ARTIFICIAL (decl
)
5222 || MAIN_NAME_P (DECL_NAME (decl
)))
5224 /* - Explicitly inlined functions cannot be hotpatched.
5225 - Artificial functions need not be hotpatched.
5226 - Making the main function hotpatchable is useless. */
5229 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
5230 if (attr
|| s390_hotpatch_trampoline_halfwords
>= 0)
5232 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl
)))
5235 warning (OPT_Wattributes
, "function %qE with the %qs attribute"
5236 " is not hotpatchable", DECL_NAME (decl
), "always_inline");
5242 get_hotpatch_attribute (attr
) : s390_hotpatch_trampoline_halfwords
;
5249 /* Hook to determine if one function can safely inline another. */
5252 s390_can_inline_p (tree caller
, tree callee
)
5254 if (s390_function_num_hotpatch_trampoline_halfwords (callee
, false) >= 0)
5257 return default_target_can_inline_p (caller
, callee
);
5260 /* Write the extra assembler code needed to declare a function properly. */
5263 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
5266 int hotpatch_trampoline_halfwords
= -1;
5270 hotpatch_trampoline_halfwords
=
5271 s390_function_num_hotpatch_trampoline_halfwords (decl
, true);
5272 if (hotpatch_trampoline_halfwords
>= 0
5273 && decl_function_context (decl
) != NULL_TREE
)
5275 warning_at (DECL_SOURCE_LOCATION (decl
), OPT_mhotpatch
,
5276 "hotpatching is not compatible with nested functions");
5277 hotpatch_trampoline_halfwords
= -1;
5281 if (hotpatch_trampoline_halfwords
> 0)
5285 /* Add a trampoline code area before the function label and initialize it
5286 with two-byte nop instructions. This area can be overwritten with code
5287 that jumps to a patched version of the function. */
5288 for (i
= 0; i
< hotpatch_trampoline_halfwords
; i
++)
5289 asm_fprintf (asm_out_file
, "\tnopr\t%%r7\n");
5290 /* Note: The function label must be aligned so that (a) the bytes of the
5291 following nop do not cross a cacheline boundary, and (b) a jump address
5292 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5293 stored directly before the label without crossing a cacheline
5294 boundary. All this is necessary to make sure the trampoline code can
5295 be changed atomically. */
5298 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
5300 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5301 atomically with a relative backwards jump to the trampoline area. */
5302 if (hotpatch_trampoline_halfwords
>= 0)
5303 asm_fprintf (asm_out_file
, "\tnop\t0\n");
5306 /* Output machine-dependent UNSPECs occurring in address constant X
5307 in assembler syntax to stdio stream FILE. Returns true if the
5308 constant X could be recognized, false otherwise. */
5311 s390_output_addr_const_extra (FILE *file
, rtx x
)
5313 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5314 switch (XINT (x
, 1))
5317 output_addr_const (file
, XVECEXP (x
, 0, 0));
5318 fprintf (file
, "@GOTENT");
5321 output_addr_const (file
, XVECEXP (x
, 0, 0));
5322 fprintf (file
, "@GOT");
5325 output_addr_const (file
, XVECEXP (x
, 0, 0));
5326 fprintf (file
, "@GOTOFF");
5329 output_addr_const (file
, XVECEXP (x
, 0, 0));
5330 fprintf (file
, "@PLT");
5333 output_addr_const (file
, XVECEXP (x
, 0, 0));
5334 fprintf (file
, "@PLTOFF");
5337 output_addr_const (file
, XVECEXP (x
, 0, 0));
5338 fprintf (file
, "@TLSGD");
5341 assemble_name (file
, get_some_local_dynamic_name ());
5342 fprintf (file
, "@TLSLDM");
5345 output_addr_const (file
, XVECEXP (x
, 0, 0));
5346 fprintf (file
, "@DTPOFF");
5349 output_addr_const (file
, XVECEXP (x
, 0, 0));
5350 fprintf (file
, "@NTPOFF");
5352 case UNSPEC_GOTNTPOFF
:
5353 output_addr_const (file
, XVECEXP (x
, 0, 0));
5354 fprintf (file
, "@GOTNTPOFF");
5356 case UNSPEC_INDNTPOFF
:
5357 output_addr_const (file
, XVECEXP (x
, 0, 0));
5358 fprintf (file
, "@INDNTPOFF");
5362 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5363 switch (XINT (x
, 1))
5365 case UNSPEC_POOL_OFFSET
:
5366 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5367 output_addr_const (file
, x
);
5373 /* Output address operand ADDR in assembler syntax to
5374 stdio stream FILE. */
5377 print_operand_address (FILE *file
, rtx addr
)
5379 struct s390_address ad
;
5381 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
5385 output_operand_lossage ("symbolic memory references are "
5386 "only supported on z10 or later");
5389 output_addr_const (file
, addr
);
5393 if (!s390_decompose_address (addr
, &ad
)
5394 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5395 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5396 output_operand_lossage ("cannot decompose address");
5399 output_addr_const (file
, ad
.disp
);
5401 fprintf (file
, "0");
5403 if (ad
.base
&& ad
.indx
)
5404 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5405 reg_names
[REGNO (ad
.base
)]);
5407 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5410 /* Output operand X in assembler syntax to stdio stream FILE.
5411 CODE specified the format flag. The following format flags
5414 'C': print opcode suffix for branch condition.
5415 'D': print opcode suffix for inverse branch condition.
5416 'E': print opcode suffix for branch on index instruction.
5417 'G': print the size of the operand in bytes.
5418 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5419 'M': print the second word of a TImode operand.
5420 'N': print the second word of a DImode operand.
5421 'O': print only the displacement of a memory reference.
5422 'R': print only the base register of a memory reference.
5423 'S': print S-type memory reference (base+displacement).
5424 'Y': print shift count operand.
5426 'b': print integer X as if it's an unsigned byte.
5427 'c': print integer X as if it's an signed byte.
5428 'e': "end" of DImode contiguous bitmask X.
5429 'f': "end" of SImode contiguous bitmask X.
5430 'h': print integer X as if it's a signed halfword.
5431 'i': print the first nonzero HImode part of X.
5432 'j': print the first HImode part unequal to -1 of X.
5433 'k': print the first nonzero SImode part of X.
5434 'm': print the first SImode part unequal to -1 of X.
5435 'o': print integer X as if it's an unsigned 32bit word.
5436 's': "start" of DImode contiguous bitmask X.
5437 't': "start" of SImode contiguous bitmask X.
5438 'x': print integer X as if it's an unsigned halfword.
5442 print_operand (FILE *file
, rtx x
, int code
)
5449 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5453 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5457 if (GET_CODE (x
) == LE
)
5458 fprintf (file
, "l");
5459 else if (GET_CODE (x
) == GT
)
5460 fprintf (file
, "h");
5462 output_operand_lossage ("invalid comparison operator "
5463 "for 'E' output modifier");
5467 if (GET_CODE (x
) == SYMBOL_REF
)
5469 fprintf (file
, "%s", ":tls_load:");
5470 output_addr_const (file
, x
);
5472 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5474 fprintf (file
, "%s", ":tls_gdcall:");
5475 output_addr_const (file
, XVECEXP (x
, 0, 0));
5477 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5479 fprintf (file
, "%s", ":tls_ldcall:");
5480 const char *name
= get_some_local_dynamic_name ();
5482 assemble_name (file
, name
);
5485 output_operand_lossage ("invalid reference for 'J' output modifier");
5489 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5494 struct s390_address ad
;
5499 output_operand_lossage ("memory reference expected for "
5500 "'O' output modifier");
5504 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5507 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5510 output_operand_lossage ("invalid address for 'O' output modifier");
5515 output_addr_const (file
, ad
.disp
);
5517 fprintf (file
, "0");
5523 struct s390_address ad
;
5528 output_operand_lossage ("memory reference expected for "
5529 "'R' output modifier");
5533 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5536 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5539 output_operand_lossage ("invalid address for 'R' output modifier");
5544 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5546 fprintf (file
, "0");
5552 struct s390_address ad
;
5557 output_operand_lossage ("memory reference expected for "
5558 "'S' output modifier");
5561 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5564 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5567 output_operand_lossage ("invalid address for 'S' output modifier");
5572 output_addr_const (file
, ad
.disp
);
5574 fprintf (file
, "0");
5577 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5582 if (GET_CODE (x
) == REG
)
5583 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5584 else if (GET_CODE (x
) == MEM
)
5585 x
= change_address (x
, VOIDmode
,
5586 plus_constant (Pmode
, XEXP (x
, 0), 4));
5588 output_operand_lossage ("register or memory expression expected "
5589 "for 'N' output modifier");
5593 if (GET_CODE (x
) == REG
)
5594 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5595 else if (GET_CODE (x
) == MEM
)
5596 x
= change_address (x
, VOIDmode
,
5597 plus_constant (Pmode
, XEXP (x
, 0), 8));
5599 output_operand_lossage ("register or memory expression expected "
5600 "for 'M' output modifier");
5604 print_shift_count_operand (file
, x
);
5608 switch (GET_CODE (x
))
5611 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5615 output_address (XEXP (x
, 0));
5622 output_addr_const (file
, x
);
5635 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
5641 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
5644 ival
= s390_extract_part (x
, HImode
, 0);
5647 ival
= s390_extract_part (x
, HImode
, -1);
5650 ival
= s390_extract_part (x
, SImode
, 0);
5653 ival
= s390_extract_part (x
, SImode
, -1);
5664 len
= (code
== 's' || code
== 'e' ? 64 : 32);
5665 ok
= s390_contiguous_bitmask_p (ival
, len
, &pos
, &len
);
5667 if (code
== 's' || code
== 't')
5668 ival
= 64 - pos
- len
;
5670 ival
= 64 - 1 - pos
;
5674 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
5676 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
5680 gcc_assert (GET_MODE (x
) == VOIDmode
);
5682 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5683 else if (code
== 'x')
5684 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5685 else if (code
== 'h')
5686 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5687 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5691 output_operand_lossage ("invalid constant - try using "
5692 "an output modifier");
5694 output_operand_lossage ("invalid constant for output modifier '%c'",
5701 output_operand_lossage ("invalid expression - try using "
5702 "an output modifier");
5704 output_operand_lossage ("invalid expression for output "
5705 "modifier '%c'", code
);
5710 /* Target hook for assembling integer objects. We need to define it
5711 here to work a round a bug in some versions of GAS, which couldn't
5712 handle values smaller than INT_MIN when printed in decimal. */
5715 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5717 if (size
== 8 && aligned_p
5718 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5720 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5724 return default_assemble_integer (x
, size
, aligned_p
);
5727 /* Returns true if register REGNO is used for forming
5728 a memory address in expression X. */
5731 reg_used_in_mem_p (int regno
, rtx x
)
5733 enum rtx_code code
= GET_CODE (x
);
5739 if (refers_to_regno_p (regno
, regno
+1,
5743 else if (code
== SET
5744 && GET_CODE (SET_DEST (x
)) == PC
)
5746 if (refers_to_regno_p (regno
, regno
+1,
5751 fmt
= GET_RTX_FORMAT (code
);
5752 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5755 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5758 else if (fmt
[i
] == 'E')
5759 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5760 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5766 /* Returns true if expression DEP_RTX sets an address register
5767 used by instruction INSN to address memory. */
5770 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
5774 if (NONJUMP_INSN_P (dep_rtx
))
5775 dep_rtx
= PATTERN (dep_rtx
);
5777 if (GET_CODE (dep_rtx
) == SET
)
5779 target
= SET_DEST (dep_rtx
);
5780 if (GET_CODE (target
) == STRICT_LOW_PART
)
5781 target
= XEXP (target
, 0);
5782 while (GET_CODE (target
) == SUBREG
)
5783 target
= SUBREG_REG (target
);
5785 if (GET_CODE (target
) == REG
)
5787 int regno
= REGNO (target
);
5789 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5791 pat
= PATTERN (insn
);
5792 if (GET_CODE (pat
) == PARALLEL
)
5794 gcc_assert (XVECLEN (pat
, 0) == 2);
5795 pat
= XVECEXP (pat
, 0, 0);
5797 gcc_assert (GET_CODE (pat
) == SET
);
5798 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5800 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5801 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5807 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5810 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
5812 rtx dep_rtx
= PATTERN (dep_insn
);
5815 if (GET_CODE (dep_rtx
) == SET
5816 && addr_generation_dependency_p (dep_rtx
, insn
))
5818 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5820 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5822 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5830 /* A C statement (sans semicolon) to update the integer scheduling priority
5831 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5832 reduce the priority to execute INSN later. Do not define this macro if
5833 you do not need to adjust the scheduling priorities of insns.
5835 A STD instruction should be scheduled earlier,
5836 in order to use the bypass. */
5838 s390_adjust_priority (rtx_insn
*insn
, int priority
)
5840 if (! INSN_P (insn
))
5843 if (s390_tune
!= PROCESSOR_2084_Z990
5844 && s390_tune
!= PROCESSOR_2094_Z9_109
5845 && s390_tune
!= PROCESSOR_2097_Z10
5846 && s390_tune
!= PROCESSOR_2817_Z196
5847 && s390_tune
!= PROCESSOR_2827_ZEC12
)
5850 switch (s390_safe_attr_type (insn
))
5854 priority
= priority
<< 3;
5858 priority
= priority
<< 1;
5867 /* The number of instructions that can be issued per cycle. */
5870 s390_issue_rate (void)
5874 case PROCESSOR_2084_Z990
:
5875 case PROCESSOR_2094_Z9_109
:
5876 case PROCESSOR_2817_Z196
:
5878 case PROCESSOR_2097_Z10
:
5879 case PROCESSOR_2827_ZEC12
:
5887 s390_first_cycle_multipass_dfa_lookahead (void)
5892 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5893 Fix up MEMs as required. */
5896 annotate_constant_pool_refs (rtx
*x
)
5901 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5902 || !CONSTANT_POOL_ADDRESS_P (*x
));
5904 /* Literal pool references can only occur inside a MEM ... */
5905 if (GET_CODE (*x
) == MEM
)
5907 rtx memref
= XEXP (*x
, 0);
5909 if (GET_CODE (memref
) == SYMBOL_REF
5910 && CONSTANT_POOL_ADDRESS_P (memref
))
5912 rtx base
= cfun
->machine
->base_reg
;
5913 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5916 *x
= replace_equiv_address (*x
, addr
);
5920 if (GET_CODE (memref
) == CONST
5921 && GET_CODE (XEXP (memref
, 0)) == PLUS
5922 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5923 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5924 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5926 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5927 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5928 rtx base
= cfun
->machine
->base_reg
;
5929 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5932 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
5937 /* ... or a load-address type pattern. */
5938 if (GET_CODE (*x
) == SET
)
5940 rtx addrref
= SET_SRC (*x
);
5942 if (GET_CODE (addrref
) == SYMBOL_REF
5943 && CONSTANT_POOL_ADDRESS_P (addrref
))
5945 rtx base
= cfun
->machine
->base_reg
;
5946 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5949 SET_SRC (*x
) = addr
;
5953 if (GET_CODE (addrref
) == CONST
5954 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5955 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5956 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5957 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5959 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5960 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5961 rtx base
= cfun
->machine
->base_reg
;
5962 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5965 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
5970 /* Annotate LTREL_BASE as well. */
5971 if (GET_CODE (*x
) == UNSPEC
5972 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5974 rtx base
= cfun
->machine
->base_reg
;
5975 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5980 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5981 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5985 annotate_constant_pool_refs (&XEXP (*x
, i
));
5987 else if (fmt
[i
] == 'E')
5989 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5990 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5995 /* Split all branches that exceed the maximum distance.
5996 Returns true if this created a new literal pool entry. */
5999 s390_split_branches (void)
6001 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
6002 int new_literal
= 0, ret
;
6007 /* We need correct insn addresses. */
6009 shorten_branches (get_insns ());
6011 /* Find all branches that exceed 64KB, and split them. */
6013 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6015 if (! JUMP_P (insn
) || tablejump_p (insn
, NULL
, NULL
))
6018 pat
= PATTERN (insn
);
6019 if (GET_CODE (pat
) == PARALLEL
)
6020 pat
= XVECEXP (pat
, 0, 0);
6021 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
6024 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
6026 label
= &SET_SRC (pat
);
6028 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
6030 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
6031 label
= &XEXP (SET_SRC (pat
), 1);
6032 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
6033 label
= &XEXP (SET_SRC (pat
), 2);
6040 if (get_attr_length (insn
) <= 4)
6043 /* We are going to use the return register as scratch register,
6044 make sure it will be saved/restored by the prologue/epilogue. */
6045 cfun_frame_layout
.save_return_addr_p
= 1;
6050 rtx mem
= force_const_mem (Pmode
, *label
);
6051 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, mem
), insn
);
6052 INSN_ADDRESSES_NEW (set_insn
, -1);
6053 annotate_constant_pool_refs (&PATTERN (set_insn
));
6060 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
6061 UNSPEC_LTREL_OFFSET
);
6062 target
= gen_rtx_CONST (Pmode
, target
);
6063 target
= force_const_mem (Pmode
, target
);
6064 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
6065 INSN_ADDRESSES_NEW (set_insn
, -1);
6066 annotate_constant_pool_refs (&PATTERN (set_insn
));
6068 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
6069 cfun
->machine
->base_reg
),
6071 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
6074 ret
= validate_change (insn
, label
, target
, 0);
6082 /* Find an annotated literal pool symbol referenced in RTX X,
6083 and store it at REF. Will abort if X contains references to
6084 more than one such pool symbol; multiple references to the same
6085 symbol are allowed, however.
6087 The rtx pointed to by REF must be initialized to NULL_RTX
6088 by the caller before calling this routine. */
6091 find_constant_pool_ref (rtx x
, rtx
*ref
)
6096 /* Ignore LTREL_BASE references. */
6097 if (GET_CODE (x
) == UNSPEC
6098 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6100 /* Likewise POOL_ENTRY insns. */
6101 if (GET_CODE (x
) == UNSPEC_VOLATILE
6102 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
6105 gcc_assert (GET_CODE (x
) != SYMBOL_REF
6106 || !CONSTANT_POOL_ADDRESS_P (x
));
6108 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
6110 rtx sym
= XVECEXP (x
, 0, 0);
6111 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
6112 && CONSTANT_POOL_ADDRESS_P (sym
));
6114 if (*ref
== NULL_RTX
)
6117 gcc_assert (*ref
== sym
);
6122 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6123 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6127 find_constant_pool_ref (XEXP (x
, i
), ref
);
6129 else if (fmt
[i
] == 'E')
6131 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6132 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
6137 /* Replace every reference to the annotated literal pool
6138 symbol REF in X by its base plus OFFSET. */
6141 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
6146 gcc_assert (*x
!= ref
);
6148 if (GET_CODE (*x
) == UNSPEC
6149 && XINT (*x
, 1) == UNSPEC_LTREF
6150 && XVECEXP (*x
, 0, 0) == ref
)
6152 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
6156 if (GET_CODE (*x
) == PLUS
6157 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
6158 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
6159 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
6160 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
6162 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
6163 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
6167 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6168 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6172 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
6174 else if (fmt
[i
] == 'E')
6176 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6177 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
6182 /* Check whether X contains an UNSPEC_LTREL_BASE.
6183 Return its constant pool symbol if found, NULL_RTX otherwise. */
6186 find_ltrel_base (rtx x
)
6191 if (GET_CODE (x
) == UNSPEC
6192 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6193 return XVECEXP (x
, 0, 0);
6195 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6196 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6200 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
6204 else if (fmt
[i
] == 'E')
6206 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6208 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
6218 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6221 replace_ltrel_base (rtx
*x
)
6226 if (GET_CODE (*x
) == UNSPEC
6227 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
6229 *x
= XVECEXP (*x
, 0, 1);
6233 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6234 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6238 replace_ltrel_base (&XEXP (*x
, i
));
6240 else if (fmt
[i
] == 'E')
6242 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6243 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
6249 /* We keep a list of constants which we have to add to internal
6250 constant tables in the middle of large functions. */
6252 #define NR_C_MODES 11
6253 machine_mode constant_modes
[NR_C_MODES
] =
6255 TFmode
, TImode
, TDmode
,
6256 DFmode
, DImode
, DDmode
,
6257 SFmode
, SImode
, SDmode
,
6264 struct constant
*next
;
6266 rtx_code_label
*label
;
6269 struct constant_pool
6271 struct constant_pool
*next
;
6272 rtx_insn
*first_insn
;
6273 rtx_insn
*pool_insn
;
6275 rtx_insn
*emit_pool_after
;
6277 struct constant
*constants
[NR_C_MODES
];
6278 struct constant
*execute
;
6279 rtx_code_label
*label
;
6283 /* Allocate new constant_pool structure. */
6285 static struct constant_pool
*
6286 s390_alloc_pool (void)
6288 struct constant_pool
*pool
;
6291 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6293 for (i
= 0; i
< NR_C_MODES
; i
++)
6294 pool
->constants
[i
] = NULL
;
6296 pool
->execute
= NULL
;
6297 pool
->label
= gen_label_rtx ();
6298 pool
->first_insn
= NULL
;
6299 pool
->pool_insn
= NULL
;
6300 pool
->insns
= BITMAP_ALLOC (NULL
);
6302 pool
->emit_pool_after
= NULL
;
6307 /* Create new constant pool covering instructions starting at INSN
6308 and chain it to the end of POOL_LIST. */
6310 static struct constant_pool
*
6311 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
6313 struct constant_pool
*pool
, **prev
;
6315 pool
= s390_alloc_pool ();
6316 pool
->first_insn
= insn
;
6318 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6325 /* End range of instructions covered by POOL at INSN and emit
6326 placeholder insn representing the pool. */
6329 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
6331 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6334 insn
= get_last_insn ();
6336 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6337 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6340 /* Add INSN to the list of insns covered by POOL. */
6343 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6345 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6348 /* Return pool out of POOL_LIST that covers INSN. */
6350 static struct constant_pool
*
6351 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6353 struct constant_pool
*pool
;
6355 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6356 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6362 /* Add constant VAL of mode MODE to the constant pool POOL. */
6365 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
6370 for (i
= 0; i
< NR_C_MODES
; i
++)
6371 if (constant_modes
[i
] == mode
)
6373 gcc_assert (i
!= NR_C_MODES
);
6375 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6376 if (rtx_equal_p (val
, c
->value
))
6381 c
= (struct constant
*) xmalloc (sizeof *c
);
6383 c
->label
= gen_label_rtx ();
6384 c
->next
= pool
->constants
[i
];
6385 pool
->constants
[i
] = c
;
6386 pool
->size
+= GET_MODE_SIZE (mode
);
6390 /* Return an rtx that represents the offset of X from the start of
6394 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6398 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6399 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6400 UNSPEC_POOL_OFFSET
);
6401 return gen_rtx_CONST (GET_MODE (x
), x
);
6404 /* Find constant VAL of mode MODE in the constant pool POOL.
6405 Return an RTX describing the distance from the start of
6406 the pool to the location of the new constant. */
6409 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6415 for (i
= 0; i
< NR_C_MODES
; i
++)
6416 if (constant_modes
[i
] == mode
)
6418 gcc_assert (i
!= NR_C_MODES
);
6420 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6421 if (rtx_equal_p (val
, c
->value
))
6426 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6429 /* Check whether INSN is an execute. Return the label_ref to its
6430 execute target template if so, NULL_RTX otherwise. */
6433 s390_execute_label (rtx insn
)
6435 if (NONJUMP_INSN_P (insn
)
6436 && GET_CODE (PATTERN (insn
)) == PARALLEL
6437 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6438 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6439 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6444 /* Add execute target for INSN to the constant pool POOL. */
6447 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6451 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6452 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6457 c
= (struct constant
*) xmalloc (sizeof *c
);
6459 c
->label
= gen_label_rtx ();
6460 c
->next
= pool
->execute
;
6466 /* Find execute target for INSN in the constant pool POOL.
6467 Return an RTX describing the distance from the start of
6468 the pool to the location of the execute target. */
6471 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6475 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6476 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6481 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6484 /* For an execute INSN, extract the execute target template. */
6487 s390_execute_target (rtx insn
)
6489 rtx pattern
= PATTERN (insn
);
6490 gcc_assert (s390_execute_label (insn
));
6492 if (XVECLEN (pattern
, 0) == 2)
6494 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6498 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6501 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6502 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6504 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6510 /* Indicate that INSN cannot be duplicated. This is the case for
6511 execute insns that carry a unique label. */
6514 s390_cannot_copy_insn_p (rtx_insn
*insn
)
6516 rtx label
= s390_execute_label (insn
);
6517 return label
&& label
!= const0_rtx
;
6520 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6521 do not emit the pool base label. */
6524 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6527 rtx_insn
*insn
= pool
->pool_insn
;
6530 /* Switch to rodata section. */
6531 if (TARGET_CPU_ZARCH
)
6533 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6534 INSN_ADDRESSES_NEW (insn
, -1);
6537 /* Ensure minimum pool alignment. */
6538 if (TARGET_CPU_ZARCH
)
6539 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6541 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6542 INSN_ADDRESSES_NEW (insn
, -1);
6544 /* Emit pool base label. */
6547 insn
= emit_label_after (pool
->label
, insn
);
6548 INSN_ADDRESSES_NEW (insn
, -1);
6551 /* Dump constants in descending alignment requirement order,
6552 ensuring proper alignment for every constant. */
6553 for (i
= 0; i
< NR_C_MODES
; i
++)
6554 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6556 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6557 rtx value
= copy_rtx (c
->value
);
6558 if (GET_CODE (value
) == CONST
6559 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6560 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6561 && XVECLEN (XEXP (value
, 0), 0) == 1)
6562 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6564 insn
= emit_label_after (c
->label
, insn
);
6565 INSN_ADDRESSES_NEW (insn
, -1);
6567 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6568 gen_rtvec (1, value
),
6569 UNSPECV_POOL_ENTRY
);
6570 insn
= emit_insn_after (value
, insn
);
6571 INSN_ADDRESSES_NEW (insn
, -1);
6574 /* Ensure minimum alignment for instructions. */
6575 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6576 INSN_ADDRESSES_NEW (insn
, -1);
6578 /* Output in-pool execute template insns. */
6579 for (c
= pool
->execute
; c
; c
= c
->next
)
6581 insn
= emit_label_after (c
->label
, insn
);
6582 INSN_ADDRESSES_NEW (insn
, -1);
6584 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6585 INSN_ADDRESSES_NEW (insn
, -1);
6588 /* Switch back to previous section. */
6589 if (TARGET_CPU_ZARCH
)
6591 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6592 INSN_ADDRESSES_NEW (insn
, -1);
6595 insn
= emit_barrier_after (insn
);
6596 INSN_ADDRESSES_NEW (insn
, -1);
6598 /* Remove placeholder insn. */
6599 remove_insn (pool
->pool_insn
);
6602 /* Free all memory used by POOL. */
6605 s390_free_pool (struct constant_pool
*pool
)
6607 struct constant
*c
, *next
;
6610 for (i
= 0; i
< NR_C_MODES
; i
++)
6611 for (c
= pool
->constants
[i
]; c
; c
= next
)
6617 for (c
= pool
->execute
; c
; c
= next
)
6623 BITMAP_FREE (pool
->insns
);
6628 /* Collect main literal pool. Return NULL on overflow. */
6630 static struct constant_pool
*
6631 s390_mainpool_start (void)
6633 struct constant_pool
*pool
;
6636 pool
= s390_alloc_pool ();
6638 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6640 if (NONJUMP_INSN_P (insn
)
6641 && GET_CODE (PATTERN (insn
)) == SET
6642 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6643 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6645 /* There might be two main_pool instructions if base_reg
6646 is call-clobbered; one for shrink-wrapped code and one
6647 for the rest. We want to keep the first. */
6648 if (pool
->pool_insn
)
6650 insn
= PREV_INSN (insn
);
6651 delete_insn (NEXT_INSN (insn
));
6654 pool
->pool_insn
= insn
;
6657 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6659 s390_add_execute (pool
, insn
);
6661 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6663 rtx pool_ref
= NULL_RTX
;
6664 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6667 rtx constant
= get_pool_constant (pool_ref
);
6668 machine_mode mode
= get_pool_mode (pool_ref
);
6669 s390_add_constant (pool
, constant
, mode
);
6673 /* If hot/cold partitioning is enabled we have to make sure that
6674 the literal pool is emitted in the same section where the
6675 initialization of the literal pool base pointer takes place.
6676 emit_pool_after is only used in the non-overflow case on non
6677 Z cpus where we can emit the literal pool at the end of the
6678 function body within the text section. */
6680 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6681 && !pool
->emit_pool_after
)
6682 pool
->emit_pool_after
= PREV_INSN (insn
);
6685 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6687 if (pool
->size
>= 4096)
6689 /* We're going to chunkify the pool, so remove the main
6690 pool placeholder insn. */
6691 remove_insn (pool
->pool_insn
);
6693 s390_free_pool (pool
);
6697 /* If the functions ends with the section where the literal pool
6698 should be emitted set the marker to its end. */
6699 if (pool
&& !pool
->emit_pool_after
)
6700 pool
->emit_pool_after
= get_last_insn ();
6705 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6706 Modify the current function to output the pool constants as well as
6707 the pool register setup instruction. */
6710 s390_mainpool_finish (struct constant_pool
*pool
)
6712 rtx base_reg
= cfun
->machine
->base_reg
;
6714 /* If the pool is empty, we're done. */
6715 if (pool
->size
== 0)
6717 /* We don't actually need a base register after all. */
6718 cfun
->machine
->base_reg
= NULL_RTX
;
6720 if (pool
->pool_insn
)
6721 remove_insn (pool
->pool_insn
);
6722 s390_free_pool (pool
);
6726 /* We need correct insn addresses. */
6727 shorten_branches (get_insns ());
6729 /* On zSeries, we use a LARL to load the pool register. The pool is
6730 located in the .rodata section, so we emit it after the function. */
6731 if (TARGET_CPU_ZARCH
)
6733 rtx set
= gen_main_base_64 (base_reg
, pool
->label
);
6734 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
6735 INSN_ADDRESSES_NEW (insn
, -1);
6736 remove_insn (pool
->pool_insn
);
6738 insn
= get_last_insn ();
6739 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6740 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6742 s390_dump_pool (pool
, 0);
6745 /* On S/390, if the total size of the function's code plus literal pool
6746 does not exceed 4096 bytes, we use BASR to set up a function base
6747 pointer, and emit the literal pool at the end of the function. */
6748 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6749 + pool
->size
+ 8 /* alignment slop */ < 4096)
6751 rtx set
= gen_main_base_31_small (base_reg
, pool
->label
);
6752 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
6753 INSN_ADDRESSES_NEW (insn
, -1);
6754 remove_insn (pool
->pool_insn
);
6756 insn
= emit_label_after (pool
->label
, insn
);
6757 INSN_ADDRESSES_NEW (insn
, -1);
6759 /* emit_pool_after will be set by s390_mainpool_start to the
6760 last insn of the section where the literal pool should be
6762 insn
= pool
->emit_pool_after
;
6764 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6765 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6767 s390_dump_pool (pool
, 1);
6770 /* Otherwise, we emit an inline literal pool and use BASR to branch
6771 over it, setting up the pool register at the same time. */
6774 rtx_code_label
*pool_end
= gen_label_rtx ();
6776 rtx pat
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6777 rtx_insn
*insn
= emit_jump_insn_after (pat
, pool
->pool_insn
);
6778 JUMP_LABEL (insn
) = pool_end
;
6779 INSN_ADDRESSES_NEW (insn
, -1);
6780 remove_insn (pool
->pool_insn
);
6782 insn
= emit_label_after (pool
->label
, insn
);
6783 INSN_ADDRESSES_NEW (insn
, -1);
6785 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6786 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6788 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6789 INSN_ADDRESSES_NEW (insn
, -1);
6791 s390_dump_pool (pool
, 1);
6795 /* Replace all literal pool references. */
6797 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6800 replace_ltrel_base (&PATTERN (insn
));
6802 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6804 rtx addr
, pool_ref
= NULL_RTX
;
6805 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6808 if (s390_execute_label (insn
))
6809 addr
= s390_find_execute (pool
, insn
);
6811 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6812 get_pool_mode (pool_ref
));
6814 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6815 INSN_CODE (insn
) = -1;
6821 /* Free the pool. */
6822 s390_free_pool (pool
);
6825 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6826 We have decided we cannot use this pool, so revert all changes
6827 to the current function that were done by s390_mainpool_start. */
6829 s390_mainpool_cancel (struct constant_pool
*pool
)
6831 /* We didn't actually change the instruction stream, so simply
6832 free the pool memory. */
6833 s390_free_pool (pool
);
6837 /* Chunkify the literal pool. */
6839 #define S390_POOL_CHUNK_MIN 0xc00
6840 #define S390_POOL_CHUNK_MAX 0xe00
6842 static struct constant_pool
*
6843 s390_chunkify_start (void)
6845 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6848 rtx pending_ltrel
= NULL_RTX
;
6851 rtx (*gen_reload_base
) (rtx
, rtx
) =
6852 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6855 /* We need correct insn addresses. */
6857 shorten_branches (get_insns ());
6859 /* Scan all insns and move literals to pool chunks. */
6861 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6863 bool section_switch_p
= false;
6865 /* Check for pending LTREL_BASE. */
6868 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6871 gcc_assert (ltrel_base
== pending_ltrel
);
6872 pending_ltrel
= NULL_RTX
;
6876 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6879 curr_pool
= s390_start_pool (&pool_list
, insn
);
6881 s390_add_execute (curr_pool
, insn
);
6882 s390_add_pool_insn (curr_pool
, insn
);
6884 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
6886 rtx pool_ref
= NULL_RTX
;
6887 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6890 rtx constant
= get_pool_constant (pool_ref
);
6891 machine_mode mode
= get_pool_mode (pool_ref
);
6894 curr_pool
= s390_start_pool (&pool_list
, insn
);
6896 s390_add_constant (curr_pool
, constant
, mode
);
6897 s390_add_pool_insn (curr_pool
, insn
);
6899 /* Don't split the pool chunk between a LTREL_OFFSET load
6900 and the corresponding LTREL_BASE. */
6901 if (GET_CODE (constant
) == CONST
6902 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6903 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6905 gcc_assert (!pending_ltrel
);
6906 pending_ltrel
= pool_ref
;
6911 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
6914 s390_add_pool_insn (curr_pool
, insn
);
6915 /* An LTREL_BASE must follow within the same basic block. */
6916 gcc_assert (!pending_ltrel
);
6920 switch (NOTE_KIND (insn
))
6922 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
6923 section_switch_p
= true;
6925 case NOTE_INSN_VAR_LOCATION
:
6926 case NOTE_INSN_CALL_ARG_LOCATION
:
6933 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6934 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6937 if (TARGET_CPU_ZARCH
)
6939 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6942 s390_end_pool (curr_pool
, NULL
);
6947 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6948 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6951 /* We will later have to insert base register reload insns.
6952 Those will have an effect on code size, which we need to
6953 consider here. This calculation makes rather pessimistic
6954 worst-case assumptions. */
6958 if (chunk_size
< S390_POOL_CHUNK_MIN
6959 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6960 && !section_switch_p
)
6963 /* Pool chunks can only be inserted after BARRIERs ... */
6964 if (BARRIER_P (insn
))
6966 s390_end_pool (curr_pool
, insn
);
6971 /* ... so if we don't find one in time, create one. */
6972 else if (chunk_size
> S390_POOL_CHUNK_MAX
6973 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6974 || section_switch_p
)
6976 rtx_insn
*label
, *jump
, *barrier
, *next
, *prev
;
6978 if (!section_switch_p
)
6980 /* We can insert the barrier only after a 'real' insn. */
6981 if (! NONJUMP_INSN_P (insn
) && ! CALL_P (insn
))
6983 if (get_attr_length (insn
) == 0)
6985 /* Don't separate LTREL_BASE from the corresponding
6986 LTREL_OFFSET load. */
6993 next
= NEXT_INSN (insn
);
6997 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
6998 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
7002 gcc_assert (!pending_ltrel
);
7004 /* The old pool has to end before the section switch
7005 note in order to make it part of the current
7007 insn
= PREV_INSN (insn
);
7010 label
= gen_label_rtx ();
7012 if (prev
&& NOTE_P (prev
))
7013 prev
= prev_nonnote_insn (prev
);
7015 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
7016 INSN_LOCATION (prev
));
7018 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
7019 barrier
= emit_barrier_after (jump
);
7020 insn
= emit_label_after (label
, barrier
);
7021 JUMP_LABEL (jump
) = label
;
7022 LABEL_NUSES (label
) = 1;
7024 INSN_ADDRESSES_NEW (jump
, -1);
7025 INSN_ADDRESSES_NEW (barrier
, -1);
7026 INSN_ADDRESSES_NEW (insn
, -1);
7028 s390_end_pool (curr_pool
, barrier
);
7036 s390_end_pool (curr_pool
, NULL
);
7037 gcc_assert (!pending_ltrel
);
7039 /* Find all labels that are branched into
7040 from an insn belonging to a different chunk. */
7042 far_labels
= BITMAP_ALLOC (NULL
);
7044 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7046 rtx_jump_table_data
*table
;
7048 /* Labels marked with LABEL_PRESERVE_P can be target
7049 of non-local jumps, so we have to mark them.
7050 The same holds for named labels.
7052 Don't do that, however, if it is the label before
7056 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
7058 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
7059 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
7060 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
7062 /* Check potential targets in a table jump (casesi_jump). */
7063 else if (tablejump_p (insn
, NULL
, &table
))
7065 rtx vec_pat
= PATTERN (table
);
7066 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
7068 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
7070 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
7072 if (s390_find_pool (pool_list
, label
)
7073 != s390_find_pool (pool_list
, insn
))
7074 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
7077 /* If we have a direct jump (conditional or unconditional),
7078 check all potential targets. */
7079 else if (JUMP_P (insn
))
7081 rtx pat
= PATTERN (insn
);
7083 if (GET_CODE (pat
) == PARALLEL
)
7084 pat
= XVECEXP (pat
, 0, 0);
7086 if (GET_CODE (pat
) == SET
)
7088 rtx label
= JUMP_LABEL (insn
);
7089 if (label
&& !ANY_RETURN_P (label
))
7091 if (s390_find_pool (pool_list
, label
)
7092 != s390_find_pool (pool_list
, insn
))
7093 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
7099 /* Insert base register reload insns before every pool. */
7101 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7103 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7105 rtx_insn
*insn
= curr_pool
->first_insn
;
7106 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
7109 /* Insert base register reload insns at every far label. */
7111 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7113 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
7115 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
7118 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7120 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
7125 BITMAP_FREE (far_labels
);
7128 /* Recompute insn addresses. */
7130 init_insn_lengths ();
7131 shorten_branches (get_insns ());
7136 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7137 After we have decided to use this list, finish implementing
7138 all changes to the current function as required. */
7141 s390_chunkify_finish (struct constant_pool
*pool_list
)
7143 struct constant_pool
*curr_pool
= NULL
;
7147 /* Replace all literal pool references. */
7149 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7152 replace_ltrel_base (&PATTERN (insn
));
7154 curr_pool
= s390_find_pool (pool_list
, insn
);
7158 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
7160 rtx addr
, pool_ref
= NULL_RTX
;
7161 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
7164 if (s390_execute_label (insn
))
7165 addr
= s390_find_execute (curr_pool
, insn
);
7167 addr
= s390_find_constant (curr_pool
,
7168 get_pool_constant (pool_ref
),
7169 get_pool_mode (pool_ref
));
7171 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
7172 INSN_CODE (insn
) = -1;
7177 /* Dump out all literal pools. */
7179 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7180 s390_dump_pool (curr_pool
, 0);
7182 /* Free pool list. */
7186 struct constant_pool
*next
= pool_list
->next
;
7187 s390_free_pool (pool_list
);
7192 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7193 We have decided we cannot use this list, so revert all changes
7194 to the current function that were done by s390_chunkify_start. */
7197 s390_chunkify_cancel (struct constant_pool
*pool_list
)
7199 struct constant_pool
*curr_pool
= NULL
;
7202 /* Remove all pool placeholder insns. */
7204 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7206 /* Did we insert an extra barrier? Remove it. */
7207 rtx_insn
*barrier
= PREV_INSN (curr_pool
->pool_insn
);
7208 rtx_insn
*jump
= barrier
? PREV_INSN (barrier
) : NULL
;
7209 rtx_insn
*label
= NEXT_INSN (curr_pool
->pool_insn
);
7211 if (jump
&& JUMP_P (jump
)
7212 && barrier
&& BARRIER_P (barrier
)
7213 && label
&& LABEL_P (label
)
7214 && GET_CODE (PATTERN (jump
)) == SET
7215 && SET_DEST (PATTERN (jump
)) == pc_rtx
7216 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
7217 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
7220 remove_insn (barrier
);
7221 remove_insn (label
);
7224 remove_insn (curr_pool
->pool_insn
);
7227 /* Remove all base register reload insns. */
7229 for (insn
= get_insns (); insn
; )
7231 rtx_insn
*next_insn
= NEXT_INSN (insn
);
7233 if (NONJUMP_INSN_P (insn
)
7234 && GET_CODE (PATTERN (insn
)) == SET
7235 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
7236 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
7242 /* Free pool list. */
7246 struct constant_pool
*next
= pool_list
->next
;
7247 s390_free_pool (pool_list
);
7252 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7255 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
7259 switch (GET_MODE_CLASS (mode
))
7262 case MODE_DECIMAL_FLOAT
:
7263 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
7265 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
7266 assemble_real (r
, mode
, align
);
7270 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
7271 mark_symbol_refs_as_used (exp
);
7280 /* Return an RTL expression representing the value of the return address
7281 for the frame COUNT steps up from the current frame. FRAME is the
7282 frame pointer of that frame. */
7285 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7290 /* Without backchain, we fail for all but the current frame. */
7292 if (!TARGET_BACKCHAIN
&& count
> 0)
7295 /* For the current frame, we need to make sure the initial
7296 value of RETURN_REGNUM is actually saved. */
7300 /* On non-z architectures branch splitting could overwrite r14. */
7301 if (TARGET_CPU_ZARCH
)
7302 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7305 cfun_frame_layout
.save_return_addr_p
= true;
7306 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7310 if (TARGET_PACKED_STACK
)
7311 offset
= -2 * UNITS_PER_LONG
;
7313 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7315 addr
= plus_constant (Pmode
, frame
, offset
);
7316 addr
= memory_address (Pmode
, addr
);
7317 return gen_rtx_MEM (Pmode
, addr
);
7320 /* Return an RTL expression representing the back chain stored in
7321 the current stack frame. */
7324 s390_back_chain_rtx (void)
7328 gcc_assert (TARGET_BACKCHAIN
);
7330 if (TARGET_PACKED_STACK
)
7331 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
7332 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7334 chain
= stack_pointer_rtx
;
7336 chain
= gen_rtx_MEM (Pmode
, chain
);
7340 /* Find first call clobbered register unused in a function.
7341 This could be used as base register in a leaf function
7342 or for holding the return address before epilogue. */
7345 find_unused_clobbered_reg (void)
7348 for (i
= 0; i
< 6; i
++)
7349 if (!df_regs_ever_live_p (i
))
7355 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7356 clobbered hard regs in SETREG. */
7359 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7361 char *regs_ever_clobbered
= (char *)data
;
7362 unsigned int i
, regno
;
7363 machine_mode mode
= GET_MODE (setreg
);
7365 if (GET_CODE (setreg
) == SUBREG
)
7367 rtx inner
= SUBREG_REG (setreg
);
7368 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
7370 regno
= subreg_regno (setreg
);
7372 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
7373 regno
= REGNO (setreg
);
7378 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7380 regs_ever_clobbered
[i
] = 1;
7383 /* Walks through all basic blocks of the current function looking
7384 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7385 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7386 each of those regs. */
7389 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
7395 memset (regs_ever_clobbered
, 0, 32);
7397 /* For non-leaf functions we have to consider all call clobbered regs to be
7401 for (i
= 0; i
< 32; i
++)
7402 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7405 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7406 this work is done by liveness analysis (mark_regs_live_at_end).
7407 Special care is needed for functions containing landing pads. Landing pads
7408 may use the eh registers, but the code which sets these registers is not
7409 contained in that function. Hence s390_regs_ever_clobbered is not able to
7410 deal with this automatically. */
7411 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7412 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7413 if (crtl
->calls_eh_return
7414 || (cfun
->machine
->has_landing_pad_p
7415 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7416 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7418 /* For nonlocal gotos all call-saved registers have to be saved.
7419 This flag is also set for the unwinding code in libgcc.
7420 See expand_builtin_unwind_init. For regs_ever_live this is done by
7422 if (crtl
->saves_all_registers
)
7423 for (i
= 0; i
< 32; i
++)
7424 if (!call_really_used_regs
[i
])
7425 regs_ever_clobbered
[i
] = 1;
7427 FOR_EACH_BB_FN (cur_bb
, cfun
)
7429 FOR_BB_INSNS (cur_bb
, cur_insn
)
7433 if (!INSN_P (cur_insn
))
7436 pat
= PATTERN (cur_insn
);
7438 /* Ignore GPR restore insns. */
7439 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
7441 if (GET_CODE (pat
) == SET
7442 && GENERAL_REG_P (SET_DEST (pat
)))
7445 if (GET_MODE (SET_SRC (pat
)) == DImode
7446 && FP_REG_P (SET_SRC (pat
)))
7450 if (GET_CODE (SET_SRC (pat
)) == MEM
)
7455 if (GET_CODE (pat
) == PARALLEL
7456 && load_multiple_operation (pat
, VOIDmode
))
7461 s390_reg_clobbered_rtx
,
7462 regs_ever_clobbered
);
7467 /* Determine the frame area which actually has to be accessed
7468 in the function epilogue. The values are stored at the
7469 given pointers AREA_BOTTOM (address of the lowest used stack
7470 address) and AREA_TOP (address of the first item which does
7471 not belong to the stack frame). */
7474 s390_frame_area (int *area_bottom
, int *area_top
)
7481 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7483 b
= (cfun_frame_layout
.gprs_offset
7484 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7485 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7486 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7489 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7491 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7492 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7493 + cfun_frame_layout
.high_fprs
* 8));
7498 if (cfun_fpr_save_p (FPR4_REGNUM
))
7500 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
7501 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
7503 if (cfun_fpr_save_p (FPR6_REGNUM
))
7505 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
7506 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
7512 /* Update gpr_save_slots in the frame layout trying to make use of
7513 FPRs as GPR save slots.
7514 This is a helper routine of s390_register_info. */
7517 s390_register_info_gprtofpr ()
7519 int save_reg_slot
= FPR0_REGNUM
;
7522 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
7525 for (i
= 15; i
>= 6; i
--)
7527 if (cfun_gpr_save_slot (i
) == 0)
7530 /* Advance to the next FP register which can be used as a
7532 while ((!call_really_used_regs
[save_reg_slot
]
7533 || df_regs_ever_live_p (save_reg_slot
)
7534 || cfun_fpr_save_p (save_reg_slot
))
7535 && FP_REGNO_P (save_reg_slot
))
7537 if (!FP_REGNO_P (save_reg_slot
))
7539 /* We only want to use ldgr/lgdr if we can get rid of
7540 stm/lm entirely. So undo the gpr slot allocation in
7541 case we ran out of FPR save slots. */
7542 for (j
= 6; j
<= 15; j
++)
7543 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
7544 cfun_gpr_save_slot (j
) = -1;
7547 cfun_gpr_save_slot (i
) = save_reg_slot
++;
7551 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7553 This is a helper routine for s390_register_info. */
7556 s390_register_info_stdarg_fpr ()
7562 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7563 f0-f4 for 64 bit. */
7565 || !TARGET_HARD_FLOAT
7566 || !cfun
->va_list_fpr_size
7567 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
7570 min_fpr
= crtl
->args
.info
.fprs
;
7571 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7572 if (max_fpr
> FP_ARG_NUM_REG
)
7573 max_fpr
= FP_ARG_NUM_REG
;
7575 for (i
= min_fpr
; i
< max_fpr
; i
++)
7576 cfun_set_fpr_save (i
+ FPR0_REGNUM
);
7579 /* Reserve the GPR save slots for GPRs which need to be saved due to
7581 This is a helper routine for s390_register_info. */
7584 s390_register_info_stdarg_gpr ()
7591 || !cfun
->va_list_gpr_size
7592 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
7595 min_gpr
= crtl
->args
.info
.gprs
;
7596 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7597 if (max_gpr
> GP_ARG_NUM_REG
)
7598 max_gpr
= GP_ARG_NUM_REG
;
7600 for (i
= min_gpr
; i
< max_gpr
; i
++)
7601 cfun_gpr_save_slot (2 + i
) = -1;
7604 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
7605 for registers which need to be saved in function prologue.
7606 This function can be used until the insns emitted for save/restore
7607 of the regs are visible in the RTL stream. */
7610 s390_register_info ()
7613 char clobbered_regs
[32];
7615 gcc_assert (!epilogue_completed
);
7617 if (reload_completed
)
7618 /* After reload we rely on our own routine to determine which
7619 registers need saving. */
7620 s390_regs_ever_clobbered (clobbered_regs
);
7622 /* During reload we use regs_ever_live as a base since reload
7623 does changes in there which we otherwise would not be aware
7625 for (i
= 0; i
< 32; i
++)
7626 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
7628 for (i
= 0; i
< 32; i
++)
7629 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
7631 /* Mark the call-saved FPRs which need to be saved.
7632 This needs to be done before checking the special GPRs since the
7633 stack pointer usage depends on whether high FPRs have to be saved
7635 cfun_frame_layout
.fpr_bitmap
= 0;
7636 cfun_frame_layout
.high_fprs
= 0;
7637 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
7638 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
7640 cfun_set_fpr_save (i
);
7641 if (i
>= FPR8_REGNUM
)
7642 cfun_frame_layout
.high_fprs
++;
7646 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7647 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7649 clobbered_regs
[BASE_REGNUM
]
7650 |= (cfun
->machine
->base_reg
7651 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7653 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
7654 |= !!frame_pointer_needed
;
7656 /* On pre z900 machines this might take until machine dependent
7658 save_return_addr_p will only be set on non-zarch machines so
7659 there is no risk that r14 goes into an FPR instead of a stack
7661 clobbered_regs
[RETURN_REGNUM
]
7663 || TARGET_TPF_PROFILING
7664 || cfun
->machine
->split_branches_pending_p
7665 || cfun_frame_layout
.save_return_addr_p
7666 || crtl
->calls_eh_return
);
7668 clobbered_regs
[STACK_POINTER_REGNUM
]
7670 || TARGET_TPF_PROFILING
7671 || cfun_save_high_fprs_p
7672 || get_frame_size () > 0
7673 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
7674 || cfun
->calls_alloca
);
7676 memset (cfun_frame_layout
.gpr_save_slots
, 0, 16);
7678 for (i
= 6; i
< 16; i
++)
7679 if (clobbered_regs
[i
])
7680 cfun_gpr_save_slot (i
) = -1;
7682 s390_register_info_stdarg_fpr ();
7683 s390_register_info_gprtofpr ();
7685 /* First find the range of GPRs to be restored. Vararg regs don't
7686 need to be restored so we do it before assigning slots to the
7688 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7689 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7690 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
7691 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
7693 /* stdarg functions might need to save GPRs 2 to 6. This might
7694 override the GPR->FPR save decision made above for r6 since
7695 vararg regs must go to the stack. */
7696 s390_register_info_stdarg_gpr ();
7698 /* Now the range of GPRs which need saving. */
7699 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7700 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7701 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
7702 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
7705 /* This function is called by s390_optimize_prologue in order to get
7706 rid of unnecessary GPR save/restore instructions. The register info
7707 for the GPRs is re-computed and the ranges are re-calculated. */
7710 s390_optimize_register_info ()
7712 char clobbered_regs
[32];
7715 gcc_assert (epilogue_completed
);
7716 gcc_assert (!cfun
->machine
->split_branches_pending_p
);
7718 s390_regs_ever_clobbered (clobbered_regs
);
7720 for (i
= 0; i
< 32; i
++)
7721 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
7723 /* There is still special treatment needed for cases invisible to
7724 s390_regs_ever_clobbered. */
7725 clobbered_regs
[RETURN_REGNUM
]
7726 |= (TARGET_TPF_PROFILING
7727 /* When expanding builtin_return_addr in ESA mode we do not
7728 know whether r14 will later be needed as scratch reg when
7729 doing branch splitting. So the builtin always accesses the
7730 r14 save slot and we need to stick to the save/restore
7731 decision for r14 even if it turns out that it didn't get
7733 || cfun_frame_layout
.save_return_addr_p
7734 || crtl
->calls_eh_return
);
7736 memset (cfun_frame_layout
.gpr_save_slots
, 0, 6);
7738 for (i
= 6; i
< 16; i
++)
7739 if (!clobbered_regs
[i
])
7740 cfun_gpr_save_slot (i
) = 0;
7742 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7743 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7744 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
7745 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
7747 s390_register_info_stdarg_gpr ();
7749 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
7750 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
7751 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
7752 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
7755 /* Fill cfun->machine with info about frame of current function. */
7758 s390_frame_info (void)
7760 HOST_WIDE_INT lowest_offset
;
7762 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
7763 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
7765 /* The va_arg builtin uses a constant distance of 16 *
7766 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7767 pointer. So even if we are going to save the stack pointer in an
7768 FPR we need the stack space in order to keep the offsets
7770 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
7772 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
7774 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
7775 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
7778 cfun_frame_layout
.frame_size
= get_frame_size ();
7779 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7780 fatal_error ("total size of local variables exceeds architecture limit");
7782 if (!TARGET_PACKED_STACK
)
7784 /* Fixed stack layout. */
7785 cfun_frame_layout
.backchain_offset
= 0;
7786 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7787 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7788 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7789 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7792 else if (TARGET_BACKCHAIN
)
7794 /* Kernel stack layout - packed stack, backchain, no float */
7795 gcc_assert (TARGET_SOFT_FLOAT
);
7796 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7799 /* The distance between the backchain and the return address
7800 save slot must not change. So we always need a slot for the
7801 stack pointer which resides in between. */
7802 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
7804 cfun_frame_layout
.gprs_offset
7805 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
7807 /* FPRs will not be saved. Nevertheless pick sane values to
7808 keep area calculations valid. */
7809 cfun_frame_layout
.f0_offset
=
7810 cfun_frame_layout
.f4_offset
=
7811 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
7817 /* Packed stack layout without backchain. */
7819 /* With stdarg FPRs need their dedicated slots. */
7820 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
7821 : (cfun_fpr_save_p (FPR4_REGNUM
) +
7822 cfun_fpr_save_p (FPR6_REGNUM
)));
7823 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
7825 num_fprs
= (cfun
->stdarg
? 2
7826 : (cfun_fpr_save_p (FPR0_REGNUM
)
7827 + cfun_fpr_save_p (FPR2_REGNUM
)));
7828 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
7830 cfun_frame_layout
.gprs_offset
7831 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7833 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
7834 - cfun_frame_layout
.high_fprs
* 8);
7837 if (cfun_save_high_fprs_p
)
7838 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7841 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7843 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7844 sized area at the bottom of the stack. This is required also for
7845 leaf functions. When GCC generates a local stack reference it
7846 will always add STACK_POINTER_OFFSET to all these references. */
7848 && !TARGET_TPF_PROFILING
7849 && cfun_frame_layout
.frame_size
== 0
7850 && !cfun
->calls_alloca
)
7853 /* Calculate the number of bytes we have used in our own register
7854 save area. With the packed stack layout we can re-use the
7855 remaining bytes for normal stack elements. */
7857 if (TARGET_PACKED_STACK
)
7858 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
7859 cfun_frame_layout
.f4_offset
),
7860 cfun_frame_layout
.gprs_offset
);
7864 if (TARGET_BACKCHAIN
)
7865 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
7867 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
7869 /* If under 31 bit an odd number of gprs has to be saved we have to
7870 adjust the frame size to sustain 8 byte alignment of stack
7872 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7873 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7874 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7877 /* Generate frame layout. Fills in register and frame data for the current
7878 function in cfun->machine. This routine can be called multiple times;
7879 it will re-do the complete frame layout every time. */
7882 s390_init_frame_layout (void)
7884 HOST_WIDE_INT frame_size
;
7887 gcc_assert (!reload_completed
);
7889 /* On S/390 machines, we may need to perform branch splitting, which
7890 will require both base and return address register. We have no
7891 choice but to assume we're going to need them until right at the
7892 end of the machine dependent reorg phase. */
7893 if (!TARGET_CPU_ZARCH
)
7894 cfun
->machine
->split_branches_pending_p
= true;
7898 frame_size
= cfun_frame_layout
.frame_size
;
7900 /* Try to predict whether we'll need the base register. */
7901 base_used
= cfun
->machine
->split_branches_pending_p
7902 || crtl
->uses_const_pool
7903 || (!DISP_IN_RANGE (frame_size
)
7904 && !CONST_OK_FOR_K (frame_size
));
7906 /* Decide which register to use as literal pool base. In small
7907 leaf functions, try to use an unused call-clobbered register
7908 as base register to avoid save/restore overhead. */
7910 cfun
->machine
->base_reg
= NULL_RTX
;
7911 else if (crtl
->is_leaf
&& !df_regs_ever_live_p (5))
7912 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7914 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7916 s390_register_info ();
7919 while (frame_size
!= cfun_frame_layout
.frame_size
);
7922 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7923 the TX is nonescaping. A transaction is considered escaping if
7924 there is at least one path from tbegin returning CC0 to the
7925 function exit block without an tend.
7927 The check so far has some limitations:
7928 - only single tbegin/tend BBs are supported
7929 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7930 - when CC is copied to a GPR and the CC0 check is done with the GPR
7931 this is not supported
7935 s390_optimize_nonescaping_tx (void)
7937 const unsigned int CC0
= 1 << 3;
7938 basic_block tbegin_bb
= NULL
;
7939 basic_block tend_bb
= NULL
;
7944 rtx_insn
*tbegin_insn
= NULL
;
7946 if (!cfun
->machine
->tbegin_p
)
7949 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
7951 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
7956 FOR_BB_INSNS (bb
, insn
)
7958 rtx ite
, cc
, pat
, target
;
7959 unsigned HOST_WIDE_INT mask
;
7961 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
7964 pat
= PATTERN (insn
);
7966 if (GET_CODE (pat
) == PARALLEL
)
7967 pat
= XVECEXP (pat
, 0, 0);
7969 if (GET_CODE (pat
) != SET
7970 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
7973 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
7979 /* Just return if the tbegin doesn't have clobbers. */
7980 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
7983 if (tbegin_bb
!= NULL
)
7986 /* Find the next conditional jump. */
7987 for (tmp
= NEXT_INSN (insn
);
7989 tmp
= NEXT_INSN (tmp
))
7991 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
7996 ite
= SET_SRC (PATTERN (tmp
));
7997 if (GET_CODE (ite
) != IF_THEN_ELSE
)
8000 cc
= XEXP (XEXP (ite
, 0), 0);
8001 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
8002 || GET_MODE (cc
) != CCRAWmode
8003 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
8006 if (bb
->succs
->length () != 2)
8009 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
8010 if (GET_CODE (XEXP (ite
, 0)) == NE
)
8014 target
= XEXP (ite
, 1);
8015 else if (mask
== (CC0
^ 0xf))
8016 target
= XEXP (ite
, 2);
8024 ei
= ei_start (bb
->succs
);
8025 e1
= ei_safe_edge (ei
);
8027 e2
= ei_safe_edge (ei
);
8029 if (e2
->flags
& EDGE_FALLTHRU
)
8032 e1
= ei_safe_edge (ei
);
8035 if (!(e1
->flags
& EDGE_FALLTHRU
))
8038 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
8040 if (tmp
== BB_END (bb
))
8045 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
8047 if (tend_bb
!= NULL
)
8054 /* Either we successfully remove the FPR clobbers here or we are not
8055 able to do anything for this TX. Both cases don't qualify for
8057 cfun
->machine
->tbegin_p
= false;
8059 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
8062 calculate_dominance_info (CDI_POST_DOMINATORS
);
8063 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
8064 free_dominance_info (CDI_POST_DOMINATORS
);
8069 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
8071 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
8072 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
8073 INSN_CODE (tbegin_insn
) = -1;
8074 df_insn_rescan (tbegin_insn
);
8079 /* Return true if it is legal to put a value with MODE into REGNO. */
8082 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
8084 switch (REGNO_REG_CLASS (regno
))
8087 if (REGNO_PAIR_OK (regno
, mode
))
8089 if (mode
== SImode
|| mode
== DImode
)
8092 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
8097 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
8102 if (REGNO_PAIR_OK (regno
, mode
))
8105 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
8110 if (GET_MODE_CLASS (mode
) == MODE_CC
)
8114 if (REGNO_PAIR_OK (regno
, mode
))
8116 if (mode
== SImode
|| mode
== Pmode
)
8127 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8130 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
8132 /* Once we've decided upon a register to use as base register, it must
8133 no longer be used for any other purpose. */
8134 if (cfun
->machine
->base_reg
)
8135 if (REGNO (cfun
->machine
->base_reg
) == old_reg
8136 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
8139 /* Prevent regrename from using call-saved regs which haven't
8140 actually been saved. This is necessary since regrename assumes
8141 the backend save/restore decisions are based on
8142 df_regs_ever_live. Since we have our own routine we have to tell
8143 regrename manually about it. */
8144 if (GENERAL_REGNO_P (new_reg
)
8145 && !call_really_used_regs
[new_reg
]
8146 && cfun_gpr_save_slot (new_reg
) == 0)
8152 /* Return nonzero if register REGNO can be used as a scratch register
8156 s390_hard_regno_scratch_ok (unsigned int regno
)
8158 /* See s390_hard_regno_rename_ok. */
8159 if (GENERAL_REGNO_P (regno
)
8160 && !call_really_used_regs
[regno
]
8161 && cfun_gpr_save_slot (regno
) == 0)
8167 /* Maximum number of registers to represent a value of mode MODE
8168 in a register of class RCLASS. */
8171 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
8176 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
8177 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
8179 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
8181 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
8185 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8188 /* Return true if we use LRA instead of reload pass. */
8192 return s390_lra_flag
;
8195 /* Return true if register FROM can be eliminated via register TO. */
8198 s390_can_eliminate (const int from
, const int to
)
8200 /* On zSeries machines, we have not marked the base register as fixed.
8201 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8202 If a function requires the base register, we say here that this
8203 elimination cannot be performed. This will cause reload to free
8204 up the base register (as if it were fixed). On the other hand,
8205 if the current function does *not* require the base register, we
8206 say here the elimination succeeds, which in turn allows reload
8207 to allocate the base register for any other purpose. */
8208 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
8210 if (TARGET_CPU_ZARCH
)
8212 s390_init_frame_layout ();
8213 return cfun
->machine
->base_reg
== NULL_RTX
;
8219 /* Everything else must point into the stack frame. */
8220 gcc_assert (to
== STACK_POINTER_REGNUM
8221 || to
== HARD_FRAME_POINTER_REGNUM
);
8223 gcc_assert (from
== FRAME_POINTER_REGNUM
8224 || from
== ARG_POINTER_REGNUM
8225 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
8227 /* Make sure we actually saved the return address. */
8228 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
8229 if (!crtl
->calls_eh_return
8231 && !cfun_frame_layout
.save_return_addr_p
)
8237 /* Return offset between register FROM and TO initially after prolog. */
8240 s390_initial_elimination_offset (int from
, int to
)
8242 HOST_WIDE_INT offset
;
8244 /* ??? Why are we called for non-eliminable pairs? */
8245 if (!s390_can_eliminate (from
, to
))
8250 case FRAME_POINTER_REGNUM
:
8251 offset
= (get_frame_size()
8252 + STACK_POINTER_OFFSET
8253 + crtl
->outgoing_args_size
);
8256 case ARG_POINTER_REGNUM
:
8257 s390_init_frame_layout ();
8258 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
8261 case RETURN_ADDRESS_POINTER_REGNUM
:
8262 s390_init_frame_layout ();
8264 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
8266 /* If it turns out that for stdarg nothing went into the reg
8267 save area we also do not need the return address
8269 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
8275 /* In order to make the following work it is not necessary for
8276 r14 to have a save slot. It is sufficient if one other GPR
8277 got one. Since the GPRs are always stored without gaps we
8278 are able to calculate where the r14 save slot would
8280 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
8281 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
8296 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8297 to register BASE. Return generated insn. */
8300 save_fpr (rtx base
, int offset
, int regnum
)
8303 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
8305 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
8306 set_mem_alias_set (addr
, get_varargs_alias_set ());
8308 set_mem_alias_set (addr
, get_frame_alias_set ());
8310 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
8313 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8314 to register BASE. Return generated insn. */
8317 restore_fpr (rtx base
, int offset
, int regnum
)
8320 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
8321 set_mem_alias_set (addr
, get_frame_alias_set ());
8323 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
8326 /* Return true if REGNO is a global register, but not one
8327 of the special ones that need to be saved/restored in anyway. */
8330 global_not_special_regno_p (int regno
)
8332 return (global_regs
[regno
]
8333 /* These registers are special and need to be
8334 restored in any case. */
8335 && !(regno
== STACK_POINTER_REGNUM
8336 || regno
== RETURN_REGNUM
8337 || regno
== BASE_REGNUM
8338 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
8341 /* Generate insn to save registers FIRST to LAST into
8342 the register save area located at offset OFFSET
8343 relative to register BASE. */
8346 save_gprs (rtx base
, int offset
, int first
, int last
)
8348 rtx addr
, insn
, note
;
8351 addr
= plus_constant (Pmode
, base
, offset
);
8352 addr
= gen_rtx_MEM (Pmode
, addr
);
8354 set_mem_alias_set (addr
, get_frame_alias_set ());
8356 /* Special-case single register. */
8360 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
8362 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
8364 if (!global_not_special_regno_p (first
))
8365 RTX_FRAME_RELATED_P (insn
) = 1;
8370 insn
= gen_store_multiple (addr
,
8371 gen_rtx_REG (Pmode
, first
),
8372 GEN_INT (last
- first
+ 1));
8374 if (first
<= 6 && cfun
->stdarg
)
8375 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
8377 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
8380 set_mem_alias_set (mem
, get_varargs_alias_set ());
8383 /* We need to set the FRAME_RELATED flag on all SETs
8384 inside the store-multiple pattern.
8386 However, we must not emit DWARF records for registers 2..5
8387 if they are stored for use by variable arguments ...
8389 ??? Unfortunately, it is not enough to simply not the
8390 FRAME_RELATED flags for those SETs, because the first SET
8391 of the PARALLEL is always treated as if it had the flag
8392 set, even if it does not. Therefore we emit a new pattern
8393 without those registers as REG_FRAME_RELATED_EXPR note. */
8395 if (first
>= 6 && !global_not_special_regno_p (first
))
8397 rtx pat
= PATTERN (insn
);
8399 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
8400 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
8401 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
8403 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
8405 RTX_FRAME_RELATED_P (insn
) = 1;
8411 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
8412 if (!global_not_special_regno_p (start
))
8418 addr
= plus_constant (Pmode
, base
,
8419 offset
+ (start
- first
) * UNITS_PER_LONG
);
8424 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
8425 gen_rtx_REG (Pmode
, start
));
8427 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
8428 gen_rtx_REG (Pmode
, start
));
8429 note
= PATTERN (note
);
8431 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
8432 RTX_FRAME_RELATED_P (insn
) = 1;
8437 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
8438 gen_rtx_REG (Pmode
, start
),
8439 GEN_INT (last
- start
+ 1));
8440 note
= PATTERN (note
);
8442 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
8444 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
8445 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
8446 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
8448 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
8450 RTX_FRAME_RELATED_P (insn
) = 1;
8456 /* Generate insn to restore registers FIRST to LAST from
8457 the register save area located at offset OFFSET
8458 relative to register BASE. */
8461 restore_gprs (rtx base
, int offset
, int first
, int last
)
8465 addr
= plus_constant (Pmode
, base
, offset
);
8466 addr
= gen_rtx_MEM (Pmode
, addr
);
8467 set_mem_alias_set (addr
, get_frame_alias_set ());
8469 /* Special-case single register. */
8473 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
8475 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
8477 RTX_FRAME_RELATED_P (insn
) = 1;
8481 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
8483 GEN_INT (last
- first
+ 1));
8484 RTX_FRAME_RELATED_P (insn
) = 1;
8488 /* Return insn sequence to load the GOT register. */
8490 static GTY(()) rtx got_symbol
;
8492 s390_load_got (void)
8496 /* We cannot use pic_offset_table_rtx here since we use this
8497 function also for non-pic if __tls_get_offset is called and in
8498 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8500 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
8504 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8505 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
8510 if (TARGET_CPU_ZARCH
)
8512 emit_move_insn (got_rtx
, got_symbol
);
8518 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
8519 UNSPEC_LTREL_OFFSET
);
8520 offset
= gen_rtx_CONST (Pmode
, offset
);
8521 offset
= force_const_mem (Pmode
, offset
);
8523 emit_move_insn (got_rtx
, offset
);
8525 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
8527 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
8529 emit_move_insn (got_rtx
, offset
);
8532 insns
= get_insns ();
8537 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8538 and the change to the stack pointer. */
8541 s390_emit_stack_tie (void)
8543 rtx mem
= gen_frame_mem (BLKmode
,
8544 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
8546 emit_insn (gen_stack_tie (mem
));
8549 /* Copy GPRS into FPR save slots. */
8552 s390_save_gprs_to_fprs (void)
8556 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
8559 for (i
= 6; i
< 16; i
++)
8561 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
8564 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
8565 gen_rtx_REG (DImode
, i
));
8566 RTX_FRAME_RELATED_P (insn
) = 1;
8571 /* Restore GPRs from FPR save slots. */
8574 s390_restore_gprs_from_fprs (void)
8578 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
8581 for (i
= 6; i
< 16; i
++)
8583 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
8586 emit_move_insn (gen_rtx_REG (DImode
, i
),
8587 gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)));
8588 df_set_regs_ever_live (i
, true);
8589 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
8590 if (i
== STACK_POINTER_REGNUM
)
8591 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8592 plus_constant (Pmode
, stack_pointer_rtx
,
8593 STACK_POINTER_OFFSET
));
8594 RTX_FRAME_RELATED_P (insn
) = 1;
8600 /* A pass run immediately before shrink-wrapping and prologue and epilogue
8605 const pass_data pass_data_s390_early_mach
=
8607 RTL_PASS
, /* type */
8608 "early_mach", /* name */
8609 OPTGROUP_NONE
, /* optinfo_flags */
8610 TV_MACH_DEP
, /* tv_id */
8611 0, /* properties_required */
8612 0, /* properties_provided */
8613 0, /* properties_destroyed */
8614 0, /* todo_flags_start */
8615 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
8618 class pass_s390_early_mach
: public rtl_opt_pass
8621 pass_s390_early_mach (gcc::context
*ctxt
)
8622 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
8625 /* opt_pass methods: */
8626 virtual unsigned int execute (function
*);
8628 }; // class pass_s390_early_mach
8631 pass_s390_early_mach::execute (function
*fun
)
8635 /* Try to get rid of the FPR clobbers. */
8636 s390_optimize_nonescaping_tx ();
8638 /* Re-compute register info. */
8639 s390_register_info ();
8641 /* If we're using a base register, ensure that it is always valid for
8642 the first non-prologue instruction. */
8643 if (fun
->machine
->base_reg
)
8644 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
8646 /* Annotate all constant pool references to let the scheduler know
8647 they implicitly use the base register. */
8648 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8651 annotate_constant_pool_refs (&PATTERN (insn
));
8652 df_insn_rescan (insn
);
8659 /* Expand the prologue into a bunch of separate insns. */
8662 s390_emit_prologue (void)
8670 /* Choose best register to use for temp use within prologue.
8671 See below for why TPF must use the register 1. */
8673 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
8675 && !TARGET_TPF_PROFILING
)
8676 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8678 temp_reg
= gen_rtx_REG (Pmode
, 1);
8680 s390_save_gprs_to_fprs ();
8682 /* Save call saved gprs. */
8683 if (cfun_frame_layout
.first_save_gpr
!= -1)
8685 insn
= save_gprs (stack_pointer_rtx
,
8686 cfun_frame_layout
.gprs_offset
+
8687 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
8688 - cfun_frame_layout
.first_save_gpr_slot
),
8689 cfun_frame_layout
.first_save_gpr
,
8690 cfun_frame_layout
.last_save_gpr
);
8694 /* Dummy insn to mark literal pool slot. */
8696 if (cfun
->machine
->base_reg
)
8697 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8699 offset
= cfun_frame_layout
.f0_offset
;
8701 /* Save f0 and f2. */
8702 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
8704 if (cfun_fpr_save_p (i
))
8706 save_fpr (stack_pointer_rtx
, offset
, i
);
8709 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
8713 /* Save f4 and f6. */
8714 offset
= cfun_frame_layout
.f4_offset
;
8715 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
8717 if (cfun_fpr_save_p (i
))
8719 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
8722 /* If f4 and f6 are call clobbered they are saved due to
8723 stdargs and therefore are not frame related. */
8724 if (!call_really_used_regs
[i
])
8725 RTX_FRAME_RELATED_P (insn
) = 1;
8727 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
8731 if (TARGET_PACKED_STACK
8732 && cfun_save_high_fprs_p
8733 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8735 offset
= (cfun_frame_layout
.f8_offset
8736 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8738 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
8739 if (cfun_fpr_save_p (i
))
8741 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
8743 RTX_FRAME_RELATED_P (insn
) = 1;
8746 if (offset
>= cfun_frame_layout
.f8_offset
)
8750 if (!TARGET_PACKED_STACK
)
8751 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
8753 if (flag_stack_usage_info
)
8754 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8756 /* Decrement stack pointer. */
8758 if (cfun_frame_layout
.frame_size
> 0)
8760 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8763 if (s390_stack_size
)
8765 HOST_WIDE_INT stack_guard
;
8767 if (s390_stack_guard
)
8768 stack_guard
= s390_stack_guard
;
8771 /* If no value for stack guard is provided the smallest power of 2
8772 larger than the current frame size is chosen. */
8774 while (stack_guard
< cfun_frame_layout
.frame_size
)
8778 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8780 warning (0, "frame size of function %qs is %wd"
8781 " bytes exceeding user provided stack limit of "
8783 "An unconditional trap is added.",
8784 current_function_name(), cfun_frame_layout
.frame_size
,
8786 emit_insn (gen_trap ());
8790 /* stack_guard has to be smaller than s390_stack_size.
8791 Otherwise we would emit an AND with zero which would
8792 not match the test under mask pattern. */
8793 if (stack_guard
>= s390_stack_size
)
8795 warning (0, "frame size of function %qs is %wd"
8796 " bytes which is more than half the stack size. "
8797 "The dynamic check would not be reliable. "
8798 "No check emitted for this function.",
8799 current_function_name(),
8800 cfun_frame_layout
.frame_size
);
8804 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8805 & ~(stack_guard
- 1));
8807 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8808 GEN_INT (stack_check_mask
));
8810 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8812 t
, const0_rtx
, const0_rtx
));
8814 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8816 t
, const0_rtx
, const0_rtx
));
8821 if (s390_warn_framesize
> 0
8822 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8823 warning (0, "frame size of %qs is %wd bytes",
8824 current_function_name (), cfun_frame_layout
.frame_size
);
8826 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8827 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8829 /* Save incoming stack pointer into temp reg. */
8830 if (TARGET_BACKCHAIN
|| next_fpr
)
8831 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8833 /* Subtract frame size from stack pointer. */
8835 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8837 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8838 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8840 insn
= emit_insn (insn
);
8844 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8845 frame_off
= force_const_mem (Pmode
, frame_off
);
8847 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8848 annotate_constant_pool_refs (&PATTERN (insn
));
8851 RTX_FRAME_RELATED_P (insn
) = 1;
8852 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8853 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8854 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8855 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8858 /* Set backchain. */
8860 if (TARGET_BACKCHAIN
)
8862 if (cfun_frame_layout
.backchain_offset
)
8863 addr
= gen_rtx_MEM (Pmode
,
8864 plus_constant (Pmode
, stack_pointer_rtx
,
8865 cfun_frame_layout
.backchain_offset
));
8867 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8868 set_mem_alias_set (addr
, get_frame_alias_set ());
8869 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8872 /* If we support non-call exceptions (e.g. for Java),
8873 we need to make sure the backchain pointer is set up
8874 before any possibly trapping memory access. */
8875 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8877 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8878 emit_clobber (addr
);
8882 /* Save fprs 8 - 15 (64 bit ABI). */
8884 if (cfun_save_high_fprs_p
&& next_fpr
)
8886 /* If the stack might be accessed through a different register
8887 we have to make sure that the stack pointer decrement is not
8888 moved below the use of the stack slots. */
8889 s390_emit_stack_tie ();
8891 insn
= emit_insn (gen_add2_insn (temp_reg
,
8892 GEN_INT (cfun_frame_layout
.f8_offset
)));
8896 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
8897 if (cfun_fpr_save_p (i
))
8899 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
8900 cfun_frame_layout
.frame_size
8901 + cfun_frame_layout
.f8_offset
8904 insn
= save_fpr (temp_reg
, offset
, i
);
8906 RTX_FRAME_RELATED_P (insn
) = 1;
8907 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8908 gen_rtx_SET (VOIDmode
,
8909 gen_rtx_MEM (DFmode
, addr
),
8910 gen_rtx_REG (DFmode
, i
)));
8914 /* Set frame pointer, if needed. */
8916 if (frame_pointer_needed
)
8918 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8919 RTX_FRAME_RELATED_P (insn
) = 1;
8922 /* Set up got pointer, if needed. */
8924 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8926 rtx_insn
*insns
= s390_load_got ();
8928 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8929 annotate_constant_pool_refs (&PATTERN (insn
));
8934 if (TARGET_TPF_PROFILING
)
8936 /* Generate a BAS instruction to serve as a function
8937 entry intercept to facilitate the use of tracing
8938 algorithms located at the branch target. */
8939 emit_insn (gen_prologue_tpf ());
8941 /* Emit a blockage here so that all code
8942 lies between the profiling mechanisms. */
8943 emit_insn (gen_blockage ());
8947 /* Expand the epilogue into a bunch of separate insns. */
8950 s390_emit_epilogue (bool sibcall
)
8952 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8953 int area_bottom
, area_top
, offset
= 0;
8958 if (TARGET_TPF_PROFILING
)
8961 /* Generate a BAS instruction to serve as a function
8962 entry intercept to facilitate the use of tracing
8963 algorithms located at the branch target. */
8965 /* Emit a blockage here so that all code
8966 lies between the profiling mechanisms. */
8967 emit_insn (gen_blockage ());
8969 emit_insn (gen_epilogue_tpf ());
8972 /* Check whether to use frame or stack pointer for restore. */
8974 frame_pointer
= (frame_pointer_needed
8975 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8977 s390_frame_area (&area_bottom
, &area_top
);
8979 /* Check whether we can access the register save area.
8980 If not, increment the frame pointer as required. */
8982 if (area_top
<= area_bottom
)
8984 /* Nothing to restore. */
8986 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8987 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8989 /* Area is in range. */
8990 offset
= cfun_frame_layout
.frame_size
;
8994 rtx insn
, frame_off
, cfa
;
8996 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8997 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8999 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
9000 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
9001 if (DISP_IN_RANGE (INTVAL (frame_off
)))
9003 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
9004 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
9005 insn
= emit_insn (insn
);
9009 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
9010 frame_off
= force_const_mem (Pmode
, frame_off
);
9012 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
9013 annotate_constant_pool_refs (&PATTERN (insn
));
9015 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
9016 RTX_FRAME_RELATED_P (insn
) = 1;
9019 /* Restore call saved fprs. */
9023 if (cfun_save_high_fprs_p
)
9025 next_offset
= cfun_frame_layout
.f8_offset
;
9026 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
9028 if (cfun_fpr_save_p (i
))
9030 restore_fpr (frame_pointer
,
9031 offset
+ next_offset
, i
);
9033 = alloc_reg_note (REG_CFA_RESTORE
,
9034 gen_rtx_REG (DFmode
, i
), cfa_restores
);
9043 next_offset
= cfun_frame_layout
.f4_offset
;
9045 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
9047 if (cfun_fpr_save_p (i
))
9049 restore_fpr (frame_pointer
,
9050 offset
+ next_offset
, i
);
9052 = alloc_reg_note (REG_CFA_RESTORE
,
9053 gen_rtx_REG (DFmode
, i
), cfa_restores
);
9056 else if (!TARGET_PACKED_STACK
)
9062 /* Return register. */
9064 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9066 /* Restore call saved gprs. */
9068 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9073 /* Check for global register and save them
9074 to stack location from where they get restored. */
9076 for (i
= cfun_frame_layout
.first_restore_gpr
;
9077 i
<= cfun_frame_layout
.last_restore_gpr
;
9080 if (global_not_special_regno_p (i
))
9082 addr
= plus_constant (Pmode
, frame_pointer
,
9083 offset
+ cfun_frame_layout
.gprs_offset
9084 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
9086 addr
= gen_rtx_MEM (Pmode
, addr
);
9087 set_mem_alias_set (addr
, get_frame_alias_set ());
9088 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
9092 = alloc_reg_note (REG_CFA_RESTORE
,
9093 gen_rtx_REG (Pmode
, i
), cfa_restores
);
9098 /* Fetch return address from stack before load multiple,
9099 this will do good for scheduling.
9101 Only do this if we already decided that r14 needs to be
9102 saved to a stack slot. (And not just because r14 happens to
9103 be in between two GPRs which need saving.) Otherwise it
9104 would be difficult to take that decision back in
9105 s390_optimize_prologue. */
9106 if (cfun_gpr_save_slot (RETURN_REGNUM
) == -1)
9108 int return_regnum
= find_unused_clobbered_reg();
9111 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
9113 addr
= plus_constant (Pmode
, frame_pointer
,
9114 offset
+ cfun_frame_layout
.gprs_offset
9116 - cfun_frame_layout
.first_save_gpr_slot
)
9118 addr
= gen_rtx_MEM (Pmode
, addr
);
9119 set_mem_alias_set (addr
, get_frame_alias_set ());
9120 emit_move_insn (return_reg
, addr
);
9122 /* Once we did that optimization we have to make sure
9123 s390_optimize_prologue does not try to remove the
9124 store of r14 since we will not be able to find the
9125 load issued here. */
9126 cfun_frame_layout
.save_return_addr_p
= true;
9130 insn
= restore_gprs (frame_pointer
,
9131 offset
+ cfun_frame_layout
.gprs_offset
9132 + (cfun_frame_layout
.first_restore_gpr
9133 - cfun_frame_layout
.first_save_gpr_slot
)
9135 cfun_frame_layout
.first_restore_gpr
,
9136 cfun_frame_layout
.last_restore_gpr
);
9137 insn
= emit_insn (insn
);
9138 REG_NOTES (insn
) = cfa_restores
;
9139 add_reg_note (insn
, REG_CFA_DEF_CFA
,
9140 plus_constant (Pmode
, stack_pointer_rtx
,
9141 STACK_POINTER_OFFSET
));
9142 RTX_FRAME_RELATED_P (insn
) = 1;
9145 s390_restore_gprs_from_fprs ();
9150 /* Return to caller. */
9152 p
= rtvec_alloc (2);
9154 RTVEC_ELT (p
, 0) = ret_rtx
;
9155 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
9156 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
9160 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
9163 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
9165 if (cfun
->machine
->base_reg
9166 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
9167 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
9170 /* Return true if the function can use simple_return to return outside
9171 of a shrink-wrapped region. At present shrink-wrapping is supported
9175 s390_can_use_simple_return_insn (void)
9180 /* Return true if the epilogue is guaranteed to contain only a return
9181 instruction and if a direct return can therefore be used instead.
9182 One of the main advantages of using direct return instructions
9183 is that we can then use conditional returns. */
9186 s390_can_use_return_insn (void)
9190 if (!reload_completed
)
9196 if (TARGET_TPF_PROFILING
)
9199 for (i
= 0; i
< 16; i
++)
9200 if (cfun_gpr_save_slot (i
))
9203 /* For 31 bit this is not covered by the frame_size check below
9204 since f4, f6 are saved in the register save area without needing
9205 additional stack space. */
9207 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
9210 if (cfun
->machine
->base_reg
9211 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
9214 return cfun_frame_layout
.frame_size
== 0;
9217 /* Return the size in bytes of a function argument of
9218 type TYPE and/or mode MODE. At least one of TYPE or
9219 MODE must be specified. */
9222 s390_function_arg_size (machine_mode mode
, const_tree type
)
9225 return int_size_in_bytes (type
);
9227 /* No type info available for some library calls ... */
9228 if (mode
!= BLKmode
)
9229 return GET_MODE_SIZE (mode
);
9231 /* If we have neither type nor mode, abort */
9235 /* Return true if a function argument of type TYPE and mode MODE
9236 is to be passed in a floating-point register, if available. */
9239 s390_function_arg_float (machine_mode mode
, const_tree type
)
9241 int size
= s390_function_arg_size (mode
, type
);
9245 /* Soft-float changes the ABI: no floating-point registers are used. */
9246 if (TARGET_SOFT_FLOAT
)
9249 /* No type info available for some library calls ... */
9251 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
9253 /* The ABI says that record types with a single member are treated
9254 just like that member would be. */
9255 while (TREE_CODE (type
) == RECORD_TYPE
)
9257 tree field
, single
= NULL_TREE
;
9259 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
9261 if (TREE_CODE (field
) != FIELD_DECL
)
9264 if (single
== NULL_TREE
)
9265 single
= TREE_TYPE (field
);
9270 if (single
== NULL_TREE
)
9276 return TREE_CODE (type
) == REAL_TYPE
;
9279 /* Return true if a function argument of type TYPE and mode MODE
9280 is to be passed in an integer register, or a pair of integer
9281 registers, if available. */
9284 s390_function_arg_integer (machine_mode mode
, const_tree type
)
9286 int size
= s390_function_arg_size (mode
, type
);
9290 /* No type info available for some library calls ... */
9292 return GET_MODE_CLASS (mode
) == MODE_INT
9293 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
9295 /* We accept small integral (and similar) types. */
9296 if (INTEGRAL_TYPE_P (type
)
9297 || POINTER_TYPE_P (type
)
9298 || TREE_CODE (type
) == NULLPTR_TYPE
9299 || TREE_CODE (type
) == OFFSET_TYPE
9300 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
9303 /* We also accept structs of size 1, 2, 4, 8 that are not
9304 passed in floating-point registers. */
9305 if (AGGREGATE_TYPE_P (type
)
9306 && exact_log2 (size
) >= 0
9307 && !s390_function_arg_float (mode
, type
))
9313 /* Return 1 if a function argument of type TYPE and mode MODE
9314 is to be passed by reference. The ABI specifies that only
9315 structures of size 1, 2, 4, or 8 bytes are passed by value,
9316 all other structures (and complex numbers) are passed by
9320 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
9321 machine_mode mode
, const_tree type
,
9322 bool named ATTRIBUTE_UNUSED
)
9324 int size
= s390_function_arg_size (mode
, type
);
9330 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
9333 if (TREE_CODE (type
) == COMPLEX_TYPE
9334 || TREE_CODE (type
) == VECTOR_TYPE
)
9341 /* Update the data in CUM to advance over an argument of mode MODE and
9342 data type TYPE. (TYPE is null for libcalls where that information
9343 may not be available.). The boolean NAMED specifies whether the
9344 argument is a named argument (as opposed to an unnamed argument
9345 matching an ellipsis). */
9348 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
9349 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9351 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9353 if (s390_function_arg_float (mode
, type
))
9357 else if (s390_function_arg_integer (mode
, type
))
9359 int size
= s390_function_arg_size (mode
, type
);
9360 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
9366 /* Define where to put the arguments to a function.
9367 Value is zero to push the argument on the stack,
9368 or a hard register in which to store the argument.
9370 MODE is the argument's machine mode.
9371 TYPE is the data type of the argument (as a tree).
9372 This is null for libcalls where that information may
9374 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9375 the preceding args and about the function being called.
9376 NAMED is nonzero if this argument is a named parameter
9377 (otherwise it is an extra parameter matching an ellipsis).
9379 On S/390, we use general purpose registers 2 through 6 to
9380 pass integer, pointer, and certain structure arguments, and
9381 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9382 to pass floating point arguments. All remaining arguments
9383 are pushed to the stack. */
9386 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
9387 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9389 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9391 if (s390_function_arg_float (mode
, type
))
9393 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
9396 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
9398 else if (s390_function_arg_integer (mode
, type
))
9400 int size
= s390_function_arg_size (mode
, type
);
9401 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9403 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
9405 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
9406 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
9407 else if (n_gprs
== 2)
9409 rtvec p
= rtvec_alloc (2);
9412 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
9415 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
9418 return gen_rtx_PARALLEL (mode
, p
);
9422 /* After the real arguments, expand_call calls us once again
9423 with a void_type_node type. Whatever we return here is
9424 passed as operand 2 to the call expanders.
9426 We don't need this feature ... */
9427 else if (type
== void_type_node
)
9433 /* Return true if return values of type TYPE should be returned
9434 in a memory buffer whose address is passed by the caller as
9435 hidden first argument. */
9438 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
9440 /* We accept small integral (and similar) types. */
9441 if (INTEGRAL_TYPE_P (type
)
9442 || POINTER_TYPE_P (type
)
9443 || TREE_CODE (type
) == OFFSET_TYPE
9444 || TREE_CODE (type
) == REAL_TYPE
)
9445 return int_size_in_bytes (type
) > 8;
9447 /* Aggregates and similar constructs are always returned
9449 if (AGGREGATE_TYPE_P (type
)
9450 || TREE_CODE (type
) == COMPLEX_TYPE
9451 || TREE_CODE (type
) == VECTOR_TYPE
)
9454 /* ??? We get called on all sorts of random stuff from
9455 aggregate_value_p. We can't abort, but it's not clear
9456 what's safe to return. Pretend it's a struct I guess. */
9460 /* Function arguments and return values are promoted to word size. */
9463 s390_promote_function_mode (const_tree type
, machine_mode mode
,
9465 const_tree fntype ATTRIBUTE_UNUSED
,
9466 int for_return ATTRIBUTE_UNUSED
)
9468 if (INTEGRAL_MODE_P (mode
)
9469 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
9471 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
9472 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
9479 /* Define where to return a (scalar) value of type RET_TYPE.
9480 If RET_TYPE is null, define where to return a (scalar)
9481 value of mode MODE from a libcall. */
9484 s390_function_and_libcall_value (machine_mode mode
,
9485 const_tree ret_type
,
9486 const_tree fntype_or_decl
,
9487 bool outgoing ATTRIBUTE_UNUSED
)
9489 /* For normal functions perform the promotion as
9490 promote_function_mode would do. */
9493 int unsignedp
= TYPE_UNSIGNED (ret_type
);
9494 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
9498 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
9499 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
9501 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
9502 return gen_rtx_REG (mode
, 16);
9503 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
9504 || UNITS_PER_LONG
== UNITS_PER_WORD
)
9505 return gen_rtx_REG (mode
, 2);
9506 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
9508 /* This case is triggered when returning a 64 bit value with
9509 -m31 -mzarch. Although the value would fit into a single
9510 register it has to be forced into a 32 bit register pair in
9511 order to match the ABI. */
9512 rtvec p
= rtvec_alloc (2);
9515 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
9517 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
9519 return gen_rtx_PARALLEL (mode
, p
);
9525 /* Define where to return a scalar return value of type RET_TYPE. */
9528 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
9531 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
9532 fn_decl_or_type
, outgoing
);
9535 /* Define where to return a scalar libcall return value of mode
9539 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
9541 return s390_function_and_libcall_value (mode
, NULL_TREE
,
9546 /* Create and return the va_list datatype.
9548 On S/390, va_list is an array type equivalent to
9550 typedef struct __va_list_tag
9554 void *__overflow_arg_area;
9555 void *__reg_save_area;
9558 where __gpr and __fpr hold the number of general purpose
9559 or floating point arguments used up to now, respectively,
9560 __overflow_arg_area points to the stack location of the
9561 next argument passed on the stack, and __reg_save_area
9562 always points to the start of the register area in the
9563 call frame of the current function. The function prologue
9564 saves all registers used for argument passing into this
9565 area if the function uses variable arguments. */
9568 s390_build_builtin_va_list (void)
9570 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
9572 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
9575 build_decl (BUILTINS_LOCATION
,
9576 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
9578 f_gpr
= build_decl (BUILTINS_LOCATION
,
9579 FIELD_DECL
, get_identifier ("__gpr"),
9580 long_integer_type_node
);
9581 f_fpr
= build_decl (BUILTINS_LOCATION
,
9582 FIELD_DECL
, get_identifier ("__fpr"),
9583 long_integer_type_node
);
9584 f_ovf
= build_decl (BUILTINS_LOCATION
,
9585 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
9587 f_sav
= build_decl (BUILTINS_LOCATION
,
9588 FIELD_DECL
, get_identifier ("__reg_save_area"),
9591 va_list_gpr_counter_field
= f_gpr
;
9592 va_list_fpr_counter_field
= f_fpr
;
9594 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9595 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9596 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9597 DECL_FIELD_CONTEXT (f_sav
) = record
;
9599 TYPE_STUB_DECL (record
) = type_decl
;
9600 TYPE_NAME (record
) = type_decl
;
9601 TYPE_FIELDS (record
) = f_gpr
;
9602 DECL_CHAIN (f_gpr
) = f_fpr
;
9603 DECL_CHAIN (f_fpr
) = f_ovf
;
9604 DECL_CHAIN (f_ovf
) = f_sav
;
9606 layout_type (record
);
9608 /* The correct type is an array type of one element. */
9609 return build_array_type (record
, build_index_type (size_zero_node
));
9612 /* Implement va_start by filling the va_list structure VALIST.
9613 STDARG_P is always true, and ignored.
9614 NEXTARG points to the first anonymous stack argument.
9616 The following global variables are used to initialize
9617 the va_list structure:
9620 holds number of gprs and fprs used for named arguments.
9621 crtl->args.arg_offset_rtx:
9622 holds the offset of the first anonymous stack argument
9623 (relative to the virtual arg pointer). */
9626 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
9628 HOST_WIDE_INT n_gpr
, n_fpr
;
9630 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9631 tree gpr
, fpr
, ovf
, sav
, t
;
9633 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9634 f_fpr
= DECL_CHAIN (f_gpr
);
9635 f_ovf
= DECL_CHAIN (f_fpr
);
9636 f_sav
= DECL_CHAIN (f_ovf
);
9638 valist
= build_simple_mem_ref (valist
);
9639 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9640 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9641 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9642 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9644 /* Count number of gp and fp argument registers used. */
9646 n_gpr
= crtl
->args
.info
.gprs
;
9647 n_fpr
= crtl
->args
.info
.fprs
;
9649 if (cfun
->va_list_gpr_size
)
9651 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9652 build_int_cst (NULL_TREE
, n_gpr
));
9653 TREE_SIDE_EFFECTS (t
) = 1;
9654 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9657 if (cfun
->va_list_fpr_size
)
9659 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9660 build_int_cst (NULL_TREE
, n_fpr
));
9661 TREE_SIDE_EFFECTS (t
) = 1;
9662 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9665 /* Find the overflow area. */
9666 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
9667 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
9669 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9671 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
9672 off
= off
< 0 ? 0 : off
;
9673 if (TARGET_DEBUG_ARG
)
9674 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9675 (int)n_gpr
, (int)n_fpr
, off
);
9677 t
= fold_build_pointer_plus_hwi (t
, off
);
9679 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9680 TREE_SIDE_EFFECTS (t
) = 1;
9681 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9684 /* Find the register save area. */
9685 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
9686 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
9688 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
9689 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
9691 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9692 TREE_SIDE_EFFECTS (t
) = 1;
9693 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9697 /* Implement va_arg by updating the va_list structure
9698 VALIST as required to retrieve an argument of type
9699 TYPE, and returning that argument.
9701 Generates code equivalent to:
9703 if (integral value) {
9704 if (size <= 4 && args.gpr < 5 ||
9705 size > 4 && args.gpr < 4 )
9706 ret = args.reg_save_area[args.gpr+8]
9708 ret = *args.overflow_arg_area++;
9709 } else if (float value) {
9711 ret = args.reg_save_area[args.fpr+64]
9713 ret = *args.overflow_arg_area++;
9714 } else if (aggregate value) {
9716 ret = *args.reg_save_area[args.gpr]
9718 ret = **args.overflow_arg_area++;
9722 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9723 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
9725 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9726 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9727 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
9728 tree lab_false
, lab_over
, addr
;
9730 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9731 f_fpr
= DECL_CHAIN (f_gpr
);
9732 f_ovf
= DECL_CHAIN (f_fpr
);
9733 f_sav
= DECL_CHAIN (f_ovf
);
9735 valist
= build_va_arg_indirect_ref (valist
);
9736 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9737 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9738 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9740 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9741 both appear on a lhs. */
9742 valist
= unshare_expr (valist
);
9743 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9745 size
= int_size_in_bytes (type
);
9747 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9749 if (TARGET_DEBUG_ARG
)
9751 fprintf (stderr
, "va_arg: aggregate type");
9755 /* Aggregates are passed by reference. */
9760 /* kernel stack layout on 31 bit: It is assumed here that no padding
9761 will be added by s390_frame_info because for va_args always an even
9762 number of gprs has to be saved r15-r2 = 14 regs. */
9763 sav_ofs
= 2 * UNITS_PER_LONG
;
9764 sav_scale
= UNITS_PER_LONG
;
9765 size
= UNITS_PER_LONG
;
9766 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9768 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9770 if (TARGET_DEBUG_ARG
)
9772 fprintf (stderr
, "va_arg: float type");
9776 /* FP args go in FP registers, if present. */
9780 sav_ofs
= 16 * UNITS_PER_LONG
;
9782 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9786 if (TARGET_DEBUG_ARG
)
9788 fprintf (stderr
, "va_arg: other type");
9792 /* Otherwise into GP registers. */
9795 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9797 /* kernel stack layout on 31 bit: It is assumed here that no padding
9798 will be added by s390_frame_info because for va_args always an even
9799 number of gprs has to be saved r15-r2 = 14 regs. */
9800 sav_ofs
= 2 * UNITS_PER_LONG
;
9802 if (size
< UNITS_PER_LONG
)
9803 sav_ofs
+= UNITS_PER_LONG
- size
;
9805 sav_scale
= UNITS_PER_LONG
;
9806 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9809 /* Pull the value out of the saved registers ... */
9811 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9812 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9813 addr
= create_tmp_var (ptr_type_node
, "addr");
9815 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9816 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9817 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9818 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9819 gimplify_and_add (t
, pre_p
);
9821 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9822 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9823 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9824 t
= fold_build_pointer_plus (t
, u
);
9826 gimplify_assign (addr
, t
, pre_p
);
9828 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9830 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9833 /* ... Otherwise out of the overflow area. */
9836 if (size
< UNITS_PER_LONG
)
9837 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
9839 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9841 gimplify_assign (addr
, t
, pre_p
);
9843 t
= fold_build_pointer_plus_hwi (t
, size
);
9844 gimplify_assign (ovf
, t
, pre_p
);
9846 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9849 /* Increment register save count. */
9851 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9852 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9853 gimplify_and_add (u
, pre_p
);
9857 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9859 addr
= fold_convert (t
, addr
);
9860 addr
= build_va_arg_indirect_ref (addr
);
9864 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9865 addr
= fold_convert (t
, addr
);
9868 return build_va_arg_indirect_ref (addr
);
9871 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9873 DEST - Register location where CC will be stored.
9874 TDB - Pointer to a 256 byte area where to store the transaction.
9875 diagnostic block. NULL if TDB is not needed.
9876 RETRY - Retry count value. If non-NULL a retry loop for CC2
9878 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9879 of the tbegin instruction pattern. */
9882 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
9884 rtx retry_plus_two
= gen_reg_rtx (SImode
);
9885 rtx retry_reg
= gen_reg_rtx (SImode
);
9886 rtx_code_label
*retry_label
= NULL
;
9888 if (retry
!= NULL_RTX
)
9890 emit_move_insn (retry_reg
, retry
);
9891 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
9892 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
9893 retry_label
= gen_label_rtx ();
9894 emit_label (retry_label
);
9898 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
), tdb
));
9900 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
9903 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
9904 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
9907 if (retry
!= NULL_RTX
)
9909 const int CC0
= 1 << 3;
9910 const int CC1
= 1 << 2;
9911 const int CC3
= 1 << 0;
9913 rtx count
= gen_reg_rtx (SImode
);
9914 rtx_code_label
*leave_label
= gen_label_rtx ();
9916 /* Exit for success and permanent failures. */
9917 jump
= s390_emit_jump (leave_label
,
9918 gen_rtx_EQ (VOIDmode
,
9919 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
9920 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
9921 LABEL_NUSES (leave_label
) = 1;
9923 /* CC2 - transient failure. Perform retry with ppa. */
9924 emit_move_insn (count
, retry_plus_two
);
9925 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
9926 emit_insn (gen_tx_assist (count
));
9927 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
9930 JUMP_LABEL (jump
) = retry_label
;
9931 LABEL_NUSES (retry_label
) = 1;
9932 emit_label (leave_label
);
9940 S390_BUILTIN_TBEGIN
,
9941 S390_BUILTIN_TBEGIN_NOFLOAT
,
9942 S390_BUILTIN_TBEGIN_RETRY
,
9943 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT
,
9944 S390_BUILTIN_TBEGINC
,
9946 S390_BUILTIN_TABORT
,
9947 S390_BUILTIN_NON_TX_STORE
,
9948 S390_BUILTIN_TX_NESTING_DEPTH
,
9949 S390_BUILTIN_TX_ASSIST
,
9954 static enum insn_code
const code_for_builtin
[S390_BUILTIN_max
] = {
9956 CODE_FOR_tbegin_nofloat
,
9957 CODE_FOR_tbegin_retry
,
9958 CODE_FOR_tbegin_retry_nofloat
,
9968 s390_init_builtins (void)
9970 tree ftype
, uint64_type
;
9971 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
9973 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
9975 /* void foo (void) */
9976 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
9977 add_builtin_function ("__builtin_tbeginc", ftype
, S390_BUILTIN_TBEGINC
,
9978 BUILT_IN_MD
, NULL
, NULL_TREE
);
9980 /* void foo (int) */
9981 ftype
= build_function_type_list (void_type_node
, integer_type_node
,
9983 add_builtin_function ("__builtin_tabort", ftype
,
9984 S390_BUILTIN_TABORT
, BUILT_IN_MD
, NULL
, noreturn_attr
);
9985 add_builtin_function ("__builtin_tx_assist", ftype
,
9986 S390_BUILTIN_TX_ASSIST
, BUILT_IN_MD
, NULL
, NULL_TREE
);
9988 /* int foo (void *) */
9989 ftype
= build_function_type_list (integer_type_node
, ptr_type_node
, NULL_TREE
);
9990 add_builtin_function ("__builtin_tbegin", ftype
, S390_BUILTIN_TBEGIN
,
9991 BUILT_IN_MD
, NULL
, returns_twice_attr
);
9992 add_builtin_function ("__builtin_tbegin_nofloat", ftype
,
9993 S390_BUILTIN_TBEGIN_NOFLOAT
,
9994 BUILT_IN_MD
, NULL
, returns_twice_attr
);
9996 /* int foo (void *, int) */
9997 ftype
= build_function_type_list (integer_type_node
, ptr_type_node
,
9998 integer_type_node
, NULL_TREE
);
9999 add_builtin_function ("__builtin_tbegin_retry", ftype
,
10000 S390_BUILTIN_TBEGIN_RETRY
,
10002 NULL
, returns_twice_attr
);
10003 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype
,
10004 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT
,
10006 NULL
, returns_twice_attr
);
10008 /* int foo (void) */
10009 ftype
= build_function_type_list (integer_type_node
, NULL_TREE
);
10010 add_builtin_function ("__builtin_tx_nesting_depth", ftype
,
10011 S390_BUILTIN_TX_NESTING_DEPTH
,
10012 BUILT_IN_MD
, NULL
, NULL_TREE
);
10013 add_builtin_function ("__builtin_tend", ftype
,
10014 S390_BUILTIN_TEND
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10016 /* void foo (uint64_t *, uint64_t) */
10018 uint64_type
= long_unsigned_type_node
;
10020 uint64_type
= long_long_unsigned_type_node
;
10022 ftype
= build_function_type_list (void_type_node
,
10023 build_pointer_type (uint64_type
),
10024 uint64_type
, NULL_TREE
);
10025 add_builtin_function ("__builtin_non_tx_store", ftype
,
10026 S390_BUILTIN_NON_TX_STORE
,
10027 BUILT_IN_MD
, NULL
, NULL_TREE
);
10030 /* Expand an expression EXP that calls a built-in function,
10031 with result going to TARGET if that's convenient
10032 (and in mode MODE if that's convenient).
10033 SUBTARGET may be used as the target for computing one of EXP's operands.
10034 IGNORE is nonzero if the value is to be ignored. */
10037 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10038 machine_mode mode ATTRIBUTE_UNUSED
,
10039 int ignore ATTRIBUTE_UNUSED
)
10043 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10044 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10045 enum insn_code icode
;
10046 rtx op
[MAX_ARGS
], pat
;
10050 call_expr_arg_iterator iter
;
10052 if (fcode
>= S390_BUILTIN_max
)
10053 internal_error ("bad builtin fcode");
10054 icode
= code_for_builtin
[fcode
];
10056 internal_error ("bad builtin fcode");
10059 error ("Transactional execution builtins not enabled (-mhtm)\n");
10061 /* Set a flag in the machine specific cfun part in order to support
10062 saving/restoring of FPRs. */
10063 if (fcode
== S390_BUILTIN_TBEGIN
|| fcode
== S390_BUILTIN_TBEGIN_RETRY
)
10064 cfun
->machine
->tbegin_p
= true;
10066 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10069 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10071 const struct insn_operand_data
*insn_op
;
10073 if (arg
== error_mark_node
)
10075 if (arity
>= MAX_ARGS
)
10078 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
10080 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
10082 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
10084 if (insn_op
->predicate
== memory_operand
)
10086 /* Don't move a NULL pointer into a register. Otherwise
10087 we have to rely on combine being able to move it back
10088 in order to get an immediate 0 in the instruction. */
10089 if (op
[arity
] != const0_rtx
)
10090 op
[arity
] = copy_to_mode_reg (Pmode
, op
[arity
]);
10091 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
10094 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
10102 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10104 || GET_MODE (target
) != tmode
10105 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10106 target
= gen_reg_rtx (tmode
);
10112 pat
= GEN_FCN (icode
) (target
);
10116 pat
= GEN_FCN (icode
) (target
, op
[0]);
10118 pat
= GEN_FCN (icode
) (op
[0]);
10122 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
10124 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10127 gcc_unreachable ();
10139 /* We call mcount before the function prologue. So a profiled leaf
10140 function should stay a leaf function. */
10143 s390_keep_leaf_when_profiled ()
10148 /* Output assembly code for the trampoline template to
10151 On S/390, we use gpr 1 internally in the trampoline code;
10152 gpr 0 is used to hold the static chain. */
10155 s390_asm_trampoline_template (FILE *file
)
10158 op
[0] = gen_rtx_REG (Pmode
, 0);
10159 op
[1] = gen_rtx_REG (Pmode
, 1);
10163 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
10164 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
10165 output_asm_insn ("br\t%1", op
); /* 2 byte */
10166 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
10170 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
10171 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
10172 output_asm_insn ("br\t%1", op
); /* 2 byte */
10173 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
10177 /* Emit RTL insns to initialize the variable parts of a trampoline.
10178 FNADDR is an RTX for the address of the function's pure code.
10179 CXT is an RTX for the static chain value for the function. */
10182 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
10184 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10187 emit_block_move (m_tramp
, assemble_trampoline_template (),
10188 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
10190 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
10191 emit_move_insn (mem
, cxt
);
10192 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
10193 emit_move_insn (mem
, fnaddr
);
10196 /* Output assembler code to FILE to increment profiler label # LABELNO
10197 for profiling a function entry. */
10200 s390_function_profiler (FILE *file
, int labelno
)
10205 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
10207 fprintf (file
, "# function profiler \n");
10209 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10210 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
10211 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
10213 op
[2] = gen_rtx_REG (Pmode
, 1);
10214 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
10215 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
10217 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
10220 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
10221 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
10226 output_asm_insn ("stg\t%0,%1", op
);
10227 output_asm_insn ("larl\t%2,%3", op
);
10228 output_asm_insn ("brasl\t%0,%4", op
);
10229 output_asm_insn ("lg\t%0,%1", op
);
10231 else if (!flag_pic
)
10233 op
[6] = gen_label_rtx ();
10235 output_asm_insn ("st\t%0,%1", op
);
10236 output_asm_insn ("bras\t%2,%l6", op
);
10237 output_asm_insn (".long\t%4", op
);
10238 output_asm_insn (".long\t%3", op
);
10239 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
10240 output_asm_insn ("l\t%0,0(%2)", op
);
10241 output_asm_insn ("l\t%2,4(%2)", op
);
10242 output_asm_insn ("basr\t%0,%0", op
);
10243 output_asm_insn ("l\t%0,%1", op
);
10247 op
[5] = gen_label_rtx ();
10248 op
[6] = gen_label_rtx ();
10250 output_asm_insn ("st\t%0,%1", op
);
10251 output_asm_insn ("bras\t%2,%l6", op
);
10252 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
10253 output_asm_insn (".long\t%4-%l5", op
);
10254 output_asm_insn (".long\t%3-%l5", op
);
10255 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
10256 output_asm_insn ("lr\t%0,%2", op
);
10257 output_asm_insn ("a\t%0,0(%2)", op
);
10258 output_asm_insn ("a\t%2,4(%2)", op
);
10259 output_asm_insn ("basr\t%0,%0", op
);
10260 output_asm_insn ("l\t%0,%1", op
);
10264 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10265 into its SYMBOL_REF_FLAGS. */
10268 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
10270 default_encode_section_info (decl
, rtl
, first
);
10272 if (TREE_CODE (decl
) == VAR_DECL
)
10274 /* If a variable has a forced alignment to < 2 bytes, mark it
10275 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10277 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
10278 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
10279 if (!DECL_SIZE (decl
)
10280 || !DECL_ALIGN (decl
)
10281 || !tree_fits_shwi_p (DECL_SIZE (decl
))
10282 || (DECL_ALIGN (decl
) <= 64
10283 && DECL_ALIGN (decl
) != tree_to_shwi (DECL_SIZE (decl
))))
10284 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
10287 /* Literal pool references don't have a decl so they are handled
10288 differently here. We rely on the information in the MEM_ALIGN
10289 entry to decide upon natural alignment. */
10291 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
10292 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
10293 && (MEM_ALIGN (rtl
) == 0
10294 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
10295 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
10296 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
10299 /* Output thunk to FILE that implements a C++ virtual function call (with
10300 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10301 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10302 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10303 relative to the resulting this pointer. */
10306 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10307 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10313 /* Make sure unwind info is emitted for the thunk if needed. */
10314 final_start_function (emit_barrier (), file
, 1);
10316 /* Operand 0 is the target function. */
10317 op
[0] = XEXP (DECL_RTL (function
), 0);
10318 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
10321 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
10322 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
10323 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
10326 /* Operand 1 is the 'this' pointer. */
10327 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10328 op
[1] = gen_rtx_REG (Pmode
, 3);
10330 op
[1] = gen_rtx_REG (Pmode
, 2);
10332 /* Operand 2 is the delta. */
10333 op
[2] = GEN_INT (delta
);
10335 /* Operand 3 is the vcall_offset. */
10336 op
[3] = GEN_INT (vcall_offset
);
10338 /* Operand 4 is the temporary register. */
10339 op
[4] = gen_rtx_REG (Pmode
, 1);
10341 /* Operands 5 to 8 can be used as labels. */
10347 /* Operand 9 can be used for temporary register. */
10350 /* Generate code. */
10353 /* Setup literal pool pointer if required. */
10354 if ((!DISP_IN_RANGE (delta
)
10355 && !CONST_OK_FOR_K (delta
)
10356 && !CONST_OK_FOR_Os (delta
))
10357 || (!DISP_IN_RANGE (vcall_offset
)
10358 && !CONST_OK_FOR_K (vcall_offset
)
10359 && !CONST_OK_FOR_Os (vcall_offset
)))
10361 op
[5] = gen_label_rtx ();
10362 output_asm_insn ("larl\t%4,%5", op
);
10365 /* Add DELTA to this pointer. */
10368 if (CONST_OK_FOR_J (delta
))
10369 output_asm_insn ("la\t%1,%2(%1)", op
);
10370 else if (DISP_IN_RANGE (delta
))
10371 output_asm_insn ("lay\t%1,%2(%1)", op
);
10372 else if (CONST_OK_FOR_K (delta
))
10373 output_asm_insn ("aghi\t%1,%2", op
);
10374 else if (CONST_OK_FOR_Os (delta
))
10375 output_asm_insn ("agfi\t%1,%2", op
);
10378 op
[6] = gen_label_rtx ();
10379 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
10383 /* Perform vcall adjustment. */
10386 if (DISP_IN_RANGE (vcall_offset
))
10388 output_asm_insn ("lg\t%4,0(%1)", op
);
10389 output_asm_insn ("ag\t%1,%3(%4)", op
);
10391 else if (CONST_OK_FOR_K (vcall_offset
))
10393 output_asm_insn ("lghi\t%4,%3", op
);
10394 output_asm_insn ("ag\t%4,0(%1)", op
);
10395 output_asm_insn ("ag\t%1,0(%4)", op
);
10397 else if (CONST_OK_FOR_Os (vcall_offset
))
10399 output_asm_insn ("lgfi\t%4,%3", op
);
10400 output_asm_insn ("ag\t%4,0(%1)", op
);
10401 output_asm_insn ("ag\t%1,0(%4)", op
);
10405 op
[7] = gen_label_rtx ();
10406 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
10407 output_asm_insn ("ag\t%4,0(%1)", op
);
10408 output_asm_insn ("ag\t%1,0(%4)", op
);
10412 /* Jump to target. */
10413 output_asm_insn ("jg\t%0", op
);
10415 /* Output literal pool if required. */
10418 output_asm_insn (".align\t4", op
);
10419 targetm
.asm_out
.internal_label (file
, "L",
10420 CODE_LABEL_NUMBER (op
[5]));
10424 targetm
.asm_out
.internal_label (file
, "L",
10425 CODE_LABEL_NUMBER (op
[6]));
10426 output_asm_insn (".long\t%2", op
);
10430 targetm
.asm_out
.internal_label (file
, "L",
10431 CODE_LABEL_NUMBER (op
[7]));
10432 output_asm_insn (".long\t%3", op
);
10437 /* Setup base pointer if required. */
10439 || (!DISP_IN_RANGE (delta
)
10440 && !CONST_OK_FOR_K (delta
)
10441 && !CONST_OK_FOR_Os (delta
))
10442 || (!DISP_IN_RANGE (delta
)
10443 && !CONST_OK_FOR_K (vcall_offset
)
10444 && !CONST_OK_FOR_Os (vcall_offset
)))
10446 op
[5] = gen_label_rtx ();
10447 output_asm_insn ("basr\t%4,0", op
);
10448 targetm
.asm_out
.internal_label (file
, "L",
10449 CODE_LABEL_NUMBER (op
[5]));
10452 /* Add DELTA to this pointer. */
10455 if (CONST_OK_FOR_J (delta
))
10456 output_asm_insn ("la\t%1,%2(%1)", op
);
10457 else if (DISP_IN_RANGE (delta
))
10458 output_asm_insn ("lay\t%1,%2(%1)", op
);
10459 else if (CONST_OK_FOR_K (delta
))
10460 output_asm_insn ("ahi\t%1,%2", op
);
10461 else if (CONST_OK_FOR_Os (delta
))
10462 output_asm_insn ("afi\t%1,%2", op
);
10465 op
[6] = gen_label_rtx ();
10466 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
10470 /* Perform vcall adjustment. */
10473 if (CONST_OK_FOR_J (vcall_offset
))
10475 output_asm_insn ("l\t%4,0(%1)", op
);
10476 output_asm_insn ("a\t%1,%3(%4)", op
);
10478 else if (DISP_IN_RANGE (vcall_offset
))
10480 output_asm_insn ("l\t%4,0(%1)", op
);
10481 output_asm_insn ("ay\t%1,%3(%4)", op
);
10483 else if (CONST_OK_FOR_K (vcall_offset
))
10485 output_asm_insn ("lhi\t%4,%3", op
);
10486 output_asm_insn ("a\t%4,0(%1)", op
);
10487 output_asm_insn ("a\t%1,0(%4)", op
);
10489 else if (CONST_OK_FOR_Os (vcall_offset
))
10491 output_asm_insn ("iilf\t%4,%3", op
);
10492 output_asm_insn ("a\t%4,0(%1)", op
);
10493 output_asm_insn ("a\t%1,0(%4)", op
);
10497 op
[7] = gen_label_rtx ();
10498 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
10499 output_asm_insn ("a\t%4,0(%1)", op
);
10500 output_asm_insn ("a\t%1,0(%4)", op
);
10503 /* We had to clobber the base pointer register.
10504 Re-setup the base pointer (with a different base). */
10505 op
[5] = gen_label_rtx ();
10506 output_asm_insn ("basr\t%4,0", op
);
10507 targetm
.asm_out
.internal_label (file
, "L",
10508 CODE_LABEL_NUMBER (op
[5]));
10511 /* Jump to target. */
10512 op
[8] = gen_label_rtx ();
10515 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
10516 else if (!nonlocal
)
10517 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10518 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10519 else if (flag_pic
== 1)
10521 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10522 output_asm_insn ("l\t%4,%0(%4)", op
);
10524 else if (flag_pic
== 2)
10526 op
[9] = gen_rtx_REG (Pmode
, 0);
10527 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
10528 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
10529 output_asm_insn ("ar\t%4,%9", op
);
10530 output_asm_insn ("l\t%4,0(%4)", op
);
10533 output_asm_insn ("br\t%4", op
);
10535 /* Output literal pool. */
10536 output_asm_insn (".align\t4", op
);
10538 if (nonlocal
&& flag_pic
== 2)
10539 output_asm_insn (".long\t%0", op
);
10542 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
10543 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
10546 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
10548 output_asm_insn (".long\t%0", op
);
10550 output_asm_insn (".long\t%0-%5", op
);
10554 targetm
.asm_out
.internal_label (file
, "L",
10555 CODE_LABEL_NUMBER (op
[6]));
10556 output_asm_insn (".long\t%2", op
);
10560 targetm
.asm_out
.internal_label (file
, "L",
10561 CODE_LABEL_NUMBER (op
[7]));
10562 output_asm_insn (".long\t%3", op
);
10565 final_end_function ();
10569 s390_valid_pointer_mode (machine_mode mode
)
10571 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
10574 /* Checks whether the given CALL_EXPR would use a caller
10575 saved register. This is used to decide whether sibling call
10576 optimization could be performed on the respective function
10580 s390_call_saved_register_used (tree call_expr
)
10582 CUMULATIVE_ARGS cum_v
;
10583 cumulative_args_t cum
;
10590 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
10591 cum
= pack_cumulative_args (&cum_v
);
10593 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
10595 parameter
= CALL_EXPR_ARG (call_expr
, i
);
10596 gcc_assert (parameter
);
10598 /* For an undeclared variable passed as parameter we will get
10599 an ERROR_MARK node here. */
10600 if (TREE_CODE (parameter
) == ERROR_MARK
)
10603 type
= TREE_TYPE (parameter
);
10606 mode
= TYPE_MODE (type
);
10609 if (pass_by_reference (&cum_v
, mode
, type
, true))
10612 type
= build_pointer_type (type
);
10615 parm_rtx
= s390_function_arg (cum
, mode
, type
, 0);
10617 s390_function_arg_advance (cum
, mode
, type
, 0);
10622 if (REG_P (parm_rtx
))
10625 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
10627 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
10631 if (GET_CODE (parm_rtx
) == PARALLEL
)
10635 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
10637 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
10639 gcc_assert (REG_P (r
));
10642 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
10644 if (!call_used_regs
[reg
+ REGNO (r
)])
10653 /* Return true if the given call expression can be
10654 turned into a sibling call.
10655 DECL holds the declaration of the function to be called whereas
10656 EXP is the call expression itself. */
10659 s390_function_ok_for_sibcall (tree decl
, tree exp
)
10661 /* The TPF epilogue uses register 1. */
10662 if (TARGET_TPF_PROFILING
)
10665 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10666 which would have to be restored before the sibcall. */
10667 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
10670 /* Register 6 on s390 is available as an argument register but unfortunately
10671 "caller saved". This makes functions needing this register for arguments
10672 not suitable for sibcalls. */
10673 return !s390_call_saved_register_used (exp
);
10676 /* Return the fixed registers used for condition codes. */
10679 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
10682 *p2
= INVALID_REGNUM
;
10687 /* This function is used by the call expanders of the machine description.
10688 It emits the call insn itself together with the necessary operations
10689 to adjust the target address and returns the emitted insn.
10690 ADDR_LOCATION is the target address rtx
10691 TLS_CALL the location of the thread-local symbol
10692 RESULT_REG the register where the result of the call should be stored
10693 RETADDR_REG the register where the return address should be stored
10694 If this parameter is NULL_RTX the call is considered
10695 to be a sibling call. */
10698 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
10701 bool plt_call
= false;
10707 /* Direct function calls need special treatment. */
10708 if (GET_CODE (addr_location
) == SYMBOL_REF
)
10710 /* When calling a global routine in PIC mode, we must
10711 replace the symbol itself with the PLT stub. */
10712 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
10714 if (retaddr_reg
!= NULL_RTX
)
10716 addr_location
= gen_rtx_UNSPEC (Pmode
,
10717 gen_rtvec (1, addr_location
),
10719 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
10723 /* For -fpic code the PLT entries might use r12 which is
10724 call-saved. Therefore we cannot do a sibcall when
10725 calling directly using a symbol ref. When reaching
10726 this point we decided (in s390_function_ok_for_sibcall)
10727 to do a sibcall for a function pointer but one of the
10728 optimizers was able to get rid of the function pointer
10729 by propagating the symbol ref into the call. This
10730 optimization is illegal for S/390 so we turn the direct
10731 call into a indirect call again. */
10732 addr_location
= force_reg (Pmode
, addr_location
);
10735 /* Unless we can use the bras(l) insn, force the
10736 routine address into a register. */
10737 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
10740 addr_location
= legitimize_pic_address (addr_location
, 0);
10742 addr_location
= force_reg (Pmode
, addr_location
);
10746 /* If it is already an indirect call or the code above moved the
10747 SYMBOL_REF to somewhere else make sure the address can be found in
10749 if (retaddr_reg
== NULL_RTX
10750 && GET_CODE (addr_location
) != SYMBOL_REF
10753 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
10754 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
10757 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
10758 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
10760 if (result_reg
!= NULL_RTX
)
10761 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
10763 if (retaddr_reg
!= NULL_RTX
)
10765 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
10767 if (tls_call
!= NULL_RTX
)
10768 vec
= gen_rtvec (3, call
, clobber
,
10769 gen_rtx_USE (VOIDmode
, tls_call
));
10771 vec
= gen_rtvec (2, call
, clobber
);
10773 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
10776 insn
= emit_call_insn (call
);
10778 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10779 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
10781 /* s390_function_ok_for_sibcall should
10782 have denied sibcalls in this case. */
10783 gcc_assert (retaddr_reg
!= NULL_RTX
);
10784 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
10789 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10792 s390_conditional_register_usage (void)
10798 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10799 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10801 if (TARGET_CPU_ZARCH
)
10803 fixed_regs
[BASE_REGNUM
] = 0;
10804 call_used_regs
[BASE_REGNUM
] = 0;
10805 fixed_regs
[RETURN_REGNUM
] = 0;
10806 call_used_regs
[RETURN_REGNUM
] = 0;
10810 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10811 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
10815 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
10816 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
10819 if (TARGET_SOFT_FLOAT
)
10821 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10822 call_used_regs
[i
] = fixed_regs
[i
] = 1;
10826 /* Corresponding function to eh_return expander. */
10828 static GTY(()) rtx s390_tpf_eh_return_symbol
;
10830 s390_emit_tpf_eh_return (rtx target
)
10835 if (!s390_tpf_eh_return_symbol
)
10836 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
10838 reg
= gen_rtx_REG (Pmode
, 2);
10839 orig_ra
= gen_rtx_REG (Pmode
, 3);
10841 emit_move_insn (reg
, target
);
10842 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
10843 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
10844 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
10845 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
10846 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
10848 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
10851 /* Rework the prologue/epilogue to avoid saving/restoring
10852 registers unnecessarily. */
10855 s390_optimize_prologue (void)
10857 rtx_insn
*insn
, *new_insn
, *next_insn
;
10859 /* Do a final recompute of the frame-related data. */
10860 s390_optimize_register_info ();
10862 /* If all special registers are in fact used, there's nothing we
10863 can do, so no point in walking the insn list. */
10865 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
10866 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
10867 && (TARGET_CPU_ZARCH
10868 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
10869 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
10872 /* Search for prologue/epilogue insns and replace them. */
10874 for (insn
= get_insns (); insn
; insn
= next_insn
)
10876 int first
, last
, off
;
10877 rtx set
, base
, offset
;
10880 next_insn
= NEXT_INSN (insn
);
10882 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
10885 pat
= PATTERN (insn
);
10887 /* Remove ldgr/lgdr instructions used for saving and restore
10888 GPRs if possible. */
10890 && GET_CODE (pat
) == SET
10891 && GET_MODE (SET_SRC (pat
)) == DImode
10892 && REG_P (SET_SRC (pat
))
10893 && REG_P (SET_DEST (pat
)))
10895 int src_regno
= REGNO (SET_SRC (pat
));
10896 int dest_regno
= REGNO (SET_DEST (pat
));
10900 if (!((GENERAL_REGNO_P (src_regno
) && FP_REGNO_P (dest_regno
))
10901 || (FP_REGNO_P (src_regno
) && GENERAL_REGNO_P (dest_regno
))))
10904 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
10905 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
10907 /* GPR must be call-saved, FPR must be call-clobbered. */
10908 if (!call_really_used_regs
[fpr_regno
]
10909 || call_really_used_regs
[gpr_regno
])
10912 /* It must not happen that what we once saved in an FPR now
10913 needs a stack slot. */
10914 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != -1);
10916 if (cfun_gpr_save_slot (gpr_regno
) == 0)
10918 remove_insn (insn
);
10923 if (GET_CODE (pat
) == PARALLEL
10924 && store_multiple_operation (pat
, VOIDmode
))
10926 set
= XVECEXP (pat
, 0, 0);
10927 first
= REGNO (SET_SRC (set
));
10928 last
= first
+ XVECLEN (pat
, 0) - 1;
10929 offset
= const0_rtx
;
10930 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10931 off
= INTVAL (offset
);
10933 if (GET_CODE (base
) != REG
|| off
< 0)
10935 if (cfun_frame_layout
.first_save_gpr
!= -1
10936 && (cfun_frame_layout
.first_save_gpr
< first
10937 || cfun_frame_layout
.last_save_gpr
> last
))
10939 if (REGNO (base
) != STACK_POINTER_REGNUM
10940 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10942 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10945 if (cfun_frame_layout
.first_save_gpr
!= -1)
10947 rtx s_pat
= save_gprs (base
,
10948 off
+ (cfun_frame_layout
.first_save_gpr
10949 - first
) * UNITS_PER_LONG
,
10950 cfun_frame_layout
.first_save_gpr
,
10951 cfun_frame_layout
.last_save_gpr
);
10952 new_insn
= emit_insn_before (s_pat
, insn
);
10953 INSN_ADDRESSES_NEW (new_insn
, -1);
10956 remove_insn (insn
);
10960 if (cfun_frame_layout
.first_save_gpr
== -1
10961 && GET_CODE (pat
) == SET
10962 && GENERAL_REG_P (SET_SRC (pat
))
10963 && GET_CODE (SET_DEST (pat
)) == MEM
)
10966 first
= REGNO (SET_SRC (set
));
10967 offset
= const0_rtx
;
10968 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10969 off
= INTVAL (offset
);
10971 if (GET_CODE (base
) != REG
|| off
< 0)
10973 if (REGNO (base
) != STACK_POINTER_REGNUM
10974 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10977 remove_insn (insn
);
10981 if (GET_CODE (pat
) == PARALLEL
10982 && load_multiple_operation (pat
, VOIDmode
))
10984 set
= XVECEXP (pat
, 0, 0);
10985 first
= REGNO (SET_DEST (set
));
10986 last
= first
+ XVECLEN (pat
, 0) - 1;
10987 offset
= const0_rtx
;
10988 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10989 off
= INTVAL (offset
);
10991 if (GET_CODE (base
) != REG
|| off
< 0)
10994 if (cfun_frame_layout
.first_restore_gpr
!= -1
10995 && (cfun_frame_layout
.first_restore_gpr
< first
10996 || cfun_frame_layout
.last_restore_gpr
> last
))
10998 if (REGNO (base
) != STACK_POINTER_REGNUM
10999 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
11001 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
11004 if (cfun_frame_layout
.first_restore_gpr
!= -1)
11006 rtx rpat
= restore_gprs (base
,
11007 off
+ (cfun_frame_layout
.first_restore_gpr
11008 - first
) * UNITS_PER_LONG
,
11009 cfun_frame_layout
.first_restore_gpr
,
11010 cfun_frame_layout
.last_restore_gpr
);
11012 /* Remove REG_CFA_RESTOREs for registers that we no
11013 longer need to save. */
11014 REG_NOTES (rpat
) = REG_NOTES (insn
);
11015 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
11016 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
11017 && ((int) REGNO (XEXP (*ptr
, 0))
11018 < cfun_frame_layout
.first_restore_gpr
))
11019 *ptr
= XEXP (*ptr
, 1);
11021 ptr
= &XEXP (*ptr
, 1);
11022 new_insn
= emit_insn_before (rpat
, insn
);
11023 RTX_FRAME_RELATED_P (new_insn
) = 1;
11024 INSN_ADDRESSES_NEW (new_insn
, -1);
11027 remove_insn (insn
);
11031 if (cfun_frame_layout
.first_restore_gpr
== -1
11032 && GET_CODE (pat
) == SET
11033 && GENERAL_REG_P (SET_DEST (pat
))
11034 && GET_CODE (SET_SRC (pat
)) == MEM
)
11037 first
= REGNO (SET_DEST (set
));
11038 offset
= const0_rtx
;
11039 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
11040 off
= INTVAL (offset
);
11042 if (GET_CODE (base
) != REG
|| off
< 0)
11045 if (REGNO (base
) != STACK_POINTER_REGNUM
11046 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
11049 remove_insn (insn
);
11055 /* On z10 and later the dynamic branch prediction must see the
11056 backward jump within a certain windows. If not it falls back to
11057 the static prediction. This function rearranges the loop backward
11058 branch in a way which makes the static prediction always correct.
11059 The function returns true if it added an instruction. */
11061 s390_fix_long_loop_prediction (rtx_insn
*insn
)
11063 rtx set
= single_set (insn
);
11064 rtx code_label
, label_ref
, new_label
;
11065 rtx_insn
*uncond_jump
;
11066 rtx_insn
*cur_insn
;
11070 /* This will exclude branch on count and branch on index patterns
11071 since these are correctly statically predicted. */
11073 || SET_DEST (set
) != pc_rtx
11074 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
11077 /* Skip conditional returns. */
11078 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
11079 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
11082 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
11083 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
11085 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
11087 code_label
= XEXP (label_ref
, 0);
11089 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
11090 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
11091 || (INSN_ADDRESSES (INSN_UID (insn
))
11092 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
11095 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
11096 distance
< PREDICT_DISTANCE
- 6;
11097 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
11098 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
11101 new_label
= gen_label_rtx ();
11102 uncond_jump
= emit_jump_insn_after (
11103 gen_rtx_SET (VOIDmode
, pc_rtx
,
11104 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
11106 emit_label_after (new_label
, uncond_jump
);
11108 tmp
= XEXP (SET_SRC (set
), 1);
11109 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
11110 XEXP (SET_SRC (set
), 2) = tmp
;
11111 INSN_CODE (insn
) = -1;
11113 XEXP (label_ref
, 0) = new_label
;
11114 JUMP_LABEL (insn
) = new_label
;
11115 JUMP_LABEL (uncond_jump
) = code_label
;
11120 /* Returns 1 if INSN reads the value of REG for purposes not related
11121 to addressing of memory, and 0 otherwise. */
11123 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
11125 return reg_referenced_p (reg
, PATTERN (insn
))
11126 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
11129 /* Starting from INSN find_cond_jump looks downwards in the insn
11130 stream for a single jump insn which is the last user of the
11131 condition code set in INSN. */
11133 find_cond_jump (rtx_insn
*insn
)
11135 for (; insn
; insn
= NEXT_INSN (insn
))
11139 if (LABEL_P (insn
))
11142 if (!JUMP_P (insn
))
11144 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
11149 /* This will be triggered by a return. */
11150 if (GET_CODE (PATTERN (insn
)) != SET
)
11153 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
11154 ite
= SET_SRC (PATTERN (insn
));
11156 if (GET_CODE (ite
) != IF_THEN_ELSE
)
11159 cc
= XEXP (XEXP (ite
, 0), 0);
11160 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
11163 if (find_reg_note (insn
, REG_DEAD
, cc
))
11171 /* Swap the condition in COND and the operands in OP0 and OP1 so that
11172 the semantics does not change. If NULL_RTX is passed as COND the
11173 function tries to find the conditional jump starting with INSN. */
11175 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
11179 if (cond
== NULL_RTX
)
11181 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
11182 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
11184 if (set
== NULL_RTX
)
11187 cond
= XEXP (SET_SRC (set
), 0);
11192 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
11195 /* On z10, instructions of the compare-and-branch family have the
11196 property to access the register occurring as second operand with
11197 its bits complemented. If such a compare is grouped with a second
11198 instruction that accesses the same register non-complemented, and
11199 if that register's value is delivered via a bypass, then the
11200 pipeline recycles, thereby causing significant performance decline.
11201 This function locates such situations and exchanges the two
11202 operands of the compare. The function return true whenever it
11205 s390_z10_optimize_cmp (rtx_insn
*insn
)
11207 rtx_insn
*prev_insn
, *next_insn
;
11208 bool insn_added_p
= false;
11209 rtx cond
, *op0
, *op1
;
11211 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
11213 /* Handle compare and branch and branch on count
11215 rtx pattern
= single_set (insn
);
11218 || SET_DEST (pattern
) != pc_rtx
11219 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
11222 cond
= XEXP (SET_SRC (pattern
), 0);
11223 op0
= &XEXP (cond
, 0);
11224 op1
= &XEXP (cond
, 1);
11226 else if (GET_CODE (PATTERN (insn
)) == SET
)
11230 /* Handle normal compare instructions. */
11231 src
= SET_SRC (PATTERN (insn
));
11232 dest
= SET_DEST (PATTERN (insn
));
11235 || !CC_REGNO_P (REGNO (dest
))
11236 || GET_CODE (src
) != COMPARE
)
11239 /* s390_swap_cmp will try to find the conditional
11240 jump when passing NULL_RTX as condition. */
11242 op0
= &XEXP (src
, 0);
11243 op1
= &XEXP (src
, 1);
11248 if (!REG_P (*op0
) || !REG_P (*op1
))
11251 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
11254 /* Swap the COMPARE arguments and its mask if there is a
11255 conflicting access in the previous insn. */
11256 prev_insn
= prev_active_insn (insn
);
11257 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
11258 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
11259 s390_swap_cmp (cond
, op0
, op1
, insn
);
11261 /* Check if there is a conflict with the next insn. If there
11262 was no conflict with the previous insn, then swap the
11263 COMPARE arguments and its mask. If we already swapped
11264 the operands, or if swapping them would cause a conflict
11265 with the previous insn, issue a NOP after the COMPARE in
11266 order to separate the two instuctions. */
11267 next_insn
= next_active_insn (insn
);
11268 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
11269 && s390_non_addr_reg_read_p (*op1
, next_insn
))
11271 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
11272 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
11274 if (REGNO (*op1
) == 0)
11275 emit_insn_after (gen_nop1 (), insn
);
11277 emit_insn_after (gen_nop (), insn
);
11278 insn_added_p
= true;
11281 s390_swap_cmp (cond
, op0
, op1
, insn
);
11283 return insn_added_p
;
11286 /* Perform machine-dependent processing. */
11291 bool pool_overflow
= false;
11293 /* Make sure all splits have been performed; splits after
11294 machine_dependent_reorg might confuse insn length counts. */
11295 split_all_insns_noflow ();
11297 /* Install the main literal pool and the associated base
11298 register load insns.
11300 In addition, there are two problematic situations we need
11303 - the literal pool might be > 4096 bytes in size, so that
11304 some of its elements cannot be directly accessed
11306 - a branch target might be > 64K away from the branch, so that
11307 it is not possible to use a PC-relative instruction.
11309 To fix those, we split the single literal pool into multiple
11310 pool chunks, reloading the pool base register at various
11311 points throughout the function to ensure it always points to
11312 the pool chunk the following code expects, and / or replace
11313 PC-relative branches by absolute branches.
11315 However, the two problems are interdependent: splitting the
11316 literal pool can move a branch further away from its target,
11317 causing the 64K limit to overflow, and on the other hand,
11318 replacing a PC-relative branch by an absolute branch means
11319 we need to put the branch target address into the literal
11320 pool, possibly causing it to overflow.
11322 So, we loop trying to fix up both problems until we manage
11323 to satisfy both conditions at the same time. Note that the
11324 loop is guaranteed to terminate as every pass of the loop
11325 strictly decreases the total number of PC-relative branches
11326 in the function. (This is not completely true as there
11327 might be branch-over-pool insns introduced by chunkify_start.
11328 Those never need to be split however.) */
11332 struct constant_pool
*pool
= NULL
;
11334 /* Collect the literal pool. */
11335 if (!pool_overflow
)
11337 pool
= s390_mainpool_start ();
11339 pool_overflow
= true;
11342 /* If literal pool overflowed, start to chunkify it. */
11344 pool
= s390_chunkify_start ();
11346 /* Split out-of-range branches. If this has created new
11347 literal pool entries, cancel current chunk list and
11348 recompute it. zSeries machines have large branch
11349 instructions, so we never need to split a branch. */
11350 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
11353 s390_chunkify_cancel (pool
);
11355 s390_mainpool_cancel (pool
);
11360 /* If we made it up to here, both conditions are satisfied.
11361 Finish up literal pool related changes. */
11363 s390_chunkify_finish (pool
);
11365 s390_mainpool_finish (pool
);
11367 /* We're done splitting branches. */
11368 cfun
->machine
->split_branches_pending_p
= false;
11372 /* Generate out-of-pool execute target insns. */
11373 if (TARGET_CPU_ZARCH
)
11375 rtx_insn
*insn
, *target
;
11378 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11380 label
= s390_execute_label (insn
);
11384 gcc_assert (label
!= const0_rtx
);
11386 target
= emit_label (XEXP (label
, 0));
11387 INSN_ADDRESSES_NEW (target
, -1);
11389 target
= emit_insn (s390_execute_target (insn
));
11390 INSN_ADDRESSES_NEW (target
, -1);
11394 /* Try to optimize prologue and epilogue further. */
11395 s390_optimize_prologue ();
11397 /* Walk over the insns and do some >=z10 specific changes. */
11398 if (s390_tune
== PROCESSOR_2097_Z10
11399 || s390_tune
== PROCESSOR_2817_Z196
11400 || s390_tune
== PROCESSOR_2827_ZEC12
)
11403 bool insn_added_p
= false;
11405 /* The insn lengths and addresses have to be up to date for the
11406 following manipulations. */
11407 shorten_branches (get_insns ());
11409 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11411 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
11415 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
11417 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
11418 || GET_CODE (PATTERN (insn
)) == SET
)
11419 && s390_tune
== PROCESSOR_2097_Z10
)
11420 insn_added_p
|= s390_z10_optimize_cmp (insn
);
11423 /* Adjust branches if we added new instructions. */
11425 shorten_branches (get_insns ());
11429 /* Return true if INSN is a fp load insn writing register REGNO. */
11431 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
11434 enum attr_type flag
= s390_safe_attr_type (insn
);
11436 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
11439 set
= single_set (insn
);
11441 if (set
== NULL_RTX
)
11444 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
11447 if (REGNO (SET_DEST (set
)) != regno
)
11453 /* This value describes the distance to be avoided between an
11454 aritmetic fp instruction and an fp load writing the same register.
11455 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11456 fine but the exact value has to be avoided. Otherwise the FP
11457 pipeline will throw an exception causing a major penalty. */
11458 #define Z10_EARLYLOAD_DISTANCE 7
11460 /* Rearrange the ready list in order to avoid the situation described
11461 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11462 moved to the very end of the ready list. */
11464 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
11466 unsigned int regno
;
11467 int nready
= *nready_p
;
11472 enum attr_type flag
;
11475 /* Skip DISTANCE - 1 active insns. */
11476 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
11477 distance
> 0 && insn
!= NULL_RTX
;
11478 distance
--, insn
= prev_active_insn (insn
))
11479 if (CALL_P (insn
) || JUMP_P (insn
))
11482 if (insn
== NULL_RTX
)
11485 set
= single_set (insn
);
11487 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
11488 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
11491 flag
= s390_safe_attr_type (insn
);
11493 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
11496 regno
= REGNO (SET_DEST (set
));
11499 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
11506 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
11511 /* The s390_sched_state variable tracks the state of the current or
11512 the last instruction group.
11514 0,1,2 number of instructions scheduled in the current group
11515 3 the last group is complete - normal insns
11516 4 the last group was a cracked/expanded insn */
11518 static int s390_sched_state
;
11520 #define S390_OOO_SCHED_STATE_NORMAL 3
11521 #define S390_OOO_SCHED_STATE_CRACKED 4
11523 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11524 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11525 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11526 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11528 static unsigned int
11529 s390_get_sched_attrmask (rtx_insn
*insn
)
11531 unsigned int mask
= 0;
11533 if (get_attr_ooo_cracked (insn
))
11534 mask
|= S390_OOO_SCHED_ATTR_MASK_CRACKED
;
11535 if (get_attr_ooo_expanded (insn
))
11536 mask
|= S390_OOO_SCHED_ATTR_MASK_EXPANDED
;
11537 if (get_attr_ooo_endgroup (insn
))
11538 mask
|= S390_OOO_SCHED_ATTR_MASK_ENDGROUP
;
11539 if (get_attr_ooo_groupalone (insn
))
11540 mask
|= S390_OOO_SCHED_ATTR_MASK_GROUPALONE
;
11544 /* Return the scheduling score for INSN. The higher the score the
11545 better. The score is calculated from the OOO scheduling attributes
11546 of INSN and the scheduling state s390_sched_state. */
11548 s390_sched_score (rtx_insn
*insn
)
11550 unsigned int mask
= s390_get_sched_attrmask (insn
);
11553 switch (s390_sched_state
)
11556 /* Try to put insns into the first slot which would otherwise
11558 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11559 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11561 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11564 /* Prefer not cracked insns while trying to put together a
11566 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11567 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
11568 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
11570 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) == 0)
11574 /* Prefer not cracked insns while trying to put together a
11576 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11577 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
11578 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
11580 /* Prefer endgroup insns in the last slot. */
11581 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0)
11584 case S390_OOO_SCHED_STATE_NORMAL
:
11585 /* Prefer not cracked insns if the last was not cracked. */
11586 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
11587 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0)
11589 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11592 case S390_OOO_SCHED_STATE_CRACKED
:
11593 /* Try to keep cracked insns together to prevent them from
11594 interrupting groups. */
11595 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11596 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11603 /* This function is called via hook TARGET_SCHED_REORDER before
11604 issuing one insn from list READY which contains *NREADYP entries.
11605 For target z10 it reorders load instructions to avoid early load
11606 conflicts in the floating point pipeline */
11608 s390_sched_reorder (FILE *file
, int verbose
,
11609 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
11611 if (s390_tune
== PROCESSOR_2097_Z10
)
11612 if (reload_completed
&& *nreadyp
> 1)
11613 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
11615 if (s390_tune
== PROCESSOR_2827_ZEC12
11616 && reload_completed
11620 int last_index
= *nreadyp
- 1;
11621 int max_index
= -1;
11622 int max_score
= -1;
11625 /* Just move the insn with the highest score to the top (the
11626 end) of the list. A full sort is not needed since a conflict
11627 in the hazard recognition cannot happen. So the top insn in
11628 the ready list will always be taken. */
11629 for (i
= last_index
; i
>= 0; i
--)
11633 if (recog_memoized (ready
[i
]) < 0)
11636 score
= s390_sched_score (ready
[i
]);
11637 if (score
> max_score
)
11644 if (max_index
!= -1)
11646 if (max_index
!= last_index
)
11648 tmp
= ready
[max_index
];
11649 ready
[max_index
] = ready
[last_index
];
11650 ready
[last_index
] = tmp
;
11654 "move insn %d to the top of list\n",
11655 INSN_UID (ready
[last_index
]));
11657 else if (verbose
> 5)
11659 "best insn %d already on top\n",
11660 INSN_UID (ready
[last_index
]));
11665 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
11668 for (i
= last_index
; i
>= 0; i
--)
11670 if (recog_memoized (ready
[i
]) < 0)
11672 fprintf (file
, "insn %d score: %d: ", INSN_UID (ready
[i
]),
11673 s390_sched_score (ready
[i
]));
11674 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11675 PRINT_OOO_ATTR (ooo_cracked
);
11676 PRINT_OOO_ATTR (ooo_expanded
);
11677 PRINT_OOO_ATTR (ooo_endgroup
);
11678 PRINT_OOO_ATTR (ooo_groupalone
);
11679 #undef PRINT_OOO_ATTR
11680 fprintf (file
, "\n");
11685 return s390_issue_rate ();
11689 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11690 the scheduler has issued INSN. It stores the last issued insn into
11691 last_scheduled_insn in order to make it available for
11692 s390_sched_reorder. */
11694 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
11696 last_scheduled_insn
= insn
;
11698 if (s390_tune
== PROCESSOR_2827_ZEC12
11699 && reload_completed
11700 && recog_memoized (insn
) >= 0)
11702 unsigned int mask
= s390_get_sched_attrmask (insn
);
11704 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
11705 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
11706 s390_sched_state
= S390_OOO_SCHED_STATE_CRACKED
;
11707 else if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0
11708 || (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
11709 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
11712 /* Only normal insns are left (mask == 0). */
11713 switch (s390_sched_state
)
11718 case S390_OOO_SCHED_STATE_NORMAL
:
11719 if (s390_sched_state
== S390_OOO_SCHED_STATE_NORMAL
)
11720 s390_sched_state
= 1;
11722 s390_sched_state
++;
11725 case S390_OOO_SCHED_STATE_CRACKED
:
11726 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
11732 fprintf (file
, "insn %d: ", INSN_UID (insn
));
11733 #define PRINT_OOO_ATTR(ATTR) \
11734 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11735 PRINT_OOO_ATTR (ooo_cracked
);
11736 PRINT_OOO_ATTR (ooo_expanded
);
11737 PRINT_OOO_ATTR (ooo_endgroup
);
11738 PRINT_OOO_ATTR (ooo_groupalone
);
11739 #undef PRINT_OOO_ATTR
11740 fprintf (file
, "\n");
11741 fprintf (file
, "sched state: %d\n", s390_sched_state
);
11745 if (GET_CODE (PATTERN (insn
)) != USE
11746 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
11753 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
11754 int verbose ATTRIBUTE_UNUSED
,
11755 int max_ready ATTRIBUTE_UNUSED
)
11757 last_scheduled_insn
= NULL
;
11758 s390_sched_state
= 0;
11761 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11762 a new number struct loop *loop should be unrolled if tuned for cpus with
11763 a built-in stride prefetcher.
11764 The loop is analyzed for memory accesses by calling check_dpu for
11765 each rtx of the loop. Depending on the loop_depth and the amount of
11766 memory accesses a new number <=nunroll is returned to improve the
11767 behaviour of the hardware prefetch unit. */
11769 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
11774 unsigned mem_count
= 0;
11776 if (s390_tune
!= PROCESSOR_2097_Z10
11777 && s390_tune
!= PROCESSOR_2817_Z196
11778 && s390_tune
!= PROCESSOR_2827_ZEC12
)
11781 /* Count the number of memory references within the loop body. */
11782 bbs
= get_loop_body (loop
);
11783 subrtx_iterator::array_type array
;
11784 for (i
= 0; i
< loop
->num_nodes
; i
++)
11785 FOR_BB_INSNS (bbs
[i
], insn
)
11786 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
11787 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
11792 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11793 if (mem_count
== 0)
11796 switch (loop_depth(loop
))
11799 return MIN (nunroll
, 28 / mem_count
);
11801 return MIN (nunroll
, 22 / mem_count
);
11803 return MIN (nunroll
, 16 / mem_count
);
11808 s390_option_override (void)
11811 cl_deferred_option
*opt
;
11812 vec
<cl_deferred_option
> *v
=
11813 (vec
<cl_deferred_option
> *) s390_deferred_options
;
11816 FOR_EACH_VEC_ELT (*v
, i
, opt
)
11818 switch (opt
->opt_index
)
11820 case OPT_mhotpatch
:
11821 s390_hotpatch_trampoline_halfwords
= (opt
->value
) ?
11822 s390_hotpatch_trampoline_halfwords_default
: -1;
11824 case OPT_mhotpatch_
:
11828 val
= integral_argument (opt
->arg
);
11831 /* argument is not a plain number */
11832 error ("argument to %qs should be a non-negative integer",
11836 else if (val
> s390_hotpatch_trampoline_halfwords_max
)
11838 error ("argument to %qs is too large (max. %d)",
11839 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max
);
11842 s390_hotpatch_trampoline_halfwords
= val
;
11846 gcc_unreachable ();
11850 /* Set up function hooks. */
11851 init_machine_status
= s390_init_machine_status
;
11853 /* Architecture mode defaults according to ABI. */
11854 if (!(target_flags_explicit
& MASK_ZARCH
))
11857 target_flags
|= MASK_ZARCH
;
11859 target_flags
&= ~MASK_ZARCH
;
11862 /* Set the march default in case it hasn't been specified on
11864 if (s390_arch
== PROCESSOR_max
)
11866 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
11867 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
11868 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
11871 /* Determine processor to tune for. */
11872 if (s390_tune
== PROCESSOR_max
)
11874 s390_tune
= s390_arch
;
11875 s390_tune_flags
= s390_arch_flags
;
11878 /* Sanity checks. */
11879 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
11880 error ("z/Architecture mode not supported on %s", s390_arch_string
);
11881 if (TARGET_64BIT
&& !TARGET_ZARCH
)
11882 error ("64-bit ABI not supported in ESA/390 mode");
11884 /* Use hardware DFP if available and not explicitly disabled by
11885 user. E.g. with -m31 -march=z10 -mzarch */
11886 if (!(target_flags_explicit
& MASK_HARD_DFP
) && TARGET_DFP
)
11887 target_flags
|= MASK_HARD_DFP
;
11889 /* Enable hardware transactions if available and not explicitly
11890 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11891 if (!(target_flags_explicit
& MASK_OPT_HTM
) && TARGET_CPU_HTM
&& TARGET_ZARCH
)
11892 target_flags
|= MASK_OPT_HTM
;
11894 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
11896 if (target_flags_explicit
& MASK_HARD_DFP
)
11898 if (!TARGET_CPU_DFP
)
11899 error ("hardware decimal floating point instructions"
11900 " not available on %s", s390_arch_string
);
11902 error ("hardware decimal floating point instructions"
11903 " not available in ESA/390 mode");
11906 target_flags
&= ~MASK_HARD_DFP
;
11909 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
11911 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
11912 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11914 target_flags
&= ~MASK_HARD_DFP
;
11917 /* Set processor cost function. */
11920 case PROCESSOR_2084_Z990
:
11921 s390_cost
= &z990_cost
;
11923 case PROCESSOR_2094_Z9_109
:
11924 s390_cost
= &z9_109_cost
;
11926 case PROCESSOR_2097_Z10
:
11927 s390_cost
= &z10_cost
;
11929 case PROCESSOR_2817_Z196
:
11930 s390_cost
= &z196_cost
;
11932 case PROCESSOR_2827_ZEC12
:
11933 s390_cost
= &zEC12_cost
;
11936 s390_cost
= &z900_cost
;
11939 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
11940 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11943 if (s390_stack_size
)
11945 if (s390_stack_guard
>= s390_stack_size
)
11946 error ("stack size must be greater than the stack guard value");
11947 else if (s390_stack_size
> 1 << 16)
11948 error ("stack size must not be greater than 64k");
11950 else if (s390_stack_guard
)
11951 error ("-mstack-guard implies use of -mstack-size");
11953 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11954 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
11955 target_flags
|= MASK_LONG_DOUBLE_128
;
11958 if (s390_tune
== PROCESSOR_2097_Z10
11959 || s390_tune
== PROCESSOR_2817_Z196
11960 || s390_tune
== PROCESSOR_2827_ZEC12
)
11962 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
11963 global_options
.x_param_values
,
11964 global_options_set
.x_param_values
);
11965 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
11966 global_options
.x_param_values
,
11967 global_options_set
.x_param_values
);
11968 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
11969 global_options
.x_param_values
,
11970 global_options_set
.x_param_values
);
11971 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
11972 global_options
.x_param_values
,
11973 global_options_set
.x_param_values
);
11976 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
11977 global_options
.x_param_values
,
11978 global_options_set
.x_param_values
);
11979 /* values for loop prefetching */
11980 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
11981 global_options
.x_param_values
,
11982 global_options_set
.x_param_values
);
11983 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
11984 global_options
.x_param_values
,
11985 global_options_set
.x_param_values
);
11986 /* s390 has more than 2 levels and the size is much larger. Since
11987 we are always running virtualized assume that we only get a small
11988 part of the caches above l1. */
11989 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
11990 global_options
.x_param_values
,
11991 global_options_set
.x_param_values
);
11992 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
11993 global_options
.x_param_values
,
11994 global_options_set
.x_param_values
);
11995 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
11996 global_options
.x_param_values
,
11997 global_options_set
.x_param_values
);
11999 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
12000 requires the arch flags to be evaluated already. Since prefetching
12001 is beneficial on s390, we enable it if available. */
12002 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
12003 flag_prefetch_loop_arrays
= 1;
12005 /* Use the alternative scheduling-pressure algorithm by default. */
12006 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
12007 global_options
.x_param_values
,
12008 global_options_set
.x_param_values
);
12012 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12013 debuggers do not yet support DWARF 3/4. */
12014 if (!global_options_set
.x_dwarf_strict
)
12016 if (!global_options_set
.x_dwarf_version
)
12020 /* Register a target-specific optimization-and-lowering pass
12021 to run immediately before prologue and epilogue generation.
12023 Registering the pass must be done at start up. It's
12024 convenient to do it here. */
12025 opt_pass
*new_pass
= new pass_s390_early_mach (g
);
12026 struct register_pass_info insert_pass_s390_early_mach
=
12028 new_pass
, /* pass */
12029 "pro_and_epilogue", /* reference_pass_name */
12030 1, /* ref_pass_instance_number */
12031 PASS_POS_INSERT_BEFORE
/* po_op */
12033 register_pass (&insert_pass_s390_early_mach
);
12036 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12039 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
12040 unsigned int align ATTRIBUTE_UNUSED
,
12041 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
12042 bool speed_p ATTRIBUTE_UNUSED
)
12044 return (size
== 1 || size
== 2
12045 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
12048 /* Initialize GCC target structure. */
12050 #undef TARGET_ASM_ALIGNED_HI_OP
12051 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12052 #undef TARGET_ASM_ALIGNED_DI_OP
12053 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12054 #undef TARGET_ASM_INTEGER
12055 #define TARGET_ASM_INTEGER s390_assemble_integer
12057 #undef TARGET_ASM_OPEN_PAREN
12058 #define TARGET_ASM_OPEN_PAREN ""
12060 #undef TARGET_ASM_CLOSE_PAREN
12061 #define TARGET_ASM_CLOSE_PAREN ""
12063 #undef TARGET_OPTION_OVERRIDE
12064 #define TARGET_OPTION_OVERRIDE s390_option_override
12066 #undef TARGET_ENCODE_SECTION_INFO
12067 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
12069 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12070 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12073 #undef TARGET_HAVE_TLS
12074 #define TARGET_HAVE_TLS true
12076 #undef TARGET_CANNOT_FORCE_CONST_MEM
12077 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
12079 #undef TARGET_DELEGITIMIZE_ADDRESS
12080 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
12082 #undef TARGET_LEGITIMIZE_ADDRESS
12083 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12085 #undef TARGET_RETURN_IN_MEMORY
12086 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
12088 #undef TARGET_INIT_BUILTINS
12089 #define TARGET_INIT_BUILTINS s390_init_builtins
12090 #undef TARGET_EXPAND_BUILTIN
12091 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
12093 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12094 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12096 #undef TARGET_ASM_OUTPUT_MI_THUNK
12097 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12098 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12099 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12101 #undef TARGET_SCHED_ADJUST_PRIORITY
12102 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12103 #undef TARGET_SCHED_ISSUE_RATE
12104 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12105 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12106 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
12108 #undef TARGET_SCHED_VARIABLE_ISSUE
12109 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12110 #undef TARGET_SCHED_REORDER
12111 #define TARGET_SCHED_REORDER s390_sched_reorder
12112 #undef TARGET_SCHED_INIT
12113 #define TARGET_SCHED_INIT s390_sched_init
12115 #undef TARGET_CANNOT_COPY_INSN_P
12116 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12117 #undef TARGET_RTX_COSTS
12118 #define TARGET_RTX_COSTS s390_rtx_costs
12119 #undef TARGET_ADDRESS_COST
12120 #define TARGET_ADDRESS_COST s390_address_cost
12121 #undef TARGET_REGISTER_MOVE_COST
12122 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12123 #undef TARGET_MEMORY_MOVE_COST
12124 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
12126 #undef TARGET_MACHINE_DEPENDENT_REORG
12127 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
12129 #undef TARGET_VALID_POINTER_MODE
12130 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
12132 #undef TARGET_BUILD_BUILTIN_VA_LIST
12133 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
12134 #undef TARGET_EXPAND_BUILTIN_VA_START
12135 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
12136 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12137 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
12139 #undef TARGET_PROMOTE_FUNCTION_MODE
12140 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
12141 #undef TARGET_PASS_BY_REFERENCE
12142 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
12144 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12145 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12146 #undef TARGET_FUNCTION_ARG
12147 #define TARGET_FUNCTION_ARG s390_function_arg
12148 #undef TARGET_FUNCTION_ARG_ADVANCE
12149 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
12150 #undef TARGET_FUNCTION_VALUE
12151 #define TARGET_FUNCTION_VALUE s390_function_value
12152 #undef TARGET_LIBCALL_VALUE
12153 #define TARGET_LIBCALL_VALUE s390_libcall_value
12155 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
12156 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12158 #undef TARGET_FIXED_CONDITION_CODE_REGS
12159 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
12161 #undef TARGET_CC_MODES_COMPATIBLE
12162 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
12164 #undef TARGET_INVALID_WITHIN_DOLOOP
12165 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
12168 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12169 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12172 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12173 #undef TARGET_MANGLE_TYPE
12174 #define TARGET_MANGLE_TYPE s390_mangle_type
12177 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12178 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12180 #undef TARGET_PREFERRED_RELOAD_CLASS
12181 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12183 #undef TARGET_SECONDARY_RELOAD
12184 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
12186 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12187 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12189 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12190 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12192 #undef TARGET_LEGITIMATE_ADDRESS_P
12193 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12195 #undef TARGET_LEGITIMATE_CONSTANT_P
12196 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12198 #undef TARGET_LRA_P
12199 #define TARGET_LRA_P s390_lra_p
12201 #undef TARGET_CAN_ELIMINATE
12202 #define TARGET_CAN_ELIMINATE s390_can_eliminate
12204 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12205 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12207 #undef TARGET_LOOP_UNROLL_ADJUST
12208 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12210 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12211 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12212 #undef TARGET_TRAMPOLINE_INIT
12213 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12215 #undef TARGET_UNWIND_WORD_MODE
12216 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12218 #undef TARGET_CANONICALIZE_COMPARISON
12219 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12221 #undef TARGET_HARD_REGNO_SCRATCH_OK
12222 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12224 #undef TARGET_ATTRIBUTE_TABLE
12225 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12227 #undef TARGET_CAN_INLINE_P
12228 #define TARGET_CAN_INLINE_P s390_can_inline_p
12230 #undef TARGET_SET_UP_BY_PROLOGUE
12231 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12233 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12234 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12235 s390_use_by_pieces_infrastructure_p
12237 struct gcc_target targetm
= TARGET_INITIALIZER
;
12239 #include "gt-s390.h"