1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* And similarly, for notes. */
307 static rtx_insn
*added_notes_insn
;
309 /* Basic block in which we are performing combines. */
310 static basic_block this_basic_block
;
311 static bool optimize_this_for_speed_p
;
314 /* Length of the currently allocated uid_insn_cost array. */
316 static int max_uid_known
;
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
321 static int *uid_insn_cost
;
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
329 struct insn_link
*next
;
332 static struct insn_link
**uid_log_links
;
335 insn_uid_check (const_rtx insn
)
337 int uid
= INSN_UID (insn
);
338 gcc_checking_assert (uid
<= max_uid_known
);
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
350 static struct obstack insn_link_obstack
;
352 /* Allocate a link. */
354 static inline struct insn_link
*
355 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
358 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
359 sizeof (struct insn_link
));
366 /* Incremented for each basic block. */
368 static int label_tick
;
370 /* Reset to label_tick for each extended basic block in scanning order. */
372 static int label_tick_ebb_start
;
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
377 static scalar_int_mode nonzero_bits_mode
;
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
385 static int nonzero_sign_valid
;
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
391 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
397 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
398 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
411 rtx_insn
*other_insn
;
414 static struct undobuf undobuf
;
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
419 static int n_occurrences
;
421 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
423 unsigned HOST_WIDE_INT
*);
424 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
427 static void do_SUBST (rtx
*, rtx
);
428 static void do_SUBST_INT (int *, int);
429 static void init_reg_last (void);
430 static void setup_incoming_promotions (rtx_insn
*);
431 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
432 static int cant_combine_insn_p (rtx_insn
*);
433 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
434 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
435 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
436 static int contains_muldiv (rtx
);
437 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
439 static void undo_all (void);
440 static void undo_commit (void);
441 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
442 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
443 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
444 static rtx
simplify_if_then_else (rtx
);
445 static rtx
simplify_set (rtx
);
446 static rtx
simplify_logical (rtx
);
447 static rtx
expand_compound_operation (rtx
);
448 static const_rtx
expand_field_assignment (const_rtx
);
449 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
450 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
451 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
452 unsigned HOST_WIDE_INT
*);
453 static rtx
canon_reg_for_combine (rtx
, rtx
);
454 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
455 scalar_int_mode
, unsigned HOST_WIDE_INT
, int);
456 static rtx
force_to_mode (rtx
, machine_mode
,
457 unsigned HOST_WIDE_INT
, int);
458 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
459 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
460 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
461 static rtx
make_field_assignment (rtx
);
462 static rtx
apply_distributive_law (rtx
);
463 static rtx
distribute_and_simplify_rtx (rtx
, int);
464 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
465 unsigned HOST_WIDE_INT
);
466 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
467 unsigned HOST_WIDE_INT
);
468 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
469 HOST_WIDE_INT
, machine_mode
, int *);
470 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
471 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
473 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
474 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
475 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
477 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
478 static void update_table_tick (rtx
);
479 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
480 static void check_promoted_subreg (rtx_insn
*, rtx
);
481 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
482 static void record_dead_and_set_regs (rtx_insn
*);
483 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
484 static rtx
get_last_value (const_rtx
);
485 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
486 static int reg_dead_at_p (rtx
, rtx_insn
*);
487 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
488 static int reg_bitfield_target_p (rtx
, rtx
);
489 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
490 static void distribute_links (struct insn_link
*);
491 static void mark_used_regs_combine (rtx
);
492 static void record_promoted_value (rtx_insn
*, rtx
);
493 static bool unmentioned_reg_p (rtx
, rtx
);
494 static void record_truncated_values (rtx
*, void *);
495 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
496 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
517 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
523 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
524 bool op0_preserve_value
)
526 int code_int
= (int)*code
;
527 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
528 *code
= (enum rtx_code
)code_int
;
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
538 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
543 ret
= split_insns (pattern
, insn
);
544 nregs
= max_reg_num ();
545 if (nregs
> reg_stat
.length ())
546 reg_stat
.safe_grow_cleared (nregs
);
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
557 find_single_use_1 (rtx dest
, rtx
*loc
)
560 enum rtx_code code
= GET_CODE (x
);
576 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
577 of a REG that occupies all of the REG, the insn uses DEST if
578 it is mentioned in the destination or the source. Otherwise, we
579 need just check the source. */
580 if (GET_CODE (SET_DEST (x
)) != CC0
581 && GET_CODE (SET_DEST (x
)) != PC
582 && !REG_P (SET_DEST (x
))
583 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
584 && REG_P (SUBREG_REG (SET_DEST (x
)))
585 && !read_modify_subreg_p (SET_DEST (x
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_costs. */
892 rtx tmp
= PATTERN (i3
);
893 PATTERN (i3
) = newpat
;
894 int tmpi
= INSN_CODE (i3
);
896 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
898 INSN_CODE (i3
) = tmpi
;
902 PATTERN (i2
) = newi2pat
;
903 tmpi
= INSN_CODE (i2
);
905 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
907 INSN_CODE (i2
) = tmpi
;
908 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
909 ? new_i2_cost
+ new_i3_cost
: 0;
913 new_cost
= new_i3_cost
;
917 if (undobuf
.other_insn
)
919 int old_other_cost
, new_other_cost
;
921 old_other_cost
= INSN_COST (undobuf
.other_insn
);
922 tmp
= PATTERN (undobuf
.other_insn
);
923 PATTERN (undobuf
.other_insn
) = newotherpat
;
924 tmpi
= INSN_CODE (undobuf
.other_insn
);
925 INSN_CODE (undobuf
.other_insn
) = -1;
926 new_other_cost
= insn_cost (undobuf
.other_insn
,
927 optimize_this_for_speed_p
);
928 PATTERN (undobuf
.other_insn
) = tmp
;
929 INSN_CODE (undobuf
.other_insn
) = tmpi
;
930 if (old_other_cost
> 0 && new_other_cost
> 0)
932 old_cost
+= old_other_cost
;
933 new_cost
+= new_other_cost
;
939 /* Disallow this combination if both new_cost and old_cost are greater than
940 zero, and new_cost is greater than old cost. */
941 int reject
= old_cost
> 0 && new_cost
> old_cost
;
945 fprintf (dump_file
, "%s combination of insns ",
946 reject
? "rejecting" : "allowing");
948 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
949 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
950 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
951 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
953 fprintf (dump_file
, "original costs ");
955 fprintf (dump_file
, "%d + ", i0_cost
);
956 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
957 fprintf (dump_file
, "%d + ", i1_cost
);
958 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
961 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
962 new_i2_cost
, new_i3_cost
, new_cost
);
964 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
970 /* Update the uid_insn_cost array with the replacement costs. */
971 INSN_COST (i2
) = new_i2_cost
;
972 INSN_COST (i3
) = new_i3_cost
;
984 /* Delete any insns that copy a register to itself. */
987 delete_noop_moves (void)
989 rtx_insn
*insn
, *next
;
992 FOR_EACH_BB_FN (bb
, cfun
)
994 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
996 next
= NEXT_INSN (insn
);
997 if (INSN_P (insn
) && noop_move_p (insn
))
1000 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1002 delete_insn_and_edges (insn
);
1009 /* Return false if we do not want to (or cannot) combine DEF. */
1011 can_combine_def_p (df_ref def
)
1013 /* Do not consider if it is pre/post modification in MEM. */
1014 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1017 unsigned int regno
= DF_REF_REGNO (def
);
1019 /* Do not combine frame pointer adjustments. */
1020 if ((regno
== FRAME_POINTER_REGNUM
1021 && (!reload_completed
|| frame_pointer_needed
))
1022 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1023 && regno
== HARD_FRAME_POINTER_REGNUM
1024 && (!reload_completed
|| frame_pointer_needed
))
1025 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1026 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1032 /* Return false if we do not want to (or cannot) combine USE. */
1034 can_combine_use_p (df_ref use
)
1036 /* Do not consider the usage of the stack pointer by function call. */
1037 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1043 /* Fill in log links field for all insns. */
1046 create_log_links (void)
1049 rtx_insn
**next_use
;
1053 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1055 /* Pass through each block from the end, recording the uses of each
1056 register and establishing log links when def is encountered.
1057 Note that we do not clear next_use array in order to save time,
1058 so we have to test whether the use is in the same basic block as def.
1060 There are a few cases below when we do not consider the definition or
1061 usage -- these are taken from original flow.c did. Don't ask me why it is
1062 done this way; I don't know and if it works, I don't want to know. */
1064 FOR_EACH_BB_FN (bb
, cfun
)
1066 FOR_BB_INSNS_REVERSE (bb
, insn
)
1068 if (!NONDEBUG_INSN_P (insn
))
1071 /* Log links are created only once. */
1072 gcc_assert (!LOG_LINKS (insn
));
1074 FOR_EACH_INSN_DEF (def
, insn
)
1076 unsigned int regno
= DF_REF_REGNO (def
);
1079 if (!next_use
[regno
])
1082 if (!can_combine_def_p (def
))
1085 use_insn
= next_use
[regno
];
1086 next_use
[regno
] = NULL
;
1088 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1093 We don't build a LOG_LINK for hard registers contained
1094 in ASM_OPERANDs. If these registers get replaced,
1095 we might wind up changing the semantics of the insn,
1096 even if reload can make what appear to be valid
1097 assignments later. */
1098 if (regno
< FIRST_PSEUDO_REGISTER
1099 && asm_noperands (PATTERN (use_insn
)) >= 0)
1102 /* Don't add duplicate links between instructions. */
1103 struct insn_link
*links
;
1104 FOR_EACH_LOG_LINK (links
, use_insn
)
1105 if (insn
== links
->insn
&& regno
== links
->regno
)
1109 LOG_LINKS (use_insn
)
1110 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1113 FOR_EACH_INSN_USE (use
, insn
)
1114 if (can_combine_use_p (use
))
1115 next_use
[DF_REF_REGNO (use
)] = insn
;
1122 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1123 true if we found a LOG_LINK that proves that A feeds B. This only works
1124 if there are no instructions between A and B which could have a link
1125 depending on A, since in that case we would not record a link for B.
1126 We also check the implicit dependency created by a cc0 setter/user
1130 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1132 struct insn_link
*links
;
1133 FOR_EACH_LOG_LINK (links
, b
)
1134 if (links
->insn
== a
)
1136 if (HAVE_cc0
&& sets_cc0_p (a
))
1141 /* Main entry point for combiner. F is the first insn of the function.
1142 NREGS is the first unused pseudo-reg number.
1144 Return nonzero if the combiner has turned an indirect jump
1145 instruction into a direct jump. */
1147 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1149 rtx_insn
*insn
, *next
;
1151 struct insn_link
*links
, *nextlinks
;
1153 basic_block last_bb
;
1155 int new_direct_jump_p
= 0;
1157 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1158 first
= NEXT_INSN (first
);
1162 combine_attempts
= 0;
1165 combine_successes
= 0;
1167 rtl_hooks
= combine_rtl_hooks
;
1169 reg_stat
.safe_grow_cleared (nregs
);
1171 init_recog_no_volatile ();
1173 /* Allocate array for insn info. */
1174 max_uid_known
= get_max_uid ();
1175 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1176 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1177 gcc_obstack_init (&insn_link_obstack
);
1179 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1181 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1182 problems when, for example, we have j <<= 1 in a loop. */
1184 nonzero_sign_valid
= 0;
1185 label_tick
= label_tick_ebb_start
= 1;
1187 /* Scan all SETs and see if we can deduce anything about what
1188 bits are known to be zero for some registers and how many copies
1189 of the sign bit are known to exist for those registers.
1191 Also set any known values so that we can use it while searching
1192 for what bits are known to be set. */
1194 setup_incoming_promotions (first
);
1195 /* Allow the entry block and the first block to fall into the same EBB.
1196 Conceptually the incoming promotions are assigned to the entry block. */
1197 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1199 create_log_links ();
1200 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1202 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1207 if (!single_pred_p (this_basic_block
)
1208 || single_pred (this_basic_block
) != last_bb
)
1209 label_tick_ebb_start
= label_tick
;
1210 last_bb
= this_basic_block
;
1212 FOR_BB_INSNS (this_basic_block
, insn
)
1213 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1217 subst_low_luid
= DF_INSN_LUID (insn
);
1220 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1222 record_dead_and_set_regs (insn
);
1225 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1226 if (REG_NOTE_KIND (links
) == REG_INC
)
1227 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1230 /* Record the current insn_cost of this instruction. */
1231 if (NONJUMP_INSN_P (insn
))
1232 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1235 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1236 dump_insn_slim (dump_file
, insn
);
1241 nonzero_sign_valid
= 1;
1243 /* Now scan all the insns in forward order. */
1244 label_tick
= label_tick_ebb_start
= 1;
1246 setup_incoming_promotions (first
);
1247 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1248 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1250 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1252 rtx_insn
*last_combined_insn
= NULL
;
1254 /* Ignore instruction combination in basic blocks that are going to
1255 be removed as unreachable anyway. See PR82386. */
1256 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1259 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1264 if (!single_pred_p (this_basic_block
)
1265 || single_pred (this_basic_block
) != last_bb
)
1266 label_tick_ebb_start
= label_tick
;
1267 last_bb
= this_basic_block
;
1269 rtl_profile_for_bb (this_basic_block
);
1270 for (insn
= BB_HEAD (this_basic_block
);
1271 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1272 insn
= next
? next
: NEXT_INSN (insn
))
1275 if (!NONDEBUG_INSN_P (insn
))
1278 while (last_combined_insn
1279 && (!NONDEBUG_INSN_P (last_combined_insn
)
1280 || last_combined_insn
->deleted ()))
1281 last_combined_insn
= PREV_INSN (last_combined_insn
);
1282 if (last_combined_insn
== NULL_RTX
1283 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1284 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1285 last_combined_insn
= insn
;
1287 /* See if we know about function return values before this
1288 insn based upon SUBREG flags. */
1289 check_promoted_subreg (insn
, PATTERN (insn
));
1291 /* See if we can find hardregs and subreg of pseudos in
1292 narrower modes. This could help turning TRUNCATEs
1294 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1296 /* Try this insn with each insn it links back to. */
1298 FOR_EACH_LOG_LINK (links
, insn
)
1299 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1300 NULL
, &new_direct_jump_p
,
1301 last_combined_insn
)) != 0)
1303 statistics_counter_event (cfun
, "two-insn combine", 1);
1307 /* Try each sequence of three linked insns ending with this one. */
1309 if (max_combine
>= 3)
1310 FOR_EACH_LOG_LINK (links
, insn
)
1312 rtx_insn
*link
= links
->insn
;
1314 /* If the linked insn has been replaced by a note, then there
1315 is no point in pursuing this chain any further. */
1319 FOR_EACH_LOG_LINK (nextlinks
, link
)
1320 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1321 NULL
, &new_direct_jump_p
,
1322 last_combined_insn
)) != 0)
1324 statistics_counter_event (cfun
, "three-insn combine", 1);
1329 /* Try to combine a jump insn that uses CC0
1330 with a preceding insn that sets CC0, and maybe with its
1331 logical predecessor as well.
1332 This is how we make decrement-and-branch insns.
1333 We need this special code because data flow connections
1334 via CC0 do not get entered in LOG_LINKS. */
1338 && (prev
= prev_nonnote_insn (insn
)) != 0
1339 && NONJUMP_INSN_P (prev
)
1340 && sets_cc0_p (PATTERN (prev
)))
1342 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1344 last_combined_insn
)) != 0)
1347 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1348 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1349 NULL
, &new_direct_jump_p
,
1350 last_combined_insn
)) != 0)
1354 /* Do the same for an insn that explicitly references CC0. */
1355 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1356 && (prev
= prev_nonnote_insn (insn
)) != 0
1357 && NONJUMP_INSN_P (prev
)
1358 && sets_cc0_p (PATTERN (prev
))
1359 && GET_CODE (PATTERN (insn
)) == SET
1360 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1362 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1364 last_combined_insn
)) != 0)
1367 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1368 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1369 NULL
, &new_direct_jump_p
,
1370 last_combined_insn
)) != 0)
1374 /* Finally, see if any of the insns that this insn links to
1375 explicitly references CC0. If so, try this insn, that insn,
1376 and its predecessor if it sets CC0. */
1379 FOR_EACH_LOG_LINK (links
, insn
)
1380 if (NONJUMP_INSN_P (links
->insn
)
1381 && GET_CODE (PATTERN (links
->insn
)) == SET
1382 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1383 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1384 && NONJUMP_INSN_P (prev
)
1385 && sets_cc0_p (PATTERN (prev
))
1386 && (next
= try_combine (insn
, links
->insn
,
1387 prev
, NULL
, &new_direct_jump_p
,
1388 last_combined_insn
)) != 0)
1392 /* Try combining an insn with two different insns whose results it
1394 if (max_combine
>= 3)
1395 FOR_EACH_LOG_LINK (links
, insn
)
1396 for (nextlinks
= links
->next
; nextlinks
;
1397 nextlinks
= nextlinks
->next
)
1398 if ((next
= try_combine (insn
, links
->insn
,
1399 nextlinks
->insn
, NULL
,
1401 last_combined_insn
)) != 0)
1404 statistics_counter_event (cfun
, "three-insn combine", 1);
1408 /* Try four-instruction combinations. */
1409 if (max_combine
>= 4)
1410 FOR_EACH_LOG_LINK (links
, insn
)
1412 struct insn_link
*next1
;
1413 rtx_insn
*link
= links
->insn
;
1415 /* If the linked insn has been replaced by a note, then there
1416 is no point in pursuing this chain any further. */
1420 FOR_EACH_LOG_LINK (next1
, link
)
1422 rtx_insn
*link1
= next1
->insn
;
1425 /* I0 -> I1 -> I2 -> I3. */
1426 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1427 if ((next
= try_combine (insn
, link
, link1
,
1430 last_combined_insn
)) != 0)
1432 statistics_counter_event (cfun
, "four-insn combine", 1);
1435 /* I0, I1 -> I2, I2 -> I3. */
1436 for (nextlinks
= next1
->next
; nextlinks
;
1437 nextlinks
= nextlinks
->next
)
1438 if ((next
= try_combine (insn
, link
, link1
,
1441 last_combined_insn
)) != 0)
1443 statistics_counter_event (cfun
, "four-insn combine", 1);
1448 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1450 rtx_insn
*link1
= next1
->insn
;
1453 /* I0 -> I2; I1, I2 -> I3. */
1454 FOR_EACH_LOG_LINK (nextlinks
, link
)
1455 if ((next
= try_combine (insn
, link
, link1
,
1458 last_combined_insn
)) != 0)
1460 statistics_counter_event (cfun
, "four-insn combine", 1);
1463 /* I0 -> I1; I1, I2 -> I3. */
1464 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1465 if ((next
= try_combine (insn
, link
, link1
,
1468 last_combined_insn
)) != 0)
1470 statistics_counter_event (cfun
, "four-insn combine", 1);
1476 /* Try this insn with each REG_EQUAL note it links back to. */
1477 FOR_EACH_LOG_LINK (links
, insn
)
1480 rtx_insn
*temp
= links
->insn
;
1481 if ((set
= single_set (temp
)) != 0
1482 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1483 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1484 /* Avoid using a register that may already been marked
1485 dead by an earlier instruction. */
1486 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1487 && (GET_MODE (note
) == VOIDmode
1488 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1489 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1490 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1491 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1492 == GET_MODE (note
))))))
1494 /* Temporarily replace the set's source with the
1495 contents of the REG_EQUAL note. The insn will
1496 be deleted or recognized by try_combine. */
1497 rtx orig_src
= SET_SRC (set
);
1498 rtx orig_dest
= SET_DEST (set
);
1499 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1500 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1501 SET_SRC (set
) = note
;
1503 i2mod_old_rhs
= copy_rtx (orig_src
);
1504 i2mod_new_rhs
= copy_rtx (note
);
1505 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1507 last_combined_insn
);
1511 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1514 SET_SRC (set
) = orig_src
;
1515 SET_DEST (set
) = orig_dest
;
1520 record_dead_and_set_regs (insn
);
1527 default_rtl_profile ();
1529 new_direct_jump_p
|= purge_all_dead_edges ();
1530 delete_noop_moves ();
1533 obstack_free (&insn_link_obstack
, NULL
);
1534 free (uid_log_links
);
1535 free (uid_insn_cost
);
1536 reg_stat
.release ();
1539 struct undo
*undo
, *next
;
1540 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1548 total_attempts
+= combine_attempts
;
1549 total_merges
+= combine_merges
;
1550 total_extras
+= combine_extras
;
1551 total_successes
+= combine_successes
;
1553 nonzero_sign_valid
= 0;
1554 rtl_hooks
= general_rtl_hooks
;
1556 /* Make recognizer allow volatile MEMs again. */
1559 return new_direct_jump_p
;
1562 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 init_reg_last (void)
1570 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1571 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1574 /* Set up any promoted values for incoming argument registers. */
1577 setup_incoming_promotions (rtx_insn
*first
)
1580 bool strictly_local
= false;
1582 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1583 arg
= DECL_CHAIN (arg
))
1585 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1587 machine_mode mode1
, mode2
, mode3
, mode4
;
1589 /* Only continue if the incoming argument is in a register. */
1593 /* Determine, if possible, whether all call sites of the current
1594 function lie within the current compilation unit. (This does
1595 take into account the exporting of a function via taking its
1596 address, and so forth.) */
1597 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1599 /* The mode and signedness of the argument before any promotions happen
1600 (equal to the mode of the pseudo holding it at that stage). */
1601 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1602 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1604 /* The mode and signedness of the argument after any source language and
1605 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1606 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1607 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1609 /* The mode and signedness of the argument as it is actually passed,
1610 see assign_parm_setup_reg in function.c. */
1611 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1612 TREE_TYPE (cfun
->decl
), 0);
1614 /* The mode of the register in which the argument is being passed. */
1615 mode4
= GET_MODE (reg
);
1617 /* Eliminate sign extensions in the callee when:
1618 (a) A mode promotion has occurred; */
1621 /* (b) The mode of the register is the same as the mode of
1622 the argument as it is passed; */
1625 /* (c) There's no language level extension; */
1628 /* (c.1) All callers are from the current compilation unit. If that's
1629 the case we don't have to rely on an ABI, we only have to know
1630 what we're generating right now, and we know that we will do the
1631 mode1 to mode2 promotion with the given sign. */
1632 else if (!strictly_local
)
1634 /* (c.2) The combination of the two promotions is useful. This is
1635 true when the signs match, or if the first promotion is unsigned.
1636 In the later case, (sign_extend (zero_extend x)) is the same as
1637 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1643 /* Record that the value was promoted from mode1 to mode3,
1644 so that any sign extension at the head of the current
1645 function may be eliminated. */
1646 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1647 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1648 record_value_for_reg (reg
, first
, x
);
1652 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1653 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1654 because some machines (maybe most) will actually do the sign-extension and
1655 this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1661 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1663 scalar_int_mode int_mode
;
1664 if (CONST_INT_P (src
)
1665 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1666 && GET_MODE_PRECISION (int_mode
) < prec
1668 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1669 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1674 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1678 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1681 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1682 unsigned HOST_WIDE_INT bits
= 0;
1683 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1684 unsigned int num
= 0;
1687 reg_equal
= XEXP (reg_equal_note
, 0);
1689 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1691 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1693 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1696 /* Don't call nonzero_bits if it cannot change anything. */
1697 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1699 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1700 if (reg_equal
&& bits
)
1701 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1702 rsp
->nonzero_bits
|= bits
;
1705 /* Don't call num_sign_bit_copies if it cannot change anything. */
1706 if (rsp
->sign_bit_copies
!= 1)
1708 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1709 if (reg_equal
&& maybe_ne (num
, GET_MODE_PRECISION (GET_MODE (x
))))
1711 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1712 if (num
== 0 || numeq
> num
)
1715 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1716 rsp
->sign_bit_copies
= num
;
1720 /* Called via note_stores. If X is a pseudo that is narrower than
1721 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1723 If we are setting only a portion of X and we can't figure out what
1724 portion, assume all bits will be used since we don't know what will
1727 Similarly, set how many bits of X are known to be copies of the sign bit
1728 at all locations in the function. This is the smallest number implied
1732 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1734 rtx_insn
*insn
= (rtx_insn
*) data
;
1735 scalar_int_mode mode
;
1738 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1739 /* If this register is undefined at the start of the file, we can't
1740 say what its contents were. */
1741 && ! REGNO_REG_SET_P
1742 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1743 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1744 && HWI_COMPUTABLE_MODE_P (mode
))
1746 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1748 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1750 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1751 rsp
->sign_bit_copies
= 1;
1755 /* If this register is being initialized using itself, and the
1756 register is uninitialized in this basic block, and there are
1757 no LOG_LINKS which set the register, then part of the
1758 register is uninitialized. In that case we can't assume
1759 anything about the number of nonzero bits.
1761 ??? We could do better if we checked this in
1762 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1763 could avoid making assumptions about the insn which initially
1764 sets the register, while still using the information in other
1765 insns. We would have to be careful to check every insn
1766 involved in the combination. */
1769 && reg_referenced_p (x
, PATTERN (insn
))
1770 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1773 struct insn_link
*link
;
1775 FOR_EACH_LOG_LINK (link
, insn
)
1776 if (dead_or_set_p (link
->insn
, x
))
1780 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1781 rsp
->sign_bit_copies
= 1;
1786 /* If this is a complex assignment, see if we can convert it into a
1787 simple assignment. */
1788 set
= expand_field_assignment (set
);
1790 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1791 set what we know about X. */
1793 if (SET_DEST (set
) == x
1794 || (paradoxical_subreg_p (SET_DEST (set
))
1795 && SUBREG_REG (SET_DEST (set
)) == x
))
1796 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1799 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1800 rsp
->sign_bit_copies
= 1;
1805 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1806 optionally insns that were previously combined into I3 or that will be
1807 combined into the merger of INSN and I3. The order is PRED, PRED2,
1808 INSN, SUCC, SUCC2, I3.
1810 Return 0 if the combination is not allowed for any reason.
1812 If the combination is allowed, *PDEST will be set to the single
1813 destination of INSN and *PSRC to the single source, and this function
1817 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1818 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1819 rtx
*pdest
, rtx
*psrc
)
1826 bool all_adjacent
= true;
1827 int (*is_volatile_p
) (const_rtx
);
1833 if (next_active_insn (succ2
) != i3
)
1834 all_adjacent
= false;
1835 if (next_active_insn (succ
) != succ2
)
1836 all_adjacent
= false;
1838 else if (next_active_insn (succ
) != i3
)
1839 all_adjacent
= false;
1840 if (next_active_insn (insn
) != succ
)
1841 all_adjacent
= false;
1843 else if (next_active_insn (insn
) != i3
)
1844 all_adjacent
= false;
1846 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1847 or a PARALLEL consisting of such a SET and CLOBBERs.
1849 If INSN has CLOBBER parallel parts, ignore them for our processing.
1850 By definition, these happen during the execution of the insn. When it
1851 is merged with another insn, all bets are off. If they are, in fact,
1852 needed and aren't also supplied in I3, they may be added by
1853 recog_for_combine. Otherwise, it won't match.
1855 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1858 Get the source and destination of INSN. If more than one, can't
1861 if (GET_CODE (PATTERN (insn
)) == SET
)
1862 set
= PATTERN (insn
);
1863 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1864 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1866 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1868 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1870 switch (GET_CODE (elt
))
1872 /* This is important to combine floating point insns
1873 for the SH4 port. */
1875 /* Combining an isolated USE doesn't make sense.
1876 We depend here on combinable_i3pat to reject them. */
1877 /* The code below this loop only verifies that the inputs of
1878 the SET in INSN do not change. We call reg_set_between_p
1879 to verify that the REG in the USE does not change between
1881 If the USE in INSN was for a pseudo register, the matching
1882 insn pattern will likely match any register; combining this
1883 with any other USE would only be safe if we knew that the
1884 used registers have identical values, or if there was
1885 something to tell them apart, e.g. different modes. For
1886 now, we forgo such complicated tests and simply disallow
1887 combining of USES of pseudo registers with any other USE. */
1888 if (REG_P (XEXP (elt
, 0))
1889 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1891 rtx i3pat
= PATTERN (i3
);
1892 int i
= XVECLEN (i3pat
, 0) - 1;
1893 unsigned int regno
= REGNO (XEXP (elt
, 0));
1897 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1899 if (GET_CODE (i3elt
) == USE
1900 && REG_P (XEXP (i3elt
, 0))
1901 && (REGNO (XEXP (i3elt
, 0)) == regno
1902 ? reg_set_between_p (XEXP (elt
, 0),
1903 PREV_INSN (insn
), i3
)
1904 : regno
>= FIRST_PSEUDO_REGISTER
))
1911 /* We can ignore CLOBBERs. */
1916 /* Ignore SETs whose result isn't used but not those that
1917 have side-effects. */
1918 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1919 && insn_nothrow_p (insn
)
1920 && !side_effects_p (elt
))
1923 /* If we have already found a SET, this is a second one and
1924 so we cannot combine with this insn. */
1932 /* Anything else means we can't combine. */
1938 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1939 so don't do anything with it. */
1940 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1949 /* The simplification in expand_field_assignment may call back to
1950 get_last_value, so set safe guard here. */
1951 subst_low_luid
= DF_INSN_LUID (insn
);
1953 set
= expand_field_assignment (set
);
1954 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1956 /* Do not eliminate user-specified register if it is in an
1957 asm input because we may break the register asm usage defined
1958 in GCC manual if allow to do so.
1959 Be aware that this may cover more cases than we expect but this
1960 should be harmless. */
1961 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1962 && extract_asm_operands (PATTERN (i3
)))
1965 /* Don't eliminate a store in the stack pointer. */
1966 if (dest
== stack_pointer_rtx
1967 /* Don't combine with an insn that sets a register to itself if it has
1968 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1969 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1970 /* Can't merge an ASM_OPERANDS. */
1971 || GET_CODE (src
) == ASM_OPERANDS
1972 /* Can't merge a function call. */
1973 || GET_CODE (src
) == CALL
1974 /* Don't eliminate a function call argument. */
1976 && (find_reg_fusage (i3
, USE
, dest
)
1978 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1979 && global_regs
[REGNO (dest
)])))
1980 /* Don't substitute into an incremented register. */
1981 || FIND_REG_INC_NOTE (i3
, dest
)
1982 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1983 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1984 /* Don't substitute into a non-local goto, this confuses CFG. */
1985 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1986 /* Make sure that DEST is not used after INSN but before SUCC, or
1987 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1990 && (reg_used_between_p (dest
, succ2
, i3
)
1991 || reg_used_between_p (dest
, succ
, succ2
)))
1992 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1993 || (!succ2
&& !succ
&& reg_used_between_p (dest
, insn
, i3
))
1995 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1996 that case SUCC is not in the insn stream, so use SUCC2
1997 instead for this test. */
1998 && reg_used_between_p (dest
, insn
,
2000 && INSN_UID (succ
) == INSN_UID (succ2
)
2002 /* Make sure that the value that is to be substituted for the register
2003 does not use any registers whose values alter in between. However,
2004 If the insns are adjacent, a use can't cross a set even though we
2005 think it might (this can happen for a sequence of insns each setting
2006 the same destination; last_set of that register might point to
2007 a NOTE). If INSN has a REG_EQUIV note, the register is always
2008 equivalent to the memory so the substitution is valid even if there
2009 are intervening stores. Also, don't move a volatile asm or
2010 UNSPEC_VOLATILE across any other insns. */
2013 || ! find_reg_note (insn
, REG_EQUIV
, src
))
2014 && modified_between_p (src
, insn
, i3
))
2015 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2016 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2017 /* Don't combine across a CALL_INSN, because that would possibly
2018 change whether the life span of some REGs crosses calls or not,
2019 and it is a pain to update that information.
2020 Exception: if source is a constant, moving it later can't hurt.
2021 Accept that as a special case. */
2022 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2025 /* DEST must either be a REG or CC0. */
2028 /* If register alignment is being enforced for multi-word items in all
2029 cases except for parameters, it is possible to have a register copy
2030 insn referencing a hard register that is not allowed to contain the
2031 mode being copied and which would not be valid as an operand of most
2032 insns. Eliminate this problem by not combining with such an insn.
2034 Also, on some machines we don't want to extend the life of a hard
2038 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2039 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
2040 /* Don't extend the life of a hard register unless it is
2041 user variable (if we have few registers) or it can't
2042 fit into the desired register (meaning something special
2044 Also avoid substituting a return register into I3, because
2045 reload can't handle a conflict with constraints of other
2047 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2048 && !targetm
.hard_regno_mode_ok (REGNO (src
),
2052 else if (GET_CODE (dest
) != CC0
)
2056 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2057 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2058 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2060 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2062 /* If the clobber represents an earlyclobber operand, we must not
2063 substitute an expression containing the clobbered register.
2064 As we do not analyze the constraint strings here, we have to
2065 make the conservative assumption. However, if the register is
2066 a fixed hard reg, the clobber cannot represent any operand;
2067 we leave it up to the machine description to either accept or
2068 reject use-and-clobber patterns. */
2070 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2071 || !fixed_regs
[REGNO (reg
)])
2072 if (reg_overlap_mentioned_p (reg
, src
))
2076 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2077 or not), reject, unless nothing volatile comes between it and I3 */
2079 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2081 /* Make sure neither succ nor succ2 contains a volatile reference. */
2082 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2084 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2086 /* We'll check insns between INSN and I3 below. */
2089 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2090 to be an explicit register variable, and was chosen for a reason. */
2092 if (GET_CODE (src
) == ASM_OPERANDS
2093 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2096 /* If INSN contains volatile references (specifically volatile MEMs),
2097 we cannot combine across any other volatile references.
2098 Even if INSN doesn't contain volatile references, any intervening
2099 volatile insn might affect machine state. */
2101 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2105 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2106 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2109 /* If INSN contains an autoincrement or autodecrement, make sure that
2110 register is not used between there and I3, and not already used in
2111 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2112 Also insist that I3 not be a jump; if it were one
2113 and the incremented register were spilled, we would lose. */
2116 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2117 if (REG_NOTE_KIND (link
) == REG_INC
2119 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2120 || (pred
!= NULL_RTX
2121 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2122 || (pred2
!= NULL_RTX
2123 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2124 || (succ
!= NULL_RTX
2125 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2126 || (succ2
!= NULL_RTX
2127 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2128 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2131 /* Don't combine an insn that follows a CC0-setting insn.
2132 An insn that uses CC0 must not be separated from the one that sets it.
2133 We do, however, allow I2 to follow a CC0-setting insn if that insn
2134 is passed as I1; in that case it will be deleted also.
2135 We also allow combining in this case if all the insns are adjacent
2136 because that would leave the two CC0 insns adjacent as well.
2137 It would be more logical to test whether CC0 occurs inside I1 or I2,
2138 but that would be much slower, and this ought to be equivalent. */
2142 p
= prev_nonnote_insn (insn
);
2143 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2148 /* If we get here, we have passed all the tests and the combination is
2157 /* LOC is the location within I3 that contains its pattern or the component
2158 of a PARALLEL of the pattern. We validate that it is valid for combining.
2160 One problem is if I3 modifies its output, as opposed to replacing it
2161 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2162 doing so would produce an insn that is not equivalent to the original insns.
2166 (set (reg:DI 101) (reg:DI 100))
2167 (set (subreg:SI (reg:DI 101) 0) <foo>)
2169 This is NOT equivalent to:
2171 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2172 (set (reg:DI 101) (reg:DI 100))])
2174 Not only does this modify 100 (in which case it might still be valid
2175 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2177 We can also run into a problem if I2 sets a register that I1
2178 uses and I1 gets directly substituted into I3 (not via I2). In that
2179 case, we would be getting the wrong value of I2DEST into I3, so we
2180 must reject the combination. This case occurs when I2 and I1 both
2181 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2182 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2183 of a SET must prevent combination from occurring. The same situation
2184 can occur for I0, in which case I0_NOT_IN_SRC is set.
2186 Before doing the above check, we first try to expand a field assignment
2187 into a set of logical operations.
2189 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2190 we place a register that is both set and used within I3. If more than one
2191 such register is detected, we fail.
2193 Return 1 if the combination is valid, zero otherwise. */
2196 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2197 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2201 if (GET_CODE (x
) == SET
)
2204 rtx dest
= SET_DEST (set
);
2205 rtx src
= SET_SRC (set
);
2206 rtx inner_dest
= dest
;
2209 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2210 || GET_CODE (inner_dest
) == SUBREG
2211 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2212 inner_dest
= XEXP (inner_dest
, 0);
2214 /* Check for the case where I3 modifies its output, as discussed
2215 above. We don't want to prevent pseudos from being combined
2216 into the address of a MEM, so only prevent the combination if
2217 i1 or i2 set the same MEM. */
2218 if ((inner_dest
!= dest
&&
2219 (!MEM_P (inner_dest
)
2220 || rtx_equal_p (i2dest
, inner_dest
)
2221 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2222 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2223 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2224 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2225 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2227 /* This is the same test done in can_combine_p except we can't test
2228 all_adjacent; we don't have to, since this instruction will stay
2229 in place, thus we are not considering increasing the lifetime of
2232 Also, if this insn sets a function argument, combining it with
2233 something that might need a spill could clobber a previous
2234 function argument; the all_adjacent test in can_combine_p also
2235 checks this; here, we do a more specific test for this case. */
2237 || (REG_P (inner_dest
)
2238 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2239 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2240 GET_MODE (inner_dest
)))
2241 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2242 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2245 /* If DEST is used in I3, it is being killed in this insn, so
2246 record that for later. We have to consider paradoxical
2247 subregs here, since they kill the whole register, but we
2248 ignore partial subregs, STRICT_LOW_PART, etc.
2249 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2250 STACK_POINTER_REGNUM, since these are always considered to be
2251 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2253 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2254 subdest
= SUBREG_REG (subdest
);
2257 && reg_referenced_p (subdest
, PATTERN (i3
))
2258 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2259 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2260 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2261 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2262 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2263 || ! fixed_regs
[REGNO (subdest
)]))
2264 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2266 if (*pi3dest_killed
)
2269 *pi3dest_killed
= subdest
;
2273 else if (GET_CODE (x
) == PARALLEL
)
2277 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2278 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2279 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2286 /* Return 1 if X is an arithmetic expression that contains a multiplication
2287 and division. We don't count multiplications by powers of two here. */
2290 contains_muldiv (rtx x
)
2292 switch (GET_CODE (x
))
2294 case MOD
: case DIV
: case UMOD
: case UDIV
:
2298 return ! (CONST_INT_P (XEXP (x
, 1))
2299 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2302 return contains_muldiv (XEXP (x
, 0))
2303 || contains_muldiv (XEXP (x
, 1));
2306 return contains_muldiv (XEXP (x
, 0));
2312 /* Determine whether INSN can be used in a combination. Return nonzero if
2313 not. This is used in try_combine to detect early some cases where we
2314 can't perform combinations. */
2317 cant_combine_insn_p (rtx_insn
*insn
)
2322 /* If this isn't really an insn, we can't do anything.
2323 This can occur when flow deletes an insn that it has merged into an
2324 auto-increment address. */
2325 if (!NONDEBUG_INSN_P (insn
))
2328 /* Never combine loads and stores involving hard regs that are likely
2329 to be spilled. The register allocator can usually handle such
2330 reg-reg moves by tying. If we allow the combiner to make
2331 substitutions of likely-spilled regs, reload might die.
2332 As an exception, we allow combinations involving fixed regs; these are
2333 not available to the register allocator so there's no risk involved. */
2335 set
= single_set (insn
);
2338 src
= SET_SRC (set
);
2339 dest
= SET_DEST (set
);
2340 if (GET_CODE (src
) == SUBREG
)
2341 src
= SUBREG_REG (src
);
2342 if (GET_CODE (dest
) == SUBREG
)
2343 dest
= SUBREG_REG (dest
);
2344 if (REG_P (src
) && REG_P (dest
)
2345 && ((HARD_REGISTER_P (src
)
2346 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2347 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2348 || (HARD_REGISTER_P (dest
)
2349 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2350 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2356 struct likely_spilled_retval_info
2358 unsigned regno
, nregs
;
2362 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2363 hard registers that are known to be written to / clobbered in full. */
2365 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2367 struct likely_spilled_retval_info
*const info
=
2368 (struct likely_spilled_retval_info
*) data
;
2369 unsigned regno
, nregs
;
2372 if (!REG_P (XEXP (set
, 0)))
2375 if (regno
>= info
->regno
+ info
->nregs
)
2377 nregs
= REG_NREGS (x
);
2378 if (regno
+ nregs
<= info
->regno
)
2380 new_mask
= (2U << (nregs
- 1)) - 1;
2381 if (regno
< info
->regno
)
2382 new_mask
>>= info
->regno
- regno
;
2384 new_mask
<<= regno
- info
->regno
;
2385 info
->mask
&= ~new_mask
;
2388 /* Return nonzero iff part of the return value is live during INSN, and
2389 it is likely spilled. This can happen when more than one insn is needed
2390 to copy the return value, e.g. when we consider to combine into the
2391 second copy insn for a complex value. */
2394 likely_spilled_retval_p (rtx_insn
*insn
)
2396 rtx_insn
*use
= BB_END (this_basic_block
);
2399 unsigned regno
, nregs
;
2400 /* We assume here that no machine mode needs more than
2401 32 hard registers when the value overlaps with a register
2402 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2404 struct likely_spilled_retval_info info
;
2406 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2408 reg
= XEXP (PATTERN (use
), 0);
2409 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2411 regno
= REGNO (reg
);
2412 nregs
= REG_NREGS (reg
);
2415 mask
= (2U << (nregs
- 1)) - 1;
2417 /* Disregard parts of the return value that are set later. */
2421 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2423 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2426 /* Check if any of the (probably) live return value registers is
2431 if ((mask
& 1 << nregs
)
2432 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2438 /* Adjust INSN after we made a change to its destination.
2440 Changing the destination can invalidate notes that say something about
2441 the results of the insn and a LOG_LINK pointing to the insn. */
2444 adjust_for_new_dest (rtx_insn
*insn
)
2446 /* For notes, be conservative and simply remove them. */
2447 remove_reg_equal_equiv_notes (insn
);
2449 /* The new insn will have a destination that was previously the destination
2450 of an insn just above it. Call distribute_links to make a LOG_LINK from
2451 the next use of that destination. */
2453 rtx set
= single_set (insn
);
2456 rtx reg
= SET_DEST (set
);
2458 while (GET_CODE (reg
) == ZERO_EXTRACT
2459 || GET_CODE (reg
) == STRICT_LOW_PART
2460 || GET_CODE (reg
) == SUBREG
)
2461 reg
= XEXP (reg
, 0);
2462 gcc_assert (REG_P (reg
));
2464 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2466 df_insn_rescan (insn
);
2469 /* Return TRUE if combine can reuse reg X in mode MODE.
2470 ADDED_SETS is nonzero if the original set is still required. */
2472 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2479 /* Don't change between modes with different underlying register sizes,
2480 since this could lead to invalid subregs. */
2481 if (maybe_ne (REGMODE_NATURAL_SIZE (mode
),
2482 REGMODE_NATURAL_SIZE (GET_MODE (x
))))
2486 /* Allow hard registers if the new mode is legal, and occupies no more
2487 registers than the old mode. */
2488 if (regno
< FIRST_PSEUDO_REGISTER
)
2489 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2490 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2492 /* Or a pseudo that is only used once. */
2493 return (regno
< reg_n_sets_max
2494 && REG_N_SETS (regno
) == 1
2496 && !REG_USERVAR_P (x
));
2500 /* Check whether X, the destination of a set, refers to part of
2501 the register specified by REG. */
2504 reg_subword_p (rtx x
, rtx reg
)
2506 /* Check that reg is an integer mode register. */
2507 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2510 if (GET_CODE (x
) == STRICT_LOW_PART
2511 || GET_CODE (x
) == ZERO_EXTRACT
)
2514 return GET_CODE (x
) == SUBREG
2515 && SUBREG_REG (x
) == reg
2516 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2519 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2520 Note that the INSN should be deleted *after* removing dead edges, so
2521 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2522 but not for a (set (pc) (label_ref FOO)). */
2525 update_cfg_for_uncondjump (rtx_insn
*insn
)
2527 basic_block bb
= BLOCK_FOR_INSN (insn
);
2528 gcc_assert (BB_END (bb
) == insn
);
2530 purge_dead_edges (bb
);
2533 if (EDGE_COUNT (bb
->succs
) == 1)
2537 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2539 /* Remove barriers from the footer if there are any. */
2540 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2541 if (BARRIER_P (insn
))
2543 if (PREV_INSN (insn
))
2544 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2546 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2547 if (NEXT_INSN (insn
))
2548 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2550 else if (LABEL_P (insn
))
2555 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2556 by an arbitrary number of CLOBBERs. */
2558 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2560 if (GET_CODE (pat
) != PARALLEL
)
2563 int len
= XVECLEN (pat
, 0);
2568 for (i
= 0; i
< n
; i
++)
2569 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2570 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2572 for ( ; i
< len
; i
++)
2573 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2574 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2580 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2581 CLOBBERs), can be split into individual SETs in that order, without
2582 changing semantics. */
2584 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2586 if (!insn_nothrow_p (insn
))
2589 rtx pat
= PATTERN (insn
);
2592 for (i
= 0; i
< n
; i
++)
2594 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2597 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2599 for (j
= i
+ 1; j
< n
; j
++)
2600 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2607 /* Try to combine the insns I0, I1 and I2 into I3.
2608 Here I0, I1 and I2 appear earlier than I3.
2609 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2612 If we are combining more than two insns and the resulting insn is not
2613 recognized, try splitting it into two insns. If that happens, I2 and I3
2614 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2615 Otherwise, I0, I1 and I2 are pseudo-deleted.
2617 Return 0 if the combination does not work. Then nothing is changed.
2618 If we did the combination, return the insn at which combine should
2621 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2622 new direct jump instruction.
2624 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2625 been I3 passed to an earlier try_combine within the same basic
2629 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2630 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2632 /* New patterns for I3 and I2, respectively. */
2633 rtx newpat
, newi2pat
= 0;
2634 rtvec newpat_vec_with_clobbers
= 0;
2635 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2636 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2638 int added_sets_0
, added_sets_1
, added_sets_2
;
2639 /* Total number of SETs to put into I3. */
2641 /* Nonzero if I2's or I1's body now appears in I3. */
2642 int i2_is_used
= 0, i1_is_used
= 0;
2643 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2644 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2645 /* Contains I3 if the destination of I3 is used in its source, which means
2646 that the old life of I3 is being killed. If that usage is placed into
2647 I2 and not in I3, a REG_DEAD note must be made. */
2648 rtx i3dest_killed
= 0;
2649 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2650 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2651 /* Copy of SET_SRC of I1 and I0, if needed. */
2652 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2653 /* Set if I2DEST was reused as a scratch register. */
2654 bool i2scratch
= false;
2655 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2656 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2657 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2658 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2659 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2660 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2661 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2662 /* Notes that must be added to REG_NOTES in I3 and I2. */
2663 rtx new_i3_notes
, new_i2_notes
;
2664 /* Notes that we substituted I3 into I2 instead of the normal case. */
2665 int i3_subst_into_i2
= 0;
2666 /* Notes that I1, I2 or I3 is a MULT operation. */
2670 int changed_i3_dest
= 0;
2673 rtx_insn
*temp_insn
;
2675 struct insn_link
*link
;
2677 rtx new_other_notes
;
2679 scalar_int_mode dest_mode
, temp_mode
;
2681 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2683 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2686 /* Only try four-insn combinations when there's high likelihood of
2687 success. Look for simple insns, such as loads of constants or
2688 binary operations involving a constant. */
2696 if (!flag_expensive_optimizations
)
2699 for (i
= 0; i
< 4; i
++)
2701 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2702 rtx set
= single_set (insn
);
2706 src
= SET_SRC (set
);
2707 if (CONSTANT_P (src
))
2712 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2714 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2715 || GET_CODE (src
) == LSHIFTRT
)
2719 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2720 are likely manipulating its value. Ideally we'll be able to combine
2721 all four insns into a bitfield insertion of some kind.
2723 Note the source in I0 might be inside a sign/zero extension and the
2724 memory modes in I0 and I3 might be different. So extract the address
2725 from the destination of I3 and search for it in the source of I0.
2727 In the event that there's a match but the source/dest do not actually
2728 refer to the same memory, the worst that happens is we try some
2729 combinations that we wouldn't have otherwise. */
2730 if ((set0
= single_set (i0
))
2731 /* Ensure the source of SET0 is a MEM, possibly buried inside
2733 && (GET_CODE (SET_SRC (set0
)) == MEM
2734 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2735 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2736 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2737 && (set3
= single_set (i3
))
2738 /* Ensure the destination of SET3 is a MEM. */
2739 && GET_CODE (SET_DEST (set3
)) == MEM
2740 /* Would it be better to extract the base address for the MEM
2741 in SET3 and look for that? I don't have cases where it matters
2742 but I could envision such cases. */
2743 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2746 if (ngood
< 2 && nshift
< 2)
2750 /* Exit early if one of the insns involved can't be used for
2753 || (i1
&& CALL_P (i1
))
2754 || (i0
&& CALL_P (i0
))
2755 || cant_combine_insn_p (i3
)
2756 || cant_combine_insn_p (i2
)
2757 || (i1
&& cant_combine_insn_p (i1
))
2758 || (i0
&& cant_combine_insn_p (i0
))
2759 || likely_spilled_retval_p (i3
))
2763 undobuf
.other_insn
= 0;
2765 /* Reset the hard register usage information. */
2766 CLEAR_HARD_REG_SET (newpat_used_regs
);
2768 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2771 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2772 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2774 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2775 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2777 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2778 INSN_UID (i2
), INSN_UID (i3
));
2781 dump_insn_slim (dump_file
, i0
);
2783 dump_insn_slim (dump_file
, i1
);
2784 dump_insn_slim (dump_file
, i2
);
2785 dump_insn_slim (dump_file
, i3
);
2788 /* If multiple insns feed into one of I2 or I3, they can be in any
2789 order. To simplify the code below, reorder them in sequence. */
2790 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2792 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2794 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2797 added_links_insn
= 0;
2798 added_notes_insn
= 0;
2800 /* First check for one important special case that the code below will
2801 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2802 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2803 we may be able to replace that destination with the destination of I3.
2804 This occurs in the common code where we compute both a quotient and
2805 remainder into a structure, in which case we want to do the computation
2806 directly into the structure to avoid register-register copies.
2808 Note that this case handles both multiple sets in I2 and also cases
2809 where I2 has a number of CLOBBERs inside the PARALLEL.
2811 We make very conservative checks below and only try to handle the
2812 most common cases of this. For example, we only handle the case
2813 where I2 and I3 are adjacent to avoid making difficult register
2816 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2817 && REG_P (SET_SRC (PATTERN (i3
)))
2818 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2819 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2820 && GET_CODE (PATTERN (i2
)) == PARALLEL
2821 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2822 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2823 below would need to check what is inside (and reg_overlap_mentioned_p
2824 doesn't support those codes anyway). Don't allow those destinations;
2825 the resulting insn isn't likely to be recognized anyway. */
2826 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2827 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2828 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2829 SET_DEST (PATTERN (i3
)))
2830 && next_active_insn (i2
) == i3
)
2832 rtx p2
= PATTERN (i2
);
2834 /* Make sure that the destination of I3,
2835 which we are going to substitute into one output of I2,
2836 is not used within another output of I2. We must avoid making this:
2837 (parallel [(set (mem (reg 69)) ...)
2838 (set (reg 69) ...)])
2839 which is not well-defined as to order of actions.
2840 (Besides, reload can't handle output reloads for this.)
2842 The problem can also happen if the dest of I3 is a memory ref,
2843 if another dest in I2 is an indirect memory ref.
2845 Neither can this PARALLEL be an asm. We do not allow combining
2846 that usually (see can_combine_p), so do not here either. */
2848 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2850 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2851 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2852 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2853 SET_DEST (XVECEXP (p2
, 0, i
))))
2855 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2856 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2861 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2862 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2863 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2868 subst_low_luid
= DF_INSN_LUID (i2
);
2870 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2871 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2872 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2873 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2875 /* Replace the dest in I2 with our dest and make the resulting
2876 insn the new pattern for I3. Then skip to where we validate
2877 the pattern. Everything was set up above. */
2878 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2880 i3_subst_into_i2
= 1;
2881 goto validate_replacement
;
2885 /* If I2 is setting a pseudo to a constant and I3 is setting some
2886 sub-part of it to another constant, merge them by making a new
2889 && (temp_expr
= single_set (i2
)) != 0
2890 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2891 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2892 && GET_CODE (PATTERN (i3
)) == SET
2893 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2894 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2896 rtx dest
= SET_DEST (PATTERN (i3
));
2897 rtx temp_dest
= SET_DEST (temp_expr
);
2901 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2903 if (CONST_INT_P (XEXP (dest
, 1))
2904 && CONST_INT_P (XEXP (dest
, 2))
2905 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2908 width
= INTVAL (XEXP (dest
, 1));
2909 offset
= INTVAL (XEXP (dest
, 2));
2910 dest
= XEXP (dest
, 0);
2911 if (BITS_BIG_ENDIAN
)
2912 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2917 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2918 dest
= XEXP (dest
, 0);
2919 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2921 width
= GET_MODE_PRECISION (dest_mode
);
2928 /* If this is the low part, we're done. */
2929 if (subreg_lowpart_p (dest
))
2931 /* Handle the case where inner is twice the size of outer. */
2932 else if (GET_MODE_PRECISION (temp_mode
)
2933 == 2 * GET_MODE_PRECISION (dest_mode
))
2934 offset
+= GET_MODE_PRECISION (dest_mode
);
2935 /* Otherwise give up for now. */
2942 rtx inner
= SET_SRC (PATTERN (i3
));
2943 rtx outer
= SET_SRC (temp_expr
);
2945 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2946 rtx_mode_t (inner
, dest_mode
),
2951 subst_low_luid
= DF_INSN_LUID (i2
);
2952 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2954 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2956 /* Replace the source in I2 with the new constant and make the
2957 resulting insn the new pattern for I3. Then skip to where we
2958 validate the pattern. Everything was set up above. */
2959 SUBST (SET_SRC (temp_expr
),
2960 immed_wide_int_const (o
, temp_mode
));
2962 newpat
= PATTERN (i2
);
2964 /* The dest of I3 has been replaced with the dest of I2. */
2965 changed_i3_dest
= 1;
2966 goto validate_replacement
;
2970 /* If we have no I1 and I2 looks like:
2971 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2973 make up a dummy I1 that is
2976 (set (reg:CC X) (compare:CC Y (const_int 0)))
2978 (We can ignore any trailing CLOBBERs.)
2980 This undoes a previous combination and allows us to match a branch-and-
2983 if (!HAVE_cc0
&& i1
== 0
2984 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2985 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2987 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2988 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2989 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2990 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2991 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2992 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2994 /* We make I1 with the same INSN_UID as I2. This gives it
2995 the same DF_INSN_LUID for value tracking. Our fake I1 will
2996 never appear in the insn stream so giving it the same INSN_UID
2997 as I2 will not cause a problem. */
2999 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3000 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3002 INSN_UID (i1
) = INSN_UID (i2
);
3004 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3005 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3006 SET_DEST (PATTERN (i1
)));
3007 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3008 SUBST_LINK (LOG_LINKS (i2
),
3009 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3012 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3013 make those two SETs separate I1 and I2 insns, and make an I0 that is
3015 if (!HAVE_cc0
&& i0
== 0
3016 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3017 && can_split_parallel_of_n_reg_sets (i2
, 2)
3018 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3019 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
3020 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3021 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3023 /* If there is no I1, there is no I0 either. */
3026 /* We make I1 with the same INSN_UID as I2. This gives it
3027 the same DF_INSN_LUID for value tracking. Our fake I1 will
3028 never appear in the insn stream so giving it the same INSN_UID
3029 as I2 will not cause a problem. */
3031 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3032 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3034 INSN_UID (i1
) = INSN_UID (i2
);
3036 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3039 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3040 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
3043 fprintf (dump_file
, "Can't combine i2 into i3\n");
3047 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
3050 fprintf (dump_file
, "Can't combine i1 into i3\n");
3054 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
3057 fprintf (dump_file
, "Can't combine i0 into i3\n");
3062 /* Record whether I2DEST is used in I2SRC and similarly for the other
3063 cases. Knowing this will help in register status updating below. */
3064 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3065 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3066 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3067 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3068 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3069 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3070 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3071 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3072 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3074 /* For the earlier insns, determine which of the subsequent ones they
3076 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3077 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3078 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3079 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3080 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3082 /* Ensure that I3's pattern can be the destination of combines. */
3083 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3084 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3085 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3086 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3093 /* See if any of the insns is a MULT operation. Unless one is, we will
3094 reject a combination that is, since it must be slower. Be conservative
3096 if (GET_CODE (i2src
) == MULT
3097 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3098 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3099 || (GET_CODE (PATTERN (i3
)) == SET
3100 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3103 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3104 We used to do this EXCEPT in one case: I3 has a post-inc in an
3105 output operand. However, that exception can give rise to insns like
3107 which is a famous insn on the PDP-11 where the value of r3 used as the
3108 source was model-dependent. Avoid this sort of thing. */
3111 if (!(GET_CODE (PATTERN (i3
)) == SET
3112 && REG_P (SET_SRC (PATTERN (i3
)))
3113 && MEM_P (SET_DEST (PATTERN (i3
)))
3114 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3115 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3116 /* It's not the exception. */
3121 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3122 if (REG_NOTE_KIND (link
) == REG_INC
3123 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3125 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3132 /* See if the SETs in I1 or I2 need to be kept around in the merged
3133 instruction: whenever the value set there is still needed past I3.
3134 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3136 For the SET in I1, we have two cases: if I1 and I2 independently feed
3137 into I3, the set in I1 needs to be kept around unless I1DEST dies
3138 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3139 in I1 needs to be kept around unless I1DEST dies or is set in either
3140 I2 or I3. The same considerations apply to I0. */
3142 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3145 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3146 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3151 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3152 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3153 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3154 && dead_or_set_p (i2
, i0dest
)));
3158 /* We are about to copy insns for the case where they need to be kept
3159 around. Check that they can be copied in the merged instruction. */
3161 if (targetm
.cannot_copy_insn_p
3162 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3163 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3164 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3170 /* If the set in I2 needs to be kept around, we must make a copy of
3171 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3172 PATTERN (I2), we are only substituting for the original I1DEST, not into
3173 an already-substituted copy. This also prevents making self-referential
3174 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3179 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3180 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3182 i2pat
= copy_rtx (PATTERN (i2
));
3187 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3188 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3190 i1pat
= copy_rtx (PATTERN (i1
));
3195 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3196 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3198 i0pat
= copy_rtx (PATTERN (i0
));
3203 /* Substitute in the latest insn for the regs set by the earlier ones. */
3205 maxreg
= max_reg_num ();
3209 /* Many machines that don't use CC0 have insns that can both perform an
3210 arithmetic operation and set the condition code. These operations will
3211 be represented as a PARALLEL with the first element of the vector
3212 being a COMPARE of an arithmetic operation with the constant zero.
3213 The second element of the vector will set some pseudo to the result
3214 of the same arithmetic operation. If we simplify the COMPARE, we won't
3215 match such a pattern and so will generate an extra insn. Here we test
3216 for this case, where both the comparison and the operation result are
3217 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3218 I2SRC. Later we will make the PARALLEL that contains I2. */
3220 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3221 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3222 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3223 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3226 rtx
*cc_use_loc
= NULL
;
3227 rtx_insn
*cc_use_insn
= NULL
;
3228 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3229 machine_mode compare_mode
, orig_compare_mode
;
3230 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3231 scalar_int_mode mode
;
3233 newpat
= PATTERN (i3
);
3234 newpat_dest
= SET_DEST (newpat
);
3235 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3237 if (undobuf
.other_insn
== 0
3238 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3241 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3242 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3243 compare_code
= simplify_compare_const (compare_code
, mode
,
3245 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3248 /* Do the rest only if op1 is const0_rtx, which may be the
3249 result of simplification. */
3250 if (op1
== const0_rtx
)
3252 /* If a single use of the CC is found, prepare to modify it
3253 when SELECT_CC_MODE returns a new CC-class mode, or when
3254 the above simplify_compare_const() returned a new comparison
3255 operator. undobuf.other_insn is assigned the CC use insn
3256 when modifying it. */
3259 #ifdef SELECT_CC_MODE
3260 machine_mode new_mode
3261 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3262 if (new_mode
!= orig_compare_mode
3263 && can_change_dest_mode (SET_DEST (newpat
),
3264 added_sets_2
, new_mode
))
3266 unsigned int regno
= REGNO (newpat_dest
);
3267 compare_mode
= new_mode
;
3268 if (regno
< FIRST_PSEUDO_REGISTER
)
3269 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3272 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3273 newpat_dest
= regno_reg_rtx
[regno
];
3277 /* Cases for modifying the CC-using comparison. */
3278 if (compare_code
!= orig_compare_code
3279 /* ??? Do we need to verify the zero rtx? */
3280 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3282 /* Replace cc_use_loc with entire new RTX. */
3284 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3285 newpat_dest
, const0_rtx
));
3286 undobuf
.other_insn
= cc_use_insn
;
3288 else if (compare_mode
!= orig_compare_mode
)
3290 /* Just replace the CC reg with a new mode. */
3291 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3292 undobuf
.other_insn
= cc_use_insn
;
3296 /* Now we modify the current newpat:
3297 First, SET_DEST(newpat) is updated if the CC mode has been
3298 altered. For targets without SELECT_CC_MODE, this should be
3300 if (compare_mode
!= orig_compare_mode
)
3301 SUBST (SET_DEST (newpat
), newpat_dest
);
3302 /* This is always done to propagate i2src into newpat. */
3303 SUBST (SET_SRC (newpat
),
3304 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3305 /* Create new version of i2pat if needed; the below PARALLEL
3306 creation needs this to work correctly. */
3307 if (! rtx_equal_p (i2src
, op0
))
3308 i2pat
= gen_rtx_SET (i2dest
, op0
);
3313 if (i2_is_used
== 0)
3315 /* It is possible that the source of I2 or I1 may be performing
3316 an unneeded operation, such as a ZERO_EXTEND of something
3317 that is known to have the high part zero. Handle that case
3318 by letting subst look at the inner insns.
3320 Another way to do this would be to have a function that tries
3321 to simplify a single insn instead of merging two or more
3322 insns. We don't do this because of the potential of infinite
3323 loops and because of the potential extra memory required.
3324 However, doing it the way we are is a bit of a kludge and
3325 doesn't catch all cases.
3327 But only do this if -fexpensive-optimizations since it slows
3328 things down and doesn't usually win.
3330 This is not done in the COMPARE case above because the
3331 unmodified I2PAT is used in the PARALLEL and so a pattern
3332 with a modified I2SRC would not match. */
3334 if (flag_expensive_optimizations
)
3336 /* Pass pc_rtx so no substitutions are done, just
3340 subst_low_luid
= DF_INSN_LUID (i1
);
3341 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3344 subst_low_luid
= DF_INSN_LUID (i2
);
3345 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3348 n_occurrences
= 0; /* `subst' counts here */
3349 subst_low_luid
= DF_INSN_LUID (i2
);
3351 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3352 copy of I2SRC each time we substitute it, in order to avoid creating
3353 self-referential RTL when we will be substituting I1SRC for I1DEST
3354 later. Likewise if I0 feeds into I2, either directly or indirectly
3355 through I1, and I0DEST is in I0SRC. */
3356 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3357 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3358 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3359 && i0dest_in_i0src
));
3362 /* Record whether I2's body now appears within I3's body. */
3363 i2_is_used
= n_occurrences
;
3366 /* If we already got a failure, don't try to do more. Otherwise, try to
3367 substitute I1 if we have it. */
3369 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3371 /* Check that an autoincrement side-effect on I1 has not been lost.
3372 This happens if I1DEST is mentioned in I2 and dies there, and
3373 has disappeared from the new pattern. */
3374 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3376 && dead_or_set_p (i2
, i1dest
)
3377 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3378 /* Before we can do this substitution, we must redo the test done
3379 above (see detailed comments there) that ensures I1DEST isn't
3380 mentioned in any SETs in NEWPAT that are field assignments. */
3381 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3389 subst_low_luid
= DF_INSN_LUID (i1
);
3391 /* If the following substitution will modify I1SRC, make a copy of it
3392 for the case where it is substituted for I1DEST in I2PAT later. */
3393 if (added_sets_2
&& i1_feeds_i2_n
)
3394 i1src_copy
= copy_rtx (i1src
);
3396 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3397 copy of I1SRC each time we substitute it, in order to avoid creating
3398 self-referential RTL when we will be substituting I0SRC for I0DEST
3400 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3401 i0_feeds_i1_n
&& i0dest_in_i0src
);
3404 /* Record whether I1's body now appears within I3's body. */
3405 i1_is_used
= n_occurrences
;
3408 /* Likewise for I0 if we have it. */
3410 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3412 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3413 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3414 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3415 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3416 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3423 /* If the following substitution will modify I0SRC, make a copy of it
3424 for the case where it is substituted for I0DEST in I1PAT later. */
3425 if (added_sets_1
&& i0_feeds_i1_n
)
3426 i0src_copy
= copy_rtx (i0src
);
3427 /* And a copy for I0DEST in I2PAT substitution. */
3428 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3429 || (i0_feeds_i2_n
)))
3430 i0src_copy2
= copy_rtx (i0src
);
3433 subst_low_luid
= DF_INSN_LUID (i0
);
3434 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3438 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3439 to count all the ways that I2SRC and I1SRC can be used. */
3440 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3441 && i2_is_used
+ added_sets_2
> 1)
3442 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3443 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3445 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3446 && (n_occurrences
+ added_sets_0
3447 + (added_sets_1
&& i0_feeds_i1_n
)
3448 + (added_sets_2
&& i0_feeds_i2_n
)
3450 /* Fail if we tried to make a new register. */
3451 || max_reg_num () != maxreg
3452 /* Fail if we couldn't do something and have a CLOBBER. */
3453 || GET_CODE (newpat
) == CLOBBER
3454 /* Fail if this new pattern is a MULT and we didn't have one before
3455 at the outer level. */
3456 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3463 /* If the actions of the earlier insns must be kept
3464 in addition to substituting them into the latest one,
3465 we must make a new PARALLEL for the latest insn
3466 to hold additional the SETs. */
3468 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3470 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3473 if (GET_CODE (newpat
) == PARALLEL
)
3475 rtvec old
= XVEC (newpat
, 0);
3476 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3477 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3478 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3479 sizeof (old
->elem
[0]) * old
->num_elem
);
3484 total_sets
= 1 + extra_sets
;
3485 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3486 XVECEXP (newpat
, 0, 0) = old
;
3490 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3496 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3498 XVECEXP (newpat
, 0, --total_sets
) = t
;
3504 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3505 i0_feeds_i1_n
&& i0dest_in_i0src
);
3506 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3507 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3509 XVECEXP (newpat
, 0, --total_sets
) = t
;
3513 validate_replacement
:
3515 /* Note which hard regs this insn has as inputs. */
3516 mark_used_regs_combine (newpat
);
3518 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3519 consider splitting this pattern, we might need these clobbers. */
3520 if (i1
&& GET_CODE (newpat
) == PARALLEL
3521 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3523 int len
= XVECLEN (newpat
, 0);
3525 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3526 for (i
= 0; i
< len
; i
++)
3527 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3530 /* We have recognized nothing yet. */
3531 insn_code_number
= -1;
3533 /* See if this is a PARALLEL of two SETs where one SET's destination is
3534 a register that is unused and this isn't marked as an instruction that
3535 might trap in an EH region. In that case, we just need the other SET.
3536 We prefer this over the PARALLEL.
3538 This can occur when simplifying a divmod insn. We *must* test for this
3539 case here because the code below that splits two independent SETs doesn't
3540 handle this case correctly when it updates the register status.
3542 It's pointless doing this if we originally had two sets, one from
3543 i3, and one from i2. Combining then splitting the parallel results
3544 in the original i2 again plus an invalid insn (which we delete).
3545 The net effect is only to move instructions around, which makes
3546 debug info less accurate.
3548 If the remaining SET came from I2 its destination should not be used
3549 between I2 and I3. See PR82024. */
3551 if (!(added_sets_2
&& i1
== 0)
3552 && is_parallel_of_n_reg_sets (newpat
, 2)
3553 && asm_noperands (newpat
) < 0)
3555 rtx set0
= XVECEXP (newpat
, 0, 0);
3556 rtx set1
= XVECEXP (newpat
, 0, 1);
3557 rtx oldpat
= newpat
;
3559 if (((REG_P (SET_DEST (set1
))
3560 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3561 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3562 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3563 && insn_nothrow_p (i3
)
3564 && !side_effects_p (SET_SRC (set1
)))
3567 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3570 else if (((REG_P (SET_DEST (set0
))
3571 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3572 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3573 && find_reg_note (i3
, REG_UNUSED
,
3574 SUBREG_REG (SET_DEST (set0
)))))
3575 && insn_nothrow_p (i3
)
3576 && !side_effects_p (SET_SRC (set0
)))
3578 rtx dest
= SET_DEST (set1
);
3579 if (GET_CODE (dest
) == SUBREG
)
3580 dest
= SUBREG_REG (dest
);
3581 if (!reg_used_between_p (dest
, i2
, i3
))
3584 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3586 if (insn_code_number
>= 0)
3587 changed_i3_dest
= 1;
3591 if (insn_code_number
< 0)
3595 /* Is the result of combination a valid instruction? */
3596 if (insn_code_number
< 0)
3597 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3599 /* If we were combining three insns and the result is a simple SET
3600 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3601 insns. There are two ways to do this. It can be split using a
3602 machine-specific method (like when you have an addition of a large
3603 constant) or by combine in the function find_split_point. */
3605 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3606 && asm_noperands (newpat
) < 0)
3608 rtx parallel
, *split
;
3609 rtx_insn
*m_split_insn
;
3611 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3612 use I2DEST as a scratch register will help. In the latter case,
3613 convert I2DEST to the mode of the source of NEWPAT if we can. */
3615 m_split_insn
= combine_split_insns (newpat
, i3
);
3617 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3618 inputs of NEWPAT. */
3620 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3621 possible to try that as a scratch reg. This would require adding
3622 more code to make it work though. */
3624 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3626 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3628 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3629 (temporarily, until we are committed to this instruction
3630 combination) does not work: for example, any call to nonzero_bits
3631 on the register (from a splitter in the MD file, for example)
3632 will get the old information, which is invalid.
3634 Since nowadays we can create registers during combine just fine,
3635 we should just create a new one here, not reuse i2dest. */
3637 /* First try to split using the original register as a
3638 scratch register. */
3639 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3640 gen_rtvec (2, newpat
,
3641 gen_rtx_CLOBBER (VOIDmode
,
3643 m_split_insn
= combine_split_insns (parallel
, i3
);
3645 /* If that didn't work, try changing the mode of I2DEST if
3647 if (m_split_insn
== 0
3648 && new_mode
!= GET_MODE (i2dest
)
3649 && new_mode
!= VOIDmode
3650 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3652 machine_mode old_mode
= GET_MODE (i2dest
);
3655 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3656 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3659 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3660 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3663 parallel
= (gen_rtx_PARALLEL
3665 gen_rtvec (2, newpat
,
3666 gen_rtx_CLOBBER (VOIDmode
,
3668 m_split_insn
= combine_split_insns (parallel
, i3
);
3670 if (m_split_insn
== 0
3671 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3675 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3676 buf
= undobuf
.undos
;
3677 undobuf
.undos
= buf
->next
;
3678 buf
->next
= undobuf
.frees
;
3679 undobuf
.frees
= buf
;
3683 i2scratch
= m_split_insn
!= 0;
3686 /* If recog_for_combine has discarded clobbers, try to use them
3687 again for the split. */
3688 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3690 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3691 m_split_insn
= combine_split_insns (parallel
, i3
);
3694 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3696 rtx m_split_pat
= PATTERN (m_split_insn
);
3697 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3698 if (insn_code_number
>= 0)
3699 newpat
= m_split_pat
;
3701 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3702 && (next_nonnote_nondebug_insn (i2
) == i3
3703 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3706 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3707 newi2pat
= PATTERN (m_split_insn
);
3709 i3set
= single_set (NEXT_INSN (m_split_insn
));
3710 i2set
= single_set (m_split_insn
);
3712 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3714 /* If I2 or I3 has multiple SETs, we won't know how to track
3715 register status, so don't use these insns. If I2's destination
3716 is used between I2 and I3, we also can't use these insns. */
3718 if (i2_code_number
>= 0 && i2set
&& i3set
3719 && (next_nonnote_nondebug_insn (i2
) == i3
3720 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3721 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3723 if (insn_code_number
>= 0)
3726 /* It is possible that both insns now set the destination of I3.
3727 If so, we must show an extra use of it. */
3729 if (insn_code_number
>= 0)
3731 rtx new_i3_dest
= SET_DEST (i3set
);
3732 rtx new_i2_dest
= SET_DEST (i2set
);
3734 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3735 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3736 || GET_CODE (new_i3_dest
) == SUBREG
)
3737 new_i3_dest
= XEXP (new_i3_dest
, 0);
3739 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3740 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3741 || GET_CODE (new_i2_dest
) == SUBREG
)
3742 new_i2_dest
= XEXP (new_i2_dest
, 0);
3744 if (REG_P (new_i3_dest
)
3745 && REG_P (new_i2_dest
)
3746 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3747 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3748 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3752 /* If we can split it and use I2DEST, go ahead and see if that
3753 helps things be recognized. Verify that none of the registers
3754 are set between I2 and I3. */
3755 if (insn_code_number
< 0
3756 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3757 && (!HAVE_cc0
|| REG_P (i2dest
))
3758 /* We need I2DEST in the proper mode. If it is a hard register
3759 or the only use of a pseudo, we can change its mode.
3760 Make sure we don't change a hard register to have a mode that
3761 isn't valid for it, or change the number of registers. */
3762 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3763 || GET_MODE (*split
) == VOIDmode
3764 || can_change_dest_mode (i2dest
, added_sets_2
,
3766 && (next_nonnote_nondebug_insn (i2
) == i3
3767 || !modified_between_p (*split
, i2
, i3
))
3768 /* We can't overwrite I2DEST if its value is still used by
3770 && ! reg_referenced_p (i2dest
, newpat
))
3772 rtx newdest
= i2dest
;
3773 enum rtx_code split_code
= GET_CODE (*split
);
3774 machine_mode split_mode
= GET_MODE (*split
);
3775 bool subst_done
= false;
3776 newi2pat
= NULL_RTX
;
3780 /* *SPLIT may be part of I2SRC, so make sure we have the
3781 original expression around for later debug processing.
3782 We should not need I2SRC any more in other cases. */
3783 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3784 i2src
= copy_rtx (i2src
);
3788 /* Get NEWDEST as a register in the proper mode. We have already
3789 validated that we can do this. */
3790 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3792 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3793 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3796 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3797 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3801 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3802 an ASHIFT. This can occur if it was inside a PLUS and hence
3803 appeared to be a memory address. This is a kludge. */
3804 if (split_code
== MULT
3805 && CONST_INT_P (XEXP (*split
, 1))
3806 && INTVAL (XEXP (*split
, 1)) > 0
3807 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3809 rtx i_rtx
= gen_int_shift_amount (split_mode
, i
);
3810 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3811 XEXP (*split
, 0), i_rtx
));
3812 /* Update split_code because we may not have a multiply
3814 split_code
= GET_CODE (*split
);
3817 /* Similarly for (plus (mult FOO (const_int pow2))). */
3818 if (split_code
== PLUS
3819 && GET_CODE (XEXP (*split
, 0)) == MULT
3820 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3821 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3822 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3824 rtx nsplit
= XEXP (*split
, 0);
3825 rtx i_rtx
= gen_int_shift_amount (GET_MODE (nsplit
), i
);
3826 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3829 /* Update split_code because we may not have a multiply
3831 split_code
= GET_CODE (*split
);
3834 #ifdef INSN_SCHEDULING
3835 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3836 be written as a ZERO_EXTEND. */
3837 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3839 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3840 what it really is. */
3841 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3843 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3844 SUBREG_REG (*split
)));
3846 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3847 SUBREG_REG (*split
)));
3851 /* Attempt to split binary operators using arithmetic identities. */
3852 if (BINARY_P (SET_SRC (newpat
))
3853 && split_mode
== GET_MODE (SET_SRC (newpat
))
3854 && ! side_effects_p (SET_SRC (newpat
)))
3856 rtx setsrc
= SET_SRC (newpat
);
3857 machine_mode mode
= GET_MODE (setsrc
);
3858 enum rtx_code code
= GET_CODE (setsrc
);
3859 rtx src_op0
= XEXP (setsrc
, 0);
3860 rtx src_op1
= XEXP (setsrc
, 1);
3862 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3863 if (rtx_equal_p (src_op0
, src_op1
))
3865 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3866 SUBST (XEXP (setsrc
, 0), newdest
);
3867 SUBST (XEXP (setsrc
, 1), newdest
);
3870 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3871 else if ((code
== PLUS
|| code
== MULT
)
3872 && GET_CODE (src_op0
) == code
3873 && GET_CODE (XEXP (src_op0
, 0)) == code
3874 && (INTEGRAL_MODE_P (mode
)
3875 || (FLOAT_MODE_P (mode
)
3876 && flag_unsafe_math_optimizations
)))
3878 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3879 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3880 rtx r
= XEXP (src_op0
, 1);
3883 /* Split both "((X op Y) op X) op Y" and
3884 "((X op Y) op Y) op X" as "T op T" where T is
3886 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3887 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3889 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3890 SUBST (XEXP (setsrc
, 0), newdest
);
3891 SUBST (XEXP (setsrc
, 1), newdest
);
3894 /* Split "((X op X) op Y) op Y)" as "T op T" where
3896 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3898 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3899 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3900 SUBST (XEXP (setsrc
, 0), newdest
);
3901 SUBST (XEXP (setsrc
, 1), newdest
);
3909 newi2pat
= gen_rtx_SET (newdest
, *split
);
3910 SUBST (*split
, newdest
);
3913 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3915 /* recog_for_combine might have added CLOBBERs to newi2pat.
3916 Make sure NEWPAT does not depend on the clobbered regs. */
3917 if (GET_CODE (newi2pat
) == PARALLEL
)
3918 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3919 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3921 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3922 if (reg_overlap_mentioned_p (reg
, newpat
))
3929 /* If the split point was a MULT and we didn't have one before,
3930 don't use one now. */
3931 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3932 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3936 /* Check for a case where we loaded from memory in a narrow mode and
3937 then sign extended it, but we need both registers. In that case,
3938 we have a PARALLEL with both loads from the same memory location.
3939 We can split this into a load from memory followed by a register-register
3940 copy. This saves at least one insn, more if register allocation can
3943 We cannot do this if the destination of the first assignment is a
3944 condition code register or cc0. We eliminate this case by making sure
3945 the SET_DEST and SET_SRC have the same mode.
3947 We cannot do this if the destination of the second assignment is
3948 a register that we have already assumed is zero-extended. Similarly
3949 for a SUBREG of such a register. */
3951 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3952 && GET_CODE (newpat
) == PARALLEL
3953 && XVECLEN (newpat
, 0) == 2
3954 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3955 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3956 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3957 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3958 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3959 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3960 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3961 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
3962 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3963 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3964 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3966 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3967 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3969 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3971 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3972 != GET_MODE_MASK (word_mode
))))
3973 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3974 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3976 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3977 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3979 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3981 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3982 != GET_MODE_MASK (word_mode
)))))
3983 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3984 SET_SRC (XVECEXP (newpat
, 0, 1)))
3985 && ! find_reg_note (i3
, REG_UNUSED
,
3986 SET_DEST (XVECEXP (newpat
, 0, 0))))
3990 newi2pat
= XVECEXP (newpat
, 0, 0);
3991 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3992 newpat
= XVECEXP (newpat
, 0, 1);
3993 SUBST (SET_SRC (newpat
),
3994 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3995 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3997 if (i2_code_number
>= 0)
3998 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4000 if (insn_code_number
>= 0)
4004 /* Similarly, check for a case where we have a PARALLEL of two independent
4005 SETs but we started with three insns. In this case, we can do the sets
4006 as two separate insns. This case occurs when some SET allows two
4007 other insns to combine, but the destination of that SET is still live.
4009 Also do this if we started with two insns and (at least) one of the
4010 resulting sets is a noop; this noop will be deleted later. */
4012 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
4013 && GET_CODE (newpat
) == PARALLEL
4014 && XVECLEN (newpat
, 0) == 2
4015 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
4016 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4017 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
4018 || set_noop_p (XVECEXP (newpat
, 0, 1)))
4019 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
4020 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4021 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4022 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4023 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4024 XVECEXP (newpat
, 0, 0))
4025 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4026 XVECEXP (newpat
, 0, 1))
4027 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4028 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4030 rtx set0
= XVECEXP (newpat
, 0, 0);
4031 rtx set1
= XVECEXP (newpat
, 0, 1);
4033 /* Normally, it doesn't matter which of the two is done first,
4034 but the one that references cc0 can't be the second, and
4035 one which uses any regs/memory set in between i2 and i3 can't
4036 be first. The PARALLEL might also have been pre-existing in i3,
4037 so we need to make sure that we won't wrongly hoist a SET to i2
4038 that would conflict with a death note present in there. */
4039 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
4040 && !(REG_P (SET_DEST (set1
))
4041 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4042 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4043 && find_reg_note (i2
, REG_DEAD
,
4044 SUBREG_REG (SET_DEST (set1
))))
4045 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4046 /* If I3 is a jump, ensure that set0 is a jump so that
4047 we do not create invalid RTL. */
4048 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4054 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4055 && !(REG_P (SET_DEST (set0
))
4056 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4057 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4058 && find_reg_note (i2
, REG_DEAD
,
4059 SUBREG_REG (SET_DEST (set0
))))
4060 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4061 /* If I3 is a jump, ensure that set1 is a jump so that
4062 we do not create invalid RTL. */
4063 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4075 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4077 if (i2_code_number
>= 0)
4079 /* recog_for_combine might have added CLOBBERs to newi2pat.
4080 Make sure NEWPAT does not depend on the clobbered regs. */
4081 if (GET_CODE (newi2pat
) == PARALLEL
)
4083 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4084 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4086 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4087 if (reg_overlap_mentioned_p (reg
, newpat
))
4095 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4097 if (insn_code_number
>= 0)
4102 /* If it still isn't recognized, fail and change things back the way they
4104 if ((insn_code_number
< 0
4105 /* Is the result a reasonable ASM_OPERANDS? */
4106 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4112 /* If we had to change another insn, make sure it is valid also. */
4113 if (undobuf
.other_insn
)
4115 CLEAR_HARD_REG_SET (newpat_used_regs
);
4117 other_pat
= PATTERN (undobuf
.other_insn
);
4118 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4121 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4128 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4129 they are adjacent to each other or not. */
4132 rtx_insn
*p
= prev_nonnote_insn (i3
);
4133 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4134 && sets_cc0_p (newi2pat
))
4141 /* Only allow this combination if insn_cost reports that the
4142 replacement instructions are cheaper than the originals. */
4143 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4149 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4153 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4154 if (undo
->kind
== UNDO_MODE
)
4156 rtx reg
= *undo
->where
.r
;
4157 machine_mode new_mode
= GET_MODE (reg
);
4158 machine_mode old_mode
= undo
->old_contents
.m
;
4160 /* Temporarily revert mode back. */
4161 adjust_reg_mode (reg
, old_mode
);
4163 if (reg
== i2dest
&& i2scratch
)
4165 /* If we used i2dest as a scratch register with a
4166 different mode, substitute it for the original
4167 i2src while its original mode is temporarily
4168 restored, and then clear i2scratch so that we don't
4169 do it again later. */
4170 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4173 /* Put back the new mode. */
4174 adjust_reg_mode (reg
, new_mode
);
4178 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4179 rtx_insn
*first
, *last
;
4184 last
= last_combined_insn
;
4189 last
= undobuf
.other_insn
;
4191 if (DF_INSN_LUID (last
)
4192 < DF_INSN_LUID (last_combined_insn
))
4193 last
= last_combined_insn
;
4196 /* We're dealing with a reg that changed mode but not
4197 meaning, so we want to turn it into a subreg for
4198 the new mode. However, because of REG sharing and
4199 because its mode had already changed, we have to do
4200 it in two steps. First, replace any debug uses of
4201 reg, with its original mode temporarily restored,
4202 with this copy we have created; then, replace the
4203 copy with the SUBREG of the original shared reg,
4204 once again changed to the new mode. */
4205 propagate_for_debug (first
, last
, reg
, tempreg
,
4207 adjust_reg_mode (reg
, new_mode
);
4208 propagate_for_debug (first
, last
, tempreg
,
4209 lowpart_subreg (old_mode
, reg
, new_mode
),
4215 /* If we will be able to accept this, we have made a
4216 change to the destination of I3. This requires us to
4217 do a few adjustments. */
4219 if (changed_i3_dest
)
4221 PATTERN (i3
) = newpat
;
4222 adjust_for_new_dest (i3
);
4225 /* We now know that we can do this combination. Merge the insns and
4226 update the status of registers and LOG_LINKS. */
4228 if (undobuf
.other_insn
)
4232 PATTERN (undobuf
.other_insn
) = other_pat
;
4234 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4235 ensure that they are still valid. Then add any non-duplicate
4236 notes added by recog_for_combine. */
4237 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4239 next
= XEXP (note
, 1);
4241 if ((REG_NOTE_KIND (note
) == REG_DEAD
4242 && !reg_referenced_p (XEXP (note
, 0),
4243 PATTERN (undobuf
.other_insn
)))
4244 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4245 && !reg_set_p (XEXP (note
, 0),
4246 PATTERN (undobuf
.other_insn
)))
4247 /* Simply drop equal note since it may be no longer valid
4248 for other_insn. It may be possible to record that CC
4249 register is changed and only discard those notes, but
4250 in practice it's unnecessary complication and doesn't
4251 give any meaningful improvement.
4254 || REG_NOTE_KIND (note
) == REG_EQUAL
4255 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4256 remove_note (undobuf
.other_insn
, note
);
4259 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4260 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4266 /* I3 now uses what used to be its destination and which is now
4267 I2's destination. This requires us to do a few adjustments. */
4268 PATTERN (i3
) = newpat
;
4269 adjust_for_new_dest (i3
);
4272 if (swap_i2i3
|| split_i2i3
)
4274 /* We might need a LOG_LINK from I3 to I2. But then we used to
4275 have one, so we still will.
4277 However, some later insn might be using I2's dest and have
4278 a LOG_LINK pointing at I3. We should change it to point at
4281 /* newi2pat is usually a SET here; however, recog_for_combine might
4282 have added some clobbers. */
4284 if (GET_CODE (x
) == PARALLEL
)
4285 x
= XVECEXP (newi2pat
, 0, 0);
4287 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4288 unsigned int regno
= reg_or_subregno (SET_DEST (x
));
4291 for (rtx_insn
*insn
= NEXT_INSN (i3
);
4294 && NONDEBUG_INSN_P (insn
)
4295 && BLOCK_FOR_INSN (insn
) == this_basic_block
;
4296 insn
= NEXT_INSN (insn
))
4298 struct insn_link
*link
;
4299 FOR_EACH_LOG_LINK (link
, insn
)
4300 if (link
->insn
== i3
&& link
->regno
== regno
)
4310 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4311 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4314 /* Compute which registers we expect to eliminate. newi2pat may be setting
4315 either i3dest or i2dest, so we must check it. */
4316 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4317 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4320 /* For i1, we need to compute both local elimination and global
4321 elimination information with respect to newi2pat because i1dest
4322 may be the same as i3dest, in which case newi2pat may be setting
4323 i1dest. Global information is used when distributing REG_DEAD
4324 note for i2 and i3, in which case it does matter if newi2pat sets
4327 Local information is used when distributing REG_DEAD note for i1,
4328 in which case it doesn't matter if newi2pat sets i1dest or not.
4329 See PR62151, if we have four insns combination:
4331 i1: r1 <- i1src (using r0)
4333 i2: r0 <- i2src (using r1)
4334 i3: r3 <- i3src (using r0)
4336 From i1's point of view, r0 is eliminated, no matter if it is set
4337 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4338 should be discarded.
4340 Note local information only affects cases in forms like "I1->I2->I3",
4341 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4342 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4344 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4347 rtx elim_i1
= (local_elim_i1
== 0
4348 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4350 /* Same case as i1. */
4351 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4353 rtx elim_i0
= (local_elim_i0
== 0
4354 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4357 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4359 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4360 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4362 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4364 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4366 /* Ensure that we do not have something that should not be shared but
4367 occurs multiple times in the new insns. Check this by first
4368 resetting all the `used' flags and then copying anything is shared. */
4370 reset_used_flags (i3notes
);
4371 reset_used_flags (i2notes
);
4372 reset_used_flags (i1notes
);
4373 reset_used_flags (i0notes
);
4374 reset_used_flags (newpat
);
4375 reset_used_flags (newi2pat
);
4376 if (undobuf
.other_insn
)
4377 reset_used_flags (PATTERN (undobuf
.other_insn
));
4379 i3notes
= copy_rtx_if_shared (i3notes
);
4380 i2notes
= copy_rtx_if_shared (i2notes
);
4381 i1notes
= copy_rtx_if_shared (i1notes
);
4382 i0notes
= copy_rtx_if_shared (i0notes
);
4383 newpat
= copy_rtx_if_shared (newpat
);
4384 newi2pat
= copy_rtx_if_shared (newi2pat
);
4385 if (undobuf
.other_insn
)
4386 reset_used_flags (PATTERN (undobuf
.other_insn
));
4388 INSN_CODE (i3
) = insn_code_number
;
4389 PATTERN (i3
) = newpat
;
4391 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4393 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4394 link
= XEXP (link
, 1))
4398 /* I2SRC must still be meaningful at this point. Some
4399 splitting operations can invalidate I2SRC, but those
4400 operations do not apply to calls. */
4402 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4406 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4409 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4414 if (undobuf
.other_insn
)
4415 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4417 /* We had one special case above where I2 had more than one set and
4418 we replaced a destination of one of those sets with the destination
4419 of I3. In that case, we have to update LOG_LINKS of insns later
4420 in this basic block. Note that this (expensive) case is rare.
4422 Also, in this case, we must pretend that all REG_NOTEs for I2
4423 actually came from I3, so that REG_UNUSED notes from I2 will be
4424 properly handled. */
4426 if (i3_subst_into_i2
)
4428 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4429 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4430 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4431 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4432 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4433 && ! find_reg_note (i2
, REG_UNUSED
,
4434 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4435 for (temp_insn
= NEXT_INSN (i2
);
4437 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4438 || BB_HEAD (this_basic_block
) != temp_insn
);
4439 temp_insn
= NEXT_INSN (temp_insn
))
4440 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4441 FOR_EACH_LOG_LINK (link
, temp_insn
)
4442 if (link
->insn
== i2
)
4448 while (XEXP (link
, 1))
4449 link
= XEXP (link
, 1);
4450 XEXP (link
, 1) = i2notes
;
4457 LOG_LINKS (i3
) = NULL
;
4459 LOG_LINKS (i2
) = NULL
;
4464 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4465 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4467 INSN_CODE (i2
) = i2_code_number
;
4468 PATTERN (i2
) = newi2pat
;
4472 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4473 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4475 SET_INSN_DELETED (i2
);
4480 LOG_LINKS (i1
) = NULL
;
4482 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4483 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4485 SET_INSN_DELETED (i1
);
4490 LOG_LINKS (i0
) = NULL
;
4492 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4493 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4495 SET_INSN_DELETED (i0
);
4498 /* Get death notes for everything that is now used in either I3 or
4499 I2 and used to die in a previous insn. If we built two new
4500 patterns, move from I1 to I2 then I2 to I3 so that we get the
4501 proper movement on registers that I2 modifies. */
4504 from_luid
= DF_INSN_LUID (i0
);
4506 from_luid
= DF_INSN_LUID (i1
);
4508 from_luid
= DF_INSN_LUID (i2
);
4510 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4511 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4513 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4515 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4516 elim_i2
, elim_i1
, elim_i0
);
4518 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4519 elim_i2
, elim_i1
, elim_i0
);
4521 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4522 elim_i2
, local_elim_i1
, local_elim_i0
);
4524 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4525 elim_i2
, elim_i1
, local_elim_i0
);
4527 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4528 elim_i2
, elim_i1
, elim_i0
);
4530 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4531 know these are REG_UNUSED and want them to go to the desired insn,
4532 so we always pass it as i3. */
4534 if (newi2pat
&& new_i2_notes
)
4535 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4539 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4542 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4543 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4544 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4545 in that case, it might delete I2. Similarly for I2 and I1.
4546 Show an additional death due to the REG_DEAD note we make here. If
4547 we discard it in distribute_notes, we will decrement it again. */
4551 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4552 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4553 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4556 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4557 elim_i2
, elim_i1
, elim_i0
);
4560 if (i2dest_in_i2src
)
4562 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4563 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4564 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4565 NULL_RTX
, NULL_RTX
);
4567 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4568 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4571 if (i1dest_in_i1src
)
4573 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4574 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4575 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4576 NULL_RTX
, NULL_RTX
);
4578 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4579 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4582 if (i0dest_in_i0src
)
4584 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4585 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4586 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4587 NULL_RTX
, NULL_RTX
);
4589 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4590 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4593 distribute_links (i3links
);
4594 distribute_links (i2links
);
4595 distribute_links (i1links
);
4596 distribute_links (i0links
);
4600 struct insn_link
*link
;
4601 rtx_insn
*i2_insn
= 0;
4602 rtx i2_val
= 0, set
;
4604 /* The insn that used to set this register doesn't exist, and
4605 this life of the register may not exist either. See if one of
4606 I3's links points to an insn that sets I2DEST. If it does,
4607 that is now the last known value for I2DEST. If we don't update
4608 this and I2 set the register to a value that depended on its old
4609 contents, we will get confused. If this insn is used, thing
4610 will be set correctly in combine_instructions. */
4611 FOR_EACH_LOG_LINK (link
, i3
)
4612 if ((set
= single_set (link
->insn
)) != 0
4613 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4614 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4616 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4618 /* If the reg formerly set in I2 died only once and that was in I3,
4619 zero its use count so it won't make `reload' do any work. */
4621 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4622 && ! i2dest_in_i2src
4623 && REGNO (i2dest
) < reg_n_sets_max
)
4624 INC_REG_N_SETS (REGNO (i2dest
), -1);
4627 if (i1
&& REG_P (i1dest
))
4629 struct insn_link
*link
;
4630 rtx_insn
*i1_insn
= 0;
4631 rtx i1_val
= 0, set
;
4633 FOR_EACH_LOG_LINK (link
, i3
)
4634 if ((set
= single_set (link
->insn
)) != 0
4635 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4636 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4638 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4641 && ! i1dest_in_i1src
4642 && REGNO (i1dest
) < reg_n_sets_max
)
4643 INC_REG_N_SETS (REGNO (i1dest
), -1);
4646 if (i0
&& REG_P (i0dest
))
4648 struct insn_link
*link
;
4649 rtx_insn
*i0_insn
= 0;
4650 rtx i0_val
= 0, set
;
4652 FOR_EACH_LOG_LINK (link
, i3
)
4653 if ((set
= single_set (link
->insn
)) != 0
4654 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4655 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4657 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4660 && ! i0dest_in_i0src
4661 && REGNO (i0dest
) < reg_n_sets_max
)
4662 INC_REG_N_SETS (REGNO (i0dest
), -1);
4665 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4666 been made to this insn. The order is important, because newi2pat
4667 can affect nonzero_bits of newpat. */
4669 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4670 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4673 if (undobuf
.other_insn
!= NULL_RTX
)
4677 fprintf (dump_file
, "modifying other_insn ");
4678 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4680 df_insn_rescan (undobuf
.other_insn
);
4683 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4687 fprintf (dump_file
, "modifying insn i0 ");
4688 dump_insn_slim (dump_file
, i0
);
4690 df_insn_rescan (i0
);
4693 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4697 fprintf (dump_file
, "modifying insn i1 ");
4698 dump_insn_slim (dump_file
, i1
);
4700 df_insn_rescan (i1
);
4703 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4707 fprintf (dump_file
, "modifying insn i2 ");
4708 dump_insn_slim (dump_file
, i2
);
4710 df_insn_rescan (i2
);
4713 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4717 fprintf (dump_file
, "modifying insn i3 ");
4718 dump_insn_slim (dump_file
, i3
);
4720 df_insn_rescan (i3
);
4723 /* Set new_direct_jump_p if a new return or simple jump instruction
4724 has been created. Adjust the CFG accordingly. */
4725 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4727 *new_direct_jump_p
= 1;
4728 mark_jump_label (PATTERN (i3
), i3
, 0);
4729 update_cfg_for_uncondjump (i3
);
4732 if (undobuf
.other_insn
!= NULL_RTX
4733 && (returnjump_p (undobuf
.other_insn
)
4734 || any_uncondjump_p (undobuf
.other_insn
)))
4736 *new_direct_jump_p
= 1;
4737 update_cfg_for_uncondjump (undobuf
.other_insn
);
4740 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4741 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4743 basic_block bb
= BLOCK_FOR_INSN (i3
);
4745 remove_edge (split_block (bb
, i3
));
4746 emit_barrier_after_bb (bb
);
4747 *new_direct_jump_p
= 1;
4750 if (undobuf
.other_insn
4751 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4752 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4754 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4756 remove_edge (split_block (bb
, undobuf
.other_insn
));
4757 emit_barrier_after_bb (bb
);
4758 *new_direct_jump_p
= 1;
4761 /* A noop might also need cleaning up of CFG, if it comes from the
4762 simplification of a jump. */
4764 && GET_CODE (newpat
) == SET
4765 && SET_SRC (newpat
) == pc_rtx
4766 && SET_DEST (newpat
) == pc_rtx
)
4768 *new_direct_jump_p
= 1;
4769 update_cfg_for_uncondjump (i3
);
4772 if (undobuf
.other_insn
!= NULL_RTX
4773 && JUMP_P (undobuf
.other_insn
)
4774 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4775 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4776 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4778 *new_direct_jump_p
= 1;
4779 update_cfg_for_uncondjump (undobuf
.other_insn
);
4782 combine_successes
++;
4785 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4786 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4787 ret
= added_links_insn
;
4788 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4789 ret
= added_notes_insn
;
4794 /* Get a marker for undoing to the current state. */
4797 get_undo_marker (void)
4799 return undobuf
.undos
;
4802 /* Undo the modifications up to the marker. */
4805 undo_to_marker (void *marker
)
4807 struct undo
*undo
, *next
;
4809 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4817 *undo
->where
.r
= undo
->old_contents
.r
;
4820 *undo
->where
.i
= undo
->old_contents
.i
;
4823 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4826 *undo
->where
.l
= undo
->old_contents
.l
;
4832 undo
->next
= undobuf
.frees
;
4833 undobuf
.frees
= undo
;
4836 undobuf
.undos
= (struct undo
*) marker
;
4839 /* Undo all the modifications recorded in undobuf. */
4847 /* We've committed to accepting the changes we made. Move all
4848 of the undos to the free list. */
4853 struct undo
*undo
, *next
;
4855 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4858 undo
->next
= undobuf
.frees
;
4859 undobuf
.frees
= undo
;
4864 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4865 where we have an arithmetic expression and return that point. LOC will
4868 try_combine will call this function to see if an insn can be split into
4872 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4875 enum rtx_code code
= GET_CODE (x
);
4877 unsigned HOST_WIDE_INT len
= 0;
4878 HOST_WIDE_INT pos
= 0;
4880 rtx inner
= NULL_RTX
;
4881 scalar_int_mode mode
, inner_mode
;
4883 /* First special-case some codes. */
4887 #ifdef INSN_SCHEDULING
4888 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4890 if (MEM_P (SUBREG_REG (x
)))
4893 return find_split_point (&SUBREG_REG (x
), insn
, false);
4896 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4897 using LO_SUM and HIGH. */
4898 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4899 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4901 machine_mode address_mode
= get_address_mode (x
);
4904 gen_rtx_LO_SUM (address_mode
,
4905 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4907 return &XEXP (XEXP (x
, 0), 0);
4910 /* If we have a PLUS whose second operand is a constant and the
4911 address is not valid, perhaps will can split it up using
4912 the machine-specific way to split large constants. We use
4913 the first pseudo-reg (one of the virtual regs) as a placeholder;
4914 it will not remain in the result. */
4915 if (GET_CODE (XEXP (x
, 0)) == PLUS
4916 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4917 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4918 MEM_ADDR_SPACE (x
)))
4920 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4921 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4924 /* This should have produced two insns, each of which sets our
4925 placeholder. If the source of the second is a valid address,
4926 we can make put both sources together and make a split point
4930 && NEXT_INSN (seq
) != NULL_RTX
4931 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4932 && NONJUMP_INSN_P (seq
)
4933 && GET_CODE (PATTERN (seq
)) == SET
4934 && SET_DEST (PATTERN (seq
)) == reg
4935 && ! reg_mentioned_p (reg
,
4936 SET_SRC (PATTERN (seq
)))
4937 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4938 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4939 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4940 && memory_address_addr_space_p
4941 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4942 MEM_ADDR_SPACE (x
)))
4944 rtx src1
= SET_SRC (PATTERN (seq
));
4945 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4947 /* Replace the placeholder in SRC2 with SRC1. If we can
4948 find where in SRC2 it was placed, that can become our
4949 split point and we can replace this address with SRC2.
4950 Just try two obvious places. */
4952 src2
= replace_rtx (src2
, reg
, src1
);
4954 if (XEXP (src2
, 0) == src1
)
4955 split
= &XEXP (src2
, 0);
4956 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4957 && XEXP (XEXP (src2
, 0), 0) == src1
)
4958 split
= &XEXP (XEXP (src2
, 0), 0);
4962 SUBST (XEXP (x
, 0), src2
);
4967 /* If that didn't work, perhaps the first operand is complex and
4968 needs to be computed separately, so make a split point there.
4969 This will occur on machines that just support REG + CONST
4970 and have a constant moved through some previous computation. */
4972 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4973 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4974 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4975 return &XEXP (XEXP (x
, 0), 0);
4978 /* If we have a PLUS whose first operand is complex, try computing it
4979 separately by making a split there. */
4980 if (GET_CODE (XEXP (x
, 0)) == PLUS
4981 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4983 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4984 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4985 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4986 return &XEXP (XEXP (x
, 0), 0);
4990 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4991 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4992 we need to put the operand into a register. So split at that
4995 if (SET_DEST (x
) == cc0_rtx
4996 && GET_CODE (SET_SRC (x
)) != COMPARE
4997 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4998 && !OBJECT_P (SET_SRC (x
))
4999 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
5000 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
5001 return &SET_SRC (x
);
5003 /* See if we can split SET_SRC as it stands. */
5004 split
= find_split_point (&SET_SRC (x
), insn
, true);
5005 if (split
&& split
!= &SET_SRC (x
))
5008 /* See if we can split SET_DEST as it stands. */
5009 split
= find_split_point (&SET_DEST (x
), insn
, false);
5010 if (split
&& split
!= &SET_DEST (x
))
5013 /* See if this is a bitfield assignment with everything constant. If
5014 so, this is an IOR of an AND, so split it into that. */
5015 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5016 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5018 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5019 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5020 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5021 && CONST_INT_P (SET_SRC (x
))
5022 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5023 + INTVAL (XEXP (SET_DEST (x
), 2)))
5024 <= GET_MODE_PRECISION (inner_mode
))
5025 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5027 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5028 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5029 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
5030 rtx dest
= XEXP (SET_DEST (x
), 0);
5031 unsigned HOST_WIDE_INT mask
5032 = (HOST_WIDE_INT_1U
<< len
) - 1;
5035 if (BITS_BIG_ENDIAN
)
5036 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5038 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5041 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5044 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5046 simplify_gen_binary (IOR
, inner_mode
,
5047 simplify_gen_binary (AND
, inner_mode
,
5052 SUBST (SET_DEST (x
), dest
);
5054 split
= find_split_point (&SET_SRC (x
), insn
, true);
5055 if (split
&& split
!= &SET_SRC (x
))
5059 /* Otherwise, see if this is an operation that we can split into two.
5060 If so, try to split that. */
5061 code
= GET_CODE (SET_SRC (x
));
5066 /* If we are AND'ing with a large constant that is only a single
5067 bit and the result is only being used in a context where we
5068 need to know if it is zero or nonzero, replace it with a bit
5069 extraction. This will avoid the large constant, which might
5070 have taken more than one insn to make. If the constant were
5071 not a valid argument to the AND but took only one insn to make,
5072 this is no worse, but if it took more than one insn, it will
5075 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5076 && REG_P (XEXP (SET_SRC (x
), 0))
5077 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5078 && REG_P (SET_DEST (x
))
5079 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5080 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5081 && XEXP (*split
, 0) == SET_DEST (x
)
5082 && XEXP (*split
, 1) == const0_rtx
)
5084 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5085 XEXP (SET_SRC (x
), 0),
5086 pos
, NULL_RTX
, 1, 1, 0, 0);
5087 if (extraction
!= 0)
5089 SUBST (SET_SRC (x
), extraction
);
5090 return find_split_point (loc
, insn
, false);
5096 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5097 is known to be on, this can be converted into a NEG of a shift. */
5098 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5099 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5100 && ((pos
= exact_log2 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5101 GET_MODE (XEXP (SET_SRC (x
),
5104 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5105 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5108 gen_rtx_LSHIFTRT (mode
,
5109 XEXP (SET_SRC (x
), 0),
5112 split
= find_split_point (&SET_SRC (x
), insn
, true);
5113 if (split
&& split
!= &SET_SRC (x
))
5119 inner
= XEXP (SET_SRC (x
), 0);
5121 /* We can't optimize if either mode is a partial integer
5122 mode as we don't know how many bits are significant
5124 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5125 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5129 len
= GET_MODE_PRECISION (inner_mode
);
5135 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5137 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5138 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5140 inner
= XEXP (SET_SRC (x
), 0);
5141 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5142 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5144 if (BITS_BIG_ENDIAN
)
5145 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5146 unsignedp
= (code
== ZERO_EXTRACT
);
5155 && known_subrange_p (pos
, len
,
5156 0, GET_MODE_PRECISION (GET_MODE (inner
)))
5157 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5159 /* For unsigned, we have a choice of a shift followed by an
5160 AND or two shifts. Use two shifts for field sizes where the
5161 constant might be too large. We assume here that we can
5162 always at least get 8-bit constants in an AND insn, which is
5163 true for every current RISC. */
5165 if (unsignedp
&& len
<= 8)
5167 unsigned HOST_WIDE_INT mask
5168 = (HOST_WIDE_INT_1U
<< len
) - 1;
5169 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5173 (mode
, gen_lowpart (mode
, inner
), pos_rtx
),
5174 gen_int_mode (mask
, mode
)));
5176 split
= find_split_point (&SET_SRC (x
), insn
, true);
5177 if (split
&& split
!= &SET_SRC (x
))
5182 int left_bits
= GET_MODE_PRECISION (mode
) - len
- pos
;
5183 int right_bits
= GET_MODE_PRECISION (mode
) - len
;
5186 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5187 gen_rtx_ASHIFT (mode
,
5188 gen_lowpart (mode
, inner
),
5189 gen_int_shift_amount (mode
, left_bits
)),
5190 gen_int_shift_amount (mode
, right_bits
)));
5192 split
= find_split_point (&SET_SRC (x
), insn
, true);
5193 if (split
&& split
!= &SET_SRC (x
))
5198 /* See if this is a simple operation with a constant as the second
5199 operand. It might be that this constant is out of range and hence
5200 could be used as a split point. */
5201 if (BINARY_P (SET_SRC (x
))
5202 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5203 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5204 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5205 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5206 return &XEXP (SET_SRC (x
), 1);
5208 /* Finally, see if this is a simple operation with its first operand
5209 not in a register. The operation might require this operand in a
5210 register, so return it as a split point. We can always do this
5211 because if the first operand were another operation, we would have
5212 already found it as a split point. */
5213 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5214 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5215 return &XEXP (SET_SRC (x
), 0);
5221 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5222 it is better to write this as (not (ior A B)) so we can split it.
5223 Similarly for IOR. */
5224 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5227 gen_rtx_NOT (GET_MODE (x
),
5228 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5230 XEXP (XEXP (x
, 0), 0),
5231 XEXP (XEXP (x
, 1), 0))));
5232 return find_split_point (loc
, insn
, set_src
);
5235 /* Many RISC machines have a large set of logical insns. If the
5236 second operand is a NOT, put it first so we will try to split the
5237 other operand first. */
5238 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5240 rtx tem
= XEXP (x
, 0);
5241 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5242 SUBST (XEXP (x
, 1), tem
);
5248 /* Canonicalization can produce (minus A (mult B C)), where C is a
5249 constant. It may be better to try splitting (plus (mult B -C) A)
5250 instead if this isn't a multiply by a power of two. */
5251 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5252 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5253 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5255 machine_mode mode
= GET_MODE (x
);
5256 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5257 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5258 SUBST (*loc
, gen_rtx_PLUS (mode
,
5260 XEXP (XEXP (x
, 1), 0),
5261 gen_int_mode (other_int
,
5264 return find_split_point (loc
, insn
, set_src
);
5267 /* Split at a multiply-accumulate instruction. However if this is
5268 the SET_SRC, we likely do not have such an instruction and it's
5269 worthless to try this split. */
5271 && (GET_CODE (XEXP (x
, 0)) == MULT
5272 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5273 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5280 /* Otherwise, select our actions depending on our rtx class. */
5281 switch (GET_RTX_CLASS (code
))
5283 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5285 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5290 case RTX_COMM_ARITH
:
5292 case RTX_COMM_COMPARE
:
5293 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5298 /* Some machines have (and (shift ...) ...) insns. If X is not
5299 an AND, but XEXP (X, 0) is, use it as our split point. */
5300 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5301 return &XEXP (x
, 0);
5303 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5309 /* Otherwise, we don't have a split point. */
5314 /* Throughout X, replace FROM with TO, and return the result.
5315 The result is TO if X is FROM;
5316 otherwise the result is X, but its contents may have been modified.
5317 If they were modified, a record was made in undobuf so that
5318 undo_all will (among other things) return X to its original state.
5320 If the number of changes necessary is too much to record to undo,
5321 the excess changes are not made, so the result is invalid.
5322 The changes already made can still be undone.
5323 undobuf.num_undo is incremented for such changes, so by testing that
5324 the caller can tell whether the result is valid.
5326 `n_occurrences' is incremented each time FROM is replaced.
5328 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5330 IN_COND is nonzero if we are at the top level of a condition.
5332 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5333 by copying if `n_occurrences' is nonzero. */
5336 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5338 enum rtx_code code
= GET_CODE (x
);
5339 machine_mode op0_mode
= VOIDmode
;
5344 /* Two expressions are equal if they are identical copies of a shared
5345 RTX or if they are both registers with the same register number
5348 #define COMBINE_RTX_EQUAL_P(X,Y) \
5350 || (REG_P (X) && REG_P (Y) \
5351 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5353 /* Do not substitute into clobbers of regs -- this will never result in
5355 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5358 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5361 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5364 /* If X and FROM are the same register but different modes, they
5365 will not have been seen as equal above. However, the log links code
5366 will make a LOG_LINKS entry for that case. If we do nothing, we
5367 will try to rerecognize our original insn and, when it succeeds,
5368 we will delete the feeding insn, which is incorrect.
5370 So force this insn not to match in this (rare) case. */
5371 if (! in_dest
&& code
== REG
&& REG_P (from
)
5372 && reg_overlap_mentioned_p (x
, from
))
5373 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5375 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5376 of which may contain things that can be combined. */
5377 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5380 /* It is possible to have a subexpression appear twice in the insn.
5381 Suppose that FROM is a register that appears within TO.
5382 Then, after that subexpression has been scanned once by `subst',
5383 the second time it is scanned, TO may be found. If we were
5384 to scan TO here, we would find FROM within it and create a
5385 self-referent rtl structure which is completely wrong. */
5386 if (COMBINE_RTX_EQUAL_P (x
, to
))
5389 /* Parallel asm_operands need special attention because all of the
5390 inputs are shared across the arms. Furthermore, unsharing the
5391 rtl results in recognition failures. Failure to handle this case
5392 specially can result in circular rtl.
5394 Solve this by doing a normal pass across the first entry of the
5395 parallel, and only processing the SET_DESTs of the subsequent
5398 if (code
== PARALLEL
5399 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5400 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5402 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5404 /* If this substitution failed, this whole thing fails. */
5405 if (GET_CODE (new_rtx
) == CLOBBER
5406 && XEXP (new_rtx
, 0) == const0_rtx
)
5409 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5411 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5413 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5416 && GET_CODE (dest
) != CC0
5417 && GET_CODE (dest
) != PC
)
5419 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5421 /* If this substitution failed, this whole thing fails. */
5422 if (GET_CODE (new_rtx
) == CLOBBER
5423 && XEXP (new_rtx
, 0) == const0_rtx
)
5426 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5432 len
= GET_RTX_LENGTH (code
);
5433 fmt
= GET_RTX_FORMAT (code
);
5435 /* We don't need to process a SET_DEST that is a register, CC0,
5436 or PC, so set up to skip this common case. All other cases
5437 where we want to suppress replacing something inside a
5438 SET_SRC are handled via the IN_DEST operand. */
5440 && (REG_P (SET_DEST (x
))
5441 || GET_CODE (SET_DEST (x
)) == CC0
5442 || GET_CODE (SET_DEST (x
)) == PC
))
5445 /* Trying to simplify the operands of a widening MULT is not likely
5446 to create RTL matching a machine insn. */
5448 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5449 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5450 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5451 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5452 && REG_P (XEXP (XEXP (x
, 0), 0))
5453 && REG_P (XEXP (XEXP (x
, 1), 0))
5458 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5461 op0_mode
= GET_MODE (XEXP (x
, 0));
5463 for (i
= 0; i
< len
; i
++)
5468 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5470 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5472 new_rtx
= (unique_copy
&& n_occurrences
5473 ? copy_rtx (to
) : to
);
5478 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5481 /* If this substitution failed, this whole thing
5483 if (GET_CODE (new_rtx
) == CLOBBER
5484 && XEXP (new_rtx
, 0) == const0_rtx
)
5488 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5491 else if (fmt
[i
] == 'e')
5493 /* If this is a register being set, ignore it. */
5494 new_rtx
= XEXP (x
, i
);
5497 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5499 || code
== STRICT_LOW_PART
))
5502 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5504 /* In general, don't install a subreg involving two
5505 modes not tieable. It can worsen register
5506 allocation, and can even make invalid reload
5507 insns, since the reg inside may need to be copied
5508 from in the outside mode, and that may be invalid
5509 if it is an fp reg copied in integer mode.
5511 We allow two exceptions to this: It is valid if
5512 it is inside another SUBREG and the mode of that
5513 SUBREG and the mode of the inside of TO is
5514 tieable and it is valid if X is a SET that copies
5517 if (GET_CODE (to
) == SUBREG
5518 && !targetm
.modes_tieable_p (GET_MODE (to
),
5519 GET_MODE (SUBREG_REG (to
)))
5520 && ! (code
== SUBREG
5521 && (targetm
.modes_tieable_p
5522 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
)))))
5526 && XEXP (x
, 0) == cc0_rtx
))))
5527 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5531 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5532 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5535 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5537 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5541 /* If we are in a SET_DEST, suppress most cases unless we
5542 have gone inside a MEM, in which case we want to
5543 simplify the address. We assume here that things that
5544 are actually part of the destination have their inner
5545 parts in the first expression. This is true for SUBREG,
5546 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5547 things aside from REG and MEM that should appear in a
5549 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5551 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5552 || code
== ZERO_EXTRACT
))
5555 code
== IF_THEN_ELSE
&& i
== 0,
5558 /* If we found that we will have to reject this combination,
5559 indicate that by returning the CLOBBER ourselves, rather than
5560 an expression containing it. This will speed things up as
5561 well as prevent accidents where two CLOBBERs are considered
5562 to be equal, thus producing an incorrect simplification. */
5564 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5567 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5569 machine_mode mode
= GET_MODE (x
);
5571 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5572 GET_MODE (SUBREG_REG (x
)),
5575 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5577 else if (CONST_SCALAR_INT_P (new_rtx
)
5578 && (GET_CODE (x
) == ZERO_EXTEND
5579 || GET_CODE (x
) == FLOAT
5580 || GET_CODE (x
) == UNSIGNED_FLOAT
))
5582 x
= simplify_unary_operation (GET_CODE (x
), GET_MODE (x
),
5584 GET_MODE (XEXP (x
, 0)));
5586 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5589 SUBST (XEXP (x
, i
), new_rtx
);
5594 /* Check if we are loading something from the constant pool via float
5595 extension; in this case we would undo compress_float_constant
5596 optimization and degenerate constant load to an immediate value. */
5597 if (GET_CODE (x
) == FLOAT_EXTEND
5598 && MEM_P (XEXP (x
, 0))
5599 && MEM_READONLY_P (XEXP (x
, 0)))
5601 rtx tmp
= avoid_constant_pool_reference (x
);
5606 /* Try to simplify X. If the simplification changed the code, it is likely
5607 that further simplification will help, so loop, but limit the number
5608 of repetitions that will be performed. */
5610 for (i
= 0; i
< 4; i
++)
5612 /* If X is sufficiently simple, don't bother trying to do anything
5614 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5615 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5617 if (GET_CODE (x
) == code
)
5620 code
= GET_CODE (x
);
5622 /* We no longer know the original mode of operand 0 since we
5623 have changed the form of X) */
5624 op0_mode
= VOIDmode
;
5630 /* If X is a commutative operation whose operands are not in the canonical
5631 order, use substitutions to swap them. */
5634 maybe_swap_commutative_operands (rtx x
)
5636 if (COMMUTATIVE_ARITH_P (x
)
5637 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5639 rtx temp
= XEXP (x
, 0);
5640 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5641 SUBST (XEXP (x
, 1), temp
);
5645 /* Simplify X, a piece of RTL. We just operate on the expression at the
5646 outer level; call `subst' to simplify recursively. Return the new
5649 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5650 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5654 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5657 enum rtx_code code
= GET_CODE (x
);
5658 machine_mode mode
= GET_MODE (x
);
5659 scalar_int_mode int_mode
;
5663 /* If this is a commutative operation, put a constant last and a complex
5664 expression first. We don't need to do this for comparisons here. */
5665 maybe_swap_commutative_operands (x
);
5667 /* Try to fold this expression in case we have constants that weren't
5670 switch (GET_RTX_CLASS (code
))
5673 if (op0_mode
== VOIDmode
)
5674 op0_mode
= GET_MODE (XEXP (x
, 0));
5675 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5678 case RTX_COMM_COMPARE
:
5680 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5681 if (cmp_mode
== VOIDmode
)
5683 cmp_mode
= GET_MODE (XEXP (x
, 1));
5684 if (cmp_mode
== VOIDmode
)
5685 cmp_mode
= op0_mode
;
5687 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5688 XEXP (x
, 0), XEXP (x
, 1));
5691 case RTX_COMM_ARITH
:
5693 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5695 case RTX_BITFIELD_OPS
:
5697 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5698 XEXP (x
, 1), XEXP (x
, 2));
5707 code
= GET_CODE (temp
);
5708 op0_mode
= VOIDmode
;
5709 mode
= GET_MODE (temp
);
5712 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5713 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5714 things. Check for cases where both arms are testing the same
5717 Don't do anything if all operands are very simple. */
5720 && ((!OBJECT_P (XEXP (x
, 0))
5721 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5722 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5723 || (!OBJECT_P (XEXP (x
, 1))
5724 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5725 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5727 && (!OBJECT_P (XEXP (x
, 0))
5728 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5729 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5731 rtx cond
, true_rtx
, false_rtx
;
5733 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5735 /* If everything is a comparison, what we have is highly unlikely
5736 to be simpler, so don't use it. */
5737 && ! (COMPARISON_P (x
)
5738 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
)))
5739 /* Similarly, if we end up with one of the expressions the same
5740 as the original, it is certainly not simpler. */
5741 && ! rtx_equal_p (x
, true_rtx
)
5742 && ! rtx_equal_p (x
, false_rtx
))
5744 rtx cop1
= const0_rtx
;
5745 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5747 if (cond_code
== NE
&& COMPARISON_P (cond
))
5750 /* Simplify the alternative arms; this may collapse the true and
5751 false arms to store-flag values. Be careful to use copy_rtx
5752 here since true_rtx or false_rtx might share RTL with x as a
5753 result of the if_then_else_cond call above. */
5754 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5755 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5757 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5758 is unlikely to be simpler. */
5759 if (general_operand (true_rtx
, VOIDmode
)
5760 && general_operand (false_rtx
, VOIDmode
))
5762 enum rtx_code reversed
;
5764 /* Restarting if we generate a store-flag expression will cause
5765 us to loop. Just drop through in this case. */
5767 /* If the result values are STORE_FLAG_VALUE and zero, we can
5768 just make the comparison operation. */
5769 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5770 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5772 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5773 && ((reversed
= reversed_comparison_code_parts
5774 (cond_code
, cond
, cop1
, NULL
))
5776 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5779 /* Likewise, we can make the negate of a comparison operation
5780 if the result values are - STORE_FLAG_VALUE and zero. */
5781 else if (CONST_INT_P (true_rtx
)
5782 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5783 && false_rtx
== const0_rtx
)
5784 x
= simplify_gen_unary (NEG
, mode
,
5785 simplify_gen_relational (cond_code
,
5789 else if (CONST_INT_P (false_rtx
)
5790 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5791 && true_rtx
== const0_rtx
5792 && ((reversed
= reversed_comparison_code_parts
5793 (cond_code
, cond
, cop1
, NULL
))
5795 x
= simplify_gen_unary (NEG
, mode
,
5796 simplify_gen_relational (reversed
,
5801 return gen_rtx_IF_THEN_ELSE (mode
,
5802 simplify_gen_relational (cond_code
,
5807 true_rtx
, false_rtx
);
5809 code
= GET_CODE (x
);
5810 op0_mode
= VOIDmode
;
5815 /* First see if we can apply the inverse distributive law. */
5816 if (code
== PLUS
|| code
== MINUS
5817 || code
== AND
|| code
== IOR
|| code
== XOR
)
5819 x
= apply_distributive_law (x
);
5820 code
= GET_CODE (x
);
5821 op0_mode
= VOIDmode
;
5824 /* If CODE is an associative operation not otherwise handled, see if we
5825 can associate some operands. This can win if they are constants or
5826 if they are logically related (i.e. (a & b) & a). */
5827 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5828 || code
== AND
|| code
== IOR
|| code
== XOR
5829 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5830 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5831 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5833 if (GET_CODE (XEXP (x
, 0)) == code
)
5835 rtx other
= XEXP (XEXP (x
, 0), 0);
5836 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5837 rtx inner_op1
= XEXP (x
, 1);
5840 /* Make sure we pass the constant operand if any as the second
5841 one if this is a commutative operation. */
5842 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5843 std::swap (inner_op0
, inner_op1
);
5844 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5845 : code
== DIV
? MULT
5847 mode
, inner_op0
, inner_op1
);
5849 /* For commutative operations, try the other pair if that one
5851 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5853 other
= XEXP (XEXP (x
, 0), 1);
5854 inner
= simplify_binary_operation (code
, mode
,
5855 XEXP (XEXP (x
, 0), 0),
5860 return simplify_gen_binary (code
, mode
, other
, inner
);
5864 /* A little bit of algebraic simplification here. */
5868 /* Ensure that our address has any ASHIFTs converted to MULT in case
5869 address-recognizing predicates are called later. */
5870 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5871 SUBST (XEXP (x
, 0), temp
);
5875 if (op0_mode
== VOIDmode
)
5876 op0_mode
= GET_MODE (SUBREG_REG (x
));
5878 /* See if this can be moved to simplify_subreg. */
5879 if (CONSTANT_P (SUBREG_REG (x
))
5880 && known_eq (subreg_lowpart_offset (mode
, op0_mode
), SUBREG_BYTE (x
))
5881 /* Don't call gen_lowpart if the inner mode
5882 is VOIDmode and we cannot simplify it, as SUBREG without
5883 inner mode is invalid. */
5884 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5885 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5886 return gen_lowpart (mode
, SUBREG_REG (x
));
5888 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5892 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5897 /* If op is known to have all lower bits zero, the result is zero. */
5898 scalar_int_mode int_mode
, int_op0_mode
;
5900 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5901 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5902 && (GET_MODE_PRECISION (int_mode
)
5903 < GET_MODE_PRECISION (int_op0_mode
))
5904 && known_eq (subreg_lowpart_offset (int_mode
, int_op0_mode
),
5906 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5907 && (nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5908 & GET_MODE_MASK (int_mode
)) == 0)
5909 return CONST0_RTX (int_mode
);
5912 /* Don't change the mode of the MEM if that would change the meaning
5914 if (MEM_P (SUBREG_REG (x
))
5915 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5916 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5917 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5918 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5920 /* Note that we cannot do any narrowing for non-constants since
5921 we might have been counting on using the fact that some bits were
5922 zero. We now do this in the SET. */
5927 temp
= expand_compound_operation (XEXP (x
, 0));
5929 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5930 replaced by (lshiftrt X C). This will convert
5931 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5933 if (GET_CODE (temp
) == ASHIFTRT
5934 && CONST_INT_P (XEXP (temp
, 1))
5935 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
5936 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5937 INTVAL (XEXP (temp
, 1)));
5939 /* If X has only a single bit that might be nonzero, say, bit I, convert
5940 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5941 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5942 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5943 or a SUBREG of one since we'd be making the expression more
5944 complex if it was just a register. */
5947 && ! (GET_CODE (temp
) == SUBREG
5948 && REG_P (SUBREG_REG (temp
)))
5949 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5950 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
5952 rtx temp1
= simplify_shift_const
5953 (NULL_RTX
, ASHIFTRT
, int_mode
,
5954 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
5955 GET_MODE_PRECISION (int_mode
) - 1 - i
),
5956 GET_MODE_PRECISION (int_mode
) - 1 - i
);
5958 /* If all we did was surround TEMP with the two shifts, we
5959 haven't improved anything, so don't use it. Otherwise,
5960 we are better off with TEMP1. */
5961 if (GET_CODE (temp1
) != ASHIFTRT
5962 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5963 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5969 /* We can't handle truncation to a partial integer mode here
5970 because we don't know the real bitsize of the partial
5972 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5975 if (HWI_COMPUTABLE_MODE_P (mode
))
5977 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5978 GET_MODE_MASK (mode
), 0));
5980 /* We can truncate a constant value and return it. */
5983 if (poly_int_rtx_p (XEXP (x
, 0), &c
))
5984 return gen_int_mode (c
, mode
);
5987 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5988 whose value is a comparison can be replaced with a subreg if
5989 STORE_FLAG_VALUE permits. */
5990 if (HWI_COMPUTABLE_MODE_P (mode
)
5991 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5992 && (temp
= get_last_value (XEXP (x
, 0)))
5993 && COMPARISON_P (temp
))
5994 return gen_lowpart (mode
, XEXP (x
, 0));
5998 /* (const (const X)) can become (const X). Do it this way rather than
5999 returning the inner CONST since CONST can be shared with a
6001 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6002 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6006 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6007 can add in an offset. find_split_point will split this address up
6008 again if it doesn't match. */
6009 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6010 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6015 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6016 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6017 bit-field and can be replaced by either a sign_extend or a
6018 sign_extract. The `and' may be a zero_extend and the two
6019 <c>, -<c> constants may be reversed. */
6020 if (GET_CODE (XEXP (x
, 0)) == XOR
6021 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6022 && CONST_INT_P (XEXP (x
, 1))
6023 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6024 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6025 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6026 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6027 && HWI_COMPUTABLE_MODE_P (int_mode
)
6028 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6029 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6030 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6031 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6032 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6033 && known_eq ((GET_MODE_PRECISION
6034 (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))),
6035 (unsigned int) i
+ 1))))
6036 return simplify_shift_const
6037 (NULL_RTX
, ASHIFTRT
, int_mode
,
6038 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6039 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6040 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6041 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6043 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6044 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6045 the bitsize of the mode - 1. This allows simplification of
6046 "a = (b & 8) == 0;" */
6047 if (XEXP (x
, 1) == constm1_rtx
6048 && !REG_P (XEXP (x
, 0))
6049 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6050 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6051 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6052 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6053 return simplify_shift_const
6054 (NULL_RTX
, ASHIFTRT
, int_mode
,
6055 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6056 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6058 GET_MODE_PRECISION (int_mode
) - 1),
6059 GET_MODE_PRECISION (int_mode
) - 1);
6061 /* If we are adding two things that have no bits in common, convert
6062 the addition into an IOR. This will often be further simplified,
6063 for example in cases like ((a & 1) + (a & 2)), which can
6066 if (HWI_COMPUTABLE_MODE_P (mode
)
6067 && (nonzero_bits (XEXP (x
, 0), mode
)
6068 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6070 /* Try to simplify the expression further. */
6071 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6072 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6074 /* If we could, great. If not, do not go ahead with the IOR
6075 replacement, since PLUS appears in many special purpose
6076 address arithmetic instructions. */
6077 if (GET_CODE (temp
) != CLOBBER
6078 && (GET_CODE (temp
) != IOR
6079 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6080 || XEXP (temp
, 1) != XEXP (x
, 1))
6081 && (XEXP (temp
, 0) != XEXP (x
, 1)
6082 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6086 /* Canonicalize x + x into x << 1. */
6087 if (GET_MODE_CLASS (mode
) == MODE_INT
6088 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6089 && !side_effects_p (XEXP (x
, 0)))
6090 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6095 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6096 (and <foo> (const_int pow2-1)) */
6097 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6098 && GET_CODE (XEXP (x
, 1)) == AND
6099 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6100 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6101 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6102 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6103 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6107 /* If we have (mult (plus A B) C), apply the distributive law and then
6108 the inverse distributive law to see if things simplify. This
6109 occurs mostly in addresses, often when unrolling loops. */
6111 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6113 rtx result
= distribute_and_simplify_rtx (x
, 0);
6118 /* Try simplify a*(b/c) as (a*b)/c. */
6119 if (FLOAT_MODE_P (mode
) && flag_associative_math
6120 && GET_CODE (XEXP (x
, 0)) == DIV
)
6122 rtx tem
= simplify_binary_operation (MULT
, mode
,
6123 XEXP (XEXP (x
, 0), 0),
6126 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6131 /* If this is a divide by a power of two, treat it as a shift if
6132 its first operand is a shift. */
6133 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6134 && CONST_INT_P (XEXP (x
, 1))
6135 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6136 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6137 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6138 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6139 || GET_CODE (XEXP (x
, 0)) == ROTATE
6140 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6141 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6146 case GT
: case GTU
: case GE
: case GEU
:
6147 case LT
: case LTU
: case LE
: case LEU
:
6148 case UNEQ
: case LTGT
:
6149 case UNGT
: case UNGE
:
6150 case UNLT
: case UNLE
:
6151 case UNORDERED
: case ORDERED
:
6152 /* If the first operand is a condition code, we can't do anything
6154 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6155 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6156 && ! CC0_P (XEXP (x
, 0))))
6158 rtx op0
= XEXP (x
, 0);
6159 rtx op1
= XEXP (x
, 1);
6160 enum rtx_code new_code
;
6162 if (GET_CODE (op0
) == COMPARE
)
6163 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6165 /* Simplify our comparison, if possible. */
6166 new_code
= simplify_comparison (code
, &op0
, &op1
);
6168 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6169 if only the low-order bit is possibly nonzero in X (such as when
6170 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6171 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6172 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6175 Remove any ZERO_EXTRACT we made when thinking this was a
6176 comparison. It may now be simpler to use, e.g., an AND. If a
6177 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6178 the call to make_compound_operation in the SET case.
6180 Don't apply these optimizations if the caller would
6181 prefer a comparison rather than a value.
6182 E.g., for the condition in an IF_THEN_ELSE most targets need
6183 an explicit comparison. */
6188 else if (STORE_FLAG_VALUE
== 1
6190 && is_int_mode (mode
, &int_mode
)
6191 && op1
== const0_rtx
6192 && int_mode
== GET_MODE (op0
)
6193 && nonzero_bits (op0
, int_mode
) == 1)
6194 return gen_lowpart (int_mode
,
6195 expand_compound_operation (op0
));
6197 else if (STORE_FLAG_VALUE
== 1
6199 && is_int_mode (mode
, &int_mode
)
6200 && op1
== const0_rtx
6201 && int_mode
== GET_MODE (op0
)
6202 && (num_sign_bit_copies (op0
, int_mode
)
6203 == GET_MODE_PRECISION (int_mode
)))
6205 op0
= expand_compound_operation (op0
);
6206 return simplify_gen_unary (NEG
, int_mode
,
6207 gen_lowpart (int_mode
, op0
),
6211 else if (STORE_FLAG_VALUE
== 1
6213 && is_int_mode (mode
, &int_mode
)
6214 && op1
== const0_rtx
6215 && int_mode
== GET_MODE (op0
)
6216 && nonzero_bits (op0
, int_mode
) == 1)
6218 op0
= expand_compound_operation (op0
);
6219 return simplify_gen_binary (XOR
, int_mode
,
6220 gen_lowpart (int_mode
, op0
),
6224 else if (STORE_FLAG_VALUE
== 1
6226 && is_int_mode (mode
, &int_mode
)
6227 && op1
== const0_rtx
6228 && int_mode
== GET_MODE (op0
)
6229 && (num_sign_bit_copies (op0
, int_mode
)
6230 == GET_MODE_PRECISION (int_mode
)))
6232 op0
= expand_compound_operation (op0
);
6233 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6236 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6241 else if (STORE_FLAG_VALUE
== -1
6243 && is_int_mode (mode
, &int_mode
)
6244 && op1
== const0_rtx
6245 && int_mode
== GET_MODE (op0
)
6246 && (num_sign_bit_copies (op0
, int_mode
)
6247 == GET_MODE_PRECISION (int_mode
)))
6248 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6250 else if (STORE_FLAG_VALUE
== -1
6252 && is_int_mode (mode
, &int_mode
)
6253 && op1
== const0_rtx
6254 && int_mode
== GET_MODE (op0
)
6255 && nonzero_bits (op0
, int_mode
) == 1)
6257 op0
= expand_compound_operation (op0
);
6258 return simplify_gen_unary (NEG
, int_mode
,
6259 gen_lowpart (int_mode
, op0
),
6263 else if (STORE_FLAG_VALUE
== -1
6265 && is_int_mode (mode
, &int_mode
)
6266 && op1
== const0_rtx
6267 && int_mode
== GET_MODE (op0
)
6268 && (num_sign_bit_copies (op0
, int_mode
)
6269 == GET_MODE_PRECISION (int_mode
)))
6271 op0
= expand_compound_operation (op0
);
6272 return simplify_gen_unary (NOT
, int_mode
,
6273 gen_lowpart (int_mode
, op0
),
6277 /* If X is 0/1, (eq X 0) is X-1. */
6278 else if (STORE_FLAG_VALUE
== -1
6280 && is_int_mode (mode
, &int_mode
)
6281 && op1
== const0_rtx
6282 && int_mode
== GET_MODE (op0
)
6283 && nonzero_bits (op0
, int_mode
) == 1)
6285 op0
= expand_compound_operation (op0
);
6286 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6289 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6290 one bit that might be nonzero, we can convert (ne x 0) to
6291 (ashift x c) where C puts the bit in the sign bit. Remove any
6292 AND with STORE_FLAG_VALUE when we are done, since we are only
6293 going to test the sign bit. */
6295 && is_int_mode (mode
, &int_mode
)
6296 && HWI_COMPUTABLE_MODE_P (int_mode
)
6297 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6298 && op1
== const0_rtx
6299 && int_mode
== GET_MODE (op0
)
6300 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6302 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6303 expand_compound_operation (op0
),
6304 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6305 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6311 /* If the code changed, return a whole new comparison.
6312 We also need to avoid using SUBST in cases where
6313 simplify_comparison has widened a comparison with a CONST_INT,
6314 since in that case the wider CONST_INT may fail the sanity
6315 checks in do_SUBST. */
6316 if (new_code
!= code
6317 || (CONST_INT_P (op1
)
6318 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6319 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6320 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6322 /* Otherwise, keep this operation, but maybe change its operands.
6323 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6324 SUBST (XEXP (x
, 0), op0
);
6325 SUBST (XEXP (x
, 1), op1
);
6330 return simplify_if_then_else (x
);
6336 /* If we are processing SET_DEST, we are done. */
6340 return expand_compound_operation (x
);
6343 return simplify_set (x
);
6347 return simplify_logical (x
);
6354 /* If this is a shift by a constant amount, simplify it. */
6355 if (CONST_INT_P (XEXP (x
, 1)))
6356 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6357 INTVAL (XEXP (x
, 1)));
6359 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6361 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6363 << exact_log2 (GET_MODE_UNIT_BITSIZE
6376 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6379 simplify_if_then_else (rtx x
)
6381 machine_mode mode
= GET_MODE (x
);
6382 rtx cond
= XEXP (x
, 0);
6383 rtx true_rtx
= XEXP (x
, 1);
6384 rtx false_rtx
= XEXP (x
, 2);
6385 enum rtx_code true_code
= GET_CODE (cond
);
6386 int comparison_p
= COMPARISON_P (cond
);
6389 enum rtx_code false_code
;
6391 scalar_int_mode int_mode
, inner_mode
;
6393 /* Simplify storing of the truth value. */
6394 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6395 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6396 XEXP (cond
, 0), XEXP (cond
, 1));
6398 /* Also when the truth value has to be reversed. */
6400 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6401 && (reversed
= reversed_comparison (cond
, mode
)))
6404 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6405 in it is being compared against certain values. Get the true and false
6406 comparisons and see if that says anything about the value of each arm. */
6409 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6411 && REG_P (XEXP (cond
, 0)))
6414 rtx from
= XEXP (cond
, 0);
6415 rtx true_val
= XEXP (cond
, 1);
6416 rtx false_val
= true_val
;
6419 /* If FALSE_CODE is EQ, swap the codes and arms. */
6421 if (false_code
== EQ
)
6423 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6424 std::swap (true_rtx
, false_rtx
);
6427 scalar_int_mode from_mode
;
6428 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6430 /* If we are comparing against zero and the expression being
6431 tested has only a single bit that might be nonzero, that is
6432 its value when it is not equal to zero. Similarly if it is
6433 known to be -1 or 0. */
6435 && true_val
== const0_rtx
6436 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6439 false_val
= gen_int_mode (nzb
, from_mode
);
6441 else if (true_code
== EQ
6442 && true_val
== const0_rtx
6443 && (num_sign_bit_copies (from
, from_mode
)
6444 == GET_MODE_PRECISION (from_mode
)))
6447 false_val
= constm1_rtx
;
6451 /* Now simplify an arm if we know the value of the register in the
6452 branch and it is used in the arm. Be careful due to the potential
6453 of locally-shared RTL. */
6455 if (reg_mentioned_p (from
, true_rtx
))
6456 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6458 pc_rtx
, pc_rtx
, 0, 0, 0);
6459 if (reg_mentioned_p (from
, false_rtx
))
6460 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6462 pc_rtx
, pc_rtx
, 0, 0, 0);
6464 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6465 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6467 true_rtx
= XEXP (x
, 1);
6468 false_rtx
= XEXP (x
, 2);
6469 true_code
= GET_CODE (cond
);
6472 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6473 reversed, do so to avoid needing two sets of patterns for
6474 subtract-and-branch insns. Similarly if we have a constant in the true
6475 arm, the false arm is the same as the first operand of the comparison, or
6476 the false arm is more complicated than the true arm. */
6479 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6480 && (true_rtx
== pc_rtx
6481 || (CONSTANT_P (true_rtx
)
6482 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6483 || true_rtx
== const0_rtx
6484 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6485 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6486 && !OBJECT_P (false_rtx
))
6487 || reg_mentioned_p (true_rtx
, false_rtx
)
6488 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6490 true_code
= reversed_comparison_code (cond
, NULL
);
6491 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6492 SUBST (XEXP (x
, 1), false_rtx
);
6493 SUBST (XEXP (x
, 2), true_rtx
);
6495 std::swap (true_rtx
, false_rtx
);
6498 /* It is possible that the conditional has been simplified out. */
6499 true_code
= GET_CODE (cond
);
6500 comparison_p
= COMPARISON_P (cond
);
6503 /* If the two arms are identical, we don't need the comparison. */
6505 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6508 /* Convert a == b ? b : a to "a". */
6509 if (true_code
== EQ
&& ! side_effects_p (cond
)
6510 && !HONOR_NANS (mode
)
6511 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6512 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6514 else if (true_code
== NE
&& ! side_effects_p (cond
)
6515 && !HONOR_NANS (mode
)
6516 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6517 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6520 /* Look for cases where we have (abs x) or (neg (abs X)). */
6522 if (GET_MODE_CLASS (mode
) == MODE_INT
6524 && XEXP (cond
, 1) == const0_rtx
6525 && GET_CODE (false_rtx
) == NEG
6526 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6527 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6528 && ! side_effects_p (true_rtx
))
6533 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6537 simplify_gen_unary (NEG
, mode
,
6538 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6544 /* Look for MIN or MAX. */
6546 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6548 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6549 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6550 && ! side_effects_p (cond
))
6555 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6558 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6561 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6564 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6569 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6570 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6571 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6572 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6573 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6574 neither 1 or -1, but it isn't worth checking for. */
6576 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6578 && is_int_mode (mode
, &int_mode
)
6579 && ! side_effects_p (x
))
6581 rtx t
= make_compound_operation (true_rtx
, SET
);
6582 rtx f
= make_compound_operation (false_rtx
, SET
);
6583 rtx cond_op0
= XEXP (cond
, 0);
6584 rtx cond_op1
= XEXP (cond
, 1);
6585 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6586 scalar_int_mode m
= int_mode
;
6587 rtx z
= 0, c1
= NULL_RTX
;
6589 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6590 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6591 || GET_CODE (t
) == ASHIFT
6592 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6593 && rtx_equal_p (XEXP (t
, 0), f
))
6594 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6596 /* If an identity-zero op is commutative, check whether there
6597 would be a match if we swapped the operands. */
6598 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6599 || GET_CODE (t
) == XOR
)
6600 && rtx_equal_p (XEXP (t
, 1), f
))
6601 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6602 else if (GET_CODE (t
) == SIGN_EXTEND
6603 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6604 && (GET_CODE (XEXP (t
, 0)) == PLUS
6605 || GET_CODE (XEXP (t
, 0)) == MINUS
6606 || GET_CODE (XEXP (t
, 0)) == IOR
6607 || GET_CODE (XEXP (t
, 0)) == XOR
6608 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6609 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6610 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6611 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6612 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6613 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6614 && (num_sign_bit_copies (f
, GET_MODE (f
))
6616 (GET_MODE_PRECISION (int_mode
)
6617 - GET_MODE_PRECISION (inner_mode
))))
6619 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6620 extend_op
= SIGN_EXTEND
;
6623 else if (GET_CODE (t
) == SIGN_EXTEND
6624 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6625 && (GET_CODE (XEXP (t
, 0)) == PLUS
6626 || GET_CODE (XEXP (t
, 0)) == IOR
6627 || GET_CODE (XEXP (t
, 0)) == XOR
)
6628 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6629 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6630 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6631 && (num_sign_bit_copies (f
, GET_MODE (f
))
6633 (GET_MODE_PRECISION (int_mode
)
6634 - GET_MODE_PRECISION (inner_mode
))))
6636 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6637 extend_op
= SIGN_EXTEND
;
6640 else if (GET_CODE (t
) == ZERO_EXTEND
6641 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6642 && (GET_CODE (XEXP (t
, 0)) == PLUS
6643 || GET_CODE (XEXP (t
, 0)) == MINUS
6644 || GET_CODE (XEXP (t
, 0)) == IOR
6645 || GET_CODE (XEXP (t
, 0)) == XOR
6646 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6647 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6648 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6649 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6650 && HWI_COMPUTABLE_MODE_P (int_mode
)
6651 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6652 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6653 && ((nonzero_bits (f
, GET_MODE (f
))
6654 & ~GET_MODE_MASK (inner_mode
))
6657 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6658 extend_op
= ZERO_EXTEND
;
6661 else if (GET_CODE (t
) == ZERO_EXTEND
6662 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6663 && (GET_CODE (XEXP (t
, 0)) == PLUS
6664 || GET_CODE (XEXP (t
, 0)) == IOR
6665 || GET_CODE (XEXP (t
, 0)) == XOR
)
6666 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6667 && HWI_COMPUTABLE_MODE_P (int_mode
)
6668 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6669 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6670 && ((nonzero_bits (f
, GET_MODE (f
))
6671 & ~GET_MODE_MASK (inner_mode
))
6674 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6675 extend_op
= ZERO_EXTEND
;
6681 machine_mode cm
= m
;
6682 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6683 && GET_MODE (c1
) != VOIDmode
)
6685 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6686 cond_op0
, cond_op1
),
6687 pc_rtx
, pc_rtx
, 0, 0, 0);
6688 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6689 simplify_gen_binary (MULT
, cm
, c1
,
6691 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6692 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6694 if (extend_op
!= UNKNOWN
)
6695 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6701 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6702 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6703 negation of a single bit, we can convert this operation to a shift. We
6704 can actually do this more generally, but it doesn't seem worth it. */
6707 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6708 && XEXP (cond
, 1) == const0_rtx
6709 && false_rtx
== const0_rtx
6710 && CONST_INT_P (true_rtx
)
6711 && ((nonzero_bits (XEXP (cond
, 0), int_mode
) == 1
6712 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6713 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6714 == GET_MODE_PRECISION (int_mode
))
6715 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6717 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6718 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6720 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6721 non-zero bit in A is C1. */
6722 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6723 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6724 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6725 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6726 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6727 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6728 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6730 rtx val
= XEXP (cond
, 0);
6731 if (inner_mode
== int_mode
)
6733 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6734 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6740 /* Simplify X, a SET expression. Return the new expression. */
6743 simplify_set (rtx x
)
6745 rtx src
= SET_SRC (x
);
6746 rtx dest
= SET_DEST (x
);
6748 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6749 rtx_insn
*other_insn
;
6751 scalar_int_mode int_mode
;
6753 /* (set (pc) (return)) gets written as (return). */
6754 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6757 /* Now that we know for sure which bits of SRC we are using, see if we can
6758 simplify the expression for the object knowing that we only need the
6761 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6763 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6764 SUBST (SET_SRC (x
), src
);
6767 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6768 the comparison result and try to simplify it unless we already have used
6769 undobuf.other_insn. */
6770 if ((GET_MODE_CLASS (mode
) == MODE_CC
6771 || GET_CODE (src
) == COMPARE
6773 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6774 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6775 && COMPARISON_P (*cc_use
)
6776 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6778 enum rtx_code old_code
= GET_CODE (*cc_use
);
6779 enum rtx_code new_code
;
6781 int other_changed
= 0;
6782 rtx inner_compare
= NULL_RTX
;
6783 machine_mode compare_mode
= GET_MODE (dest
);
6785 if (GET_CODE (src
) == COMPARE
)
6787 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6788 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6790 inner_compare
= op0
;
6791 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6795 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6797 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6800 new_code
= old_code
;
6801 else if (!CONSTANT_P (tmp
))
6803 new_code
= GET_CODE (tmp
);
6804 op0
= XEXP (tmp
, 0);
6805 op1
= XEXP (tmp
, 1);
6809 rtx pat
= PATTERN (other_insn
);
6810 undobuf
.other_insn
= other_insn
;
6811 SUBST (*cc_use
, tmp
);
6813 /* Attempt to simplify CC user. */
6814 if (GET_CODE (pat
) == SET
)
6816 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6817 if (new_rtx
!= NULL_RTX
)
6818 SUBST (SET_SRC (pat
), new_rtx
);
6821 /* Convert X into a no-op move. */
6822 SUBST (SET_DEST (x
), pc_rtx
);
6823 SUBST (SET_SRC (x
), pc_rtx
);
6827 /* Simplify our comparison, if possible. */
6828 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6830 #ifdef SELECT_CC_MODE
6831 /* If this machine has CC modes other than CCmode, check to see if we
6832 need to use a different CC mode here. */
6833 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6834 compare_mode
= GET_MODE (op0
);
6835 else if (inner_compare
6836 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6837 && new_code
== old_code
6838 && op0
== XEXP (inner_compare
, 0)
6839 && op1
== XEXP (inner_compare
, 1))
6840 compare_mode
= GET_MODE (inner_compare
);
6842 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6844 /* If the mode changed, we have to change SET_DEST, the mode in the
6845 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6846 a hard register, just build new versions with the proper mode. If it
6847 is a pseudo, we lose unless it is only time we set the pseudo, in
6848 which case we can safely change its mode. */
6849 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6851 if (can_change_dest_mode (dest
, 0, compare_mode
))
6853 unsigned int regno
= REGNO (dest
);
6856 if (regno
< FIRST_PSEUDO_REGISTER
)
6857 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6860 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6861 new_dest
= regno_reg_rtx
[regno
];
6864 SUBST (SET_DEST (x
), new_dest
);
6865 SUBST (XEXP (*cc_use
, 0), new_dest
);
6871 #endif /* SELECT_CC_MODE */
6873 /* If the code changed, we have to build a new comparison in
6874 undobuf.other_insn. */
6875 if (new_code
!= old_code
)
6877 int other_changed_previously
= other_changed
;
6878 unsigned HOST_WIDE_INT mask
;
6879 rtx old_cc_use
= *cc_use
;
6881 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6885 /* If the only change we made was to change an EQ into an NE or
6886 vice versa, OP0 has only one bit that might be nonzero, and OP1
6887 is zero, check if changing the user of the condition code will
6888 produce a valid insn. If it won't, we can keep the original code
6889 in that insn by surrounding our operation with an XOR. */
6891 if (((old_code
== NE
&& new_code
== EQ
)
6892 || (old_code
== EQ
&& new_code
== NE
))
6893 && ! other_changed_previously
&& op1
== const0_rtx
6894 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6895 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6897 rtx pat
= PATTERN (other_insn
), note
= 0;
6899 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6900 && ! check_asm_operands (pat
)))
6902 *cc_use
= old_cc_use
;
6905 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6913 undobuf
.other_insn
= other_insn
;
6915 /* Don't generate a compare of a CC with 0, just use that CC. */
6916 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6918 SUBST (SET_SRC (x
), op0
);
6921 /* Otherwise, if we didn't previously have the same COMPARE we
6922 want, create it from scratch. */
6923 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6924 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6926 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6932 /* Get SET_SRC in a form where we have placed back any
6933 compound expressions. Then do the checks below. */
6934 src
= make_compound_operation (src
, SET
);
6935 SUBST (SET_SRC (x
), src
);
6938 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6939 and X being a REG or (subreg (reg)), we may be able to convert this to
6940 (set (subreg:m2 x) (op)).
6942 We can always do this if M1 is narrower than M2 because that means that
6943 we only care about the low bits of the result.
6945 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6946 perform a narrower operation than requested since the high-order bits will
6947 be undefined. On machine where it is defined, this transformation is safe
6948 as long as M1 and M2 have the same number of words. */
6950 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6951 && !OBJECT_P (SUBREG_REG (src
))
6952 && (known_equal_after_align_up
6953 (GET_MODE_SIZE (GET_MODE (src
)),
6954 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))),
6956 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
6957 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6958 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
6959 GET_MODE (SUBREG_REG (src
)),
6962 || (GET_CODE (dest
) == SUBREG
6963 && REG_P (SUBREG_REG (dest
)))))
6965 SUBST (SET_DEST (x
),
6966 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6968 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6970 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6973 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6976 && partial_subreg_p (src
)
6977 && subreg_lowpart_p (src
))
6979 rtx inner
= SUBREG_REG (src
);
6980 machine_mode inner_mode
= GET_MODE (inner
);
6982 /* Here we make sure that we don't have a sign bit on. */
6983 if (val_signbit_known_clear_p (GET_MODE (src
),
6984 nonzero_bits (inner
, inner_mode
)))
6986 SUBST (SET_SRC (x
), inner
);
6991 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6992 would require a paradoxical subreg. Replace the subreg with a
6993 zero_extend to avoid the reload that would otherwise be required.
6994 Don't do this unless we have a scalar integer mode, otherwise the
6995 transformation is incorrect. */
6997 enum rtx_code extend_op
;
6998 if (paradoxical_subreg_p (src
)
6999 && MEM_P (SUBREG_REG (src
))
7000 && SCALAR_INT_MODE_P (GET_MODE (src
))
7001 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
7004 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
7009 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7010 are comparing an item known to be 0 or -1 against 0, use a logical
7011 operation instead. Check for one of the arms being an IOR of the other
7012 arm with some value. We compute three terms to be IOR'ed together. In
7013 practice, at most two will be nonzero. Then we do the IOR's. */
7015 if (GET_CODE (dest
) != PC
7016 && GET_CODE (src
) == IF_THEN_ELSE
7017 && is_int_mode (GET_MODE (src
), &int_mode
)
7018 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7019 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7020 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
7021 && (!HAVE_conditional_move
7022 || ! can_conditionally_move_p (int_mode
))
7023 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
7024 == GET_MODE_PRECISION (int_mode
))
7025 && ! side_effects_p (src
))
7027 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7028 ? XEXP (src
, 1) : XEXP (src
, 2));
7029 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7030 ? XEXP (src
, 2) : XEXP (src
, 1));
7031 rtx term1
= const0_rtx
, term2
, term3
;
7033 if (GET_CODE (true_rtx
) == IOR
7034 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7035 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7036 else if (GET_CODE (true_rtx
) == IOR
7037 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7038 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7039 else if (GET_CODE (false_rtx
) == IOR
7040 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7041 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7042 else if (GET_CODE (false_rtx
) == IOR
7043 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7044 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7046 term2
= simplify_gen_binary (AND
, int_mode
,
7047 XEXP (XEXP (src
, 0), 0), true_rtx
);
7048 term3
= simplify_gen_binary (AND
, int_mode
,
7049 simplify_gen_unary (NOT
, int_mode
,
7050 XEXP (XEXP (src
, 0), 0),
7055 simplify_gen_binary (IOR
, int_mode
,
7056 simplify_gen_binary (IOR
, int_mode
,
7063 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7064 whole thing fail. */
7065 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7067 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7070 /* Convert this into a field assignment operation, if possible. */
7071 return make_field_assignment (x
);
7074 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7078 simplify_logical (rtx x
)
7080 rtx op0
= XEXP (x
, 0);
7081 rtx op1
= XEXP (x
, 1);
7082 scalar_int_mode mode
;
7084 switch (GET_CODE (x
))
7087 /* We can call simplify_and_const_int only if we don't lose
7088 any (sign) bits when converting INTVAL (op1) to
7089 "unsigned HOST_WIDE_INT". */
7090 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7091 && CONST_INT_P (op1
)
7092 && (HWI_COMPUTABLE_MODE_P (mode
)
7093 || INTVAL (op1
) > 0))
7095 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7096 if (GET_CODE (x
) != AND
)
7103 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7104 apply the distributive law and then the inverse distributive
7105 law to see if things simplify. */
7106 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7108 rtx result
= distribute_and_simplify_rtx (x
, 0);
7112 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7114 rtx result
= distribute_and_simplify_rtx (x
, 1);
7121 /* If we have (ior (and A B) C), apply the distributive law and then
7122 the inverse distributive law to see if things simplify. */
7124 if (GET_CODE (op0
) == AND
)
7126 rtx result
= distribute_and_simplify_rtx (x
, 0);
7131 if (GET_CODE (op1
) == AND
)
7133 rtx result
= distribute_and_simplify_rtx (x
, 1);
7146 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7147 operations" because they can be replaced with two more basic operations.
7148 ZERO_EXTEND is also considered "compound" because it can be replaced with
7149 an AND operation, which is simpler, though only one operation.
7151 The function expand_compound_operation is called with an rtx expression
7152 and will convert it to the appropriate shifts and AND operations,
7153 simplifying at each stage.
7155 The function make_compound_operation is called to convert an expression
7156 consisting of shifts and ANDs into the equivalent compound expression.
7157 It is the inverse of this function, loosely speaking. */
7160 expand_compound_operation (rtx x
)
7162 unsigned HOST_WIDE_INT pos
= 0, len
;
7164 unsigned int modewidth
;
7166 scalar_int_mode inner_mode
;
7168 switch (GET_CODE (x
))
7174 /* We can't necessarily use a const_int for a multiword mode;
7175 it depends on implicitly extending the value.
7176 Since we don't know the right way to extend it,
7177 we can't tell whether the implicit way is right.
7179 Even for a mode that is no wider than a const_int,
7180 we can't win, because we need to sign extend one of its bits through
7181 the rest of it, and we don't know which bit. */
7182 if (CONST_INT_P (XEXP (x
, 0)))
7185 /* Reject modes that aren't scalar integers because turning vector
7186 or complex modes into shifts causes problems. */
7187 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7190 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7191 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7192 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7193 reloaded. If not for that, MEM's would very rarely be safe.
7195 Reject modes bigger than a word, because we might not be able
7196 to reference a two-register group starting with an arbitrary register
7197 (and currently gen_lowpart might crash for a SUBREG). */
7199 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7202 len
= GET_MODE_PRECISION (inner_mode
);
7203 /* If the inner object has VOIDmode (the only way this can happen
7204 is if it is an ASM_OPERANDS), we can't do anything since we don't
7205 know how much masking to do. */
7217 /* If the operand is a CLOBBER, just return it. */
7218 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7221 if (!CONST_INT_P (XEXP (x
, 1))
7222 || !CONST_INT_P (XEXP (x
, 2)))
7225 /* Reject modes that aren't scalar integers because turning vector
7226 or complex modes into shifts causes problems. */
7227 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7230 len
= INTVAL (XEXP (x
, 1));
7231 pos
= INTVAL (XEXP (x
, 2));
7233 /* This should stay within the object being extracted, fail otherwise. */
7234 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7237 if (BITS_BIG_ENDIAN
)
7238 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7246 /* We've rejected non-scalar operations by now. */
7247 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7249 /* Convert sign extension to zero extension, if we know that the high
7250 bit is not set, as this is easier to optimize. It will be converted
7251 back to cheaper alternative in make_extraction. */
7252 if (GET_CODE (x
) == SIGN_EXTEND
7253 && HWI_COMPUTABLE_MODE_P (mode
)
7254 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7255 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7258 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7259 rtx temp2
= expand_compound_operation (temp
);
7261 /* Make sure this is a profitable operation. */
7262 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7263 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7265 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7266 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7272 /* We can optimize some special cases of ZERO_EXTEND. */
7273 if (GET_CODE (x
) == ZERO_EXTEND
)
7275 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7276 know that the last value didn't have any inappropriate bits
7278 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7279 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7280 && HWI_COMPUTABLE_MODE_P (mode
)
7281 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7282 & ~GET_MODE_MASK (inner_mode
)) == 0)
7283 return XEXP (XEXP (x
, 0), 0);
7285 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7286 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7287 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7288 && subreg_lowpart_p (XEXP (x
, 0))
7289 && HWI_COMPUTABLE_MODE_P (mode
)
7290 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7291 & ~GET_MODE_MASK (inner_mode
)) == 0)
7292 return SUBREG_REG (XEXP (x
, 0));
7294 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7295 is a comparison and STORE_FLAG_VALUE permits. This is like
7296 the first case, but it works even when MODE is larger
7297 than HOST_WIDE_INT. */
7298 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7299 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7300 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7301 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7302 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7303 return XEXP (XEXP (x
, 0), 0);
7305 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7306 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7307 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7308 && subreg_lowpart_p (XEXP (x
, 0))
7309 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7310 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7311 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7312 return SUBREG_REG (XEXP (x
, 0));
7316 /* If we reach here, we want to return a pair of shifts. The inner
7317 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7318 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7319 logical depending on the value of UNSIGNEDP.
7321 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7322 converted into an AND of a shift.
7324 We must check for the case where the left shift would have a negative
7325 count. This can happen in a case like (x >> 31) & 255 on machines
7326 that can't shift by a constant. On those machines, we would first
7327 combine the shift with the AND to produce a variable-position
7328 extraction. Then the constant of 31 would be substituted in
7329 to produce such a position. */
7331 modewidth
= GET_MODE_PRECISION (mode
);
7332 if (modewidth
>= pos
+ len
)
7334 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7335 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7337 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7338 tem
, modewidth
- pos
- len
);
7339 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7340 mode
, tem
, modewidth
- len
);
7342 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7343 tem
= simplify_and_const_int (NULL_RTX
, mode
,
7344 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7347 (HOST_WIDE_INT_1U
<< len
) - 1);
7349 /* Any other cases we can't handle. */
7352 /* If we couldn't do this for some reason, return the original
7354 if (GET_CODE (tem
) == CLOBBER
)
7360 /* X is a SET which contains an assignment of one object into
7361 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7362 or certain SUBREGS). If possible, convert it into a series of
7365 We half-heartedly support variable positions, but do not at all
7366 support variable lengths. */
7369 expand_field_assignment (const_rtx x
)
7372 rtx pos
; /* Always counts from low bit. */
7374 rtx mask
, cleared
, masked
;
7375 scalar_int_mode compute_mode
;
7377 /* Loop until we find something we can't simplify. */
7380 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7381 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7383 rtx x0
= XEXP (SET_DEST (x
), 0);
7384 if (!GET_MODE_PRECISION (GET_MODE (x0
)).is_constant (&len
))
7386 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7387 pos
= gen_int_mode (subreg_lsb (XEXP (SET_DEST (x
), 0)),
7390 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7391 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7393 inner
= XEXP (SET_DEST (x
), 0);
7394 if (!GET_MODE_PRECISION (GET_MODE (inner
)).is_constant (&inner_len
))
7397 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7398 pos
= XEXP (SET_DEST (x
), 2);
7400 /* A constant position should stay within the width of INNER. */
7401 if (CONST_INT_P (pos
) && INTVAL (pos
) + len
> inner_len
)
7404 if (BITS_BIG_ENDIAN
)
7406 if (CONST_INT_P (pos
))
7407 pos
= GEN_INT (inner_len
- len
- INTVAL (pos
));
7408 else if (GET_CODE (pos
) == MINUS
7409 && CONST_INT_P (XEXP (pos
, 1))
7410 && INTVAL (XEXP (pos
, 1)) == inner_len
- len
)
7411 /* If position is ADJUST - X, new position is X. */
7412 pos
= XEXP (pos
, 0);
7414 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7415 gen_int_mode (inner_len
- len
,
7421 /* If the destination is a subreg that overwrites the whole of the inner
7422 register, we can move the subreg to the source. */
7423 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7424 /* We need SUBREGs to compute nonzero_bits properly. */
7425 && nonzero_sign_valid
7426 && !read_modify_subreg_p (SET_DEST (x
)))
7428 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7430 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7437 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7438 inner
= SUBREG_REG (inner
);
7440 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7441 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7443 /* Don't do anything for vector or complex integral types. */
7444 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7447 /* Try to find an integral mode to pun with. */
7448 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7449 .exists (&compute_mode
))
7452 inner
= gen_lowpart (compute_mode
, inner
);
7455 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7456 if (len
>= HOST_BITS_PER_WIDE_INT
)
7459 /* Don't try to compute in too wide unsupported modes. */
7460 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7463 /* Now compute the equivalent expression. Make a copy of INNER
7464 for the SET_DEST in case it is a MEM into which we will substitute;
7465 we don't want shared RTL in that case. */
7466 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7468 cleared
= simplify_gen_binary (AND
, compute_mode
,
7469 simplify_gen_unary (NOT
, compute_mode
,
7470 simplify_gen_binary (ASHIFT
,
7475 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7476 simplify_gen_binary (
7478 gen_lowpart (compute_mode
, SET_SRC (x
)),
7482 x
= gen_rtx_SET (copy_rtx (inner
),
7483 simplify_gen_binary (IOR
, compute_mode
,
7490 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7491 it is an RTX that represents the (variable) starting position; otherwise,
7492 POS is the (constant) starting bit position. Both are counted from the LSB.
7494 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7496 IN_DEST is nonzero if this is a reference in the destination of a SET.
7497 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7498 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7501 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7502 ZERO_EXTRACT should be built even for bits starting at bit 0.
7504 MODE is the desired mode of the result (if IN_DEST == 0).
7506 The result is an RTX for the extraction or NULL_RTX if the target
7510 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7511 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7512 int in_dest
, int in_compare
)
7514 /* This mode describes the size of the storage area
7515 to fetch the overall value from. Within that, we
7516 ignore the POS lowest bits, etc. */
7517 machine_mode is_mode
= GET_MODE (inner
);
7518 machine_mode inner_mode
;
7519 scalar_int_mode wanted_inner_mode
;
7520 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7521 scalar_int_mode pos_mode
= word_mode
;
7522 machine_mode extraction_mode
= word_mode
;
7524 rtx orig_pos_rtx
= pos_rtx
;
7525 HOST_WIDE_INT orig_pos
;
7527 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7528 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7530 if (GET_CODE (inner
) == SUBREG
7531 && subreg_lowpart_p (inner
)
7532 && (paradoxical_subreg_p (inner
)
7533 /* If trying or potentionally trying to extract
7534 bits outside of is_mode, don't look through
7535 non-paradoxical SUBREGs. See PR82192. */
7536 || (pos_rtx
== NULL_RTX
7537 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))))
7539 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7540 consider just the QI as the memory to extract from.
7541 The subreg adds or removes high bits; its mode is
7542 irrelevant to the meaning of this extraction,
7543 since POS and LEN count from the lsb. */
7544 if (MEM_P (SUBREG_REG (inner
)))
7545 is_mode
= GET_MODE (SUBREG_REG (inner
));
7546 inner
= SUBREG_REG (inner
);
7548 else if (GET_CODE (inner
) == ASHIFT
7549 && CONST_INT_P (XEXP (inner
, 1))
7550 && pos_rtx
== 0 && pos
== 0
7551 && len
> UINTVAL (XEXP (inner
, 1)))
7553 /* We're extracting the least significant bits of an rtx
7554 (ashift X (const_int C)), where LEN > C. Extract the
7555 least significant (LEN - C) bits of X, giving an rtx
7556 whose mode is MODE, then shift it left C times. */
7557 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7558 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7559 unsignedp
, in_dest
, in_compare
);
7561 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7563 else if (GET_CODE (inner
) == TRUNCATE
7564 /* If trying or potentionally trying to extract
7565 bits outside of is_mode, don't look through
7566 TRUNCATE. See PR82192. */
7567 && pos_rtx
== NULL_RTX
7568 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7569 inner
= XEXP (inner
, 0);
7571 inner_mode
= GET_MODE (inner
);
7573 /* See if this can be done without an extraction. We never can if the
7574 width of the field is not the same as that of some integer mode. For
7575 registers, we can only avoid the extraction if the position is at the
7576 low-order bit and this is either not in the destination or we have the
7577 appropriate STRICT_LOW_PART operation available.
7579 For MEM, we can avoid an extract if the field starts on an appropriate
7580 boundary and we can change the mode of the memory reference. */
7582 scalar_int_mode tmode
;
7583 if (int_mode_for_size (len
, 1).exists (&tmode
)
7584 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7586 && (pos
== 0 || REG_P (inner
))
7587 && (inner_mode
== tmode
7589 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7590 || reg_truncated_to_mode (tmode
, inner
))
7593 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7594 || (MEM_P (inner
) && pos_rtx
== 0
7596 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7597 : BITS_PER_UNIT
)) == 0
7598 /* We can't do this if we are widening INNER_MODE (it
7599 may not be aligned, for one thing). */
7600 && !paradoxical_subreg_p (tmode
, inner_mode
)
7601 && (inner_mode
== tmode
7602 || (! mode_dependent_address_p (XEXP (inner
, 0),
7603 MEM_ADDR_SPACE (inner
))
7604 && ! MEM_VOLATILE_P (inner
))))))
7606 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7607 field. If the original and current mode are the same, we need not
7608 adjust the offset. Otherwise, we do if bytes big endian.
7610 If INNER is not a MEM, get a piece consisting of just the field
7611 of interest (in this case POS % BITS_PER_WORD must be 0). */
7617 /* POS counts from lsb, but make OFFSET count in memory order. */
7618 if (BYTES_BIG_ENDIAN
)
7619 offset
= bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode
)
7622 offset
= pos
/ BITS_PER_UNIT
;
7624 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7626 else if (REG_P (inner
))
7628 if (tmode
!= inner_mode
)
7630 /* We can't call gen_lowpart in a DEST since we
7631 always want a SUBREG (see below) and it would sometimes
7632 return a new hard register. */
7636 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7638 /* Avoid creating invalid subregs, for example when
7639 simplifying (x>>32)&255. */
7640 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7643 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7646 new_rtx
= gen_lowpart (tmode
, inner
);
7652 new_rtx
= force_to_mode (inner
, tmode
,
7653 len
>= HOST_BITS_PER_WIDE_INT
7655 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7657 /* If this extraction is going into the destination of a SET,
7658 make a STRICT_LOW_PART unless we made a MEM. */
7661 return (MEM_P (new_rtx
) ? new_rtx
7662 : (GET_CODE (new_rtx
) != SUBREG
7663 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7664 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7669 if (CONST_SCALAR_INT_P (new_rtx
))
7670 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7671 mode
, new_rtx
, tmode
);
7673 /* If we know that no extraneous bits are set, and that the high
7674 bit is not set, convert the extraction to the cheaper of
7675 sign and zero extension, that are equivalent in these cases. */
7676 if (flag_expensive_optimizations
7677 && (HWI_COMPUTABLE_MODE_P (tmode
)
7678 && ((nonzero_bits (new_rtx
, tmode
)
7679 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7682 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7683 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7685 /* Prefer ZERO_EXTENSION, since it gives more information to
7687 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7688 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7693 /* Otherwise, sign- or zero-extend unless we already are in the
7696 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7700 /* Unless this is a COMPARE or we have a funny memory reference,
7701 don't do anything with zero-extending field extracts starting at
7702 the low-order bit since they are simple AND operations. */
7703 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7704 && ! in_compare
&& unsignedp
)
7707 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7708 if the position is not a constant and the length is not 1. In all
7709 other cases, we would only be going outside our object in cases when
7710 an original shift would have been undefined. */
7712 && ((pos_rtx
== 0 && maybe_gt (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7713 || (pos_rtx
!= 0 && len
!= 1)))
7716 enum extraction_pattern pattern
= (in_dest
? EP_insv
7717 : unsignedp
? EP_extzv
: EP_extv
);
7719 /* If INNER is not from memory, we want it to have the mode of a register
7720 extraction pattern's structure operand, or word_mode if there is no
7721 such pattern. The same applies to extraction_mode and pos_mode
7722 and their respective operands.
7724 For memory, assume that the desired extraction_mode and pos_mode
7725 are the same as for a register operation, since at present we don't
7726 have named patterns for aligned memory structures. */
7727 struct extraction_insn insn
;
7728 unsigned int inner_size
;
7729 if (GET_MODE_BITSIZE (inner_mode
).is_constant (&inner_size
)
7730 && get_best_reg_extraction_insn (&insn
, pattern
, inner_size
, mode
))
7732 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7733 pos_mode
= insn
.pos_mode
;
7734 extraction_mode
= insn
.field_mode
;
7737 /* Never narrow an object, since that might not be safe. */
7739 if (mode
!= VOIDmode
7740 && partial_subreg_p (extraction_mode
, mode
))
7741 extraction_mode
= mode
;
7744 wanted_inner_mode
= wanted_inner_reg_mode
;
7747 /* Be careful not to go beyond the extracted object and maintain the
7748 natural alignment of the memory. */
7749 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7750 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7751 > GET_MODE_BITSIZE (wanted_inner_mode
))
7752 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7757 if (BITS_BIG_ENDIAN
)
7759 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7760 BITS_BIG_ENDIAN style. If position is constant, compute new
7761 position. Otherwise, build subtraction.
7762 Note that POS is relative to the mode of the original argument.
7763 If it's a MEM we need to recompute POS relative to that.
7764 However, if we're extracting from (or inserting into) a register,
7765 we want to recompute POS relative to wanted_inner_mode. */
7768 width
= GET_MODE_BITSIZE (wanted_inner_mode
);
7769 else if (!GET_MODE_BITSIZE (is_mode
).is_constant (&width
))
7773 pos
= width
- len
- pos
;
7776 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7777 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7779 /* POS may be less than 0 now, but we check for that below.
7780 Note that it can only be less than 0 if !MEM_P (inner). */
7783 /* If INNER has a wider mode, and this is a constant extraction, try to
7784 make it smaller and adjust the byte to point to the byte containing
7786 if (wanted_inner_mode
!= VOIDmode
7787 && inner_mode
!= wanted_inner_mode
7789 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7791 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7792 && ! MEM_VOLATILE_P (inner
))
7794 poly_int64 offset
= 0;
7796 /* The computations below will be correct if the machine is big
7797 endian in both bits and bytes or little endian in bits and bytes.
7798 If it is mixed, we must adjust. */
7800 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7801 adjust OFFSET to compensate. */
7802 if (BYTES_BIG_ENDIAN
7803 && paradoxical_subreg_p (is_mode
, inner_mode
))
7804 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7806 /* We can now move to the desired byte. */
7807 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7808 * GET_MODE_SIZE (wanted_inner_mode
);
7809 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7811 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7812 && is_mode
!= wanted_inner_mode
)
7813 offset
= (GET_MODE_SIZE (is_mode
)
7814 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7816 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7819 /* If INNER is not memory, get it into the proper mode. If we are changing
7820 its mode, POS must be a constant and smaller than the size of the new
7822 else if (!MEM_P (inner
))
7824 /* On the LHS, don't create paradoxical subregs implicitely truncating
7825 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7827 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7831 if (GET_MODE (inner
) != wanted_inner_mode
7833 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7839 inner
= force_to_mode (inner
, wanted_inner_mode
,
7841 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7843 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7848 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7849 have to zero extend. Otherwise, we can just use a SUBREG.
7851 We dealt with constant rtxes earlier, so pos_rtx cannot
7852 have VOIDmode at this point. */
7854 && (GET_MODE_SIZE (pos_mode
)
7855 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7857 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7858 GET_MODE (pos_rtx
));
7860 /* If we know that no extraneous bits are set, and that the high
7861 bit is not set, convert extraction to cheaper one - either
7862 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7864 if (flag_expensive_optimizations
7865 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7866 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7867 & ~(((unsigned HOST_WIDE_INT
)
7868 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7872 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7873 GET_MODE (pos_rtx
));
7875 /* Prefer ZERO_EXTENSION, since it gives more information to
7877 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7878 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7884 /* Make POS_RTX unless we already have it and it is correct. If we don't
7885 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7887 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7888 pos_rtx
= orig_pos_rtx
;
7890 else if (pos_rtx
== 0)
7891 pos_rtx
= GEN_INT (pos
);
7893 /* Make the required operation. See if we can use existing rtx. */
7894 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7895 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7897 new_rtx
= gen_lowpart (mode
, new_rtx
);
7902 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7903 can be commuted with any other operations in X. Return X without
7904 that shift if so. */
7907 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
7909 enum rtx_code code
= GET_CODE (x
);
7915 /* This is the shift itself. If it is wide enough, we will return
7916 either the value being shifted if the shift count is equal to
7917 COUNT or a shift for the difference. */
7918 if (CONST_INT_P (XEXP (x
, 1))
7919 && INTVAL (XEXP (x
, 1)) >= count
)
7920 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7921 INTVAL (XEXP (x
, 1)) - count
);
7925 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7926 return simplify_gen_unary (code
, mode
, tem
, mode
);
7930 case PLUS
: case IOR
: case XOR
: case AND
:
7931 /* If we can safely shift this constant and we find the inner shift,
7932 make a new operation. */
7933 if (CONST_INT_P (XEXP (x
, 1))
7934 && (UINTVAL (XEXP (x
, 1))
7935 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7936 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7938 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7939 return simplify_gen_binary (code
, mode
, tem
,
7940 gen_int_mode (val
, mode
));
7951 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7952 level of the expression and MODE is its mode. IN_CODE is as for
7953 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7954 that should be used when recursing on operands of *X_PTR.
7956 There are two possible actions:
7958 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7959 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7961 - Return a new rtx, which the caller returns directly. */
7964 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
7965 enum rtx_code in_code
,
7966 enum rtx_code
*next_code_ptr
)
7969 enum rtx_code next_code
= *next_code_ptr
;
7970 enum rtx_code code
= GET_CODE (x
);
7971 int mode_width
= GET_MODE_PRECISION (mode
);
7976 scalar_int_mode inner_mode
;
7977 bool equality_comparison
= false;
7981 equality_comparison
= true;
7985 /* Process depending on the code of this operation. If NEW is set
7986 nonzero, it will be returned. */
7991 /* Convert shifts by constants into multiplications if inside
7993 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7994 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7995 && INTVAL (XEXP (x
, 1)) >= 0)
7997 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7998 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
8000 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8001 if (GET_CODE (new_rtx
) == NEG
)
8003 new_rtx
= XEXP (new_rtx
, 0);
8006 multval
= trunc_int_for_mode (multval
, mode
);
8007 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8014 lhs
= make_compound_operation (lhs
, next_code
);
8015 rhs
= make_compound_operation (rhs
, next_code
);
8016 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8018 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8020 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8022 else if (GET_CODE (lhs
) == MULT
8023 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8025 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8026 simplify_gen_unary (NEG
, mode
,
8029 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8033 SUBST (XEXP (x
, 0), lhs
);
8034 SUBST (XEXP (x
, 1), rhs
);
8036 maybe_swap_commutative_operands (x
);
8042 lhs
= make_compound_operation (lhs
, next_code
);
8043 rhs
= make_compound_operation (rhs
, next_code
);
8044 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8046 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8048 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8050 else if (GET_CODE (rhs
) == MULT
8051 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8053 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8054 simplify_gen_unary (NEG
, mode
,
8057 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8061 SUBST (XEXP (x
, 0), lhs
);
8062 SUBST (XEXP (x
, 1), rhs
);
8067 /* If the second operand is not a constant, we can't do anything
8069 if (!CONST_INT_P (XEXP (x
, 1)))
8072 /* If the constant is a power of two minus one and the first operand
8073 is a logical right shift, make an extraction. */
8074 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8075 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8077 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8078 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8079 i
, 1, 0, in_code
== COMPARE
);
8082 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8083 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8084 && subreg_lowpart_p (XEXP (x
, 0))
8085 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8087 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8088 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8090 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8091 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8092 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8094 i
, 1, 0, in_code
== COMPARE
);
8096 /* If we narrowed the mode when dropping the subreg, then we lose. */
8097 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8100 /* If that didn't give anything, see if the AND simplifies on
8102 if (!new_rtx
&& i
>= 0)
8104 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8105 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8106 0, in_code
== COMPARE
);
8109 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8110 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8111 || GET_CODE (XEXP (x
, 0)) == IOR
)
8112 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8113 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8114 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8116 /* Apply the distributive law, and then try to make extractions. */
8117 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8118 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8120 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8122 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8125 /* If we are have (and (rotate X C) M) and C is larger than the number
8126 of bits in M, this is an extraction. */
8128 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8129 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8130 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8131 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8133 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8134 new_rtx
= make_extraction (mode
, new_rtx
,
8135 (GET_MODE_PRECISION (mode
)
8136 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8137 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8140 /* On machines without logical shifts, if the operand of the AND is
8141 a logical shift and our mask turns off all the propagated sign
8142 bits, we can replace the logical shift with an arithmetic shift. */
8143 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8144 && !have_insn_for (LSHIFTRT
, mode
)
8145 && have_insn_for (ASHIFTRT
, mode
)
8146 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8147 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8148 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8149 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8151 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8153 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8154 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8156 gen_rtx_ASHIFTRT (mode
,
8157 make_compound_operation (XEXP (XEXP (x
,
8161 XEXP (XEXP (x
, 0), 1)));
8164 /* If the constant is one less than a power of two, this might be
8165 representable by an extraction even if no shift is present.
8166 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8167 we are in a COMPARE. */
8168 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8169 new_rtx
= make_extraction (mode
,
8170 make_compound_operation (XEXP (x
, 0),
8172 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8174 /* If we are in a comparison and this is an AND with a power of two,
8175 convert this into the appropriate bit extract. */
8176 else if (in_code
== COMPARE
8177 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8178 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8179 new_rtx
= make_extraction (mode
,
8180 make_compound_operation (XEXP (x
, 0),
8182 i
, NULL_RTX
, 1, 1, 0, 1);
8184 /* If the one operand is a paradoxical subreg of a register or memory and
8185 the constant (limited to the smaller mode) has only zero bits where
8186 the sub expression has known zero bits, this can be expressed as
8188 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8192 sub
= XEXP (XEXP (x
, 0), 0);
8193 machine_mode sub_mode
= GET_MODE (sub
);
8195 if ((REG_P (sub
) || MEM_P (sub
))
8196 && GET_MODE_PRECISION (sub_mode
).is_constant (&sub_width
)
8197 && sub_width
< mode_width
)
8199 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8200 unsigned HOST_WIDE_INT mask
;
8202 /* original AND constant with all the known zero bits set */
8203 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8204 if ((mask
& mode_mask
) == mode_mask
)
8206 new_rtx
= make_compound_operation (sub
, next_code
);
8207 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0, sub_width
,
8208 1, 0, in_code
== COMPARE
);
8216 /* If the sign bit is known to be zero, replace this with an
8217 arithmetic shift. */
8218 if (have_insn_for (ASHIFTRT
, mode
)
8219 && ! have_insn_for (LSHIFTRT
, mode
)
8220 && mode_width
<= HOST_BITS_PER_WIDE_INT
8221 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8223 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8224 make_compound_operation (XEXP (x
, 0),
8236 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8237 this is a SIGN_EXTRACT. */
8238 if (CONST_INT_P (rhs
)
8239 && GET_CODE (lhs
) == ASHIFT
8240 && CONST_INT_P (XEXP (lhs
, 1))
8241 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8242 && INTVAL (XEXP (lhs
, 1)) >= 0
8243 && INTVAL (rhs
) < mode_width
)
8245 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8246 new_rtx
= make_extraction (mode
, new_rtx
,
8247 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8248 NULL_RTX
, mode_width
- INTVAL (rhs
),
8249 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8253 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8254 If so, try to merge the shifts into a SIGN_EXTEND. We could
8255 also do this for some cases of SIGN_EXTRACT, but it doesn't
8256 seem worth the effort; the case checked for occurs on Alpha. */
8259 && ! (GET_CODE (lhs
) == SUBREG
8260 && (OBJECT_P (SUBREG_REG (lhs
))))
8261 && CONST_INT_P (rhs
)
8262 && INTVAL (rhs
) >= 0
8263 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8264 && INTVAL (rhs
) < mode_width
8265 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8266 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8268 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8269 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8274 /* Call ourselves recursively on the inner expression. If we are
8275 narrowing the object and it has a different RTL code from
8276 what it originally did, do this SUBREG as a force_to_mode. */
8278 rtx inner
= SUBREG_REG (x
), simplified
;
8279 enum rtx_code subreg_code
= in_code
;
8281 /* If the SUBREG is masking of a logical right shift,
8282 make an extraction. */
8283 if (GET_CODE (inner
) == LSHIFTRT
8284 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8285 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8286 && CONST_INT_P (XEXP (inner
, 1))
8287 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8288 && subreg_lowpart_p (x
))
8290 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8291 int width
= GET_MODE_PRECISION (inner_mode
)
8292 - INTVAL (XEXP (inner
, 1));
8293 if (width
> mode_width
)
8295 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8296 width
, 1, 0, in_code
== COMPARE
);
8300 /* If in_code is COMPARE, it isn't always safe to pass it through
8301 to the recursive make_compound_operation call. */
8302 if (subreg_code
== COMPARE
8303 && (!subreg_lowpart_p (x
)
8304 || GET_CODE (inner
) == SUBREG
8305 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8306 is (const_int 0), rather than
8307 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8308 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8309 for non-equality comparisons against 0 is not equivalent
8310 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8311 || (GET_CODE (inner
) == AND
8312 && CONST_INT_P (XEXP (inner
, 1))
8313 && partial_subreg_p (x
)
8314 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8315 >= GET_MODE_BITSIZE (mode
) - 1)))
8318 tem
= make_compound_operation (inner
, subreg_code
);
8321 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8325 if (GET_CODE (tem
) != GET_CODE (inner
)
8326 && partial_subreg_p (x
)
8327 && subreg_lowpart_p (x
))
8330 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8332 /* If we have something other than a SUBREG, we might have
8333 done an expansion, so rerun ourselves. */
8334 if (GET_CODE (newer
) != SUBREG
)
8335 newer
= make_compound_operation (newer
, in_code
);
8337 /* force_to_mode can expand compounds. If it just re-expanded
8338 the compound, use gen_lowpart to convert to the desired
8340 if (rtx_equal_p (newer
, x
)
8341 /* Likewise if it re-expanded the compound only partially.
8342 This happens for SUBREG of ZERO_EXTRACT if they extract
8343 the same number of bits. */
8344 || (GET_CODE (newer
) == SUBREG
8345 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8346 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8347 && GET_CODE (inner
) == AND
8348 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8349 return gen_lowpart (GET_MODE (x
), tem
);
8364 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8365 *next_code_ptr
= next_code
;
8369 /* Look at the expression rooted at X. Look for expressions
8370 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8371 Form these expressions.
8373 Return the new rtx, usually just X.
8375 Also, for machines like the VAX that don't have logical shift insns,
8376 try to convert logical to arithmetic shift operations in cases where
8377 they are equivalent. This undoes the canonicalizations to logical
8378 shifts done elsewhere.
8380 We try, as much as possible, to re-use rtl expressions to save memory.
8382 IN_CODE says what kind of expression we are processing. Normally, it is
8383 SET. In a memory address it is MEM. When processing the arguments of
8384 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8385 precisely it is an equality comparison against zero. */
8388 make_compound_operation (rtx x
, enum rtx_code in_code
)
8390 enum rtx_code code
= GET_CODE (x
);
8393 enum rtx_code next_code
;
8396 /* Select the code to be used in recursive calls. Once we are inside an
8397 address, we stay there. If we have a comparison, set to COMPARE,
8398 but once inside, go back to our default of SET. */
8400 next_code
= (code
== MEM
? MEM
8401 : ((code
== COMPARE
|| COMPARISON_P (x
))
8402 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8403 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8405 scalar_int_mode mode
;
8406 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8408 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8412 code
= GET_CODE (x
);
8415 /* Now recursively process each operand of this operation. We need to
8416 handle ZERO_EXTEND specially so that we don't lose track of the
8418 if (code
== ZERO_EXTEND
)
8420 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8421 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8422 new_rtx
, GET_MODE (XEXP (x
, 0)));
8425 SUBST (XEXP (x
, 0), new_rtx
);
8429 fmt
= GET_RTX_FORMAT (code
);
8430 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8433 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8434 SUBST (XEXP (x
, i
), new_rtx
);
8436 else if (fmt
[i
] == 'E')
8437 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8439 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8440 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8443 maybe_swap_commutative_operands (x
);
8447 /* Given M see if it is a value that would select a field of bits
8448 within an item, but not the entire word. Return -1 if not.
8449 Otherwise, return the starting position of the field, where 0 is the
8452 *PLEN is set to the length of the field. */
8455 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8457 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8458 int pos
= m
? ctz_hwi (m
) : -1;
8462 /* Now shift off the low-order zero bits and see if we have a
8463 power of two minus 1. */
8464 len
= exact_log2 ((m
>> pos
) + 1);
8473 /* If X refers to a register that equals REG in value, replace these
8474 references with REG. */
8476 canon_reg_for_combine (rtx x
, rtx reg
)
8483 enum rtx_code code
= GET_CODE (x
);
8484 switch (GET_RTX_CLASS (code
))
8487 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8488 if (op0
!= XEXP (x
, 0))
8489 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8494 case RTX_COMM_ARITH
:
8495 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8496 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8497 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8498 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8502 case RTX_COMM_COMPARE
:
8503 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8504 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8505 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8506 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8507 GET_MODE (op0
), op0
, op1
);
8511 case RTX_BITFIELD_OPS
:
8512 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8513 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8514 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8515 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8516 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8517 GET_MODE (op0
), op0
, op1
, op2
);
8523 if (rtx_equal_p (get_last_value (reg
), x
)
8524 || rtx_equal_p (reg
, get_last_value (x
)))
8533 fmt
= GET_RTX_FORMAT (code
);
8535 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8538 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8539 if (op
!= XEXP (x
, i
))
8549 else if (fmt
[i
] == 'E')
8552 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8554 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8555 if (op
!= XVECEXP (x
, i
, j
))
8562 XVECEXP (x
, i
, j
) = op
;
8573 /* Return X converted to MODE. If the value is already truncated to
8574 MODE we can just return a subreg even though in the general case we
8575 would need an explicit truncation. */
8578 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8580 if (!CONST_INT_P (x
)
8581 && partial_subreg_p (mode
, GET_MODE (x
))
8582 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8583 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8585 /* Bit-cast X into an integer mode. */
8586 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8587 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8588 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8592 return gen_lowpart (mode
, x
);
8595 /* See if X can be simplified knowing that we will only refer to it in
8596 MODE and will only refer to those bits that are nonzero in MASK.
8597 If other bits are being computed or if masking operations are done
8598 that select a superset of the bits in MASK, they can sometimes be
8601 Return a possibly simplified expression, but always convert X to
8602 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8604 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8605 are all off in X. This is used when X will be complemented, by either
8606 NOT, NEG, or XOR. */
8609 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8612 enum rtx_code code
= GET_CODE (x
);
8613 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8614 machine_mode op_mode
;
8615 unsigned HOST_WIDE_INT nonzero
;
8617 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8618 code below will do the wrong thing since the mode of such an
8619 expression is VOIDmode.
8621 Also do nothing if X is a CLOBBER; this can happen if X was
8622 the return value from a call to gen_lowpart. */
8623 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8626 /* We want to perform the operation in its present mode unless we know
8627 that the operation is valid in MODE, in which case we do the operation
8629 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8630 && have_insn_for (code
, mode
))
8631 ? mode
: GET_MODE (x
));
8633 /* It is not valid to do a right-shift in a narrower mode
8634 than the one it came in with. */
8635 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8636 && partial_subreg_p (mode
, GET_MODE (x
)))
8637 op_mode
= GET_MODE (x
);
8639 /* Truncate MASK to fit OP_MODE. */
8641 mask
&= GET_MODE_MASK (op_mode
);
8643 /* Determine what bits of X are guaranteed to be (non)zero. */
8644 nonzero
= nonzero_bits (x
, mode
);
8646 /* If none of the bits in X are needed, return a zero. */
8647 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8650 /* If X is a CONST_INT, return a new one. Do this here since the
8651 test below will fail. */
8652 if (CONST_INT_P (x
))
8654 if (SCALAR_INT_MODE_P (mode
))
8655 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8658 x
= GEN_INT (INTVAL (x
) & mask
);
8659 return gen_lowpart_common (mode
, x
);
8663 /* If X is narrower than MODE and we want all the bits in X's mode, just
8664 get X in the proper mode. */
8665 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8666 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8667 return gen_lowpart (mode
, x
);
8669 /* We can ignore the effect of a SUBREG if it narrows the mode or
8670 if the constant masks to zero all the bits the mode doesn't have. */
8671 if (GET_CODE (x
) == SUBREG
8672 && subreg_lowpart_p (x
)
8673 && (partial_subreg_p (x
)
8675 & GET_MODE_MASK (GET_MODE (x
))
8676 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))) == 0))
8677 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8679 scalar_int_mode int_mode
, xmode
;
8680 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8681 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8682 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8684 return force_int_to_mode (x
, int_mode
, xmode
,
8685 as_a
<scalar_int_mode
> (op_mode
),
8688 return gen_lowpart_or_truncate (mode
, x
);
8691 /* Subroutine of force_to_mode that handles cases in which both X and
8692 the result are scalar integers. MODE is the mode of the result,
8693 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8694 is preferred for simplified versions of X. The other arguments
8695 are as for force_to_mode. */
8698 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8699 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8702 enum rtx_code code
= GET_CODE (x
);
8703 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8704 unsigned HOST_WIDE_INT fuller_mask
;
8706 poly_int64 const_op0
;
8708 /* When we have an arithmetic operation, or a shift whose count we
8709 do not know, we need to assume that all bits up to the highest-order
8710 bit in MASK will be needed. This is how we form such a mask. */
8711 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8712 fuller_mask
= HOST_WIDE_INT_M1U
;
8714 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8720 /* If X is a (clobber (const_int)), return it since we know we are
8721 generating something that won't match. */
8728 x
= expand_compound_operation (x
);
8729 if (GET_CODE (x
) != code
)
8730 return force_to_mode (x
, mode
, mask
, next_select
);
8734 /* Similarly for a truncate. */
8735 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8738 /* If this is an AND with a constant, convert it into an AND
8739 whose constant is the AND of that constant with MASK. If it
8740 remains an AND of MASK, delete it since it is redundant. */
8742 if (CONST_INT_P (XEXP (x
, 1)))
8744 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8745 mask
& INTVAL (XEXP (x
, 1)));
8748 /* If X is still an AND, see if it is an AND with a mask that
8749 is just some low-order bits. If so, and it is MASK, we don't
8752 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8753 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8756 /* If it remains an AND, try making another AND with the bits
8757 in the mode mask that aren't in MASK turned on. If the
8758 constant in the AND is wide enough, this might make a
8759 cheaper constant. */
8761 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8762 && GET_MODE_MASK (xmode
) != mask
8763 && HWI_COMPUTABLE_MODE_P (xmode
))
8765 unsigned HOST_WIDE_INT cval
8766 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8769 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8770 gen_int_mode (cval
, xmode
));
8771 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8772 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8782 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8783 low-order bits (as in an alignment operation) and FOO is already
8784 aligned to that boundary, mask C1 to that boundary as well.
8785 This may eliminate that PLUS and, later, the AND. */
8788 unsigned int width
= GET_MODE_PRECISION (mode
);
8789 unsigned HOST_WIDE_INT smask
= mask
;
8791 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8792 number, sign extend it. */
8794 if (width
< HOST_BITS_PER_WIDE_INT
8795 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8796 smask
|= HOST_WIDE_INT_M1U
<< width
;
8798 if (CONST_INT_P (XEXP (x
, 1))
8799 && pow2p_hwi (- smask
)
8800 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8801 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8802 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8803 (INTVAL (XEXP (x
, 1)) & smask
)),
8804 mode
, smask
, next_select
);
8810 /* Substituting into the operands of a widening MULT is not likely to
8811 create RTL matching a machine insn. */
8813 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8814 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8815 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8816 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8817 && REG_P (XEXP (XEXP (x
, 0), 0))
8818 && REG_P (XEXP (XEXP (x
, 1), 0)))
8819 return gen_lowpart_or_truncate (mode
, x
);
8821 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8822 most significant bit in MASK since carries from those bits will
8823 affect the bits we are interested in. */
8828 /* If X is (minus C Y) where C's least set bit is larger than any bit
8829 in the mask, then we may replace with (neg Y). */
8830 if (poly_int_rtx_p (XEXP (x
, 0), &const_op0
)
8831 && (unsigned HOST_WIDE_INT
) known_alignment (const_op0
) > mask
)
8833 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8834 return force_to_mode (x
, mode
, mask
, next_select
);
8837 /* Similarly, if C contains every bit in the fuller_mask, then we may
8838 replace with (not Y). */
8839 if (CONST_INT_P (XEXP (x
, 0))
8840 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8842 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8843 return force_to_mode (x
, mode
, mask
, next_select
);
8851 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8852 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8853 operation which may be a bitfield extraction. Ensure that the
8854 constant we form is not wider than the mode of X. */
8856 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8857 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8858 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8859 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8860 && CONST_INT_P (XEXP (x
, 1))
8861 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8862 + floor_log2 (INTVAL (XEXP (x
, 1))))
8863 < GET_MODE_PRECISION (xmode
))
8864 && (UINTVAL (XEXP (x
, 1))
8865 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8867 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8868 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8870 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8871 XEXP (XEXP (x
, 0), 0), temp
);
8872 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8873 XEXP (XEXP (x
, 0), 1));
8874 return force_to_mode (x
, mode
, mask
, next_select
);
8878 /* For most binary operations, just propagate into the operation and
8879 change the mode if we have an operation of that mode. */
8881 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8882 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8884 /* If we ended up truncating both operands, truncate the result of the
8885 operation instead. */
8886 if (GET_CODE (op0
) == TRUNCATE
8887 && GET_CODE (op1
) == TRUNCATE
)
8889 op0
= XEXP (op0
, 0);
8890 op1
= XEXP (op1
, 0);
8893 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8894 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8896 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8898 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8904 /* For left shifts, do the same, but just for the first operand.
8905 However, we cannot do anything with shifts where we cannot
8906 guarantee that the counts are smaller than the size of the mode
8907 because such a count will have a different meaning in a
8910 if (! (CONST_INT_P (XEXP (x
, 1))
8911 && INTVAL (XEXP (x
, 1)) >= 0
8912 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8913 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8914 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8915 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8918 /* If the shift count is a constant and we can do arithmetic in
8919 the mode of the shift, refine which bits we need. Otherwise, use the
8920 conservative form of the mask. */
8921 if (CONST_INT_P (XEXP (x
, 1))
8922 && INTVAL (XEXP (x
, 1)) >= 0
8923 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8924 && HWI_COMPUTABLE_MODE_P (op_mode
))
8925 mask
>>= INTVAL (XEXP (x
, 1));
8929 op0
= gen_lowpart_or_truncate (op_mode
,
8930 force_to_mode (XEXP (x
, 0), mode
,
8931 mask
, next_select
));
8933 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
8935 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8941 /* Here we can only do something if the shift count is a constant,
8942 this shift constant is valid for the host, and we can do arithmetic
8945 if (CONST_INT_P (XEXP (x
, 1))
8946 && INTVAL (XEXP (x
, 1)) >= 0
8947 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8948 && HWI_COMPUTABLE_MODE_P (op_mode
))
8950 rtx inner
= XEXP (x
, 0);
8951 unsigned HOST_WIDE_INT inner_mask
;
8953 /* Select the mask of the bits we need for the shift operand. */
8954 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8956 /* We can only change the mode of the shift if we can do arithmetic
8957 in the mode of the shift and INNER_MASK is no wider than the
8958 width of X's mode. */
8959 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
8962 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8964 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
8966 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8971 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8972 shift and AND produces only copies of the sign bit (C2 is one less
8973 than a power of two), we can do this with just a shift. */
8975 if (GET_CODE (x
) == LSHIFTRT
8976 && CONST_INT_P (XEXP (x
, 1))
8977 /* The shift puts one of the sign bit copies in the least significant
8979 && ((INTVAL (XEXP (x
, 1))
8980 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8981 >= GET_MODE_PRECISION (xmode
))
8982 && pow2p_hwi (mask
+ 1)
8983 /* Number of bits left after the shift must be more than the mask
8985 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8986 <= GET_MODE_PRECISION (xmode
))
8987 /* Must be more sign bit copies than the mask needs. */
8988 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8989 >= exact_log2 (mask
+ 1)))
8991 int nbits
= GET_MODE_PRECISION (xmode
) - exact_log2 (mask
+ 1);
8992 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
8993 gen_int_shift_amount (xmode
, nbits
));
8998 /* If we are just looking for the sign bit, we don't need this shift at
8999 all, even if it has a variable count. */
9000 if (val_signbit_p (xmode
, mask
))
9001 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9003 /* If this is a shift by a constant, get a mask that contains those bits
9004 that are not copies of the sign bit. We then have two cases: If
9005 MASK only includes those bits, this can be a logical shift, which may
9006 allow simplifications. If MASK is a single-bit field not within
9007 those bits, we are requesting a copy of the sign bit and hence can
9008 shift the sign bit to the appropriate location. */
9010 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
9011 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
9013 unsigned HOST_WIDE_INT nonzero
;
9016 /* If the considered data is wider than HOST_WIDE_INT, we can't
9017 represent a mask for all its bits in a single scalar.
9018 But we only care about the lower bits, so calculate these. */
9020 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
9022 nonzero
= HOST_WIDE_INT_M1U
;
9024 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9025 is the number of bits a full-width mask would have set.
9026 We need only shift if these are fewer than nonzero can
9027 hold. If not, we must keep all bits set in nonzero. */
9029 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
9030 < HOST_BITS_PER_WIDE_INT
)
9031 nonzero
>>= INTVAL (XEXP (x
, 1))
9032 + HOST_BITS_PER_WIDE_INT
9033 - GET_MODE_PRECISION (xmode
);
9037 nonzero
= GET_MODE_MASK (xmode
);
9038 nonzero
>>= INTVAL (XEXP (x
, 1));
9041 if ((mask
& ~nonzero
) == 0)
9043 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9044 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9045 if (GET_CODE (x
) != ASHIFTRT
)
9046 return force_to_mode (x
, mode
, mask
, next_select
);
9049 else if ((i
= exact_log2 (mask
)) >= 0)
9051 x
= simplify_shift_const
9052 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9053 GET_MODE_PRECISION (xmode
) - 1 - i
);
9055 if (GET_CODE (x
) != ASHIFTRT
)
9056 return force_to_mode (x
, mode
, mask
, next_select
);
9060 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9061 even if the shift count isn't a constant. */
9063 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9067 /* If this is a zero- or sign-extension operation that just affects bits
9068 we don't care about, remove it. Be sure the call above returned
9069 something that is still a shift. */
9071 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9072 && CONST_INT_P (XEXP (x
, 1))
9073 && INTVAL (XEXP (x
, 1)) >= 0
9074 && (INTVAL (XEXP (x
, 1))
9075 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9076 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9077 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9078 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9085 /* If the shift count is constant and we can do computations
9086 in the mode of X, compute where the bits we care about are.
9087 Otherwise, we can't do anything. Don't change the mode of
9088 the shift or propagate MODE into the shift, though. */
9089 if (CONST_INT_P (XEXP (x
, 1))
9090 && INTVAL (XEXP (x
, 1)) >= 0)
9092 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9093 xmode
, gen_int_mode (mask
, xmode
),
9095 if (temp
&& CONST_INT_P (temp
))
9096 x
= simplify_gen_binary (code
, xmode
,
9097 force_to_mode (XEXP (x
, 0), xmode
,
9098 INTVAL (temp
), next_select
),
9104 /* If we just want the low-order bit, the NEG isn't needed since it
9105 won't change the low-order bit. */
9107 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9109 /* We need any bits less significant than the most significant bit in
9110 MASK since carries from those bits will affect the bits we are
9116 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9117 same as the XOR case above. Ensure that the constant we form is not
9118 wider than the mode of X. */
9120 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9121 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9122 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9123 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9124 < GET_MODE_PRECISION (xmode
))
9125 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9127 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9128 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9129 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9130 temp
, XEXP (XEXP (x
, 0), 1));
9132 return force_to_mode (x
, mode
, mask
, next_select
);
9135 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9136 use the full mask inside the NOT. */
9140 op0
= gen_lowpart_or_truncate (op_mode
,
9141 force_to_mode (XEXP (x
, 0), mode
, mask
,
9143 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9145 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9151 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9152 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9153 which is equal to STORE_FLAG_VALUE. */
9154 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9155 && XEXP (x
, 1) == const0_rtx
9156 && GET_MODE (XEXP (x
, 0)) == mode
9157 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9158 && (nonzero_bits (XEXP (x
, 0), mode
)
9159 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9160 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9165 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9166 written in a narrower mode. We play it safe and do not do so. */
9168 op0
= gen_lowpart_or_truncate (xmode
,
9169 force_to_mode (XEXP (x
, 1), mode
,
9170 mask
, next_select
));
9171 op1
= gen_lowpart_or_truncate (xmode
,
9172 force_to_mode (XEXP (x
, 2), mode
,
9173 mask
, next_select
));
9174 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9175 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9176 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9184 /* Ensure we return a value of the proper mode. */
9185 return gen_lowpart_or_truncate (mode
, x
);
9188 /* Return nonzero if X is an expression that has one of two values depending on
9189 whether some other value is zero or nonzero. In that case, we return the
9190 value that is being tested, *PTRUE is set to the value if the rtx being
9191 returned has a nonzero value, and *PFALSE is set to the other alternative.
9193 If we return zero, we set *PTRUE and *PFALSE to X. */
9196 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9198 machine_mode mode
= GET_MODE (x
);
9199 enum rtx_code code
= GET_CODE (x
);
9200 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9201 unsigned HOST_WIDE_INT nz
;
9202 scalar_int_mode int_mode
;
9204 /* If we are comparing a value against zero, we are done. */
9205 if ((code
== NE
|| code
== EQ
)
9206 && XEXP (x
, 1) == const0_rtx
)
9208 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9209 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9213 /* If this is a unary operation whose operand has one of two values, apply
9214 our opcode to compute those values. */
9215 else if (UNARY_P (x
)
9216 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9218 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9219 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9220 GET_MODE (XEXP (x
, 0)));
9224 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9225 make can't possibly match and would suppress other optimizations. */
9226 else if (code
== COMPARE
)
9229 /* If this is a binary operation, see if either side has only one of two
9230 values. If either one does or if both do and they are conditional on
9231 the same value, compute the new true and false values. */
9232 else if (BINARY_P (x
))
9234 rtx op0
= XEXP (x
, 0);
9235 rtx op1
= XEXP (x
, 1);
9236 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9237 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9239 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9240 && (REG_P (op0
) || REG_P (op1
)))
9242 /* Try to enable a simplification by undoing work done by
9243 if_then_else_cond if it converted a REG into something more
9248 true0
= false0
= op0
;
9253 true1
= false1
= op1
;
9257 if ((cond0
!= 0 || cond1
!= 0)
9258 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9260 /* If if_then_else_cond returned zero, then true/false are the
9261 same rtl. We must copy one of them to prevent invalid rtl
9264 true0
= copy_rtx (true0
);
9265 else if (cond1
== 0)
9266 true1
= copy_rtx (true1
);
9268 if (COMPARISON_P (x
))
9270 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9272 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9277 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9278 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9281 return cond0
? cond0
: cond1
;
9284 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9285 operands is zero when the other is nonzero, and vice-versa,
9286 and STORE_FLAG_VALUE is 1 or -1. */
9288 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9289 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9291 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9293 rtx op0
= XEXP (XEXP (x
, 0), 1);
9294 rtx op1
= XEXP (XEXP (x
, 1), 1);
9296 cond0
= XEXP (XEXP (x
, 0), 0);
9297 cond1
= XEXP (XEXP (x
, 1), 0);
9299 if (COMPARISON_P (cond0
)
9300 && COMPARISON_P (cond1
)
9301 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9302 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9303 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9304 || ((swap_condition (GET_CODE (cond0
))
9305 == reversed_comparison_code (cond1
, NULL
))
9306 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9307 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9308 && ! side_effects_p (x
))
9310 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9311 *pfalse
= simplify_gen_binary (MULT
, mode
,
9313 ? simplify_gen_unary (NEG
, mode
,
9321 /* Similarly for MULT, AND and UMIN, except that for these the result
9323 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9324 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9325 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9327 cond0
= XEXP (XEXP (x
, 0), 0);
9328 cond1
= XEXP (XEXP (x
, 1), 0);
9330 if (COMPARISON_P (cond0
)
9331 && COMPARISON_P (cond1
)
9332 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9333 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9334 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9335 || ((swap_condition (GET_CODE (cond0
))
9336 == reversed_comparison_code (cond1
, NULL
))
9337 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9338 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9339 && ! side_effects_p (x
))
9341 *ptrue
= *pfalse
= const0_rtx
;
9347 else if (code
== IF_THEN_ELSE
)
9349 /* If we have IF_THEN_ELSE already, extract the condition and
9350 canonicalize it if it is NE or EQ. */
9351 cond0
= XEXP (x
, 0);
9352 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9353 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9354 return XEXP (cond0
, 0);
9355 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9357 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9358 return XEXP (cond0
, 0);
9364 /* If X is a SUBREG, we can narrow both the true and false values
9365 if the inner expression, if there is a condition. */
9366 else if (code
== SUBREG
9367 && (cond0
= if_then_else_cond (SUBREG_REG (x
), &true0
,
9370 true0
= simplify_gen_subreg (mode
, true0
,
9371 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9372 false0
= simplify_gen_subreg (mode
, false0
,
9373 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9374 if (true0
&& false0
)
9382 /* If X is a constant, this isn't special and will cause confusions
9383 if we treat it as such. Likewise if it is equivalent to a constant. */
9384 else if (CONSTANT_P (x
)
9385 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9388 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9389 will be least confusing to the rest of the compiler. */
9390 else if (mode
== BImode
)
9392 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9396 /* If X is known to be either 0 or -1, those are the true and
9397 false values when testing X. */
9398 else if (x
== constm1_rtx
|| x
== const0_rtx
9399 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9400 && (num_sign_bit_copies (x
, int_mode
)
9401 == GET_MODE_PRECISION (int_mode
))))
9403 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9407 /* Likewise for 0 or a single bit. */
9408 else if (HWI_COMPUTABLE_MODE_P (mode
)
9409 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9411 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9415 /* Otherwise fail; show no condition with true and false values the same. */
9416 *ptrue
= *pfalse
= x
;
9420 /* Return the value of expression X given the fact that condition COND
9421 is known to be true when applied to REG as its first operand and VAL
9422 as its second. X is known to not be shared and so can be modified in
9425 We only handle the simplest cases, and specifically those cases that
9426 arise with IF_THEN_ELSE expressions. */
9429 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9431 enum rtx_code code
= GET_CODE (x
);
9435 if (side_effects_p (x
))
9438 /* If either operand of the condition is a floating point value,
9439 then we have to avoid collapsing an EQ comparison. */
9441 && rtx_equal_p (x
, reg
)
9442 && ! FLOAT_MODE_P (GET_MODE (x
))
9443 && ! FLOAT_MODE_P (GET_MODE (val
)))
9446 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9449 /* If X is (abs REG) and we know something about REG's relationship
9450 with zero, we may be able to simplify this. */
9452 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9455 case GE
: case GT
: case EQ
:
9458 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9460 GET_MODE (XEXP (x
, 0)));
9465 /* The only other cases we handle are MIN, MAX, and comparisons if the
9466 operands are the same as REG and VAL. */
9468 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9470 if (rtx_equal_p (XEXP (x
, 0), val
))
9472 std::swap (val
, reg
);
9473 cond
= swap_condition (cond
);
9476 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9478 if (COMPARISON_P (x
))
9480 if (comparison_dominates_p (cond
, code
))
9481 return const_true_rtx
;
9483 code
= reversed_comparison_code (x
, NULL
);
9485 && comparison_dominates_p (cond
, code
))
9490 else if (code
== SMAX
|| code
== SMIN
9491 || code
== UMIN
|| code
== UMAX
)
9493 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9495 /* Do not reverse the condition when it is NE or EQ.
9496 This is because we cannot conclude anything about
9497 the value of 'SMAX (x, y)' when x is not equal to y,
9498 but we can when x equals y. */
9499 if ((code
== SMAX
|| code
== UMAX
)
9500 && ! (cond
== EQ
|| cond
== NE
))
9501 cond
= reverse_condition (cond
);
9506 return unsignedp
? x
: XEXP (x
, 1);
9508 return unsignedp
? x
: XEXP (x
, 0);
9510 return unsignedp
? XEXP (x
, 1) : x
;
9512 return unsignedp
? XEXP (x
, 0) : x
;
9519 else if (code
== SUBREG
)
9521 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9522 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9524 if (SUBREG_REG (x
) != r
)
9526 /* We must simplify subreg here, before we lose track of the
9527 original inner_mode. */
9528 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9529 inner_mode
, SUBREG_BYTE (x
));
9533 SUBST (SUBREG_REG (x
), r
);
9538 /* We don't have to handle SIGN_EXTEND here, because even in the
9539 case of replacing something with a modeless CONST_INT, a
9540 CONST_INT is already (supposed to be) a valid sign extension for
9541 its narrower mode, which implies it's already properly
9542 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9543 story is different. */
9544 else if (code
== ZERO_EXTEND
)
9546 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9547 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9549 if (XEXP (x
, 0) != r
)
9551 /* We must simplify the zero_extend here, before we lose
9552 track of the original inner_mode. */
9553 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9558 SUBST (XEXP (x
, 0), r
);
9564 fmt
= GET_RTX_FORMAT (code
);
9565 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9568 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9569 else if (fmt
[i
] == 'E')
9570 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9571 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9578 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9579 assignment as a field assignment. */
9582 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9584 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9586 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9588 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9590 x
= adjust_address_nv (x
, GET_MODE (y
),
9591 byte_lowpart_offset (GET_MODE (y
),
9595 if (x
== y
|| rtx_equal_p (x
, y
))
9598 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9601 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9602 Note that all SUBREGs of MEM are paradoxical; otherwise they
9603 would have been rewritten. */
9604 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9605 && MEM_P (SUBREG_REG (y
))
9606 && rtx_equal_p (SUBREG_REG (y
),
9607 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9610 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9611 && MEM_P (SUBREG_REG (x
))
9612 && rtx_equal_p (SUBREG_REG (x
),
9613 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9616 /* We used to see if get_last_value of X and Y were the same but that's
9617 not correct. In one direction, we'll cause the assignment to have
9618 the wrong destination and in the case, we'll import a register into this
9619 insn that might have already have been dead. So fail if none of the
9620 above cases are true. */
9624 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9625 Return that assignment if so.
9627 We only handle the most common cases. */
9630 make_field_assignment (rtx x
)
9632 rtx dest
= SET_DEST (x
);
9633 rtx src
= SET_SRC (x
);
9638 unsigned HOST_WIDE_INT len
;
9641 /* All the rules in this function are specific to scalar integers. */
9642 scalar_int_mode mode
;
9643 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9646 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9647 a clear of a one-bit field. We will have changed it to
9648 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9651 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9652 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9653 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9654 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9656 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9659 return gen_rtx_SET (assign
, const0_rtx
);
9663 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9664 && subreg_lowpart_p (XEXP (src
, 0))
9665 && partial_subreg_p (XEXP (src
, 0))
9666 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9667 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9668 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9669 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9671 assign
= make_extraction (VOIDmode
, dest
, 0,
9672 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9675 return gen_rtx_SET (assign
, const0_rtx
);
9679 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9681 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9682 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9683 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9685 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9688 return gen_rtx_SET (assign
, const1_rtx
);
9692 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9693 SRC is an AND with all bits of that field set, then we can discard
9695 if (GET_CODE (dest
) == ZERO_EXTRACT
9696 && CONST_INT_P (XEXP (dest
, 1))
9697 && GET_CODE (src
) == AND
9698 && CONST_INT_P (XEXP (src
, 1)))
9700 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9701 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9702 unsigned HOST_WIDE_INT ze_mask
;
9704 if (width
>= HOST_BITS_PER_WIDE_INT
)
9707 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9709 /* Complete overlap. We can remove the source AND. */
9710 if ((and_mask
& ze_mask
) == ze_mask
)
9711 return gen_rtx_SET (dest
, XEXP (src
, 0));
9713 /* Partial overlap. We can reduce the source AND. */
9714 if ((and_mask
& ze_mask
) != and_mask
)
9716 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9717 gen_int_mode (and_mask
& ze_mask
, mode
));
9718 return gen_rtx_SET (dest
, src
);
9722 /* The other case we handle is assignments into a constant-position
9723 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9724 a mask that has all one bits except for a group of zero bits and
9725 OTHER is known to have zeros where C1 has ones, this is such an
9726 assignment. Compute the position and length from C1. Shift OTHER
9727 to the appropriate position, force it to the required mode, and
9728 make the extraction. Check for the AND in both operands. */
9730 /* One or more SUBREGs might obscure the constant-position field
9731 assignment. The first one we are likely to encounter is an outer
9732 narrowing SUBREG, which we can just strip for the purposes of
9733 identifying the constant-field assignment. */
9734 scalar_int_mode src_mode
= mode
;
9735 if (GET_CODE (src
) == SUBREG
9736 && subreg_lowpart_p (src
)
9737 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9738 src
= SUBREG_REG (src
);
9740 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9743 rhs
= expand_compound_operation (XEXP (src
, 0));
9744 lhs
= expand_compound_operation (XEXP (src
, 1));
9746 if (GET_CODE (rhs
) == AND
9747 && CONST_INT_P (XEXP (rhs
, 1))
9748 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9749 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9750 /* The second SUBREG that might get in the way is a paradoxical
9751 SUBREG around the first operand of the AND. We want to
9752 pretend the operand is as wide as the destination here. We
9753 do this by adjusting the MEM to wider mode for the sole
9754 purpose of the call to rtx_equal_for_field_assignment_p. Also
9755 note this trick only works for MEMs. */
9756 else if (GET_CODE (rhs
) == AND
9757 && paradoxical_subreg_p (XEXP (rhs
, 0))
9758 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9759 && CONST_INT_P (XEXP (rhs
, 1))
9760 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9762 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9763 else if (GET_CODE (lhs
) == AND
9764 && CONST_INT_P (XEXP (lhs
, 1))
9765 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9766 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9767 /* The second SUBREG that might get in the way is a paradoxical
9768 SUBREG around the first operand of the AND. We want to
9769 pretend the operand is as wide as the destination here. We
9770 do this by adjusting the MEM to wider mode for the sole
9771 purpose of the call to rtx_equal_for_field_assignment_p. Also
9772 note this trick only works for MEMs. */
9773 else if (GET_CODE (lhs
) == AND
9774 && paradoxical_subreg_p (XEXP (lhs
, 0))
9775 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9776 && CONST_INT_P (XEXP (lhs
, 1))
9777 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9779 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9783 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9785 || pos
+ len
> GET_MODE_PRECISION (mode
)
9786 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9787 || (c1
& nonzero_bits (other
, mode
)) != 0)
9790 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9794 /* The mode to use for the source is the mode of the assignment, or of
9795 what is inside a possible STRICT_LOW_PART. */
9796 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9797 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9799 /* Shift OTHER right POS places and make it the source, restricting it
9800 to the proper length and mode. */
9802 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9803 src_mode
, other
, pos
),
9805 src
= force_to_mode (src
, new_mode
,
9806 len
>= HOST_BITS_PER_WIDE_INT
9808 : (HOST_WIDE_INT_1U
<< len
) - 1,
9811 /* If SRC is masked by an AND that does not make a difference in
9812 the value being stored, strip it. */
9813 if (GET_CODE (assign
) == ZERO_EXTRACT
9814 && CONST_INT_P (XEXP (assign
, 1))
9815 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9816 && GET_CODE (src
) == AND
9817 && CONST_INT_P (XEXP (src
, 1))
9818 && UINTVAL (XEXP (src
, 1))
9819 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9820 src
= XEXP (src
, 0);
9822 return gen_rtx_SET (assign
, src
);
9825 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9829 apply_distributive_law (rtx x
)
9831 enum rtx_code code
= GET_CODE (x
);
9832 enum rtx_code inner_code
;
9833 rtx lhs
, rhs
, other
;
9836 /* Distributivity is not true for floating point as it can change the
9837 value. So we don't do it unless -funsafe-math-optimizations. */
9838 if (FLOAT_MODE_P (GET_MODE (x
))
9839 && ! flag_unsafe_math_optimizations
)
9842 /* The outer operation can only be one of the following: */
9843 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9844 && code
!= PLUS
&& code
!= MINUS
)
9850 /* If either operand is a primitive we can't do anything, so get out
9852 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9855 lhs
= expand_compound_operation (lhs
);
9856 rhs
= expand_compound_operation (rhs
);
9857 inner_code
= GET_CODE (lhs
);
9858 if (inner_code
!= GET_CODE (rhs
))
9861 /* See if the inner and outer operations distribute. */
9868 /* These all distribute except over PLUS. */
9869 if (code
== PLUS
|| code
== MINUS
)
9874 if (code
!= PLUS
&& code
!= MINUS
)
9879 /* This is also a multiply, so it distributes over everything. */
9882 /* This used to handle SUBREG, but this turned out to be counter-
9883 productive, since (subreg (op ...)) usually is not handled by
9884 insn patterns, and this "optimization" therefore transformed
9885 recognizable patterns into unrecognizable ones. Therefore the
9886 SUBREG case was removed from here.
9888 It is possible that distributing SUBREG over arithmetic operations
9889 leads to an intermediate result than can then be optimized further,
9890 e.g. by moving the outer SUBREG to the other side of a SET as done
9891 in simplify_set. This seems to have been the original intent of
9892 handling SUBREGs here.
9894 However, with current GCC this does not appear to actually happen,
9895 at least on major platforms. If some case is found where removing
9896 the SUBREG case here prevents follow-on optimizations, distributing
9897 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9903 /* Set LHS and RHS to the inner operands (A and B in the example
9904 above) and set OTHER to the common operand (C in the example).
9905 There is only one way to do this unless the inner operation is
9907 if (COMMUTATIVE_ARITH_P (lhs
)
9908 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9909 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9910 else if (COMMUTATIVE_ARITH_P (lhs
)
9911 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9912 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9913 else if (COMMUTATIVE_ARITH_P (lhs
)
9914 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9915 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9916 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9917 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9921 /* Form the new inner operation, seeing if it simplifies first. */
9922 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9924 /* There is one exception to the general way of distributing:
9925 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9926 if (code
== XOR
&& inner_code
== IOR
)
9929 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9932 /* We may be able to continuing distributing the result, so call
9933 ourselves recursively on the inner operation before forming the
9934 outer operation, which we return. */
9935 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9936 apply_distributive_law (tem
), other
);
9939 /* See if X is of the form (* (+ A B) C), and if so convert to
9940 (+ (* A C) (* B C)) and try to simplify.
9942 Most of the time, this results in no change. However, if some of
9943 the operands are the same or inverses of each other, simplifications
9946 For example, (and (ior A B) (not B)) can occur as the result of
9947 expanding a bit field assignment. When we apply the distributive
9948 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9949 which then simplifies to (and (A (not B))).
9951 Note that no checks happen on the validity of applying the inverse
9952 distributive law. This is pointless since we can do it in the
9953 few places where this routine is called.
9955 N is the index of the term that is decomposed (the arithmetic operation,
9956 i.e. (+ A B) in the first example above). !N is the index of the term that
9957 is distributed, i.e. of C in the first example above. */
9959 distribute_and_simplify_rtx (rtx x
, int n
)
9962 enum rtx_code outer_code
, inner_code
;
9963 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9965 /* Distributivity is not true for floating point as it can change the
9966 value. So we don't do it unless -funsafe-math-optimizations. */
9967 if (FLOAT_MODE_P (GET_MODE (x
))
9968 && ! flag_unsafe_math_optimizations
)
9971 decomposed
= XEXP (x
, n
);
9972 if (!ARITHMETIC_P (decomposed
))
9975 mode
= GET_MODE (x
);
9976 outer_code
= GET_CODE (x
);
9977 distributed
= XEXP (x
, !n
);
9979 inner_code
= GET_CODE (decomposed
);
9980 inner_op0
= XEXP (decomposed
, 0);
9981 inner_op1
= XEXP (decomposed
, 1);
9983 /* Special case (and (xor B C) (not A)), which is equivalent to
9984 (xor (ior A B) (ior A C)) */
9985 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9987 distributed
= XEXP (distributed
, 0);
9993 /* Distribute the second term. */
9994 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9995 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9999 /* Distribute the first term. */
10000 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
10001 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
10004 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
10005 new_op0
, new_op1
));
10006 if (GET_CODE (tmp
) != outer_code
10007 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
10008 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
10014 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10015 in MODE. Return an equivalent form, if different from (and VAROP
10016 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10019 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
10020 unsigned HOST_WIDE_INT constop
)
10022 unsigned HOST_WIDE_INT nonzero
;
10023 unsigned HOST_WIDE_INT orig_constop
;
10027 orig_varop
= varop
;
10028 orig_constop
= constop
;
10029 if (GET_CODE (varop
) == CLOBBER
)
10032 /* Simplify VAROP knowing that we will be only looking at some of the
10035 Note by passing in CONSTOP, we guarantee that the bits not set in
10036 CONSTOP are not significant and will never be examined. We must
10037 ensure that is the case by explicitly masking out those bits
10038 before returning. */
10039 varop
= force_to_mode (varop
, mode
, constop
, 0);
10041 /* If VAROP is a CLOBBER, we will fail so return it. */
10042 if (GET_CODE (varop
) == CLOBBER
)
10045 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10046 to VAROP and return the new constant. */
10047 if (CONST_INT_P (varop
))
10048 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10050 /* See what bits may be nonzero in VAROP. Unlike the general case of
10051 a call to nonzero_bits, here we don't care about bits outside
10054 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10056 /* Turn off all bits in the constant that are known to already be zero.
10057 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10058 which is tested below. */
10060 constop
&= nonzero
;
10062 /* If we don't have any bits left, return zero. */
10066 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10067 a power of two, we can replace this with an ASHIFT. */
10068 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10069 && (i
= exact_log2 (constop
)) >= 0)
10070 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10072 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10073 or XOR, then try to apply the distributive law. This may eliminate
10074 operations if either branch can be simplified because of the AND.
10075 It may also make some cases more complex, but those cases probably
10076 won't match a pattern either with or without this. */
10078 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10080 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10084 apply_distributive_law
10085 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10086 simplify_and_const_int (NULL_RTX
, varop_mode
,
10089 simplify_and_const_int (NULL_RTX
, varop_mode
,
10094 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10095 the AND and see if one of the operands simplifies to zero. If so, we
10096 may eliminate it. */
10098 if (GET_CODE (varop
) == PLUS
10099 && pow2p_hwi (constop
+ 1))
10103 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10104 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10105 if (o0
== const0_rtx
)
10107 if (o1
== const0_rtx
)
10111 /* Make a SUBREG if necessary. If we can't make it, fail. */
10112 varop
= gen_lowpart (mode
, varop
);
10113 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10116 /* If we are only masking insignificant bits, return VAROP. */
10117 if (constop
== nonzero
)
10120 if (varop
== orig_varop
&& constop
== orig_constop
)
10123 /* Otherwise, return an AND. */
10124 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10128 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10131 Return an equivalent form, if different from X. Otherwise, return X. If
10132 X is zero, we are to always construct the equivalent form. */
10135 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10136 unsigned HOST_WIDE_INT constop
)
10138 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10143 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10144 gen_int_mode (constop
, mode
));
10145 if (GET_MODE (x
) != mode
)
10146 x
= gen_lowpart (mode
, x
);
10150 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10151 We don't care about bits outside of those defined in MODE.
10153 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10154 a shift, AND, or zero_extract, we can do better. */
10157 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10158 scalar_int_mode mode
,
10159 unsigned HOST_WIDE_INT
*nonzero
)
10162 reg_stat_type
*rsp
;
10164 /* If X is a register whose nonzero bits value is current, use it.
10165 Otherwise, if X is a register whose value we can find, use that
10166 value. Otherwise, use the previously-computed global nonzero bits
10167 for this register. */
10169 rsp
= ®_stat
[REGNO (x
)];
10170 if (rsp
->last_set_value
!= 0
10171 && (rsp
->last_set_mode
== mode
10172 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10173 && GET_MODE_CLASS (mode
) == MODE_INT
))
10174 && ((rsp
->last_set_label
>= label_tick_ebb_start
10175 && rsp
->last_set_label
< label_tick
)
10176 || (rsp
->last_set_label
== label_tick
10177 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10178 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10179 && REGNO (x
) < reg_n_sets_max
10180 && REG_N_SETS (REGNO (x
)) == 1
10181 && !REGNO_REG_SET_P
10182 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10185 /* Note that, even if the precision of last_set_mode is lower than that
10186 of mode, record_value_for_reg invoked nonzero_bits on the register
10187 with nonzero_bits_mode (because last_set_mode is necessarily integral
10188 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10189 are all valid, hence in mode too since nonzero_bits_mode is defined
10190 to the largest HWI_COMPUTABLE_MODE_P mode. */
10191 *nonzero
&= rsp
->last_set_nonzero_bits
;
10195 tem
= get_last_value (x
);
10198 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10199 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10204 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10206 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10208 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10209 /* We don't know anything about the upper bits. */
10210 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10218 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10219 end of X that are known to be equal to the sign bit. X will be used
10220 in mode MODE; the returned value will always be between 1 and the
10221 number of bits in MODE. */
10224 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10225 scalar_int_mode mode
,
10226 unsigned int *result
)
10229 reg_stat_type
*rsp
;
10231 rsp
= ®_stat
[REGNO (x
)];
10232 if (rsp
->last_set_value
!= 0
10233 && rsp
->last_set_mode
== mode
10234 && ((rsp
->last_set_label
>= label_tick_ebb_start
10235 && rsp
->last_set_label
< label_tick
)
10236 || (rsp
->last_set_label
== label_tick
10237 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10238 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10239 && REGNO (x
) < reg_n_sets_max
10240 && REG_N_SETS (REGNO (x
)) == 1
10241 && !REGNO_REG_SET_P
10242 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10245 *result
= rsp
->last_set_sign_bit_copies
;
10249 tem
= get_last_value (x
);
10253 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10254 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10255 *result
= rsp
->sign_bit_copies
;
10260 /* Return the number of "extended" bits there are in X, when interpreted
10261 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10262 unsigned quantities, this is the number of high-order zero bits.
10263 For signed quantities, this is the number of copies of the sign bit
10264 minus 1. In both case, this function returns the number of "spare"
10265 bits. For example, if two quantities for which this function returns
10266 at least 1 are added, the addition is known not to overflow.
10268 This function will always return 0 unless called during combine, which
10269 implies that it must be called from a define_split. */
10272 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10274 if (nonzero_sign_valid
== 0)
10277 scalar_int_mode int_mode
;
10279 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10280 && HWI_COMPUTABLE_MODE_P (int_mode
)
10281 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10282 - floor_log2 (nonzero_bits (x
, int_mode
)))
10284 : num_sign_bit_copies (x
, mode
) - 1);
10287 /* This function is called from `simplify_shift_const' to merge two
10288 outer operations. Specifically, we have already found that we need
10289 to perform operation *POP0 with constant *PCONST0 at the outermost
10290 position. We would now like to also perform OP1 with constant CONST1
10291 (with *POP0 being done last).
10293 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10294 the resulting operation. *PCOMP_P is set to 1 if we would need to
10295 complement the innermost operand, otherwise it is unchanged.
10297 MODE is the mode in which the operation will be done. No bits outside
10298 the width of this mode matter. It is assumed that the width of this mode
10299 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10301 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10302 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10303 result is simply *PCONST0.
10305 If the resulting operation cannot be expressed as one operation, we
10306 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10309 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10311 enum rtx_code op0
= *pop0
;
10312 HOST_WIDE_INT const0
= *pconst0
;
10314 const0
&= GET_MODE_MASK (mode
);
10315 const1
&= GET_MODE_MASK (mode
);
10317 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10321 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10324 if (op1
== UNKNOWN
|| op0
== SET
)
10327 else if (op0
== UNKNOWN
)
10328 op0
= op1
, const0
= const1
;
10330 else if (op0
== op1
)
10354 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10355 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10358 /* If the two constants aren't the same, we can't do anything. The
10359 remaining six cases can all be done. */
10360 else if (const0
!= const1
)
10368 /* (a & b) | b == b */
10370 else /* op1 == XOR */
10371 /* (a ^ b) | b == a | b */
10377 /* (a & b) ^ b == (~a) & b */
10378 op0
= AND
, *pcomp_p
= 1;
10379 else /* op1 == IOR */
10380 /* (a | b) ^ b == a & ~b */
10381 op0
= AND
, const0
= ~const0
;
10386 /* (a | b) & b == b */
10388 else /* op1 == XOR */
10389 /* (a ^ b) & b) == (~a) & b */
10396 /* Check for NO-OP cases. */
10397 const0
&= GET_MODE_MASK (mode
);
10399 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10401 else if (const0
== 0 && op0
== AND
)
10403 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10409 /* ??? Slightly redundant with the above mask, but not entirely.
10410 Moving this above means we'd have to sign-extend the mode mask
10411 for the final test. */
10412 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10413 *pconst0
= trunc_int_for_mode (const0
, mode
);
10418 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10419 the shift in. The original shift operation CODE is performed on OP in
10420 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10421 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10422 result of the shift is subject to operation OUTER_CODE with operand
10425 static scalar_int_mode
10426 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10427 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10428 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10430 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10432 /* In general we can't perform in wider mode for right shift and rotate. */
10436 /* We can still widen if the bits brought in from the left are identical
10437 to the sign bit of ORIG_MODE. */
10438 if (num_sign_bit_copies (op
, mode
)
10439 > (unsigned) (GET_MODE_PRECISION (mode
)
10440 - GET_MODE_PRECISION (orig_mode
)))
10445 /* Similarly here but with zero bits. */
10446 if (HWI_COMPUTABLE_MODE_P (mode
)
10447 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10450 /* We can also widen if the bits brought in will be masked off. This
10451 operation is performed in ORIG_MODE. */
10452 if (outer_code
== AND
)
10454 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10457 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10466 gcc_unreachable ();
10473 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10474 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10475 if we cannot simplify it. Otherwise, return a simplified value.
10477 The shift is normally computed in the widest mode we find in VAROP, as
10478 long as it isn't a different number of words than RESULT_MODE. Exceptions
10479 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10482 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10483 rtx varop
, int orig_count
)
10485 enum rtx_code orig_code
= code
;
10486 rtx orig_varop
= varop
;
10488 machine_mode mode
= result_mode
;
10489 machine_mode shift_mode
;
10490 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10491 /* We form (outer_op (code varop count) (outer_const)). */
10492 enum rtx_code outer_op
= UNKNOWN
;
10493 HOST_WIDE_INT outer_const
= 0;
10494 int complement_p
= 0;
10497 /* Make sure and truncate the "natural" shift on the way in. We don't
10498 want to do this inside the loop as it makes it more difficult to
10500 if (SHIFT_COUNT_TRUNCATED
)
10501 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10503 /* If we were given an invalid count, don't do anything except exactly
10504 what was requested. */
10506 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10509 count
= orig_count
;
10511 /* Unless one of the branches of the `if' in this loop does a `continue',
10512 we will `break' the loop after the `if'. */
10516 /* If we have an operand of (clobber (const_int 0)), fail. */
10517 if (GET_CODE (varop
) == CLOBBER
)
10520 /* Convert ROTATERT to ROTATE. */
10521 if (code
== ROTATERT
)
10523 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10525 count
= bitsize
- count
;
10528 shift_mode
= result_mode
;
10529 if (shift_mode
!= mode
)
10531 /* We only change the modes of scalar shifts. */
10532 int_mode
= as_a
<scalar_int_mode
> (mode
);
10533 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10534 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10535 int_result_mode
, int_mode
,
10536 outer_op
, outer_const
);
10539 scalar_int_mode shift_unit_mode
10540 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10542 /* Handle cases where the count is greater than the size of the mode
10543 minus 1. For ASHIFT, use the size minus one as the count (this can
10544 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10545 take the count modulo the size. For other shifts, the result is
10548 Since these shifts are being produced by the compiler by combining
10549 multiple operations, each of which are defined, we know what the
10550 result is supposed to be. */
10552 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10554 if (code
== ASHIFTRT
)
10555 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10556 else if (code
== ROTATE
|| code
== ROTATERT
)
10557 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10560 /* We can't simply return zero because there may be an
10562 varop
= const0_rtx
;
10568 /* If we discovered we had to complement VAROP, leave. Making a NOT
10569 here would cause an infinite loop. */
10573 if (shift_mode
== shift_unit_mode
)
10575 /* An arithmetic right shift of a quantity known to be -1 or 0
10577 if (code
== ASHIFTRT
10578 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10579 == GET_MODE_PRECISION (shift_unit_mode
)))
10585 /* If we are doing an arithmetic right shift and discarding all but
10586 the sign bit copies, this is equivalent to doing a shift by the
10587 bitsize minus one. Convert it into that shift because it will
10588 often allow other simplifications. */
10590 if (code
== ASHIFTRT
10591 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10592 >= GET_MODE_PRECISION (shift_unit_mode
)))
10593 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10595 /* We simplify the tests below and elsewhere by converting
10596 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10597 `make_compound_operation' will convert it to an ASHIFTRT for
10598 those machines (such as VAX) that don't have an LSHIFTRT. */
10599 if (code
== ASHIFTRT
10600 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10601 && val_signbit_known_clear_p (shift_unit_mode
,
10602 nonzero_bits (varop
,
10606 if (((code
== LSHIFTRT
10607 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10608 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10610 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10611 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10612 & GET_MODE_MASK (shift_unit_mode
))))
10613 && !side_effects_p (varop
))
10614 varop
= const0_rtx
;
10617 switch (GET_CODE (varop
))
10623 new_rtx
= expand_compound_operation (varop
);
10624 if (new_rtx
!= varop
)
10632 /* The following rules apply only to scalars. */
10633 if (shift_mode
!= shift_unit_mode
)
10635 int_mode
= as_a
<scalar_int_mode
> (mode
);
10637 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10638 minus the width of a smaller mode, we can do this with a
10639 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10640 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10641 && ! mode_dependent_address_p (XEXP (varop
, 0),
10642 MEM_ADDR_SPACE (varop
))
10643 && ! MEM_VOLATILE_P (varop
)
10644 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10647 new_rtx
= adjust_address_nv (varop
, tmode
,
10648 BYTES_BIG_ENDIAN
? 0
10649 : count
/ BITS_PER_UNIT
);
10651 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10652 : ZERO_EXTEND
, int_mode
, new_rtx
);
10659 /* The following rules apply only to scalars. */
10660 if (shift_mode
!= shift_unit_mode
)
10662 int_mode
= as_a
<scalar_int_mode
> (mode
);
10663 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10665 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10666 the same number of words as what we've seen so far. Then store
10667 the widest mode in MODE. */
10668 if (subreg_lowpart_p (varop
)
10669 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10670 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10671 && (CEIL (GET_MODE_SIZE (inner_mode
), UNITS_PER_WORD
)
10672 == CEIL (GET_MODE_SIZE (int_mode
), UNITS_PER_WORD
))
10673 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10675 varop
= SUBREG_REG (varop
);
10676 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10683 /* Some machines use MULT instead of ASHIFT because MULT
10684 is cheaper. But it is still better on those machines to
10685 merge two shifts into one. */
10686 if (CONST_INT_P (XEXP (varop
, 1))
10687 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10689 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10690 varop
= simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10691 XEXP (varop
, 0), log2_rtx
);
10697 /* Similar, for when divides are cheaper. */
10698 if (CONST_INT_P (XEXP (varop
, 1))
10699 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10701 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10702 varop
= simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10703 XEXP (varop
, 0), log2_rtx
);
10709 /* If we are extracting just the sign bit of an arithmetic
10710 right shift, that shift is not needed. However, the sign
10711 bit of a wider mode may be different from what would be
10712 interpreted as the sign bit in a narrower mode, so, if
10713 the result is narrower, don't discard the shift. */
10714 if (code
== LSHIFTRT
10715 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10716 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10717 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10719 varop
= XEXP (varop
, 0);
10728 /* The following rules apply only to scalars. */
10729 if (shift_mode
!= shift_unit_mode
)
10731 int_mode
= as_a
<scalar_int_mode
> (mode
);
10732 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10733 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10735 /* Here we have two nested shifts. The result is usually the
10736 AND of a new shift with a mask. We compute the result below. */
10737 if (CONST_INT_P (XEXP (varop
, 1))
10738 && INTVAL (XEXP (varop
, 1)) >= 0
10739 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10740 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10741 && HWI_COMPUTABLE_MODE_P (int_mode
))
10743 enum rtx_code first_code
= GET_CODE (varop
);
10744 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10745 unsigned HOST_WIDE_INT mask
;
10748 /* We have one common special case. We can't do any merging if
10749 the inner code is an ASHIFTRT of a smaller mode. However, if
10750 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10751 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10752 we can convert it to
10753 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10754 This simplifies certain SIGN_EXTEND operations. */
10755 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10756 && count
== (GET_MODE_PRECISION (int_result_mode
)
10757 - GET_MODE_PRECISION (int_varop_mode
)))
10759 /* C3 has the low-order C1 bits zero. */
10761 mask
= GET_MODE_MASK (int_mode
)
10762 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10764 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10765 XEXP (varop
, 0), mask
);
10766 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10767 int_result_mode
, varop
, count
);
10768 count
= first_count
;
10773 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10774 than C1 high-order bits equal to the sign bit, we can convert
10775 this to either an ASHIFT or an ASHIFTRT depending on the
10778 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10780 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10781 && int_varop_mode
== shift_unit_mode
10782 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10785 varop
= XEXP (varop
, 0);
10786 count
-= first_count
;
10796 /* There are some cases we can't do. If CODE is ASHIFTRT,
10797 we can only do this if FIRST_CODE is also ASHIFTRT.
10799 We can't do the case when CODE is ROTATE and FIRST_CODE is
10802 If the mode of this shift is not the mode of the outer shift,
10803 we can't do this if either shift is a right shift or ROTATE.
10805 Finally, we can't do any of these if the mode is too wide
10806 unless the codes are the same.
10808 Handle the case where the shift codes are the same
10811 if (code
== first_code
)
10813 if (int_varop_mode
!= int_result_mode
10814 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10815 || code
== ROTATE
))
10818 count
+= first_count
;
10819 varop
= XEXP (varop
, 0);
10823 if (code
== ASHIFTRT
10824 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10825 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10826 || (int_varop_mode
!= int_result_mode
10827 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10828 || first_code
== ROTATE
10829 || code
== ROTATE
)))
10832 /* To compute the mask to apply after the shift, shift the
10833 nonzero bits of the inner shift the same way the
10834 outer shift will. */
10836 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10838 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10840 = simplify_const_binary_operation (code
, int_result_mode
,
10841 mask_rtx
, count_rtx
);
10843 /* Give up if we can't compute an outer operation to use. */
10845 || !CONST_INT_P (mask_rtx
)
10846 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10848 int_result_mode
, &complement_p
))
10851 /* If the shifts are in the same direction, we add the
10852 counts. Otherwise, we subtract them. */
10853 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10854 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10855 count
+= first_count
;
10857 count
-= first_count
;
10859 /* If COUNT is positive, the new shift is usually CODE,
10860 except for the two exceptions below, in which case it is
10861 FIRST_CODE. If the count is negative, FIRST_CODE should
10864 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10865 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10867 else if (count
< 0)
10868 code
= first_code
, count
= -count
;
10870 varop
= XEXP (varop
, 0);
10874 /* If we have (A << B << C) for any shift, we can convert this to
10875 (A << C << B). This wins if A is a constant. Only try this if
10876 B is not a constant. */
10878 else if (GET_CODE (varop
) == code
10879 && CONST_INT_P (XEXP (varop
, 0))
10880 && !CONST_INT_P (XEXP (varop
, 1)))
10882 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10883 sure the result will be masked. See PR70222. */
10884 if (code
== LSHIFTRT
10885 && int_mode
!= int_result_mode
10886 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10887 GET_MODE_MASK (int_result_mode
)
10888 >> orig_count
, int_result_mode
,
10891 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10892 up outer sign extension (often left and right shift) is
10893 hardly more efficient than the original. See PR70429. */
10894 if (code
== ASHIFTRT
&& int_mode
!= int_result_mode
)
10897 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10898 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
10901 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
10908 /* The following rules apply only to scalars. */
10909 if (shift_mode
!= shift_unit_mode
)
10912 /* Make this fit the case below. */
10913 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10919 /* The following rules apply only to scalars. */
10920 if (shift_mode
!= shift_unit_mode
)
10922 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10923 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10925 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10926 with C the size of VAROP - 1 and the shift is logical if
10927 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10928 we have an (le X 0) operation. If we have an arithmetic shift
10929 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10930 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10932 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10933 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10934 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10935 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10936 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
10937 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10940 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
10943 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10944 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
10949 /* If we have (shift (logical)), move the logical to the outside
10950 to allow it to possibly combine with another logical and the
10951 shift to combine with another shift. This also canonicalizes to
10952 what a ZERO_EXTRACT looks like. Also, some machines have
10953 (and (shift)) insns. */
10955 if (CONST_INT_P (XEXP (varop
, 1))
10956 /* We can't do this if we have (ashiftrt (xor)) and the
10957 constant has its sign bit set in shift_unit_mode with
10958 shift_unit_mode wider than result_mode. */
10959 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10960 && int_result_mode
!= shift_unit_mode
10961 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10962 shift_unit_mode
) < 0)
10963 && (new_rtx
= simplify_const_binary_operation
10964 (code
, int_result_mode
,
10965 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
10966 gen_int_shift_amount (int_result_mode
, count
))) != 0
10967 && CONST_INT_P (new_rtx
)
10968 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10969 INTVAL (new_rtx
), int_result_mode
,
10972 varop
= XEXP (varop
, 0);
10976 /* If we can't do that, try to simplify the shift in each arm of the
10977 logical expression, make a new logical expression, and apply
10978 the inverse distributive law. This also can't be done for
10979 (ashiftrt (xor)) where we've widened the shift and the constant
10980 changes the sign bit. */
10981 if (CONST_INT_P (XEXP (varop
, 1))
10982 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10983 && int_result_mode
!= shift_unit_mode
10984 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10985 shift_unit_mode
) < 0))
10987 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
10988 XEXP (varop
, 0), count
);
10989 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
10990 XEXP (varop
, 1), count
);
10992 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
10994 varop
= apply_distributive_law (varop
);
11002 /* The following rules apply only to scalars. */
11003 if (shift_mode
!= shift_unit_mode
)
11005 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11007 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11008 says that the sign bit can be tested, FOO has mode MODE, C is
11009 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11010 that may be nonzero. */
11011 if (code
== LSHIFTRT
11012 && XEXP (varop
, 1) == const0_rtx
11013 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
11014 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11015 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11016 && STORE_FLAG_VALUE
== -1
11017 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11018 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11019 int_result_mode
, &complement_p
))
11021 varop
= XEXP (varop
, 0);
11028 /* The following rules apply only to scalars. */
11029 if (shift_mode
!= shift_unit_mode
)
11031 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11033 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11034 than the number of bits in the mode is equivalent to A. */
11035 if (code
== LSHIFTRT
11036 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11037 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11039 varop
= XEXP (varop
, 0);
11044 /* NEG commutes with ASHIFT since it is multiplication. Move the
11045 NEG outside to allow shifts to combine. */
11047 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11048 int_result_mode
, &complement_p
))
11050 varop
= XEXP (varop
, 0);
11056 /* The following rules apply only to scalars. */
11057 if (shift_mode
!= shift_unit_mode
)
11059 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11061 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11062 is one less than the number of bits in the mode is
11063 equivalent to (xor A 1). */
11064 if (code
== LSHIFTRT
11065 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11066 && XEXP (varop
, 1) == constm1_rtx
11067 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11068 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11069 int_result_mode
, &complement_p
))
11072 varop
= XEXP (varop
, 0);
11076 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11077 that might be nonzero in BAR are those being shifted out and those
11078 bits are known zero in FOO, we can replace the PLUS with FOO.
11079 Similarly in the other operand order. This code occurs when
11080 we are computing the size of a variable-size array. */
11082 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11083 && count
< HOST_BITS_PER_WIDE_INT
11084 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11085 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11086 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11088 varop
= XEXP (varop
, 0);
11091 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11092 && count
< HOST_BITS_PER_WIDE_INT
11093 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11094 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11096 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11097 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)) == 0)
11099 varop
= XEXP (varop
, 1);
11103 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11105 && CONST_INT_P (XEXP (varop
, 1))
11106 && (new_rtx
= simplify_const_binary_operation
11107 (ASHIFT
, int_result_mode
,
11108 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11109 gen_int_shift_amount (int_result_mode
, count
))) != 0
11110 && CONST_INT_P (new_rtx
)
11111 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11112 INTVAL (new_rtx
), int_result_mode
,
11115 varop
= XEXP (varop
, 0);
11119 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11120 signbit', and attempt to change the PLUS to an XOR and move it to
11121 the outer operation as is done above in the AND/IOR/XOR case
11122 leg for shift(logical). See details in logical handling above
11123 for reasoning in doing so. */
11124 if (code
== LSHIFTRT
11125 && CONST_INT_P (XEXP (varop
, 1))
11126 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11127 && (new_rtx
= simplify_const_binary_operation
11128 (code
, int_result_mode
,
11129 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11130 gen_int_shift_amount (int_result_mode
, count
))) != 0
11131 && CONST_INT_P (new_rtx
)
11132 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11133 INTVAL (new_rtx
), int_result_mode
,
11136 varop
= XEXP (varop
, 0);
11143 /* The following rules apply only to scalars. */
11144 if (shift_mode
!= shift_unit_mode
)
11146 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11148 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11149 with C the size of VAROP - 1 and the shift is logical if
11150 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11151 we have a (gt X 0) operation. If the shift is arithmetic with
11152 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11153 we have a (neg (gt X 0)) operation. */
11155 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11156 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11157 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11158 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11159 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11160 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11161 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11164 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11167 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11168 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11175 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11176 if the truncate does not affect the value. */
11177 if (code
== LSHIFTRT
11178 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11179 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11180 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11181 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11182 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11184 rtx varop_inner
= XEXP (varop
, 0);
11185 int new_count
= count
+ INTVAL (XEXP (varop_inner
, 1));
11186 rtx new_count_rtx
= gen_int_shift_amount (GET_MODE (varop_inner
),
11188 varop_inner
= gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11189 XEXP (varop_inner
, 0),
11191 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11204 shift_mode
= result_mode
;
11205 if (shift_mode
!= mode
)
11207 /* We only change the modes of scalar shifts. */
11208 int_mode
= as_a
<scalar_int_mode
> (mode
);
11209 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11210 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11211 int_mode
, outer_op
, outer_const
);
11214 /* We have now finished analyzing the shift. The result should be
11215 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11216 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11217 to the result of the shift. OUTER_CONST is the relevant constant,
11218 but we must turn off all bits turned off in the shift. */
11220 if (outer_op
== UNKNOWN
11221 && orig_code
== code
&& orig_count
== count
11222 && varop
== orig_varop
11223 && shift_mode
== GET_MODE (varop
))
11226 /* Make a SUBREG if necessary. If we can't make it, fail. */
11227 varop
= gen_lowpart (shift_mode
, varop
);
11228 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11231 /* If we have an outer operation and we just made a shift, it is
11232 possible that we could have simplified the shift were it not
11233 for the outer operation. So try to do the simplification
11236 if (outer_op
!= UNKNOWN
)
11237 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11242 x
= simplify_gen_binary (code
, shift_mode
, varop
,
11243 gen_int_shift_amount (shift_mode
, count
));
11245 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11246 turn off all the bits that the shift would have turned off. */
11247 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11248 /* We only change the modes of scalar shifts. */
11249 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11250 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11252 /* Do the remainder of the processing in RESULT_MODE. */
11253 x
= gen_lowpart_or_truncate (result_mode
, x
);
11255 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11258 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11260 if (outer_op
!= UNKNOWN
)
11262 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11264 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11265 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11266 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11268 if (outer_op
== AND
)
11269 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11270 else if (outer_op
== SET
)
11272 /* This means that we have determined that the result is
11273 equivalent to a constant. This should be rare. */
11274 if (!side_effects_p (x
))
11275 x
= GEN_INT (outer_const
);
11277 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11278 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11280 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11281 GEN_INT (outer_const
));
11287 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11288 The result of the shift is RESULT_MODE. If we cannot simplify it,
11289 return X or, if it is NULL, synthesize the expression with
11290 simplify_gen_binary. Otherwise, return a simplified value.
11292 The shift is normally computed in the widest mode we find in VAROP, as
11293 long as it isn't a different number of words than RESULT_MODE. Exceptions
11294 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11297 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11298 rtx varop
, int count
)
11300 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11305 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
,
11306 gen_int_shift_amount (GET_MODE (varop
), count
));
11307 if (GET_MODE (x
) != result_mode
)
11308 x
= gen_lowpart (result_mode
, x
);
11313 /* A subroutine of recog_for_combine. See there for arguments and
11317 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11319 rtx pat
= *pnewpat
;
11320 rtx pat_without_clobbers
;
11321 int insn_code_number
;
11322 int num_clobbers_to_add
= 0;
11324 rtx notes
= NULL_RTX
;
11325 rtx old_notes
, old_pat
;
11328 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11329 we use to indicate that something didn't match. If we find such a
11330 thing, force rejection. */
11331 if (GET_CODE (pat
) == PARALLEL
)
11332 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11333 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11334 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11337 old_pat
= PATTERN (insn
);
11338 old_notes
= REG_NOTES (insn
);
11339 PATTERN (insn
) = pat
;
11340 REG_NOTES (insn
) = NULL_RTX
;
11342 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11343 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11345 if (insn_code_number
< 0)
11346 fputs ("Failed to match this instruction:\n", dump_file
);
11348 fputs ("Successfully matched this instruction:\n", dump_file
);
11349 print_rtl_single (dump_file
, pat
);
11352 /* If it isn't, there is the possibility that we previously had an insn
11353 that clobbered some register as a side effect, but the combined
11354 insn doesn't need to do that. So try once more without the clobbers
11355 unless this represents an ASM insn. */
11357 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11358 && GET_CODE (pat
) == PARALLEL
)
11362 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11363 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11366 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11370 SUBST_INT (XVECLEN (pat
, 0), pos
);
11373 pat
= XVECEXP (pat
, 0, 0);
11375 PATTERN (insn
) = pat
;
11376 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11377 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11379 if (insn_code_number
< 0)
11380 fputs ("Failed to match this instruction:\n", dump_file
);
11382 fputs ("Successfully matched this instruction:\n", dump_file
);
11383 print_rtl_single (dump_file
, pat
);
11387 pat_without_clobbers
= pat
;
11389 PATTERN (insn
) = old_pat
;
11390 REG_NOTES (insn
) = old_notes
;
11392 /* Recognize all noop sets, these will be killed by followup pass. */
11393 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11394 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11396 /* If we had any clobbers to add, make a new pattern than contains
11397 them. Then check to make sure that all of them are dead. */
11398 if (num_clobbers_to_add
)
11400 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11401 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11402 ? (XVECLEN (pat
, 0)
11403 + num_clobbers_to_add
)
11404 : num_clobbers_to_add
+ 1));
11406 if (GET_CODE (pat
) == PARALLEL
)
11407 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11408 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11410 XVECEXP (newpat
, 0, 0) = pat
;
11412 add_clobbers (newpat
, insn_code_number
);
11414 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11415 i
< XVECLEN (newpat
, 0); i
++)
11417 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11418 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11420 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11422 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11423 notes
= alloc_reg_note (REG_UNUSED
,
11424 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11430 if (insn_code_number
>= 0
11431 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11433 old_pat
= PATTERN (insn
);
11434 old_notes
= REG_NOTES (insn
);
11435 old_icode
= INSN_CODE (insn
);
11436 PATTERN (insn
) = pat
;
11437 REG_NOTES (insn
) = notes
;
11438 INSN_CODE (insn
) = insn_code_number
;
11440 /* Allow targets to reject combined insn. */
11441 if (!targetm
.legitimate_combined_insn (insn
))
11443 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11444 fputs ("Instruction not appropriate for target.",
11447 /* Callers expect recog_for_combine to strip
11448 clobbers from the pattern on failure. */
11449 pat
= pat_without_clobbers
;
11452 insn_code_number
= -1;
11455 PATTERN (insn
) = old_pat
;
11456 REG_NOTES (insn
) = old_notes
;
11457 INSN_CODE (insn
) = old_icode
;
11463 return insn_code_number
;
11466 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11467 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11468 Return whether anything was so changed. */
11471 change_zero_ext (rtx pat
)
11473 bool changed
= false;
11474 rtx
*src
= &SET_SRC (pat
);
11476 subrtx_ptr_iterator::array_type array
;
11477 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11480 scalar_int_mode mode
, inner_mode
;
11481 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11485 if (GET_CODE (x
) == ZERO_EXTRACT
11486 && CONST_INT_P (XEXP (x
, 1))
11487 && CONST_INT_P (XEXP (x
, 2))
11488 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11489 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11491 size
= INTVAL (XEXP (x
, 1));
11493 int start
= INTVAL (XEXP (x
, 2));
11494 if (BITS_BIG_ENDIAN
)
11495 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11498 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0),
11499 gen_int_shift_amount (inner_mode
, start
));
11503 if (mode
!= inner_mode
)
11505 if (REG_P (x
) && HARD_REGISTER_P (x
)
11506 && !can_change_dest_mode (x
, 0, mode
))
11509 x
= gen_lowpart_SUBREG (mode
, x
);
11512 else if (GET_CODE (x
) == ZERO_EXTEND
11513 && GET_CODE (XEXP (x
, 0)) == SUBREG
11514 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11515 && !paradoxical_subreg_p (XEXP (x
, 0))
11516 && subreg_lowpart_p (XEXP (x
, 0)))
11518 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11519 size
= GET_MODE_PRECISION (inner_mode
);
11520 x
= SUBREG_REG (XEXP (x
, 0));
11521 if (GET_MODE (x
) != mode
)
11523 if (REG_P (x
) && HARD_REGISTER_P (x
)
11524 && !can_change_dest_mode (x
, 0, mode
))
11527 x
= gen_lowpart_SUBREG (mode
, x
);
11530 else if (GET_CODE (x
) == ZERO_EXTEND
11531 && REG_P (XEXP (x
, 0))
11532 && HARD_REGISTER_P (XEXP (x
, 0))
11533 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11535 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11536 size
= GET_MODE_PRECISION (inner_mode
);
11537 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11542 if (!(GET_CODE (x
) == LSHIFTRT
11543 && CONST_INT_P (XEXP (x
, 1))
11544 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11546 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11547 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11555 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11556 maybe_swap_commutative_operands (**iter
);
11558 rtx
*dst
= &SET_DEST (pat
);
11559 scalar_int_mode mode
;
11560 if (GET_CODE (*dst
) == ZERO_EXTRACT
11561 && REG_P (XEXP (*dst
, 0))
11562 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11563 && CONST_INT_P (XEXP (*dst
, 1))
11564 && CONST_INT_P (XEXP (*dst
, 2)))
11566 rtx reg
= XEXP (*dst
, 0);
11567 int width
= INTVAL (XEXP (*dst
, 1));
11568 int offset
= INTVAL (XEXP (*dst
, 2));
11569 int reg_width
= GET_MODE_PRECISION (mode
);
11570 if (BITS_BIG_ENDIAN
)
11571 offset
= reg_width
- width
- offset
;
11574 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11575 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11576 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11578 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11581 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11582 w
= gen_rtx_IOR (mode
, x
, z
);
11583 SUBST (SET_DEST (pat
), reg
);
11584 SUBST (SET_SRC (pat
), w
);
11592 /* Like recog, but we receive the address of a pointer to a new pattern.
11593 We try to match the rtx that the pointer points to.
11594 If that fails, we may try to modify or replace the pattern,
11595 storing the replacement into the same pointer object.
11597 Modifications include deletion or addition of CLOBBERs. If the
11598 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11599 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11600 (and undo if that fails).
11602 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11603 the CLOBBERs are placed.
11605 The value is the final insn code from the pattern ultimately matched,
11609 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11611 rtx pat
= *pnewpat
;
11612 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11613 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11614 return insn_code_number
;
11616 void *marker
= get_undo_marker ();
11617 bool changed
= false;
11619 if (GET_CODE (pat
) == SET
)
11620 changed
= change_zero_ext (pat
);
11621 else if (GET_CODE (pat
) == PARALLEL
)
11624 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11626 rtx set
= XVECEXP (pat
, 0, i
);
11627 if (GET_CODE (set
) == SET
)
11628 changed
|= change_zero_ext (set
);
11634 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11636 if (insn_code_number
< 0)
11637 undo_to_marker (marker
);
11640 return insn_code_number
;
11643 /* Like gen_lowpart_general but for use by combine. In combine it
11644 is not possible to create any new pseudoregs. However, it is
11645 safe to create invalid memory addresses, because combine will
11646 try to recognize them and all they will do is make the combine
11649 If for some reason this cannot do its job, an rtx
11650 (clobber (const_int 0)) is returned.
11651 An insn containing that will not be recognized. */
11654 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11656 machine_mode imode
= GET_MODE (x
);
11659 if (omode
== imode
)
11662 /* We can only support MODE being wider than a word if X is a
11663 constant integer or has a mode the same size. */
11664 if (maybe_gt (GET_MODE_SIZE (omode
), UNITS_PER_WORD
)
11665 && ! (CONST_SCALAR_INT_P (x
)
11666 || known_eq (GET_MODE_SIZE (imode
), GET_MODE_SIZE (omode
))))
11669 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11670 won't know what to do. So we will strip off the SUBREG here and
11671 process normally. */
11672 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11674 x
= SUBREG_REG (x
);
11676 /* For use in case we fall down into the address adjustments
11677 further below, we need to adjust the known mode and size of
11678 x; imode and isize, since we just adjusted x. */
11679 imode
= GET_MODE (x
);
11681 if (imode
== omode
)
11685 result
= gen_lowpart_common (omode
, x
);
11692 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11694 if (MEM_VOLATILE_P (x
)
11695 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11698 /* If we want to refer to something bigger than the original memref,
11699 generate a paradoxical subreg instead. That will force a reload
11700 of the original memref X. */
11701 if (paradoxical_subreg_p (omode
, imode
))
11702 return gen_rtx_SUBREG (omode
, x
, 0);
11704 poly_int64 offset
= byte_lowpart_offset (omode
, imode
);
11705 return adjust_address_nv (x
, omode
, offset
);
11708 /* If X is a comparison operator, rewrite it in a new mode. This
11709 probably won't match, but may allow further simplifications. */
11710 else if (COMPARISON_P (x
))
11711 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11713 /* If we couldn't simplify X any other way, just enclose it in a
11714 SUBREG. Normally, this SUBREG won't match, but some patterns may
11715 include an explicit SUBREG or we may simplify it further in combine. */
11720 if (imode
== VOIDmode
)
11722 imode
= int_mode_for_mode (omode
).require ();
11723 x
= gen_lowpart_common (imode
, x
);
11727 res
= lowpart_subreg (omode
, x
, imode
);
11733 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11736 /* Try to simplify a comparison between OP0 and a constant OP1,
11737 where CODE is the comparison code that will be tested, into a
11738 (CODE OP0 const0_rtx) form.
11740 The result is a possibly different comparison code to use.
11741 *POP1 may be updated. */
11743 static enum rtx_code
11744 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11745 rtx op0
, rtx
*pop1
)
11747 scalar_int_mode int_mode
;
11748 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11750 /* Get the constant we are comparing against and turn off all bits
11751 not on in our mode. */
11752 if (mode
!= VOIDmode
)
11753 const_op
= trunc_int_for_mode (const_op
, mode
);
11755 /* If we are comparing against a constant power of two and the value
11756 being compared can only have that single bit nonzero (e.g., it was
11757 `and'ed with that bit), we can replace this with a comparison
11760 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11761 || code
== LT
|| code
== LTU
)
11762 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11763 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11764 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11765 && (nonzero_bits (op0
, int_mode
)
11766 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11768 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11772 /* Similarly, if we are comparing a value known to be either -1 or
11773 0 with -1, change it to the opposite comparison against zero. */
11775 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11776 || code
== GEU
|| code
== LTU
)
11777 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11778 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11780 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11784 /* Do some canonicalizations based on the comparison code. We prefer
11785 comparisons against zero and then prefer equality comparisons.
11786 If we can reduce the size of a constant, we will do that too. */
11790 /* < C is equivalent to <= (C - 1) */
11795 /* ... fall through to LE case below. */
11796 gcc_fallthrough ();
11802 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11809 /* If we are doing a <= 0 comparison on a value known to have
11810 a zero sign bit, we can replace this with == 0. */
11811 else if (const_op
== 0
11812 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11813 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11814 && (nonzero_bits (op0
, int_mode
)
11815 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11821 /* >= C is equivalent to > (C - 1). */
11826 /* ... fall through to GT below. */
11827 gcc_fallthrough ();
11833 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11840 /* If we are doing a > 0 comparison on a value known to have
11841 a zero sign bit, we can replace this with != 0. */
11842 else if (const_op
== 0
11843 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11844 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11845 && (nonzero_bits (op0
, int_mode
)
11846 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11852 /* < C is equivalent to <= (C - 1). */
11857 /* ... fall through ... */
11858 gcc_fallthrough ();
11860 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11861 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11862 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11863 && ((unsigned HOST_WIDE_INT
) const_op
11864 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11874 /* unsigned <= 0 is equivalent to == 0 */
11877 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11878 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11879 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11880 && ((unsigned HOST_WIDE_INT
) const_op
11881 == ((HOST_WIDE_INT_1U
11882 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
11890 /* >= C is equivalent to > (C - 1). */
11895 /* ... fall through ... */
11896 gcc_fallthrough ();
11899 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11900 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11901 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11902 && ((unsigned HOST_WIDE_INT
) const_op
11903 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11913 /* unsigned > 0 is equivalent to != 0 */
11916 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11917 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11918 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11919 && ((unsigned HOST_WIDE_INT
) const_op
11920 == (HOST_WIDE_INT_1U
11921 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
11932 *pop1
= GEN_INT (const_op
);
11936 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11937 comparison code that will be tested.
11939 The result is a possibly different comparison code to use. *POP0 and
11940 *POP1 may be updated.
11942 It is possible that we might detect that a comparison is either always
11943 true or always false. However, we do not perform general constant
11944 folding in combine, so this knowledge isn't useful. Such tautologies
11945 should have been detected earlier. Hence we ignore all such cases. */
11947 static enum rtx_code
11948 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11954 scalar_int_mode mode
, inner_mode
, tmode
;
11955 opt_scalar_int_mode tmode_iter
;
11957 /* Try a few ways of applying the same transformation to both operands. */
11960 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11961 so check specially. */
11962 if (!WORD_REGISTER_OPERATIONS
11963 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11964 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11965 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11966 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11967 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11968 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11969 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
11970 && (is_a
<scalar_int_mode
>
11971 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
11972 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
11973 && CONST_INT_P (XEXP (op0
, 1))
11974 && XEXP (op0
, 1) == XEXP (op1
, 1)
11975 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11976 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11977 && (INTVAL (XEXP (op0
, 1))
11978 == (GET_MODE_PRECISION (mode
)
11979 - GET_MODE_PRECISION (inner_mode
))))
11981 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11982 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11985 /* If both operands are the same constant shift, see if we can ignore the
11986 shift. We can if the shift is a rotate or if the bits shifted out of
11987 this shift are known to be zero for both inputs and if the type of
11988 comparison is compatible with the shift. */
11989 if (GET_CODE (op0
) == GET_CODE (op1
)
11990 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11991 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11992 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11993 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11994 || (GET_CODE (op0
) == ASHIFTRT
11995 && (code
!= GTU
&& code
!= LTU
11996 && code
!= GEU
&& code
!= LEU
)))
11997 && CONST_INT_P (XEXP (op0
, 1))
11998 && INTVAL (XEXP (op0
, 1)) >= 0
11999 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12000 && XEXP (op0
, 1) == XEXP (op1
, 1))
12002 machine_mode mode
= GET_MODE (op0
);
12003 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12004 int shift_count
= INTVAL (XEXP (op0
, 1));
12006 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
12007 mask
&= (mask
>> shift_count
) << shift_count
;
12008 else if (GET_CODE (op0
) == ASHIFT
)
12009 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
12011 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
12012 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
12013 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
12018 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12019 SUBREGs are of the same mode, and, in both cases, the AND would
12020 be redundant if the comparison was done in the narrower mode,
12021 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12022 and the operand's possibly nonzero bits are 0xffffff01; in that case
12023 if we only care about QImode, we don't need the AND). This case
12024 occurs if the output mode of an scc insn is not SImode and
12025 STORE_FLAG_VALUE == 1 (e.g., the 386).
12027 Similarly, check for a case where the AND's are ZERO_EXTEND
12028 operations from some narrower mode even though a SUBREG is not
12031 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
12032 && CONST_INT_P (XEXP (op0
, 1))
12033 && CONST_INT_P (XEXP (op1
, 1)))
12035 rtx inner_op0
= XEXP (op0
, 0);
12036 rtx inner_op1
= XEXP (op1
, 0);
12037 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
12038 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
12041 if (paradoxical_subreg_p (inner_op0
)
12042 && GET_CODE (inner_op1
) == SUBREG
12043 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12044 && (GET_MODE (SUBREG_REG (inner_op0
))
12045 == GET_MODE (SUBREG_REG (inner_op1
)))
12046 && ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12047 GET_MODE (SUBREG_REG (inner_op0
)))) == 0
12048 && ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12049 GET_MODE (SUBREG_REG (inner_op1
)))) == 0)
12051 op0
= SUBREG_REG (inner_op0
);
12052 op1
= SUBREG_REG (inner_op1
);
12054 /* The resulting comparison is always unsigned since we masked
12055 off the original sign bit. */
12056 code
= unsigned_condition (code
);
12062 FOR_EACH_MODE_UNTIL (tmode
,
12063 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12064 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12066 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12067 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12068 code
= unsigned_condition (code
);
12077 /* If both operands are NOT, we can strip off the outer operation
12078 and adjust the comparison code for swapped operands; similarly for
12079 NEG, except that this must be an equality comparison. */
12080 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12081 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12082 && (code
== EQ
|| code
== NE
)))
12083 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12089 /* If the first operand is a constant, swap the operands and adjust the
12090 comparison code appropriately, but don't do this if the second operand
12091 is already a constant integer. */
12092 if (swap_commutative_operands_p (op0
, op1
))
12094 std::swap (op0
, op1
);
12095 code
= swap_condition (code
);
12098 /* We now enter a loop during which we will try to simplify the comparison.
12099 For the most part, we only are concerned with comparisons with zero,
12100 but some things may really be comparisons with zero but not start
12101 out looking that way. */
12103 while (CONST_INT_P (op1
))
12105 machine_mode raw_mode
= GET_MODE (op0
);
12106 scalar_int_mode int_mode
;
12107 int equality_comparison_p
;
12108 int sign_bit_comparison_p
;
12109 int unsigned_comparison_p
;
12110 HOST_WIDE_INT const_op
;
12112 /* We only want to handle integral modes. This catches VOIDmode,
12113 CCmode, and the floating-point modes. An exception is that we
12114 can handle VOIDmode if OP0 is a COMPARE or a comparison
12117 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12118 && ! (raw_mode
== VOIDmode
12119 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12122 /* Try to simplify the compare to constant, possibly changing the
12123 comparison op, and/or changing op1 to zero. */
12124 code
= simplify_compare_const (code
, raw_mode
, op0
, &op1
);
12125 const_op
= INTVAL (op1
);
12127 /* Compute some predicates to simplify code below. */
12129 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12130 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12131 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12134 /* If this is a sign bit comparison and we can do arithmetic in
12135 MODE, say that we will only be needing the sign bit of OP0. */
12136 if (sign_bit_comparison_p
12137 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12138 && HWI_COMPUTABLE_MODE_P (int_mode
))
12139 op0
= force_to_mode (op0
, int_mode
,
12141 << (GET_MODE_PRECISION (int_mode
) - 1),
12144 if (COMPARISON_P (op0
))
12146 /* We can't do anything if OP0 is a condition code value, rather
12147 than an actual data value. */
12149 || CC0_P (XEXP (op0
, 0))
12150 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12153 /* Get the two operands being compared. */
12154 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12155 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12157 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12159 /* Check for the cases where we simply want the result of the
12160 earlier test or the opposite of that result. */
12161 if (code
== NE
|| code
== EQ
12162 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12163 && (code
== LT
|| code
== GE
)))
12165 enum rtx_code new_code
;
12166 if (code
== LT
|| code
== NE
)
12167 new_code
= GET_CODE (op0
);
12169 new_code
= reversed_comparison_code (op0
, NULL
);
12171 if (new_code
!= UNKNOWN
)
12182 if (raw_mode
== VOIDmode
)
12184 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12186 /* Now try cases based on the opcode of OP0. If none of the cases
12187 does a "continue", we exit this loop immediately after the
12190 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12191 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12192 switch (GET_CODE (op0
))
12195 /* If we are extracting a single bit from a variable position in
12196 a constant that has only a single bit set and are comparing it
12197 with zero, we can convert this into an equality comparison
12198 between the position and the location of the single bit. */
12199 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12200 have already reduced the shift count modulo the word size. */
12201 if (!SHIFT_COUNT_TRUNCATED
12202 && CONST_INT_P (XEXP (op0
, 0))
12203 && XEXP (op0
, 1) == const1_rtx
12204 && equality_comparison_p
&& const_op
== 0
12205 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12207 if (BITS_BIG_ENDIAN
)
12208 i
= BITS_PER_WORD
- 1 - i
;
12210 op0
= XEXP (op0
, 2);
12214 /* Result is nonzero iff shift count is equal to I. */
12215 code
= reverse_condition (code
);
12222 tem
= expand_compound_operation (op0
);
12231 /* If testing for equality, we can take the NOT of the constant. */
12232 if (equality_comparison_p
12233 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12235 op0
= XEXP (op0
, 0);
12240 /* If just looking at the sign bit, reverse the sense of the
12242 if (sign_bit_comparison_p
)
12244 op0
= XEXP (op0
, 0);
12245 code
= (code
== GE
? LT
: GE
);
12251 /* If testing for equality, we can take the NEG of the constant. */
12252 if (equality_comparison_p
12253 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12255 op0
= XEXP (op0
, 0);
12260 /* The remaining cases only apply to comparisons with zero. */
12264 /* When X is ABS or is known positive,
12265 (neg X) is < 0 if and only if X != 0. */
12267 if (sign_bit_comparison_p
12268 && (GET_CODE (XEXP (op0
, 0)) == ABS
12269 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12270 && (nonzero_bits (XEXP (op0
, 0), mode
)
12271 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12274 op0
= XEXP (op0
, 0);
12275 code
= (code
== LT
? NE
: EQ
);
12279 /* If we have NEG of something whose two high-order bits are the
12280 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12281 if (num_sign_bit_copies (op0
, mode
) >= 2)
12283 op0
= XEXP (op0
, 0);
12284 code
= swap_condition (code
);
12290 /* If we are testing equality and our count is a constant, we
12291 can perform the inverse operation on our RHS. */
12292 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12293 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12294 op1
, XEXP (op0
, 1))) != 0)
12296 op0
= XEXP (op0
, 0);
12301 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12302 a particular bit. Convert it to an AND of a constant of that
12303 bit. This will be converted into a ZERO_EXTRACT. */
12304 if (const_op
== 0 && sign_bit_comparison_p
12305 && CONST_INT_P (XEXP (op0
, 1))
12306 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12308 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12311 - INTVAL (XEXP (op0
, 1)))));
12312 code
= (code
== LT
? NE
: EQ
);
12316 /* Fall through. */
12319 /* ABS is ignorable inside an equality comparison with zero. */
12320 if (const_op
== 0 && equality_comparison_p
)
12322 op0
= XEXP (op0
, 0);
12328 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12329 (compare FOO CONST) if CONST fits in FOO's mode and we
12330 are either testing inequality or have an unsigned
12331 comparison with ZERO_EXTEND or a signed comparison with
12332 SIGN_EXTEND. But don't do it if we don't have a compare
12333 insn of the given mode, since we'd have to revert it
12334 later on, and then we wouldn't know whether to sign- or
12336 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12337 && ! unsigned_comparison_p
12338 && HWI_COMPUTABLE_MODE_P (mode
)
12339 && trunc_int_for_mode (const_op
, mode
) == const_op
12340 && have_insn_for (COMPARE
, mode
))
12342 op0
= XEXP (op0
, 0);
12348 /* Check for the case where we are comparing A - C1 with C2, that is
12350 (subreg:MODE (plus (A) (-C1))) op (C2)
12352 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12353 comparison in the wider mode. One of the following two conditions
12354 must be true in order for this to be valid:
12356 1. The mode extension results in the same bit pattern being added
12357 on both sides and the comparison is equality or unsigned. As
12358 C2 has been truncated to fit in MODE, the pattern can only be
12361 2. The mode extension results in the sign bit being copied on
12364 The difficulty here is that we have predicates for A but not for
12365 (A - C1) so we need to check that C1 is within proper bounds so
12366 as to perturbate A as little as possible. */
12368 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12369 && subreg_lowpart_p (op0
)
12370 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12372 && GET_MODE_PRECISION (inner_mode
) > mode_width
12373 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12374 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12376 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12377 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12380 && (unsigned HOST_WIDE_INT
) c1
12381 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12382 && (equality_comparison_p
|| unsigned_comparison_p
)
12383 /* (A - C1) zero-extends if it is positive and sign-extends
12384 if it is negative, C2 both zero- and sign-extends. */
12385 && (((nonzero_bits (a
, inner_mode
)
12386 & ~GET_MODE_MASK (mode
)) == 0
12388 /* (A - C1) sign-extends if it is positive and 1-extends
12389 if it is negative, C2 both sign- and 1-extends. */
12390 || (num_sign_bit_copies (a
, inner_mode
)
12391 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12394 || ((unsigned HOST_WIDE_INT
) c1
12395 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12396 /* (A - C1) always sign-extends, like C2. */
12397 && num_sign_bit_copies (a
, inner_mode
)
12398 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12399 - (mode_width
- 1))))
12401 op0
= SUBREG_REG (op0
);
12406 /* If the inner mode is narrower and we are extracting the low part,
12407 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12408 if (paradoxical_subreg_p (op0
))
12410 else if (subreg_lowpart_p (op0
)
12411 && GET_MODE_CLASS (mode
) == MODE_INT
12412 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12413 && (code
== NE
|| code
== EQ
)
12414 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12415 && !paradoxical_subreg_p (op0
)
12416 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12417 & ~GET_MODE_MASK (mode
)) == 0)
12419 /* Remove outer subregs that don't do anything. */
12420 tem
= gen_lowpart (inner_mode
, op1
);
12422 if ((nonzero_bits (tem
, inner_mode
)
12423 & ~GET_MODE_MASK (mode
)) == 0)
12425 op0
= SUBREG_REG (op0
);
12437 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12438 && (unsigned_comparison_p
|| equality_comparison_p
)
12439 && HWI_COMPUTABLE_MODE_P (mode
)
12440 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12442 && have_insn_for (COMPARE
, mode
))
12444 op0
= XEXP (op0
, 0);
12450 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12451 this for equality comparisons due to pathological cases involving
12453 if (equality_comparison_p
12454 && (tem
= simplify_binary_operation (MINUS
, mode
,
12455 op1
, XEXP (op0
, 1))) != 0)
12457 op0
= XEXP (op0
, 0);
12462 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12463 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12464 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12466 op0
= XEXP (XEXP (op0
, 0), 0);
12467 code
= (code
== LT
? EQ
: NE
);
12473 /* We used to optimize signed comparisons against zero, but that
12474 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12475 arrive here as equality comparisons, or (GEU, LTU) are
12476 optimized away. No need to special-case them. */
12478 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12479 (eq B (minus A C)), whichever simplifies. We can only do
12480 this for equality comparisons due to pathological cases involving
12482 if (equality_comparison_p
12483 && (tem
= simplify_binary_operation (PLUS
, mode
,
12484 XEXP (op0
, 1), op1
)) != 0)
12486 op0
= XEXP (op0
, 0);
12491 if (equality_comparison_p
12492 && (tem
= simplify_binary_operation (MINUS
, mode
,
12493 XEXP (op0
, 0), op1
)) != 0)
12495 op0
= XEXP (op0
, 1);
12500 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12501 of bits in X minus 1, is one iff X > 0. */
12502 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12503 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12504 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12505 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12507 op0
= XEXP (op0
, 1);
12508 code
= (code
== GE
? LE
: GT
);
12514 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12515 if C is zero or B is a constant. */
12516 if (equality_comparison_p
12517 && (tem
= simplify_binary_operation (XOR
, mode
,
12518 XEXP (op0
, 1), op1
)) != 0)
12520 op0
= XEXP (op0
, 0);
12528 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12530 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12531 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12532 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12534 op0
= XEXP (op0
, 1);
12535 code
= (code
== GE
? GT
: LE
);
12541 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12542 will be converted to a ZERO_EXTRACT later. */
12543 if (const_op
== 0 && equality_comparison_p
12544 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12545 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12547 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12548 XEXP (XEXP (op0
, 0), 1));
12549 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12553 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12554 zero and X is a comparison and C1 and C2 describe only bits set
12555 in STORE_FLAG_VALUE, we can compare with X. */
12556 if (const_op
== 0 && equality_comparison_p
12557 && mode_width
<= HOST_BITS_PER_WIDE_INT
12558 && CONST_INT_P (XEXP (op0
, 1))
12559 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12560 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12561 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12562 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12564 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12565 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12566 if ((~STORE_FLAG_VALUE
& mask
) == 0
12567 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12568 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12569 && COMPARISON_P (tem
))))
12571 op0
= XEXP (XEXP (op0
, 0), 0);
12576 /* If we are doing an equality comparison of an AND of a bit equal
12577 to the sign bit, replace this with a LT or GE comparison of
12578 the underlying value. */
12579 if (equality_comparison_p
12581 && CONST_INT_P (XEXP (op0
, 1))
12582 && mode_width
<= HOST_BITS_PER_WIDE_INT
12583 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12584 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12586 op0
= XEXP (op0
, 0);
12587 code
= (code
== EQ
? GE
: LT
);
12591 /* If this AND operation is really a ZERO_EXTEND from a narrower
12592 mode, the constant fits within that mode, and this is either an
12593 equality or unsigned comparison, try to do this comparison in
12598 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12599 -> (ne:DI (reg:SI 4) (const_int 0))
12601 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12602 known to hold a value of the required mode the
12603 transformation is invalid. */
12604 if ((equality_comparison_p
|| unsigned_comparison_p
)
12605 && CONST_INT_P (XEXP (op0
, 1))
12606 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12607 & GET_MODE_MASK (mode
))
12609 && const_op
>> i
== 0
12610 && int_mode_for_size (i
, 1).exists (&tmode
))
12612 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12616 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12617 fits in both M1 and M2 and the SUBREG is either paradoxical
12618 or represents the low part, permute the SUBREG and the AND
12620 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12621 && CONST_INT_P (XEXP (op0
, 1)))
12623 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12624 /* Require an integral mode, to avoid creating something like
12626 if ((is_a
<scalar_int_mode
>
12627 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12628 /* It is unsafe to commute the AND into the SUBREG if the
12629 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12630 not defined. As originally written the upper bits
12631 have a defined value due to the AND operation.
12632 However, if we commute the AND inside the SUBREG then
12633 they no longer have defined values and the meaning of
12634 the code has been changed.
12635 Also C1 should not change value in the smaller mode,
12636 see PR67028 (a positive C1 can become negative in the
12637 smaller mode, so that the AND does no longer mask the
12639 && ((WORD_REGISTER_OPERATIONS
12640 && mode_width
> GET_MODE_PRECISION (tmode
)
12641 && mode_width
<= BITS_PER_WORD
12642 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12643 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12644 && subreg_lowpart_p (XEXP (op0
, 0))))
12645 && mode_width
<= HOST_BITS_PER_WIDE_INT
12646 && HWI_COMPUTABLE_MODE_P (tmode
)
12647 && (c1
& ~mask
) == 0
12648 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12650 && c1
!= GET_MODE_MASK (tmode
))
12652 op0
= simplify_gen_binary (AND
, tmode
,
12653 SUBREG_REG (XEXP (op0
, 0)),
12654 gen_int_mode (c1
, tmode
));
12655 op0
= gen_lowpart (mode
, op0
);
12660 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12661 if (const_op
== 0 && equality_comparison_p
12662 && XEXP (op0
, 1) == const1_rtx
12663 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12665 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12666 XEXP (XEXP (op0
, 0), 0), 1);
12667 code
= (code
== NE
? EQ
: NE
);
12671 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12672 (eq (and (lshiftrt X) 1) 0).
12673 Also handle the case where (not X) is expressed using xor. */
12674 if (const_op
== 0 && equality_comparison_p
12675 && XEXP (op0
, 1) == const1_rtx
12676 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12678 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12679 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12681 if (GET_CODE (shift_op
) == NOT
12682 || (GET_CODE (shift_op
) == XOR
12683 && CONST_INT_P (XEXP (shift_op
, 1))
12684 && CONST_INT_P (shift_count
)
12685 && HWI_COMPUTABLE_MODE_P (mode
)
12686 && (UINTVAL (XEXP (shift_op
, 1))
12687 == HOST_WIDE_INT_1U
12688 << INTVAL (shift_count
))))
12691 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12692 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12693 code
= (code
== NE
? EQ
: NE
);
12700 /* If we have (compare (ashift FOO N) (const_int C)) and
12701 the high order N bits of FOO (N+1 if an inequality comparison)
12702 are known to be zero, we can do this by comparing FOO with C
12703 shifted right N bits so long as the low-order N bits of C are
12705 if (CONST_INT_P (XEXP (op0
, 1))
12706 && INTVAL (XEXP (op0
, 1)) >= 0
12707 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12708 < HOST_BITS_PER_WIDE_INT
)
12709 && (((unsigned HOST_WIDE_INT
) const_op
12710 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12712 && mode_width
<= HOST_BITS_PER_WIDE_INT
12713 && (nonzero_bits (XEXP (op0
, 0), mode
)
12714 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12715 + ! equality_comparison_p
))) == 0)
12717 /* We must perform a logical shift, not an arithmetic one,
12718 as we want the top N bits of C to be zero. */
12719 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12721 temp
>>= INTVAL (XEXP (op0
, 1));
12722 op1
= gen_int_mode (temp
, mode
);
12723 op0
= XEXP (op0
, 0);
12727 /* If we are doing a sign bit comparison, it means we are testing
12728 a particular bit. Convert it to the appropriate AND. */
12729 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12730 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12732 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12735 - INTVAL (XEXP (op0
, 1)))));
12736 code
= (code
== LT
? NE
: EQ
);
12740 /* If this an equality comparison with zero and we are shifting
12741 the low bit to the sign bit, we can convert this to an AND of the
12743 if (const_op
== 0 && equality_comparison_p
12744 && CONST_INT_P (XEXP (op0
, 1))
12745 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12747 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12753 /* If this is an equality comparison with zero, we can do this
12754 as a logical shift, which might be much simpler. */
12755 if (equality_comparison_p
&& const_op
== 0
12756 && CONST_INT_P (XEXP (op0
, 1)))
12758 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12760 INTVAL (XEXP (op0
, 1)));
12764 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12765 do the comparison in a narrower mode. */
12766 if (! unsigned_comparison_p
12767 && CONST_INT_P (XEXP (op0
, 1))
12768 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12769 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12770 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12772 && (((unsigned HOST_WIDE_INT
) const_op
12773 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12774 <= GET_MODE_MASK (tmode
)))
12776 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12780 /* Likewise if OP0 is a PLUS of a sign extension with a
12781 constant, which is usually represented with the PLUS
12782 between the shifts. */
12783 if (! unsigned_comparison_p
12784 && CONST_INT_P (XEXP (op0
, 1))
12785 && GET_CODE (XEXP (op0
, 0)) == PLUS
12786 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12787 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12788 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12789 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12791 && (((unsigned HOST_WIDE_INT
) const_op
12792 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12793 <= GET_MODE_MASK (tmode
)))
12795 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12796 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12797 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12798 add_const
, XEXP (op0
, 1));
12800 op0
= simplify_gen_binary (PLUS
, tmode
,
12801 gen_lowpart (tmode
, inner
),
12808 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12809 the low order N bits of FOO are known to be zero, we can do this
12810 by comparing FOO with C shifted left N bits so long as no
12811 overflow occurs. Even if the low order N bits of FOO aren't known
12812 to be zero, if the comparison is >= or < we can use the same
12813 optimization and for > or <= by setting all the low
12814 order N bits in the comparison constant. */
12815 if (CONST_INT_P (XEXP (op0
, 1))
12816 && INTVAL (XEXP (op0
, 1)) > 0
12817 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12818 && mode_width
<= HOST_BITS_PER_WIDE_INT
12819 && (((unsigned HOST_WIDE_INT
) const_op
12820 + (GET_CODE (op0
) != LSHIFTRT
12821 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12824 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12826 unsigned HOST_WIDE_INT low_bits
12827 = (nonzero_bits (XEXP (op0
, 0), mode
)
12828 & ((HOST_WIDE_INT_1U
12829 << INTVAL (XEXP (op0
, 1))) - 1));
12830 if (low_bits
== 0 || !equality_comparison_p
)
12832 /* If the shift was logical, then we must make the condition
12834 if (GET_CODE (op0
) == LSHIFTRT
)
12835 code
= unsigned_condition (code
);
12837 const_op
= (unsigned HOST_WIDE_INT
) const_op
12838 << INTVAL (XEXP (op0
, 1));
12840 && (code
== GT
|| code
== GTU
12841 || code
== LE
|| code
== LEU
))
12843 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12844 op1
= GEN_INT (const_op
);
12845 op0
= XEXP (op0
, 0);
12850 /* If we are using this shift to extract just the sign bit, we
12851 can replace this with an LT or GE comparison. */
12853 && (equality_comparison_p
|| sign_bit_comparison_p
)
12854 && CONST_INT_P (XEXP (op0
, 1))
12855 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12857 op0
= XEXP (op0
, 0);
12858 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12870 /* Now make any compound operations involved in this comparison. Then,
12871 check for an outmost SUBREG on OP0 that is not doing anything or is
12872 paradoxical. The latter transformation must only be performed when
12873 it is known that the "extra" bits will be the same in op0 and op1 or
12874 that they don't matter. There are three cases to consider:
12876 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12877 care bits and we can assume they have any convenient value. So
12878 making the transformation is safe.
12880 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12881 In this case the upper bits of op0 are undefined. We should not make
12882 the simplification in that case as we do not know the contents of
12885 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12886 In that case we know those bits are zeros or ones. We must also be
12887 sure that they are the same as the upper bits of op1.
12889 We can never remove a SUBREG for a non-equality comparison because
12890 the sign bit is in a different place in the underlying object. */
12892 rtx_code op0_mco_code
= SET
;
12893 if (op1
== const0_rtx
)
12894 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12896 op0
= make_compound_operation (op0
, op0_mco_code
);
12897 op1
= make_compound_operation (op1
, SET
);
12899 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12900 && is_int_mode (GET_MODE (op0
), &mode
)
12901 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12902 && (code
== NE
|| code
== EQ
))
12904 if (paradoxical_subreg_p (op0
))
12906 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12908 if (REG_P (SUBREG_REG (op0
)))
12910 op0
= SUBREG_REG (op0
);
12911 op1
= gen_lowpart (inner_mode
, op1
);
12914 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12915 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12916 & ~GET_MODE_MASK (mode
)) == 0)
12918 tem
= gen_lowpart (inner_mode
, op1
);
12920 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
12921 op0
= SUBREG_REG (op0
), op1
= tem
;
12925 /* We now do the opposite procedure: Some machines don't have compare
12926 insns in all modes. If OP0's mode is an integer mode smaller than a
12927 word and we can't do a compare in that mode, see if there is a larger
12928 mode for which we can do the compare. There are a number of cases in
12929 which we can use the wider mode. */
12931 if (is_int_mode (GET_MODE (op0
), &mode
)
12932 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12933 && ! have_insn_for (COMPARE
, mode
))
12934 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
12936 tmode
= tmode_iter
.require ();
12937 if (!HWI_COMPUTABLE_MODE_P (tmode
))
12939 if (have_insn_for (COMPARE
, tmode
))
12943 /* If this is a test for negative, we can make an explicit
12944 test of the sign bit. Test this first so we can use
12945 a paradoxical subreg to extend OP0. */
12947 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12948 && HWI_COMPUTABLE_MODE_P (mode
))
12950 unsigned HOST_WIDE_INT sign
12951 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12952 op0
= simplify_gen_binary (AND
, tmode
,
12953 gen_lowpart (tmode
, op0
),
12954 gen_int_mode (sign
, tmode
));
12955 code
= (code
== LT
) ? NE
: EQ
;
12959 /* If the only nonzero bits in OP0 and OP1 are those in the
12960 narrower mode and this is an equality or unsigned comparison,
12961 we can use the wider mode. Similarly for sign-extended
12962 values, in which case it is true for all comparisons. */
12963 zero_extended
= ((code
== EQ
|| code
== NE
12964 || code
== GEU
|| code
== GTU
12965 || code
== LEU
|| code
== LTU
)
12966 && (nonzero_bits (op0
, tmode
)
12967 & ~GET_MODE_MASK (mode
)) == 0
12968 && ((CONST_INT_P (op1
)
12969 || (nonzero_bits (op1
, tmode
)
12970 & ~GET_MODE_MASK (mode
)) == 0)));
12973 || ((num_sign_bit_copies (op0
, tmode
)
12974 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12975 - GET_MODE_PRECISION (mode
)))
12976 && (num_sign_bit_copies (op1
, tmode
)
12977 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12978 - GET_MODE_PRECISION (mode
)))))
12980 /* If OP0 is an AND and we don't have an AND in MODE either,
12981 make a new AND in the proper mode. */
12982 if (GET_CODE (op0
) == AND
12983 && !have_insn_for (AND
, mode
))
12984 op0
= simplify_gen_binary (AND
, tmode
,
12985 gen_lowpart (tmode
,
12987 gen_lowpart (tmode
,
12993 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
12995 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13000 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13002 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13011 /* We may have changed the comparison operands. Re-canonicalize. */
13012 if (swap_commutative_operands_p (op0
, op1
))
13014 std::swap (op0
, op1
);
13015 code
= swap_condition (code
);
13018 /* If this machine only supports a subset of valid comparisons, see if we
13019 can convert an unsupported one into a supported one. */
13020 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
13028 /* Utility function for record_value_for_reg. Count number of
13033 enum rtx_code code
= GET_CODE (x
);
13037 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
13038 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
13040 rtx x0
= XEXP (x
, 0);
13041 rtx x1
= XEXP (x
, 1);
13044 return 1 + 2 * count_rtxs (x0
);
13046 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13047 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13048 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13049 return 2 + 2 * count_rtxs (x0
)
13050 + count_rtxs (x
== XEXP (x1
, 0)
13051 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13053 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13054 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13055 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13056 return 2 + 2 * count_rtxs (x1
)
13057 + count_rtxs (x
== XEXP (x0
, 0)
13058 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13061 fmt
= GET_RTX_FORMAT (code
);
13062 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13064 ret
+= count_rtxs (XEXP (x
, i
));
13065 else if (fmt
[i
] == 'E')
13066 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13067 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13072 /* Utility function for following routine. Called when X is part of a value
13073 being stored into last_set_value. Sets last_set_table_tick
13074 for each register mentioned. Similar to mention_regs in cse.c */
13077 update_table_tick (rtx x
)
13079 enum rtx_code code
= GET_CODE (x
);
13080 const char *fmt
= GET_RTX_FORMAT (code
);
13085 unsigned int regno
= REGNO (x
);
13086 unsigned int endregno
= END_REGNO (x
);
13089 for (r
= regno
; r
< endregno
; r
++)
13091 reg_stat_type
*rsp
= ®_stat
[r
];
13092 rsp
->last_set_table_tick
= label_tick
;
13098 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13101 /* Check for identical subexpressions. If x contains
13102 identical subexpression we only have to traverse one of
13104 if (i
== 0 && ARITHMETIC_P (x
))
13106 /* Note that at this point x1 has already been
13108 rtx x0
= XEXP (x
, 0);
13109 rtx x1
= XEXP (x
, 1);
13111 /* If x0 and x1 are identical then there is no need to
13116 /* If x0 is identical to a subexpression of x1 then while
13117 processing x1, x0 has already been processed. Thus we
13118 are done with x. */
13119 if (ARITHMETIC_P (x1
)
13120 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13123 /* If x1 is identical to a subexpression of x0 then we
13124 still have to process the rest of x0. */
13125 if (ARITHMETIC_P (x0
)
13126 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13128 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13133 update_table_tick (XEXP (x
, i
));
13135 else if (fmt
[i
] == 'E')
13136 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13137 update_table_tick (XVECEXP (x
, i
, j
));
13140 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13141 are saying that the register is clobbered and we no longer know its
13142 value. If INSN is zero, don't update reg_stat[].last_set; this is
13143 only permitted with VALUE also zero and is used to invalidate the
13147 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13149 unsigned int regno
= REGNO (reg
);
13150 unsigned int endregno
= END_REGNO (reg
);
13152 reg_stat_type
*rsp
;
13154 /* If VALUE contains REG and we have a previous value for REG, substitute
13155 the previous value. */
13156 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13160 /* Set things up so get_last_value is allowed to see anything set up to
13162 subst_low_luid
= DF_INSN_LUID (insn
);
13163 tem
= get_last_value (reg
);
13165 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13166 it isn't going to be useful and will take a lot of time to process,
13167 so just use the CLOBBER. */
13171 if (ARITHMETIC_P (tem
)
13172 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13173 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13174 tem
= XEXP (tem
, 0);
13175 else if (count_occurrences (value
, reg
, 1) >= 2)
13177 /* If there are two or more occurrences of REG in VALUE,
13178 prevent the value from growing too much. */
13179 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
13180 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13183 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13187 /* For each register modified, show we don't know its value, that
13188 we don't know about its bitwise content, that its value has been
13189 updated, and that we don't know the location of the death of the
13191 for (i
= regno
; i
< endregno
; i
++)
13193 rsp
= ®_stat
[i
];
13196 rsp
->last_set
= insn
;
13198 rsp
->last_set_value
= 0;
13199 rsp
->last_set_mode
= VOIDmode
;
13200 rsp
->last_set_nonzero_bits
= 0;
13201 rsp
->last_set_sign_bit_copies
= 0;
13202 rsp
->last_death
= 0;
13203 rsp
->truncated_to_mode
= VOIDmode
;
13206 /* Mark registers that are being referenced in this value. */
13208 update_table_tick (value
);
13210 /* Now update the status of each register being set.
13211 If someone is using this register in this block, set this register
13212 to invalid since we will get confused between the two lives in this
13213 basic block. This makes using this register always invalid. In cse, we
13214 scan the table to invalidate all entries using this register, but this
13215 is too much work for us. */
13217 for (i
= regno
; i
< endregno
; i
++)
13219 rsp
= ®_stat
[i
];
13220 rsp
->last_set_label
= label_tick
;
13222 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13223 rsp
->last_set_invalid
= 1;
13225 rsp
->last_set_invalid
= 0;
13228 /* The value being assigned might refer to X (like in "x++;"). In that
13229 case, we must replace it with (clobber (const_int 0)) to prevent
13231 rsp
= ®_stat
[regno
];
13232 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13234 value
= copy_rtx (value
);
13235 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13239 /* For the main register being modified, update the value, the mode, the
13240 nonzero bits, and the number of sign bit copies. */
13242 rsp
->last_set_value
= value
;
13246 machine_mode mode
= GET_MODE (reg
);
13247 subst_low_luid
= DF_INSN_LUID (insn
);
13248 rsp
->last_set_mode
= mode
;
13249 if (GET_MODE_CLASS (mode
) == MODE_INT
13250 && HWI_COMPUTABLE_MODE_P (mode
))
13251 mode
= nonzero_bits_mode
;
13252 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13253 rsp
->last_set_sign_bit_copies
13254 = num_sign_bit_copies (value
, GET_MODE (reg
));
13258 /* Called via note_stores from record_dead_and_set_regs to handle one
13259 SET or CLOBBER in an insn. DATA is the instruction in which the
13260 set is occurring. */
13263 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13265 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13267 if (GET_CODE (dest
) == SUBREG
)
13268 dest
= SUBREG_REG (dest
);
13270 if (!record_dead_insn
)
13273 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13279 /* If we are setting the whole register, we know its value. Otherwise
13280 show that we don't know the value. We can handle a SUBREG if it's
13281 the low part, but we must be careful with paradoxical SUBREGs on
13282 RISC architectures because we cannot strip e.g. an extension around
13283 a load and record the naked load since the RTL middle-end considers
13284 that the upper bits are defined according to LOAD_EXTEND_OP. */
13285 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13286 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13287 else if (GET_CODE (setter
) == SET
13288 && GET_CODE (SET_DEST (setter
)) == SUBREG
13289 && SUBREG_REG (SET_DEST (setter
)) == dest
13290 && known_le (GET_MODE_PRECISION (GET_MODE (dest
)),
13292 && subreg_lowpart_p (SET_DEST (setter
)))
13293 record_value_for_reg (dest
, record_dead_insn
,
13294 WORD_REGISTER_OPERATIONS
13295 && paradoxical_subreg_p (SET_DEST (setter
))
13297 : gen_lowpart (GET_MODE (dest
),
13298 SET_SRC (setter
)));
13300 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13302 else if (MEM_P (dest
)
13303 /* Ignore pushes, they clobber nothing. */
13304 && ! push_operand (dest
, GET_MODE (dest
)))
13305 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13308 /* Update the records of when each REG was most recently set or killed
13309 for the things done by INSN. This is the last thing done in processing
13310 INSN in the combiner loop.
13312 We update reg_stat[], in particular fields last_set, last_set_value,
13313 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13314 last_death, and also the similar information mem_last_set (which insn
13315 most recently modified memory) and last_call_luid (which insn was the
13316 most recent subroutine call). */
13319 record_dead_and_set_regs (rtx_insn
*insn
)
13324 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13326 if (REG_NOTE_KIND (link
) == REG_DEAD
13327 && REG_P (XEXP (link
, 0)))
13329 unsigned int regno
= REGNO (XEXP (link
, 0));
13330 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13332 for (i
= regno
; i
< endregno
; i
++)
13334 reg_stat_type
*rsp
;
13336 rsp
= ®_stat
[i
];
13337 rsp
->last_death
= insn
;
13340 else if (REG_NOTE_KIND (link
) == REG_INC
)
13341 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13346 hard_reg_set_iterator hrsi
;
13347 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13349 reg_stat_type
*rsp
;
13351 rsp
= ®_stat
[i
];
13352 rsp
->last_set_invalid
= 1;
13353 rsp
->last_set
= insn
;
13354 rsp
->last_set_value
= 0;
13355 rsp
->last_set_mode
= VOIDmode
;
13356 rsp
->last_set_nonzero_bits
= 0;
13357 rsp
->last_set_sign_bit_copies
= 0;
13358 rsp
->last_death
= 0;
13359 rsp
->truncated_to_mode
= VOIDmode
;
13362 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13364 /* We can't combine into a call pattern. Remember, though, that
13365 the return value register is set at this LUID. We could
13366 still replace a register with the return value from the
13367 wrong subroutine call! */
13368 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13371 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13374 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13375 register present in the SUBREG, so for each such SUBREG go back and
13376 adjust nonzero and sign bit information of the registers that are
13377 known to have some zero/sign bits set.
13379 This is needed because when combine blows the SUBREGs away, the
13380 information on zero/sign bits is lost and further combines can be
13381 missed because of that. */
13384 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13386 struct insn_link
*links
;
13388 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13389 machine_mode mode
= GET_MODE (subreg
);
13391 if (!HWI_COMPUTABLE_MODE_P (mode
))
13394 for (links
= LOG_LINKS (insn
); links
;)
13396 reg_stat_type
*rsp
;
13398 insn
= links
->insn
;
13399 set
= single_set (insn
);
13401 if (! set
|| !REG_P (SET_DEST (set
))
13402 || REGNO (SET_DEST (set
)) != regno
13403 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13405 links
= links
->next
;
13409 rsp
= ®_stat
[regno
];
13410 if (rsp
->last_set
== insn
)
13412 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13413 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13416 if (REG_P (SET_SRC (set
)))
13418 regno
= REGNO (SET_SRC (set
));
13419 links
= LOG_LINKS (insn
);
13426 /* Check if X, a register, is known to contain a value already
13427 truncated to MODE. In this case we can use a subreg to refer to
13428 the truncated value even though in the generic case we would need
13429 an explicit truncation. */
13432 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13434 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13435 machine_mode truncated
= rsp
->truncated_to_mode
;
13438 || rsp
->truncation_label
< label_tick_ebb_start
)
13440 if (!partial_subreg_p (mode
, truncated
))
13442 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13447 /* If X is a hard reg or a subreg record the mode that the register is
13448 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13449 able to turn a truncate into a subreg using this information. Return true
13450 if traversing X is complete. */
13453 record_truncated_value (rtx x
)
13455 machine_mode truncated_mode
;
13456 reg_stat_type
*rsp
;
13458 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13460 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13461 truncated_mode
= GET_MODE (x
);
13463 if (!partial_subreg_p (truncated_mode
, original_mode
))
13466 truncated_mode
= GET_MODE (x
);
13467 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13470 x
= SUBREG_REG (x
);
13472 /* ??? For hard-regs we now record everything. We might be able to
13473 optimize this using last_set_mode. */
13474 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13475 truncated_mode
= GET_MODE (x
);
13479 rsp
= ®_stat
[REGNO (x
)];
13480 if (rsp
->truncated_to_mode
== 0
13481 || rsp
->truncation_label
< label_tick_ebb_start
13482 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13484 rsp
->truncated_to_mode
= truncated_mode
;
13485 rsp
->truncation_label
= label_tick
;
13491 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13492 the modes they are used in. This can help truning TRUNCATEs into
13496 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13498 subrtx_var_iterator::array_type array
;
13499 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13500 if (record_truncated_value (*iter
))
13501 iter
.skip_subrtxes ();
13504 /* Scan X for promoted SUBREGs. For each one found,
13505 note what it implies to the registers used in it. */
13508 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13510 if (GET_CODE (x
) == SUBREG
13511 && SUBREG_PROMOTED_VAR_P (x
)
13512 && REG_P (SUBREG_REG (x
)))
13513 record_promoted_value (insn
, x
);
13516 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13519 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13523 check_promoted_subreg (insn
, XEXP (x
, i
));
13527 if (XVEC (x
, i
) != 0)
13528 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13529 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13535 /* Verify that all the registers and memory references mentioned in *LOC are
13536 still valid. *LOC was part of a value set in INSN when label_tick was
13537 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13538 the invalid references with (clobber (const_int 0)) and return 1. This
13539 replacement is useful because we often can get useful information about
13540 the form of a value (e.g., if it was produced by a shift that always
13541 produces -1 or 0) even though we don't know exactly what registers it
13542 was produced from. */
13545 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13548 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13549 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13554 unsigned int regno
= REGNO (x
);
13555 unsigned int endregno
= END_REGNO (x
);
13558 for (j
= regno
; j
< endregno
; j
++)
13560 reg_stat_type
*rsp
= ®_stat
[j
];
13561 if (rsp
->last_set_invalid
13562 /* If this is a pseudo-register that was only set once and not
13563 live at the beginning of the function, it is always valid. */
13564 || (! (regno
>= FIRST_PSEUDO_REGISTER
13565 && regno
< reg_n_sets_max
13566 && REG_N_SETS (regno
) == 1
13567 && (!REGNO_REG_SET_P
13568 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13570 && rsp
->last_set_label
> tick
))
13573 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13580 /* If this is a memory reference, make sure that there were no stores after
13581 it that might have clobbered the value. We don't have alias info, so we
13582 assume any store invalidates it. Moreover, we only have local UIDs, so
13583 we also assume that there were stores in the intervening basic blocks. */
13584 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13585 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13588 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13592 for (i
= 0; i
< len
; i
++)
13596 /* Check for identical subexpressions. If x contains
13597 identical subexpression we only have to traverse one of
13599 if (i
== 1 && ARITHMETIC_P (x
))
13601 /* Note that at this point x0 has already been checked
13602 and found valid. */
13603 rtx x0
= XEXP (x
, 0);
13604 rtx x1
= XEXP (x
, 1);
13606 /* If x0 and x1 are identical then x is also valid. */
13610 /* If x1 is identical to a subexpression of x0 then
13611 while checking x0, x1 has already been checked. Thus
13612 it is valid and so as x. */
13613 if (ARITHMETIC_P (x0
)
13614 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13617 /* If x0 is identical to a subexpression of x1 then x is
13618 valid iff the rest of x1 is valid. */
13619 if (ARITHMETIC_P (x1
)
13620 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13622 get_last_value_validate (&XEXP (x1
,
13623 x0
== XEXP (x1
, 0) ? 1 : 0),
13624 insn
, tick
, replace
);
13627 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13631 else if (fmt
[i
] == 'E')
13632 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13633 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13634 insn
, tick
, replace
) == 0)
13638 /* If we haven't found a reason for it to be invalid, it is valid. */
13642 /* Get the last value assigned to X, if known. Some registers
13643 in the value may be replaced with (clobber (const_int 0)) if their value
13644 is known longer known reliably. */
13647 get_last_value (const_rtx x
)
13649 unsigned int regno
;
13651 reg_stat_type
*rsp
;
13653 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13654 then convert it to the desired mode. If this is a paradoxical SUBREG,
13655 we cannot predict what values the "extra" bits might have. */
13656 if (GET_CODE (x
) == SUBREG
13657 && subreg_lowpart_p (x
)
13658 && !paradoxical_subreg_p (x
)
13659 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13660 return gen_lowpart (GET_MODE (x
), value
);
13666 rsp
= ®_stat
[regno
];
13667 value
= rsp
->last_set_value
;
13669 /* If we don't have a value, or if it isn't for this basic block and
13670 it's either a hard register, set more than once, or it's a live
13671 at the beginning of the function, return 0.
13673 Because if it's not live at the beginning of the function then the reg
13674 is always set before being used (is never used without being set).
13675 And, if it's set only once, and it's always set before use, then all
13676 uses must have the same last value, even if it's not from this basic
13680 || (rsp
->last_set_label
< label_tick_ebb_start
13681 && (regno
< FIRST_PSEUDO_REGISTER
13682 || regno
>= reg_n_sets_max
13683 || REG_N_SETS (regno
) != 1
13685 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13688 /* If the value was set in a later insn than the ones we are processing,
13689 we can't use it even if the register was only set once. */
13690 if (rsp
->last_set_label
== label_tick
13691 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13694 /* If fewer bits were set than what we are asked for now, we cannot use
13696 if (maybe_lt (GET_MODE_PRECISION (rsp
->last_set_mode
),
13697 GET_MODE_PRECISION (GET_MODE (x
))))
13700 /* If the value has all its registers valid, return it. */
13701 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13704 /* Otherwise, make a copy and replace any invalid register with
13705 (clobber (const_int 0)). If that fails for some reason, return 0. */
13707 value
= copy_rtx (value
);
13708 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13714 /* Define three variables used for communication between the following
13717 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13718 static int reg_dead_flag
;
13720 /* Function called via note_stores from reg_dead_at_p.
13722 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13723 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13726 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13728 unsigned int regno
, endregno
;
13733 regno
= REGNO (dest
);
13734 endregno
= END_REGNO (dest
);
13735 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13736 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13739 /* Return nonzero if REG is known to be dead at INSN.
13741 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13742 referencing REG, it is dead. If we hit a SET referencing REG, it is
13743 live. Otherwise, see if it is live or dead at the start of the basic
13744 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13745 must be assumed to be always live. */
13748 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13753 /* Set variables for reg_dead_at_p_1. */
13754 reg_dead_regno
= REGNO (reg
);
13755 reg_dead_endregno
= END_REGNO (reg
);
13759 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13760 we allow the machine description to decide whether use-and-clobber
13761 patterns are OK. */
13762 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13764 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13765 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13769 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13770 beginning of basic block. */
13771 block
= BLOCK_FOR_INSN (insn
);
13776 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13779 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13781 return reg_dead_flag
== 1 ? 1 : 0;
13783 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13787 if (insn
== BB_HEAD (block
))
13790 insn
= PREV_INSN (insn
);
13793 /* Look at live-in sets for the basic block that we were in. */
13794 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13795 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13801 /* Note hard registers in X that are used. */
13804 mark_used_regs_combine (rtx x
)
13806 RTX_CODE code
= GET_CODE (x
);
13807 unsigned int regno
;
13818 case ADDR_DIFF_VEC
:
13820 /* CC0 must die in the insn after it is set, so we don't need to take
13821 special note of it here. */
13826 /* If we are clobbering a MEM, mark any hard registers inside the
13827 address as used. */
13828 if (MEM_P (XEXP (x
, 0)))
13829 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13834 /* A hard reg in a wide mode may really be multiple registers.
13835 If so, mark all of them just like the first. */
13836 if (regno
< FIRST_PSEUDO_REGISTER
)
13838 /* None of this applies to the stack, frame or arg pointers. */
13839 if (regno
== STACK_POINTER_REGNUM
13840 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13841 && regno
== HARD_FRAME_POINTER_REGNUM
)
13842 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13843 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13844 || regno
== FRAME_POINTER_REGNUM
)
13847 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13853 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13855 rtx testreg
= SET_DEST (x
);
13857 while (GET_CODE (testreg
) == SUBREG
13858 || GET_CODE (testreg
) == ZERO_EXTRACT
13859 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13860 testreg
= XEXP (testreg
, 0);
13862 if (MEM_P (testreg
))
13863 mark_used_regs_combine (XEXP (testreg
, 0));
13865 mark_used_regs_combine (SET_SRC (x
));
13873 /* Recursively scan the operands of this expression. */
13876 const char *fmt
= GET_RTX_FORMAT (code
);
13878 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13881 mark_used_regs_combine (XEXP (x
, i
));
13882 else if (fmt
[i
] == 'E')
13886 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13887 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13893 /* Remove register number REGNO from the dead registers list of INSN.
13895 Return the note used to record the death, if there was one. */
13898 remove_death (unsigned int regno
, rtx_insn
*insn
)
13900 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13903 remove_note (insn
, note
);
13908 /* For each register (hardware or pseudo) used within expression X, if its
13909 death is in an instruction with luid between FROM_LUID (inclusive) and
13910 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13911 list headed by PNOTES.
13913 That said, don't move registers killed by maybe_kill_insn.
13915 This is done when X is being merged by combination into TO_INSN. These
13916 notes will then be distributed as needed. */
13919 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13924 enum rtx_code code
= GET_CODE (x
);
13928 unsigned int regno
= REGNO (x
);
13929 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13931 /* If we do not know where the register died, it may still die between
13932 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13933 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
13935 rtx_insn
*insn
= prev_real_nondebug_insn (to_insn
);
13937 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
13938 && DF_INSN_LUID (insn
) >= from_luid
)
13940 if (dead_or_set_regno_p (insn
, regno
))
13942 if (find_regno_note (insn
, REG_DEAD
, regno
))
13947 insn
= prev_real_nondebug_insn (insn
);
13951 /* Don't move the register if it gets killed in between from and to. */
13952 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13953 && ! reg_referenced_p (x
, maybe_kill_insn
))
13957 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13958 && DF_INSN_LUID (where_dead
) >= from_luid
13959 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13961 rtx note
= remove_death (regno
, where_dead
);
13963 /* It is possible for the call above to return 0. This can occur
13964 when last_death points to I2 or I1 that we combined with.
13965 In that case make a new note.
13967 We must also check for the case where X is a hard register
13968 and NOTE is a death note for a range of hard registers
13969 including X. In that case, we must put REG_DEAD notes for
13970 the remaining registers in place of NOTE. */
13972 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13973 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
13975 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13976 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13977 unsigned int ourend
= END_REGNO (x
);
13980 for (i
= deadregno
; i
< deadend
; i
++)
13981 if (i
< regno
|| i
>= ourend
)
13982 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13985 /* If we didn't find any note, or if we found a REG_DEAD note that
13986 covers only part of the given reg, and we have a multi-reg hard
13987 register, then to be safe we must check for REG_DEAD notes
13988 for each register other than the first. They could have
13989 their own REG_DEAD notes lying around. */
13990 else if ((note
== 0
13992 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
13994 && regno
< FIRST_PSEUDO_REGISTER
13995 && REG_NREGS (x
) > 1)
13997 unsigned int ourend
= END_REGNO (x
);
13998 unsigned int i
, offset
;
14002 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
14006 for (i
= regno
+ offset
; i
< ourend
; i
++)
14007 move_deaths (regno_reg_rtx
[i
],
14008 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
14011 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
14013 XEXP (note
, 1) = *pnotes
;
14017 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
14023 else if (GET_CODE (x
) == SET
)
14025 rtx dest
= SET_DEST (x
);
14027 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14029 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14030 that accesses one word of a multi-word item, some
14031 piece of everything register in the expression is used by
14032 this insn, so remove any old death. */
14033 /* ??? So why do we test for equality of the sizes? */
14035 if (GET_CODE (dest
) == ZERO_EXTRACT
14036 || GET_CODE (dest
) == STRICT_LOW_PART
14037 || (GET_CODE (dest
) == SUBREG
14038 && !read_modify_subreg_p (dest
)))
14040 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14044 /* If this is some other SUBREG, we know it replaces the entire
14045 value, so use that as the destination. */
14046 if (GET_CODE (dest
) == SUBREG
)
14047 dest
= SUBREG_REG (dest
);
14049 /* If this is a MEM, adjust deaths of anything used in the address.
14050 For a REG (the only other possibility), the entire value is
14051 being replaced so the old value is not used in this insn. */
14054 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14059 else if (GET_CODE (x
) == CLOBBER
)
14062 len
= GET_RTX_LENGTH (code
);
14063 fmt
= GET_RTX_FORMAT (code
);
14065 for (i
= 0; i
< len
; i
++)
14070 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14071 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14074 else if (fmt
[i
] == 'e')
14075 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14079 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14080 pattern of an insn. X must be a REG. */
14083 reg_bitfield_target_p (rtx x
, rtx body
)
14087 if (GET_CODE (body
) == SET
)
14089 rtx dest
= SET_DEST (body
);
14091 unsigned int regno
, tregno
, endregno
, endtregno
;
14093 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14094 target
= XEXP (dest
, 0);
14095 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14096 target
= SUBREG_REG (XEXP (dest
, 0));
14100 if (GET_CODE (target
) == SUBREG
)
14101 target
= SUBREG_REG (target
);
14103 if (!REG_P (target
))
14106 tregno
= REGNO (target
), regno
= REGNO (x
);
14107 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14108 return target
== x
;
14110 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14111 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14113 return endregno
> tregno
&& regno
< endtregno
;
14116 else if (GET_CODE (body
) == PARALLEL
)
14117 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14118 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14124 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14125 as appropriate. I3 and I2 are the insns resulting from the combination
14126 insns including FROM (I2 may be zero).
14128 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14129 not need REG_DEAD notes because they are being substituted for. This
14130 saves searching in the most common cases.
14132 Each note in the list is either ignored or placed on some insns, depending
14133 on the type of note. */
14136 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14137 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14139 rtx note
, next_note
;
14141 rtx_insn
*tem_insn
;
14143 for (note
= notes
; note
; note
= next_note
)
14145 rtx_insn
*place
= 0, *place2
= 0;
14147 next_note
= XEXP (note
, 1);
14148 switch (REG_NOTE_KIND (note
))
14152 /* Doesn't matter much where we put this, as long as it's somewhere.
14153 It is preferable to keep these notes on branches, which is most
14154 likely to be i3. */
14158 case REG_NON_LOCAL_GOTO
:
14163 gcc_assert (i2
&& JUMP_P (i2
));
14168 case REG_EH_REGION
:
14169 /* These notes must remain with the call or trapping instruction. */
14172 else if (i2
&& CALL_P (i2
))
14176 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14177 if (may_trap_p (i3
))
14179 else if (i2
&& may_trap_p (i2
))
14181 /* ??? Otherwise assume we've combined things such that we
14182 can now prove that the instructions can't trap. Drop the
14183 note in this case. */
14187 case REG_ARGS_SIZE
:
14188 /* ??? How to distribute between i3-i1. Assume i3 contains the
14189 entire adjustment. Assert i3 contains at least some adjust. */
14190 if (!noop_move_p (i3
))
14192 poly_int64 old_size
, args_size
= get_args_size (note
);
14193 /* fixup_args_size_notes looks at REG_NORETURN note,
14194 so ensure the note is placed there first. */
14198 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14199 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14203 XEXP (n
, 1) = REG_NOTES (i3
);
14204 REG_NOTES (i3
) = n
;
14208 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14209 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14210 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14211 gcc_assert (maybe_ne (old_size
, args_size
)
14213 && !ACCUMULATE_OUTGOING_ARGS
14214 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14221 case REG_CALL_DECL
:
14222 case REG_CALL_NOCF_CHECK
:
14223 /* These notes must remain with the call. It should not be
14224 possible for both I2 and I3 to be a call. */
14229 gcc_assert (i2
&& CALL_P (i2
));
14235 /* Any clobbers for i3 may still exist, and so we must process
14236 REG_UNUSED notes from that insn.
14238 Any clobbers from i2 or i1 can only exist if they were added by
14239 recog_for_combine. In that case, recog_for_combine created the
14240 necessary REG_UNUSED notes. Trying to keep any original
14241 REG_UNUSED notes from these insns can cause incorrect output
14242 if it is for the same register as the original i3 dest.
14243 In that case, we will notice that the register is set in i3,
14244 and then add a REG_UNUSED note for the destination of i3, which
14245 is wrong. However, it is possible to have REG_UNUSED notes from
14246 i2 or i1 for register which were both used and clobbered, so
14247 we keep notes from i2 or i1 if they will turn into REG_DEAD
14250 /* If this register is set or clobbered in I3, put the note there
14251 unless there is one already. */
14252 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14254 if (from_insn
!= i3
)
14257 if (! (REG_P (XEXP (note
, 0))
14258 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14259 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14262 /* Otherwise, if this register is used by I3, then this register
14263 now dies here, so we must put a REG_DEAD note here unless there
14265 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14266 && ! (REG_P (XEXP (note
, 0))
14267 ? find_regno_note (i3
, REG_DEAD
,
14268 REGNO (XEXP (note
, 0)))
14269 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14271 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14275 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14276 but we can't tell which at this point. We must reset any
14277 expectations we had about the value that was previously
14278 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14279 and, if appropriate, restore its previous value, but we
14280 don't have enough information for that at this point. */
14283 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14285 /* Otherwise, if this register is now referenced in i2
14286 then the register used to be modified in one of the
14287 original insns. If it was i3 (say, in an unused
14288 parallel), it's now completely gone, so the note can
14289 be discarded. But if it was modified in i2, i1 or i0
14290 and we still reference it in i2, then we're
14291 referencing the previous value, and since the
14292 register was modified and REG_UNUSED, we know that
14293 the previous value is now dead. So, if we only
14294 reference the register in i2, we change the note to
14295 REG_DEAD, to reflect the previous value. However, if
14296 we're also setting or clobbering the register as
14297 scratch, we know (because the register was not
14298 referenced in i3) that it's unused, just as it was
14299 unused before, and we place the note in i2. */
14300 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14301 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14303 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14304 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14305 if (! (REG_P (XEXP (note
, 0))
14306 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14307 REGNO (XEXP (note
, 0)))
14308 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14319 /* These notes say something about results of an insn. We can
14320 only support them if they used to be on I3 in which case they
14321 remain on I3. Otherwise they are ignored.
14323 If the note refers to an expression that is not a constant, we
14324 must also ignore the note since we cannot tell whether the
14325 equivalence is still true. It might be possible to do
14326 slightly better than this (we only have a problem if I2DEST
14327 or I1DEST is present in the expression), but it doesn't
14328 seem worth the trouble. */
14330 if (from_insn
== i3
14331 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14336 /* These notes say something about how a register is used. They must
14337 be present on any use of the register in I2 or I3. */
14338 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14341 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14350 case REG_LABEL_TARGET
:
14351 case REG_LABEL_OPERAND
:
14352 /* This can show up in several ways -- either directly in the
14353 pattern, or hidden off in the constant pool with (or without?)
14354 a REG_EQUAL note. */
14355 /* ??? Ignore the without-reg_equal-note problem for now. */
14356 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14357 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14358 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14359 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14363 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14364 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14365 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14366 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14374 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14375 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14377 if (place
&& JUMP_P (place
)
14378 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14379 && (JUMP_LABEL (place
) == NULL
14380 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14382 rtx label
= JUMP_LABEL (place
);
14385 JUMP_LABEL (place
) = XEXP (note
, 0);
14386 else if (LABEL_P (label
))
14387 LABEL_NUSES (label
)--;
14390 if (place2
&& JUMP_P (place2
)
14391 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14392 && (JUMP_LABEL (place2
) == NULL
14393 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14395 rtx label
= JUMP_LABEL (place2
);
14398 JUMP_LABEL (place2
) = XEXP (note
, 0);
14399 else if (LABEL_P (label
))
14400 LABEL_NUSES (label
)--;
14406 /* This note says something about the value of a register prior
14407 to the execution of an insn. It is too much trouble to see
14408 if the note is still correct in all situations. It is better
14409 to simply delete it. */
14413 /* If we replaced the right hand side of FROM_INSN with a
14414 REG_EQUAL note, the original use of the dying register
14415 will not have been combined into I3 and I2. In such cases,
14416 FROM_INSN is guaranteed to be the first of the combined
14417 instructions, so we simply need to search back before
14418 FROM_INSN for the previous use or set of this register,
14419 then alter the notes there appropriately.
14421 If the register is used as an input in I3, it dies there.
14422 Similarly for I2, if it is nonzero and adjacent to I3.
14424 If the register is not used as an input in either I3 or I2
14425 and it is not one of the registers we were supposed to eliminate,
14426 there are two possibilities. We might have a non-adjacent I2
14427 or we might have somehow eliminated an additional register
14428 from a computation. For example, we might have had A & B where
14429 we discover that B will always be zero. In this case we will
14430 eliminate the reference to A.
14432 In both cases, we must search to see if we can find a previous
14433 use of A and put the death note there. */
14436 && from_insn
== i2mod
14437 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14438 tem_insn
= from_insn
;
14442 && CALL_P (from_insn
)
14443 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14445 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14447 /* If the new I2 sets the same register that is marked
14448 dead in the note, we do not in general know where to
14449 put the note. One important case we _can_ handle is
14450 when the note comes from I3. */
14451 if (from_insn
== i3
)
14456 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14458 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14459 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14461 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14463 && reg_overlap_mentioned_p (XEXP (note
, 0),
14465 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14466 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14473 basic_block bb
= this_basic_block
;
14475 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14477 if (!NONDEBUG_INSN_P (tem_insn
))
14479 if (tem_insn
== BB_HEAD (bb
))
14484 /* If the register is being set at TEM_INSN, see if that is all
14485 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14486 into a REG_UNUSED note instead. Don't delete sets to
14487 global register vars. */
14488 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14489 || !global_regs
[REGNO (XEXP (note
, 0))])
14490 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14492 rtx set
= single_set (tem_insn
);
14493 rtx inner_dest
= 0;
14494 rtx_insn
*cc0_setter
= NULL
;
14497 for (inner_dest
= SET_DEST (set
);
14498 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14499 || GET_CODE (inner_dest
) == SUBREG
14500 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14501 inner_dest
= XEXP (inner_dest
, 0))
14504 /* Verify that it was the set, and not a clobber that
14505 modified the register.
14507 CC0 targets must be careful to maintain setter/user
14508 pairs. If we cannot delete the setter due to side
14509 effects, mark the user with an UNUSED note instead
14512 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14513 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14515 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14516 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14517 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14519 /* Move the notes and links of TEM_INSN elsewhere.
14520 This might delete other dead insns recursively.
14521 First set the pattern to something that won't use
14523 rtx old_notes
= REG_NOTES (tem_insn
);
14525 PATTERN (tem_insn
) = pc_rtx
;
14526 REG_NOTES (tem_insn
) = NULL
;
14528 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14529 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14530 distribute_links (LOG_LINKS (tem_insn
));
14532 unsigned int regno
= REGNO (XEXP (note
, 0));
14533 reg_stat_type
*rsp
= ®_stat
[regno
];
14534 if (rsp
->last_set
== tem_insn
)
14535 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14537 SET_INSN_DELETED (tem_insn
);
14538 if (tem_insn
== i2
)
14541 /* Delete the setter too. */
14544 PATTERN (cc0_setter
) = pc_rtx
;
14545 old_notes
= REG_NOTES (cc0_setter
);
14546 REG_NOTES (cc0_setter
) = NULL
;
14548 distribute_notes (old_notes
, cc0_setter
,
14550 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14551 distribute_links (LOG_LINKS (cc0_setter
));
14553 SET_INSN_DELETED (cc0_setter
);
14554 if (cc0_setter
== i2
)
14560 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14562 /* If there isn't already a REG_UNUSED note, put one
14563 here. Do not place a REG_DEAD note, even if
14564 the register is also used here; that would not
14565 match the algorithm used in lifetime analysis
14566 and can cause the consistency check in the
14567 scheduler to fail. */
14568 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14569 REGNO (XEXP (note
, 0))))
14574 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14575 || (CALL_P (tem_insn
)
14576 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14580 /* If we are doing a 3->2 combination, and we have a
14581 register which formerly died in i3 and was not used
14582 by i2, which now no longer dies in i3 and is used in
14583 i2 but does not die in i2, and place is between i2
14584 and i3, then we may need to move a link from place to
14586 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14588 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14589 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14591 struct insn_link
*links
= LOG_LINKS (place
);
14592 LOG_LINKS (place
) = NULL
;
14593 distribute_links (links
);
14598 if (tem_insn
== BB_HEAD (bb
))
14604 /* If the register is set or already dead at PLACE, we needn't do
14605 anything with this note if it is still a REG_DEAD note.
14606 We check here if it is set at all, not if is it totally replaced,
14607 which is what `dead_or_set_p' checks, so also check for it being
14610 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14612 unsigned int regno
= REGNO (XEXP (note
, 0));
14613 reg_stat_type
*rsp
= ®_stat
[regno
];
14615 if (dead_or_set_p (place
, XEXP (note
, 0))
14616 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14618 /* Unless the register previously died in PLACE, clear
14619 last_death. [I no longer understand why this is
14621 if (rsp
->last_death
!= place
)
14622 rsp
->last_death
= 0;
14626 rsp
->last_death
= place
;
14628 /* If this is a death note for a hard reg that is occupying
14629 multiple registers, ensure that we are still using all
14630 parts of the object. If we find a piece of the object
14631 that is unused, we must arrange for an appropriate REG_DEAD
14632 note to be added for it. However, we can't just emit a USE
14633 and tag the note to it, since the register might actually
14634 be dead; so we recourse, and the recursive call then finds
14635 the previous insn that used this register. */
14637 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14639 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14640 bool all_used
= true;
14643 for (i
= regno
; i
< endregno
; i
++)
14644 if ((! refers_to_regno_p (i
, PATTERN (place
))
14645 && ! find_regno_fusage (place
, USE
, i
))
14646 || dead_or_set_regno_p (place
, i
))
14654 /* Put only REG_DEAD notes for pieces that are
14655 not already dead or set. */
14657 for (i
= regno
; i
< endregno
;
14658 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14660 rtx piece
= regno_reg_rtx
[i
];
14661 basic_block bb
= this_basic_block
;
14663 if (! dead_or_set_p (place
, piece
)
14664 && ! reg_bitfield_target_p (piece
,
14667 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14670 distribute_notes (new_note
, place
, place
,
14671 NULL
, NULL_RTX
, NULL_RTX
,
14674 else if (! refers_to_regno_p (i
, PATTERN (place
))
14675 && ! find_regno_fusage (place
, USE
, i
))
14676 for (tem_insn
= PREV_INSN (place
); ;
14677 tem_insn
= PREV_INSN (tem_insn
))
14679 if (!NONDEBUG_INSN_P (tem_insn
))
14681 if (tem_insn
== BB_HEAD (bb
))
14685 if (dead_or_set_p (tem_insn
, piece
)
14686 || reg_bitfield_target_p (piece
,
14687 PATTERN (tem_insn
)))
14689 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14702 /* Any other notes should not be present at this point in the
14704 gcc_unreachable ();
14709 XEXP (note
, 1) = REG_NOTES (place
);
14710 REG_NOTES (place
) = note
;
14712 /* Set added_notes_insn to the earliest insn we added a note to. */
14713 if (added_notes_insn
== 0
14714 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14715 added_notes_insn
= place
;
14720 add_shallow_copy_of_reg_note (place2
, note
);
14722 /* Set added_notes_insn to the earliest insn we added a note to. */
14723 if (added_notes_insn
== 0
14724 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14725 added_notes_insn
= place2
;
14730 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14731 I3, I2, and I1 to new locations. This is also called to add a link
14732 pointing at I3 when I3's destination is changed. */
14735 distribute_links (struct insn_link
*links
)
14737 struct insn_link
*link
, *next_link
;
14739 for (link
= links
; link
; link
= next_link
)
14741 rtx_insn
*place
= 0;
14745 next_link
= link
->next
;
14747 /* If the insn that this link points to is a NOTE, ignore it. */
14748 if (NOTE_P (link
->insn
))
14752 rtx pat
= PATTERN (link
->insn
);
14753 if (GET_CODE (pat
) == SET
)
14755 else if (GET_CODE (pat
) == PARALLEL
)
14758 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14760 set
= XVECEXP (pat
, 0, i
);
14761 if (GET_CODE (set
) != SET
)
14764 reg
= SET_DEST (set
);
14765 while (GET_CODE (reg
) == ZERO_EXTRACT
14766 || GET_CODE (reg
) == STRICT_LOW_PART
14767 || GET_CODE (reg
) == SUBREG
)
14768 reg
= XEXP (reg
, 0);
14773 if (REGNO (reg
) == link
->regno
)
14776 if (i
== XVECLEN (pat
, 0))
14782 reg
= SET_DEST (set
);
14784 while (GET_CODE (reg
) == ZERO_EXTRACT
14785 || GET_CODE (reg
) == STRICT_LOW_PART
14786 || GET_CODE (reg
) == SUBREG
)
14787 reg
= XEXP (reg
, 0);
14792 /* A LOG_LINK is defined as being placed on the first insn that uses
14793 a register and points to the insn that sets the register. Start
14794 searching at the next insn after the target of the link and stop
14795 when we reach a set of the register or the end of the basic block.
14797 Note that this correctly handles the link that used to point from
14798 I3 to I2. Also note that not much searching is typically done here
14799 since most links don't point very far away. */
14801 for (insn
= NEXT_INSN (link
->insn
);
14802 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14803 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14804 insn
= NEXT_INSN (insn
))
14805 if (DEBUG_INSN_P (insn
))
14807 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14809 if (reg_referenced_p (reg
, PATTERN (insn
)))
14813 else if (CALL_P (insn
)
14814 && find_reg_fusage (insn
, USE
, reg
))
14819 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14822 /* If we found a place to put the link, place it there unless there
14823 is already a link to the same insn as LINK at that point. */
14827 struct insn_link
*link2
;
14829 FOR_EACH_LOG_LINK (link2
, place
)
14830 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14835 link
->next
= LOG_LINKS (place
);
14836 LOG_LINKS (place
) = link
;
14838 /* Set added_links_insn to the earliest insn we added a
14840 if (added_links_insn
== 0
14841 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14842 added_links_insn
= place
;
14848 /* Check for any register or memory mentioned in EQUIV that is not
14849 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14850 of EXPR where some registers may have been replaced by constants. */
14853 unmentioned_reg_p (rtx equiv
, rtx expr
)
14855 subrtx_iterator::array_type array
;
14856 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14858 const_rtx x
= *iter
;
14859 if ((REG_P (x
) || MEM_P (x
))
14860 && !reg_mentioned_p (x
, expr
))
14866 DEBUG_FUNCTION
void
14867 dump_combine_stats (FILE *file
)
14871 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14872 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14876 dump_combine_total_stats (FILE *file
)
14880 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14881 total_attempts
, total_merges
, total_extras
, total_successes
);
14884 /* Try combining insns through substitution. */
14885 static unsigned int
14886 rest_of_handle_combine (void)
14888 int rebuild_jump_labels_after_combine
;
14890 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14891 df_note_add_problem ();
14894 regstat_init_n_sets_and_refs ();
14895 reg_n_sets_max
= max_reg_num ();
14897 rebuild_jump_labels_after_combine
14898 = combine_instructions (get_insns (), max_reg_num ());
14900 /* Combining insns may have turned an indirect jump into a
14901 direct jump. Rebuild the JUMP_LABEL fields of jumping
14903 if (rebuild_jump_labels_after_combine
)
14905 if (dom_info_available_p (CDI_DOMINATORS
))
14906 free_dominance_info (CDI_DOMINATORS
);
14907 timevar_push (TV_JUMP
);
14908 rebuild_jump_labels (get_insns ());
14910 timevar_pop (TV_JUMP
);
14913 regstat_free_n_sets_and_refs ();
14919 const pass_data pass_data_combine
=
14921 RTL_PASS
, /* type */
14922 "combine", /* name */
14923 OPTGROUP_NONE
, /* optinfo_flags */
14924 TV_COMBINE
, /* tv_id */
14925 PROP_cfglayout
, /* properties_required */
14926 0, /* properties_provided */
14927 0, /* properties_destroyed */
14928 0, /* todo_flags_start */
14929 TODO_df_finish
, /* todo_flags_finish */
14932 class pass_combine
: public rtl_opt_pass
14935 pass_combine (gcc::context
*ctxt
)
14936 : rtl_opt_pass (pass_data_combine
, ctxt
)
14939 /* opt_pass methods: */
14940 virtual bool gate (function
*) { return (optimize
> 0); }
14941 virtual unsigned int execute (function
*)
14943 return rest_of_handle_combine ();
14946 }; // class pass_combine
14948 } // anon namespace
14951 make_pass_combine (gcc::context
*ctxt
)
14953 return new pass_combine (ctxt
);