1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
111 (FPSCR_PR 524288) ;; 1 << 19
112 (FPSCR_SZ 1048576) ;; 1 << 20
113 (FPSCR_FR 2097152) ;; 1 << 21
116 (define_c_enum "unspec" [
117 ;; These are used with unspec.
146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
152 UNSPEC_GOTOFFFUNCDESC
154 UNSPEC_BUILTIN_STRLEN
157 (define_c_enum "unspecv" [
158 ;; These are used with unspec_volatile.
175 ;; -------------------------------------------------------------------------
177 ;; -------------------------------------------------------------------------
182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a"
183 (const (symbol_ref "sh_cpu_attr")))
185 (define_attr "endian" "big,little"
186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
187 (const_string "little") (const_string "big"))))
189 ;; Indicate if the default fpu mode is single precision.
190 (define_attr "fpu_single" "yes,no"
191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
192 (const_string "yes") (const_string "no"))))
194 (define_attr "fmovd" "yes,no"
195 (const (if_then_else (symbol_ref "TARGET_FMOVD")
196 (const_string "yes") (const_string "no"))))
198 (define_attr "pipe_model" "sh1,sh4"
200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
201 (const_string "sh1"))))
203 ;; cbranch conditional branch instructions
204 ;; jump unconditional jumps
205 ;; arith ordinary arithmetic
206 ;; arith3 a compound insn that behaves similarly to a sequence of
207 ;; three insns of type arith
208 ;; arith3b like above, but might end with a redirected branch
210 ;; load_si Likewise, SImode variant for general register.
211 ;; fload Likewise, but load to fp register.
213 ;; fstore floating point register to memory
214 ;; move general purpose register to register
215 ;; movi8 8-bit immediate to general purpose register
216 ;; mt_group other sh4 mt instructions
217 ;; fmove register to register, floating point
218 ;; smpy word precision integer multiply
219 ;; dmpy longword or doublelongword precision integer multiply
221 ;; pload load of pr reg, which can't be put into delay slot of rts
222 ;; prset copy register to pr reg, ditto
223 ;; pstore store of pr reg, which can't be put into delay slot of jsr
224 ;; prget copy pr to register, ditto
225 ;; pcload pc relative load of constant value
226 ;; pcfload Likewise, but load to fp register.
227 ;; pcload_si Likewise, SImode variant for general register.
228 ;; rte return from exception
229 ;; sfunc special function call with known used registers
230 ;; call function call
232 ;; fpscr_toggle toggle a bit in the fpscr
233 ;; fdiv floating point divide (or square root)
234 ;; gp_fpul move from general purpose register to fpul
235 ;; fpul_gp move from fpul to general purpose register
236 ;; mac_gp move from mac[lh] to general purpose register
237 ;; gp_mac move from general purpose register to mac[lh]
238 ;; mac_mem move from mac[lh] to memory
239 ;; mem_mac move from memory to mac[lh]
240 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
241 ;; ftrc_s fix_truncsfsi2_i4
242 ;; dfdiv double precision floating point divide (or square root)
243 ;; cwb ic_invalidate_line_i
244 ;; movua SH4a unaligned load
245 ;; fsrra square root reciprocal approximate
246 ;; fsca sine and cosine approximate
247 ;; tls_load load TLS related address
248 ;; nil no-op move, will be deleted.
251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
257 (const_string "other"))
259 ;; We define a new attribute namely "insn_class".We use
260 ;; this for the DFA based pipeline description.
262 ;; mt_group SH4 "mt" group instructions.
264 ;; ex_group SH4 "ex" group instructions.
266 ;; ls_group SH4 "ls" group instructions.
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
274 (eq_attr "type" "cbranch,jump") (const_string "br_group")
275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
276 (const_string "fe_group")
277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
279 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
280 (const_string "none")))
282 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
283 ;; so these do not belong in an insn group, although they are modeled
284 ;; with their own define_insn_reservations.
286 ;; Indicate what precision must be selected in fpscr for this insn, if any.
287 (define_attr "fp_mode" "single,double,none" (const_string "none"))
289 ;; Indicate if the fpu mode is set by this instruction
290 ;; "unknown" must have the value as "none" in fp_mode, and means
291 ;; that the instruction/abi has left the processor in an unknown
293 ;; "none" means that nothing has changed and no mode is set.
294 ;; This attribute is only used for the Renesas ABI.
295 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
297 ; If a conditional branch destination is within -252..258 bytes away
298 ; from the instruction it can be 2 bytes long. Something in the
299 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
300 ; branches are initially assumed to be 16 bytes long.
301 ; In machine_dependent_reorg, we split all branches that are longer than
304 ;; The maximum range used for SImode constant pool entries is 1018. A final
305 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
306 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
307 ;; instruction around the pool table, 2 bytes of alignment before the table,
308 ;; and 30 bytes of alignment after the table. That gives a maximum total
309 ;; pool size of 1058 bytes.
310 ;; Worst case code/pool content size ratio is 1:2 (using asms).
311 ;; Thus, in the worst case, there is one instruction in front of a maximum
312 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
313 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
314 ;; If we have a forward branch, the initial table will be put after the
315 ;; unconditional branch.
317 ;; ??? We could do much better by keeping track of the actual pcloads within
318 ;; the branch range and in the pcload range in front of the branch range.
320 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
322 (define_attr "short_cbranch_p" "no,yes"
323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
331 ] (const_string "no")))
333 (define_attr "med_branch_p" "no,yes"
334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
342 ] (const_string "no")))
344 (define_attr "med_cbranch_p" "no,yes"
345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
353 ] (const_string "no")))
355 (define_attr "braf_branch_p" "no,yes"
356 (cond [(match_test "! TARGET_SH2")
358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
366 ] (const_string "no")))
368 (define_attr "braf_cbranch_p" "no,yes"
369 (cond [(match_test "! TARGET_SH2")
371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
379 ] (const_string "no")))
381 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
382 ;; For wider ranges, we need a combination of a code and a data part.
383 ;; If we can get a scratch register for a long range jump, the code
384 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
385 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
386 ;; long; otherwise, it must be 6 bytes long.
388 ;; All other instructions are two bytes long by default.
390 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
391 ;; but getattrtab doesn't understand this.
392 (define_attr "length" ""
393 (cond [(eq_attr "type" "cbranch")
394 (cond [(eq_attr "short_cbranch_p" "yes")
396 (eq_attr "med_cbranch_p" "yes")
398 (eq_attr "braf_cbranch_p" "yes")
400 ;; ??? using pc is not computed transitively.
401 (ne (match_dup 0) (match_dup 0))
403 (match_test "flag_pic")
406 (eq_attr "type" "jump")
407 (cond [(eq_attr "med_branch_p" "yes")
409 (and (match_test "prev_nonnote_insn (insn)")
410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
413 (symbol_ref "code_for_indirect_jump_scratch"))))
414 (cond [(eq_attr "braf_branch_p" "yes")
416 (not (match_test "flag_pic"))
418 (match_test "TARGET_SH2")
419 (const_int 10)] (const_int 18))
420 (eq_attr "braf_branch_p" "yes")
422 ;; ??? using pc is not computed transitively.
423 (ne (match_dup 0) (match_dup 0))
425 (match_test "flag_pic")
430 ;; DFA descriptions for the pipelines
435 (include "iterators.md")
436 (include "predicates.md")
437 (include "constraints.md")
439 ;; Definitions for filling delay slots
441 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
443 (define_attr "banked" "yes,no"
444 (cond [(match_test "sh_loads_bankedreg_p (insn)")
445 (const_string "yes")]
446 (const_string "no")))
448 ;; ??? This should be (nil) instead of (const_int 0)
449 (define_attr "hit_stack" "yes,no"
450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
452 (const_string "yes")))
454 (define_attr "interrupt_function" "no,yes"
455 (const (symbol_ref "current_function_interrupt")))
457 (define_attr "in_delay_slot" "yes,no"
458 (cond [(eq_attr "type" "cbranch") (const_string "no")
459 (eq_attr "type" "pcload,pcload_si") (const_string "no")
460 (eq_attr "type" "fpscr_toggle") (const_string "no")
461 (eq_attr "needs_delay_slot" "yes") (const_string "no")
462 (eq_attr "length" "2") (const_string "yes")
463 ] (const_string "no")))
465 (define_attr "cond_delay_slot" "yes,no"
466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
467 ] (const_string "no")))
469 (define_attr "is_sfunc" ""
470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
472 ;; SH4 Double-precision computation with double-precision result -
473 ;; the two halves are ready at different times.
474 (define_attr "dfp_comp" "yes,no"
475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
476 (const_string "no")))
478 ;; Insns for which the latency of a preceding fp insn is decreased by one.
479 (define_attr "late_fp_use" "yes,no" (const_string "no"))
480 ;; And feeding insns for which this relevant.
481 (define_attr "any_fp_comp" "yes,no"
482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
483 (const_string "yes")]
484 (const_string "no")))
486 (define_attr "any_int_load" "yes,no"
487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
488 (const_string "yes")]
489 (const_string "no")))
491 (define_attr "highpart" "user, ignore, extend, depend, must_split"
492 (const_string "user"))
495 (eq_attr "needs_delay_slot" "yes")
496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
498 ;; Since a normal return (rts) implicitly uses the PR register,
499 ;; we can't allow PR register loads in an rts delay slot.
500 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
501 ;; stack, and thus we can't put a pop instruction in its delay slot.
502 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
503 ;; pop instruction can go in the delay slot, unless it references a banked
504 ;; register (the register bank is switched by rte).
506 (eq_attr "type" "return")
507 [(and (eq_attr "in_delay_slot" "yes")
508 (ior (and (eq_attr "interrupt_function" "no")
509 (eq_attr "type" "!pload,prset"))
510 (and (eq_attr "interrupt_function" "yes")
511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
512 (eq_attr "banked" "no"))))
515 ;; Since a call implicitly uses the PR register, we can't allow
516 ;; a PR register store in a jsr delay slot.
519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
520 [(and (eq_attr "in_delay_slot" "yes")
521 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
523 ;; Conditional branches with delay slots are available starting with SH2.
524 ;; If zero displacement conditional branches are fast, disable the delay
525 ;; slot if the branch jumps over only one 2-byte insn.
527 (and (eq_attr "type" "cbranch")
528 (match_test "TARGET_SH2")
529 (not (and (match_test "TARGET_ZDCBRANCH")
530 (match_test "sh_cbranch_distance (insn, 4) == 2"))))
531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
533 ;; -------------------------------------------------------------------------
534 ;; SImode signed integer comparisons
535 ;; -------------------------------------------------------------------------
537 ;; Patterns to generate the tst instruction which are usually formed by
539 ;; The canonical form here being used is (eq (and (op) (op)) 0).
540 ;; For some bit patterns, such as contiguous bits, we also must accept
541 ;; zero_extract forms. Single bit tests are also handled via zero_extract
542 ;; patterns in the 'bit field extract patterns' section. All variants
543 ;; are eventually converted to the 'tstsi_t' insn.
544 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
545 ;; constants that won't fit into 8 bits. After having captured the constant
546 ;; we can decide better whether/how to load it into a register and do other
547 ;; post-combine optimizations such as bypassing sign/zero extensions.
548 (define_insn_and_split "tstsi_t"
550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
555 || satisfies_constraint_K08 (operands[1]))"
557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
558 && !sh_in_recog_treg_set_expr ()"
561 gcc_assert (CONST_INT_P (operands[1]));
563 HOST_WIDE_INT op1val = INTVAL (operands[1]);
564 rtx reg = operands[0];
566 reg = SUBREG_REG (reg);
567 gcc_assert (REG_P (reg));
568 bool op0_dead_after_this =
569 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (reg));
575 "tstsi_t: trying to optimize const_int 0x%08x\n",
578 /* See if we can convert a test with a reg and a constant into
579 something simpler, if the reg is known to be zero or sign
581 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
583 if (eop0.ext_code != UNKNOWN)
585 /* Adjust the constant, trying to eliminate bits that are not
586 contributing to the result. */
587 if (eop0.from_mode == QImode)
589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
591 else if (eop0.from_mode == HImode)
593 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
594 ? 0x8000 : 0)) & 0xFFFF;
597 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
600 /* Try to bypass the sign/zero extension first if op0 dies after
602 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
605 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
607 operands[0] = eop0.use_as_unextended_reg (curr_insn);
609 else if ((eop0.from_mode == QImode && op1val == 0xFF)
610 || (eop0.from_mode == HImode && op1val == 0xFFFF))
613 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
614 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
618 else if (eop0.ext_code == SIGN_EXTEND
619 && ((eop0.from_mode == QImode && op1val == 0x80)
620 || (eop0.from_mode == HImode && op1val == 0x8000)))
623 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
624 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
628 else if (!CONST_OK_FOR_K08 (op1val))
631 fprintf (dump_file, "tstsi_t: converting const_int to signed "
634 /* If here we haven't done anything yet. Convert the constant
635 to a signed value to reduce the constant pool size. */
636 operands[0] = eop0.use_as_extended_reg (curr_insn);
638 if (eop0.from_mode == QImode)
639 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
640 else if (eop0.from_mode == HImode)
641 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
644 operands[0] = eop0.use_as_extended_reg (curr_insn);
649 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
652 /* Try to fit the constant into 8 bits by shuffling the value in the
654 Doing that usually results in smaller code as the constants in the
655 pools are avoided (32 bit constant = load + constant = 6 bytes).
656 However, if the constant load (LS insn) can be hoisted insn dependencies
657 can be avoided and chances for parallel execution increase. The common
663 FIXME: For now we do that only when optimizing for size until there is
666 FIXME: If there are multiple tst insns in the block with the same
667 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
668 variant instead and load the constant into a reg. For that we'd need
669 to do some analysis. */
671 if (CONST_OK_FOR_K08 (op1val))
675 else if ((op1val & 0xFFFF) == 0
676 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
678 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
679 op1val = op1val >> 16;
680 rtx r = gen_reg_rtx (SImode);
681 emit_insn (gen_rotlsi3_16 (r, operands[0]));
684 else if ((op1val & 0xFF) == 0
685 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
687 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
688 op1val = op1val >> 8;
689 rtx r = gen_reg_rtx (SImode);
690 emit_insn (gen_swapbsi2 (r, operands[0]));
693 else if ((op1val & 3) == 0
694 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
696 op1val = op1val >> 2;
697 rtx r = gen_reg_rtx (SImode);
698 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
701 else if ((op1val & 1) == 0
702 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
704 op1val = op1val >> 1;
705 rtx r = gen_reg_rtx (SImode);
706 emit_insn (gen_shlr (r, operands[0]));
710 operands[1] = GEN_INT (op1val);
712 if (!satisfies_constraint_K08 (operands[1]))
713 operands[1] = force_reg (SImode, operands[1]);
715 emit_insn (gen_tstsi_t (operands[0], operands[1]));
718 [(set_attr "type" "mt_group")])
720 ;; This pattern is used by combine when testing QI/HImode subregs with a
721 ;; negative constant. Ignore high bits by masking them out in the constant.
722 (define_insn_and_split "*tst<mode>_t"
725 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
726 (match_operand 1 "const_int_operand")) 0)
728 "TARGET_SH1 && can_create_pseudo_p ()"
732 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
734 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
735 operands[1] = GEN_INT (INTVAL (operands[1])
736 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
739 ;; This pattern might be risky because it also tests the upper bits and not
740 ;; only the subreg. We have to check whether the operands have been sign
741 ;; or zero extended. In the worst case, a zero extension has to be inserted
742 ;; to mask out the unwanted bits.
743 (define_insn_and_split "*tst<mode>_t_subregs"
747 (and:SI (match_operand:SI 0 "arith_reg_operand")
748 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
750 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
752 "&& !sh_in_recog_treg_set_expr ()"
755 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
759 (define_insn_and_split "*tst<mode>_t_subregs"
763 (and:SI (match_operand:SI 0 "arith_reg_operand")
764 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
766 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
768 "&& !sh_in_recog_treg_set_expr ()"
771 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
775 ;; Extract contiguous bits and compare them against zero.
776 ;; Notice that this will not be used for single bits. Special single bit
777 ;; extraction patterns are in the 'bit field extract patterns' section.
778 (define_insn_and_split "*tst<mode>_t_zero_extract"
780 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
781 (match_operand 1 "const_int_operand")
782 (match_operand 2 "const_int_operand"))
784 "TARGET_SH1 && can_create_pseudo_p ()"
788 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
790 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
791 if (GET_MODE (operands[0]) != SImode)
792 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
795 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
796 ;; The shifted-out bits in the mask will always be zero, since the
797 ;; shifted-in bits in the reg will also be always zero.
798 (define_insn_and_split "*tstsi_t_shift_mask"
800 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
801 (match_operand 1 "const_int_operand"))
802 (match_operand 2 "const_int_operand"))
804 "TARGET_SH1 && can_create_pseudo_p ()"
808 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
810 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
813 (define_insn "cmpeqsi_t"
815 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
816 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
822 [(set_attr "type" "mt_group")])
824 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
825 ;; Try to fix that in the split1 pass by looking for the previous set
826 ;; of the tested op. Also see if there is a preceeding sign/zero
827 ;; extension that can be avoided.
830 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
831 "TARGET_SH1 && can_create_pseudo_p () && optimize
832 && !sh_in_recog_treg_set_expr ()"
833 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
836 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
838 /* If the tested reg is not dead after this insn, it's probably used by
839 something else after the comparison. It's probably better to leave
841 rtx reg = operands[0];
843 reg = SUBREG_REG (reg);
844 gcc_assert (REG_P (reg));
845 if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) != NULL_RTX)
848 /* FIXME: Maybe also search the predecessor basic blocks to catch
850 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
851 prev_nonnote_nondebug_insn_bb);
853 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
854 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
857 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
860 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
861 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
862 || CONST_INT_P (XEXP (op.set_src, 1)))))
865 /* Assume that the operands of the andsi insn are compatible with the
866 operands of the tstsi_t insn, which is generally the case. */
868 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
869 emit_insn (gen_tstsi_t (copy_rtx (XEXP (op.set_src, 0)),
870 copy_rtx (XEXP (op.set_src, 1))));
874 /* Converting HImode into tests against 0xFFFF tends to increase the code
875 size, as it will create constant pool entries. Disable it for now. */
876 const bool enable_himode = false;
878 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
879 extended reg is used after this insn, if we know that _before_ the zero
880 extension the value was loaded via sign extending mem load, we can just
881 use the value of the mem load directly. */
882 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
885 if (eop.ext_code != UNKNOWN
886 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
887 && eop.can_use_as_unextended_reg ()
888 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
890 /* Bypass the sign/zero extension and test against the bit mask, but
891 only if it's the only use of the sign/zero extracted value.
892 Otherwise we'd be introducing new constants in the pool. */
894 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
895 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
897 emit_insn (gen_tstsi_t (
898 eop.use_as_unextended_reg (curr_insn),
899 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
904 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
908 (define_insn "cmpgtsi_t"
910 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
911 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
916 [(set_attr "type" "mt_group")])
918 (define_insn "cmpgesi_t"
920 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
921 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
926 [(set_attr "type" "mt_group")])
928 ;; Recombine a cmp/pz followed by a nott into a shll.
929 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
930 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
933 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
935 "TARGET_SH1 && can_create_pseudo_p () && optimize
936 && !sh_in_recog_treg_set_expr ()"
940 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
942 rtx_insn* i = next_nonnote_nondebug_insn_bb (curr_insn);
946 fprintf (dump_file, "cmpgesi_t: following insn is \n");
947 print_rtl_single (dump_file, i);
948 fprintf (dump_file, "\n");
951 if (sh_is_nott_insn (i))
955 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
956 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
957 set_insn_deleted (i);
961 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
962 Thus we can remove it only if T is marked as dead afterwards. */
963 if (rtx dest_reg = !TARGET_SH2A
964 && sh_reg_dead_or_unused_after_insn (i, T_REG)
965 ? sh_movrt_set_dest (i) : NULL)
969 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
970 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
971 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
972 REG_DEAD, get_t_reg_rtx ());
973 set_insn_deleted (i);
978 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
983 ;; FIXME: This is actually wrong. There is no way to literally move a
984 ;; general reg to t reg. Luckily, it seems that this pattern will be only
985 ;; used when the general reg is known be either '0' or '1' during combine.
986 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
987 ;; Due to interactions with other patterns, combine fails to pick the latter
988 ;; and invert the dependent logic.
989 (define_insn "*negtstsi"
990 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
991 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
993 [(set_attr "type" "mt_group")])
995 ;; Some integer sign comparison patterns can be realized with the div0s insn.
996 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
998 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
999 ;; variations are converted. The negative forms will split into a trailing
1000 ;; nott sequence, which will be eliminated either by the
1001 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
1002 (define_insn "cmp_div0s"
1003 [(set (reg:SI T_REG)
1004 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
1005 (match_operand:SI 1 "arith_reg_operand" "r"))
1009 [(set_attr "type" "arith")])
1011 (define_insn_and_split "*cmp_div0s_1"
1012 [(set (reg:SI T_REG)
1013 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1015 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1017 "TARGET_SH1 && can_create_pseudo_p ()"
1020 [(set (reg:SI T_REG)
1021 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1023 (define_insn_and_split "*cmp_div0s_2"
1024 [(set (reg:SI T_REG)
1025 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1027 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1029 "TARGET_SH1 && can_create_pseudo_p ()"
1032 [(set (reg:SI T_REG)
1033 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1035 (define_insn_and_split "*cmp_div0s_3"
1036 [(set (reg:SI T_REG)
1037 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1039 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1041 "TARGET_SH1 && can_create_pseudo_p ()"
1044 [(set (reg:SI T_REG)
1045 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1046 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1048 (define_insn_and_split "*cmp_div0s_4"
1049 [(set (reg:SI T_REG)
1050 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1051 (match_operand:SI 1 "arith_reg_operand"))
1053 "TARGET_SH1 && can_create_pseudo_p ()"
1056 [(set (reg:SI T_REG)
1057 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1058 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1060 (define_insn_and_split "*cmp_div0s_5"
1061 [(set (reg:SI T_REG)
1062 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1064 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1066 "TARGET_SH1 && can_create_pseudo_p ()"
1069 [(set (reg:SI T_REG)
1070 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1071 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1073 (define_insn_and_split "*cmp_div0s_6"
1074 [(set (reg:SI T_REG)
1075 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1079 "TARGET_SH1 && can_create_pseudo_p ()"
1082 [(set (reg:SI T_REG)
1083 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1084 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1086 ;; In some cases, it might be shorter to get a tested bit into bit 31 and
1087 ;; use div0s. Otherwise it's usually better to just leave the xor and tst
1088 ;; sequence. The only thing we can try to do here is avoiding the large
1090 (define_insn_and_split "*cmp_div0s_7"
1091 [(set (reg:SI T_REG)
1092 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1093 (match_operand:SI 1 "arith_reg_operand"))
1095 (match_operand 2 "const_int_operand")))]
1096 "TARGET_SH1 && can_create_pseudo_p ()
1097 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15
1098 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1099 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1104 const int bitpos = INTVAL (operands[2]);
1106 rtx op0 = gen_reg_rtx (SImode);
1107 rtx op1 = gen_reg_rtx (SImode);
1109 if (bitpos == 23 || bitpos == 30 || bitpos == 29)
1111 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos)));
1112 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos)));
1114 else if (bitpos == 15)
1116 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0])));
1117 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1])));
1119 else if (bitpos == 7)
1121 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0])));
1122 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1])));
1124 else if (bitpos == 31)
1132 emit_insn (gen_cmp_div0s (op0, op1));
1136 ;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better.
1137 ;; Thus allow the following patterns only for higher bit positions where
1138 ;; we it's more likely to save the large tst constant.
1139 (define_insn_and_split "*cmp_div0s_8"
1140 [(set (reg:SI T_REG)
1141 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand")
1143 (match_operand 2 "const_int_operand"))
1144 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand")
1147 "TARGET_SH1 && can_create_pseudo_p ()
1148 && (INTVAL (operands[2]) == 15
1149 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1150 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1153 [(set (reg:SI T_REG)
1154 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1155 (const_int 1) (match_dup 2)))
1156 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1158 (define_insn_and_split "*cmp_div0s_9"
1159 [(set (reg:SI T_REG)
1160 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1161 (match_operand:SI 1 "arith_reg_operand"))
1162 (match_operand 2 "const_int_operand"))
1164 (match_operand 3 "const_int_operand")))]
1165 "TARGET_SH1 && can_create_pseudo_p ()
1166 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3]))
1167 && (INTVAL (operands[3]) == 15
1168 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29
1169 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)"
1172 [(set (reg:SI T_REG)
1173 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1174 (const_int 1) (match_dup 3)))
1175 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1177 ;; -------------------------------------------------------------------------
1178 ;; SImode compare and branch
1179 ;; -------------------------------------------------------------------------
1181 (define_expand "cbranchsi4"
1183 (if_then_else (match_operator 0 "comparison_operator"
1184 [(match_operand:SI 1 "arith_operand" "")
1185 (match_operand:SI 2 "arith_operand" "")])
1186 (label_ref (match_operand 3 "" ""))
1188 (clobber (reg:SI T_REG))]
1189 "can_create_pseudo_p ()"
1191 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE);
1195 ;; Combine patterns to invert compare and branch operations for which we
1196 ;; don't have actual comparison insns. These patterns are used in cases
1197 ;; which appear after the initial cbranchsi expansion, which also does
1198 ;; some condition inversion.
1201 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1202 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1203 (label_ref (match_operand 2))
1205 (clobber (reg:SI T_REG))]
1207 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1208 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1209 (label_ref (match_dup 2))
1212 ;; FIXME: These don't seem to have any effect on the generated cbranch code
1213 ;; anymore, but only on some register allocation choices.
1216 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1217 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1218 (label_ref (match_operand 2))
1220 (clobber (reg:SI T_REG))]
1222 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1223 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1224 (label_ref (match_dup 2))
1229 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1230 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1231 (label_ref (match_operand 2))
1233 (clobber (reg:SI T_REG))]
1235 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1236 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1237 (label_ref (match_dup 2))
1242 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1243 (match_operand:SI 1 "arith_reg_operand" ""))
1244 (label_ref (match_operand 2))
1246 (clobber (reg:SI T_REG))]
1248 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1249 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1250 (label_ref (match_dup 2))
1255 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1256 (match_operand:SI 1 "arith_reg_operand" ""))
1257 (label_ref (match_operand 2))
1259 (clobber (reg:SI T_REG))]
1261 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1262 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1263 (label_ref (match_dup 2))
1266 ;; -------------------------------------------------------------------------
1267 ;; SImode unsigned integer comparisons
1268 ;; -------------------------------------------------------------------------
1270 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1271 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1272 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1273 ;; handled here, something else would just load a '0' into the second operand
1274 ;; and do the comparison. We can do slightly better by just setting the
1276 (define_insn_and_split "cmpgeusi_t"
1277 [(set (reg:SI T_REG)
1278 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1279 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1282 "&& satisfies_constraint_Z (operands[1])"
1283 [(set (reg:SI T_REG) (const_int 1))]
1285 [(set_attr "type" "mt_group")])
1287 (define_insn "cmpgtusi_t"
1288 [(set (reg:SI T_REG)
1289 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1290 (match_operand:SI 1 "arith_reg_operand" "r")))]
1293 [(set_attr "type" "mt_group")])
1295 ;; -------------------------------------------------------------------------
1296 ;; DImode compare and branch
1297 ;; -------------------------------------------------------------------------
1299 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1300 ;; Therefore, we aim to have a set of three branches that go straight to the
1301 ;; destination, i.e. only one of them is taken at any one time.
1302 ;; This mechanism should also be slightly better for the sh4-200.
1304 (define_expand "cbranchdi4"
1306 (if_then_else (match_operator 0 "comparison_operator"
1307 [(match_operand:DI 1 "arith_operand")
1308 (match_operand:DI 2 "arith_operand")])
1309 (label_ref (match_operand 3))
1311 (clobber (reg:SI T_REG))]
1312 "TARGET_SH2 && can_create_pseudo_p ()"
1314 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1319 ;; -------------------------------------------------------------------------
1320 ;; DImode signed integer comparisons
1321 ;; -------------------------------------------------------------------------
1324 [(set (reg:SI T_REG)
1325 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1326 (match_operand:DI 1 "arith_operand" "r"))
1330 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1333 [(set_attr "length" "6")
1334 (set_attr "type" "arith3b")])
1336 (define_insn "cmpeqdi_t"
1337 [(set (reg:SI T_REG)
1338 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1339 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1342 static const char* alt[] =
1349 "cmp/eq %S1,%S0" "\n"
1351 " cmp/eq %R1,%R0" "\n"
1354 return alt[which_alternative];
1356 [(set_attr "length" "6")
1357 (set_attr "type" "arith3b")])
1360 [(set (reg:SI T_REG)
1361 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1362 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1363 ;; If we applied this split when not optimizing, it would only be
1364 ;; applied during the machine-dependent reorg, when no new basic blocks
1366 "TARGET_SH1 && reload_completed && optimize"
1367 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1368 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1369 (label_ref (match_dup 6))
1371 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1374 operands[2] = gen_highpart (SImode, operands[0]);
1375 operands[3] = operands[1] == const0_rtx
1377 : gen_highpart (SImode, operands[1]);
1378 operands[4] = gen_lowpart (SImode, operands[0]);
1379 operands[5] = gen_lowpart (SImode, operands[1]);
1380 operands[6] = gen_label_rtx ();
1383 (define_insn "cmpgtdi_t"
1384 [(set (reg:SI T_REG)
1385 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1386 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1389 static const char* alt[] =
1391 "cmp/eq %S1,%S0" "\n"
1393 " cmp/gt %S1,%S0" "\n"
1394 " cmp/hi %R1,%R0" "\n"
1400 " cmp/hi %S0,%R0" "\n"
1403 return alt[which_alternative];
1405 [(set_attr "length" "8")
1406 (set_attr "type" "arith3")])
1408 (define_insn "cmpgedi_t"
1409 [(set (reg:SI T_REG)
1410 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1411 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1414 static const char* alt[] =
1416 "cmp/eq %S1,%S0" "\n"
1418 " cmp/ge %S1,%S0" "\n"
1419 " cmp/hs %R1,%R0" "\n"
1424 return alt[which_alternative];
1426 [(set_attr "length" "8,2")
1427 (set_attr "type" "arith3,mt_group")])
1429 ;; -------------------------------------------------------------------------
1430 ;; DImode unsigned integer comparisons
1431 ;; -------------------------------------------------------------------------
1433 (define_insn "cmpgeudi_t"
1434 [(set (reg:SI T_REG)
1435 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1436 (match_operand:DI 1 "arith_reg_operand" "r")))]
1439 return "cmp/eq %S1,%S0" "\n"
1441 " cmp/hs %S1,%S0" "\n"
1442 " cmp/hs %R1,%R0" "\n"
1445 [(set_attr "length" "8")
1446 (set_attr "type" "arith3")])
1448 (define_insn "cmpgtudi_t"
1449 [(set (reg:SI T_REG)
1450 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1451 (match_operand:DI 1 "arith_reg_operand" "r")))]
1454 return "cmp/eq %S1,%S0" "\n"
1456 " cmp/hi %S1,%S0" "\n"
1457 " cmp/hi %R1,%R0" "\n"
1460 [(set_attr "length" "8")
1461 (set_attr "type" "arith3")])
1463 ;; -------------------------------------------------------------------------
1464 ;; Conditional move instructions
1465 ;; -------------------------------------------------------------------------
1467 (define_insn "*movsicc_t_false"
1468 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1469 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1470 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1471 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1472 "TARGET_PRETEND_CMOVE
1473 && (arith_reg_operand (operands[1], SImode)
1474 || (immediate_operand (operands[1], SImode)
1475 && satisfies_constraint_I08 (operands[1])))"
1481 [(set_attr "type" "mt_group,arith") ;; poor approximation
1482 (set_attr "length" "4")])
1484 (define_insn "*movsicc_t_true"
1485 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1486 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1487 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1488 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1489 "TARGET_PRETEND_CMOVE
1490 && (arith_reg_operand (operands[1], SImode)
1491 || (immediate_operand (operands[1], SImode)
1492 && satisfies_constraint_I08 (operands[1])))"
1498 [(set_attr "type" "mt_group,arith") ;; poor approximation
1499 (set_attr "length" "4")])
1501 (define_expand "movsicc"
1502 [(set (match_operand:SI 0 "arith_reg_dest" "")
1503 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1504 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1505 (match_operand:SI 3 "arith_reg_operand" "")))]
1506 "TARGET_PRETEND_CMOVE"
1508 rtx_code code = GET_CODE (operands[1]);
1509 rtx_code new_code = code;
1510 rtx op0 = XEXP (operands[1], 0);
1511 rtx op1 = XEXP (operands[1], 1);
1513 if (! currently_expanding_to_rtl)
1518 case LT: case LE: case LEU: case LTU:
1519 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1523 new_code = reverse_condition (code);
1525 case EQ: case GT: case GE: case GEU: case GTU:
1531 sh_emit_scc_to_t (new_code, op0, op1);
1532 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1533 gen_rtx_REG (SImode, T_REG), const0_rtx);
1536 ;; -------------------------------------------------------------------------
1537 ;; Addition instructions
1538 ;; -------------------------------------------------------------------------
1540 (define_insn_and_split "adddi3"
1541 [(set (match_operand:DI 0 "arith_reg_dest")
1542 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1543 (match_operand:DI 2 "arith_reg_operand")))
1544 (clobber (reg:SI T_REG))]
1547 "&& can_create_pseudo_p ()"
1550 emit_insn (gen_clrt ());
1551 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1552 gen_lowpart (SImode, operands[1]),
1553 gen_lowpart (SImode, operands[2])));
1554 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1555 gen_highpart (SImode, operands[1]),
1556 gen_highpart (SImode, operands[2])));
1561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1562 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1563 (match_operand:SI 2 "arith_reg_operand" "r"))
1566 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1569 [(set_attr "type" "arith")])
1571 ;; A simplified version of the addc insn, where the exact value of the
1572 ;; T bit doesn't matter. This is easier for combine to pick up.
1573 ;; We allow a reg or 0 for one of the operands in order to be able to
1574 ;; do 'reg + T' sequences.
1575 (define_insn_and_split "*addc"
1576 [(set (match_operand:SI 0 "arith_reg_dest")
1577 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1578 (match_operand:SI 2 "arith_reg_or_0_operand"))
1579 (match_operand 3 "treg_set_expr")))
1580 (clobber (reg:SI T_REG))]
1581 "TARGET_SH1 && can_create_pseudo_p ()"
1586 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1587 if (ti.has_trailing_nott ())
1589 if (operands[2] == const0_rtx)
1591 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1592 remove_insn (ti.trailing_nott ());
1593 emit_insn (gen_subc (operands[0], operands[1],
1594 force_reg (SImode, GEN_INT (-1))));
1597 else if (!TARGET_SH2A)
1599 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1600 On SH2A keep the nott insn, because nott-addc sequence doesn't
1601 mutate the inputs. */
1602 remove_insn (ti.trailing_nott ());
1603 rtx tmp = gen_reg_rtx (SImode);
1604 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1605 emit_insn (gen_subc (operands[0], operands[1], tmp));
1610 emit_insn (gen_addc (operands[0], operands[1],
1611 force_reg (SImode, operands[2])));
1615 (define_insn_and_split "*addc"
1616 [(set (match_operand:SI 0 "arith_reg_dest")
1617 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1618 (match_operand:SI 2 "arith_reg_operand"))
1619 (match_operand:SI 3 "arith_reg_operand")))
1620 (clobber (reg:SI T_REG))]
1621 "TARGET_SH1 && can_create_pseudo_p ()"
1624 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1626 (clobber (reg:SI T_REG))])])
1628 (define_insn_and_split "*addc"
1629 [(set (match_operand:SI 0 "arith_reg_dest")
1630 (plus:SI (match_operand 1 "treg_set_expr")
1631 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1632 (match_operand:SI 3 "arith_reg_operand"))))
1633 (clobber (reg:SI T_REG))]
1634 "TARGET_SH1 && can_create_pseudo_p ()"
1637 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1639 (clobber (reg:SI T_REG))])])
1641 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1642 ;; matched. Split this up into a simple sub add sequence, as this will save
1643 ;; us one sett insn.
1644 (define_insn_and_split "*minus_plus_one"
1645 [(set (match_operand:SI 0 "arith_reg_dest" "")
1646 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1647 (match_operand:SI 2 "arith_reg_operand" ""))
1652 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1653 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1656 ;; The tree optimiziers canonicalize
1661 ;; On SH2A an add-bclr sequence will be used to handle this.
1662 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
1663 (define_insn_and_split "*round_int_even"
1664 [(set (match_operand:SI 0 "arith_reg_dest")
1665 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1668 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
1669 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1672 [(set (match_dup 0) (const_int -2))
1673 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
1674 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
1676 operands[2] = gen_reg_rtx (SImode);
1679 ;; If the *round_int_even pattern is combined with another plus,
1680 ;; convert it into an addc pattern to emit an shlr-addc sequence.
1681 ;; This split is taken by combine on non-SH2A and SH2A.
1683 [(set (match_operand:SI 0 "arith_reg_dest")
1684 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1687 (match_operand:SI 2 "arith_reg_operand")))]
1688 "TARGET_SH1 && can_create_pseudo_p ()"
1689 [(parallel [(set (match_dup 0)
1690 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1691 (and:SI (match_dup 1) (const_int 1))))
1692 (clobber (reg:SI T_REG))])])
1694 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1695 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1696 ;; operation, as opposed to sequences such as
1700 ;; Even if the constant is not CSE-ed, a sequence such as
1703 ;; can be scheduled much better since the load of the constant can be
1704 ;; done earlier, before any comparison insns that store the result in
1706 ;; However, avoid things like 'reg + 1', which would expand into a
1707 ;; 3 insn sequence, instead of add #imm8.
1708 (define_insn_and_split "*addc_t_r"
1709 [(set (match_operand:SI 0 "arith_reg_dest")
1710 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
1711 (match_operand:SI 2 "arith_reg_operand")))
1712 (clobber (reg:SI T_REG))]
1713 "TARGET_SH1 && can_create_pseudo_p ()"
1716 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
1718 (clobber (reg:SI T_REG))])])
1720 (define_insn_and_split "*addc_r_t"
1721 [(set (match_operand:SI 0 "arith_reg_dest")
1722 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1723 (match_operand 2 "treg_set_expr_not_const01")))
1724 (clobber (reg:SI T_REG))]
1725 "TARGET_SH1 && can_create_pseudo_p ()"
1728 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
1730 (clobber (reg:SI T_REG))])])
1732 ;; Convert '2 * reg + T' into 'reg + reg + T'.
1733 (define_insn_and_split "*addc_2r_t"
1734 [(set (match_operand:SI 0 "arith_reg_dest")
1735 (plus:SI (match_operand 1 "treg_set_expr")
1736 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
1738 (clobber (reg:SI T_REG))]
1739 "TARGET_SH1 && can_create_pseudo_p ()"
1742 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
1744 (clobber (reg:SI T_REG))])])
1746 (define_insn_and_split "*addc_2r_t"
1747 [(set (match_operand:SI 0 "arith_reg_dest")
1748 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
1750 (match_operand 2 "treg_set_expr")))
1751 (clobber (reg:SI T_REG))]
1752 "TARGET_SH1 && can_create_pseudo_p ()"
1755 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1757 (clobber (reg:SI T_REG))])])
1759 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
1760 (define_insn_and_split "*addc_negreg_t"
1761 [(set (match_operand:SI 0 "arith_reg_dest")
1762 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
1763 (match_operand:SI 2 "arith_reg_operand"))
1764 (match_operand:SI 3 "arith_reg_operand")))
1765 (clobber (reg:SI T_REG))]
1766 "TARGET_SH1 && can_create_pseudo_p ()"
1769 [(set (match_dup 4) (neg:SI (match_dup 3)))
1770 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
1772 (clobber (reg:SI T_REG))])]
1774 operands[4] = gen_reg_rtx (SImode);
1777 (define_expand "addsi3"
1778 [(set (match_operand:SI 0 "arith_reg_dest")
1779 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1780 (match_operand:SI 2 "arith_or_int_operand")))]
1783 if (!arith_operand (operands[2], SImode))
1785 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
1787 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2]));
1793 ;; The *addsi3_compact is made an insn_and_split and accepts actually
1794 ;; impossible constraints to make LRA's register elimination work well on SH.
1795 ;; The problem is that LRA expects something like
1796 ;; (set rA (plus rB (const_int N)))
1797 ;; to work. We can do that, but we have to split out an additional reg-reg
1798 ;; copy or constant load before the actual add insn.
1799 ;; Use u constraint for that case to avoid the invalid value in the stack
1801 ;; This also results in better code when LRA is not used. However, we have
1802 ;; to use different sets of patterns and the order of these patterns is
1804 ;; In some cases the constant zero might end up in operands[2] of the
1805 ;; patterns. We have to accept that and convert it into a reg-reg move.
1806 (define_insn_and_split "*addsi3_compact_lra"
1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
1808 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1809 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
1810 "TARGET_SH1 && sh_lra_p ()
1811 && (! reg_overlap_mentioned_p (operands[0], operands[1])
1812 || arith_operand (operands[2], SImode))"
1816 "&& reload_completed
1817 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
1818 [(set (match_dup 0) (match_dup 2))
1819 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
1821 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
1822 if (satisfies_constraint_I08 (operands[2]))
1823 std::swap (operands[1], operands[2]);
1825 [(set_attr "type" "arith")])
1827 (define_insn_and_split "addsi3_scr"
1828 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u")
1829 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r")
1830 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n")))
1831 (clobber (match_scratch:SI 3 "=X,X,&u"))]
1837 "&& reload_completed"
1838 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1840 if (operands[2] == const0_rtx)
1842 emit_move_insn (operands[0], operands[1]);
1846 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2]))
1848 if (reg_overlap_mentioned_p (operands[0], operands[1]))
1850 emit_move_insn (operands[3], operands[2]);
1851 emit_move_insn (operands[0], operands[1]);
1852 operands[2] = operands[3];
1856 emit_move_insn (operands[0], operands[2]);
1857 operands[2] = operands[1];
1860 else if (!reg_overlap_mentioned_p (operands[0], operands[1]))
1862 if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1863 emit_move_insn (operands[0], operands[1]);
1865 operands[2] = operands[1];
1868 [(set_attr "type" "arith")])
1870 ;; Old reload might generate add insns directly (not through the expander) for
1871 ;; address register calculations when reloading, in which case it won't try
1872 ;; the addsi_scr pattern. Because reload will sometimes try to validate
1873 ;; the generated insns and their constraints, this pattern must be
1874 ;; recognizable during and after reload. However, when reload generates
1875 ;; address register calculations for the stack pointer, we don't allow this
1876 ;; pattern. This will make reload prefer using indexed @(reg + reg) address
1877 ;; modes when the displacement of a @(disp + reg) doesn't fit.
1878 (define_insn_and_split "*addsi3"
1879 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1880 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
1881 (match_operand:SI 2 "arith_or_int_operand" "rn")))]
1882 "TARGET_SH1 && !sh_lra_p ()
1883 && (reload_completed || reload_in_progress)
1884 && !reg_overlap_mentioned_p (operands[0], operands[1])
1885 && (!reload_in_progress
1886 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG)
1887 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))"
1890 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1892 if (operands[2] == const0_rtx)
1894 emit_move_insn (operands[0], operands[1]);
1898 if (CONST_INT_P (operands[2]))
1900 if (satisfies_constraint_I08 (operands[2]))
1901 emit_move_insn (operands[0], operands[1]);
1904 emit_move_insn (operands[0], operands[2]);
1905 operands[2] = operands[1];
1908 else if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1909 emit_move_insn (operands[0], operands[1]);
1911 operands[2] = operands[1];
1914 (define_insn_and_split "*addsi3"
1915 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1916 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1917 (match_operand:SI 2 "arith_operand" "rI08,Z")))]
1918 "TARGET_SH1 && !sh_lra_p ()"
1922 "&& operands[2] == const0_rtx"
1923 [(set (match_dup 0) (match_dup 1))]
1926 [(set_attr "type" "arith")])
1928 ;; -------------------------------------------------------------------------
1929 ;; Subtraction instructions
1930 ;; -------------------------------------------------------------------------
1932 (define_insn_and_split "subdi3"
1933 [(set (match_operand:DI 0 "arith_reg_dest")
1934 (minus:DI (match_operand:DI 1 "arith_reg_operand")
1935 (match_operand:DI 2 "arith_reg_operand")))
1936 (clobber (reg:SI T_REG))]
1939 "&& can_create_pseudo_p ()"
1942 emit_insn (gen_clrt ());
1943 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
1944 gen_lowpart (SImode, operands[1]),
1945 gen_lowpart (SImode, operands[2])));
1946 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
1947 gen_highpart (SImode, operands[1]),
1948 gen_highpart (SImode, operands[2])));
1953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1954 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1955 (match_operand:SI 2 "arith_reg_operand" "r"))
1958 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1963 [(set_attr "type" "arith")])
1965 ;; A simplified version of the subc insn, where the exact value of the
1966 ;; T bit doesn't matter. This is easier for combine to pick up.
1967 ;; We allow a reg or 0 for one of the operands in order to be able to
1968 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
1970 (define_insn_and_split "*subc"
1971 [(set (match_operand:SI 0 "arith_reg_dest")
1972 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
1973 (match_operand:SI 2 "arith_reg_or_0_operand"))
1974 (match_operand 3 "treg_set_expr")))
1975 (clobber (reg:SI T_REG))]
1976 "TARGET_SH1 && can_create_pseudo_p ()"
1981 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1982 if (ti.has_trailing_nott ())
1984 if (operands[2] == const0_rtx)
1986 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
1987 remove_insn (ti.trailing_nott ());
1988 emit_insn (gen_addc (operands[0], operands[1],
1989 force_reg (SImode, GEN_INT (-1))));
1992 else if (!TARGET_SH2A)
1994 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
1995 On SH2A keep the nott insn, because nott-subc sequence doesn't
1996 mutate the inputs. */
1997 remove_insn (ti.trailing_nott ());
1998 rtx tmp = gen_reg_rtx (SImode);
1999 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
2000 emit_insn (gen_addc (operands[0], operands[1], tmp));
2005 emit_insn (gen_subc (operands[0], operands[1],
2006 force_reg (SImode, operands[2])));
2010 ;; Convert reg - T - reg = reg - reg - T
2011 (define_insn_and_split "*subc"
2012 [(set (match_operand:SI 0 "arith_reg_dest")
2013 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2014 (match_operand 2 "treg_set_expr"))
2015 (match_operand:SI 3 "arith_reg_operand")))
2016 (clobber (reg:SI T_REG))]
2017 "TARGET_SH1 && can_create_pseudo_p ()"
2020 [(parallel [(set (match_dup 0)
2021 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2023 (clobber (reg:SI T_REG))])])
2025 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2026 ;; better, if the sett insn can be done early.
2027 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2028 (define_insn_and_split "*subc"
2029 [(set (match_operand:SI 0 "arith_reg_dest" "")
2030 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2031 (match_operand:SI 2 "arith_reg_operand" "")))
2032 (clobber (reg:SI T_REG))]
2033 "TARGET_SH1 && can_create_pseudo_p ()"
2036 [(parallel [(set (match_dup 0)
2037 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2039 (clobber (reg:SI T_REG))])])
2041 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2042 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2043 ;; operation, as opposed to sequences such as
2047 ;; Even if the constant is not CSE-ed, a sequence such as
2050 ;; can be scheduled much better since the load of the constant can be
2051 ;; done earlier, before any comparison insns that store the result in
2053 ;; However, avoid things like 'reg - 1', which would expand into a
2054 ;; 3 insn sequence, instead of add #imm8.
2055 (define_insn_and_split "*subc"
2056 [(set (match_operand:SI 0 "arith_reg_dest" "")
2057 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2058 (match_operand 2 "treg_set_expr_not_const01")))
2059 (clobber (reg:SI T_REG))]
2060 "TARGET_SH1 && can_create_pseudo_p ()"
2063 [(parallel [(set (match_dup 0)
2064 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2066 (clobber (reg:SI T_REG))])])
2069 ;; (1 - T) - op2 = 1 - op2 - T
2070 (define_insn_and_split "*subc_negt_reg"
2071 [(set (match_operand:SI 0 "arith_reg_dest")
2072 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2073 (match_operand:SI 2 "arith_reg_operand")))
2074 (clobber (reg:SI T_REG))]
2075 "TARGET_SH1 && can_create_pseudo_p ()"
2080 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2081 if (ti.remove_trailing_nott ())
2083 /* (1 - T) - op2 = 1 - op2 - T */
2084 emit_insn (gen_subc (operands[0],
2085 force_reg (SImode, GEN_INT (1)), operands[2]));
2089 /* T - op2: use movt,sub sequence. */
2090 rtx tmp = gen_reg_rtx (SImode);
2091 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2092 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2098 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2099 ;; (op1 - T) + op3 = op1 - (-op3) - T
2100 (define_insn_and_split "*subc_negreg_t"
2101 [(set (match_operand:SI 0 "arith_reg_dest")
2102 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2103 (match_operand 2 "treg_set_expr"))
2104 (match_operand:SI 3 "arith_reg_operand")))
2105 (clobber (reg:SI T_REG))]
2106 "TARGET_SH1 && can_create_pseudo_p ()"
2111 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2112 if (ti.remove_trailing_nott ())
2114 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2115 rtx tmp = gen_reg_rtx (SImode);
2116 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2117 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2121 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2122 rtx tmp = gen_reg_rtx (SImode);
2123 emit_insn (gen_negsi2 (tmp, operands[3]));
2124 emit_insn (gen_subc (operands[0], operands[1], tmp));
2129 (define_insn "*subsi3_internal"
2130 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2131 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2132 (match_operand:SI 2 "arith_reg_operand" "r")))]
2135 [(set_attr "type" "arith")])
2142 ;; since this will sometimes save one instruction.
2143 ;; Otherwise we might get a sequence like
2147 ;; if the source and dest regs are the same.
2148 (define_expand "subsi3"
2149 [(set (match_operand:SI 0 "arith_reg_operand" "")
2150 (minus:SI (match_operand:SI 1 "arith_operand" "")
2151 (match_operand:SI 2 "arith_reg_operand" "")))]
2154 if (CONST_INT_P (operands[1]))
2156 emit_insn (gen_negsi2 (operands[0], operands[2]));
2157 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2162 ;; -------------------------------------------------------------------------
2163 ;; Division instructions
2164 ;; -------------------------------------------------------------------------
2166 ;; We take advantage of the library routines which don't clobber as many
2167 ;; registers as a normal function call would.
2169 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2170 ;; also has an effect on the register that holds the address of the sfunc.
2171 ;; To make this work, we have an extra dummy insn that shows the use
2172 ;; of this register for reorg.
2174 (define_insn "use_sfunc_addr"
2175 [(set (reg:SI PR_REG)
2176 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2177 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2179 [(set_attr "length" "0")])
2181 (define_insn "udivsi3_sh2a"
2182 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2183 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2184 (match_operand:SI 2 "arith_reg_operand" "z")))]
2187 [(set_attr "type" "arith")
2188 (set_attr "in_delay_slot" "no")])
2190 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2191 ;; hard register 0. If we used hard register 0, then the next instruction
2192 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2193 ;; gets allocated to a stack slot that needs its address reloaded, then
2194 ;; there is nothing to prevent reload from using r0 to reload the address.
2195 ;; This reload would clobber the value in r0 we are trying to store.
2196 ;; If we let reload allocate r0, then this problem can never happen.
2197 (define_insn "udivsi3_i1"
2198 [(set (match_operand:SI 0 "register_operand" "=z,z")
2199 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2200 (clobber (reg:SI T_REG))
2201 (clobber (reg:SI PR_REG))
2202 (clobber (reg:SI R1_REG))
2203 (clobber (reg:SI R4_REG))
2204 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2205 (use (match_operand 2 "" "Z,Ccl"))]
2206 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2210 [(set_attr "type" "sfunc")
2211 (set_attr "needs_delay_slot" "yes")])
2213 (define_insn "udivsi3_i4"
2214 [(set (match_operand:SI 0 "register_operand" "=y,y")
2215 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2216 (clobber (reg:SI T_REG))
2217 (clobber (reg:SI PR_REG))
2218 (clobber (reg:DF DR0_REG))
2219 (clobber (reg:DF DR2_REG))
2220 (clobber (reg:DF DR4_REG))
2221 (clobber (reg:SI R0_REG))
2222 (clobber (reg:SI R1_REG))
2223 (clobber (reg:SI R4_REG))
2224 (clobber (reg:SI R5_REG))
2225 (clobber (reg:SI FPSCR_STAT_REG))
2226 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2227 (use (match_operand 2 "" "Z,Ccl"))
2228 (use (reg:SI FPSCR_MODES_REG))]
2229 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2233 [(set_attr "type" "sfunc")
2234 (set_attr "fp_mode" "double")
2235 (set_attr "needs_delay_slot" "yes")])
2237 (define_insn "udivsi3_i4_single"
2238 [(set (match_operand:SI 0 "register_operand" "=y,y")
2239 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2240 (clobber (reg:SI T_REG))
2241 (clobber (reg:SI PR_REG))
2242 (clobber (reg:DF DR0_REG))
2243 (clobber (reg:DF DR2_REG))
2244 (clobber (reg:DF DR4_REG))
2245 (clobber (reg:SI R0_REG))
2246 (clobber (reg:SI R1_REG))
2247 (clobber (reg:SI R4_REG))
2248 (clobber (reg:SI R5_REG))
2249 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2250 (use (match_operand 2 "" "Z,Ccl"))]
2251 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2255 [(set_attr "type" "sfunc")
2256 (set_attr "needs_delay_slot" "yes")])
2258 (define_insn "udivsi3_i4_int"
2259 [(set (match_operand:SI 0 "register_operand" "=z")
2260 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2261 (clobber (reg:SI T_REG))
2262 (clobber (reg:SI R1_REG))
2263 (clobber (reg:SI PR_REG))
2264 (clobber (reg:SI MACH_REG))
2265 (clobber (reg:SI MACL_REG))
2266 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2269 [(set_attr "type" "sfunc")
2270 (set_attr "needs_delay_slot" "yes")])
2273 (define_expand "udivsi3"
2274 [(set (match_operand:SI 0 "register_operand")
2275 (udiv:SI (match_operand:SI 1 "general_operand")
2276 (match_operand:SI 2 "general_operand")))]
2280 rtx func_ptr = gen_reg_rtx (Pmode);
2282 /* Emit the move of the address to a pseudo outside of the libcall. */
2283 if (TARGET_DIVIDE_CALL_TABLE)
2285 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2286 that causes problems when the divide code is supposed to come from a
2287 separate library. Division by zero is undefined, so dividing 1 can be
2288 implemented by comparing with the divisor. */
2289 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2291 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2292 emit_insn (gen_cstoresi4 (operands[0], test,
2293 operands[1], operands[2]));
2296 else if (operands[2] == const0_rtx)
2298 emit_move_insn (operands[0], operands[2]);
2301 function_symbol (func_ptr, "__udivsi3_i4i", SFUNC_GOT);
2302 last = gen_udivsi3_i4_int (operands[0], func_ptr);
2304 else if (TARGET_DIVIDE_CALL_FP)
2306 rtx lab = function_symbol (func_ptr, "__udivsi3_i4", SFUNC_STATIC).lab;
2307 if (TARGET_FPU_SINGLE)
2308 last = gen_udivsi3_i4_single (operands[0], func_ptr, lab);
2310 last = gen_udivsi3_i4 (operands[0], func_ptr, lab);
2312 else if (TARGET_SH2A)
2314 operands[1] = force_reg (SImode, operands[1]);
2315 operands[2] = force_reg (SImode, operands[2]);
2316 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2321 rtx lab = function_symbol (func_ptr, "__udivsi3", SFUNC_STATIC).lab;
2322 last = gen_udivsi3_i1 (operands[0], func_ptr, lab);
2324 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2325 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2330 (define_insn "divsi3_sh2a"
2331 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2332 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2333 (match_operand:SI 2 "arith_reg_operand" "z")))]
2336 [(set_attr "type" "arith")
2337 (set_attr "in_delay_slot" "no")])
2339 (define_insn "divsi3_i1"
2340 [(set (match_operand:SI 0 "register_operand" "=z")
2341 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2342 (clobber (reg:SI T_REG))
2343 (clobber (reg:SI PR_REG))
2344 (clobber (reg:SI R1_REG))
2345 (clobber (reg:SI R2_REG))
2346 (clobber (reg:SI R3_REG))
2347 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2348 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2350 [(set_attr "type" "sfunc")
2351 (set_attr "needs_delay_slot" "yes")])
2353 (define_insn "divsi3_i4"
2354 [(set (match_operand:SI 0 "register_operand" "=y,y")
2355 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2356 (clobber (reg:SI PR_REG))
2357 (clobber (reg:DF DR0_REG))
2358 (clobber (reg:DF DR2_REG))
2359 (clobber (reg:SI FPSCR_STAT_REG))
2360 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2361 (use (match_operand 2 "" "Z,Ccl"))
2362 (use (reg:SI FPSCR_MODES_REG))]
2363 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2367 [(set_attr "type" "sfunc")
2368 (set_attr "fp_mode" "double")
2369 (set_attr "needs_delay_slot" "yes")])
2371 (define_insn "divsi3_i4_single"
2372 [(set (match_operand:SI 0 "register_operand" "=y,y")
2373 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2374 (clobber (reg:SI PR_REG))
2375 (clobber (reg:DF DR0_REG))
2376 (clobber (reg:DF DR2_REG))
2377 (clobber (reg:SI R2_REG))
2378 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2379 (use (match_operand 2 "" "Z,Ccl"))]
2380 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2384 [(set_attr "type" "sfunc")
2385 (set_attr "needs_delay_slot" "yes")])
2387 (define_insn "divsi3_i4_int"
2388 [(set (match_operand:SI 0 "register_operand" "=z")
2389 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2390 (clobber (reg:SI T_REG))
2391 (clobber (reg:SI PR_REG))
2392 (clobber (reg:SI R1_REG))
2393 (clobber (reg:SI MACH_REG))
2394 (clobber (reg:SI MACL_REG))
2395 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2398 [(set_attr "type" "sfunc")
2399 (set_attr "needs_delay_slot" "yes")])
2401 (define_expand "divsi3"
2402 [(set (match_operand:SI 0 "register_operand")
2403 (div:SI (match_operand:SI 1 "general_operand")
2404 (match_operand:SI 2 "general_operand")))]
2408 rtx func_ptr = gen_reg_rtx (Pmode);
2410 /* Emit the move of the address to a pseudo outside of the libcall. */
2411 if (TARGET_DIVIDE_CALL_TABLE)
2413 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT);
2414 last = gen_divsi3_i4_int (operands[0], func_ptr);
2416 else if (TARGET_DIVIDE_CALL_FP)
2418 rtx lab = function_symbol (func_ptr, sh_divsi3_libfunc,
2420 if (TARGET_FPU_SINGLE)
2421 last = gen_divsi3_i4_single (operands[0], func_ptr, lab);
2423 last = gen_divsi3_i4 (operands[0], func_ptr, lab);
2425 else if (TARGET_SH2A)
2427 operands[1] = force_reg (SImode, operands[1]);
2428 operands[2] = force_reg (SImode, operands[2]);
2429 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2434 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT);
2435 last = gen_divsi3_i1 (operands[0], func_ptr);
2437 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2438 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2444 ;; -------------------------------------------------------------------------
2445 ;; Multiplication instructions
2446 ;; -------------------------------------------------------------------------
2448 (define_insn_and_split "mulhisi3"
2449 [(set (match_operand:SI 0 "arith_reg_dest")
2450 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2451 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2452 (clobber (reg:SI MACL_REG))]
2453 "TARGET_SH1 && can_create_pseudo_p ()"
2456 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1))
2457 (sign_extend:SI (match_dup 2))))
2458 (set (match_dup 0) (reg:SI MACL_REG))])
2460 (define_insn_and_split "umulhisi3"
2461 [(set (match_operand:SI 0 "arith_reg_dest")
2462 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2463 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2464 (clobber (reg:SI MACL_REG))]
2465 "TARGET_SH1 && can_create_pseudo_p ()"
2468 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1))
2469 (zero_extend:SI (match_dup 2))))
2470 (set (match_dup 0) (reg:SI MACL_REG))])
2472 (define_insn "umulhisi3_i"
2473 [(set (reg:SI MACL_REG)
2474 (mult:SI (zero_extend:SI
2475 (match_operand:HI 0 "arith_reg_operand" "r"))
2477 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2480 [(set_attr "type" "smpy")])
2482 (define_insn "mulhisi3_i"
2483 [(set (reg:SI MACL_REG)
2484 (mult:SI (sign_extend:SI
2485 (match_operand:HI 0 "arith_reg_operand" "r"))
2487 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2490 [(set_attr "type" "smpy")])
2493 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2494 ;; a call to a routine which clobbers known registers.
2495 (define_insn "mulsi3_call"
2496 [(set (match_operand:SI 1 "register_operand" "=z")
2497 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2498 (clobber (reg:SI MACL_REG))
2499 (clobber (reg:SI T_REG))
2500 (clobber (reg:SI PR_REG))
2501 (clobber (reg:SI R3_REG))
2502 (clobber (reg:SI R2_REG))
2503 (clobber (reg:SI R1_REG))
2504 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2507 [(set_attr "type" "sfunc")
2508 (set_attr "needs_delay_slot" "yes")])
2510 (define_insn "mul_r"
2511 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2512 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2513 (match_operand:SI 2 "arith_reg_operand" "z")))]
2516 [(set_attr "type" "dmpy")])
2518 (define_insn "mul_l"
2519 [(set (reg:SI MACL_REG)
2520 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2521 (match_operand:SI 1 "arith_reg_operand" "r")))]
2524 [(set_attr "type" "dmpy")])
2526 (define_insn_and_split "mulsi3_i"
2527 [(set (match_operand:SI 0 "arith_reg_dest")
2528 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2529 (match_operand:SI 2 "arith_reg_operand")))
2530 (clobber (reg:SI MACL_REG))]
2531 "TARGET_SH2 && can_create_pseudo_p ()"
2534 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2)))
2535 (set (match_dup 0) (reg:SI MACL_REG))])
2537 (define_expand "mulsi3"
2538 [(set (match_operand:SI 0 "arith_reg_dest")
2539 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2540 (match_operand:SI 2 "arith_reg_operand")))]
2545 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2546 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2548 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
2550 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0]));
2554 /* FIXME: For some reason, expanding the mul_l insn and the macl store
2555 insn early gives slightly better code. In particular it prevents
2556 the decrement-test loop type to be used in some cases which saves
2557 one multiplication in the loop setup code.
2559 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2]));
2562 emit_insn (gen_mul_l (operands[1], operands[2]));
2563 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
2568 (define_insn "mulsidi3_i"
2569 [(set (reg:SI MACH_REG)
2573 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2574 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2576 (set (reg:SI MACL_REG)
2577 (mult:SI (match_dup 0)
2581 [(set_attr "type" "dmpy")])
2583 (define_expand "mulsidi3"
2584 [(set (match_operand:DI 0 "arith_reg_dest")
2585 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2586 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2589 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
2593 (define_insn_and_split "mulsidi3_compact"
2594 [(set (match_operand:DI 0 "arith_reg_dest")
2595 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2596 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2597 (clobber (reg:SI MACH_REG))
2598 (clobber (reg:SI MACL_REG))]
2599 "TARGET_SH2 && can_create_pseudo_p ()"
2604 rtx low_dst = gen_lowpart (SImode, operands[0]);
2605 rtx high_dst = gen_highpart (SImode, operands[0]);
2607 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2609 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2610 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2611 /* We need something to tag the possible REG_EQUAL notes on to. */
2612 emit_move_insn (operands[0], operands[0]);
2616 (define_insn "umulsidi3_i"
2617 [(set (reg:SI MACH_REG)
2621 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2622 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2624 (set (reg:SI MACL_REG)
2625 (mult:SI (match_dup 0)
2629 [(set_attr "type" "dmpy")])
2631 (define_expand "umulsidi3"
2632 [(set (match_operand:DI 0 "arith_reg_dest")
2633 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2634 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2637 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
2641 (define_insn_and_split "umulsidi3_compact"
2642 [(set (match_operand:DI 0 "arith_reg_dest")
2643 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2644 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2645 (clobber (reg:SI MACH_REG))
2646 (clobber (reg:SI MACL_REG))]
2647 "TARGET_SH2 && can_create_pseudo_p ()"
2652 rtx low_dst = gen_lowpart (SImode, operands[0]);
2653 rtx high_dst = gen_highpart (SImode, operands[0]);
2655 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
2657 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2658 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2659 /* We need something to tag the possible REG_EQUAL notes on to. */
2660 emit_move_insn (operands[0], operands[0]);
2664 (define_insn "smulsi3_highpart_i"
2665 [(set (reg:SI MACH_REG)
2669 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2670 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2672 (clobber (reg:SI MACL_REG))]
2675 [(set_attr "type" "dmpy")])
2677 (define_insn_and_split "smulsi3_highpart"
2678 [(set (match_operand:SI 0 "arith_reg_dest")
2682 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2683 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2685 (clobber (reg:SI MACL_REG))
2686 (clobber (reg:SI MACH_REG))]
2687 "TARGET_SH2 && can_create_pseudo_p ()"
2692 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2693 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2696 (define_insn "umulsi3_highpart_i"
2697 [(set (reg:SI MACH_REG)
2701 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2702 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2704 (clobber (reg:SI MACL_REG))]
2707 [(set_attr "type" "dmpy")])
2709 (define_insn_and_split "umulsi3_highpart"
2710 [(set (match_operand:SI 0 "arith_reg_dest")
2714 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2715 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2717 (clobber (reg:SI MACL_REG))]
2718 "TARGET_SH2 && can_create_pseudo_p ()"
2723 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2724 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2727 ;; -------------------------------------------------------------------------
2728 ;; Logical operations
2729 ;; -------------------------------------------------------------------------
2731 (define_expand "andsi3"
2732 [(set (match_operand:SI 0 "arith_reg_dest")
2733 (and:SI (match_operand:SI 1 "arith_reg_operand")
2734 (match_operand:SI 2 "logical_and_operand")))]
2737 /* If it is possible to turn the and insn into a zero extension
2738 already, redundant zero extensions will be folded, which results
2740 Ideally the splitter of *andsi_compact would be enough, if redundant
2741 zero extensions were detected after the combine pass, which does not
2742 happen at the moment. */
2744 if (satisfies_constraint_Jmb (operands[2]))
2746 emit_insn (gen_zero_extendqisi2 (operands[0],
2747 gen_lowpart (QImode, operands[1])));
2750 else if (satisfies_constraint_Jmw (operands[2]))
2752 emit_insn (gen_zero_extendhisi2 (operands[0],
2753 gen_lowpart (HImode, operands[1])));
2758 (define_insn_and_split "*andsi_compact"
2759 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
2760 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
2761 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
2769 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
2771 if (satisfies_constraint_Jmb (operands[2]))
2772 operands[1] = gen_lowpart (QImode, operands[1]);
2773 else if (satisfies_constraint_Jmw (operands[2]))
2774 operands[1] = gen_lowpart (HImode, operands[1]);
2778 [(set_attr "type" "arith")])
2780 (define_insn "*andsi3_bclr"
2781 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2782 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2783 (match_operand:SI 2 "const_int_operand" "Psz")))]
2784 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
2786 [(set_attr "type" "arith")])
2788 (define_expand "iorsi3"
2789 [(set (match_operand:SI 0 "arith_reg_dest")
2790 (ior:SI (match_operand:SI 1 "arith_reg_operand")
2791 (match_operand:SI 2 "logical_operand")))])
2793 (define_insn "*iorsi3_compact"
2794 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
2795 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2796 (match_operand:SI 2 "logical_operand" "r,K08")))]
2798 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
2800 [(set_attr "type" "arith")])
2802 (define_insn "*iorsi3_bset"
2803 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2804 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2805 (match_operand:SI 2 "const_int_operand" "Pso")))]
2806 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
2808 [(set_attr "type" "arith")])
2810 (define_insn "xorsi3"
2811 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
2812 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2813 (match_operand:SI 2 "logical_operand" "K08,r")))]
2816 [(set_attr "type" "arith")])
2818 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
2819 ;; of results where one of the inputs is a T bit store. Notice that this
2820 ;; pattern must not match during reload. If reload picks this pattern it
2821 ;; will be impossible to split it afterwards.
2822 (define_insn_and_split "*logical_op_t"
2823 [(set (match_operand:SI 0 "arith_reg_dest")
2824 (match_operator:SI 3 "logical_operator"
2825 [(match_operand:SI 1 "arith_reg_operand")
2826 (match_operand:SI 2 "t_reg_operand")]))]
2827 "TARGET_SH1 && can_create_pseudo_p ()"
2830 [(set (match_dup 4) (reg:SI T_REG))
2831 (set (match_dup 0) (match_dup 3))]
2833 operands[4] = gen_reg_rtx (SImode);
2834 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2835 operands[1], operands[4]);
2838 ;; -------------------------------------------------------------------------
2839 ;; Shifts and rotates
2840 ;; -------------------------------------------------------------------------
2842 ;; Let combine see that we can get the MSB and LSB into the T bit
2843 ;; via shll and shlr. This allows it to plug it into insns that can have
2844 ;; the T bit as an input (e.g. addc).
2845 ;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
2846 (define_insn_and_split "*reg_lsb_t"
2847 [(set (reg:SI T_REG)
2848 (and:SI (match_operand:SI 0 "arith_reg_operand")
2850 "TARGET_SH1 && can_create_pseudo_p ()"
2855 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
2856 : gen_shlr (gen_reg_rtx (SImode), operands[0]));
2859 (define_insn_and_split "*reg_msb_t"
2860 [(set (reg:SI T_REG)
2861 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
2863 "TARGET_SH1 && can_create_pseudo_p ()"
2868 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
2871 (define_expand "rotrsi3"
2872 [(set (match_operand:SI 0 "arith_reg_dest")
2873 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
2874 (match_operand:SI 2 "const_int_operand")))]
2877 HOST_WIDE_INT ival = INTVAL (operands[2]);
2880 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
2887 (define_insn "rotrsi3_1"
2888 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2889 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2892 (and:SI (match_dup 1) (const_int 1)))]
2895 [(set_attr "type" "arith")])
2897 ;; A slimplified version of rotr for combine.
2898 (define_insn "*rotrsi3_1"
2899 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2900 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2902 (clobber (reg:SI T_REG))]
2905 [(set_attr "type" "arith")])
2907 (define_insn "rotlsi3_1"
2908 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2909 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2912 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2915 [(set_attr "type" "arith")])
2917 ;; A simplified version of rotl for combine.
2918 (define_insn "*rotlsi3_1"
2919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2920 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2922 (clobber (reg:SI T_REG))]
2925 [(set_attr "type" "arith")])
2927 (define_insn "rotlsi3_31"
2928 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2929 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2931 (clobber (reg:SI T_REG))]
2934 [(set_attr "type" "arith")])
2936 (define_insn "rotlsi3_16"
2937 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2938 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2942 [(set_attr "type" "arith")])
2944 (define_expand "rotlsi3"
2945 [(set (match_operand:SI 0 "arith_reg_dest")
2946 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
2947 (match_operand:SI 2 "const_int_operand")))]
2950 static const char rot_tab[] = {
2951 000, 000, 000, 000, 000, 000, 010, 001,
2952 001, 001, 011, 013, 003, 003, 003, 003,
2953 003, 003, 003, 003, 003, 013, 012, 002,
2954 002, 002, 010, 000, 000, 000, 000, 000,
2957 int count = INTVAL (operands[2]);
2958 int choice = rot_tab[count];
2959 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2965 emit_move_insn (operands[0], operands[1]);
2966 count -= (count & 16) * 2;
2969 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2976 parts[0] = gen_reg_rtx (SImode);
2977 parts[1] = gen_reg_rtx (SImode);
2978 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2979 emit_move_insn (parts[choice-1], operands[1]);
2980 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2981 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2982 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2983 count = (count & ~16) - 8;
2987 for (; count > 0; count--)
2988 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2989 for (; count < 0; count++)
2990 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2995 (define_insn "rotlhi3_8"
2996 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
2997 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
3001 [(set_attr "type" "arith")])
3003 (define_expand "rotlhi3"
3004 [(set (match_operand:HI 0 "arith_reg_operand")
3005 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
3006 (match_operand:HI 2 "const_int_operand")))]
3009 if (INTVAL (operands[2]) != 8)
3013 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
3014 ;; They can also be used to implement things like
3016 ;; int x0 = (y >> 1) | (t << 31); // rotcr
3017 ;; int x1 = (y << 1) | t; // rotcl
3018 (define_insn "rotcr"
3019 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3020 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3022 (ashift:SI (match_operand:SI 2 "t_reg_operand")
3025 (and:SI (match_dup 1) (const_int 1)))]
3028 [(set_attr "type" "arith")])
3030 (define_insn "rotcl"
3031 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3032 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3034 (match_operand:SI 2 "t_reg_operand")))
3036 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3039 [(set_attr "type" "arith")])
3041 ;; Simplified rotcr version for combine, which allows arbitrary shift
3042 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
3043 ;; directly. Otherwise we have to insert a shift in between.
3044 (define_insn_and_split "*rotcr"
3045 [(set (match_operand:SI 0 "arith_reg_dest")
3046 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
3047 (match_operand:SI 2 "const_int_operand"))
3048 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
3050 (clobber (reg:SI T_REG))]
3051 "TARGET_SH1 && can_create_pseudo_p ()"
3056 rtx_insn *prev_set_t_insn = NULL;
3058 if (!arith_reg_operand (operands[3], SImode))
3060 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
3061 if (!ti.was_treg_operand ())
3062 prev_set_t_insn = ti.first_insn ();
3064 operands[3] = get_t_reg_rtx ();
3066 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
3068 /* Convert to a movrt, rotr sequence. */
3069 remove_insn (ti.trailing_nott ());
3070 rtx tmp = gen_reg_rtx (SImode);
3071 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
3072 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
3077 if (operands[1] == const0_rtx)
3079 operands[1] = gen_reg_rtx (SImode);
3080 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
3083 if (INTVAL (operands[2]) > 1)
3085 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3086 rtx tmp_t_reg = NULL_RTX;
3088 /* If we're going to emit a shift sequence that clobbers the T_REG,
3089 try to find the previous insn that sets the T_REG and emit the
3090 shift insn before that insn, to remove the T_REG dependency.
3091 If the insn that sets the T_REG cannot be found, store the T_REG
3092 in a temporary reg and restore it after the shift. */
3093 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
3094 && ! sh_dynamicalize_shift_p (shift_count))
3096 if (prev_set_t_insn == NULL)
3097 prev_set_t_insn = prev_nonnote_nondebug_insn_bb (curr_insn);
3099 /* Skip the nott insn, which was probably inserted by the splitter
3100 of *rotcr_neg_t. Don't use one of the recog functions
3101 here during insn splitting, since that causes problems in later
3103 if (prev_set_t_insn != NULL_RTX)
3105 rtx pat = PATTERN (prev_set_t_insn);
3106 if (GET_CODE (pat) == SET
3107 && t_reg_operand (XEXP (pat, 0), SImode)
3108 && negt_reg_operand (XEXP (pat, 1), SImode))
3109 prev_set_t_insn = prev_nonnote_nondebug_insn_bb
3113 if (! (prev_set_t_insn != NULL_RTX
3114 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3115 && ! reg_referenced_p (get_t_reg_rtx (),
3116 PATTERN (prev_set_t_insn))))
3118 prev_set_t_insn = NULL;
3119 tmp_t_reg = gen_reg_rtx (SImode);
3120 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3124 rtx shift_result = gen_reg_rtx (SImode);
3125 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
3126 operands[1] = shift_result;
3128 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3129 if (prev_set_t_insn != NULL_RTX)
3130 emit_insn_before (shift_insn, prev_set_t_insn);
3132 emit_insn (shift_insn);
3134 /* Restore T_REG if it has been saved before. */
3135 if (tmp_t_reg != NULL_RTX)
3136 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3139 /* For the rotcr insn to work, operands[3] must be in T_REG.
3140 If it is not we can get it there by shifting it right one bit.
3141 In this case T_REG is not an input for this insn, thus we don't have to
3142 pay attention as of where to insert the shlr insn. */
3143 if (! t_reg_operand (operands[3], SImode))
3145 /* We don't care about the shifted result here, only the T_REG. */
3146 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3147 operands[3] = get_t_reg_rtx ();
3150 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
3154 ;; If combine tries the same as above but with swapped operands, split
3155 ;; it so that it will try the pattern above.
3157 [(set (match_operand:SI 0 "arith_reg_dest")
3158 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
3160 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
3161 (match_operand:SI 3 "const_int_operand"))))]
3162 "TARGET_SH1 && can_create_pseudo_p ()"
3163 [(parallel [(set (match_dup 0)
3164 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3165 (ashift:SI (match_dup 1) (const_int 31))))
3166 (clobber (reg:SI T_REG))])])
3168 ;; Basically the same as the rotcr pattern above, but for rotcl.
3169 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
3170 (define_insn_and_split "*rotcl"
3171 [(set (match_operand:SI 0 "arith_reg_dest")
3172 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3173 (match_operand:SI 2 "const_int_operand"))
3174 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
3176 (clobber (reg:SI T_REG))]
3179 "&& can_create_pseudo_p ()"
3182 gcc_assert (INTVAL (operands[2]) > 0);
3184 if (INTVAL (operands[2]) > 1)
3186 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3187 rtx_insn *prev_set_t_insn = NULL;
3188 rtx tmp_t_reg = NULL_RTX;
3190 /* If we're going to emit a shift sequence that clobbers the T_REG,
3191 try to find the previous insn that sets the T_REG and emit the
3192 shift insn before that insn, to remove the T_REG dependency.
3193 If the insn that sets the T_REG cannot be found, store the T_REG
3194 in a temporary reg and restore it after the shift. */
3195 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
3196 && ! sh_dynamicalize_shift_p (shift_count))
3198 prev_set_t_insn = prev_nonnote_nondebug_insn_bb (curr_insn);
3200 /* Skip the nott insn, which was probably inserted by the splitter
3201 of *rotcl_neg_t. Don't use one of the recog functions
3202 here during insn splitting, since that causes problems in later
3204 if (prev_set_t_insn != NULL_RTX)
3206 rtx pat = PATTERN (prev_set_t_insn);
3207 if (GET_CODE (pat) == SET
3208 && t_reg_operand (XEXP (pat, 0), SImode)
3209 && negt_reg_operand (XEXP (pat, 1), SImode))
3210 prev_set_t_insn = prev_nonnote_nondebug_insn_bb
3214 if (! (prev_set_t_insn != NULL_RTX
3215 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3216 && ! reg_referenced_p (get_t_reg_rtx (),
3217 PATTERN (prev_set_t_insn))))
3219 prev_set_t_insn = NULL;
3220 tmp_t_reg = gen_reg_rtx (SImode);
3221 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3225 rtx shift_result = gen_reg_rtx (SImode);
3226 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
3227 operands[1] = shift_result;
3229 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3230 if (prev_set_t_insn != NULL_RTX)
3231 emit_insn_before (shift_insn, prev_set_t_insn);
3233 emit_insn (shift_insn);
3235 /* Restore T_REG if it has been saved before. */
3236 if (tmp_t_reg != NULL_RTX)
3237 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3240 /* For the rotcl insn to work, operands[3] must be in T_REG.
3241 If it is not we can get it there by shifting it right one bit.
3242 In this case T_REG is not an input for this insn, thus we don't have to
3243 pay attention as of where to insert the shlr insn. */
3244 if (! t_reg_operand (operands[3], SImode))
3246 /* We don't care about the shifted result here, only the T_REG. */
3247 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3248 operands[3] = get_t_reg_rtx ();
3251 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
3255 ;; rotcl combine pattern variations
3256 (define_insn_and_split "*rotcl"
3257 [(set (match_operand:SI 0 "arith_reg_dest")
3258 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3259 (match_operand:SI 2 "const_int_operand"))
3260 (match_operand 3 "treg_set_expr")))
3261 (clobber (reg:SI T_REG))]
3264 "&& can_create_pseudo_p ()"
3265 [(parallel [(set (match_dup 0)
3266 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3267 (and:SI (match_dup 3) (const_int 1))))
3268 (clobber (reg:SI T_REG))])]
3270 sh_split_treg_set_expr (operands[3], curr_insn);
3271 operands[3] = get_t_reg_rtx ();
3274 (define_insn_and_split "*rotcl"
3275 [(set (match_operand:SI 0 "arith_reg_dest")
3276 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
3278 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3279 (match_operand:SI 3 "const_int_operand"))))
3280 (clobber (reg:SI T_REG))]
3283 "&& can_create_pseudo_p ()"
3284 [(parallel [(set (match_dup 0)
3285 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3286 (and:SI (match_dup 1) (const_int 1))))
3287 (clobber (reg:SI T_REG))])])
3289 (define_insn_and_split "*rotcl"
3290 [(set (match_operand:SI 0 "arith_reg_dest")
3291 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3292 (match_operand:SI 2 "const_int_operand"))
3293 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3295 (clobber (reg:SI T_REG))]
3298 "&& can_create_pseudo_p ()"
3299 [(parallel [(set (match_dup 0)
3300 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3301 (and:SI (reg:SI T_REG) (const_int 1))))
3302 (clobber (reg:SI T_REG))])]
3304 /* We don't care about the result of the left shift, only the T_REG. */
3305 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3308 (define_insn_and_split "*rotcl"
3309 [(set (match_operand:SI 0 "arith_reg_dest")
3310 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3312 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3313 (match_operand:SI 2 "const_int_operand"))))
3314 (clobber (reg:SI T_REG))]
3317 "&& can_create_pseudo_p ()"
3318 [(parallel [(set (match_dup 0)
3319 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3320 (and:SI (reg:SI T_REG) (const_int 1))))
3321 (clobber (reg:SI T_REG))])]
3323 /* We don't care about the result of the left shift, only the T_REG. */
3324 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3327 (define_insn_and_split "*rotcl"
3328 [(set (match_operand:SI 0 "arith_reg_dest")
3329 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3330 (match_operand 2 "const_int_operand"))
3331 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
3333 (match_operand 4 "const_int_operand"))))
3334 (clobber (reg:SI T_REG))]
3337 "&& can_create_pseudo_p ()"
3338 [(parallel [(set (match_dup 0)
3339 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3340 (and:SI (match_dup 5) (const_int 1))))
3341 (clobber (reg:SI T_REG))])]
3343 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
3345 /* On SH2A we can use the bld insn to zero extract a single bit
3347 operands[5] = get_t_reg_rtx ();
3348 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
3352 /* If we can't use the bld insn we have to emit a tst + nott sequence
3353 to get the extracted bit into the T bit.
3354 This will probably be worse than pre-shifting the operand. */
3355 operands[5] = gen_reg_rtx (SImode);
3356 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
3360 ;; rotcr combine bridge pattern which will make combine try out more
3361 ;; complex patterns.
3362 (define_insn_and_split "*rotcr"
3363 [(set (match_operand:SI 0 "arith_reg_dest")
3364 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
3365 "TARGET_SH1 && can_create_pseudo_p ()"
3368 [(parallel [(set (match_dup 0)
3369 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
3370 (ashift:SI (match_dup 1) (const_int 31))))
3371 (clobber (reg:SI T_REG))])])
3373 (define_insn_and_split "*rotcr"
3374 [(set (match_operand:SI 0 "arith_reg_dest")
3375 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
3376 (const_int -2147483648)) ;; 0xffffffff80000000
3377 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3379 (clobber (reg:SI T_REG))]
3382 "&& can_create_pseudo_p ()"
3385 rtx tmp = gen_reg_rtx (SImode);
3386 emit_insn (gen_shll (tmp, operands[1]));
3387 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
3391 (define_insn_and_split "*rotcr"
3392 [(set (match_operand:SI 0 "arith_reg_dest")
3393 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3395 (const_int -2147483648))) ;; 0xffffffff80000000
3396 (clobber (reg:SI T_REG))]
3399 "&& can_create_pseudo_p ()"
3402 emit_insn (gen_sett ());
3403 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ()));
3407 ;; rotcr combine patterns for rotating in the negated T_REG value.
3408 (define_insn_and_split "*rotcr_neg_t"
3409 [(set (match_operand:SI 0 "arith_reg_dest")
3410 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
3411 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3412 (match_operand:SI 3 "const_int_operand"))))
3413 (clobber (reg:SI T_REG))]
3416 "&& can_create_pseudo_p ()"
3417 [(parallel [(set (match_dup 0)
3418 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3419 (ashift:SI (reg:SI T_REG) (const_int 31))))
3420 (clobber (reg:SI T_REG))])]
3422 emit_insn (gen_nott (get_t_reg_rtx ()));
3425 (define_insn_and_split "*rotcr_neg_t"
3426 [(set (match_operand:SI 0 "arith_reg_dest")
3427 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3428 (match_operand:SI 2 "const_int_operand"))
3429 (match_operand:SI 3 "negt_reg_shl31_operand")))
3430 (clobber (reg:SI T_REG))]
3433 "&& can_create_pseudo_p ()"
3434 [(parallel [(set (match_dup 0)
3435 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3436 (ashift:SI (reg:SI T_REG) (const_int 31))))
3437 (clobber (reg:SI T_REG))])]
3439 emit_insn (gen_nott (get_t_reg_rtx ()));
3442 ;; rotcl combine patterns for rotating in the negated T_REG value.
3443 ;; For some strange reason these have to be specified as splits which combine
3444 ;; will pick up. If they are specified as insn_and_split like the
3445 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
3446 ;; but not emit them on non-SH2A targets.
3448 [(set (match_operand:SI 0 "arith_reg_dest")
3449 (ior:SI (match_operand:SI 1 "negt_reg_operand")
3450 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3451 (match_operand:SI 3 "const_int_operand"))))]
3453 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3454 (parallel [(set (match_dup 0)
3455 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3456 (and:SI (reg:SI T_REG) (const_int 1))))
3457 (clobber (reg:SI T_REG))])])
3460 [(set (match_operand:SI 0 "arith_reg_dest")
3461 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3462 (match_operand:SI 3 "const_int_operand"))
3463 (match_operand:SI 1 "negt_reg_operand")))]
3465 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3466 (parallel [(set (match_dup 0)
3467 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3468 (and:SI (reg:SI T_REG) (const_int 1))))
3469 (clobber (reg:SI T_REG))])])
3471 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3472 ;; SImode shift left
3474 (define_expand "ashlsi3"
3475 [(set (match_operand:SI 0 "arith_reg_operand" "")
3476 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3477 (match_operand:SI 2 "shift_count_operand" "")))]
3481 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3483 /* Don't force the constant into a reg yet. Some other optimizations
3484 might not see through the reg that holds the shift count. */
3487 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
3489 if (CONST_INT_P (operands[2])
3490 && sh_ashlsi_clobbers_t_reg_p (operands[2])
3491 && ! sh_dynamicalize_shift_p (operands[2]))
3493 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
3498 /* Expand a library call for the dynamic shift. */
3499 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3501 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3502 rtx funcaddr = gen_reg_rtx (Pmode);
3503 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
3504 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
3510 (define_insn "ashlsi3_k"
3511 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3512 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
3513 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
3518 [(set_attr "type" "arith")])
3520 (define_insn_and_split "ashlsi3_d"
3521 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3522 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3523 (match_operand:SI 2 "shift_count_operand" "r")))]
3526 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3527 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3530 if (satisfies_constraint_P27 (operands[2]))
3532 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
3535 else if (! satisfies_constraint_P27 (operands[2]))
3537 /* This must happen before reload, otherwise the constant will be moved
3538 into a register due to the "r" constraint, after which this split
3539 cannot be done anymore.
3540 Unfortunately the move insn will not always be eliminated.
3541 Also, here we must not create a shift sequence that clobbers the
3543 emit_move_insn (operands[0], operands[1]);
3544 gen_shifty_op (ASHIFT, operands);
3550 [(set_attr "type" "dyn_shift")])
3552 ;; If dynamic shifts are not available use a library function.
3553 ;; By specifying the pattern we reduce the number of call clobbered regs.
3554 ;; In order to make combine understand the truncation of the shift amount
3555 ;; operand we have to allow it to use pseudo regs for the shift operands.
3556 (define_insn "ashlsi3_d_call"
3557 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3558 (ashift:SI (reg:SI R4_REG)
3559 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3561 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3562 (use (match_operand 3 "" "Z,Ccl"))
3563 (clobber (reg:SI T_REG))
3564 (clobber (reg:SI PR_REG))]
3565 "TARGET_SH1 && !TARGET_DYNSHIFT"
3569 [(set_attr "type" "sfunc")
3570 (set_attr "needs_delay_slot" "yes")])
3572 (define_insn_and_split "ashlsi3_n"
3573 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3574 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3575 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
3576 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3578 "&& (reload_completed
3579 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3582 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3584 /* If this pattern was picked and dynamic shifts are supported, switch
3585 to dynamic shift pattern before reload. */
3586 operands[2] = force_reg (SImode, operands[2]);
3587 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3590 gen_shifty_op (ASHIFT, operands);
3595 (define_insn_and_split "ashlsi3_n_clobbers_t"
3596 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3597 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3598 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
3599 (clobber (reg:SI T_REG))]
3600 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
3602 "&& (reload_completed || INTVAL (operands[2]) == 31
3603 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3606 if (INTVAL (operands[2]) == 31)
3608 /* If the shift amount is 31 we split into a different sequence before
3609 reload so that it gets a chance to allocate R0 for the sequence.
3610 If it fails to do so (due to pressure on R0), it will take one insn
3611 more for the and. */
3612 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
3613 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3615 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3617 /* If this pattern was picked and dynamic shifts are supported, switch
3618 to dynamic shift pattern before reload. */
3619 operands[2] = force_reg (SImode, operands[2]);
3620 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3623 gen_shifty_op (ASHIFT, operands);
3629 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3630 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3632 (lt:SI (match_dup 1) (const_int 0)))]
3635 [(set_attr "type" "arith")])
3637 (define_insn "*ashlsi_c_void"
3638 [(set (reg:SI T_REG)
3639 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3640 (clobber (match_scratch:SI 1 "=0"))]
3641 "TARGET_SH1 && cse_not_expected"
3643 [(set_attr "type" "arith")])
3646 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3648 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3650 && peep2_reg_dead_p (2, operands[0])
3651 && peep2_reg_dead_p (2, operands[1])"
3654 emit_insn (gen_shll (operands[1], operands[1]));
3658 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3659 ;; HImode shift left
3661 (define_expand "ashlhi3"
3662 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3663 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3664 (match_operand:SI 2 "nonmemory_operand" "")))
3665 (clobber (reg:SI T_REG))])]
3668 if (!CONST_INT_P (operands[2]))
3670 /* It may be possible to call gen_ashlhi3 directly with more generic
3671 operands. Make sure operands[1] is a HImode register here. */
3672 if (!arith_reg_operand (operands[1], HImode))
3673 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3676 (define_insn "ashlhi3_k"
3677 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3678 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3679 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3680 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3684 [(set_attr "type" "arith")])
3686 (define_insn_and_split "*ashlhi3_n"
3687 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3688 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3689 (match_operand:HI 2 "const_int_operand" "n")))
3690 (clobber (reg:SI T_REG))]
3693 "&& reload_completed"
3694 [(use (reg:SI R0_REG))]
3696 gen_shifty_hi_op (ASHIFT, operands);
3700 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3701 ;; DImode shift left
3703 (define_expand "ashldi3"
3704 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3705 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
3706 (match_operand:DI 2 "immediate_operand" "")))
3707 (clobber (reg:SI T_REG))])]
3710 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
3712 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
3715 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
3717 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
3724 ;; Expander for DImode shift left with SImode operations.
3725 (define_expand "ashldi3_std"
3726 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3727 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3728 (match_operand:DI 2 "const_int_operand" "n")))]
3729 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3731 rtx low_src = gen_lowpart (SImode, operands[1]);
3732 rtx high_src = gen_highpart (SImode, operands[1]);
3733 rtx dst = gen_reg_rtx (DImode);
3734 rtx low_dst = gen_lowpart (SImode, dst);
3735 rtx high_dst = gen_highpart (SImode, dst);
3736 rtx tmp0 = gen_reg_rtx (SImode);
3737 rtx tmp1 = gen_reg_rtx (SImode);
3739 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3740 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3741 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3742 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3743 emit_move_insn (operands[0], dst);
3747 (define_insn_and_split "ashldi3_k"
3748 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3749 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3751 (clobber (reg:SI T_REG))]
3754 "&& reload_completed"
3757 rtx high = gen_highpart (SImode, operands[0]);
3758 rtx low = gen_lowpart (SImode, operands[0]);
3759 emit_insn (gen_shll (low, low));
3760 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
3764 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3765 ;; SImode arithmetic shift right
3767 ;; We can't do HImode right shifts correctly unless we start out with an
3768 ;; explicit zero / sign extension; doing that would result in worse overall
3769 ;; code, so just let the machine independent code widen the mode.
3770 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3772 (define_expand "ashrsi3"
3773 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3774 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3775 (match_operand:SI 2 "nonmemory_operand" "")))
3776 (clobber (reg:SI T_REG))])]
3779 if (expand_ashiftrt (operands))
3786 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3787 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3790 (and:SI (match_dup 1) (const_int 1)))]
3793 [(set_attr "type" "arith")])
3795 (define_insn "ashrsi3_k"
3796 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3797 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3798 (match_operand:SI 2 "const_int_operand" "M")))
3799 (clobber (reg:SI T_REG))]
3800 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3802 [(set_attr "type" "arith")])
3804 (define_insn_and_split "ashrsi2_16"
3805 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3806 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3811 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3812 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3814 operands[2] = gen_lowpart (HImode, operands[0]);
3817 (define_insn_and_split "ashrsi2_31"
3818 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3819 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3821 (clobber (reg:SI T_REG))]
3827 emit_insn (gen_shll (operands[0], operands[1]));
3828 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3832 ;; If the shift amount is changed by combine it will try to plug the
3833 ;; use on the symbol of the library function and the PR clobber.
3834 (define_insn_and_split "*ashrsi2_31"
3835 [(set (match_operand:SI 0 "arith_reg_dest")
3836 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3838 (clobber (reg:SI T_REG))
3839 (clobber (reg:SI PR_REG))
3840 (use (match_operand:SI 2 "symbol_ref_operand"))]
3844 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
3845 (clobber (reg:SI T_REG))])])
3847 (define_insn "ashrsi3_d"
3848 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3849 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3850 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3853 [(set_attr "type" "dyn_shift")])
3855 (define_insn "ashrsi3_n"
3856 [(set (reg:SI R4_REG)
3857 (ashiftrt:SI (reg:SI R4_REG)
3858 (match_operand:SI 0 "const_int_operand" "i,i")))
3859 (clobber (reg:SI T_REG))
3860 (clobber (reg:SI PR_REG))
3861 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
3862 (use (match_operand 2 "" "Z,Ccl"))]
3867 [(set_attr "type" "sfunc")
3868 (set_attr "needs_delay_slot" "yes")])
3870 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3871 ;; DImode arithmetic shift right
3873 (define_expand "ashrdi3"
3874 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3875 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
3876 (match_operand:DI 2 "immediate_operand" "")))
3877 (clobber (reg:SI T_REG))])]
3880 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
3884 (define_insn_and_split "ashrdi3_k"
3885 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3886 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
3888 (clobber (reg:SI T_REG))]
3891 "&& reload_completed"
3894 rtx high = gen_highpart (SImode, operands[0]);
3895 rtx low = gen_lowpart (SImode, operands[0]);
3896 emit_insn (gen_shar (high, high));
3897 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
3901 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3902 ;; SImode logical shift right
3904 (define_expand "lshrsi3"
3905 [(set (match_operand:SI 0 "arith_reg_dest" "")
3906 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3907 (match_operand:SI 2 "shift_count_operand" "")))]
3910 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
3911 here, otherwise the pattern will never match due to the shift amount reg
3914 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3916 /* Don't force the constant into a reg yet. Some other optimizations
3917 might not see through the reg that holds the shift count. */
3918 if (sh_lshrsi_clobbers_t_reg_p (operands[2]))
3919 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2]));
3921 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2]));
3925 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
3927 rtx neg_count = gen_reg_rtx (SImode);
3928 emit_insn (gen_negsi2 (neg_count, operands[2]));
3929 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
3933 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
3935 if (CONST_INT_P (operands[2])
3936 && sh_lshrsi_clobbers_t_reg_p (operands[2])
3937 && ! sh_dynamicalize_shift_p (operands[2]))
3939 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
3944 /* Expand a library call for the dynamic shift. */
3945 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3947 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3948 rtx funcaddr = gen_reg_rtx (Pmode);
3949 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
3950 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
3955 (define_insn "lshrsi3_k"
3956 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3957 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3958 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
3961 [(set_attr "type" "arith")])
3963 (define_insn_and_split "lshrsi3_d"
3964 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3965 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3966 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
3969 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3970 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
3973 /* The shift count const_int is a negative value for all dynamic
3974 right shift insns. */
3975 operands[2] = GEN_INT (- INTVAL (operands[2]));
3977 if (satisfies_constraint_P27 (operands[2]))
3979 /* This will not be done for a shift amount of 1, because it would
3980 clobber the T_REG. */
3981 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
3984 else if (! satisfies_constraint_P27 (operands[2]))
3986 /* This must happen before reload, otherwise the constant will be moved
3987 into a register due to the "r" constraint, after which this split
3988 cannot be done anymore.
3989 Unfortunately the move insn will not always be eliminated.
3990 Also, here we must not create a shift sequence that clobbers the
3992 emit_move_insn (operands[0], operands[1]);
3993 gen_shifty_op (LSHIFTRT, operands);
3999 [(set_attr "type" "dyn_shift")])
4001 ;; If dynamic shifts are not available use a library function.
4002 ;; By specifying the pattern we reduce the number of call clobbered regs.
4003 ;; In order to make combine understand the truncation of the shift amount
4004 ;; operand we have to allow it to use pseudo regs for the shift operands.
4005 (define_insn "lshrsi3_d_call"
4006 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
4007 (lshiftrt:SI (reg:SI R4_REG)
4008 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
4010 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
4011 (use (match_operand 3 "" "Z,Ccl"))
4012 (clobber (reg:SI T_REG))
4013 (clobber (reg:SI PR_REG))]
4014 "TARGET_SH1 && !TARGET_DYNSHIFT"
4018 [(set_attr "type" "sfunc")
4019 (set_attr "needs_delay_slot" "yes")])
4021 (define_insn_and_split "lshrsi3_n"
4022 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4023 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4024 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
4025 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
4027 "&& (reload_completed
4028 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4031 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4033 /* If this pattern was picked and dynamic shifts are supported, switch
4034 to dynamic shift pattern before reload. */
4035 operands[2] = GEN_INT (- INTVAL (operands[2]));
4036 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4039 gen_shifty_op (LSHIFTRT, operands);
4044 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
4045 ;; the shlr pattern.
4046 (define_insn_and_split "lshrsi3_n_clobbers_t"
4047 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4048 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4049 (match_operand:SI 2 "not_p27_rshift_count_operand")))
4050 (clobber (reg:SI T_REG))]
4051 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
4053 "&& (reload_completed || INTVAL (operands[2]) == 31
4054 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4057 if (INTVAL (operands[2]) == 31)
4059 emit_insn (gen_shll (operands[0], operands[1]));
4060 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
4062 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4064 /* If this pattern was picked and dynamic shifts are supported, switch
4065 to dynamic shift pattern before reload. */
4066 operands[2] = GEN_INT (- INTVAL (operands[2]));
4067 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4070 gen_shifty_op (LSHIFTRT, operands);
4076 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4080 (and:SI (match_dup 1) (const_int 1)))]
4083 [(set_attr "type" "arith")])
4085 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4086 ;; DImode logical shift right
4088 (define_expand "lshrdi3"
4089 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4090 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4091 (match_operand:DI 2 "immediate_operand" "")))
4092 (clobber (reg:SI T_REG))])]
4095 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4099 (define_insn_and_split "lshrdi3_k"
4100 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4101 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4103 (clobber (reg:SI T_REG))]
4106 "&& reload_completed"
4109 rtx high = gen_highpart (SImode, operands[0]);
4110 rtx low = gen_lowpart (SImode, operands[0]);
4111 emit_insn (gen_shlr (high, high));
4112 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4116 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4117 ;; Combined left/right shifts
4120 [(set (match_operand:SI 0 "register_operand" "")
4121 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4122 (match_operand:SI 2 "const_int_operand" ""))
4123 (match_operand:SI 3 "const_int_operand" "")))]
4124 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4125 [(use (reg:SI R0_REG))]
4127 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4133 [(set (match_operand:SI 0 "register_operand" "")
4134 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4135 (match_operand:SI 2 "const_int_operand" ""))
4136 (match_operand:SI 3 "const_int_operand" "")))
4137 (clobber (reg:SI T_REG))]
4138 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4139 [(use (reg:SI R0_REG))]
4141 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4147 [(set (match_operand:SI 0 "register_operand" "=r")
4148 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4149 (match_operand:SI 2 "const_int_operand" "n"))
4150 (match_operand:SI 3 "const_int_operand" "n")))
4151 (clobber (reg:SI T_REG))]
4152 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4154 [(set (attr "length")
4155 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4157 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4159 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4161 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4163 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4165 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4167 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4168 (const_string "16")]
4169 (const_string "18")))
4170 (set_attr "type" "arith")])
4173 [(set (match_operand:SI 0 "register_operand" "=z")
4174 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4175 (match_operand:SI 2 "const_int_operand" "n"))
4176 (match_operand:SI 3 "const_int_operand" "n")))
4177 (clobber (reg:SI T_REG))]
4178 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4180 [(set (attr "length")
4181 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4183 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4185 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4187 (const_string "10")))
4188 (set_attr "type" "arith")])
4190 ;; shift left / and combination with a scratch register: The combine pass
4191 ;; does not accept the individual instructions, even though they are
4192 ;; cheap. But it needs a precise description so that it is usable after
4194 (define_insn "and_shl_scratch"
4195 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4199 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4200 (match_operand:SI 2 "const_int_operand" "N,n"))
4201 (match_operand:SI 3 "" "0,r"))
4202 (match_operand:SI 4 "const_int_operand" "n,n"))
4203 (match_operand:SI 5 "const_int_operand" "n,n")))
4204 (clobber (reg:SI T_REG))]
4207 [(set (attr "length")
4208 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4210 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4212 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4214 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4215 (const_string "10")]
4216 (const_string "12")))
4217 (set_attr "type" "arith")])
4220 [(set (match_operand:SI 0 "register_operand" "")
4224 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4225 (match_operand:SI 2 "const_int_operand" ""))
4226 (match_operand:SI 3 "register_operand" ""))
4227 (match_operand:SI 4 "const_int_operand" ""))
4228 (match_operand:SI 5 "const_int_operand" "")))
4229 (clobber (reg:SI T_REG))]
4231 [(use (reg:SI R0_REG))]
4233 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4235 if (INTVAL (operands[2]))
4237 gen_shifty_op (LSHIFTRT, operands);
4239 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4240 operands[2] = operands[4];
4241 gen_shifty_op (ASHIFT, operands);
4242 if (INTVAL (operands[5]))
4244 operands[2] = operands[5];
4245 gen_shifty_op (LSHIFTRT, operands);
4250 ;; signed left/right shift combination.
4252 [(set (match_operand:SI 0 "register_operand" "")
4254 (ashift:SI (match_operand:SI 1 "register_operand" "")
4255 (match_operand:SI 2 "const_int_operand" ""))
4256 (match_operand:SI 3 "const_int_operand" "")
4258 (clobber (reg:SI T_REG))]
4260 [(use (reg:SI R0_REG))]
4262 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
4267 (define_insn "shl_sext_ext"
4268 [(set (match_operand:SI 0 "register_operand" "=r")
4270 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4271 (match_operand:SI 2 "const_int_operand" "n"))
4272 (match_operand:SI 3 "const_int_operand" "n")
4274 (clobber (reg:SI T_REG))]
4275 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4277 [(set (attr "length")
4278 (cond [(match_test "shl_sext_length (insn)")
4280 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4282 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4284 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4286 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4288 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4290 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4292 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4293 (const_string "16")]
4294 (const_string "18")))
4295 (set_attr "type" "arith")])
4297 (define_insn "shl_sext_sub"
4298 [(set (match_operand:SI 0 "register_operand" "=z")
4300 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4301 (match_operand:SI 2 "const_int_operand" "n"))
4302 (match_operand:SI 3 "const_int_operand" "n")
4304 (clobber (reg:SI T_REG))]
4305 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4307 [(set (attr "length")
4308 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4310 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4312 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4314 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4315 (const_string "12")]
4316 (const_string "14")))
4317 (set_attr "type" "arith")])
4319 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
4320 ;; shifts by 16, and allow the xtrct instruction to be generated from C
4322 (define_insn "xtrct_left"
4323 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4324 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4326 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4330 [(set_attr "type" "arith")])
4332 (define_insn "xtrct_right"
4333 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4334 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4336 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4340 [(set_attr "type" "arith")])
4342 ;; -------------------------------------------------------------------------
4344 ;; -------------------------------------------------------------------------
4347 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4348 (neg:SI (plus:SI (reg:SI T_REG)
4349 (match_operand:SI 1 "arith_reg_operand" "r"))))
4351 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4355 [(set_attr "type" "arith")])
4357 ;; A simplified version of the negc insn, where the exact value of the
4358 ;; T bit doesn't matter. This is easier for combine to pick up.
4359 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
4360 ;; extra patterns for this case.
4361 (define_insn_and_split "*negc"
4362 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4363 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
4364 (match_operand 2 "treg_set_expr")))
4365 (clobber (reg:SI T_REG))]
4366 "TARGET_SH1 && can_create_pseudo_p ()"
4371 sh_split_treg_set_expr (operands[2], curr_insn);
4372 emit_insn (gen_negc (operands[0], operands[1]));
4376 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
4378 (define_insn_and_split "negdi2"
4379 [(set (match_operand:DI 0 "arith_reg_dest")
4380 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
4381 (clobber (reg:SI T_REG))]
4384 "&& can_create_pseudo_p ()"
4387 emit_insn (gen_clrt ());
4388 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4389 gen_lowpart (SImode, operands[1])));
4390 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4391 gen_highpart (SImode, operands[1])));
4395 (define_insn "negsi2"
4396 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4397 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4400 [(set_attr "type" "arith")])
4402 (define_insn_and_split "one_cmplsi2"
4403 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4404 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4407 "&& can_create_pseudo_p ()"
4408 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
4409 (set (match_dup 0) (reg:SI T_REG))]
4412 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
4415 (set (reg0) (not:SI (reg0) (reg1)))
4416 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
4417 (clobber (reg:SI T_REG))])
4419 ... match and combine the sequence manually in the split pass after the
4420 combine pass. Notice that combine does try the target pattern of this
4421 split, but if the pattern is added it interferes with other patterns, in
4422 particular with the div0s comparisons.
4423 This could also be done with a peephole but doing it here before register
4424 allocation can save one temporary.
4425 When we're here, the not:SI pattern obviously has been matched already
4426 and we only have to see whether the following insn is the left shift. */
4428 rtx_insn *i = next_nonnote_nondebug_insn_bb (curr_insn);
4429 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
4432 rtx p = PATTERN (i);
4433 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
4436 rtx p0 = XVECEXP (p, 0, 0);
4437 rtx p1 = XVECEXP (p, 0, 1);
4439 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
4440 GET_CODE (p0) == SET
4441 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
4442 && REG_P (XEXP (XEXP (p0, 1), 0))
4443 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
4444 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
4445 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
4447 /* (clobber (reg:SI T_REG)) */
4448 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
4449 && REGNO (XEXP (p1, 0)) == T_REG)
4451 operands[0] = XEXP (p0, 0);
4452 set_insn_deleted (i);
4457 [(set_attr "type" "arith")])
4459 (define_insn_and_split "abs<mode>2"
4460 [(set (match_operand:SIDI 0 "arith_reg_dest")
4461 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
4462 (clobber (reg:SI T_REG))]
4465 "&& can_create_pseudo_p ()"
4468 if (<MODE>mode == SImode)
4469 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4472 rtx high_src = gen_highpart (SImode, operands[1]);
4473 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4476 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4481 (define_insn_and_split "*negabs<mode>2"
4482 [(set (match_operand:SIDI 0 "arith_reg_dest")
4483 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
4484 (clobber (reg:SI T_REG))]
4487 "&& can_create_pseudo_p ()"
4490 if (<MODE>mode == SImode)
4491 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4494 rtx high_src = gen_highpart (SImode, operands[1]);
4495 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4498 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4503 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4504 ;; This can be used as some kind of conditional execution, which is useful
4506 ;; Actually the instruction scheduling should decide whether to use a
4507 ;; zero-offset branch or not for any generic case involving a single
4508 ;; instruction on SH4 202.
4509 (define_insn_and_split "negsi_cond"
4510 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4512 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
4513 (match_operand:SI 1 "arith_reg_operand" "0,0")
4514 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4515 "TARGET_SH1 && TARGET_ZDCBRANCH"
4517 static const char* alt[] =
4527 return alt[which_alternative];
4529 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
4532 rtx_code_label *skip_neg_label = gen_label_rtx ();
4534 emit_move_insn (operands[0], operands[1]);
4536 emit_jump_insn (INTVAL (operands[3])
4537 ? gen_branch_true (skip_neg_label)
4538 : gen_branch_false (skip_neg_label));
4540 emit_label_after (skip_neg_label,
4541 emit_insn (gen_negsi2 (operands[0], operands[1])));
4544 [(set_attr "type" "arith") ;; poor approximation
4545 (set_attr "length" "4")])
4547 (define_insn_and_split "negdi_cond"
4548 [(set (match_operand:DI 0 "arith_reg_dest")
4550 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
4551 (match_operand:DI 1 "arith_reg_operand")
4552 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
4553 (clobber (reg:SI T_REG))]
4556 "&& can_create_pseudo_p ()"
4559 rtx_code_label *skip_neg_label = gen_label_rtx ();
4561 emit_move_insn (operands[0], operands[1]);
4563 emit_jump_insn (INTVAL (operands[3])
4564 ? gen_branch_true (skip_neg_label)
4565 : gen_branch_false (skip_neg_label));
4567 if (!INTVAL (operands[3]))
4568 emit_insn (gen_clrt ());
4570 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4571 gen_lowpart (SImode, operands[1])));
4572 emit_label_after (skip_neg_label,
4573 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4574 gen_highpart (SImode, operands[1]))));
4578 (define_expand "bswapsi2"
4579 [(set (match_operand:SI 0 "arith_reg_dest" "")
4580 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
4583 if (! can_create_pseudo_p ())
4587 rtx tmp0 = gen_reg_rtx (SImode);
4588 rtx tmp1 = gen_reg_rtx (SImode);
4590 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
4591 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
4592 emit_insn (gen_swapbsi2 (operands[0], tmp1));
4597 (define_insn "swapbsi2"
4598 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4599 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4600 (const_int -65536)) ;; 0xFFFF0000
4601 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4603 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4604 (const_int 255)))))]
4607 [(set_attr "type" "arith")])
4609 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
4610 ;; partial byte swap expressions such as...
4611 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
4612 ;; ...which are currently not handled by the tree optimizers.
4613 ;; The combine pass will not initially try to combine the full expression,
4614 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
4615 ;; pattern acts as an intermediate pattern that will eventually lead combine
4616 ;; to the swapbsi2 pattern above.
4617 ;; As a side effect this also improves code that does (x & 0xFF) << 8
4618 ;; or (x << 8) & 0xFF00.
4619 (define_insn_and_split "*swapbisi2_and_shl8"
4620 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4621 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4624 (match_operand:SI 2 "arith_reg_operand" "r")))]
4625 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4627 "&& can_create_pseudo_p ()"
4630 rtx tmp0 = gen_reg_rtx (SImode);
4631 rtx tmp1 = gen_reg_rtx (SImode);
4633 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
4634 emit_insn (gen_swapbsi2 (tmp1, tmp0));
4635 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
4639 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
4640 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
4641 (define_insn_and_split "*swapbhisi2"
4642 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4643 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4646 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
4647 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4649 "&& can_create_pseudo_p ()"
4652 rtx tmp = gen_reg_rtx (SImode);
4654 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
4655 emit_insn (gen_swapbsi2 (operands[0], tmp));
4659 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
4663 ;; which can be simplified to...
4666 [(set (match_operand:SI 0 "arith_reg_dest" "")
4667 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4668 (const_int -65536)) ;; 0xFFFF0000
4669 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4671 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4673 (set (match_operand:SI 2 "arith_reg_dest" "")
4675 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
4677 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4678 (const_int -65536)) ;; 0xFFFF0000
4679 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4681 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4682 (const_int 255)))))])
4684 ;; -------------------------------------------------------------------------
4685 ;; Zero extension instructions
4686 ;; -------------------------------------------------------------------------
4688 (define_expand "zero_extend<mode>si2"
4689 [(set (match_operand:SI 0 "arith_reg_dest")
4690 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
4692 (define_insn_and_split "*zero_extend<mode>si2_compact"
4693 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4694 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4697 "&& can_create_pseudo_p ()"
4698 [(set (match_dup 0) (match_dup 2))]
4700 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4701 reg with a following zero extension. In the split pass after combine,
4702 try to figure out how the extended reg was set. If it originated from
4703 the T bit we can replace the zero extension with a reg move, which will
4704 be eliminated. Notice that this also helps the *cbranch_t splitter when
4705 it tries to post-combine tests and conditional branches, as it does not
4706 check for zero extensions. */
4707 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4708 if (operands[2] == NULL_RTX)
4711 [(set_attr "type" "arith")])
4713 (define_insn "zero_extendqihi2"
4714 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4715 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4718 [(set_attr "type" "arith")])
4720 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
4721 ;; They could also be used for simple memory addresses like @Rn by setting
4722 ;; the displacement value to zero. However, doing so too early results in
4723 ;; missed opportunities for other optimizations such as post-inc or index
4724 ;; addressing loads.
4725 ;; We don't allow the zero extending loads to match during RTL expansion,
4726 ;; as this would pessimize other optimization opportunities such as bit
4727 ;; extractions of unsigned mems, where the zero extraction is irrelevant.
4728 ;; If the zero extracting mem loads are emitted early it will be more
4729 ;; difficult to change them back to sign extending loads (which are preferred).
4730 ;; The combine pass will also try to combine mem loads and zero extends,
4731 ;; which is prevented by 'sh_legitimate_combined_insn'.
4732 (define_insn "*zero_extend<mode>si2_disp_mem"
4733 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4735 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
4739 movu.<bw> @(0,%t1),%0"
4740 [(set_attr "type" "load")
4741 (set_attr "length" "4")])
4743 ;; Convert the zero extending loads in sequences such as:
4744 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
4745 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4747 ;; back to sign extending loads like:
4748 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
4749 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4751 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
4752 ;; is only 2 bytes in size if the displacement is {K04|K05}.
4753 ;; If the displacement is greater it doesn't matter, so we convert anyways.
4755 [(set (match_operand:SI 0 "arith_reg_dest" "")
4756 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
4757 (set (match_operand 2 "nonimmediate_operand" "")
4758 (match_operand 3 "arith_reg_operand" ""))]
4760 && REGNO (operands[0]) == REGNO (operands[3])
4761 && peep2_reg_dead_p (2, operands[0])
4762 && GET_MODE_SIZE (GET_MODE (operands[2]))
4763 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
4764 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
4765 (set (match_dup 2) (match_dup 3))])
4767 ;; Fold sequences such as
4771 ;; movu.b @(0,r3),r7
4772 ;; This does not reduce the code size but the number of instructions is
4773 ;; halved, which results in faster code.
4775 [(set (match_operand:SI 0 "arith_reg_dest" "")
4776 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
4777 (set (match_operand:SI 2 "arith_reg_dest" "")
4778 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
4780 && GET_MODE (operands[1]) == GET_MODE (operands[3])
4781 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
4782 && REGNO (operands[0]) == REGNO (operands[3])
4783 && (REGNO (operands[2]) == REGNO (operands[0])
4784 || peep2_reg_dead_p (2, operands[0]))"
4785 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
4788 = replace_equiv_address (operands[1],
4789 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
4793 ;; -------------------------------------------------------------------------
4794 ;; Sign extension instructions
4795 ;; -------------------------------------------------------------------------
4797 ;; ??? This should be a define expand.
4798 ;; ??? Or perhaps it should be dropped?
4800 ;; convert_move generates good code for SH[1-4].
4802 (define_expand "extend<mode>si2"
4803 [(set (match_operand:SI 0 "arith_reg_dest")
4804 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
4806 (define_insn_and_split "*extend<mode>si2_compact_reg"
4807 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4808 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4811 "&& can_create_pseudo_p ()"
4812 [(set (match_dup 0) (match_dup 2))]
4814 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4815 reg with a following sign extension. In the split pass after combine,
4816 try to figure the extended reg was set. If it originated from the T
4817 bit we can replace the sign extension with a reg move, which will be
4819 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4820 if (operands[2] == NULL_RTX)
4823 [(set_attr "type" "arith")])
4825 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4827 (define_insn "*extend<mode>si2_compact_mem_disp"
4828 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4832 (match_operand:SI 1 "arith_reg_operand" "%r,r")
4833 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
4834 "TARGET_SH1 && ! TARGET_SH2A
4835 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
4837 mov.<bw> @(%O2,%1),%0
4839 [(set_attr "type" "load")])
4841 (define_insn "*extend<mode>si2_compact_mem_disp"
4842 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4846 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4847 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
4848 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
4850 mov.<bw> @(%O2,%1),%0
4852 mov.<bw> @(%O2,%1),%0"
4853 [(set_attr "type" "load")
4854 (set_attr "length" "2,2,4")])
4856 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
4857 ;; constraints, otherwise wrong code might get generated.
4858 (define_insn "*extend<mode>si2_predec"
4859 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4860 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))]
4863 [(set_attr "type" "load")])
4865 ;; The *_snd patterns will take care of other QImode/HImode addressing
4866 ;; modes than displacement addressing. They must be defined _after_ the
4867 ;; displacement addressing patterns. Otherwise the displacement addressing
4868 ;; patterns will not be picked.
4869 (define_insn "*extend<mode>si2_compact_snd"
4870 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4872 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4875 [(set_attr "type" "load")])
4877 (define_expand "extendqihi2"
4878 [(set (match_operand:HI 0 "arith_reg_dest")
4879 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
4882 (define_insn "*extendqihi2_compact_reg"
4883 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4884 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4887 [(set_attr "type" "arith")])
4889 ;; -------------------------------------------------------------------------
4890 ;; Move instructions
4891 ;; -------------------------------------------------------------------------
4893 (define_expand "push"
4894 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4895 (match_operand:SI 0 "register_operand"))])
4897 (define_expand "pop"
4898 [(set (match_operand:SI 0 "register_operand")
4899 (mem:SI (post_inc:SI (reg:SI SP_REG))))])
4901 (define_expand "push_e"
4902 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
4903 (match_operand:SF 0 "" ""))
4904 (use (reg:SI FPSCR_MODES_REG))
4905 (clobber (scratch:SI))])])
4907 (define_insn "push_fpul"
4908 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
4911 [(set_attr "type" "fstore")
4912 (set_attr "late_fp_use" "yes")
4913 (set_attr "hit_stack" "yes")])
4915 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
4917 (define_expand "push_4"
4918 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
4919 (match_operand:DF 0 "" ""))
4920 (use (reg:SI FPSCR_MODES_REG))
4921 (clobber (scratch:SI))])])
4923 (define_expand "pop_e"
4924 [(parallel [(set (match_operand:SF 0 "" "")
4925 (mem:SF (post_inc:SI (reg:SI SP_REG))))
4926 (use (reg:SI FPSCR_MODES_REG))
4927 (clobber (scratch:SI))])])
4929 (define_insn "pop_fpul"
4930 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
4933 [(set_attr "type" "load")
4934 (set_attr "hit_stack" "yes")])
4936 (define_expand "pop_4"
4937 [(parallel [(set (match_operand:DF 0 "" "")
4938 (mem:DF (post_inc:SI (reg:SI SP_REG))))
4939 (use (reg:SI FPSCR_MODES_REG))
4940 (clobber (scratch:SI))])])
4942 (define_expand "push_fpscr"
4949 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
4950 REG_INC, stack_pointer_rtx);
4954 (define_expand "pop_fpscr"
4961 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
4962 REG_INC, stack_pointer_rtx);
4966 ;; The clrt and sett patterns can happen as the result of optimization and
4968 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
4969 ;; In this case they might not disappear completely, because the T reg is
4970 ;; a fixed hard reg.
4971 ;; When DImode operations that use the T reg as carry/borrow are split into
4972 ;; individual SImode operations, the T reg is usually cleared before the
4973 ;; first SImode insn.
4975 [(set (reg:SI T_REG) (const_int 0))]
4978 [(set_attr "type" "mt_group")])
4981 [(set (reg:SI T_REG) (const_int 1))]
4984 [(set_attr "type" "mt_group")])
4986 ;; Use the combine pass to transform sequences such as
4990 ;; mov.l @(r0,r4),r0
4996 ;; See also PR 39423.
4997 ;; Notice that these patterns have a T_REG clobber, because the shift
4998 ;; sequence that will be split out might clobber the T_REG. Ideally, the
4999 ;; clobber would be added conditionally, depending on the result of
5000 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
5001 ;; through the ashlsi3 expander in order to get the right shift insn --
5002 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
5003 ;; FIXME: Combine never tries this kind of patterns for DImode.
5004 (define_insn_and_split "*movsi_index_disp_load"
5005 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5006 (match_operand:SI 1 "mem_index_disp_operand" "m"))
5007 (clobber (reg:SI T_REG))]
5010 "&& can_create_pseudo_p ()"
5011 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5012 (set (match_dup 0) (match_dup 7))]
5014 rtx mem = operands[1];
5015 rtx plus0_rtx = XEXP (mem, 0);
5016 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5017 rtx mult_rtx = XEXP (plus1_rtx, 0);
5019 operands[1] = XEXP (mult_rtx, 0);
5020 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5021 operands[3] = XEXP (plus1_rtx, 1);
5022 operands[4] = XEXP (plus0_rtx, 1);
5023 operands[5] = gen_reg_rtx (SImode);
5024 operands[6] = gen_reg_rtx (SImode);
5026 replace_equiv_address (mem,
5027 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5029 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
5032 (define_insn_and_split "*movhi_index_disp_load"
5033 [(set (match_operand:SI 0 "arith_reg_dest")
5034 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
5035 (clobber (reg:SI T_REG))]
5038 "&& can_create_pseudo_p ()"
5041 rtx mem = operands[1];
5042 rtx plus0_rtx = XEXP (mem, 0);
5043 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5044 rtx mult_rtx = XEXP (plus1_rtx, 0);
5046 rtx op_1 = XEXP (mult_rtx, 0);
5047 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5048 rtx op_3 = XEXP (plus1_rtx, 1);
5049 rtx op_4 = XEXP (plus0_rtx, 1);
5050 rtx op_5 = gen_reg_rtx (SImode);
5051 rtx op_6 = gen_reg_rtx (SImode);
5052 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
5054 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
5055 emit_insn (gen_addsi3 (op_6, op_5, op_3));
5057 if (<CODE> == SIGN_EXTEND)
5059 emit_insn (gen_extendhisi2 (operands[0], op_7));
5062 else if (<CODE> == ZERO_EXTEND)
5064 /* On SH2A the movu.w insn can be used for zero extending loads. */
5066 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
5069 emit_insn (gen_extendhisi2 (operands[0], op_7));
5070 emit_insn (gen_zero_extendhisi2 (operands[0],
5071 gen_lowpart (HImode, operands[0])));
5079 (define_insn_and_split "*mov<mode>_index_disp_store"
5080 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
5081 (match_operand:HISI 1 "arith_reg_operand" "r"))
5082 (clobber (reg:SI T_REG))]
5085 "&& can_create_pseudo_p ()"
5086 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5087 (set (match_dup 7) (match_dup 1))]
5089 rtx mem = operands[0];
5090 rtx plus0_rtx = XEXP (mem, 0);
5091 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5092 rtx mult_rtx = XEXP (plus1_rtx, 0);
5094 operands[0] = XEXP (mult_rtx, 0);
5095 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5096 operands[3] = XEXP (plus1_rtx, 1);
5097 operands[4] = XEXP (plus0_rtx, 1);
5098 operands[5] = gen_reg_rtx (SImode);
5099 operands[6] = gen_reg_rtx (SImode);
5101 replace_equiv_address (mem,
5102 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5104 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
5107 ;; t/r must come after r/r, lest reload will try to reload stuff like
5108 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5109 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5110 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5111 ;; those alternatives will not be taken, as they will be converted into
5112 ;; PC-relative loads.
5113 (define_insn "movsi_i"
5114 [(set (match_operand:SI 0 "general_movdst_operand"
5115 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r")
5116 (match_operand:SI 1 "general_movsrc_operand"
5117 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))]
5118 "TARGET_SH1 && !TARGET_FPU_ANY
5119 && (register_operand (operands[0], SImode)
5120 || register_operand (operands[1], SImode))"
5138 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5139 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5140 (set_attr_alternative "length"
5146 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5147 (const_int 4) (const_int 2))
5150 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5151 (const_int 4) (const_int 2))
5160 ;; t/r must come after r/r, lest reload will try to reload stuff like
5161 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5162 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5163 ;; will require a reload.
5164 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5165 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5166 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5167 ;; those alternatives will not be taken, as they will be converted into
5168 ;; PC-relative loads.
5169 (define_insn "movsi_ie"
5170 [(set (match_operand:SI 0 "general_movdst_operand"
5171 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y")
5172 (match_operand:SI 1 "general_movsrc_operand"
5173 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))]
5174 "TARGET_SH1 && TARGET_FPU_ANY
5175 && ((register_operand (operands[0], SImode)
5176 && !fpscr_operand (operands[0], SImode))
5177 || (register_operand (operands[1], SImode)
5178 && !fpscr_operand (operands[1], SImode)))"
5203 ! move optimized away"
5204 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5205 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
5206 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5207 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5208 (set_attr_alternative "length"
5214 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5215 (const_int 4) (const_int 2))
5218 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5219 (const_int 4) (const_int 2))
5236 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5237 ;; those alternatives will not be taken, as they will be converted into
5238 ;; PC-relative loads.
5239 (define_insn "movsi_i_lowpart"
5240 [(set (strict_low_part
5241 (match_operand:SI 0 "general_movdst_operand"
5242 "+r,r, r, r, r, r,r,r,m,r"))
5243 (match_operand:SI 1 "general_movsrc_operand"
5244 " Q,r,I08,I20,I28,mr,x,l,r,i"))]
5246 && (register_operand (operands[0], SImode)
5247 || register_operand (operands[1], SImode))"
5259 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store,
5261 (set_attr_alternative "length"
5267 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5268 (const_int 4) (const_int 2))
5271 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5272 (const_int 4) (const_int 2))
5275 (define_insn_and_split "load_ra"
5276 [(set (match_operand:SI 0 "general_movdst_operand" "")
5277 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5280 "&& ! currently_expanding_to_rtl"
5281 [(set (match_dup 0) (match_dup 1))])
5283 (define_expand "movsi"
5284 [(set (match_operand:SI 0 "general_movdst_operand" "")
5285 (match_operand:SI 1 "general_movsrc_operand" ""))]
5288 prepare_move_operands (operands, SImode);
5291 (define_expand "ic_invalidate_line"
5292 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand")
5293 (match_dup 1)] UNSPEC_ICACHE)
5294 (clobber (scratch:SI))])]
5297 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5301 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5302 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5303 ;; the requirement *1*00 for associative address writes. The alignment of
5304 ;; %0 implies that its least significant bit is cleared,
5305 ;; thus we clear the V bit of a matching entry if there is one.
5306 (define_insn "ic_invalidate_line_i"
5307 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5308 (match_operand:SI 1 "register_operand" "r")]
5310 (clobber (match_scratch:SI 2 "=&r"))]
5313 return "ocbwb @%0" "\n"
5314 " extu.w %0,%2" "\n"
5318 [(set_attr "length" "8")
5319 (set_attr "type" "cwb")])
5321 (define_insn "ic_invalidate_line_sh4a"
5322 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5324 "TARGET_SH4A || TARGET_SH4_300"
5326 return "ocbwb @%0" "\n"
5330 [(set_attr "length" "6")
5331 (set_attr "type" "cwb")])
5333 (define_expand "mov<mode>"
5334 [(set (match_operand:QIHI 0 "general_movdst_operand")
5335 (match_operand:QIHI 1 "general_movsrc_operand"))]
5338 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
5339 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
5341 rtx reg = gen_reg_rtx(SImode);
5342 emit_move_insn (reg, operands[1]);
5343 operands[1] = gen_lowpart (<MODE>mode, reg);
5346 prepare_move_operands (operands, <MODE>mode);
5349 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
5350 ;; constraints, otherwise wrong code might get generated.
5351 (define_insn "*mov<mode>_load_predec"
5352 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
5353 (match_operand:QIHISI 1 "pre_dec_mem" "<"))]
5356 [(set_attr "type" "load")])
5358 (define_insn "*mov<mode>_store_postinc"
5359 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>")
5360 (match_operand:QIHISI 1 "arith_reg_operand" "z"))]
5363 [(set_attr "type" "store")])
5365 ;; Specifying the displacement addressing load / store patterns separately
5366 ;; before the generic movqi / movhi pattern allows controlling the order
5367 ;; in which load / store insns are selected in a more fine grained way.
5368 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5369 ;; "enabled" attribute as it is done in other targets.
5370 (define_insn "*mov<mode>_store_mem_disp04"
5372 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5373 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
5374 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
5375 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
5377 mov.<bw> %2,@(%O1,%0)
5379 [(set_attr "type" "store")])
5381 (define_insn "*mov<mode>_store_mem_disp12"
5383 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5384 (match_operand:SI 1 "const_int_operand" "<disp12>")))
5385 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
5386 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
5387 "mov.<bw> %2,@(%O1,%0)"
5388 [(set_attr "type" "store")
5389 (set_attr "length" "4")])
5391 (define_insn "*mov<mode>_load_mem_disp04"
5392 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
5394 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5395 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
5396 "TARGET_SH1 && ! TARGET_SH2A
5397 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
5399 mov.<bw> @(%O2,%1),%0
5401 [(set_attr "type" "load")])
5403 (define_insn "*mov<mode>_load_mem_disp12"
5404 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
5407 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5408 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
5409 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
5411 mov.<bw> @(%O2,%1),%0
5413 mov.<bw> @(%O2,%1),%0"
5414 [(set_attr "type" "load")
5415 (set_attr "length" "2,2,4")])
5417 ;; The order of the constraint alternatives is important here.
5418 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
5419 ;; placed into delay slots. Since there is no QImode PC relative load, the
5420 ;; Q constraint and general_movsrc_operand will reject it for QImode.
5421 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
5422 ;; a preference of using r0 als the register operand for addressing modes
5423 ;; other than displacement addressing.
5424 ;; The Sdd alternatives allow only r0 as register operand, even though on
5425 ;; SH2A any register could be allowed by switching to a 32 bit insn.
5426 ;; Generally sticking to the r0 is preferrable, since it generates smaller
5427 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
5428 (define_insn "*mov<mode>"
5429 [(set (match_operand:QIHI 0 "general_movdst_operand"
5430 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
5431 (match_operand:QIHI 1 "general_movsrc_operand"
5432 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
5434 && (arith_reg_operand (operands[0], <MODE>mode)
5435 || arith_reg_operand (operands[1], <MODE>mode))"
5448 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
5449 (set (attr "length")
5450 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4)
5451 (match_operand 1 "long_displacement_mem_operand") (const_int 4)]
5454 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5455 ;; compiled with -m2 -ml -O3 -funroll-loops
5456 (define_insn "*movdi_i"
5457 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x")
5458 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))]
5460 && (arith_reg_operand (operands[0], DImode)
5461 || arith_reg_operand (operands[1], DImode))"
5463 return output_movedouble (insn, operands, DImode);
5465 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move")
5466 (set (attr "length")
5467 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5468 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5471 ;; If the output is a register and the input is memory or a register, we have
5472 ;; to be careful and see which word needs to be loaded first.
5474 [(set (match_operand:DI 0 "general_movdst_operand" "")
5475 (match_operand:DI 1 "general_movsrc_operand" ""))]
5476 "TARGET_SH1 && reload_completed"
5477 [(set (match_dup 2) (match_dup 3))
5478 (set (match_dup 4) (match_dup 5))]
5482 if ((MEM_P (operands[0])
5483 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5484 || (MEM_P (operands[1])
5485 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5488 switch (GET_CODE (operands[0]))
5491 regno = REGNO (operands[0]);
5494 regno = subreg_regno (operands[0]);
5503 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5505 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5506 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5507 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5508 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5512 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5513 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5514 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5515 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5518 if (operands[2] == 0 || operands[3] == 0
5519 || operands[4] == 0 || operands[5] == 0)
5523 (define_expand "movdi"
5524 [(set (match_operand:DI 0 "general_movdst_operand" "")
5525 (match_operand:DI 1 "general_movsrc_operand" ""))]
5528 prepare_move_operands (operands, DImode);
5530 /* When the dest operand is (R0, R1) register pair, split it to
5531 two movsi of which dest is R1 and R0 so as to lower R0-register
5532 pressure on the first movsi. Apply only for simple source not
5533 to make complex rtl here. */
5534 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
5535 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5537 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
5538 gen_rtx_SUBREG (SImode, operands[1], 4)));
5539 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
5540 gen_rtx_SUBREG (SImode, operands[1], 0)));
5545 ;; FIXME: This should be a define_insn_and_split.
5546 (define_insn "movdf_k"
5547 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m")
5548 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))]
5550 && (!TARGET_FPU_DOUBLE || reload_completed
5551 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
5552 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
5553 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
5554 && (arith_reg_operand (operands[0], DFmode)
5555 || arith_reg_operand (operands[1], DFmode))"
5557 return output_movedouble (insn, operands, DFmode);
5559 [(set_attr "type" "move,pcload,load,store")
5560 (set (attr "length")
5561 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5562 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5565 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
5566 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
5567 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
5568 ;; the d/m/c/X alternative, which is split later into single-precision
5569 ;; instructions. And when not optimizing, no splits are done before fixing
5570 ;; up pcloads, so we need usable length information for that.
5571 ;; A DF constant load results in the following worst-case 8 byte sequence:
5576 (define_insn "movdf_i4"
5577 [(set (match_operand:DF 0 "general_movdst_operand"
5578 "=d,r, d,d,m, r,r,m,!??r,!???d")
5579 (match_operand:DF 1 "general_movsrc_operand"
5580 " d,r, F,m,d,FQ,m,r, d, r"))
5581 (use (reg:SI FPSCR_MODES_REG))
5582 (clobber (match_scratch:SI 2
5583 "=X,X,&z,X,X, X,X,X, X, X"))]
5585 && (arith_reg_operand (operands[0], DFmode)
5586 || arith_reg_operand (operands[1], DFmode))"
5588 switch (which_alternative)
5592 return "fmov %1,%0";
5593 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
5594 return "fmov %R1,%R0" "\n"
5597 return "fmov %S1,%S0" "\n"
5601 return "fmov.d %1,%0";
5606 [(set_attr_alternative "length"
5607 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
5609 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
5610 (if_then_else (match_operand 1 "displacement_mem_operand")
5611 (if_then_else (eq_attr "fmovd" "yes")
5612 (const_int 4) (const_int 8))
5613 (if_then_else (eq_attr "fmovd" "yes")
5614 (const_int 2) (const_int 4)))
5615 (if_then_else (match_operand 0 "displacement_mem_operand")
5616 (if_then_else (eq_attr "fmovd" "yes")
5617 (const_int 4) (const_int 8))
5618 (if_then_else (eq_attr "fmovd" "yes")
5619 (const_int 2) (const_int 4)))
5621 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5622 (const_int 8) (const_int 4))
5623 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5624 (const_int 8) (const_int 4))
5627 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,
5629 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
5630 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5631 (const_string "double")
5632 (const_string "none")))])
5634 ;; Moving DFmode between fp/general registers through memory
5635 ;; (the top of the stack) is faster than moving through fpul even for
5636 ;; little endian. Because the type of an instruction is important for its
5637 ;; scheduling, it is beneficial to split these operations, rather than
5638 ;; emitting them in one single chunk, even if this will expose a stack
5639 ;; use that will prevent scheduling of other stack accesses beyond this
5642 [(set (match_operand:DF 0 "register_operand")
5643 (match_operand:DF 1 "register_operand"))
5644 (use (reg:SI FPSCR_MODES_REG))
5645 (clobber (match_scratch:SI 2))]
5646 "TARGET_FPU_DOUBLE && reload_completed
5647 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
5652 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
5653 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
5654 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5655 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
5656 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
5657 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5661 ;; local-alloc sometimes allocates scratch registers even when not required,
5662 ;; so we must be prepared to handle these.
5664 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
5666 [(set (match_operand:DF 0 "general_movdst_operand" "")
5667 (match_operand:DF 1 "general_movsrc_operand" ""))
5668 (use (reg:SI FPSCR_MODES_REG))
5669 (clobber (match_scratch:SI 2))]
5672 && true_regnum (operands[0]) < 16
5673 && true_regnum (operands[1]) < 16"
5674 [(set (match_dup 0) (match_dup 1))]
5676 /* If this was a reg <-> mem operation with base + index reg addressing,
5677 we have to handle this in a special way. */
5678 rtx mem = operands[0];
5680 if (! memory_operand (mem, DFmode))
5685 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
5686 mem = SUBREG_REG (mem);
5689 rtx addr = XEXP (mem, 0);
5690 if (GET_CODE (addr) == PLUS
5691 && REG_P (XEXP (addr, 0))
5692 && REG_P (XEXP (addr, 1)))
5695 rtx reg0 = gen_rtx_REG (Pmode, 0);
5696 rtx regop = operands[store_p], word0 ,word1;
5698 if (GET_CODE (regop) == SUBREG)
5699 alter_subreg (®op, true);
5700 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
5704 mem = copy_rtx (mem);
5705 PUT_MODE (mem, SImode);
5706 word0 = gen_rtx_SUBREG (SImode, regop, 0);
5707 alter_subreg (&word0, true);
5708 word1 = gen_rtx_SUBREG (SImode, regop, 4);
5709 alter_subreg (&word1, true);
5710 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
5713 ? gen_movsi_ie (mem, word0)
5714 : gen_movsi_ie (word0, mem));
5715 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5716 mem = copy_rtx (mem);
5718 ? gen_movsi_ie (mem, word1)
5719 : gen_movsi_ie (word1, mem));
5720 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5724 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5725 emit_insn (gen_movsi_ie (word1, mem));
5726 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5727 mem = copy_rtx (mem);
5728 emit_insn (gen_movsi_ie (word0, mem));
5735 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
5737 [(set (match_operand:DF 0 "register_operand" "")
5738 (match_operand:DF 1 "memory_operand" ""))
5739 (use (reg:SI FPSCR_MODES_REG))
5740 (clobber (reg:SI R0_REG))]
5741 "TARGET_FPU_DOUBLE && reload_completed"
5742 [(parallel [(set (match_dup 0) (match_dup 1))
5743 (use (reg:SI FPSCR_MODES_REG))
5744 (clobber (scratch:SI))])]
5747 (define_expand "reload_indf__frn"
5748 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
5749 (match_operand:DF 1 "immediate_operand" "FQ"))
5750 (use (reg:SI FPSCR_MODES_REG))
5751 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5755 (define_expand "reload_outdf__RnFRm"
5756 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
5757 (match_operand:DF 1 "register_operand" "af,r"))
5758 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
5762 ;; Simplify no-op moves.
5764 [(set (match_operand:SF 0 "register_operand" "")
5765 (match_operand:SF 1 "register_operand" ""))
5766 (use (reg:SI FPSCR_MODES_REG))
5767 (clobber (match_scratch:SI 2))]
5768 "TARGET_SH2E && reload_completed
5769 && true_regnum (operands[0]) == true_regnum (operands[1])"
5770 [(set (match_dup 0) (match_dup 0))]
5773 ;; fmovd substitute post-reload splits
5775 [(set (match_operand:DF 0 "register_operand" "")
5776 (match_operand:DF 1 "register_operand" ""))
5777 (use (reg:SI FPSCR_MODES_REG))
5778 (clobber (match_scratch:SI 2))]
5779 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
5780 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5781 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5784 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
5785 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
5786 gen_rtx_REG (SFmode, src)));
5787 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
5788 gen_rtx_REG (SFmode, src + 1)));
5793 [(set (match_operand:DF 0 "register_operand" "")
5794 (mem:DF (match_operand:SI 1 "register_operand" "")))
5795 (use (reg:SI FPSCR_MODES_REG))
5796 (clobber (match_scratch:SI 2))]
5797 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5798 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5799 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
5802 int regno = true_regnum (operands[0]);
5804 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
5806 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
5807 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5808 regno + SH_REG_MSW_OFFSET),
5810 add_reg_note (insn, REG_INC, operands[1]);
5811 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5812 regno + SH_REG_LSW_OFFSET),
5813 change_address (mem, SFmode, NULL_RTX)));
5818 [(set (match_operand:DF 0 "register_operand" "")
5819 (match_operand:DF 1 "memory_operand" ""))
5820 (use (reg:SI FPSCR_MODES_REG))
5821 (clobber (match_scratch:SI 2))]
5822 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5823 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
5826 int regno = true_regnum (operands[0]);
5828 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
5829 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5830 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5832 operands[1] = copy_rtx (mem2);
5833 addr = XEXP (mem2, 0);
5835 switch (GET_CODE (addr))
5838 /* This is complicated. If the register is an arithmetic register
5839 we can just fall through to the REG+DISP case below. Otherwise
5840 we have to use a combination of POST_INC and REG addressing... */
5841 if (! arith_reg_operand (operands[1], SFmode))
5843 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
5844 insn = emit_insn (gen_movsf_ie (reg0, mem2));
5845 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5847 emit_insn (gen_movsf_ie (reg1, operands[1]));
5849 /* If we have modified the stack pointer, the value that we have
5850 read with post-increment might be modified by an interrupt,
5851 so write it back. */
5852 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
5853 emit_insn (gen_push_e (reg0));
5855 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
5862 emit_insn (gen_movsf_ie (reg0, operands[1]));
5863 operands[1] = copy_rtx (operands[1]);
5864 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
5865 emit_insn (gen_movsf_ie (reg1, operands[1]));
5869 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
5870 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5872 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
5873 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5885 [(set (match_operand:DF 0 "memory_operand" "")
5886 (match_operand:DF 1 "register_operand" ""))
5887 (use (reg:SI FPSCR_MODES_REG))
5888 (clobber (match_scratch:SI 2))]
5889 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5890 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5893 int regno = true_regnum (operands[1]);
5895 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5896 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5898 operands[0] = copy_rtx (operands[0]);
5899 PUT_MODE (operands[0], SFmode);
5900 addr = XEXP (operands[0], 0);
5902 switch (GET_CODE (addr))
5905 /* This is complicated. If the register is an arithmetic register
5906 we can just fall through to the REG+DISP case below. Otherwise
5907 we have to use a combination of REG and PRE_DEC addressing... */
5908 if (! arith_reg_operand (operands[0], SFmode))
5910 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
5911 emit_insn (gen_movsf_ie (operands[0], reg1));
5913 operands[0] = copy_rtx (operands[0]);
5914 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
5916 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5917 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5923 /* Since REG+DISP addressing has already been decided upon by gcc
5924 we can rely upon it having chosen an arithmetic register as the
5925 register component of the address. Just emit the lower numbered
5926 register first, to the lower address, then the higher numbered
5927 register to the higher address. */
5928 emit_insn (gen_movsf_ie (operands[0], reg0));
5930 operands[0] = copy_rtx (operands[0]);
5931 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
5933 emit_insn (gen_movsf_ie (operands[0], reg1));
5937 /* This is easy. Output the word to go to the higher address
5938 first (ie the word in the higher numbered register) then the
5939 word to go to the lower address. */
5941 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
5942 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5944 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5945 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5957 ;; If the output is a register and the input is memory or a register, we have
5958 ;; to be careful and see which word needs to be loaded first.
5960 [(set (match_operand:DF 0 "general_movdst_operand" "")
5961 (match_operand:DF 1 "general_movsrc_operand" ""))]
5962 "TARGET_SH1 && reload_completed"
5963 [(set (match_dup 2) (match_dup 3))
5964 (set (match_dup 4) (match_dup 5))]
5968 if ((MEM_P (operands[0])
5969 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5970 || (MEM_P (operands[1])
5971 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5974 switch (GET_CODE (operands[0]))
5977 regno = REGNO (operands[0]);
5980 regno = subreg_regno (operands[0]);
5989 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5991 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5992 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5993 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5994 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
5998 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
5999 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
6000 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
6001 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
6004 if (operands[2] == 0 || operands[3] == 0
6005 || operands[4] == 0 || operands[5] == 0)
6009 (define_expand "movdf"
6010 [(set (match_operand:DF 0 "general_movdst_operand" "")
6011 (match_operand:DF 1 "general_movsrc_operand" ""))]
6014 prepare_move_operands (operands, DFmode);
6015 if (TARGET_FPU_DOUBLE)
6017 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
6022 ;; FIXME Although the movsf_i pattern is not used when there's an FPU,
6023 ;; it somehow influences some RA choices also on FPU targets.
6024 ;; For non-FPU targets it's actually not needed.
6025 (define_insn "movsf_i"
6026 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r")
6027 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6030 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6031 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6032 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6033 && (arith_reg_operand (operands[0], SFmode)
6034 || arith_reg_operand (operands[1], SFmode))"
6043 [(set_attr "type" "move,move,pcload,load,store,move,move")
6044 (set_attr_alternative "length"
6047 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6048 (const_int 4) (const_int 2))
6049 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6050 (const_int 4) (const_int 2))
6051 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6052 (const_int 4) (const_int 2))
6056 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6057 ;; update_flow_info would not know where to put REG_EQUAL notes
6058 ;; when the destination changes mode.
6059 (define_insn "movsf_ie"
6060 [(set (match_operand:SF 0 "general_movdst_operand"
6061 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
6062 (match_operand:SF 1 "general_movsrc_operand"
6063 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6064 (use (reg:SI FPSCR_MODES_REG))
6065 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
6067 && (arith_reg_operand (operands[0], SFmode)
6068 || fpul_operand (operands[0], SFmode)
6069 || arith_reg_operand (operands[1], SFmode)
6070 || fpul_operand (operands[1], SFmode)
6071 || arith_reg_operand (operands[2], SImode))"
6091 ! move optimized away"
6092 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6093 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6094 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6095 (set_attr_alternative "length"
6101 (if_then_else (match_operand 1 "displacement_mem_operand")
6102 (const_int 4) (const_int 2))
6103 (if_then_else (match_operand 0 "displacement_mem_operand")
6104 (const_int 4) (const_int 2))
6106 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6107 (const_int 4) (const_int 2))
6108 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6109 (const_int 4) (const_int 2))
6119 (set_attr_alternative "fp_mode"
6120 [(if_then_else (eq_attr "fmovd" "yes")
6121 (const_string "single") (const_string "none"))
6122 (const_string "none")
6123 (const_string "single")
6124 (const_string "single")
6125 (const_string "none")
6126 (if_then_else (eq_attr "fmovd" "yes")
6127 (const_string "single") (const_string "none"))
6128 (if_then_else (eq_attr "fmovd" "yes")
6129 (const_string "single") (const_string "none"))
6130 (const_string "none")
6131 (const_string "none")
6132 (const_string "none")
6133 (const_string "none")
6134 (const_string "none")
6135 (const_string "none")
6136 (const_string "none")
6137 (const_string "none")
6138 (const_string "none")
6139 (const_string "none")
6140 (const_string "none")
6141 (const_string "none")])])
6143 (define_insn_and_split "movsf_ie_ra"
6144 [(set (match_operand:SF 0 "general_movdst_operand"
6145 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
6146 (match_operand:SF 1 "general_movsrc_operand"
6147 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
6148 (use (reg:SI FPSCR_MODES_REG))
6149 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
6152 && (arith_reg_operand (operands[0], SFmode)
6153 || fpul_operand (operands[0], SFmode)
6154 || arith_reg_operand (operands[1], SFmode)
6155 || fpul_operand (operands[1], SFmode))"
6175 ! move optimized away"
6177 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
6180 if (! rtx_equal_p (operands[0], operands[1]))
6182 emit_insn (gen_movsf_ie (operands[2], operands[1]));
6183 emit_insn (gen_movsf_ie (operands[0], operands[2]));
6186 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6187 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6188 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6189 (set_attr_alternative "length"
6195 (if_then_else (match_operand 1 "displacement_mem_operand")
6196 (const_int 4) (const_int 2))
6197 (if_then_else (match_operand 0 "displacement_mem_operand")
6198 (const_int 4) (const_int 2))
6200 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6201 (const_int 4) (const_int 2))
6202 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6203 (const_int 4) (const_int 2))
6213 (set_attr_alternative "fp_mode"
6214 [(if_then_else (eq_attr "fmovd" "yes")
6215 (const_string "single") (const_string "none"))
6216 (const_string "none")
6217 (const_string "single")
6218 (const_string "single")
6219 (const_string "none")
6220 (if_then_else (eq_attr "fmovd" "yes")
6221 (const_string "single") (const_string "none"))
6222 (if_then_else (eq_attr "fmovd" "yes")
6223 (const_string "single") (const_string "none"))
6224 (const_string "none")
6225 (const_string "none")
6226 (const_string "none")
6227 (const_string "none")
6228 (const_string "none")
6229 (const_string "none")
6230 (const_string "none")
6231 (const_string "none")
6232 (const_string "none")
6233 (const_string "none")
6234 (const_string "none")
6235 (const_string "none")])])
6238 [(set (match_operand:SF 0 "register_operand" "")
6239 (match_operand:SF 1 "register_operand" ""))
6240 (use (reg:SI FPSCR_MODES_REG))
6241 (clobber (reg:SI FPUL_REG))]
6243 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6244 (use (reg:SI FPSCR_MODES_REG))
6245 (clobber (scratch:SI))])
6246 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6247 (use (reg:SI FPSCR_MODES_REG))
6248 (clobber (scratch:SI))])]
6251 (define_expand "movsf"
6252 [(set (match_operand:SF 0 "general_movdst_operand" "")
6253 (match_operand:SF 1 "general_movsrc_operand" ""))]
6256 prepare_move_operands (operands, SFmode);
6259 if (lra_in_progress)
6261 if (GET_CODE (operands[0]) == SCRATCH)
6263 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
6267 emit_insn (gen_movsf_ie (operands[0], operands[1]));
6272 (define_expand "reload_insf__frn"
6273 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
6274 (match_operand:SF 1 "immediate_operand" "FQ"))
6275 (use (reg:SI FPSCR_MODES_REG))
6276 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6280 (define_expand "reload_insi__i_fpul"
6281 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
6282 (match_operand:SI 1 "immediate_operand" "i"))
6283 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6287 (define_insn "*movsi_y"
6288 [(set (match_operand:SI 0 "register_operand" "=y,y")
6289 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
6290 (clobber (match_scratch:SI 2 "=&z,r"))]
6292 && (reload_in_progress || reload_completed)"
6294 [(set_attr "length" "4")
6295 (set_attr "type" "pcload,move")])
6298 [(set (match_operand:SI 0 "register_operand" "")
6299 (match_operand:SI 1 "immediate_operand" ""))
6300 (clobber (match_operand:SI 2 "register_operand" ""))]
6302 [(set (match_dup 2) (match_dup 1))
6303 (set (match_dup 0) (match_dup 2))]
6306 ;; ------------------------------------------------------------------------
6307 ;; Define the real conditional branch instructions.
6308 ;; ------------------------------------------------------------------------
6310 (define_expand "branch_true"
6311 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
6312 (label_ref (match_operand 0))
6316 (define_expand "branch_false"
6317 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6318 (label_ref (match_operand 0))
6322 (define_insn_and_split "*cbranch_t"
6323 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
6324 (label_ref (match_operand 0))
6328 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
6333 /* Try to canonicalize the branch condition if it is not one of:
6334 (ne (reg:SI T_REG) (const_int 0))
6335 (eq (reg:SI T_REG) (const_int 0))
6337 Instead of splitting out a new insn, we modify the current insn's
6338 operands as needed. This preserves things such as REG_DEAD notes. */
6340 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
6341 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
6342 && XEXP (operands[1], 1) == const0_rtx)
6345 int branch_cond = sh_eval_treg_value (operands[1]);
6346 rtx new_cond_rtx = NULL_RTX;
6348 if (branch_cond == 0)
6349 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
6350 else if (branch_cond == 1)
6351 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
6353 if (new_cond_rtx != NULL_RTX)
6354 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
6355 new_cond_rtx, false);
6358 [(set_attr "type" "cbranch")])
6360 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
6361 ;; which destination is too far away.
6362 ;; The const_int_operand is distinct for each branch target; it avoids
6363 ;; unwanted matches with redundant_insn.
6364 (define_insn "block_branch_redirect"
6365 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
6368 [(set_attr "length" "0")])
6370 ;; This one has the additional purpose to record a possible scratch register
6371 ;; for the following branch.
6372 ;; ??? Unfortunately, just setting the scratch register is not good enough,
6373 ;; because the insn then might be deemed dead and deleted. And we can't
6374 ;; make the use in the jump insn explicit because that would disable
6375 ;; delay slot scheduling from the target.
6376 (define_insn "indirect_jump_scratch"
6377 [(set (match_operand:SI 0 "register_operand" "=r")
6378 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
6379 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
6382 [(set_attr "length" "0")])
6384 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
6385 ;; being pulled into the delay slot of a condbranch that has been made to
6386 ;; jump around the unconditional jump because it was out of range.
6387 (define_insn "stuff_delay_slot"
6389 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
6390 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
6393 [(set_attr "length" "0")
6394 (set_attr "cond_delay_slot" "yes")])
6396 ;; Conditional branch insns
6398 ; operand 0 is the loop count pseudo register
6399 ; operand 1 is the label to jump to at the top of the loop
6400 (define_expand "doloop_end"
6401 [(parallel [(set (pc)
6402 (if_then_else (ne:SI (match_operand:SI 0 "" "")
6404 (label_ref (match_operand 1 "" ""))
6407 (plus:SI (match_dup 0) (const_int -1)))
6408 (clobber (reg:SI T_REG))])]
6411 if (GET_MODE (operands[0]) != SImode)
6413 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
6417 (define_insn_and_split "doloop_end_split"
6419 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
6421 (label_ref (match_operand 1 "" ""))
6423 (set (match_operand:SI 0 "arith_reg_dest" "=r")
6424 (plus:SI (match_dup 2) (const_int -1)))
6425 (clobber (reg:SI T_REG))]
6429 [(parallel [(set (reg:SI T_REG)
6430 (eq:SI (match_dup 2) (const_int 1)))
6431 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
6432 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6433 (label_ref (match_dup 1))
6436 [(set_attr "type" "cbranch")])
6438 ;; ------------------------------------------------------------------------
6439 ;; Jump and linkage insns
6440 ;; ------------------------------------------------------------------------
6442 (define_insn "jump_compact"
6444 (label_ref (match_operand 0 "" "")))]
6445 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
6447 /* The length is 16 if the delay slot is unfilled. */
6448 if (get_attr_length(insn) > 4)
6449 return output_far_jump(insn, operands[0]);
6453 [(set_attr "type" "jump")
6454 (set_attr "needs_delay_slot" "yes")])
6456 (define_insn "*jump_compact_crossing"
6458 (label_ref (match_operand 0 "" "")))]
6460 && flag_reorder_blocks_and_partition
6461 && CROSSING_JUMP_P (insn)"
6463 /* The length is 16 if the delay slot is unfilled. */
6464 return output_far_jump(insn, operands[0]);
6466 [(set_attr "type" "jump")
6467 (set_attr "length" "16")])
6469 (define_expand "jump"
6471 (label_ref (match_operand 0 "" "")))]
6474 emit_jump_insn (gen_jump_compact (operands[0]));
6478 (define_insn "calli"
6479 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6480 (match_operand 1 "" ""))
6481 (use (reg:SI FPSCR_MODES_REG))
6482 (clobber (reg:SI PR_REG))]
6483 "TARGET_SH1 && !TARGET_FDPIC"
6485 if (TARGET_SH2A && dbr_sequence_length () == 0)
6490 [(set_attr "type" "call")
6491 (set (attr "fp_mode")
6492 (if_then_else (eq_attr "fpu_single" "yes")
6493 (const_string "single") (const_string "double")))
6494 (set_attr "needs_delay_slot" "yes")
6495 (set_attr "fp_set" "unknown")])
6497 (define_insn "calli_fdpic"
6498 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6500 (use (reg:SI FPSCR_MODES_REG))
6501 (use (reg:SI PIC_REG))
6502 (clobber (reg:SI PR_REG))]
6505 if (TARGET_SH2A && dbr_sequence_length () == 0)
6510 [(set_attr "type" "call")
6511 (set (attr "fp_mode")
6512 (if_then_else (eq_attr "fpu_single" "yes")
6513 (const_string "single") (const_string "double")))
6514 (set_attr "needs_delay_slot" "yes")
6515 (set_attr "fp_set" "unknown")])
6517 ;; This is TBR relative jump instruction for SH2A architecture.
6518 ;; Its use is enabled by assigning an attribute "function_vector"
6519 ;; and the vector number to a function during its declaration.
6520 (define_insn "calli_tbr_rel"
6521 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
6522 (match_operand 1 "" ""))
6523 (use (reg:SI FPSCR_MODES_REG))
6524 (use (match_scratch 2))
6525 (clobber (reg:SI PR_REG))]
6526 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
6528 unsigned HOST_WIDE_INT vect_num;
6529 vect_num = sh2a_get_function_vector_number (operands[0]);
6530 operands[2] = GEN_INT (vect_num * 4);
6532 return "jsr/n @@(%O2,tbr)";
6534 [(set_attr "type" "call")
6535 (set (attr "fp_mode")
6536 (if_then_else (eq_attr "fpu_single" "yes")
6537 (const_string "single") (const_string "double")))
6538 (set_attr "needs_delay_slot" "no")
6539 (set_attr "fp_set" "unknown")])
6541 ;; This is a pc-rel call, using bsrf, for use with PIC.
6542 (define_insn "calli_pcrel"
6543 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6544 (match_operand 1 "" ""))
6545 (use (reg:SI FPSCR_MODES_REG))
6546 (use (reg:SI PIC_REG))
6547 (use (match_operand 2 "" ""))
6548 (clobber (reg:SI PR_REG))]
6551 return "bsrf %0" "\n"
6554 [(set_attr "type" "call")
6555 (set (attr "fp_mode")
6556 (if_then_else (eq_attr "fpu_single" "yes")
6557 (const_string "single") (const_string "double")))
6558 (set_attr "needs_delay_slot" "yes")
6559 (set_attr "fp_set" "unknown")])
6561 (define_insn_and_split "call_pcrel"
6562 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6563 (match_operand 1 "" ""))
6564 (use (reg:SI FPSCR_MODES_REG))
6565 (use (reg:SI PIC_REG))
6566 (clobber (reg:SI PR_REG))
6567 (clobber (match_scratch:SI 2 "=&r"))]
6573 rtx lab = PATTERN (gen_call_site ());
6575 sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
6576 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
6579 [(set_attr "type" "call")
6580 (set (attr "fp_mode")
6581 (if_then_else (eq_attr "fpu_single" "yes")
6582 (const_string "single") (const_string "double")))
6583 (set_attr "needs_delay_slot" "yes")
6584 (set_attr "fp_set" "unknown")])
6586 (define_insn "call_valuei"
6587 [(set (match_operand 0 "" "=rf")
6588 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6589 (match_operand 2 "" "")))
6590 (use (reg:SI FPSCR_MODES_REG))
6591 (clobber (reg:SI PR_REG))]
6592 "TARGET_SH1 && !TARGET_FDPIC"
6594 if (TARGET_SH2A && dbr_sequence_length () == 0)
6599 [(set_attr "type" "call")
6600 (set (attr "fp_mode")
6601 (if_then_else (eq_attr "fpu_single" "yes")
6602 (const_string "single") (const_string "double")))
6603 (set_attr "needs_delay_slot" "yes")
6604 (set_attr "fp_set" "unknown")])
6606 (define_insn "call_valuei_fdpic"
6607 [(set (match_operand 0 "" "=rf")
6608 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6610 (use (reg:SI FPSCR_REG))
6611 (use (reg:SI PIC_REG))
6612 (clobber (reg:SI PR_REG))]
6615 if (TARGET_SH2A && dbr_sequence_length () == 0)
6620 [(set_attr "type" "call")
6621 (set (attr "fp_mode")
6622 (if_then_else (eq_attr "fpu_single" "yes")
6623 (const_string "single") (const_string "double")))
6624 (set_attr "needs_delay_slot" "yes")
6625 (set_attr "fp_set" "unknown")])
6627 ;; This is TBR relative jump instruction for SH2A architecture.
6628 ;; Its use is enabled by assigning an attribute "function_vector"
6629 ;; and the vector number to a function during its declaration.
6630 (define_insn "call_valuei_tbr_rel"
6631 [(set (match_operand 0 "" "=rf")
6632 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6633 (match_operand 2 "" "")))
6634 (use (reg:SI FPSCR_MODES_REG))
6635 (use (match_scratch 3))
6636 (clobber (reg:SI PR_REG))]
6637 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
6639 unsigned HOST_WIDE_INT vect_num;
6640 vect_num = sh2a_get_function_vector_number (operands[1]);
6641 operands[3] = GEN_INT (vect_num * 4);
6643 return "jsr/n @@(%O3,tbr)";
6645 [(set_attr "type" "call")
6646 (set (attr "fp_mode")
6647 (if_then_else (eq_attr "fpu_single" "yes")
6648 (const_string "single") (const_string "double")))
6649 (set_attr "needs_delay_slot" "no")
6650 (set_attr "fp_set" "unknown")])
6652 (define_insn "call_valuei_pcrel"
6653 [(set (match_operand 0 "" "=rf")
6654 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6655 (match_operand 2 "" "")))
6656 (use (reg:SI FPSCR_MODES_REG))
6657 (use (reg:SI PIC_REG))
6658 (use (match_operand 3 "" ""))
6659 (clobber (reg:SI PR_REG))]
6662 return "bsrf %1" "\n"
6665 [(set_attr "type" "call")
6666 (set (attr "fp_mode")
6667 (if_then_else (eq_attr "fpu_single" "yes")
6668 (const_string "single") (const_string "double")))
6669 (set_attr "needs_delay_slot" "yes")
6670 (set_attr "fp_set" "unknown")])
6672 (define_insn_and_split "call_value_pcrel"
6673 [(set (match_operand 0 "" "=rf")
6674 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6675 (match_operand 2 "" "")))
6676 (use (reg:SI FPSCR_MODES_REG))
6677 (use (reg:SI PIC_REG))
6678 (clobber (reg:SI PR_REG))
6679 (clobber (match_scratch:SI 3 "=&r"))]
6685 rtx lab = PATTERN (gen_call_site ());
6687 sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
6688 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
6689 operands[2], copy_rtx (lab)));
6692 [(set_attr "type" "call")
6693 (set (attr "fp_mode")
6694 (if_then_else (eq_attr "fpu_single" "yes")
6695 (const_string "single") (const_string "double")))
6696 (set_attr "needs_delay_slot" "yes")
6697 (set_attr "fp_set" "unknown")])
6699 (define_expand "call"
6700 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6701 (match_operand 1 "" ""))
6702 (match_operand 2 "" "")
6703 (use (reg:SI FPSCR_MODES_REG))
6704 (clobber (reg:SI PR_REG))])]
6709 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6710 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6713 if (!flag_pic && TARGET_SH2A
6714 && MEM_P (operands[0])
6715 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6717 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
6719 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
6724 if (flag_pic && TARGET_SH2
6725 && MEM_P (operands[0])
6726 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6728 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
6733 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6734 operands[1] = operands[2];
6739 operands[0] = sh_load_function_descriptor (operands[0]);
6740 emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
6743 emit_call_insn (gen_calli (operands[0], operands[1]));
6747 (define_expand "call_value"
6748 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6749 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6750 (match_operand 2 "" "")))
6751 (match_operand 3 "" "")
6752 (use (reg:SI FPSCR_MODES_REG))
6753 (clobber (reg:SI PR_REG))])]
6758 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6759 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6762 if (!flag_pic && TARGET_SH2A
6763 && MEM_P (operands[1])
6764 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6766 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
6768 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
6769 XEXP (operands[1], 0), operands[2]));
6773 if (flag_pic && TARGET_SH2
6774 && MEM_P (operands[1])
6775 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6777 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6782 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6786 operands[1] = sh_load_function_descriptor (operands[1]);
6787 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
6791 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6795 (define_insn "sibcalli"
6796 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6797 (match_operand 1 "" ""))
6798 (use (reg:SI FPSCR_MODES_REG))
6800 "TARGET_SH1 && !TARGET_FDPIC"
6802 [(set_attr "needs_delay_slot" "yes")
6803 (set (attr "fp_mode")
6804 (if_then_else (eq_attr "fpu_single" "yes")
6805 (const_string "single") (const_string "double")))
6806 (set_attr "type" "jump_ind")])
6808 (define_insn "sibcalli_fdpic"
6809 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6811 (use (reg:SI FPSCR_MODES_REG))
6812 (use (reg:SI PIC_REG))
6816 [(set_attr "needs_delay_slot" "yes")
6817 (set (attr "fp_mode")
6818 (if_then_else (eq_attr "fpu_single" "yes")
6819 (const_string "single") (const_string "double")))
6820 (set_attr "type" "jump_ind")])
6822 (define_insn "sibcalli_pcrel"
6823 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6824 (match_operand 1 "" ""))
6825 (use (match_operand 2 "" ""))
6826 (use (reg:SI FPSCR_MODES_REG))
6828 "TARGET_SH2 && !TARGET_FDPIC"
6830 return "braf %0" "\n"
6833 [(set_attr "needs_delay_slot" "yes")
6834 (set (attr "fp_mode")
6835 (if_then_else (eq_attr "fpu_single" "yes")
6836 (const_string "single") (const_string "double")))
6837 (set_attr "type" "jump_ind")])
6839 (define_insn "sibcalli_pcrel_fdpic"
6840 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6842 (use (match_operand 2))
6843 (use (reg:SI FPSCR_MODES_REG))
6844 (use (reg:SI PIC_REG))
6846 "TARGET_SH2 && TARGET_FDPIC"
6848 return "braf %0" "\n"
6851 [(set_attr "needs_delay_slot" "yes")
6852 (set (attr "fp_mode")
6853 (if_then_else (eq_attr "fpu_single" "yes")
6854 (const_string "single") (const_string "double")))
6855 (set_attr "type" "jump_ind")])
6857 ;; This uses an unspec to describe that the symbol_ref is very close.
6858 (define_insn "sibcalli_thunk"
6859 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
6861 (match_operand 1 "" ""))
6862 (use (reg:SI FPSCR_MODES_REG))
6866 [(set_attr "needs_delay_slot" "yes")
6867 (set (attr "fp_mode")
6868 (if_then_else (eq_attr "fpu_single" "yes")
6869 (const_string "single") (const_string "double")))
6870 (set_attr "type" "jump")
6871 (set_attr "length" "2")])
6873 (define_insn_and_split "sibcall_pcrel"
6874 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6875 (match_operand 1 "" ""))
6876 (use (reg:SI FPSCR_MODES_REG))
6877 (clobber (match_scratch:SI 2 "=&k"))
6879 "TARGET_SH2 && !TARGET_FDPIC"
6884 rtx lab = PATTERN (gen_call_site ());
6887 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6888 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6890 SIBLING_CALL_P (call_insn) = 1;
6893 [(set_attr "needs_delay_slot" "yes")
6894 (set (attr "fp_mode")
6895 (if_then_else (eq_attr "fpu_single" "yes")
6896 (const_string "single") (const_string "double")))
6897 (set_attr "type" "jump_ind")])
6899 (define_insn_and_split "sibcall_pcrel_fdpic"
6900 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
6902 (use (reg:SI FPSCR_MODES_REG))
6903 (use (reg:SI PIC_REG))
6904 (clobber (match_scratch:SI 2 "=k"))
6906 "TARGET_SH2 && TARGET_FDPIC"
6908 "&& reload_completed"
6911 rtx lab = PATTERN (gen_call_site ());
6913 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6914 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
6916 SIBLING_CALL_P (i) = 1;
6919 [(set_attr "needs_delay_slot" "yes")
6920 (set (attr "fp_mode")
6921 (if_then_else (eq_attr "fpu_single" "yes")
6922 (const_string "single") (const_string "double")))
6923 (set_attr "type" "jump_ind")])
6925 (define_expand "sibcall"
6927 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6928 (match_operand 1 "" ""))
6929 (match_operand 2 "" "")
6930 (use (reg:SI FPSCR_MODES_REG))
6936 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6937 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6940 if (flag_pic && TARGET_SH2
6941 && MEM_P (operands[0])
6942 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6943 /* The PLT needs the PIC register, but the epilogue would have
6944 to restore it, so we can only use PC-relative PIC calls for
6945 static functions. */
6946 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6949 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
6952 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6956 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6960 operands[0] = sh_load_function_descriptor (operands[0]);
6961 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
6964 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6968 (define_insn "sibcall_valuei"
6969 [(set (match_operand 0 "" "=rf")
6970 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6971 (match_operand 2 "" "")))
6972 (use (reg:SI FPSCR_MODES_REG))
6974 "TARGET_SH1 && !TARGET_FDPIC"
6976 [(set_attr "needs_delay_slot" "yes")
6977 (set (attr "fp_mode")
6978 (if_then_else (eq_attr "fpu_single" "yes")
6979 (const_string "single") (const_string "double")))
6980 (set_attr "type" "jump_ind")])
6982 (define_insn "sibcall_valuei_fdpic"
6983 [(set (match_operand 0 "" "=rf")
6984 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6986 (use (reg:SI FPSCR_MODES_REG))
6987 (use (reg:SI PIC_REG))
6991 [(set_attr "needs_delay_slot" "yes")
6992 (set (attr "fp_mode")
6993 (if_then_else (eq_attr "fpu_single" "yes")
6994 (const_string "single") (const_string "double")))
6995 (set_attr "type" "jump_ind")])
6997 (define_insn "sibcall_valuei_pcrel"
6998 [(set (match_operand 0 "" "=rf")
6999 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7000 (match_operand 2 "" "")))
7001 (use (match_operand 3 "" ""))
7002 (use (reg:SI FPSCR_MODES_REG))
7004 "TARGET_SH2 && !TARGET_FDPIC"
7006 return "braf %1" "\n"
7009 [(set_attr "needs_delay_slot" "yes")
7010 (set (attr "fp_mode")
7011 (if_then_else (eq_attr "fpu_single" "yes")
7012 (const_string "single") (const_string "double")))
7013 (set_attr "type" "jump_ind")])
7015 (define_insn "sibcall_valuei_pcrel_fdpic"
7016 [(set (match_operand 0 "" "=rf")
7017 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7019 (use (match_operand 3))
7020 (use (reg:SI FPSCR_MODES_REG))
7021 (use (reg:SI PIC_REG))
7023 "TARGET_SH2 && TARGET_FDPIC"
7025 return "braf %1" "\n"
7028 [(set_attr "needs_delay_slot" "yes")
7029 (set (attr "fp_mode")
7030 (if_then_else (eq_attr "fpu_single" "yes")
7031 (const_string "single") (const_string "double")))
7032 (set_attr "type" "jump_ind")])
7034 ;; sibcall_value_pcrel used to have a =&k clobber for the scratch register
7035 ;; that it needs for the branch address. This causes troubles when there
7036 ;; is a big overlap of argument and return value registers. Hence, use a
7037 ;; fixed call clobbered register for the address. See also PR 67260.
7038 (define_insn_and_split "sibcall_value_pcrel"
7039 [(set (match_operand 0 "" "=rf")
7040 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7041 (match_operand 2 "" "")))
7042 (use (reg:SI FPSCR_MODES_REG))
7043 (clobber (reg:SI R1_REG))
7045 "TARGET_SH2 && !TARGET_FDPIC"
7050 rtx lab = PATTERN (gen_call_site ());
7051 rtx tmp = gen_rtx_REG (SImode, R1_REG);
7053 sh_expand_sym_label2reg (tmp, operands[1], lab, true);
7054 rtx call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
7058 SIBLING_CALL_P (call_insn) = 1;
7061 [(set_attr "needs_delay_slot" "yes")
7062 (set (attr "fp_mode")
7063 (if_then_else (eq_attr "fpu_single" "yes")
7064 (const_string "single") (const_string "double")))
7065 (set_attr "type" "jump_ind")])
7067 ;; Like for sibcall_value_pcrel, use a fixed call clobbered register for
7068 ;; the branch address.
7069 (define_insn_and_split "sibcall_value_pcrel_fdpic"
7070 [(set (match_operand 0 "" "=rf")
7071 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
7073 (use (reg:SI FPSCR_MODES_REG))
7074 (use (reg:SI PIC_REG))
7075 (clobber (reg:SI R1_REG))
7077 "TARGET_SH2 && TARGET_FDPIC"
7079 "&& reload_completed"
7082 rtx lab = PATTERN (gen_call_site ());
7083 rtx tmp = gen_rtx_REG (SImode, R1_REG);
7085 sh_expand_sym_label2reg (tmp, operands[1], lab, true);
7086 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
7090 SIBLING_CALL_P (i) = 1;
7093 [(set_attr "needs_delay_slot" "yes")
7094 (set (attr "fp_mode")
7095 (if_then_else (eq_attr "fpu_single" "yes")
7096 (const_string "single") (const_string "double")))
7097 (set_attr "type" "jump_ind")])
7099 (define_expand "sibcall_value"
7101 [(set (match_operand 0 "arith_reg_operand" "")
7102 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7103 (match_operand 2 "" "")))
7104 (match_operand 3 "" "")
7105 (use (reg:SI FPSCR_MODES_REG))
7111 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7112 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7115 if (flag_pic && TARGET_SH2
7116 && MEM_P (operands[1])
7117 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7118 /* The PLT needs the PIC register, but the epilogue would have
7119 to restore it, so we can only use PC-relative PIC calls for
7120 static functions. */
7121 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7124 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
7125 XEXP (operands[1], 0),
7128 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
7129 XEXP (operands[1], 0),
7134 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
7138 operands[1] = sh_load_function_descriptor (operands[1]);
7139 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
7143 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
7147 (define_expand "sibcall_epilogue"
7151 sh_expand_epilogue (true);
7155 (define_insn "indirect_jump_compact"
7157 (match_operand:SI 0 "arith_reg_operand" "r"))]
7160 [(set_attr "needs_delay_slot" "yes")
7161 (set_attr "type" "jump_ind")])
7163 (define_expand "indirect_jump"
7165 (match_operand 0 "register_operand" ""))]
7168 if (GET_MODE (operands[0]) != Pmode)
7169 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
7172 ;; The use of operand 1 / 2 helps us distinguish case table jumps
7173 ;; which can be present in structured code from indirect jumps which can not
7174 ;; be present in structured code. This allows -fprofile-arcs to work.
7176 ;; For SH1 processors.
7177 (define_insn "casesi_jump_1"
7179 (match_operand:SI 0 "register_operand" "r"))
7180 (use (label_ref (match_operand 1 "" "")))]
7183 [(set_attr "needs_delay_slot" "yes")
7184 (set_attr "type" "jump_ind")])
7186 ;; For all later processors.
7187 (define_insn "casesi_jump_2"
7188 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
7189 (label_ref (match_operand 1 "" ""))))
7190 (use (label_ref (match_operand 2 "" "")))]
7192 && (! INSN_UID (operands[1])
7193 || prev_real_insn (as_a<rtx_insn *> (operands[1])) == insn)"
7195 [(set_attr "needs_delay_slot" "yes")
7196 (set_attr "type" "jump_ind")])
7198 ;; Call subroutine returning any type.
7199 ;; ??? This probably doesn't work.
7200 (define_expand "untyped_call"
7201 [(parallel [(call (match_operand 0 "" "")
7203 (match_operand 1 "" "")
7204 (match_operand 2 "" "")])]
7205 "TARGET_SH2E || TARGET_SH2A"
7207 /* RA does not know that the call sets the function value registers.
7208 We avoid problems by claiming that those registers are clobbered
7210 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7211 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
7213 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7215 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7217 rtx set = XVECEXP (operands[2], 0, i);
7218 emit_move_insn (SET_DEST (set), SET_SRC (set));
7221 /* The optimizer does not know that the call sets the function value
7222 registers we stored in the result block. We avoid problems by
7223 claiming that all hard registers are used and clobbered at this
7225 emit_insn (gen_blockage ());
7230 ;; ------------------------------------------------------------------------
7232 ;; ------------------------------------------------------------------------
7235 [(set (reg:SI T_REG)
7236 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
7237 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7238 (plus:SI (match_dup 1) (const_int -1)))]
7241 [(set_attr "type" "arith")])
7248 ;; Load address of a label. This is only generated by the casesi expand,
7249 ;; and by machine_dependent_reorg (fixing up fp moves).
7250 ;; This must use unspec, because this only works for labels that are
7253 [(set (reg:SI R0_REG)
7254 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
7257 [(set_attr "in_delay_slot" "no")
7258 (set_attr "type" "arith")])
7260 ;; machine_dependent_reorg will make this a `mova'.
7261 (define_insn "mova_const"
7262 [(set (reg:SI R0_REG)
7263 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
7266 [(set_attr "in_delay_slot" "no")
7267 (set_attr "type" "arith")])
7269 ;; Loads of the GOTPC relocation values must not be optimized away
7270 ;; by e.g. any kind of CSE and must stay as they are. Although there
7271 ;; are other various ways to ensure this, we use an artificial counter
7272 ;; operand to generate unique symbols.
7273 (define_expand "GOTaddr2picreg"
7274 [(set (reg:SI R0_REG)
7275 (unspec:SI [(const:SI (unspec:SI [(match_dup 2)
7276 (match_operand:SI 0 "" "")]
7277 UNSPEC_PIC))] UNSPEC_MOVA))
7279 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC)))
7280 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))]
7283 if (TARGET_VXWORKS_RTP)
7285 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
7286 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7287 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
7293 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7294 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7298 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7299 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
7302 ;; A helper for GOTaddr2picreg to finish up the initialization of the
7304 (define_expand "vxworks_picreg"
7305 [(set (reg:SI PIC_REG)
7306 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
7307 (set (reg:SI R0_REG)
7308 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
7309 (set (reg:SI PIC_REG)
7310 (mem:SI (reg:SI PIC_REG)))
7311 (set (reg:SI PIC_REG)
7312 (mem:SI (plus:SI (reg:SI PIC_REG)
7314 "TARGET_VXWORKS_RTP")
7316 (define_expand "builtin_setjmp_receiver"
7317 [(match_operand 0 "" "")]
7320 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7324 (define_expand "call_site"
7325 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
7328 static HOST_WIDE_INT i = 0;
7329 operands[0] = GEN_INT (i);
7333 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
7334 ;; in symGOT_load expand.
7335 (define_insn_and_split "chk_guard_add"
7336 [(set (match_operand:SI 0 "register_operand" "=&r")
7337 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7342 "TARGET_SH1 && reload_completed"
7343 [(set (match_dup 0) (reg:SI PIC_REG))
7344 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
7346 [(set_attr "type" "arith")])
7348 (define_expand "sym_label2reg"
7349 [(set (match_operand:SI 0 "" "")
7350 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7351 (const (plus:SI (match_operand:SI 2 "" "")
7356 (define_expand "symPCREL_label2reg"
7357 [(set (match_operand:SI 0 "" "")
7360 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
7361 (const:SI (plus:SI (match_operand:SI 2 "" "")
7362 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
7366 (define_expand "symGOT_load"
7367 [(set (match_dup 2) (match_operand 1 "" ""))
7368 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
7369 (set (match_operand 0 "" "") (mem (match_dup 3)))]
7373 bool stack_chk_guard_p = false;
7375 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7376 : gen_rtx_REG (Pmode, PIC_REG);
7378 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7379 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7382 && flag_stack_protect
7383 && GET_CODE (operands[1]) == CONST
7384 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
7385 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
7386 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
7387 "__stack_chk_guard") == 0)
7388 stack_chk_guard_p = true;
7390 emit_move_insn (operands[2], operands[1]);
7392 /* When stack protector inserts codes after the result is set to
7393 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
7394 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
7395 when rX is a GOT address for the guard symbol. Ugly but doesn't
7396 matter because this is a rare situation. */
7397 if (stack_chk_guard_p)
7398 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
7400 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
7402 /* N.B. This is not constant for a GOTPLT relocation. */
7403 mem = gen_rtx_MEM (Pmode, operands[3]);
7404 MEM_NOTRAP_P (mem) = 1;
7405 /* ??? Should we have a special alias set for the GOT? */
7406 emit_move_insn (operands[0], mem);
7411 (define_expand "sym2GOT"
7412 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
7416 (define_expand "symGOT2reg"
7417 [(match_operand 0 "" "") (match_operand 1 "" "")]
7422 gotsym = gen_sym2GOT (operands[1]);
7423 PUT_MODE (gotsym, Pmode);
7424 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7426 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7431 (define_expand "sym2GOTFUNCDESC"
7432 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
7435 (define_expand "symGOTFUNCDESC2reg"
7436 [(match_operand 0) (match_operand 1)]
7439 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
7440 PUT_MODE (gotsym, Pmode);
7441 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7443 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7448 (define_expand "symGOTPLT2reg"
7449 [(match_operand 0 "" "") (match_operand 1 "" "")]
7452 rtx pltsym = gen_rtx_CONST (Pmode,
7453 gen_rtx_UNSPEC (Pmode,
7454 gen_rtvec (1, operands[1]),
7456 emit_insn (gen_symGOT_load (operands[0], pltsym));
7460 (define_expand "sym2GOTOFF"
7461 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
7465 (define_expand "symGOTOFF2reg"
7466 [(match_operand 0 "" "") (match_operand 1 "" "")]
7470 rtx t = (!can_create_pseudo_p ()
7472 : gen_reg_rtx (GET_MODE (operands[0])));
7474 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7475 : gen_rtx_REG (Pmode, PIC_REG);
7477 gotoffsym = gen_sym2GOTOFF (operands[1]);
7478 PUT_MODE (gotoffsym, Pmode);
7479 emit_move_insn (t, gotoffsym);
7480 rtx_insn *insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7482 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7487 (define_expand "sym2GOTOFFFUNCDESC"
7488 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
7491 (define_expand "symGOTOFFFUNCDESC2reg"
7492 [(match_operand 0) (match_operand 1)]
7495 rtx picreg = sh_get_fdpic_reg_initial_val ();
7496 rtx t = !can_create_pseudo_p ()
7498 : gen_reg_rtx (GET_MODE (operands[0]));
7500 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
7501 PUT_MODE (gotoffsym, Pmode);
7502 emit_move_insn (t, gotoffsym);
7503 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7507 (define_expand "symPLT_label2reg"
7508 [(set (match_operand:SI 0 "" "")
7511 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
7512 (const:SI (plus:SI (match_operand:SI 2 "" "")
7513 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
7514 ;; Even though the PIC register is not really used by the call
7515 ;; sequence in which this is expanded, the PLT code assumes the PIC
7516 ;; register is set, so we must not skip its initialization. Since
7517 ;; we only use this expand as part of calling sequences, and never
7518 ;; to take the address of a function, this is the best point to
7519 ;; insert the (use). Using the PLT to take the address of a
7520 ;; function would be wrong, not only because the PLT entry could
7521 ;; then be called from a function that doesn't initialize the PIC
7522 ;; register to the proper GOT, but also because pointers to the
7523 ;; same function might not compare equal, should they be set by
7524 ;; different shared libraries.
7525 (use (reg:SI PIC_REG))]
7529 (define_expand "sym2PIC"
7530 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
7534 ;; -------------------------------------------------------------------------
7535 ;; TLS code generation.
7537 ;; FIXME: The multi-insn asm blocks should be converted to use
7538 ;; define_insn_and_split.
7539 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
7540 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
7543 (define_insn "tls_global_dynamic"
7544 [(set (match_operand:SI 0 "register_operand" "=&z")
7545 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7548 (use (reg:SI FPSCR_MODES_REG))
7549 (use (reg:SI PIC_REG))
7550 (clobber (reg:SI PR_REG))
7551 (clobber (scratch:SI))]
7554 return "mov.l 1f,r4" "\n"
7563 "1: .long %a1@TLSGD" "\n"
7564 "2: .long __tls_get_addr@PLT" "\n"
7567 [(set_attr "type" "tls_load")
7568 (set_attr "length" "26")])
7570 (define_insn "tls_local_dynamic"
7571 [(set (match_operand:SI 0 "register_operand" "=&z")
7572 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7575 (use (reg:SI FPSCR_MODES_REG))
7576 (use (reg:SI PIC_REG))
7577 (clobber (reg:SI PR_REG))
7578 (clobber (scratch:SI))]
7581 return "mov.l 1f,r4" "\n"
7590 "1: .long %a1@TLSLDM" "\n"
7591 "2: .long __tls_get_addr@PLT" "\n"
7594 [(set_attr "type" "tls_load")
7595 (set_attr "length" "26")])
7597 (define_expand "sym2DTPOFF"
7598 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
7602 (define_expand "symDTPOFF2reg"
7603 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
7607 rtx t = (!can_create_pseudo_p ()
7609 : gen_reg_rtx (GET_MODE (operands[0])));
7611 dtpoffsym = gen_sym2DTPOFF (operands[1]);
7612 PUT_MODE (dtpoffsym, Pmode);
7613 emit_move_insn (t, dtpoffsym);
7614 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
7618 (define_expand "sym2GOTTPOFF"
7619 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
7623 (define_insn "tls_initial_exec"
7624 [(set (match_operand:SI 0 "register_operand" "=&r")
7625 (unspec:SI [(match_operand:SI 1 "" "")]
7627 (use (reg:SI GBR_REG))
7628 (use (reg:SI PIC_REG))
7629 (clobber (reg:SI R0_REG))]
7632 return "mov.l 1f,r0" "\n"
7634 " mov.l @(r0,r12),r0" "\n"
7641 [(set_attr "type" "tls_load")
7642 (set_attr "length" "16")])
7644 (define_expand "sym2TPOFF"
7645 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7649 (define_expand "symTPOFF2reg"
7650 [(match_operand 0 "" "") (match_operand 1 "" "")]
7655 tpoffsym = gen_sym2TPOFF (operands[1]);
7656 PUT_MODE (tpoffsym, Pmode);
7657 emit_move_insn (operands[0], tpoffsym);
7661 ;;------------------------------------------------------------------------------
7662 ;; Thread pointer getter and setter.
7664 ;; On SH the thread pointer is kept in the GBR.
7665 ;; These patterns are usually expanded from the respective built-in functions.
7666 (define_expand "get_thread_pointersi"
7667 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
7670 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
7671 (define_insn "store_gbr"
7672 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
7675 [(set_attr "type" "tls_load")])
7677 (define_expand "set_thread_pointersi"
7678 [(set (reg:SI GBR_REG)
7679 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
7683 (define_insn "load_gbr"
7684 [(set (reg:SI GBR_REG)
7685 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
7689 [(set_attr "type" "move")])
7691 ;;------------------------------------------------------------------------------
7692 ;; Thread pointer relative memory loads and stores.
7694 ;; On SH there are GBR displacement address modes which can be utilized to
7695 ;; access memory behind the thread pointer.
7696 ;; Since we do not allow using GBR for general purpose memory accesses, these
7697 ;; GBR addressing modes are formed by the combine pass.
7698 ;; This could be done with fewer patterns than below by using a mem predicate
7699 ;; for the GBR mem, but then reload would try to reload addresses with a
7700 ;; zero displacement for some strange reason.
7702 (define_insn "*mov<mode>_gbr_load"
7703 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7704 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7705 (match_operand:QIHISI 1 "gbr_displacement"))))]
7707 "mov.<bwl> @(%O1,gbr),%0"
7708 [(set_attr "type" "load")])
7710 (define_insn "*mov<mode>_gbr_load"
7711 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7712 (mem:QIHISI (reg:SI GBR_REG)))]
7714 "mov.<bwl> @(0,gbr),%0"
7715 [(set_attr "type" "load")])
7717 (define_insn "*mov<mode>_gbr_load"
7718 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7720 (mem:QIHI (plus:SI (reg:SI GBR_REG)
7721 (match_operand:QIHI 1 "gbr_displacement")))))]
7723 "mov.<bw> @(%O1,gbr),%0"
7724 [(set_attr "type" "load")])
7726 (define_insn "*mov<mode>_gbr_load"
7727 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7728 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
7730 "mov.<bw> @(0,gbr),%0"
7731 [(set_attr "type" "load")])
7733 (define_insn "*mov<mode>_gbr_store"
7734 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7735 (match_operand:QIHISI 0 "gbr_displacement")))
7736 (match_operand:QIHISI 1 "register_operand" "z"))]
7738 "mov.<bwl> %1,@(%O0,gbr)"
7739 [(set_attr "type" "store")])
7741 (define_insn "*mov<mode>_gbr_store"
7742 [(set (mem:QIHISI (reg:SI GBR_REG))
7743 (match_operand:QIHISI 0 "register_operand" "z"))]
7745 "mov.<bwl> %0,@(0,gbr)"
7746 [(set_attr "type" "store")])
7748 ;; DImode memory accesses have to be split in two SImode accesses.
7749 ;; Split them before reload, so that it gets a better chance to figure out
7750 ;; how to deal with the R0 restriction for the individual SImode accesses.
7751 ;; Do not match this insn during or after reload because it can't be split
7753 (define_insn_and_split "*movdi_gbr_load"
7754 [(set (match_operand:DI 0 "arith_reg_dest")
7755 (match_operand:DI 1 "gbr_address_mem"))]
7756 "TARGET_SH1 && can_create_pseudo_p ()"
7759 [(set (match_dup 3) (match_dup 5))
7760 (set (match_dup 4) (match_dup 6))]
7762 /* Swap low/high part load order on little endian, so that the result reg
7763 of the second load can be used better. */
7764 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
7765 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7766 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7767 operands[4 - off] = gen_highpart (SImode, operands[0]);
7768 operands[6 - off] = gen_highpart (SImode, operands[1]);
7771 (define_insn_and_split "*movdi_gbr_store"
7772 [(set (match_operand:DI 0 "gbr_address_mem")
7773 (match_operand:DI 1 "register_operand"))]
7774 "TARGET_SH1 && can_create_pseudo_p ()"
7777 [(set (match_dup 3) (match_dup 5))
7778 (set (match_dup 4) (match_dup 6))]
7780 /* Swap low/high part store order on big endian, so that stores of function
7781 call results can save a reg copy. */
7782 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
7783 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7784 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7785 operands[4 - off] = gen_highpart (SImode, operands[0]);
7786 operands[6 - off] = gen_highpart (SImode, operands[1]);
7789 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
7790 ;; in particular when the displacements are in the range of the regular move
7791 ;; insns. Thus, in the first split pass after the combine pass we search
7792 ;; for missed opportunities and try to fix them up ourselves.
7793 ;; If an equivalent GBR address can be determined the load / store is split
7794 ;; into one of the GBR load / store patterns.
7795 ;; All of that must happen before reload (GBR address modes use R0 as the
7796 ;; other operand) and there's no point of doing it if the GBR is not
7797 ;; referenced in a function at all.
7799 [(set (match_operand:QIHISIDI 0 "register_operand")
7800 (match_operand:QIHISIDI 1 "memory_operand"))]
7801 "TARGET_SH1 && !reload_in_progress && !reload_completed
7802 && df_regs_ever_live_p (GBR_REG)"
7803 [(set (match_dup 0) (match_dup 1))]
7805 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7806 if (gbr_mem != NULL_RTX)
7807 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7813 [(set (match_operand:SI 0 "register_operand")
7814 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7815 "TARGET_SH1 && !reload_in_progress && !reload_completed
7816 && df_regs_ever_live_p (GBR_REG)"
7817 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
7819 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7820 if (gbr_mem != NULL_RTX)
7821 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7826 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
7827 ;; Split those so that a GBR load can be used.
7829 [(set (match_operand:SI 0 "register_operand")
7830 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7831 "TARGET_SH2A && !reload_in_progress && !reload_completed
7832 && df_regs_ever_live_p (GBR_REG)"
7833 [(set (match_dup 2) (match_dup 1))
7834 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
7836 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7837 if (gbr_mem != NULL_RTX)
7839 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
7840 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7847 [(set (match_operand:QIHISIDI 0 "memory_operand")
7848 (match_operand:QIHISIDI 1 "register_operand"))]
7849 "TARGET_SH1 && !reload_in_progress && !reload_completed
7850 && df_regs_ever_live_p (GBR_REG)"
7851 [(set (match_dup 0) (match_dup 1))]
7853 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
7854 if (gbr_mem != NULL_RTX)
7855 operands[0] = replace_equiv_address (operands[0], gbr_mem);
7860 ;;------------------------------------------------------------------------------
7861 ;; case instruction for switch statements.
7863 ;; operand 0 is index
7864 ;; operand 1 is the minimum bound
7865 ;; operand 2 is the maximum bound - minimum bound + 1
7866 ;; operand 3 is CODE_LABEL for the table;
7867 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7868 (define_expand "casesi"
7869 [(match_operand:SI 0 "arith_reg_operand" "")
7870 (match_operand:SI 1 "arith_reg_operand" "")
7871 (match_operand:SI 2 "arith_reg_operand" "")
7872 (match_operand 3 "" "") (match_operand 4 "" "")]
7875 rtx reg = gen_reg_rtx (SImode);
7876 rtx reg2 = gen_reg_rtx (SImode);
7878 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7879 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7880 /* If optimizing, casesi_worker depends on the mode of the instruction
7881 before label it 'uses' - operands[3]. */
7882 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7884 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7886 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7888 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7889 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7890 operands[3], but to lab. We will fix this up in
7891 machine_dependent_reorg. */
7896 (define_expand "casesi_0"
7897 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7898 (set (match_dup 4) (minus:SI (match_dup 4)
7899 (match_operand:SI 1 "arith_operand" "")))
7901 (gtu:SI (match_dup 4)
7902 (match_operand:SI 2 "arith_reg_operand" "")))
7904 (if_then_else (ne (reg:SI T_REG)
7906 (label_ref (match_operand 3 "" ""))
7911 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7912 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7913 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7915 ;; The use on the T_REG in the casesi_worker* patterns links the bounds
7916 ;; checking insns and the table memory access. See also PR 69713.
7917 (define_insn "casesi_worker_0"
7918 [(set (match_operand:SI 0 "register_operand" "=r,r")
7919 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7920 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7921 (clobber (match_scratch:SI 3 "=X,1"))
7922 (clobber (match_scratch:SI 4 "=&z,z"))
7923 (use (reg:SI T_REG))]
7928 [(set (match_operand:SI 0 "register_operand" "")
7929 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7930 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7931 (clobber (match_scratch:SI 3 ""))
7932 (clobber (match_scratch:SI 4))
7933 (use (reg:SI T_REG))]
7934 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7935 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7936 (parallel [(set (match_dup 0)
7937 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7938 (label_ref (match_dup 2))] UNSPEC_CASESI))
7939 (clobber (match_dup 3))])
7940 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7942 if (GET_CODE (operands[2]) == CODE_LABEL)
7943 LABEL_NUSES (operands[2])++;
7947 [(set (match_operand:SI 0 "register_operand" "")
7948 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7949 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7950 (clobber (match_scratch:SI 3 ""))
7951 (clobber (match_scratch:SI 4))
7952 (use (reg:SI T_REG))]
7953 "TARGET_SH2 && reload_completed"
7954 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7955 (parallel [(set (match_dup 0)
7956 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7957 (label_ref (match_dup 2))] UNSPEC_CASESI))
7958 (clobber (match_dup 3))])]
7960 if (GET_CODE (operands[2]) == CODE_LABEL)
7961 LABEL_NUSES (operands[2])++;
7964 ;; This may be replaced with casesi_worker_2 in sh_reorg for PIC.
7965 ;; The insn length is set to 8 for that case.
7966 (define_insn "casesi_worker_1"
7967 [(set (match_operand:SI 0 "register_operand" "=r,r")
7968 (unspec:SI [(reg:SI R0_REG)
7969 (match_operand:SI 1 "register_operand" "0,r")
7970 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7971 (clobber (match_scratch:SI 3 "=X,1"))]
7974 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7976 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
7978 switch (GET_MODE (diff_vec))
7981 return "shll2 %1" "\n"
7982 " mov.l @(r0,%1),%0";
7984 return "add %1,%1" "\n"
7985 " mov.w @(r0,%1),%0";
7987 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7988 return "mov.b @(r0,%1),%0" "\n"
7991 return "mov.b @(r0,%1),%0";
7997 [(set_attr_alternative "length"
7998 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))
7999 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])])
8001 (define_insn "casesi_worker_2"
8002 [(set (match_operand:SI 0 "register_operand" "=r,r")
8003 (unspec:SI [(reg:SI R0_REG)
8004 (match_operand:SI 1 "register_operand" "0,r")
8005 (label_ref (match_operand 2 "" ""))
8006 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
8007 (clobber (match_operand:SI 4 "" "=X,1"))]
8008 "TARGET_SH2 && reload_completed && flag_pic"
8010 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
8011 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
8013 switch (GET_MODE (diff_vec))
8016 return "shll2 %1" "\n"
8019 " mov.l @(r0,%1),%0";
8021 return "add %1,%1" "\n"
8024 " mov.w @(r0,%1),%0";
8026 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
8027 return "add r0,%1" "\n"
8029 " mov.b @(r0,%1),%0" "\n"
8032 return "add r0,%1" "\n"
8034 " mov.b @(r0,%1),%0";
8039 [(set_attr "length" "8")])
8041 (define_expand "simple_return"
8043 "sh_can_use_simple_return_p ()")
8045 (define_expand "return"
8047 "reload_completed && epilogue_completed")
8049 (define_insn "*<code>_i"
8053 && ! sh_cfun_trap_exit_p ()"
8055 if (TARGET_SH2A && (dbr_sequence_length () == 0)
8056 && !current_function_interrupt)
8061 [(set_attr "type" "return")
8062 (set_attr "needs_delay_slot" "yes")])
8064 ;; trapa has no delay slot.
8065 (define_insn "*return_trapa"
8067 "TARGET_SH1 && reload_completed"
8069 [(set_attr "type" "return")])
8071 (define_expand "prologue"
8075 sh_expand_prologue ();
8079 (define_expand "epilogue"
8083 sh_expand_epilogue (false);
8086 (define_expand "eh_return"
8087 [(use (match_operand 0 "register_operand" ""))]
8090 emit_insn (gen_eh_set_ra_si (operands[0]));
8094 ;; Clobber the return address on the stack. We can't expand this
8095 ;; until we know where it will be put in the stack frame.
8097 (define_insn "eh_set_ra_si"
8098 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
8100 (clobber (match_scratch:SI 1 "=&r"))]
8105 [(unspec_volatile [(match_operand 0 "register_operand" "")]
8107 (clobber (match_scratch 1 ""))]
8111 sh_set_return_address (operands[0], operands[1]);
8115 (define_insn "blockage"
8116 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8119 [(set_attr "length" "0")])
8121 ;; Define movml instructions for SH2A target. Currently they are
8122 ;; used to push and pop all banked registers only.
8124 (define_insn "movml_push_banked"
8125 [(set (match_operand:SI 0 "register_operand" "=r")
8126 (plus (match_dup 0) (const_int -32)))
8127 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
8128 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
8129 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
8130 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
8131 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
8132 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
8133 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
8134 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
8135 "TARGET_SH2A && REGNO (operands[0]) == 15"
8137 [(set_attr "in_delay_slot" "no")])
8139 (define_insn "movml_pop_banked"
8140 [(set (match_operand:SI 0 "register_operand" "=r")
8141 (plus (match_dup 0) (const_int 32)))
8142 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
8143 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
8144 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
8145 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
8146 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
8147 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
8148 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
8149 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
8150 "TARGET_SH2A && REGNO (operands[0]) == 15"
8152 [(set_attr "in_delay_slot" "no")])
8154 ;; ------------------------------------------------------------------------
8156 ;; ------------------------------------------------------------------------
8159 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8160 (match_operand:SI 1 "t_reg_operand"))]
8163 [(set_attr "type" "arith")])
8165 (define_insn "movrt"
8166 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8167 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8170 [(set_attr "type" "arith")])
8172 (define_expand "cstoresi4"
8173 [(set (match_operand:SI 0 "register_operand")
8174 (match_operator:SI 1 "comparison_operator"
8175 [(match_operand:SI 2 "cmpsi_operand")
8176 (match_operand:SI 3 "arith_operand")]))]
8179 if (sh_expand_t_scc (operands))
8182 if (! currently_expanding_to_rtl)
8185 sh_emit_compare_and_set (operands, SImode);
8189 (define_expand "cstoredi4"
8190 [(set (match_operand:SI 0 "register_operand")
8191 (match_operator:SI 1 "comparison_operator"
8192 [(match_operand:DI 2 "arith_operand")
8193 (match_operand:DI 3 "arith_operand")]))]
8196 if (sh_expand_t_scc (operands))
8199 if (! currently_expanding_to_rtl)
8202 sh_emit_compare_and_set (operands, DImode);
8206 ;; Move the complement of the T reg to a reg.
8207 ;; On SH2A the movrt insn can be used.
8208 ;; On anything else than SH2A this has to be done with multiple instructions.
8209 ;; One obvious way would be:
8214 ;; However, this puts pressure on r0 in most cases and thus the following is
8220 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
8221 ;; becomes a one instruction operation. Moreover, care must be taken that
8222 ;; the insn can still be combined with inverted compare and branch code
8223 ;; around it. On the other hand, if a function returns the complement of
8224 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
8225 ;; lead to better code.
8226 (define_expand "movnegt"
8227 [(set (match_operand:SI 0 "arith_reg_dest" "")
8228 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8232 emit_insn (gen_movrt (operands[0], operands[1]));
8235 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
8236 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
8241 (define_insn_and_split "movrt_negc"
8242 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8243 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8244 (set (reg:SI T_REG) (const_int 1))
8245 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
8248 "&& !sh_in_recog_treg_set_expr ()"
8251 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8256 [(set_attr "type" "arith")])
8258 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
8259 ;; pattern can be used by the combine pass. Using a scratch reg for the
8260 ;; -1 constant results in slightly better register allocations compared to
8261 ;; generating a pseudo reg before reload.
8262 (define_insn_and_split "*movrt_negc"
8263 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8264 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8265 (clobber (match_scratch:SI 2 "=r"))
8266 (clobber (reg:SI T_REG))]
8267 "TARGET_SH1 && ! TARGET_SH2A"
8269 "&& !sh_in_recog_treg_set_expr ()"
8272 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8274 else if (reload_completed)
8276 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
8277 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
8284 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
8285 ;; clobber the T bit, which is useful when storing the T bit and the
8286 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
8287 ;; Usually we don't want this insn to be matched, except for cases where the
8288 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
8289 (define_insn_and_split "movrt_xor"
8290 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
8291 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8292 (use (reg:SI T_REG))]
8295 "&& reload_completed"
8296 [(set (match_dup 0) (reg:SI T_REG))
8297 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
8300 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
8302 ;; Notice that 0 - 0x80000000 = 0x80000000.
8304 ;; Single bit tests are usually done with zero_extract. On non-SH2A this
8305 ;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
8306 ;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
8307 ;; This is a special case of the generic treg_set_expr pattern and thus has
8308 ;; to come first or it will never match.
8309 (define_insn_and_split "*mov_t_msb_neg"
8310 [(set (match_operand:SI 0 "arith_reg_dest")
8311 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
8313 (const_int 2147483647)))
8314 (clobber (reg:SI T_REG))]
8317 "&& can_create_pseudo_p ()"
8318 [(parallel [(set (match_dup 0)
8319 (plus:SI (zero_extract:SI (match_dup 1)
8320 (const_int 1) (const_int 0))
8321 (const_int 2147483647)))
8322 (clobber (reg:SI T_REG))])])
8324 (define_insn_and_split "*mov_t_msb_neg"
8325 [(set (match_operand:SI 0 "arith_reg_dest")
8326 (plus:SI (match_operand 1 "treg_set_expr")
8327 (const_int 2147483647))) ;; 0x7fffffff
8328 (clobber (reg:SI T_REG))]
8331 "&& can_create_pseudo_p ()"
8334 if (negt_reg_operand (operands[1], VOIDmode))
8336 emit_insn (gen_negc (operands[0],
8337 force_reg (SImode, GEN_INT (-2147483648LL))));
8341 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8342 if (ti.remove_trailing_nott ())
8343 emit_insn (gen_negc (operands[0],
8344 force_reg (SImode, GEN_INT (-2147483648LL))));
8346 emit_insn (gen_addc (operands[0],
8347 force_reg (SImode, const0_rtx),
8348 force_reg (SImode, GEN_INT (2147483647))));
8352 (define_insn_and_split "*mov_t_msb_neg"
8353 [(set (match_operand:SI 0 "arith_reg_dest")
8354 (if_then_else:SI (match_operand 1 "treg_set_expr")
8355 (match_operand 2 "const_int_operand")
8356 (match_operand 3 "const_int_operand")))
8357 (clobber (reg:SI T_REG))]
8358 "TARGET_SH1 && can_create_pseudo_p ()
8359 && ((INTVAL (operands[2]) == -2147483648LL
8360 && INTVAL (operands[3]) == 2147483647LL)
8361 || (INTVAL (operands[2]) == 2147483647LL
8362 && INTVAL (operands[3]) == -2147483648LL))"
8367 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8369 if (INTVAL (operands[2]) == -2147483648LL)
8371 if (ti.remove_trailing_nott ())
8372 emit_insn (gen_negc (operands[0],
8373 force_reg (SImode, GEN_INT (-2147483648LL))));
8375 emit_insn (gen_addc (operands[0],
8376 force_reg (SImode, const0_rtx),
8377 force_reg (SImode, operands[3])));
8380 else if (INTVAL (operands[2]) == 2147483647LL)
8382 if (ti.remove_trailing_nott ())
8383 emit_insn (gen_addc (operands[0],
8384 force_reg (SImode, const0_rtx),
8385 force_reg (SImode, GEN_INT (2147483647LL))));
8387 emit_insn (gen_negc (operands[0],
8388 force_reg (SImode, GEN_INT (-2147483648LL))));
8395 ;; Store (negated) T bit as all zeros or ones in a reg.
8396 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
8397 ;; not Rn,Rn ! Rn = 0 - Rn
8398 (define_insn_and_split "mov_neg_si_t"
8399 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8400 (neg:SI (match_operand 1 "treg_set_expr")))]
8403 gcc_assert (t_reg_operand (operands[1], VOIDmode));
8404 return "subc %0,%0";
8406 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
8409 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8410 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
8412 if (ti.remove_trailing_nott ())
8413 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
8417 [(set_attr "type" "arith")])
8419 ;; Invert the T bit.
8420 ;; On SH2A we can use the nott insn. On anything else this must be done with
8421 ;; multiple insns like:
8424 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
8425 ;; pass will look for this insn. Disallow using it if pseudos can't be
8427 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
8428 ;; surrounding insns might not see and recombine it. Defer the splitting
8429 ;; of the nott until after the whole insn containing the treg_set_expr
8431 (define_insn_and_split "nott"
8432 [(set (reg:SI T_REG)
8433 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
8434 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
8436 gcc_assert (TARGET_SH2A);
8439 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
8440 [(set (match_dup 0) (reg:SI T_REG))
8441 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
8443 operands[0] = gen_reg_rtx (SImode);
8446 ;; Store T bit as MSB in a reg.
8447 ;; T = 0: 0x00000000 -> reg
8448 ;; T = 1: 0x80000000 -> reg
8449 (define_insn_and_split "*movt_msb"
8450 [(set (match_operand:SI 0 "arith_reg_dest")
8451 (mult:SI (match_operand:SI 1 "t_reg_operand")
8452 (const_int -2147483648))) ;; 0xffffffff80000000
8453 (clobber (reg:SI T_REG))]
8457 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
8459 ;; Store inverted T bit as MSB in a reg.
8460 ;; T = 0: 0x80000000 -> reg
8461 ;; T = 1: 0x00000000 -> reg
8462 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
8463 ;; On non SH2A we resort to the following sequence:
8467 ;; The T bit value will be modified during the sequence, but the rotcr insn
8468 ;; will restore its original value.
8469 (define_insn_and_split "*negt_msb"
8470 [(set (match_operand:SI 0 "arith_reg_dest")
8471 (match_operand:SI 1 "negt_reg_shl31_operand"))]
8474 "&& can_create_pseudo_p ()"
8477 rtx tmp = gen_reg_rtx (SImode);
8481 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
8482 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
8486 emit_move_insn (tmp, get_t_reg_rtx ());
8487 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
8488 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
8493 ;; The *cset_zero patterns convert optimizations such as
8494 ;; "if (test) x = 0;"
8496 ;; "x &= -(test == 0);"
8497 ;; back to conditional branch sequences if zero-displacement branches
8499 ;; FIXME: These patterns can be removed when conditional execution patterns
8500 ;; are implemented, since ifcvt will not perform these optimizations if
8501 ;; conditional execution is supported.
8502 (define_insn "*cset_zero"
8503 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8504 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
8506 (match_operand:SI 2 "arith_reg_operand" "0")))]
8507 "TARGET_SH1 && TARGET_ZDCBRANCH"
8513 [(set_attr "type" "arith") ;; poor approximation
8514 (set_attr "length" "4")])
8516 (define_insn "*cset_zero"
8517 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8518 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
8519 (match_operand:SI 2 "arith_reg_operand" "0")
8521 "TARGET_SH1 && TARGET_ZDCBRANCH"
8523 int tval = sh_eval_treg_value (operands[1]);
8528 else if (tval == false)
8535 [(set_attr "type" "arith") ;; poor approximation
8536 (set_attr "length" "4")])
8538 (define_insn_and_split "*cset_zero"
8539 [(set (match_operand:SI 0 "arith_reg_dest")
8540 (if_then_else:SI (match_operand 1 "treg_set_expr_not_const01")
8541 (match_dup 0) (const_int 0)))
8542 (clobber (reg:SI T_REG))]
8543 "TARGET_SH1 && TARGET_ZDCBRANCH && can_create_pseudo_p ()"
8547 (if_then_else:SI (match_dup 1) (match_dup 0) (const_int 0)))]
8549 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8550 if (ti.remove_trailing_nott ())
8551 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const0_rtx);
8553 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const1_rtx);
8556 (define_expand "cstoresf4"
8557 [(set (match_operand:SI 0 "register_operand")
8558 (match_operator:SI 1 "ordered_comparison_operator"
8559 [(match_operand:SF 2 "arith_operand")
8560 (match_operand:SF 3 "arith_operand")]))]
8563 if (! currently_expanding_to_rtl)
8566 sh_emit_compare_and_set (operands, SFmode);
8570 (define_expand "cstoredf4"
8571 [(set (match_operand:SI 0 "register_operand")
8572 (match_operator:SI 1 "ordered_comparison_operator"
8573 [(match_operand:DF 2 "arith_operand")
8574 (match_operand:DF 3 "arith_operand")]))]
8577 if (! currently_expanding_to_rtl)
8580 sh_emit_compare_and_set (operands, DFmode);
8584 ;; Sometimes the T bit result of insns is needed in normal registers.
8585 ;; Instead of open coding all the pattern variations, use the treg_set_expr
8586 ;; predicate to match any T bit output insn and split it out after.
8587 ;; This pattern should be below all other related patterns so that it is
8588 ;; considered as a last resort option during matching. This allows
8589 ;; overriding it with special case patterns.
8590 (define_insn_and_split "any_treg_expr_to_reg"
8591 [(set (match_operand:SI 0 "arith_reg_dest")
8592 (match_operand 1 "treg_set_expr"))
8593 (clobber (reg:SI T_REG))]
8594 "TARGET_SH1 && can_create_pseudo_p ()"
8596 "&& !sh_in_recog_treg_set_expr ()"
8600 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
8602 if (t_reg_operand (operands[1], VOIDmode))
8605 fprintf (dump_file, "t_reg_operand: emitting movt\n");
8606 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8609 if (negt_reg_operand (operands[1], VOIDmode))
8612 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
8613 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8617 /* If the split out insns ended with a nott, emit a movrt sequence,
8618 otherwise a normal movt. */
8619 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8621 if (ti.remove_trailing_nott ())
8623 /* Emit this same insn_and_split again. However, the next time it
8624 is split, it will emit the actual negc/movrt insn. This gives
8625 other surrounding insns the chance to see the trailing movrt. */
8628 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
8629 i = emit_insn (gen_any_treg_expr_to_reg (
8630 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
8635 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8637 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
8640 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
8644 ;; -------------------------------------------------------------------------
8645 ;; Instructions to cope with inline literal tables
8646 ;; -------------------------------------------------------------------------
8648 ;; 2 byte integer in line
8649 (define_insn "consttable_2"
8650 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8651 (match_operand 1 "" "")]
8655 if (operands[1] != const0_rtx)
8656 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8659 [(set_attr "length" "2")
8660 (set_attr "in_delay_slot" "no")])
8662 ;; 4 byte integer in line
8663 (define_insn "consttable_4"
8664 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8665 (match_operand 1 "" "")]
8669 if (operands[1] != const0_rtx)
8671 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8672 mark_symbol_refs_as_used (operands[0]);
8676 [(set_attr "length" "4")
8677 (set_attr "in_delay_slot" "no")])
8679 ;; 8 byte integer in line
8680 (define_insn "consttable_8"
8681 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8682 (match_operand 1 "" "")]
8686 if (operands[1] != const0_rtx)
8687 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8690 [(set_attr "length" "8")
8691 (set_attr "in_delay_slot" "no")])
8693 ;; 4 byte floating point
8694 (define_insn "consttable_sf"
8695 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8696 (match_operand 1 "" "")]
8700 if (operands[1] != const0_rtx)
8701 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8702 SFmode, GET_MODE_ALIGNMENT (SFmode));
8705 [(set_attr "length" "4")
8706 (set_attr "in_delay_slot" "no")])
8708 ;; 8 byte floating point
8709 (define_insn "consttable_df"
8710 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8711 (match_operand 1 "" "")]
8715 if (operands[1] != const0_rtx)
8716 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8717 DFmode, GET_MODE_ALIGNMENT (DFmode));
8720 [(set_attr "length" "8")
8721 (set_attr "in_delay_slot" "no")])
8723 ;; Alignment is needed for some constant tables; it may also be added for
8724 ;; Instructions at the start of loops, or after unconditional branches.
8725 ;; ??? We would get more accurate lengths if we did instruction
8726 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8727 ;; here is too conservative.
8729 ;; align to a two byte boundary
8730 (define_expand "align_2"
8731 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8735 ;; Align to a four byte boundary.
8736 ;; align_4 and align_log are instructions for the starts of loops, or
8737 ;; after unconditional branches, which may take up extra room.
8738 (define_expand "align_4"
8739 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8743 ;; Align to a cache line boundary.
8744 (define_insn "align_log"
8745 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8748 [(set_attr "length" "0")
8749 (set_attr "in_delay_slot" "no")])
8751 ;; Emitted at the end of the literal table, used to emit the
8752 ;; 32bit branch labels if needed.
8753 (define_insn "consttable_end"
8754 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8757 return output_jump_label_table ();
8759 [(set_attr "in_delay_slot" "no")])
8761 ;; Emitted at the end of the window in the literal table.
8762 (define_insn "consttable_window_end"
8763 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8766 [(set_attr "length" "0")
8767 (set_attr "in_delay_slot" "no")])
8769 ;; -------------------------------------------------------------------------
8770 ;; Minimum / maximum operations.
8771 ;; -------------------------------------------------------------------------
8773 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
8774 ;; and smax standard name patterns are defined, they will be used during
8775 ;; initial expansion and combine will then be able to form the actual min-max
8777 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
8778 ;; clipped, but there is currently no way of making use of this information.
8779 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8780 (define_expand "<code>si3"
8781 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
8782 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8783 (match_operand 2 "const_int_operand")))
8784 (clobber (reg:SI T_REG))])]
8787 /* Force the comparison value into a register, because greater-than
8788 comparisons can work only on registers. Combine will be able to pick up
8789 the constant value from the REG_EQUAL note when trying to form a min-max
8791 operands[2] = force_reg (SImode, operands[2]);
8795 ;; smax (smin (...))
8797 ;; smin (smax (...))
8798 (define_insn_and_split "*clips"
8799 [(set (match_operand:SI 0 "arith_reg_dest")
8800 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
8801 (match_operand 2 "clips_max_const_int"))
8802 (match_operand 3 "clips_min_const_int")))]
8807 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
8809 (define_insn "*clips"
8810 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8811 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
8812 (match_operand 2 "clips_min_const_int"))
8813 (match_operand 3 "clips_max_const_int")))]
8816 if (INTVAL (operands[3]) == 127)
8817 return "clips.b %0";
8818 else if (INTVAL (operands[3]) == 32767)
8819 return "clips.w %0";
8823 [(set_attr "type" "arith")])
8825 ;; If the expanded smin or smax patterns were not combined, split them into
8826 ;; a compare and branch sequence, because there are no real smin or smax
8828 (define_insn_and_split "*<code>si3"
8829 [(set (match_operand:SI 0 "arith_reg_dest")
8830 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8831 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
8832 (clobber (reg:SI T_REG))]
8833 "TARGET_SH2A && can_create_pseudo_p ()"
8838 rtx_code_label *skip_label = gen_label_rtx ();
8839 emit_move_insn (operands[0], operands[1]);
8841 rtx cmp_val = operands[2];
8842 if (satisfies_constraint_M (cmp_val))
8843 cmp_val = const0_rtx;
8845 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
8846 emit_jump_insn (<CODE> == SMIN
8847 ? gen_branch_false (skip_label)
8848 : gen_branch_true (skip_label));
8850 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
8854 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
8855 ;; with a register and a constant.
8856 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
8857 ;; clipped, but there is currently no way of making use of this information.
8858 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8859 (define_expand "uminsi3"
8860 [(set (match_operand:SI 0 "arith_reg_dest")
8861 (umin:SI (match_operand:SI 1 "arith_reg_operand")
8862 (match_operand 2 "const_int_operand")))]
8865 if (INTVAL (operands[2]) == 1)
8867 emit_insn (gen_clipu_one (operands[0], operands[1]));
8870 else if (! clipu_max_const_int (operands[2], VOIDmode))
8874 (define_insn "*clipu"
8875 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8876 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
8877 (match_operand 2 "clipu_max_const_int")))]
8880 if (INTVAL (operands[2]) == 255)
8881 return "clipu.b %0";
8882 else if (INTVAL (operands[2]) == 65535)
8883 return "clipu.w %0";
8887 [(set_attr "type" "arith")])
8889 (define_insn_and_split "clipu_one"
8890 [(set (match_operand:SI 0 "arith_reg_dest")
8891 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
8892 (clobber (reg:SI T_REG))]
8895 "&& can_create_pseudo_p ()"
8898 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
8899 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8903 ;; -------------------------------------------------------------------------
8905 ;; -------------------------------------------------------------------------
8907 ;; String/block move insn.
8909 (define_expand "movmemsi"
8910 [(parallel [(set (mem:BLK (match_operand:BLK 0))
8911 (mem:BLK (match_operand:BLK 1)))
8912 (use (match_operand:SI 2 "nonmemory_operand"))
8913 (use (match_operand:SI 3 "immediate_operand"))
8914 (clobber (reg:SI PR_REG))
8915 (clobber (reg:SI R4_REG))
8916 (clobber (reg:SI R5_REG))
8917 (clobber (reg:SI R0_REG))])]
8920 if (expand_block_move (operands))
8926 (define_insn "block_move_real"
8927 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8928 (mem:BLK (reg:SI R5_REG)))
8929 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8930 (use (match_operand 1 "" "Z,Ccl"))
8931 (clobber (reg:SI PR_REG))
8932 (clobber (reg:SI R0_REG))])]
8933 "TARGET_SH1 && ! TARGET_HARD_SH4"
8937 [(set_attr "type" "sfunc")
8938 (set_attr "needs_delay_slot" "yes")])
8940 (define_insn "block_lump_real"
8941 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8942 (mem:BLK (reg:SI R5_REG)))
8943 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8944 (use (match_operand 1 "" "Z,Ccl"))
8945 (use (reg:SI R6_REG))
8946 (clobber (reg:SI PR_REG))
8947 (clobber (reg:SI T_REG))
8948 (clobber (reg:SI R4_REG))
8949 (clobber (reg:SI R5_REG))
8950 (clobber (reg:SI R6_REG))
8951 (clobber (reg:SI R0_REG))])]
8952 "TARGET_SH1 && ! TARGET_HARD_SH4"
8956 [(set_attr "type" "sfunc")
8957 (set_attr "needs_delay_slot" "yes")])
8959 (define_insn "block_move_real_i4"
8960 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8961 (mem:BLK (reg:SI R5_REG)))
8962 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8963 (use (match_operand 1 "" "Z,Ccl"))
8964 (clobber (reg:SI PR_REG))
8965 (clobber (reg:SI R0_REG))
8966 (clobber (reg:SI R1_REG))
8967 (clobber (reg:SI R2_REG))])]
8972 [(set_attr "type" "sfunc")
8973 (set_attr "needs_delay_slot" "yes")])
8975 (define_insn "block_lump_real_i4"
8976 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8977 (mem:BLK (reg:SI R5_REG)))
8978 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8979 (use (match_operand 1 "" "Z,Ccl"))
8980 (use (reg:SI R6_REG))
8981 (clobber (reg:SI PR_REG))
8982 (clobber (reg:SI T_REG))
8983 (clobber (reg:SI R4_REG))
8984 (clobber (reg:SI R5_REG))
8985 (clobber (reg:SI R6_REG))
8986 (clobber (reg:SI R0_REG))
8987 (clobber (reg:SI R1_REG))
8988 (clobber (reg:SI R2_REG))
8989 (clobber (reg:SI R3_REG))])]
8994 [(set_attr "type" "sfunc")
8995 (set_attr "needs_delay_slot" "yes")])
8997 ;; byte compare pattern
8999 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
9000 (define_insn "cmpstr_t"
9001 [(set (reg:SI T_REG)
9006 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
9007 (match_operand:SI 1 "arith_reg_operand" "r"))
9008 (const_int 8) (const_int 0))
9009 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9010 (const_int 8) (const_int 8)))
9011 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9012 (const_int 8) (const_int 16)))
9013 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9014 (const_int 8) (const_int 24)))
9018 [(set_attr "type" "mt_group")])
9020 (define_expand "cmpstrsi"
9021 [(set (match_operand:SI 0 "register_operand")
9022 (compare:SI (match_operand:BLK 1 "memory_operand")
9023 (match_operand:BLK 2 "memory_operand")))
9024 (use (match_operand 3 "immediate_operand"))]
9025 "TARGET_SH1 && optimize"
9027 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
9033 (define_expand "cmpstrnsi"
9034 [(set (match_operand:SI 0 "register_operand")
9035 (compare:SI (match_operand:BLK 1 "memory_operand")
9036 (match_operand:BLK 2 "memory_operand")))
9037 (use (match_operand:SI 3 "nonmemory_operand"))
9038 (use (match_operand:SI 4 "immediate_operand"))]
9039 "TARGET_SH1 && optimize"
9041 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
9047 (define_expand "strlensi"
9048 [(set (match_operand:SI 0 "register_operand")
9049 (unspec:SI [(match_operand:BLK 1 "memory_operand")
9050 (match_operand:SI 2 "immediate_operand")
9051 (match_operand:SI 3 "immediate_operand")]
9052 UNSPEC_BUILTIN_STRLEN))]
9053 "TARGET_SH1 && optimize"
9055 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
9061 (define_expand "setmemqi"
9062 [(parallel [(set (match_operand:BLK 0 "memory_operand")
9063 (match_operand 2 "const_int_operand"))
9064 (use (match_operand:QI 1 "const_int_operand"))
9065 (use (match_operand:QI 3 "const_int_operand"))])]
9066 "TARGET_SH1 && optimize"
9068 if (optimize_insn_for_size_p ())
9071 sh_expand_setmem (operands);
9076 ;; -------------------------------------------------------------------------
9077 ;; Floating point instructions.
9078 ;; -------------------------------------------------------------------------
9080 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
9081 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
9082 ;; This avoids problems with reload. As a consequence, user initiated fpscr
9083 ;; stores to memory will always be ferried through a general register.
9084 ;; User initiated fpscr loads always have to undergo bit masking to preserve
9085 ;; the current fpu mode settings for the compiler generated code. Thus such
9086 ;; fpscr loads will always have to go through general registers anyways.
9087 (define_insn "lds_fpscr"
9088 [(set (reg:SI FPSCR_REG)
9089 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
9090 (set (reg:SI FPSCR_STAT_REG)
9091 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
9092 (set (reg:SI FPSCR_MODES_REG)
9093 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9098 [(set_attr "type" "gp_fpscr,mem_fpscr")])
9100 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
9102 (define_insn "sts_fpscr"
9103 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
9105 (use (reg:SI FPSCR_STAT_REG))
9106 (use (reg:SI FPSCR_MODES_REG))]
9111 [(set_attr "type" "mac_gp,fstore")])
9113 (define_expand "set_fpscr"
9114 [(parallel [(set (reg:SI FPSCR_REG)
9115 (match_operand:SI 0 "general_operand"))
9116 (set (reg:SI FPSCR_STAT_REG)
9117 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
9120 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
9121 get the current FPSCR value first.
9122 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
9124 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
9126 rtx a = force_reg (SImode, operands[0]);
9128 rtx b = gen_reg_rtx (SImode);
9129 emit_insn (gen_sts_fpscr (b));
9131 rtx a_xor_b = gen_reg_rtx (SImode);
9132 emit_insn (gen_xorsi3 (a_xor_b, a, b));
9134 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
9135 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
9137 rtx r = gen_reg_rtx (SImode);
9138 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
9139 emit_insn (gen_lds_fpscr (r));
9144 ;; ??? This uses the fp unit, but has no type indicating that.
9145 ;; If we did that, this would either give a bogus latency or introduce
9146 ;; a bogus FIFO constraint.
9147 ;; Since this insn is currently only used for prologues/epilogues,
9148 ;; it is probably best to claim no function unit, which matches the
9150 (define_insn "toggle_sz"
9151 [(set (reg:SI FPSCR_REG)
9152 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
9153 (set (reg:SI FPSCR_MODES_REG)
9154 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9157 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
9159 ;; Toggle FPU precision PR mode.
9161 (define_insn "toggle_pr"
9162 [(set (reg:SI FPSCR_REG)
9163 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
9164 (set (reg:SI FPSCR_MODES_REG)
9165 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9168 [(set_attr "type" "fpscr_toggle")])
9170 (define_expand "addsf3"
9171 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9172 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
9173 (match_operand:SF 2 "fp_arith_reg_operand")))]
9176 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
9180 (define_insn "addsf3_i"
9181 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9182 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9183 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9184 (clobber (reg:SI FPSCR_STAT_REG))
9185 (use (reg:SI FPSCR_MODES_REG))]
9188 [(set_attr "type" "fp")
9189 (set_attr "fp_mode" "single")])
9191 (define_expand "subsf3"
9192 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9193 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9194 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9197 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
9201 (define_insn "subsf3_i"
9202 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9203 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9204 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9205 (clobber (reg:SI FPSCR_STAT_REG))
9206 (use (reg:SI FPSCR_MODES_REG))]
9209 [(set_attr "type" "fp")
9210 (set_attr "fp_mode" "single")])
9212 (define_expand "mulsf3"
9213 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9214 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9215 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9218 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
9222 (define_insn "mulsf3_i"
9223 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9224 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9225 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9226 (clobber (reg:SI FPSCR_STAT_REG))
9227 (use (reg:SI FPSCR_MODES_REG))]
9230 [(set_attr "type" "fp")
9231 (set_attr "fp_mode" "single")])
9233 ;; FMA (fused multiply-add) patterns
9234 (define_expand "fmasf4"
9235 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9236 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
9237 (match_operand:SF 2 "fp_arith_reg_operand")
9238 (match_operand:SF 3 "fp_arith_reg_operand")))]
9241 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3]));
9245 (define_insn "fmasf4_i"
9246 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9247 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
9248 (match_operand:SF 2 "fp_arith_reg_operand" "f")
9249 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
9250 (clobber (reg:SI FPSCR_STAT_REG))
9251 (use (reg:SI FPSCR_MODES_REG))]
9254 [(set_attr "type" "fp")
9255 (set_attr "fp_mode" "single")])
9257 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
9258 ;; previous transformations. If FMA is generally allowed, let the combine
9260 (define_insn_and_split "*fmasf4"
9261 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9262 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
9263 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
9264 (match_operand:SF 3 "arith_reg_operand" "0")))
9265 (clobber (reg:SI FPSCR_STAT_REG))
9266 (use (reg:SI FPSCR_MODES_REG))]
9267 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
9269 "&& can_create_pseudo_p ()"
9270 [(parallel [(set (match_dup 0)
9271 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
9272 (clobber (reg:SI FPSCR_STAT_REG))
9273 (use (reg:SI FPSCR_MODES_REG))])]
9275 /* Change 'b * a + a' into 'a * b + a'.
9276 This is better for register allocation. */
9277 if (REGNO (operands[2]) == REGNO (operands[3]))
9278 std::swap (operands[1], operands[2]);
9280 [(set_attr "type" "fp")
9281 (set_attr "fp_mode" "single")])
9283 (define_expand "divsf3"
9284 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9285 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
9286 (match_operand:SF 2 "fp_arith_reg_operand")))]
9289 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
9293 (define_insn "divsf3_i"
9294 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9295 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9296 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9297 (clobber (reg:SI FPSCR_STAT_REG))
9298 (use (reg:SI FPSCR_MODES_REG))]
9301 [(set_attr "type" "fdiv")
9302 (set_attr "fp_mode" "single")])
9304 (define_expand "floatsisf2"
9305 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9306 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
9309 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
9313 (define_insn "floatsisf2_i4"
9314 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9315 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
9316 (clobber (reg:SI FPSCR_STAT_REG))
9317 (use (reg:SI FPSCR_MODES_REG))]
9320 [(set_attr "type" "fp")
9321 (set_attr "fp_mode" "single")])
9323 (define_expand "fix_truncsfsi2"
9324 [(set (match_operand:SI 0 "fpul_operand")
9325 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))]
9328 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
9332 (define_insn "fix_truncsfsi2_i4"
9333 [(set (match_operand:SI 0 "fpul_operand" "=y")
9334 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9335 (clobber (reg:SI FPSCR_STAT_REG))
9336 (use (reg:SI FPSCR_MODES_REG))]
9339 [(set_attr "type" "ftrc_s")
9340 (set_attr "fp_mode" "single")])
9342 (define_insn "cmpgtsf_t"
9343 [(set (reg:SI T_REG)
9344 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9345 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9346 (clobber (reg:SI FPSCR_STAT_REG))
9347 (use (reg:SI FPSCR_MODES_REG))]
9348 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9350 [(set_attr "type" "fp_cmp")
9351 (set_attr "fp_mode" "single")])
9353 (define_insn "cmpeqsf_t"
9354 [(set (reg:SI T_REG)
9355 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9356 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9357 (clobber (reg:SI FPSCR_STAT_REG))
9358 (use (reg:SI FPSCR_MODES_REG))]
9359 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9361 [(set_attr "type" "fp_cmp")
9362 (set_attr "fp_mode" "single")])
9364 (define_insn "ieee_ccmpeqsf_t"
9365 [(set (reg:SI T_REG)
9366 (ior:SI (reg:SI T_REG)
9367 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9368 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
9369 (clobber (reg:SI FPSCR_STAT_REG))
9370 (use (reg:SI FPSCR_MODES_REG))]
9371 "TARGET_IEEE && TARGET_SH2E"
9373 return output_ieee_ccmpeq (insn, operands);
9375 [(set_attr "length" "4")
9376 (set_attr "fp_mode" "single")])
9378 (define_expand "cbranchsf4"
9380 (if_then_else (match_operator 0 "ordered_comparison_operator"
9381 [(match_operand:SF 1 "arith_operand" "")
9382 (match_operand:SF 2 "arith_operand" "")])
9383 (match_operand 3 "" "")
9387 sh_emit_compare_and_branch (operands, SFmode);
9391 (define_expand "negsf2"
9392 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9393 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9396 (define_insn "*negsf2_i"
9397 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9398 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9401 [(set_attr "type" "fmove")])
9403 (define_expand "sqrtsf2"
9404 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9405 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
9408 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
9412 (define_insn "sqrtsf2_i"
9413 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9414 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9415 (clobber (reg:SI FPSCR_STAT_REG))
9416 (use (reg:SI FPSCR_MODES_REG))]
9419 [(set_attr "type" "fdiv")
9420 (set_attr "fp_mode" "single")])
9422 (define_insn "rsqrtsf2"
9423 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9424 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")]
9426 (clobber (reg:SI FPSCR_STAT_REG))
9427 (use (reg:SI FPSCR_MODES_REG))]
9428 "TARGET_FPU_ANY && TARGET_FSRRA"
9430 [(set_attr "type" "fsrra")
9431 (set_attr "fp_mode" "single")])
9433 ;; When the sincos pattern is defined, the builtin functions sin and cos
9434 ;; will be expanded to the sincos pattern and one of the output values will
9436 (define_expand "sincossf3"
9437 [(set (match_operand:SF 0 "nonimmediate_operand")
9438 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
9439 (set (match_operand:SF 1 "nonimmediate_operand")
9440 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
9441 "TARGET_FPU_ANY && TARGET_FSCA"
9443 rtx scaled = gen_reg_rtx (SFmode);
9444 rtx truncated = gen_reg_rtx (SImode);
9445 rtx fsca = gen_reg_rtx (V2SFmode);
9446 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
9448 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
9449 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
9450 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
9452 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
9453 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
9457 (define_insn_and_split "fsca"
9458 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
9460 (unspec:SF [(mult:SF
9461 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
9462 (match_operand:SF 2 "fsca_scale_factor" "i"))
9464 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
9466 (clobber (reg:SI FPSCR_STAT_REG))
9467 (use (reg:SI FPSCR_MODES_REG))]
9468 "TARGET_FPU_ANY && TARGET_FSCA"
9470 "&& !fpul_operand (operands[1], SImode)"
9473 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
9474 to a simple reg, otherwise reload will have trouble reloading the
9475 pseudo into fpul. */
9476 rtx x = XEXP (operands[1], 0);
9477 while (x != NULL_RTX && !fpul_operand (x, SImode))
9479 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
9482 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
9483 emit_insn (gen_fsca (operands[0], x, operands[2]));
9486 [(set_attr "type" "fsca")
9487 (set_attr "fp_mode" "single")])
9489 (define_expand "abssf2"
9490 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9491 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9494 (define_insn "*abssf2_i"
9495 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9496 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9499 [(set_attr "type" "fmove")])
9501 (define_expand "adddf3"
9502 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9503 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9504 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9507 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
9511 (define_insn "adddf3_i"
9512 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9513 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9514 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9515 (clobber (reg:SI FPSCR_STAT_REG))
9516 (use (reg:SI FPSCR_MODES_REG))]
9519 [(set_attr "type" "dfp_arith")
9520 (set_attr "fp_mode" "double")])
9522 (define_expand "subdf3"
9523 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9524 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9525 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9528 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
9532 (define_insn "subdf3_i"
9533 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9534 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9535 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9536 (clobber (reg:SI FPSCR_STAT_REG))
9537 (use (reg:SI FPSCR_MODES_REG))]
9540 [(set_attr "type" "dfp_arith")
9541 (set_attr "fp_mode" "double")])
9543 (define_expand "muldf3"
9544 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9545 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9546 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9549 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
9553 (define_insn "muldf3_i"
9554 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9555 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9556 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9557 (clobber (reg:SI FPSCR_STAT_REG))
9558 (use (reg:SI FPSCR_MODES_REG))]
9561 [(set_attr "type" "dfp_mul")
9562 (set_attr "fp_mode" "double")])
9564 (define_expand "divdf3"
9565 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9566 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9567 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9570 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
9574 (define_insn "divdf3_i"
9575 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9576 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9577 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9578 (clobber (reg:SI FPSCR_STAT_REG))
9579 (use (reg:SI FPSCR_MODES_REG))]
9582 [(set_attr "type" "dfdiv")
9583 (set_attr "fp_mode" "double")])
9585 (define_expand "floatsidf2"
9586 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9587 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9590 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
9594 (define_insn "floatsidf2_i"
9595 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9596 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9597 (clobber (reg:SI FPSCR_STAT_REG))
9598 (use (reg:SI FPSCR_MODES_REG))]
9601 [(set_attr "type" "dfp_conv")
9602 (set_attr "fp_mode" "double")])
9604 (define_expand "fix_truncdfsi2"
9605 [(set (match_operand:SI 0 "fpul_operand" "")
9606 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9609 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
9613 (define_insn "fix_truncdfsi2_i"
9614 [(set (match_operand:SI 0 "fpul_operand" "=y")
9615 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9616 (clobber (reg:SI FPSCR_STAT_REG))
9617 (use (reg:SI FPSCR_MODES_REG))]
9620 [(set_attr "type" "dfp_conv")
9621 (set_attr "dfp_comp" "no")
9622 (set_attr "fp_mode" "double")])
9624 (define_insn "cmpgtdf_t"
9625 [(set (reg:SI T_REG)
9626 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9627 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9628 (clobber (reg:SI FPSCR_STAT_REG))
9629 (use (reg:SI FPSCR_MODES_REG))]
9632 [(set_attr "type" "dfp_cmp")
9633 (set_attr "fp_mode" "double")])
9635 (define_insn "cmpeqdf_t"
9636 [(set (reg:SI T_REG)
9637 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9638 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9639 (clobber (reg:SI FPSCR_STAT_REG))
9640 (use (reg:SI FPSCR_MODES_REG))]
9643 [(set_attr "type" "dfp_cmp")
9644 (set_attr "fp_mode" "double")])
9646 (define_insn "*ieee_ccmpeqdf_t"
9647 [(set (reg:SI T_REG)
9648 (ior:SI (reg:SI T_REG)
9649 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9650 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
9651 (clobber (reg:SI FPSCR_STAT_REG))
9652 (use (reg:SI FPSCR_MODES_REG))]
9653 "TARGET_IEEE && TARGET_FPU_DOUBLE"
9655 return output_ieee_ccmpeq (insn, operands);
9657 [(set_attr "length" "4")
9658 (set_attr "fp_mode" "double")])
9660 (define_expand "cbranchdf4"
9662 (if_then_else (match_operator 0 "ordered_comparison_operator"
9663 [(match_operand:DF 1 "arith_operand" "")
9664 (match_operand:DF 2 "arith_operand" "")])
9665 (match_operand 3 "" "")
9669 sh_emit_compare_and_branch (operands, DFmode);
9673 (define_expand "negdf2"
9674 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9675 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9676 "TARGET_FPU_DOUBLE")
9678 (define_insn "*negdf2_i"
9679 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9680 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9683 [(set_attr "type" "fmove")])
9685 (define_expand "sqrtdf2"
9686 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9687 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9690 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
9694 (define_insn "sqrtdf2_i"
9695 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9696 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9697 (clobber (reg:SI FPSCR_STAT_REG))
9698 (use (reg:SI FPSCR_MODES_REG))]
9701 [(set_attr "type" "dfdiv")
9702 (set_attr "fp_mode" "double")])
9704 (define_expand "absdf2"
9705 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9706 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9707 "TARGET_FPU_DOUBLE")
9709 (define_insn "*absdf2_i"
9710 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9711 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9714 [(set_attr "type" "fmove")])
9716 (define_expand "extendsfdf2"
9717 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9718 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9721 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
9725 (define_insn "extendsfdf2_i4"
9726 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9727 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9728 (clobber (reg:SI FPSCR_STAT_REG))
9729 (use (reg:SI FPSCR_MODES_REG))]
9732 [(set_attr "type" "fp")
9733 (set_attr "fp_mode" "double")])
9735 (define_expand "truncdfsf2"
9736 [(set (match_operand:SF 0 "fpul_operand" "")
9737 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9740 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
9744 (define_insn "truncdfsf2_i4"
9745 [(set (match_operand:SF 0 "fpul_operand" "=y")
9746 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9747 (clobber (reg:SI FPSCR_STAT_REG))
9748 (use (reg:SI FPSCR_MODES_REG))]
9751 [(set_attr "type" "fp")
9752 (set_attr "fp_mode" "double")])
9754 ;; -------------------------------------------------------------------------
9755 ;; Bit field extract patterns.
9756 ;; -------------------------------------------------------------------------
9758 ;; These give better code for packed bitfields, because they allow
9759 ;; auto-increment addresses to be generated.
9761 (define_expand "insv"
9762 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9763 (match_operand:SI 1 "immediate_operand" "")
9764 (match_operand:SI 2 "immediate_operand" ""))
9765 (match_operand:SI 3 "general_operand" ""))]
9766 "TARGET_SH1 && TARGET_BIG_ENDIAN"
9768 rtx addr_target, orig_address, shift_reg, qi_val;
9769 HOST_WIDE_INT bitsize, size, v = 0;
9770 rtx x = operands[3];
9772 if (TARGET_SH2A && TARGET_BITOPS
9773 && (satisfies_constraint_Sbw (operands[0])
9774 || satisfies_constraint_Sbv (operands[0]))
9775 && satisfies_constraint_M (operands[1])
9776 && satisfies_constraint_K03 (operands[2]))
9778 if (satisfies_constraint_N (operands[3]))
9780 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
9783 else if (satisfies_constraint_M (operands[3]))
9785 emit_insn (gen_bset_m2a (operands[0], operands[2]));
9788 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
9789 && satisfies_constraint_M (operands[1]))
9791 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9794 else if (REG_P (operands[3])
9795 && satisfies_constraint_M (operands[1]))
9797 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
9798 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9802 /* ??? expmed doesn't care for non-register predicates. */
9803 if (! memory_operand (operands[0], VOIDmode)
9804 || ! immediate_operand (operands[1], VOIDmode)
9805 || ! immediate_operand (operands[2], VOIDmode)
9806 || ! general_operand (x, VOIDmode))
9808 /* If this isn't a 16 / 24 / 32 bit field, or if
9809 it doesn't start on a byte boundary, then fail. */
9810 bitsize = INTVAL (operands[1]);
9811 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9812 || (INTVAL (operands[2]) % 8) != 0)
9816 orig_address = XEXP (operands[0], 0);
9817 shift_reg = gen_reg_rtx (SImode);
9818 if (CONST_INT_P (x))
9821 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9825 emit_insn (gen_movsi (shift_reg, operands[3]));
9826 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9828 addr_target = copy_addr_to_reg (plus_constant (Pmode,
9829 orig_address, size - 1));
9831 operands[0] = replace_equiv_address (operands[0], addr_target);
9832 emit_insn (gen_movqi (operands[0], qi_val));
9836 if (CONST_INT_P (x))
9838 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9841 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9842 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9844 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9845 emit_insn (gen_movqi (operands[0], qi_val));
9851 (define_insn "movua"
9852 [(set (match_operand:SI 0 "register_operand" "=z")
9853 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
9857 [(set_attr "type" "movua")])
9859 ;; We shouldn't need this, but cse replaces increments with references
9860 ;; to other regs before flow has a chance to create post_inc
9861 ;; addressing modes, and only postreload's cse_move2add brings the
9862 ;; increments back to a usable form.
9864 [(set (match_operand:SI 0 "register_operand" "")
9865 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9866 (const_int 32) (const_int 0)))
9867 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9868 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
9869 [(set (match_operand:SI 0 "register_operand" "")
9870 (sign_extract:SI (mem:SI (post_inc:SI
9871 (match_operand:SI 1 "register_operand" "")))
9872 (const_int 32) (const_int 0)))]
9875 (define_expand "extv"
9876 [(set (match_operand:SI 0 "register_operand" "")
9877 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9878 (match_operand 2 "const_int_operand" "")
9879 (match_operand 3 "const_int_operand" "")))]
9880 "TARGET_SH4A || TARGET_SH2A"
9882 if (TARGET_SH2A && TARGET_BITOPS
9883 && (satisfies_constraint_Sbw (operands[1])
9884 || satisfies_constraint_Sbv (operands[1]))
9885 && satisfies_constraint_M (operands[2])
9886 && satisfies_constraint_K03 (operands[3]))
9888 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
9889 if (REGNO (operands[0]) != T_REG)
9890 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9894 && INTVAL (operands[2]) == 32
9895 && INTVAL (operands[3]) == 0
9896 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9898 rtx src = adjust_address (operands[1], BLKmode, 0);
9899 set_mem_size (src, 4);
9900 emit_insn (gen_movua (operands[0], src));
9907 (define_expand "extzv"
9908 [(set (match_operand:SI 0 "register_operand" "")
9909 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9910 (match_operand 2 "const_int_operand" "")
9911 (match_operand 3 "const_int_operand" "")))]
9912 "TARGET_SH4A || TARGET_SH2A"
9914 if (TARGET_SH2A && TARGET_BITOPS
9915 && (satisfies_constraint_Sbw (operands[1])
9916 || satisfies_constraint_Sbv (operands[1]))
9917 && satisfies_constraint_M (operands[2])
9918 && satisfies_constraint_K03 (operands[3]))
9920 emit_insn (gen_bld_m2a (operands[1], operands[3]));
9921 if (REGNO (operands[0]) != T_REG)
9922 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9926 && INTVAL (operands[2]) == 32
9927 && INTVAL (operands[3]) == 0
9928 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9930 rtx src = adjust_address (operands[1], BLKmode, 0);
9931 set_mem_size (src, 4);
9932 emit_insn (gen_movua (operands[0], src));
9939 ;; -------------------------------------------------------------------------
9940 ;; Extract negated single bit and zero extend it.
9941 ;; Generally we don't care about the exact xor const_int value, as long
9942 ;; as it contains the extracted bit. For simplicity, the pattern variations
9943 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
9944 ;; a xor const_int -1 value.
9946 (define_insn_and_split "*neg_zero_extract_0"
9947 [(set (reg:SI T_REG)
9948 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
9949 (match_operand 1 "const_int_operand"))
9951 (match_operand 2 "const_int_operand")))]
9952 "TARGET_SH1 && can_create_pseudo_p ()
9953 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
9956 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
9959 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
9961 /* Use cmp/pz to extract bit 31 into the T bit. */
9962 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
9966 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
9967 if (GET_MODE (operands[0]) != SImode)
9968 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
9971 (define_insn_and_split "*neg_zero_extract_1"
9972 [(set (reg:SI T_REG)
9973 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
9978 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9979 (const_int 1) (const_int 0)))])
9981 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
9982 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
9983 (define_insn_and_split "*neg_zero_extract_2"
9984 [(set (reg:SI T_REG)
9985 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
9987 (match_operand 1 "const_int_operand"))
9989 "TARGET_SH1 && can_create_pseudo_p ()"
9992 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9993 (const_int 1) (match_dup 1)))])
9995 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
9996 (define_insn_and_split "*neg_zero_extract_3"
9997 [(set (reg:SI T_REG)
9998 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
10001 "TARGET_SH1 && can_create_pseudo_p ()"
10004 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10005 (const_int 1) (const_int 31)))])
10007 ;; This is required for some bit patterns of DImode subregs.
10008 ;; It looks like combine gets confused by the DImode right shift and fails
10009 ;; to simplify things.
10010 (define_insn_and_split "*neg_zero_extract_4"
10011 [(set (reg:SI T_REG)
10013 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
10014 (match_operand 1 "const_int_operand"))
10015 (match_operand 2 "const_int_operand"))
10016 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
10017 (match_operand 4 "const_int_operand"))))
10019 "TARGET_SH1 && can_create_pseudo_p ()
10020 && INTVAL (operands[4]) > 0
10021 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
10024 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
10025 (const_int 1) (match_dup 2)))])
10027 (define_insn_and_split "*neg_zero_extract_5"
10028 [(set (reg:SI T_REG)
10029 (and:SI (not:SI (subreg:SI
10030 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10031 (match_operand 1 "const_int_operand"))
10034 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10035 && INTVAL (operands[1]) < 32"
10038 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10039 (const_int 1) (match_dup 1)))]
10041 operands[0] = gen_lowpart (SImode, operands[0]);
10044 (define_insn_and_split "*neg_zero_extract_6"
10045 [(set (reg:SI T_REG)
10046 (and:SI (not:SI (subreg:SI
10047 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10048 (match_operand 1 "const_int_operand"))
10051 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10052 && INTVAL (operands[1]) < 32"
10055 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10056 (const_int 1) (match_dup 1)))]
10058 operands[0] = gen_lowpart (SImode, operands[0]);
10061 ;; -------------------------------------------------------------------------
10062 ;; Extract single bit and zero extend it.
10063 ;; All patterns store the result bit in the T bit, although that is not
10064 ;; always possible to do with a single insn and a nott must be appended.
10065 ;; The trailing nott will be optimized away in most cases. E.g. if the
10066 ;; extracted bit is fed into a branch condition, the condition can be
10067 ;; inverted and the nott will be eliminated.
10068 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
10069 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
10071 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
10072 (define_insn_and_split "*zero_extract_0"
10073 [(set (reg:SI T_REG)
10074 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10076 (match_operand 1 "const_int_operand")))]
10077 "TARGET_SH1 && can_create_pseudo_p ()
10078 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
10081 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
10083 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
10085 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
10087 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
10091 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
10092 if (GET_MODE (operands[0]) != SImode)
10093 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10096 ;; This is required for some bit patterns of DImode subregs.
10097 ;; It looks like combine gets confused by the DImode right shift and fails
10098 ;; to simplify things.
10099 (define_insn_and_split "*zero_extract_1"
10100 [(set (reg:SI T_REG)
10101 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10103 (match_operand 1 "const_int_operand"))
10105 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10106 && INTVAL (operands[1]) < 32"
10109 [(set (reg:SI T_REG)
10110 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10112 (define_insn_and_split "*zero_extract_2"
10113 [(set (reg:SI T_REG)
10114 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10116 (match_operand 1 "const_int_operand"))
10118 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10119 && INTVAL (operands[1]) < 32"
10122 [(set (reg:SI T_REG)
10123 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10125 (define_insn_and_split "*zero_extract_3"
10126 [(set (match_operand:SI 0 "arith_reg_dest")
10127 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
10128 (match_operand 2 "const_int_operand"))
10129 (match_operand 3 "const_int_operand")))
10130 (clobber (reg:SI T_REG))]
10131 "TARGET_SH1 && can_create_pseudo_p ()
10132 && exact_log2 (INTVAL (operands[3])) >= 0"
10137 int rshift = INTVAL (operands[2]);
10138 int lshift = exact_log2 (INTVAL (operands[3]));
10140 rtx tmp = gen_reg_rtx (SImode);
10141 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10144 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx,
10145 GEN_INT (rshift + lshift))),
10146 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ()))));
10147 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift)));
10150 ;; -------------------------------------------------------------------------
10151 ;; SH2A instructions for bitwise operations.
10152 ;; FIXME: Convert multiple instruction insns to insn_and_split.
10153 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
10155 ;; Clear a bit in a memory location.
10156 (define_insn "bclr_m2a"
10157 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10159 (not:QI (ashift:QI (const_int 1)
10160 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10162 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10165 bclr.b %1,@(0,%t0)"
10166 [(set_attr "length" "4,4")])
10168 (define_insn "bclrmem_m2a"
10169 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10170 (and:QI (match_dup 0)
10171 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
10172 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
10175 bclr.b %W1,@(0,%t0)"
10176 [(set_attr "length" "4,4")])
10178 ;; Set a bit in a memory location.
10179 (define_insn "bset_m2a"
10180 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10182 (ashift:QI (const_int 1)
10183 (match_operand:QI 1 "const_int_operand" "K03,K03"))
10185 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10188 bset.b %1,@(0,%t0)"
10189 [(set_attr "length" "4,4")])
10191 (define_insn "bsetmem_m2a"
10192 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10193 (ior:QI (match_dup 0)
10194 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
10195 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
10198 bset.b %V1,@(0,%t0)"
10199 [(set_attr "length" "4,4")])
10201 ;;; Transfer the contents of the T bit to a specified bit of memory.
10202 (define_insn "bst_m2a"
10203 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
10204 (if_then_else (eq (reg:SI T_REG) (const_int 0))
10206 (not:QI (ashift:QI (const_int 1)
10207 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10210 (ashift:QI (const_int 1) (match_dup 1))
10212 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10216 [(set_attr "length" "4")])
10218 ;; Store a specified bit of memory in the T bit.
10219 (define_insn "bld_m2a"
10220 [(set (reg:SI T_REG)
10222 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
10224 (match_operand 1 "const_int_operand" "K03,K03")))]
10225 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10229 [(set_attr "length" "4,4")])
10231 ;; Store a specified bit of memory in the T bit.
10232 (define_insn "bldsign_m2a"
10233 [(set (reg:SI T_REG)
10235 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10237 (match_operand 1 "const_int_operand" "K03,K03")))]
10238 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10242 [(set_attr "length" "4,4")])
10244 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
10245 (define_insn "bld<mode>_reg"
10246 [(set (reg:SI T_REG)
10247 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
10249 (match_operand 1 "const_int_operand" "K03")))]
10250 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
10253 ;; Take logical and of a specified bit of memory with the T bit and
10254 ;; store its result in the T bit.
10255 (define_insn "band_m2a"
10256 [(set (reg:SI T_REG)
10257 (and:SI (reg:SI T_REG)
10259 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10261 (match_operand 1 "const_int_operand" "K03,K03"))))]
10262 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10265 band.b %1,@(0,%t0)"
10266 [(set_attr "length" "4,4")])
10268 (define_insn "bandreg_m2a"
10269 [(set (match_operand:SI 0 "register_operand" "=r,r")
10270 (and:SI (zero_extract:SI
10271 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10273 (match_operand 2 "const_int_operand" "K03,K03"))
10274 (match_operand:SI 3 "register_operand" "r,r")))]
10275 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10277 static const char* alt[] =
10279 "band.b %2,%1" "\n"
10282 "band.b %2,@(0,%t1)" "\n"
10285 return alt[which_alternative];
10287 [(set_attr "length" "6,6")])
10289 ;; Take logical or of a specified bit of memory with the T bit and
10290 ;; store its result in the T bit.
10291 (define_insn "bor_m2a"
10292 [(set (reg:SI T_REG)
10293 (ior:SI (reg:SI T_REG)
10295 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10297 (match_operand 1 "const_int_operand" "K03,K03"))))]
10298 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10302 [(set_attr "length" "4,4")])
10304 (define_insn "borreg_m2a"
10305 [(set (match_operand:SI 0 "register_operand" "=r,r")
10306 (ior:SI (zero_extract:SI
10307 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10309 (match_operand 2 "const_int_operand" "K03,K03"))
10310 (match_operand:SI 3 "register_operand" "=r,r")))]
10311 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10313 static const char* alt[] =
10318 "bor.b %2,@(0,%t1)" "\n"
10321 return alt[which_alternative];
10323 [(set_attr "length" "6,6")])
10325 ;; Take exclusive or of a specified bit of memory with the T bit and
10326 ;; store its result in the T bit.
10327 (define_insn "bxor_m2a"
10328 [(set (reg:SI T_REG)
10329 (xor:SI (reg:SI T_REG)
10331 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10333 (match_operand 1 "const_int_operand" "K03,K03"))))]
10334 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10337 bxor.b %1,@(0,%t0)"
10338 [(set_attr "length" "4,4")])
10340 (define_insn "bxorreg_m2a"
10341 [(set (match_operand:SI 0 "register_operand" "=r,r")
10342 (xor:SI (zero_extract:SI
10343 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10345 (match_operand 2 "const_int_operand" "K03,K03"))
10346 (match_operand:SI 3 "register_operand" "=r,r")))]
10347 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10349 static const char* alt[] =
10351 "bxor.b %2,%1" "\n"
10354 "bxor.b %2,@(0,%t1)" "\n"
10357 return alt[which_alternative];
10359 [(set_attr "length" "6,6")])
10361 ;; -------------------------------------------------------------------------
10363 ;; -------------------------------------------------------------------------
10364 ;; This matches cases where the bit in a memory location is set.
10366 [(set (match_operand:SI 0 "register_operand")
10367 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10369 (ior:SI (match_dup 0)
10370 (match_operand:SI 2 "const_int_operand")))
10372 (match_operand 3 "arith_reg_operand"))]
10373 "TARGET_SH2A && TARGET_BITOPS
10374 && satisfies_constraint_Pso (operands[2])
10375 && REGNO (operands[0]) == REGNO (operands[3])"
10376 [(set (match_dup 1)
10377 (ior:QI (match_dup 1) (match_dup 2)))]
10380 ;; This matches cases where the bit in a memory location is cleared.
10382 [(set (match_operand:SI 0 "register_operand")
10383 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10385 (and:SI (match_dup 0)
10386 (match_operand:SI 2 "const_int_operand")))
10388 (match_operand 3 "arith_reg_operand"))]
10389 "TARGET_SH2A && TARGET_BITOPS
10390 && satisfies_constraint_Psz (operands[2])
10391 && REGNO (operands[0]) == REGNO (operands[3])"
10392 [(set (match_dup 1)
10393 (and:QI (match_dup 1) (match_dup 2)))]
10396 ;; This matches cases where a stack pointer increment at the start of the
10397 ;; epilogue combines with a stack slot read loading the return value.
10399 [(set (match_operand:SI 0 "arith_reg_operand" "")
10400 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
10401 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
10402 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
10405 ;; See the comment on the dt combiner pattern above.
10407 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10408 (plus:SI (match_dup 0)
10410 (set (reg:SI T_REG)
10411 (eq:SI (match_dup 0) (const_int 0)))]
10415 ;; The following peepholes fold load sequences for which reload was not
10416 ;; able to generate a displacement addressing move insn.
10417 ;; This can happen when reload has to transform a move insn
10418 ;; without displacement into one with displacement. Or when reload can't
10419 ;; fit a displacement into the insn's constraints. In the latter case, the
10420 ;; load destination reg remains at r0, which reload compensates by inserting
10421 ;; another mov insn.
10425 ;; mov.{b,w} @(r0,r15),r0
10428 ;; mov.{b,w} @(54,r15),r3
10431 [(set (match_operand:SI 0 "arith_reg_dest" "")
10432 (match_operand:SI 1 "const_int_operand" ""))
10433 (set (match_operand:SI 2 "arith_reg_dest" "")
10435 (mem:QI (plus:SI (match_dup 0)
10436 (match_operand:SI 3 "arith_reg_operand" "")))))
10437 (set (match_operand:QI 4 "arith_reg_dest" "")
10438 (match_operand:QI 5 "arith_reg_operand" ""))]
10440 && sh_legitimate_index_p (QImode, operands[1], true, true)
10441 && REGNO (operands[2]) == REGNO (operands[5])
10442 && peep2_reg_dead_p (3, operands[5])"
10443 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
10447 [(set (match_operand:SI 0 "arith_reg_dest" "")
10448 (match_operand:SI 1 "const_int_operand" ""))
10449 (set (match_operand:SI 2 "arith_reg_dest" "")
10451 (mem:HI (plus:SI (match_dup 0)
10452 (match_operand:SI 3 "arith_reg_operand" "")))))
10453 (set (match_operand:HI 4 "arith_reg_dest" "")
10454 (match_operand:HI 5 "arith_reg_operand" ""))]
10456 && sh_legitimate_index_p (HImode, operands[1], true, true)
10457 && REGNO (operands[2]) == REGNO (operands[5])
10458 && peep2_reg_dead_p (3, operands[5])"
10459 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
10464 ;; mov.{b,w} @(r0,r15),r1
10466 ;; mov.{b,w} @(54,r15),r1
10469 [(set (match_operand:SI 0 "arith_reg_dest" "")
10470 (match_operand:SI 1 "const_int_operand" ""))
10471 (set (match_operand:SI 2 "arith_reg_dest" "")
10473 (mem:QI (plus:SI (match_dup 0)
10474 (match_operand:SI 3 "arith_reg_operand" "")))))]
10476 && sh_legitimate_index_p (QImode, operands[1], true, true)
10477 && (peep2_reg_dead_p (2, operands[0])
10478 || REGNO (operands[0]) == REGNO (operands[2]))"
10479 [(set (match_dup 2)
10480 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
10484 [(set (match_operand:SI 0 "arith_reg_dest" "")
10485 (match_operand:SI 1 "const_int_operand" ""))
10486 (set (match_operand:SI 2 "arith_reg_dest" "")
10488 (mem:HI (plus:SI (match_dup 0)
10489 (match_operand:SI 3 "arith_reg_operand" "")))))]
10491 && sh_legitimate_index_p (HImode, operands[1], true, true)
10492 && (peep2_reg_dead_p (2, operands[0])
10493 || REGNO (operands[0]) == REGNO (operands[2]))"
10494 [(set (match_dup 2)
10495 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
10499 ;; mov.{b,w} @(r0,r15),r0
10502 ;; mov.{b,w} @(r0,r15),r3
10504 ;; This can happen when initially a displacement address is picked, where
10505 ;; the destination reg is fixed to r0, and then the address is transformed
10506 ;; into 'r0 + reg'.
10508 [(set (match_operand:SI 0 "arith_reg_dest" "")
10510 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10511 (match_operand:SI 2 "arith_reg_operand" "")))))
10512 (set (match_operand:QI 3 "arith_reg_dest" "")
10513 (match_operand:QI 4 "arith_reg_operand" ""))]
10515 && REGNO (operands[0]) == REGNO (operands[4])
10516 && peep2_reg_dead_p (2, operands[0])"
10517 [(set (match_dup 3)
10518 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
10522 [(set (match_operand:SI 0 "arith_reg_dest" "")
10524 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10525 (match_operand:SI 2 "arith_reg_operand" "")))))
10526 (set (match_operand:HI 3 "arith_reg_dest" "")
10527 (match_operand:HI 4 "arith_reg_operand" ""))]
10529 && REGNO (operands[0]) == REGNO (operands[4])
10530 && peep2_reg_dead_p (2, operands[0])"
10531 [(set (match_dup 3)
10532 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
10536 ;; mov b,c -> extu.bw a,c
10538 [(set (match_operand:SI 0 "arith_reg_dest")
10539 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
10540 (set (match_operand:SI 2 "arith_reg_dest")
10542 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10543 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
10546 ;; extu.bw r1,r1 -> extu.bw r0,r1
10548 [(set (match_operand 0 "arith_reg_dest")
10549 (match_operand 1 "arith_reg_operand"))
10550 (set (match_operand:SI 2 "arith_reg_dest")
10551 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
10553 && REGNO (operands[0]) == REGNO (operands[3])
10554 && (REGNO (operands[0]) == REGNO (operands[2])
10555 || peep2_reg_dead_p (2, operands[0]))"
10556 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
10558 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
10562 ;; mov b,a -> < nop >
10564 [(set (match_operand 0 "register_operand")
10565 (match_operand 1 "register_operand"))
10566 (set (match_operand 2 "register_operand")
10567 (match_operand 3 "register_operand"))]
10569 && REGNO (operands[0]) == REGNO (operands[3])
10570 && REGNO (operands[1]) == REGNO (operands[2])
10571 && peep2_reg_dead_p (2, operands[3])"
10575 ;; and r4,r1 -> mov r1,r0
10576 ;; mov r1,r0 and #3,r0
10577 (define_code_iterator ANDIORXOR [and ior xor])
10579 [(set (match_operand:SI 0 "register_operand")
10580 (match_operand:SI 1 "const_logical_operand"))
10581 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
10582 (set (reg:SI R0_REG) (match_dup 2))]
10584 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
10585 [(set (reg:SI R0_REG) (match_dup 2))
10586 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
10588 ;; ... r2,r0 ... r2,r0
10589 ;; or r1,r0 -> or r0,r1
10592 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
10594 [(set (match_operand:SI 0 "arith_reg_dest")
10595 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
10596 (set (match_dup 1) (match_dup 0))]
10597 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10598 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
10601 ;; add #-48,r0 -> add #-48,r12
10602 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
10605 [(set (match_operand:SI 0 "arith_reg_dest")
10606 (match_operand:SI 1 "arith_reg_dest"))
10607 (set (match_dup 0) (plus:SI (match_dup 0)
10608 (match_operand:SI 2 "const_int_operand")))
10609 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
10611 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
10614 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
10615 sh_peephole_emit_move_insn (operands[3], operands[1]);
10618 ;; mov.l @(r0,r9),r1
10619 ;; mov r1,r0 -> mov @(r0,r9),r0
10621 [(set (match_operand:SI 0 "arith_reg_dest")
10622 (match_operand:SI 1 "general_movsrc_operand"))
10623 (set (match_operand:SI 2 "arith_reg_dest")
10625 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10628 sh_peephole_emit_move_insn (operands[2], operands[1]);
10632 [(set (match_operand:QIHI 0 "register_operand")
10633 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
10634 (set (match_operand:QIHI 2 "register_operand")
10636 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10639 sh_peephole_emit_move_insn (operands[2], operands[1]);
10643 [(set (match_operand:SI 0 "arith_reg_dest")
10644 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
10645 (set (match_operand:SI 2 "arith_reg_dest")
10647 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10650 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
10651 sh_remove_overlapping_post_inc (operands[2], operands[1]))));
10654 ;; mov.w @(18,r1),r0 (r0 = HImode)
10655 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
10656 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
10657 ;; tst r1,r13 tst r0,r13
10659 [(set (match_operand 0 "arith_reg_dest")
10660 (match_operand 1 "arith_reg_dest"))
10661 (set (match_operand:SI 2 "arith_reg_dest")
10662 (match_operand:SI 3))
10663 (set (reg:SI T_REG)
10664 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10665 (match_operand:SI 5 "arith_reg_operand"))
10668 && peep2_reg_dead_p (3, operands[0])
10669 && !reg_overlap_mentioned_p (operands[0], operands[3])
10670 && (REGNO (operands[0]) == REGNO (operands[4])
10671 || REGNO (operands[0]) == REGNO (operands[5]))
10672 && (REGNO (operands[2]) == REGNO (operands[4])
10673 || REGNO (operands[2]) == REGNO (operands[5]))"
10676 if (REGNO (operands[1]) == REGNO (operands[2]))
10677 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
10679 // We don't know what the new set insn will be in detail. Just make sure
10680 // that it still can be recognized and the constraints are satisfied.
10681 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10682 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10684 recog_data_d prev_recog_data = recog_data;
10685 bool i_invalid = insn_invalid_p (i, false);
10686 recog_data = prev_recog_data;
10691 sh_check_add_incdec_notes (i);
10693 emit_insn (gen_tstsi_t (operands[2],
10694 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10697 ;; mov.w @(18,r1),r0 (r0 = HImode)
10698 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
10699 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
10700 ;; tst r1,r13 tst r0,r13
10702 [(set (match_operand:SI 2 "arith_reg_dest")
10703 (match_operand:SI 3))
10704 (set (match_operand 0 "arith_reg_dest")
10705 (match_operand 1 "arith_reg_operand"))
10706 (set (reg:SI T_REG)
10707 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10708 (match_operand:SI 5 "arith_reg_operand"))
10711 && peep2_reg_dead_p (3, operands[0])
10712 && !reg_overlap_mentioned_p (operands[0], operands[3])
10713 && (REGNO (operands[0]) == REGNO (operands[4])
10714 || REGNO (operands[0]) == REGNO (operands[5]))
10715 && (REGNO (operands[2]) == REGNO (operands[4])
10716 || REGNO (operands[2]) == REGNO (operands[5]))"
10719 // We don't know what the new set insn will be in detail. Just make sure
10720 // that it still can be recognized and the constraints are satisfied.
10721 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10722 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10724 recog_data_d prev_recog_data = recog_data;
10725 bool i_invalid = insn_invalid_p (i, false);
10726 recog_data = prev_recog_data;
10731 sh_check_add_incdec_notes (i);
10733 emit_insn (gen_tstsi_t (operands[2],
10734 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10737 ;; This is not a peephole, but it's here because it's actually supposed
10738 ;; to be one. It tries to convert a sequence such as
10739 ;; movt r2 -> movt r2
10740 ;; movt r13 mov r2,r13
10741 ;; This gives the schduler a bit more freedom to hoist a following
10742 ;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
10743 ;; better chances for parallel execution.
10744 ;; We can do this with a peephole2 pattern, but then the cprop_hardreg
10745 ;; pass will revert the change. See also PR 64331.
10746 ;; Thus do it manually in one of the split passes after register allocation.
10747 ;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy.
10749 [(set (match_operand:SI 0 "arith_reg_dest")
10750 (match_operand:SI 1 "t_reg_operand"))]
10751 "TARGET_SH1 && reload_completed"
10752 [(set (match_dup 0) (match_dup 1))]
10754 rtx t_reg = get_t_reg_rtx ();
10756 for (rtx_insn* i = prev_nonnote_nondebug_insn_bb (curr_insn); i != NULL;
10757 i = prev_nonnote_nondebug_insn_bb (i))
10759 if (!INSN_P (i) || DEBUG_INSN_P (i))
10762 if (modified_in_p (t_reg, i) || BARRIER_P (i))
10765 if (sh_is_movt_insn (i))
10767 rtx r = sh_movt_set_dest (i);
10768 if (!modified_between_p (r, i, curr_insn))
10778 [(set (match_operand:SI 0 "register_operand" "=r")
10779 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10780 (set (mem:SF (match_dup 0))
10781 (match_operand:SF 2 "general_movsrc_operand" ""))]
10782 "TARGET_SH1 && REGNO (operands[0]) == 0
10783 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10784 || (GET_CODE (operands[2]) == SUBREG
10785 && REGNO (SUBREG_REG (operands[2])) < 16))
10786 && reg_unused_after (operands[0], insn)"
10787 "mov.l %2,@(%0,%1)")
10790 [(set (match_operand:SI 0 "register_operand" "=r")
10791 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10792 (set (match_operand:SF 2 "general_movdst_operand" "")
10794 (mem:SF (match_dup 0)))]
10795 "TARGET_SH1 && REGNO (operands[0]) == 0
10796 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10797 || (GET_CODE (operands[2]) == SUBREG
10798 && REGNO (SUBREG_REG (operands[2])) < 16))
10799 && reg_unused_after (operands[0], insn)"
10800 "mov.l @(%0,%1),%2")
10803 [(set (match_operand:SI 0 "register_operand" "=r")
10804 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10805 (set (mem:SF (match_dup 0))
10806 (match_operand:SF 2 "general_movsrc_operand" ""))]
10807 "TARGET_SH2E && REGNO (operands[0]) == 0
10808 && ((REG_P (operands[2])
10809 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10810 || (GET_CODE (operands[2]) == SUBREG
10811 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10812 && reg_unused_after (operands[0], insn)"
10813 "fmov{.s|} %2,@(%0,%1)")
10816 [(set (match_operand:SI 0 "register_operand" "=r")
10817 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10818 (set (match_operand:SF 2 "general_movdst_operand" "")
10820 (mem:SF (match_dup 0)))]
10821 "TARGET_SH2E && REGNO (operands[0]) == 0
10822 && ((REG_P (operands[2])
10823 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10824 || (GET_CODE (operands[2]) == SUBREG
10825 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10826 && reg_unused_after (operands[0], insn)"
10827 "fmov{.s|} @(%0,%1),%2")
10829 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
10830 (define_insn "sp_switch_1"
10831 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
10832 UNSPECV_SP_SWITCH_B))]
10835 return "mov.l r0,@-r15" "\n"
10836 " mov.l %0,r0" "\n"
10837 " mov.l @r0,r0" "\n"
10838 " mov.l r15,@-r0" "\n"
10841 [(set_attr "length" "10")])
10843 ;; Switch back to the original stack for interrupt functions with the
10844 ;; sp_switch attribute.
10845 (define_insn "sp_switch_2"
10846 [(unspec_volatile [(const_int 0)]
10847 UNSPECV_SP_SWITCH_E)]
10850 return "mov.l @r15,r15" "\n"
10853 [(set_attr "length" "4")])
10856 ;; In user mode, the "pref" instruction will raise a RADDERR exception
10857 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
10858 ;; implementation of __builtin_prefetch for VxWorks RTPs.
10859 (define_expand "prefetch"
10860 [(prefetch (match_operand 0 "address_operand" "")
10861 (match_operand:SI 1 "const_int_operand" "")
10862 (match_operand:SI 2 "const_int_operand" ""))]
10863 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP")
10865 (define_insn "*prefetch"
10866 [(prefetch (match_operand:SI 0 "register_operand" "r")
10867 (match_operand:SI 1 "const_int_operand" "n")
10868 (match_operand:SI 2 "const_int_operand" "n"))]
10869 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP"
10871 [(set_attr "type" "other")])
10873 ;; -------------------------------------------------------------------------
10874 ;; Stack Protector Patterns
10875 ;; -------------------------------------------------------------------------
10877 (define_expand "stack_protect_set"
10878 [(set (match_operand 0 "memory_operand" "")
10879 (match_operand 1 "memory_operand" ""))]
10882 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
10886 (define_insn "stack_protect_set_si"
10887 [(set (match_operand:SI 0 "memory_operand" "=m")
10888 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10889 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10892 return "mov.l %1,%2" "\n"
10893 " mov.l %2,%0" "\n"
10896 [(set_attr "type" "other")
10897 (set_attr "length" "6")])
10899 (define_expand "stack_protect_test"
10900 [(match_operand 0 "memory_operand" "")
10901 (match_operand 1 "memory_operand" "")
10902 (match_operand 2 "" "")]
10905 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
10906 emit_jump_insn (gen_branch_true (operands[2]));
10910 (define_insn "stack_protect_test_si"
10911 [(set (reg:SI T_REG)
10912 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
10913 (match_operand:SI 1 "memory_operand" "m")]
10915 (set (match_scratch:SI 2 "=&r") (const_int 0))
10916 (set (match_scratch:SI 3 "=&r") (const_int 0))]
10919 return "mov.l %0,%2" "\n"
10920 " mov.l %1,%3" "\n"
10921 " cmp/eq %2,%3" "\n"
10925 [(set_attr "type" "other")
10926 (set_attr "length" "10")])
10928 ;; -------------------------------------------------------------------------
10929 ;; Atomic operations
10930 ;; -------------------------------------------------------------------------
10932 (include "sync.md")