1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
120 /* Define a default value for REVERSIBLE_CC_MODE.
121 We can never assume that a condition code mode is safe to reverse unless
122 the md tells us so. */
123 #ifndef REVERSIBLE_CC_MODE
124 #define REVERSIBLE_CC_MODE(MODE) 0
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid
;
135 static int max_uid_cuid
;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno
;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx
*reg_last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx
*reg_last_set
;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set
;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid
;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn
;
172 /* This is an insn that belongs before subst_insn, but is not currently
173 on the insn chain. */
175 static rtx subst_prev_insn
;
177 /* This is the lowest CUID that `subst' is currently dealing with.
178 get_last_value will not return a value if the register was set at or
179 after this CUID. If not for this mechanism, we could get confused if
180 I2 or I1 in try_combine were an insn that used the old value of a register
181 to obtain a new value. In that case, we might erroneously get the
182 new value of the register when we wanted the old one. */
184 static int subst_low_cuid
;
186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
187 must consider all these registers to be always live. */
189 static HARD_REG_SET newpat_used_regs
;
191 /* This is an insn to which a LOG_LINKS entry has been added. If this
192 insn is the earlier than I2 or I3, combine should rescan starting at
195 static rtx added_links_insn
;
197 /* Basic block number of the block in which we are performing combines. */
198 static int this_basic_block
;
200 /* A bitmap indicating which blocks had registers go dead at entry.
201 After combine, we'll need to re-do global life analysis with
202 those blocks as starting points. */
203 static sbitmap refresh_blocks
;
204 static int need_refresh
;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx
*reg_last_set_value
;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label
;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick
;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid
;
269 /* Incremented for each label. */
271 static int label_tick
;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode
;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies
;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid
;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode
*reg_last_set_mode
;
308 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
309 static char *reg_last_set_sign_bit_copies
;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r
; int i
;} old_contents
;
320 union {rtx
*r
; int *i
;} where
;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo
*previous_undos
;
346 static struct undobuf undobuf
;
348 /* Number of times the pseudo being substituted for
349 was found and replaced. */
351 static int n_occurrences
;
353 static void do_SUBST
PROTO((rtx
*, rtx
));
354 static void do_SUBST_INT
PROTO((int *, int));
355 static void init_reg_last_arrays
PROTO((void));
356 static void setup_incoming_promotions
PROTO((void));
357 static void set_nonzero_bits_and_sign_copies
PROTO((rtx
, rtx
, void *));
358 static int can_combine_p
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
359 static int sets_function_arg_p
PROTO((rtx
));
360 static int combinable_i3pat
PROTO((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
361 static int contains_muldiv
PROTO((rtx
));
362 static rtx try_combine
PROTO((rtx
, rtx
, rtx
));
363 static void undo_all
PROTO((void));
364 static rtx
*find_split_point
PROTO((rtx
*, rtx
));
365 static rtx subst
PROTO((rtx
, rtx
, rtx
, int, int));
366 static rtx combine_simplify_rtx
PROTO((rtx
, enum machine_mode
, int, int));
367 static rtx simplify_if_then_else
PROTO((rtx
));
368 static rtx simplify_set
PROTO((rtx
));
369 static rtx simplify_logical
PROTO((rtx
, int));
370 static rtx expand_compound_operation
PROTO((rtx
));
371 static rtx expand_field_assignment
PROTO((rtx
));
372 static rtx make_extraction
PROTO((enum machine_mode
, rtx
, int, rtx
, int,
374 static rtx extract_left_shift
PROTO((rtx
, int));
375 static rtx make_compound_operation
PROTO((rtx
, enum rtx_code
));
376 static int get_pos_from_mask
PROTO((unsigned HOST_WIDE_INT
, int *));
377 static rtx force_to_mode
PROTO((rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
, rtx
, int));
379 static rtx if_then_else_cond
PROTO((rtx
, rtx
*, rtx
*));
380 static rtx known_cond
PROTO((rtx
, enum rtx_code
, rtx
, rtx
));
381 static int rtx_equal_for_field_assignment_p
PROTO((rtx
, rtx
));
382 static rtx make_field_assignment
PROTO((rtx
));
383 static rtx apply_distributive_law
PROTO((rtx
));
384 static rtx simplify_and_const_int
PROTO((rtx
, enum machine_mode
, rtx
,
385 unsigned HOST_WIDE_INT
));
386 static unsigned HOST_WIDE_INT nonzero_bits
PROTO((rtx
, enum machine_mode
));
387 static int num_sign_bit_copies
PROTO((rtx
, enum machine_mode
));
388 static int merge_outer_ops
PROTO((enum rtx_code
*, HOST_WIDE_INT
*,
389 enum rtx_code
, HOST_WIDE_INT
,
390 enum machine_mode
, int *));
391 static rtx simplify_shift_const
PROTO((rtx
, enum rtx_code
, enum machine_mode
,
393 static int recog_for_combine
PROTO((rtx
*, rtx
, rtx
*));
394 static rtx gen_lowpart_for_combine
PROTO((enum machine_mode
, rtx
));
395 static rtx gen_rtx_combine
PVPROTO((enum rtx_code code
, enum machine_mode mode
,
397 static rtx gen_binary
PROTO((enum rtx_code
, enum machine_mode
,
399 static rtx gen_unary
PROTO((enum rtx_code
, enum machine_mode
,
400 enum machine_mode
, rtx
));
401 static enum rtx_code simplify_comparison
PROTO((enum rtx_code
, rtx
*, rtx
*));
402 static int reversible_comparison_p
PROTO((rtx
));
403 static void update_table_tick
PROTO((rtx
));
404 static void record_value_for_reg
PROTO((rtx
, rtx
, rtx
));
405 static void record_dead_and_set_regs_1
PROTO((rtx
, rtx
, void *));
406 static void record_dead_and_set_regs
PROTO((rtx
));
407 static int get_last_value_validate
PROTO((rtx
*, rtx
, int, int));
408 static rtx get_last_value
PROTO((rtx
));
409 static int use_crosses_set_p
PROTO((rtx
, int));
410 static void reg_dead_at_p_1
PROTO((rtx
, rtx
, void *));
411 static int reg_dead_at_p
PROTO((rtx
, rtx
));
412 static void move_deaths
PROTO((rtx
, rtx
, int, rtx
, rtx
*));
413 static int reg_bitfield_target_p
PROTO((rtx
, rtx
));
414 static void distribute_notes
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
415 static void distribute_links
PROTO((rtx
));
416 static void mark_used_regs_combine
PROTO((rtx
));
417 static int insn_cuid
PROTO((rtx
));
419 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
420 insn. The substitution can be undone by undo_all. If INTO is already
421 set to NEWVAL, do not record this change. Because computing NEWVAL might
422 also call SUBST, we have to compute it before we put anything into
426 do_SUBST(into
, newval
)
432 if (oldval
== newval
)
436 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
438 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
442 buf
->old_contents
.r
= oldval
;
445 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
448 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
450 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
451 for the value of a HOST_WIDE_INT value (including CONST_INT) is
455 do_SUBST_INT(into
, newval
)
461 if (oldval
== newval
)
465 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
467 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
471 buf
->old_contents
.i
= oldval
;
474 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
477 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
479 /* Main entry point for combiner. F is the first insn of the function.
480 NREGS is the first unused pseudo-reg number. */
483 combine_instructions (f
, nregs
)
487 register rtx insn
, next
;
492 register rtx links
, nextlinks
;
494 combine_attempts
= 0;
497 combine_successes
= 0;
498 undobuf
.undos
= undobuf
.previous_undos
= 0;
500 combine_max_regno
= nregs
;
502 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
503 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
504 reg_sign_bit_copies
= (char *) xcalloc (nregs
, sizeof (char));
506 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
507 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
508 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
509 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
510 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
511 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
513 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
514 reg_last_set_nonzero_bits
515 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
516 reg_last_set_sign_bit_copies
517 = (char *) xmalloc (nregs
* sizeof (char));
519 init_reg_last_arrays ();
521 init_recog_no_volatile ();
523 /* Compute maximum uid value so uid_cuid can be allocated. */
525 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
526 if (INSN_UID (insn
) > i
)
529 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
532 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
534 /* Don't use reg_nonzero_bits when computing it. This can cause problems
535 when, for example, we have j <<= 1 in a loop. */
537 nonzero_sign_valid
= 0;
539 /* Compute the mapping from uids to cuids.
540 Cuids are numbers assigned to insns, like uids,
541 except that cuids increase monotonically through the code.
543 Scan all SETs and see if we can deduce anything about what
544 bits are known to be zero for some registers and how many copies
545 of the sign bit are known to exist for those registers.
547 Also set any known values so that we can use it while searching
548 for what bits are known to be set. */
552 /* We need to initialize it here, because record_dead_and_set_regs may call
554 subst_prev_insn
= NULL_RTX
;
556 setup_incoming_promotions ();
558 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
559 sbitmap_zero (refresh_blocks
);
562 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
564 uid_cuid
[INSN_UID (insn
)] = ++i
;
568 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
570 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
572 record_dead_and_set_regs (insn
);
575 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
576 if (REG_NOTE_KIND (links
) == REG_INC
)
577 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
582 if (GET_CODE (insn
) == CODE_LABEL
)
586 nonzero_sign_valid
= 1;
588 /* Now scan all the insns in forward order. */
590 this_basic_block
= -1;
594 init_reg_last_arrays ();
595 setup_incoming_promotions ();
597 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
601 /* If INSN starts a new basic block, update our basic block number. */
602 if (this_basic_block
+ 1 < n_basic_blocks
603 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
606 if (GET_CODE (insn
) == CODE_LABEL
)
609 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
)) != 0)
617 /* Try each sequence of three linked insns ending with this one. */
619 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
620 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
621 nextlinks
= XEXP (nextlinks
, 1))
622 if ((next
= try_combine (insn
, XEXP (links
, 0),
623 XEXP (nextlinks
, 0))) != 0)
627 /* Try to combine a jump insn that uses CC0
628 with a preceding insn that sets CC0, and maybe with its
629 logical predecessor as well.
630 This is how we make decrement-and-branch insns.
631 We need this special code because data flow connections
632 via CC0 do not get entered in LOG_LINKS. */
634 if (GET_CODE (insn
) == JUMP_INSN
635 && (prev
= prev_nonnote_insn (insn
)) != 0
636 && GET_CODE (prev
) == INSN
637 && sets_cc0_p (PATTERN (prev
)))
639 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
642 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
643 nextlinks
= XEXP (nextlinks
, 1))
644 if ((next
= try_combine (insn
, prev
,
645 XEXP (nextlinks
, 0))) != 0)
649 /* Do the same for an insn that explicitly references CC0. */
650 if (GET_CODE (insn
) == INSN
651 && (prev
= prev_nonnote_insn (insn
)) != 0
652 && GET_CODE (prev
) == INSN
653 && sets_cc0_p (PATTERN (prev
))
654 && GET_CODE (PATTERN (insn
)) == SET
655 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
657 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
660 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
661 nextlinks
= XEXP (nextlinks
, 1))
662 if ((next
= try_combine (insn
, prev
,
663 XEXP (nextlinks
, 0))) != 0)
667 /* Finally, see if any of the insns that this insn links to
668 explicitly references CC0. If so, try this insn, that insn,
669 and its predecessor if it sets CC0. */
670 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
671 if (GET_CODE (XEXP (links
, 0)) == INSN
672 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
673 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
674 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
675 && GET_CODE (prev
) == INSN
676 && sets_cc0_p (PATTERN (prev
))
677 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
681 /* Try combining an insn with two different insns whose results it
683 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
684 for (nextlinks
= XEXP (links
, 1); nextlinks
;
685 nextlinks
= XEXP (nextlinks
, 1))
686 if ((next
= try_combine (insn
, XEXP (links
, 0),
687 XEXP (nextlinks
, 0))) != 0)
690 if (GET_CODE (insn
) != NOTE
)
691 record_dead_and_set_regs (insn
);
700 compute_bb_for_insn (get_max_uid ());
701 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
706 sbitmap_free (refresh_blocks
);
707 free (reg_nonzero_bits
);
708 free (reg_sign_bit_copies
);
709 free (reg_last_death
);
711 free (reg_last_set_value
);
712 free (reg_last_set_table_tick
);
713 free (reg_last_set_label
);
714 free (reg_last_set_invalid
);
715 free (reg_last_set_mode
);
716 free (reg_last_set_nonzero_bits
);
717 free (reg_last_set_sign_bit_copies
);
720 total_attempts
+= combine_attempts
;
721 total_merges
+= combine_merges
;
722 total_extras
+= combine_extras
;
723 total_successes
+= combine_successes
;
725 nonzero_sign_valid
= 0;
727 /* Make recognizer allow volatile MEMs again. */
731 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
734 init_reg_last_arrays ()
736 int nregs
= combine_max_regno
;
738 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
739 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
740 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
741 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
742 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
743 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
744 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
745 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
746 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
749 /* Set up any promoted values for incoming argument registers. */
752 setup_incoming_promotions ()
754 #ifdef PROMOTE_FUNCTION_ARGS
757 enum machine_mode mode
;
759 rtx first
= get_insns ();
761 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
762 if (FUNCTION_ARG_REGNO_P (regno
)
763 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
766 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
769 gen_rtx_CLOBBER (mode
, const0_rtx
)));
774 /* Called via note_stores. If X is a pseudo that is narrower than
775 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
777 If we are setting only a portion of X and we can't figure out what
778 portion, assume all bits will be used since we don't know what will
781 Similarly, set how many bits of X are known to be copies of the sign bit
782 at all locations in the function. This is the smallest number implied
786 set_nonzero_bits_and_sign_copies (x
, set
, data
)
789 void *data ATTRIBUTE_UNUSED
;
793 if (GET_CODE (x
) == REG
794 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
795 /* If this register is undefined at the start of the file, we can't
796 say what its contents were. */
797 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
798 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
800 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
802 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
803 reg_sign_bit_copies
[REGNO (x
)] = 1;
807 /* If this is a complex assignment, see if we can convert it into a
808 simple assignment. */
809 set
= expand_field_assignment (set
);
811 /* If this is a simple assignment, or we have a paradoxical SUBREG,
812 set what we know about X. */
814 if (SET_DEST (set
) == x
815 || (GET_CODE (SET_DEST (set
)) == SUBREG
816 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
817 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
818 && SUBREG_REG (SET_DEST (set
)) == x
))
820 rtx src
= SET_SRC (set
);
822 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
823 /* If X is narrower than a word and SRC is a non-negative
824 constant that would appear negative in the mode of X,
825 sign-extend it for use in reg_nonzero_bits because some
826 machines (maybe most) will actually do the sign-extension
827 and this is the conservative approach.
829 ??? For 2.5, try to tighten up the MD files in this regard
830 instead of this kludge. */
832 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
833 && GET_CODE (src
) == CONST_INT
835 && 0 != (INTVAL (src
)
837 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
838 src
= GEN_INT (INTVAL (src
)
839 | ((HOST_WIDE_INT
) (-1)
840 << GET_MODE_BITSIZE (GET_MODE (x
))));
843 reg_nonzero_bits
[REGNO (x
)]
844 |= nonzero_bits (src
, nonzero_bits_mode
);
845 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
846 if (reg_sign_bit_copies
[REGNO (x
)] == 0
847 || reg_sign_bit_copies
[REGNO (x
)] > num
)
848 reg_sign_bit_copies
[REGNO (x
)] = num
;
852 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
853 reg_sign_bit_copies
[REGNO (x
)] = 1;
858 /* See if INSN can be combined into I3. PRED and SUCC are optionally
859 insns that were previously combined into I3 or that will be combined
860 into the merger of INSN and I3.
862 Return 0 if the combination is not allowed for any reason.
864 If the combination is allowed, *PDEST will be set to the single
865 destination of INSN and *PSRC to the single source, and this function
869 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
872 rtx pred ATTRIBUTE_UNUSED
;
877 rtx set
= 0, src
, dest
;
882 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
883 && next_active_insn (succ
) == i3
)
884 : next_active_insn (insn
) == i3
);
886 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
887 or a PARALLEL consisting of such a SET and CLOBBERs.
889 If INSN has CLOBBER parallel parts, ignore them for our processing.
890 By definition, these happen during the execution of the insn. When it
891 is merged with another insn, all bets are off. If they are, in fact,
892 needed and aren't also supplied in I3, they may be added by
893 recog_for_combine. Otherwise, it won't match.
895 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
898 Get the source and destination of INSN. If more than one, can't
901 if (GET_CODE (PATTERN (insn
)) == SET
)
902 set
= PATTERN (insn
);
903 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
904 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
906 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
908 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
910 switch (GET_CODE (elt
))
912 /* This is important to combine floating point insns
915 /* Combining an isolated USE doesn't make sense.
916 We depend here on combinable_i3_pat to reject them. */
917 /* The code below this loop only verifies that the inputs of
918 the SET in INSN do not change. We call reg_set_between_p
919 to verify that the REG in the USE does not change betweeen
921 If the USE in INSN was for a pseudo register, the matching
922 insn pattern will likely match any register; combining this
923 with any other USE would only be safe if we knew that the
924 used registers have identical values, or if there was
925 something to tell them apart, e.g. different modes. For
926 now, we forgo such compilcated tests and simply disallow
927 combining of USES of pseudo registers with any other USE. */
928 if (GET_CODE (XEXP (elt
, 0)) == REG
929 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
931 rtx i3pat
= PATTERN (i3
);
932 int i
= XVECLEN (i3pat
, 0) - 1;
933 int regno
= REGNO (XEXP (elt
, 0));
936 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
937 if (GET_CODE (i3elt
) == USE
938 && GET_CODE (XEXP (i3elt
, 0)) == REG
939 && (REGNO (XEXP (i3elt
, 0)) == regno
940 ? reg_set_between_p (XEXP (elt
, 0),
941 PREV_INSN (insn
), i3
)
942 : regno
>= FIRST_PSEUDO_REGISTER
))
949 /* We can ignore CLOBBERs. */
954 /* Ignore SETs whose result isn't used but not those that
955 have side-effects. */
956 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
957 && ! side_effects_p (elt
))
960 /* If we have already found a SET, this is a second one and
961 so we cannot combine with this insn. */
969 /* Anything else means we can't combine. */
975 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
976 so don't do anything with it. */
977 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
986 set
= expand_field_assignment (set
);
987 src
= SET_SRC (set
), dest
= SET_DEST (set
);
989 /* Don't eliminate a store in the stack pointer. */
990 if (dest
== stack_pointer_rtx
991 /* If we couldn't eliminate a field assignment, we can't combine. */
992 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
993 /* Don't combine with an insn that sets a register to itself if it has
994 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
995 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
996 /* Can't merge a function call. */
997 || GET_CODE (src
) == CALL
998 /* Don't eliminate a function call argument. */
999 || (GET_CODE (i3
) == CALL_INSN
1000 && (find_reg_fusage (i3
, USE
, dest
)
1001 || (GET_CODE (dest
) == REG
1002 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1003 && global_regs
[REGNO (dest
)])))
1004 /* Don't substitute into an incremented register. */
1005 || FIND_REG_INC_NOTE (i3
, dest
)
1006 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1008 /* Don't combine the end of a libcall into anything. */
1009 /* ??? This gives worse code, and appears to be unnecessary, since no
1010 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1011 use REG_RETVAL notes for noconflict blocks, but other code here
1012 makes sure that those insns don't disappear. */
1013 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1015 /* Make sure that DEST is not used after SUCC but before I3. */
1016 || (succ
&& ! all_adjacent
1017 && reg_used_between_p (dest
, succ
, i3
))
1018 /* Make sure that the value that is to be substituted for the register
1019 does not use any registers whose values alter in between. However,
1020 If the insns are adjacent, a use can't cross a set even though we
1021 think it might (this can happen for a sequence of insns each setting
1022 the same destination; reg_last_set of that register might point to
1023 a NOTE). If INSN has a REG_EQUIV note, the register is always
1024 equivalent to the memory so the substitution is valid even if there
1025 are intervening stores. Also, don't move a volatile asm or
1026 UNSPEC_VOLATILE across any other insns. */
1028 && (((GET_CODE (src
) != MEM
1029 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1030 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1031 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1032 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1033 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1034 better register allocation by not doing the combine. */
1035 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1036 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1037 /* Don't combine across a CALL_INSN, because that would possibly
1038 change whether the life span of some REGs crosses calls or not,
1039 and it is a pain to update that information.
1040 Exception: if source is a constant, moving it later can't hurt.
1041 Accept that special case, because it helps -fforce-addr a lot. */
1042 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1045 /* DEST must either be a REG or CC0. */
1046 if (GET_CODE (dest
) == REG
)
1048 /* If register alignment is being enforced for multi-word items in all
1049 cases except for parameters, it is possible to have a register copy
1050 insn referencing a hard register that is not allowed to contain the
1051 mode being copied and which would not be valid as an operand of most
1052 insns. Eliminate this problem by not combining with such an insn.
1054 Also, on some machines we don't want to extend the life of a hard
1057 This is the same test done in can_combine except that we don't test
1058 if SRC is a CALL operation to permit a hard register with
1059 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1062 if (GET_CODE (src
) == REG
1063 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1064 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1065 /* Don't extend the life of a hard register unless it is
1066 user variable (if we have few registers) or it can't
1067 fit into the desired register (meaning something special
1069 Also avoid substituting a return register into I3, because
1070 reload can't handle a conflict with constraints of other
1072 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1073 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
1074 || (SMALL_REGISTER_CLASSES
1075 && ((! all_adjacent
&& ! REG_USERVAR_P (src
))
1076 || (FUNCTION_VALUE_REGNO_P (REGNO (src
))
1077 && ! REG_USERVAR_P (src
))))))))
1080 else if (GET_CODE (dest
) != CC0
)
1083 /* Don't substitute for a register intended as a clobberable operand.
1084 Similarly, don't substitute an expression containing a register that
1085 will be clobbered in I3. */
1086 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1087 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1088 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1089 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1091 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1094 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1095 or not), reject, unless nothing volatile comes between it and I3 */
1097 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1099 /* Make sure succ doesn't contain a volatile reference. */
1100 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1103 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1104 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1105 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1109 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1110 to be an explicit register variable, and was chosen for a reason. */
1112 if (GET_CODE (src
) == ASM_OPERANDS
1113 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1116 /* If there are any volatile insns between INSN and I3, reject, because
1117 they might affect machine state. */
1119 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1120 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1121 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1124 /* If INSN or I2 contains an autoincrement or autodecrement,
1125 make sure that register is not used between there and I3,
1126 and not already used in I3 either.
1127 Also insist that I3 not be a jump; if it were one
1128 and the incremented register were spilled, we would lose. */
1131 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1132 if (REG_NOTE_KIND (link
) == REG_INC
1133 && (GET_CODE (i3
) == JUMP_INSN
1134 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1135 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1140 /* Don't combine an insn that follows a CC0-setting insn.
1141 An insn that uses CC0 must not be separated from the one that sets it.
1142 We do, however, allow I2 to follow a CC0-setting insn if that insn
1143 is passed as I1; in that case it will be deleted also.
1144 We also allow combining in this case if all the insns are adjacent
1145 because that would leave the two CC0 insns adjacent as well.
1146 It would be more logical to test whether CC0 occurs inside I1 or I2,
1147 but that would be much slower, and this ought to be equivalent. */
1149 p
= prev_nonnote_insn (insn
);
1150 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1155 /* If we get here, we have passed all the tests and the combination is
1164 /* Check if PAT is an insn - or a part of it - used to set up an
1165 argument for a function in a hard register. */
1168 sets_function_arg_p (pat
)
1174 switch (GET_CODE (pat
))
1177 return sets_function_arg_p (PATTERN (pat
));
1180 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1181 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1187 inner_dest
= SET_DEST (pat
);
1188 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1189 || GET_CODE (inner_dest
) == SUBREG
1190 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1191 inner_dest
= XEXP (inner_dest
, 0);
1193 return (GET_CODE (inner_dest
) == REG
1194 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1195 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1204 /* LOC is the location within I3 that contains its pattern or the component
1205 of a PARALLEL of the pattern. We validate that it is valid for combining.
1207 One problem is if I3 modifies its output, as opposed to replacing it
1208 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1209 so would produce an insn that is not equivalent to the original insns.
1213 (set (reg:DI 101) (reg:DI 100))
1214 (set (subreg:SI (reg:DI 101) 0) <foo>)
1216 This is NOT equivalent to:
1218 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1219 (set (reg:DI 101) (reg:DI 100))])
1221 Not only does this modify 100 (in which case it might still be valid
1222 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1224 We can also run into a problem if I2 sets a register that I1
1225 uses and I1 gets directly substituted into I3 (not via I2). In that
1226 case, we would be getting the wrong value of I2DEST into I3, so we
1227 must reject the combination. This case occurs when I2 and I1 both
1228 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1229 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1230 of a SET must prevent combination from occurring.
1232 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1233 if the destination of a SET is a hard register that isn't a user
1236 Before doing the above check, we first try to expand a field assignment
1237 into a set of logical operations.
1239 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1240 we place a register that is both set and used within I3. If more than one
1241 such register is detected, we fail.
1243 Return 1 if the combination is valid, zero otherwise. */
1246 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1252 rtx
*pi3dest_killed
;
1256 if (GET_CODE (x
) == SET
)
1258 rtx set
= expand_field_assignment (x
);
1259 rtx dest
= SET_DEST (set
);
1260 rtx src
= SET_SRC (set
);
1261 rtx inner_dest
= dest
;
1264 rtx inner_src
= src
;
1269 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1270 || GET_CODE (inner_dest
) == SUBREG
1271 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1272 inner_dest
= XEXP (inner_dest
, 0);
1274 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1277 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1278 || GET_CODE (inner_src
) == SUBREG
1279 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1280 inner_src
= XEXP (inner_src
, 0);
1282 /* If it is better that two different modes keep two different pseudos,
1283 avoid combining them. This avoids producing the following pattern
1285 (set (subreg:SI (reg/v:QI 21) 0)
1286 (lshiftrt:SI (reg/v:SI 20)
1288 If that were made, reload could not handle the pair of
1289 reg 20/21, since it would try to get any GENERAL_REGS
1290 but some of them don't handle QImode. */
1292 if (rtx_equal_p (inner_src
, i2dest
)
1293 && GET_CODE (inner_dest
) == REG
1294 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1298 /* Check for the case where I3 modifies its output, as
1300 if ((inner_dest
!= dest
1301 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1302 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1304 /* This is the same test done in can_combine_p except that we
1305 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1306 CALL operation. Moreover, we can't test all_adjacent; we don't
1307 have to, since this instruction will stay in place, thus we are
1308 not considering increasing the lifetime of INNER_DEST.
1310 Also, if this insn sets a function argument, combining it with
1311 something that might need a spill could clobber a previous
1312 function argument; the all_adjacent test in can_combine_p also
1313 checks this; here, we do a more specific test for this case. */
1315 || (GET_CODE (inner_dest
) == REG
1316 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1317 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1318 GET_MODE (inner_dest
))
1319 || (SMALL_REGISTER_CLASSES
&& GET_CODE (src
) != CALL
1320 && ! REG_USERVAR_P (inner_dest
)
1321 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest
))
1322 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest
))
1324 && sets_function_arg_p (prev_nonnote_insn (i3
)))))))
1325 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1328 /* If DEST is used in I3, it is being killed in this insn,
1329 so record that for later.
1330 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1331 STACK_POINTER_REGNUM, since these are always considered to be
1332 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1333 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1334 && reg_referenced_p (dest
, PATTERN (i3
))
1335 && REGNO (dest
) != FRAME_POINTER_REGNUM
1336 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1337 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1339 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1340 && (REGNO (dest
) != ARG_POINTER_REGNUM
1341 || ! fixed_regs
[REGNO (dest
)])
1343 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1345 if (*pi3dest_killed
)
1348 *pi3dest_killed
= dest
;
1352 else if (GET_CODE (x
) == PARALLEL
)
1356 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1357 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1358 i1_not_in_src
, pi3dest_killed
))
1365 /* Return 1 if X is an arithmetic expression that contains a multiplication
1366 and division. We don't count multiplications by powers of two here. */
1372 switch (GET_CODE (x
))
1374 case MOD
: case DIV
: case UMOD
: case UDIV
:
1378 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1379 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1381 switch (GET_RTX_CLASS (GET_CODE (x
)))
1383 case 'c': case '<': case '2':
1384 return contains_muldiv (XEXP (x
, 0))
1385 || contains_muldiv (XEXP (x
, 1));
1388 return contains_muldiv (XEXP (x
, 0));
1396 /* Try to combine the insns I1 and I2 into I3.
1397 Here I1 and I2 appear earlier than I3.
1398 I1 can be zero; then we combine just I2 into I3.
1400 It we are combining three insns and the resulting insn is not recognized,
1401 try splitting it into two insns. If that happens, I2 and I3 are retained
1402 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1405 Return 0 if the combination does not work. Then nothing is changed.
1406 If we did the combination, return the insn at which combine should
1410 try_combine (i3
, i2
, i1
)
1411 register rtx i3
, i2
, i1
;
1413 /* New patterns for I3 and I3, respectively. */
1414 rtx newpat
, newi2pat
= 0;
1415 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1416 int added_sets_1
, added_sets_2
;
1417 /* Total number of SETs to put into I3. */
1419 /* Nonzero is I2's body now appears in I3. */
1421 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1422 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1423 /* Contains I3 if the destination of I3 is used in its source, which means
1424 that the old life of I3 is being killed. If that usage is placed into
1425 I2 and not in I3, a REG_DEAD note must be made. */
1426 rtx i3dest_killed
= 0;
1427 /* SET_DEST and SET_SRC of I2 and I1. */
1428 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1429 /* PATTERN (I2), or a copy of it in certain cases. */
1431 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1432 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1433 int i1_feeds_i3
= 0;
1434 /* Notes that must be added to REG_NOTES in I3 and I2. */
1435 rtx new_i3_notes
, new_i2_notes
;
1436 /* Notes that we substituted I3 into I2 instead of the normal case. */
1437 int i3_subst_into_i2
= 0;
1438 /* Notes that I1, I2 or I3 is a MULT operation. */
1446 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1447 This can occur when flow deletes an insn that it has merged into an
1448 auto-increment address. We also can't do anything if I3 has a
1449 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1452 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1453 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1454 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1456 /* ??? This gives worse code, and appears to be unnecessary, since no
1457 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1458 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1465 undobuf
.undos
= undobuf
.previous_undos
= 0;
1466 undobuf
.other_insn
= 0;
1468 /* Save the current high-water-mark so we can free storage if we didn't
1469 accept this combination. */
1470 undobuf
.storage
= (char *) oballoc (0);
1472 /* Reset the hard register usage information. */
1473 CLEAR_HARD_REG_SET (newpat_used_regs
);
1475 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1476 code below, set I1 to be the earlier of the two insns. */
1477 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1478 temp
= i1
, i1
= i2
, i2
= temp
;
1480 added_links_insn
= 0;
1482 /* First check for one important special-case that the code below will
1483 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1484 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1485 we may be able to replace that destination with the destination of I3.
1486 This occurs in the common code where we compute both a quotient and
1487 remainder into a structure, in which case we want to do the computation
1488 directly into the structure to avoid register-register copies.
1490 We make very conservative checks below and only try to handle the
1491 most common cases of this. For example, we only handle the case
1492 where I2 and I3 are adjacent to avoid making difficult register
1495 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1496 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1497 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1498 && (! SMALL_REGISTER_CLASSES
1499 || (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1500 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1501 || REG_USERVAR_P (SET_DEST (PATTERN (i3
)))))
1502 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1503 && GET_CODE (PATTERN (i2
)) == PARALLEL
1504 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1505 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1506 below would need to check what is inside (and reg_overlap_mentioned_p
1507 doesn't support those codes anyway). Don't allow those destinations;
1508 the resulting insn isn't likely to be recognized anyway. */
1509 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1510 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1511 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1512 SET_DEST (PATTERN (i3
)))
1513 && next_real_insn (i2
) == i3
)
1515 rtx p2
= PATTERN (i2
);
1517 /* Make sure that the destination of I3,
1518 which we are going to substitute into one output of I2,
1519 is not used within another output of I2. We must avoid making this:
1520 (parallel [(set (mem (reg 69)) ...)
1521 (set (reg 69) ...)])
1522 which is not well-defined as to order of actions.
1523 (Besides, reload can't handle output reloads for this.)
1525 The problem can also happen if the dest of I3 is a memory ref,
1526 if another dest in I2 is an indirect memory ref. */
1527 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1528 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1529 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1530 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1531 SET_DEST (XVECEXP (p2
, 0, i
))))
1534 if (i
== XVECLEN (p2
, 0))
1535 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1536 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1541 subst_low_cuid
= INSN_CUID (i2
);
1543 added_sets_2
= added_sets_1
= 0;
1544 i2dest
= SET_SRC (PATTERN (i3
));
1546 /* Replace the dest in I2 with our dest and make the resulting
1547 insn the new pattern for I3. Then skip to where we
1548 validate the pattern. Everything was set up above. */
1549 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1550 SET_DEST (PATTERN (i3
)));
1553 i3_subst_into_i2
= 1;
1554 goto validate_replacement
;
1559 /* If we have no I1 and I2 looks like:
1560 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1562 make up a dummy I1 that is
1565 (set (reg:CC X) (compare:CC Y (const_int 0)))
1567 (We can ignore any trailing CLOBBERs.)
1569 This undoes a previous combination and allows us to match a branch-and-
1572 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1573 && XVECLEN (PATTERN (i2
), 0) >= 2
1574 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1575 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1577 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1578 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1579 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1580 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1581 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1582 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1584 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1585 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1590 /* We make I1 with the same INSN_UID as I2. This gives it
1591 the same INSN_CUID for value tracking. Our fake I1 will
1592 never appear in the insn stream so giving it the same INSN_UID
1593 as I2 will not cause a problem. */
1595 subst_prev_insn
= i1
1596 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1597 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1600 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1601 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1602 SET_DEST (PATTERN (i1
)));
1607 /* Verify that I2 and I1 are valid for combining. */
1608 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1609 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1615 /* Record whether I2DEST is used in I2SRC and similarly for the other
1616 cases. Knowing this will help in register status updating below. */
1617 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1618 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1619 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1621 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1623 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1625 /* Ensure that I3's pattern can be the destination of combines. */
1626 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1627 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1634 /* See if any of the insns is a MULT operation. Unless one is, we will
1635 reject a combination that is, since it must be slower. Be conservative
1637 if (GET_CODE (i2src
) == MULT
1638 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1639 || (GET_CODE (PATTERN (i3
)) == SET
1640 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1643 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1644 We used to do this EXCEPT in one case: I3 has a post-inc in an
1645 output operand. However, that exception can give rise to insns like
1647 which is a famous insn on the PDP-11 where the value of r3 used as the
1648 source was model-dependent. Avoid this sort of thing. */
1651 if (!(GET_CODE (PATTERN (i3
)) == SET
1652 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1653 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1654 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1655 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1656 /* It's not the exception. */
1659 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1660 if (REG_NOTE_KIND (link
) == REG_INC
1661 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1663 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1670 /* See if the SETs in I1 or I2 need to be kept around in the merged
1671 instruction: whenever the value set there is still needed past I3.
1672 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1674 For the SET in I1, we have two cases: If I1 and I2 independently
1675 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1676 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1677 in I1 needs to be kept around unless I1DEST dies or is set in either
1678 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1679 I1DEST. If so, we know I1 feeds into I2. */
1681 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1684 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1685 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1687 /* If the set in I2 needs to be kept around, we must make a copy of
1688 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1689 PATTERN (I2), we are only substituting for the original I1DEST, not into
1690 an already-substituted copy. This also prevents making self-referential
1691 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1694 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1695 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1699 i2pat
= copy_rtx (i2pat
);
1703 /* Substitute in the latest insn for the regs set by the earlier ones. */
1705 maxreg
= max_reg_num ();
1709 /* It is possible that the source of I2 or I1 may be performing an
1710 unneeded operation, such as a ZERO_EXTEND of something that is known
1711 to have the high part zero. Handle that case by letting subst look at
1712 the innermost one of them.
1714 Another way to do this would be to have a function that tries to
1715 simplify a single insn instead of merging two or more insns. We don't
1716 do this because of the potential of infinite loops and because
1717 of the potential extra memory required. However, doing it the way
1718 we are is a bit of a kludge and doesn't catch all cases.
1720 But only do this if -fexpensive-optimizations since it slows things down
1721 and doesn't usually win. */
1723 if (flag_expensive_optimizations
)
1725 /* Pass pc_rtx so no substitutions are done, just simplifications.
1726 The cases that we are interested in here do not involve the few
1727 cases were is_replaced is checked. */
1730 subst_low_cuid
= INSN_CUID (i1
);
1731 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1735 subst_low_cuid
= INSN_CUID (i2
);
1736 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1739 undobuf
.previous_undos
= undobuf
.undos
;
1743 /* Many machines that don't use CC0 have insns that can both perform an
1744 arithmetic operation and set the condition code. These operations will
1745 be represented as a PARALLEL with the first element of the vector
1746 being a COMPARE of an arithmetic operation with the constant zero.
1747 The second element of the vector will set some pseudo to the result
1748 of the same arithmetic operation. If we simplify the COMPARE, we won't
1749 match such a pattern and so will generate an extra insn. Here we test
1750 for this case, where both the comparison and the operation result are
1751 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1752 I2SRC. Later we will make the PARALLEL that contains I2. */
1754 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1755 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1756 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1757 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1759 #ifdef EXTRA_CC_MODES
1761 enum machine_mode compare_mode
;
1764 newpat
= PATTERN (i3
);
1765 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1769 #ifdef EXTRA_CC_MODES
1770 /* See if a COMPARE with the operand we substituted in should be done
1771 with the mode that is currently being used. If not, do the same
1772 processing we do in `subst' for a SET; namely, if the destination
1773 is used only once, try to replace it with a register of the proper
1774 mode and also replace the COMPARE. */
1775 if (undobuf
.other_insn
== 0
1776 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1777 &undobuf
.other_insn
))
1778 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1780 != GET_MODE (SET_DEST (newpat
))))
1782 int regno
= REGNO (SET_DEST (newpat
));
1783 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1785 if (regno
< FIRST_PSEUDO_REGISTER
1786 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1787 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1789 if (regno
>= FIRST_PSEUDO_REGISTER
)
1790 SUBST (regno_reg_rtx
[regno
], new_dest
);
1792 SUBST (SET_DEST (newpat
), new_dest
);
1793 SUBST (XEXP (*cc_use
, 0), new_dest
);
1794 SUBST (SET_SRC (newpat
),
1795 gen_rtx_combine (COMPARE
, compare_mode
,
1796 i2src
, const0_rtx
));
1799 undobuf
.other_insn
= 0;
1806 n_occurrences
= 0; /* `subst' counts here */
1808 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1809 need to make a unique copy of I2SRC each time we substitute it
1810 to avoid self-referential rtl. */
1812 subst_low_cuid
= INSN_CUID (i2
);
1813 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1814 ! i1_feeds_i3
&& i1dest_in_i1src
);
1815 undobuf
.previous_undos
= undobuf
.undos
;
1817 /* Record whether i2's body now appears within i3's body. */
1818 i2_is_used
= n_occurrences
;
1821 /* If we already got a failure, don't try to do more. Otherwise,
1822 try to substitute in I1 if we have it. */
1824 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1826 /* Before we can do this substitution, we must redo the test done
1827 above (see detailed comments there) that ensures that I1DEST
1828 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1830 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1838 subst_low_cuid
= INSN_CUID (i1
);
1839 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1840 undobuf
.previous_undos
= undobuf
.undos
;
1843 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1844 to count all the ways that I2SRC and I1SRC can be used. */
1845 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1846 && i2_is_used
+ added_sets_2
> 1)
1847 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1848 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1850 /* Fail if we tried to make a new register (we used to abort, but there's
1851 really no reason to). */
1852 || max_reg_num () != maxreg
1853 /* Fail if we couldn't do something and have a CLOBBER. */
1854 || GET_CODE (newpat
) == CLOBBER
1855 /* Fail if this new pattern is a MULT and we didn't have one before
1856 at the outer level. */
1857 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1864 /* If the actions of the earlier insns must be kept
1865 in addition to substituting them into the latest one,
1866 we must make a new PARALLEL for the latest insn
1867 to hold additional the SETs. */
1869 if (added_sets_1
|| added_sets_2
)
1873 if (GET_CODE (newpat
) == PARALLEL
)
1875 rtvec old
= XVEC (newpat
, 0);
1876 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1877 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1878 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
1879 sizeof (old
->elem
[0]) * old
->num_elem
);
1884 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1885 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1886 XVECEXP (newpat
, 0, 0) = old
;
1890 XVECEXP (newpat
, 0, --total_sets
)
1891 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1892 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1896 /* If there is no I1, use I2's body as is. We used to also not do
1897 the subst call below if I2 was substituted into I3,
1898 but that could lose a simplification. */
1900 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1902 /* See comment where i2pat is assigned. */
1903 XVECEXP (newpat
, 0, --total_sets
)
1904 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1908 /* We come here when we are replacing a destination in I2 with the
1909 destination of I3. */
1910 validate_replacement
:
1912 /* Note which hard regs this insn has as inputs. */
1913 mark_used_regs_combine (newpat
);
1915 /* Is the result of combination a valid instruction? */
1916 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1918 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1919 the second SET's destination is a register that is unused. In that case,
1920 we just need the first SET. This can occur when simplifying a divmod
1921 insn. We *must* test for this case here because the code below that
1922 splits two independent SETs doesn't handle this case correctly when it
1923 updates the register status. Also check the case where the first
1924 SET's destination is unused. That would not cause incorrect code, but
1925 does cause an unneeded insn to remain. */
1927 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1928 && XVECLEN (newpat
, 0) == 2
1929 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1930 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1931 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1932 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1933 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1934 && asm_noperands (newpat
) < 0)
1936 newpat
= XVECEXP (newpat
, 0, 0);
1937 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1940 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1941 && XVECLEN (newpat
, 0) == 2
1942 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1943 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1944 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1945 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1946 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1947 && asm_noperands (newpat
) < 0)
1949 newpat
= XVECEXP (newpat
, 0, 1);
1950 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1953 /* If we were combining three insns and the result is a simple SET
1954 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1955 insns. There are two ways to do this. It can be split using a
1956 machine-specific method (like when you have an addition of a large
1957 constant) or by combine in the function find_split_point. */
1959 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1960 && asm_noperands (newpat
) < 0)
1962 rtx m_split
, *split
;
1963 rtx ni2dest
= i2dest
;
1965 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1966 use I2DEST as a scratch register will help. In the latter case,
1967 convert I2DEST to the mode of the source of NEWPAT if we can. */
1969 m_split
= split_insns (newpat
, i3
);
1971 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1972 inputs of NEWPAT. */
1974 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1975 possible to try that as a scratch reg. This would require adding
1976 more code to make it work though. */
1978 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
1980 /* If I2DEST is a hard register or the only use of a pseudo,
1981 we can change its mode. */
1982 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1983 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1984 && GET_CODE (i2dest
) == REG
1985 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1986 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
1987 && ! REG_USERVAR_P (i2dest
))))
1988 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
1991 m_split
= split_insns (gen_rtx_PARALLEL
1993 gen_rtvec (2, newpat
,
1994 gen_rtx_CLOBBER (VOIDmode
,
1999 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2000 && XVECLEN (m_split
, 0) == 2
2001 && (next_real_insn (i2
) == i3
2002 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2006 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2007 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2009 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2010 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2012 /* In case we changed the mode of I2DEST, replace it in the
2013 pseudo-register table here. We can't do it above in case this
2014 code doesn't get executed and we do a split the other way. */
2016 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2017 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2019 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2021 /* If I2 or I3 has multiple SETs, we won't know how to track
2022 register status, so don't use these insns. If I2's destination
2023 is used between I2 and I3, we also can't use these insns. */
2025 if (i2_code_number
>= 0 && i2set
&& i3set
2026 && (next_real_insn (i2
) == i3
2027 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2028 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2030 if (insn_code_number
>= 0)
2033 /* It is possible that both insns now set the destination of I3.
2034 If so, we must show an extra use of it. */
2036 if (insn_code_number
>= 0)
2038 rtx new_i3_dest
= SET_DEST (i3set
);
2039 rtx new_i2_dest
= SET_DEST (i2set
);
2041 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2042 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2043 || GET_CODE (new_i3_dest
) == SUBREG
)
2044 new_i3_dest
= XEXP (new_i3_dest
, 0);
2046 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2047 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2048 || GET_CODE (new_i2_dest
) == SUBREG
)
2049 new_i2_dest
= XEXP (new_i2_dest
, 0);
2051 if (GET_CODE (new_i3_dest
) == REG
2052 && GET_CODE (new_i2_dest
) == REG
2053 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2054 REG_N_SETS (REGNO (new_i2_dest
))++;
2058 /* If we can split it and use I2DEST, go ahead and see if that
2059 helps things be recognized. Verify that none of the registers
2060 are set between I2 and I3. */
2061 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2063 && GET_CODE (i2dest
) == REG
2065 /* We need I2DEST in the proper mode. If it is a hard register
2066 or the only use of a pseudo, we can change its mode. */
2067 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2068 || GET_MODE (*split
) == VOIDmode
2069 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2070 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2071 && ! REG_USERVAR_P (i2dest
)))
2072 && (next_real_insn (i2
) == i3
2073 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2074 /* We can't overwrite I2DEST if its value is still used by
2076 && ! reg_referenced_p (i2dest
, newpat
))
2078 rtx newdest
= i2dest
;
2079 enum rtx_code split_code
= GET_CODE (*split
);
2080 enum machine_mode split_mode
= GET_MODE (*split
);
2082 /* Get NEWDEST as a register in the proper mode. We have already
2083 validated that we can do this. */
2084 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2086 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2088 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2089 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2092 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2093 an ASHIFT. This can occur if it was inside a PLUS and hence
2094 appeared to be a memory address. This is a kludge. */
2095 if (split_code
== MULT
2096 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2097 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2099 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2100 XEXP (*split
, 0), GEN_INT (i
)));
2101 /* Update split_code because we may not have a multiply
2103 split_code
= GET_CODE (*split
);
2106 #ifdef INSN_SCHEDULING
2107 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2108 be written as a ZERO_EXTEND. */
2109 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2110 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2114 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2115 SUBST (*split
, newdest
);
2116 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2118 /* If the split point was a MULT and we didn't have one before,
2119 don't use one now. */
2120 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2121 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2125 /* Check for a case where we loaded from memory in a narrow mode and
2126 then sign extended it, but we need both registers. In that case,
2127 we have a PARALLEL with both loads from the same memory location.
2128 We can split this into a load from memory followed by a register-register
2129 copy. This saves at least one insn, more if register allocation can
2132 We cannot do this if the destination of the second assignment is
2133 a register that we have already assumed is zero-extended. Similarly
2134 for a SUBREG of such a register. */
2136 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2137 && GET_CODE (newpat
) == PARALLEL
2138 && XVECLEN (newpat
, 0) == 2
2139 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2140 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2141 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2142 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2143 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2144 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2146 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2147 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2148 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2149 (GET_CODE (temp
) == REG
2150 && reg_nonzero_bits
[REGNO (temp
)] != 0
2151 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2152 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2153 && (reg_nonzero_bits
[REGNO (temp
)]
2154 != GET_MODE_MASK (word_mode
))))
2155 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2156 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2157 (GET_CODE (temp
) == REG
2158 && reg_nonzero_bits
[REGNO (temp
)] != 0
2159 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2160 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2161 && (reg_nonzero_bits
[REGNO (temp
)]
2162 != GET_MODE_MASK (word_mode
)))))
2163 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2164 SET_SRC (XVECEXP (newpat
, 0, 1)))
2165 && ! find_reg_note (i3
, REG_UNUSED
,
2166 SET_DEST (XVECEXP (newpat
, 0, 0))))
2170 newi2pat
= XVECEXP (newpat
, 0, 0);
2171 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2172 newpat
= XVECEXP (newpat
, 0, 1);
2173 SUBST (SET_SRC (newpat
),
2174 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2175 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2177 if (i2_code_number
>= 0)
2178 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2180 if (insn_code_number
>= 0)
2185 /* If we will be able to accept this, we have made a change to the
2186 destination of I3. This can invalidate a LOG_LINKS pointing
2187 to I3. No other part of combine.c makes such a transformation.
2189 The new I3 will have a destination that was previously the
2190 destination of I1 or I2 and which was used in i2 or I3. Call
2191 distribute_links to make a LOG_LINK from the next use of
2192 that destination. */
2194 PATTERN (i3
) = newpat
;
2195 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2197 /* I3 now uses what used to be its destination and which is
2198 now I2's destination. That means we need a LOG_LINK from
2199 I3 to I2. But we used to have one, so we still will.
2201 However, some later insn might be using I2's dest and have
2202 a LOG_LINK pointing at I3. We must remove this link.
2203 The simplest way to remove the link is to point it at I1,
2204 which we know will be a NOTE. */
2206 for (insn
= NEXT_INSN (i3
);
2207 insn
&& (this_basic_block
== n_basic_blocks
- 1
2208 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2209 insn
= NEXT_INSN (insn
))
2211 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
2212 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2214 for (link
= LOG_LINKS (insn
); link
;
2215 link
= XEXP (link
, 1))
2216 if (XEXP (link
, 0) == i3
)
2217 XEXP (link
, 0) = i1
;
2225 /* Similarly, check for a case where we have a PARALLEL of two independent
2226 SETs but we started with three insns. In this case, we can do the sets
2227 as two separate insns. This case occurs when some SET allows two
2228 other insns to combine, but the destination of that SET is still live. */
2230 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2231 && GET_CODE (newpat
) == PARALLEL
2232 && XVECLEN (newpat
, 0) == 2
2233 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2234 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2235 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2236 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2237 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2238 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2239 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2241 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2242 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2243 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2244 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2245 XVECEXP (newpat
, 0, 0))
2246 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2247 XVECEXP (newpat
, 0, 1))
2248 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2249 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2251 /* Normally, it doesn't matter which of the two is done first,
2252 but it does if one references cc0. In that case, it has to
2255 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2257 newi2pat
= XVECEXP (newpat
, 0, 0);
2258 newpat
= XVECEXP (newpat
, 0, 1);
2263 newi2pat
= XVECEXP (newpat
, 0, 1);
2264 newpat
= XVECEXP (newpat
, 0, 0);
2267 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2269 if (i2_code_number
>= 0)
2270 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2273 /* If it still isn't recognized, fail and change things back the way they
2275 if ((insn_code_number
< 0
2276 /* Is the result a reasonable ASM_OPERANDS? */
2277 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2283 /* If we had to change another insn, make sure it is valid also. */
2284 if (undobuf
.other_insn
)
2286 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2287 rtx new_other_notes
;
2290 CLEAR_HARD_REG_SET (newpat_used_regs
);
2292 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2295 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2301 PATTERN (undobuf
.other_insn
) = other_pat
;
2303 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2304 are still valid. Then add any non-duplicate notes added by
2305 recog_for_combine. */
2306 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2308 next
= XEXP (note
, 1);
2310 if (REG_NOTE_KIND (note
) == REG_UNUSED
2311 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2313 if (GET_CODE (XEXP (note
, 0)) == REG
)
2314 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2316 remove_note (undobuf
.other_insn
, note
);
2320 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2321 if (GET_CODE (XEXP (note
, 0)) == REG
)
2322 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2324 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2325 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2328 /* We now know that we can do this combination. Merge the insns and
2329 update the status of registers and LOG_LINKS. */
2332 rtx i3notes
, i2notes
, i1notes
= 0;
2333 rtx i3links
, i2links
, i1links
= 0;
2336 /* Compute which registers we expect to eliminate. newi2pat may be setting
2337 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2338 same as i3dest, in which case newi2pat may be setting i1dest. */
2339 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2340 || i2dest_in_i2src
|| i2dest_in_i1src
2342 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2343 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2346 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2348 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2349 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2351 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2353 /* Ensure that we do not have something that should not be shared but
2354 occurs multiple times in the new insns. Check this by first
2355 resetting all the `used' flags and then copying anything is shared. */
2357 reset_used_flags (i3notes
);
2358 reset_used_flags (i2notes
);
2359 reset_used_flags (i1notes
);
2360 reset_used_flags (newpat
);
2361 reset_used_flags (newi2pat
);
2362 if (undobuf
.other_insn
)
2363 reset_used_flags (PATTERN (undobuf
.other_insn
));
2365 i3notes
= copy_rtx_if_shared (i3notes
);
2366 i2notes
= copy_rtx_if_shared (i2notes
);
2367 i1notes
= copy_rtx_if_shared (i1notes
);
2368 newpat
= copy_rtx_if_shared (newpat
);
2369 newi2pat
= copy_rtx_if_shared (newi2pat
);
2370 if (undobuf
.other_insn
)
2371 reset_used_flags (PATTERN (undobuf
.other_insn
));
2373 INSN_CODE (i3
) = insn_code_number
;
2374 PATTERN (i3
) = newpat
;
2375 if (undobuf
.other_insn
)
2376 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2378 /* We had one special case above where I2 had more than one set and
2379 we replaced a destination of one of those sets with the destination
2380 of I3. In that case, we have to update LOG_LINKS of insns later
2381 in this basic block. Note that this (expensive) case is rare.
2383 Also, in this case, we must pretend that all REG_NOTEs for I2
2384 actually came from I3, so that REG_UNUSED notes from I2 will be
2385 properly handled. */
2387 if (i3_subst_into_i2
)
2389 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2390 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2391 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2392 && ! find_reg_note (i2
, REG_UNUSED
,
2393 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2394 for (temp
= NEXT_INSN (i2
);
2395 temp
&& (this_basic_block
== n_basic_blocks
- 1
2396 || BLOCK_HEAD (this_basic_block
) != temp
);
2397 temp
= NEXT_INSN (temp
))
2398 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2399 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2400 if (XEXP (link
, 0) == i2
)
2401 XEXP (link
, 0) = i3
;
2406 while (XEXP (link
, 1))
2407 link
= XEXP (link
, 1);
2408 XEXP (link
, 1) = i2notes
;
2422 INSN_CODE (i2
) = i2_code_number
;
2423 PATTERN (i2
) = newi2pat
;
2427 PUT_CODE (i2
, NOTE
);
2428 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2429 NOTE_SOURCE_FILE (i2
) = 0;
2436 PUT_CODE (i1
, NOTE
);
2437 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2438 NOTE_SOURCE_FILE (i1
) = 0;
2441 /* Get death notes for everything that is now used in either I3 or
2442 I2 and used to die in a previous insn. If we built two new
2443 patterns, move from I1 to I2 then I2 to I3 so that we get the
2444 proper movement on registers that I2 modifies. */
2448 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2449 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2452 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2455 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2457 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2460 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2463 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2466 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2469 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2470 know these are REG_UNUSED and want them to go to the desired insn,
2471 so we always pass it as i3. We have not counted the notes in
2472 reg_n_deaths yet, so we need to do so now. */
2474 if (newi2pat
&& new_i2_notes
)
2476 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2477 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2478 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2480 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2485 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2486 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2487 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2489 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2492 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2493 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2494 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2495 in that case, it might delete I2. Similarly for I2 and I1.
2496 Show an additional death due to the REG_DEAD note we make here. If
2497 we discard it in distribute_notes, we will decrement it again. */
2501 if (GET_CODE (i3dest_killed
) == REG
)
2502 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2504 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2505 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2507 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2509 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2511 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2515 if (i2dest_in_i2src
)
2517 if (GET_CODE (i2dest
) == REG
)
2518 REG_N_DEATHS (REGNO (i2dest
))++;
2520 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2521 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2522 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2524 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2525 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2526 NULL_RTX
, NULL_RTX
);
2529 if (i1dest_in_i1src
)
2531 if (GET_CODE (i1dest
) == REG
)
2532 REG_N_DEATHS (REGNO (i1dest
))++;
2534 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2535 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2536 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2538 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2539 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2540 NULL_RTX
, NULL_RTX
);
2543 distribute_links (i3links
);
2544 distribute_links (i2links
);
2545 distribute_links (i1links
);
2547 if (GET_CODE (i2dest
) == REG
)
2550 rtx i2_insn
= 0, i2_val
= 0, set
;
2552 /* The insn that used to set this register doesn't exist, and
2553 this life of the register may not exist either. See if one of
2554 I3's links points to an insn that sets I2DEST. If it does,
2555 that is now the last known value for I2DEST. If we don't update
2556 this and I2 set the register to a value that depended on its old
2557 contents, we will get confused. If this insn is used, thing
2558 will be set correctly in combine_instructions. */
2560 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2561 if ((set
= single_set (XEXP (link
, 0))) != 0
2562 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2563 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2565 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2567 /* If the reg formerly set in I2 died only once and that was in I3,
2568 zero its use count so it won't make `reload' do any work. */
2570 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2571 && ! i2dest_in_i2src
)
2573 regno
= REGNO (i2dest
);
2574 REG_N_SETS (regno
)--;
2575 if (REG_N_SETS (regno
) == 0
2576 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
2578 REG_N_REFS (regno
) = 0;
2582 if (i1
&& GET_CODE (i1dest
) == REG
)
2585 rtx i1_insn
= 0, i1_val
= 0, set
;
2587 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2588 if ((set
= single_set (XEXP (link
, 0))) != 0
2589 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2590 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2592 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2594 regno
= REGNO (i1dest
);
2595 if (! added_sets_1
&& ! i1dest_in_i1src
)
2597 REG_N_SETS (regno
)--;
2598 if (REG_N_SETS (regno
) == 0
2599 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
2601 REG_N_REFS (regno
) = 0;
2605 /* Update reg_nonzero_bits et al for any changes that may have been made
2608 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2610 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2612 /* If I3 is now an unconditional jump, ensure that it has a
2613 BARRIER following it since it may have initially been a
2614 conditional jump. It may also be the last nonnote insn. */
2616 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2617 && ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2618 || GET_CODE (temp
) != BARRIER
))
2619 emit_barrier_after (i3
);
2622 combine_successes
++;
2624 /* Clear this here, so that subsequent get_last_value calls are not
2626 subst_prev_insn
= NULL_RTX
;
2628 if (added_links_insn
2629 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2630 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2631 return added_links_insn
;
2633 return newi2pat
? i2
: i3
;
2636 /* Undo all the modifications recorded in undobuf. */
2641 struct undo
*undo
, *next
;
2643 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2647 *undo
->where
.i
= undo
->old_contents
.i
;
2649 *undo
->where
.r
= undo
->old_contents
.r
;
2651 undo
->next
= undobuf
.frees
;
2652 undobuf
.frees
= undo
;
2655 obfree (undobuf
.storage
);
2656 undobuf
.undos
= undobuf
.previous_undos
= 0;
2658 /* Clear this here, so that subsequent get_last_value calls are not
2660 subst_prev_insn
= NULL_RTX
;
2663 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2664 where we have an arithmetic expression and return that point. LOC will
2667 try_combine will call this function to see if an insn can be split into
2671 find_split_point (loc
, insn
)
2676 enum rtx_code code
= GET_CODE (x
);
2678 int len
= 0, pos
= 0, unsignedp
= 0;
2679 rtx inner
= NULL_RTX
;
2681 /* First special-case some codes. */
2685 #ifdef INSN_SCHEDULING
2686 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2688 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2691 return find_split_point (&SUBREG_REG (x
), insn
);
2695 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2696 using LO_SUM and HIGH. */
2697 if (GET_CODE (XEXP (x
, 0)) == CONST
2698 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2701 gen_rtx_combine (LO_SUM
, Pmode
,
2702 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2704 return &XEXP (XEXP (x
, 0), 0);
2708 /* If we have a PLUS whose second operand is a constant and the
2709 address is not valid, perhaps will can split it up using
2710 the machine-specific way to split large constants. We use
2711 the first pseudo-reg (one of the virtual regs) as a placeholder;
2712 it will not remain in the result. */
2713 if (GET_CODE (XEXP (x
, 0)) == PLUS
2714 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2715 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2717 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2718 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2721 /* This should have produced two insns, each of which sets our
2722 placeholder. If the source of the second is a valid address,
2723 we can make put both sources together and make a split point
2726 if (seq
&& XVECLEN (seq
, 0) == 2
2727 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2728 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2729 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2730 && ! reg_mentioned_p (reg
,
2731 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2732 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2733 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2734 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2735 && memory_address_p (GET_MODE (x
),
2736 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2738 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2739 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2741 /* Replace the placeholder in SRC2 with SRC1. If we can
2742 find where in SRC2 it was placed, that can become our
2743 split point and we can replace this address with SRC2.
2744 Just try two obvious places. */
2746 src2
= replace_rtx (src2
, reg
, src1
);
2748 if (XEXP (src2
, 0) == src1
)
2749 split
= &XEXP (src2
, 0);
2750 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2751 && XEXP (XEXP (src2
, 0), 0) == src1
)
2752 split
= &XEXP (XEXP (src2
, 0), 0);
2756 SUBST (XEXP (x
, 0), src2
);
2761 /* If that didn't work, perhaps the first operand is complex and
2762 needs to be computed separately, so make a split point there.
2763 This will occur on machines that just support REG + CONST
2764 and have a constant moved through some previous computation. */
2766 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2767 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2768 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2770 return &XEXP (XEXP (x
, 0), 0);
2776 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2777 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2778 we need to put the operand into a register. So split at that
2781 if (SET_DEST (x
) == cc0_rtx
2782 && GET_CODE (SET_SRC (x
)) != COMPARE
2783 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2784 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2785 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2786 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2787 return &SET_SRC (x
);
2790 /* See if we can split SET_SRC as it stands. */
2791 split
= find_split_point (&SET_SRC (x
), insn
);
2792 if (split
&& split
!= &SET_SRC (x
))
2795 /* See if we can split SET_DEST as it stands. */
2796 split
= find_split_point (&SET_DEST (x
), insn
);
2797 if (split
&& split
!= &SET_DEST (x
))
2800 /* See if this is a bitfield assignment with everything constant. If
2801 so, this is an IOR of an AND, so split it into that. */
2802 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2803 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2804 <= HOST_BITS_PER_WIDE_INT
)
2805 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2806 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2807 && GET_CODE (SET_SRC (x
)) == CONST_INT
2808 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2809 + INTVAL (XEXP (SET_DEST (x
), 2)))
2810 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2811 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2813 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2814 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2815 int src
= INTVAL (SET_SRC (x
));
2816 rtx dest
= XEXP (SET_DEST (x
), 0);
2817 enum machine_mode mode
= GET_MODE (dest
);
2818 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2820 if (BITS_BIG_ENDIAN
)
2821 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2823 if ((unsigned HOST_WIDE_INT
) src
== mask
)
2825 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2828 gen_binary (IOR
, mode
,
2829 gen_binary (AND
, mode
, dest
,
2830 GEN_INT (~ (mask
<< pos
)
2831 & GET_MODE_MASK (mode
))),
2832 GEN_INT (src
<< pos
)));
2834 SUBST (SET_DEST (x
), dest
);
2836 split
= find_split_point (&SET_SRC (x
), insn
);
2837 if (split
&& split
!= &SET_SRC (x
))
2841 /* Otherwise, see if this is an operation that we can split into two.
2842 If so, try to split that. */
2843 code
= GET_CODE (SET_SRC (x
));
2848 /* If we are AND'ing with a large constant that is only a single
2849 bit and the result is only being used in a context where we
2850 need to know if it is zero or non-zero, replace it with a bit
2851 extraction. This will avoid the large constant, which might
2852 have taken more than one insn to make. If the constant were
2853 not a valid argument to the AND but took only one insn to make,
2854 this is no worse, but if it took more than one insn, it will
2857 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2858 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2859 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2860 && GET_CODE (SET_DEST (x
)) == REG
2861 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2862 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2863 && XEXP (*split
, 0) == SET_DEST (x
)
2864 && XEXP (*split
, 1) == const0_rtx
)
2866 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
2867 XEXP (SET_SRC (x
), 0),
2868 pos
, NULL_RTX
, 1, 1, 0, 0);
2869 if (extraction
!= 0)
2871 SUBST (SET_SRC (x
), extraction
);
2872 return find_split_point (loc
, insn
);
2878 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2879 is known to be on, this can be converted into a NEG of a shift. */
2880 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
2881 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
2882 && 1 <= (pos
= exact_log2
2883 (nonzero_bits (XEXP (SET_SRC (x
), 0),
2884 GET_MODE (XEXP (SET_SRC (x
), 0))))))
2886 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
2889 gen_rtx_combine (NEG
, mode
,
2890 gen_rtx_combine (LSHIFTRT
, mode
,
2891 XEXP (SET_SRC (x
), 0),
2894 split
= find_split_point (&SET_SRC (x
), insn
);
2895 if (split
&& split
!= &SET_SRC (x
))
2901 inner
= XEXP (SET_SRC (x
), 0);
2903 /* We can't optimize if either mode is a partial integer
2904 mode as we don't know how many bits are significant
2906 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
2907 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
2911 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2917 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2918 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2920 inner
= XEXP (SET_SRC (x
), 0);
2921 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2922 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2924 if (BITS_BIG_ENDIAN
)
2925 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2926 unsignedp
= (code
== ZERO_EXTRACT
);
2934 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2936 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2938 /* For unsigned, we have a choice of a shift followed by an
2939 AND or two shifts. Use two shifts for field sizes where the
2940 constant might be too large. We assume here that we can
2941 always at least get 8-bit constants in an AND insn, which is
2942 true for every current RISC. */
2944 if (unsignedp
&& len
<= 8)
2949 gen_rtx_combine (LSHIFTRT
, mode
,
2950 gen_lowpart_for_combine (mode
, inner
),
2952 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
2954 split
= find_split_point (&SET_SRC (x
), insn
);
2955 if (split
&& split
!= &SET_SRC (x
))
2962 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
2963 gen_rtx_combine (ASHIFT
, mode
,
2964 gen_lowpart_for_combine (mode
, inner
),
2965 GEN_INT (GET_MODE_BITSIZE (mode
)
2967 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
2969 split
= find_split_point (&SET_SRC (x
), insn
);
2970 if (split
&& split
!= &SET_SRC (x
))
2975 /* See if this is a simple operation with a constant as the second
2976 operand. It might be that this constant is out of range and hence
2977 could be used as a split point. */
2978 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2979 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2980 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2981 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2982 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2983 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2984 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2986 return &XEXP (SET_SRC (x
), 1);
2988 /* Finally, see if this is a simple operation with its first operand
2989 not in a register. The operation might require this operand in a
2990 register, so return it as a split point. We can always do this
2991 because if the first operand were another operation, we would have
2992 already found it as a split point. */
2993 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2994 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2995 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2996 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2997 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2998 return &XEXP (SET_SRC (x
), 0);
3004 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3005 it is better to write this as (not (ior A B)) so we can split it.
3006 Similarly for IOR. */
3007 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3010 gen_rtx_combine (NOT
, GET_MODE (x
),
3011 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3013 XEXP (XEXP (x
, 0), 0),
3014 XEXP (XEXP (x
, 1), 0))));
3015 return find_split_point (loc
, insn
);
3018 /* Many RISC machines have a large set of logical insns. If the
3019 second operand is a NOT, put it first so we will try to split the
3020 other operand first. */
3021 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3023 rtx tem
= XEXP (x
, 0);
3024 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3025 SUBST (XEXP (x
, 1), tem
);
3033 /* Otherwise, select our actions depending on our rtx class. */
3034 switch (GET_RTX_CLASS (code
))
3036 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3038 split
= find_split_point (&XEXP (x
, 2), insn
);
3041 /* ... fall through ... */
3045 split
= find_split_point (&XEXP (x
, 1), insn
);
3048 /* ... fall through ... */
3050 /* Some machines have (and (shift ...) ...) insns. If X is not
3051 an AND, but XEXP (X, 0) is, use it as our split point. */
3052 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3053 return &XEXP (x
, 0);
3055 split
= find_split_point (&XEXP (x
, 0), insn
);
3061 /* Otherwise, we don't have a split point. */
3065 /* Throughout X, replace FROM with TO, and return the result.
3066 The result is TO if X is FROM;
3067 otherwise the result is X, but its contents may have been modified.
3068 If they were modified, a record was made in undobuf so that
3069 undo_all will (among other things) return X to its original state.
3071 If the number of changes necessary is too much to record to undo,
3072 the excess changes are not made, so the result is invalid.
3073 The changes already made can still be undone.
3074 undobuf.num_undo is incremented for such changes, so by testing that
3075 the caller can tell whether the result is valid.
3077 `n_occurrences' is incremented each time FROM is replaced.
3079 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3081 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3082 by copying if `n_occurrences' is non-zero. */
3085 subst (x
, from
, to
, in_dest
, unique_copy
)
3086 register rtx x
, from
, to
;
3090 register enum rtx_code code
= GET_CODE (x
);
3091 enum machine_mode op0_mode
= VOIDmode
;
3092 register const char *fmt
;
3093 register int len
, i
;
3096 /* Two expressions are equal if they are identical copies of a shared
3097 RTX or if they are both registers with the same register number
3100 #define COMBINE_RTX_EQUAL_P(X,Y) \
3102 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3103 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3105 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3108 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3111 /* If X and FROM are the same register but different modes, they will
3112 not have been seen as equal above. However, flow.c will make a
3113 LOG_LINKS entry for that case. If we do nothing, we will try to
3114 rerecognize our original insn and, when it succeeds, we will
3115 delete the feeding insn, which is incorrect.
3117 So force this insn not to match in this (rare) case. */
3118 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3119 && REGNO (x
) == REGNO (from
))
3120 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3122 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3123 of which may contain things that can be combined. */
3124 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3127 /* It is possible to have a subexpression appear twice in the insn.
3128 Suppose that FROM is a register that appears within TO.
3129 Then, after that subexpression has been scanned once by `subst',
3130 the second time it is scanned, TO may be found. If we were
3131 to scan TO here, we would find FROM within it and create a
3132 self-referent rtl structure which is completely wrong. */
3133 if (COMBINE_RTX_EQUAL_P (x
, to
))
3136 /* Parallel asm_operands need special attention because all of the
3137 inputs are shared across the arms. Furthermore, unsharing the
3138 rtl results in recognition failures. Failure to handle this case
3139 specially can result in circular rtl.
3141 Solve this by doing a normal pass across the first entry of the
3142 parallel, and only processing the SET_DESTs of the subsequent
3145 if (code
== PARALLEL
3146 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3147 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3149 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3151 /* If this substitution failed, this whole thing fails. */
3152 if (GET_CODE (new) == CLOBBER
3153 && XEXP (new, 0) == const0_rtx
)
3156 SUBST (XVECEXP (x
, 0, 0), new);
3158 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3160 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3162 if (GET_CODE (dest
) != REG
3163 && GET_CODE (dest
) != CC0
3164 && GET_CODE (dest
) != PC
)
3166 new = subst (dest
, from
, to
, 0, unique_copy
);
3168 /* If this substitution failed, this whole thing fails. */
3169 if (GET_CODE (new) == CLOBBER
3170 && XEXP (new, 0) == const0_rtx
)
3173 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3179 len
= GET_RTX_LENGTH (code
);
3180 fmt
= GET_RTX_FORMAT (code
);
3182 /* We don't need to process a SET_DEST that is a register, CC0,
3183 or PC, so set up to skip this common case. All other cases
3184 where we want to suppress replacing something inside a
3185 SET_SRC are handled via the IN_DEST operand. */
3187 && (GET_CODE (SET_DEST (x
)) == REG
3188 || GET_CODE (SET_DEST (x
)) == CC0
3189 || GET_CODE (SET_DEST (x
)) == PC
))
3192 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3195 op0_mode
= GET_MODE (XEXP (x
, 0));
3197 for (i
= 0; i
< len
; i
++)
3202 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3204 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3206 new = (unique_copy
&& n_occurrences
3207 ? copy_rtx (to
) : to
);
3212 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3215 /* If this substitution failed, this whole thing
3217 if (GET_CODE (new) == CLOBBER
3218 && XEXP (new, 0) == const0_rtx
)
3222 SUBST (XVECEXP (x
, i
, j
), new);
3225 else if (fmt
[i
] == 'e')
3227 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3229 /* In general, don't install a subreg involving two
3230 modes not tieable. It can worsen register
3231 allocation, and can even make invalid reload
3232 insns, since the reg inside may need to be copied
3233 from in the outside mode, and that may be invalid
3234 if it is an fp reg copied in integer mode.
3236 We allow two exceptions to this: It is valid if
3237 it is inside another SUBREG and the mode of that
3238 SUBREG and the mode of the inside of TO is
3239 tieable and it is valid if X is a SET that copies
3242 if (GET_CODE (to
) == SUBREG
3243 && ! MODES_TIEABLE_P (GET_MODE (to
),
3244 GET_MODE (SUBREG_REG (to
)))
3245 && ! (code
== SUBREG
3246 && MODES_TIEABLE_P (GET_MODE (x
),
3247 GET_MODE (SUBREG_REG (to
))))
3249 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3252 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3254 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3258 /* If we are in a SET_DEST, suppress most cases unless we
3259 have gone inside a MEM, in which case we want to
3260 simplify the address. We assume here that things that
3261 are actually part of the destination have their inner
3262 parts in the first expression. This is true for SUBREG,
3263 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3264 things aside from REG and MEM that should appear in a
3266 new = subst (XEXP (x
, i
), from
, to
,
3268 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3269 || code
== ZERO_EXTRACT
))
3271 && i
== 0), unique_copy
);
3273 /* If we found that we will have to reject this combination,
3274 indicate that by returning the CLOBBER ourselves, rather than
3275 an expression containing it. This will speed things up as
3276 well as prevent accidents where two CLOBBERs are considered
3277 to be equal, thus producing an incorrect simplification. */
3279 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3282 SUBST (XEXP (x
, i
), new);
3287 /* Try to simplify X. If the simplification changed the code, it is likely
3288 that further simplification will help, so loop, but limit the number
3289 of repetitions that will be performed. */
3291 for (i
= 0; i
< 4; i
++)
3293 /* If X is sufficiently simple, don't bother trying to do anything
3295 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3296 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3298 if (GET_CODE (x
) == code
)
3301 code
= GET_CODE (x
);
3303 /* We no longer know the original mode of operand 0 since we
3304 have changed the form of X) */
3305 op0_mode
= VOIDmode
;
3311 /* Simplify X, a piece of RTL. We just operate on the expression at the
3312 outer level; call `subst' to simplify recursively. Return the new
3315 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3316 will be the iteration even if an expression with a code different from
3317 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3320 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3322 enum machine_mode op0_mode
;
3326 enum rtx_code code
= GET_CODE (x
);
3327 enum machine_mode mode
= GET_MODE (x
);
3331 /* If this is a commutative operation, put a constant last and a complex
3332 expression first. We don't need to do this for comparisons here. */
3333 if (GET_RTX_CLASS (code
) == 'c'
3334 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3335 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3336 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3337 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3338 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3339 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3342 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3343 SUBST (XEXP (x
, 1), temp
);
3346 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3347 sign extension of a PLUS with a constant, reverse the order of the sign
3348 extension and the addition. Note that this not the same as the original
3349 code, but overflow is undefined for signed values. Also note that the
3350 PLUS will have been partially moved "inside" the sign-extension, so that
3351 the first operand of X will really look like:
3352 (ashiftrt (plus (ashift A C4) C5) C4).
3354 (plus (ashiftrt (ashift A C4) C2) C4)
3355 and replace the first operand of X with that expression. Later parts
3356 of this function may simplify the expression further.
3358 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3359 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3360 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3362 We do this to simplify address expressions. */
3364 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3365 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3366 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3367 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3368 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3369 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3370 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3371 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3372 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3373 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3374 XEXP (XEXP (x
, 0), 1))) != 0)
3377 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3378 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3379 INTVAL (XEXP (XEXP (x
, 0), 1)));
3381 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3382 INTVAL (XEXP (XEXP (x
, 0), 1)));
3384 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3387 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3388 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3389 things. Check for cases where both arms are testing the same
3392 Don't do anything if all operands are very simple. */
3394 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3395 || GET_RTX_CLASS (code
) == '<')
3396 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3397 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3398 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3400 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3401 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3402 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3404 || (GET_RTX_CLASS (code
) == '1'
3405 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3406 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3407 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3410 rtx cond
, true, false;
3412 cond
= if_then_else_cond (x
, &true, &false);
3414 /* If everything is a comparison, what we have is highly unlikely
3415 to be simpler, so don't use it. */
3416 && ! (GET_RTX_CLASS (code
) == '<'
3417 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3418 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3420 rtx cop1
= const0_rtx
;
3421 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3423 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3426 /* Simplify the alternative arms; this may collapse the true and
3427 false arms to store-flag values. */
3428 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3429 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3431 /* Restarting if we generate a store-flag expression will cause
3432 us to loop. Just drop through in this case. */
3434 /* If the result values are STORE_FLAG_VALUE and zero, we can
3435 just make the comparison operation. */
3436 if (true == const_true_rtx
&& false == const0_rtx
)
3437 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3438 else if (true == const0_rtx
&& false == const_true_rtx
)
3439 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3441 /* Likewise, we can make the negate of a comparison operation
3442 if the result values are - STORE_FLAG_VALUE and zero. */
3443 else if (GET_CODE (true) == CONST_INT
3444 && INTVAL (true) == - STORE_FLAG_VALUE
3445 && false == const0_rtx
)
3446 x
= gen_unary (NEG
, mode
, mode
,
3447 gen_binary (cond_code
, mode
, cond
, cop1
));
3448 else if (GET_CODE (false) == CONST_INT
3449 && INTVAL (false) == - STORE_FLAG_VALUE
3450 && true == const0_rtx
)
3451 x
= gen_unary (NEG
, mode
, mode
,
3452 gen_binary (reverse_condition (cond_code
),
3455 return gen_rtx_IF_THEN_ELSE (mode
,
3456 gen_binary (cond_code
, VOIDmode
,
3460 code
= GET_CODE (x
);
3461 op0_mode
= VOIDmode
;
3465 /* Try to fold this expression in case we have constants that weren't
3468 switch (GET_RTX_CLASS (code
))
3471 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3474 temp
= simplify_relational_operation (code
, op0_mode
,
3475 XEXP (x
, 0), XEXP (x
, 1));
3476 #ifdef FLOAT_STORE_FLAG_VALUE
3477 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3478 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
3479 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
3484 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3488 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3489 XEXP (x
, 1), XEXP (x
, 2));
3494 x
= temp
, code
= GET_CODE (temp
);
3496 /* First see if we can apply the inverse distributive law. */
3497 if (code
== PLUS
|| code
== MINUS
3498 || code
== AND
|| code
== IOR
|| code
== XOR
)
3500 x
= apply_distributive_law (x
);
3501 code
= GET_CODE (x
);
3504 /* If CODE is an associative operation not otherwise handled, see if we
3505 can associate some operands. This can win if they are constants or
3506 if they are logically related (i.e. (a & b) & a. */
3507 if ((code
== PLUS
|| code
== MINUS
3508 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3509 || code
== DIV
|| code
== UDIV
3510 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3511 && INTEGRAL_MODE_P (mode
))
3513 if (GET_CODE (XEXP (x
, 0)) == code
)
3515 rtx other
= XEXP (XEXP (x
, 0), 0);
3516 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3517 rtx inner_op1
= XEXP (x
, 1);
3520 /* Make sure we pass the constant operand if any as the second
3521 one if this is a commutative operation. */
3522 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3524 rtx tem
= inner_op0
;
3525 inner_op0
= inner_op1
;
3528 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3529 : code
== DIV
? MULT
3530 : code
== UDIV
? MULT
3532 mode
, inner_op0
, inner_op1
);
3534 /* For commutative operations, try the other pair if that one
3536 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3538 other
= XEXP (XEXP (x
, 0), 1);
3539 inner
= simplify_binary_operation (code
, mode
,
3540 XEXP (XEXP (x
, 0), 0),
3545 return gen_binary (code
, mode
, other
, inner
);
3549 /* A little bit of algebraic simplification here. */
3553 /* Ensure that our address has any ASHIFTs converted to MULT in case
3554 address-recognizing predicates are called later. */
3555 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3556 SUBST (XEXP (x
, 0), temp
);
3560 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3561 is paradoxical. If we can't do that safely, then it becomes
3562 something nonsensical so that this combination won't take place. */
3564 if (GET_CODE (SUBREG_REG (x
)) == MEM
3565 && (GET_MODE_SIZE (mode
)
3566 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3568 rtx inner
= SUBREG_REG (x
);
3569 int endian_offset
= 0;
3570 /* Don't change the mode of the MEM
3571 if that would change the meaning of the address. */
3572 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3573 || mode_dependent_address_p (XEXP (inner
, 0)))
3574 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3576 if (BYTES_BIG_ENDIAN
)
3578 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3579 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3580 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3581 endian_offset
-= (UNITS_PER_WORD
3582 - GET_MODE_SIZE (GET_MODE (inner
)));
3584 /* Note if the plus_constant doesn't make a valid address
3585 then this combination won't be accepted. */
3586 x
= gen_rtx_MEM (mode
,
3587 plus_constant (XEXP (inner
, 0),
3588 (SUBREG_WORD (x
) * UNITS_PER_WORD
3590 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3591 MEM_COPY_ATTRIBUTES (x
, inner
);
3595 /* If we are in a SET_DEST, these other cases can't apply. */
3599 /* Changing mode twice with SUBREG => just change it once,
3600 or not at all if changing back to starting mode. */
3601 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3603 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3604 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3605 return SUBREG_REG (SUBREG_REG (x
));
3607 SUBST_INT (SUBREG_WORD (x
),
3608 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3609 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3612 /* SUBREG of a hard register => just change the register number
3613 and/or mode. If the hard register is not valid in that mode,
3614 suppress this combination. If the hard register is the stack,
3615 frame, or argument pointer, leave this as a SUBREG. */
3617 if (GET_CODE (SUBREG_REG (x
)) == REG
3618 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3619 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3620 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3621 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3623 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3624 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3626 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3628 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3630 return gen_rtx_REG (mode
,
3631 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3633 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3636 /* For a constant, try to pick up the part we want. Handle a full
3637 word and low-order part. Only do this if we are narrowing
3638 the constant; if it is being widened, we have no idea what
3639 the extra bits will have been set to. */
3641 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3642 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3643 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3644 && GET_MODE_CLASS (mode
) == MODE_INT
)
3646 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3652 /* If we want a subreg of a constant, at offset 0,
3653 take the low bits. On a little-endian machine, that's
3654 always valid. On a big-endian machine, it's valid
3655 only if the constant's mode fits in one word. Note that we
3656 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3657 if (CONSTANT_P (SUBREG_REG (x
))
3658 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3659 || ! WORDS_BIG_ENDIAN
)
3660 ? SUBREG_WORD (x
) == 0
3662 == ((GET_MODE_SIZE (op0_mode
)
3663 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3665 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3666 && (! WORDS_BIG_ENDIAN
3667 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3668 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3670 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3671 since we are saying that the high bits don't matter. */
3672 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3673 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3674 return SUBREG_REG (x
);
3676 /* Note that we cannot do any narrowing for non-constants since
3677 we might have been counting on using the fact that some bits were
3678 zero. We now do this in the SET. */
3683 /* (not (plus X -1)) can become (neg X). */
3684 if (GET_CODE (XEXP (x
, 0)) == PLUS
3685 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3686 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3688 /* Similarly, (not (neg X)) is (plus X -1). */
3689 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3690 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3693 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3694 if (GET_CODE (XEXP (x
, 0)) == XOR
3695 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3696 && (temp
= simplify_unary_operation (NOT
, mode
,
3697 XEXP (XEXP (x
, 0), 1),
3699 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3701 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3702 other than 1, but that is not valid. We could do a similar
3703 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3704 but this doesn't seem common enough to bother with. */
3705 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3706 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3707 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3708 XEXP (XEXP (x
, 0), 1));
3710 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3711 && subreg_lowpart_p (XEXP (x
, 0))
3712 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3713 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3714 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3715 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3717 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3719 x
= gen_rtx_ROTATE (inner_mode
,
3720 gen_unary (NOT
, inner_mode
, inner_mode
,
3722 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3723 return gen_lowpart_for_combine (mode
, x
);
3726 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3727 reversing the comparison code if valid. */
3728 if (STORE_FLAG_VALUE
== -1
3729 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3730 && reversible_comparison_p (XEXP (x
, 0)))
3731 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3732 mode
, XEXP (XEXP (x
, 0), 0),
3733 XEXP (XEXP (x
, 0), 1));
3735 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3736 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3737 perform the above simplification. */
3739 if (STORE_FLAG_VALUE
== -1
3740 && XEXP (x
, 1) == const1_rtx
3741 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3742 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3743 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3744 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3746 /* Apply De Morgan's laws to reduce number of patterns for machines
3747 with negating logical insns (and-not, nand, etc.). If result has
3748 only one NOT, put it first, since that is how the patterns are
3751 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3753 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3755 if (GET_CODE (in1
) == NOT
)
3756 in1
= XEXP (in1
, 0);
3758 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3760 if (GET_CODE (in2
) == NOT
)
3761 in2
= XEXP (in2
, 0);
3762 else if (GET_CODE (in2
) == CONST_INT
3763 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3764 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3766 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3768 if (GET_CODE (in2
) == NOT
)
3771 in2
= in1
; in1
= tem
;
3774 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3780 /* (neg (plus X 1)) can become (not X). */
3781 if (GET_CODE (XEXP (x
, 0)) == PLUS
3782 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3783 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3785 /* Similarly, (neg (not X)) is (plus X 1). */
3786 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3787 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3789 /* (neg (minus X Y)) can become (minus Y X). */
3790 if (GET_CODE (XEXP (x
, 0)) == MINUS
3791 && (! FLOAT_MODE_P (mode
)
3792 /* x-y != -(y-x) with IEEE floating point. */
3793 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3795 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3796 XEXP (XEXP (x
, 0), 0));
3798 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3799 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3800 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3801 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3803 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3804 if we can then eliminate the NEG (e.g.,
3805 if the operand is a constant). */
3807 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3809 temp
= simplify_unary_operation (NEG
, mode
,
3810 XEXP (XEXP (x
, 0), 0), mode
);
3813 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3818 temp
= expand_compound_operation (XEXP (x
, 0));
3820 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3821 replaced by (lshiftrt X C). This will convert
3822 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3824 if (GET_CODE (temp
) == ASHIFTRT
3825 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3826 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3827 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3828 INTVAL (XEXP (temp
, 1)));
3830 /* If X has only a single bit that might be nonzero, say, bit I, convert
3831 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3832 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3833 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3834 or a SUBREG of one since we'd be making the expression more
3835 complex if it was just a register. */
3837 if (GET_CODE (temp
) != REG
3838 && ! (GET_CODE (temp
) == SUBREG
3839 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3840 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3842 rtx temp1
= simplify_shift_const
3843 (NULL_RTX
, ASHIFTRT
, mode
,
3844 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3845 GET_MODE_BITSIZE (mode
) - 1 - i
),
3846 GET_MODE_BITSIZE (mode
) - 1 - i
);
3848 /* If all we did was surround TEMP with the two shifts, we
3849 haven't improved anything, so don't use it. Otherwise,
3850 we are better off with TEMP1. */
3851 if (GET_CODE (temp1
) != ASHIFTRT
3852 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3853 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3859 /* We can't handle truncation to a partial integer mode here
3860 because we don't know the real bitsize of the partial
3862 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3865 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3866 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3867 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3869 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3870 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3872 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3873 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3874 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3875 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3876 return XEXP (XEXP (x
, 0), 0);
3878 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3879 (OP:SI foo:SI) if OP is NEG or ABS. */
3880 if ((GET_CODE (XEXP (x
, 0)) == ABS
3881 || GET_CODE (XEXP (x
, 0)) == NEG
)
3882 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3883 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3884 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3885 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3886 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3888 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3890 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3891 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3892 && subreg_lowpart_p (XEXP (x
, 0)))
3893 return SUBREG_REG (XEXP (x
, 0));
3895 /* If we know that the value is already truncated, we can
3896 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3897 is nonzero for the corresponding modes. But don't do this
3898 for an (LSHIFTRT (MULT ...)) since this will cause problems
3899 with the umulXi3_highpart patterns. */
3900 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3901 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3902 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3903 >= GET_MODE_BITSIZE (mode
) + 1
3904 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3905 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3906 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3908 /* A truncate of a comparison can be replaced with a subreg if
3909 STORE_FLAG_VALUE permits. This is like the previous test,
3910 but it works even if the comparison is done in a mode larger
3911 than HOST_BITS_PER_WIDE_INT. */
3912 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3913 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3914 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0)
3915 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3917 /* Similarly, a truncate of a register whose value is a
3918 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3920 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3921 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0
3922 && (temp
= get_last_value (XEXP (x
, 0)))
3923 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
3924 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3928 case FLOAT_TRUNCATE
:
3929 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3930 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
3931 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3932 return XEXP (XEXP (x
, 0), 0);
3934 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3935 (OP:SF foo:SF) if OP is NEG or ABS. */
3936 if ((GET_CODE (XEXP (x
, 0)) == ABS
3937 || GET_CODE (XEXP (x
, 0)) == NEG
)
3938 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
3939 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3940 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3941 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3943 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3944 is (float_truncate:SF x). */
3945 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3946 && subreg_lowpart_p (XEXP (x
, 0))
3947 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
3948 return SUBREG_REG (XEXP (x
, 0));
3953 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3954 using cc0, in which case we want to leave it as a COMPARE
3955 so we can distinguish it from a register-register-copy. */
3956 if (XEXP (x
, 1) == const0_rtx
)
3959 /* In IEEE floating point, x-0 is not the same as x. */
3960 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3961 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
3963 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
3969 /* (const (const X)) can become (const X). Do it this way rather than
3970 returning the inner CONST since CONST can be shared with a
3972 if (GET_CODE (XEXP (x
, 0)) == CONST
)
3973 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3978 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3979 can add in an offset. find_split_point will split this address up
3980 again if it doesn't match. */
3981 if (GET_CODE (XEXP (x
, 0)) == HIGH
3982 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
3988 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3989 outermost. That's because that's the way indexed addresses are
3990 supposed to appear. This code used to check many more cases, but
3991 they are now checked elsewhere. */
3992 if (GET_CODE (XEXP (x
, 0)) == PLUS
3993 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
3994 return gen_binary (PLUS
, mode
,
3995 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3997 XEXP (XEXP (x
, 0), 1));
3999 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4000 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4001 bit-field and can be replaced by either a sign_extend or a
4002 sign_extract. The `and' may be a zero_extend and the two
4003 <c>, -<c> constants may be reversed. */
4004 if (GET_CODE (XEXP (x
, 0)) == XOR
4005 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4006 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4007 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
4008 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4009 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4010 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4011 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4012 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4013 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4014 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4015 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4016 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4018 return simplify_shift_const
4019 (NULL_RTX
, ASHIFTRT
, mode
,
4020 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4021 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4022 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4023 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4025 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4026 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4027 is 1. This produces better code than the alternative immediately
4029 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4030 && reversible_comparison_p (XEXP (x
, 0))
4031 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4032 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
4034 gen_unary (NEG
, mode
, mode
,
4035 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
4036 mode
, XEXP (XEXP (x
, 0), 0),
4037 XEXP (XEXP (x
, 0), 1)));
4039 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4040 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4041 the bitsize of the mode - 1. This allows simplification of
4042 "a = (b & 8) == 0;" */
4043 if (XEXP (x
, 1) == constm1_rtx
4044 && GET_CODE (XEXP (x
, 0)) != REG
4045 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4046 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4047 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4048 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4049 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4050 gen_rtx_combine (XOR
, mode
,
4051 XEXP (x
, 0), const1_rtx
),
4052 GET_MODE_BITSIZE (mode
) - 1),
4053 GET_MODE_BITSIZE (mode
) - 1);
4055 /* If we are adding two things that have no bits in common, convert
4056 the addition into an IOR. This will often be further simplified,
4057 for example in cases like ((a & 1) + (a & 2)), which can
4060 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4061 && (nonzero_bits (XEXP (x
, 0), mode
)
4062 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4063 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4067 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4068 by reversing the comparison code if valid. */
4069 if (STORE_FLAG_VALUE
== 1
4070 && XEXP (x
, 0) == const1_rtx
4071 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4072 && reversible_comparison_p (XEXP (x
, 1)))
4073 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
4074 mode
, XEXP (XEXP (x
, 1), 0),
4075 XEXP (XEXP (x
, 1), 1));
4077 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4078 (and <foo> (const_int pow2-1)) */
4079 if (GET_CODE (XEXP (x
, 1)) == AND
4080 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4081 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4082 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4083 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4084 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4086 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4088 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4089 return gen_binary (MINUS
, mode
,
4090 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4091 XEXP (XEXP (x
, 1), 0)),
4092 XEXP (XEXP (x
, 1), 1));
4096 /* If we have (mult (plus A B) C), apply the distributive law and then
4097 the inverse distributive law to see if things simplify. This
4098 occurs mostly in addresses, often when unrolling loops. */
4100 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4102 x
= apply_distributive_law
4103 (gen_binary (PLUS
, mode
,
4104 gen_binary (MULT
, mode
,
4105 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4106 gen_binary (MULT
, mode
,
4107 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
4109 if (GET_CODE (x
) != MULT
)
4115 /* If this is a divide by a power of two, treat it as a shift if
4116 its first operand is a shift. */
4117 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4118 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4119 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4120 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4121 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4122 || GET_CODE (XEXP (x
, 0)) == ROTATE
4123 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4124 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4128 case GT
: case GTU
: case GE
: case GEU
:
4129 case LT
: case LTU
: case LE
: case LEU
:
4130 /* If the first operand is a condition code, we can't do anything
4132 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4133 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4135 && XEXP (x
, 0) != cc0_rtx
4139 rtx op0
= XEXP (x
, 0);
4140 rtx op1
= XEXP (x
, 1);
4141 enum rtx_code new_code
;
4143 if (GET_CODE (op0
) == COMPARE
)
4144 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4146 /* Simplify our comparison, if possible. */
4147 new_code
= simplify_comparison (code
, &op0
, &op1
);
4149 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4150 if only the low-order bit is possibly nonzero in X (such as when
4151 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4152 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4153 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4156 Remove any ZERO_EXTRACT we made when thinking this was a
4157 comparison. It may now be simpler to use, e.g., an AND. If a
4158 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4159 the call to make_compound_operation in the SET case. */
4161 if (STORE_FLAG_VALUE
== 1
4162 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4163 && op1
== const0_rtx
&& nonzero_bits (op0
, mode
) == 1)
4164 return gen_lowpart_for_combine (mode
,
4165 expand_compound_operation (op0
));
4167 else if (STORE_FLAG_VALUE
== 1
4168 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4169 && op1
== const0_rtx
4170 && (num_sign_bit_copies (op0
, mode
)
4171 == GET_MODE_BITSIZE (mode
)))
4173 op0
= expand_compound_operation (op0
);
4174 return gen_unary (NEG
, mode
, mode
,
4175 gen_lowpart_for_combine (mode
, op0
));
4178 else if (STORE_FLAG_VALUE
== 1
4179 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4180 && op1
== const0_rtx
4181 && nonzero_bits (op0
, mode
) == 1)
4183 op0
= expand_compound_operation (op0
);
4184 return gen_binary (XOR
, mode
,
4185 gen_lowpart_for_combine (mode
, op0
),
4189 else if (STORE_FLAG_VALUE
== 1
4190 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4191 && op1
== const0_rtx
4192 && (num_sign_bit_copies (op0
, mode
)
4193 == GET_MODE_BITSIZE (mode
)))
4195 op0
= expand_compound_operation (op0
);
4196 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4199 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4201 if (STORE_FLAG_VALUE
== -1
4202 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4203 && op1
== const0_rtx
4204 && (num_sign_bit_copies (op0
, mode
)
4205 == GET_MODE_BITSIZE (mode
)))
4206 return gen_lowpart_for_combine (mode
,
4207 expand_compound_operation (op0
));
4209 else if (STORE_FLAG_VALUE
== -1
4210 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4211 && op1
== const0_rtx
4212 && nonzero_bits (op0
, mode
) == 1)
4214 op0
= expand_compound_operation (op0
);
4215 return gen_unary (NEG
, mode
, mode
,
4216 gen_lowpart_for_combine (mode
, op0
));
4219 else if (STORE_FLAG_VALUE
== -1
4220 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4221 && op1
== const0_rtx
4222 && (num_sign_bit_copies (op0
, mode
)
4223 == GET_MODE_BITSIZE (mode
)))
4225 op0
= expand_compound_operation (op0
);
4226 return gen_unary (NOT
, mode
, mode
,
4227 gen_lowpart_for_combine (mode
, op0
));
4230 /* If X is 0/1, (eq X 0) is X-1. */
4231 else if (STORE_FLAG_VALUE
== -1
4232 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4233 && op1
== const0_rtx
4234 && nonzero_bits (op0
, mode
) == 1)
4236 op0
= expand_compound_operation (op0
);
4237 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4240 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4241 one bit that might be nonzero, we can convert (ne x 0) to
4242 (ashift x c) where C puts the bit in the sign bit. Remove any
4243 AND with STORE_FLAG_VALUE when we are done, since we are only
4244 going to test the sign bit. */
4245 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4246 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4247 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4248 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4249 && op1
== const0_rtx
4250 && mode
== GET_MODE (op0
)
4251 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4253 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4254 expand_compound_operation (op0
),
4255 GET_MODE_BITSIZE (mode
) - 1 - i
);
4256 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4262 /* If the code changed, return a whole new comparison. */
4263 if (new_code
!= code
)
4264 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4266 /* Otherwise, keep this operation, but maybe change its operands.
4267 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4268 SUBST (XEXP (x
, 0), op0
);
4269 SUBST (XEXP (x
, 1), op1
);
4274 return simplify_if_then_else (x
);
4280 /* If we are processing SET_DEST, we are done. */
4284 return expand_compound_operation (x
);
4287 return simplify_set (x
);
4292 return simplify_logical (x
, last
);
4295 /* (abs (neg <foo>)) -> (abs <foo>) */
4296 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4297 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4299 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4301 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4304 /* If operand is something known to be positive, ignore the ABS. */
4305 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4306 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4307 <= HOST_BITS_PER_WIDE_INT
)
4308 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4309 & ((HOST_WIDE_INT
) 1
4310 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4315 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4316 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4317 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4322 /* (ffs (*_extend <X>)) = (ffs <X>) */
4323 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4324 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4325 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4329 /* (float (sign_extend <X>)) = (float <X>). */
4330 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4331 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4339 /* If this is a shift by a constant amount, simplify it. */
4340 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4341 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4342 INTVAL (XEXP (x
, 1)));
4344 #ifdef SHIFT_COUNT_TRUNCATED
4345 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4347 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4349 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4363 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4366 simplify_if_then_else (x
)
4369 enum machine_mode mode
= GET_MODE (x
);
4370 rtx cond
= XEXP (x
, 0);
4371 rtx
true = XEXP (x
, 1);
4372 rtx
false = XEXP (x
, 2);
4373 enum rtx_code true_code
= GET_CODE (cond
);
4374 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4378 /* Simplify storing of the truth value. */
4379 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4380 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4382 /* Also when the truth value has to be reversed. */
4383 if (comparison_p
&& reversible_comparison_p (cond
)
4384 && true == const0_rtx
&& false == const_true_rtx
)
4385 return gen_binary (reverse_condition (true_code
),
4386 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4388 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4389 in it is being compared against certain values. Get the true and false
4390 comparisons and see if that says anything about the value of each arm. */
4392 if (comparison_p
&& reversible_comparison_p (cond
)
4393 && GET_CODE (XEXP (cond
, 0)) == REG
)
4396 rtx from
= XEXP (cond
, 0);
4397 enum rtx_code false_code
= reverse_condition (true_code
);
4398 rtx true_val
= XEXP (cond
, 1);
4399 rtx false_val
= true_val
;
4402 /* If FALSE_CODE is EQ, swap the codes and arms. */
4404 if (false_code
== EQ
)
4406 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4407 temp
= true, true = false, false = temp
;
4410 /* If we are comparing against zero and the expression being tested has
4411 only a single bit that might be nonzero, that is its value when it is
4412 not equal to zero. Similarly if it is known to be -1 or 0. */
4414 if (true_code
== EQ
&& true_val
== const0_rtx
4415 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4416 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4417 else if (true_code
== EQ
&& true_val
== const0_rtx
4418 && (num_sign_bit_copies (from
, GET_MODE (from
))
4419 == GET_MODE_BITSIZE (GET_MODE (from
))))
4420 false_code
= EQ
, false_val
= constm1_rtx
;
4422 /* Now simplify an arm if we know the value of the register in the
4423 branch and it is used in the arm. Be careful due to the potential
4424 of locally-shared RTL. */
4426 if (reg_mentioned_p (from
, true))
4427 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4428 pc_rtx
, pc_rtx
, 0, 0);
4429 if (reg_mentioned_p (from
, false))
4430 false = subst (known_cond (copy_rtx (false), false_code
,
4432 pc_rtx
, pc_rtx
, 0, 0);
4434 SUBST (XEXP (x
, 1), swapped
? false : true);
4435 SUBST (XEXP (x
, 2), swapped
? true : false);
4437 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4440 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4441 reversed, do so to avoid needing two sets of patterns for
4442 subtract-and-branch insns. Similarly if we have a constant in the true
4443 arm, the false arm is the same as the first operand of the comparison, or
4444 the false arm is more complicated than the true arm. */
4446 if (comparison_p
&& reversible_comparison_p (cond
)
4448 || (CONSTANT_P (true)
4449 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4450 || true == const0_rtx
4451 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4452 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4453 || (GET_CODE (true) == SUBREG
4454 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4455 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4456 || reg_mentioned_p (true, false)
4457 || rtx_equal_p (false, XEXP (cond
, 0))))
4459 true_code
= reverse_condition (true_code
);
4461 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4464 SUBST (XEXP (x
, 1), false);
4465 SUBST (XEXP (x
, 2), true);
4467 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4469 /* It is possible that the conditional has been simplified out. */
4470 true_code
= GET_CODE (cond
);
4471 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4474 /* If the two arms are identical, we don't need the comparison. */
4476 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4479 /* Convert a == b ? b : a to "a". */
4480 if (true_code
== EQ
&& ! side_effects_p (cond
)
4481 && rtx_equal_p (XEXP (cond
, 0), false)
4482 && rtx_equal_p (XEXP (cond
, 1), true))
4484 else if (true_code
== NE
&& ! side_effects_p (cond
)
4485 && rtx_equal_p (XEXP (cond
, 0), true)
4486 && rtx_equal_p (XEXP (cond
, 1), false))
4489 /* Look for cases where we have (abs x) or (neg (abs X)). */
4491 if (GET_MODE_CLASS (mode
) == MODE_INT
4492 && GET_CODE (false) == NEG
4493 && rtx_equal_p (true, XEXP (false, 0))
4495 && rtx_equal_p (true, XEXP (cond
, 0))
4496 && ! side_effects_p (true))
4501 return gen_unary (ABS
, mode
, mode
, true);
4504 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4509 /* Look for MIN or MAX. */
4511 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4513 && rtx_equal_p (XEXP (cond
, 0), true)
4514 && rtx_equal_p (XEXP (cond
, 1), false)
4515 && ! side_effects_p (cond
))
4520 return gen_binary (SMAX
, mode
, true, false);
4523 return gen_binary (SMIN
, mode
, true, false);
4526 return gen_binary (UMAX
, mode
, true, false);
4529 return gen_binary (UMIN
, mode
, true, false);
4534 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4535 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4536 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4537 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4538 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4539 neither 1 or -1, but it isn't worth checking for. */
4541 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4542 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4544 rtx t
= make_compound_operation (true, SET
);
4545 rtx f
= make_compound_operation (false, SET
);
4546 rtx cond_op0
= XEXP (cond
, 0);
4547 rtx cond_op1
= XEXP (cond
, 1);
4548 enum rtx_code op
= NIL
, extend_op
= NIL
;
4549 enum machine_mode m
= mode
;
4550 rtx z
= 0, c1
= NULL_RTX
;
4552 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4553 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4554 || GET_CODE (t
) == ASHIFT
4555 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4556 && rtx_equal_p (XEXP (t
, 0), f
))
4557 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4559 /* If an identity-zero op is commutative, check whether there
4560 would be a match if we swapped the operands. */
4561 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4562 || GET_CODE (t
) == XOR
)
4563 && rtx_equal_p (XEXP (t
, 1), f
))
4564 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4565 else if (GET_CODE (t
) == SIGN_EXTEND
4566 && (GET_CODE (XEXP (t
, 0)) == PLUS
4567 || GET_CODE (XEXP (t
, 0)) == MINUS
4568 || GET_CODE (XEXP (t
, 0)) == IOR
4569 || GET_CODE (XEXP (t
, 0)) == XOR
4570 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4571 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4572 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4573 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4574 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4575 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4576 && (num_sign_bit_copies (f
, GET_MODE (f
))
4577 > (GET_MODE_BITSIZE (mode
)
4578 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4580 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4581 extend_op
= SIGN_EXTEND
;
4582 m
= GET_MODE (XEXP (t
, 0));
4584 else if (GET_CODE (t
) == SIGN_EXTEND
4585 && (GET_CODE (XEXP (t
, 0)) == PLUS
4586 || GET_CODE (XEXP (t
, 0)) == IOR
4587 || GET_CODE (XEXP (t
, 0)) == XOR
)
4588 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4589 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4590 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4591 && (num_sign_bit_copies (f
, GET_MODE (f
))
4592 > (GET_MODE_BITSIZE (mode
)
4593 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4595 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4596 extend_op
= SIGN_EXTEND
;
4597 m
= GET_MODE (XEXP (t
, 0));
4599 else if (GET_CODE (t
) == ZERO_EXTEND
4600 && (GET_CODE (XEXP (t
, 0)) == PLUS
4601 || GET_CODE (XEXP (t
, 0)) == MINUS
4602 || GET_CODE (XEXP (t
, 0)) == IOR
4603 || GET_CODE (XEXP (t
, 0)) == XOR
4604 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4605 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4606 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4607 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4608 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4609 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4610 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4611 && ((nonzero_bits (f
, GET_MODE (f
))
4612 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4615 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4616 extend_op
= ZERO_EXTEND
;
4617 m
= GET_MODE (XEXP (t
, 0));
4619 else if (GET_CODE (t
) == ZERO_EXTEND
4620 && (GET_CODE (XEXP (t
, 0)) == PLUS
4621 || GET_CODE (XEXP (t
, 0)) == IOR
4622 || GET_CODE (XEXP (t
, 0)) == XOR
)
4623 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4624 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4625 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4626 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4627 && ((nonzero_bits (f
, GET_MODE (f
))
4628 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4631 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4632 extend_op
= ZERO_EXTEND
;
4633 m
= GET_MODE (XEXP (t
, 0));
4638 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4639 pc_rtx
, pc_rtx
, 0, 0);
4640 temp
= gen_binary (MULT
, m
, temp
,
4641 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4642 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4643 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4645 if (extend_op
!= NIL
)
4646 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4652 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4653 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4654 negation of a single bit, we can convert this operation to a shift. We
4655 can actually do this more generally, but it doesn't seem worth it. */
4657 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4658 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4659 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4660 && (i
= exact_log2 (INTVAL (true))) >= 0)
4661 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4662 == GET_MODE_BITSIZE (mode
))
4663 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4665 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4666 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4671 /* Simplify X, a SET expression. Return the new expression. */
4677 rtx src
= SET_SRC (x
);
4678 rtx dest
= SET_DEST (x
);
4679 enum machine_mode mode
4680 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4684 /* (set (pc) (return)) gets written as (return). */
4685 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4688 /* Now that we know for sure which bits of SRC we are using, see if we can
4689 simplify the expression for the object knowing that we only need the
4692 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4694 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4695 SUBST (SET_SRC (x
), src
);
4698 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4699 the comparison result and try to simplify it unless we already have used
4700 undobuf.other_insn. */
4701 if ((GET_CODE (src
) == COMPARE
4706 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4707 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4708 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4709 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4711 enum rtx_code old_code
= GET_CODE (*cc_use
);
4712 enum rtx_code new_code
;
4714 int other_changed
= 0;
4715 enum machine_mode compare_mode
= GET_MODE (dest
);
4717 if (GET_CODE (src
) == COMPARE
)
4718 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4720 op0
= src
, op1
= const0_rtx
;
4722 /* Simplify our comparison, if possible. */
4723 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4725 #ifdef EXTRA_CC_MODES
4726 /* If this machine has CC modes other than CCmode, check to see if we
4727 need to use a different CC mode here. */
4728 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4729 #endif /* EXTRA_CC_MODES */
4731 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4732 /* If the mode changed, we have to change SET_DEST, the mode in the
4733 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4734 a hard register, just build new versions with the proper mode. If it
4735 is a pseudo, we lose unless it is only time we set the pseudo, in
4736 which case we can safely change its mode. */
4737 if (compare_mode
!= GET_MODE (dest
))
4739 int regno
= REGNO (dest
);
4740 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4742 if (regno
< FIRST_PSEUDO_REGISTER
4743 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4745 if (regno
>= FIRST_PSEUDO_REGISTER
)
4746 SUBST (regno_reg_rtx
[regno
], new_dest
);
4748 SUBST (SET_DEST (x
), new_dest
);
4749 SUBST (XEXP (*cc_use
, 0), new_dest
);
4757 /* If the code changed, we have to build a new comparison in
4758 undobuf.other_insn. */
4759 if (new_code
!= old_code
)
4761 unsigned HOST_WIDE_INT mask
;
4763 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4766 /* If the only change we made was to change an EQ into an NE or
4767 vice versa, OP0 has only one bit that might be nonzero, and OP1
4768 is zero, check if changing the user of the condition code will
4769 produce a valid insn. If it won't, we can keep the original code
4770 in that insn by surrounding our operation with an XOR. */
4772 if (((old_code
== NE
&& new_code
== EQ
)
4773 || (old_code
== EQ
&& new_code
== NE
))
4774 && ! other_changed
&& op1
== const0_rtx
4775 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4776 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4778 rtx pat
= PATTERN (other_insn
), note
= 0;
4780 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4781 && ! check_asm_operands (pat
)))
4783 PUT_CODE (*cc_use
, old_code
);
4786 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4794 undobuf
.other_insn
= other_insn
;
4797 /* If we are now comparing against zero, change our source if
4798 needed. If we do not use cc0, we always have a COMPARE. */
4799 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4801 SUBST (SET_SRC (x
), op0
);
4807 /* Otherwise, if we didn't previously have a COMPARE in the
4808 correct mode, we need one. */
4809 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4812 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4817 /* Otherwise, update the COMPARE if needed. */
4818 SUBST (XEXP (src
, 0), op0
);
4819 SUBST (XEXP (src
, 1), op1
);
4824 /* Get SET_SRC in a form where we have placed back any
4825 compound expressions. Then do the checks below. */
4826 src
= make_compound_operation (src
, SET
);
4827 SUBST (SET_SRC (x
), src
);
4830 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4831 and X being a REG or (subreg (reg)), we may be able to convert this to
4832 (set (subreg:m2 x) (op)).
4834 We can always do this if M1 is narrower than M2 because that means that
4835 we only care about the low bits of the result.
4837 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4838 perform a narrower operation than requested since the high-order bits will
4839 be undefined. On machine where it is defined, this transformation is safe
4840 as long as M1 and M2 have the same number of words. */
4842 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4843 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4844 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4847 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4848 #ifndef WORD_REGISTER_OPERATIONS
4849 && (GET_MODE_SIZE (GET_MODE (src
))
4850 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4852 #ifdef CLASS_CANNOT_CHANGE_SIZE
4853 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
4854 && (TEST_HARD_REG_BIT
4855 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
4857 && (GET_MODE_SIZE (GET_MODE (src
))
4858 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
4860 && (GET_CODE (dest
) == REG
4861 || (GET_CODE (dest
) == SUBREG
4862 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4864 SUBST (SET_DEST (x
),
4865 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4867 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4869 src
= SET_SRC (x
), dest
= SET_DEST (x
);
4872 #ifdef LOAD_EXTEND_OP
4873 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4874 would require a paradoxical subreg. Replace the subreg with a
4875 zero_extend to avoid the reload that would otherwise be required. */
4877 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4878 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
4879 && SUBREG_WORD (src
) == 0
4880 && (GET_MODE_SIZE (GET_MODE (src
))
4881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4882 && GET_CODE (SUBREG_REG (src
)) == MEM
)
4885 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
4886 GET_MODE (src
), XEXP (src
, 0)));
4892 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4893 are comparing an item known to be 0 or -1 against 0, use a logical
4894 operation instead. Check for one of the arms being an IOR of the other
4895 arm with some value. We compute three terms to be IOR'ed together. In
4896 practice, at most two will be nonzero. Then we do the IOR's. */
4898 if (GET_CODE (dest
) != PC
4899 && GET_CODE (src
) == IF_THEN_ELSE
4900 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
4901 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
4902 && XEXP (XEXP (src
, 0), 1) == const0_rtx
4903 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
4904 #ifdef HAVE_conditional_move
4905 && ! can_conditionally_move_p (GET_MODE (src
))
4907 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
4908 GET_MODE (XEXP (XEXP (src
, 0), 0)))
4909 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
4910 && ! side_effects_p (src
))
4912 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
4913 ? XEXP (src
, 1) : XEXP (src
, 2));
4914 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
4915 ? XEXP (src
, 2) : XEXP (src
, 1));
4916 rtx term1
= const0_rtx
, term2
, term3
;
4918 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
4919 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
4920 else if (GET_CODE (true) == IOR
4921 && rtx_equal_p (XEXP (true, 1), false))
4922 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
4923 else if (GET_CODE (false) == IOR
4924 && rtx_equal_p (XEXP (false, 0), true))
4925 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
4926 else if (GET_CODE (false) == IOR
4927 && rtx_equal_p (XEXP (false, 1), true))
4928 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
4930 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
4931 term3
= gen_binary (AND
, GET_MODE (src
),
4932 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
4933 XEXP (XEXP (src
, 0), 0)),
4937 gen_binary (IOR
, GET_MODE (src
),
4938 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
4944 #ifdef HAVE_conditional_arithmetic
4945 /* If we have conditional arithmetic and the operand of a SET is
4946 a conditional expression, replace this with an IF_THEN_ELSE.
4947 We can either have a conditional expression or a MULT of that expression
4949 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
4950 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
4951 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
4952 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
4953 || (GET_CODE (XEXP (src
, 0)) == MULT
4954 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
4955 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
4957 rtx cond
= XEXP (src
, 0);
4958 rtx true_val
= const1_rtx
;
4959 rtx false_arm
, true_arm
;
4961 if (GET_CODE (cond
) == MULT
)
4963 true_val
= XEXP (cond
, 1);
4964 cond
= XEXP (cond
, 0);
4967 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
4969 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
4970 GET_MODE (XEXP (src
, 0)), true_val
);
4971 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
4972 GET_MODE (XEXP (src
, 0)), const0_rtx
);
4976 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
4977 true_val
, XEXP (src
, 1));
4978 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
4979 const0_rtx
, XEXP (src
, 1));
4982 /* Canonicalize if true_arm is the simpler one. */
4983 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
4984 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
4985 && reversible_comparison_p (cond
))
4987 rtx temp
= true_arm
;
4989 true_arm
= false_arm
;
4992 cond
= gen_rtx_combine (reverse_condition (GET_CODE (cond
)),
4993 GET_MODE (cond
), XEXP (cond
, 0),
4997 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
4998 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5001 true_arm
, false_arm
);
5002 SUBST (SET_SRC (x
), src
);
5006 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5007 whole thing fail. */
5008 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5010 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5013 /* Convert this into a field assignment operation, if possible. */
5014 return make_field_assignment (x
);
5017 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5018 result. LAST is nonzero if this is the last retry. */
5021 simplify_logical (x
, last
)
5025 enum machine_mode mode
= GET_MODE (x
);
5026 rtx op0
= XEXP (x
, 0);
5027 rtx op1
= XEXP (x
, 1);
5029 switch (GET_CODE (x
))
5032 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5033 insn (and may simplify more). */
5034 if (GET_CODE (op0
) == XOR
5035 && rtx_equal_p (XEXP (op0
, 0), op1
)
5036 && ! side_effects_p (op1
))
5037 x
= gen_binary (AND
, mode
,
5038 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5040 if (GET_CODE (op0
) == XOR
5041 && rtx_equal_p (XEXP (op0
, 1), op1
)
5042 && ! side_effects_p (op1
))
5043 x
= gen_binary (AND
, mode
,
5044 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5046 /* Similarly for (~ (A ^ B)) & A. */
5047 if (GET_CODE (op0
) == NOT
5048 && GET_CODE (XEXP (op0
, 0)) == XOR
5049 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5050 && ! side_effects_p (op1
))
5051 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5053 if (GET_CODE (op0
) == NOT
5054 && GET_CODE (XEXP (op0
, 0)) == XOR
5055 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5056 && ! side_effects_p (op1
))
5057 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5059 /* We can call simplify_and_const_int only if we don't lose
5060 any (sign) bits when converting INTVAL (op1) to
5061 "unsigned HOST_WIDE_INT". */
5062 if (GET_CODE (op1
) == CONST_INT
5063 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5064 || INTVAL (op1
) > 0))
5066 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5068 /* If we have (ior (and (X C1) C2)) and the next restart would be
5069 the last, simplify this by making C1 as small as possible
5072 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5073 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5074 && GET_CODE (op1
) == CONST_INT
)
5075 return gen_binary (IOR
, mode
,
5076 gen_binary (AND
, mode
, XEXP (op0
, 0),
5077 GEN_INT (INTVAL (XEXP (op0
, 1))
5078 & ~ INTVAL (op1
))), op1
);
5080 if (GET_CODE (x
) != AND
)
5083 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5084 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5085 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5088 /* Convert (A | B) & A to A. */
5089 if (GET_CODE (op0
) == IOR
5090 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5091 || rtx_equal_p (XEXP (op0
, 1), op1
))
5092 && ! side_effects_p (XEXP (op0
, 0))
5093 && ! side_effects_p (XEXP (op0
, 1)))
5096 /* In the following group of tests (and those in case IOR below),
5097 we start with some combination of logical operations and apply
5098 the distributive law followed by the inverse distributive law.
5099 Most of the time, this results in no change. However, if some of
5100 the operands are the same or inverses of each other, simplifications
5103 For example, (and (ior A B) (not B)) can occur as the result of
5104 expanding a bit field assignment. When we apply the distributive
5105 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5106 which then simplifies to (and (A (not B))).
5108 If we have (and (ior A B) C), apply the distributive law and then
5109 the inverse distributive law to see if things simplify. */
5111 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5113 x
= apply_distributive_law
5114 (gen_binary (GET_CODE (op0
), mode
,
5115 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5116 gen_binary (AND
, mode
, XEXP (op0
, 1), op1
)));
5117 if (GET_CODE (x
) != AND
)
5121 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5122 return apply_distributive_law
5123 (gen_binary (GET_CODE (op1
), mode
,
5124 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5125 gen_binary (AND
, mode
, XEXP (op1
, 1), op0
)));
5127 /* Similarly, taking advantage of the fact that
5128 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5130 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5131 return apply_distributive_law
5132 (gen_binary (XOR
, mode
,
5133 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5134 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 1))));
5136 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5137 return apply_distributive_law
5138 (gen_binary (XOR
, mode
,
5139 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5140 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 1))));
5144 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5145 if (GET_CODE (op1
) == CONST_INT
5146 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5147 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
5150 /* Convert (A & B) | A to A. */
5151 if (GET_CODE (op0
) == AND
5152 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5153 || rtx_equal_p (XEXP (op0
, 1), op1
))
5154 && ! side_effects_p (XEXP (op0
, 0))
5155 && ! side_effects_p (XEXP (op0
, 1)))
5158 /* If we have (ior (and A B) C), apply the distributive law and then
5159 the inverse distributive law to see if things simplify. */
5161 if (GET_CODE (op0
) == AND
)
5163 x
= apply_distributive_law
5164 (gen_binary (AND
, mode
,
5165 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5166 gen_binary (IOR
, mode
, XEXP (op0
, 1), op1
)));
5168 if (GET_CODE (x
) != IOR
)
5172 if (GET_CODE (op1
) == AND
)
5174 x
= apply_distributive_law
5175 (gen_binary (AND
, mode
,
5176 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5177 gen_binary (IOR
, mode
, XEXP (op1
, 1), op0
)));
5179 if (GET_CODE (x
) != IOR
)
5183 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5184 mode size to (rotate A CX). */
5186 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5187 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5188 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5189 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5190 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5191 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5192 == GET_MODE_BITSIZE (mode
)))
5193 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5194 (GET_CODE (op0
) == ASHIFT
5195 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5197 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5198 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5199 does not affect any of the bits in OP1, it can really be done
5200 as a PLUS and we can associate. We do this by seeing if OP1
5201 can be safely shifted left C bits. */
5202 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5203 && GET_CODE (XEXP (op0
, 0)) == PLUS
5204 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5205 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5206 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5208 int count
= INTVAL (XEXP (op0
, 1));
5209 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5211 if (mask
>> count
== INTVAL (op1
)
5212 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5214 SUBST (XEXP (XEXP (op0
, 0), 1),
5215 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5222 /* If we are XORing two things that have no bits in common,
5223 convert them into an IOR. This helps to detect rotation encoded
5224 using those methods and possibly other simplifications. */
5226 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5227 && (nonzero_bits (op0
, mode
)
5228 & nonzero_bits (op1
, mode
)) == 0)
5229 return (gen_binary (IOR
, mode
, op0
, op1
));
5231 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5232 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5235 int num_negated
= 0;
5237 if (GET_CODE (op0
) == NOT
)
5238 num_negated
++, op0
= XEXP (op0
, 0);
5239 if (GET_CODE (op1
) == NOT
)
5240 num_negated
++, op1
= XEXP (op1
, 0);
5242 if (num_negated
== 2)
5244 SUBST (XEXP (x
, 0), op0
);
5245 SUBST (XEXP (x
, 1), op1
);
5247 else if (num_negated
== 1)
5248 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5251 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5252 correspond to a machine insn or result in further simplifications
5253 if B is a constant. */
5255 if (GET_CODE (op0
) == AND
5256 && rtx_equal_p (XEXP (op0
, 1), op1
)
5257 && ! side_effects_p (op1
))
5258 return gen_binary (AND
, mode
,
5259 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5262 else if (GET_CODE (op0
) == AND
5263 && rtx_equal_p (XEXP (op0
, 0), op1
)
5264 && ! side_effects_p (op1
))
5265 return gen_binary (AND
, mode
,
5266 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5269 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5270 comparison if STORE_FLAG_VALUE is 1. */
5271 if (STORE_FLAG_VALUE
== 1
5272 && op1
== const1_rtx
5273 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5274 && reversible_comparison_p (op0
))
5275 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5276 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5278 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5279 is (lt foo (const_int 0)), so we can perform the above
5280 simplification if STORE_FLAG_VALUE is 1. */
5282 if (STORE_FLAG_VALUE
== 1
5283 && op1
== const1_rtx
5284 && GET_CODE (op0
) == LSHIFTRT
5285 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5286 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5287 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5289 /* (xor (comparison foo bar) (const_int sign-bit))
5290 when STORE_FLAG_VALUE is the sign bit. */
5291 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5292 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5293 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5294 && op1
== const_true_rtx
5295 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5296 && reversible_comparison_p (op0
))
5297 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5298 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5309 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5310 operations" because they can be replaced with two more basic operations.
5311 ZERO_EXTEND is also considered "compound" because it can be replaced with
5312 an AND operation, which is simpler, though only one operation.
5314 The function expand_compound_operation is called with an rtx expression
5315 and will convert it to the appropriate shifts and AND operations,
5316 simplifying at each stage.
5318 The function make_compound_operation is called to convert an expression
5319 consisting of shifts and ANDs into the equivalent compound expression.
5320 It is the inverse of this function, loosely speaking. */
5323 expand_compound_operation (x
)
5331 switch (GET_CODE (x
))
5336 /* We can't necessarily use a const_int for a multiword mode;
5337 it depends on implicitly extending the value.
5338 Since we don't know the right way to extend it,
5339 we can't tell whether the implicit way is right.
5341 Even for a mode that is no wider than a const_int,
5342 we can't win, because we need to sign extend one of its bits through
5343 the rest of it, and we don't know which bit. */
5344 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5347 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5348 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5349 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5350 reloaded. If not for that, MEM's would very rarely be safe.
5352 Reject MODEs bigger than a word, because we might not be able
5353 to reference a two-register group starting with an arbitrary register
5354 (and currently gen_lowpart might crash for a SUBREG). */
5356 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5359 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5360 /* If the inner object has VOIDmode (the only way this can happen
5361 is if it is a ASM_OPERANDS), we can't do anything since we don't
5362 know how much masking to do. */
5371 /* If the operand is a CLOBBER, just return it. */
5372 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5375 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5376 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5377 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5380 len
= INTVAL (XEXP (x
, 1));
5381 pos
= INTVAL (XEXP (x
, 2));
5383 /* If this goes outside the object being extracted, replace the object
5384 with a (use (mem ...)) construct that only combine understands
5385 and is used only for this purpose. */
5386 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5387 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5389 if (BITS_BIG_ENDIAN
)
5390 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5398 /* We can optimize some special cases of ZERO_EXTEND. */
5399 if (GET_CODE (x
) == ZERO_EXTEND
)
5401 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5402 know that the last value didn't have any inappropriate bits
5404 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5405 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5406 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5407 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5408 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5409 return XEXP (XEXP (x
, 0), 0);
5411 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5412 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5413 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5414 && subreg_lowpart_p (XEXP (x
, 0))
5415 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5416 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5417 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5418 return SUBREG_REG (XEXP (x
, 0));
5420 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5421 is a comparison and STORE_FLAG_VALUE permits. This is like
5422 the first case, but it works even when GET_MODE (x) is larger
5423 than HOST_WIDE_INT. */
5424 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5425 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5426 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5427 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5428 <= HOST_BITS_PER_WIDE_INT
)
5429 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5430 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5431 return XEXP (XEXP (x
, 0), 0);
5433 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5434 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5435 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5436 && subreg_lowpart_p (XEXP (x
, 0))
5437 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5438 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5439 <= HOST_BITS_PER_WIDE_INT
)
5440 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5441 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5442 return SUBREG_REG (XEXP (x
, 0));
5444 /* If sign extension is cheaper than zero extension, then use it
5445 if we know that no extraneous bits are set, and that the high
5447 if (flag_expensive_optimizations
5448 && ((GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5449 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (x
))
5450 & ~ (((unsigned HOST_WIDE_INT
)
5451 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5454 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5455 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5456 <= HOST_BITS_PER_WIDE_INT
)
5457 && (((HOST_WIDE_INT
) STORE_FLAG_VALUE
5458 & ~ (((unsigned HOST_WIDE_INT
)
5459 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5463 rtx temp
= gen_rtx_SIGN_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5465 if (rtx_cost (temp
, SET
) < rtx_cost (x
, SET
))
5466 return expand_compound_operation (temp
);
5470 /* If we reach here, we want to return a pair of shifts. The inner
5471 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5472 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5473 logical depending on the value of UNSIGNEDP.
5475 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5476 converted into an AND of a shift.
5478 We must check for the case where the left shift would have a negative
5479 count. This can happen in a case like (x >> 31) & 255 on machines
5480 that can't shift by a constant. On those machines, we would first
5481 combine the shift with the AND to produce a variable-position
5482 extraction. Then the constant of 31 would be substituted in to produce
5483 a such a position. */
5485 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5486 if (modewidth
>= pos
- len
)
5487 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5489 simplify_shift_const (NULL_RTX
, ASHIFT
,
5492 modewidth
- pos
- len
),
5495 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5496 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5497 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5500 ((HOST_WIDE_INT
) 1 << len
) - 1);
5502 /* Any other cases we can't handle. */
5506 /* If we couldn't do this for some reason, return the original
5508 if (GET_CODE (tem
) == CLOBBER
)
5514 /* X is a SET which contains an assignment of one object into
5515 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5516 or certain SUBREGS). If possible, convert it into a series of
5519 We half-heartedly support variable positions, but do not at all
5520 support variable lengths. */
5523 expand_field_assignment (x
)
5527 rtx pos
; /* Always counts from low bit. */
5530 enum machine_mode compute_mode
;
5532 /* Loop until we find something we can't simplify. */
5535 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5536 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5538 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5539 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5540 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5542 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5543 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5545 inner
= XEXP (SET_DEST (x
), 0);
5546 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5547 pos
= XEXP (SET_DEST (x
), 2);
5549 /* If the position is constant and spans the width of INNER,
5550 surround INNER with a USE to indicate this. */
5551 if (GET_CODE (pos
) == CONST_INT
5552 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5553 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5555 if (BITS_BIG_ENDIAN
)
5557 if (GET_CODE (pos
) == CONST_INT
)
5558 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5560 else if (GET_CODE (pos
) == MINUS
5561 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5562 && (INTVAL (XEXP (pos
, 1))
5563 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5564 /* If position is ADJUST - X, new position is X. */
5565 pos
= XEXP (pos
, 0);
5567 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5568 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5574 /* A SUBREG between two modes that occupy the same numbers of words
5575 can be done by moving the SUBREG to the source. */
5576 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5577 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5578 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5579 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5580 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5582 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5583 gen_lowpart_for_combine
5584 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5591 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5592 inner
= SUBREG_REG (inner
);
5594 compute_mode
= GET_MODE (inner
);
5596 /* Don't attempt bitwise arithmetic on non-integral modes. */
5597 if (! INTEGRAL_MODE_P (compute_mode
))
5599 enum machine_mode imode
;
5601 /* Something is probably seriously wrong if this matches. */
5602 if (! FLOAT_MODE_P (compute_mode
))
5605 /* Try to find an integral mode to pun with. */
5606 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5607 if (imode
== BLKmode
)
5610 compute_mode
= imode
;
5611 inner
= gen_lowpart_for_combine (imode
, inner
);
5614 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5615 if (len
< HOST_BITS_PER_WIDE_INT
)
5616 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5620 /* Now compute the equivalent expression. Make a copy of INNER
5621 for the SET_DEST in case it is a MEM into which we will substitute;
5622 we don't want shared RTL in that case. */
5624 (VOIDmode
, copy_rtx (inner
),
5625 gen_binary (IOR
, compute_mode
,
5626 gen_binary (AND
, compute_mode
,
5627 gen_unary (NOT
, compute_mode
,
5633 gen_binary (ASHIFT
, compute_mode
,
5634 gen_binary (AND
, compute_mode
,
5635 gen_lowpart_for_combine
5636 (compute_mode
, SET_SRC (x
)),
5644 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5645 it is an RTX that represents a variable starting position; otherwise,
5646 POS is the (constant) starting bit position (counted from the LSB).
5648 INNER may be a USE. This will occur when we started with a bitfield
5649 that went outside the boundary of the object in memory, which is
5650 allowed on most machines. To isolate this case, we produce a USE
5651 whose mode is wide enough and surround the MEM with it. The only
5652 code that understands the USE is this routine. If it is not removed,
5653 it will cause the resulting insn not to match.
5655 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5658 IN_DEST is non-zero if this is a reference in the destination of a
5659 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5660 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5663 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5664 ZERO_EXTRACT should be built even for bits starting at bit 0.
5666 MODE is the desired mode of the result (if IN_DEST == 0).
5668 The result is an RTX for the extraction or NULL_RTX if the target
5672 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5673 unsignedp
, in_dest
, in_compare
)
5674 enum machine_mode mode
;
5680 int in_dest
, in_compare
;
5682 /* This mode describes the size of the storage area
5683 to fetch the overall value from. Within that, we
5684 ignore the POS lowest bits, etc. */
5685 enum machine_mode is_mode
= GET_MODE (inner
);
5686 enum machine_mode inner_mode
;
5687 enum machine_mode wanted_inner_mode
= byte_mode
;
5688 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5689 enum machine_mode pos_mode
= word_mode
;
5690 enum machine_mode extraction_mode
= word_mode
;
5691 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5694 rtx orig_pos_rtx
= pos_rtx
;
5697 /* Get some information about INNER and get the innermost object. */
5698 if (GET_CODE (inner
) == USE
)
5699 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5700 /* We don't need to adjust the position because we set up the USE
5701 to pretend that it was a full-word object. */
5702 spans_byte
= 1, inner
= XEXP (inner
, 0);
5703 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5705 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5706 consider just the QI as the memory to extract from.
5707 The subreg adds or removes high bits; its mode is
5708 irrelevant to the meaning of this extraction,
5709 since POS and LEN count from the lsb. */
5710 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5711 is_mode
= GET_MODE (SUBREG_REG (inner
));
5712 inner
= SUBREG_REG (inner
);
5715 inner_mode
= GET_MODE (inner
);
5717 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5718 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5720 /* See if this can be done without an extraction. We never can if the
5721 width of the field is not the same as that of some integer mode. For
5722 registers, we can only avoid the extraction if the position is at the
5723 low-order bit and this is either not in the destination or we have the
5724 appropriate STRICT_LOW_PART operation available.
5726 For MEM, we can avoid an extract if the field starts on an appropriate
5727 boundary and we can change the mode of the memory reference. However,
5728 we cannot directly access the MEM if we have a USE and the underlying
5729 MEM is not TMODE. This combination means that MEM was being used in a
5730 context where bits outside its mode were being referenced; that is only
5731 valid in bit-field insns. */
5733 if (tmode
!= BLKmode
5734 && ! (spans_byte
&& inner_mode
!= tmode
)
5735 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5736 && GET_CODE (inner
) != MEM
5738 || (GET_CODE (inner
) == REG
5739 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5740 != CODE_FOR_nothing
))))
5741 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5743 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5744 : BITS_PER_UNIT
)) == 0
5745 /* We can't do this if we are widening INNER_MODE (it
5746 may not be aligned, for one thing). */
5747 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5748 && (inner_mode
== tmode
5749 || (! mode_dependent_address_p (XEXP (inner
, 0))
5750 && ! MEM_VOLATILE_P (inner
))))))
5752 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5753 field. If the original and current mode are the same, we need not
5754 adjust the offset. Otherwise, we do if bytes big endian.
5756 If INNER is not a MEM, get a piece consisting of just the field
5757 of interest (in this case POS % BITS_PER_WORD must be 0). */
5759 if (GET_CODE (inner
) == MEM
)
5762 /* POS counts from lsb, but make OFFSET count in memory order. */
5763 if (BYTES_BIG_ENDIAN
)
5764 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5766 offset
= pos
/ BITS_PER_UNIT
;
5768 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
5769 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5770 MEM_COPY_ATTRIBUTES (new, inner
);
5772 else if (GET_CODE (inner
) == REG
)
5774 /* We can't call gen_lowpart_for_combine here since we always want
5775 a SUBREG and it would sometimes return a new hard register. */
5776 if (tmode
!= inner_mode
)
5777 new = gen_rtx_SUBREG (tmode
, inner
,
5779 && (GET_MODE_SIZE (inner_mode
)
5781 ? (((GET_MODE_SIZE (inner_mode
)
5782 - GET_MODE_SIZE (tmode
))
5784 - pos
/ BITS_PER_WORD
)
5785 : pos
/ BITS_PER_WORD
));
5790 new = force_to_mode (inner
, tmode
,
5791 len
>= HOST_BITS_PER_WIDE_INT
5792 ? GET_MODE_MASK (tmode
)
5793 : ((HOST_WIDE_INT
) 1 << len
) - 1,
5796 /* If this extraction is going into the destination of a SET,
5797 make a STRICT_LOW_PART unless we made a MEM. */
5800 return (GET_CODE (new) == MEM
? new
5801 : (GET_CODE (new) != SUBREG
5802 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5803 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5805 /* Otherwise, sign- or zero-extend unless we already are in the
5808 return (mode
== tmode
? new
5809 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5813 /* Unless this is a COMPARE or we have a funny memory reference,
5814 don't do anything with zero-extending field extracts starting at
5815 the low-order bit since they are simple AND operations. */
5816 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5817 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5820 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5821 we would be spanning bytes or if the position is not a constant and the
5822 length is not 1. In all other cases, we would only be going outside
5823 our object in cases when an original shift would have been
5825 if (! spans_byte
&& GET_CODE (inner
) == MEM
5826 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5827 || (pos_rtx
!= 0 && len
!= 1)))
5830 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5831 and the mode for the result. */
5835 wanted_inner_reg_mode
5836 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
5837 if (wanted_inner_reg_mode
== VOIDmode
)
5838 wanted_inner_reg_mode
= word_mode
;
5840 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
5841 if (pos_mode
== VOIDmode
)
5842 pos_mode
= word_mode
;
5844 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
5845 if (extraction_mode
== VOIDmode
)
5846 extraction_mode
= word_mode
;
5851 if (! in_dest
&& unsignedp
)
5853 wanted_inner_reg_mode
5854 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
5855 if (wanted_inner_reg_mode
== VOIDmode
)
5856 wanted_inner_reg_mode
= word_mode
;
5858 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
5859 if (pos_mode
== VOIDmode
)
5860 pos_mode
= word_mode
;
5862 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
5863 if (extraction_mode
== VOIDmode
)
5864 extraction_mode
= word_mode
;
5869 if (! in_dest
&& ! unsignedp
)
5871 wanted_inner_reg_mode
5872 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
5873 if (wanted_inner_reg_mode
== VOIDmode
)
5874 wanted_inner_reg_mode
= word_mode
;
5876 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
5877 if (pos_mode
== VOIDmode
)
5878 pos_mode
= word_mode
;
5880 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
5881 if (extraction_mode
== VOIDmode
)
5882 extraction_mode
= word_mode
;
5886 /* Never narrow an object, since that might not be safe. */
5888 if (mode
!= VOIDmode
5889 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
5890 extraction_mode
= mode
;
5892 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
5893 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5894 pos_mode
= GET_MODE (pos_rtx
);
5896 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5897 if we have to change the mode of memory and cannot, the desired mode is
5899 if (GET_CODE (inner
) != MEM
)
5900 wanted_inner_mode
= wanted_inner_reg_mode
;
5901 else if (inner_mode
!= wanted_inner_mode
5902 && (mode_dependent_address_p (XEXP (inner
, 0))
5903 || MEM_VOLATILE_P (inner
)))
5904 wanted_inner_mode
= extraction_mode
;
5908 if (BITS_BIG_ENDIAN
)
5910 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5911 BITS_BIG_ENDIAN style. If position is constant, compute new
5912 position. Otherwise, build subtraction.
5913 Note that POS is relative to the mode of the original argument.
5914 If it's a MEM we need to recompute POS relative to that.
5915 However, if we're extracting from (or inserting into) a register,
5916 we want to recompute POS relative to wanted_inner_mode. */
5917 int width
= (GET_CODE (inner
) == MEM
5918 ? GET_MODE_BITSIZE (is_mode
)
5919 : GET_MODE_BITSIZE (wanted_inner_mode
));
5922 pos
= width
- len
- pos
;
5925 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
5926 GEN_INT (width
- len
), pos_rtx
);
5927 /* POS may be less than 0 now, but we check for that below.
5928 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5931 /* If INNER has a wider mode, make it smaller. If this is a constant
5932 extract, try to adjust the byte to point to the byte containing
5934 if (wanted_inner_mode
!= VOIDmode
5935 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
5936 && ((GET_CODE (inner
) == MEM
5937 && (inner_mode
== wanted_inner_mode
5938 || (! mode_dependent_address_p (XEXP (inner
, 0))
5939 && ! MEM_VOLATILE_P (inner
))))))
5943 /* The computations below will be correct if the machine is big
5944 endian in both bits and bytes or little endian in bits and bytes.
5945 If it is mixed, we must adjust. */
5947 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5948 adjust OFFSET to compensate. */
5949 if (BYTES_BIG_ENDIAN
5951 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
5952 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
5954 /* If this is a constant position, we can move to the desired byte. */
5957 offset
+= pos
/ BITS_PER_UNIT
;
5958 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
5961 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
5963 && is_mode
!= wanted_inner_mode
)
5964 offset
= (GET_MODE_SIZE (is_mode
)
5965 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
5967 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
5969 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
5970 plus_constant (XEXP (inner
, 0), offset
));
5971 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
5972 MEM_COPY_ATTRIBUTES (newmem
, inner
);
5977 /* If INNER is not memory, we can always get it into the proper mode. If we
5978 are changing its mode, POS must be a constant and smaller than the size
5980 else if (GET_CODE (inner
) != MEM
)
5982 if (GET_MODE (inner
) != wanted_inner_mode
5984 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
5987 inner
= force_to_mode (inner
, wanted_inner_mode
,
5989 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
5990 ? GET_MODE_MASK (wanted_inner_mode
)
5991 : (((HOST_WIDE_INT
) 1 << len
) - 1) << orig_pos
,
5995 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5996 have to zero extend. Otherwise, we can just use a SUBREG. */
5998 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5999 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6000 else if (pos_rtx
!= 0
6001 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6002 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6004 /* Make POS_RTX unless we already have it and it is correct. If we don't
6005 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6007 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6008 pos_rtx
= orig_pos_rtx
;
6010 else if (pos_rtx
== 0)
6011 pos_rtx
= GEN_INT (pos
);
6013 /* Make the required operation. See if we can use existing rtx. */
6014 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6015 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6017 new = gen_lowpart_for_combine (mode
, new);
6022 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6023 with any other operations in X. Return X without that shift if so. */
6026 extract_left_shift (x
, count
)
6030 enum rtx_code code
= GET_CODE (x
);
6031 enum machine_mode mode
= GET_MODE (x
);
6037 /* This is the shift itself. If it is wide enough, we will return
6038 either the value being shifted if the shift count is equal to
6039 COUNT or a shift for the difference. */
6040 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6041 && INTVAL (XEXP (x
, 1)) >= count
)
6042 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6043 INTVAL (XEXP (x
, 1)) - count
);
6047 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6048 return gen_unary (code
, mode
, mode
, tem
);
6052 case PLUS
: case IOR
: case XOR
: case AND
:
6053 /* If we can safely shift this constant and we find the inner shift,
6054 make a new operation. */
6055 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6056 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6057 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6058 return gen_binary (code
, mode
, tem
,
6059 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6070 /* Look at the expression rooted at X. Look for expressions
6071 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6072 Form these expressions.
6074 Return the new rtx, usually just X.
6076 Also, for machines like the Vax that don't have logical shift insns,
6077 try to convert logical to arithmetic shift operations in cases where
6078 they are equivalent. This undoes the canonicalizations to logical
6079 shifts done elsewhere.
6081 We try, as much as possible, to re-use rtl expressions to save memory.
6083 IN_CODE says what kind of expression we are processing. Normally, it is
6084 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6085 being kludges), it is MEM. When processing the arguments of a comparison
6086 or a COMPARE against zero, it is COMPARE. */
6089 make_compound_operation (x
, in_code
)
6091 enum rtx_code in_code
;
6093 enum rtx_code code
= GET_CODE (x
);
6094 enum machine_mode mode
= GET_MODE (x
);
6095 int mode_width
= GET_MODE_BITSIZE (mode
);
6097 enum rtx_code next_code
;
6103 /* Select the code to be used in recursive calls. Once we are inside an
6104 address, we stay there. If we have a comparison, set to COMPARE,
6105 but once inside, go back to our default of SET. */
6107 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6108 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6109 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6110 : in_code
== COMPARE
? SET
: in_code
);
6112 /* Process depending on the code of this operation. If NEW is set
6113 non-zero, it will be returned. */
6118 /* Convert shifts by constants into multiplications if inside
6120 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6121 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6122 && INTVAL (XEXP (x
, 1)) >= 0)
6124 new = make_compound_operation (XEXP (x
, 0), next_code
);
6125 new = gen_rtx_combine (MULT
, mode
, new,
6126 GEN_INT ((HOST_WIDE_INT
) 1
6127 << INTVAL (XEXP (x
, 1))));
6132 /* If the second operand is not a constant, we can't do anything
6134 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6137 /* If the constant is a power of two minus one and the first operand
6138 is a logical right shift, make an extraction. */
6139 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6140 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6142 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6143 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6144 0, in_code
== COMPARE
);
6147 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6148 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6149 && subreg_lowpart_p (XEXP (x
, 0))
6150 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6151 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6153 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6155 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6156 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6157 0, in_code
== COMPARE
);
6159 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6160 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6161 || GET_CODE (XEXP (x
, 0)) == IOR
)
6162 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6163 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6164 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6166 /* Apply the distributive law, and then try to make extractions. */
6167 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6168 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6170 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6172 new = make_compound_operation (new, in_code
);
6175 /* If we are have (and (rotate X C) M) and C is larger than the number
6176 of bits in M, this is an extraction. */
6178 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6179 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6180 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6181 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6183 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6184 new = make_extraction (mode
, new,
6185 (GET_MODE_BITSIZE (mode
)
6186 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6187 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6190 /* On machines without logical shifts, if the operand of the AND is
6191 a logical shift and our mask turns off all the propagated sign
6192 bits, we can replace the logical shift with an arithmetic shift. */
6193 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6194 && (lshr_optab
->handlers
[(int) mode
].insn_code
6195 == CODE_FOR_nothing
)
6196 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6197 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6198 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6199 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6200 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6202 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6204 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6205 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6207 gen_rtx_combine (ASHIFTRT
, mode
,
6208 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6210 XEXP (XEXP (x
, 0), 1)));
6213 /* If the constant is one less than a power of two, this might be
6214 representable by an extraction even if no shift is present.
6215 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6216 we are in a COMPARE. */
6217 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6218 new = make_extraction (mode
,
6219 make_compound_operation (XEXP (x
, 0),
6221 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6223 /* If we are in a comparison and this is an AND with a power of two,
6224 convert this into the appropriate bit extract. */
6225 else if (in_code
== COMPARE
6226 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6227 new = make_extraction (mode
,
6228 make_compound_operation (XEXP (x
, 0),
6230 i
, NULL_RTX
, 1, 1, 0, 1);
6235 /* If the sign bit is known to be zero, replace this with an
6236 arithmetic shift. */
6237 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6238 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6239 && mode_width
<= HOST_BITS_PER_WIDE_INT
6240 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6242 new = gen_rtx_combine (ASHIFTRT
, mode
,
6243 make_compound_operation (XEXP (x
, 0),
6249 /* ... fall through ... */
6255 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6256 this is a SIGN_EXTRACT. */
6257 if (GET_CODE (rhs
) == CONST_INT
6258 && GET_CODE (lhs
) == ASHIFT
6259 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6260 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6262 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6263 new = make_extraction (mode
, new,
6264 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6265 NULL_RTX
, mode_width
- INTVAL (rhs
),
6266 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6269 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6270 If so, try to merge the shifts into a SIGN_EXTEND. We could
6271 also do this for some cases of SIGN_EXTRACT, but it doesn't
6272 seem worth the effort; the case checked for occurs on Alpha. */
6274 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6275 && ! (GET_CODE (lhs
) == SUBREG
6276 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6277 && GET_CODE (rhs
) == CONST_INT
6278 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6279 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6280 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6281 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6282 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6287 /* Call ourselves recursively on the inner expression. If we are
6288 narrowing the object and it has a different RTL code from
6289 what it originally did, do this SUBREG as a force_to_mode. */
6291 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6292 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6293 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6294 && subreg_lowpart_p (x
))
6296 rtx newer
= force_to_mode (tem
, mode
,
6297 GET_MODE_MASK (mode
), NULL_RTX
, 0);
6299 /* If we have something other than a SUBREG, we might have
6300 done an expansion, so rerun outselves. */
6301 if (GET_CODE (newer
) != SUBREG
)
6302 newer
= make_compound_operation (newer
, in_code
);
6307 /* If this is a paradoxical subreg, and the new code is a sign or
6308 zero extension, omit the subreg and widen the extension. If it
6309 is a regular subreg, we can still get rid of the subreg by not
6310 widening so much, or in fact removing the extension entirely. */
6311 if ((GET_CODE (tem
) == SIGN_EXTEND
6312 || GET_CODE (tem
) == ZERO_EXTEND
)
6313 && subreg_lowpart_p (x
))
6315 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6316 || (GET_MODE_SIZE (mode
) >
6317 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6318 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6320 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6331 x
= gen_lowpart_for_combine (mode
, new);
6332 code
= GET_CODE (x
);
6335 /* Now recursively process each operand of this operation. */
6336 fmt
= GET_RTX_FORMAT (code
);
6337 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6340 new = make_compound_operation (XEXP (x
, i
), next_code
);
6341 SUBST (XEXP (x
, i
), new);
6347 /* Given M see if it is a value that would select a field of bits
6348 within an item, but not the entire word. Return -1 if not.
6349 Otherwise, return the starting position of the field, where 0 is the
6352 *PLEN is set to the length of the field. */
6355 get_pos_from_mask (m
, plen
)
6356 unsigned HOST_WIDE_INT m
;
6359 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6360 int pos
= exact_log2 (m
& - m
);
6365 /* Now shift off the low-order zero bits and see if we have a power of
6367 *plen
= exact_log2 ((m
>> pos
) + 1);
6375 /* See if X can be simplified knowing that we will only refer to it in
6376 MODE and will only refer to those bits that are nonzero in MASK.
6377 If other bits are being computed or if masking operations are done
6378 that select a superset of the bits in MASK, they can sometimes be
6381 Return a possibly simplified expression, but always convert X to
6382 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6384 Also, if REG is non-zero and X is a register equal in value to REG,
6387 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6388 are all off in X. This is used when X will be complemented, by either
6389 NOT, NEG, or XOR. */
6392 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6394 enum machine_mode mode
;
6395 unsigned HOST_WIDE_INT mask
;
6399 enum rtx_code code
= GET_CODE (x
);
6400 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6401 enum machine_mode op_mode
;
6402 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6405 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6406 code below will do the wrong thing since the mode of such an
6407 expression is VOIDmode.
6409 Also do nothing if X is a CLOBBER; this can happen if X was
6410 the return value from a call to gen_lowpart_for_combine. */
6411 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6414 /* We want to perform the operation is its present mode unless we know
6415 that the operation is valid in MODE, in which case we do the operation
6417 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6418 && code_to_optab
[(int) code
] != 0
6419 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6420 != CODE_FOR_nothing
))
6421 ? mode
: GET_MODE (x
));
6423 /* It is not valid to do a right-shift in a narrower mode
6424 than the one it came in with. */
6425 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6426 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6427 op_mode
= GET_MODE (x
);
6429 /* Truncate MASK to fit OP_MODE. */
6431 mask
&= GET_MODE_MASK (op_mode
);
6433 /* When we have an arithmetic operation, or a shift whose count we
6434 do not know, we need to assume that all bit the up to the highest-order
6435 bit in MASK will be needed. This is how we form such a mask. */
6437 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6438 ? GET_MODE_MASK (op_mode
)
6439 : ((HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1)) - 1);
6441 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
6443 /* Determine what bits of X are guaranteed to be (non)zero. */
6444 nonzero
= nonzero_bits (x
, mode
);
6446 /* If none of the bits in X are needed, return a zero. */
6447 if (! just_select
&& (nonzero
& mask
) == 0)
6450 /* If X is a CONST_INT, return a new one. Do this here since the
6451 test below will fail. */
6452 if (GET_CODE (x
) == CONST_INT
)
6454 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6455 int width
= GET_MODE_BITSIZE (mode
);
6457 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6458 number, sign extend it. */
6459 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6460 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6461 cval
|= (HOST_WIDE_INT
) -1 << width
;
6463 return GEN_INT (cval
);
6466 /* If X is narrower than MODE and we want all the bits in X's mode, just
6467 get X in the proper mode. */
6468 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6469 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
6470 return gen_lowpart_for_combine (mode
, x
);
6472 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6473 MASK are already known to be zero in X, we need not do anything. */
6474 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
6480 /* If X is a (clobber (const_int)), return it since we know we are
6481 generating something that won't match. */
6485 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6486 spanned the boundary of the MEM. If we are now masking so it is
6487 within that boundary, we don't need the USE any more. */
6488 if (! BITS_BIG_ENDIAN
6489 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6490 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6497 x
= expand_compound_operation (x
);
6498 if (GET_CODE (x
) != code
)
6499 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6503 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6504 || rtx_equal_p (reg
, get_last_value (x
))))
6509 if (subreg_lowpart_p (x
)
6510 /* We can ignore the effect of this SUBREG if it narrows the mode or
6511 if the constant masks to zero all the bits the mode doesn't
6513 && ((GET_MODE_SIZE (GET_MODE (x
))
6514 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6516 & GET_MODE_MASK (GET_MODE (x
))
6517 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6518 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6522 /* If this is an AND with a constant, convert it into an AND
6523 whose constant is the AND of that constant with MASK. If it
6524 remains an AND of MASK, delete it since it is redundant. */
6526 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6528 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6529 mask
& INTVAL (XEXP (x
, 1)));
6531 /* If X is still an AND, see if it is an AND with a mask that
6532 is just some low-order bits. If so, and it is MASK, we don't
6535 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6536 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6539 /* If it remains an AND, try making another AND with the bits
6540 in the mode mask that aren't in MASK turned on. If the
6541 constant in the AND is wide enough, this might make a
6542 cheaper constant. */
6544 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6545 && GET_MODE_MASK (GET_MODE (x
)) != mask
6546 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6548 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6549 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
6550 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6553 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6554 number, sign extend it. */
6555 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6556 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6557 cval
|= (HOST_WIDE_INT
) -1 << width
;
6559 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6560 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6570 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6571 low-order bits (as in an alignment operation) and FOO is already
6572 aligned to that boundary, mask C1 to that boundary as well.
6573 This may eliminate that PLUS and, later, the AND. */
6576 int width
= GET_MODE_BITSIZE (mode
);
6577 unsigned HOST_WIDE_INT smask
= mask
;
6579 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6580 number, sign extend it. */
6582 if (width
< HOST_BITS_PER_WIDE_INT
6583 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6584 smask
|= (HOST_WIDE_INT
) -1 << width
;
6586 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6587 && exact_log2 (- smask
) >= 0)
6591 && (XEXP (x
, 0) == stack_pointer_rtx
6592 || XEXP (x
, 0) == frame_pointer_rtx
))
6594 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6595 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6597 sp_mask
&= ~ (sp_alignment
- 1);
6598 if ((sp_mask
& ~ smask
) == 0
6599 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~ smask
) != 0)
6600 return force_to_mode (plus_constant (XEXP (x
, 0),
6601 ((INTVAL (XEXP (x
, 1)) -
6602 STACK_BIAS
) & smask
)
6604 mode
, smask
, reg
, next_select
);
6607 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~ smask
) == 0
6608 && (INTVAL (XEXP (x
, 1)) & ~ smask
) != 0)
6609 return force_to_mode (plus_constant (XEXP (x
, 0),
6610 (INTVAL (XEXP (x
, 1))
6612 mode
, smask
, reg
, next_select
);
6616 /* ... fall through ... */
6620 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6621 most significant bit in MASK since carries from those bits will
6622 affect the bits we are interested in. */
6628 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6629 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6630 operation which may be a bitfield extraction. Ensure that the
6631 constant we form is not wider than the mode of X. */
6633 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6634 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6635 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6636 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6637 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6638 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6639 + floor_log2 (INTVAL (XEXP (x
, 1))))
6640 < GET_MODE_BITSIZE (GET_MODE (x
)))
6641 && (INTVAL (XEXP (x
, 1))
6642 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6644 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6645 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6646 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6647 XEXP (XEXP (x
, 0), 0), temp
);
6648 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6649 XEXP (XEXP (x
, 0), 1));
6650 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6654 /* For most binary operations, just propagate into the operation and
6655 change the mode if we have an operation of that mode. */
6657 op0
= gen_lowpart_for_combine (op_mode
,
6658 force_to_mode (XEXP (x
, 0), mode
, mask
,
6660 op1
= gen_lowpart_for_combine (op_mode
,
6661 force_to_mode (XEXP (x
, 1), mode
, mask
,
6664 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6665 MASK since OP1 might have been sign-extended but we never want
6666 to turn on extra bits, since combine might have previously relied
6667 on them being off. */
6668 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6669 && (INTVAL (op1
) & mask
) != 0)
6670 op1
= GEN_INT (INTVAL (op1
) & mask
);
6672 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6673 x
= gen_binary (code
, op_mode
, op0
, op1
);
6677 /* For left shifts, do the same, but just for the first operand.
6678 However, we cannot do anything with shifts where we cannot
6679 guarantee that the counts are smaller than the size of the mode
6680 because such a count will have a different meaning in a
6683 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6684 && INTVAL (XEXP (x
, 1)) >= 0
6685 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6686 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6687 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6688 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6691 /* If the shift count is a constant and we can do arithmetic in
6692 the mode of the shift, refine which bits we need. Otherwise, use the
6693 conservative form of the mask. */
6694 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6695 && INTVAL (XEXP (x
, 1)) >= 0
6696 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6697 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6698 mask
>>= INTVAL (XEXP (x
, 1));
6702 op0
= gen_lowpart_for_combine (op_mode
,
6703 force_to_mode (XEXP (x
, 0), op_mode
,
6704 mask
, reg
, next_select
));
6706 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6707 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6711 /* Here we can only do something if the shift count is a constant,
6712 this shift constant is valid for the host, and we can do arithmetic
6715 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6716 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6717 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6719 rtx inner
= XEXP (x
, 0);
6721 /* Select the mask of the bits we need for the shift operand. */
6722 mask
<<= INTVAL (XEXP (x
, 1));
6724 /* We can only change the mode of the shift if we can do arithmetic
6725 in the mode of the shift and MASK is no wider than the width of
6727 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6728 || (mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
6729 op_mode
= GET_MODE (x
);
6731 inner
= force_to_mode (inner
, op_mode
, mask
, reg
, next_select
);
6733 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6734 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6737 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6738 shift and AND produces only copies of the sign bit (C2 is one less
6739 than a power of two), we can do this with just a shift. */
6741 if (GET_CODE (x
) == LSHIFTRT
6742 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6743 && ((INTVAL (XEXP (x
, 1))
6744 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6745 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6746 && exact_log2 (mask
+ 1) >= 0
6747 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6748 >= exact_log2 (mask
+ 1)))
6749 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6750 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6751 - exact_log2 (mask
+ 1)));
6756 /* If we are just looking for the sign bit, we don't need this shift at
6757 all, even if it has a variable count. */
6758 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6759 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6760 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6761 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6763 /* If this is a shift by a constant, get a mask that contains those bits
6764 that are not copies of the sign bit. We then have two cases: If
6765 MASK only includes those bits, this can be a logical shift, which may
6766 allow simplifications. If MASK is a single-bit field not within
6767 those bits, we are requesting a copy of the sign bit and hence can
6768 shift the sign bit to the appropriate location. */
6770 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6771 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6775 /* If the considered data is wider then HOST_WIDE_INT, we can't
6776 represent a mask for all its bits in a single scalar.
6777 But we only care about the lower bits, so calculate these. */
6779 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6781 nonzero
= ~ (HOST_WIDE_INT
) 0;
6783 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6784 is the number of bits a full-width mask would have set.
6785 We need only shift if these are fewer than nonzero can
6786 hold. If not, we must keep all bits set in nonzero. */
6788 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6789 < HOST_BITS_PER_WIDE_INT
)
6790 nonzero
>>= INTVAL (XEXP (x
, 1))
6791 + HOST_BITS_PER_WIDE_INT
6792 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6796 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6797 nonzero
>>= INTVAL (XEXP (x
, 1));
6800 if ((mask
& ~ nonzero
) == 0
6801 || (i
= exact_log2 (mask
)) >= 0)
6803 x
= simplify_shift_const
6804 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6805 i
< 0 ? INTVAL (XEXP (x
, 1))
6806 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
6808 if (GET_CODE (x
) != ASHIFTRT
)
6809 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6813 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6814 even if the shift count isn't a constant. */
6816 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
6820 /* If this is a zero- or sign-extension operation that just affects bits
6821 we don't care about, remove it. Be sure the call above returned
6822 something that is still a shift. */
6824 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
6825 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6826 && INTVAL (XEXP (x
, 1)) >= 0
6827 && (INTVAL (XEXP (x
, 1))
6828 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
6829 && GET_CODE (XEXP (x
, 0)) == ASHIFT
6830 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6831 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
6832 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
6839 /* If the shift count is constant and we can do computations
6840 in the mode of X, compute where the bits we care about are.
6841 Otherwise, we can't do anything. Don't change the mode of
6842 the shift or propagate MODE into the shift, though. */
6843 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6844 && INTVAL (XEXP (x
, 1)) >= 0)
6846 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
6847 GET_MODE (x
), GEN_INT (mask
),
6849 if (temp
&& GET_CODE(temp
) == CONST_INT
)
6851 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
6852 INTVAL (temp
), reg
, next_select
));
6857 /* If we just want the low-order bit, the NEG isn't needed since it
6858 won't change the low-order bit. */
6860 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
6862 /* We need any bits less significant than the most significant bit in
6863 MASK since carries from those bits will affect the bits we are
6869 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6870 same as the XOR case above. Ensure that the constant we form is not
6871 wider than the mode of X. */
6873 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6874 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6875 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6876 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
6877 < GET_MODE_BITSIZE (GET_MODE (x
)))
6878 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
6880 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
6881 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
6882 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
6884 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6887 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6888 use the full mask inside the NOT. */
6892 op0
= gen_lowpart_for_combine (op_mode
,
6893 force_to_mode (XEXP (x
, 0), mode
, mask
,
6895 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6896 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
6900 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6901 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6902 which is equal to STORE_FLAG_VALUE. */
6903 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
6904 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
6905 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
6906 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6911 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6912 written in a narrower mode. We play it safe and do not do so. */
6915 gen_lowpart_for_combine (GET_MODE (x
),
6916 force_to_mode (XEXP (x
, 1), mode
,
6917 mask
, reg
, next_select
)));
6919 gen_lowpart_for_combine (GET_MODE (x
),
6920 force_to_mode (XEXP (x
, 2), mode
,
6921 mask
, reg
,next_select
)));
6928 /* Ensure we return a value of the proper mode. */
6929 return gen_lowpart_for_combine (mode
, x
);
6932 /* Return nonzero if X is an expression that has one of two values depending on
6933 whether some other value is zero or nonzero. In that case, we return the
6934 value that is being tested, *PTRUE is set to the value if the rtx being
6935 returned has a nonzero value, and *PFALSE is set to the other alternative.
6937 If we return zero, we set *PTRUE and *PFALSE to X. */
6940 if_then_else_cond (x
, ptrue
, pfalse
)
6942 rtx
*ptrue
, *pfalse
;
6944 enum machine_mode mode
= GET_MODE (x
);
6945 enum rtx_code code
= GET_CODE (x
);
6946 int size
= GET_MODE_BITSIZE (mode
);
6947 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
6948 unsigned HOST_WIDE_INT nz
;
6950 /* If we are comparing a value against zero, we are done. */
6951 if ((code
== NE
|| code
== EQ
)
6952 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
6954 *ptrue
= (code
== NE
) ? const1_rtx
: const0_rtx
;
6955 *pfalse
= (code
== NE
) ? const0_rtx
: const1_rtx
;
6959 /* If this is a unary operation whose operand has one of two values, apply
6960 our opcode to compute those values. */
6961 else if (GET_RTX_CLASS (code
) == '1'
6962 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
6964 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
6965 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
6969 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6970 make can't possibly match and would suppress other optimizations. */
6971 else if (code
== COMPARE
)
6974 /* If this is a binary operation, see if either side has only one of two
6975 values. If either one does or if both do and they are conditional on
6976 the same value, compute the new true and false values. */
6977 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
6978 || GET_RTX_CLASS (code
) == '<')
6980 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
6981 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
6983 if ((cond0
!= 0 || cond1
!= 0)
6984 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
6986 /* If if_then_else_cond returned zero, then true/false are the
6987 same rtl. We must copy one of them to prevent invalid rtl
6990 true0
= copy_rtx (true0
);
6991 else if (cond1
== 0)
6992 true1
= copy_rtx (true1
);
6994 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
6995 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
6996 return cond0
? cond0
: cond1
;
6999 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7000 operands is zero when the other is non-zero, and vice-versa,
7001 and STORE_FLAG_VALUE is 1 or -1. */
7003 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7004 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7006 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7008 rtx op0
= XEXP (XEXP (x
, 0), 1);
7009 rtx op1
= XEXP (XEXP (x
, 1), 1);
7011 cond0
= XEXP (XEXP (x
, 0), 0);
7012 cond1
= XEXP (XEXP (x
, 1), 0);
7014 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7015 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7016 && reversible_comparison_p (cond1
)
7017 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7018 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7019 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7020 || ((swap_condition (GET_CODE (cond0
))
7021 == reverse_condition (GET_CODE (cond1
)))
7022 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7023 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7024 && ! side_effects_p (x
))
7026 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7027 *pfalse
= gen_binary (MULT
, mode
,
7029 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7035 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7037 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7038 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7039 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7041 cond0
= XEXP (XEXP (x
, 0), 0);
7042 cond1
= XEXP (XEXP (x
, 1), 0);
7044 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7045 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7046 && reversible_comparison_p (cond1
)
7047 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7048 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7049 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7050 || ((swap_condition (GET_CODE (cond0
))
7051 == reverse_condition (GET_CODE (cond1
)))
7052 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7053 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7054 && ! side_effects_p (x
))
7056 *ptrue
= *pfalse
= const0_rtx
;
7062 else if (code
== IF_THEN_ELSE
)
7064 /* If we have IF_THEN_ELSE already, extract the condition and
7065 canonicalize it if it is NE or EQ. */
7066 cond0
= XEXP (x
, 0);
7067 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7068 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7069 return XEXP (cond0
, 0);
7070 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7072 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7073 return XEXP (cond0
, 0);
7079 /* If X is a normal SUBREG with both inner and outer modes integral,
7080 we can narrow both the true and false values of the inner expression,
7081 if there is a condition. */
7082 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7083 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7084 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7085 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7088 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7090 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7095 /* If X is a constant, this isn't special and will cause confusions
7096 if we treat it as such. Likewise if it is equivalent to a constant. */
7097 else if (CONSTANT_P (x
)
7098 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7101 /* If X is known to be either 0 or -1, those are the true and
7102 false values when testing X. */
7103 else if (num_sign_bit_copies (x
, mode
) == size
)
7105 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7109 /* Likewise for 0 or a single bit. */
7110 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7112 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7116 /* Otherwise fail; show no condition with true and false values the same. */
7117 *ptrue
= *pfalse
= x
;
7121 /* Return the value of expression X given the fact that condition COND
7122 is known to be true when applied to REG as its first operand and VAL
7123 as its second. X is known to not be shared and so can be modified in
7126 We only handle the simplest cases, and specifically those cases that
7127 arise with IF_THEN_ELSE expressions. */
7130 known_cond (x
, cond
, reg
, val
)
7135 enum rtx_code code
= GET_CODE (x
);
7140 if (side_effects_p (x
))
7143 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
7146 /* If X is (abs REG) and we know something about REG's relationship
7147 with zero, we may be able to simplify this. */
7149 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7152 case GE
: case GT
: case EQ
:
7155 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7161 /* The only other cases we handle are MIN, MAX, and comparisons if the
7162 operands are the same as REG and VAL. */
7164 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7166 if (rtx_equal_p (XEXP (x
, 0), val
))
7167 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7169 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7171 if (GET_RTX_CLASS (code
) == '<')
7172 return (comparison_dominates_p (cond
, code
) ? const_true_rtx
7173 : (comparison_dominates_p (cond
,
7174 reverse_condition (code
))
7177 else if (code
== SMAX
|| code
== SMIN
7178 || code
== UMIN
|| code
== UMAX
)
7180 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7182 if (code
== SMAX
|| code
== UMAX
)
7183 cond
= reverse_condition (cond
);
7188 return unsignedp
? x
: XEXP (x
, 1);
7190 return unsignedp
? x
: XEXP (x
, 0);
7192 return unsignedp
? XEXP (x
, 1) : x
;
7194 return unsignedp
? XEXP (x
, 0) : x
;
7202 fmt
= GET_RTX_FORMAT (code
);
7203 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7206 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7207 else if (fmt
[i
] == 'E')
7208 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7209 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7216 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7217 assignment as a field assignment. */
7220 rtx_equal_for_field_assignment_p (x
, y
)
7224 if (x
== y
|| rtx_equal_p (x
, y
))
7227 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7230 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7231 Note that all SUBREGs of MEM are paradoxical; otherwise they
7232 would have been rewritten. */
7233 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7234 && GET_CODE (SUBREG_REG (y
)) == MEM
7235 && rtx_equal_p (SUBREG_REG (y
),
7236 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7239 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7240 && GET_CODE (SUBREG_REG (x
)) == MEM
7241 && rtx_equal_p (SUBREG_REG (x
),
7242 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7245 /* We used to see if get_last_value of X and Y were the same but that's
7246 not correct. In one direction, we'll cause the assignment to have
7247 the wrong destination and in the case, we'll import a register into this
7248 insn that might have already have been dead. So fail if none of the
7249 above cases are true. */
7253 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7254 Return that assignment if so.
7256 We only handle the most common cases. */
7259 make_field_assignment (x
)
7262 rtx dest
= SET_DEST (x
);
7263 rtx src
= SET_SRC (x
);
7269 enum machine_mode mode
;
7271 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7272 a clear of a one-bit field. We will have changed it to
7273 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7276 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7277 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7278 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7279 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7281 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7284 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7288 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7289 && subreg_lowpart_p (XEXP (src
, 0))
7290 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7291 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7292 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7293 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7294 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7296 assign
= make_extraction (VOIDmode
, dest
, 0,
7297 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7300 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7304 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7306 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7307 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7308 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7310 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7313 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7317 /* The other case we handle is assignments into a constant-position
7318 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7319 a mask that has all one bits except for a group of zero bits and
7320 OTHER is known to have zeros where C1 has ones, this is such an
7321 assignment. Compute the position and length from C1. Shift OTHER
7322 to the appropriate position, force it to the required mode, and
7323 make the extraction. Check for the AND in both operands. */
7325 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7328 rhs
= expand_compound_operation (XEXP (src
, 0));
7329 lhs
= expand_compound_operation (XEXP (src
, 1));
7331 if (GET_CODE (rhs
) == AND
7332 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7333 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7334 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7335 else if (GET_CODE (lhs
) == AND
7336 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7337 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7338 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7342 pos
= get_pos_from_mask ((~ c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7343 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7344 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7345 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7348 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7352 /* The mode to use for the source is the mode of the assignment, or of
7353 what is inside a possible STRICT_LOW_PART. */
7354 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7355 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7357 /* Shift OTHER right POS places and make it the source, restricting it
7358 to the proper length and mode. */
7360 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7361 GET_MODE (src
), other
, pos
),
7363 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7364 ? GET_MODE_MASK (mode
)
7365 : ((HOST_WIDE_INT
) 1 << len
) - 1,
7368 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7371 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7375 apply_distributive_law (x
)
7378 enum rtx_code code
= GET_CODE (x
);
7379 rtx lhs
, rhs
, other
;
7381 enum rtx_code inner_code
;
7383 /* Distributivity is not true for floating point.
7384 It can change the value. So don't do it.
7385 -- rms and moshier@world.std.com. */
7386 if (FLOAT_MODE_P (GET_MODE (x
)))
7389 /* The outer operation can only be one of the following: */
7390 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7391 && code
!= PLUS
&& code
!= MINUS
)
7394 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7396 /* If either operand is a primitive we can't do anything, so get out
7398 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7399 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7402 lhs
= expand_compound_operation (lhs
);
7403 rhs
= expand_compound_operation (rhs
);
7404 inner_code
= GET_CODE (lhs
);
7405 if (inner_code
!= GET_CODE (rhs
))
7408 /* See if the inner and outer operations distribute. */
7415 /* These all distribute except over PLUS. */
7416 if (code
== PLUS
|| code
== MINUS
)
7421 if (code
!= PLUS
&& code
!= MINUS
)
7426 /* This is also a multiply, so it distributes over everything. */
7430 /* Non-paradoxical SUBREGs distributes over all operations, provided
7431 the inner modes and word numbers are the same, this is an extraction
7432 of a low-order part, we don't convert an fp operation to int or
7433 vice versa, and we would not be converting a single-word
7434 operation into a multi-word operation. The latter test is not
7435 required, but it prevents generating unneeded multi-word operations.
7436 Some of the previous tests are redundant given the latter test, but
7437 are retained because they are required for correctness.
7439 We produce the result slightly differently in this case. */
7441 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7442 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7443 || ! subreg_lowpart_p (lhs
)
7444 || (GET_MODE_CLASS (GET_MODE (lhs
))
7445 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7446 || (GET_MODE_SIZE (GET_MODE (lhs
))
7447 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7448 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7451 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7452 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7453 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7459 /* Set LHS and RHS to the inner operands (A and B in the example
7460 above) and set OTHER to the common operand (C in the example).
7461 These is only one way to do this unless the inner operation is
7463 if (GET_RTX_CLASS (inner_code
) == 'c'
7464 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7465 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7466 else if (GET_RTX_CLASS (inner_code
) == 'c'
7467 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7468 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7469 else if (GET_RTX_CLASS (inner_code
) == 'c'
7470 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7471 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7472 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7473 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7477 /* Form the new inner operation, seeing if it simplifies first. */
7478 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7480 /* There is one exception to the general way of distributing:
7481 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7482 if (code
== XOR
&& inner_code
== IOR
)
7485 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7488 /* We may be able to continuing distributing the result, so call
7489 ourselves recursively on the inner operation before forming the
7490 outer operation, which we return. */
7491 return gen_binary (inner_code
, GET_MODE (x
),
7492 apply_distributive_law (tem
), other
);
7495 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7498 Return an equivalent form, if different from X. Otherwise, return X. If
7499 X is zero, we are to always construct the equivalent form. */
7502 simplify_and_const_int (x
, mode
, varop
, constop
)
7504 enum machine_mode mode
;
7506 unsigned HOST_WIDE_INT constop
;
7508 unsigned HOST_WIDE_INT nonzero
;
7511 /* Simplify VAROP knowing that we will be only looking at some of the
7513 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7515 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7516 CONST_INT, we are done. */
7517 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7520 /* See what bits may be nonzero in VAROP. Unlike the general case of
7521 a call to nonzero_bits, here we don't care about bits outside
7524 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7525 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7527 /* Turn off all bits in the constant that are known to already be zero.
7528 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7529 which is tested below. */
7533 /* If we don't have any bits left, return zero. */
7537 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7538 a power of two, we can replace this with a ASHIFT. */
7539 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7540 && (i
= exact_log2 (constop
)) >= 0)
7541 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7543 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7544 or XOR, then try to apply the distributive law. This may eliminate
7545 operations if either branch can be simplified because of the AND.
7546 It may also make some cases more complex, but those cases probably
7547 won't match a pattern either with or without this. */
7549 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7551 gen_lowpart_for_combine
7553 apply_distributive_law
7554 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7555 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7556 XEXP (varop
, 0), constop
),
7557 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7558 XEXP (varop
, 1), constop
))));
7560 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7561 if we already had one (just check for the simplest cases). */
7562 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7563 && GET_MODE (XEXP (x
, 0)) == mode
7564 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7565 varop
= XEXP (x
, 0);
7567 varop
= gen_lowpart_for_combine (mode
, varop
);
7569 /* If we can't make the SUBREG, try to return what we were given. */
7570 if (GET_CODE (varop
) == CLOBBER
)
7571 return x
? x
: varop
;
7573 /* If we are only masking insignificant bits, return VAROP. */
7574 if (constop
== nonzero
)
7577 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7578 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7579 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7583 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7584 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7585 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7587 SUBST (XEXP (x
, 0), varop
);
7593 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7594 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7595 is less useful. We can't allow both, because that results in exponential
7596 run time recursion. There is a nullstone testcase that triggered
7597 this. This macro avoids accidental uses of num_sign_bit_copies. */
7598 #define num_sign_bit_copies()
7600 /* Given an expression, X, compute which bits in X can be non-zero.
7601 We don't care about bits outside of those defined in MODE.
7603 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7604 a shift, AND, or zero_extract, we can do better. */
7606 static unsigned HOST_WIDE_INT
7607 nonzero_bits (x
, mode
)
7609 enum machine_mode mode
;
7611 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7612 unsigned HOST_WIDE_INT inner_nz
;
7614 int mode_width
= GET_MODE_BITSIZE (mode
);
7617 /* For floating-point values, assume all bits are needed. */
7618 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7621 /* If X is wider than MODE, use its mode instead. */
7622 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7624 mode
= GET_MODE (x
);
7625 nonzero
= GET_MODE_MASK (mode
);
7626 mode_width
= GET_MODE_BITSIZE (mode
);
7629 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7630 /* Our only callers in this case look for single bit values. So
7631 just return the mode mask. Those tests will then be false. */
7634 #ifndef WORD_REGISTER_OPERATIONS
7635 /* If MODE is wider than X, but both are a single word for both the host
7636 and target machines, we can compute this from which bits of the
7637 object might be nonzero in its own mode, taking into account the fact
7638 that on many CISC machines, accessing an object in a wider mode
7639 causes the high-order bits to become undefined. So they are
7640 not known to be zero. */
7642 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7643 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7644 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7645 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7647 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7648 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
7653 code
= GET_CODE (x
);
7657 #ifdef POINTERS_EXTEND_UNSIGNED
7658 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7659 all the bits above ptr_mode are known to be zero. */
7660 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7661 && REGNO_POINTER_FLAG (REGNO (x
)))
7662 nonzero
&= GET_MODE_MASK (ptr_mode
);
7665 #ifdef STACK_BOUNDARY
7666 /* If this is the stack pointer, we may know something about its
7667 alignment. If PUSH_ROUNDING is defined, it is possible for the
7668 stack to be momentarily aligned only to that amount, so we pick
7669 the least alignment. */
7671 /* We can't check for arg_pointer_rtx here, because it is not
7672 guaranteed to have as much alignment as the stack pointer.
7673 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7674 alignment but the argument pointer has only 64 bit alignment. */
7676 if ((x
== frame_pointer_rtx
7677 || x
== stack_pointer_rtx
7678 || x
== hard_frame_pointer_rtx
7679 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7680 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7686 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7688 #ifdef PUSH_ROUNDING
7689 if (REGNO (x
) == STACK_POINTER_REGNUM
)
7690 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7693 /* We must return here, otherwise we may get a worse result from
7694 one of the choices below. There is nothing useful below as
7695 far as the stack pointer is concerned. */
7696 return nonzero
&= ~ (sp_alignment
- 1);
7700 /* If X is a register whose nonzero bits value is current, use it.
7701 Otherwise, if X is a register whose value we can find, use that
7702 value. Otherwise, use the previously-computed global nonzero bits
7703 for this register. */
7705 if (reg_last_set_value
[REGNO (x
)] != 0
7706 && reg_last_set_mode
[REGNO (x
)] == mode
7707 && (reg_last_set_label
[REGNO (x
)] == label_tick
7708 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7709 && REG_N_SETS (REGNO (x
)) == 1
7710 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7712 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7713 return reg_last_set_nonzero_bits
[REGNO (x
)];
7715 tem
= get_last_value (x
);
7719 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7720 /* If X is narrower than MODE and TEM is a non-negative
7721 constant that would appear negative in the mode of X,
7722 sign-extend it for use in reg_nonzero_bits because some
7723 machines (maybe most) will actually do the sign-extension
7724 and this is the conservative approach.
7726 ??? For 2.5, try to tighten up the MD files in this regard
7727 instead of this kludge. */
7729 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7730 && GET_CODE (tem
) == CONST_INT
7732 && 0 != (INTVAL (tem
)
7733 & ((HOST_WIDE_INT
) 1
7734 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7735 tem
= GEN_INT (INTVAL (tem
)
7736 | ((HOST_WIDE_INT
) (-1)
7737 << GET_MODE_BITSIZE (GET_MODE (x
))));
7739 return nonzero_bits (tem
, mode
);
7741 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7742 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7747 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7748 /* If X is negative in MODE, sign-extend the value. */
7749 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7750 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7751 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7757 #ifdef LOAD_EXTEND_OP
7758 /* In many, if not most, RISC machines, reading a byte from memory
7759 zeros the rest of the register. Noticing that fact saves a lot
7760 of extra zero-extends. */
7761 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7762 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7772 /* If this produces an integer result, we know which bits are set.
7773 Code here used to clear bits outside the mode of X, but that is
7776 if (GET_MODE_CLASS (mode
) == MODE_INT
7777 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7778 nonzero
= STORE_FLAG_VALUE
;
7783 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7784 and num_sign_bit_copies. */
7785 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7786 == GET_MODE_BITSIZE (GET_MODE (x
)))
7790 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
7791 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
7796 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7797 and num_sign_bit_copies. */
7798 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7799 == GET_MODE_BITSIZE (GET_MODE (x
)))
7805 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
7809 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
7810 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7811 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7815 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7816 Otherwise, show all the bits in the outer mode but not the inner
7818 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
7819 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7821 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7823 & (((HOST_WIDE_INT
) 1
7824 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
7825 inner_nz
|= (GET_MODE_MASK (mode
)
7826 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
7829 nonzero
&= inner_nz
;
7833 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7834 & nonzero_bits (XEXP (x
, 1), mode
));
7838 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
7839 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7840 | nonzero_bits (XEXP (x
, 1), mode
));
7843 case PLUS
: case MINUS
:
7845 case DIV
: case UDIV
:
7846 case MOD
: case UMOD
:
7847 /* We can apply the rules of arithmetic to compute the number of
7848 high- and low-order zero bits of these operations. We start by
7849 computing the width (position of the highest-order non-zero bit)
7850 and the number of low-order zero bits for each value. */
7852 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
7853 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
7854 int width0
= floor_log2 (nz0
) + 1;
7855 int width1
= floor_log2 (nz1
) + 1;
7856 int low0
= floor_log2 (nz0
& -nz0
);
7857 int low1
= floor_log2 (nz1
& -nz1
);
7858 HOST_WIDE_INT op0_maybe_minusp
7859 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7860 HOST_WIDE_INT op1_maybe_minusp
7861 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7862 int result_width
= mode_width
;
7870 && (XEXP (x
, 0) == stack_pointer_rtx
7871 || XEXP (x
, 0) == frame_pointer_rtx
)
7872 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7874 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7876 nz0
= (GET_MODE_MASK (mode
) & ~ (sp_alignment
- 1));
7877 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
7878 width0
= floor_log2 (nz0
) + 1;
7879 width1
= floor_log2 (nz1
) + 1;
7880 low0
= floor_log2 (nz0
& -nz0
);
7881 low1
= floor_log2 (nz1
& -nz1
);
7884 result_width
= MAX (width0
, width1
) + 1;
7885 result_low
= MIN (low0
, low1
);
7888 result_low
= MIN (low0
, low1
);
7891 result_width
= width0
+ width1
;
7892 result_low
= low0
+ low1
;
7895 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7896 result_width
= width0
;
7899 result_width
= width0
;
7902 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7903 result_width
= MIN (width0
, width1
);
7904 result_low
= MIN (low0
, low1
);
7907 result_width
= MIN (width0
, width1
);
7908 result_low
= MIN (low0
, low1
);
7914 if (result_width
< mode_width
)
7915 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
7918 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
7923 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7924 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7925 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
7929 /* If this is a SUBREG formed for a promoted variable that has
7930 been zero-extended, we know that at least the high-order bits
7931 are zero, though others might be too. */
7933 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
7934 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
7935 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
7937 /* If the inner mode is a single word for both the host and target
7938 machines, we can compute this from which bits of the inner
7939 object might be nonzero. */
7940 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
7941 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7942 <= HOST_BITS_PER_WIDE_INT
))
7944 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
7946 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7947 /* If this is a typical RISC machine, we only have to worry
7948 about the way loads are extended. */
7949 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
7951 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1)))
7952 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
7955 /* On many CISC machines, accessing an object in a wider mode
7956 causes the high-order bits to become undefined. So they are
7957 not known to be zero. */
7958 if (GET_MODE_SIZE (GET_MODE (x
))
7959 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7960 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
7961 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
7970 /* The nonzero bits are in two classes: any bits within MODE
7971 that aren't in GET_MODE (x) are always significant. The rest of the
7972 nonzero bits are those that are significant in the operand of
7973 the shift when shifted the appropriate number of bits. This
7974 shows that high-order bits are cleared by the right shift and
7975 low-order bits by left shifts. */
7976 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7977 && INTVAL (XEXP (x
, 1)) >= 0
7978 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7980 enum machine_mode inner_mode
= GET_MODE (x
);
7981 int width
= GET_MODE_BITSIZE (inner_mode
);
7982 int count
= INTVAL (XEXP (x
, 1));
7983 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
7984 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7985 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
7986 unsigned HOST_WIDE_INT outer
= 0;
7988 if (mode_width
> width
)
7989 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
7991 if (code
== LSHIFTRT
)
7993 else if (code
== ASHIFTRT
)
7997 /* If the sign bit may have been nonzero before the shift, we
7998 need to mark all the places it could have been copied to
7999 by the shift as possibly nonzero. */
8000 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8001 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8003 else if (code
== ASHIFT
)
8006 inner
= ((inner
<< (count
% width
)
8007 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8009 nonzero
&= (outer
| inner
);
8014 /* This is at most the number of bits in the mode. */
8015 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8019 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8020 | nonzero_bits (XEXP (x
, 2), mode
));
8030 /* See the macro definition above. */
8031 #undef num_sign_bit_copies
8033 /* Return the number of bits at the high-order end of X that are known to
8034 be equal to the sign bit. X will be used in mode MODE; if MODE is
8035 VOIDmode, X will be used in its own mode. The returned value will always
8036 be between 1 and the number of bits in MODE. */
8039 num_sign_bit_copies (x
, mode
)
8041 enum machine_mode mode
;
8043 enum rtx_code code
= GET_CODE (x
);
8045 int num0
, num1
, result
;
8046 unsigned HOST_WIDE_INT nonzero
;
8049 /* If we weren't given a mode, use the mode of X. If the mode is still
8050 VOIDmode, we don't know anything. Likewise if one of the modes is
8053 if (mode
== VOIDmode
)
8054 mode
= GET_MODE (x
);
8056 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8059 bitwidth
= GET_MODE_BITSIZE (mode
);
8061 /* For a smaller object, just ignore the high bits. */
8062 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8063 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
8064 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
8066 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8068 #ifndef WORD_REGISTER_OPERATIONS
8069 /* If this machine does not do all register operations on the entire
8070 register and MODE is wider than the mode of X, we can say nothing
8071 at all about the high-order bits. */
8074 /* Likewise on machines that do, if the mode of the object is smaller
8075 than a word and loads of that size don't sign extend, we can say
8076 nothing about the high order bits. */
8077 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8078 #ifdef LOAD_EXTEND_OP
8079 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8090 #ifdef POINTERS_EXTEND_UNSIGNED
8091 /* If pointers extend signed and this is a pointer in Pmode, say that
8092 all the bits above ptr_mode are known to be sign bit copies. */
8093 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8094 && REGNO_POINTER_FLAG (REGNO (x
)))
8095 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8098 if (reg_last_set_value
[REGNO (x
)] != 0
8099 && reg_last_set_mode
[REGNO (x
)] == mode
8100 && (reg_last_set_label
[REGNO (x
)] == label_tick
8101 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8102 && REG_N_SETS (REGNO (x
)) == 1
8103 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8105 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8106 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8108 tem
= get_last_value (x
);
8110 return num_sign_bit_copies (tem
, mode
);
8112 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8113 return reg_sign_bit_copies
[REGNO (x
)];
8117 #ifdef LOAD_EXTEND_OP
8118 /* Some RISC machines sign-extend all loads of smaller than a word. */
8119 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8120 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
8125 /* If the constant is negative, take its 1's complement and remask.
8126 Then see how many zero bits we have. */
8127 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8128 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8129 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8130 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
8132 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8135 /* If this is a SUBREG for a promoted object that is sign-extended
8136 and we are looking at it in a wider mode, we know that at least the
8137 high-order bits are known to be sign bit copies. */
8139 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8140 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8141 num_sign_bit_copies (SUBREG_REG (x
), mode
));
8143 /* For a smaller object, just ignore the high bits. */
8144 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8146 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8147 return MAX (1, (num0
8148 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8152 #ifdef WORD_REGISTER_OPERATIONS
8153 #ifdef LOAD_EXTEND_OP
8154 /* For paradoxical SUBREGs on machines where all register operations
8155 affect the entire register, just look inside. Note that we are
8156 passing MODE to the recursive call, so the number of sign bit copies
8157 will remain relative to that mode, not the inner mode. */
8159 /* This works only if loads sign extend. Otherwise, if we get a
8160 reload for the inner part, it may be loaded from the stack, and
8161 then we lose all sign bit copies that existed before the store
8164 if ((GET_MODE_SIZE (GET_MODE (x
))
8165 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8166 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8167 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8173 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8174 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
8178 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8179 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8182 /* For a smaller object, just ignore the high bits. */
8183 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8184 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8188 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8190 case ROTATE
: case ROTATERT
:
8191 /* If we are rotating left by a number of bits less than the number
8192 of sign bit copies, we can just subtract that amount from the
8194 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8195 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8197 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8198 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8199 : bitwidth
- INTVAL (XEXP (x
, 1))));
8204 /* In general, this subtracts one sign bit copy. But if the value
8205 is known to be positive, the number of sign bit copies is the
8206 same as that of the input. Finally, if the input has just one bit
8207 that might be nonzero, all the bits are copies of the sign bit. */
8208 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8209 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8210 return num0
> 1 ? num0
- 1 : 1;
8212 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8217 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8222 case IOR
: case AND
: case XOR
:
8223 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8224 /* Logical operations will preserve the number of sign-bit copies.
8225 MIN and MAX operations always return one of the operands. */
8226 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8227 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8228 return MIN (num0
, num1
);
8230 case PLUS
: case MINUS
:
8231 /* For addition and subtraction, we can have a 1-bit carry. However,
8232 if we are subtracting 1 from a positive number, there will not
8233 be such a carry. Furthermore, if the positive number is known to
8234 be 0 or 1, we know the result is either -1 or 0. */
8236 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8237 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8239 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8240 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8241 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8242 : bitwidth
- floor_log2 (nonzero
) - 1);
8245 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8246 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8247 return MAX (1, MIN (num0
, num1
) - 1);
8250 /* The number of bits of the product is the sum of the number of
8251 bits of both terms. However, unless one of the terms if known
8252 to be positive, we must allow for an additional bit since negating
8253 a negative number can remove one sign bit copy. */
8255 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8256 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8258 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8260 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8261 || (((nonzero_bits (XEXP (x
, 0), mode
)
8262 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8263 && ((nonzero_bits (XEXP (x
, 1), mode
)
8264 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8267 return MAX (1, result
);
8270 /* The result must be <= the first operand. If the first operand
8271 has the high bit set, we know nothing about the number of sign
8273 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8275 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8276 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8279 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8282 /* The result must be <= the scond operand. */
8283 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8286 /* Similar to unsigned division, except that we have to worry about
8287 the case where the divisor is negative, in which case we have
8289 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8291 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8292 || (nonzero_bits (XEXP (x
, 1), mode
)
8293 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8299 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8301 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8302 || (nonzero_bits (XEXP (x
, 1), mode
)
8303 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8309 /* Shifts by a constant add to the number of bits equal to the
8311 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8312 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8313 && INTVAL (XEXP (x
, 1)) > 0)
8314 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8319 /* Left shifts destroy copies. */
8320 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8321 || INTVAL (XEXP (x
, 1)) < 0
8322 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8325 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8326 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8329 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8330 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8331 return MIN (num0
, num1
);
8333 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8334 case GEU
: case GTU
: case LEU
: case LTU
:
8335 if (STORE_FLAG_VALUE
== -1)
8343 /* If we haven't been able to figure it out by one of the above rules,
8344 see if some of the high-order bits are known to be zero. If so,
8345 count those bits and return one less than that amount. If we can't
8346 safely compute the mask for this mode, always return BITWIDTH. */
8348 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8351 nonzero
= nonzero_bits (x
, mode
);
8352 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8353 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8356 /* Return the number of "extended" bits there are in X, when interpreted
8357 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8358 unsigned quantities, this is the number of high-order zero bits.
8359 For signed quantities, this is the number of copies of the sign bit
8360 minus 1. In both case, this function returns the number of "spare"
8361 bits. For example, if two quantities for which this function returns
8362 at least 1 are added, the addition is known not to overflow.
8364 This function will always return 0 unless called during combine, which
8365 implies that it must be called from a define_split. */
8368 extended_count (x
, mode
, unsignedp
)
8370 enum machine_mode mode
;
8373 if (nonzero_sign_valid
== 0)
8377 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8378 && (GET_MODE_BITSIZE (mode
) - 1
8379 - floor_log2 (nonzero_bits (x
, mode
))))
8380 : num_sign_bit_copies (x
, mode
) - 1);
8383 /* This function is called from `simplify_shift_const' to merge two
8384 outer operations. Specifically, we have already found that we need
8385 to perform operation *POP0 with constant *PCONST0 at the outermost
8386 position. We would now like to also perform OP1 with constant CONST1
8387 (with *POP0 being done last).
8389 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8390 the resulting operation. *PCOMP_P is set to 1 if we would need to
8391 complement the innermost operand, otherwise it is unchanged.
8393 MODE is the mode in which the operation will be done. No bits outside
8394 the width of this mode matter. It is assumed that the width of this mode
8395 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8397 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8398 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8399 result is simply *PCONST0.
8401 If the resulting operation cannot be expressed as one operation, we
8402 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8405 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8406 enum rtx_code
*pop0
;
8407 HOST_WIDE_INT
*pconst0
;
8409 HOST_WIDE_INT const1
;
8410 enum machine_mode mode
;
8413 enum rtx_code op0
= *pop0
;
8414 HOST_WIDE_INT const0
= *pconst0
;
8416 const0
&= GET_MODE_MASK (mode
);
8417 const1
&= GET_MODE_MASK (mode
);
8419 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8423 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8426 if (op1
== NIL
|| op0
== SET
)
8429 else if (op0
== NIL
)
8430 op0
= op1
, const0
= const1
;
8432 else if (op0
== op1
)
8456 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8457 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8460 /* If the two constants aren't the same, we can't do anything. The
8461 remaining six cases can all be done. */
8462 else if (const0
!= const1
)
8470 /* (a & b) | b == b */
8472 else /* op1 == XOR */
8473 /* (a ^ b) | b == a | b */
8479 /* (a & b) ^ b == (~a) & b */
8480 op0
= AND
, *pcomp_p
= 1;
8481 else /* op1 == IOR */
8482 /* (a | b) ^ b == a & ~b */
8483 op0
= AND
, *pconst0
= ~ const0
;
8488 /* (a | b) & b == b */
8490 else /* op1 == XOR */
8491 /* (a ^ b) & b) == (~a) & b */
8498 /* Check for NO-OP cases. */
8499 const0
&= GET_MODE_MASK (mode
);
8501 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8503 else if (const0
== 0 && op0
== AND
)
8505 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8509 /* ??? Slightly redundant with the above mask, but not entirely.
8510 Moving this above means we'd have to sign-extend the mode mask
8511 for the final test. */
8512 const0
= trunc_int_for_mode (const0
, mode
);
8520 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8521 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8522 that we started with.
8524 The shift is normally computed in the widest mode we find in VAROP, as
8525 long as it isn't a different number of words than RESULT_MODE. Exceptions
8526 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8529 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
8532 enum machine_mode result_mode
;
8536 enum rtx_code orig_code
= code
;
8537 int orig_count
= count
;
8538 enum machine_mode mode
= result_mode
;
8539 enum machine_mode shift_mode
, tmode
;
8541 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8542 /* We form (outer_op (code varop count) (outer_const)). */
8543 enum rtx_code outer_op
= NIL
;
8544 HOST_WIDE_INT outer_const
= 0;
8546 int complement_p
= 0;
8549 /* If we were given an invalid count, don't do anything except exactly
8550 what was requested. */
8552 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
8557 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (count
));
8560 /* Unless one of the branches of the `if' in this loop does a `continue',
8561 we will `break' the loop after the `if'. */
8565 /* If we have an operand of (clobber (const_int 0)), just return that
8567 if (GET_CODE (varop
) == CLOBBER
)
8570 /* If we discovered we had to complement VAROP, leave. Making a NOT
8571 here would cause an infinite loop. */
8575 /* Convert ROTATERT to ROTATE. */
8576 if (code
== ROTATERT
)
8577 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8579 /* We need to determine what mode we will do the shift in. If the
8580 shift is a right shift or a ROTATE, we must always do it in the mode
8581 it was originally done in. Otherwise, we can do it in MODE, the
8582 widest mode encountered. */
8584 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8585 ? result_mode
: mode
);
8587 /* Handle cases where the count is greater than the size of the mode
8588 minus 1. For ASHIFT, use the size minus one as the count (this can
8589 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8590 take the count modulo the size. For other shifts, the result is
8593 Since these shifts are being produced by the compiler by combining
8594 multiple operations, each of which are defined, we know what the
8595 result is supposed to be. */
8597 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8599 if (code
== ASHIFTRT
)
8600 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8601 else if (code
== ROTATE
|| code
== ROTATERT
)
8602 count
%= GET_MODE_BITSIZE (shift_mode
);
8605 /* We can't simply return zero because there may be an
8613 /* Negative counts are invalid and should not have been made (a
8614 programmer-specified negative count should have been handled
8619 /* An arithmetic right shift of a quantity known to be -1 or 0
8621 if (code
== ASHIFTRT
8622 && (num_sign_bit_copies (varop
, shift_mode
)
8623 == GET_MODE_BITSIZE (shift_mode
)))
8629 /* If we are doing an arithmetic right shift and discarding all but
8630 the sign bit copies, this is equivalent to doing a shift by the
8631 bitsize minus one. Convert it into that shift because it will often
8632 allow other simplifications. */
8634 if (code
== ASHIFTRT
8635 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8636 >= GET_MODE_BITSIZE (shift_mode
)))
8637 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8639 /* We simplify the tests below and elsewhere by converting
8640 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8641 `make_compound_operation' will convert it to a ASHIFTRT for
8642 those machines (such as Vax) that don't have a LSHIFTRT. */
8643 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8645 && ((nonzero_bits (varop
, shift_mode
)
8646 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8650 switch (GET_CODE (varop
))
8656 new = expand_compound_operation (varop
);
8665 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8666 minus the width of a smaller mode, we can do this with a
8667 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8668 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8669 && ! mode_dependent_address_p (XEXP (varop
, 0))
8670 && ! MEM_VOLATILE_P (varop
)
8671 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8672 MODE_INT
, 1)) != BLKmode
)
8674 if (BYTES_BIG_ENDIAN
)
8675 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
8677 new = gen_rtx_MEM (tmode
,
8678 plus_constant (XEXP (varop
, 0),
8679 count
/ BITS_PER_UNIT
));
8680 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
8681 MEM_COPY_ATTRIBUTES (new, varop
);
8682 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8683 : ZERO_EXTEND
, mode
, new);
8690 /* Similar to the case above, except that we can only do this if
8691 the resulting mode is the same as that of the underlying
8692 MEM and adjust the address depending on the *bits* endianness
8693 because of the way that bit-field extract insns are defined. */
8694 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8695 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8696 MODE_INT
, 1)) != BLKmode
8697 && tmode
== GET_MODE (XEXP (varop
, 0)))
8699 if (BITS_BIG_ENDIAN
)
8700 new = XEXP (varop
, 0);
8703 new = copy_rtx (XEXP (varop
, 0));
8704 SUBST (XEXP (new, 0),
8705 plus_constant (XEXP (new, 0),
8706 count
/ BITS_PER_UNIT
));
8709 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8710 : ZERO_EXTEND
, mode
, new);
8717 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8718 the same number of words as what we've seen so far. Then store
8719 the widest mode in MODE. */
8720 if (subreg_lowpart_p (varop
)
8721 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8722 > GET_MODE_SIZE (GET_MODE (varop
)))
8723 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8724 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8727 varop
= SUBREG_REG (varop
);
8728 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8729 mode
= GET_MODE (varop
);
8735 /* Some machines use MULT instead of ASHIFT because MULT
8736 is cheaper. But it is still better on those machines to
8737 merge two shifts into one. */
8738 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8739 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8741 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8742 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8748 /* Similar, for when divides are cheaper. */
8749 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8750 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8752 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8753 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8759 /* If we are extracting just the sign bit of an arithmetic right
8760 shift, that shift is not needed. */
8761 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
8763 varop
= XEXP (varop
, 0);
8767 /* ... fall through ... */
8772 /* Here we have two nested shifts. The result is usually the
8773 AND of a new shift with a mask. We compute the result below. */
8774 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8775 && INTVAL (XEXP (varop
, 1)) >= 0
8776 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8777 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8778 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8780 enum rtx_code first_code
= GET_CODE (varop
);
8781 int first_count
= INTVAL (XEXP (varop
, 1));
8782 unsigned HOST_WIDE_INT mask
;
8785 /* We have one common special case. We can't do any merging if
8786 the inner code is an ASHIFTRT of a smaller mode. However, if
8787 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8788 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8789 we can convert it to
8790 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8791 This simplifies certain SIGN_EXTEND operations. */
8792 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8793 && (GET_MODE_BITSIZE (result_mode
)
8794 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
8796 /* C3 has the low-order C1 bits zero. */
8798 mask
= (GET_MODE_MASK (mode
)
8799 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
8801 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8802 XEXP (varop
, 0), mask
);
8803 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8805 count
= first_count
;
8810 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8811 than C1 high-order bits equal to the sign bit, we can convert
8812 this to either an ASHIFT or a ASHIFTRT depending on the
8815 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8817 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8818 && GET_MODE (varop
) == shift_mode
8819 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8822 count
-= first_count
;
8824 count
= - count
, code
= ASHIFT
;
8825 varop
= XEXP (varop
, 0);
8829 /* There are some cases we can't do. If CODE is ASHIFTRT,
8830 we can only do this if FIRST_CODE is also ASHIFTRT.
8832 We can't do the case when CODE is ROTATE and FIRST_CODE is
8835 If the mode of this shift is not the mode of the outer shift,
8836 we can't do this if either shift is a right shift or ROTATE.
8838 Finally, we can't do any of these if the mode is too wide
8839 unless the codes are the same.
8841 Handle the case where the shift codes are the same
8844 if (code
== first_code
)
8846 if (GET_MODE (varop
) != result_mode
8847 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8851 count
+= first_count
;
8852 varop
= XEXP (varop
, 0);
8856 if (code
== ASHIFTRT
8857 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8858 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8859 || (GET_MODE (varop
) != result_mode
8860 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8861 || first_code
== ROTATE
8862 || code
== ROTATE
)))
8865 /* To compute the mask to apply after the shift, shift the
8866 nonzero bits of the inner shift the same way the
8867 outer shift will. */
8869 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8872 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8875 /* Give up if we can't compute an outer operation to use. */
8877 || GET_CODE (mask_rtx
) != CONST_INT
8878 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8880 result_mode
, &complement_p
))
8883 /* If the shifts are in the same direction, we add the
8884 counts. Otherwise, we subtract them. */
8885 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8886 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8887 count
+= first_count
;
8889 count
-= first_count
;
8891 /* If COUNT is positive, the new shift is usually CODE,
8892 except for the two exceptions below, in which case it is
8893 FIRST_CODE. If the count is negative, FIRST_CODE should
8896 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8897 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8900 code
= first_code
, count
= - count
;
8902 varop
= XEXP (varop
, 0);
8906 /* If we have (A << B << C) for any shift, we can convert this to
8907 (A << C << B). This wins if A is a constant. Only try this if
8908 B is not a constant. */
8910 else if (GET_CODE (varop
) == code
8911 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8913 = simplify_binary_operation (code
, mode
,
8917 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
8924 /* Make this fit the case below. */
8925 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
8926 GEN_INT (GET_MODE_MASK (mode
)));
8932 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8933 with C the size of VAROP - 1 and the shift is logical if
8934 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8935 we have an (le X 0) operation. If we have an arithmetic shift
8936 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8937 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8939 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8940 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8941 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8942 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8943 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8944 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8947 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
8950 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8951 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8956 /* If we have (shift (logical)), move the logical to the outside
8957 to allow it to possibly combine with another logical and the
8958 shift to combine with another shift. This also canonicalizes to
8959 what a ZERO_EXTRACT looks like. Also, some machines have
8960 (and (shift)) insns. */
8962 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8963 && (new = simplify_binary_operation (code
, result_mode
,
8965 GEN_INT (count
))) != 0
8966 && GET_CODE(new) == CONST_INT
8967 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8968 INTVAL (new), result_mode
, &complement_p
))
8970 varop
= XEXP (varop
, 0);
8974 /* If we can't do that, try to simplify the shift in each arm of the
8975 logical expression, make a new logical expression, and apply
8976 the inverse distributive law. */
8978 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8979 XEXP (varop
, 0), count
);
8980 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8981 XEXP (varop
, 1), count
);
8983 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8984 varop
= apply_distributive_law (varop
);
8991 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8992 says that the sign bit can be tested, FOO has mode MODE, C is
8993 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8994 that may be nonzero. */
8995 if (code
== LSHIFTRT
8996 && XEXP (varop
, 1) == const0_rtx
8997 && GET_MODE (XEXP (varop
, 0)) == result_mode
8998 && count
== GET_MODE_BITSIZE (result_mode
) - 1
8999 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9000 && ((STORE_FLAG_VALUE
9001 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
9002 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9003 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9004 (HOST_WIDE_INT
) 1, result_mode
,
9007 varop
= XEXP (varop
, 0);
9014 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9015 than the number of bits in the mode is equivalent to A. */
9016 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9017 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9019 varop
= XEXP (varop
, 0);
9024 /* NEG commutes with ASHIFT since it is multiplication. Move the
9025 NEG outside to allow shifts to combine. */
9027 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9028 (HOST_WIDE_INT
) 0, result_mode
,
9031 varop
= XEXP (varop
, 0);
9037 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9038 is one less than the number of bits in the mode is
9039 equivalent to (xor A 1). */
9040 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9041 && XEXP (varop
, 1) == constm1_rtx
9042 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9043 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9044 (HOST_WIDE_INT
) 1, result_mode
,
9048 varop
= XEXP (varop
, 0);
9052 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9053 that might be nonzero in BAR are those being shifted out and those
9054 bits are known zero in FOO, we can replace the PLUS with FOO.
9055 Similarly in the other operand order. This code occurs when
9056 we are computing the size of a variable-size array. */
9058 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9059 && count
< HOST_BITS_PER_WIDE_INT
9060 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9061 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9062 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9064 varop
= XEXP (varop
, 0);
9067 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9068 && count
< HOST_BITS_PER_WIDE_INT
9069 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9070 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9072 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9073 & nonzero_bits (XEXP (varop
, 1),
9076 varop
= XEXP (varop
, 1);
9080 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9082 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9083 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9085 GEN_INT (count
))) != 0
9086 && GET_CODE(new) == CONST_INT
9087 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9088 INTVAL (new), result_mode
, &complement_p
))
9090 varop
= XEXP (varop
, 0);
9096 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9097 with C the size of VAROP - 1 and the shift is logical if
9098 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9099 we have a (gt X 0) operation. If the shift is arithmetic with
9100 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9101 we have a (neg (gt X 0)) operation. */
9103 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9104 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9105 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9106 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9107 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9108 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9109 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9112 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9115 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9116 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9123 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9124 if the truncate does not affect the value. */
9125 if (code
== LSHIFTRT
9126 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9127 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9128 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9129 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9130 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9132 rtx varop_inner
= XEXP (varop
, 0);
9134 varop_inner
= gen_rtx_combine (LSHIFTRT
,
9135 GET_MODE (varop_inner
),
9136 XEXP (varop_inner
, 0),
9137 GEN_INT (count
+ INTVAL (XEXP (varop_inner
, 1))));
9138 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9152 /* We need to determine what mode to do the shift in. If the shift is
9153 a right shift or ROTATE, we must always do it in the mode it was
9154 originally done in. Otherwise, we can do it in MODE, the widest mode
9155 encountered. The code we care about is that of the shift that will
9156 actually be done, not the shift that was originally requested. */
9158 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9159 ? result_mode
: mode
);
9161 /* We have now finished analyzing the shift. The result should be
9162 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9163 OUTER_OP is non-NIL, it is an operation that needs to be applied
9164 to the result of the shift. OUTER_CONST is the relevant constant,
9165 but we must turn off all bits turned off in the shift.
9167 If we were passed a value for X, see if we can use any pieces of
9168 it. If not, make new rtx. */
9170 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9171 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9172 && INTVAL (XEXP (x
, 1)) == count
)
9173 const_rtx
= XEXP (x
, 1);
9175 const_rtx
= GEN_INT (count
);
9177 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9178 && GET_MODE (XEXP (x
, 0)) == shift_mode
9179 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9180 varop
= XEXP (x
, 0);
9181 else if (GET_MODE (varop
) != shift_mode
)
9182 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9184 /* If we can't make the SUBREG, try to return what we were given. */
9185 if (GET_CODE (varop
) == CLOBBER
)
9186 return x
? x
: varop
;
9188 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9193 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9194 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9196 SUBST (XEXP (x
, 0), varop
);
9197 SUBST (XEXP (x
, 1), const_rtx
);
9200 /* If we have an outer operation and we just made a shift, it is
9201 possible that we could have simplified the shift were it not
9202 for the outer operation. So try to do the simplification
9205 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9206 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9207 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9208 INTVAL (XEXP (x
, 1)));
9210 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9211 turn off all the bits that the shift would have turned off. */
9212 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9213 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9214 GET_MODE_MASK (result_mode
) >> orig_count
);
9216 /* Do the remainder of the processing in RESULT_MODE. */
9217 x
= gen_lowpart_for_combine (result_mode
, x
);
9219 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9222 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9224 if (outer_op
!= NIL
)
9226 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9227 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9229 if (outer_op
== AND
)
9230 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9231 else if (outer_op
== SET
)
9232 /* This means that we have determined that the result is
9233 equivalent to a constant. This should be rare. */
9234 x
= GEN_INT (outer_const
);
9235 else if (GET_RTX_CLASS (outer_op
) == '1')
9236 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9238 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9244 /* Like recog, but we receive the address of a pointer to a new pattern.
9245 We try to match the rtx that the pointer points to.
9246 If that fails, we may try to modify or replace the pattern,
9247 storing the replacement into the same pointer object.
9249 Modifications include deletion or addition of CLOBBERs.
9251 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9252 the CLOBBERs are placed.
9254 The value is the final insn code from the pattern ultimately matched,
9258 recog_for_combine (pnewpat
, insn
, pnotes
)
9263 register rtx pat
= *pnewpat
;
9264 int insn_code_number
;
9265 int num_clobbers_to_add
= 0;
9269 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9270 we use to indicate that something didn't match. If we find such a
9271 thing, force rejection. */
9272 if (GET_CODE (pat
) == PARALLEL
)
9273 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9274 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9275 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9278 /* Is the result of combination a valid instruction? */
9279 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9281 /* If it isn't, there is the possibility that we previously had an insn
9282 that clobbered some register as a side effect, but the combined
9283 insn doesn't need to do that. So try once more without the clobbers
9284 unless this represents an ASM insn. */
9286 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9287 && GET_CODE (pat
) == PARALLEL
)
9291 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9292 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9295 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9299 SUBST_INT (XVECLEN (pat
, 0), pos
);
9302 pat
= XVECEXP (pat
, 0, 0);
9304 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9307 /* If we had any clobbers to add, make a new pattern than contains
9308 them. Then check to make sure that all of them are dead. */
9309 if (num_clobbers_to_add
)
9311 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9312 gen_rtvec (GET_CODE (pat
) == PARALLEL
9314 + num_clobbers_to_add
)
9315 : num_clobbers_to_add
+ 1));
9317 if (GET_CODE (pat
) == PARALLEL
)
9318 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9319 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9321 XVECEXP (newpat
, 0, 0) = pat
;
9323 add_clobbers (newpat
, insn_code_number
);
9325 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9326 i
< XVECLEN (newpat
, 0); i
++)
9328 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9329 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9331 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9332 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9340 return insn_code_number
;
9343 /* Like gen_lowpart but for use by combine. In combine it is not possible
9344 to create any new pseudoregs. However, it is safe to create
9345 invalid memory addresses, because combine will try to recognize
9346 them and all they will do is make the combine attempt fail.
9348 If for some reason this cannot do its job, an rtx
9349 (clobber (const_int 0)) is returned.
9350 An insn containing that will not be recognized. */
9355 gen_lowpart_for_combine (mode
, x
)
9356 enum machine_mode mode
;
9361 if (GET_MODE (x
) == mode
)
9364 /* We can only support MODE being wider than a word if X is a
9365 constant integer or has a mode the same size. */
9367 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9368 && ! ((GET_MODE (x
) == VOIDmode
9369 && (GET_CODE (x
) == CONST_INT
9370 || GET_CODE (x
) == CONST_DOUBLE
))
9371 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9372 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9374 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9375 won't know what to do. So we will strip off the SUBREG here and
9376 process normally. */
9377 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9380 if (GET_MODE (x
) == mode
)
9384 result
= gen_lowpart_common (mode
, x
);
9386 && GET_CODE (result
) == SUBREG
9387 && GET_CODE (SUBREG_REG (result
)) == REG
9388 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9389 && (GET_MODE_SIZE (GET_MODE (result
))
9390 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result
)))))
9391 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result
))) = 1;
9396 if (GET_CODE (x
) == MEM
)
9398 register int offset
= 0;
9401 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9403 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9404 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9406 /* If we want to refer to something bigger than the original memref,
9407 generate a perverse subreg instead. That will force a reload
9408 of the original memref X. */
9409 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9410 return gen_rtx_SUBREG (mode
, x
, 0);
9412 if (WORDS_BIG_ENDIAN
)
9413 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9414 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9416 if (BYTES_BIG_ENDIAN
)
9418 /* Adjust the address so that the address-after-the-data is
9420 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9421 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9423 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9424 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
9425 MEM_COPY_ATTRIBUTES (new, x
);
9429 /* If X is a comparison operator, rewrite it in a new mode. This
9430 probably won't match, but may allow further simplifications. */
9431 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9432 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9434 /* If we couldn't simplify X any other way, just enclose it in a
9435 SUBREG. Normally, this SUBREG won't match, but some patterns may
9436 include an explicit SUBREG or we may simplify it further in combine. */
9441 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9442 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9443 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9445 return gen_rtx_SUBREG (mode
, x
, word
);
9449 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9450 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9452 If the identical expression was previously in the insn (in the undobuf),
9453 it will be returned. Only if it is not found will a new expression
9458 gen_rtx_combine
VPROTO((enum rtx_code code
, enum machine_mode mode
, ...))
9460 #ifndef ANSI_PROTOTYPES
9462 enum machine_mode mode
;
9474 #ifndef ANSI_PROTOTYPES
9475 code
= va_arg (p
, enum rtx_code
);
9476 mode
= va_arg (p
, enum machine_mode
);
9479 n_args
= GET_RTX_LENGTH (code
);
9480 fmt
= GET_RTX_FORMAT (code
);
9482 if (n_args
== 0 || n_args
> 3)
9485 /* Get each arg and verify that it is supposed to be an expression. */
9486 for (j
= 0; j
< n_args
; j
++)
9491 args
[j
] = va_arg (p
, rtx
);
9496 /* See if this is in undobuf. Be sure we don't use objects that came
9497 from another insn; this could produce circular rtl structures. */
9499 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9501 && GET_CODE (undo
->old_contents
.r
) == code
9502 && GET_MODE (undo
->old_contents
.r
) == mode
)
9504 for (j
= 0; j
< n_args
; j
++)
9505 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9509 return undo
->old_contents
.r
;
9512 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9513 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9514 rt
= rtx_alloc (code
);
9515 PUT_MODE (rt
, mode
);
9516 XEXP (rt
, 0) = args
[0];
9519 XEXP (rt
, 1) = args
[1];
9521 XEXP (rt
, 2) = args
[2];
9526 /* These routines make binary and unary operations by first seeing if they
9527 fold; if not, a new expression is allocated. */
9530 gen_binary (code
, mode
, op0
, op1
)
9532 enum machine_mode mode
;
9538 if (GET_RTX_CLASS (code
) == 'c'
9539 && (GET_CODE (op0
) == CONST_INT
9540 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9541 tem
= op0
, op0
= op1
, op1
= tem
;
9543 if (GET_RTX_CLASS (code
) == '<')
9545 enum machine_mode op_mode
= GET_MODE (op0
);
9547 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9548 just (REL_OP X Y). */
9549 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9551 op1
= XEXP (op0
, 1);
9552 op0
= XEXP (op0
, 0);
9553 op_mode
= GET_MODE (op0
);
9556 if (op_mode
== VOIDmode
)
9557 op_mode
= GET_MODE (op1
);
9558 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9561 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9566 /* Put complex operands first and constants second. */
9567 if (GET_RTX_CLASS (code
) == 'c'
9568 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9569 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9570 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9571 || (GET_CODE (op0
) == SUBREG
9572 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9573 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9574 return gen_rtx_combine (code
, mode
, op1
, op0
);
9576 /* If we are turning off bits already known off in OP0, we need not do
9578 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9579 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9580 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
9583 return gen_rtx_combine (code
, mode
, op0
, op1
);
9587 gen_unary (code
, mode
, op0_mode
, op0
)
9589 enum machine_mode mode
, op0_mode
;
9592 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
9597 return gen_rtx_combine (code
, mode
, op0
);
9600 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9601 comparison code that will be tested.
9603 The result is a possibly different comparison code to use. *POP0 and
9604 *POP1 may be updated.
9606 It is possible that we might detect that a comparison is either always
9607 true or always false. However, we do not perform general constant
9608 folding in combine, so this knowledge isn't useful. Such tautologies
9609 should have been detected earlier. Hence we ignore all such cases. */
9611 static enum rtx_code
9612 simplify_comparison (code
, pop0
, pop1
)
9621 enum machine_mode mode
, tmode
;
9623 /* Try a few ways of applying the same transformation to both operands. */
9626 #ifndef WORD_REGISTER_OPERATIONS
9627 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9628 so check specially. */
9629 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9630 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9631 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9632 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9633 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9634 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9635 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9636 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9637 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9638 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9639 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9640 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9641 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9642 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9643 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9644 && (INTVAL (XEXP (op0
, 1))
9645 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9647 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9649 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9650 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9654 /* If both operands are the same constant shift, see if we can ignore the
9655 shift. We can if the shift is a rotate or if the bits shifted out of
9656 this shift are known to be zero for both inputs and if the type of
9657 comparison is compatible with the shift. */
9658 if (GET_CODE (op0
) == GET_CODE (op1
)
9659 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9660 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9661 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9662 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9663 || (GET_CODE (op0
) == ASHIFTRT
9664 && (code
!= GTU
&& code
!= LTU
9665 && code
!= GEU
&& code
!= GEU
)))
9666 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9667 && INTVAL (XEXP (op0
, 1)) >= 0
9668 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9669 && XEXP (op0
, 1) == XEXP (op1
, 1))
9671 enum machine_mode mode
= GET_MODE (op0
);
9672 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9673 int shift_count
= INTVAL (XEXP (op0
, 1));
9675 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9676 mask
&= (mask
>> shift_count
) << shift_count
;
9677 else if (GET_CODE (op0
) == ASHIFT
)
9678 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9680 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
9681 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
9682 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9687 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9688 SUBREGs are of the same mode, and, in both cases, the AND would
9689 be redundant if the comparison was done in the narrower mode,
9690 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9691 and the operand's possibly nonzero bits are 0xffffff01; in that case
9692 if we only care about QImode, we don't need the AND). This case
9693 occurs if the output mode of an scc insn is not SImode and
9694 STORE_FLAG_VALUE == 1 (e.g., the 386).
9696 Similarly, check for a case where the AND's are ZERO_EXTEND
9697 operations from some narrower mode even though a SUBREG is not
9700 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9701 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9702 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9704 rtx inner_op0
= XEXP (op0
, 0);
9705 rtx inner_op1
= XEXP (op1
, 0);
9706 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9707 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9710 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9711 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9712 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9713 && (GET_MODE (SUBREG_REG (inner_op0
))
9714 == GET_MODE (SUBREG_REG (inner_op1
)))
9715 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9716 <= HOST_BITS_PER_WIDE_INT
)
9717 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9718 GET_MODE (SUBREG_REG (inner_op0
)))))
9719 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9720 GET_MODE (SUBREG_REG (inner_op1
))))))
9722 op0
= SUBREG_REG (inner_op0
);
9723 op1
= SUBREG_REG (inner_op1
);
9725 /* The resulting comparison is always unsigned since we masked
9726 off the original sign bit. */
9727 code
= unsigned_condition (code
);
9733 for (tmode
= GET_CLASS_NARROWEST_MODE
9734 (GET_MODE_CLASS (GET_MODE (op0
)));
9735 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9736 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9738 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9739 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9740 code
= unsigned_condition (code
);
9749 /* If both operands are NOT, we can strip off the outer operation
9750 and adjust the comparison code for swapped operands; similarly for
9751 NEG, except that this must be an equality comparison. */
9752 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9753 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9754 && (code
== EQ
|| code
== NE
)))
9755 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9761 /* If the first operand is a constant, swap the operands and adjust the
9762 comparison code appropriately, but don't do this if the second operand
9763 is already a constant integer. */
9764 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9766 tem
= op0
, op0
= op1
, op1
= tem
;
9767 code
= swap_condition (code
);
9770 /* We now enter a loop during which we will try to simplify the comparison.
9771 For the most part, we only are concerned with comparisons with zero,
9772 but some things may really be comparisons with zero but not start
9773 out looking that way. */
9775 while (GET_CODE (op1
) == CONST_INT
)
9777 enum machine_mode mode
= GET_MODE (op0
);
9778 int mode_width
= GET_MODE_BITSIZE (mode
);
9779 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9780 int equality_comparison_p
;
9781 int sign_bit_comparison_p
;
9782 int unsigned_comparison_p
;
9783 HOST_WIDE_INT const_op
;
9785 /* We only want to handle integral modes. This catches VOIDmode,
9786 CCmode, and the floating-point modes. An exception is that we
9787 can handle VOIDmode if OP0 is a COMPARE or a comparison
9790 if (GET_MODE_CLASS (mode
) != MODE_INT
9791 && ! (mode
== VOIDmode
9792 && (GET_CODE (op0
) == COMPARE
9793 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9796 /* Get the constant we are comparing against and turn off all bits
9797 not on in our mode. */
9798 const_op
= INTVAL (op1
);
9799 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
9802 /* If we are comparing against a constant power of two and the value
9803 being compared can only have that single bit nonzero (e.g., it was
9804 `and'ed with that bit), we can replace this with a comparison
9807 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9808 || code
== LT
|| code
== LTU
)
9809 && mode_width
<= HOST_BITS_PER_WIDE_INT
9810 && exact_log2 (const_op
) >= 0
9811 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9813 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9814 op1
= const0_rtx
, const_op
= 0;
9817 /* Similarly, if we are comparing a value known to be either -1 or
9818 0 with -1, change it to the opposite comparison against zero. */
9821 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9822 || code
== GEU
|| code
== LTU
)
9823 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9825 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9826 op1
= const0_rtx
, const_op
= 0;
9829 /* Do some canonicalizations based on the comparison code. We prefer
9830 comparisons against zero and then prefer equality comparisons.
9831 If we can reduce the size of a constant, we will do that too. */
9836 /* < C is equivalent to <= (C - 1) */
9840 op1
= GEN_INT (const_op
);
9842 /* ... fall through to LE case below. */
9848 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9852 op1
= GEN_INT (const_op
);
9856 /* If we are doing a <= 0 comparison on a value known to have
9857 a zero sign bit, we can replace this with == 0. */
9858 else if (const_op
== 0
9859 && mode_width
<= HOST_BITS_PER_WIDE_INT
9860 && (nonzero_bits (op0
, mode
)
9861 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9866 /* >= C is equivalent to > (C - 1). */
9870 op1
= GEN_INT (const_op
);
9872 /* ... fall through to GT below. */
9878 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9882 op1
= GEN_INT (const_op
);
9886 /* If we are doing a > 0 comparison on a value known to have
9887 a zero sign bit, we can replace this with != 0. */
9888 else if (const_op
== 0
9889 && mode_width
<= HOST_BITS_PER_WIDE_INT
9890 && (nonzero_bits (op0
, mode
)
9891 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9896 /* < C is equivalent to <= (C - 1). */
9900 op1
= GEN_INT (const_op
);
9902 /* ... fall through ... */
9905 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9906 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9907 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9909 const_op
= 0, op1
= const0_rtx
;
9917 /* unsigned <= 0 is equivalent to == 0 */
9921 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9922 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9923 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9925 const_op
= 0, op1
= const0_rtx
;
9931 /* >= C is equivalent to < (C - 1). */
9935 op1
= GEN_INT (const_op
);
9937 /* ... fall through ... */
9940 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9941 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9942 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9944 const_op
= 0, op1
= const0_rtx
;
9952 /* unsigned > 0 is equivalent to != 0 */
9956 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9957 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9958 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9960 const_op
= 0, op1
= const0_rtx
;
9969 /* Compute some predicates to simplify code below. */
9971 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9972 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9973 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9976 /* If this is a sign bit comparison and we can do arithmetic in
9977 MODE, say that we will only be needing the sign bit of OP0. */
9978 if (sign_bit_comparison_p
9979 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9980 op0
= force_to_mode (op0
, mode
,
9982 << (GET_MODE_BITSIZE (mode
) - 1)),
9985 /* Now try cases based on the opcode of OP0. If none of the cases
9986 does a "continue", we exit this loop immediately after the
9989 switch (GET_CODE (op0
))
9992 /* If we are extracting a single bit from a variable position in
9993 a constant that has only a single bit set and are comparing it
9994 with zero, we can convert this into an equality comparison
9995 between the position and the location of the single bit. */
9997 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
9998 && XEXP (op0
, 1) == const1_rtx
9999 && equality_comparison_p
&& const_op
== 0
10000 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10002 if (BITS_BIG_ENDIAN
)
10005 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10006 if (mode
== VOIDmode
)
10008 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10010 i
= BITS_PER_WORD
- 1 - i
;
10014 op0
= XEXP (op0
, 2);
10018 /* Result is nonzero iff shift count is equal to I. */
10019 code
= reverse_condition (code
);
10023 /* ... fall through ... */
10026 tem
= expand_compound_operation (op0
);
10035 /* If testing for equality, we can take the NOT of the constant. */
10036 if (equality_comparison_p
10037 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10039 op0
= XEXP (op0
, 0);
10044 /* If just looking at the sign bit, reverse the sense of the
10046 if (sign_bit_comparison_p
)
10048 op0
= XEXP (op0
, 0);
10049 code
= (code
== GE
? LT
: GE
);
10055 /* If testing for equality, we can take the NEG of the constant. */
10056 if (equality_comparison_p
10057 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10059 op0
= XEXP (op0
, 0);
10064 /* The remaining cases only apply to comparisons with zero. */
10068 /* When X is ABS or is known positive,
10069 (neg X) is < 0 if and only if X != 0. */
10071 if (sign_bit_comparison_p
10072 && (GET_CODE (XEXP (op0
, 0)) == ABS
10073 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10074 && (nonzero_bits (XEXP (op0
, 0), mode
)
10075 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10077 op0
= XEXP (op0
, 0);
10078 code
= (code
== LT
? NE
: EQ
);
10082 /* If we have NEG of something whose two high-order bits are the
10083 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10084 if (num_sign_bit_copies (op0
, mode
) >= 2)
10086 op0
= XEXP (op0
, 0);
10087 code
= swap_condition (code
);
10093 /* If we are testing equality and our count is a constant, we
10094 can perform the inverse operation on our RHS. */
10095 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10096 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10097 op1
, XEXP (op0
, 1))) != 0)
10099 op0
= XEXP (op0
, 0);
10104 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10105 a particular bit. Convert it to an AND of a constant of that
10106 bit. This will be converted into a ZERO_EXTRACT. */
10107 if (const_op
== 0 && sign_bit_comparison_p
10108 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10109 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10111 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10114 - INTVAL (XEXP (op0
, 1)))));
10115 code
= (code
== LT
? NE
: EQ
);
10119 /* ... fall through ... */
10122 /* ABS is ignorable inside an equality comparison with zero. */
10123 if (const_op
== 0 && equality_comparison_p
)
10125 op0
= XEXP (op0
, 0);
10132 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10133 to (compare FOO CONST) if CONST fits in FOO's mode and we
10134 are either testing inequality or have an unsigned comparison
10135 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10136 if (! unsigned_comparison_p
10137 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10138 <= HOST_BITS_PER_WIDE_INT
)
10139 && ((unsigned HOST_WIDE_INT
) const_op
10140 < (((unsigned HOST_WIDE_INT
) 1
10141 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10143 op0
= XEXP (op0
, 0);
10149 /* Check for the case where we are comparing A - C1 with C2,
10150 both constants are smaller than 1/2 the maximum positive
10151 value in MODE, and the comparison is equality or unsigned.
10152 In that case, if A is either zero-extended to MODE or has
10153 sufficient sign bits so that the high-order bit in MODE
10154 is a copy of the sign in the inner mode, we can prove that it is
10155 safe to do the operation in the wider mode. This simplifies
10156 many range checks. */
10158 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10159 && subreg_lowpart_p (op0
)
10160 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10161 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10162 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10163 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
10164 < (HOST_WIDE_INT
)(GET_MODE_MASK (mode
) / 2))
10165 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10166 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10167 GET_MODE (SUBREG_REG (op0
)))
10168 & ~ GET_MODE_MASK (mode
))
10169 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10170 GET_MODE (SUBREG_REG (op0
)))
10171 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10172 - GET_MODE_BITSIZE (mode
)))))
10174 op0
= SUBREG_REG (op0
);
10178 /* If the inner mode is narrower and we are extracting the low part,
10179 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10180 if (subreg_lowpart_p (op0
)
10181 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10182 /* Fall through */ ;
10186 /* ... fall through ... */
10189 if ((unsigned_comparison_p
|| equality_comparison_p
)
10190 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10191 <= HOST_BITS_PER_WIDE_INT
)
10192 && ((unsigned HOST_WIDE_INT
) const_op
10193 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10195 op0
= XEXP (op0
, 0);
10201 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10202 this for equality comparisons due to pathological cases involving
10204 if (equality_comparison_p
10205 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10206 op1
, XEXP (op0
, 1))))
10208 op0
= XEXP (op0
, 0);
10213 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10214 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10215 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10217 op0
= XEXP (XEXP (op0
, 0), 0);
10218 code
= (code
== LT
? EQ
: NE
);
10224 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10225 (eq B (minus A C)), whichever simplifies. We can only do
10226 this for equality comparisons due to pathological cases involving
10228 if (equality_comparison_p
10229 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10230 XEXP (op0
, 1), op1
)))
10232 op0
= XEXP (op0
, 0);
10237 if (equality_comparison_p
10238 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10239 XEXP (op0
, 0), op1
)))
10241 op0
= XEXP (op0
, 1);
10246 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10247 of bits in X minus 1, is one iff X > 0. */
10248 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10249 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10250 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10251 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10253 op0
= XEXP (op0
, 1);
10254 code
= (code
== GE
? LE
: GT
);
10260 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10261 if C is zero or B is a constant. */
10262 if (equality_comparison_p
10263 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10264 XEXP (op0
, 1), op1
)))
10266 op0
= XEXP (op0
, 0);
10273 case LT
: case LTU
: case LE
: case LEU
:
10274 case GT
: case GTU
: case GE
: case GEU
:
10275 /* We can't do anything if OP0 is a condition code value, rather
10276 than an actual data value. */
10279 || XEXP (op0
, 0) == cc0_rtx
10281 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10284 /* Get the two operands being compared. */
10285 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10286 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10288 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10290 /* Check for the cases where we simply want the result of the
10291 earlier test or the opposite of that result. */
10293 || (code
== EQ
&& reversible_comparison_p (op0
))
10294 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10295 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10296 && (STORE_FLAG_VALUE
10297 & (((HOST_WIDE_INT
) 1
10298 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10300 || (code
== GE
&& reversible_comparison_p (op0
)))))
10302 code
= (code
== LT
|| code
== NE
10303 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
10304 op0
= tem
, op1
= tem1
;
10310 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10312 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10313 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10314 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10316 op0
= XEXP (op0
, 1);
10317 code
= (code
== GE
? GT
: LE
);
10323 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10324 will be converted to a ZERO_EXTRACT later. */
10325 if (const_op
== 0 && equality_comparison_p
10326 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10327 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10329 op0
= simplify_and_const_int
10330 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10332 XEXP (XEXP (op0
, 0), 1)),
10333 (HOST_WIDE_INT
) 1);
10337 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10338 zero and X is a comparison and C1 and C2 describe only bits set
10339 in STORE_FLAG_VALUE, we can compare with X. */
10340 if (const_op
== 0 && equality_comparison_p
10341 && mode_width
<= HOST_BITS_PER_WIDE_INT
10342 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10343 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10344 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10345 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10346 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10348 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10349 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10350 if ((~ STORE_FLAG_VALUE
& mask
) == 0
10351 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10352 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10353 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10355 op0
= XEXP (XEXP (op0
, 0), 0);
10360 /* If we are doing an equality comparison of an AND of a bit equal
10361 to the sign bit, replace this with a LT or GE comparison of
10362 the underlying value. */
10363 if (equality_comparison_p
10365 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10366 && mode_width
<= HOST_BITS_PER_WIDE_INT
10367 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10368 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10370 op0
= XEXP (op0
, 0);
10371 code
= (code
== EQ
? GE
: LT
);
10375 /* If this AND operation is really a ZERO_EXTEND from a narrower
10376 mode, the constant fits within that mode, and this is either an
10377 equality or unsigned comparison, try to do this comparison in
10378 the narrower mode. */
10379 if ((equality_comparison_p
|| unsigned_comparison_p
)
10380 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10381 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10382 & GET_MODE_MASK (mode
))
10384 && const_op
>> i
== 0
10385 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10387 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10391 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10392 in both M1 and M2 and the SUBREG is either paradoxical or
10393 represents the low part, permute the SUBREG and the AND and
10395 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10397 #ifdef WORD_REGISTER_OPERATIONS
10399 > (GET_MODE_BITSIZE
10400 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10401 && mode_width
<= BITS_PER_WORD
)
10404 <= (GET_MODE_BITSIZE
10405 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10406 && subreg_lowpart_p (XEXP (op0
, 0))))
10407 #ifndef WORD_REGISTER_OPERATIONS
10408 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10409 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10410 As originally written the upper bits have a defined value
10411 due to the AND operation. However, if we commute the AND
10412 inside the SUBREG then they no longer have defined values
10413 and the meaning of the code has been changed. */
10414 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10415 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10417 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10418 && mode_width
<= HOST_BITS_PER_WIDE_INT
10419 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10420 <= HOST_BITS_PER_WIDE_INT
)
10421 && (INTVAL (XEXP (op0
, 1)) & ~ mask
) == 0
10422 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10423 & INTVAL (XEXP (op0
, 1)))
10424 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10425 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10426 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10430 = gen_lowpart_for_combine
10432 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10433 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10440 /* If we have (compare (ashift FOO N) (const_int C)) and
10441 the high order N bits of FOO (N+1 if an inequality comparison)
10442 are known to be zero, we can do this by comparing FOO with C
10443 shifted right N bits so long as the low-order N bits of C are
10445 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10446 && INTVAL (XEXP (op0
, 1)) >= 0
10447 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10448 < HOST_BITS_PER_WIDE_INT
)
10450 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10451 && mode_width
<= HOST_BITS_PER_WIDE_INT
10452 && (nonzero_bits (XEXP (op0
, 0), mode
)
10453 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
10454 + ! equality_comparison_p
))) == 0)
10456 /* We must perform a logical shift, not an arithmetic one,
10457 as we want the top N bits of C to be zero. */
10458 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10460 temp
>>= INTVAL (XEXP (op0
, 1));
10461 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10462 op0
= XEXP (op0
, 0);
10466 /* If we are doing a sign bit comparison, it means we are testing
10467 a particular bit. Convert it to the appropriate AND. */
10468 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10469 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10471 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10474 - INTVAL (XEXP (op0
, 1)))));
10475 code
= (code
== LT
? NE
: EQ
);
10479 /* If this an equality comparison with zero and we are shifting
10480 the low bit to the sign bit, we can convert this to an AND of the
10482 if (const_op
== 0 && equality_comparison_p
10483 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10484 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10486 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10487 (HOST_WIDE_INT
) 1);
10493 /* If this is an equality comparison with zero, we can do this
10494 as a logical shift, which might be much simpler. */
10495 if (equality_comparison_p
&& const_op
== 0
10496 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10498 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10500 INTVAL (XEXP (op0
, 1)));
10504 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10505 do the comparison in a narrower mode. */
10506 if (! unsigned_comparison_p
10507 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10508 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10509 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10510 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10511 MODE_INT
, 1)) != BLKmode
10512 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10513 || ((unsigned HOST_WIDE_INT
) - const_op
10514 <= GET_MODE_MASK (tmode
))))
10516 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10520 /* Likewise if OP0 is a PLUS of a sign extension with a
10521 constant, which is usually represented with the PLUS
10522 between the shifts. */
10523 if (! unsigned_comparison_p
10524 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10525 && GET_CODE (XEXP (op0
, 0)) == PLUS
10526 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10527 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10528 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10529 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10530 MODE_INT
, 1)) != BLKmode
10531 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10532 || ((unsigned HOST_WIDE_INT
) - const_op
10533 <= GET_MODE_MASK (tmode
))))
10535 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10536 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10537 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10540 op0
= gen_binary (PLUS
, tmode
,
10541 gen_lowpart_for_combine (tmode
, inner
),
10546 /* ... fall through ... */
10548 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10549 the low order N bits of FOO are known to be zero, we can do this
10550 by comparing FOO with C shifted left N bits so long as no
10551 overflow occurs. */
10552 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10553 && INTVAL (XEXP (op0
, 1)) >= 0
10554 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10555 && mode_width
<= HOST_BITS_PER_WIDE_INT
10556 && (nonzero_bits (XEXP (op0
, 0), mode
)
10557 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10559 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10562 const_op
<<= INTVAL (XEXP (op0
, 1));
10563 op1
= GEN_INT (const_op
);
10564 op0
= XEXP (op0
, 0);
10568 /* If we are using this shift to extract just the sign bit, we
10569 can replace this with an LT or GE comparison. */
10571 && (equality_comparison_p
|| sign_bit_comparison_p
)
10572 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10573 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10575 op0
= XEXP (op0
, 0);
10576 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10588 /* Now make any compound operations involved in this comparison. Then,
10589 check for an outmost SUBREG on OP0 that is not doing anything or is
10590 paradoxical. The latter case can only occur when it is known that the
10591 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10592 We can never remove a SUBREG for a non-equality comparison because the
10593 sign bit is in a different place in the underlying object. */
10595 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10596 op1
= make_compound_operation (op1
, SET
);
10598 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10599 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10600 && (code
== NE
|| code
== EQ
)
10601 && ((GET_MODE_SIZE (GET_MODE (op0
))
10602 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10604 op0
= SUBREG_REG (op0
);
10605 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10608 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10609 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10610 && (code
== NE
|| code
== EQ
)
10611 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10612 <= HOST_BITS_PER_WIDE_INT
)
10613 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10614 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
10615 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10617 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10618 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
10619 op0
= SUBREG_REG (op0
), op1
= tem
;
10621 /* We now do the opposite procedure: Some machines don't have compare
10622 insns in all modes. If OP0's mode is an integer mode smaller than a
10623 word and we can't do a compare in that mode, see if there is a larger
10624 mode for which we can do the compare. There are a number of cases in
10625 which we can use the wider mode. */
10627 mode
= GET_MODE (op0
);
10628 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10629 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10630 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10631 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10633 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10634 tmode
= GET_MODE_WIDER_MODE (tmode
))
10635 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10637 /* If the only nonzero bits in OP0 and OP1 are those in the
10638 narrower mode and this is an equality or unsigned comparison,
10639 we can use the wider mode. Similarly for sign-extended
10640 values, in which case it is true for all comparisons. */
10641 if (((code
== EQ
|| code
== NE
10642 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10643 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
10644 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
10645 || ((num_sign_bit_copies (op0
, tmode
)
10646 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10647 && (num_sign_bit_copies (op1
, tmode
)
10648 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10650 /* If OP0 is an AND and we don't have an AND in MODE either,
10651 make a new AND in the proper mode. */
10652 if (GET_CODE (op0
) == AND
10653 && (add_optab
->handlers
[(int) mode
].insn_code
10654 == CODE_FOR_nothing
))
10655 op0
= gen_binary (AND
, tmode
,
10656 gen_lowpart_for_combine (tmode
,
10658 gen_lowpart_for_combine (tmode
,
10661 op0
= gen_lowpart_for_combine (tmode
, op0
);
10662 op1
= gen_lowpart_for_combine (tmode
, op1
);
10666 /* If this is a test for negative, we can make an explicit
10667 test of the sign bit. */
10669 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10670 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10672 op0
= gen_binary (AND
, tmode
,
10673 gen_lowpart_for_combine (tmode
, op0
),
10674 GEN_INT ((HOST_WIDE_INT
) 1
10675 << (GET_MODE_BITSIZE (mode
) - 1)));
10676 code
= (code
== LT
) ? NE
: EQ
;
10681 #ifdef CANONICALIZE_COMPARISON
10682 /* If this machine only supports a subset of valid comparisons, see if we
10683 can convert an unsupported one into a supported one. */
10684 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10693 /* Return 1 if we know that X, a comparison operation, is not operating
10694 on a floating-point value or is EQ or NE, meaning that we can safely
10698 reversible_comparison_p (x
)
10701 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
10703 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
10706 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
10709 case MODE_PARTIAL_INT
:
10710 case MODE_COMPLEX_INT
:
10714 /* If the mode of the condition codes tells us that this is safe,
10715 we need look no further. */
10716 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
10719 /* Otherwise try and find where the condition codes were last set and
10721 x
= get_last_value (XEXP (x
, 0));
10722 return (x
&& GET_CODE (x
) == COMPARE
10723 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
10730 /* Utility function for following routine. Called when X is part of a value
10731 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10732 for each register mentioned. Similar to mention_regs in cse.c */
10735 update_table_tick (x
)
10738 register enum rtx_code code
= GET_CODE (x
);
10739 register const char *fmt
= GET_RTX_FORMAT (code
);
10744 int regno
= REGNO (x
);
10745 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10746 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10748 for (i
= regno
; i
< endregno
; i
++)
10749 reg_last_set_table_tick
[i
] = label_tick
;
10754 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10755 /* Note that we can't have an "E" in values stored; see
10756 get_last_value_validate. */
10758 update_table_tick (XEXP (x
, i
));
10761 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10762 are saying that the register is clobbered and we no longer know its
10763 value. If INSN is zero, don't update reg_last_set; this is only permitted
10764 with VALUE also zero and is used to invalidate the register. */
10767 record_value_for_reg (reg
, insn
, value
)
10772 int regno
= REGNO (reg
);
10773 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10774 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
10777 /* If VALUE contains REG and we have a previous value for REG, substitute
10778 the previous value. */
10779 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10783 /* Set things up so get_last_value is allowed to see anything set up to
10785 subst_low_cuid
= INSN_CUID (insn
);
10786 tem
= get_last_value (reg
);
10788 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10789 it isn't going to be useful and will take a lot of time to process,
10790 so just use the CLOBBER. */
10794 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
10795 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
10796 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10797 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10798 tem
= XEXP (tem
, 0);
10800 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10804 /* For each register modified, show we don't know its value, that
10805 we don't know about its bitwise content, that its value has been
10806 updated, and that we don't know the location of the death of the
10808 for (i
= regno
; i
< endregno
; i
++)
10811 reg_last_set
[i
] = insn
;
10812 reg_last_set_value
[i
] = 0;
10813 reg_last_set_mode
[i
] = 0;
10814 reg_last_set_nonzero_bits
[i
] = 0;
10815 reg_last_set_sign_bit_copies
[i
] = 0;
10816 reg_last_death
[i
] = 0;
10819 /* Mark registers that are being referenced in this value. */
10821 update_table_tick (value
);
10823 /* Now update the status of each register being set.
10824 If someone is using this register in this block, set this register
10825 to invalid since we will get confused between the two lives in this
10826 basic block. This makes using this register always invalid. In cse, we
10827 scan the table to invalidate all entries using this register, but this
10828 is too much work for us. */
10830 for (i
= regno
; i
< endregno
; i
++)
10832 reg_last_set_label
[i
] = label_tick
;
10833 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
10834 reg_last_set_invalid
[i
] = 1;
10836 reg_last_set_invalid
[i
] = 0;
10839 /* The value being assigned might refer to X (like in "x++;"). In that
10840 case, we must replace it with (clobber (const_int 0)) to prevent
10842 if (value
&& ! get_last_value_validate (&value
, insn
,
10843 reg_last_set_label
[regno
], 0))
10845 value
= copy_rtx (value
);
10846 if (! get_last_value_validate (&value
, insn
,
10847 reg_last_set_label
[regno
], 1))
10851 /* For the main register being modified, update the value, the mode, the
10852 nonzero bits, and the number of sign bit copies. */
10854 reg_last_set_value
[regno
] = value
;
10858 subst_low_cuid
= INSN_CUID (insn
);
10859 reg_last_set_mode
[regno
] = GET_MODE (reg
);
10860 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
10861 reg_last_set_sign_bit_copies
[regno
]
10862 = num_sign_bit_copies (value
, GET_MODE (reg
));
10866 /* Called via note_stores from record_dead_and_set_regs to handle one
10867 SET or CLOBBER in an insn. DATA is the instruction in which the
10868 set is occurring. */
10871 record_dead_and_set_regs_1 (dest
, setter
, data
)
10875 rtx record_dead_insn
= (rtx
) data
;
10877 if (GET_CODE (dest
) == SUBREG
)
10878 dest
= SUBREG_REG (dest
);
10880 if (GET_CODE (dest
) == REG
)
10882 /* If we are setting the whole register, we know its value. Otherwise
10883 show that we don't know the value. We can handle SUBREG in
10885 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10886 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10887 else if (GET_CODE (setter
) == SET
10888 && GET_CODE (SET_DEST (setter
)) == SUBREG
10889 && SUBREG_REG (SET_DEST (setter
)) == dest
10890 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10891 && subreg_lowpart_p (SET_DEST (setter
)))
10892 record_value_for_reg (dest
, record_dead_insn
,
10893 gen_lowpart_for_combine (GET_MODE (dest
),
10894 SET_SRC (setter
)));
10896 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10898 else if (GET_CODE (dest
) == MEM
10899 /* Ignore pushes, they clobber nothing. */
10900 && ! push_operand (dest
, GET_MODE (dest
)))
10901 mem_last_set
= INSN_CUID (record_dead_insn
);
10904 /* Update the records of when each REG was most recently set or killed
10905 for the things done by INSN. This is the last thing done in processing
10906 INSN in the combiner loop.
10908 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10909 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10910 and also the similar information mem_last_set (which insn most recently
10911 modified memory) and last_call_cuid (which insn was the most recent
10912 subroutine call). */
10915 record_dead_and_set_regs (insn
)
10921 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10923 if (REG_NOTE_KIND (link
) == REG_DEAD
10924 && GET_CODE (XEXP (link
, 0)) == REG
)
10926 int regno
= REGNO (XEXP (link
, 0));
10928 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10929 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
10932 for (i
= regno
; i
< endregno
; i
++)
10933 reg_last_death
[i
] = insn
;
10935 else if (REG_NOTE_KIND (link
) == REG_INC
)
10936 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10939 if (GET_CODE (insn
) == CALL_INSN
)
10941 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10942 if (call_used_regs
[i
])
10944 reg_last_set_value
[i
] = 0;
10945 reg_last_set_mode
[i
] = 0;
10946 reg_last_set_nonzero_bits
[i
] = 0;
10947 reg_last_set_sign_bit_copies
[i
] = 0;
10948 reg_last_death
[i
] = 0;
10951 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10954 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
10957 /* Utility routine for the following function. Verify that all the registers
10958 mentioned in *LOC are valid when *LOC was part of a value set when
10959 label_tick == TICK. Return 0 if some are not.
10961 If REPLACE is non-zero, replace the invalid reference with
10962 (clobber (const_int 0)) and return 1. This replacement is useful because
10963 we often can get useful information about the form of a value (e.g., if
10964 it was produced by a shift that always produces -1 or 0) even though
10965 we don't know exactly what registers it was produced from. */
10968 get_last_value_validate (loc
, insn
, tick
, replace
)
10975 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10976 int len
= GET_RTX_LENGTH (GET_CODE (x
));
10979 if (GET_CODE (x
) == REG
)
10981 int regno
= REGNO (x
);
10982 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10983 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10986 for (j
= regno
; j
< endregno
; j
++)
10987 if (reg_last_set_invalid
[j
]
10988 /* If this is a pseudo-register that was only set once and not
10989 live at the beginning of the function, it is always valid. */
10990 || (! (regno
>= FIRST_PSEUDO_REGISTER
10991 && REG_N_SETS (regno
) == 1
10992 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))
10993 && reg_last_set_label
[j
] > tick
))
10996 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11002 /* If this is a memory reference, make sure that there were
11003 no stores after it that might have clobbered the value. We don't
11004 have alias info, so we assume any store invalidates it. */
11005 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11006 && INSN_CUID (insn
) <= mem_last_set
)
11009 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11013 for (i
= 0; i
< len
; i
++)
11015 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11016 /* Don't bother with these. They shouldn't occur anyway. */
11020 /* If we haven't found a reason for it to be invalid, it is valid. */
11024 /* Get the last value assigned to X, if known. Some registers
11025 in the value may be replaced with (clobber (const_int 0)) if their value
11026 is known longer known reliably. */
11035 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11036 then convert it to the desired mode. If this is a paradoxical SUBREG,
11037 we cannot predict what values the "extra" bits might have. */
11038 if (GET_CODE (x
) == SUBREG
11039 && subreg_lowpart_p (x
)
11040 && (GET_MODE_SIZE (GET_MODE (x
))
11041 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11042 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11043 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11045 if (GET_CODE (x
) != REG
)
11049 value
= reg_last_set_value
[regno
];
11051 /* If we don't have a value, or if it isn't for this basic block and
11052 it's either a hard register, set more than once, or it's a live
11053 at the beginning of the function, return 0.
11055 Because if it's not live at the beginnning of the function then the reg
11056 is always set before being used (is never used without being set).
11057 And, if it's set only once, and it's always set before use, then all
11058 uses must have the same last value, even if it's not from this basic
11062 || (reg_last_set_label
[regno
] != label_tick
11063 && (regno
< FIRST_PSEUDO_REGISTER
11064 || REG_N_SETS (regno
) != 1
11065 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))))
11068 /* If the value was set in a later insn than the ones we are processing,
11069 we can't use it even if the register was only set once. */
11070 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11073 /* If the value has all its registers valid, return it. */
11074 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11075 reg_last_set_label
[regno
], 0))
11078 /* Otherwise, make a copy and replace any invalid register with
11079 (clobber (const_int 0)). If that fails for some reason, return 0. */
11081 value
= copy_rtx (value
);
11082 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11083 reg_last_set_label
[regno
], 1))
11089 /* Return nonzero if expression X refers to a REG or to memory
11090 that is set in an instruction more recent than FROM_CUID. */
11093 use_crosses_set_p (x
, from_cuid
)
11097 register const char *fmt
;
11099 register enum rtx_code code
= GET_CODE (x
);
11103 register int regno
= REGNO (x
);
11104 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11105 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11107 #ifdef PUSH_ROUNDING
11108 /* Don't allow uses of the stack pointer to be moved,
11109 because we don't know whether the move crosses a push insn. */
11110 if (regno
== STACK_POINTER_REGNUM
)
11113 for (;regno
< endreg
; regno
++)
11114 if (reg_last_set
[regno
]
11115 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11120 if (code
== MEM
&& mem_last_set
> from_cuid
)
11123 fmt
= GET_RTX_FORMAT (code
);
11125 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11130 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11131 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11134 else if (fmt
[i
] == 'e'
11135 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11141 /* Define three variables used for communication between the following
11144 static int reg_dead_regno
, reg_dead_endregno
;
11145 static int reg_dead_flag
;
11147 /* Function called via note_stores from reg_dead_at_p.
11149 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11150 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11153 reg_dead_at_p_1 (dest
, x
, data
)
11156 void *data ATTRIBUTE_UNUSED
;
11158 int regno
, endregno
;
11160 if (GET_CODE (dest
) != REG
)
11163 regno
= REGNO (dest
);
11164 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11165 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11167 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11168 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11171 /* Return non-zero if REG is known to be dead at INSN.
11173 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11174 referencing REG, it is dead. If we hit a SET referencing REG, it is
11175 live. Otherwise, see if it is live or dead at the start of the basic
11176 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11177 must be assumed to be always live. */
11180 reg_dead_at_p (reg
, insn
)
11186 /* Set variables for reg_dead_at_p_1. */
11187 reg_dead_regno
= REGNO (reg
);
11188 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11189 ? HARD_REGNO_NREGS (reg_dead_regno
,
11195 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11196 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11198 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11199 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11203 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11204 beginning of function. */
11205 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11206 insn
= prev_nonnote_insn (insn
))
11208 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11210 return reg_dead_flag
== 1 ? 1 : 0;
11212 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11216 /* Get the basic block number that we were in. */
11221 for (block
= 0; block
< n_basic_blocks
; block
++)
11222 if (insn
== BLOCK_HEAD (block
))
11225 if (block
== n_basic_blocks
)
11229 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11230 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11236 /* Note hard registers in X that are used. This code is similar to
11237 that in flow.c, but much simpler since we don't care about pseudos. */
11240 mark_used_regs_combine (x
)
11243 register RTX_CODE code
= GET_CODE (x
);
11244 register int regno
;
11256 case ADDR_DIFF_VEC
:
11259 /* CC0 must die in the insn after it is set, so we don't need to take
11260 special note of it here. */
11266 /* If we are clobbering a MEM, mark any hard registers inside the
11267 address as used. */
11268 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11269 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11274 /* A hard reg in a wide mode may really be multiple registers.
11275 If so, mark all of them just like the first. */
11276 if (regno
< FIRST_PSEUDO_REGISTER
)
11278 /* None of this applies to the stack, frame or arg pointers */
11279 if (regno
== STACK_POINTER_REGNUM
11280 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11281 || regno
== HARD_FRAME_POINTER_REGNUM
11283 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11284 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11286 || regno
== FRAME_POINTER_REGNUM
)
11289 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11291 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
11297 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11299 register rtx testreg
= SET_DEST (x
);
11301 while (GET_CODE (testreg
) == SUBREG
11302 || GET_CODE (testreg
) == ZERO_EXTRACT
11303 || GET_CODE (testreg
) == SIGN_EXTRACT
11304 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11305 testreg
= XEXP (testreg
, 0);
11307 if (GET_CODE (testreg
) == MEM
)
11308 mark_used_regs_combine (XEXP (testreg
, 0));
11310 mark_used_regs_combine (SET_SRC (x
));
11318 /* Recursively scan the operands of this expression. */
11321 register const char *fmt
= GET_RTX_FORMAT (code
);
11323 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11326 mark_used_regs_combine (XEXP (x
, i
));
11327 else if (fmt
[i
] == 'E')
11331 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11332 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11339 /* Remove register number REGNO from the dead registers list of INSN.
11341 Return the note used to record the death, if there was one. */
11344 remove_death (regno
, insn
)
11348 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11352 REG_N_DEATHS (regno
)--;
11353 remove_note (insn
, note
);
11359 /* For each register (hardware or pseudo) used within expression X, if its
11360 death is in an instruction with cuid between FROM_CUID (inclusive) and
11361 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11362 list headed by PNOTES.
11364 That said, don't move registers killed by maybe_kill_insn.
11366 This is done when X is being merged by combination into TO_INSN. These
11367 notes will then be distributed as needed. */
11370 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11372 rtx maybe_kill_insn
;
11377 register const char *fmt
;
11378 register int len
, i
;
11379 register enum rtx_code code
= GET_CODE (x
);
11383 register int regno
= REGNO (x
);
11384 register rtx where_dead
= reg_last_death
[regno
];
11385 register rtx before_dead
, after_dead
;
11387 /* Don't move the register if it gets killed in between from and to */
11388 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11389 && !reg_referenced_p (x
, maybe_kill_insn
))
11392 /* WHERE_DEAD could be a USE insn made by combine, so first we
11393 make sure that we have insns with valid INSN_CUID values. */
11394 before_dead
= where_dead
;
11395 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11396 before_dead
= PREV_INSN (before_dead
);
11397 after_dead
= where_dead
;
11398 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11399 after_dead
= NEXT_INSN (after_dead
);
11401 if (before_dead
&& after_dead
11402 && INSN_CUID (before_dead
) >= from_cuid
11403 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11404 || (where_dead
!= after_dead
11405 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11407 rtx note
= remove_death (regno
, where_dead
);
11409 /* It is possible for the call above to return 0. This can occur
11410 when reg_last_death points to I2 or I1 that we combined with.
11411 In that case make a new note.
11413 We must also check for the case where X is a hard register
11414 and NOTE is a death note for a range of hard registers
11415 including X. In that case, we must put REG_DEAD notes for
11416 the remaining registers in place of NOTE. */
11418 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11419 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11420 > GET_MODE_SIZE (GET_MODE (x
))))
11422 int deadregno
= REGNO (XEXP (note
, 0));
11424 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11425 GET_MODE (XEXP (note
, 0))));
11426 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11429 for (i
= deadregno
; i
< deadend
; i
++)
11430 if (i
< regno
|| i
>= ourend
)
11431 REG_NOTES (where_dead
)
11432 = gen_rtx_EXPR_LIST (REG_DEAD
,
11433 gen_rtx_REG (reg_raw_mode
[i
], i
),
11434 REG_NOTES (where_dead
));
11436 /* If we didn't find any note, or if we found a REG_DEAD note that
11437 covers only part of the given reg, and we have a multi-reg hard
11438 register, then to be safe we must check for REG_DEAD notes
11439 for each register other than the first. They could have
11440 their own REG_DEAD notes lying around. */
11441 else if ((note
== 0
11443 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11444 < GET_MODE_SIZE (GET_MODE (x
)))))
11445 && regno
< FIRST_PSEUDO_REGISTER
11446 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11448 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11453 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11457 for (i
= regno
+ offset
; i
< ourend
; i
++)
11458 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11459 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11462 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11464 XEXP (note
, 1) = *pnotes
;
11468 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11470 REG_N_DEATHS (regno
)++;
11476 else if (GET_CODE (x
) == SET
)
11478 rtx dest
= SET_DEST (x
);
11480 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11482 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11483 that accesses one word of a multi-word item, some
11484 piece of everything register in the expression is used by
11485 this insn, so remove any old death. */
11487 if (GET_CODE (dest
) == ZERO_EXTRACT
11488 || GET_CODE (dest
) == STRICT_LOW_PART
11489 || (GET_CODE (dest
) == SUBREG
11490 && (((GET_MODE_SIZE (GET_MODE (dest
))
11491 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11492 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11493 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11495 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11499 /* If this is some other SUBREG, we know it replaces the entire
11500 value, so use that as the destination. */
11501 if (GET_CODE (dest
) == SUBREG
)
11502 dest
= SUBREG_REG (dest
);
11504 /* If this is a MEM, adjust deaths of anything used in the address.
11505 For a REG (the only other possibility), the entire value is
11506 being replaced so the old value is not used in this insn. */
11508 if (GET_CODE (dest
) == MEM
)
11509 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11514 else if (GET_CODE (x
) == CLOBBER
)
11517 len
= GET_RTX_LENGTH (code
);
11518 fmt
= GET_RTX_FORMAT (code
);
11520 for (i
= 0; i
< len
; i
++)
11525 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11526 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11529 else if (fmt
[i
] == 'e')
11530 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11534 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11535 pattern of an insn. X must be a REG. */
11538 reg_bitfield_target_p (x
, body
)
11544 if (GET_CODE (body
) == SET
)
11546 rtx dest
= SET_DEST (body
);
11548 int regno
, tregno
, endregno
, endtregno
;
11550 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11551 target
= XEXP (dest
, 0);
11552 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11553 target
= SUBREG_REG (XEXP (dest
, 0));
11557 if (GET_CODE (target
) == SUBREG
)
11558 target
= SUBREG_REG (target
);
11560 if (GET_CODE (target
) != REG
)
11563 tregno
= REGNO (target
), regno
= REGNO (x
);
11564 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11565 return target
== x
;
11567 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11568 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11570 return endregno
> tregno
&& regno
< endtregno
;
11573 else if (GET_CODE (body
) == PARALLEL
)
11574 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11575 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11581 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11582 as appropriate. I3 and I2 are the insns resulting from the combination
11583 insns including FROM (I2 may be zero).
11585 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11586 not need REG_DEAD notes because they are being substituted for. This
11587 saves searching in the most common cases.
11589 Each note in the list is either ignored or placed on some insns, depending
11590 on the type of note. */
11593 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11597 rtx elim_i2
, elim_i1
;
11599 rtx note
, next_note
;
11602 for (note
= notes
; note
; note
= next_note
)
11604 rtx place
= 0, place2
= 0;
11606 /* If this NOTE references a pseudo register, ensure it references
11607 the latest copy of that register. */
11608 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11609 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11610 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11612 next_note
= XEXP (note
, 1);
11613 switch (REG_NOTE_KIND (note
))
11616 case REG_EXEC_COUNT
:
11617 /* Doesn't matter much where we put this, as long as it's somewhere.
11618 It is preferable to keep these notes on branches, which is most
11619 likely to be i3. */
11623 case REG_EH_REGION
:
11624 case REG_EH_RETHROW
:
11625 /* These notes must remain with the call. It should not be
11626 possible for both I2 and I3 to be a call. */
11627 if (GET_CODE (i3
) == CALL_INSN
)
11629 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11636 /* Any clobbers for i3 may still exist, and so we must process
11637 REG_UNUSED notes from that insn.
11639 Any clobbers from i2 or i1 can only exist if they were added by
11640 recog_for_combine. In that case, recog_for_combine created the
11641 necessary REG_UNUSED notes. Trying to keep any original
11642 REG_UNUSED notes from these insns can cause incorrect output
11643 if it is for the same register as the original i3 dest.
11644 In that case, we will notice that the register is set in i3,
11645 and then add a REG_UNUSED note for the destination of i3, which
11646 is wrong. However, it is possible to have REG_UNUSED notes from
11647 i2 or i1 for register which were both used and clobbered, so
11648 we keep notes from i2 or i1 if they will turn into REG_DEAD
11651 /* If this register is set or clobbered in I3, put the note there
11652 unless there is one already. */
11653 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11655 if (from_insn
!= i3
)
11658 if (! (GET_CODE (XEXP (note
, 0)) == REG
11659 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11660 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11663 /* Otherwise, if this register is used by I3, then this register
11664 now dies here, so we must put a REG_DEAD note here unless there
11666 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11667 && ! (GET_CODE (XEXP (note
, 0)) == REG
11668 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
11669 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11671 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11680 /* These notes say something about results of an insn. We can
11681 only support them if they used to be on I3 in which case they
11682 remain on I3. Otherwise they are ignored.
11684 If the note refers to an expression that is not a constant, we
11685 must also ignore the note since we cannot tell whether the
11686 equivalence is still true. It might be possible to do
11687 slightly better than this (we only have a problem if I2DEST
11688 or I1DEST is present in the expression), but it doesn't
11689 seem worth the trouble. */
11691 if (from_insn
== i3
11692 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11697 case REG_NO_CONFLICT
:
11698 /* These notes say something about how a register is used. They must
11699 be present on any use of the register in I2 or I3. */
11700 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11703 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11713 /* This can show up in several ways -- either directly in the
11714 pattern, or hidden off in the constant pool with (or without?)
11715 a REG_EQUAL note. */
11716 /* ??? Ignore the without-reg_equal-note problem for now. */
11717 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11718 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11719 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11720 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11724 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11725 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11726 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11727 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11737 /* It is too much trouble to try to see if this note is still
11738 correct in all situations. It is better to simply delete it. */
11742 /* If the insn previously containing this note still exists,
11743 put it back where it was. Otherwise move it to the previous
11744 insn. Adjust the corresponding REG_LIBCALL note. */
11745 if (GET_CODE (from_insn
) != NOTE
)
11749 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
11750 place
= prev_real_insn (from_insn
);
11752 XEXP (tem
, 0) = place
;
11757 /* This is handled similarly to REG_RETVAL. */
11758 if (GET_CODE (from_insn
) != NOTE
)
11762 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
11763 place
= next_real_insn (from_insn
);
11765 XEXP (tem
, 0) = place
;
11770 /* If the register is used as an input in I3, it dies there.
11771 Similarly for I2, if it is non-zero and adjacent to I3.
11773 If the register is not used as an input in either I3 or I2
11774 and it is not one of the registers we were supposed to eliminate,
11775 there are two possibilities. We might have a non-adjacent I2
11776 or we might have somehow eliminated an additional register
11777 from a computation. For example, we might have had A & B where
11778 we discover that B will always be zero. In this case we will
11779 eliminate the reference to A.
11781 In both cases, we must search to see if we can find a previous
11782 use of A and put the death note there. */
11785 && GET_CODE (from_insn
) == CALL_INSN
11786 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
11788 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
11790 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
11791 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11794 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
11797 /* If the register is used in both I2 and I3 and it dies in I3,
11798 we might have added another reference to it. If reg_n_refs
11799 was 2, bump it to 3. This has to be correct since the
11800 register must have been set somewhere. The reason this is
11801 done is because local-alloc.c treats 2 references as a
11804 if (place
== i3
&& i2
!= 0 && GET_CODE (XEXP (note
, 0)) == REG
11805 && REG_N_REFS (REGNO (XEXP (note
, 0)))== 2
11806 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11807 REG_N_REFS (REGNO (XEXP (note
, 0))) = 3;
11811 basic_block bb
= BASIC_BLOCK (this_basic_block
);
11813 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
11815 if (GET_RTX_CLASS (GET_CODE (tem
)) != 'i')
11817 if (tem
== bb
->head
)
11822 /* If the register is being set at TEM, see if that is all
11823 TEM is doing. If so, delete TEM. Otherwise, make this
11824 into a REG_UNUSED note instead. */
11825 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
11827 rtx set
= single_set (tem
);
11828 rtx inner_dest
= 0;
11830 rtx cc0_setter
= NULL_RTX
;
11834 for (inner_dest
= SET_DEST (set
);
11835 GET_CODE (inner_dest
) == STRICT_LOW_PART
11836 || GET_CODE (inner_dest
) == SUBREG
11837 || GET_CODE (inner_dest
) == ZERO_EXTRACT
;
11838 inner_dest
= XEXP (inner_dest
, 0))
11841 /* Verify that it was the set, and not a clobber that
11842 modified the register.
11844 CC0 targets must be careful to maintain setter/user
11845 pairs. If we cannot delete the setter due to side
11846 effects, mark the user with an UNUSED note instead
11849 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
11850 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
11852 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
11853 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
11854 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
11858 /* Move the notes and links of TEM elsewhere.
11859 This might delete other dead insns recursively.
11860 First set the pattern to something that won't use
11863 PATTERN (tem
) = pc_rtx
;
11865 distribute_notes (REG_NOTES (tem
), tem
, tem
,
11866 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11867 distribute_links (LOG_LINKS (tem
));
11869 PUT_CODE (tem
, NOTE
);
11870 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
11871 NOTE_SOURCE_FILE (tem
) = 0;
11874 /* Delete the setter too. */
11877 PATTERN (cc0_setter
) = pc_rtx
;
11879 distribute_notes (REG_NOTES (cc0_setter
),
11880 cc0_setter
, cc0_setter
,
11881 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11882 distribute_links (LOG_LINKS (cc0_setter
));
11884 PUT_CODE (cc0_setter
, NOTE
);
11885 NOTE_LINE_NUMBER (cc0_setter
)
11886 = NOTE_INSN_DELETED
;
11887 NOTE_SOURCE_FILE (cc0_setter
) = 0;
11891 /* If the register is both set and used here, put the
11892 REG_DEAD note here, but place a REG_UNUSED note
11893 here too unless there already is one. */
11894 else if (reg_referenced_p (XEXP (note
, 0),
11899 if (! find_regno_note (tem
, REG_UNUSED
,
11900 REGNO (XEXP (note
, 0))))
11902 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
11907 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
11909 /* If there isn't already a REG_UNUSED note, put one
11911 if (! find_regno_note (tem
, REG_UNUSED
,
11912 REGNO (XEXP (note
, 0))))
11917 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
11918 || (GET_CODE (tem
) == CALL_INSN
11919 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
11923 /* If we are doing a 3->2 combination, and we have a
11924 register which formerly died in i3 and was not used
11925 by i2, which now no longer dies in i3 and is used in
11926 i2 but does not die in i2, and place is between i2
11927 and i3, then we may need to move a link from place to
11929 if (i2
&& INSN_UID (place
) <= max_uid_cuid
11930 && INSN_CUID (place
) > INSN_CUID (i2
)
11931 && from_insn
&& INSN_CUID (from_insn
) > INSN_CUID (i2
)
11932 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11934 rtx links
= LOG_LINKS (place
);
11935 LOG_LINKS (place
) = 0;
11936 distribute_links (links
);
11941 if (tem
== bb
->head
)
11945 /* We haven't found an insn for the death note and it
11946 is still a REG_DEAD note, but we have hit the beginning
11947 of the block. If the existing life info says the reg
11948 was dead, there's nothing left to do. Otherwise, we'll
11949 need to do a global life update after combine. */
11950 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0)
11952 int regno
= REGNO (XEXP (note
, 0));
11953 if (REGNO_REG_SET_P (bb
->global_live_at_start
, regno
))
11955 SET_BIT (refresh_blocks
, this_basic_block
);
11961 /* If the register is set or already dead at PLACE, we needn't do
11962 anything with this note if it is still a REG_DEAD note.
11963 We can here if it is set at all, not if is it totally replace,
11964 which is what `dead_or_set_p' checks, so also check for it being
11967 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
11969 int regno
= REGNO (XEXP (note
, 0));
11971 if (dead_or_set_p (place
, XEXP (note
, 0))
11972 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
11974 /* Unless the register previously died in PLACE, clear
11975 reg_last_death. [I no longer understand why this is
11977 if (reg_last_death
[regno
] != place
)
11978 reg_last_death
[regno
] = 0;
11982 reg_last_death
[regno
] = place
;
11984 /* If this is a death note for a hard reg that is occupying
11985 multiple registers, ensure that we are still using all
11986 parts of the object. If we find a piece of the object
11987 that is unused, we must add a USE for that piece before
11988 PLACE and put the appropriate REG_DEAD note on it.
11990 An alternative would be to put a REG_UNUSED for the pieces
11991 on the insn that set the register, but that can't be done if
11992 it is not in the same block. It is simpler, though less
11993 efficient, to add the USE insns. */
11995 if (place
&& regno
< FIRST_PSEUDO_REGISTER
11996 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
11999 = regno
+ HARD_REGNO_NREGS (regno
,
12000 GET_MODE (XEXP (note
, 0)));
12004 for (i
= regno
; i
< endregno
; i
++)
12005 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12006 && ! find_regno_fusage (place
, USE
, i
))
12008 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12011 /* See if we already placed a USE note for this
12012 register in front of PLACE. */
12014 GET_CODE (PREV_INSN (p
)) == INSN
12015 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
12017 if (rtx_equal_p (piece
,
12018 XEXP (PATTERN (PREV_INSN (p
)), 0)))
12027 = emit_insn_before (gen_rtx_USE (VOIDmode
,
12030 REG_NOTES (use_insn
)
12031 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12032 REG_NOTES (use_insn
));
12038 /* Check for the case where the register dying partially
12039 overlaps the register set by this insn. */
12041 for (i
= regno
; i
< endregno
; i
++)
12042 if (dead_or_set_regno_p (place
, i
))
12050 /* Put only REG_DEAD notes for pieces that are
12051 still used and that are not already dead or set. */
12053 for (i
= regno
; i
< endregno
; i
++)
12055 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12057 if ((reg_referenced_p (piece
, PATTERN (place
))
12058 || (GET_CODE (place
) == CALL_INSN
12059 && find_reg_fusage (place
, USE
, piece
)))
12060 && ! dead_or_set_p (place
, piece
)
12061 && ! reg_bitfield_target_p (piece
,
12064 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12065 REG_NOTES (place
));
12075 /* Any other notes should not be present at this point in the
12082 XEXP (note
, 1) = REG_NOTES (place
);
12083 REG_NOTES (place
) = note
;
12085 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12086 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12087 && GET_CODE (XEXP (note
, 0)) == REG
)
12088 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12092 if ((REG_NOTE_KIND (note
) == REG_DEAD
12093 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12094 && GET_CODE (XEXP (note
, 0)) == REG
)
12095 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12097 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12098 REG_NOTE_KIND (note
),
12100 REG_NOTES (place2
));
12105 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12106 I3, I2, and I1 to new locations. This is also called in one case to
12107 add a link pointing at I3 when I3's destination is changed. */
12110 distribute_links (links
)
12113 rtx link
, next_link
;
12115 for (link
= links
; link
; link
= next_link
)
12121 next_link
= XEXP (link
, 1);
12123 /* If the insn that this link points to is a NOTE or isn't a single
12124 set, ignore it. In the latter case, it isn't clear what we
12125 can do other than ignore the link, since we can't tell which
12126 register it was for. Such links wouldn't be used by combine
12129 It is not possible for the destination of the target of the link to
12130 have been changed by combine. The only potential of this is if we
12131 replace I3, I2, and I1 by I3 and I2. But in that case the
12132 destination of I2 also remains unchanged. */
12134 if (GET_CODE (XEXP (link
, 0)) == NOTE
12135 || (set
= single_set (XEXP (link
, 0))) == 0)
12138 reg
= SET_DEST (set
);
12139 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12140 || GET_CODE (reg
) == SIGN_EXTRACT
12141 || GET_CODE (reg
) == STRICT_LOW_PART
)
12142 reg
= XEXP (reg
, 0);
12144 /* A LOG_LINK is defined as being placed on the first insn that uses
12145 a register and points to the insn that sets the register. Start
12146 searching at the next insn after the target of the link and stop
12147 when we reach a set of the register or the end of the basic block.
12149 Note that this correctly handles the link that used to point from
12150 I3 to I2. Also note that not much searching is typically done here
12151 since most links don't point very far away. */
12153 for (insn
= NEXT_INSN (XEXP (link
, 0));
12154 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12155 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12156 insn
= NEXT_INSN (insn
))
12157 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
12158 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12160 if (reg_referenced_p (reg
, PATTERN (insn
)))
12164 else if (GET_CODE (insn
) == CALL_INSN
12165 && find_reg_fusage (insn
, USE
, reg
))
12171 /* If we found a place to put the link, place it there unless there
12172 is already a link to the same insn as LINK at that point. */
12178 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12179 if (XEXP (link2
, 0) == XEXP (link
, 0))
12184 XEXP (link
, 1) = LOG_LINKS (place
);
12185 LOG_LINKS (place
) = link
;
12187 /* Set added_links_insn to the earliest insn we added a
12189 if (added_links_insn
== 0
12190 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12191 added_links_insn
= place
;
12197 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12203 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12204 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12205 insn
= NEXT_INSN (insn
);
12207 if (INSN_UID (insn
) > max_uid_cuid
)
12210 return INSN_CUID (insn
);
12214 dump_combine_stats (file
)
12219 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12220 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12224 dump_combine_total_stats (file
)
12229 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12230 total_attempts
, total_merges
, total_extras
, total_successes
);