1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
5 // +build ignore_for_gccgo
6 // +build ppc64 ppc64le
11 "runtime/internal/sys"
16 // Go currently requires POWER5 as a minimum for ppc64, so we need
17 // to check for ISA 2.03 and beyond.
18 _PPC_FEATURE_POWER5_PLUS
= 0x00020000 // ISA 2.03 (POWER5+)
19 _PPC_FEATURE_ARCH_2_05
= 0x00001000 // ISA 2.05 (POWER6)
20 _PPC_FEATURE_POWER6_EXT
= 0x00000200 // mffgpr/mftgpr extension (POWER6x)
21 _PPC_FEATURE_ARCH_2_06
= 0x00000100 // ISA 2.06 (POWER7)
22 _PPC_FEATURE2_ARCH_2_07
= 0x80000000 // ISA 2.07 (POWER8)
24 // Standalone capabilities
25 _PPC_FEATURE_HAS_ALTIVEC
= 0x10000000 // SIMD/Vector unit
26 _PPC_FEATURE_HAS_VSX
= 0x00000080 // Vector scalar unit
29 type facilities
struct {
30 _
[sys
.CacheLineSize
]byte
31 isPOWER5x
bool // ISA 2.03
32 isPOWER6
bool // ISA 2.05
33 isPOWER6x
bool // ISA 2.05 + mffgpr/mftgpr extension
34 isPOWER7
bool // ISA 2.06
35 isPOWER8
bool // ISA 2.07
36 hasVMX
bool // Vector unit
37 hasVSX
bool // Vector scalar unit
38 _
[sys
.CacheLineSize
]byte
41 // cpu can be tested at runtime in go assembler code to check for
42 // a certain ISA level or hardware capability, for example:
43 // ·cpu+facilities_hasVSX(SB) for checking the availability of VSX
45 // ·cpu+facilities_isPOWER7(SB) for checking if the processor implements
46 // ISA 2.06 instructions.
49 func archauxv(tag
, val
uintptr) {
52 cpu
.isPOWER5x
= val
&_PPC_FEATURE_POWER5_PLUS
!= 0
53 cpu
.isPOWER6
= val
&_PPC_FEATURE_ARCH_2_05
!= 0
54 cpu
.isPOWER6x
= val
&_PPC_FEATURE_POWER6_EXT
!= 0
55 cpu
.isPOWER7
= val
&_PPC_FEATURE_ARCH_2_06
!= 0
56 cpu
.hasVMX
= val
&_PPC_FEATURE_HAS_ALTIVEC
!= 0
57 cpu
.hasVSX
= val
&_PPC_FEATURE_HAS_VSX
!= 0
59 cpu
.isPOWER8
= val
&_PPC_FEATURE2_ARCH_2_07
!= 0