gcc/config/rs6000/rs6000.c

   1 /* Subroutines used for code generation on IBM RS/6000.
   2    Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   4    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  21    MA 02111-1307, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "rtl.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "insn-attr.h"
  34 #include "flags.h"
  35 #include "recog.h"
  36 #include "obstack.h"
  37 #include "tree.h"
  38 #include "expr.h"
  39 #include "optabs.h"
  40 #include "except.h"
  41 #include "function.h"
  42 #include "output.h"
  43 #include "basic-block.h"
  44 #include "integrate.h"
  45 #include "toplev.h"
  46 #include "ggc.h"
  47 #include "hashtab.h"
  48 #include "tm_p.h"
  49 #include "target.h"
  50 #include "target-def.h"
  51 #include "langhooks.h"
  52 #include "reload.h"
  53 #include "cfglayout.h"
  54 #include "sched-int.h"
  55 #if TARGET_XCOFF
  56 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
  57 #endif
  58
  59 #ifndef TARGET_NO_PROTOTYPE
  60 #define TARGET_NO_PROTOTYPE 0
  61 #endif
  62
  63 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
  64 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \
  65                                           && !((n) & 1))
  66
  67 #define min(A,B)        ((A) < (B) ? (A) : (B))
  68 #define max(A,B)        ((A) > (B) ? (A) : (B))
  69
  70 /* Structure used to define the rs6000 stack */
  71 typedef struct rs6000_stack {
  72   int first_gp_reg_save;        /* first callee saved GP register used */
  73   int first_fp_reg_save;        /* first callee saved FP register used */
  74   int first_altivec_reg_save;   /* first callee saved AltiVec register used */
  75   int lr_save_p;                /* true if the link reg needs to be saved */
  76   int cr_save_p;                /* true if the CR reg needs to be saved */
  77   unsigned int vrsave_mask;     /* mask of vec registers to save */
  78   int toc_save_p;               /* true if the TOC needs to be saved */
  79   int push_p;                   /* true if we need to allocate stack space */
  80   int calls_p;                  /* true if the function makes any calls */
  81   enum rs6000_abi abi;          /* which ABI to use */
  82   int gp_save_offset;           /* offset to save GP regs from initial SP */
  83   int fp_save_offset;           /* offset to save FP regs from initial SP */
  84   int altivec_save_offset;      /* offset to save AltiVec regs from initial SP */
  85   int lr_save_offset;           /* offset to save LR from initial SP */
  86   int cr_save_offset;           /* offset to save CR from initial SP */
  87   int vrsave_save_offset;       /* offset to save VRSAVE from initial SP */
  88   int spe_gp_save_offset;       /* offset to save spe 64-bit gprs  */
  89   int toc_save_offset;          /* offset to save the TOC pointer */
  90   int varargs_save_offset;      /* offset to save the varargs registers */
  91   int ehrd_offset;              /* offset to EH return data */
  92   int reg_size;                 /* register size (4 or 8) */
  93   int varargs_size;             /* size to hold V.4 args passed in regs */
  94   HOST_WIDE_INT vars_size;      /* variable save area size */
  95   int parm_size;                /* outgoing parameter size */
  96   int save_size;                /* save area size */
  97   int fixed_size;               /* fixed size of stack frame */
  98   int gp_size;                  /* size of saved GP registers */
  99   int fp_size;                  /* size of saved FP registers */
 100   int altivec_size;             /* size of saved AltiVec registers */
 101   int cr_size;                  /* size to hold CR if not in save_size */
 102   int lr_size;                  /* size to hold LR if not in save_size */
 103   int vrsave_size;              /* size to hold VRSAVE if not in save_size */
 104   int altivec_padding_size;     /* size of altivec alignment padding if
 105                                    not in save_size */
 106   int spe_gp_size;              /* size of 64-bit GPR save size for SPE */
 107   int spe_padding_size;
 108   int toc_size;                 /* size to hold TOC if not in save_size */
 109   HOST_WIDE_INT total_size;     /* total bytes allocated for stack */
 110   int spe_64bit_regs_used;
 111 } rs6000_stack_t;
 112
 113 /* Target cpu type */
 114
 115 enum processor_type rs6000_cpu;
 116 struct rs6000_cpu_select rs6000_select[3] =
 117 {
 118   /* switch             name,                   tune    arch */
 119   { (const char *)0,    "--with-cpu=",          1,      1 },
 120   { (const char *)0,    "-mcpu=",               1,      1 },
 121   { (const char *)0,    "-mtune=",              1,      0 },
 122 };
 123
 124 /* Always emit branch hint bits.  */
 125 static GTY(()) bool rs6000_always_hint;
 126
 127 /* Schedule instructions for group formation.  */
 128 static GTY(()) bool rs6000_sched_groups;
 129
 130 /* Support adjust_priority scheduler hook
 131    and -mprioritize-restricted-insns= option.  */
 132 const char *rs6000_sched_restricted_insns_priority_str;
 133 int rs6000_sched_restricted_insns_priority;
 134
 135 /* Support for -msched-costly-dep option.  */
 136 const char *rs6000_sched_costly_dep_str;
 137 enum rs6000_dependence_cost rs6000_sched_costly_dep;
 138
 139 /* Support for -minsert-sched-nops option.  */
 140 const char *rs6000_sched_insert_nops_str;
 141 enum rs6000_nop_insertion rs6000_sched_insert_nops;
 142
 143 /* Size of long double */
 144 const char *rs6000_long_double_size_string;
 145 int rs6000_long_double_type_size;
 146
 147 /* Whether -mabi=altivec has appeared */
 148 int rs6000_altivec_abi;
 149
 150 /* Whether VRSAVE instructions should be generated.  */
 151 int rs6000_altivec_vrsave;
 152
 153 /* String from -mvrsave= option.  */
 154 const char *rs6000_altivec_vrsave_string;
 155
 156 /* Nonzero if we want SPE ABI extensions.  */
 157 int rs6000_spe_abi;
 158
 159 /* Whether isel instructions should be generated.  */
 160 int rs6000_isel;
 161
 162 /* Whether SPE simd instructions should be generated.  */
 163 int rs6000_spe;
 164
 165 /* Nonzero if floating point operations are done in the GPRs.  */
 166 int rs6000_float_gprs = 0;
 167
 168 /* String from -mfloat-gprs=.  */
 169 const char *rs6000_float_gprs_string;
 170
 171 /* String from -misel=.  */
 172 const char *rs6000_isel_string;
 173
 174 /* String from -mspe=.  */
 175 const char *rs6000_spe_string;
 176
 177 /* Set to nonzero once AIX common-mode calls have been defined.  */
 178 static GTY(()) int common_mode_defined;
 179
 180 /* Save information from a "cmpxx" operation until the branch or scc is
 181    emitted.  */
 182 rtx rs6000_compare_op0, rs6000_compare_op1;
 183 int rs6000_compare_fp_p;
 184
 185 /* Label number of label created for -mrelocatable, to call to so we can
 186    get the address of the GOT section */
 187 int rs6000_pic_labelno;
 188
 189 #ifdef USING_ELFOS_H
 190 /* Which abi to adhere to */
 191 const char *rs6000_abi_name;
 192
 193 /* Semantics of the small data area */
 194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
 195
 196 /* Which small data model to use */
 197 const char *rs6000_sdata_name = (char *)0;
 198
 199 /* Counter for labels which are to be placed in .fixup.  */
 200 int fixuplabelno = 0;
 201 #endif
 202
 203 /* Bit size of immediate TLS offsets and string from which it is decoded.  */
 204 int rs6000_tls_size = 32;
 205 const char *rs6000_tls_size_string;
 206
 207 /* ABI enumeration available for subtarget to use.  */
 208 enum rs6000_abi rs6000_current_abi;
 209
 210 /* ABI string from -mabi= option.  */
 211 const char *rs6000_abi_string;
 212
 213 /* Debug flags */
 214 const char *rs6000_debug_name;
 215 int rs6000_debug_stack;         /* debug stack applications */
 216 int rs6000_debug_arg;           /* debug argument handling */
 217
 218 /* Opaque types.  */
 219 static GTY(()) tree opaque_V2SI_type_node;
 220 static GTY(()) tree opaque_V2SF_type_node;
 221 static GTY(()) tree opaque_p_V2SI_type_node;
 222 static GTY(()) tree V16QI_type_node;
 223 static GTY(()) tree V2SI_type_node;
 224 static GTY(()) tree V2SF_type_node;
 225 static GTY(()) tree V4HI_type_node;
 226 static GTY(()) tree V4SI_type_node;
 227 static GTY(()) tree V4SF_type_node;
 228 static GTY(()) tree V8HI_type_node;
 229 static GTY(()) tree unsigned_V16QI_type_node;
 230 static GTY(()) tree unsigned_V8HI_type_node;
 231 static GTY(()) tree unsigned_V4SI_type_node;
 232 static GTY(()) tree bool_char_type_node;        /* __bool char */
 233 static GTY(()) tree bool_short_type_node;       /* __bool short */
 234 static GTY(()) tree bool_int_type_node;         /* __bool int */
 235 static GTY(()) tree pixel_type_node;            /* __pixel */
 236 static GTY(()) tree bool_V16QI_type_node;       /* __vector __bool char */
 237 static GTY(()) tree bool_V8HI_type_node;        /* __vector __bool short */
 238 static GTY(()) tree bool_V4SI_type_node;        /* __vector __bool int */
 239 static GTY(()) tree pixel_V8HI_type_node;       /* __vector __pixel */
 240
 241 int rs6000_warn_altivec_long = 1;               /* On by default. */
 242 const char *rs6000_warn_altivec_long_switch;
 243
 244 const char *rs6000_traceback_name;
 245 static enum {
 246   traceback_default = 0,
 247   traceback_none,
 248   traceback_part,
 249   traceback_full
 250 } rs6000_traceback;
 251
 252 /* Flag to say the TOC is initialized */
 253 int toc_initialized;
 254 char toc_label_name[10];
 255
 256 /* Alias set for saves and restores from the rs6000 stack.  */
 257 static GTY(()) int rs6000_sr_alias_set;
 258
 259 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
 260    The only place that looks at this is rs6000_set_default_type_attributes;
 261    everywhere else should rely on the presence or absence of a longcall
 262    attribute on the function declaration.  */
 263 int rs6000_default_long_calls;
 264 const char *rs6000_longcall_switch;
 265
 266 /* Control alignment for fields within structures.  */
 267 /* String from -malign-XXXXX.  */
 268 const char *rs6000_alignment_string;
 269 int rs6000_alignment_flags;
 270
 271 struct builtin_description
 272 {
 273   /* mask is not const because we're going to alter it below.  This
 274      nonsense will go away when we rewrite the -march infrastructure
 275      to give us more target flag bits.  */
 276   unsigned int mask;
 277   const enum insn_code icode;
 278   const char *const name;
 279   const enum rs6000_builtins code;
 280 };
 281
 282 static bool rs6000_function_ok_for_sibcall (tree, tree);
 283 static int num_insns_constant_wide (HOST_WIDE_INT);
 284 static void validate_condition_mode (enum rtx_code, enum machine_mode);
 285 static rtx rs6000_generate_compare (enum rtx_code);
 286 static void rs6000_maybe_dead (rtx);
 287 static void rs6000_emit_stack_tie (void);
 288 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
 289 static rtx spe_synthesize_frame_save (rtx);
 290 static bool spe_func_has_64bit_regs_p (void);
 291 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
 292                              int, HOST_WIDE_INT);
 293 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
 294 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
 295 static unsigned rs6000_hash_constant (rtx);
 296 static unsigned toc_hash_function (const void *);
 297 static int toc_hash_eq (const void *, const void *);
 298 static int constant_pool_expr_1 (rtx, int *, int *);
 299 static bool constant_pool_expr_p (rtx);
 300 static bool toc_relative_expr_p (rtx);
 301 static bool legitimate_small_data_p (enum machine_mode, rtx);
 302 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
 303 static bool legitimate_indexed_address_p (rtx, int);
 304 static bool legitimate_indirect_address_p (rtx, int);
 305 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
 306 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
 307 static struct machine_function * rs6000_init_machine_status (void);
 308 static bool rs6000_assemble_integer (rtx, unsigned int, int);
 309 #ifdef HAVE_GAS_HIDDEN
 310 static void rs6000_assemble_visibility (tree, int);
 311 #endif
 312 static int rs6000_ra_ever_killed (void);
 313 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
 314 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
 315 static const char *rs6000_mangle_fundamental_type (tree);
 316 extern const struct attribute_spec rs6000_attribute_table[];
 317 static void rs6000_set_default_type_attributes (tree);
 318 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
 319 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
 320 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
 321                                     tree);
 322 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 323 static bool rs6000_return_in_memory (tree, tree);
 324 static void rs6000_file_start (void);
 325 #if TARGET_ELF
 326 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
 327 static void rs6000_elf_asm_out_constructor (rtx, int);
 328 static void rs6000_elf_asm_out_destructor (rtx, int);
 329 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
 330 static void rs6000_elf_unique_section (tree, int);
 331 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
 332                                            unsigned HOST_WIDE_INT);
 333 static void rs6000_elf_encode_section_info (tree, rtx, int)
 334      ATTRIBUTE_UNUSED;
 335 static bool rs6000_elf_in_small_data_p (tree);
 336 #endif
 337 #if TARGET_XCOFF
 338 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
 339 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
 340 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
 341 static void rs6000_xcoff_unique_section (tree, int);
 342 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
 343                                              unsigned HOST_WIDE_INT);
 344 static const char * rs6000_xcoff_strip_name_encoding (const char *);
 345 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
 346 static void rs6000_xcoff_file_start (void);
 347 static void rs6000_xcoff_file_end (void);
 348 #endif
 349 #if TARGET_MACHO
 350 static bool rs6000_binds_local_p (tree);
 351 #endif
 352 static int rs6000_use_dfa_pipeline_interface (void);
 353 static int rs6000_variable_issue (FILE *, int, rtx, int);
 354 static bool rs6000_rtx_costs (rtx, int, int, int *);
 355 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
 356 static bool is_microcoded_insn (rtx);
 357 static int is_dispatch_slot_restricted (rtx);
 358 static bool is_cracked_insn (rtx);
 359 static bool is_branch_slot_insn (rtx);
 360 static int rs6000_adjust_priority (rtx, int);
 361 static int rs6000_issue_rate (void);
 362 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
 363 static rtx get_next_active_insn (rtx, rtx);
 364 static bool insn_terminates_group_p (rtx , enum group_termination);
 365 static bool is_costly_group (rtx *, rtx);
 366 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
 367 static int redefine_groups (FILE *, int, rtx, rtx);
 368 static int pad_groups (FILE *, int, rtx, rtx);
 369 static void rs6000_sched_finish (FILE *, int);
 370 static int rs6000_use_sched_lookahead (void);
 371
 372 static void rs6000_init_builtins (void);
 373 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
 374 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
 375 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
 376 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
 377 static void altivec_init_builtins (void);
 378 static void rs6000_common_init_builtins (void);
 379 static void rs6000_init_libfuncs (void);
 380
 381 static void enable_mask_for_builtins (struct builtin_description *, int,
 382                                       enum rs6000_builtins,
 383                                       enum rs6000_builtins);
 384 static tree build_opaque_vector_type (tree, int);
 385 static void spe_init_builtins (void);
 386 static rtx spe_expand_builtin (tree, rtx, bool *);
 387 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
 388 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
 389 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
 390 static rs6000_stack_t *rs6000_stack_info (void);
 391 static void debug_stack_info (rs6000_stack_t *);
 392
 393 static rtx altivec_expand_builtin (tree, rtx, bool *);
 394 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
 395 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
 396 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
 397 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
 398 static rtx altivec_expand_predicate_builtin (enum insn_code,
 399                                             const char *, tree, rtx);
 400 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
 401 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
 402 static void rs6000_parse_abi_options (void);
 403 static void rs6000_parse_alignment_option (void);
 404 static void rs6000_parse_tls_size_option (void);
 405 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
 406 static int first_altivec_reg_to_save (void);
 407 static unsigned int compute_vrsave_mask (void);
 408 static void is_altivec_return_reg (rtx, void *);
 409 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
 410 int easy_vector_constant (rtx, enum machine_mode);
 411 static int easy_vector_same (rtx, enum machine_mode);
 412 static int easy_vector_splat_const (int, enum machine_mode);
 413 static bool is_ev64_opaque_type (tree);
 414 static rtx rs6000_dwarf_register_span (rtx);
 415 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
 416 static rtx rs6000_tls_get_addr (void);
 417 static rtx rs6000_got_sym (void);
 418 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
 419 static const char *rs6000_get_some_local_dynamic_name (void);
 420 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
 421 static rtx rs6000_complex_function_value (enum machine_mode);
 422 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
 423                                     enum machine_mode, tree);
 424 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
 425                                       enum machine_mode, tree, int);
 426 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
 427 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
 428                                     enum machine_mode, tree,
 429                                     int *, int);
 430 #if TARGET_MACHO
 431 static void macho_branch_islands (void);
 432 static void add_compiler_branch_island (tree, tree, int);
 433 static int no_previous_def (tree function_name);
 434 static tree get_prev_label (tree function_name);
 435 #endif
 436
 437 static tree rs6000_build_builtin_va_list (void);
 438
 439 /* Hash table stuff for keeping track of TOC entries.  */
 440
 441 struct toc_hash_struct GTY(())
 442 {
 443   /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
 444      ASM_OUTPUT_SPECIAL_POOL_ENTRY_P.  */
 445   rtx key;
 446   enum machine_mode key_mode;
 447   int labelno;
 448 };
 449
 450 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
 451 \f
 452 /* Default register names.  */
 453 char rs6000_reg_names[][8] =
 454 {
 455       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 456       "8",  "9", "10", "11", "12", "13", "14", "15",
 457      "16", "17", "18", "19", "20", "21", "22", "23",
 458      "24", "25", "26", "27", "28", "29", "30", "31",
 459       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 460       "8",  "9", "10", "11", "12", "13", "14", "15",
 461      "16", "17", "18", "19", "20", "21", "22", "23",
 462      "24", "25", "26", "27", "28", "29", "30", "31",
 463      "mq", "lr", "ctr","ap",
 464       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 465       "xer",
 466       /* AltiVec registers.  */
 467       "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
 468       "8",  "9",  "10", "11", "12", "13", "14", "15",
 469       "16", "17", "18", "19", "20", "21", "22", "23",
 470       "24", "25", "26", "27", "28", "29", "30", "31",
 471       "vrsave", "vscr",
 472       /* SPE registers.  */
 473       "spe_acc", "spefscr"
 474 };
 475
 476 #ifdef TARGET_REGNAMES
 477 static const char alt_reg_names[][8] =
 478 {
 479    "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
 480    "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
 481   "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
 482   "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
 483    "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
 484    "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
 485   "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
 486   "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
 487     "mq",    "lr",  "ctr",   "ap",
 488   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
 489    "xer",
 490   /* AltiVec registers.  */
 491    "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
 492    "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
 493   "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
 494   "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
 495   "vrsave", "vscr",
 496   /* SPE registers.  */
 497   "spe_acc", "spefscr"
 498 };
 499 #endif
 500 \f
 501 #ifndef MASK_STRICT_ALIGN
 502 #define MASK_STRICT_ALIGN 0
 503 #endif
 504 #ifndef TARGET_PROFILE_KERNEL
 505 #define TARGET_PROFILE_KERNEL 0
 506 #endif
 507
 508 /* The VRSAVE bitmask puts bit %v0 as the most significant bit.  */
 509 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
 510
 511 /* Return 1 for a symbol ref for a thread-local storage symbol.  */
 512 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
 513   (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
 514 \f
 515 /* Initialize the GCC target structure.  */
 516 #undef TARGET_ATTRIBUTE_TABLE
 517 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
 518 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
 519 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
 520
 521 #undef TARGET_ASM_ALIGNED_DI_OP
 522 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
 523
 524 /* Default unaligned ops are only provided for ELF.  Find the ops needed
 525    for non-ELF systems.  */
 526 #ifndef OBJECT_FORMAT_ELF
 527 #if TARGET_XCOFF
 528 /* For XCOFF.  rs6000_assemble_integer will handle unaligned DIs on
 529    64-bit targets.  */
 530 #undef TARGET_ASM_UNALIGNED_HI_OP
 531 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
 532 #undef TARGET_ASM_UNALIGNED_SI_OP
 533 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
 534 #undef TARGET_ASM_UNALIGNED_DI_OP
 535 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
 536 #else
 537 /* For Darwin.  */
 538 #undef TARGET_ASM_UNALIGNED_HI_OP
 539 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
 540 #undef TARGET_ASM_UNALIGNED_SI_OP
 541 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
 542 #endif
 543 #endif
 544
 545 /* This hook deals with fixups for relocatable code and DI-mode objects
 546    in 64-bit code.  */
 547 #undef TARGET_ASM_INTEGER
 548 #define TARGET_ASM_INTEGER rs6000_assemble_integer
 549
 550 #ifdef HAVE_GAS_HIDDEN
 551 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
 552 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
 553 #endif
 554
 555 #undef TARGET_HAVE_TLS
 556 #define TARGET_HAVE_TLS HAVE_AS_TLS
 557
 558 #undef TARGET_CANNOT_FORCE_CONST_MEM
 559 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
 560
 561 #undef TARGET_ASM_FUNCTION_PROLOGUE
 562 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
 563 #undef TARGET_ASM_FUNCTION_EPILOGUE
 564 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
 565
 566 #undef  TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
 567 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
 568 #undef  TARGET_SCHED_VARIABLE_ISSUE
 569 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
 570
 571 #undef TARGET_SCHED_ISSUE_RATE
 572 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
 573 #undef TARGET_SCHED_ADJUST_COST
 574 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
 575 #undef TARGET_SCHED_ADJUST_PRIORITY
 576 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
 577 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
 578 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
 579 #undef TARGET_SCHED_FINISH
 580 #define TARGET_SCHED_FINISH rs6000_sched_finish
 581
 582 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
 583 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
 584
 585 #undef TARGET_INIT_BUILTINS
 586 #define TARGET_INIT_BUILTINS rs6000_init_builtins
 587
 588 #undef TARGET_EXPAND_BUILTIN
 589 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
 590
 591 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
 592 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
 593
 594 #undef TARGET_INIT_LIBFUNCS
 595 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
 596
 597 #if TARGET_MACHO
 598 #undef TARGET_BINDS_LOCAL_P
 599 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
 600 #endif
 601
 602 #undef TARGET_ASM_OUTPUT_MI_THUNK
 603 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
 604
 605 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
 606 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
 607
 608 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 609 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
 610
 611 #undef TARGET_RTX_COSTS
 612 #define TARGET_RTX_COSTS rs6000_rtx_costs
 613 #undef TARGET_ADDRESS_COST
 614 #define TARGET_ADDRESS_COST hook_int_rtx_0
 615
 616 #undef TARGET_VECTOR_OPAQUE_P
 617 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
 618
 619 #undef TARGET_DWARF_REGISTER_SPAN
 620 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
 621
 622 /* On rs6000, function arguments are promoted, as are function return
 623    values.  */
 624 #undef TARGET_PROMOTE_FUNCTION_ARGS
 625 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
 626 #undef TARGET_PROMOTE_FUNCTION_RETURN
 627 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
 628
 629 #undef TARGET_RETURN_IN_MEMORY
 630 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
 631
 632 #undef TARGET_SETUP_INCOMING_VARARGS
 633 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
 634
 635 /* Always strict argument naming on rs6000.  */
 636 #undef TARGET_STRICT_ARGUMENT_NAMING
 637 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
 638 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
 639 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
 640 #undef TARGET_SPLIT_COMPLEX_ARG
 641 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
 642
 643 #undef TARGET_BUILD_BUILTIN_VA_LIST
 644 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
 645
 646 struct gcc_target targetm = TARGET_INITIALIZER;
 647 \f
 648 /* Override command line options.  Mostly we process the processor
 649    type and sometimes adjust other TARGET_ options.  */
 650
 651 void
 652 rs6000_override_options (const char *default_cpu)
 653 {
 654   size_t i, j;
 655   struct rs6000_cpu_select *ptr;
 656   int set_masks;
 657
 658   /* Simplifications for entries below.  */
 659
 660   enum {
 661     POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
 662     POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
 663   };
 664
 665   /* This table occasionally claims that a processor does not support
 666      a particular feature even though it does, but the feature is slower
 667      than the alternative.  Thus, it shouldn't be relied on as a
 668      complete description of the processor's support.
 669
 670      Please keep this list in order, and don't forget to update the
 671      documentation in invoke.texi when adding a new processor or
 672      flag.  */
 673   static struct ptt
 674     {
 675       const char *const name;           /* Canonical processor name.  */
 676       const enum processor_type processor; /* Processor type enum value.  */
 677       const int target_enable;  /* Target flags to enable.  */
 678     } const processor_target_table[]
 679       = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 680          {"403", PROCESSOR_PPC403,
 681           POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
 682          {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 683          {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
 684          {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 685          {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
 686          {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
 687          {"601", PROCESSOR_PPC601,
 688           MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
 689          {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 690          {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 691          {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 692          {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 693          {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 694          {"620", PROCESSOR_PPC620,
 695           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 696          {"630", PROCESSOR_PPC630,
 697           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 698          {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 699          {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
 700          {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
 701          {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 702          {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 703          {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 704          {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 705          {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 706          {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 707          {"970", PROCESSOR_POWER4,
 708           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 709          {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
 710          {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 711          {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 712          {"G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK},
 713          {"G5", PROCESSOR_POWER4,
 714           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 715          {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 716          {"power2", PROCESSOR_POWER,
 717           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 718          {"power3", PROCESSOR_PPC630,
 719           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 720          {"power4", PROCESSOR_POWER4,
 721           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
 722          {"power5", PROCESSOR_POWER5,
 723           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
 724          {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
 725          {"powerpc64", PROCESSOR_POWERPC64,
 726           POWERPC_BASE_MASK | MASK_POWERPC64},
 727          {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 728          {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 729          {"rios2", PROCESSOR_RIOS2,
 730           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 731          {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 732          {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 733          {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
 734       };
 735
 736   const size_t ptt_size = ARRAY_SIZE (processor_target_table);
 737
 738   /* Some OSs don't support saving the high part of 64-bit registers on
 739      context switch.  Other OSs don't support saving Altivec registers.
 740      On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
 741      settings; if the user wants either, the user must explicitly specify
 742      them and we won't interfere with the user's specification.  */
 743
 744   enum {
 745     POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
 746     POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
 747                      | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
 748                      | MASK_MFCRF)
 749   };
 750  set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
 751 #ifdef OS_MISSING_POWERPC64
 752   if (OS_MISSING_POWERPC64)
 753     set_masks &= ~MASK_POWERPC64;
 754 #endif
 755 #ifdef OS_MISSING_ALTIVEC
 756   if (OS_MISSING_ALTIVEC)
 757     set_masks &= ~MASK_ALTIVEC;
 758 #endif
 759
 760   /* Don't override these by the processor default if given explicitly.  */
 761   set_masks &= ~(target_flags_explicit
 762                  & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
 763
 764   /* Identify the processor type.  */
 765   rs6000_select[0].string = default_cpu;
 766   rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
 767
 768   for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
 769     {
 770       ptr = &rs6000_select[i];
 771       if (ptr->string != (char *)0 && ptr->string[0] != '\0')
 772         {
 773           for (j = 0; j < ptt_size; j++)
 774             if (! strcmp (ptr->string, processor_target_table[j].name))
 775               {
 776                 if (ptr->set_tune_p)
 777                   rs6000_cpu = processor_target_table[j].processor;
 778
 779                 if (ptr->set_arch_p)
 780                   {
 781                     target_flags &= ~set_masks;
 782                     target_flags |= (processor_target_table[j].target_enable
 783                                      & set_masks);
 784                   }
 785                 break;
 786               }
 787
 788           if (j == ptt_size)
 789             error ("bad value (%s) for %s switch", ptr->string, ptr->name);
 790         }
 791     }
 792
 793   if (TARGET_E500)
 794     rs6000_isel = 1;
 795
 796   /* If we are optimizing big endian systems for space, use the load/store
 797      multiple and string instructions.  */
 798   if (BYTES_BIG_ENDIAN && optimize_size)
 799     target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
 800
 801   /* Don't allow -mmultiple or -mstring on little endian systems
 802      unless the cpu is a 750, because the hardware doesn't support the
 803      instructions used in little endian mode, and causes an alignment
 804      trap.  The 750 does not cause an alignment trap (except when the
 805      target is unaligned).  */
 806
 807   if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
 808     {
 809       if (TARGET_MULTIPLE)
 810         {
 811           target_flags &= ~MASK_MULTIPLE;
 812           if ((target_flags_explicit & MASK_MULTIPLE) != 0)
 813             warning ("-mmultiple is not supported on little endian systems");
 814         }
 815
 816       if (TARGET_STRING)
 817         {
 818           target_flags &= ~MASK_STRING;
 819           if ((target_flags_explicit & MASK_STRING) != 0)
 820             warning ("-mstring is not supported on little endian systems");
 821         }
 822     }
 823
 824   /* Set debug flags */
 825   if (rs6000_debug_name)
 826     {
 827       if (! strcmp (rs6000_debug_name, "all"))
 828         rs6000_debug_stack = rs6000_debug_arg = 1;
 829       else if (! strcmp (rs6000_debug_name, "stack"))
 830         rs6000_debug_stack = 1;
 831       else if (! strcmp (rs6000_debug_name, "arg"))
 832         rs6000_debug_arg = 1;
 833       else
 834         error ("unknown -mdebug-%s switch", rs6000_debug_name);
 835     }
 836
 837   if (rs6000_traceback_name)
 838     {
 839       if (! strncmp (rs6000_traceback_name, "full", 4))
 840         rs6000_traceback = traceback_full;
 841       else if (! strncmp (rs6000_traceback_name, "part", 4))
 842         rs6000_traceback = traceback_part;
 843       else if (! strncmp (rs6000_traceback_name, "no", 2))
 844         rs6000_traceback = traceback_none;
 845       else
 846         error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
 847                rs6000_traceback_name);
 848     }
 849
 850   /* Set size of long double */
 851   rs6000_long_double_type_size = 64;
 852   if (rs6000_long_double_size_string)
 853     {
 854       char *tail;
 855       int size = strtol (rs6000_long_double_size_string, &tail, 10);
 856       if (*tail != '\0' || (size != 64 && size != 128))
 857         error ("Unknown switch -mlong-double-%s",
 858                rs6000_long_double_size_string);
 859       else
 860         rs6000_long_double_type_size = size;
 861     }
 862
 863   /* Set Altivec ABI as default for powerpc64 linux.  */
 864   if (TARGET_ELF && TARGET_64BIT)
 865     {
 866       rs6000_altivec_abi = 1;
 867       rs6000_altivec_vrsave = 1;
 868     }
 869
 870   /* Handle -mabi= options.  */
 871   rs6000_parse_abi_options ();
 872
 873   /* Handle -malign-XXXXX option.  */
 874   rs6000_parse_alignment_option ();
 875
 876   /* Handle generic -mFOO=YES/NO options.  */
 877   rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
 878                               &rs6000_altivec_vrsave);
 879   rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
 880                               &rs6000_isel);
 881   rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
 882   rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
 883                               &rs6000_float_gprs);
 884
 885   /* Handle -mtls-size option.  */
 886   rs6000_parse_tls_size_option ();
 887
 888 #ifdef SUBTARGET_OVERRIDE_OPTIONS
 889   SUBTARGET_OVERRIDE_OPTIONS;
 890 #endif
 891 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
 892   SUBSUBTARGET_OVERRIDE_OPTIONS;
 893 #endif
 894
 895   if (TARGET_E500)
 896     {
 897       if (TARGET_ALTIVEC)
 898         error ("AltiVec and E500 instructions cannot coexist");
 899
 900       /* The e500 does not have string instructions, and we set
 901          MASK_STRING above when optimizing for size.  */
 902       if ((target_flags & MASK_STRING) != 0)
 903         target_flags = target_flags & ~MASK_STRING;
 904
 905       /* No SPE means 64-bit long doubles, even if an E500.  */
 906       if (rs6000_spe_string != 0
 907           && !strcmp (rs6000_spe_string, "no"))
 908         rs6000_long_double_type_size = 64;
 909     }
 910   else if (rs6000_select[1].string != NULL)
 911     {
 912       /* For the powerpc-eabispe configuration, we set all these by
 913          default, so let's unset them if we manually set another
 914          CPU that is not the E500.  */
 915       if (rs6000_abi_string == 0)
 916         rs6000_spe_abi = 0;
 917       if (rs6000_spe_string == 0)
 918         rs6000_spe = 0;
 919       if (rs6000_float_gprs_string == 0)
 920         rs6000_float_gprs = 0;
 921       if (rs6000_isel_string == 0)
 922         rs6000_isel = 0;
 923       if (rs6000_long_double_size_string == 0)
 924         rs6000_long_double_type_size = 64;
 925     }
 926
 927   rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
 928                         && rs6000_cpu != PROCESSOR_POWER5);
 929   rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
 930                          || rs6000_cpu == PROCESSOR_POWER5);
 931
 932   /* Handle -m(no-)longcall option.  This is a bit of a cheap hack,
 933      using TARGET_OPTIONS to handle a toggle switch, but we're out of
 934      bits in target_flags so TARGET_SWITCHES cannot be used.
 935      Assumption here is that rs6000_longcall_switch points into the
 936      text of the complete option, rather than being a copy, so we can
 937      scan back for the presence or absence of the no- modifier.  */
 938   if (rs6000_longcall_switch)
 939     {
 940       const char *base = rs6000_longcall_switch;
 941       while (base[-1] != 'm') base--;
 942
 943       if (*rs6000_longcall_switch != '\0')
 944         error ("invalid option `%s'", base);
 945       rs6000_default_long_calls = (base[0] != 'n');
 946     }
 947
 948   /* Handle -m(no-)warn-altivec-long similarly.  */
 949   if (rs6000_warn_altivec_long_switch)
 950     {
 951       const char *base = rs6000_warn_altivec_long_switch;
 952       while (base[-1] != 'm') base--;
 953
 954       if (*rs6000_warn_altivec_long_switch != '\0')
 955         error ("invalid option `%s'", base);
 956       rs6000_warn_altivec_long = (base[0] != 'n');
 957     }
 958
 959   /* Handle -mprioritize-restricted-insns option.  */
 960   rs6000_sched_restricted_insns_priority
 961     = (rs6000_sched_groups ? 1 : 0);
 962   if (rs6000_sched_restricted_insns_priority_str)
 963     rs6000_sched_restricted_insns_priority =
 964       atoi (rs6000_sched_restricted_insns_priority_str);
 965
 966   /* Handle -msched-costly-dep option.  */
 967   rs6000_sched_costly_dep
 968     = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
 969   if (rs6000_sched_costly_dep_str)
 970     {
 971       if (! strcmp (rs6000_sched_costly_dep_str, "no"))
 972         rs6000_sched_costly_dep = no_dep_costly;
 973       else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
 974         rs6000_sched_costly_dep = all_deps_costly;
 975       else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
 976         rs6000_sched_costly_dep = true_store_to_load_dep_costly;
 977       else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
 978         rs6000_sched_costly_dep = store_to_load_dep_costly;
 979       else
 980         rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
 981     }
 982
 983   /* Handle -minsert-sched-nops option.  */
 984   rs6000_sched_insert_nops
 985     = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
 986   if (rs6000_sched_insert_nops_str)
 987     {
 988       if (! strcmp (rs6000_sched_insert_nops_str, "no"))
 989         rs6000_sched_insert_nops = sched_finish_none;
 990       else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
 991         rs6000_sched_insert_nops = sched_finish_pad_groups;
 992       else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
 993         rs6000_sched_insert_nops = sched_finish_regroup_exact;
 994       else
 995         rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
 996     }
 997
 998 #ifdef TARGET_REGNAMES
 999   /* If the user desires alternate register names, copy in the
1000      alternate names now.  */
1001   if (TARGET_REGNAMES)
1002     memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1003 #endif
1004
1005   /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1006      If -maix-struct-return or -msvr4-struct-return was explicitly
1007      used, don't override with the ABI default.  */
1008   if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1009     {
1010       if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1011         target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1012       else
1013         target_flags |= MASK_AIX_STRUCT_RET;
1014     }
1015
1016   if (TARGET_LONG_DOUBLE_128
1017       && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1018     REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1019
1020   /* Allocate an alias set for register saves & restores from stack.  */
1021   rs6000_sr_alias_set = new_alias_set ();
1022
1023   if (TARGET_TOC)
1024     ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1025
1026   /* We can only guarantee the availability of DI pseudo-ops when
1027      assembling for 64-bit targets.  */
1028   if (!TARGET_64BIT)
1029     {
1030       targetm.asm_out.aligned_op.di = NULL;
1031       targetm.asm_out.unaligned_op.di = NULL;
1032     }
1033
1034   /* Set maximum branch target alignment at two instructions, eight bytes.  */
1035   align_jumps_max_skip = 8;
1036   align_loops_max_skip = 8;
1037
1038   /* Arrange to save and restore machine status around nested functions.  */
1039   init_machine_status = rs6000_init_machine_status;
1040
1041   /* We should always be splitting complex arguments, but we can't break
1042      Linux and Darwin ABIs at the moment.  For now, only AIX is fixed.  */
1043   if (DEFAULT_ABI != ABI_AIX)
1044     targetm.calls.split_complex_arg = NULL;
1045 }
1046
1047 /* Handle generic options of the form -mfoo=yes/no.
1048    NAME is the option name.
1049    VALUE is the option value.
1050    FLAG is the pointer to the flag where to store a 1 or 0, depending on
1051    whether the option value is 'yes' or 'no' respectively.  */
1052 static void
1053 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1054 {
1055   if (value == 0)
1056     return;
1057   else if (!strcmp (value, "yes"))
1058     *flag = 1;
1059   else if (!strcmp (value, "no"))
1060     *flag = 0;
1061   else
1062     error ("unknown -m%s= option specified: '%s'", name, value);
1063 }
1064
1065 /* Handle -mabi= options.  */
1066 static void
1067 rs6000_parse_abi_options (void)
1068 {
1069   if (rs6000_abi_string == 0)
1070     return;
1071   else if (! strcmp (rs6000_abi_string, "altivec"))
1072     {
1073       rs6000_altivec_abi = 1;
1074       rs6000_spe_abi = 0;
1075     }
1076   else if (! strcmp (rs6000_abi_string, "no-altivec"))
1077     rs6000_altivec_abi = 0;
1078   else if (! strcmp (rs6000_abi_string, "spe"))
1079     {
1080       rs6000_spe_abi = 1;
1081       rs6000_altivec_abi = 0;
1082       if (!TARGET_SPE_ABI)
1083         error ("not configured for ABI: '%s'", rs6000_abi_string);
1084     }
1085
1086   else if (! strcmp (rs6000_abi_string, "no-spe"))
1087     rs6000_spe_abi = 0;
1088   else
1089     error ("unknown ABI specified: '%s'", rs6000_abi_string);
1090 }
1091
1092 /* Handle -malign-XXXXXX options.  */
1093 static void
1094 rs6000_parse_alignment_option (void)
1095 {
1096   if (rs6000_alignment_string == 0)
1097     return;
1098   else if (! strcmp (rs6000_alignment_string, "power"))
1099     rs6000_alignment_flags = MASK_ALIGN_POWER;
1100   else if (! strcmp (rs6000_alignment_string, "natural"))
1101     rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1102   else
1103     error ("unknown -malign-XXXXX option specified: '%s'",
1104            rs6000_alignment_string);
1105 }
1106
1107 /* Validate and record the size specified with the -mtls-size option.  */
1108
1109 static void
1110 rs6000_parse_tls_size_option (void)
1111 {
1112   if (rs6000_tls_size_string == 0)
1113     return;
1114   else if (strcmp (rs6000_tls_size_string, "16") == 0)
1115     rs6000_tls_size = 16;
1116   else if (strcmp (rs6000_tls_size_string, "32") == 0)
1117     rs6000_tls_size = 32;
1118   else if (strcmp (rs6000_tls_size_string, "64") == 0)
1119     rs6000_tls_size = 64;
1120   else
1121     error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1122 }
1123
1124 void
1125 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1126 {
1127 }
1128 \f
1129 /* Do anything needed at the start of the asm file.  */
1130
1131 static void
1132 rs6000_file_start (void)
1133 {
1134   size_t i;
1135   char buffer[80];
1136   const char *start = buffer;
1137   struct rs6000_cpu_select *ptr;
1138   const char *default_cpu = TARGET_CPU_DEFAULT;
1139   FILE *file = asm_out_file;
1140
1141   default_file_start ();
1142
1143 #ifdef TARGET_BI_ARCH
1144   if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1145     default_cpu = 0;
1146 #endif
1147
1148   if (flag_verbose_asm)
1149     {
1150       sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1151       rs6000_select[0].string = default_cpu;
1152
1153       for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1154         {
1155           ptr = &rs6000_select[i];
1156           if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1157             {
1158               fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1159               start = "";
1160             }
1161         }
1162
1163 #ifdef USING_ELFOS_H
1164       switch (rs6000_sdata)
1165         {
1166         case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1167         case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1168         case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1169         case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1170         }
1171
1172       if (rs6000_sdata && g_switch_value)
1173         {
1174           fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1175                    g_switch_value);
1176           start = "";
1177         }
1178 #endif
1179
1180       if (*start == '\0')
1181         putc ('\n', file);
1182     }
1183 }
1184 \f
1185 /* Return nonzero if this function is known to have a null epilogue.  */
1186
1187 int
1188 direct_return (void)
1189 {
1190   if (reload_completed)
1191     {
1192       rs6000_stack_t *info = rs6000_stack_info ();
1193
1194       if (info->first_gp_reg_save == 32
1195           && info->first_fp_reg_save == 64
1196           && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1197           && ! info->lr_save_p
1198           && ! info->cr_save_p
1199           && info->vrsave_mask == 0
1200           && ! info->push_p)
1201         return 1;
1202     }
1203
1204   return 0;
1205 }
1206
1207 /* Returns 1 always.  */
1208
1209 int
1210 any_operand (rtx op ATTRIBUTE_UNUSED,
1211              enum machine_mode mode ATTRIBUTE_UNUSED)
1212 {
1213   return 1;
1214 }
1215
1216 /* Returns 1 if op is the count register.  */
1217 int
1218 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1219 {
1220   if (GET_CODE (op) != REG)
1221     return 0;
1222
1223   if (REGNO (op) == COUNT_REGISTER_REGNUM)
1224     return 1;
1225
1226   if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1227     return 1;
1228
1229   return 0;
1230 }
1231
1232 /* Returns 1 if op is an altivec register.  */
1233 int
1234 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1235 {
1236
1237   return (register_operand (op, mode)
1238           && (GET_CODE (op) != REG
1239               || REGNO (op) > FIRST_PSEUDO_REGISTER
1240               || ALTIVEC_REGNO_P (REGNO (op))));
1241 }
1242
1243 int
1244 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1245 {
1246   if (GET_CODE (op) != REG)
1247     return 0;
1248
1249   if (XER_REGNO_P (REGNO (op)))
1250     return 1;
1251
1252   return 0;
1253 }
1254
1255 /* Return 1 if OP is a signed 8-bit constant.  Int multiplication
1256    by such constants completes more quickly.  */
1257
1258 int
1259 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1260 {
1261   return ( GET_CODE (op) == CONST_INT
1262           && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1263 }
1264
1265 /* Return 1 if OP is a constant that can fit in a D field.  */
1266
1267 int
1268 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1269 {
1270   return (GET_CODE (op) == CONST_INT
1271           && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1272 }
1273
1274 /* Similar for an unsigned D field.  */
1275
1276 int
1277 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1278 {
1279   return (GET_CODE (op) == CONST_INT
1280           && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1281 }
1282
1283 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
1284
1285 int
1286 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1287 {
1288   return (GET_CODE (op) == CONST_INT
1289           && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1290 }
1291
1292 /* Returns 1 if OP is a CONST_INT that is a positive value
1293    and an exact power of 2.  */
1294
1295 int
1296 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1297 {
1298   return (GET_CODE (op) == CONST_INT
1299           && INTVAL (op) > 0
1300           && exact_log2 (INTVAL (op)) >= 0);
1301 }
1302
1303 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1304    ctr, or lr).  */
1305
1306 int
1307 gpc_reg_operand (rtx op, enum machine_mode mode)
1308 {
1309   return (register_operand (op, mode)
1310           && (GET_CODE (op) != REG
1311               || (REGNO (op) >= ARG_POINTER_REGNUM
1312                   && !XER_REGNO_P (REGNO (op)))
1313               || REGNO (op) < MQ_REGNO));
1314 }
1315
1316 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1317    CR field.  */
1318
1319 int
1320 cc_reg_operand (rtx op, enum machine_mode mode)
1321 {
1322   return (register_operand (op, mode)
1323           && (GET_CODE (op) != REG
1324               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1325               || CR_REGNO_P (REGNO (op))));
1326 }
1327
1328 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1329    CR field that isn't CR0.  */
1330
1331 int
1332 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1333 {
1334   return (register_operand (op, mode)
1335           && (GET_CODE (op) != REG
1336               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1337               || CR_REGNO_NOT_CR0_P (REGNO (op))));
1338 }
1339
1340 /* Returns 1 if OP is either a constant integer valid for a D-field or
1341    a non-special register.  If a register, it must be in the proper
1342    mode unless MODE is VOIDmode.  */
1343
1344 int
1345 reg_or_short_operand (rtx op, enum machine_mode mode)
1346 {
1347   return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1348 }
1349
1350 /* Similar, except check if the negation of the constant would be
1351    valid for a D-field.  */
1352
1353 int
1354 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1355 {
1356   if (GET_CODE (op) == CONST_INT)
1357     return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1358
1359   return gpc_reg_operand (op, mode);
1360 }
1361
1362 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1363    a non-special register.  If a register, it must be in the proper
1364    mode unless MODE is VOIDmode.  */
1365
1366 int
1367 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1368 {
1369   if (gpc_reg_operand (op, mode))
1370     return 1;
1371   else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1372     return 1;
1373
1374   return 0;
1375 }
1376
1377
1378 /* Return 1 if the operand is either a register or an integer whose
1379    high-order 16 bits are zero.  */
1380
1381 int
1382 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1383 {
1384   return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1385 }
1386
1387 /* Return 1 is the operand is either a non-special register or ANY
1388    constant integer.  */
1389
1390 int
1391 reg_or_cint_operand (rtx op, enum machine_mode mode)
1392 {
1393   return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1394 }
1395
1396 /* Return 1 is the operand is either a non-special register or ANY
1397    32-bit signed constant integer.  */
1398
1399 int
1400 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1401 {
1402   return (gpc_reg_operand (op, mode)
1403           || (GET_CODE (op) == CONST_INT
1404 #if HOST_BITS_PER_WIDE_INT != 32
1405               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1406                   < (unsigned HOST_WIDE_INT) 0x100000000ll)
1407 #endif
1408               ));
1409 }
1410
1411 /* Return 1 is the operand is either a non-special register or a 32-bit
1412    signed constant integer valid for 64-bit addition.  */
1413
1414 int
1415 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1416 {
1417   return (gpc_reg_operand (op, mode)
1418           || (GET_CODE (op) == CONST_INT
1419 #if HOST_BITS_PER_WIDE_INT == 32
1420               && INTVAL (op) < 0x7fff8000
1421 #else
1422               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1423                   < 0x100000000ll)
1424 #endif
1425               ));
1426 }
1427
1428 /* Return 1 is the operand is either a non-special register or a 32-bit
1429    signed constant integer valid for 64-bit subtraction.  */
1430
1431 int
1432 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1433 {
1434   return (gpc_reg_operand (op, mode)
1435           || (GET_CODE (op) == CONST_INT
1436 #if HOST_BITS_PER_WIDE_INT == 32
1437               && (- INTVAL (op)) < 0x7fff8000
1438 #else
1439               && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1440                   < 0x100000000ll)
1441 #endif
1442               ));
1443 }
1444
1445 /* Return 1 is the operand is either a non-special register or ANY
1446    32-bit unsigned constant integer.  */
1447
1448 int
1449 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1450 {
1451   if (GET_CODE (op) == CONST_INT)
1452     {
1453       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1454         {
1455           if (GET_MODE_BITSIZE (mode) <= 32)
1456             abort ();
1457
1458           if (INTVAL (op) < 0)
1459             return 0;
1460         }
1461
1462       return ((INTVAL (op) & GET_MODE_MASK (mode)
1463                & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1464     }
1465   else if (GET_CODE (op) == CONST_DOUBLE)
1466     {
1467       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1468           || mode != DImode)
1469         abort ();
1470
1471       return CONST_DOUBLE_HIGH (op) == 0;
1472     }
1473   else
1474     return gpc_reg_operand (op, mode);
1475 }
1476
1477 /* Return 1 if the operand is an operand that can be loaded via the GOT.  */
1478
1479 int
1480 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1481 {
1482   return (GET_CODE (op) == SYMBOL_REF
1483           || GET_CODE (op) == CONST
1484           || GET_CODE (op) == LABEL_REF);
1485 }
1486
1487 /* Return 1 if the operand is a simple references that can be loaded via
1488    the GOT (labels involving addition aren't allowed).  */
1489
1490 int
1491 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1492 {
1493   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1494 }
1495
1496 /* Return the number of instructions it takes to form a constant in an
1497    integer register.  */
1498
1499 static int
1500 num_insns_constant_wide (HOST_WIDE_INT value)
1501 {
1502   /* signed constant loadable with {cal|addi} */
1503   if (CONST_OK_FOR_LETTER_P (value, 'I'))
1504     return 1;
1505
1506   /* constant loadable with {cau|addis} */
1507   else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1508     return 1;
1509
1510 #if HOST_BITS_PER_WIDE_INT == 64
1511   else if (TARGET_POWERPC64)
1512     {
1513       HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1514       HOST_WIDE_INT high = value >> 31;
1515
1516       if (high == 0 || high == -1)
1517         return 2;
1518
1519       high >>= 1;
1520
1521       if (low == 0)
1522         return num_insns_constant_wide (high) + 1;
1523       else
1524         return (num_insns_constant_wide (high)
1525                 + num_insns_constant_wide (low) + 1);
1526     }
1527 #endif
1528
1529   else
1530     return 2;
1531 }
1532
1533 int
1534 num_insns_constant (rtx op, enum machine_mode mode)
1535 {
1536   if (GET_CODE (op) == CONST_INT)
1537     {
1538 #if HOST_BITS_PER_WIDE_INT == 64
1539       if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1540           && mask64_operand (op, mode))
1541             return 2;
1542       else
1543 #endif
1544         return num_insns_constant_wide (INTVAL (op));
1545     }
1546
1547   else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1548     {
1549       long l;
1550       REAL_VALUE_TYPE rv;
1551
1552       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1553       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1554       return num_insns_constant_wide ((HOST_WIDE_INT) l);
1555     }
1556
1557   else if (GET_CODE (op) == CONST_DOUBLE)
1558     {
1559       HOST_WIDE_INT low;
1560       HOST_WIDE_INT high;
1561       long l[2];
1562       REAL_VALUE_TYPE rv;
1563       int endian = (WORDS_BIG_ENDIAN == 0);
1564
1565       if (mode == VOIDmode || mode == DImode)
1566         {
1567           high = CONST_DOUBLE_HIGH (op);
1568           low  = CONST_DOUBLE_LOW (op);
1569         }
1570       else
1571         {
1572           REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1573           REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1574           high = l[endian];
1575           low  = l[1 - endian];
1576         }
1577
1578       if (TARGET_32BIT)
1579         return (num_insns_constant_wide (low)
1580                 + num_insns_constant_wide (high));
1581
1582       else
1583         {
1584           if (high == 0 && low >= 0)
1585             return num_insns_constant_wide (low);
1586
1587           else if (high == -1 && low < 0)
1588             return num_insns_constant_wide (low);
1589
1590           else if (mask64_operand (op, mode))
1591             return 2;
1592
1593           else if (low == 0)
1594             return num_insns_constant_wide (high) + 1;
1595
1596           else
1597             return (num_insns_constant_wide (high)
1598                     + num_insns_constant_wide (low) + 1);
1599         }
1600     }
1601
1602   else
1603     abort ();
1604 }
1605
1606 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1607    register with one instruction per word.  We only do this if we can
1608    safely read CONST_DOUBLE_{LOW,HIGH}.  */
1609
1610 int
1611 easy_fp_constant (rtx op, enum machine_mode mode)
1612 {
1613   if (GET_CODE (op) != CONST_DOUBLE
1614       || GET_MODE (op) != mode
1615       || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1616     return 0;
1617
1618   /* Consider all constants with -msoft-float to be easy.  */
1619   if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1620       && mode != DImode)
1621     return 1;
1622
1623   /* If we are using V.4 style PIC, consider all constants to be hard.  */
1624   if (flag_pic && DEFAULT_ABI == ABI_V4)
1625     return 0;
1626
1627 #ifdef TARGET_RELOCATABLE
1628   /* Similarly if we are using -mrelocatable, consider all constants
1629      to be hard.  */
1630   if (TARGET_RELOCATABLE)
1631     return 0;
1632 #endif
1633
1634   if (mode == TFmode)
1635     {
1636       long k[4];
1637       REAL_VALUE_TYPE rv;
1638
1639       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1640       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1641
1642       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1643               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1644               && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1645               && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1646     }
1647
1648   else if (mode == DFmode)
1649     {
1650       long k[2];
1651       REAL_VALUE_TYPE rv;
1652
1653       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1654       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1655
1656       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1657               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1658     }
1659
1660   else if (mode == SFmode)
1661     {
1662       long l;
1663       REAL_VALUE_TYPE rv;
1664
1665       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1666       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1667
1668       return num_insns_constant_wide (l) == 1;
1669     }
1670
1671   else if (mode == DImode)
1672     return ((TARGET_POWERPC64
1673              && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1674             || (num_insns_constant (op, DImode) <= 2));
1675
1676   else if (mode == SImode)
1677     return 1;
1678   else
1679     abort ();
1680 }
1681
1682 /* Returns the constant for the splat instruction, if exists.  */
1683
1684 static int
1685 easy_vector_splat_const (int cst, enum machine_mode mode)
1686 {
1687   switch (mode)
1688     {
1689     case V4SImode:
1690       if (EASY_VECTOR_15 (cst)
1691           || EASY_VECTOR_15_ADD_SELF (cst))
1692         return cst;
1693       if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1694         break;
1695       cst = cst >> 16;
1696     case V8HImode:
1697       if (EASY_VECTOR_15 (cst)
1698           || EASY_VECTOR_15_ADD_SELF (cst))
1699         return cst;
1700       if ((cst & 0xff) != ((cst >> 8) & 0xff))
1701         break;
1702       cst = cst >> 8;
1703     case V16QImode:
1704           if (EASY_VECTOR_15 (cst)
1705               || EASY_VECTOR_15_ADD_SELF (cst))
1706             return cst;
1707     default:
1708       break;
1709     }
1710   return 0;
1711 }
1712
1713
1714 /* Return nonzero if all elements of a vector have the same value.  */
1715
1716 static int
1717 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1718 {
1719   int units, i, cst;
1720
1721   units = CONST_VECTOR_NUNITS (op);
1722
1723   cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1724   for (i = 1; i < units; ++i)
1725     if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1726       break;
1727   if (i == units && easy_vector_splat_const (cst, mode))
1728     return 1;
1729   return 0;
1730 }
1731
1732 /* Return 1 if the operand is a CONST_INT and can be put into a
1733    register without using memory.  */
1734
1735 int
1736 easy_vector_constant (rtx op, enum machine_mode mode)
1737 {
1738   int cst, cst2;
1739
1740   if (GET_CODE (op) != CONST_VECTOR
1741       || (!TARGET_ALTIVEC
1742           && !TARGET_SPE))
1743     return 0;
1744
1745   if (zero_constant (op, mode)
1746       && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1747           || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1748     return 1;
1749
1750   if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1751     return 0;
1752
1753   if (TARGET_SPE && mode == V1DImode)
1754     return 0;
1755
1756   cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
1757   cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1758
1759   /* Limit SPE vectors to 15 bits signed.  These we can generate with:
1760        li r0, CONSTANT1
1761        evmergelo r0, r0, r0
1762        li r0, CONSTANT2
1763
1764      I don't know how efficient it would be to allow bigger constants,
1765      considering we'll have an extra 'ori' for every 'li'.  I doubt 5
1766      instructions is better than a 64-bit memory load, but I don't
1767      have the e500 timing specs.  */
1768   if (TARGET_SPE && mode == V2SImode
1769       && cst  >= -0x7fff && cst <= 0x7fff
1770       && cst2 >= -0x7fff && cst2 <= 0x7fff)
1771     return 1;
1772
1773   if (TARGET_ALTIVEC
1774       && easy_vector_same (op, mode))
1775     {
1776       cst = easy_vector_splat_const (cst, mode);
1777       if (EASY_VECTOR_15_ADD_SELF (cst)
1778           || EASY_VECTOR_15 (cst))
1779         return 1;
1780     }
1781   return 0;
1782 }
1783
1784 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.  */
1785
1786 int
1787 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1788 {
1789   int cst;
1790   if (TARGET_ALTIVEC
1791       && GET_CODE (op) == CONST_VECTOR
1792       && easy_vector_same (op, mode))
1793     {
1794       cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
1795       if (EASY_VECTOR_15_ADD_SELF (cst))
1796         return 1;
1797     }
1798   return 0;
1799 }
1800
1801 /* Generate easy_vector_constant out of a easy_vector_constant_add_self.  */
1802
1803 rtx
1804 gen_easy_vector_constant_add_self (rtx op)
1805 {
1806   int i, units;
1807   rtvec v;
1808   units = GET_MODE_NUNITS (GET_MODE (op));
1809   v = rtvec_alloc (units);
1810
1811   for (i = 0; i < units; i++)
1812     RTVEC_ELT (v, i) =
1813       GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1814   return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1815 }
1816
1817 const char *
1818 output_vec_const_move (rtx *operands)
1819 {
1820   int cst, cst2;
1821   enum machine_mode mode;
1822   rtx dest, vec;
1823
1824   dest = operands[0];
1825   vec = operands[1];
1826
1827   cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1828   cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1829   mode = GET_MODE (dest);
1830
1831   if (TARGET_ALTIVEC)
1832     {
1833       if (zero_constant (vec, mode))
1834         return "vxor %0,%0,%0";
1835       else if (easy_vector_constant (vec, mode))
1836         {
1837           operands[1] = GEN_INT (cst);
1838           switch (mode)
1839             {
1840             case V4SImode:
1841               if (EASY_VECTOR_15 (cst))
1842                 {
1843                   operands[1] = GEN_INT (cst);
1844                   return "vspltisw %0,%1";
1845                 }
1846               else if (EASY_VECTOR_15_ADD_SELF (cst))
1847                 return "#";
1848               cst = cst >> 16;
1849             case V8HImode:
1850               if (EASY_VECTOR_15 (cst))
1851                 {
1852                   operands[1] = GEN_INT (cst);
1853                   return "vspltish %0,%1";
1854                 }
1855               else if (EASY_VECTOR_15_ADD_SELF (cst))
1856                 return "#";
1857               cst = cst >> 8;
1858             case V16QImode:
1859               if (EASY_VECTOR_15 (cst))
1860                 {
1861                   operands[1] = GEN_INT (cst);
1862                   return "vspltisb %0,%1";
1863                 }
1864               else if (EASY_VECTOR_15_ADD_SELF (cst))
1865                 return "#";
1866             default:
1867               abort ();
1868             }
1869         }
1870       else
1871         abort ();
1872     }
1873
1874   if (TARGET_SPE)
1875     {
1876       /* Vector constant 0 is handled as a splitter of V2SI, and in the
1877          pattern of V1DI, V4HI, and V2SF.
1878
1879          FIXME: We should probably return # and add post reload
1880          splitters for these, but this way is so easy ;-).
1881       */
1882       operands[1] = GEN_INT (cst);
1883       operands[2] = GEN_INT (cst2);
1884       if (cst == cst2)
1885         return "li %0,%1\n\tevmergelo %0,%0,%0";
1886       else
1887         return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1888     }
1889
1890   abort ();
1891 }
1892
1893 /* Return 1 if the operand is the constant 0.  This works for scalars
1894    as well as vectors.  */
1895 int
1896 zero_constant (rtx op, enum machine_mode mode)
1897 {
1898   return op == CONST0_RTX (mode);
1899 }
1900
1901 /* Return 1 if the operand is 0.0.  */
1902 int
1903 zero_fp_constant (rtx op, enum machine_mode mode)
1904 {
1905   return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1906 }
1907
1908 /* Return 1 if the operand is in volatile memory.  Note that during
1909    the RTL generation phase, memory_operand does not return TRUE for
1910    volatile memory references.  So this function allows us to
1911    recognize volatile references where its safe.  */
1912
1913 int
1914 volatile_mem_operand (rtx op, enum machine_mode mode)
1915 {
1916   if (GET_CODE (op) != MEM)
1917     return 0;
1918
1919   if (!MEM_VOLATILE_P (op))
1920     return 0;
1921
1922   if (mode != GET_MODE (op))
1923     return 0;
1924
1925   if (reload_completed)
1926     return memory_operand (op, mode);
1927
1928   if (reload_in_progress)
1929     return strict_memory_address_p (mode, XEXP (op, 0));
1930
1931   return memory_address_p (mode, XEXP (op, 0));
1932 }
1933
1934 /* Return 1 if the operand is an offsettable memory operand.  */
1935
1936 int
1937 offsettable_mem_operand (rtx op, enum machine_mode mode)
1938 {
1939   return ((GET_CODE (op) == MEM)
1940           && offsettable_address_p (reload_completed || reload_in_progress,
1941                                     mode, XEXP (op, 0)));
1942 }
1943
1944 /* Return 1 if the operand is either an easy FP constant (see above) or
1945    memory.  */
1946
1947 int
1948 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1949 {
1950   return memory_operand (op, mode) || easy_fp_constant (op, mode);
1951 }
1952
1953 /* Return 1 if the operand is either a non-special register or an item
1954    that can be used as the operand of a `mode' add insn.  */
1955
1956 int
1957 add_operand (rtx op, enum machine_mode mode)
1958 {
1959   if (GET_CODE (op) == CONST_INT)
1960     return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1961             || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1962
1963   return gpc_reg_operand (op, mode);
1964 }
1965
1966 /* Return 1 if OP is a constant but not a valid add_operand.  */
1967
1968 int
1969 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1970 {
1971   return (GET_CODE (op) == CONST_INT
1972           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1973           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1974 }
1975
1976 /* Return 1 if the operand is a non-special register or a constant that
1977    can be used as the operand of an OR or XOR insn on the RS/6000.  */
1978
1979 int
1980 logical_operand (rtx op, enum machine_mode mode)
1981 {
1982   HOST_WIDE_INT opl, oph;
1983
1984   if (gpc_reg_operand (op, mode))
1985     return 1;
1986
1987   if (GET_CODE (op) == CONST_INT)
1988     {
1989       opl = INTVAL (op) & GET_MODE_MASK (mode);
1990
1991 #if HOST_BITS_PER_WIDE_INT <= 32
1992       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1993         return 0;
1994 #endif
1995     }
1996   else if (GET_CODE (op) == CONST_DOUBLE)
1997     {
1998       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1999         abort ();
2000
2001       opl = CONST_DOUBLE_LOW (op);
2002       oph = CONST_DOUBLE_HIGH (op);
2003       if (oph != 0)
2004         return 0;
2005     }
2006   else
2007     return 0;
2008
2009   return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2010           || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2011 }
2012
2013 /* Return 1 if C is a constant that is not a logical operand (as
2014    above), but could be split into one.  */
2015
2016 int
2017 non_logical_cint_operand (rtx op, enum machine_mode mode)
2018 {
2019   return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2020           && ! logical_operand (op, mode)
2021           && reg_or_logical_cint_operand (op, mode));
2022 }
2023
2024 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2025    RS/6000.  It is if there are no more than two 1->0 or 0->1 transitions.
2026    Reject all ones and all zeros, since these should have been optimized
2027    away and confuse the making of MB and ME.  */
2028
2029 int
2030 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2031 {
2032   HOST_WIDE_INT c, lsb;
2033
2034   if (GET_CODE (op) != CONST_INT)
2035     return 0;
2036
2037   c = INTVAL (op);
2038
2039   /* Fail in 64-bit mode if the mask wraps around because the upper
2040      32-bits of the mask will all be 1s, contrary to GCC's internal view.  */
2041   if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2042     return 0;
2043
2044   /* We don't change the number of transitions by inverting,
2045      so make sure we start with the LS bit zero.  */
2046   if (c & 1)
2047     c = ~c;
2048
2049   /* Reject all zeros or all ones.  */
2050   if (c == 0)
2051     return 0;
2052
2053   /* Find the first transition.  */
2054   lsb = c & -c;
2055
2056   /* Invert to look for a second transition.  */
2057   c = ~c;
2058
2059   /* Erase first transition.  */
2060   c &= -lsb;
2061
2062   /* Find the second transition (if any).  */
2063   lsb = c & -c;
2064
2065   /* Match if all the bits above are 1's (or c is zero).  */
2066   return c == -lsb;
2067 }
2068
2069 /* Return 1 for the PowerPC64 rlwinm corner case.  */
2070
2071 int
2072 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2073 {
2074   HOST_WIDE_INT c, lsb;
2075
2076   if (GET_CODE (op) != CONST_INT)
2077     return 0;
2078
2079   c = INTVAL (op);
2080
2081   if ((c & 0x80000001) != 0x80000001)
2082     return 0;
2083
2084   c = ~c;
2085   if (c == 0)
2086     return 0;
2087
2088   lsb = c & -c;
2089   c = ~c;
2090   c &= -lsb;
2091   lsb = c & -c;
2092   return c == -lsb;
2093 }
2094
2095 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2096    It is if there are no more than one 1->0 or 0->1 transitions.
2097    Reject all zeros, since zero should have been optimized away and
2098    confuses the making of MB and ME.  */
2099
2100 int
2101 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2102 {
2103   if (GET_CODE (op) == CONST_INT)
2104     {
2105       HOST_WIDE_INT c, lsb;
2106
2107       c = INTVAL (op);
2108
2109       /* Reject all zeros.  */
2110       if (c == 0)
2111         return 0;
2112
2113       /* We don't change the number of transitions by inverting,
2114          so make sure we start with the LS bit zero.  */
2115       if (c & 1)
2116         c = ~c;
2117
2118       /* Find the transition, and check that all bits above are 1's.  */
2119       lsb = c & -c;
2120
2121       /* Match if all the bits above are 1's (or c is zero).  */
2122       return c == -lsb;
2123     }
2124   return 0;
2125 }
2126
2127 /* Like mask64_operand, but allow up to three transitions.  This
2128    predicate is used by insn patterns that generate two rldicl or
2129    rldicr machine insns.  */
2130
2131 int
2132 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2133 {
2134   if (GET_CODE (op) == CONST_INT)
2135     {
2136       HOST_WIDE_INT c, lsb;
2137
2138       c = INTVAL (op);
2139
2140       /* Disallow all zeros.  */
2141       if (c == 0)
2142         return 0;
2143
2144       /* We don't change the number of transitions by inverting,
2145          so make sure we start with the LS bit zero.  */
2146       if (c & 1)
2147         c = ~c;
2148
2149       /* Find the first transition.  */
2150       lsb = c & -c;
2151
2152       /* Invert to look for a second transition.  */
2153       c = ~c;
2154
2155       /* Erase first transition.  */
2156       c &= -lsb;
2157
2158       /* Find the second transition.  */
2159       lsb = c & -c;
2160
2161       /* Invert to look for a third transition.  */
2162       c = ~c;
2163
2164       /* Erase second transition.  */
2165       c &= -lsb;
2166
2167       /* Find the third transition (if any).  */
2168       lsb = c & -c;
2169
2170       /* Match if all the bits above are 1's (or c is zero).  */
2171       return c == -lsb;
2172     }
2173   return 0;
2174 }
2175
2176 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2177    implement ANDing by the mask IN.  */
2178 void
2179 build_mask64_2_operands (rtx in, rtx *out)
2180 {
2181 #if HOST_BITS_PER_WIDE_INT >= 64
2182   unsigned HOST_WIDE_INT c, lsb, m1, m2;
2183   int shift;
2184
2185   if (GET_CODE (in) != CONST_INT)
2186     abort ();
2187
2188   c = INTVAL (in);
2189   if (c & 1)
2190     {
2191       /* Assume c initially something like 0x00fff000000fffff.  The idea
2192          is to rotate the word so that the middle ^^^^^^ group of zeros
2193          is at the MS end and can be cleared with an rldicl mask.  We then
2194          rotate back and clear off the MS    ^^ group of zeros with a
2195          second rldicl.  */
2196       c = ~c;                   /*   c == 0xff000ffffff00000 */
2197       lsb = c & -c;             /* lsb == 0x0000000000100000 */
2198       m1 = -lsb;                /*  m1 == 0xfffffffffff00000 */
2199       c = ~c;                   /*   c == 0x00fff000000fffff */
2200       c &= -lsb;                /*   c == 0x00fff00000000000 */
2201       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2202       c = ~c;                   /*   c == 0xff000fffffffffff */
2203       c &= -lsb;                /*   c == 0xff00000000000000 */
2204       shift = 0;
2205       while ((lsb >>= 1) != 0)
2206         shift++;                /* shift == 44 on exit from loop */
2207       m1 <<= 64 - shift;        /*  m1 == 0xffffff0000000000 */
2208       m1 = ~m1;                 /*  m1 == 0x000000ffffffffff */
2209       m2 = ~c;                  /*  m2 == 0x00ffffffffffffff */
2210     }
2211   else
2212     {
2213       /* Assume c initially something like 0xff000f0000000000.  The idea
2214          is to rotate the word so that the     ^^^  middle group of zeros
2215          is at the LS end and can be cleared with an rldicr mask.  We then
2216          rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2217          a second rldicr.  */
2218       lsb = c & -c;             /* lsb == 0x0000010000000000 */
2219       m2 = -lsb;                /*  m2 == 0xffffff0000000000 */
2220       c = ~c;                   /*   c == 0x00fff0ffffffffff */
2221       c &= -lsb;                /*   c == 0x00fff00000000000 */
2222       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2223       c = ~c;                   /*   c == 0xff000fffffffffff */
2224       c &= -lsb;                /*   c == 0xff00000000000000 */
2225       shift = 0;
2226       while ((lsb >>= 1) != 0)
2227         shift++;                /* shift == 44 on exit from loop */
2228       m1 = ~c;                  /*  m1 == 0x00ffffffffffffff */
2229       m1 >>= shift;             /*  m1 == 0x0000000000000fff */
2230       m1 = ~m1;                 /*  m1 == 0xfffffffffffff000 */
2231     }
2232
2233   /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2234      masks will be all 1's.  We are guaranteed more than one transition.  */
2235   out[0] = GEN_INT (64 - shift);
2236   out[1] = GEN_INT (m1);
2237   out[2] = GEN_INT (shift);
2238   out[3] = GEN_INT (m2);
2239 #else
2240   (void)in;
2241   (void)out;
2242   abort ();
2243 #endif
2244 }
2245
2246 /* Return 1 if the operand is either a non-special register or a constant
2247    that can be used as the operand of a PowerPC64 logical AND insn.  */
2248
2249 int
2250 and64_operand (rtx op, enum machine_mode mode)
2251 {
2252   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2253     return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2254
2255   return (logical_operand (op, mode) || mask64_operand (op, mode));
2256 }
2257
2258 /* Like the above, but also match constants that can be implemented
2259    with two rldicl or rldicr insns.  */
2260
2261 int
2262 and64_2_operand (rtx op, enum machine_mode mode)
2263 {
2264   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2265     return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2266
2267   return logical_operand (op, mode) || mask64_2_operand (op, mode);
2268 }
2269
2270 /* Return 1 if the operand is either a non-special register or a
2271    constant that can be used as the operand of an RS/6000 logical AND insn.  */
2272
2273 int
2274 and_operand (rtx op, enum machine_mode mode)
2275 {
2276   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2277     return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2278
2279   return (logical_operand (op, mode) || mask_operand (op, mode));
2280 }
2281
2282 /* Return 1 if the operand is a general register or memory operand.  */
2283
2284 int
2285 reg_or_mem_operand (rtx op, enum machine_mode mode)
2286 {
2287   return (gpc_reg_operand (op, mode)
2288           || memory_operand (op, mode)
2289           || macho_lo_sum_memory_operand (op, mode)
2290           || volatile_mem_operand (op, mode));
2291 }
2292
2293 /* Return 1 if the operand is a general register or memory operand without
2294    pre_inc or pre_dec which produces invalid form of PowerPC lwa
2295    instruction.  */
2296
2297 int
2298 lwa_operand (rtx op, enum machine_mode mode)
2299 {
2300   rtx inner = op;
2301
2302   if (reload_completed && GET_CODE (inner) == SUBREG)
2303     inner = SUBREG_REG (inner);
2304
2305   return gpc_reg_operand (inner, mode)
2306     || (memory_operand (inner, mode)
2307         && GET_CODE (XEXP (inner, 0)) != PRE_INC
2308         && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2309         && (GET_CODE (XEXP (inner, 0)) != PLUS
2310             || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2311             || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2312 }
2313
2314 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.  */
2315
2316 int
2317 symbol_ref_operand (rtx op, enum machine_mode mode)
2318 {
2319   if (mode != VOIDmode && GET_MODE (op) != mode)
2320     return 0;
2321
2322   return (GET_CODE (op) == SYMBOL_REF
2323           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2324 }
2325
2326 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2327    to CALL.  This is a SYMBOL_REF, a pseudo-register, LR or CTR.  */
2328
2329 int
2330 call_operand (rtx op, enum machine_mode mode)
2331 {
2332   if (mode != VOIDmode && GET_MODE (op) != mode)
2333     return 0;
2334
2335   return (GET_CODE (op) == SYMBOL_REF
2336           || (GET_CODE (op) == REG
2337               && (REGNO (op) == LINK_REGISTER_REGNUM
2338                   || REGNO (op) == COUNT_REGISTER_REGNUM
2339                   || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2340 }
2341
2342 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2343    this file.  */
2344
2345 int
2346 current_file_function_operand (rtx op,
2347                               enum machine_mode mode ATTRIBUTE_UNUSED)
2348 {
2349   return (GET_CODE (op) == SYMBOL_REF
2350           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2351           && (SYMBOL_REF_LOCAL_P (op)
2352               || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2353 }
2354
2355 /* Return 1 if this operand is a valid input for a move insn.  */
2356
2357 int
2358 input_operand (rtx op, enum machine_mode mode)
2359 {
2360   /* Memory is always valid.  */
2361   if (memory_operand (op, mode))
2362     return 1;
2363
2364   /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary.  */
2365   if (GET_CODE (op) == CONSTANT_P_RTX)
2366     return 1;
2367
2368   /* For floating-point, easy constants are valid.  */
2369   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2370       && CONSTANT_P (op)
2371       && easy_fp_constant (op, mode))
2372     return 1;
2373
2374   /* Allow any integer constant.  */
2375   if (GET_MODE_CLASS (mode) == MODE_INT
2376       && (GET_CODE (op) == CONST_INT
2377           || GET_CODE (op) == CONST_DOUBLE))
2378     return 1;
2379
2380   /* Allow easy vector constants.  */
2381   if (GET_CODE (op) == CONST_VECTOR
2382       && easy_vector_constant (op, mode))
2383     return 1;
2384
2385   /* For floating-point or multi-word mode, the only remaining valid type
2386      is a register.  */
2387   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2388       || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2389     return register_operand (op, mode);
2390
2391   /* The only cases left are integral modes one word or smaller (we
2392      do not get called for MODE_CC values).  These can be in any
2393      register.  */
2394   if (register_operand (op, mode))
2395     return 1;
2396
2397   /* A SYMBOL_REF referring to the TOC is valid.  */
2398   if (legitimate_constant_pool_address_p (op))
2399     return 1;
2400
2401   /* A constant pool expression (relative to the TOC) is valid */
2402   if (toc_relative_expr_p (op))
2403     return 1;
2404
2405   /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2406      to be valid.  */
2407   if (DEFAULT_ABI == ABI_V4
2408       && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2409       && small_data_operand (op, Pmode))
2410     return 1;
2411
2412   return 0;
2413 }
2414
2415
2416 /* Darwin, AIX increases natural record alignment to doubleword if the first
2417    field is an FP double while the FP fields remain word aligned.  */
2418
2419 unsigned int
2420 rs6000_special_round_type_align (tree type, int computed, int specified)
2421 {
2422   tree field = TYPE_FIELDS (type);
2423
2424   /* Skip all the static variables only if ABI is greater than
2425      1 or equal to 0.  */
2426   while (field != NULL && TREE_CODE (field) == VAR_DECL)
2427     field = TREE_CHAIN (field);
2428
2429   if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2430     return MAX (computed, specified);
2431
2432   return MAX (MAX (computed, specified), 64);
2433 }
2434
2435 /* Return 1 for an operand in small memory on V.4/eabi.  */
2436
2437 int
2438 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2439                     enum machine_mode mode ATTRIBUTE_UNUSED)
2440 {
2441 #if TARGET_ELF
2442   rtx sym_ref;
2443
2444   if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2445     return 0;
2446
2447   if (DEFAULT_ABI != ABI_V4)
2448     return 0;
2449
2450   if (GET_CODE (op) == SYMBOL_REF)
2451     sym_ref = op;
2452
2453   else if (GET_CODE (op) != CONST
2454            || GET_CODE (XEXP (op, 0)) != PLUS
2455            || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2456            || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2457     return 0;
2458
2459   else
2460     {
2461       rtx sum = XEXP (op, 0);
2462       HOST_WIDE_INT summand;
2463
2464       /* We have to be careful here, because it is the referenced address
2465         that must be 32k from _SDA_BASE_, not just the symbol.  */
2466       summand = INTVAL (XEXP (sum, 1));
2467       if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2468        return 0;
2469
2470       sym_ref = XEXP (sum, 0);
2471     }
2472
2473   return SYMBOL_REF_SMALL_P (sym_ref);
2474 #else
2475   return 0;
2476 #endif
2477 }
2478
2479 /* Return true, if operand is a memory operand and has a
2480    displacement divisible by 4.  */
2481
2482 int
2483 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2484 {
2485   rtx addr;
2486   int off = 0;
2487
2488   if (!memory_operand (op, mode))
2489     return 0;
2490
2491   addr = XEXP (op, 0);
2492   if (GET_CODE (addr) == PLUS
2493       && GET_CODE (XEXP (addr, 0)) == REG
2494       && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2495     off = INTVAL (XEXP (addr, 1));
2496
2497   return (off % 4) == 0;
2498 }
2499
2500 /* Return true if either operand is a general purpose register.  */
2501
2502 bool
2503 gpr_or_gpr_p (rtx op0, rtx op1)
2504 {
2505   return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2506           || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2507 }
2508
2509 \f
2510 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address.  */
2511
2512 static int
2513 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2514 {
2515   switch (GET_CODE(op))
2516     {
2517     case SYMBOL_REF:
2518       if (RS6000_SYMBOL_REF_TLS_P (op))
2519         return 0;
2520       else if (CONSTANT_POOL_ADDRESS_P (op))
2521         {
2522           if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2523             {
2524               *have_sym = 1;
2525               return 1;
2526             }
2527           else
2528             return 0;
2529         }
2530       else if (! strcmp (XSTR (op, 0), toc_label_name))
2531         {
2532           *have_toc = 1;
2533           return 1;
2534         }
2535       else
2536         return 0;
2537     case PLUS:
2538     case MINUS:
2539       return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2540               && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2541     case CONST:
2542       return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2543     case CONST_INT:
2544       return 1;
2545     default:
2546       return 0;
2547     }
2548 }
2549
2550 static bool
2551 constant_pool_expr_p (rtx op)
2552 {
2553   int have_sym = 0;
2554   int have_toc = 0;
2555   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2556 }
2557
2558 static bool
2559 toc_relative_expr_p (rtx op)
2560 {
2561   int have_sym = 0;
2562   int have_toc = 0;
2563   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2564 }
2565
2566 /* SPE offset addressing is limited to 5-bits worth of double words.  */
2567 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2568
2569 bool
2570 legitimate_constant_pool_address_p (rtx x)
2571 {
2572   return (TARGET_TOC
2573           && GET_CODE (x) == PLUS
2574           && GET_CODE (XEXP (x, 0)) == REG
2575           && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2576           && constant_pool_expr_p (XEXP (x, 1)));
2577 }
2578
2579 static bool
2580 legitimate_small_data_p (enum machine_mode mode, rtx x)
2581 {
2582   return (DEFAULT_ABI == ABI_V4
2583           && !flag_pic && !TARGET_TOC
2584           && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2585           && small_data_operand (x, mode));
2586 }
2587
2588 static bool
2589 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2590 {
2591   unsigned HOST_WIDE_INT offset, extra;
2592
2593   if (GET_CODE (x) != PLUS)
2594     return false;
2595   if (GET_CODE (XEXP (x, 0)) != REG)
2596     return false;
2597   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2598     return false;
2599   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2600     return false;
2601
2602   offset = INTVAL (XEXP (x, 1));
2603   extra = 0;
2604   switch (mode)
2605     {
2606     case V16QImode:
2607     case V8HImode:
2608     case V4SFmode:
2609     case V4SImode:
2610       /* AltiVec vector modes.  Only reg+reg addressing is valid here,
2611          which leaves the only valid constant offset of zero, which by
2612          canonicalization rules is also invalid.  */
2613       return false;
2614
2615     case V4HImode:
2616     case V2SImode:
2617     case V1DImode:
2618     case V2SFmode:
2619       /* SPE vector modes.  */
2620       return SPE_CONST_OFFSET_OK (offset);
2621
2622     case DFmode:
2623     case DImode:
2624       if (mode == DFmode || !TARGET_POWERPC64)
2625         extra = 4;
2626       else if (offset & 3)
2627         return false;
2628       break;
2629
2630     case TFmode:
2631     case TImode:
2632       if (mode == TFmode || !TARGET_POWERPC64)
2633         extra = 12;
2634       else if (offset & 3)
2635         return false;
2636       else
2637         extra = 8;
2638       break;
2639
2640     default:
2641       break;
2642     }
2643
2644   offset += 0x8000;
2645   return (offset < 0x10000) && (offset + extra < 0x10000);
2646 }
2647
2648 static bool
2649 legitimate_indexed_address_p (rtx x, int strict)
2650 {
2651   rtx op0, op1;
2652
2653   if (GET_CODE (x) != PLUS)
2654     return false;
2655   op0 = XEXP (x, 0);
2656   op1 = XEXP (x, 1);
2657
2658   if (!REG_P (op0) || !REG_P (op1))
2659     return false;
2660
2661   return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2662            && INT_REG_OK_FOR_INDEX_P (op1, strict))
2663           || (INT_REG_OK_FOR_BASE_P (op1, strict)
2664               && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2665 }
2666
2667 static inline bool
2668 legitimate_indirect_address_p (rtx x, int strict)
2669 {
2670   return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2671 }
2672
2673 static bool
2674 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2675 {
2676     if (!TARGET_MACHO || !flag_pic
2677         || mode != SImode || GET_CODE(x) != MEM)
2678       return false;
2679     x = XEXP (x, 0);
2680
2681   if (GET_CODE (x) != LO_SUM)
2682     return false;
2683   if (GET_CODE (XEXP (x, 0)) != REG)
2684     return false;
2685   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2686     return false;
2687   x = XEXP (x, 1);
2688
2689   return CONSTANT_P (x);
2690 }
2691
2692 static bool
2693 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2694 {
2695   if (GET_CODE (x) != LO_SUM)
2696     return false;
2697   if (GET_CODE (XEXP (x, 0)) != REG)
2698     return false;
2699   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2700     return false;
2701   x = XEXP (x, 1);
2702
2703   if (TARGET_ELF || TARGET_MACHO)
2704     {
2705       if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2706         return false;
2707       if (TARGET_TOC)
2708         return false;
2709       if (GET_MODE_NUNITS (mode) != 1)
2710         return false;
2711       if (GET_MODE_BITSIZE (mode) > 32
2712           && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2713         return false;
2714
2715       return CONSTANT_P (x);
2716     }
2717
2718   return false;
2719 }
2720
2721
2722 /* Try machine-dependent ways of modifying an illegitimate address
2723    to be legitimate.  If we find one, return the new, valid address.
2724    This is used from only one place: `memory_address' in explow.c.
2725
2726    OLDX is the address as it was before break_out_memory_refs was
2727    called.  In some cases it is useful to look at this to decide what
2728    needs to be done.
2729
2730    MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2731
2732    It is always safe for this function to do nothing.  It exists to
2733    recognize opportunities to optimize the output.
2734
2735    On RS/6000, first check for the sum of a register with a constant
2736    integer that is out of range.  If so, generate code to add the
2737    constant with the low-order 16 bits masked to the register and force
2738    this result into another register (this can be done with `cau').
2739    Then generate an address of REG+(CONST&0xffff), allowing for the
2740    possibility of bit 16 being a one.
2741
2742    Then check for the sum of a register and something not constant, try to
2743    load the other things into a register and return the sum.  */
2744
2745 rtx
2746 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2747                            enum machine_mode mode)
2748 {
2749   if (GET_CODE (x) == SYMBOL_REF)
2750     {
2751       enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2752       if (model != 0)
2753         return rs6000_legitimize_tls_address (x, model);
2754     }
2755
2756   if (GET_CODE (x) == PLUS
2757       && GET_CODE (XEXP (x, 0)) == REG
2758       && GET_CODE (XEXP (x, 1)) == CONST_INT
2759       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2760     {
2761       HOST_WIDE_INT high_int, low_int;
2762       rtx sum;
2763       low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2764       high_int = INTVAL (XEXP (x, 1)) - low_int;
2765       sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2766                                          GEN_INT (high_int)), 0);
2767       return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2768     }
2769   else if (GET_CODE (x) == PLUS
2770            && GET_CODE (XEXP (x, 0)) == REG
2771            && GET_CODE (XEXP (x, 1)) != CONST_INT
2772            && GET_MODE_NUNITS (mode) == 1
2773            && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2774                || TARGET_POWERPC64
2775                || (mode != DFmode && mode != TFmode))
2776            && (TARGET_POWERPC64 || mode != DImode)
2777            && mode != TImode)
2778     {
2779       return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2780                            force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2781     }
2782   else if (ALTIVEC_VECTOR_MODE (mode))
2783     {
2784       rtx reg;
2785
2786       /* Make sure both operands are registers.  */
2787       if (GET_CODE (x) == PLUS)
2788         return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2789                              force_reg (Pmode, XEXP (x, 1)));
2790
2791       reg = force_reg (Pmode, x);
2792       return reg;
2793     }
2794   else if (SPE_VECTOR_MODE (mode))
2795     {
2796       /* We accept [reg + reg] and [reg + OFFSET].  */
2797
2798       if (GET_CODE (x) == PLUS)
2799       {
2800         rtx op1 = XEXP (x, 0);
2801         rtx op2 = XEXP (x, 1);
2802
2803         op1 = force_reg (Pmode, op1);
2804
2805         if (GET_CODE (op2) != REG
2806             && (GET_CODE (op2) != CONST_INT
2807                 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2808           op2 = force_reg (Pmode, op2);
2809
2810         return gen_rtx_PLUS (Pmode, op1, op2);
2811       }
2812
2813       return force_reg (Pmode, x);
2814     }
2815   else if (TARGET_ELF
2816            && TARGET_32BIT
2817            && TARGET_NO_TOC
2818            && ! flag_pic
2819            && GET_CODE (x) != CONST_INT
2820            && GET_CODE (x) != CONST_DOUBLE
2821            && CONSTANT_P (x)
2822            && GET_MODE_NUNITS (mode) == 1
2823            && (GET_MODE_BITSIZE (mode) <= 32
2824                || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2825     {
2826       rtx reg = gen_reg_rtx (Pmode);
2827       emit_insn (gen_elf_high (reg, x));
2828       return gen_rtx_LO_SUM (Pmode, reg, x);
2829     }
2830   else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2831            && ! flag_pic
2832 #if TARGET_MACHO
2833            && ! MACHO_DYNAMIC_NO_PIC_P
2834 #endif
2835            && GET_CODE (x) != CONST_INT
2836            && GET_CODE (x) != CONST_DOUBLE
2837            && CONSTANT_P (x)
2838            && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2839            && mode != DImode
2840            && mode != TImode)
2841     {
2842       rtx reg = gen_reg_rtx (Pmode);
2843       emit_insn (gen_macho_high (reg, x));
2844       return gen_rtx_LO_SUM (Pmode, reg, x);
2845     }
2846   else if (TARGET_TOC
2847            && constant_pool_expr_p (x)
2848            && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2849     {
2850       return create_TOC_reference (x);
2851     }
2852   else
2853     return NULL_RTX;
2854 }
2855
2856 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2857    We need to emit DTP-relative relocations.  */
2858
2859 void
2860 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2861 {
2862   switch (size)
2863     {
2864     case 4:
2865       fputs ("\t.long\t", file);
2866       break;
2867     case 8:
2868       fputs (DOUBLE_INT_ASM_OP, file);
2869       break;
2870     default:
2871       abort ();
2872     }
2873   output_addr_const (file, x);
2874   fputs ("@dtprel+0x8000", file);
2875 }
2876
2877 /* Construct the SYMBOL_REF for the tls_get_addr function.  */
2878
2879 static GTY(()) rtx rs6000_tls_symbol;
2880 static rtx
2881 rs6000_tls_get_addr (void)
2882 {
2883   if (!rs6000_tls_symbol)
2884     rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2885
2886   return rs6000_tls_symbol;
2887 }
2888
2889 /* Construct the SYMBOL_REF for TLS GOT references.  */
2890
2891 static GTY(()) rtx rs6000_got_symbol;
2892 static rtx
2893 rs6000_got_sym (void)
2894 {
2895   if (!rs6000_got_symbol)
2896     {
2897       rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2898       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2899       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2900     }
2901
2902   return rs6000_got_symbol;
2903 }
2904
2905 /* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
2906    this (thread-local) address.  */
2907
2908 static rtx
2909 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2910 {
2911   rtx dest, insn;
2912
2913   dest = gen_reg_rtx (Pmode);
2914   if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2915     {
2916       rtx tlsreg;
2917
2918       if (TARGET_64BIT)
2919         {
2920           tlsreg = gen_rtx_REG (Pmode, 13);
2921           insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2922         }
2923       else
2924         {
2925           tlsreg = gen_rtx_REG (Pmode, 2);
2926           insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2927         }
2928       emit_insn (insn);
2929     }
2930   else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2931     {
2932       rtx tlsreg, tmp;
2933
2934       tmp = gen_reg_rtx (Pmode);
2935       if (TARGET_64BIT)
2936         {
2937           tlsreg = gen_rtx_REG (Pmode, 13);
2938           insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2939         }
2940       else
2941         {
2942           tlsreg = gen_rtx_REG (Pmode, 2);
2943           insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2944         }
2945       emit_insn (insn);
2946       if (TARGET_64BIT)
2947         insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2948       else
2949         insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2950       emit_insn (insn);
2951     }
2952   else
2953     {
2954       rtx r3, got, tga, tmp1, tmp2, eqv;
2955
2956       if (TARGET_64BIT)
2957         got = gen_rtx_REG (Pmode, TOC_REGISTER);
2958       else
2959         {
2960           if (flag_pic == 1)
2961             got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2962           else
2963             {
2964               rtx gsym = rs6000_got_sym ();
2965               got = gen_reg_rtx (Pmode);
2966               if (flag_pic == 0)
2967                 rs6000_emit_move (got, gsym, Pmode);
2968               else
2969                 {
2970                   char buf[30];
2971                   static int tls_got_labelno = 0;
2972                   rtx tempLR, lab, tmp3, mem;
2973                   rtx first, last;
2974
2975                   ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2976                   lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2977                   tempLR = gen_reg_rtx (Pmode);
2978                   tmp1 = gen_reg_rtx (Pmode);
2979                   tmp2 = gen_reg_rtx (Pmode);
2980                   tmp3 = gen_reg_rtx (Pmode);
2981                   mem = gen_rtx_MEM (Pmode, tmp1);
2982                   RTX_UNCHANGING_P (mem) = 1;
2983
2984                   first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2985                                                              gsym));
2986                   emit_move_insn (tmp1, tempLR);
2987                   emit_move_insn (tmp2, mem);
2988                   emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2989                   last = emit_move_insn (got, tmp3);
2990                   REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2991                                                         REG_NOTES (last));
2992                   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2993                                                          REG_NOTES (first));
2994                   REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2995                                                         REG_NOTES (last));
2996                 }
2997             }
2998         }
2999
3000       if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3001         {
3002           r3 = gen_rtx_REG (Pmode, 3);
3003           if (TARGET_64BIT)
3004             insn = gen_tls_gd_64 (r3, got, addr);
3005           else
3006             insn = gen_tls_gd_32 (r3, got, addr);
3007           start_sequence ();
3008           emit_insn (insn);
3009           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3010           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3011           insn = emit_call_insn (insn);
3012           CONST_OR_PURE_CALL_P (insn) = 1;
3013           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3014           insn = get_insns ();
3015           end_sequence ();
3016           emit_libcall_block (insn, dest, r3, addr);
3017         }
3018       else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3019         {
3020           r3 = gen_rtx_REG (Pmode, 3);
3021           if (TARGET_64BIT)
3022             insn = gen_tls_ld_64 (r3, got);
3023           else
3024             insn = gen_tls_ld_32 (r3, got);
3025           start_sequence ();
3026           emit_insn (insn);
3027           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3028           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3029           insn = emit_call_insn (insn);
3030           CONST_OR_PURE_CALL_P (insn) = 1;
3031           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3032           insn = get_insns ();
3033           end_sequence ();
3034           tmp1 = gen_reg_rtx (Pmode);
3035           eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3036                                 UNSPEC_TLSLD);
3037           emit_libcall_block (insn, tmp1, r3, eqv);
3038           if (rs6000_tls_size == 16)
3039             {
3040               if (TARGET_64BIT)
3041                 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3042               else
3043                 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3044             }
3045           else if (rs6000_tls_size == 32)
3046             {
3047               tmp2 = gen_reg_rtx (Pmode);
3048               if (TARGET_64BIT)
3049                 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3050               else
3051                 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3052               emit_insn (insn);
3053               if (TARGET_64BIT)
3054                 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3055               else
3056                 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3057             }
3058           else
3059             {
3060               tmp2 = gen_reg_rtx (Pmode);
3061               if (TARGET_64BIT)
3062                 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3063               else
3064                 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3065               emit_insn (insn);
3066               insn = gen_rtx_SET (Pmode, dest,
3067                                   gen_rtx_PLUS (Pmode, tmp2, tmp1));
3068             }
3069           emit_insn (insn);
3070         }
3071       else
3072         {
3073           /* IE, or 64 bit offset LE.  */
3074           tmp2 = gen_reg_rtx (Pmode);
3075           if (TARGET_64BIT)
3076             insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3077           else
3078             insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3079           emit_insn (insn);
3080           if (TARGET_64BIT)
3081             insn = gen_tls_tls_64 (dest, tmp2, addr);
3082           else
3083             insn = gen_tls_tls_32 (dest, tmp2, addr);
3084           emit_insn (insn);
3085         }
3086     }
3087
3088   return dest;
3089 }
3090
3091 /* Return 1 if X is a SYMBOL_REF for a TLS symbol.  This is used in
3092    instruction definitions.  */
3093
3094 int
3095 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3096 {
3097   return RS6000_SYMBOL_REF_TLS_P (x);
3098 }
3099
3100 /* Return 1 if X contains a thread-local symbol.  */
3101
3102 bool
3103 rs6000_tls_referenced_p (rtx x)
3104 {
3105   if (! TARGET_HAVE_TLS)
3106     return false;
3107
3108   return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3109 }
3110
3111 /* Return 1 if *X is a thread-local symbol.  This is the same as
3112    rs6000_tls_symbol_ref except for the type of the unused argument.  */
3113
3114 static inline int
3115 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3116 {
3117   return RS6000_SYMBOL_REF_TLS_P (*x);
3118 }
3119
3120 /* The convention appears to be to define this wherever it is used.
3121    With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3122    is now used here.  */
3123 #ifndef REG_MODE_OK_FOR_BASE_P
3124 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3125 #endif
3126
3127 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS.  Returns a value to
3128    replace the input X, or the original X if no replacement is called for.
3129    The output parameter *WIN is 1 if the calling macro should goto WIN,
3130    0 if it should not.
3131
3132    For RS/6000, we wish to handle large displacements off a base
3133    register by splitting the addend across an addiu/addis and the mem insn.
3134    This cuts number of extra insns needed from 3 to 1.
3135
3136    On Darwin, we use this to generate code for floating point constants.
3137    A movsf_low is generated so we wind up with 2 instructions rather than 3.
3138    The Darwin code is inside #if TARGET_MACHO because only then is
3139    machopic_function_base_name() defined.  */
3140 rtx
3141 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3142         int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
3143 {
3144   /* We must recognize output that we have already generated ourselves.  */
3145   if (GET_CODE (x) == PLUS
3146       && GET_CODE (XEXP (x, 0)) == PLUS
3147       && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3148       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3149       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3150     {
3151       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3152                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3153                    opnum, (enum reload_type)type);
3154       *win = 1;
3155       return x;
3156     }
3157
3158 #if TARGET_MACHO
3159   if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3160       && GET_CODE (x) == LO_SUM
3161       && GET_CODE (XEXP (x, 0)) == PLUS
3162       && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3163       && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3164       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3165       && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3166       && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3167       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3168       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3169     {
3170       /* Result of previous invocation of this function on Darwin
3171          floating point constant.  */
3172       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3173                 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3174                 opnum, (enum reload_type)type);
3175       *win = 1;
3176       return x;
3177     }
3178 #endif
3179   if (GET_CODE (x) == PLUS
3180       && GET_CODE (XEXP (x, 0)) == REG
3181       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3182       && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3183       && GET_CODE (XEXP (x, 1)) == CONST_INT
3184       && !SPE_VECTOR_MODE (mode)
3185       && !ALTIVEC_VECTOR_MODE (mode))
3186     {
3187       HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3188       HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3189       HOST_WIDE_INT high
3190         = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3191
3192       /* Check for 32-bit overflow.  */
3193       if (high + low != val)
3194         {
3195           *win = 0;
3196           return x;
3197         }
3198
3199       /* Reload the high part into a base reg; leave the low part
3200          in the mem directly.  */
3201
3202       x = gen_rtx_PLUS (GET_MODE (x),
3203                         gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3204                                       GEN_INT (high)),
3205                         GEN_INT (low));
3206
3207       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3208                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3209                    opnum, (enum reload_type)type);
3210       *win = 1;
3211       return x;
3212     }
3213 #if TARGET_MACHO
3214   if (GET_CODE (x) == SYMBOL_REF
3215       && DEFAULT_ABI == ABI_DARWIN
3216       && !ALTIVEC_VECTOR_MODE (mode)
3217       && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3218       /* Don't do this for TFmode, since the result isn't offsettable.  */
3219       && mode != TFmode)
3220     {
3221       if (flag_pic)
3222         {
3223           rtx offset = gen_rtx_CONST (Pmode,
3224                          gen_rtx_MINUS (Pmode, x,
3225                            gen_rtx_SYMBOL_REF (Pmode,
3226                              machopic_function_base_name ())));
3227           x = gen_rtx_LO_SUM (GET_MODE (x),
3228                 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3229                   gen_rtx_HIGH (Pmode, offset)), offset);
3230         }
3231       else
3232         x = gen_rtx_LO_SUM (GET_MODE (x),
3233               gen_rtx_HIGH (Pmode, x), x);
3234
3235       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3236                    BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3237                    opnum, (enum reload_type)type);
3238       *win = 1;
3239       return x;
3240     }
3241 #endif
3242   if (TARGET_TOC
3243       && constant_pool_expr_p (x)
3244       && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3245     {
3246       (x) = create_TOC_reference (x);
3247       *win = 1;
3248       return x;
3249     }
3250   *win = 0;
3251   return x;
3252 }
3253
3254 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3255    that is a valid memory address for an instruction.
3256    The MODE argument is the machine mode for the MEM expression
3257    that wants to use this address.
3258
3259    On the RS/6000, there are four valid address: a SYMBOL_REF that
3260    refers to a constant pool entry of an address (or the sum of it
3261    plus a constant), a short (16-bit signed) constant plus a register,
3262    the sum of two registers, or a register indirect, possibly with an
3263    auto-increment.  For DFmode and DImode with a constant plus register,
3264    we must ensure that both words are addressable or PowerPC64 with offset
3265    word aligned.
3266
3267    For modes spanning multiple registers (DFmode in 32-bit GPRs,
3268    32-bit DImode, TImode), indexed addressing cannot be used because
3269    adjacent memory cells are accessed by adding word-sized offsets
3270    during assembly output.  */
3271 int
3272 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3273 {
3274   if (RS6000_SYMBOL_REF_TLS_P (x))
3275     return 0;
3276   if (legitimate_indirect_address_p (x, reg_ok_strict))
3277     return 1;
3278   if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3279       && !ALTIVEC_VECTOR_MODE (mode)
3280       && !SPE_VECTOR_MODE (mode)
3281       && TARGET_UPDATE
3282       && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3283     return 1;
3284   if (legitimate_small_data_p (mode, x))
3285     return 1;
3286   if (legitimate_constant_pool_address_p (x))
3287     return 1;
3288   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
3289   if (! reg_ok_strict
3290       && GET_CODE (x) == PLUS
3291       && GET_CODE (XEXP (x, 0)) == REG
3292       && (XEXP (x, 0) == virtual_stack_vars_rtx
3293          || XEXP (x, 0) == arg_pointer_rtx)
3294       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3295     return 1;
3296   if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3297     return 1;
3298   if (mode != TImode
3299       && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3300           || TARGET_POWERPC64
3301           || (mode != DFmode && mode != TFmode))
3302       && (TARGET_POWERPC64 || mode != DImode)
3303       && legitimate_indexed_address_p (x, reg_ok_strict))
3304     return 1;
3305   if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3306     return 1;
3307   return 0;
3308 }
3309
3310 /* Go to LABEL if ADDR (a legitimate address expression)
3311    has an effect that depends on the machine mode it is used for.
3312
3313    On the RS/6000 this is true of all integral offsets (since AltiVec
3314    modes don't allow them) or is a pre-increment or decrement.
3315
3316    ??? Except that due to conceptual problems in offsettable_address_p
3317    we can't really report the problems of integral offsets.  So leave
3318    this assuming that the adjustable offset must be valid for the
3319    sub-words of a TFmode operand, which is what we had before.  */
3320
3321 bool
3322 rs6000_mode_dependent_address (rtx addr)
3323 {
3324   switch (GET_CODE (addr))
3325     {
3326     case PLUS:
3327       if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3328         {
3329           unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3330           return val + 12 + 0x8000 >= 0x10000;
3331         }
3332       break;
3333
3334     case LO_SUM:
3335       return true;
3336
3337     case PRE_INC:
3338     case PRE_DEC:
3339       return TARGET_UPDATE;
3340
3341     default:
3342       break;
3343     }
3344
3345   return false;
3346 }
3347
3348 /* Return number of consecutive hard regs needed starting at reg REGNO
3349    to hold something of mode MODE.
3350    This is ordinarily the length in words of a value of mode MODE
3351    but can be less for certain modes in special long registers.
3352
3353    For the SPE, GPRs are 64 bits but only 32 bits are visible in
3354    scalar instructions.  The upper 32 bits are only available to the
3355    SIMD instructions.
3356
3357    POWER and PowerPC GPRs hold 32 bits worth;
3358    PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */
3359
3360 int
3361 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3362 {
3363   if (FP_REGNO_P (regno))
3364     return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3365
3366   if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3367     return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3368
3369   if (ALTIVEC_REGNO_P (regno))
3370     return
3371       (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3372
3373   return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3374 }
3375 \f
3376 /* Try to output insns to set TARGET equal to the constant C if it can
3377    be done in less than N insns.  Do all computations in MODE.
3378    Returns the place where the output has been placed if it can be
3379    done and the insns have been emitted.  If it would take more than N
3380    insns, zero is returned and no insns and emitted.  */
3381
3382 rtx
3383 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3384                        rtx source, int n ATTRIBUTE_UNUSED)
3385 {
3386   rtx result, insn, set;
3387   HOST_WIDE_INT c0, c1;
3388
3389   if (mode == QImode || mode == HImode)
3390     {
3391       if (dest == NULL)
3392         dest = gen_reg_rtx (mode);
3393       emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3394       return dest;
3395     }
3396   else if (mode == SImode)
3397     {
3398       result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3399
3400       emit_insn (gen_rtx_SET (VOIDmode, result,
3401                               GEN_INT (INTVAL (source)
3402                                        & (~ (HOST_WIDE_INT) 0xffff))));
3403       emit_insn (gen_rtx_SET (VOIDmode, dest,
3404                               gen_rtx_IOR (SImode, result,
3405                                            GEN_INT (INTVAL (source) & 0xffff))));
3406       result = dest;
3407     }
3408   else if (mode == DImode)
3409     {
3410       if (GET_CODE (source) == CONST_INT)
3411         {
3412           c0 = INTVAL (source);
3413           c1 = -(c0 < 0);
3414         }
3415       else if (GET_CODE (source) == CONST_DOUBLE)
3416         {
3417 #if HOST_BITS_PER_WIDE_INT >= 64
3418           c0 = CONST_DOUBLE_LOW (source);
3419           c1 = -(c0 < 0);
3420 #else
3421           c0 = CONST_DOUBLE_LOW (source);
3422           c1 = CONST_DOUBLE_HIGH (source);
3423 #endif
3424         }
3425       else
3426         abort ();
3427
3428       result = rs6000_emit_set_long_const (dest, c0, c1);
3429     }
3430   else
3431     abort ();
3432
3433   insn = get_last_insn ();
3434   set = single_set (insn);
3435   if (! CONSTANT_P (SET_SRC (set)))
3436     set_unique_reg_note (insn, REG_EQUAL, source);
3437
3438   return result;
3439 }
3440
3441 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3442    fall back to a straight forward decomposition.  We do this to avoid
3443    exponential run times encountered when looking for longer sequences
3444    with rs6000_emit_set_const.  */
3445 static rtx
3446 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3447 {
3448   if (!TARGET_POWERPC64)
3449     {
3450       rtx operand1, operand2;
3451
3452       operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3453                                         DImode);
3454       operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3455                                         DImode);
3456       emit_move_insn (operand1, GEN_INT (c1));
3457       emit_move_insn (operand2, GEN_INT (c2));
3458     }
3459   else
3460     {
3461       HOST_WIDE_INT ud1, ud2, ud3, ud4;
3462
3463       ud1 = c1 & 0xffff;
3464       ud2 = (c1 & 0xffff0000) >> 16;
3465 #if HOST_BITS_PER_WIDE_INT >= 64
3466       c2 = c1 >> 32;
3467 #endif
3468       ud3 = c2 & 0xffff;
3469       ud4 = (c2 & 0xffff0000) >> 16;
3470
3471       if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3472           || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3473         {
3474           if (ud1 & 0x8000)
3475             emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) -  0x8000)));
3476           else
3477             emit_move_insn (dest, GEN_INT (ud1));
3478         }
3479
3480       else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3481                || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3482         {
3483           if (ud2 & 0x8000)
3484             emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3485                                            - 0x80000000));
3486           else
3487             emit_move_insn (dest, GEN_INT (ud2 << 16));
3488           if (ud1 != 0)
3489             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3490         }
3491       else if ((ud4 == 0xffff && (ud3 & 0x8000))
3492                || (ud4 == 0 && ! (ud3 & 0x8000)))
3493         {
3494           if (ud3 & 0x8000)
3495             emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3496                                            - 0x80000000));
3497           else
3498             emit_move_insn (dest, GEN_INT (ud3 << 16));
3499
3500           if (ud2 != 0)
3501             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3502           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3503           if (ud1 != 0)
3504             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3505         }
3506       else
3507         {
3508           if (ud4 & 0x8000)
3509             emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3510                                            - 0x80000000));
3511           else
3512             emit_move_insn (dest, GEN_INT (ud4 << 16));
3513
3514           if (ud3 != 0)
3515             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3516
3517           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3518           if (ud2 != 0)
3519             emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3520                                                GEN_INT (ud2 << 16)));
3521           if (ud1 != 0)
3522             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3523         }
3524     }
3525   return dest;
3526 }
3527
3528 /* Emit a move from SOURCE to DEST in mode MODE.  */
3529 void
3530 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3531 {
3532   rtx operands[2];
3533   operands[0] = dest;
3534   operands[1] = source;
3535
3536   /* Sanity checks.  Check that we get CONST_DOUBLE only when we should.  */
3537   if (GET_CODE (operands[1]) == CONST_DOUBLE
3538       && ! FLOAT_MODE_P (mode)
3539       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3540     {
3541       /* FIXME.  This should never happen.  */
3542       /* Since it seems that it does, do the safe thing and convert
3543          to a CONST_INT.  */
3544       operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3545     }
3546   if (GET_CODE (operands[1]) == CONST_DOUBLE
3547       && ! FLOAT_MODE_P (mode)
3548       && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3549            && CONST_DOUBLE_LOW (operands[1]) >= 0)
3550           || (CONST_DOUBLE_HIGH (operands[1]) == -1
3551               && CONST_DOUBLE_LOW (operands[1]) < 0)))
3552     abort ();
3553
3554   /* Check if GCC is setting up a block move that will end up using FP
3555      registers as temporaries.  We must make sure this is acceptable.  */
3556   if (GET_CODE (operands[0]) == MEM
3557       && GET_CODE (operands[1]) == MEM
3558       && mode == DImode
3559       && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3560           || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3561       && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3562                                             ? 32 : MEM_ALIGN (operands[0])))
3563             || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3564                                                ? 32
3565                                                : MEM_ALIGN (operands[1]))))
3566       && ! MEM_VOLATILE_P (operands [0])
3567       && ! MEM_VOLATILE_P (operands [1]))
3568     {
3569       emit_move_insn (adjust_address (operands[0], SImode, 0),
3570                       adjust_address (operands[1], SImode, 0));
3571       emit_move_insn (adjust_address (operands[0], SImode, 4),
3572                       adjust_address (operands[1], SImode, 4));
3573       return;
3574     }
3575
3576   if (!no_new_pseudos)
3577     {
3578       if (GET_CODE (operands[1]) == MEM && optimize > 0
3579           && (mode == QImode || mode == HImode || mode == SImode)
3580           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3581         {
3582           rtx reg = gen_reg_rtx (word_mode);
3583
3584           emit_insn (gen_rtx_SET (word_mode, reg,
3585                                   gen_rtx_ZERO_EXTEND (word_mode,
3586                                                        operands[1])));
3587           operands[1] = gen_lowpart (mode, reg);
3588         }
3589       if (GET_CODE (operands[0]) != REG)
3590         operands[1] = force_reg (mode, operands[1]);
3591     }
3592
3593   if (mode == SFmode && ! TARGET_POWERPC
3594       && TARGET_HARD_FLOAT && TARGET_FPRS
3595       && GET_CODE (operands[0]) == MEM)
3596     {
3597       int regnum;
3598
3599       if (reload_in_progress || reload_completed)
3600         regnum = true_regnum (operands[1]);
3601       else if (GET_CODE (operands[1]) == REG)
3602         regnum = REGNO (operands[1]);
3603       else
3604         regnum = -1;
3605
3606       /* If operands[1] is a register, on POWER it may have
3607          double-precision data in it, so truncate it to single
3608          precision.  */
3609       if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3610         {
3611           rtx newreg;
3612           newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3613           emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3614           operands[1] = newreg;
3615         }
3616     }
3617
3618   /* Recognize the case where operand[1] is a reference to thread-local
3619      data and load its address to a register.  */
3620   if (GET_CODE (operands[1]) == SYMBOL_REF)
3621     {
3622       enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3623       if (model != 0)
3624         operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3625     }
3626
3627   /* Handle the case where reload calls us with an invalid address.  */
3628   if (reload_in_progress && mode == Pmode
3629       && (! general_operand (operands[1], mode)
3630           || ! nonimmediate_operand (operands[0], mode)))
3631     goto emit_set;
3632
3633   /* Handle the case of CONSTANT_P_RTX.  */
3634   if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3635     goto emit_set;
3636
3637   /* 128-bit constant floating-point values on Darwin should really be
3638      loaded as two parts.  */
3639   if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3640       && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3641       && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3642     {
3643       /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3644          know how to get a DFmode SUBREG of a TFmode.  */
3645       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3646                         simplify_gen_subreg (DImode, operands[1], mode, 0),
3647                         DImode);
3648       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3649                                              GET_MODE_SIZE (DImode)),
3650                         simplify_gen_subreg (DImode, operands[1], mode,
3651                                              GET_MODE_SIZE (DImode)),
3652                         DImode);
3653       return;
3654     }
3655
3656   /* FIXME:  In the long term, this switch statement should go away
3657      and be replaced by a sequence of tests based on things like
3658      mode == Pmode.  */
3659   switch (mode)
3660     {
3661     case HImode:
3662     case QImode:
3663       if (CONSTANT_P (operands[1])
3664           && GET_CODE (operands[1]) != CONST_INT)
3665         operands[1] = force_const_mem (mode, operands[1]);
3666       break;
3667
3668     case TFmode:
3669     case DFmode:
3670     case SFmode:
3671       if (CONSTANT_P (operands[1])
3672           && ! easy_fp_constant (operands[1], mode))
3673         operands[1] = force_const_mem (mode, operands[1]);
3674       break;
3675
3676     case V16QImode:
3677     case V8HImode:
3678     case V4SFmode:
3679     case V4SImode:
3680     case V4HImode:
3681     case V2SFmode:
3682     case V2SImode:
3683     case V1DImode:
3684       if (CONSTANT_P (operands[1])
3685           && !easy_vector_constant (operands[1], mode))
3686         operands[1] = force_const_mem (mode, operands[1]);
3687       break;
3688
3689     case SImode:
3690     case DImode:
3691       /* Use default pattern for address of ELF small data */
3692       if (TARGET_ELF
3693           && mode == Pmode
3694           && DEFAULT_ABI == ABI_V4
3695           && (GET_CODE (operands[1]) == SYMBOL_REF
3696               || GET_CODE (operands[1]) == CONST)
3697           && small_data_operand (operands[1], mode))
3698         {
3699           emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3700           return;
3701         }
3702
3703       if (DEFAULT_ABI == ABI_V4
3704           && mode == Pmode && mode == SImode
3705           && flag_pic == 1 && got_operand (operands[1], mode))
3706         {
3707           emit_insn (gen_movsi_got (operands[0], operands[1]));
3708           return;
3709         }
3710
3711       if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3712           && TARGET_NO_TOC
3713           && ! flag_pic
3714           && mode == Pmode
3715           && CONSTANT_P (operands[1])
3716           && GET_CODE (operands[1]) != HIGH
3717           && GET_CODE (operands[1]) != CONST_INT)
3718         {
3719           rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3720
3721           /* If this is a function address on -mcall-aixdesc,
3722              convert it to the address of the descriptor.  */
3723           if (DEFAULT_ABI == ABI_AIX
3724               && GET_CODE (operands[1]) == SYMBOL_REF
3725               && XSTR (operands[1], 0)[0] == '.')
3726             {
3727               const char *name = XSTR (operands[1], 0);
3728               rtx new_ref;
3729               while (*name == '.')
3730                 name++;
3731               new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3732               CONSTANT_POOL_ADDRESS_P (new_ref)
3733                 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3734               SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3735               SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3736               SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3737               operands[1] = new_ref;
3738             }
3739
3740           if (DEFAULT_ABI == ABI_DARWIN)
3741             {
3742 #if TARGET_MACHO
3743               if (MACHO_DYNAMIC_NO_PIC_P)
3744                 {
3745                   /* Take care of any required data indirection.  */
3746                   operands[1] = rs6000_machopic_legitimize_pic_address (
3747                                   operands[1], mode, operands[0]);
3748                   if (operands[0] != operands[1])
3749                     emit_insn (gen_rtx_SET (VOIDmode,
3750                                             operands[0], operands[1]));
3751                   return;
3752                 }
3753 #endif
3754               emit_insn (gen_macho_high (target, operands[1]));
3755               emit_insn (gen_macho_low (operands[0], target, operands[1]));
3756               return;
3757             }
3758
3759           emit_insn (gen_elf_high (target, operands[1]));
3760           emit_insn (gen_elf_low (operands[0], target, operands[1]));
3761           return;
3762         }
3763
3764       /* If this is a SYMBOL_REF that refers to a constant pool entry,
3765          and we have put it in the TOC, we just need to make a TOC-relative
3766          reference to it.  */
3767       if (TARGET_TOC
3768           && GET_CODE (operands[1]) == SYMBOL_REF
3769           && constant_pool_expr_p (operands[1])
3770           && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3771                                               get_pool_mode (operands[1])))
3772         {
3773           operands[1] = create_TOC_reference (operands[1]);
3774         }
3775       else if (mode == Pmode
3776                && CONSTANT_P (operands[1])
3777                && ((GET_CODE (operands[1]) != CONST_INT
3778                     && ! easy_fp_constant (operands[1], mode))
3779                    || (GET_CODE (operands[1]) == CONST_INT
3780                        && num_insns_constant (operands[1], mode) > 2)
3781                    || (GET_CODE (operands[0]) == REG
3782                        && FP_REGNO_P (REGNO (operands[0]))))
3783                && GET_CODE (operands[1]) != HIGH
3784                && ! legitimate_constant_pool_address_p (operands[1])
3785                && ! toc_relative_expr_p (operands[1]))
3786         {
3787           /* Emit a USE operation so that the constant isn't deleted if
3788              expensive optimizations are turned on because nobody
3789              references it.  This should only be done for operands that
3790              contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3791              This should not be done for operands that contain LABEL_REFs.
3792              For now, we just handle the obvious case.  */
3793           if (GET_CODE (operands[1]) != LABEL_REF)
3794             emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3795
3796 #if TARGET_MACHO
3797           /* Darwin uses a special PIC legitimizer.  */
3798           if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3799             {
3800               operands[1] =
3801                 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3802                                                         operands[0]);
3803               if (operands[0] != operands[1])
3804                 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3805               return;
3806             }
3807 #endif
3808
3809           /* If we are to limit the number of things we put in the TOC and
3810              this is a symbol plus a constant we can add in one insn,
3811              just put the symbol in the TOC and add the constant.  Don't do
3812              this if reload is in progress.  */
3813           if (GET_CODE (operands[1]) == CONST
3814               && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3815               && GET_CODE (XEXP (operands[1], 0)) == PLUS
3816               && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3817               && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3818                   || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3819               && ! side_effects_p (operands[0]))
3820             {
3821               rtx sym =
3822                 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3823               rtx other = XEXP (XEXP (operands[1], 0), 1);
3824
3825               sym = force_reg (mode, sym);
3826               if (mode == SImode)
3827                 emit_insn (gen_addsi3 (operands[0], sym, other));
3828               else
3829                 emit_insn (gen_adddi3 (operands[0], sym, other));
3830               return;
3831             }
3832
3833           operands[1] = force_const_mem (mode, operands[1]);
3834
3835           if (TARGET_TOC
3836               && constant_pool_expr_p (XEXP (operands[1], 0))
3837               && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3838                         get_pool_constant (XEXP (operands[1], 0)),
3839                         get_pool_mode (XEXP (operands[1], 0))))
3840             {
3841               operands[1]
3842                 = gen_rtx_MEM (mode,
3843                                create_TOC_reference (XEXP (operands[1], 0)));
3844               set_mem_alias_set (operands[1], get_TOC_alias_set ());
3845               RTX_UNCHANGING_P (operands[1]) = 1;
3846             }
3847         }
3848       break;
3849
3850     case TImode:
3851       if (GET_CODE (operands[0]) == MEM
3852           && GET_CODE (XEXP (operands[0], 0)) != REG
3853           && ! reload_in_progress)
3854         operands[0]
3855           = replace_equiv_address (operands[0],
3856                                    copy_addr_to_reg (XEXP (operands[0], 0)));
3857
3858       if (GET_CODE (operands[1]) == MEM
3859           && GET_CODE (XEXP (operands[1], 0)) != REG
3860           && ! reload_in_progress)
3861         operands[1]
3862           = replace_equiv_address (operands[1],
3863                                    copy_addr_to_reg (XEXP (operands[1], 0)));
3864       if (TARGET_POWER)
3865         {
3866           emit_insn (gen_rtx_PARALLEL (VOIDmode,
3867                        gen_rtvec (2,
3868                                   gen_rtx_SET (VOIDmode,
3869                                                operands[0], operands[1]),
3870                                   gen_rtx_CLOBBER (VOIDmode,
3871                                                    gen_rtx_SCRATCH (SImode)))));
3872           return;
3873         }
3874       break;
3875
3876     default:
3877       abort ();
3878     }
3879
3880   /* Above, we may have called force_const_mem which may have returned
3881      an invalid address.  If we can, fix this up; otherwise, reload will
3882      have to deal with it.  */
3883   if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3884     operands[1] = validize_mem (operands[1]);
3885
3886  emit_set:
3887   emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3888 }
3889 \f
3890 /* Nonzero if we can use a floating-point register to pass this arg.  */
3891 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE)         \
3892   (GET_MODE_CLASS (MODE) == MODE_FLOAT          \
3893    && (CUM)->fregno <= FP_ARG_MAX_REG           \
3894    && TARGET_HARD_FLOAT && TARGET_FPRS)
3895
3896 /* Nonzero if we can use an AltiVec register to pass this arg.  */
3897 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED)      \
3898   (ALTIVEC_VECTOR_MODE (MODE)                           \
3899    && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG              \
3900    && TARGET_ALTIVEC_ABI                                \
3901    && (NAMED))
3902
3903 /* Return a nonzero value to say to return the function value in
3904    memory, just as large structures are always returned.  TYPE will be
3905    the data type of the value, and FNTYPE will be the type of the
3906    function doing the returning, or @code{NULL} for libcalls.
3907
3908    The AIX ABI for the RS/6000 specifies that all structures are
3909    returned in memory.  The Darwin ABI does the same.  The SVR4 ABI
3910    specifies that structures <= 8 bytes are returned in r3/r4, but a
3911    draft put them in memory, and GCC used to implement the draft
3912    instead of the final standard.  Therefore, TARGET_AIX_STRUCT_RET
3913    controls this instead of DEFAULT_ABI; V.4 targets needing backward
3914    compatibility can change DRAFT_V4_STRUCT_RET to override the
3915    default, and -m switches get the final word.  See
3916    rs6000_override_options for more details.
3917
3918    The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3919    long double support is enabled.  These values are returned in memory.
3920
3921    int_size_in_bytes returns -1 for variable size objects, which go in
3922    memory always.  The cast to unsigned makes -1 > 8.  */
3923
3924 static bool
3925 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3926 {
3927   if (AGGREGATE_TYPE_P (type)
3928       && (TARGET_AIX_STRUCT_RET
3929           || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3930     return true;
3931   if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3932     return true;
3933   return false;
3934 }
3935
3936 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3937    for a call to a function whose data type is FNTYPE.
3938    For a library call, FNTYPE is 0.
3939
3940    For incoming args we set the number of arguments in the prototype large
3941    so we never return a PARALLEL.  */
3942
3943 void
3944 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3945                       rtx libname ATTRIBUTE_UNUSED, int incoming,
3946                       int libcall, int n_named_args)
3947 {
3948   static CUMULATIVE_ARGS zero_cumulative;
3949
3950   *cum = zero_cumulative;
3951   cum->words = 0;
3952   cum->fregno = FP_ARG_MIN_REG;
3953   cum->vregno = ALTIVEC_ARG_MIN_REG;
3954   cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3955   cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3956                       ? CALL_LIBCALL : CALL_NORMAL);
3957   cum->sysv_gregno = GP_ARG_MIN_REG;
3958   cum->stdarg = fntype
3959     && (TYPE_ARG_TYPES (fntype) != 0
3960         && (TREE_VALUE (tree_last  (TYPE_ARG_TYPES (fntype)))
3961             != void_type_node));
3962
3963   cum->nargs_prototype = 0;
3964   if (incoming || cum->prototype)
3965     cum->nargs_prototype = n_named_args;
3966
3967   /* Check for a longcall attribute.  */
3968   if (fntype
3969       && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3970       && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3971     cum->call_cookie = CALL_LONG;
3972
3973   if (TARGET_DEBUG_ARG)
3974     {
3975       fprintf (stderr, "\ninit_cumulative_args:");
3976       if (fntype)
3977         {
3978           tree ret_type = TREE_TYPE (fntype);
3979           fprintf (stderr, " ret code = %s,",
3980                    tree_code_name[ (int)TREE_CODE (ret_type) ]);
3981         }
3982
3983       if (cum->call_cookie & CALL_LONG)
3984         fprintf (stderr, " longcall,");
3985
3986       fprintf (stderr, " proto = %d, nargs = %d\n",
3987                cum->prototype, cum->nargs_prototype);
3988     }
3989
3990     if (fntype
3991         && !TARGET_ALTIVEC
3992         && TARGET_ALTIVEC_ABI
3993         && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3994       {
3995         error ("Cannot return value in vector register because"
3996                " altivec instructions are disabled, use -maltivec"
3997                " to enable them.");
3998       }
3999 }
4000 \f
4001 /* If defined, a C expression which determines whether, and in which
4002    direction, to pad out an argument with extra space.  The value
4003    should be of type `enum direction': either `upward' to pad above
4004    the argument, `downward' to pad below, or `none' to inhibit
4005    padding.
4006
4007    For the AIX ABI structs are always stored left shifted in their
4008    argument slot.  */
4009
4010 enum direction
4011 function_arg_padding (enum machine_mode mode, tree type)
4012 {
4013 #ifndef AGGREGATE_PADDING_FIXED
4014 #define AGGREGATE_PADDING_FIXED 0
4015 #endif
4016 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4017 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4018 #endif
4019
4020   if (!AGGREGATE_PADDING_FIXED)
4021     {
4022       /* GCC used to pass structures of the same size as integer types as
4023          if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4024          ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4025          passed padded downward, except that -mstrict-align further
4026          muddied the water in that multi-component structures of 2 and 4
4027          bytes in size were passed padded upward.
4028
4029          The following arranges for best compatibility with previous
4030          versions of gcc, but removes the -mstrict-align dependency.  */
4031       if (BYTES_BIG_ENDIAN)
4032         {
4033           HOST_WIDE_INT size = 0;
4034
4035           if (mode == BLKmode)
4036             {
4037               if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4038                 size = int_size_in_bytes (type);
4039             }
4040           else
4041             size = GET_MODE_SIZE (mode);
4042
4043           if (size == 1 || size == 2 || size == 4)
4044             return downward;
4045         }
4046       return upward;
4047     }
4048
4049   if (AGGREGATES_PAD_UPWARD_ALWAYS)
4050     {
4051       if (type != 0 && AGGREGATE_TYPE_P (type))
4052         return upward;
4053     }
4054
4055   /* Fall back to the default.  */
4056   return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4057 }
4058
4059 /* If defined, a C expression that gives the alignment boundary, in bits,
4060    of an argument with the specified mode and type.  If it is not defined,
4061    PARM_BOUNDARY is used for all arguments.
4062
4063    V.4 wants long longs to be double word aligned.  */
4064
4065 int
4066 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4067 {
4068   if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
4069     return 64;
4070    else if (SPE_VECTOR_MODE (mode))
4071      return 64;
4072   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4073     return 128;
4074   else
4075     return PARM_BOUNDARY;
4076 }
4077
4078 /* Compute the size (in words) of a function argument.  */
4079
4080 static unsigned long
4081 rs6000_arg_size (enum machine_mode mode, tree type)
4082 {
4083   unsigned long size;
4084
4085   if (mode != BLKmode)
4086     size = GET_MODE_SIZE (mode);
4087   else
4088     size = int_size_in_bytes (type);
4089
4090   if (TARGET_32BIT)
4091     return (size + 3) >> 2;
4092   else
4093     return (size + 7) >> 3;
4094 }
4095 \f
4096 /* Update the data in CUM to advance over an argument
4097    of mode MODE and data type TYPE.
4098    (TYPE is null for libcalls where that information may not be available.)  */
4099
4100 void
4101 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4102                       tree type, int named)
4103 {
4104   cum->nargs_prototype--;
4105
4106   if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4107     {
4108       if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4109         {
4110           cum->vregno++;
4111           if (!TARGET_ALTIVEC)
4112             error ("Cannot pass argument in vector register because"
4113                    " altivec instructions are disabled, use -maltivec"
4114                    " to enable them.");
4115         }
4116       /* PowerPC64 Linux and AIX allocates GPRs for a vector argument
4117          even if it is going to be passed in a vector register.
4118          Darwin does the same for variable-argument functions.  */
4119       if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4120                    || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4121         {
4122           int align;
4123
4124           /* Vector parameters must be 16-byte aligned.  This places
4125              them at 2 mod 4 in terms of words in 32-bit mode, since
4126              the parameter save area starts at offset 24 from the
4127              stack.  In 64-bit mode, they just have to start on an
4128              even word, since the parameter save area is 16-byte
4129              aligned.  Space for GPRs is reserved even if the argument
4130              will be passed in memory.  */
4131           if (TARGET_32BIT)
4132             align = ((6 - (cum->words & 3)) & 3);
4133           else
4134             align = cum->words & 1;
4135           cum->words += align + rs6000_arg_size (mode, type);
4136
4137           if (TARGET_DEBUG_ARG)
4138             {
4139               fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4140                        cum->words, align);
4141               fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4142                        cum->nargs_prototype, cum->prototype,
4143                        GET_MODE_NAME (mode));
4144             }
4145         }
4146     }
4147   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4148            && !cum->stdarg
4149            && cum->sysv_gregno <= GP_ARG_MAX_REG)
4150     cum->sysv_gregno++;
4151   else if (DEFAULT_ABI == ABI_V4)
4152     {
4153       if (TARGET_HARD_FLOAT && TARGET_FPRS
4154           && (mode == SFmode || mode == DFmode))
4155         {
4156           if (cum->fregno <= FP_ARG_V4_MAX_REG)
4157             cum->fregno++;
4158           else
4159             {
4160               if (mode == DFmode)
4161                 cum->words += cum->words & 1;
4162               cum->words += rs6000_arg_size (mode, type);
4163             }
4164         }
4165       else
4166         {
4167           int n_words;
4168           int gregno = cum->sysv_gregno;
4169
4170           /* Aggregates and IEEE quad get passed by reference.  */
4171           if ((type && AGGREGATE_TYPE_P (type))
4172               || mode == TFmode)
4173             n_words = 1;
4174           else
4175             n_words = rs6000_arg_size (mode, type);
4176
4177           /* Long long and SPE vectors are put in odd registers.  */
4178           if (n_words == 2 && (gregno & 1) == 0)
4179             gregno += 1;
4180
4181           /* Long long and SPE vectors are not split between registers
4182              and stack.  */
4183           if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4184             {
4185               /* Long long is aligned on the stack.  */
4186               if (n_words == 2)
4187                 cum->words += cum->words & 1;
4188               cum->words += n_words;
4189             }
4190
4191           /* Note: continuing to accumulate gregno past when we've started
4192              spilling to the stack indicates the fact that we've started
4193              spilling to the stack to expand_builtin_saveregs.  */
4194           cum->sysv_gregno = gregno + n_words;
4195         }
4196
4197       if (TARGET_DEBUG_ARG)
4198         {
4199           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4200                    cum->words, cum->fregno);
4201           fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4202                    cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4203           fprintf (stderr, "mode = %4s, named = %d\n",
4204                    GET_MODE_NAME (mode), named);
4205         }
4206     }
4207   else
4208     {
4209       int align = (TARGET_32BIT && (cum->words & 1) != 0
4210                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4211
4212       cum->words += align + rs6000_arg_size (mode, type);
4213
4214       if (GET_MODE_CLASS (mode) == MODE_FLOAT
4215           && TARGET_HARD_FLOAT && TARGET_FPRS)
4216         cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4217
4218       if (TARGET_DEBUG_ARG)
4219         {
4220           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4221                    cum->words, cum->fregno);
4222           fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4223                    cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4224           fprintf (stderr, "named = %d, align = %d\n", named, align);
4225         }
4226     }
4227 }
4228
4229 /* Determine where to put a SIMD argument on the SPE.  */
4230
4231 static rtx
4232 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4233                          tree type)
4234 {
4235   if (cum->stdarg)
4236     {
4237       int gregno = cum->sysv_gregno;
4238       int n_words = rs6000_arg_size (mode, type);
4239
4240       /* SPE vectors are put in odd registers.  */
4241       if (n_words == 2 && (gregno & 1) == 0)
4242         gregno += 1;
4243
4244       if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4245         {
4246           rtx r1, r2;
4247           enum machine_mode m = SImode;
4248
4249           r1 = gen_rtx_REG (m, gregno);
4250           r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4251           r2 = gen_rtx_REG (m, gregno + 1);
4252           r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4253           return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4254         }
4255       else
4256         return NULL_RTX;
4257     }
4258   else
4259     {
4260       if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4261         return gen_rtx_REG (mode, cum->sysv_gregno);
4262       else
4263         return NULL_RTX;
4264     }
4265 }
4266
4267 /* Determine where to place an argument in 64-bit mode with 32-bit ABI.  */
4268
4269 static rtx
4270 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4271                            tree type, int align_words)
4272 {
4273   if (mode == DFmode)
4274     {
4275       /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4276          in vararg list into zero, one or two GPRs */
4277       if (align_words >= GP_ARG_NUM_REG)
4278         return gen_rtx_PARALLEL (DFmode,
4279                  gen_rtvec (2,
4280                             gen_rtx_EXPR_LIST (VOIDmode,
4281                                                NULL_RTX, const0_rtx),
4282                             gen_rtx_EXPR_LIST (VOIDmode,
4283                                                gen_rtx_REG (mode,
4284                                                             cum->fregno),
4285                                                const0_rtx)));
4286       else if (align_words + rs6000_arg_size (mode, type)
4287                > GP_ARG_NUM_REG)
4288         /* If this is partially on the stack, then we only
4289            include the portion actually in registers here.  */
4290         return gen_rtx_PARALLEL (DFmode,
4291                  gen_rtvec (2,
4292                             gen_rtx_EXPR_LIST (VOIDmode,
4293                                                gen_rtx_REG (SImode,
4294                                                             GP_ARG_MIN_REG
4295                                                             + align_words),
4296                                                const0_rtx),
4297                             gen_rtx_EXPR_LIST (VOIDmode,
4298                                                gen_rtx_REG (mode,
4299                                                             cum->fregno),
4300                                                const0_rtx)));
4301
4302       /* split a DFmode arg into two GPRs */
4303       return gen_rtx_PARALLEL (DFmode,
4304                gen_rtvec (3,
4305                           gen_rtx_EXPR_LIST (VOIDmode,
4306                                              gen_rtx_REG (SImode,
4307                                                           GP_ARG_MIN_REG
4308                                                           + align_words),
4309                                              const0_rtx),
4310                           gen_rtx_EXPR_LIST (VOIDmode,
4311                                              gen_rtx_REG (SImode,
4312                                                           GP_ARG_MIN_REG
4313                                                           + align_words + 1),
4314                                              GEN_INT (4)),
4315                           gen_rtx_EXPR_LIST (VOIDmode,
4316                                              gen_rtx_REG (mode, cum->fregno),
4317                                              const0_rtx)));
4318     }
4319   /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4320      or two GPRs */
4321   else if (mode == DImode)
4322     {
4323       if (align_words < GP_ARG_NUM_REG - 1)
4324         return gen_rtx_PARALLEL (DImode,
4325                  gen_rtvec (2,
4326                             gen_rtx_EXPR_LIST (VOIDmode,
4327                                                gen_rtx_REG (SImode,
4328                                                             GP_ARG_MIN_REG
4329                                                             + align_words),
4330                                                const0_rtx),
4331                             gen_rtx_EXPR_LIST (VOIDmode,
4332                                                gen_rtx_REG (SImode,
4333                                                             GP_ARG_MIN_REG
4334                                                             + align_words + 1),
4335                                                GEN_INT (4))));
4336       else if (align_words == GP_ARG_NUM_REG - 1)
4337           return gen_rtx_PARALLEL (DImode,
4338                    gen_rtvec (2,
4339                               gen_rtx_EXPR_LIST (VOIDmode,
4340                                                  NULL_RTX, const0_rtx),
4341                               gen_rtx_EXPR_LIST (VOIDmode,
4342                                                  gen_rtx_REG (SImode,
4343                                                               GP_ARG_MIN_REG
4344                                                               + align_words),
4345                                                  const0_rtx)));
4346     }
4347   else if (ALTIVEC_VECTOR_MODE (mode) && align_words == GP_ARG_NUM_REG - 2)
4348     {
4349       /* Varargs vector regs must be saved in R9-R10.  */
4350       return gen_rtx_PARALLEL (mode,
4351                                gen_rtvec (3,
4352                                  gen_rtx_EXPR_LIST (VOIDmode,
4353                                                      NULL_RTX, const0_rtx),
4354                                  gen_rtx_EXPR_LIST (VOIDmode,
4355                                                     gen_rtx_REG (SImode,
4356                                                                  GP_ARG_MIN_REG
4357                                                                  + align_words),
4358                                                     const0_rtx),
4359                                  gen_rtx_EXPR_LIST (VOIDmode,
4360                                                     gen_rtx_REG (SImode,
4361                                                                  GP_ARG_MIN_REG
4362                                                                  + align_words + 1),
4363                                                     GEN_INT (4))));
4364     }
4365   else if ((mode == BLKmode || ALTIVEC_VECTOR_MODE (mode))
4366            && align_words <= (GP_ARG_NUM_REG - 1))
4367     {
4368       /* AltiVec vector regs are saved in R5-R8. */
4369       int k;
4370       int size = int_size_in_bytes (type);
4371       int no_units = ((size - 1) / 4) + 1;
4372       int max_no_words = GP_ARG_NUM_REG - align_words;
4373       int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4374       rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4375
4376       memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4377
4378       for (k=0; k < rtlvec_len; k++)
4379         rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4380                                        gen_rtx_REG (SImode,
4381                                                     GP_ARG_MIN_REG
4382                                                     + align_words + k),
4383                                        k == 0 ? const0_rtx : GEN_INT (k*4));
4384
4385       return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rtlvec));
4386     }
4387   return NULL_RTX;
4388 }
4389
4390 /* Determine where to put an argument to a function.
4391    Value is zero to push the argument on the stack,
4392    or a hard register in which to store the argument.
4393
4394    MODE is the argument's machine mode.
4395    TYPE is the data type of the argument (as a tree).
4396     This is null for libcalls where that information may
4397     not be available.
4398    CUM is a variable of type CUMULATIVE_ARGS which gives info about
4399     the preceding args and about the function being called.
4400    NAMED is nonzero if this argument is a named parameter
4401     (otherwise it is an extra parameter matching an ellipsis).
4402
4403    On RS/6000 the first eight words of non-FP are normally in registers
4404    and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
4405    Under V.4, the first 8 FP args are in registers.
4406
4407    If this is floating-point and no prototype is specified, we use
4408    both an FP and integer register (or possibly FP reg and stack).  Library
4409    functions (when CALL_LIBCALL is set) always have the proper types for args,
4410    so we can pass the FP value just in one register.  emit_library_function
4411    doesn't support PARALLEL anyway.  */
4412
4413 struct rtx_def *
4414 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4415               tree type, int named)
4416 {
4417   enum rs6000_abi abi = DEFAULT_ABI;
4418
4419   /* Return a marker to indicate whether CR1 needs to set or clear the
4420      bit that V.4 uses to say fp args were passed in registers.
4421      Assume that we don't need the marker for software floating point,
4422      or compiler generated library calls.  */
4423   if (mode == VOIDmode)
4424     {
4425       if (abi == ABI_V4
4426           && cum->nargs_prototype < 0
4427           && (cum->call_cookie & CALL_LIBCALL) == 0
4428           && (cum->prototype || TARGET_NO_PROTOTYPE))
4429         {
4430           /* For the SPE, we need to crxor CR6 always.  */
4431           if (TARGET_SPE_ABI)
4432             return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4433           else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4434             return GEN_INT (cum->call_cookie
4435                             | ((cum->fregno == FP_ARG_MIN_REG)
4436                                ? CALL_V4_SET_FP_ARGS
4437                                : CALL_V4_CLEAR_FP_ARGS));
4438         }
4439
4440       return GEN_INT (cum->call_cookie);
4441     }
4442
4443   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4444     if (TARGET_64BIT && ! cum->prototype)
4445       {
4446        /* Vector parameters get passed in vector register
4447           and also in GPRs or memory, in absence of prototype.  */
4448        int align_words;
4449        rtx slot;
4450        align_words = (cum->words + 1) & ~1;
4451
4452        if (align_words >= GP_ARG_NUM_REG)
4453          {
4454            slot = NULL_RTX;
4455          }
4456        else
4457          {
4458            slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4459          }
4460        return gen_rtx_PARALLEL (mode,
4461                 gen_rtvec (2,
4462                            gen_rtx_EXPR_LIST (VOIDmode,
4463                                               slot, const0_rtx),
4464                            gen_rtx_EXPR_LIST (VOIDmode,
4465                                               gen_rtx_REG (mode, cum->vregno),
4466                                               const0_rtx)));
4467       }
4468     else
4469       return gen_rtx_REG (mode, cum->vregno);
4470   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4471     {
4472       if (named || abi == ABI_V4)
4473         return NULL_RTX;
4474       else
4475         {
4476           /* Vector parameters to varargs functions under AIX or Darwin
4477              get passed in memory and possibly also in GPRs.  */
4478           int align, align_words;
4479           enum machine_mode part_mode = mode;
4480
4481           /* Vector parameters must be 16-byte aligned.  This places them at
4482              2 mod 4 in terms of words in 32-bit mode, since the parameter
4483              save area starts at offset 24 from the stack.  In 64-bit mode,
4484              they just have to start on an even word, since the parameter
4485              save area is 16-byte aligned.  */
4486           if (TARGET_32BIT)
4487             align = ((6 - (cum->words & 3)) & 3);
4488           else
4489             align = cum->words & 1;
4490           align_words = cum->words + align;
4491
4492           /* Out of registers?  Memory, then.  */
4493           if (align_words >= GP_ARG_NUM_REG)
4494             return NULL_RTX;
4495
4496           /* The vector value goes in GPRs.  Only the part of the
4497              value in GPRs is reported here.  */
4498           if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4499               > GP_ARG_NUM_REG)
4500             /* Fortunately, there are only two possibilities, the value
4501                is either wholly in GPRs or half in GPRs and half not.  */
4502             part_mode = DImode;
4503
4504           if (TARGET_32BIT
4505               && (TARGET_POWERPC64 || (align_words == GP_ARG_NUM_REG - 2)))
4506             return rs6000_mixed_function_arg (cum, part_mode, type, align_words);
4507           else
4508             return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4509         }
4510     }
4511   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4512     return rs6000_spe_function_arg (cum, mode, type);
4513   else if (abi == ABI_V4)
4514     {
4515       if (TARGET_HARD_FLOAT && TARGET_FPRS
4516           && (mode == SFmode || mode == DFmode))
4517         {
4518           if (cum->fregno <= FP_ARG_V4_MAX_REG)
4519             return gen_rtx_REG (mode, cum->fregno);
4520           else
4521             return NULL_RTX;
4522         }
4523       else
4524         {
4525           int n_words;
4526           int gregno = cum->sysv_gregno;
4527
4528           /* Aggregates and IEEE quad get passed by reference.  */
4529           if ((type && AGGREGATE_TYPE_P (type))
4530               || mode == TFmode)
4531             n_words = 1;
4532           else
4533             n_words = rs6000_arg_size (mode, type);
4534
4535           /* Long long and SPE vectors are put in odd registers.  */
4536           if (n_words == 2 && (gregno & 1) == 0)
4537             gregno += 1;
4538
4539           /* Long long does not split between registers and stack.  */
4540           if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4541             return gen_rtx_REG (mode, gregno);
4542           else
4543             return NULL_RTX;
4544         }
4545     }
4546   else
4547     {
4548       int align = (TARGET_32BIT && (cum->words & 1) != 0
4549                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4550       int align_words = cum->words + align;
4551
4552       if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4553         return NULL_RTX;
4554
4555       if (TARGET_32BIT && TARGET_POWERPC64
4556           && (mode == DImode || mode == BLKmode))
4557         return rs6000_mixed_function_arg (cum, mode, type, align_words);
4558
4559       if (USE_FP_FOR_ARG_P (cum, mode, type))
4560         {
4561           rtx fpr[2];
4562           rtx *r;
4563           bool needs_psave;
4564           enum machine_mode fmode = mode;
4565           int n;
4566           unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4567
4568           if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4569             {
4570               /* Long double split over regs and memory.  */
4571               if (fmode == TFmode)
4572                 fmode = DFmode;
4573
4574               /* Currently, we only ever need one reg here because complex
4575                  doubles are split.  */
4576               if (cum->fregno != FP_ARG_MAX_REG - 1)
4577                 abort ();
4578             }
4579           fpr[1] = gen_rtx_REG (fmode, cum->fregno);
4580
4581           /* Do we also need to pass this arg in the parameter save
4582              area?  */
4583           needs_psave = (type
4584                          && (cum->nargs_prototype <= 0
4585                              || (DEFAULT_ABI == ABI_AIX
4586                                  && TARGET_XL_CALL
4587                                  && align_words >= GP_ARG_NUM_REG)));
4588
4589           if (!needs_psave && mode == fmode)
4590             return fpr[1];
4591
4592           if (TARGET_32BIT && TARGET_POWERPC64
4593               && mode == DFmode && cum->stdarg)
4594             return rs6000_mixed_function_arg (cum, mode, type, align_words);
4595
4596           /* Describe where this piece goes.  */
4597           r = fpr + 1;
4598           *r = gen_rtx_EXPR_LIST (VOIDmode, *r, const0_rtx);
4599           n = 1;
4600
4601           if (needs_psave)
4602             {
4603               /* Now describe the part that goes in gprs or the stack.
4604                  This piece must come first, before the fprs.  */
4605               rtx reg = NULL_RTX;
4606               if (align_words < GP_ARG_NUM_REG)
4607                 {
4608                   unsigned long n_words = rs6000_arg_size (mode, type);
4609                   enum machine_mode rmode = mode;
4610
4611                   if (align_words + n_words > GP_ARG_NUM_REG)
4612                     /* If this is partially on the stack, then we only
4613                        include the portion actually in registers here.
4614                        We know this can only be one register because
4615                        complex doubles are splt.  */
4616                     rmode = Pmode;
4617                   reg = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
4618                 }
4619               *--r = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4620               ++n;
4621             }
4622
4623           return gen_rtx_PARALLEL (mode, gen_rtvec_v (n, r));
4624         }
4625       else if (align_words < GP_ARG_NUM_REG)
4626         return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4627       else
4628         return NULL_RTX;
4629     }
4630 }
4631 \f
4632 /* For an arg passed partly in registers and partly in memory,
4633    this is the number of registers used.
4634    For args passed entirely in registers or entirely in memory, zero.  */
4635
4636 int
4637 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4638                             tree type, int named)
4639 {
4640   int ret = 0;
4641
4642   if (DEFAULT_ABI == ABI_V4)
4643     return 0;
4644
4645   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4646       && cum->nargs_prototype >= 0)
4647     return 0;
4648
4649   if (USE_FP_FOR_ARG_P (cum, mode, type))
4650     {
4651       if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4652         ret = FP_ARG_MAX_REG - cum->fregno;
4653       else if (cum->nargs_prototype >= 0)
4654         return 0;
4655     }
4656
4657   if (cum->words < GP_ARG_NUM_REG
4658       && GP_ARG_NUM_REG < cum->words + rs6000_arg_size (mode, type))
4659     ret = GP_ARG_NUM_REG - cum->words;
4660
4661   if (ret != 0 && TARGET_DEBUG_ARG)
4662     fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4663
4664   return ret;
4665 }
4666 \f
4667 /* A C expression that indicates when an argument must be passed by
4668    reference.  If nonzero for an argument, a copy of that argument is
4669    made in memory and a pointer to the argument is passed instead of
4670    the argument itself.  The pointer is passed in whatever way is
4671    appropriate for passing a pointer to that type.
4672
4673    Under V.4, structures and unions are passed by reference.
4674
4675    As an extension to all ABIs, variable sized types are passed by
4676    reference.  */
4677
4678 int
4679 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4680                                 enum machine_mode mode ATTRIBUTE_UNUSED,
4681                                 tree type, int named ATTRIBUTE_UNUSED)
4682 {
4683   if (DEFAULT_ABI == ABI_V4
4684       && ((type && AGGREGATE_TYPE_P (type))
4685           || mode == TFmode))
4686     {
4687       if (TARGET_DEBUG_ARG)
4688         fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4689
4690       return 1;
4691     }
4692   return type && int_size_in_bytes (type) < 0;
4693 }
4694
4695 static void
4696 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
4697 {
4698   int i;
4699   enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4700
4701   if (nregs == 0)
4702     return;
4703
4704     for (i = 0; i < nregs; i++)
4705     {
4706       rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4707       if (reload_completed)
4708       {
4709         if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4710           tem = NULL_RTX;
4711         else
4712           tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4713                                      i * GET_MODE_SIZE(reg_mode));
4714       }
4715       else
4716         tem = replace_equiv_address (tem, XEXP (tem, 0));
4717
4718       if (tem == NULL_RTX)
4719         abort ();
4720
4721       emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4722     }
4723 }
4724
4725 \f
4726 /* Perform any needed actions needed for a function that is receiving a
4727    variable number of arguments.
4728
4729    CUM is as above.
4730
4731    MODE and TYPE are the mode and type of the current parameter.
4732
4733    PRETEND_SIZE is a variable that should be set to the amount of stack
4734    that must be pushed by the prolog to pretend that our caller pushed
4735    it.
4736
4737    Normally, this macro will push all remaining incoming registers on the
4738    stack and set PRETEND_SIZE to the length of the registers pushed.  */
4739
4740 static void
4741 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4742                 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4743 {
4744   CUMULATIVE_ARGS next_cum;
4745   int reg_size = TARGET_32BIT ? 4 : 8;
4746   rtx save_area = NULL_RTX, mem;
4747   int first_reg_offset, set;
4748
4749   /* Skip the last named argument.  */
4750   next_cum = *cum;
4751   function_arg_advance (&next_cum, mode, type, 1);
4752
4753   if (DEFAULT_ABI == ABI_V4)
4754     {
4755       /* Indicate to allocate space on the stack for varargs save area.  */
4756       cfun->machine->sysv_varargs_p = 1;
4757       if (! no_rtl)
4758         save_area = plus_constant (virtual_stack_vars_rtx,
4759                                    - RS6000_VARARGS_SIZE);
4760
4761       first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4762     }
4763   else
4764     {
4765       first_reg_offset = next_cum.words;
4766       save_area = virtual_incoming_args_rtx;
4767       cfun->machine->sysv_varargs_p = 0;
4768
4769       if (MUST_PASS_IN_STACK (mode, type))
4770         first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4771     }
4772
4773   set = get_varargs_alias_set ();
4774   if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4775     {
4776       mem = gen_rtx_MEM (BLKmode,
4777                          plus_constant (save_area,
4778                                         first_reg_offset * reg_size)),
4779       set_mem_alias_set (mem, set);
4780       set_mem_align (mem, BITS_PER_WORD);
4781
4782       rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4783                                   GP_ARG_NUM_REG - first_reg_offset);
4784     }
4785
4786   /* Save FP registers if needed.  */
4787   if (DEFAULT_ABI == ABI_V4
4788       && TARGET_HARD_FLOAT && TARGET_FPRS
4789       && ! no_rtl
4790       && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4791     {
4792       int fregno = next_cum.fregno;
4793       rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4794       rtx lab = gen_label_rtx ();
4795       int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4796
4797       emit_jump_insn (gen_rtx_SET (VOIDmode,
4798                                    pc_rtx,
4799                                    gen_rtx_IF_THEN_ELSE (VOIDmode,
4800                                             gen_rtx_NE (VOIDmode, cr1,
4801                                                         const0_rtx),
4802                                             gen_rtx_LABEL_REF (VOIDmode, lab),
4803                                             pc_rtx)));
4804
4805       while (fregno <= FP_ARG_V4_MAX_REG)
4806         {
4807           mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4808           set_mem_alias_set (mem, set);
4809           emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4810           fregno++;
4811           off += 8;
4812         }
4813
4814       emit_label (lab);
4815     }
4816 }
4817
4818 /* Create the va_list data type.  */
4819
4820 static tree
4821 rs6000_build_builtin_va_list (void)
4822 {
4823   tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4824
4825   /* For AIX, prefer 'char *' because that's what the system
4826      header files like.  */
4827   if (DEFAULT_ABI != ABI_V4)
4828     return build_pointer_type (char_type_node);
4829
4830   record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4831   type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4832
4833   f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4834                       unsigned_char_type_node);
4835   f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4836                       unsigned_char_type_node);
4837   /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4838      every user file.  */
4839   f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4840                       short_unsigned_type_node);
4841   f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4842                       ptr_type_node);
4843   f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4844                       ptr_type_node);
4845
4846   DECL_FIELD_CONTEXT (f_gpr) = record;
4847   DECL_FIELD_CONTEXT (f_fpr) = record;
4848   DECL_FIELD_CONTEXT (f_res) = record;
4849   DECL_FIELD_CONTEXT (f_ovf) = record;
4850   DECL_FIELD_CONTEXT (f_sav) = record;
4851
4852   TREE_CHAIN (record) = type_decl;
4853   TYPE_NAME (record) = type_decl;
4854   TYPE_FIELDS (record) = f_gpr;
4855   TREE_CHAIN (f_gpr) = f_fpr;
4856   TREE_CHAIN (f_fpr) = f_res;
4857   TREE_CHAIN (f_res) = f_ovf;
4858   TREE_CHAIN (f_ovf) = f_sav;
4859
4860   layout_type (record);
4861
4862   /* The correct type is an array type of one element.  */
4863   return build_array_type (record, build_index_type (size_zero_node));
4864 }
4865
4866 /* Implement va_start.  */
4867
4868 void
4869 rs6000_va_start (tree valist, rtx nextarg)
4870 {
4871   HOST_WIDE_INT words, n_gpr, n_fpr;
4872   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4873   tree gpr, fpr, ovf, sav, t;
4874
4875   /* Only SVR4 needs something special.  */
4876   if (DEFAULT_ABI != ABI_V4)
4877     {
4878       std_expand_builtin_va_start (valist, nextarg);
4879       return;
4880     }
4881
4882   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4883   f_fpr = TREE_CHAIN (f_gpr);
4884   f_res = TREE_CHAIN (f_fpr);
4885   f_ovf = TREE_CHAIN (f_res);
4886   f_sav = TREE_CHAIN (f_ovf);
4887
4888   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4889   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4890   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4891   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4892   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4893
4894   /* Count number of gp and fp argument registers used.  */
4895   words = current_function_args_info.words;
4896   n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4897   n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4898
4899   if (TARGET_DEBUG_ARG)
4900     fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4901              HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4902              words, n_gpr, n_fpr);
4903
4904   t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4905   TREE_SIDE_EFFECTS (t) = 1;
4906   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4907
4908   t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4909   TREE_SIDE_EFFECTS (t) = 1;
4910   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4911
4912   /* Find the overflow area.  */
4913   t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4914   if (words != 0)
4915     t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4916                build_int_2 (words * UNITS_PER_WORD, 0));
4917   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4918   TREE_SIDE_EFFECTS (t) = 1;
4919   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4920
4921   /* Find the register save area.  */
4922   t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4923   t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4924              build_int_2 (-RS6000_VARARGS_SIZE, -1));
4925   t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4926   TREE_SIDE_EFFECTS (t) = 1;
4927   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4928 }
4929
4930 /* Implement va_arg.  */
4931
4932 rtx
4933 rs6000_va_arg (tree valist, tree type)
4934 {
4935   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4936   tree gpr, fpr, ovf, sav, reg, t, u;
4937   int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4938   rtx lab_false, lab_over, addr_rtx, r;
4939
4940   if (DEFAULT_ABI != ABI_V4)
4941     {
4942       /* Variable sized types are passed by reference.  */
4943       if (int_size_in_bytes (type) < 0)
4944         {
4945           u = build_pointer_type (type);
4946
4947           /* Args grow upward.  */
4948           t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4949                      build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4950           TREE_SIDE_EFFECTS (t) = 1;
4951
4952           t = build1 (NOP_EXPR, build_pointer_type (u), t);
4953           TREE_SIDE_EFFECTS (t) = 1;
4954
4955           t = build1 (INDIRECT_REF, u, t);
4956           TREE_SIDE_EFFECTS (t) = 1;
4957
4958           return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4959         }
4960       if (targetm.calls.split_complex_arg
4961           && TREE_CODE (type) == COMPLEX_TYPE)
4962         {
4963           tree elem_type = TREE_TYPE (type);
4964           enum machine_mode elem_mode = TYPE_MODE (elem_type);
4965           int elem_size = GET_MODE_SIZE (elem_mode);
4966
4967           if (elem_size < UNITS_PER_WORD)
4968             {
4969               rtx real_part, imag_part, dest_real, rr;
4970
4971               real_part = rs6000_va_arg (valist, elem_type);
4972               imag_part = rs6000_va_arg (valist, elem_type);
4973
4974               /* We're not returning the value here, but the address.
4975                  real_part and imag_part are not contiguous, and we know
4976                  there is space available to pack real_part next to
4977                  imag_part.  float _Complex is not promoted to
4978                  double _Complex by the default promotion rules that
4979                  promote float to double.  */
4980               if (2 * elem_size > UNITS_PER_WORD)
4981                 abort ();
4982
4983               real_part = gen_rtx_MEM (elem_mode, real_part);
4984               imag_part = gen_rtx_MEM (elem_mode, imag_part);
4985
4986               dest_real = adjust_address (imag_part, elem_mode, -elem_size);
4987               rr = gen_reg_rtx (elem_mode);
4988               emit_move_insn (rr, real_part);
4989               emit_move_insn (dest_real, rr);
4990
4991               return XEXP (dest_real, 0);
4992             }
4993         }
4994
4995       return std_expand_builtin_va_arg (valist, type);
4996     }
4997
4998   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4999   f_fpr = TREE_CHAIN (f_gpr);
5000   f_res = TREE_CHAIN (f_fpr);
5001   f_ovf = TREE_CHAIN (f_res);
5002   f_sav = TREE_CHAIN (f_ovf);
5003
5004   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5005   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
5006   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
5007   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
5008   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
5009
5010   size = int_size_in_bytes (type);
5011   rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5012
5013   if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
5014     {
5015       /* Aggregates and long doubles are passed by reference.  */
5016       indirect_p = 1;
5017       reg = gpr;
5018       n_reg = 1;
5019       sav_ofs = 0;
5020       sav_scale = 4;
5021       size = UNITS_PER_WORD;
5022       rsize = 1;
5023     }
5024   else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
5025     {
5026       /* FP args go in FP registers, if present.  */
5027       indirect_p = 0;
5028       reg = fpr;
5029       n_reg = 1;
5030       sav_ofs = 8*4;
5031       sav_scale = 8;
5032     }
5033   else
5034     {
5035       /* Otherwise into GP registers.  */
5036       indirect_p = 0;
5037       reg = gpr;
5038       n_reg = rsize;
5039       sav_ofs = 0;
5040       sav_scale = 4;
5041     }
5042
5043   /* Pull the value out of the saved registers....  */
5044
5045   lab_false = gen_label_rtx ();
5046   lab_over = gen_label_rtx ();
5047   addr_rtx = gen_reg_rtx (Pmode);
5048
5049   /*  AltiVec vectors never go in registers.  */
5050   if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
5051     {
5052       TREE_THIS_VOLATILE (reg) = 1;
5053       emit_cmp_and_jump_insns
5054         (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
5055          GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
5056          lab_false);
5057
5058       /* Long long is aligned in the registers.  */
5059       if (n_reg > 1)
5060         {
5061           u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5062                      build_int_2 (n_reg - 1, 0));
5063           u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
5064           u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
5065           TREE_SIDE_EFFECTS (u) = 1;
5066           expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
5067         }
5068
5069       if (sav_ofs)
5070         t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
5071       else
5072         t = sav;
5073
5074       u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
5075                  build_int_2 (n_reg, 0));
5076       TREE_SIDE_EFFECTS (u) = 1;
5077
5078       u = build1 (CONVERT_EXPR, integer_type_node, u);
5079       TREE_SIDE_EFFECTS (u) = 1;
5080
5081       u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
5082       TREE_SIDE_EFFECTS (u) = 1;
5083
5084       t = build (PLUS_EXPR, ptr_type_node, t, u);
5085       TREE_SIDE_EFFECTS (t) = 1;
5086
5087       r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5088       if (r != addr_rtx)
5089         emit_move_insn (addr_rtx, r);
5090
5091       emit_jump_insn (gen_jump (lab_over));
5092       emit_barrier ();
5093     }
5094
5095   emit_label (lab_false);
5096
5097   /* ... otherwise out of the overflow area.  */
5098
5099   /* Make sure we don't find reg 7 for the next int arg.
5100
5101      All AltiVec vectors go in the overflow area.  So in the AltiVec
5102      case we need to get the vectors from the overflow area, but
5103      remember where the GPRs and FPRs are.  */
5104   if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
5105                     || !TARGET_ALTIVEC))
5106     {
5107       t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
5108       TREE_SIDE_EFFECTS (t) = 1;
5109       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5110     }
5111
5112   /* Care for on-stack alignment if needed.  */
5113   if (rsize <= 1)
5114     t = ovf;
5115   else
5116     {
5117       int align;
5118
5119       /* AltiVec vectors are 16 byte aligned.  */
5120       if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
5121         align = 15;
5122       else
5123         align = 7;
5124
5125       t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
5126       t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
5127     }
5128   t = save_expr (t);
5129
5130   r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5131   if (r != addr_rtx)
5132     emit_move_insn (addr_rtx, r);
5133
5134   t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
5135   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5136   TREE_SIDE_EFFECTS (t) = 1;
5137   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5138
5139   emit_label (lab_over);
5140
5141   if (indirect_p)
5142     {
5143       r = gen_rtx_MEM (Pmode, addr_rtx);
5144       set_mem_alias_set (r, get_varargs_alias_set ());
5145       emit_move_insn (addr_rtx, r);
5146     }
5147
5148   return addr_rtx;
5149 }
5150
5151 /* Builtins.  */
5152
5153 #define def_builtin(MASK, NAME, TYPE, CODE)                     \
5154 do {                                                            \
5155   if ((MASK) & target_flags)                                    \
5156     builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD,      \
5157                       NULL, NULL_TREE);                         \
5158 } while (0)
5159
5160 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */
5161
5162 static const struct builtin_description bdesc_3arg[] =
5163 {
5164   { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5165   { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5166   { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5167   { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5168   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5169   { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5170   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5171   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5172   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5173   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5174   { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5175   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5176   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5177   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5178   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5179   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5180   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5181   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5182   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5183   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5184   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5185   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5186   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5187 };
5188
5189 /* DST operations: void foo (void *, const int, const char).  */
5190
5191 static const struct builtin_description bdesc_dst[] =
5192 {
5193   { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5194   { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5195   { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5196   { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5197 };
5198
5199 /* Simple binary operations: VECc = foo (VECa, VECb).  */
5200
5201 static struct builtin_description bdesc_2arg[] =
5202 {
5203   { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5204   { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5205   { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5206   { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5207   { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5208   { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5209   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5210   { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5211   { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5212   { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5213   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5214   { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5215   { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5216   { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5217   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5218   { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5219   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5220   { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5221   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5222   { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5223   { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5224   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5225   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5226   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5227   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5228   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5229   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5230   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5231   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5232   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5233   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5234   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5235   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5236   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5237   { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5238   { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5239   { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5240   { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5241   { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5242   { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5243   { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5244   { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5245   { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5246   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5247   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5248   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5249   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5250   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5251   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5252   { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5253   { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5254   { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5255   { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5256   { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5257   { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5258   { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5259   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5260   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5261   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5262   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5263   { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5264   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5265   { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5266   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5267   { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5268   { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5269   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5270   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5271   { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5272   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5273   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5274   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5275   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5276   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5277   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5278   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5279   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5280   { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5281   { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5282   { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5283   { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5284   { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5285   { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5286   { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5287   { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5288   { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5289   { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5290   { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5291   { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5292   { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5293   { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5294   { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5295   { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5296   { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5297   { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5298   { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5299   { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5300   { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5301   { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5302   { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5303   { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5304   { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5305   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5306   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5307   { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5308   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5309   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5310   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5311   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5312   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5313   { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5314   { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5315   { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5316
5317   /* Place holder, leave as first spe builtin.  */
5318   { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5319   { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5320   { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5321   { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5322   { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5323   { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5324   { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5325   { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5326   { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5327   { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5328   { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5329   { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5330   { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5331   { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5332   { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5333   { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5334   { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5335   { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5336   { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5337   { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5338   { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5339   { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5340   { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5341   { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5342   { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5343   { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5344   { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5345   { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5346   { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5347   { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5348   { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5349   { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5350   { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5351   { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5352   { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5353   { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5354   { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5355   { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5356   { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5357   { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5358   { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5359   { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5360   { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5361   { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5362   { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5363   { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5364   { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5365   { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5366   { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5367   { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5368   { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5369   { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5370   { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5371   { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5372   { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5373   { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5374   { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5375   { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5376   { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5377   { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5378   { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5379   { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5380   { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5381   { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5382   { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5383   { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5384   { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5385   { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5386   { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5387   { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5388   { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5389   { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5390   { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5391   { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5392   { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5393   { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5394   { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5395   { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5396   { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5397   { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5398   { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5399   { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5400   { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5401   { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5402   { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5403   { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5404   { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5405   { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5406   { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5407   { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5408   { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5409   { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5410   { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5411   { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5412   { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5413   { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5414   { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5415   { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5416   { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5417   { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5418   { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5419   { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5420   { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5421   { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5422   { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5423   { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5424   { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5425   { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5426   { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5427
5428   /* SPE binary operations expecting a 5-bit unsigned literal.  */
5429   { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5430
5431   { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5432   { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5433   { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5434   { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5435   { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5436   { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5437   { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5438   { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5439   { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5440   { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5441   { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5442   { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5443   { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5444   { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5445   { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5446   { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5447   { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5448   { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5449   { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5450   { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5451   { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5452   { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5453   { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5454   { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5455   { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5456   { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5457
5458   /* Place-holder.  Leave as last binary SPE builtin.  */
5459   { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5460 };
5461
5462 /* AltiVec predicates.  */
5463
5464 struct builtin_description_predicates
5465 {
5466   const unsigned int mask;
5467   const enum insn_code icode;
5468   const char *opcode;
5469   const char *const name;
5470   const enum rs6000_builtins code;
5471 };
5472
5473 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5474 {
5475   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5476   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5477   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5478   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5479   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5480   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5481   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5482   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5483   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5484   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5485   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5486   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5487   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5488 };
5489
5490 /* SPE predicates.  */
5491 static struct builtin_description bdesc_spe_predicates[] =
5492 {
5493   /* Place-holder.  Leave as first.  */
5494   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5495   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5496   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5497   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5498   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5499   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5500   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5501   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5502   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5503   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5504   /* Place-holder.  Leave as last.  */
5505   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5506 };
5507
5508 /* SPE evsel predicates.  */
5509 static struct builtin_description bdesc_spe_evsel[] =
5510 {
5511   /* Place-holder.  Leave as first.  */
5512   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5513   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5514   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5515   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5516   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5517   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5518   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5519   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5520   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5521   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5522   /* Place-holder.  Leave as last.  */
5523   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5524 };
5525
5526 /* ABS* operations.  */
5527
5528 static const struct builtin_description bdesc_abs[] =
5529 {
5530   { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5531   { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5532   { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5533   { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5534   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5535   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5536   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5537 };
5538
5539 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5540    foo (VECa).  */
5541
5542 static struct builtin_description bdesc_1arg[] =
5543 {
5544   { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5545   { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5546   { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5547   { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5548   { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5549   { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5550   { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5551   { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5552   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5553   { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5554   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5555   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5556   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5557   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5558   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5559   { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5560   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5561
5562   /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5563      end with SPE_BUILTIN_EVSUBFUSIAAW.  */
5564   { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5565   { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5566   { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5567   { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5568   { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5569   { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5570   { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5571   { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5572   { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5573   { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5574   { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5575   { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5576   { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5577   { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5578   { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5579   { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5580   { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5581   { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5582   { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5583   { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5584   { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5585   { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5586   { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5587   { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5588   { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5589   { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5590   { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5591   { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5592
5593   /* Place-holder.  Leave as last unary SPE builtin.  */
5594   { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5595 };
5596
5597 static rtx
5598 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5599 {
5600   rtx pat;
5601   tree arg0 = TREE_VALUE (arglist);
5602   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5603   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5604   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5605
5606   if (icode == CODE_FOR_nothing)
5607     /* Builtin not supported on this processor.  */
5608     return 0;
5609
5610   /* If we got invalid arguments bail out before generating bad rtl.  */
5611   if (arg0 == error_mark_node)
5612     return const0_rtx;
5613
5614   if (icode == CODE_FOR_altivec_vspltisb
5615       || icode == CODE_FOR_altivec_vspltish
5616       || icode == CODE_FOR_altivec_vspltisw
5617       || icode == CODE_FOR_spe_evsplatfi
5618       || icode == CODE_FOR_spe_evsplati)
5619     {
5620       /* Only allow 5-bit *signed* literals.  */
5621       if (GET_CODE (op0) != CONST_INT
5622           || INTVAL (op0) > 0x1f
5623           || INTVAL (op0) < -0x1f)
5624         {
5625           error ("argument 1 must be a 5-bit signed literal");
5626           return const0_rtx;
5627         }
5628     }
5629
5630   if (target == 0
5631       || GET_MODE (target) != tmode
5632       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5633     target = gen_reg_rtx (tmode);
5634
5635   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5636     op0 = copy_to_mode_reg (mode0, op0);
5637
5638   pat = GEN_FCN (icode) (target, op0);
5639   if (! pat)
5640     return 0;
5641   emit_insn (pat);
5642
5643   return target;
5644 }
5645
5646 static rtx
5647 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5648 {
5649   rtx pat, scratch1, scratch2;
5650   tree arg0 = TREE_VALUE (arglist);
5651   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5652   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5653   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5654
5655   /* If we have invalid arguments, bail out before generating bad rtl.  */
5656   if (arg0 == error_mark_node)
5657     return const0_rtx;
5658
5659   if (target == 0
5660       || GET_MODE (target) != tmode
5661       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5662     target = gen_reg_rtx (tmode);
5663
5664   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5665     op0 = copy_to_mode_reg (mode0, op0);
5666
5667   scratch1 = gen_reg_rtx (mode0);
5668   scratch2 = gen_reg_rtx (mode0);
5669
5670   pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5671   if (! pat)
5672     return 0;
5673   emit_insn (pat);
5674
5675   return target;
5676 }
5677
5678 static rtx
5679 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5680 {
5681   rtx pat;
5682   tree arg0 = TREE_VALUE (arglist);
5683   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5684   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5685   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5686   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5687   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5688   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5689
5690   if (icode == CODE_FOR_nothing)
5691     /* Builtin not supported on this processor.  */
5692     return 0;
5693
5694   /* If we got invalid arguments bail out before generating bad rtl.  */
5695   if (arg0 == error_mark_node || arg1 == error_mark_node)
5696     return const0_rtx;
5697
5698   if (icode == CODE_FOR_altivec_vcfux
5699       || icode == CODE_FOR_altivec_vcfsx
5700       || icode == CODE_FOR_altivec_vctsxs
5701       || icode == CODE_FOR_altivec_vctuxs
5702       || icode == CODE_FOR_altivec_vspltb
5703       || icode == CODE_FOR_altivec_vsplth
5704       || icode == CODE_FOR_altivec_vspltw
5705       || icode == CODE_FOR_spe_evaddiw
5706       || icode == CODE_FOR_spe_evldd
5707       || icode == CODE_FOR_spe_evldh
5708       || icode == CODE_FOR_spe_evldw
5709       || icode == CODE_FOR_spe_evlhhesplat
5710       || icode == CODE_FOR_spe_evlhhossplat
5711       || icode == CODE_FOR_spe_evlhhousplat
5712       || icode == CODE_FOR_spe_evlwhe
5713       || icode == CODE_FOR_spe_evlwhos
5714       || icode == CODE_FOR_spe_evlwhou
5715       || icode == CODE_FOR_spe_evlwhsplat
5716       || icode == CODE_FOR_spe_evlwwsplat
5717       || icode == CODE_FOR_spe_evrlwi
5718       || icode == CODE_FOR_spe_evslwi
5719       || icode == CODE_FOR_spe_evsrwis
5720       || icode == CODE_FOR_spe_evsubifw
5721       || icode == CODE_FOR_spe_evsrwiu)
5722     {
5723       /* Only allow 5-bit unsigned literals.  */
5724       STRIP_NOPS (arg1);
5725       if (TREE_CODE (arg1) != INTEGER_CST
5726           || TREE_INT_CST_LOW (arg1) & ~0x1f)
5727         {
5728           error ("argument 2 must be a 5-bit unsigned literal");
5729           return const0_rtx;
5730         }
5731     }
5732
5733   if (target == 0
5734       || GET_MODE (target) != tmode
5735       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5736     target = gen_reg_rtx (tmode);
5737
5738   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5739     op0 = copy_to_mode_reg (mode0, op0);
5740   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5741     op1 = copy_to_mode_reg (mode1, op1);
5742
5743   pat = GEN_FCN (icode) (target, op0, op1);
5744   if (! pat)
5745     return 0;
5746   emit_insn (pat);
5747
5748   return target;
5749 }
5750
5751 static rtx
5752 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5753                                   tree arglist, rtx target)
5754 {
5755   rtx pat, scratch;
5756   tree cr6_form = TREE_VALUE (arglist);
5757   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5758   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5759   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5760   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5761   enum machine_mode tmode = SImode;
5762   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5763   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5764   int cr6_form_int;
5765
5766   if (TREE_CODE (cr6_form) != INTEGER_CST)
5767     {
5768       error ("argument 1 of __builtin_altivec_predicate must be a constant");
5769       return const0_rtx;
5770     }
5771   else
5772     cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5773
5774   if (mode0 != mode1)
5775     abort ();
5776
5777   /* If we have invalid arguments, bail out before generating bad rtl.  */
5778   if (arg0 == error_mark_node || arg1 == error_mark_node)
5779     return const0_rtx;
5780
5781   if (target == 0
5782       || GET_MODE (target) != tmode
5783       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5784     target = gen_reg_rtx (tmode);
5785
5786   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5787     op0 = copy_to_mode_reg (mode0, op0);
5788   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5789     op1 = copy_to_mode_reg (mode1, op1);
5790
5791   scratch = gen_reg_rtx (mode0);
5792
5793   pat = GEN_FCN (icode) (scratch, op0, op1,
5794                          gen_rtx_SYMBOL_REF (Pmode, opcode));
5795   if (! pat)
5796     return 0;
5797   emit_insn (pat);
5798
5799   /* The vec_any* and vec_all* predicates use the same opcodes for two
5800      different operations, but the bits in CR6 will be different
5801      depending on what information we want.  So we have to play tricks
5802      with CR6 to get the right bits out.
5803
5804      If you think this is disgusting, look at the specs for the
5805      AltiVec predicates.  */
5806
5807      switch (cr6_form_int)
5808        {
5809        case 0:
5810          emit_insn (gen_cr6_test_for_zero (target));
5811          break;
5812        case 1:
5813          emit_insn (gen_cr6_test_for_zero_reverse (target));
5814          break;
5815        case 2:
5816          emit_insn (gen_cr6_test_for_lt (target));
5817          break;
5818        case 3:
5819          emit_insn (gen_cr6_test_for_lt_reverse (target));
5820          break;
5821        default:
5822          error ("argument 1 of __builtin_altivec_predicate is out of range");
5823          break;
5824        }
5825
5826   return target;
5827 }
5828
5829 static rtx
5830 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5831 {
5832   rtx pat, addr;
5833   tree arg0 = TREE_VALUE (arglist);
5834   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5835   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5836   enum machine_mode mode0 = Pmode;
5837   enum machine_mode mode1 = Pmode;
5838   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5839   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5840
5841   if (icode == CODE_FOR_nothing)
5842     /* Builtin not supported on this processor.  */
5843     return 0;
5844
5845   /* If we got invalid arguments bail out before generating bad rtl.  */
5846   if (arg0 == error_mark_node || arg1 == error_mark_node)
5847     return const0_rtx;
5848
5849   if (target == 0
5850       || GET_MODE (target) != tmode
5851       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5852     target = gen_reg_rtx (tmode);
5853
5854   op1 = copy_to_mode_reg (mode1, op1);
5855
5856   if (op0 == const0_rtx)
5857     {
5858       addr = gen_rtx_MEM (tmode, op1);
5859     }
5860   else
5861     {
5862       op0 = copy_to_mode_reg (mode0, op0);
5863       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5864     }
5865
5866   pat = GEN_FCN (icode) (target, addr);
5867
5868   if (! pat)
5869     return 0;
5870   emit_insn (pat);
5871
5872   return target;
5873 }
5874
5875 static rtx
5876 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5877 {
5878   tree arg0 = TREE_VALUE (arglist);
5879   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5880   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5881   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5882   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5883   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5884   rtx pat, addr;
5885   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5886   enum machine_mode mode1 = Pmode;
5887   enum machine_mode mode2 = Pmode;
5888
5889   /* Invalid arguments.  Bail before doing anything stoopid!  */
5890   if (arg0 == error_mark_node
5891       || arg1 == error_mark_node
5892       || arg2 == error_mark_node)
5893     return const0_rtx;
5894
5895   if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5896     op0 = copy_to_mode_reg (tmode, op0);
5897
5898   op2 = copy_to_mode_reg (mode2, op2);
5899
5900   if (op1 == const0_rtx)
5901     {
5902       addr = gen_rtx_MEM (tmode, op2);
5903     }
5904   else
5905     {
5906       op1 = copy_to_mode_reg (mode1, op1);
5907       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5908     }
5909
5910   pat = GEN_FCN (icode) (addr, op0);
5911   if (pat)
5912     emit_insn (pat);
5913   return NULL_RTX;
5914 }
5915
5916 static rtx
5917 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5918 {
5919   rtx pat;
5920   tree arg0 = TREE_VALUE (arglist);
5921   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5922   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5923   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5924   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5925   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5926   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5927   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5928   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5929   enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5930
5931   if (icode == CODE_FOR_nothing)
5932     /* Builtin not supported on this processor.  */
5933     return 0;
5934
5935   /* If we got invalid arguments bail out before generating bad rtl.  */
5936   if (arg0 == error_mark_node
5937       || arg1 == error_mark_node
5938       || arg2 == error_mark_node)
5939     return const0_rtx;
5940
5941   if (icode == CODE_FOR_altivec_vsldoi_4sf
5942       || icode == CODE_FOR_altivec_vsldoi_4si
5943       || icode == CODE_FOR_altivec_vsldoi_8hi
5944       || icode == CODE_FOR_altivec_vsldoi_16qi)
5945     {
5946       /* Only allow 4-bit unsigned literals.  */
5947       STRIP_NOPS (arg2);
5948       if (TREE_CODE (arg2) != INTEGER_CST
5949           || TREE_INT_CST_LOW (arg2) & ~0xf)
5950         {
5951           error ("argument 3 must be a 4-bit unsigned literal");
5952           return const0_rtx;
5953         }
5954     }
5955
5956   if (target == 0
5957       || GET_MODE (target) != tmode
5958       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5959     target = gen_reg_rtx (tmode);
5960
5961   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5962     op0 = copy_to_mode_reg (mode0, op0);
5963   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5964     op1 = copy_to_mode_reg (mode1, op1);
5965   if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5966     op2 = copy_to_mode_reg (mode2, op2);
5967
5968   pat = GEN_FCN (icode) (target, op0, op1, op2);
5969   if (! pat)
5970     return 0;
5971   emit_insn (pat);
5972
5973   return target;
5974 }
5975
5976 /* Expand the lvx builtins.  */
5977 static rtx
5978 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5979 {
5980   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5981   tree arglist = TREE_OPERAND (exp, 1);
5982   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5983   tree arg0;
5984   enum machine_mode tmode, mode0;
5985   rtx pat, op0;
5986   enum insn_code icode;
5987
5988   switch (fcode)
5989     {
5990     case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5991       icode = CODE_FOR_altivec_lvx_16qi;
5992       break;
5993     case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5994       icode = CODE_FOR_altivec_lvx_8hi;
5995       break;
5996     case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5997       icode = CODE_FOR_altivec_lvx_4si;
5998       break;
5999     case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6000       icode = CODE_FOR_altivec_lvx_4sf;
6001       break;
6002     default:
6003       *expandedp = false;
6004       return NULL_RTX;
6005     }
6006
6007   *expandedp = true;
6008
6009   arg0 = TREE_VALUE (arglist);
6010   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6011   tmode = insn_data[icode].operand[0].mode;
6012   mode0 = insn_data[icode].operand[1].mode;
6013
6014   if (target == 0
6015       || GET_MODE (target) != tmode
6016       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6017     target = gen_reg_rtx (tmode);
6018
6019   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6020     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6021
6022   pat = GEN_FCN (icode) (target, op0);
6023   if (! pat)
6024     return 0;
6025   emit_insn (pat);
6026   return target;
6027 }
6028
6029 /* Expand the stvx builtins.  */
6030 static rtx
6031 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6032                            bool *expandedp)
6033 {
6034   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6035   tree arglist = TREE_OPERAND (exp, 1);
6036   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6037   tree arg0, arg1;
6038   enum machine_mode mode0, mode1;
6039   rtx pat, op0, op1;
6040   enum insn_code icode;
6041
6042   switch (fcode)
6043     {
6044     case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6045       icode = CODE_FOR_altivec_stvx_16qi;
6046       break;
6047     case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6048       icode = CODE_FOR_altivec_stvx_8hi;
6049       break;
6050     case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6051       icode = CODE_FOR_altivec_stvx_4si;
6052       break;
6053     case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6054       icode = CODE_FOR_altivec_stvx_4sf;
6055       break;
6056     default:
6057       *expandedp = false;
6058       return NULL_RTX;
6059     }
6060
6061   arg0 = TREE_VALUE (arglist);
6062   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6063   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6064   op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6065   mode0 = insn_data[icode].operand[0].mode;
6066   mode1 = insn_data[icode].operand[1].mode;
6067
6068   if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6069     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6070   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6071     op1 = copy_to_mode_reg (mode1, op1);
6072
6073   pat = GEN_FCN (icode) (op0, op1);
6074   if (pat)
6075     emit_insn (pat);
6076
6077   *expandedp = true;
6078   return NULL_RTX;
6079 }
6080
6081 /* Expand the dst builtins.  */
6082 static rtx
6083 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6084                             bool *expandedp)
6085 {
6086   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6087   tree arglist = TREE_OPERAND (exp, 1);
6088   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6089   tree arg0, arg1, arg2;
6090   enum machine_mode mode0, mode1, mode2;
6091   rtx pat, op0, op1, op2;
6092   struct builtin_description *d;
6093   size_t i;
6094
6095   *expandedp = false;
6096
6097   /* Handle DST variants.  */
6098   d = (struct builtin_description *) bdesc_dst;
6099   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6100     if (d->code == fcode)
6101       {
6102         arg0 = TREE_VALUE (arglist);
6103         arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6104         arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6105         op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6106         op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6107         op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6108         mode0 = insn_data[d->icode].operand[0].mode;
6109         mode1 = insn_data[d->icode].operand[1].mode;
6110         mode2 = insn_data[d->icode].operand[2].mode;
6111
6112         /* Invalid arguments, bail out before generating bad rtl.  */
6113         if (arg0 == error_mark_node
6114             || arg1 == error_mark_node
6115             || arg2 == error_mark_node)
6116           return const0_rtx;
6117
6118         *expandedp = true;
6119         STRIP_NOPS (arg2);
6120         if (TREE_CODE (arg2) != INTEGER_CST
6121             || TREE_INT_CST_LOW (arg2) & ~0x3)
6122           {
6123             error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
6124             return const0_rtx;
6125           }
6126
6127         if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6128           op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6129         if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6130           op1 = copy_to_mode_reg (mode1, op1);
6131
6132         pat = GEN_FCN (d->icode) (op0, op1, op2);
6133         if (pat != 0)
6134           emit_insn (pat);
6135
6136         return NULL_RTX;
6137       }
6138
6139   return NULL_RTX;
6140 }
6141
6142 /* Expand the builtin in EXP and store the result in TARGET.  Store
6143    true in *EXPANDEDP if we found a builtin to expand.  */
6144 static rtx
6145 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6146 {
6147   struct builtin_description *d;
6148   struct builtin_description_predicates *dp;
6149   size_t i;
6150   enum insn_code icode;
6151   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6152   tree arglist = TREE_OPERAND (exp, 1);
6153   tree arg0;
6154   rtx op0, pat;
6155   enum machine_mode tmode, mode0;
6156   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6157
6158   target = altivec_expand_ld_builtin (exp, target, expandedp);
6159   if (*expandedp)
6160     return target;
6161
6162   target = altivec_expand_st_builtin (exp, target, expandedp);
6163   if (*expandedp)
6164     return target;
6165
6166   target = altivec_expand_dst_builtin (exp, target, expandedp);
6167   if (*expandedp)
6168     return target;
6169
6170   *expandedp = true;
6171
6172   switch (fcode)
6173     {
6174     case ALTIVEC_BUILTIN_STVX:
6175       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6176     case ALTIVEC_BUILTIN_STVEBX:
6177       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6178     case ALTIVEC_BUILTIN_STVEHX:
6179       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6180     case ALTIVEC_BUILTIN_STVEWX:
6181       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6182     case ALTIVEC_BUILTIN_STVXL:
6183       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6184
6185     case ALTIVEC_BUILTIN_MFVSCR:
6186       icode = CODE_FOR_altivec_mfvscr;
6187       tmode = insn_data[icode].operand[0].mode;
6188
6189       if (target == 0
6190           || GET_MODE (target) != tmode
6191           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6192         target = gen_reg_rtx (tmode);
6193
6194       pat = GEN_FCN (icode) (target);
6195       if (! pat)
6196         return 0;
6197       emit_insn (pat);
6198       return target;
6199
6200     case ALTIVEC_BUILTIN_MTVSCR:
6201       icode = CODE_FOR_altivec_mtvscr;
6202       arg0 = TREE_VALUE (arglist);
6203       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6204       mode0 = insn_data[icode].operand[0].mode;
6205
6206       /* If we got invalid arguments bail out before generating bad rtl.  */
6207       if (arg0 == error_mark_node)
6208         return const0_rtx;
6209
6210       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6211         op0 = copy_to_mode_reg (mode0, op0);
6212
6213       pat = GEN_FCN (icode) (op0);
6214       if (pat)
6215         emit_insn (pat);
6216       return NULL_RTX;
6217
6218     case ALTIVEC_BUILTIN_DSSALL:
6219       emit_insn (gen_altivec_dssall ());
6220       return NULL_RTX;
6221
6222     case ALTIVEC_BUILTIN_DSS:
6223       icode = CODE_FOR_altivec_dss;
6224       arg0 = TREE_VALUE (arglist);
6225       STRIP_NOPS (arg0);
6226       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6227       mode0 = insn_data[icode].operand[0].mode;
6228
6229       /* If we got invalid arguments bail out before generating bad rtl.  */
6230       if (arg0 == error_mark_node)
6231         return const0_rtx;
6232
6233       if (TREE_CODE (arg0) != INTEGER_CST
6234           || TREE_INT_CST_LOW (arg0) & ~0x3)
6235         {
6236           error ("argument to dss must be a 2-bit unsigned literal");
6237           return const0_rtx;
6238         }
6239
6240       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6241         op0 = copy_to_mode_reg (mode0, op0);
6242
6243       emit_insn (gen_altivec_dss (op0));
6244       return NULL_RTX;
6245
6246     case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6247       arg0 = TREE_VALUE (arglist);
6248       while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR)
6249         arg0 = TREE_OPERAND (arg0, 0);
6250       error ("invalid parameter combination for `%s' AltiVec intrinsic",
6251              TREE_STRING_POINTER (arg0));
6252
6253       return const0_rtx;
6254     }
6255
6256   /* Expand abs* operations.  */
6257   d = (struct builtin_description *) bdesc_abs;
6258   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6259     if (d->code == fcode)
6260       return altivec_expand_abs_builtin (d->icode, arglist, target);
6261
6262   /* Expand the AltiVec predicates.  */
6263   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6264   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6265     if (dp->code == fcode)
6266       return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
6267
6268   /* LV* are funky.  We initialized them differently.  */
6269   switch (fcode)
6270     {
6271     case ALTIVEC_BUILTIN_LVSL:
6272       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6273                                            arglist, target);
6274     case ALTIVEC_BUILTIN_LVSR:
6275       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6276                                           arglist, target);
6277     case ALTIVEC_BUILTIN_LVEBX:
6278       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6279                                           arglist, target);
6280     case ALTIVEC_BUILTIN_LVEHX:
6281       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6282                                           arglist, target);
6283     case ALTIVEC_BUILTIN_LVEWX:
6284       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6285                                           arglist, target);
6286     case ALTIVEC_BUILTIN_LVXL:
6287       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6288                                           arglist, target);
6289     case ALTIVEC_BUILTIN_LVX:
6290       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6291                                           arglist, target);
6292     default:
6293       break;
6294       /* Fall through.  */
6295     }
6296
6297   *expandedp = false;
6298   return NULL_RTX;
6299 }
6300
6301 /* Binops that need to be initialized manually, but can be expanded
6302    automagically by rs6000_expand_binop_builtin.  */
6303 static struct builtin_description bdesc_2arg_spe[] =
6304 {
6305   { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6306   { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6307   { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6308   { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6309   { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6310   { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6311   { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6312   { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6313   { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6314   { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6315   { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6316   { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6317   { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6318   { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6319   { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6320   { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6321   { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6322   { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6323   { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6324   { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6325   { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6326   { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6327 };
6328
6329 /* Expand the builtin in EXP and store the result in TARGET.  Store
6330    true in *EXPANDEDP if we found a builtin to expand.
6331
6332    This expands the SPE builtins that are not simple unary and binary
6333    operations.  */
6334 static rtx
6335 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6336 {
6337   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6338   tree arglist = TREE_OPERAND (exp, 1);
6339   tree arg1, arg0;
6340   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6341   enum insn_code icode;
6342   enum machine_mode tmode, mode0;
6343   rtx pat, op0;
6344   struct builtin_description *d;
6345   size_t i;
6346
6347   *expandedp = true;
6348
6349   /* Syntax check for a 5-bit unsigned immediate.  */
6350   switch (fcode)
6351     {
6352     case SPE_BUILTIN_EVSTDD:
6353     case SPE_BUILTIN_EVSTDH:
6354     case SPE_BUILTIN_EVSTDW:
6355     case SPE_BUILTIN_EVSTWHE:
6356     case SPE_BUILTIN_EVSTWHO:
6357     case SPE_BUILTIN_EVSTWWE:
6358     case SPE_BUILTIN_EVSTWWO:
6359       arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6360       if (TREE_CODE (arg1) != INTEGER_CST
6361           || TREE_INT_CST_LOW (arg1) & ~0x1f)
6362         {
6363           error ("argument 2 must be a 5-bit unsigned literal");
6364           return const0_rtx;
6365         }
6366       break;
6367     default:
6368       break;
6369     }
6370
6371   /* The evsplat*i instructions are not quite generic.  */
6372   switch (fcode)
6373     {
6374     case SPE_BUILTIN_EVSPLATFI:
6375       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6376                                          arglist, target);
6377     case SPE_BUILTIN_EVSPLATI:
6378       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6379                                          arglist, target);
6380     default:
6381       break;
6382     }
6383
6384   d = (struct builtin_description *) bdesc_2arg_spe;
6385   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6386     if (d->code == fcode)
6387       return rs6000_expand_binop_builtin (d->icode, arglist, target);
6388
6389   d = (struct builtin_description *) bdesc_spe_predicates;
6390   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6391     if (d->code == fcode)
6392       return spe_expand_predicate_builtin (d->icode, arglist, target);
6393
6394   d = (struct builtin_description *) bdesc_spe_evsel;
6395   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6396     if (d->code == fcode)
6397       return spe_expand_evsel_builtin (d->icode, arglist, target);
6398
6399   switch (fcode)
6400     {
6401     case SPE_BUILTIN_EVSTDDX:
6402       return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6403     case SPE_BUILTIN_EVSTDHX:
6404       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6405     case SPE_BUILTIN_EVSTDWX:
6406       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6407     case SPE_BUILTIN_EVSTWHEX:
6408       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6409     case SPE_BUILTIN_EVSTWHOX:
6410       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6411     case SPE_BUILTIN_EVSTWWEX:
6412       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6413     case SPE_BUILTIN_EVSTWWOX:
6414       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6415     case SPE_BUILTIN_EVSTDD:
6416       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6417     case SPE_BUILTIN_EVSTDH:
6418       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6419     case SPE_BUILTIN_EVSTDW:
6420       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6421     case SPE_BUILTIN_EVSTWHE:
6422       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6423     case SPE_BUILTIN_EVSTWHO:
6424       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6425     case SPE_BUILTIN_EVSTWWE:
6426       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6427     case SPE_BUILTIN_EVSTWWO:
6428       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6429     case SPE_BUILTIN_MFSPEFSCR:
6430       icode = CODE_FOR_spe_mfspefscr;
6431       tmode = insn_data[icode].operand[0].mode;
6432
6433       if (target == 0
6434           || GET_MODE (target) != tmode
6435           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6436         target = gen_reg_rtx (tmode);
6437
6438       pat = GEN_FCN (icode) (target);
6439       if (! pat)
6440         return 0;
6441       emit_insn (pat);
6442       return target;
6443     case SPE_BUILTIN_MTSPEFSCR:
6444       icode = CODE_FOR_spe_mtspefscr;
6445       arg0 = TREE_VALUE (arglist);
6446       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6447       mode0 = insn_data[icode].operand[0].mode;
6448
6449       if (arg0 == error_mark_node)
6450         return const0_rtx;
6451
6452       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6453         op0 = copy_to_mode_reg (mode0, op0);
6454
6455       pat = GEN_FCN (icode) (op0);
6456       if (pat)
6457         emit_insn (pat);
6458       return NULL_RTX;
6459     default:
6460       break;
6461     }
6462
6463   *expandedp = false;
6464   return NULL_RTX;
6465 }
6466
6467 static rtx
6468 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6469 {
6470   rtx pat, scratch, tmp;
6471   tree form = TREE_VALUE (arglist);
6472   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6473   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6474   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6475   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6476   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6477   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6478   int form_int;
6479   enum rtx_code code;
6480
6481   if (TREE_CODE (form) != INTEGER_CST)
6482     {
6483       error ("argument 1 of __builtin_spe_predicate must be a constant");
6484       return const0_rtx;
6485     }
6486   else
6487     form_int = TREE_INT_CST_LOW (form);
6488
6489   if (mode0 != mode1)
6490     abort ();
6491
6492   if (arg0 == error_mark_node || arg1 == error_mark_node)
6493     return const0_rtx;
6494
6495   if (target == 0
6496       || GET_MODE (target) != SImode
6497       || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6498     target = gen_reg_rtx (SImode);
6499
6500   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6501     op0 = copy_to_mode_reg (mode0, op0);
6502   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6503     op1 = copy_to_mode_reg (mode1, op1);
6504
6505   scratch = gen_reg_rtx (CCmode);
6506
6507   pat = GEN_FCN (icode) (scratch, op0, op1);
6508   if (! pat)
6509     return const0_rtx;
6510   emit_insn (pat);
6511
6512   /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6513      _lower_.  We use one compare, but look in different bits of the
6514      CR for each variant.
6515
6516      There are 2 elements in each SPE simd type (upper/lower).  The CR
6517      bits are set as follows:
6518
6519      BIT0  | BIT 1  | BIT 2   | BIT 3
6520      U     |   L    | (U | L) | (U & L)
6521
6522      So, for an "all" relationship, BIT 3 would be set.
6523      For an "any" relationship, BIT 2 would be set.  Etc.
6524
6525      Following traditional nomenclature, these bits map to:
6526
6527      BIT0  | BIT 1  | BIT 2   | BIT 3
6528      LT    | GT     | EQ      | OV
6529
6530      Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6531   */
6532
6533   switch (form_int)
6534     {
6535       /* All variant.  OV bit.  */
6536     case 0:
6537       /* We need to get to the OV bit, which is the ORDERED bit.  We
6538          could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6539          that's ugly and will trigger a validate_condition_mode abort.
6540          So let's just use another pattern.  */
6541       emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6542       return target;
6543       /* Any variant.  EQ bit.  */
6544     case 1:
6545       code = EQ;
6546       break;
6547       /* Upper variant.  LT bit.  */
6548     case 2:
6549       code = LT;
6550       break;
6551       /* Lower variant.  GT bit.  */
6552     case 3:
6553       code = GT;
6554       break;
6555     default:
6556       error ("argument 1 of __builtin_spe_predicate is out of range");
6557       return const0_rtx;
6558     }
6559
6560   tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6561   emit_move_insn (target, tmp);
6562
6563   return target;
6564 }
6565
6566 /* The evsel builtins look like this:
6567
6568      e = __builtin_spe_evsel_OP (a, b, c, d);
6569
6570    and work like this:
6571
6572      e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6573      e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6574 */
6575
6576 static rtx
6577 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6578 {
6579   rtx pat, scratch;
6580   tree arg0 = TREE_VALUE (arglist);
6581   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6582   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6583   tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6584   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6585   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6586   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6587   rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6588   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6589   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6590
6591   if (mode0 != mode1)
6592     abort ();
6593
6594   if (arg0 == error_mark_node || arg1 == error_mark_node
6595       || arg2 == error_mark_node || arg3 == error_mark_node)
6596     return const0_rtx;
6597
6598   if (target == 0
6599       || GET_MODE (target) != mode0
6600       || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6601     target = gen_reg_rtx (mode0);
6602
6603   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6604     op0 = copy_to_mode_reg (mode0, op0);
6605   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6606     op1 = copy_to_mode_reg (mode0, op1);
6607   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6608     op2 = copy_to_mode_reg (mode0, op2);
6609   if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6610     op3 = copy_to_mode_reg (mode0, op3);
6611
6612   /* Generate the compare.  */
6613   scratch = gen_reg_rtx (CCmode);
6614   pat = GEN_FCN (icode) (scratch, op0, op1);
6615   if (! pat)
6616     return const0_rtx;
6617   emit_insn (pat);
6618
6619   if (mode0 == V2SImode)
6620     emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6621   else
6622     emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6623
6624   return target;
6625 }
6626
6627 /* Expand an expression EXP that calls a built-in function,
6628    with result going to TARGET if that's convenient
6629    (and in mode MODE if that's convenient).
6630    SUBTARGET may be used as the target for computing one of EXP's operands.
6631    IGNORE is nonzero if the value is to be ignored.  */
6632
6633 static rtx
6634 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6635                       enum machine_mode mode ATTRIBUTE_UNUSED,
6636                       int ignore ATTRIBUTE_UNUSED)
6637 {
6638   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6639   tree arglist = TREE_OPERAND (exp, 1);
6640   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6641   struct builtin_description *d;
6642   size_t i;
6643   rtx ret;
6644   bool success;
6645
6646   if (TARGET_ALTIVEC)
6647     {
6648       ret = altivec_expand_builtin (exp, target, &success);
6649
6650       if (success)
6651         return ret;
6652     }
6653   if (TARGET_SPE)
6654     {
6655       ret = spe_expand_builtin (exp, target, &success);
6656
6657       if (success)
6658         return ret;
6659     }
6660
6661   if (TARGET_ALTIVEC || TARGET_SPE)
6662     {
6663       /* Handle simple unary operations.  */
6664       d = (struct builtin_description *) bdesc_1arg;
6665       for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6666         if (d->code == fcode)
6667           return rs6000_expand_unop_builtin (d->icode, arglist, target);
6668
6669       /* Handle simple binary operations.  */
6670       d = (struct builtin_description *) bdesc_2arg;
6671       for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6672         if (d->code == fcode)
6673           return rs6000_expand_binop_builtin (d->icode, arglist, target);
6674
6675       /* Handle simple ternary operations.  */
6676       d = (struct builtin_description *) bdesc_3arg;
6677       for (i = 0; i < ARRAY_SIZE  (bdesc_3arg); i++, d++)
6678         if (d->code == fcode)
6679           return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6680     }
6681
6682   abort ();
6683   return NULL_RTX;
6684 }
6685
6686 static tree
6687 build_opaque_vector_type (tree node, int nunits)
6688 {
6689   node = copy_node (node);
6690   TYPE_MAIN_VARIANT (node) = node;
6691   return build_vector_type (node, nunits);
6692 }
6693
6694 static void
6695 rs6000_init_builtins (void)
6696 {
6697   V2SI_type_node = build_vector_type (intSI_type_node, 2);
6698   V2SF_type_node = build_vector_type (float_type_node, 2);
6699   V4HI_type_node = build_vector_type (intHI_type_node, 4);
6700   V4SI_type_node = build_vector_type (intSI_type_node, 4);
6701   V4SF_type_node = build_vector_type (float_type_node, 4);
6702   V8HI_type_node = build_vector_type (intHI_type_node, 8);
6703   V16QI_type_node = build_vector_type (intQI_type_node, 16);
6704
6705   unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
6706   unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
6707   unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
6708
6709   opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
6710   opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6711   opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6712
6713   /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
6714      types, especially in C++ land.  Similarly, 'vector pixel' is distinct from
6715      'vector unsigned short'.  */
6716
6717   bool_char_type_node = copy_node (unsigned_intQI_type_node);
6718   TYPE_MAIN_VARIANT (bool_char_type_node) = bool_char_type_node;
6719   bool_short_type_node = copy_node (unsigned_intHI_type_node);
6720   TYPE_MAIN_VARIANT (bool_short_type_node) = bool_short_type_node;
6721   bool_int_type_node = copy_node (unsigned_intSI_type_node);
6722   TYPE_MAIN_VARIANT (bool_int_type_node) = bool_int_type_node;
6723   pixel_type_node = copy_node (unsigned_intHI_type_node);
6724   TYPE_MAIN_VARIANT (pixel_type_node) = pixel_type_node;
6725
6726   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6727                                             get_identifier ("__bool char"),
6728                                             bool_char_type_node));
6729   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6730                                             get_identifier ("__bool short"),
6731                                             bool_short_type_node));
6732   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6733                                             get_identifier ("__bool int"),
6734                                             bool_int_type_node));
6735   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6736                                             get_identifier ("__pixel"),
6737                                             pixel_type_node));
6738
6739   bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
6740   bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
6741   bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
6742   pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
6743
6744   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6745                                             get_identifier ("__vector unsigned char"),
6746                                             unsigned_V16QI_type_node));
6747   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6748                                             get_identifier ("__vector signed char"),
6749                                             V16QI_type_node));
6750   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6751                                             get_identifier ("__vector __bool char"),
6752                                             bool_V16QI_type_node));
6753
6754   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6755                                             get_identifier ("__vector unsigned short"),
6756                                             unsigned_V8HI_type_node));
6757   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6758                                             get_identifier ("__vector signed short"),
6759                                             V8HI_type_node));
6760   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6761                                             get_identifier ("__vector __bool short"),
6762                                             bool_V8HI_type_node));
6763
6764   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6765                                             get_identifier ("__vector unsigned int"),
6766                                             unsigned_V4SI_type_node));
6767   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6768                                             get_identifier ("__vector signed int"),
6769                                             V4SI_type_node));
6770   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6771                                             get_identifier ("__vector __bool int"),
6772                                             bool_V4SI_type_node));
6773
6774   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6775                                             get_identifier ("__vector float"),
6776                                             V4SF_type_node));
6777   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6778                                             get_identifier ("__vector __pixel"),
6779                                             pixel_V8HI_type_node));
6780
6781   if (TARGET_SPE)
6782     spe_init_builtins ();
6783   if (TARGET_ALTIVEC)
6784     altivec_init_builtins ();
6785   if (TARGET_ALTIVEC || TARGET_SPE)
6786     rs6000_common_init_builtins ();
6787 }
6788
6789 /* Search through a set of builtins and enable the mask bits.
6790    DESC is an array of builtins.
6791    SIZE is the total number of builtins.
6792    START is the builtin enum at which to start.
6793    END is the builtin enum at which to end.  */
6794 static void
6795 enable_mask_for_builtins (struct builtin_description *desc, int size,
6796                           enum rs6000_builtins start,
6797                           enum rs6000_builtins end)
6798 {
6799   int i;
6800
6801   for (i = 0; i < size; ++i)
6802     if (desc[i].code == start)
6803       break;
6804
6805   if (i == size)
6806     return;
6807
6808   for (; i < size; ++i)
6809     {
6810       /* Flip all the bits on.  */
6811       desc[i].mask = target_flags;
6812       if (desc[i].code == end)
6813         break;
6814     }
6815 }
6816
6817 static void
6818 spe_init_builtins (void)
6819 {
6820   tree endlink = void_list_node;
6821   tree puint_type_node = build_pointer_type (unsigned_type_node);
6822   tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6823   struct builtin_description *d;
6824   size_t i;
6825
6826   tree v2si_ftype_4_v2si
6827     = build_function_type
6828     (opaque_V2SI_type_node,
6829      tree_cons (NULL_TREE, opaque_V2SI_type_node,
6830                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6831                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6832                                       tree_cons (NULL_TREE, opaque_V2SI_type_node,
6833                                                  endlink)))));
6834
6835   tree v2sf_ftype_4_v2sf
6836     = build_function_type
6837     (opaque_V2SF_type_node,
6838      tree_cons (NULL_TREE, opaque_V2SF_type_node,
6839                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6840                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6841                                       tree_cons (NULL_TREE, opaque_V2SF_type_node,
6842                                                  endlink)))));
6843
6844   tree int_ftype_int_v2si_v2si
6845     = build_function_type
6846     (integer_type_node,
6847      tree_cons (NULL_TREE, integer_type_node,
6848                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6849                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6850                                       endlink))));
6851
6852   tree int_ftype_int_v2sf_v2sf
6853     = build_function_type
6854     (integer_type_node,
6855      tree_cons (NULL_TREE, integer_type_node,
6856                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6857                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6858                                       endlink))));
6859
6860   tree void_ftype_v2si_puint_int
6861     = build_function_type (void_type_node,
6862                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6863                                       tree_cons (NULL_TREE, puint_type_node,
6864                                                  tree_cons (NULL_TREE,
6865                                                             integer_type_node,
6866                                                             endlink))));
6867
6868   tree void_ftype_v2si_puint_char
6869     = build_function_type (void_type_node,
6870                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6871                                       tree_cons (NULL_TREE, puint_type_node,
6872                                                  tree_cons (NULL_TREE,
6873                                                             char_type_node,
6874                                                             endlink))));
6875
6876   tree void_ftype_v2si_pv2si_int
6877     = build_function_type (void_type_node,
6878                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6879                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6880                                                  tree_cons (NULL_TREE,
6881                                                             integer_type_node,
6882                                                             endlink))));
6883
6884   tree void_ftype_v2si_pv2si_char
6885     = build_function_type (void_type_node,
6886                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6887                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6888                                                  tree_cons (NULL_TREE,
6889                                                             char_type_node,
6890                                                             endlink))));
6891
6892   tree void_ftype_int
6893     = build_function_type (void_type_node,
6894                            tree_cons (NULL_TREE, integer_type_node, endlink));
6895
6896   tree int_ftype_void
6897     = build_function_type (integer_type_node, endlink);
6898
6899   tree v2si_ftype_pv2si_int
6900     = build_function_type (opaque_V2SI_type_node,
6901                            tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6902                                       tree_cons (NULL_TREE, integer_type_node,
6903                                                  endlink)));
6904
6905   tree v2si_ftype_puint_int
6906     = build_function_type (opaque_V2SI_type_node,
6907                            tree_cons (NULL_TREE, puint_type_node,
6908                                       tree_cons (NULL_TREE, integer_type_node,
6909                                                  endlink)));
6910
6911   tree v2si_ftype_pushort_int
6912     = build_function_type (opaque_V2SI_type_node,
6913                            tree_cons (NULL_TREE, pushort_type_node,
6914                                       tree_cons (NULL_TREE, integer_type_node,
6915                                                  endlink)));
6916
6917   tree v2si_ftype_signed_char
6918     = build_function_type (opaque_V2SI_type_node,
6919                            tree_cons (NULL_TREE, signed_char_type_node,
6920                                       endlink));
6921
6922   /* The initialization of the simple binary and unary builtins is
6923      done in rs6000_common_init_builtins, but we have to enable the
6924      mask bits here manually because we have run out of `target_flags'
6925      bits.  We really need to redesign this mask business.  */
6926
6927   enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6928                             ARRAY_SIZE (bdesc_2arg),
6929                             SPE_BUILTIN_EVADDW,
6930                             SPE_BUILTIN_EVXOR);
6931   enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6932                             ARRAY_SIZE (bdesc_1arg),
6933                             SPE_BUILTIN_EVABS,
6934                             SPE_BUILTIN_EVSUBFUSIAAW);
6935   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6936                             ARRAY_SIZE (bdesc_spe_predicates),
6937                             SPE_BUILTIN_EVCMPEQ,
6938                             SPE_BUILTIN_EVFSTSTLT);
6939   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6940                             ARRAY_SIZE (bdesc_spe_evsel),
6941                             SPE_BUILTIN_EVSEL_CMPGTS,
6942                             SPE_BUILTIN_EVSEL_FSTSTEQ);
6943
6944   (*lang_hooks.decls.pushdecl)
6945     (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6946                  opaque_V2SI_type_node));
6947
6948   /* Initialize irregular SPE builtins.  */
6949
6950   def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6951   def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6952   def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6953   def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6954   def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6955   def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6956   def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6957   def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6958   def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6959   def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6960   def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6961   def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6962   def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6963   def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6964   def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6965   def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6966   def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6967   def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6968
6969   /* Loads.  */
6970   def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6971   def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6972   def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6973   def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6974   def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6975   def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6976   def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6977   def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6978   def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6979   def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6980   def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6981   def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6982   def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6983   def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6984   def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6985   def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6986   def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6987   def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6988   def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6989   def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6990   def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6991   def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6992
6993   /* Predicates.  */
6994   d = (struct builtin_description *) bdesc_spe_predicates;
6995   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6996     {
6997       tree type;
6998
6999       switch (insn_data[d->icode].operand[1].mode)
7000         {
7001         case V2SImode:
7002           type = int_ftype_int_v2si_v2si;
7003           break;
7004         case V2SFmode:
7005           type = int_ftype_int_v2sf_v2sf;
7006           break;
7007         default:
7008           abort ();
7009         }
7010
7011       def_builtin (d->mask, d->name, type, d->code);
7012     }
7013
7014   /* Evsel predicates.  */
7015   d = (struct builtin_description *) bdesc_spe_evsel;
7016   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7017     {
7018       tree type;
7019
7020       switch (insn_data[d->icode].operand[1].mode)
7021         {
7022         case V2SImode:
7023           type = v2si_ftype_4_v2si;
7024           break;
7025         case V2SFmode:
7026           type = v2sf_ftype_4_v2sf;
7027           break;
7028         default:
7029           abort ();
7030         }
7031
7032       def_builtin (d->mask, d->name, type, d->code);
7033     }
7034 }
7035
7036 static void
7037 altivec_init_builtins (void)
7038 {
7039   struct builtin_description *d;
7040   struct builtin_description_predicates *dp;
7041   size_t i;
7042   tree pfloat_type_node = build_pointer_type (float_type_node);
7043   tree pint_type_node = build_pointer_type (integer_type_node);
7044   tree pshort_type_node = build_pointer_type (short_integer_type_node);
7045   tree pchar_type_node = build_pointer_type (char_type_node);
7046
7047   tree pvoid_type_node = build_pointer_type (void_type_node);
7048
7049   tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7050   tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7051   tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7052   tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7053
7054   tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7055
7056   tree int_ftype_int_v4si_v4si
7057     = build_function_type_list (integer_type_node,
7058                                 integer_type_node, V4SI_type_node,
7059                                 V4SI_type_node, NULL_TREE);
7060   tree v4sf_ftype_pcfloat
7061     = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7062   tree void_ftype_pfloat_v4sf
7063     = build_function_type_list (void_type_node,
7064                                 pfloat_type_node, V4SF_type_node, NULL_TREE);
7065   tree v4si_ftype_pcint
7066     = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7067   tree void_ftype_pint_v4si
7068     = build_function_type_list (void_type_node,
7069                                 pint_type_node, V4SI_type_node, NULL_TREE);
7070   tree v8hi_ftype_pcshort
7071     = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7072   tree void_ftype_pshort_v8hi
7073     = build_function_type_list (void_type_node,
7074                                 pshort_type_node, V8HI_type_node, NULL_TREE);
7075   tree v16qi_ftype_pcchar
7076     = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7077   tree void_ftype_pchar_v16qi
7078     = build_function_type_list (void_type_node,
7079                                 pchar_type_node, V16QI_type_node, NULL_TREE);
7080   tree void_ftype_v4si
7081     = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7082   tree v8hi_ftype_void
7083     = build_function_type (V8HI_type_node, void_list_node);
7084   tree void_ftype_void
7085     = build_function_type (void_type_node, void_list_node);
7086   tree void_ftype_qi
7087     = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
7088
7089   tree v16qi_ftype_long_pcvoid
7090     = build_function_type_list (V16QI_type_node,
7091                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7092   tree v8hi_ftype_long_pcvoid
7093     = build_function_type_list (V8HI_type_node,
7094                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7095   tree v4si_ftype_long_pcvoid
7096     = build_function_type_list (V4SI_type_node,
7097                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7098
7099   tree void_ftype_v4si_long_pvoid
7100     = build_function_type_list (void_type_node,
7101                                 V4SI_type_node, long_integer_type_node,
7102                                 pvoid_type_node, NULL_TREE);
7103   tree void_ftype_v16qi_long_pvoid
7104     = build_function_type_list (void_type_node,
7105                                 V16QI_type_node, long_integer_type_node,
7106                                 pvoid_type_node, NULL_TREE);
7107   tree void_ftype_v8hi_long_pvoid
7108     = build_function_type_list (void_type_node,
7109                                 V8HI_type_node, long_integer_type_node,
7110                                 pvoid_type_node, NULL_TREE);
7111   tree int_ftype_int_v8hi_v8hi
7112     = build_function_type_list (integer_type_node,
7113                                 integer_type_node, V8HI_type_node,
7114                                 V8HI_type_node, NULL_TREE);
7115   tree int_ftype_int_v16qi_v16qi
7116     = build_function_type_list (integer_type_node,
7117                                 integer_type_node, V16QI_type_node,
7118                                 V16QI_type_node, NULL_TREE);
7119   tree int_ftype_int_v4sf_v4sf
7120     = build_function_type_list (integer_type_node,
7121                                 integer_type_node, V4SF_type_node,
7122                                 V4SF_type_node, NULL_TREE);
7123   tree v4si_ftype_v4si
7124     = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7125   tree v8hi_ftype_v8hi
7126     = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7127   tree v16qi_ftype_v16qi
7128     = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7129   tree v4sf_ftype_v4sf
7130     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7131   tree void_ftype_pcvoid_int_int
7132     = build_function_type_list (void_type_node,
7133                                 pcvoid_type_node, integer_type_node,
7134                                 integer_type_node, NULL_TREE);
7135   tree int_ftype_pcchar
7136     = build_function_type_list (integer_type_node,
7137                                 pcchar_type_node, NULL_TREE);
7138
7139   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7140                ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7141   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7142                ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7143   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7144                ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7145   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7146                ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7147   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7148                ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7149   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7150                ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7151   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7152                ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7153   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7154                ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7155   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7156   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7157   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7158   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
7159   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7160   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7161   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7162   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7163   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7164   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7165   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7166   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7167   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7168   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7169   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7170   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7171
7172   /* See altivec.h for usage of "__builtin_altivec_compiletime_error".  */
7173   def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7174                ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7175
7176   /* Add the DST variants.  */
7177   d = (struct builtin_description *) bdesc_dst;
7178   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7179     def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7180
7181   /* Initialize the predicates.  */
7182   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7183   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7184     {
7185       enum machine_mode mode1;
7186       tree type;
7187
7188       mode1 = insn_data[dp->icode].operand[1].mode;
7189
7190       switch (mode1)
7191         {
7192         case V4SImode:
7193           type = int_ftype_int_v4si_v4si;
7194           break;
7195         case V8HImode:
7196           type = int_ftype_int_v8hi_v8hi;
7197           break;
7198         case V16QImode:
7199           type = int_ftype_int_v16qi_v16qi;
7200           break;
7201         case V4SFmode:
7202           type = int_ftype_int_v4sf_v4sf;
7203           break;
7204         default:
7205           abort ();
7206         }
7207
7208       def_builtin (dp->mask, dp->name, type, dp->code);
7209     }
7210
7211   /* Initialize the abs* operators.  */
7212   d = (struct builtin_description *) bdesc_abs;
7213   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7214     {
7215       enum machine_mode mode0;
7216       tree type;
7217
7218       mode0 = insn_data[d->icode].operand[0].mode;
7219
7220       switch (mode0)
7221         {
7222         case V4SImode:
7223           type = v4si_ftype_v4si;
7224           break;
7225         case V8HImode:
7226           type = v8hi_ftype_v8hi;
7227           break;
7228         case V16QImode:
7229           type = v16qi_ftype_v16qi;
7230           break;
7231         case V4SFmode:
7232           type = v4sf_ftype_v4sf;
7233           break;
7234         default:
7235           abort ();
7236         }
7237
7238       def_builtin (d->mask, d->name, type, d->code);
7239     }
7240 }
7241
7242 static void
7243 rs6000_common_init_builtins (void)
7244 {
7245   struct builtin_description *d;
7246   size_t i;
7247
7248   tree v4sf_ftype_v4sf_v4sf_v16qi
7249     = build_function_type_list (V4SF_type_node,
7250                                 V4SF_type_node, V4SF_type_node,
7251                                 V16QI_type_node, NULL_TREE);
7252   tree v4si_ftype_v4si_v4si_v16qi
7253     = build_function_type_list (V4SI_type_node,
7254                                 V4SI_type_node, V4SI_type_node,
7255                                 V16QI_type_node, NULL_TREE);
7256   tree v8hi_ftype_v8hi_v8hi_v16qi
7257     = build_function_type_list (V8HI_type_node,
7258                                 V8HI_type_node, V8HI_type_node,
7259                                 V16QI_type_node, NULL_TREE);
7260   tree v16qi_ftype_v16qi_v16qi_v16qi
7261     = build_function_type_list (V16QI_type_node,
7262                                 V16QI_type_node, V16QI_type_node,
7263                                 V16QI_type_node, NULL_TREE);
7264   tree v4si_ftype_int
7265     = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7266   tree v8hi_ftype_int
7267     = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7268   tree v16qi_ftype_int
7269     = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7270   tree v8hi_ftype_v16qi
7271     = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7272   tree v4sf_ftype_v4sf
7273     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7274
7275   tree v2si_ftype_v2si_v2si
7276     = build_function_type_list (opaque_V2SI_type_node,
7277                                 opaque_V2SI_type_node,
7278                                 opaque_V2SI_type_node, NULL_TREE);
7279
7280   tree v2sf_ftype_v2sf_v2sf
7281     = build_function_type_list (opaque_V2SF_type_node,
7282                                 opaque_V2SF_type_node,
7283                                 opaque_V2SF_type_node, NULL_TREE);
7284
7285   tree v2si_ftype_int_int
7286     = build_function_type_list (opaque_V2SI_type_node,
7287                                 integer_type_node, integer_type_node,
7288                                 NULL_TREE);
7289
7290   tree v2si_ftype_v2si
7291     = build_function_type_list (opaque_V2SI_type_node,
7292                                 opaque_V2SI_type_node, NULL_TREE);
7293
7294   tree v2sf_ftype_v2sf
7295     = build_function_type_list (opaque_V2SF_type_node,
7296                                 opaque_V2SF_type_node, NULL_TREE);
7297
7298   tree v2sf_ftype_v2si
7299     = build_function_type_list (opaque_V2SF_type_node,
7300                                 opaque_V2SI_type_node, NULL_TREE);
7301
7302   tree v2si_ftype_v2sf
7303     = build_function_type_list (opaque_V2SI_type_node,
7304                                 opaque_V2SF_type_node, NULL_TREE);
7305
7306   tree v2si_ftype_v2si_char
7307     = build_function_type_list (opaque_V2SI_type_node,
7308                                 opaque_V2SI_type_node,
7309                                 char_type_node, NULL_TREE);
7310
7311   tree v2si_ftype_int_char
7312     = build_function_type_list (opaque_V2SI_type_node,
7313                                 integer_type_node, char_type_node, NULL_TREE);
7314
7315   tree v2si_ftype_char
7316     = build_function_type_list (opaque_V2SI_type_node,
7317                                 char_type_node, NULL_TREE);
7318
7319   tree int_ftype_int_int
7320     = build_function_type_list (integer_type_node,
7321                                 integer_type_node, integer_type_node,
7322                                 NULL_TREE);
7323
7324   tree v4si_ftype_v4si_v4si
7325     = build_function_type_list (V4SI_type_node,
7326                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7327   tree v4sf_ftype_v4si_int
7328     = build_function_type_list (V4SF_type_node,
7329                                 V4SI_type_node, integer_type_node, NULL_TREE);
7330   tree v4si_ftype_v4sf_int
7331     = build_function_type_list (V4SI_type_node,
7332                                 V4SF_type_node, integer_type_node, NULL_TREE);
7333   tree v4si_ftype_v4si_int
7334     = build_function_type_list (V4SI_type_node,
7335                                 V4SI_type_node, integer_type_node, NULL_TREE);
7336   tree v8hi_ftype_v8hi_int
7337     = build_function_type_list (V8HI_type_node,
7338                                 V8HI_type_node, integer_type_node, NULL_TREE);
7339   tree v16qi_ftype_v16qi_int
7340     = build_function_type_list (V16QI_type_node,
7341                                 V16QI_type_node, integer_type_node, NULL_TREE);
7342   tree v16qi_ftype_v16qi_v16qi_int
7343     = build_function_type_list (V16QI_type_node,
7344                                 V16QI_type_node, V16QI_type_node,
7345                                 integer_type_node, NULL_TREE);
7346   tree v8hi_ftype_v8hi_v8hi_int
7347     = build_function_type_list (V8HI_type_node,
7348                                 V8HI_type_node, V8HI_type_node,
7349                                 integer_type_node, NULL_TREE);
7350   tree v4si_ftype_v4si_v4si_int
7351     = build_function_type_list (V4SI_type_node,
7352                                 V4SI_type_node, V4SI_type_node,
7353                                 integer_type_node, NULL_TREE);
7354   tree v4sf_ftype_v4sf_v4sf_int
7355     = build_function_type_list (V4SF_type_node,
7356                                 V4SF_type_node, V4SF_type_node,
7357                                 integer_type_node, NULL_TREE);
7358   tree v4sf_ftype_v4sf_v4sf
7359     = build_function_type_list (V4SF_type_node,
7360                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7361   tree v4sf_ftype_v4sf_v4sf_v4si
7362     = build_function_type_list (V4SF_type_node,
7363                                 V4SF_type_node, V4SF_type_node,
7364                                 V4SI_type_node, NULL_TREE);
7365   tree v4sf_ftype_v4sf_v4sf_v4sf
7366     = build_function_type_list (V4SF_type_node,
7367                                 V4SF_type_node, V4SF_type_node,
7368                                 V4SF_type_node, NULL_TREE);
7369   tree v4si_ftype_v4si_v4si_v4si
7370     = build_function_type_list (V4SI_type_node,
7371                                 V4SI_type_node, V4SI_type_node,
7372                                 V4SI_type_node, NULL_TREE);
7373   tree v8hi_ftype_v8hi_v8hi
7374     = build_function_type_list (V8HI_type_node,
7375                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7376   tree v8hi_ftype_v8hi_v8hi_v8hi
7377     = build_function_type_list (V8HI_type_node,
7378                                 V8HI_type_node, V8HI_type_node,
7379                                 V8HI_type_node, NULL_TREE);
7380  tree v4si_ftype_v8hi_v8hi_v4si
7381     = build_function_type_list (V4SI_type_node,
7382                                 V8HI_type_node, V8HI_type_node,
7383                                 V4SI_type_node, NULL_TREE);
7384  tree v4si_ftype_v16qi_v16qi_v4si
7385     = build_function_type_list (V4SI_type_node,
7386                                 V16QI_type_node, V16QI_type_node,
7387                                 V4SI_type_node, NULL_TREE);
7388   tree v16qi_ftype_v16qi_v16qi
7389     = build_function_type_list (V16QI_type_node,
7390                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7391   tree v4si_ftype_v4sf_v4sf
7392     = build_function_type_list (V4SI_type_node,
7393                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7394   tree v8hi_ftype_v16qi_v16qi
7395     = build_function_type_list (V8HI_type_node,
7396                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7397   tree v4si_ftype_v8hi_v8hi
7398     = build_function_type_list (V4SI_type_node,
7399                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7400   tree v8hi_ftype_v4si_v4si
7401     = build_function_type_list (V8HI_type_node,
7402                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7403   tree v16qi_ftype_v8hi_v8hi
7404     = build_function_type_list (V16QI_type_node,
7405                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7406   tree v4si_ftype_v16qi_v4si
7407     = build_function_type_list (V4SI_type_node,
7408                                 V16QI_type_node, V4SI_type_node, NULL_TREE);
7409   tree v4si_ftype_v16qi_v16qi
7410     = build_function_type_list (V4SI_type_node,
7411                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7412   tree v4si_ftype_v8hi_v4si
7413     = build_function_type_list (V4SI_type_node,
7414                                 V8HI_type_node, V4SI_type_node, NULL_TREE);
7415   tree v4si_ftype_v8hi
7416     = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7417   tree int_ftype_v4si_v4si
7418     = build_function_type_list (integer_type_node,
7419                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7420   tree int_ftype_v4sf_v4sf
7421     = build_function_type_list (integer_type_node,
7422                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7423   tree int_ftype_v16qi_v16qi
7424     = build_function_type_list (integer_type_node,
7425                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7426   tree int_ftype_v8hi_v8hi
7427     = build_function_type_list (integer_type_node,
7428                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7429
7430   /* Add the simple ternary operators.  */
7431   d = (struct builtin_description *) bdesc_3arg;
7432   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7433     {
7434
7435       enum machine_mode mode0, mode1, mode2, mode3;
7436       tree type;
7437
7438       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7439         continue;
7440
7441       mode0 = insn_data[d->icode].operand[0].mode;
7442       mode1 = insn_data[d->icode].operand[1].mode;
7443       mode2 = insn_data[d->icode].operand[2].mode;
7444       mode3 = insn_data[d->icode].operand[3].mode;
7445
7446       /* When all four are of the same mode.  */
7447       if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7448         {
7449           switch (mode0)
7450             {
7451             case V4SImode:
7452               type = v4si_ftype_v4si_v4si_v4si;
7453               break;
7454             case V4SFmode:
7455               type = v4sf_ftype_v4sf_v4sf_v4sf;
7456               break;
7457             case V8HImode:
7458               type = v8hi_ftype_v8hi_v8hi_v8hi;
7459               break;
7460             case V16QImode:
7461               type = v16qi_ftype_v16qi_v16qi_v16qi;
7462               break;
7463             default:
7464               abort();
7465             }
7466         }
7467       else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7468         {
7469           switch (mode0)
7470             {
7471             case V4SImode:
7472               type = v4si_ftype_v4si_v4si_v16qi;
7473               break;
7474             case V4SFmode:
7475               type = v4sf_ftype_v4sf_v4sf_v16qi;
7476               break;
7477             case V8HImode:
7478               type = v8hi_ftype_v8hi_v8hi_v16qi;
7479               break;
7480             case V16QImode:
7481               type = v16qi_ftype_v16qi_v16qi_v16qi;
7482               break;
7483             default:
7484               abort();
7485             }
7486         }
7487       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7488                && mode3 == V4SImode)
7489         type = v4si_ftype_v16qi_v16qi_v4si;
7490       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7491                && mode3 == V4SImode)
7492         type = v4si_ftype_v8hi_v8hi_v4si;
7493       else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7494                && mode3 == V4SImode)
7495         type = v4sf_ftype_v4sf_v4sf_v4si;
7496
7497       /* vchar, vchar, vchar, 4 bit literal.  */
7498       else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7499                && mode3 == QImode)
7500         type = v16qi_ftype_v16qi_v16qi_int;
7501
7502       /* vshort, vshort, vshort, 4 bit literal.  */
7503       else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7504                && mode3 == QImode)
7505         type = v8hi_ftype_v8hi_v8hi_int;
7506
7507       /* vint, vint, vint, 4 bit literal.  */
7508       else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7509                && mode3 == QImode)
7510         type = v4si_ftype_v4si_v4si_int;
7511
7512       /* vfloat, vfloat, vfloat, 4 bit literal.  */
7513       else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7514                && mode3 == QImode)
7515         type = v4sf_ftype_v4sf_v4sf_int;
7516
7517       else
7518         abort ();
7519
7520       def_builtin (d->mask, d->name, type, d->code);
7521     }
7522
7523   /* Add the simple binary operators.  */
7524   d = (struct builtin_description *) bdesc_2arg;
7525   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7526     {
7527       enum machine_mode mode0, mode1, mode2;
7528       tree type;
7529
7530       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7531         continue;
7532
7533       mode0 = insn_data[d->icode].operand[0].mode;
7534       mode1 = insn_data[d->icode].operand[1].mode;
7535       mode2 = insn_data[d->icode].operand[2].mode;
7536
7537       /* When all three operands are of the same mode.  */
7538       if (mode0 == mode1 && mode1 == mode2)
7539         {
7540           switch (mode0)
7541             {
7542             case V4SFmode:
7543               type = v4sf_ftype_v4sf_v4sf;
7544               break;
7545             case V4SImode:
7546               type = v4si_ftype_v4si_v4si;
7547               break;
7548             case V16QImode:
7549               type = v16qi_ftype_v16qi_v16qi;
7550               break;
7551             case V8HImode:
7552               type = v8hi_ftype_v8hi_v8hi;
7553               break;
7554             case V2SImode:
7555               type = v2si_ftype_v2si_v2si;
7556               break;
7557             case V2SFmode:
7558               type = v2sf_ftype_v2sf_v2sf;
7559               break;
7560             case SImode:
7561               type = int_ftype_int_int;
7562               break;
7563             default:
7564               abort ();
7565             }
7566         }
7567
7568       /* A few other combos we really don't want to do manually.  */
7569
7570       /* vint, vfloat, vfloat.  */
7571       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7572         type = v4si_ftype_v4sf_v4sf;
7573
7574       /* vshort, vchar, vchar.  */
7575       else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7576         type = v8hi_ftype_v16qi_v16qi;
7577
7578       /* vint, vshort, vshort.  */
7579       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7580         type = v4si_ftype_v8hi_v8hi;
7581
7582       /* vshort, vint, vint.  */
7583       else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7584         type = v8hi_ftype_v4si_v4si;
7585
7586       /* vchar, vshort, vshort.  */
7587       else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7588         type = v16qi_ftype_v8hi_v8hi;
7589
7590       /* vint, vchar, vint.  */
7591       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7592         type = v4si_ftype_v16qi_v4si;
7593
7594       /* vint, vchar, vchar.  */
7595       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7596         type = v4si_ftype_v16qi_v16qi;
7597
7598       /* vint, vshort, vint.  */
7599       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7600         type = v4si_ftype_v8hi_v4si;
7601
7602       /* vint, vint, 5 bit literal.  */
7603       else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7604         type = v4si_ftype_v4si_int;
7605
7606       /* vshort, vshort, 5 bit literal.  */
7607       else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7608         type = v8hi_ftype_v8hi_int;
7609
7610       /* vchar, vchar, 5 bit literal.  */
7611       else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7612         type = v16qi_ftype_v16qi_int;
7613
7614       /* vfloat, vint, 5 bit literal.  */
7615       else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7616         type = v4sf_ftype_v4si_int;
7617
7618       /* vint, vfloat, 5 bit literal.  */
7619       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7620         type = v4si_ftype_v4sf_int;
7621
7622       else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7623         type = v2si_ftype_int_int;
7624
7625       else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7626         type = v2si_ftype_v2si_char;
7627
7628       else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7629         type = v2si_ftype_int_char;
7630
7631       /* int, x, x.  */
7632       else if (mode0 == SImode)
7633         {
7634           switch (mode1)
7635             {
7636             case V4SImode:
7637               type = int_ftype_v4si_v4si;
7638               break;
7639             case V4SFmode:
7640               type = int_ftype_v4sf_v4sf;
7641               break;
7642             case V16QImode:
7643               type = int_ftype_v16qi_v16qi;
7644               break;
7645             case V8HImode:
7646               type = int_ftype_v8hi_v8hi;
7647               break;
7648             default:
7649               abort ();
7650             }
7651         }
7652
7653       else
7654         abort ();
7655
7656       def_builtin (d->mask, d->name, type, d->code);
7657     }
7658
7659   /* Add the simple unary operators.  */
7660   d = (struct builtin_description *) bdesc_1arg;
7661   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7662     {
7663       enum machine_mode mode0, mode1;
7664       tree type;
7665
7666       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7667         continue;
7668
7669       mode0 = insn_data[d->icode].operand[0].mode;
7670       mode1 = insn_data[d->icode].operand[1].mode;
7671
7672       if (mode0 == V4SImode && mode1 == QImode)
7673         type = v4si_ftype_int;
7674       else if (mode0 == V8HImode && mode1 == QImode)
7675         type = v8hi_ftype_int;
7676       else if (mode0 == V16QImode && mode1 == QImode)
7677         type = v16qi_ftype_int;
7678       else if (mode0 == V4SFmode && mode1 == V4SFmode)
7679         type = v4sf_ftype_v4sf;
7680       else if (mode0 == V8HImode && mode1 == V16QImode)
7681         type = v8hi_ftype_v16qi;
7682       else if (mode0 == V4SImode && mode1 == V8HImode)
7683         type = v4si_ftype_v8hi;
7684       else if (mode0 == V2SImode && mode1 == V2SImode)
7685         type = v2si_ftype_v2si;
7686       else if (mode0 == V2SFmode && mode1 == V2SFmode)
7687         type = v2sf_ftype_v2sf;
7688       else if (mode0 == V2SFmode && mode1 == V2SImode)
7689         type = v2sf_ftype_v2si;
7690       else if (mode0 == V2SImode && mode1 == V2SFmode)
7691         type = v2si_ftype_v2sf;
7692       else if (mode0 == V2SImode && mode1 == QImode)
7693         type = v2si_ftype_char;
7694       else
7695         abort ();
7696
7697       def_builtin (d->mask, d->name, type, d->code);
7698     }
7699 }
7700
7701 static void
7702 rs6000_init_libfuncs (void)
7703 {
7704   if (!TARGET_HARD_FLOAT)
7705     return;
7706
7707   if (DEFAULT_ABI != ABI_V4)
7708     {
7709       if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7710         {
7711           /* AIX library routines for float->int conversion.  */
7712           set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7713           set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7714           set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
7715           set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
7716         }
7717
7718       /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines.  */
7719       set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7720       set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7721       set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7722       set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7723     }
7724   else
7725     {
7726       /* 32-bit SVR4 quad floating point routines.  */
7727
7728       set_optab_libfunc (add_optab, TFmode, "_q_add");
7729       set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7730       set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7731       set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7732       set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7733       if (TARGET_PPC_GPOPT || TARGET_POWER2)
7734         set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7735
7736       set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7737       set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7738       set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7739       set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7740       set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7741       set_optab_libfunc (le_optab, TFmode, "_q_fle");
7742
7743       set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7744       set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7745       set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7746       set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7747       set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7748       set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7749       set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7750     }
7751 }
7752 \f
7753 /* Expand a block move operation, and return 1 if successful.  Return 0
7754    if we should let the compiler generate normal code.
7755
7756    operands[0] is the destination
7757    operands[1] is the source
7758    operands[2] is the length
7759    operands[3] is the alignment */
7760
7761 #define MAX_MOVE_REG 4
7762
7763 int
7764 expand_block_move (rtx operands[])
7765 {
7766   rtx orig_dest = operands[0];
7767   rtx orig_src  = operands[1];
7768   rtx bytes_rtx = operands[2];
7769   rtx align_rtx = operands[3];
7770   int constp    = (GET_CODE (bytes_rtx) == CONST_INT);
7771   int align;
7772   int bytes;
7773   int offset;
7774   int move_bytes;
7775   rtx stores[MAX_MOVE_REG];
7776   int num_reg = 0;
7777
7778   /* If this is not a fixed size move, just call memcpy */
7779   if (! constp)
7780     return 0;
7781
7782   /* If this is not a fixed size alignment, abort */
7783   if (GET_CODE (align_rtx) != CONST_INT)
7784     abort ();
7785   align = INTVAL (align_rtx);
7786
7787   /* Anything to move? */
7788   bytes = INTVAL (bytes_rtx);
7789   if (bytes <= 0)
7790     return 1;
7791
7792   /* store_one_arg depends on expand_block_move to handle at least the size of
7793      reg_parm_stack_space.  */
7794   if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7795     return 0;
7796
7797   for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7798     {
7799       union {
7800         rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7801         rtx (*mov) (rtx, rtx);
7802       } gen_func;
7803       enum machine_mode mode = BLKmode;
7804       rtx src, dest;
7805
7806       if (TARGET_STRING
7807           && bytes > 24         /* move up to 32 bytes at a time */
7808           && ! fixed_regs[5]
7809           && ! fixed_regs[6]
7810           && ! fixed_regs[7]
7811           && ! fixed_regs[8]
7812           && ! fixed_regs[9]
7813           && ! fixed_regs[10]
7814           && ! fixed_regs[11]
7815           && ! fixed_regs[12])
7816         {
7817           move_bytes = (bytes > 32) ? 32 : bytes;
7818           gen_func.movstrsi = gen_movstrsi_8reg;
7819         }
7820       else if (TARGET_STRING
7821                && bytes > 16    /* move up to 24 bytes at a time */
7822                && ! fixed_regs[5]
7823                && ! fixed_regs[6]
7824                && ! fixed_regs[7]
7825                && ! fixed_regs[8]
7826                && ! fixed_regs[9]
7827                && ! fixed_regs[10])
7828         {
7829           move_bytes = (bytes > 24) ? 24 : bytes;
7830           gen_func.movstrsi = gen_movstrsi_6reg;
7831         }
7832       else if (TARGET_STRING
7833                && bytes > 8     /* move up to 16 bytes at a time */
7834                && ! fixed_regs[5]
7835                && ! fixed_regs[6]
7836                && ! fixed_regs[7]
7837                && ! fixed_regs[8])
7838         {
7839           move_bytes = (bytes > 16) ? 16 : bytes;
7840           gen_func.movstrsi = gen_movstrsi_4reg;
7841         }
7842       else if (bytes >= 8 && TARGET_POWERPC64
7843                /* 64-bit loads and stores require word-aligned
7844                   displacements.  */
7845                && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7846         {
7847           move_bytes = 8;
7848           mode = DImode;
7849           gen_func.mov = gen_movdi;
7850         }
7851       else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7852         {                       /* move up to 8 bytes at a time */
7853           move_bytes = (bytes > 8) ? 8 : bytes;
7854           gen_func.movstrsi = gen_movstrsi_2reg;
7855         }
7856       else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7857         {                       /* move 4 bytes */
7858           move_bytes = 4;
7859           mode = SImode;
7860           gen_func.mov = gen_movsi;
7861         }
7862       else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7863         {                       /* move 2 bytes */
7864           move_bytes = 2;
7865           mode = HImode;
7866           gen_func.mov = gen_movhi;
7867         }
7868       else if (TARGET_STRING && bytes > 1)
7869         {                       /* move up to 4 bytes at a time */
7870           move_bytes = (bytes > 4) ? 4 : bytes;
7871           gen_func.movstrsi = gen_movstrsi_1reg;
7872         }
7873       else /* move 1 byte at a time */
7874         {
7875           move_bytes = 1;
7876           mode = QImode;
7877           gen_func.mov = gen_movqi;
7878         }
7879
7880       src = adjust_address (orig_src, mode, offset);
7881       dest = adjust_address (orig_dest, mode, offset);
7882
7883       if (mode != BLKmode)
7884         {
7885           rtx tmp_reg = gen_reg_rtx (mode);
7886
7887           emit_insn ((*gen_func.mov) (tmp_reg, src));
7888           stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7889         }
7890
7891       if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7892         {
7893           int i;
7894           for (i = 0; i < num_reg; i++)
7895             emit_insn (stores[i]);
7896           num_reg = 0;
7897         }
7898
7899       if (mode == BLKmode)
7900         {
7901           /* Move the address into scratch registers.  The movstrsi
7902              patterns require zero offset.  */
7903           if (!REG_P (XEXP (src, 0)))
7904             {
7905               rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7906               src = replace_equiv_address (src, src_reg);
7907             }
7908           set_mem_size (src, GEN_INT (move_bytes));
7909
7910           if (!REG_P (XEXP (dest, 0)))
7911             {
7912               rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7913               dest = replace_equiv_address (dest, dest_reg);
7914             }
7915           set_mem_size (dest, GEN_INT (move_bytes));
7916
7917           emit_insn ((*gen_func.movstrsi) (dest, src,
7918                                            GEN_INT (move_bytes & 31),
7919                                            align_rtx));
7920         }
7921     }
7922
7923   return 1;
7924 }
7925
7926 \f
7927 /* Return 1 if OP is a load multiple operation.  It is known to be a
7928    PARALLEL and the first section will be tested.  */
7929
7930 int
7931 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7932 {
7933   int count = XVECLEN (op, 0);
7934   unsigned int dest_regno;
7935   rtx src_addr;
7936   int i;
7937
7938   /* Perform a quick check so we don't blow up below.  */
7939   if (count <= 1
7940       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7941       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7942       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7943     return 0;
7944
7945   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7946   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7947
7948   for (i = 1; i < count; i++)
7949     {
7950       rtx elt = XVECEXP (op, 0, i);
7951
7952       if (GET_CODE (elt) != SET
7953           || GET_CODE (SET_DEST (elt)) != REG
7954           || GET_MODE (SET_DEST (elt)) != SImode
7955           || REGNO (SET_DEST (elt)) != dest_regno + i
7956           || GET_CODE (SET_SRC (elt)) != MEM
7957           || GET_MODE (SET_SRC (elt)) != SImode
7958           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7959           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7960           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7961           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7962         return 0;
7963     }
7964
7965   return 1;
7966 }
7967
7968 /* Similar, but tests for store multiple.  Here, the second vector element
7969    is a CLOBBER.  It will be tested later.  */
7970
7971 int
7972 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7973 {
7974   int count = XVECLEN (op, 0) - 1;
7975   unsigned int src_regno;
7976   rtx dest_addr;
7977   int i;
7978
7979   /* Perform a quick check so we don't blow up below.  */
7980   if (count <= 1
7981       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7982       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7983       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7984     return 0;
7985
7986   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7987   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7988
7989   for (i = 1; i < count; i++)
7990     {
7991       rtx elt = XVECEXP (op, 0, i + 1);
7992
7993       if (GET_CODE (elt) != SET
7994           || GET_CODE (SET_SRC (elt)) != REG
7995           || GET_MODE (SET_SRC (elt)) != SImode
7996           || REGNO (SET_SRC (elt)) != src_regno + i
7997           || GET_CODE (SET_DEST (elt)) != MEM
7998           || GET_MODE (SET_DEST (elt)) != SImode
7999           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
8000           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
8001           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
8002           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
8003         return 0;
8004     }
8005
8006   return 1;
8007 }
8008
8009 /* Return a string to perform a load_multiple operation.
8010    operands[0] is the vector.
8011    operands[1] is the source address.
8012    operands[2] is the first destination register.  */
8013
8014 const char *
8015 rs6000_output_load_multiple (rtx operands[3])
8016 {
8017   /* We have to handle the case where the pseudo used to contain the address
8018      is assigned to one of the output registers.  */
8019   int i, j;
8020   int words = XVECLEN (operands[0], 0);
8021   rtx xop[10];
8022
8023   if (XVECLEN (operands[0], 0) == 1)
8024     return "{l|lwz} %2,0(%1)";
8025
8026   for (i = 0; i < words; i++)
8027     if (refers_to_regno_p (REGNO (operands[2]) + i,
8028                            REGNO (operands[2]) + i + 1, operands[1], 0))
8029       {
8030         if (i == words-1)
8031           {
8032             xop[0] = GEN_INT (4 * (words-1));
8033             xop[1] = operands[1];
8034             xop[2] = operands[2];
8035             output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8036             return "";
8037           }
8038         else if (i == 0)
8039           {
8040             xop[0] = GEN_INT (4 * (words-1));
8041             xop[1] = operands[1];
8042             xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8043             output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8044             return "";
8045           }
8046         else
8047           {
8048             for (j = 0; j < words; j++)
8049               if (j != i)
8050                 {
8051                   xop[0] = GEN_INT (j * 4);
8052                   xop[1] = operands[1];
8053                   xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8054                   output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8055                 }
8056             xop[0] = GEN_INT (i * 4);
8057             xop[1] = operands[1];
8058             output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8059             return "";
8060           }
8061       }
8062
8063   return "{lsi|lswi} %2,%1,%N0";
8064 }
8065
8066 /* Return 1 for a parallel vrsave operation.  */
8067
8068 int
8069 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8070 {
8071   int count = XVECLEN (op, 0);
8072   unsigned int dest_regno, src_regno;
8073   int i;
8074
8075   if (count <= 1
8076       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8077       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8078       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
8079     return 0;
8080
8081   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8082   src_regno  = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8083
8084   if (dest_regno != VRSAVE_REGNO
8085       && src_regno != VRSAVE_REGNO)
8086     return 0;
8087
8088   for (i = 1; i < count; i++)
8089     {
8090       rtx elt = XVECEXP (op, 0, i);
8091
8092       if (GET_CODE (elt) != CLOBBER
8093           && GET_CODE (elt) != SET)
8094         return 0;
8095     }
8096
8097   return 1;
8098 }
8099
8100 /* Return 1 for an PARALLEL suitable for mfcr.  */
8101
8102 int
8103 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8104 {
8105   int count = XVECLEN (op, 0);
8106   int i;
8107
8108   /* Perform a quick check so we don't blow up below.  */
8109   if (count < 1
8110       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8111       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8112       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8113     return 0;
8114
8115   for (i = 0; i < count; i++)
8116     {
8117       rtx exp = XVECEXP (op, 0, i);
8118       rtx unspec;
8119       int maskval;
8120       rtx src_reg;
8121
8122       src_reg = XVECEXP (SET_SRC (exp), 0, 0);
8123
8124       if (GET_CODE (src_reg) != REG
8125           || GET_MODE (src_reg) != CCmode
8126           || ! CR_REGNO_P (REGNO (src_reg)))
8127         return 0;
8128
8129       if (GET_CODE (exp) != SET
8130           || GET_CODE (SET_DEST (exp)) != REG
8131           || GET_MODE (SET_DEST (exp)) != SImode
8132           || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
8133         return 0;
8134       unspec = SET_SRC (exp);
8135       maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
8136
8137       if (GET_CODE (unspec) != UNSPEC
8138           || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
8139           || XVECLEN (unspec, 0) != 2
8140           || XVECEXP (unspec, 0, 0) != src_reg
8141           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8142           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8143         return 0;
8144     }
8145   return 1;
8146 }
8147
8148 /* Return 1 for an PARALLEL suitable for mtcrf.  */
8149
8150 int
8151 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8152 {
8153   int count = XVECLEN (op, 0);
8154   int i;
8155   rtx src_reg;
8156
8157   /* Perform a quick check so we don't blow up below.  */
8158   if (count < 1
8159       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8160       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8161       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8162     return 0;
8163   src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
8164
8165   if (GET_CODE (src_reg) != REG
8166       || GET_MODE (src_reg) != SImode
8167       || ! INT_REGNO_P (REGNO (src_reg)))
8168     return 0;
8169
8170   for (i = 0; i < count; i++)
8171     {
8172       rtx exp = XVECEXP (op, 0, i);
8173       rtx unspec;
8174       int maskval;
8175
8176       if (GET_CODE (exp) != SET
8177           || GET_CODE (SET_DEST (exp)) != REG
8178           || GET_MODE (SET_DEST (exp)) != CCmode
8179           || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
8180         return 0;
8181       unspec = SET_SRC (exp);
8182       maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
8183
8184       if (GET_CODE (unspec) != UNSPEC
8185           || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
8186           || XVECLEN (unspec, 0) != 2
8187           || XVECEXP (unspec, 0, 0) != src_reg
8188           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8189           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8190         return 0;
8191     }
8192   return 1;
8193 }
8194
8195 /* Return 1 for an PARALLEL suitable for lmw.  */
8196
8197 int
8198 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8199 {
8200   int count = XVECLEN (op, 0);
8201   unsigned int dest_regno;
8202   rtx src_addr;
8203   unsigned int base_regno;
8204   HOST_WIDE_INT offset;
8205   int i;
8206
8207   /* Perform a quick check so we don't blow up below.  */
8208   if (count <= 1
8209       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8210       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8211       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8212     return 0;
8213
8214   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8215   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8216
8217   if (dest_regno > 31
8218       || count != 32 - (int) dest_regno)
8219     return 0;
8220
8221   if (legitimate_indirect_address_p (src_addr, 0))
8222     {
8223       offset = 0;
8224       base_regno = REGNO (src_addr);
8225       if (base_regno == 0)
8226         return 0;
8227     }
8228   else if (legitimate_offset_address_p (SImode, src_addr, 0))
8229     {
8230       offset = INTVAL (XEXP (src_addr, 1));
8231       base_regno = REGNO (XEXP (src_addr, 0));
8232     }
8233   else
8234     return 0;
8235
8236   for (i = 0; i < count; i++)
8237     {
8238       rtx elt = XVECEXP (op, 0, i);
8239       rtx newaddr;
8240       rtx addr_reg;
8241       HOST_WIDE_INT newoffset;
8242
8243       if (GET_CODE (elt) != SET
8244           || GET_CODE (SET_DEST (elt)) != REG
8245           || GET_MODE (SET_DEST (elt)) != SImode
8246           || REGNO (SET_DEST (elt)) != dest_regno + i
8247           || GET_CODE (SET_SRC (elt)) != MEM
8248           || GET_MODE (SET_SRC (elt)) != SImode)
8249         return 0;
8250       newaddr = XEXP (SET_SRC (elt), 0);
8251       if (legitimate_indirect_address_p (newaddr, 0))
8252         {
8253           newoffset = 0;
8254           addr_reg = newaddr;
8255         }
8256       else if (legitimate_offset_address_p (SImode, newaddr, 0))
8257         {
8258           addr_reg = XEXP (newaddr, 0);
8259           newoffset = INTVAL (XEXP (newaddr, 1));
8260         }
8261       else
8262         return 0;
8263       if (REGNO (addr_reg) != base_regno
8264           || newoffset != offset + 4 * i)
8265         return 0;
8266     }
8267
8268   return 1;
8269 }
8270
8271 /* Return 1 for an PARALLEL suitable for stmw.  */
8272
8273 int
8274 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8275 {
8276   int count = XVECLEN (op, 0);
8277   unsigned int src_regno;
8278   rtx dest_addr;
8279   unsigned int base_regno;
8280   HOST_WIDE_INT offset;
8281   int i;
8282
8283   /* Perform a quick check so we don't blow up below.  */
8284   if (count <= 1
8285       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8286       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8287       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8288     return 0;
8289
8290   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8291   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8292
8293   if (src_regno > 31
8294       || count != 32 - (int) src_regno)
8295     return 0;
8296
8297   if (legitimate_indirect_address_p (dest_addr, 0))
8298     {
8299       offset = 0;
8300       base_regno = REGNO (dest_addr);
8301       if (base_regno == 0)
8302         return 0;
8303     }
8304   else if (legitimate_offset_address_p (SImode, dest_addr, 0))
8305     {
8306       offset = INTVAL (XEXP (dest_addr, 1));
8307       base_regno = REGNO (XEXP (dest_addr, 0));
8308     }
8309   else
8310     return 0;
8311
8312   for (i = 0; i < count; i++)
8313     {
8314       rtx elt = XVECEXP (op, 0, i);
8315       rtx newaddr;
8316       rtx addr_reg;
8317       HOST_WIDE_INT newoffset;
8318
8319       if (GET_CODE (elt) != SET
8320           || GET_CODE (SET_SRC (elt)) != REG
8321           || GET_MODE (SET_SRC (elt)) != SImode
8322           || REGNO (SET_SRC (elt)) != src_regno + i
8323           || GET_CODE (SET_DEST (elt)) != MEM
8324           || GET_MODE (SET_DEST (elt)) != SImode)
8325         return 0;
8326       newaddr = XEXP (SET_DEST (elt), 0);
8327       if (legitimate_indirect_address_p (newaddr, 0))
8328         {
8329           newoffset = 0;
8330           addr_reg = newaddr;
8331         }
8332       else if (legitimate_offset_address_p (SImode, newaddr, 0))
8333         {
8334           addr_reg = XEXP (newaddr, 0);
8335           newoffset = INTVAL (XEXP (newaddr, 1));
8336         }
8337       else
8338         return 0;
8339       if (REGNO (addr_reg) != base_regno
8340           || newoffset != offset + 4 * i)
8341         return 0;
8342     }
8343
8344   return 1;
8345 }
8346 \f
8347 /* A validation routine: say whether CODE, a condition code, and MODE
8348    match.  The other alternatives either don't make sense or should
8349    never be generated.  */
8350
8351 static void
8352 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8353 {
8354   if ((GET_RTX_CLASS (code) != RTX_COMPARE
8355        && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8356       || GET_MODE_CLASS (mode) != MODE_CC)
8357     abort ();
8358
8359   /* These don't make sense.  */
8360   if ((code == GT || code == LT || code == GE || code == LE)
8361       && mode == CCUNSmode)
8362     abort ();
8363
8364   if ((code == GTU || code == LTU || code == GEU || code == LEU)
8365       && mode != CCUNSmode)
8366     abort ();
8367
8368   if (mode != CCFPmode
8369       && (code == ORDERED || code == UNORDERED
8370           || code == UNEQ || code == LTGT
8371           || code == UNGT || code == UNLT
8372           || code == UNGE || code == UNLE))
8373     abort ();
8374
8375   /* These should never be generated except for
8376      flag_finite_math_only.  */
8377   if (mode == CCFPmode
8378       && ! flag_finite_math_only
8379       && (code == LE || code == GE
8380           || code == UNEQ || code == LTGT
8381           || code == UNGT || code == UNLT))
8382     abort ();
8383
8384   /* These are invalid; the information is not there.  */
8385   if (mode == CCEQmode
8386       && code != EQ && code != NE)
8387     abort ();
8388 }
8389
8390 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
8391    We only check the opcode against the mode of the CC value here.  */
8392
8393 int
8394 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8395 {
8396   enum rtx_code code = GET_CODE (op);
8397   enum machine_mode cc_mode;
8398
8399   if (!COMPARISON_P (op))
8400     return 0;
8401
8402   cc_mode = GET_MODE (XEXP (op, 0));
8403   if (GET_MODE_CLASS (cc_mode) != MODE_CC)
8404     return 0;
8405
8406   validate_condition_mode (code, cc_mode);
8407
8408   return 1;
8409 }
8410
8411 /* Return 1 if OP is a comparison operation that is valid for a branch
8412    insn and which is true if the corresponding bit in the CC register
8413    is set.  */
8414
8415 int
8416 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
8417 {
8418   enum rtx_code code;
8419
8420   if (! branch_comparison_operator (op, mode))
8421     return 0;
8422
8423   code = GET_CODE (op);
8424   return (code == EQ || code == LT || code == GT
8425           || code == LTU || code == GTU
8426           || code == UNORDERED);
8427 }
8428
8429 /* Return 1 if OP is a comparison operation that is valid for an scc
8430    insn: it must be a positive comparison.  */
8431
8432 int
8433 scc_comparison_operator (rtx op, enum machine_mode mode)
8434 {
8435   return branch_positive_comparison_operator (op, mode);
8436 }
8437
8438 int
8439 trap_comparison_operator (rtx op, enum machine_mode mode)
8440 {
8441   if (mode != VOIDmode && mode != GET_MODE (op))
8442     return 0;
8443   return COMPARISON_P (op);
8444 }
8445
8446 int
8447 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8448 {
8449   enum rtx_code code = GET_CODE (op);
8450   return (code == AND || code == IOR || code == XOR);
8451 }
8452
8453 int
8454 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8455 {
8456   enum rtx_code code = GET_CODE (op);
8457   return (code == IOR || code == XOR);
8458 }
8459
8460 int
8461 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8462 {
8463   enum rtx_code code = GET_CODE (op);
8464   return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8465 }
8466 \f
8467 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8468    mask required to convert the result of a rotate insn into a shift
8469    left insn of SHIFTOP bits.  Both are known to be SImode CONST_INT.  */
8470
8471 int
8472 includes_lshift_p (rtx shiftop, rtx andop)
8473 {
8474   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8475
8476   shift_mask <<= INTVAL (shiftop);
8477
8478   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8479 }
8480
8481 /* Similar, but for right shift.  */
8482
8483 int
8484 includes_rshift_p (rtx shiftop, rtx andop)
8485 {
8486   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8487
8488   shift_mask >>= INTVAL (shiftop);
8489
8490   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8491 }
8492
8493 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8494    to perform a left shift.  It must have exactly SHIFTOP least
8495    significant 0's, then one or more 1's, then zero or more 0's.  */
8496
8497 int
8498 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8499 {
8500   if (GET_CODE (andop) == CONST_INT)
8501     {
8502       HOST_WIDE_INT c, lsb, shift_mask;
8503
8504       c = INTVAL (andop);
8505       if (c == 0 || c == ~0)
8506         return 0;
8507
8508       shift_mask = ~0;
8509       shift_mask <<= INTVAL (shiftop);
8510
8511       /* Find the least significant one bit.  */
8512       lsb = c & -c;
8513
8514       /* It must coincide with the LSB of the shift mask.  */
8515       if (-lsb != shift_mask)
8516         return 0;
8517
8518       /* Invert to look for the next transition (if any).  */
8519       c = ~c;
8520
8521       /* Remove the low group of ones (originally low group of zeros).  */
8522       c &= -lsb;
8523
8524       /* Again find the lsb, and check we have all 1's above.  */
8525       lsb = c & -c;
8526       return c == -lsb;
8527     }
8528   else if (GET_CODE (andop) == CONST_DOUBLE
8529            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8530     {
8531       HOST_WIDE_INT low, high, lsb;
8532       HOST_WIDE_INT shift_mask_low, shift_mask_high;
8533
8534       low = CONST_DOUBLE_LOW (andop);
8535       if (HOST_BITS_PER_WIDE_INT < 64)
8536         high = CONST_DOUBLE_HIGH (andop);
8537
8538       if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8539           || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8540         return 0;
8541
8542       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8543         {
8544           shift_mask_high = ~0;
8545           if (INTVAL (shiftop) > 32)
8546             shift_mask_high <<= INTVAL (shiftop) - 32;
8547
8548           lsb = high & -high;
8549
8550           if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8551             return 0;
8552
8553           high = ~high;
8554           high &= -lsb;
8555
8556           lsb = high & -high;
8557           return high == -lsb;
8558         }
8559
8560       shift_mask_low = ~0;
8561       shift_mask_low <<= INTVAL (shiftop);
8562
8563       lsb = low & -low;
8564
8565       if (-lsb != shift_mask_low)
8566         return 0;
8567
8568       if (HOST_BITS_PER_WIDE_INT < 64)
8569         high = ~high;
8570       low = ~low;
8571       low &= -lsb;
8572
8573       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8574         {
8575           lsb = high & -high;
8576           return high == -lsb;
8577         }
8578
8579       lsb = low & -low;
8580       return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8581     }
8582   else
8583     return 0;
8584 }
8585
8586 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8587    to perform a left shift.  It must have SHIFTOP or more least
8588    significant 0's, with the remainder of the word 1's.  */
8589
8590 int
8591 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8592 {
8593   if (GET_CODE (andop) == CONST_INT)
8594     {
8595       HOST_WIDE_INT c, lsb, shift_mask;
8596
8597       shift_mask = ~0;
8598       shift_mask <<= INTVAL (shiftop);
8599       c = INTVAL (andop);
8600
8601       /* Find the least significant one bit.  */
8602       lsb = c & -c;
8603
8604       /* It must be covered by the shift mask.
8605          This test also rejects c == 0.  */
8606       if ((lsb & shift_mask) == 0)
8607         return 0;
8608
8609       /* Check we have all 1's above the transition, and reject all 1's.  */
8610       return c == -lsb && lsb != 1;
8611     }
8612   else if (GET_CODE (andop) == CONST_DOUBLE
8613            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8614     {
8615       HOST_WIDE_INT low, lsb, shift_mask_low;
8616
8617       low = CONST_DOUBLE_LOW (andop);
8618
8619       if (HOST_BITS_PER_WIDE_INT < 64)
8620         {
8621           HOST_WIDE_INT high, shift_mask_high;
8622
8623           high = CONST_DOUBLE_HIGH (andop);
8624
8625           if (low == 0)
8626             {
8627               shift_mask_high = ~0;
8628               if (INTVAL (shiftop) > 32)
8629                 shift_mask_high <<= INTVAL (shiftop) - 32;
8630
8631               lsb = high & -high;
8632
8633               if ((lsb & shift_mask_high) == 0)
8634                 return 0;
8635
8636               return high == -lsb;
8637             }
8638           if (high != ~0)
8639             return 0;
8640         }
8641
8642       shift_mask_low = ~0;
8643       shift_mask_low <<= INTVAL (shiftop);
8644
8645       lsb = low & -low;
8646
8647       if ((lsb & shift_mask_low) == 0)
8648         return 0;
8649
8650       return low == -lsb && lsb != 1;
8651     }
8652   else
8653     return 0;
8654 }
8655
8656 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8657    for lfq and stfq insns iff the registers are hard registers.   */
8658
8659 int
8660 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8661 {
8662   /* We might have been passed a SUBREG.  */
8663   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8664     return 0;
8665
8666   /* We might have been passed non floating point registers.  */
8667   if (!FP_REGNO_P (REGNO (reg1))
8668       || !FP_REGNO_P (REGNO (reg2)))
8669     return 0;
8670
8671   return (REGNO (reg1) == REGNO (reg2) - 1);
8672 }
8673
8674 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8675    addr1 and addr2 must be in consecutive memory locations
8676    (addr2 == addr1 + 8).  */
8677
8678 int
8679 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
8680 {
8681   rtx addr1, addr2;
8682   unsigned int reg1;
8683   int offset1;
8684
8685   /* The mems cannot be volatile.  */
8686   if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8687     return 0;
8688
8689   addr1 = XEXP (mem1, 0);
8690   addr2 = XEXP (mem2, 0);
8691
8692   /* Extract an offset (if used) from the first addr.  */
8693   if (GET_CODE (addr1) == PLUS)
8694     {
8695       /* If not a REG, return zero.  */
8696       if (GET_CODE (XEXP (addr1, 0)) != REG)
8697         return 0;
8698       else
8699         {
8700           reg1 = REGNO (XEXP (addr1, 0));
8701           /* The offset must be constant!  */
8702           if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8703             return 0;
8704           offset1 = INTVAL (XEXP (addr1, 1));
8705         }
8706     }
8707   else if (GET_CODE (addr1) != REG)
8708     return 0;
8709   else
8710     {
8711       reg1 = REGNO (addr1);
8712       /* This was a simple (mem (reg)) expression.  Offset is 0.  */
8713       offset1 = 0;
8714     }
8715
8716   /* Make sure the second address is a (mem (plus (reg) (const_int)))
8717      or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8718      register as addr1.  */
8719   if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8720     return 1;
8721   if (GET_CODE (addr2) != PLUS)
8722     return 0;
8723
8724   if (GET_CODE (XEXP (addr2, 0)) != REG
8725       || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8726     return 0;
8727
8728   if (reg1 != REGNO (XEXP (addr2, 0)))
8729     return 0;
8730
8731   /* The offset for the second addr must be 8 more than the first addr.  */
8732   if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8733     return 0;
8734
8735   /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq
8736      instructions.  */
8737   return 1;
8738 }
8739 \f
8740 /* Return the register class of a scratch register needed to copy IN into
8741    or out of a register in CLASS in MODE.  If it can be done directly,
8742    NO_REGS is returned.  */
8743
8744 enum reg_class
8745 secondary_reload_class (enum reg_class class,
8746                         enum machine_mode mode ATTRIBUTE_UNUSED,
8747                         rtx in)
8748 {
8749   int regno;
8750
8751   if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8752 #if TARGET_MACHO
8753                     && MACHOPIC_INDIRECT
8754 #endif
8755                     ))
8756     {
8757       /* We cannot copy a symbolic operand directly into anything
8758          other than BASE_REGS for TARGET_ELF.  So indicate that a
8759          register from BASE_REGS is needed as an intermediate
8760          register.
8761
8762          On Darwin, pic addresses require a load from memory, which
8763          needs a base register.  */
8764       if (class != BASE_REGS
8765           && (GET_CODE (in) == SYMBOL_REF
8766               || GET_CODE (in) == HIGH
8767               || GET_CODE (in) == LABEL_REF
8768               || GET_CODE (in) == CONST))
8769         return BASE_REGS;
8770     }
8771
8772   if (GET_CODE (in) == REG)
8773     {
8774       regno = REGNO (in);
8775       if (regno >= FIRST_PSEUDO_REGISTER)
8776         {
8777           regno = true_regnum (in);
8778           if (regno >= FIRST_PSEUDO_REGISTER)
8779             regno = -1;
8780         }
8781     }
8782   else if (GET_CODE (in) == SUBREG)
8783     {
8784       regno = true_regnum (in);
8785       if (regno >= FIRST_PSEUDO_REGISTER)
8786         regno = -1;
8787     }
8788   else
8789     regno = -1;
8790
8791   /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8792      into anything.  */
8793   if (class == GENERAL_REGS || class == BASE_REGS
8794       || (regno >= 0 && INT_REGNO_P (regno)))
8795     return NO_REGS;
8796
8797   /* Constants, memory, and FP registers can go into FP registers.  */
8798   if ((regno == -1 || FP_REGNO_P (regno))
8799       && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8800     return NO_REGS;
8801
8802   /* Memory, and AltiVec registers can go into AltiVec registers.  */
8803   if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8804       && class == ALTIVEC_REGS)
8805     return NO_REGS;
8806
8807   /* We can copy among the CR registers.  */
8808   if ((class == CR_REGS || class == CR0_REGS)
8809       && regno >= 0 && CR_REGNO_P (regno))
8810     return NO_REGS;
8811
8812   /* Otherwise, we need GENERAL_REGS.  */
8813   return GENERAL_REGS;
8814 }
8815 \f
8816 /* Given a comparison operation, return the bit number in CCR to test.  We
8817    know this is a valid comparison.
8818
8819    SCC_P is 1 if this is for an scc.  That means that %D will have been
8820    used instead of %C, so the bits will be in different places.
8821
8822    Return -1 if OP isn't a valid comparison for some reason.  */
8823
8824 int
8825 ccr_bit (rtx op, int scc_p)
8826 {
8827   enum rtx_code code = GET_CODE (op);
8828   enum machine_mode cc_mode;
8829   int cc_regnum;
8830   int base_bit;
8831   rtx reg;
8832
8833   if (!COMPARISON_P (op))
8834     return -1;
8835
8836   reg = XEXP (op, 0);
8837
8838   if (GET_CODE (reg) != REG
8839       || ! CR_REGNO_P (REGNO (reg)))
8840     abort ();
8841
8842   cc_mode = GET_MODE (reg);
8843   cc_regnum = REGNO (reg);
8844   base_bit = 4 * (cc_regnum - CR0_REGNO);
8845
8846   validate_condition_mode (code, cc_mode);
8847
8848   /* When generating a sCOND operation, only positive conditions are
8849      allowed.  */
8850   if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8851       && code != GTU && code != LTU)
8852     abort ();
8853
8854   switch (code)
8855     {
8856     case NE:
8857       return scc_p ? base_bit + 3 : base_bit + 2;
8858     case EQ:
8859       return base_bit + 2;
8860     case GT:  case GTU:  case UNLE:
8861       return base_bit + 1;
8862     case LT:  case LTU:  case UNGE:
8863       return base_bit;
8864     case ORDERED:  case UNORDERED:
8865       return base_bit + 3;
8866
8867     case GE:  case GEU:
8868       /* If scc, we will have done a cror to put the bit in the
8869          unordered position.  So test that bit.  For integer, this is ! LT
8870          unless this is an scc insn.  */
8871       return scc_p ? base_bit + 3 : base_bit;
8872
8873     case LE:  case LEU:
8874       return scc_p ? base_bit + 3 : base_bit + 1;
8875
8876     default:
8877       abort ();
8878     }
8879 }
8880 \f
8881 /* Return the GOT register.  */
8882
8883 struct rtx_def *
8884 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8885 {
8886   /* The second flow pass currently (June 1999) can't update
8887      regs_ever_live without disturbing other parts of the compiler, so
8888      update it here to make the prolog/epilogue code happy.  */
8889   if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8890     regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8891
8892   current_function_uses_pic_offset_table = 1;
8893
8894   return pic_offset_table_rtx;
8895 }
8896 \f
8897 /* Function to init struct machine_function.
8898    This will be called, via a pointer variable,
8899    from push_function_context.  */
8900
8901 static struct machine_function *
8902 rs6000_init_machine_status (void)
8903 {
8904   return ggc_alloc_cleared (sizeof (machine_function));
8905 }
8906 \f
8907 /* These macros test for integers and extract the low-order bits.  */
8908 #define INT_P(X)  \
8909 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)    \
8910  && GET_MODE (X) == VOIDmode)
8911
8912 #define INT_LOWPART(X) \
8913   (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8914
8915 int
8916 extract_MB (rtx op)
8917 {
8918   int i;
8919   unsigned long val = INT_LOWPART (op);
8920
8921   /* If the high bit is zero, the value is the first 1 bit we find
8922      from the left.  */
8923   if ((val & 0x80000000) == 0)
8924     {
8925       if ((val & 0xffffffff) == 0)
8926         abort ();
8927
8928       i = 1;
8929       while (((val <<= 1) & 0x80000000) == 0)
8930         ++i;
8931       return i;
8932     }
8933
8934   /* If the high bit is set and the low bit is not, or the mask is all
8935      1's, the value is zero.  */
8936   if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8937     return 0;
8938
8939   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8940      from the right.  */
8941   i = 31;
8942   while (((val >>= 1) & 1) != 0)
8943     --i;
8944
8945   return i;
8946 }
8947
8948 int
8949 extract_ME (rtx op)
8950 {
8951   int i;
8952   unsigned long val = INT_LOWPART (op);
8953
8954   /* If the low bit is zero, the value is the first 1 bit we find from
8955      the right.  */
8956   if ((val & 1) == 0)
8957     {
8958       if ((val & 0xffffffff) == 0)
8959         abort ();
8960
8961       i = 30;
8962       while (((val >>= 1) & 1) == 0)
8963         --i;
8964
8965       return i;
8966     }
8967
8968   /* If the low bit is set and the high bit is not, or the mask is all
8969      1's, the value is 31.  */
8970   if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8971     return 31;
8972
8973   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8974      from the left.  */
8975   i = 0;
8976   while (((val <<= 1) & 0x80000000) != 0)
8977     ++i;
8978
8979   return i;
8980 }
8981
8982 /* Locate some local-dynamic symbol still in use by this function
8983    so that we can print its name in some tls_ld pattern.  */
8984
8985 static const char *
8986 rs6000_get_some_local_dynamic_name (void)
8987 {
8988   rtx insn;
8989
8990   if (cfun->machine->some_ld_name)
8991     return cfun->machine->some_ld_name;
8992
8993   for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8994     if (INSN_P (insn)
8995         && for_each_rtx (&PATTERN (insn),
8996                          rs6000_get_some_local_dynamic_name_1, 0))
8997       return cfun->machine->some_ld_name;
8998
8999   abort ();
9000 }
9001
9002 /* Helper function for rs6000_get_some_local_dynamic_name.  */
9003
9004 static int
9005 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9006 {
9007   rtx x = *px;
9008
9009   if (GET_CODE (x) == SYMBOL_REF)
9010     {
9011       const char *str = XSTR (x, 0);
9012       if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9013         {
9014           cfun->machine->some_ld_name = str;
9015           return 1;
9016         }
9017     }
9018
9019   return 0;
9020 }
9021
9022 /* Print an operand.  Recognize special options, documented below.  */
9023
9024 #if TARGET_ELF
9025 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9026 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9027 #else
9028 #define SMALL_DATA_RELOC "sda21"
9029 #define SMALL_DATA_REG 0
9030 #endif
9031
9032 void
9033 print_operand (FILE *file, rtx x, int code)
9034 {
9035   int i;
9036   HOST_WIDE_INT val;
9037   unsigned HOST_WIDE_INT uval;
9038
9039   switch (code)
9040     {
9041     case '.':
9042       /* Write out an instruction after the call which may be replaced
9043          with glue code by the loader.  This depends on the AIX version.  */
9044       asm_fprintf (file, RS6000_CALL_GLUE);
9045       return;
9046
9047       /* %a is output_address.  */
9048
9049     case 'A':
9050       /* If X is a constant integer whose low-order 5 bits are zero,
9051          write 'l'.  Otherwise, write 'r'.  This is a kludge to fix a bug
9052          in the AIX assembler where "sri" with a zero shift count
9053          writes a trash instruction.  */
9054       if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9055         putc ('l', file);
9056       else
9057         putc ('r', file);
9058       return;
9059
9060     case 'b':
9061       /* If constant, low-order 16 bits of constant, unsigned.
9062          Otherwise, write normally.  */
9063       if (INT_P (x))
9064         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9065       else
9066         print_operand (file, x, 0);
9067       return;
9068
9069     case 'B':
9070       /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9071          for 64-bit mask direction.  */
9072       putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
9073       return;
9074
9075       /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9076          output_operand.  */
9077
9078     case 'c':
9079       /* X is a CR register.  Print the number of the GT bit of the CR.  */
9080       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9081         output_operand_lossage ("invalid %%E value");
9082       else
9083         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9084       return;
9085
9086     case 'D':
9087       /* Like 'J' but get to the GT bit.  */
9088       if (GET_CODE (x) != REG)
9089         abort ();
9090
9091       /* Bit 1 is GT bit.  */
9092       i = 4 * (REGNO (x) - CR0_REGNO) + 1;
9093
9094       /* If we want bit 31, write a shift count of zero, not 32.  */
9095       fprintf (file, "%d", i == 31 ? 0 : i + 1);
9096       return;
9097
9098     case 'E':
9099       /* X is a CR register.  Print the number of the EQ bit of the CR */
9100       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9101         output_operand_lossage ("invalid %%E value");
9102       else
9103         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9104       return;
9105
9106     case 'f':
9107       /* X is a CR register.  Print the shift count needed to move it
9108          to the high-order four bits.  */
9109       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9110         output_operand_lossage ("invalid %%f value");
9111       else
9112         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9113       return;
9114
9115     case 'F':
9116       /* Similar, but print the count for the rotate in the opposite
9117          direction.  */
9118       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9119         output_operand_lossage ("invalid %%F value");
9120       else
9121         fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9122       return;
9123
9124     case 'G':
9125       /* X is a constant integer.  If it is negative, print "m",
9126          otherwise print "z".  This is to make an aze or ame insn.  */
9127       if (GET_CODE (x) != CONST_INT)
9128         output_operand_lossage ("invalid %%G value");
9129       else if (INTVAL (x) >= 0)
9130         putc ('z', file);
9131       else
9132         putc ('m', file);
9133       return;
9134
9135     case 'h':
9136       /* If constant, output low-order five bits.  Otherwise, write
9137          normally.  */
9138       if (INT_P (x))
9139         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9140       else
9141         print_operand (file, x, 0);
9142       return;
9143
9144     case 'H':
9145       /* If constant, output low-order six bits.  Otherwise, write
9146          normally.  */
9147       if (INT_P (x))
9148         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9149       else
9150         print_operand (file, x, 0);
9151       return;
9152
9153     case 'I':
9154       /* Print `i' if this is a constant, else nothing.  */
9155       if (INT_P (x))
9156         putc ('i', file);
9157       return;
9158
9159     case 'j':
9160       /* Write the bit number in CCR for jump.  */
9161       i = ccr_bit (x, 0);
9162       if (i == -1)
9163         output_operand_lossage ("invalid %%j code");
9164       else
9165         fprintf (file, "%d", i);
9166       return;
9167
9168     case 'J':
9169       /* Similar, but add one for shift count in rlinm for scc and pass
9170          scc flag to `ccr_bit'.  */
9171       i = ccr_bit (x, 1);
9172       if (i == -1)
9173         output_operand_lossage ("invalid %%J code");
9174       else
9175         /* If we want bit 31, write a shift count of zero, not 32.  */
9176         fprintf (file, "%d", i == 31 ? 0 : i + 1);
9177       return;
9178
9179     case 'k':
9180       /* X must be a constant.  Write the 1's complement of the
9181          constant.  */
9182       if (! INT_P (x))
9183         output_operand_lossage ("invalid %%k value");
9184       else
9185         fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9186       return;
9187
9188     case 'K':
9189       /* X must be a symbolic constant on ELF.  Write an
9190          expression suitable for an 'addi' that adds in the low 16
9191          bits of the MEM.  */
9192       if (GET_CODE (x) != CONST)
9193         {
9194           print_operand_address (file, x);
9195           fputs ("@l", file);
9196         }
9197       else
9198         {
9199           if (GET_CODE (XEXP (x, 0)) != PLUS
9200               || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9201                   && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9202               || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9203             output_operand_lossage ("invalid %%K value");
9204           print_operand_address (file, XEXP (XEXP (x, 0), 0));
9205           fputs ("@l", file);
9206           /* For GNU as, there must be a non-alphanumeric character
9207              between 'l' and the number.  The '-' is added by
9208              print_operand() already.  */
9209           if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9210             fputs ("+", file);
9211           print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9212         }
9213       return;
9214
9215       /* %l is output_asm_label.  */
9216
9217     case 'L':
9218       /* Write second word of DImode or DFmode reference.  Works on register
9219          or non-indexed memory only.  */
9220       if (GET_CODE (x) == REG)
9221         fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9222       else if (GET_CODE (x) == MEM)
9223         {
9224           /* Handle possible auto-increment.  Since it is pre-increment and
9225              we have already done it, we can just use an offset of word.  */
9226           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9227               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9228             output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9229                                            UNITS_PER_WORD));
9230           else
9231             output_address (XEXP (adjust_address_nv (x, SImode,
9232                                                      UNITS_PER_WORD),
9233                                   0));
9234
9235           if (small_data_operand (x, GET_MODE (x)))
9236             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9237                      reg_names[SMALL_DATA_REG]);
9238         }
9239       return;
9240
9241     case 'm':
9242       /* MB value for a mask operand.  */
9243       if (! mask_operand (x, SImode))
9244         output_operand_lossage ("invalid %%m value");
9245
9246       fprintf (file, "%d", extract_MB (x));
9247       return;
9248
9249     case 'M':
9250       /* ME value for a mask operand.  */
9251       if (! mask_operand (x, SImode))
9252         output_operand_lossage ("invalid %%M value");
9253
9254       fprintf (file, "%d", extract_ME (x));
9255       return;
9256
9257       /* %n outputs the negative of its operand.  */
9258
9259     case 'N':
9260       /* Write the number of elements in the vector times 4.  */
9261       if (GET_CODE (x) != PARALLEL)
9262         output_operand_lossage ("invalid %%N value");
9263       else
9264         fprintf (file, "%d", XVECLEN (x, 0) * 4);
9265       return;
9266
9267     case 'O':
9268       /* Similar, but subtract 1 first.  */
9269       if (GET_CODE (x) != PARALLEL)
9270         output_operand_lossage ("invalid %%O value");
9271       else
9272         fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9273       return;
9274
9275     case 'p':
9276       /* X is a CONST_INT that is a power of two.  Output the logarithm.  */
9277       if (! INT_P (x)
9278           || INT_LOWPART (x) < 0
9279           || (i = exact_log2 (INT_LOWPART (x))) < 0)
9280         output_operand_lossage ("invalid %%p value");
9281       else
9282         fprintf (file, "%d", i);
9283       return;
9284
9285     case 'P':
9286       /* The operand must be an indirect memory reference.  The result
9287          is the register name.  */
9288       if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9289           || REGNO (XEXP (x, 0)) >= 32)
9290         output_operand_lossage ("invalid %%P value");
9291       else
9292         fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
9293       return;
9294
9295     case 'q':
9296       /* This outputs the logical code corresponding to a boolean
9297          expression.  The expression may have one or both operands
9298          negated (if one, only the first one).  For condition register
9299          logical operations, it will also treat the negated
9300          CR codes as NOTs, but not handle NOTs of them.  */
9301       {
9302         const char *const *t = 0;
9303         const char *s;
9304         enum rtx_code code = GET_CODE (x);
9305         static const char * const tbl[3][3] = {
9306           { "and", "andc", "nor" },
9307           { "or", "orc", "nand" },
9308           { "xor", "eqv", "xor" } };
9309
9310         if (code == AND)
9311           t = tbl[0];
9312         else if (code == IOR)
9313           t = tbl[1];
9314         else if (code == XOR)
9315           t = tbl[2];
9316         else
9317           output_operand_lossage ("invalid %%q value");
9318
9319         if (GET_CODE (XEXP (x, 0)) != NOT)
9320           s = t[0];
9321         else
9322           {
9323             if (GET_CODE (XEXP (x, 1)) == NOT)
9324               s = t[2];
9325             else
9326               s = t[1];
9327           }
9328
9329         fputs (s, file);
9330       }
9331       return;
9332
9333     case 'Q':
9334       if (TARGET_MFCRF)
9335         fputc (',', file);
9336         /* FALLTHRU */
9337       else
9338         return;
9339
9340     case 'R':
9341       /* X is a CR register.  Print the mask for `mtcrf'.  */
9342       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9343         output_operand_lossage ("invalid %%R value");
9344       else
9345         fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9346       return;
9347
9348     case 's':
9349       /* Low 5 bits of 32 - value */
9350       if (! INT_P (x))
9351         output_operand_lossage ("invalid %%s value");
9352       else
9353         fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9354       return;
9355
9356     case 'S':
9357       /* PowerPC64 mask position.  All 0's is excluded.
9358          CONST_INT 32-bit mask is considered sign-extended so any
9359          transition must occur within the CONST_INT, not on the boundary.  */
9360       if (! mask64_operand (x, DImode))
9361         output_operand_lossage ("invalid %%S value");
9362
9363       uval = INT_LOWPART (x);
9364
9365       if (uval & 1)     /* Clear Left */
9366         {
9367 #if HOST_BITS_PER_WIDE_INT > 64
9368           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9369 #endif
9370           i = 64;
9371         }
9372       else              /* Clear Right */
9373         {
9374           uval = ~uval;
9375 #if HOST_BITS_PER_WIDE_INT > 64
9376           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9377 #endif
9378           i = 63;
9379         }
9380       while (uval != 0)
9381         --i, uval >>= 1;
9382       if (i < 0)
9383         abort ();
9384       fprintf (file, "%d", i);
9385       return;
9386
9387     case 't':
9388       /* Like 'J' but get to the OVERFLOW/UNORDERED bit.  */
9389       if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9390         abort ();
9391
9392       /* Bit 3 is OV bit.  */
9393       i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9394
9395       /* If we want bit 31, write a shift count of zero, not 32.  */
9396       fprintf (file, "%d", i == 31 ? 0 : i + 1);
9397       return;
9398
9399     case 'T':
9400       /* Print the symbolic name of a branch target register.  */
9401       if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9402                                   && REGNO (x) != COUNT_REGISTER_REGNUM))
9403         output_operand_lossage ("invalid %%T value");
9404       else if (REGNO (x) == LINK_REGISTER_REGNUM)
9405         fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9406       else
9407         fputs ("ctr", file);
9408       return;
9409
9410     case 'u':
9411       /* High-order 16 bits of constant for use in unsigned operand.  */
9412       if (! INT_P (x))
9413         output_operand_lossage ("invalid %%u value");
9414       else
9415         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9416                  (INT_LOWPART (x) >> 16) & 0xffff);
9417       return;
9418
9419     case 'v':
9420       /* High-order 16 bits of constant for use in signed operand.  */
9421       if (! INT_P (x))
9422         output_operand_lossage ("invalid %%v value");
9423       else
9424         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9425                  (INT_LOWPART (x) >> 16) & 0xffff);
9426       return;
9427
9428     case 'U':
9429       /* Print `u' if this has an auto-increment or auto-decrement.  */
9430       if (GET_CODE (x) == MEM
9431           && (GET_CODE (XEXP (x, 0)) == PRE_INC
9432               || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9433         putc ('u', file);
9434       return;
9435
9436     case 'V':
9437       /* Print the trap code for this operand.  */
9438       switch (GET_CODE (x))
9439         {
9440         case EQ:
9441           fputs ("eq", file);   /* 4 */
9442           break;
9443         case NE:
9444           fputs ("ne", file);   /* 24 */
9445           break;
9446         case LT:
9447           fputs ("lt", file);   /* 16 */
9448           break;
9449         case LE:
9450           fputs ("le", file);   /* 20 */
9451           break;
9452         case GT:
9453           fputs ("gt", file);   /* 8 */
9454           break;
9455         case GE:
9456           fputs ("ge", file);   /* 12 */
9457           break;
9458         case LTU:
9459           fputs ("llt", file);  /* 2 */
9460           break;
9461         case LEU:
9462           fputs ("lle", file);  /* 6 */
9463           break;
9464         case GTU:
9465           fputs ("lgt", file);  /* 1 */
9466           break;
9467         case GEU:
9468           fputs ("lge", file);  /* 5 */
9469           break;
9470         default:
9471           abort ();
9472         }
9473       break;
9474
9475     case 'w':
9476       /* If constant, low-order 16 bits of constant, signed.  Otherwise, write
9477          normally.  */
9478       if (INT_P (x))
9479         fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9480                  ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9481       else
9482         print_operand (file, x, 0);
9483       return;
9484
9485     case 'W':
9486       /* MB value for a PowerPC64 rldic operand.  */
9487       val = (GET_CODE (x) == CONST_INT
9488              ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9489
9490       if (val < 0)
9491         i = -1;
9492       else
9493         for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9494           if ((val <<= 1) < 0)
9495             break;
9496
9497 #if HOST_BITS_PER_WIDE_INT == 32
9498       if (GET_CODE (x) == CONST_INT && i >= 0)
9499         i += 32;  /* zero-extend high-part was all 0's */
9500       else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9501         {
9502           val = CONST_DOUBLE_LOW (x);
9503
9504           if (val == 0)
9505             abort ();
9506           else if (val < 0)
9507             --i;
9508           else
9509             for ( ; i < 64; i++)
9510               if ((val <<= 1) < 0)
9511                 break;
9512         }
9513 #endif
9514
9515       fprintf (file, "%d", i + 1);
9516       return;
9517
9518     case 'X':
9519       if (GET_CODE (x) == MEM
9520           && legitimate_indexed_address_p (XEXP (x, 0), 0))
9521         putc ('x', file);
9522       return;
9523
9524     case 'Y':
9525       /* Like 'L', for third word of TImode  */
9526       if (GET_CODE (x) == REG)
9527         fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9528       else if (GET_CODE (x) == MEM)
9529         {
9530           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9531               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9532             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9533           else
9534             output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9535           if (small_data_operand (x, GET_MODE (x)))
9536             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9537                      reg_names[SMALL_DATA_REG]);
9538         }
9539       return;
9540
9541     case 'z':
9542       /* X is a SYMBOL_REF.  Write out the name preceded by a
9543          period and without any trailing data in brackets.  Used for function
9544          names.  If we are configured for System V (or the embedded ABI) on
9545          the PowerPC, do not emit the period, since those systems do not use
9546          TOCs and the like.  */
9547       if (GET_CODE (x) != SYMBOL_REF)
9548         abort ();
9549
9550       if (XSTR (x, 0)[0] != '.')
9551         {
9552           switch (DEFAULT_ABI)
9553             {
9554             default:
9555               abort ();
9556
9557             case ABI_AIX:
9558               putc ('.', file);
9559               break;
9560
9561             case ABI_V4:
9562             case ABI_DARWIN:
9563               break;
9564             }
9565         }
9566       /* For macho, we need to check it see if we need a stub.  */
9567       if (TARGET_MACHO)
9568         {
9569           const char *name = XSTR (x, 0);
9570 #if TARGET_MACHO
9571           if (machopic_classify_name (name) == MACHOPIC_UNDEFINED_FUNCTION)
9572             name = machopic_stub_name (name);
9573 #endif
9574           assemble_name (file, name);
9575         }
9576      else if (TARGET_AIX)
9577         RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9578       else
9579         assemble_name (file, XSTR (x, 0));
9580       return;
9581
9582     case 'Z':
9583       /* Like 'L', for last word of TImode.  */
9584       if (GET_CODE (x) == REG)
9585         fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9586       else if (GET_CODE (x) == MEM)
9587         {
9588           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9589               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9590             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9591           else
9592             output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9593           if (small_data_operand (x, GET_MODE (x)))
9594             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9595                      reg_names[SMALL_DATA_REG]);
9596         }
9597       return;
9598
9599       /* Print AltiVec or SPE memory operand.  */
9600     case 'y':
9601       {
9602         rtx tmp;
9603
9604         if (GET_CODE (x) != MEM)
9605           abort ();
9606
9607         tmp = XEXP (x, 0);
9608
9609         if (TARGET_E500)
9610           {
9611             /* Handle [reg].  */
9612             if (GET_CODE (tmp) == REG)
9613               {
9614                 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9615                 break;
9616               }
9617             /* Handle [reg+UIMM].  */
9618             else if (GET_CODE (tmp) == PLUS &&
9619                      GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9620               {
9621                 int x;
9622
9623                 if (GET_CODE (XEXP (tmp, 0)) != REG)
9624                   abort ();
9625
9626                 x = INTVAL (XEXP (tmp, 1));
9627                 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9628                 break;
9629               }
9630
9631             /* Fall through.  Must be [reg+reg].  */
9632           }
9633         if (GET_CODE (tmp) == REG)
9634           fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9635         else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9636           {
9637             if (REGNO (XEXP (tmp, 0)) == 0)
9638               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9639                        reg_names[ REGNO (XEXP (tmp, 0)) ]);
9640             else
9641               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9642                        reg_names[ REGNO (XEXP (tmp, 1)) ]);
9643           }
9644         else
9645           abort ();
9646         break;
9647       }
9648
9649     case 0:
9650       if (GET_CODE (x) == REG)
9651         fprintf (file, "%s", reg_names[REGNO (x)]);
9652       else if (GET_CODE (x) == MEM)
9653         {
9654           /* We need to handle PRE_INC and PRE_DEC here, since we need to
9655              know the width from the mode.  */
9656           if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9657             fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9658                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9659           else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9660             fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9661                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9662           else
9663             output_address (XEXP (x, 0));
9664         }
9665       else
9666         output_addr_const (file, x);
9667       return;
9668
9669     case '&':
9670       assemble_name (file, rs6000_get_some_local_dynamic_name ());
9671       return;
9672
9673     default:
9674       output_operand_lossage ("invalid %%xn code");
9675     }
9676 }
9677 \f
9678 /* Print the address of an operand.  */
9679
9680 void
9681 print_operand_address (FILE *file, rtx x)
9682 {
9683   if (GET_CODE (x) == REG)
9684     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9685   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9686            || GET_CODE (x) == LABEL_REF)
9687     {
9688       output_addr_const (file, x);
9689       if (small_data_operand (x, GET_MODE (x)))
9690         fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9691                  reg_names[SMALL_DATA_REG]);
9692       else if (TARGET_TOC)
9693         abort ();
9694     }
9695   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9696     {
9697       if (REGNO (XEXP (x, 0)) == 0)
9698         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9699                  reg_names[ REGNO (XEXP (x, 0)) ]);
9700       else
9701         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9702                  reg_names[ REGNO (XEXP (x, 1)) ]);
9703     }
9704   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9705     fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9706              INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9707 #if TARGET_ELF
9708   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9709            && CONSTANT_P (XEXP (x, 1)))
9710     {
9711       output_addr_const (file, XEXP (x, 1));
9712       fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9713     }
9714 #endif
9715 #if TARGET_MACHO
9716   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9717            && CONSTANT_P (XEXP (x, 1)))
9718     {
9719       fprintf (file, "lo16(");
9720       output_addr_const (file, XEXP (x, 1));
9721       fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9722     }
9723 #endif
9724   else if (legitimate_constant_pool_address_p (x))
9725     {
9726       if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9727         {
9728           rtx contains_minus = XEXP (x, 1);
9729           rtx minus, symref;
9730           const char *name;
9731
9732           /* Find the (minus (sym) (toc)) buried in X, and temporarily
9733              turn it into (sym) for output_addr_const.  */
9734           while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9735             contains_minus = XEXP (contains_minus, 0);
9736
9737           minus = XEXP (contains_minus, 0);
9738           symref = XEXP (minus, 0);
9739           XEXP (contains_minus, 0) = symref;
9740           if (TARGET_ELF)
9741             {
9742               char *newname;
9743
9744               name = XSTR (symref, 0);
9745               newname = alloca (strlen (name) + sizeof ("@toc"));
9746               strcpy (newname, name);
9747               strcat (newname, "@toc");
9748               XSTR (symref, 0) = newname;
9749             }
9750           output_addr_const (file, XEXP (x, 1));
9751           if (TARGET_ELF)
9752             XSTR (symref, 0) = name;
9753           XEXP (contains_minus, 0) = minus;
9754         }
9755       else
9756         output_addr_const (file, XEXP (x, 1));
9757
9758       fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9759     }
9760   else
9761     abort ();
9762 }
9763 \f
9764 /* Target hook for assembling integer objects.  The PowerPC version has
9765    to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9766    is defined.  It also needs to handle DI-mode objects on 64-bit
9767    targets.  */
9768
9769 static bool
9770 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9771 {
9772 #ifdef RELOCATABLE_NEEDS_FIXUP
9773   /* Special handling for SI values.  */
9774   if (size == 4 && aligned_p)
9775     {
9776       extern int in_toc_section (void);
9777       static int recurse = 0;
9778
9779       /* For -mrelocatable, we mark all addresses that need to be fixed up
9780          in the .fixup section.  */
9781       if (TARGET_RELOCATABLE
9782           && !in_toc_section ()
9783           && !in_text_section ()
9784           && !in_unlikely_text_section ()
9785           && !recurse
9786           && GET_CODE (x) != CONST_INT
9787           && GET_CODE (x) != CONST_DOUBLE
9788           && CONSTANT_P (x))
9789         {
9790           char buf[256];
9791
9792           recurse = 1;
9793           ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9794           fixuplabelno++;
9795           ASM_OUTPUT_LABEL (asm_out_file, buf);
9796           fprintf (asm_out_file, "\t.long\t(");
9797           output_addr_const (asm_out_file, x);
9798           fprintf (asm_out_file, ")@fixup\n");
9799           fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9800           ASM_OUTPUT_ALIGN (asm_out_file, 2);
9801           fprintf (asm_out_file, "\t.long\t");
9802           assemble_name (asm_out_file, buf);
9803           fprintf (asm_out_file, "\n\t.previous\n");
9804           recurse = 0;
9805           return true;
9806         }
9807       /* Remove initial .'s to turn a -mcall-aixdesc function
9808          address into the address of the descriptor, not the function
9809          itself.  */
9810       else if (GET_CODE (x) == SYMBOL_REF
9811                && XSTR (x, 0)[0] == '.'
9812                && DEFAULT_ABI == ABI_AIX)
9813         {
9814           const char *name = XSTR (x, 0);
9815           while (*name == '.')
9816             name++;
9817
9818           fprintf (asm_out_file, "\t.long\t%s\n", name);
9819           return true;
9820         }
9821     }
9822 #endif /* RELOCATABLE_NEEDS_FIXUP */
9823   return default_assemble_integer (x, size, aligned_p);
9824 }
9825
9826 #ifdef HAVE_GAS_HIDDEN
9827 /* Emit an assembler directive to set symbol visibility for DECL to
9828    VISIBILITY_TYPE.  */
9829
9830 static void
9831 rs6000_assemble_visibility (tree decl, int vis)
9832 {
9833   /* Functions need to have their entry point symbol visibility set as
9834      well as their descriptor symbol visibility.  */
9835   if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9836     {
9837       static const char * const visibility_types[] = {
9838         NULL, "internal", "hidden", "protected"
9839       };
9840
9841       const char *name, *type;
9842
9843       name = ((* targetm.strip_name_encoding)
9844               (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9845       type = visibility_types[vis];
9846
9847       fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9848       fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9849     }
9850   else
9851     default_assemble_visibility (decl, vis);
9852 }
9853 #endif
9854 \f
9855 enum rtx_code
9856 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9857 {
9858   /* Reversal of FP compares takes care -- an ordered compare
9859      becomes an unordered compare and vice versa.  */
9860   if (mode == CCFPmode
9861       && (!flag_finite_math_only
9862           || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9863           || code == UNEQ || code == LTGT))
9864     return reverse_condition_maybe_unordered (code);
9865   else
9866     return reverse_condition (code);
9867 }
9868
9869 /* Generate a compare for CODE.  Return a brand-new rtx that
9870    represents the result of the compare.  */
9871
9872 static rtx
9873 rs6000_generate_compare (enum rtx_code code)
9874 {
9875   enum machine_mode comp_mode;
9876   rtx compare_result;
9877
9878   if (rs6000_compare_fp_p)
9879     comp_mode = CCFPmode;
9880   else if (code == GTU || code == LTU
9881           || code == GEU || code == LEU)
9882     comp_mode = CCUNSmode;
9883   else
9884     comp_mode = CCmode;
9885
9886   /* First, the compare.  */
9887   compare_result = gen_reg_rtx (comp_mode);
9888
9889   /* SPE FP compare instructions on the GPRs.  Yuck!  */
9890   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9891       && rs6000_compare_fp_p)
9892     {
9893       rtx cmp, or1, or2, or_result, compare_result2;
9894
9895       /* Note: The E500 comparison instructions set the GT bit (x +
9896          1), on success.  This explains the mess.  */
9897
9898       switch (code)
9899         {
9900         case EQ: case UNEQ: case NE: case LTGT:
9901           cmp = flag_finite_math_only
9902             ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9903                                rs6000_compare_op1)
9904             : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9905                                rs6000_compare_op1);
9906           break;
9907         case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
9908           cmp = flag_finite_math_only
9909             ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9910                                rs6000_compare_op1)
9911             : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9912                                rs6000_compare_op1);
9913           break;
9914         case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
9915           cmp = flag_finite_math_only
9916             ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9917                                rs6000_compare_op1)
9918             : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9919                                rs6000_compare_op1);
9920           break;
9921         default:
9922           abort ();
9923         }
9924
9925       /* Synthesize LE and GE from LT/GT || EQ.  */
9926       if (code == LE || code == GE || code == LEU || code == GEU)
9927         {
9928           emit_insn (cmp);
9929
9930           switch (code)
9931             {
9932             case LE: code = LT; break;
9933             case GE: code = GT; break;
9934             case LEU: code = LT; break;
9935             case GEU: code = GT; break;
9936             default: abort ();
9937             }
9938
9939           or1 = gen_reg_rtx (SImode);
9940           or2 = gen_reg_rtx (SImode);
9941           or_result = gen_reg_rtx (CCEQmode);
9942           compare_result2 = gen_reg_rtx (CCFPmode);
9943
9944           /* Do the EQ.  */
9945           cmp = flag_finite_math_only
9946             ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9947                                rs6000_compare_op1)
9948             : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9949                                rs6000_compare_op1);
9950           emit_insn (cmp);
9951
9952           or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
9953           or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
9954
9955           /* OR them together.  */
9956           cmp = gen_rtx_SET (VOIDmode, or_result,
9957                              gen_rtx_COMPARE (CCEQmode,
9958                                               gen_rtx_IOR (SImode, or1, or2),
9959                                               const_true_rtx));
9960           compare_result = or_result;
9961           code = EQ;
9962         }
9963       else
9964         {
9965           if (code == NE || code == LTGT)
9966             code = NE;
9967           else
9968             code = EQ;
9969         }
9970
9971       emit_insn (cmp);
9972     }
9973   else
9974     emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9975                             gen_rtx_COMPARE (comp_mode,
9976                                              rs6000_compare_op0,
9977                                              rs6000_compare_op1)));
9978
9979   /* Some kinds of FP comparisons need an OR operation;
9980      under flag_finite_math_only we don't bother.  */
9981   if (rs6000_compare_fp_p
9982       && ! flag_finite_math_only
9983       && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9984       && (code == LE || code == GE
9985           || code == UNEQ || code == LTGT
9986           || code == UNGT || code == UNLT))
9987     {
9988       enum rtx_code or1, or2;
9989       rtx or1_rtx, or2_rtx, compare2_rtx;
9990       rtx or_result = gen_reg_rtx (CCEQmode);
9991
9992       switch (code)
9993         {
9994         case LE: or1 = LT;  or2 = EQ;  break;
9995         case GE: or1 = GT;  or2 = EQ;  break;
9996         case UNEQ: or1 = UNORDERED;  or2 = EQ;  break;
9997         case LTGT: or1 = LT;  or2 = GT;  break;
9998         case UNGT: or1 = UNORDERED;  or2 = GT;  break;
9999         case UNLT: or1 = UNORDERED;  or2 = LT;  break;
10000         default:  abort ();
10001         }
10002       validate_condition_mode (or1, comp_mode);
10003       validate_condition_mode (or2, comp_mode);
10004       or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10005       or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10006       compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10007                                       gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10008                                       const_true_rtx);
10009       emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10010
10011       compare_result = or_result;
10012       code = EQ;
10013     }
10014
10015   validate_condition_mode (code, GET_MODE (compare_result));
10016
10017   return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10018 }
10019
10020
10021 /* Emit the RTL for an sCOND pattern.  */
10022
10023 void
10024 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10025 {
10026   rtx condition_rtx;
10027   enum machine_mode op_mode;
10028   enum rtx_code cond_code;
10029
10030   condition_rtx = rs6000_generate_compare (code);
10031   cond_code = GET_CODE (condition_rtx);
10032
10033   if (TARGET_E500 && rs6000_compare_fp_p
10034       && !TARGET_FPRS && TARGET_HARD_FLOAT)
10035     {
10036       rtx t;
10037
10038       PUT_MODE (condition_rtx, SImode);
10039       t = XEXP (condition_rtx, 0);
10040
10041       if (cond_code != NE && cond_code != EQ)
10042         abort ();
10043
10044       if (cond_code == NE)
10045         emit_insn (gen_e500_flip_gt_bit (t, t));
10046
10047       emit_insn (gen_move_from_CR_gt_bit (result, t));
10048       return;
10049     }
10050
10051   if (cond_code == NE
10052       || cond_code == GE || cond_code == LE
10053       || cond_code == GEU || cond_code == LEU
10054       || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10055     {
10056       rtx not_result = gen_reg_rtx (CCEQmode);
10057       rtx not_op, rev_cond_rtx;
10058       enum machine_mode cc_mode;
10059
10060       cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10061
10062       rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10063                                      SImode, XEXP (condition_rtx, 0), const0_rtx);
10064       not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10065       emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10066       condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10067     }
10068
10069   op_mode = GET_MODE (rs6000_compare_op0);
10070   if (op_mode == VOIDmode)
10071     op_mode = GET_MODE (rs6000_compare_op1);
10072
10073   if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10074     {
10075       PUT_MODE (condition_rtx, DImode);
10076       convert_move (result, condition_rtx, 0);
10077     }
10078   else
10079     {
10080       PUT_MODE (condition_rtx, SImode);
10081       emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10082     }
10083 }
10084
10085 /* Emit a branch of kind CODE to location LOC.  */
10086
10087 void
10088 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10089 {
10090   rtx condition_rtx, loc_ref;
10091
10092   condition_rtx = rs6000_generate_compare (code);
10093   loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10094   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10095                                gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10096                                                      loc_ref, pc_rtx)));
10097 }
10098
10099 /* Return the string to output a conditional branch to LABEL, which is
10100    the operand number of the label, or -1 if the branch is really a
10101    conditional return.
10102
10103    OP is the conditional expression.  XEXP (OP, 0) is assumed to be a
10104    condition code register and its mode specifies what kind of
10105    comparison we made.
10106
10107    REVERSED is nonzero if we should reverse the sense of the comparison.
10108
10109    INSN is the insn.  */
10110
10111 char *
10112 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10113 {
10114   static char string[64];
10115   enum rtx_code code = GET_CODE (op);
10116   rtx cc_reg = XEXP (op, 0);
10117   enum machine_mode mode = GET_MODE (cc_reg);
10118   int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10119   int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10120   int really_reversed = reversed ^ need_longbranch;
10121   char *s = string;
10122   const char *ccode;
10123   const char *pred;
10124   rtx note;
10125
10126   validate_condition_mode (code, mode);
10127
10128   /* Work out which way this really branches.  We could use
10129      reverse_condition_maybe_unordered here always but this
10130      makes the resulting assembler clearer.  */
10131   if (really_reversed)
10132     {
10133       /* Reversal of FP compares takes care -- an ordered compare
10134          becomes an unordered compare and vice versa.  */
10135       if (mode == CCFPmode)
10136         code = reverse_condition_maybe_unordered (code);
10137       else
10138         code = reverse_condition (code);
10139     }
10140
10141   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10142     {
10143       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10144          to the GT bit.  */
10145       if (code == EQ)
10146         /* Opposite of GT.  */
10147         code = GT;
10148       else if (code == NE)
10149         code = UNLE;
10150       else
10151         abort ();
10152     }
10153
10154   switch (code)
10155     {
10156       /* Not all of these are actually distinct opcodes, but
10157          we distinguish them for clarity of the resulting assembler.  */
10158     case NE: case LTGT:
10159       ccode = "ne"; break;
10160     case EQ: case UNEQ:
10161       ccode = "eq"; break;
10162     case GE: case GEU:
10163       ccode = "ge"; break;
10164     case GT: case GTU: case UNGT:
10165       ccode = "gt"; break;
10166     case LE: case LEU:
10167       ccode = "le"; break;
10168     case LT: case LTU: case UNLT:
10169       ccode = "lt"; break;
10170     case UNORDERED: ccode = "un"; break;
10171     case ORDERED: ccode = "nu"; break;
10172     case UNGE: ccode = "nl"; break;
10173     case UNLE: ccode = "ng"; break;
10174     default:
10175       abort ();
10176     }
10177
10178   /* Maybe we have a guess as to how likely the branch is.
10179      The old mnemonics don't have a way to specify this information.  */
10180   pred = "";
10181   note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10182   if (note != NULL_RTX)
10183     {
10184       /* PROB is the difference from 50%.  */
10185       int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10186
10187       /* Only hint for highly probable/improbable branches on newer
10188          cpus as static prediction overrides processor dynamic
10189          prediction.  For older cpus we may as well always hint, but
10190          assume not taken for branches that are very close to 50% as a
10191          mispredicted taken branch is more expensive than a
10192          mispredicted not-taken branch.  */
10193       if (rs6000_always_hint
10194           || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10195         {
10196           if (abs (prob) > REG_BR_PROB_BASE / 20
10197               && ((prob > 0) ^ need_longbranch))
10198               pred = "+";
10199           else
10200             pred = "-";
10201         }
10202     }
10203
10204   if (label == NULL)
10205     s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10206   else
10207     s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10208
10209   /* We need to escape any '%' characters in the reg_names string.
10210      Assume they'd only be the first character....  */
10211   if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10212     *s++ = '%';
10213   s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10214
10215   if (label != NULL)
10216     {
10217       /* If the branch distance was too far, we may have to use an
10218          unconditional branch to go the distance.  */
10219       if (need_longbranch)
10220         s += sprintf (s, ",$+8\n\tb %s", label);
10221       else
10222         s += sprintf (s, ",%s", label);
10223     }
10224
10225   return string;
10226 }
10227
10228 /* Return the string to flip the GT bit on a CR.  */
10229 char *
10230 output_e500_flip_gt_bit (rtx dst, rtx src)
10231 {
10232   static char string[64];
10233   int a, b;
10234
10235   if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10236       || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10237     abort ();
10238
10239   /* GT bit.  */
10240   a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10241   b = 4 * (REGNO (src) - CR0_REGNO) + 1;
10242
10243   sprintf (string, "crnot %d,%d", a, b);
10244   return string;
10245 }
10246
10247 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10248    operands of the last comparison is nonzero/true, FALSE_COND if it
10249    is zero/false.  Return 0 if the hardware has no such operation.  */
10250
10251 int
10252 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10253 {
10254   enum rtx_code code = GET_CODE (op);
10255   rtx op0 = rs6000_compare_op0;
10256   rtx op1 = rs6000_compare_op1;
10257   REAL_VALUE_TYPE c1;
10258   enum machine_mode compare_mode = GET_MODE (op0);
10259   enum machine_mode result_mode = GET_MODE (dest);
10260   rtx temp;
10261
10262   /* These modes should always match.  */
10263   if (GET_MODE (op1) != compare_mode
10264       /* In the isel case however, we can use a compare immediate, so
10265          op1 may be a small constant.  */
10266       && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10267     return 0;
10268   if (GET_MODE (true_cond) != result_mode)
10269     return 0;
10270   if (GET_MODE (false_cond) != result_mode)
10271     return 0;
10272
10273   /* First, work out if the hardware can do this at all, or
10274      if it's too slow....  */
10275   if (! rs6000_compare_fp_p)
10276     {
10277       if (TARGET_ISEL)
10278         return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10279       return 0;
10280     }
10281   else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10282            && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10283     return 0;
10284
10285   /* Eliminate half of the comparisons by switching operands, this
10286      makes the remaining code simpler.  */
10287   if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10288       || code == LTGT || code == LT || code == UNLE)
10289     {
10290       code = reverse_condition_maybe_unordered (code);
10291       temp = true_cond;
10292       true_cond = false_cond;
10293       false_cond = temp;
10294     }
10295
10296   /* UNEQ and LTGT take four instructions for a comparison with zero,
10297      it'll probably be faster to use a branch here too.  */
10298   if (code == UNEQ && HONOR_NANS (compare_mode))
10299     return 0;
10300
10301   if (GET_CODE (op1) == CONST_DOUBLE)
10302     REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10303
10304   /* We're going to try to implement comparisons by performing
10305      a subtract, then comparing against zero.  Unfortunately,
10306      Inf - Inf is NaN which is not zero, and so if we don't
10307      know that the operand is finite and the comparison
10308      would treat EQ different to UNORDERED, we can't do it.  */
10309   if (HONOR_INFINITIES (compare_mode)
10310       && code != GT && code != UNGE
10311       && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10312       /* Constructs of the form (a OP b ? a : b) are safe.  */
10313       && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10314           || (! rtx_equal_p (op0, true_cond)
10315               && ! rtx_equal_p (op1, true_cond))))
10316     return 0;
10317   /* At this point we know we can use fsel.  */
10318
10319   /* Reduce the comparison to a comparison against zero.  */
10320   temp = gen_reg_rtx (compare_mode);
10321   emit_insn (gen_rtx_SET (VOIDmode, temp,
10322                           gen_rtx_MINUS (compare_mode, op0, op1)));
10323   op0 = temp;
10324   op1 = CONST0_RTX (compare_mode);
10325
10326   /* If we don't care about NaNs we can reduce some of the comparisons
10327      down to faster ones.  */
10328   if (! HONOR_NANS (compare_mode))
10329     switch (code)
10330       {
10331       case GT:
10332         code = LE;
10333         temp = true_cond;
10334         true_cond = false_cond;
10335         false_cond = temp;
10336         break;
10337       case UNGE:
10338         code = GE;
10339         break;
10340       case UNEQ:
10341         code = EQ;
10342         break;
10343       default:
10344         break;
10345       }
10346
10347   /* Now, reduce everything down to a GE.  */
10348   switch (code)
10349     {
10350     case GE:
10351       break;
10352
10353     case LE:
10354       temp = gen_reg_rtx (compare_mode);
10355       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10356       op0 = temp;
10357       break;
10358
10359     case ORDERED:
10360       temp = gen_reg_rtx (compare_mode);
10361       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10362       op0 = temp;
10363       break;
10364
10365     case EQ:
10366       temp = gen_reg_rtx (compare_mode);
10367       emit_insn (gen_rtx_SET (VOIDmode, temp,
10368                               gen_rtx_NEG (compare_mode,
10369                                            gen_rtx_ABS (compare_mode, op0))));
10370       op0 = temp;
10371       break;
10372
10373     case UNGE:
10374       /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10375       temp = gen_reg_rtx (result_mode);
10376       emit_insn (gen_rtx_SET (VOIDmode, temp,
10377                               gen_rtx_IF_THEN_ELSE (result_mode,
10378                                                     gen_rtx_GE (VOIDmode,
10379                                                                 op0, op1),
10380                                                     true_cond, false_cond)));
10381       false_cond = true_cond;
10382       true_cond = temp;
10383
10384       temp = gen_reg_rtx (compare_mode);
10385       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10386       op0 = temp;
10387       break;
10388
10389     case GT:
10390       /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10391       temp = gen_reg_rtx (result_mode);
10392       emit_insn (gen_rtx_SET (VOIDmode, temp,
10393                               gen_rtx_IF_THEN_ELSE (result_mode,
10394                                                     gen_rtx_GE (VOIDmode,
10395                                                                 op0, op1),
10396                                                     true_cond, false_cond)));
10397       true_cond = false_cond;
10398       false_cond = temp;
10399
10400       temp = gen_reg_rtx (compare_mode);
10401       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10402       op0 = temp;
10403       break;
10404
10405     default:
10406       abort ();
10407     }
10408
10409   emit_insn (gen_rtx_SET (VOIDmode, dest,
10410                           gen_rtx_IF_THEN_ELSE (result_mode,
10411                                                 gen_rtx_GE (VOIDmode,
10412                                                             op0, op1),
10413                                                 true_cond, false_cond)));
10414   return 1;
10415 }
10416
10417 /* Same as above, but for ints (isel).  */
10418
10419 static int
10420 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10421 {
10422   rtx condition_rtx, cr;
10423
10424   /* All isel implementations thus far are 32-bits.  */
10425   if (GET_MODE (rs6000_compare_op0) != SImode)
10426     return 0;
10427
10428   /* We still have to do the compare, because isel doesn't do a
10429      compare, it just looks at the CRx bits set by a previous compare
10430      instruction.  */
10431   condition_rtx = rs6000_generate_compare (GET_CODE (op));
10432   cr = XEXP (condition_rtx, 0);
10433
10434   if (GET_MODE (cr) == CCmode)
10435     emit_insn (gen_isel_signed (dest, condition_rtx,
10436                                 true_cond, false_cond, cr));
10437   else
10438     emit_insn (gen_isel_unsigned (dest, condition_rtx,
10439                                   true_cond, false_cond, cr));
10440
10441   return 1;
10442 }
10443
10444 const char *
10445 output_isel (rtx *operands)
10446 {
10447   enum rtx_code code;
10448
10449   code = GET_CODE (operands[1]);
10450   if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10451     {
10452       PUT_CODE (operands[1], reverse_condition (code));
10453       return "isel %0,%3,%2,%j1";
10454     }
10455   else
10456     return "isel %0,%2,%3,%j1";
10457 }
10458
10459 void
10460 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10461 {
10462   enum machine_mode mode = GET_MODE (op0);
10463   enum rtx_code c;
10464   rtx target;
10465
10466   if (code == SMAX || code == SMIN)
10467     c = GE;
10468   else
10469     c = GEU;
10470
10471   if (code == SMAX || code == UMAX)
10472     target = emit_conditional_move (dest, c, op0, op1, mode,
10473                                     op0, op1, mode, 0);
10474   else
10475     target = emit_conditional_move (dest, c, op0, op1, mode,
10476                                     op1, op0, mode, 0);
10477   if (target == NULL_RTX)
10478     abort ();
10479   if (target != dest)
10480     emit_move_insn (dest, target);
10481 }
10482
10483 /* Emit instructions to move SRC to DST.  Called by splitters for
10484    multi-register moves.  It will emit at most one instruction for
10485    each register that is accessed; that is, it won't emit li/lis pairs
10486    (or equivalent for 64-bit code).  One of SRC or DST must be a hard
10487    register.  */
10488
10489 void
10490 rs6000_split_multireg_move (rtx dst, rtx src)
10491 {
10492   /* The register number of the first register being moved.  */
10493   int reg;
10494   /* The mode that is to be moved.  */
10495   enum machine_mode mode;
10496   /* The mode that the move is being done in, and its size.  */
10497   enum machine_mode reg_mode;
10498   int reg_mode_size;
10499   /* The number of registers that will be moved.  */
10500   int nregs;
10501
10502   reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10503   mode = GET_MODE (dst);
10504   nregs = HARD_REGNO_NREGS (reg, mode);
10505   if (FP_REGNO_P (reg))
10506     reg_mode = DFmode;
10507   else if (ALTIVEC_REGNO_P (reg))
10508     reg_mode = V16QImode;
10509   else
10510     reg_mode = word_mode;
10511   reg_mode_size = GET_MODE_SIZE (reg_mode);
10512
10513   if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10514     abort ();
10515
10516   if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10517     {
10518       /* Move register range backwards, if we might have destructive
10519          overlap.  */
10520       int i;
10521       for (i = nregs - 1; i >= 0; i--)
10522         emit_insn (gen_rtx_SET (VOIDmode,
10523                                 simplify_gen_subreg (reg_mode, dst, mode,
10524                                                      i * reg_mode_size),
10525                                 simplify_gen_subreg (reg_mode, src, mode,
10526                                                      i * reg_mode_size)));
10527     }
10528   else
10529     {
10530       int i;
10531       int j = -1;
10532       bool used_update = false;
10533
10534       if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10535         {
10536           rtx breg;
10537
10538           if (GET_CODE (XEXP (src, 0)) == PRE_INC
10539               || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10540             {
10541               rtx delta_rtx;
10542               breg = XEXP (XEXP (src, 0), 0);
10543               delta_rtx =  GET_CODE (XEXP (src, 0)) == PRE_INC
10544                   ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10545                   : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10546               emit_insn (TARGET_32BIT
10547                          ? gen_addsi3 (breg, breg, delta_rtx)
10548                          : gen_adddi3 (breg, breg, delta_rtx));
10549               src = gen_rtx_MEM (mode, breg);
10550             }
10551
10552           /* We have now address involving an base register only.
10553              If we use one of the registers to address memory,
10554              we have change that register last.  */
10555
10556           breg = (GET_CODE (XEXP (src, 0)) == PLUS
10557                   ? XEXP (XEXP (src, 0), 0)
10558                   : XEXP (src, 0));
10559
10560           if (!REG_P (breg))
10561               abort();
10562
10563           if (REGNO (breg) >= REGNO (dst)
10564               && REGNO (breg) < REGNO (dst) + nregs)
10565             j = REGNO (breg) - REGNO (dst);
10566         }
10567
10568       if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10569         {
10570           rtx breg;
10571
10572           if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10573               || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10574             {
10575               rtx delta_rtx;
10576               breg = XEXP (XEXP (dst, 0), 0);
10577               delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10578                 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10579                 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10580
10581               /* We have to update the breg before doing the store.
10582                  Use store with update, if available.  */
10583
10584               if (TARGET_UPDATE)
10585                 {
10586                   rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10587                   emit_insn (TARGET_32BIT
10588                              ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10589                              : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10590                   used_update = true;
10591                 }
10592               else
10593                 emit_insn (TARGET_32BIT
10594                            ? gen_addsi3 (breg, breg, delta_rtx)
10595                            : gen_adddi3 (breg, breg, delta_rtx));
10596               dst = gen_rtx_MEM (mode, breg);
10597             }
10598         }
10599
10600       for (i = 0; i < nregs; i++)
10601         {
10602           /* Calculate index to next subword.  */
10603           ++j;
10604           if (j == nregs)
10605             j = 0;
10606
10607           /* If compiler already emited move of first word by
10608              store with update, no need to do anything.  */
10609           if (j == 0 && used_update)
10610             continue;
10611
10612           emit_insn (gen_rtx_SET (VOIDmode,
10613                                   simplify_gen_subreg (reg_mode, dst, mode,
10614                                                        j * reg_mode_size),
10615                                   simplify_gen_subreg (reg_mode, src, mode,
10616                                                        j * reg_mode_size)));
10617         }
10618     }
10619 }
10620
10621 \f
10622 /* This page contains routines that are used to determine what the
10623    function prologue and epilogue code will do and write them out.  */
10624
10625 /* Return the first fixed-point register that is required to be
10626    saved. 32 if none.  */
10627
10628 int
10629 first_reg_to_save (void)
10630 {
10631   int first_reg;
10632
10633   /* Find lowest numbered live register.  */
10634   for (first_reg = 13; first_reg <= 31; first_reg++)
10635     if (regs_ever_live[first_reg]
10636         && (! call_used_regs[first_reg]
10637             || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10638                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10639                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10640       break;
10641
10642 #if TARGET_MACHO
10643   if (flag_pic
10644       && current_function_uses_pic_offset_table
10645       && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10646     return RS6000_PIC_OFFSET_TABLE_REGNUM;
10647 #endif
10648
10649   return first_reg;
10650 }
10651
10652 /* Similar, for FP regs.  */
10653
10654 int
10655 first_fp_reg_to_save (void)
10656 {
10657   int first_reg;
10658
10659   /* Find lowest numbered live register.  */
10660   for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10661     if (regs_ever_live[first_reg])
10662       break;
10663
10664   return first_reg;
10665 }
10666
10667 /* Similar, for AltiVec regs.  */
10668
10669 static int
10670 first_altivec_reg_to_save (void)
10671 {
10672   int i;
10673
10674   /* Stack frame remains as is unless we are in AltiVec ABI.  */
10675   if (! TARGET_ALTIVEC_ABI)
10676     return LAST_ALTIVEC_REGNO + 1;
10677
10678   /* Find lowest numbered live register.  */
10679   for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10680     if (regs_ever_live[i])
10681       break;
10682
10683   return i;
10684 }
10685
10686 /* Return a 32-bit mask of the AltiVec registers we need to set in
10687    VRSAVE.  Bit n of the return value is 1 if Vn is live.  The MSB in
10688    the 32-bit word is 0.  */
10689
10690 static unsigned int
10691 compute_vrsave_mask (void)
10692 {
10693   unsigned int i, mask = 0;
10694
10695   /* First, find out if we use _any_ altivec registers.  */
10696   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10697     if (regs_ever_live[i])
10698       mask |= ALTIVEC_REG_BIT (i);
10699
10700   if (mask == 0)
10701     return mask;
10702
10703   /* Next, remove the argument registers from the set.  These must
10704      be in the VRSAVE mask set by the caller, so we don't need to add
10705      them in again.  More importantly, the mask we compute here is
10706      used to generate CLOBBERs in the set_vrsave insn, and we do not
10707      wish the argument registers to die.  */
10708   for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10709     mask &= ~ALTIVEC_REG_BIT (i);
10710
10711   /* Similarly, remove the return value from the set.  */
10712   {
10713     bool yes = false;
10714     diddle_return_value (is_altivec_return_reg, &yes);
10715     if (yes)
10716       mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10717   }
10718
10719   return mask;
10720 }
10721
10722 static void
10723 is_altivec_return_reg (rtx reg, void *xyes)
10724 {
10725   bool *yes = (bool *) xyes;
10726   if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10727     *yes = true;
10728 }
10729
10730 \f
10731 /* Calculate the stack information for the current function.  This is
10732    complicated by having two separate calling sequences, the AIX calling
10733    sequence and the V.4 calling sequence.
10734
10735    AIX (and Darwin/Mac OS X) stack frames look like:
10736                                                           32-bit  64-bit
10737         SP----> +---------------------------------------+
10738                 | back chain to caller                  | 0       0
10739                 +---------------------------------------+
10740                 | saved CR                              | 4       8 (8-11)
10741                 +---------------------------------------+
10742                 | saved LR                              | 8       16
10743                 +---------------------------------------+
10744                 | reserved for compilers                | 12      24
10745                 +---------------------------------------+
10746                 | reserved for binders                  | 16      32
10747                 +---------------------------------------+
10748                 | saved TOC pointer                     | 20      40
10749                 +---------------------------------------+
10750                 | Parameter save area (P)               | 24      48
10751                 +---------------------------------------+
10752                 | Alloca space (A)                      | 24+P    etc.
10753                 +---------------------------------------+
10754                 | Local variable space (L)              | 24+P+A
10755                 +---------------------------------------+
10756                 | Float/int conversion temporary (X)    | 24+P+A+L
10757                 +---------------------------------------+
10758                 | Save area for AltiVec registers (W)   | 24+P+A+L+X
10759                 +---------------------------------------+
10760                 | AltiVec alignment padding (Y)         | 24+P+A+L+X+W
10761                 +---------------------------------------+
10762                 | Save area for VRSAVE register (Z)     | 24+P+A+L+X+W+Y
10763                 +---------------------------------------+
10764                 | Save area for GP registers (G)        | 24+P+A+X+L+X+W+Y+Z
10765                 +---------------------------------------+
10766                 | Save area for FP registers (F)        | 24+P+A+X+L+X+W+Y+Z+G
10767                 +---------------------------------------+
10768         old SP->| back chain to caller's caller         |
10769                 +---------------------------------------+
10770
10771    The required alignment for AIX configurations is two words (i.e., 8
10772    or 16 bytes).
10773
10774
10775    V.4 stack frames look like:
10776
10777         SP----> +---------------------------------------+
10778                 | back chain to caller                  | 0
10779                 +---------------------------------------+
10780                 | caller's saved LR                     | 4
10781                 +---------------------------------------+
10782                 | Parameter save area (P)               | 8
10783                 +---------------------------------------+
10784                 | Alloca space (A)                      | 8+P
10785                 +---------------------------------------+
10786                 | Varargs save area (V)                 | 8+P+A
10787                 +---------------------------------------+
10788                 | Local variable space (L)              | 8+P+A+V
10789                 +---------------------------------------+
10790                 | Float/int conversion temporary (X)    | 8+P+A+V+L
10791                 +---------------------------------------+
10792                 | Save area for AltiVec registers (W)   | 8+P+A+V+L+X
10793                 +---------------------------------------+
10794                 | AltiVec alignment padding (Y)         | 8+P+A+V+L+X+W
10795                 +---------------------------------------+
10796                 | Save area for VRSAVE register (Z)     | 8+P+A+V+L+X+W+Y
10797                 +---------------------------------------+
10798                 | SPE: area for 64-bit GP registers     |
10799                 +---------------------------------------+
10800                 | SPE alignment padding                 |
10801                 +---------------------------------------+
10802                 | saved CR (C)                          | 8+P+A+V+L+X+W+Y+Z
10803                 +---------------------------------------+
10804                 | Save area for GP registers (G)        | 8+P+A+V+L+X+W+Y+Z+C
10805                 +---------------------------------------+
10806                 | Save area for FP registers (F)        | 8+P+A+V+L+X+W+Y+Z+C+G
10807                 +---------------------------------------+
10808         old SP->| back chain to caller's caller         |
10809                 +---------------------------------------+
10810
10811    The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10812    given.  (But note below and in sysv4.h that we require only 8 and
10813    may round up the size of our stack frame anyways.  The historical
10814    reason is early versions of powerpc-linux which didn't properly
10815    align the stack at program startup.  A happy side-effect is that
10816    -mno-eabi libraries can be used with -meabi programs.)
10817
10818    The EABI configuration defaults to the V.4 layout.  However,
10819    the stack alignment requirements may differ.  If -mno-eabi is not
10820    given, the required stack alignment is 8 bytes; if -mno-eabi is
10821    given, the required alignment is 16 bytes.  (But see V.4 comment
10822    above.)  */
10823
10824 #ifndef ABI_STACK_BOUNDARY
10825 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10826 #endif
10827
10828 static rs6000_stack_t *
10829 rs6000_stack_info (void)
10830 {
10831   static rs6000_stack_t info, zero_info;
10832   rs6000_stack_t *info_ptr = &info;
10833   int reg_size = TARGET_32BIT ? 4 : 8;
10834   int ehrd_size;
10835   HOST_WIDE_INT non_fixed_size;
10836
10837   /* Zero all fields portably.  */
10838   info = zero_info;
10839
10840   if (TARGET_SPE)
10841     {
10842       /* Cache value so we don't rescan instruction chain over and over.  */
10843       if (cfun->machine->insn_chain_scanned_p == 0)
10844         {
10845           cfun->machine->insn_chain_scanned_p = 1;
10846           info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10847         }
10848     }
10849
10850   /* Select which calling sequence.  */
10851   info_ptr->abi = DEFAULT_ABI;
10852
10853   /* Calculate which registers need to be saved & save area size.  */
10854   info_ptr->first_gp_reg_save = first_reg_to_save ();
10855   /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10856      even if it currently looks like we won't.  */
10857   if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10858        || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10859        || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10860       && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10861     info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10862   else
10863     info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10864
10865   /* For the SPE, we have an additional upper 32-bits on each GPR.
10866      Ideally we should save the entire 64-bits only when the upper
10867      half is used in SIMD instructions.  Since we only record
10868      registers live (not the size they are used in), this proves
10869      difficult because we'd have to traverse the instruction chain at
10870      the right time, taking reload into account.  This is a real pain,
10871      so we opt to save the GPRs in 64-bits always if but one register
10872      gets used in 64-bits.  Otherwise, all the registers in the frame
10873      get saved in 32-bits.
10874
10875      So... since when we save all GPRs (except the SP) in 64-bits, the
10876      traditional GP save area will be empty.  */
10877   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10878     info_ptr->gp_size = 0;
10879
10880   info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10881   info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10882
10883   info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10884   info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10885                                  - info_ptr->first_altivec_reg_save);
10886
10887   /* Does this function call anything?  */
10888   info_ptr->calls_p = (! current_function_is_leaf
10889                        || cfun->machine->ra_needs_full_frame);
10890
10891   /* Determine if we need to save the link register.  */
10892   if (rs6000_ra_ever_killed ()
10893       || (DEFAULT_ABI == ABI_AIX
10894           && current_function_profile
10895           && !TARGET_PROFILE_KERNEL)
10896 #ifdef TARGET_RELOCATABLE
10897       || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10898 #endif
10899       || (info_ptr->first_fp_reg_save != 64
10900           && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10901       || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10902       || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10903       || (DEFAULT_ABI == ABI_DARWIN
10904           && flag_pic
10905           && current_function_uses_pic_offset_table)
10906       || info_ptr->calls_p)
10907     {
10908       info_ptr->lr_save_p = 1;
10909       regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10910     }
10911
10912   /* Determine if we need to save the condition code registers.  */
10913   if (regs_ever_live[CR2_REGNO]
10914       || regs_ever_live[CR3_REGNO]
10915       || regs_ever_live[CR4_REGNO])
10916     {
10917       info_ptr->cr_save_p = 1;
10918       if (DEFAULT_ABI == ABI_V4)
10919         info_ptr->cr_size = reg_size;
10920     }
10921
10922   /* If the current function calls __builtin_eh_return, then we need
10923      to allocate stack space for registers that will hold data for
10924      the exception handler.  */
10925   if (current_function_calls_eh_return)
10926     {
10927       unsigned int i;
10928       for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10929         continue;
10930
10931       /* SPE saves EH registers in 64-bits.  */
10932       ehrd_size = i * (TARGET_SPE_ABI
10933                        && info_ptr->spe_64bit_regs_used != 0
10934                        ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10935     }
10936   else
10937     ehrd_size = 0;
10938
10939   /* Determine various sizes.  */
10940   info_ptr->reg_size     = reg_size;
10941   info_ptr->fixed_size   = RS6000_SAVE_AREA;
10942   info_ptr->varargs_size = RS6000_VARARGS_AREA;
10943   info_ptr->vars_size    = RS6000_ALIGN (get_frame_size (), 8);
10944   info_ptr->parm_size    = RS6000_ALIGN (current_function_outgoing_args_size,
10945                                          TARGET_ALTIVEC ? 16 : 8);
10946
10947   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10948     info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10949   else
10950     info_ptr->spe_gp_size = 0;
10951
10952   if (TARGET_ALTIVEC_ABI)
10953     info_ptr->vrsave_mask = compute_vrsave_mask ();
10954   else
10955     info_ptr->vrsave_mask = 0;
10956
10957   if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
10958     info_ptr->vrsave_size  = 4;
10959   else
10960     info_ptr->vrsave_size  = 0;
10961
10962   /* Calculate the offsets.  */
10963   switch (DEFAULT_ABI)
10964     {
10965     case ABI_NONE:
10966     default:
10967       abort ();
10968
10969     case ABI_AIX:
10970     case ABI_DARWIN:
10971       info_ptr->fp_save_offset   = - info_ptr->fp_size;
10972       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
10973
10974       if (TARGET_ALTIVEC_ABI)
10975         {
10976           info_ptr->vrsave_save_offset
10977             = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10978
10979           /* Align stack so vector save area is on a quadword boundary.  */
10980           if (info_ptr->altivec_size != 0)
10981             info_ptr->altivec_padding_size
10982               = 16 - (-info_ptr->vrsave_save_offset % 16);
10983           else
10984             info_ptr->altivec_padding_size = 0;
10985
10986           info_ptr->altivec_save_offset
10987             = info_ptr->vrsave_save_offset
10988             - info_ptr->altivec_padding_size
10989             - info_ptr->altivec_size;
10990
10991           /* Adjust for AltiVec case.  */
10992           info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10993         }
10994       else
10995         info_ptr->ehrd_offset      = info_ptr->gp_save_offset - ehrd_size;
10996       info_ptr->cr_save_offset   = reg_size; /* first word when 64-bit.  */
10997       info_ptr->lr_save_offset   = 2*reg_size;
10998       break;
10999
11000     case ABI_V4:
11001       info_ptr->fp_save_offset   = - info_ptr->fp_size;
11002       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
11003       info_ptr->cr_save_offset   = info_ptr->gp_save_offset - info_ptr->cr_size;
11004
11005       if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11006       {
11007         /* Align stack so SPE GPR save area is aligned on a
11008            double-word boundary.  */
11009         if (info_ptr->spe_gp_size != 0)
11010           info_ptr->spe_padding_size
11011             = 8 - (-info_ptr->cr_save_offset % 8);
11012         else
11013           info_ptr->spe_padding_size = 0;
11014
11015         info_ptr->spe_gp_save_offset
11016           = info_ptr->cr_save_offset
11017           - info_ptr->spe_padding_size
11018           - info_ptr->spe_gp_size;
11019
11020         /* Adjust for SPE case.  */
11021         info_ptr->toc_save_offset
11022           = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11023       }
11024       else if (TARGET_ALTIVEC_ABI)
11025         {
11026           info_ptr->vrsave_save_offset
11027             = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11028
11029           /* Align stack so vector save area is on a quadword boundary.  */
11030           if (info_ptr->altivec_size != 0)
11031             info_ptr->altivec_padding_size
11032               = 16 - (-info_ptr->vrsave_save_offset % 16);
11033           else
11034             info_ptr->altivec_padding_size = 0;
11035
11036           info_ptr->altivec_save_offset
11037             = info_ptr->vrsave_save_offset
11038             - info_ptr->altivec_padding_size
11039             - info_ptr->altivec_size;
11040
11041           /* Adjust for AltiVec case.  */
11042           info_ptr->toc_save_offset
11043             = info_ptr->altivec_save_offset - info_ptr->toc_size;
11044         }
11045       else
11046         info_ptr->toc_save_offset  = info_ptr->cr_save_offset - info_ptr->toc_size;
11047       info_ptr->ehrd_offset      = info_ptr->toc_save_offset - ehrd_size;
11048       info_ptr->lr_save_offset   = reg_size;
11049       break;
11050     }
11051
11052   info_ptr->save_size    = RS6000_ALIGN (info_ptr->fp_size
11053                                          + info_ptr->gp_size
11054                                          + info_ptr->altivec_size
11055                                          + info_ptr->altivec_padding_size
11056                                          + info_ptr->spe_gp_size
11057                                          + info_ptr->spe_padding_size
11058                                          + ehrd_size
11059                                          + info_ptr->cr_size
11060                                          + info_ptr->lr_size
11061                                          + info_ptr->vrsave_size
11062                                          + info_ptr->toc_size,
11063                                          (TARGET_ALTIVEC_ABI || ABI_DARWIN)
11064                                          ? 16 : 8);
11065
11066   non_fixed_size         = (info_ptr->vars_size
11067                             + info_ptr->parm_size
11068                             + info_ptr->save_size
11069                             + info_ptr->varargs_size);
11070
11071   info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11072                                        ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11073
11074   /* Determine if we need to allocate any stack frame:
11075
11076      For AIX we need to push the stack if a frame pointer is needed
11077      (because the stack might be dynamically adjusted), if we are
11078      debugging, if we make calls, or if the sum of fp_save, gp_save,
11079      and local variables are more than the space needed to save all
11080      non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11081      + 18*8 = 288 (GPR13 reserved).
11082
11083      For V.4 we don't have the stack cushion that AIX uses, but assume
11084      that the debugger can handle stackless frames.  */
11085
11086   if (info_ptr->calls_p)
11087     info_ptr->push_p = 1;
11088
11089   else if (DEFAULT_ABI == ABI_V4)
11090     info_ptr->push_p = non_fixed_size != 0;
11091
11092   else if (frame_pointer_needed)
11093     info_ptr->push_p = 1;
11094
11095   else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11096     info_ptr->push_p = 1;
11097
11098   else
11099     info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11100
11101   /* Zero offsets if we're not saving those registers.  */
11102   if (info_ptr->fp_size == 0)
11103     info_ptr->fp_save_offset = 0;
11104
11105   if (info_ptr->gp_size == 0)
11106     info_ptr->gp_save_offset = 0;
11107
11108   if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11109     info_ptr->altivec_save_offset = 0;
11110
11111   if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11112     info_ptr->vrsave_save_offset = 0;
11113
11114   if (! TARGET_SPE_ABI
11115       || info_ptr->spe_64bit_regs_used == 0
11116       || info_ptr->spe_gp_size == 0)
11117     info_ptr->spe_gp_save_offset = 0;
11118
11119   if (! info_ptr->lr_save_p)
11120     info_ptr->lr_save_offset = 0;
11121
11122   if (! info_ptr->cr_save_p)
11123     info_ptr->cr_save_offset = 0;
11124
11125   if (! info_ptr->toc_save_p)
11126     info_ptr->toc_save_offset = 0;
11127
11128   return info_ptr;
11129 }
11130
11131 /* Return true if the current function uses any GPRs in 64-bit SIMD
11132    mode.  */
11133
11134 static bool
11135 spe_func_has_64bit_regs_p (void)
11136 {
11137   rtx insns, insn;
11138
11139   /* Functions that save and restore all the call-saved registers will
11140      need to save/restore the registers in 64-bits.  */
11141   if (current_function_calls_eh_return
11142       || current_function_calls_setjmp
11143       || current_function_has_nonlocal_goto)
11144     return true;
11145
11146   insns = get_insns ();
11147
11148   for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11149     {
11150       if (INSN_P (insn))
11151         {
11152           rtx i;
11153
11154           i = PATTERN (insn);
11155           if (GET_CODE (i) == SET
11156               && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
11157             return true;
11158         }
11159     }
11160
11161   return false;
11162 }
11163
11164 static void
11165 debug_stack_info (rs6000_stack_t *info)
11166 {
11167   const char *abi_string;
11168
11169   if (! info)
11170     info = rs6000_stack_info ();
11171
11172   fprintf (stderr, "\nStack information for function %s:\n",
11173            ((current_function_decl && DECL_NAME (current_function_decl))
11174             ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11175             : "<unknown>"));
11176
11177   switch (info->abi)
11178     {
11179     default:             abi_string = "Unknown";        break;
11180     case ABI_NONE:       abi_string = "NONE";           break;
11181     case ABI_AIX:        abi_string = "AIX";            break;
11182     case ABI_DARWIN:     abi_string = "Darwin";         break;
11183     case ABI_V4:         abi_string = "V.4";            break;
11184     }
11185
11186   fprintf (stderr, "\tABI                 = %5s\n", abi_string);
11187
11188   if (TARGET_ALTIVEC_ABI)
11189     fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11190
11191   if (TARGET_SPE_ABI)
11192     fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11193
11194   if (info->first_gp_reg_save != 32)
11195     fprintf (stderr, "\tfirst_gp_reg_save   = %5d\n", info->first_gp_reg_save);
11196
11197   if (info->first_fp_reg_save != 64)
11198     fprintf (stderr, "\tfirst_fp_reg_save   = %5d\n", info->first_fp_reg_save);
11199
11200   if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11201     fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11202              info->first_altivec_reg_save);
11203
11204   if (info->lr_save_p)
11205     fprintf (stderr, "\tlr_save_p           = %5d\n", info->lr_save_p);
11206
11207   if (info->cr_save_p)
11208     fprintf (stderr, "\tcr_save_p           = %5d\n", info->cr_save_p);
11209
11210   if (info->toc_save_p)
11211     fprintf (stderr, "\ttoc_save_p          = %5d\n", info->toc_save_p);
11212
11213   if (info->vrsave_mask)
11214     fprintf (stderr, "\tvrsave_mask         = 0x%x\n", info->vrsave_mask);
11215
11216   if (info->push_p)
11217     fprintf (stderr, "\tpush_p              = %5d\n", info->push_p);
11218
11219   if (info->calls_p)
11220     fprintf (stderr, "\tcalls_p             = %5d\n", info->calls_p);
11221
11222   if (info->gp_save_offset)
11223     fprintf (stderr, "\tgp_save_offset      = %5d\n", info->gp_save_offset);
11224
11225   if (info->fp_save_offset)
11226     fprintf (stderr, "\tfp_save_offset      = %5d\n", info->fp_save_offset);
11227
11228   if (info->altivec_save_offset)
11229     fprintf (stderr, "\taltivec_save_offset = %5d\n",
11230              info->altivec_save_offset);
11231
11232   if (info->spe_gp_save_offset)
11233     fprintf (stderr, "\tspe_gp_save_offset  = %5d\n",
11234              info->spe_gp_save_offset);
11235
11236   if (info->vrsave_save_offset)
11237     fprintf (stderr, "\tvrsave_save_offset  = %5d\n",
11238              info->vrsave_save_offset);
11239
11240   if (info->lr_save_offset)
11241     fprintf (stderr, "\tlr_save_offset      = %5d\n", info->lr_save_offset);
11242
11243   if (info->cr_save_offset)
11244     fprintf (stderr, "\tcr_save_offset      = %5d\n", info->cr_save_offset);
11245
11246   if (info->toc_save_offset)
11247     fprintf (stderr, "\ttoc_save_offset     = %5d\n", info->toc_save_offset);
11248
11249   if (info->varargs_save_offset)
11250     fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11251
11252   if (info->total_size)
11253     fprintf (stderr, "\ttotal_size          = "HOST_WIDE_INT_PRINT_DEC"\n",
11254              info->total_size);
11255
11256   if (info->varargs_size)
11257     fprintf (stderr, "\tvarargs_size        = %5d\n", info->varargs_size);
11258
11259   if (info->vars_size)
11260     fprintf (stderr, "\tvars_size           = "HOST_WIDE_INT_PRINT_DEC"\n",
11261              info->vars_size);
11262
11263   if (info->parm_size)
11264     fprintf (stderr, "\tparm_size           = %5d\n", info->parm_size);
11265
11266   if (info->fixed_size)
11267     fprintf (stderr, "\tfixed_size          = %5d\n", info->fixed_size);
11268
11269   if (info->gp_size)
11270     fprintf (stderr, "\tgp_size             = %5d\n", info->gp_size);
11271
11272   if (info->spe_gp_size)
11273     fprintf (stderr, "\tspe_gp_size         = %5d\n", info->spe_gp_size);
11274
11275   if (info->fp_size)
11276     fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
11277
11278   if (info->altivec_size)
11279     fprintf (stderr, "\taltivec_size        = %5d\n", info->altivec_size);
11280
11281   if (info->vrsave_size)
11282     fprintf (stderr, "\tvrsave_size         = %5d\n", info->vrsave_size);
11283
11284   if (info->altivec_padding_size)
11285     fprintf (stderr, "\taltivec_padding_size= %5d\n",
11286              info->altivec_padding_size);
11287
11288   if (info->spe_padding_size)
11289     fprintf (stderr, "\tspe_padding_size    = %5d\n",
11290              info->spe_padding_size);
11291
11292   if (info->lr_size)
11293     fprintf (stderr, "\tlr_size             = %5d\n", info->lr_size);
11294
11295   if (info->cr_size)
11296     fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
11297
11298   if (info->toc_size)
11299     fprintf (stderr, "\ttoc_size            = %5d\n", info->toc_size);
11300
11301   if (info->save_size)
11302     fprintf (stderr, "\tsave_size           = %5d\n", info->save_size);
11303
11304   if (info->reg_size != 4)
11305     fprintf (stderr, "\treg_size            = %5d\n", info->reg_size);
11306
11307   fprintf (stderr, "\n");
11308 }
11309
11310 rtx
11311 rs6000_return_addr (int count, rtx frame)
11312 {
11313   /* Currently we don't optimize very well between prolog and body
11314      code and for PIC code the code can be actually quite bad, so
11315      don't try to be too clever here.  */
11316   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11317     {
11318       cfun->machine->ra_needs_full_frame = 1;
11319
11320       return
11321         gen_rtx_MEM
11322           (Pmode,
11323            memory_address
11324            (Pmode,
11325             plus_constant (copy_to_reg
11326                            (gen_rtx_MEM (Pmode,
11327                                          memory_address (Pmode, frame))),
11328                            RETURN_ADDRESS_OFFSET)));
11329     }
11330
11331   cfun->machine->ra_need_lr = 1;
11332   return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11333 }
11334
11335 /* Say whether a function is a candidate for sibcall handling or not.
11336    We do not allow indirect calls to be optimized into sibling calls.
11337    Also, we can't do it if there are any vector parameters; there's
11338    nowhere to put the VRsave code so it works; note that functions with
11339    vector parameters are required to have a prototype, so the argument
11340    type info must be available here.  (The tail recursion case can work
11341    with vector parameters, but there's no way to distinguish here.) */
11342 static bool
11343 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11344 {
11345   tree type;
11346   if (decl)
11347     {
11348       if (TARGET_ALTIVEC_VRSAVE)
11349         {
11350           for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11351                type; type = TREE_CHAIN (type))
11352             {
11353               if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11354                 return false;
11355             }
11356         }
11357       if (DEFAULT_ABI == ABI_DARWIN
11358           || (*targetm.binds_local_p) (decl))
11359         {
11360           tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11361
11362           if (!lookup_attribute ("longcall", attr_list)
11363               || lookup_attribute ("shortcall", attr_list))
11364             return true;
11365         }
11366     }
11367   return false;
11368 }
11369
11370 static int
11371 rs6000_ra_ever_killed (void)
11372 {
11373   rtx top;
11374   rtx reg;
11375   rtx insn;
11376
11377   if (current_function_is_thunk)
11378     return 0;
11379
11380   /* regs_ever_live has LR marked as used if any sibcalls are present,
11381      but this should not force saving and restoring in the
11382      pro/epilogue.  Likewise, reg_set_between_p thinks a sibcall
11383      clobbers LR, so that is inappropriate.  */
11384
11385   /* Also, the prologue can generate a store into LR that
11386      doesn't really count, like this:
11387
11388         move LR->R0
11389         bcl to set PIC register
11390         move LR->R31
11391         move R0->LR
11392
11393      When we're called from the epilogue, we need to avoid counting
11394      this as a store.  */
11395
11396   push_topmost_sequence ();
11397   top = get_insns ();
11398   pop_topmost_sequence ();
11399   reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11400
11401   for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11402     {
11403       if (INSN_P (insn))
11404         {
11405           if (FIND_REG_INC_NOTE (insn, reg))
11406             return 1;
11407           else if (GET_CODE (insn) == CALL_INSN
11408                    && !SIBLING_CALL_P (insn))
11409             return 1;
11410           else if (set_of (reg, insn) != NULL_RTX
11411                    && !prologue_epilogue_contains (insn))
11412             return 1;
11413         }
11414     }
11415   return 0;
11416 }
11417 \f
11418 /* Add a REG_MAYBE_DEAD note to the insn.  */
11419 static void
11420 rs6000_maybe_dead (rtx insn)
11421 {
11422   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11423                                         const0_rtx,
11424                                         REG_NOTES (insn));
11425 }
11426
11427 /* Emit instructions needed to load the TOC register.
11428    This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11429    a constant pool; or for SVR4 -fpic.  */
11430
11431 void
11432 rs6000_emit_load_toc_table (int fromprolog)
11433 {
11434   rtx dest, insn;
11435   dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11436
11437   if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11438     {
11439       rtx temp = (fromprolog
11440                   ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11441                   : gen_reg_rtx (Pmode));
11442       insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11443       if (fromprolog)
11444         rs6000_maybe_dead (insn);
11445       insn = emit_move_insn (dest, temp);
11446       if (fromprolog)
11447         rs6000_maybe_dead (insn);
11448     }
11449   else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11450     {
11451       char buf[30];
11452       rtx tempLR = (fromprolog
11453                     ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11454                     : gen_reg_rtx (Pmode));
11455       rtx temp0 = (fromprolog
11456                    ? gen_rtx_REG (Pmode, 0)
11457                    : gen_reg_rtx (Pmode));
11458       rtx symF;
11459
11460       /* possibly create the toc section */
11461       if (! toc_initialized)
11462         {
11463           toc_section ();
11464           function_section (current_function_decl);
11465         }
11466
11467       if (fromprolog)
11468         {
11469           rtx symL;
11470
11471           ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11472           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11473
11474           ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11475           symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11476
11477           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11478                                                                symF)));
11479           rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11480           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
11481                                                                symL,
11482                                                                symF)));
11483         }
11484       else
11485         {
11486           rtx tocsym;
11487           static int reload_toc_labelno = 0;
11488
11489           tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11490
11491           ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11492           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11493
11494           emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11495           emit_move_insn (dest, tempLR);
11496           emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11497         }
11498       insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11499       if (fromprolog)
11500         rs6000_maybe_dead (insn);
11501     }
11502   else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11503     {
11504       /* This is for AIX code running in non-PIC ELF32.  */
11505       char buf[30];
11506       rtx realsym;
11507       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11508       realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11509
11510       insn = emit_insn (gen_elf_high (dest, realsym));
11511       if (fromprolog)
11512         rs6000_maybe_dead (insn);
11513       insn = emit_insn (gen_elf_low (dest, dest, realsym));
11514       if (fromprolog)
11515         rs6000_maybe_dead (insn);
11516     }
11517   else if (DEFAULT_ABI == ABI_AIX)
11518     {
11519       if (TARGET_32BIT)
11520         insn = emit_insn (gen_load_toc_aix_si (dest));
11521       else
11522         insn = emit_insn (gen_load_toc_aix_di (dest));
11523       if (fromprolog)
11524         rs6000_maybe_dead (insn);
11525     }
11526   else
11527     abort ();
11528 }
11529
11530 /* Emit instructions to restore the link register after determining where
11531    its value has been stored.  */
11532
11533 void
11534 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11535 {
11536   rs6000_stack_t *info = rs6000_stack_info ();
11537   rtx operands[2];
11538
11539   operands[0] = source;
11540   operands[1] = scratch;
11541
11542   if (info->lr_save_p)
11543     {
11544       rtx frame_rtx = stack_pointer_rtx;
11545       HOST_WIDE_INT sp_offset = 0;
11546       rtx tmp;
11547
11548       if (frame_pointer_needed
11549           || current_function_calls_alloca
11550           || info->total_size > 32767)
11551         {
11552           emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11553           frame_rtx = operands[1];
11554         }
11555       else if (info->push_p)
11556         sp_offset = info->total_size;
11557
11558       tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11559       tmp = gen_rtx_MEM (Pmode, tmp);
11560       emit_move_insn (tmp, operands[0]);
11561     }
11562   else
11563     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11564 }
11565
11566 static GTY(()) int set = -1;
11567
11568 int
11569 get_TOC_alias_set (void)
11570 {
11571   if (set == -1)
11572     set = new_alias_set ();
11573   return set;
11574 }
11575
11576 /* This returns nonzero if the current function uses the TOC.  This is
11577    determined by the presence of (use (unspec ... UNSPEC_TOC)), which
11578    is generated by the ABI_V4 load_toc_* patterns.  */
11579 #if TARGET_ELF
11580 static int
11581 uses_TOC (void)
11582 {
11583   rtx insn;
11584
11585   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11586     if (INSN_P (insn))
11587       {
11588         rtx pat = PATTERN (insn);
11589         int i;
11590
11591         if (GET_CODE (pat) == PARALLEL)
11592           for (i = 0; i < XVECLEN (pat, 0); i++)
11593             {
11594               rtx sub = XVECEXP (pat, 0, i);
11595               if (GET_CODE (sub) == USE)
11596                 {
11597                   sub = XEXP (sub, 0);
11598                   if (GET_CODE (sub) == UNSPEC
11599                       && XINT (sub, 1) == UNSPEC_TOC)
11600                     return 1;
11601                 }
11602             }
11603       }
11604   return 0;
11605 }
11606 #endif
11607
11608 rtx
11609 create_TOC_reference (rtx symbol)
11610 {
11611   return gen_rtx_PLUS (Pmode,
11612            gen_rtx_REG (Pmode, TOC_REGISTER),
11613              gen_rtx_CONST (Pmode,
11614                gen_rtx_MINUS (Pmode, symbol,
11615                  gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11616 }
11617
11618 /* If _Unwind_* has been called from within the same module,
11619    toc register is not guaranteed to be saved to 40(1) on function
11620    entry.  Save it there in that case.  */
11621
11622 void
11623 rs6000_aix_emit_builtin_unwind_init (void)
11624 {
11625   rtx mem;
11626   rtx stack_top = gen_reg_rtx (Pmode);
11627   rtx opcode_addr = gen_reg_rtx (Pmode);
11628   rtx opcode = gen_reg_rtx (SImode);
11629   rtx tocompare = gen_reg_rtx (SImode);
11630   rtx no_toc_save_needed = gen_label_rtx ();
11631
11632   mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11633   emit_move_insn (stack_top, mem);
11634
11635   mem = gen_rtx_MEM (Pmode,
11636                      gen_rtx_PLUS (Pmode, stack_top,
11637                                    GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11638   emit_move_insn (opcode_addr, mem);
11639   emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11640   emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11641                                            : 0xE8410028, SImode));
11642
11643   do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11644                            SImode, NULL_RTX, NULL_RTX,
11645                            no_toc_save_needed);
11646
11647   mem = gen_rtx_MEM (Pmode,
11648                      gen_rtx_PLUS (Pmode, stack_top,
11649                                    GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11650   emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11651   emit_label (no_toc_save_needed);
11652 }
11653 \f
11654 /* This ties together stack memory (MEM with an alias set of
11655    rs6000_sr_alias_set) and the change to the stack pointer.  */
11656
11657 static void
11658 rs6000_emit_stack_tie (void)
11659 {
11660   rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11661
11662   set_mem_alias_set (mem, rs6000_sr_alias_set);
11663   emit_insn (gen_stack_tie (mem));
11664 }
11665
11666 /* Emit the correct code for allocating stack space, as insns.
11667    If COPY_R12, make sure a copy of the old frame is left in r12.
11668    The generated code may use hard register 0 as a temporary.  */
11669
11670 static void
11671 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11672 {
11673   rtx insn;
11674   rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11675   rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11676   rtx todec = GEN_INT (-size);
11677
11678   if (current_function_limit_stack)
11679     {
11680       if (REG_P (stack_limit_rtx)
11681           && REGNO (stack_limit_rtx) > 1
11682           && REGNO (stack_limit_rtx) <= 31)
11683         {
11684           emit_insn (TARGET_32BIT
11685                      ? gen_addsi3 (tmp_reg,
11686                                    stack_limit_rtx,
11687                                    GEN_INT (size))
11688                      : gen_adddi3 (tmp_reg,
11689                                    stack_limit_rtx,
11690                                    GEN_INT (size)));
11691
11692           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11693                                     const0_rtx));
11694         }
11695       else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11696                && TARGET_32BIT
11697                && DEFAULT_ABI == ABI_V4)
11698         {
11699           rtx toload = gen_rtx_CONST (VOIDmode,
11700                                       gen_rtx_PLUS (Pmode,
11701                                                     stack_limit_rtx,
11702                                                     GEN_INT (size)));
11703
11704           emit_insn (gen_elf_high (tmp_reg, toload));
11705           emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11706           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11707                                     const0_rtx));
11708         }
11709       else
11710         warning ("stack limit expression is not supported");
11711     }
11712
11713   if (copy_r12 || ! TARGET_UPDATE)
11714     emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11715
11716   if (TARGET_UPDATE)
11717     {
11718       if (size > 32767)
11719         {
11720           /* Need a note here so that try_split doesn't get confused.  */
11721           if (get_last_insn() == NULL_RTX)
11722             emit_note (NOTE_INSN_DELETED);
11723           insn = emit_move_insn (tmp_reg, todec);
11724           try_split (PATTERN (insn), insn, 0);
11725           todec = tmp_reg;
11726         }
11727
11728       insn = emit_insn (TARGET_32BIT
11729                         ? gen_movsi_update (stack_reg, stack_reg,
11730                                             todec, stack_reg)
11731                         : gen_movdi_update (stack_reg, stack_reg,
11732                                             todec, stack_reg));
11733     }
11734   else
11735     {
11736       insn = emit_insn (TARGET_32BIT
11737                         ? gen_addsi3 (stack_reg, stack_reg, todec)
11738                         : gen_adddi3 (stack_reg, stack_reg, todec));
11739       emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11740                       gen_rtx_REG (Pmode, 12));
11741     }
11742
11743   RTX_FRAME_RELATED_P (insn) = 1;
11744   REG_NOTES (insn) =
11745     gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11746                        gen_rtx_SET (VOIDmode, stack_reg,
11747                                     gen_rtx_PLUS (Pmode, stack_reg,
11748                                                   GEN_INT (-size))),
11749                        REG_NOTES (insn));
11750 }
11751
11752 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11753    with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11754    is not NULL.  It would be nice if dwarf2out_frame_debug_expr could
11755    deduce these equivalences by itself so it wasn't necessary to hold
11756    its hand so much.  */
11757
11758 static void
11759 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11760                       rtx reg2, rtx rreg)
11761 {
11762   rtx real, temp;
11763
11764   /* copy_rtx will not make unique copies of registers, so we need to
11765      ensure we don't have unwanted sharing here.  */
11766   if (reg == reg2)
11767     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11768
11769   if (reg == rreg)
11770     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11771
11772   real = copy_rtx (PATTERN (insn));
11773
11774   if (reg2 != NULL_RTX)
11775     real = replace_rtx (real, reg2, rreg);
11776
11777   real = replace_rtx (real, reg,
11778                       gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11779                                                         STACK_POINTER_REGNUM),
11780                                     GEN_INT (val)));
11781
11782   /* We expect that 'real' is either a SET or a PARALLEL containing
11783      SETs (and possibly other stuff).  In a PARALLEL, all the SETs
11784      are important so they all have to be marked RTX_FRAME_RELATED_P.  */
11785
11786   if (GET_CODE (real) == SET)
11787     {
11788       rtx set = real;
11789
11790       temp = simplify_rtx (SET_SRC (set));
11791       if (temp)
11792         SET_SRC (set) = temp;
11793       temp = simplify_rtx (SET_DEST (set));
11794       if (temp)
11795         SET_DEST (set) = temp;
11796       if (GET_CODE (SET_DEST (set)) == MEM)
11797         {
11798           temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11799           if (temp)
11800             XEXP (SET_DEST (set), 0) = temp;
11801         }
11802     }
11803   else if (GET_CODE (real) == PARALLEL)
11804     {
11805       int i;
11806       for (i = 0; i < XVECLEN (real, 0); i++)
11807         if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11808           {
11809             rtx set = XVECEXP (real, 0, i);
11810
11811             temp = simplify_rtx (SET_SRC (set));
11812             if (temp)
11813               SET_SRC (set) = temp;
11814             temp = simplify_rtx (SET_DEST (set));
11815             if (temp)
11816               SET_DEST (set) = temp;
11817             if (GET_CODE (SET_DEST (set)) == MEM)
11818               {
11819                 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11820                 if (temp)
11821                   XEXP (SET_DEST (set), 0) = temp;
11822               }
11823             RTX_FRAME_RELATED_P (set) = 1;
11824           }
11825     }
11826   else
11827     abort ();
11828
11829   if (TARGET_SPE)
11830     real = spe_synthesize_frame_save (real);
11831
11832   RTX_FRAME_RELATED_P (insn) = 1;
11833   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11834                                         real,
11835                                         REG_NOTES (insn));
11836 }
11837
11838 /* Given an SPE frame note, return a PARALLEL of SETs with the
11839    original note, plus a synthetic register save.  */
11840
11841 static rtx
11842 spe_synthesize_frame_save (rtx real)
11843 {
11844   rtx synth, offset, reg, real2;
11845
11846   if (GET_CODE (real) != SET
11847       || GET_MODE (SET_SRC (real)) != V2SImode)
11848     return real;
11849
11850   /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11851      frame related note.  The parallel contains a set of the register
11852      being saved, and another set to a synthetic register (n+1200).
11853      This is so we can differentiate between 64-bit and 32-bit saves.
11854      Words cannot describe this nastiness.  */
11855
11856   if (GET_CODE (SET_DEST (real)) != MEM
11857       || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11858       || GET_CODE (SET_SRC (real)) != REG)
11859     abort ();
11860
11861   /* Transform:
11862        (set (mem (plus (reg x) (const y)))
11863             (reg z))
11864      into:
11865        (set (mem (plus (reg x) (const y+4)))
11866             (reg z+1200))
11867   */
11868
11869   real2 = copy_rtx (real);
11870   PUT_MODE (SET_DEST (real2), SImode);
11871   reg = SET_SRC (real2);
11872   real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11873   synth = copy_rtx (real2);
11874
11875   if (BYTES_BIG_ENDIAN)
11876     {
11877       offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11878       real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11879     }
11880
11881   reg = SET_SRC (synth);
11882
11883   synth = replace_rtx (synth, reg,
11884                        gen_rtx_REG (SImode, REGNO (reg) + 1200));
11885
11886   offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11887   synth = replace_rtx (synth, offset,
11888                        GEN_INT (INTVAL (offset)
11889                                 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11890
11891   RTX_FRAME_RELATED_P (synth) = 1;
11892   RTX_FRAME_RELATED_P (real2) = 1;
11893   if (BYTES_BIG_ENDIAN)
11894     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11895   else
11896     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11897
11898   return real;
11899 }
11900
11901 /* Returns an insn that has a vrsave set operation with the
11902    appropriate CLOBBERs.  */
11903
11904 static rtx
11905 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11906 {
11907   int nclobs, i;
11908   rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11909   rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11910
11911   clobs[0]
11912     = gen_rtx_SET (VOIDmode,
11913                    vrsave,
11914                    gen_rtx_UNSPEC_VOLATILE (SImode,
11915                                             gen_rtvec (2, reg, vrsave),
11916                                             30));
11917
11918   nclobs = 1;
11919
11920   /* We need to clobber the registers in the mask so the scheduler
11921      does not move sets to VRSAVE before sets of AltiVec registers.
11922
11923      However, if the function receives nonlocal gotos, reload will set
11924      all call saved registers live.  We will end up with:
11925
11926         (set (reg 999) (mem))
11927         (parallel [ (set (reg vrsave) (unspec blah))
11928                     (clobber (reg 999))])
11929
11930      The clobber will cause the store into reg 999 to be dead, and
11931      flow will attempt to delete an epilogue insn.  In this case, we
11932      need an unspec use/set of the register.  */
11933
11934   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11935     if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
11936       {
11937         if (!epiloguep || call_used_regs [i])
11938           clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11939                                              gen_rtx_REG (V4SImode, i));
11940         else
11941           {
11942             rtx reg = gen_rtx_REG (V4SImode, i);
11943
11944             clobs[nclobs++]
11945               = gen_rtx_SET (VOIDmode,
11946                              reg,
11947                              gen_rtx_UNSPEC (V4SImode,
11948                                              gen_rtvec (1, reg), 27));
11949           }
11950       }
11951
11952   insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11953
11954   for (i = 0; i < nclobs; ++i)
11955     XVECEXP (insn, 0, i) = clobs[i];
11956
11957   return insn;
11958 }
11959
11960 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11961    Save REGNO into [FRAME_REG + OFFSET] in mode MODE.  */
11962
11963 static void
11964 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11965                  unsigned int regno, int offset, HOST_WIDE_INT total_size)
11966 {
11967   rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11968   rtx replacea, replaceb;
11969
11970   int_rtx = GEN_INT (offset);
11971
11972   /* Some cases that need register indexed addressing.  */
11973   if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11974       || (TARGET_SPE_ABI
11975           && SPE_VECTOR_MODE (mode)
11976           && !SPE_CONST_OFFSET_OK (offset)))
11977     {
11978       /* Whomever calls us must make sure r11 is available in the
11979          flow path of instructions in the prologue.  */
11980       offset_rtx = gen_rtx_REG (Pmode, 11);
11981       emit_move_insn (offset_rtx, int_rtx);
11982
11983       replacea = offset_rtx;
11984       replaceb = int_rtx;
11985     }
11986   else
11987     {
11988       offset_rtx = int_rtx;
11989       replacea = NULL_RTX;
11990       replaceb = NULL_RTX;
11991     }
11992
11993   reg = gen_rtx_REG (mode, regno);
11994   addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11995   mem = gen_rtx_MEM (mode, addr);
11996   set_mem_alias_set (mem, rs6000_sr_alias_set);
11997
11998   insn = emit_move_insn (mem, reg);
11999
12000   rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12001 }
12002
12003 /* Emit an offset memory reference suitable for a frame store, while
12004    converting to a valid addressing mode.  */
12005
12006 static rtx
12007 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12008 {
12009   rtx int_rtx, offset_rtx;
12010
12011   int_rtx = GEN_INT (offset);
12012
12013   if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12014     {
12015       offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12016       emit_move_insn (offset_rtx, int_rtx);
12017     }
12018   else
12019     offset_rtx = int_rtx;
12020
12021   return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12022 }
12023
12024 /* Emit function prologue as insns.  */
12025
12026 void
12027 rs6000_emit_prologue (void)
12028 {
12029   rs6000_stack_t *info = rs6000_stack_info ();
12030   enum machine_mode reg_mode = Pmode;
12031   int reg_size = TARGET_32BIT ? 4 : 8;
12032   rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12033   rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12034   rtx frame_reg_rtx = sp_reg_rtx;
12035   rtx cr_save_rtx = NULL_RTX;
12036   rtx insn;
12037   int saving_FPRs_inline;
12038   int using_store_multiple;
12039   HOST_WIDE_INT sp_offset = 0;
12040
12041    if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12042      {
12043        reg_mode = V2SImode;
12044        reg_size = 8;
12045      }
12046
12047   using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12048                           && (!TARGET_SPE_ABI
12049                               || info->spe_64bit_regs_used == 0)
12050                           && info->first_gp_reg_save < 31);
12051   saving_FPRs_inline = (info->first_fp_reg_save == 64
12052                         || FP_SAVE_INLINE (info->first_fp_reg_save)
12053                         || current_function_calls_eh_return
12054                         || cfun->machine->ra_need_lr);
12055
12056   /* For V.4, update stack before we do any saving and set back pointer.  */
12057   if (info->push_p
12058       && (DEFAULT_ABI == ABI_V4
12059           || current_function_calls_eh_return))
12060     {
12061       if (info->total_size < 32767)
12062         sp_offset = info->total_size;
12063       else
12064         frame_reg_rtx = frame_ptr_rtx;
12065       rs6000_emit_allocate_stack (info->total_size,
12066                                   (frame_reg_rtx != sp_reg_rtx
12067                                    && (info->cr_save_p
12068                                        || info->lr_save_p
12069                                        || info->first_fp_reg_save < 64
12070                                        || info->first_gp_reg_save < 32
12071                                        )));
12072       if (frame_reg_rtx != sp_reg_rtx)
12073         rs6000_emit_stack_tie ();
12074     }
12075
12076   /* Save AltiVec registers if needed.  */
12077   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12078     {
12079       int i;
12080
12081       /* There should be a non inline version of this, for when we
12082          are saving lots of vector registers.  */
12083       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12084         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12085           {
12086             rtx areg, savereg, mem;
12087             int offset;
12088
12089             offset = info->altivec_save_offset + sp_offset
12090               + 16 * (i - info->first_altivec_reg_save);
12091
12092             savereg = gen_rtx_REG (V4SImode, i);
12093
12094             areg = gen_rtx_REG (Pmode, 0);
12095             emit_move_insn (areg, GEN_INT (offset));
12096
12097             /* AltiVec addressing mode is [reg+reg].  */
12098             mem = gen_rtx_MEM (V4SImode,
12099                                gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12100
12101             set_mem_alias_set (mem, rs6000_sr_alias_set);
12102
12103             insn = emit_move_insn (mem, savereg);
12104
12105             rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12106                                   areg, GEN_INT (offset));
12107           }
12108     }
12109
12110   /* VRSAVE is a bit vector representing which AltiVec registers
12111      are used.  The OS uses this to determine which vector
12112      registers to save on a context switch.  We need to save
12113      VRSAVE on the stack frame, add whatever AltiVec registers we
12114      used in this function, and do the corresponding magic in the
12115      epilogue.  */
12116
12117   if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12118       && info->vrsave_mask != 0)
12119     {
12120       rtx reg, mem, vrsave;
12121       int offset;
12122
12123       /* Get VRSAVE onto a GPR.  */
12124       reg = gen_rtx_REG (SImode, 12);
12125       vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12126       if (TARGET_MACHO)
12127         emit_insn (gen_get_vrsave_internal (reg));
12128       else
12129         emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12130
12131       /* Save VRSAVE.  */
12132       offset = info->vrsave_save_offset + sp_offset;
12133       mem
12134         = gen_rtx_MEM (SImode,
12135                        gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12136       set_mem_alias_set (mem, rs6000_sr_alias_set);
12137       insn = emit_move_insn (mem, reg);
12138
12139       /* Include the registers in the mask.  */
12140       emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12141
12142       insn = emit_insn (generate_set_vrsave (reg, info, 0));
12143     }
12144
12145   /* If we use the link register, get it into r0.  */
12146   if (info->lr_save_p)
12147     emit_move_insn (gen_rtx_REG (Pmode, 0),
12148                     gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12149
12150   /* If we need to save CR, put it into r12.  */
12151   if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12152     {
12153       cr_save_rtx = gen_rtx_REG (SImode, 12);
12154       emit_insn (gen_movesi_from_cr (cr_save_rtx));
12155     }
12156
12157   /* Do any required saving of fpr's.  If only one or two to save, do
12158      it ourselves.  Otherwise, call function.  */
12159   if (saving_FPRs_inline)
12160     {
12161       int i;
12162       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12163         if ((regs_ever_live[info->first_fp_reg_save+i]
12164              && ! call_used_regs[info->first_fp_reg_save+i]))
12165           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12166                            info->first_fp_reg_save + i,
12167                            info->fp_save_offset + sp_offset + 8 * i,
12168                            info->total_size);
12169     }
12170   else if (info->first_fp_reg_save != 64)
12171     {
12172       int i;
12173       char rname[30];
12174       const char *alloc_rname;
12175       rtvec p;
12176       p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12177
12178       RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12179                                           gen_rtx_REG (Pmode,
12180                                                        LINK_REGISTER_REGNUM));
12181       sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12182                info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12183       alloc_rname = ggc_strdup (rname);
12184       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12185                                       gen_rtx_SYMBOL_REF (Pmode,
12186                                                           alloc_rname));
12187       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12188         {
12189           rtx addr, reg, mem;
12190           reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12191           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12192                                GEN_INT (info->fp_save_offset
12193                                         + sp_offset + 8*i));
12194           mem = gen_rtx_MEM (DFmode, addr);
12195           set_mem_alias_set (mem, rs6000_sr_alias_set);
12196
12197           RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12198         }
12199       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12200       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12201                             NULL_RTX, NULL_RTX);
12202     }
12203
12204   /* Save GPRs.  This is done as a PARALLEL if we are using
12205      the store-multiple instructions.  */
12206   if (using_store_multiple)
12207     {
12208       rtvec p;
12209       int i;
12210       p = rtvec_alloc (32 - info->first_gp_reg_save);
12211       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12212         {
12213           rtx addr, reg, mem;
12214           reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12215           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12216                                GEN_INT (info->gp_save_offset
12217                                         + sp_offset
12218                                         + reg_size * i));
12219           mem = gen_rtx_MEM (reg_mode, addr);
12220           set_mem_alias_set (mem, rs6000_sr_alias_set);
12221
12222           RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12223         }
12224       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12225       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12226                             NULL_RTX, NULL_RTX);
12227     }
12228   else
12229     {
12230       int i;
12231       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12232         if ((regs_ever_live[info->first_gp_reg_save+i]
12233              && ! call_used_regs[info->first_gp_reg_save+i])
12234             || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12235                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12236                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12237           {
12238             rtx addr, reg, mem;
12239             reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12240
12241             if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12242               {
12243                 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12244                 rtx b;
12245
12246                 if (!SPE_CONST_OFFSET_OK (offset))
12247                   {
12248                     b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12249                     emit_move_insn (b, GEN_INT (offset));
12250                   }
12251                 else
12252                   b = GEN_INT (offset);
12253
12254                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12255                 mem = gen_rtx_MEM (V2SImode, addr);
12256                 set_mem_alias_set (mem, rs6000_sr_alias_set);
12257                 insn = emit_move_insn (mem, reg);
12258
12259                 if (GET_CODE (b) == CONST_INT)
12260                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12261                                         NULL_RTX, NULL_RTX);
12262                 else
12263                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12264                                         b, GEN_INT (offset));
12265               }
12266             else
12267               {
12268                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12269                                      GEN_INT (info->gp_save_offset
12270                                               + sp_offset
12271                                               + reg_size * i));
12272                 mem = gen_rtx_MEM (reg_mode, addr);
12273                 set_mem_alias_set (mem, rs6000_sr_alias_set);
12274
12275                 insn = emit_move_insn (mem, reg);
12276                 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12277                                       NULL_RTX, NULL_RTX);
12278               }
12279           }
12280     }
12281
12282   /* ??? There's no need to emit actual instructions here, but it's the
12283      easiest way to get the frame unwind information emitted.  */
12284   if (current_function_calls_eh_return)
12285     {
12286       unsigned int i, regno;
12287
12288       /* In AIX ABI we need to pretend we save r2 here.  */
12289       if (TARGET_AIX)
12290         {
12291           rtx addr, reg, mem;
12292
12293           reg = gen_rtx_REG (reg_mode, 2);
12294           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12295                                GEN_INT (sp_offset + 5 * reg_size));
12296           mem = gen_rtx_MEM (reg_mode, addr);
12297           set_mem_alias_set (mem, rs6000_sr_alias_set);
12298
12299           insn = emit_move_insn (mem, reg);
12300           rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12301                                 NULL_RTX, NULL_RTX);
12302           PATTERN (insn) = gen_blockage ();
12303         }
12304
12305       for (i = 0; ; ++i)
12306         {
12307           regno = EH_RETURN_DATA_REGNO (i);
12308           if (regno == INVALID_REGNUM)
12309             break;
12310
12311           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12312                            info->ehrd_offset + sp_offset
12313                            + reg_size * (int) i,
12314                            info->total_size);
12315         }
12316     }
12317
12318   /* Save lr if we used it.  */
12319   if (info->lr_save_p)
12320     {
12321       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12322                                GEN_INT (info->lr_save_offset + sp_offset));
12323       rtx reg = gen_rtx_REG (Pmode, 0);
12324       rtx mem = gen_rtx_MEM (Pmode, addr);
12325       /* This should not be of rs6000_sr_alias_set, because of
12326          __builtin_return_address.  */
12327
12328       insn = emit_move_insn (mem, reg);
12329       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12330                             reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12331     }
12332
12333   /* Save CR if we use any that must be preserved.  */
12334   if (info->cr_save_p)
12335     {
12336       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12337                                GEN_INT (info->cr_save_offset + sp_offset));
12338       rtx mem = gen_rtx_MEM (SImode, addr);
12339
12340       set_mem_alias_set (mem, rs6000_sr_alias_set);
12341
12342       /* If r12 was used to hold the original sp, copy cr into r0 now
12343          that it's free.  */
12344       if (REGNO (frame_reg_rtx) == 12)
12345         {
12346           cr_save_rtx = gen_rtx_REG (SImode, 0);
12347           emit_insn (gen_movesi_from_cr (cr_save_rtx));
12348         }
12349       insn = emit_move_insn (mem, cr_save_rtx);
12350
12351       /* Now, there's no way that dwarf2out_frame_debug_expr is going
12352          to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12353          But that's OK.  All we have to do is specify that _one_ condition
12354          code register is saved in this stack slot.  The thrower's epilogue
12355          will then restore all the call-saved registers.
12356          We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux.  */
12357       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12358                             cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
12359     }
12360
12361   /* Update stack and set back pointer unless this is V.4,
12362      for which it was done previously.  */
12363   if (info->push_p
12364       && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
12365     rs6000_emit_allocate_stack (info->total_size, FALSE);
12366
12367   /* Set frame pointer, if needed.  */
12368   if (frame_pointer_needed)
12369     {
12370       insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
12371                              sp_reg_rtx);
12372       RTX_FRAME_RELATED_P (insn) = 1;
12373     }
12374
12375   /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up.  */
12376   if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
12377       || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
12378           && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
12379   {
12380     /* If emit_load_toc_table will use the link register, we need to save
12381        it.  We use R12 for this purpose because emit_load_toc_table
12382        can use register 0.  This allows us to use a plain 'blr' to return
12383        from the procedure more often.  */
12384     int save_LR_around_toc_setup = (TARGET_ELF
12385                                     && DEFAULT_ABI != ABI_AIX
12386                                     && flag_pic
12387                                     && ! info->lr_save_p
12388                                     && EXIT_BLOCK_PTR->pred != NULL);
12389     if (save_LR_around_toc_setup)
12390       {
12391         rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12392         rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
12393         rs6000_emit_load_toc_table (TRUE);
12394         rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
12395       }
12396     else
12397       rs6000_emit_load_toc_table (TRUE);
12398   }
12399
12400 #if TARGET_MACHO
12401   if (DEFAULT_ABI == ABI_DARWIN
12402       && flag_pic && current_function_uses_pic_offset_table)
12403     {
12404       rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12405       const char *picbase = machopic_function_base_name ();
12406       rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
12407
12408       rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
12409
12410       rs6000_maybe_dead (
12411         emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
12412                         gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
12413     }
12414 #endif
12415 }
12416
12417 /* Write function prologue.  */
12418
12419 static void
12420 rs6000_output_function_prologue (FILE *file,
12421                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12422 {
12423   rs6000_stack_t *info = rs6000_stack_info ();
12424
12425   if (TARGET_DEBUG_STACK)
12426     debug_stack_info (info);
12427
12428   /* Write .extern for any function we will call to save and restore
12429      fp values.  */
12430   if (info->first_fp_reg_save < 64
12431       && !FP_SAVE_INLINE (info->first_fp_reg_save))
12432     fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
12433              SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
12434              RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
12435              RESTORE_FP_SUFFIX);
12436
12437   /* Write .extern for AIX common mode routines, if needed.  */
12438   if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
12439     {
12440       fputs ("\t.extern __mulh\n", file);
12441       fputs ("\t.extern __mull\n", file);
12442       fputs ("\t.extern __divss\n", file);
12443       fputs ("\t.extern __divus\n", file);
12444       fputs ("\t.extern __quoss\n", file);
12445       fputs ("\t.extern __quous\n", file);
12446       common_mode_defined = 1;
12447     }
12448
12449   if (! HAVE_prologue)
12450     {
12451       start_sequence ();
12452
12453       /* A NOTE_INSN_DELETED is supposed to be at the start and end of
12454          the "toplevel" insn chain.  */
12455       emit_note (NOTE_INSN_DELETED);
12456       rs6000_emit_prologue ();
12457       emit_note (NOTE_INSN_DELETED);
12458
12459       /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12460       {
12461         rtx insn;
12462         unsigned addr = 0;
12463         for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12464           {
12465             INSN_ADDRESSES_NEW (insn, addr);
12466             addr += 4;
12467           }
12468       }
12469
12470       if (TARGET_DEBUG_STACK)
12471         debug_rtx_list (get_insns (), 100);
12472       final (get_insns (), file, FALSE, FALSE);
12473       end_sequence ();
12474     }
12475
12476   rs6000_pic_labelno++;
12477 }
12478
12479 /* Emit function epilogue as insns.
12480
12481    At present, dwarf2out_frame_debug_expr doesn't understand
12482    register restores, so we don't bother setting RTX_FRAME_RELATED_P
12483    anywhere in the epilogue.  Most of the insns below would in any case
12484    need special notes to explain where r11 is in relation to the stack.  */
12485
12486 void
12487 rs6000_emit_epilogue (int sibcall)
12488 {
12489   rs6000_stack_t *info;
12490   int restoring_FPRs_inline;
12491   int using_load_multiple;
12492   int using_mfcr_multiple;
12493   int use_backchain_to_restore_sp;
12494   int sp_offset = 0;
12495   rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12496   rtx frame_reg_rtx = sp_reg_rtx;
12497   enum machine_mode reg_mode = Pmode;
12498   int reg_size = TARGET_32BIT ? 4 : 8;
12499   int i;
12500
12501   info = rs6000_stack_info ();
12502
12503   if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12504     {
12505       reg_mode = V2SImode;
12506       reg_size = 8;
12507     }
12508
12509   using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12510                          && (!TARGET_SPE_ABI
12511                              || info->spe_64bit_regs_used == 0)
12512                          && info->first_gp_reg_save < 31);
12513   restoring_FPRs_inline = (sibcall
12514                            || current_function_calls_eh_return
12515                            || info->first_fp_reg_save == 64
12516                            || FP_SAVE_INLINE (info->first_fp_reg_save));
12517   use_backchain_to_restore_sp = (frame_pointer_needed
12518                                  || current_function_calls_alloca
12519                                  || info->total_size > 32767);
12520   using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12521                          || rs6000_cpu == PROCESSOR_PPC603
12522                          || rs6000_cpu == PROCESSOR_PPC750
12523                          || optimize_size);
12524
12525   /* If we have a frame pointer, a call to alloca,  or a large stack
12526      frame, restore the old stack pointer using the backchain.  Otherwise,
12527      we know what size to update it with.  */
12528   if (use_backchain_to_restore_sp)
12529     {
12530       /* Under V.4, don't reset the stack pointer until after we're done
12531          loading the saved registers.  */
12532       if (DEFAULT_ABI == ABI_V4)
12533         frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12534
12535       emit_move_insn (frame_reg_rtx,
12536                       gen_rtx_MEM (Pmode, sp_reg_rtx));
12537
12538     }
12539   else if (info->push_p)
12540     {
12541       if (DEFAULT_ABI == ABI_V4
12542           || current_function_calls_eh_return)
12543         sp_offset = info->total_size;
12544       else
12545         {
12546           emit_insn (TARGET_32BIT
12547                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12548                                    GEN_INT (info->total_size))
12549                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12550                                    GEN_INT (info->total_size)));
12551         }
12552     }
12553
12554   /* Restore AltiVec registers if needed.  */
12555   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12556     {
12557       int i;
12558
12559       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12560         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12561           {
12562             rtx addr, areg, mem;
12563
12564             areg = gen_rtx_REG (Pmode, 0);
12565             emit_move_insn
12566               (areg, GEN_INT (info->altivec_save_offset
12567                               + sp_offset
12568                               + 16 * (i - info->first_altivec_reg_save)));
12569
12570             /* AltiVec addressing mode is [reg+reg].  */
12571             addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12572             mem = gen_rtx_MEM (V4SImode, addr);
12573             set_mem_alias_set (mem, rs6000_sr_alias_set);
12574
12575             emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12576           }
12577     }
12578
12579   /* Restore VRSAVE if needed.  */
12580   if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12581       && info->vrsave_mask != 0)
12582     {
12583       rtx addr, mem, reg;
12584
12585       addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12586                            GEN_INT (info->vrsave_save_offset + sp_offset));
12587       mem = gen_rtx_MEM (SImode, addr);
12588       set_mem_alias_set (mem, rs6000_sr_alias_set);
12589       reg = gen_rtx_REG (SImode, 12);
12590       emit_move_insn (reg, mem);
12591
12592       emit_insn (generate_set_vrsave (reg, info, 1));
12593     }
12594
12595   /* Get the old lr if we saved it.  */
12596   if (info->lr_save_p)
12597     {
12598       rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12599                                       info->lr_save_offset + sp_offset);
12600
12601       set_mem_alias_set (mem, rs6000_sr_alias_set);
12602
12603       emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12604     }
12605
12606   /* Get the old cr if we saved it.  */
12607   if (info->cr_save_p)
12608     {
12609       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12610                                GEN_INT (info->cr_save_offset + sp_offset));
12611       rtx mem = gen_rtx_MEM (SImode, addr);
12612
12613       set_mem_alias_set (mem, rs6000_sr_alias_set);
12614
12615       emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12616     }
12617
12618   /* Set LR here to try to overlap restores below.  */
12619   if (info->lr_save_p)
12620     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12621                     gen_rtx_REG (Pmode, 0));
12622
12623   /* Load exception handler data registers, if needed.  */
12624   if (current_function_calls_eh_return)
12625     {
12626       unsigned int i, regno;
12627
12628       if (TARGET_AIX)
12629         {
12630           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12631                                    GEN_INT (sp_offset + 5 * reg_size));
12632           rtx mem = gen_rtx_MEM (reg_mode, addr);
12633
12634           set_mem_alias_set (mem, rs6000_sr_alias_set);
12635
12636           emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12637         }
12638
12639       for (i = 0; ; ++i)
12640         {
12641           rtx mem;
12642
12643           regno = EH_RETURN_DATA_REGNO (i);
12644           if (regno == INVALID_REGNUM)
12645             break;
12646
12647           mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12648                                       info->ehrd_offset + sp_offset
12649                                       + reg_size * (int) i);
12650           set_mem_alias_set (mem, rs6000_sr_alias_set);
12651
12652           emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12653         }
12654     }
12655
12656   /* Restore GPRs.  This is done as a PARALLEL if we are using
12657      the load-multiple instructions.  */
12658   if (using_load_multiple)
12659     {
12660       rtvec p;
12661       p = rtvec_alloc (32 - info->first_gp_reg_save);
12662       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12663         {
12664           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12665                                    GEN_INT (info->gp_save_offset
12666                                             + sp_offset
12667                                             + reg_size * i));
12668           rtx mem = gen_rtx_MEM (reg_mode, addr);
12669
12670           set_mem_alias_set (mem, rs6000_sr_alias_set);
12671
12672           RTVEC_ELT (p, i) =
12673             gen_rtx_SET (VOIDmode,
12674                          gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12675                          mem);
12676         }
12677       emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12678     }
12679   else
12680     for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12681       if ((regs_ever_live[info->first_gp_reg_save+i]
12682            && ! call_used_regs[info->first_gp_reg_save+i])
12683           || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12684               && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12685                   || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12686         {
12687           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12688                                    GEN_INT (info->gp_save_offset
12689                                             + sp_offset
12690                                             + reg_size * i));
12691           rtx mem = gen_rtx_MEM (reg_mode, addr);
12692
12693           /* Restore 64-bit quantities for SPE.  */
12694           if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12695             {
12696               int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12697               rtx b;
12698
12699               if (!SPE_CONST_OFFSET_OK (offset))
12700                 {
12701                   b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12702                   emit_move_insn (b, GEN_INT (offset));
12703                 }
12704               else
12705                 b = GEN_INT (offset);
12706
12707               addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12708               mem = gen_rtx_MEM (V2SImode, addr);
12709             }
12710
12711           set_mem_alias_set (mem, rs6000_sr_alias_set);
12712
12713           emit_move_insn (gen_rtx_REG (reg_mode,
12714                                        info->first_gp_reg_save + i), mem);
12715         }
12716
12717   /* Restore fpr's if we need to do it without calling a function.  */
12718   if (restoring_FPRs_inline)
12719     for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12720       if ((regs_ever_live[info->first_fp_reg_save+i]
12721            && ! call_used_regs[info->first_fp_reg_save+i]))
12722         {
12723           rtx addr, mem;
12724           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12725                                GEN_INT (info->fp_save_offset
12726                                         + sp_offset
12727                                         + 8 * i));
12728           mem = gen_rtx_MEM (DFmode, addr);
12729           set_mem_alias_set (mem, rs6000_sr_alias_set);
12730
12731           emit_move_insn (gen_rtx_REG (DFmode,
12732                                        info->first_fp_reg_save + i),
12733                           mem);
12734         }
12735
12736   /* If we saved cr, restore it here.  Just those that were used.  */
12737   if (info->cr_save_p)
12738     {
12739       rtx r12_rtx = gen_rtx_REG (SImode, 12);
12740       int count = 0;
12741
12742       if (using_mfcr_multiple)
12743         {
12744           for (i = 0; i < 8; i++)
12745             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12746               count++;
12747           if (count == 0)
12748             abort ();
12749         }
12750
12751       if (using_mfcr_multiple && count > 1)
12752         {
12753           rtvec p;
12754           int ndx;
12755
12756           p = rtvec_alloc (count);
12757
12758           ndx = 0;
12759           for (i = 0; i < 8; i++)
12760             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12761               {
12762                 rtvec r = rtvec_alloc (2);
12763                 RTVEC_ELT (r, 0) = r12_rtx;
12764                 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12765                 RTVEC_ELT (p, ndx) =
12766                   gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12767                                gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12768                 ndx++;
12769               }
12770           emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12771           if (ndx != count)
12772             abort ();
12773         }
12774       else
12775         for (i = 0; i < 8; i++)
12776           if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12777             {
12778               emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12779                                                            CR0_REGNO+i),
12780                                               r12_rtx));
12781             }
12782     }
12783
12784   /* If this is V.4, unwind the stack pointer after all of the loads
12785      have been done.  We need to emit a block here so that sched
12786      doesn't decide to move the sp change before the register restores
12787      (which may not have any obvious dependency on the stack).  This
12788      doesn't hurt performance, because there is no scheduling that can
12789      be done after this point.  */
12790   if (DEFAULT_ABI == ABI_V4
12791       || current_function_calls_eh_return)
12792     {
12793       if (frame_reg_rtx != sp_reg_rtx)
12794           rs6000_emit_stack_tie ();
12795
12796       if (use_backchain_to_restore_sp)
12797         {
12798           emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12799         }
12800       else if (sp_offset != 0)
12801         {
12802           emit_insn (TARGET_32BIT
12803                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12804                                    GEN_INT (sp_offset))
12805                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12806                                    GEN_INT (sp_offset)));
12807         }
12808     }
12809
12810   if (current_function_calls_eh_return)
12811     {
12812       rtx sa = EH_RETURN_STACKADJ_RTX;
12813       emit_insn (TARGET_32BIT
12814                  ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12815                  : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12816     }
12817
12818   if (!sibcall)
12819     {
12820       rtvec p;
12821       if (! restoring_FPRs_inline)
12822         p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12823       else
12824         p = rtvec_alloc (2);
12825
12826       RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12827       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12828                                       gen_rtx_REG (Pmode,
12829                                                    LINK_REGISTER_REGNUM));
12830
12831       /* If we have to restore more than two FP registers, branch to the
12832          restore function.  It will return to our caller.  */
12833       if (! restoring_FPRs_inline)
12834         {
12835           int i;
12836           char rname[30];
12837           const char *alloc_rname;
12838
12839           sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12840                    info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12841           alloc_rname = ggc_strdup (rname);
12842           RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12843                                           gen_rtx_SYMBOL_REF (Pmode,
12844                                                               alloc_rname));
12845
12846           for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12847             {
12848               rtx addr, mem;
12849               addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12850                                    GEN_INT (info->fp_save_offset + 8*i));
12851               mem = gen_rtx_MEM (DFmode, addr);
12852               set_mem_alias_set (mem, rs6000_sr_alias_set);
12853
12854               RTVEC_ELT (p, i+3) =
12855                 gen_rtx_SET (VOIDmode,
12856                              gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12857                              mem);
12858             }
12859         }
12860
12861       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12862     }
12863 }
12864
12865 /* Write function epilogue.  */
12866
12867 static void
12868 rs6000_output_function_epilogue (FILE *file,
12869                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12870 {
12871   rs6000_stack_t *info = rs6000_stack_info ();
12872
12873   if (! HAVE_epilogue)
12874     {
12875       rtx insn = get_last_insn ();
12876       /* If the last insn was a BARRIER, we don't have to write anything except
12877          the trace table.  */
12878       if (GET_CODE (insn) == NOTE)
12879         insn = prev_nonnote_insn (insn);
12880       if (insn == 0 ||  GET_CODE (insn) != BARRIER)
12881         {
12882           /* This is slightly ugly, but at least we don't have two
12883              copies of the epilogue-emitting code.  */
12884           start_sequence ();
12885
12886           /* A NOTE_INSN_DELETED is supposed to be at the start
12887              and end of the "toplevel" insn chain.  */
12888           emit_note (NOTE_INSN_DELETED);
12889           rs6000_emit_epilogue (FALSE);
12890           emit_note (NOTE_INSN_DELETED);
12891
12892           /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12893           {
12894             rtx insn;
12895             unsigned addr = 0;
12896             for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12897               {
12898                 INSN_ADDRESSES_NEW (insn, addr);
12899                 addr += 4;
12900               }
12901           }
12902
12903           if (TARGET_DEBUG_STACK)
12904             debug_rtx_list (get_insns (), 100);
12905           final (get_insns (), file, FALSE, FALSE);
12906           end_sequence ();
12907         }
12908     }
12909
12910 #if TARGET_MACHO
12911   macho_branch_islands ();
12912   /* Mach-O doesn't support labels at the end of objects, so if
12913      it looks like we might want one, insert a NOP.  */
12914   {
12915     rtx insn = get_last_insn ();
12916     while (insn
12917            && NOTE_P (insn)
12918            && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12919       insn = PREV_INSN (insn);
12920     if (insn
12921         && (LABEL_P (insn)
12922             || (NOTE_P (insn)
12923                 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12924       fputs ("\tnop\n", file);
12925   }
12926 #endif
12927
12928   /* Output a traceback table here.  See /usr/include/sys/debug.h for info
12929      on its format.
12930
12931      We don't output a traceback table if -finhibit-size-directive was
12932      used.  The documentation for -finhibit-size-directive reads
12933      ``don't output a @code{.size} assembler directive, or anything
12934      else that would cause trouble if the function is split in the
12935      middle, and the two halves are placed at locations far apart in
12936      memory.''  The traceback table has this property, since it
12937      includes the offset from the start of the function to the
12938      traceback table itself.
12939
12940      System V.4 Powerpc's (and the embedded ABI derived from it) use a
12941      different traceback table.  */
12942   if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12943       && rs6000_traceback != traceback_none)
12944     {
12945       const char *fname = NULL;
12946       const char *language_string = lang_hooks.name;
12947       int fixed_parms = 0, float_parms = 0, parm_info = 0;
12948       int i;
12949       int optional_tbtab;
12950
12951       if (rs6000_traceback == traceback_full)
12952         optional_tbtab = 1;
12953       else if (rs6000_traceback == traceback_part)
12954         optional_tbtab = 0;
12955       else
12956         optional_tbtab = !optimize_size && !TARGET_ELF;
12957
12958       if (optional_tbtab)
12959         {
12960           fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12961           while (*fname == '.') /* V.4 encodes . in the name */
12962             fname++;
12963
12964           /* Need label immediately before tbtab, so we can compute
12965              its offset from the function start.  */
12966           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12967           ASM_OUTPUT_LABEL (file, fname);
12968         }
12969
12970       /* The .tbtab pseudo-op can only be used for the first eight
12971          expressions, since it can't handle the possibly variable
12972          length fields that follow.  However, if you omit the optional
12973          fields, the assembler outputs zeros for all optional fields
12974          anyways, giving each variable length field is minimum length
12975          (as defined in sys/debug.h).  Thus we can not use the .tbtab
12976          pseudo-op at all.  */
12977
12978       /* An all-zero word flags the start of the tbtab, for debuggers
12979          that have to find it by searching forward from the entry
12980          point or from the current pc.  */
12981       fputs ("\t.long 0\n", file);
12982
12983       /* Tbtab format type.  Use format type 0.  */
12984       fputs ("\t.byte 0,", file);
12985
12986       /* Language type.  Unfortunately, there does not seem to be any
12987          official way to discover the language being compiled, so we
12988          use language_string.
12989          C is 0.  Fortran is 1.  Pascal is 2.  Ada is 3.  C++ is 9.
12990          Java is 13.  Objective-C is 14.  */
12991       if (! strcmp (language_string, "GNU C"))
12992         i = 0;
12993       else if (! strcmp (language_string, "GNU F77"))
12994         i = 1;
12995       else if (! strcmp (language_string, "GNU Pascal"))
12996         i = 2;
12997       else if (! strcmp (language_string, "GNU Ada"))
12998         i = 3;
12999       else if (! strcmp (language_string, "GNU C++"))
13000         i = 9;
13001       else if (! strcmp (language_string, "GNU Java"))
13002         i = 13;
13003       else if (! strcmp (language_string, "GNU Objective-C"))
13004         i = 14;
13005       else
13006         abort ();
13007       fprintf (file, "%d,", i);
13008
13009       /* 8 single bit fields: global linkage (not set for C extern linkage,
13010          apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13011          from start of procedure stored in tbtab, internal function, function
13012          has controlled storage, function has no toc, function uses fp,
13013          function logs/aborts fp operations.  */
13014       /* Assume that fp operations are used if any fp reg must be saved.  */
13015       fprintf (file, "%d,",
13016                (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
13017
13018       /* 6 bitfields: function is interrupt handler, name present in
13019          proc table, function calls alloca, on condition directives
13020          (controls stack walks, 3 bits), saves condition reg, saves
13021          link reg.  */
13022       /* The `function calls alloca' bit seems to be set whenever reg 31 is
13023          set up as a frame pointer, even when there is no alloca call.  */
13024       fprintf (file, "%d,",
13025                ((optional_tbtab << 6)
13026                 | ((optional_tbtab & frame_pointer_needed) << 5)
13027                 | (info->cr_save_p << 1)
13028                 | (info->lr_save_p)));
13029
13030       /* 3 bitfields: saves backchain, fixup code, number of fpr saved
13031          (6 bits).  */
13032       fprintf (file, "%d,",
13033                (info->push_p << 7) | (64 - info->first_fp_reg_save));
13034
13035       /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
13036       fprintf (file, "%d,", (32 - first_reg_to_save ()));
13037
13038       if (optional_tbtab)
13039         {
13040           /* Compute the parameter info from the function decl argument
13041              list.  */
13042           tree decl;
13043           int next_parm_info_bit = 31;
13044
13045           for (decl = DECL_ARGUMENTS (current_function_decl);
13046                decl; decl = TREE_CHAIN (decl))
13047             {
13048               rtx parameter = DECL_INCOMING_RTL (decl);
13049               enum machine_mode mode = GET_MODE (parameter);
13050
13051               if (GET_CODE (parameter) == REG)
13052                 {
13053                   if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13054                     {
13055                       int bits;
13056
13057                       float_parms++;
13058
13059                       if (mode == SFmode)
13060                         bits = 0x2;
13061                       else if (mode == DFmode || mode == TFmode)
13062                         bits = 0x3;
13063                       else
13064                         abort ();
13065
13066                       /* If only one bit will fit, don't or in this entry.  */
13067                       if (next_parm_info_bit > 0)
13068                         parm_info |= (bits << (next_parm_info_bit - 1));
13069                       next_parm_info_bit -= 2;
13070                     }
13071                   else
13072                     {
13073                       fixed_parms += ((GET_MODE_SIZE (mode)
13074                                        + (UNITS_PER_WORD - 1))
13075                                       / UNITS_PER_WORD);
13076                       next_parm_info_bit -= 1;
13077                     }
13078                 }
13079             }
13080         }
13081
13082       /* Number of fixed point parameters.  */
13083       /* This is actually the number of words of fixed point parameters; thus
13084          an 8 byte struct counts as 2; and thus the maximum value is 8.  */
13085       fprintf (file, "%d,", fixed_parms);
13086
13087       /* 2 bitfields: number of floating point parameters (7 bits), parameters
13088          all on stack.  */
13089       /* This is actually the number of fp registers that hold parameters;
13090          and thus the maximum value is 13.  */
13091       /* Set parameters on stack bit if parameters are not in their original
13092          registers, regardless of whether they are on the stack?  Xlc
13093          seems to set the bit when not optimizing.  */
13094       fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13095
13096       if (! optional_tbtab)
13097         return;
13098
13099       /* Optional fields follow.  Some are variable length.  */
13100
13101       /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13102          11 double float.  */
13103       /* There is an entry for each parameter in a register, in the order that
13104          they occur in the parameter list.  Any intervening arguments on the
13105          stack are ignored.  If the list overflows a long (max possible length
13106          34 bits) then completely leave off all elements that don't fit.  */
13107       /* Only emit this long if there was at least one parameter.  */
13108       if (fixed_parms || float_parms)
13109         fprintf (file, "\t.long %d\n", parm_info);
13110
13111       /* Offset from start of code to tb table.  */
13112       fputs ("\t.long ", file);
13113       ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13114 #if TARGET_AIX
13115       RS6000_OUTPUT_BASENAME (file, fname);
13116 #else
13117       assemble_name (file, fname);
13118 #endif
13119       fputs ("-.", file);
13120 #if TARGET_AIX
13121       RS6000_OUTPUT_BASENAME (file, fname);
13122 #else
13123       assemble_name (file, fname);
13124 #endif
13125       putc ('\n', file);
13126
13127       /* Interrupt handler mask.  */
13128       /* Omit this long, since we never set the interrupt handler bit
13129          above.  */
13130
13131       /* Number of CTL (controlled storage) anchors.  */
13132       /* Omit this long, since the has_ctl bit is never set above.  */
13133
13134       /* Displacement into stack of each CTL anchor.  */
13135       /* Omit this list of longs, because there are no CTL anchors.  */
13136
13137       /* Length of function name.  */
13138       if (*fname == '*')
13139         ++fname;
13140       fprintf (file, "\t.short %d\n", (int) strlen (fname));
13141
13142       /* Function name.  */
13143       assemble_string (fname, strlen (fname));
13144
13145       /* Register for alloca automatic storage; this is always reg 31.
13146          Only emit this if the alloca bit was set above.  */
13147       if (frame_pointer_needed)
13148         fputs ("\t.byte 31\n", file);
13149
13150       fputs ("\t.align 2\n", file);
13151     }
13152 }
13153 \f
13154 /* A C compound statement that outputs the assembler code for a thunk
13155    function, used to implement C++ virtual function calls with
13156    multiple inheritance.  The thunk acts as a wrapper around a virtual
13157    function, adjusting the implicit object parameter before handing
13158    control off to the real function.
13159
13160    First, emit code to add the integer DELTA to the location that
13161    contains the incoming first argument.  Assume that this argument
13162    contains a pointer, and is the one used to pass the `this' pointer
13163    in C++.  This is the incoming argument *before* the function
13164    prologue, e.g. `%o0' on a sparc.  The addition must preserve the
13165    values of all other incoming arguments.
13166
13167    After the addition, emit code to jump to FUNCTION, which is a
13168    `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does
13169    not touch the return address.  Hence returning from FUNCTION will
13170    return to whoever called the current `thunk'.
13171
13172    The effect must be as if FUNCTION had been called directly with the
13173    adjusted first argument.  This macro is responsible for emitting
13174    all of the code for a thunk function; output_function_prologue()
13175    and output_function_epilogue() are not invoked.
13176
13177    The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already
13178    been extracted from it.)  It might possibly be useful on some
13179    targets, but probably not.
13180
13181    If you do not define this macro, the target-independent code in the
13182    C++ frontend will generate a less efficient heavyweight thunk that
13183    calls FUNCTION instead of jumping to it.  The generic approach does
13184    not support varargs.  */
13185
13186 static void
13187 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13188                         HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13189                         tree function)
13190 {
13191   rtx this, insn, funexp;
13192
13193   reload_completed = 1;
13194   epilogue_completed = 1;
13195   no_new_pseudos = 1;
13196
13197   /* Mark the end of the (empty) prologue.  */
13198   emit_note (NOTE_INSN_PROLOGUE_END);
13199
13200   /* Find the "this" pointer.  If the function returns a structure,
13201      the structure return pointer is in r3.  */
13202   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13203     this = gen_rtx_REG (Pmode, 4);
13204   else
13205     this = gen_rtx_REG (Pmode, 3);
13206
13207   /* Apply the constant offset, if required.  */
13208   if (delta)
13209     {
13210       rtx delta_rtx = GEN_INT (delta);
13211       emit_insn (TARGET_32BIT
13212                  ? gen_addsi3 (this, this, delta_rtx)
13213                  : gen_adddi3 (this, this, delta_rtx));
13214     }
13215
13216   /* Apply the offset from the vtable, if required.  */
13217   if (vcall_offset)
13218     {
13219       rtx vcall_offset_rtx = GEN_INT (vcall_offset);
13220       rtx tmp = gen_rtx_REG (Pmode, 12);
13221
13222       emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
13223       if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
13224         {
13225           emit_insn (TARGET_32BIT
13226                      ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
13227                      : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
13228           emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
13229         }
13230       else
13231         {
13232           rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
13233
13234           emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
13235         }
13236       emit_insn (TARGET_32BIT
13237                  ? gen_addsi3 (this, this, tmp)
13238                  : gen_adddi3 (this, this, tmp));
13239     }
13240
13241   /* Generate a tail call to the target function.  */
13242   if (!TREE_USED (function))
13243     {
13244       assemble_external (function);
13245       TREE_USED (function) = 1;
13246     }
13247   funexp = XEXP (DECL_RTL (function), 0);
13248   funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
13249
13250 #if TARGET_MACHO
13251   if (MACHOPIC_INDIRECT)
13252     funexp = machopic_indirect_call_target (funexp);
13253 #endif
13254
13255   /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
13256      generate sibcall RTL explicitly to avoid constraint abort.  */
13257   insn = emit_call_insn (
13258            gen_rtx_PARALLEL (VOIDmode,
13259              gen_rtvec (4,
13260                         gen_rtx_CALL (VOIDmode,
13261                                       funexp, const0_rtx),
13262                         gen_rtx_USE (VOIDmode, const0_rtx),
13263                         gen_rtx_USE (VOIDmode,
13264                                      gen_rtx_REG (SImode,
13265                                                   LINK_REGISTER_REGNUM)),
13266                         gen_rtx_RETURN (VOIDmode))));
13267   SIBLING_CALL_P (insn) = 1;
13268   emit_barrier ();
13269
13270   /* Run just enough of rest_of_compilation to get the insns emitted.
13271      There's not really enough bulk here to make other passes such as
13272      instruction scheduling worth while.  Note that use_thunk calls
13273      assemble_start_function and assemble_end_function.  */
13274   insn = get_insns ();
13275   insn_locators_initialize ();
13276   shorten_branches (insn);
13277   final_start_function (insn, file, 1);
13278   final (insn, file, 1, 0);
13279   final_end_function ();
13280
13281   reload_completed = 0;
13282   epilogue_completed = 0;
13283   no_new_pseudos = 0;
13284 }
13285 \f
13286 /* A quick summary of the various types of 'constant-pool tables'
13287    under PowerPC:
13288
13289    Target       Flags           Name            One table per
13290    AIX          (none)          AIX TOC         object file
13291    AIX          -mfull-toc      AIX TOC         object file
13292    AIX          -mminimal-toc   AIX minimal TOC translation unit
13293    SVR4/EABI    (none)          SVR4 SDATA      object file
13294    SVR4/EABI    -fpic           SVR4 pic        object file
13295    SVR4/EABI    -fPIC           SVR4 PIC        translation unit
13296    SVR4/EABI    -mrelocatable   EABI TOC        function
13297    SVR4/EABI    -maix           AIX TOC         object file
13298    SVR4/EABI    -maix -mminimal-toc
13299                                 AIX minimal TOC translation unit
13300
13301    Name                 Reg.    Set by  entries       contains:
13302                                         made by  addrs? fp?     sum?
13303
13304    AIX TOC              2       crt0    as       Y      option  option
13305    AIX minimal TOC      30      prolog  gcc      Y      Y       option
13306    SVR4 SDATA           13      crt0    gcc      N      Y       N
13307    SVR4 pic             30      prolog  ld       Y      not yet N
13308    SVR4 PIC             30      prolog  gcc      Y      option  option
13309    EABI TOC             30      prolog  gcc      Y      option  option
13310
13311 */
13312
13313 /* Hash functions for the hash table.  */
13314
13315 static unsigned
13316 rs6000_hash_constant (rtx k)
13317 {
13318   enum rtx_code code = GET_CODE (k);
13319   enum machine_mode mode = GET_MODE (k);
13320   unsigned result = (code << 3) ^ mode;
13321   const char *format;
13322   int flen, fidx;
13323
13324   format = GET_RTX_FORMAT (code);
13325   flen = strlen (format);
13326   fidx = 0;
13327
13328   switch (code)
13329     {
13330     case LABEL_REF:
13331       return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
13332
13333     case CONST_DOUBLE:
13334       if (mode != VOIDmode)
13335         return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
13336       flen = 2;
13337       break;
13338
13339     case CODE_LABEL:
13340       fidx = 3;
13341       break;
13342
13343     default:
13344       break;
13345     }
13346
13347   for (; fidx < flen; fidx++)
13348     switch (format[fidx])
13349       {
13350       case 's':
13351         {
13352           unsigned i, len;
13353           const char *str = XSTR (k, fidx);
13354           len = strlen (str);
13355           result = result * 613 + len;
13356           for (i = 0; i < len; i++)
13357             result = result * 613 + (unsigned) str[i];
13358           break;
13359         }
13360       case 'u':
13361       case 'e':
13362         result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
13363         break;
13364       case 'i':
13365       case 'n':
13366         result = result * 613 + (unsigned) XINT (k, fidx);
13367         break;
13368       case 'w':
13369         if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
13370           result = result * 613 + (unsigned) XWINT (k, fidx);
13371         else
13372           {
13373             size_t i;
13374             for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
13375               result = result * 613 + (unsigned) (XWINT (k, fidx)
13376                                                   >> CHAR_BIT * i);
13377           }
13378         break;
13379       case '0':
13380         break;
13381       default:
13382         abort ();
13383       }
13384
13385   return result;
13386 }
13387
13388 static unsigned
13389 toc_hash_function (const void *hash_entry)
13390 {
13391   const struct toc_hash_struct *thc =
13392     (const struct toc_hash_struct *) hash_entry;
13393   return rs6000_hash_constant (thc->key) ^ thc->key_mode;
13394 }
13395
13396 /* Compare H1 and H2 for equivalence.  */
13397
13398 static int
13399 toc_hash_eq (const void *h1, const void *h2)
13400 {
13401   rtx r1 = ((const struct toc_hash_struct *) h1)->key;
13402   rtx r2 = ((const struct toc_hash_struct *) h2)->key;
13403
13404   if (((const struct toc_hash_struct *) h1)->key_mode
13405       != ((const struct toc_hash_struct *) h2)->key_mode)
13406     return 0;
13407
13408   return rtx_equal_p (r1, r2);
13409 }
13410
13411 /* These are the names given by the C++ front-end to vtables, and
13412    vtable-like objects.  Ideally, this logic should not be here;
13413    instead, there should be some programmatic way of inquiring as
13414    to whether or not an object is a vtable.  */
13415
13416 #define VTABLE_NAME_P(NAME)                             \
13417   (strncmp ("_vt.", name, strlen("_vt.")) == 0          \
13418   || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0       \
13419   || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0       \
13420   || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0       \
13421   || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
13422
13423 void
13424 rs6000_output_symbol_ref (FILE *file, rtx x)
13425 {
13426   /* Currently C++ toc references to vtables can be emitted before it
13427      is decided whether the vtable is public or private.  If this is
13428      the case, then the linker will eventually complain that there is
13429      a reference to an unknown section.  Thus, for vtables only,
13430      we emit the TOC reference to reference the symbol and not the
13431      section.  */
13432   const char *name = XSTR (x, 0);
13433
13434   if (VTABLE_NAME_P (name))
13435     {
13436       RS6000_OUTPUT_BASENAME (file, name);
13437     }
13438   else
13439     assemble_name (file, name);
13440 }
13441
13442 /* Output a TOC entry.  We derive the entry name from what is being
13443    written.  */
13444
13445 void
13446 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
13447 {
13448   char buf[256];
13449   const char *name = buf;
13450   const char *real_name;
13451   rtx base = x;
13452   int offset = 0;
13453
13454   if (TARGET_NO_TOC)
13455     abort ();
13456
13457   /* When the linker won't eliminate them, don't output duplicate
13458      TOC entries (this happens on AIX if there is any kind of TOC,
13459      and on SVR4 under -fPIC or -mrelocatable).  Don't do this for
13460      CODE_LABELs.  */
13461   if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
13462     {
13463       struct toc_hash_struct *h;
13464       void * * found;
13465
13466       /* Create toc_hash_table.  This can't be done at OVERRIDE_OPTIONS
13467          time because GGC is not initialized at that point.  */
13468       if (toc_hash_table == NULL)
13469         toc_hash_table = htab_create_ggc (1021, toc_hash_function,
13470                                           toc_hash_eq, NULL);
13471
13472       h = ggc_alloc (sizeof (*h));
13473       h->key = x;
13474       h->key_mode = mode;
13475       h->labelno = labelno;
13476
13477       found = htab_find_slot (toc_hash_table, h, 1);
13478       if (*found == NULL)
13479         *found = h;
13480       else  /* This is indeed a duplicate.
13481                Set this label equal to that label.  */
13482         {
13483           fputs ("\t.set ", file);
13484           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13485           fprintf (file, "%d,", labelno);
13486           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13487           fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13488                                               found)->labelno));
13489           return;
13490         }
13491     }
13492
13493   /* If we're going to put a double constant in the TOC, make sure it's
13494      aligned properly when strict alignment is on.  */
13495   if (GET_CODE (x) == CONST_DOUBLE
13496       && STRICT_ALIGNMENT
13497       && GET_MODE_BITSIZE (mode) >= 64
13498       && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13499     ASM_OUTPUT_ALIGN (file, 3);
13500   }
13501
13502   (*targetm.asm_out.internal_label) (file, "LC", labelno);
13503
13504   /* Handle FP constants specially.  Note that if we have a minimal
13505      TOC, things we put here aren't actually in the TOC, so we can allow
13506      FP constants.  */
13507   if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13508     {
13509       REAL_VALUE_TYPE rv;
13510       long k[4];
13511
13512       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13513       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13514
13515       if (TARGET_64BIT)
13516         {
13517           if (TARGET_MINIMAL_TOC)
13518             fputs (DOUBLE_INT_ASM_OP, file);
13519           else
13520             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13521                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13522                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13523           fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13524                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13525                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13526           return;
13527         }
13528       else
13529         {
13530           if (TARGET_MINIMAL_TOC)
13531             fputs ("\t.long ", file);
13532           else
13533             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13534                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13535                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13536           fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13537                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13538                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13539           return;
13540         }
13541     }
13542   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13543     {
13544       REAL_VALUE_TYPE rv;
13545       long k[2];
13546
13547       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13548       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13549
13550       if (TARGET_64BIT)
13551         {
13552           if (TARGET_MINIMAL_TOC)
13553             fputs (DOUBLE_INT_ASM_OP, file);
13554           else
13555             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13556                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13557           fprintf (file, "0x%lx%08lx\n",
13558                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13559           return;
13560         }
13561       else
13562         {
13563           if (TARGET_MINIMAL_TOC)
13564             fputs ("\t.long ", file);
13565           else
13566             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13567                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13568           fprintf (file, "0x%lx,0x%lx\n",
13569                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13570           return;
13571         }
13572     }
13573   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13574     {
13575       REAL_VALUE_TYPE rv;
13576       long l;
13577
13578       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13579       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13580
13581       if (TARGET_64BIT)
13582         {
13583           if (TARGET_MINIMAL_TOC)
13584             fputs (DOUBLE_INT_ASM_OP, file);
13585           else
13586             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13587           fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13588           return;
13589         }
13590       else
13591         {
13592           if (TARGET_MINIMAL_TOC)
13593             fputs ("\t.long ", file);
13594           else
13595             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13596           fprintf (file, "0x%lx\n", l & 0xffffffff);
13597           return;
13598         }
13599     }
13600   else if (GET_MODE (x) == VOIDmode
13601            && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13602     {
13603       unsigned HOST_WIDE_INT low;
13604       HOST_WIDE_INT high;
13605
13606       if (GET_CODE (x) == CONST_DOUBLE)
13607         {
13608           low = CONST_DOUBLE_LOW (x);
13609           high = CONST_DOUBLE_HIGH (x);
13610         }
13611       else
13612 #if HOST_BITS_PER_WIDE_INT == 32
13613         {
13614           low = INTVAL (x);
13615           high = (low & 0x80000000) ? ~0 : 0;
13616         }
13617 #else
13618         {
13619           low = INTVAL (x) & 0xffffffff;
13620           high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13621         }
13622 #endif
13623
13624       /* TOC entries are always Pmode-sized, but since this
13625          is a bigendian machine then if we're putting smaller
13626          integer constants in the TOC we have to pad them.
13627          (This is still a win over putting the constants in
13628          a separate constant pool, because then we'd have
13629          to have both a TOC entry _and_ the actual constant.)
13630
13631          For a 32-bit target, CONST_INT values are loaded and shifted
13632          entirely within `low' and can be stored in one TOC entry.  */
13633
13634       if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13635         abort ();/* It would be easy to make this work, but it doesn't now.  */
13636
13637       if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13638         {
13639 #if HOST_BITS_PER_WIDE_INT == 32
13640           lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13641                          POINTER_SIZE, &low, &high, 0);
13642 #else
13643           low |= high << 32;
13644           low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13645           high = (HOST_WIDE_INT) low >> 32;
13646           low &= 0xffffffff;
13647 #endif
13648         }
13649
13650       if (TARGET_64BIT)
13651         {
13652           if (TARGET_MINIMAL_TOC)
13653             fputs (DOUBLE_INT_ASM_OP, file);
13654           else
13655             fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13656                      (long) high & 0xffffffff, (long) low & 0xffffffff);
13657           fprintf (file, "0x%lx%08lx\n",
13658                    (long) high & 0xffffffff, (long) low & 0xffffffff);
13659           return;
13660         }
13661       else
13662         {
13663           if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13664             {
13665               if (TARGET_MINIMAL_TOC)
13666                 fputs ("\t.long ", file);
13667               else
13668                 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13669                          (long) high & 0xffffffff, (long) low & 0xffffffff);
13670               fprintf (file, "0x%lx,0x%lx\n",
13671                        (long) high & 0xffffffff, (long) low & 0xffffffff);
13672             }
13673           else
13674             {
13675               if (TARGET_MINIMAL_TOC)
13676                 fputs ("\t.long ", file);
13677               else
13678                 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13679               fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13680             }
13681           return;
13682         }
13683     }
13684
13685   if (GET_CODE (x) == CONST)
13686     {
13687       if (GET_CODE (XEXP (x, 0)) != PLUS)
13688         abort ();
13689
13690       base = XEXP (XEXP (x, 0), 0);
13691       offset = INTVAL (XEXP (XEXP (x, 0), 1));
13692     }
13693
13694   if (GET_CODE (base) == SYMBOL_REF)
13695     name = XSTR (base, 0);
13696   else if (GET_CODE (base) == LABEL_REF)
13697     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13698   else if (GET_CODE (base) == CODE_LABEL)
13699     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13700   else
13701     abort ();
13702
13703   real_name = (*targetm.strip_name_encoding) (name);
13704   if (TARGET_MINIMAL_TOC)
13705     fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13706   else
13707     {
13708       fprintf (file, "\t.tc %s", real_name);
13709
13710       if (offset < 0)
13711         fprintf (file, ".N%d", - offset);
13712       else if (offset)
13713         fprintf (file, ".P%d", offset);
13714
13715       fputs ("[TC],", file);
13716     }
13717
13718   /* Currently C++ toc references to vtables can be emitted before it
13719      is decided whether the vtable is public or private.  If this is
13720      the case, then the linker will eventually complain that there is
13721      a TOC reference to an unknown section.  Thus, for vtables only,
13722      we emit the TOC reference to reference the symbol and not the
13723      section.  */
13724   if (VTABLE_NAME_P (name))
13725     {
13726       RS6000_OUTPUT_BASENAME (file, name);
13727       if (offset < 0)
13728         fprintf (file, "%d", offset);
13729       else if (offset > 0)
13730         fprintf (file, "+%d", offset);
13731     }
13732   else
13733     output_addr_const (file, x);
13734   putc ('\n', file);
13735 }
13736 \f
13737 /* Output an assembler pseudo-op to write an ASCII string of N characters
13738    starting at P to FILE.
13739
13740    On the RS/6000, we have to do this using the .byte operation and
13741    write out special characters outside the quoted string.
13742    Also, the assembler is broken; very long strings are truncated,
13743    so we must artificially break them up early.  */
13744
13745 void
13746 output_ascii (FILE *file, const char *p, int n)
13747 {
13748   char c;
13749   int i, count_string;
13750   const char *for_string = "\t.byte \"";
13751   const char *for_decimal = "\t.byte ";
13752   const char *to_close = NULL;
13753
13754   count_string = 0;
13755   for (i = 0; i < n; i++)
13756     {
13757       c = *p++;
13758       if (c >= ' ' && c < 0177)
13759         {
13760           if (for_string)
13761             fputs (for_string, file);
13762           putc (c, file);
13763
13764           /* Write two quotes to get one.  */
13765           if (c == '"')
13766             {
13767               putc (c, file);
13768               ++count_string;
13769             }
13770
13771           for_string = NULL;
13772           for_decimal = "\"\n\t.byte ";
13773           to_close = "\"\n";
13774           ++count_string;
13775
13776           if (count_string >= 512)
13777             {
13778               fputs (to_close, file);
13779
13780               for_string = "\t.byte \"";
13781               for_decimal = "\t.byte ";
13782               to_close = NULL;
13783               count_string = 0;
13784             }
13785         }
13786       else
13787         {
13788           if (for_decimal)
13789             fputs (for_decimal, file);
13790           fprintf (file, "%d", c);
13791
13792           for_string = "\n\t.byte \"";
13793           for_decimal = ", ";
13794           to_close = "\n";
13795           count_string = 0;
13796         }
13797     }
13798
13799   /* Now close the string if we have written one.  Then end the line.  */
13800   if (to_close)
13801     fputs (to_close, file);
13802 }
13803 \f
13804 /* Generate a unique section name for FILENAME for a section type
13805    represented by SECTION_DESC.  Output goes into BUF.
13806
13807    SECTION_DESC can be any string, as long as it is different for each
13808    possible section type.
13809
13810    We name the section in the same manner as xlc.  The name begins with an
13811    underscore followed by the filename (after stripping any leading directory
13812    names) with the last period replaced by the string SECTION_DESC.  If
13813    FILENAME does not contain a period, SECTION_DESC is appended to the end of
13814    the name.  */
13815
13816 void
13817 rs6000_gen_section_name (char **buf, const char *filename,
13818                          const char *section_desc)
13819 {
13820   const char *q, *after_last_slash, *last_period = 0;
13821   char *p;
13822   int len;
13823
13824   after_last_slash = filename;
13825   for (q = filename; *q; q++)
13826     {
13827       if (*q == '/')
13828         after_last_slash = q + 1;
13829       else if (*q == '.')
13830         last_period = q;
13831     }
13832
13833   len = strlen (after_last_slash) + strlen (section_desc) + 2;
13834   *buf = (char *) xmalloc (len);
13835
13836   p = *buf;
13837   *p++ = '_';
13838
13839   for (q = after_last_slash; *q; q++)
13840     {
13841       if (q == last_period)
13842         {
13843           strcpy (p, section_desc);
13844           p += strlen (section_desc);
13845           break;
13846         }
13847
13848       else if (ISALNUM (*q))
13849         *p++ = *q;
13850     }
13851
13852   if (last_period == 0)
13853     strcpy (p, section_desc);
13854   else
13855     *p = '\0';
13856 }
13857 \f
13858 /* Emit profile function.  */
13859
13860 void
13861 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13862 {
13863   if (TARGET_PROFILE_KERNEL)
13864     return;
13865
13866   if (DEFAULT_ABI == ABI_AIX)
13867     {
13868 #ifndef NO_PROFILE_COUNTERS
13869 # define NO_PROFILE_COUNTERS 0
13870 #endif
13871       if (NO_PROFILE_COUNTERS)
13872         emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13873       else
13874         {
13875           char buf[30];
13876           const char *label_name;
13877           rtx fun;
13878
13879           ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13880           label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13881           fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13882
13883           emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13884                              fun, Pmode);
13885         }
13886     }
13887   else if (DEFAULT_ABI == ABI_DARWIN)
13888     {
13889       const char *mcount_name = RS6000_MCOUNT;
13890       int caller_addr_regno = LINK_REGISTER_REGNUM;
13891
13892       /* Be conservative and always set this, at least for now.  */
13893       current_function_uses_pic_offset_table = 1;
13894
13895 #if TARGET_MACHO
13896       /* For PIC code, set up a stub and collect the caller's address
13897          from r0, which is where the prologue puts it.  */
13898       if (MACHOPIC_INDIRECT)
13899         {
13900           mcount_name = machopic_stub_name (mcount_name);
13901           if (current_function_uses_pic_offset_table)
13902             caller_addr_regno = 0;
13903         }
13904 #endif
13905       emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13906                          0, VOIDmode, 1,
13907                          gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13908     }
13909 }
13910
13911 /* Write function profiler code.  */
13912
13913 void
13914 output_function_profiler (FILE *file, int labelno)
13915 {
13916   char buf[100];
13917   int save_lr = 8;
13918
13919   switch (DEFAULT_ABI)
13920     {
13921     default:
13922       abort ();
13923
13924     case ABI_V4:
13925       save_lr = 4;
13926       if (!TARGET_32BIT)
13927         {
13928           warning ("no profiling of 64-bit code for this ABI");
13929           return;
13930         }
13931       ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13932       fprintf (file, "\tmflr %s\n", reg_names[0]);
13933       if (flag_pic == 1)
13934         {
13935           fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13936           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13937                        reg_names[0], save_lr, reg_names[1]);
13938           asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13939           asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13940           assemble_name (file, buf);
13941           asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13942         }
13943       else if (flag_pic > 1)
13944         {
13945           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13946                        reg_names[0], save_lr, reg_names[1]);
13947           /* Now, we need to get the address of the label.  */
13948           fputs ("\tbl 1f\n\t.long ", file);
13949           assemble_name (file, buf);
13950           fputs ("-.\n1:", file);
13951           asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13952           asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13953                        reg_names[0], reg_names[11]);
13954           asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13955                        reg_names[0], reg_names[0], reg_names[11]);
13956         }
13957       else
13958         {
13959           asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13960           assemble_name (file, buf);
13961           fputs ("@ha\n", file);
13962           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13963                        reg_names[0], save_lr, reg_names[1]);
13964           asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13965           assemble_name (file, buf);
13966           asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13967         }
13968
13969       /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH.  */
13970       fprintf (file, "\tbl %s%s\n",
13971                RS6000_MCOUNT, flag_pic ? "@plt" : "");
13972       break;
13973
13974     case ABI_AIX:
13975     case ABI_DARWIN:
13976       if (!TARGET_PROFILE_KERNEL)
13977         {
13978           /* Don't do anything, done in output_profile_hook ().  */
13979         }
13980       else
13981         {
13982           if (TARGET_32BIT)
13983             abort ();
13984
13985           asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13986           asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13987
13988           if (current_function_needs_context)
13989             {
13990               asm_fprintf (file, "\tstd %s,24(%s)\n",
13991                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13992               fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13993               asm_fprintf (file, "\tld %s,24(%s)\n",
13994                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13995             }
13996           else
13997             fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13998         }
13999       break;
14000     }
14001 }
14002
14003 \f
14004 static int
14005 rs6000_use_dfa_pipeline_interface (void)
14006 {
14007   return 1;
14008 }
14009
14010 /* Power4 load update and store update instructions are cracked into a
14011    load or store and an integer insn which are executed in the same cycle.
14012    Branches have their own dispatch slot which does not count against the
14013    GCC issue rate, but it changes the program flow so there are no other
14014    instructions to issue in this cycle.  */
14015
14016 static int
14017 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14018                        int verbose ATTRIBUTE_UNUSED,
14019                        rtx insn, int more)
14020 {
14021   if (GET_CODE (PATTERN (insn)) == USE
14022       || GET_CODE (PATTERN (insn)) == CLOBBER)
14023     return more;
14024
14025   if (rs6000_sched_groups)
14026     {
14027       if (is_microcoded_insn (insn))
14028         return 0;
14029       else if (is_cracked_insn (insn))
14030         return more > 2 ? more - 2 : 0;
14031     }
14032
14033   return more - 1;
14034 }
14035
14036 /* Adjust the cost of a scheduling dependency.  Return the new cost of
14037    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
14038
14039 static int
14040 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
14041                     int cost)
14042 {
14043   if (! recog_memoized (insn))
14044     return 0;
14045
14046   if (REG_NOTE_KIND (link) != 0)
14047     return 0;
14048
14049   if (REG_NOTE_KIND (link) == 0)
14050     {
14051       /* Data dependency; DEP_INSN writes a register that INSN reads
14052          some cycles later.  */
14053       switch (get_attr_type (insn))
14054         {
14055         case TYPE_JMPREG:
14056           /* Tell the first scheduling pass about the latency between
14057              a mtctr and bctr (and mtlr and br/blr).  The first
14058              scheduling pass will not know about this latency since
14059              the mtctr instruction, which has the latency associated
14060              to it, will be generated by reload.  */
14061           return TARGET_POWER ? 5 : 4;
14062         case TYPE_BRANCH:
14063           /* Leave some extra cycles between a compare and its
14064              dependent branch, to inhibit expensive mispredicts.  */
14065           if ((rs6000_cpu_attr == CPU_PPC603
14066                || rs6000_cpu_attr == CPU_PPC604
14067                || rs6000_cpu_attr == CPU_PPC604E
14068                || rs6000_cpu_attr == CPU_PPC620
14069                || rs6000_cpu_attr == CPU_PPC630
14070                || rs6000_cpu_attr == CPU_PPC750
14071                || rs6000_cpu_attr == CPU_PPC7400
14072                || rs6000_cpu_attr == CPU_PPC7450
14073                || rs6000_cpu_attr == CPU_POWER4
14074                || rs6000_cpu_attr == CPU_POWER5)
14075               && recog_memoized (dep_insn)
14076               && (INSN_CODE (dep_insn) >= 0)
14077               && (get_attr_type (dep_insn) == TYPE_CMP
14078                   || get_attr_type (dep_insn) == TYPE_COMPARE
14079                   || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
14080                   || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14081                   || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14082                   || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14083                   || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14084                   || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14085             return cost + 2;
14086         default:
14087           break;
14088         }
14089       /* Fall out to return default cost.  */
14090     }
14091
14092   return cost;
14093 }
14094
14095 /* The function returns a true if INSN is microcoded.
14096    Return false otherwise.  */
14097
14098 static bool
14099 is_microcoded_insn (rtx insn)
14100 {
14101   if (!insn || !INSN_P (insn)
14102       || GET_CODE (PATTERN (insn)) == USE
14103       || GET_CODE (PATTERN (insn)) == CLOBBER)
14104     return false;
14105
14106   if (rs6000_sched_groups)
14107     {
14108       enum attr_type type = get_attr_type (insn);
14109       if (type == TYPE_LOAD_EXT_U
14110           || type == TYPE_LOAD_EXT_UX
14111           || type == TYPE_LOAD_UX
14112           || type == TYPE_STORE_UX
14113           || type == TYPE_MFCR)
14114         return true;
14115     }
14116
14117   return false;
14118 }
14119
14120 /* The function returns a nonzero value if INSN can be scheduled only
14121    as the first insn in a dispatch group ("dispatch-slot restricted").
14122    In this case, the returned value indicates how many dispatch slots
14123    the insn occupies (at the beginning of the group).
14124    Return 0 otherwise.  */
14125
14126 static int
14127 is_dispatch_slot_restricted (rtx insn)
14128 {
14129   enum attr_type type;
14130
14131   if (!rs6000_sched_groups)
14132     return 0;
14133
14134   if (!insn
14135       || insn == NULL_RTX
14136       || GET_CODE (insn) == NOTE
14137       || GET_CODE (PATTERN (insn)) == USE
14138       || GET_CODE (PATTERN (insn)) == CLOBBER)
14139     return 0;
14140
14141   type = get_attr_type (insn);
14142
14143   switch (type)
14144     {
14145     case TYPE_MFCR:
14146     case TYPE_MFCRF:
14147     case TYPE_MTCR:
14148     case TYPE_DELAYED_CR:
14149     case TYPE_CR_LOGICAL:
14150     case TYPE_MTJMPR:
14151     case TYPE_MFJMPR:
14152       return 1;
14153     case TYPE_IDIV:
14154     case TYPE_LDIV:
14155       return 2;
14156     default:
14157       if (rs6000_cpu == PROCESSOR_POWER5
14158           && is_cracked_insn (insn))
14159         return 2;
14160       return 0;
14161     }
14162 }
14163
14164 /* The function returns true if INSN is cracked into 2 instructions
14165    by the processor (and therefore occupies 2 issue slots).  */
14166
14167 static bool
14168 is_cracked_insn (rtx insn)
14169 {
14170   if (!insn || !INSN_P (insn)
14171       || GET_CODE (PATTERN (insn)) == USE
14172       || GET_CODE (PATTERN (insn)) == CLOBBER)
14173     return false;
14174
14175   if (rs6000_sched_groups)
14176     {
14177       enum attr_type type = get_attr_type (insn);
14178       if (type == TYPE_LOAD_U || type == TYPE_STORE_U
14179                || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14180                || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14181                || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14182                || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14183                || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14184                || type == TYPE_IDIV || type == TYPE_LDIV
14185                || type == TYPE_INSERT_WORD)
14186         return true;
14187     }
14188
14189   return false;
14190 }
14191
14192 /* The function returns true if INSN can be issued only from
14193    the branch slot.  */
14194
14195 static bool
14196 is_branch_slot_insn (rtx insn)
14197 {
14198   if (!insn || !INSN_P (insn)
14199       || GET_CODE (PATTERN (insn)) == USE
14200       || GET_CODE (PATTERN (insn)) == CLOBBER)
14201     return false;
14202
14203   if (rs6000_sched_groups)
14204     {
14205       enum attr_type type = get_attr_type (insn);
14206       if (type == TYPE_BRANCH || type == TYPE_JMPREG)
14207         return true;
14208       return false;
14209     }
14210
14211   return false;
14212 }
14213
14214 /* A C statement (sans semicolon) to update the integer scheduling
14215    priority INSN_PRIORITY (INSN). Increase the priority to execute the
14216    INSN earlier, reduce the priority to execute INSN later.  Do not
14217    define this macro if you do not need to adjust the scheduling
14218    priorities of insns.  */
14219
14220 static int
14221 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
14222 {
14223   /* On machines (like the 750) which have asymmetric integer units,
14224      where one integer unit can do multiply and divides and the other
14225      can't, reduce the priority of multiply/divide so it is scheduled
14226      before other integer operations.  */
14227
14228 #if 0
14229   if (! INSN_P (insn))
14230     return priority;
14231
14232   if (GET_CODE (PATTERN (insn)) == USE)
14233     return priority;
14234
14235   switch (rs6000_cpu_attr) {
14236   case CPU_PPC750:
14237     switch (get_attr_type (insn))
14238       {
14239       default:
14240         break;
14241
14242       case TYPE_IMUL:
14243       case TYPE_IDIV:
14244         fprintf (stderr, "priority was %#x (%d) before adjustment\n",
14245                  priority, priority);
14246         if (priority >= 0 && priority < 0x01000000)
14247           priority >>= 3;
14248         break;
14249       }
14250   }
14251 #endif
14252
14253   if (is_dispatch_slot_restricted (insn)
14254       && reload_completed
14255       && current_sched_info->sched_max_insns_priority
14256       && rs6000_sched_restricted_insns_priority)
14257     {
14258
14259       /* Prioritize insns that can be dispatched only in the first dispatch slot.  */
14260       if (rs6000_sched_restricted_insns_priority == 1)
14261         /* Attach highest priority to insn. This means that in
14262            haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
14263            precede 'priority' (critical path) considerations.  */
14264         return current_sched_info->sched_max_insns_priority;
14265       else if (rs6000_sched_restricted_insns_priority == 2)
14266         /* Increase priority of insn by a minimal amount. This means that in
14267            haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
14268            precede dispatch-slot restriction considerations.  */
14269         return (priority + 1);
14270     }
14271
14272   return priority;
14273 }
14274
14275 /* Return how many instructions the machine can issue per cycle.  */
14276
14277 static int
14278 rs6000_issue_rate (void)
14279 {
14280   /* Use issue rate of 1 for first scheduling pass to decrease degradation.  */
14281   if (!reload_completed)
14282     return 1;
14283
14284   switch (rs6000_cpu_attr) {
14285   case CPU_RIOS1:  /* ? */
14286   case CPU_RS64A:
14287   case CPU_PPC601: /* ? */
14288   case CPU_PPC7450:
14289     return 3;
14290   case CPU_PPC440:
14291   case CPU_PPC603:
14292   case CPU_PPC750:
14293   case CPU_PPC7400:
14294   case CPU_PPC8540:
14295     return 2;
14296   case CPU_RIOS2:
14297   case CPU_PPC604:
14298   case CPU_PPC604E:
14299   case CPU_PPC620:
14300   case CPU_PPC630:
14301     return 4;
14302   case CPU_POWER4:
14303   case CPU_POWER5:
14304     return 5;
14305   default:
14306     return 1;
14307   }
14308 }
14309
14310 /* Return how many instructions to look ahead for better insn
14311    scheduling.  */
14312
14313 static int
14314 rs6000_use_sched_lookahead (void)
14315 {
14316   if (rs6000_cpu_attr == CPU_PPC8540)
14317     return 4;
14318   return 0;
14319 }
14320
14321 /* Determine is PAT refers to memory.  */
14322
14323 static bool
14324 is_mem_ref (rtx pat)
14325 {
14326   const char * fmt;
14327   int i, j;
14328   bool ret = false;
14329
14330   if (GET_CODE (pat) == MEM)
14331     return true;
14332
14333   /* Recursively process the pattern.  */
14334   fmt = GET_RTX_FORMAT (GET_CODE (pat));
14335
14336   for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
14337     {
14338       if (fmt[i] == 'e')
14339         ret |= is_mem_ref (XEXP (pat, i));
14340       else if (fmt[i] == 'E')
14341         for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
14342           ret |= is_mem_ref (XVECEXP (pat, i, j));
14343     }
14344
14345   return ret;
14346 }
14347
14348 /* Determine if PAT is a PATTERN of a load insn.  */
14349
14350 static bool
14351 is_load_insn1 (rtx pat)
14352 {
14353   if (!pat || pat == NULL_RTX)
14354     return false;
14355
14356   if (GET_CODE (pat) == SET)
14357     return is_mem_ref (SET_SRC (pat));
14358
14359   if (GET_CODE (pat) == PARALLEL)
14360     {
14361       int i;
14362
14363       for (i = 0; i < XVECLEN (pat, 0); i++)
14364         if (is_load_insn1 (XVECEXP (pat, 0, i)))
14365           return true;
14366     }
14367
14368   return false;
14369 }
14370
14371 /* Determine if INSN loads from memory.  */
14372
14373 static bool
14374 is_load_insn (rtx insn)
14375 {
14376   if (!insn || !INSN_P (insn))
14377     return false;
14378
14379   if (GET_CODE (insn) == CALL_INSN)
14380     return false;
14381
14382   return is_load_insn1 (PATTERN (insn));
14383 }
14384
14385 /* Determine if PAT is a PATTERN of a store insn.  */
14386
14387 static bool
14388 is_store_insn1 (rtx pat)
14389 {
14390   if (!pat || pat == NULL_RTX)
14391     return false;
14392
14393   if (GET_CODE (pat) == SET)
14394     return is_mem_ref (SET_DEST (pat));
14395
14396   if (GET_CODE (pat) == PARALLEL)
14397     {
14398       int i;
14399
14400       for (i = 0; i < XVECLEN (pat, 0); i++)
14401         if (is_store_insn1 (XVECEXP (pat, 0, i)))
14402           return true;
14403     }
14404
14405   return false;
14406 }
14407
14408 /* Determine if INSN stores to memory.  */
14409
14410 static bool
14411 is_store_insn (rtx insn)
14412 {
14413   if (!insn || !INSN_P (insn))
14414     return false;
14415
14416   return is_store_insn1 (PATTERN (insn));
14417 }
14418
14419 /* Returns whether the dependence between INSN and NEXT is considered
14420    costly by the given target.  */
14421
14422 static bool
14423 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
14424 {
14425   /* If the flag is not enbled - no dependence is considered costly;
14426      allow all dependent insns in the same group.
14427      This is the most aggressive option.  */
14428   if (rs6000_sched_costly_dep == no_dep_costly)
14429     return false;
14430
14431   /* If the flag is set to 1 - a dependence is always considered costly;
14432      do not allow dependent instructions in the same group.
14433      This is the most conservative option.  */
14434   if (rs6000_sched_costly_dep == all_deps_costly)
14435     return true;
14436
14437   if (rs6000_sched_costly_dep == store_to_load_dep_costly
14438       && is_load_insn (next)
14439       && is_store_insn (insn))
14440     /* Prevent load after store in the same group.  */
14441     return true;
14442
14443   if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
14444       && is_load_insn (next)
14445       && is_store_insn (insn)
14446       && (!link || (int) REG_NOTE_KIND (link) == 0))
14447      /* Prevent load after store in the same group if it is a true dependence.  */
14448      return true;
14449
14450   /* The flag is set to X; dependences with latency >= X are considered costly,
14451      and will not be scheduled in the same group.  */
14452   if (rs6000_sched_costly_dep <= max_dep_latency
14453       && ((cost - distance) >= (int)rs6000_sched_costly_dep))
14454     return true;
14455
14456   return false;
14457 }
14458
14459 /* Return the next insn after INSN that is found before TAIL is reached,
14460    skipping any "non-active" insns - insns that will not actually occupy
14461    an issue slot.  Return NULL_RTX if such an insn is not found.  */
14462
14463 static rtx
14464 get_next_active_insn (rtx insn, rtx tail)
14465 {
14466   rtx next_insn;
14467
14468   if (!insn || insn == tail)
14469     return NULL_RTX;
14470
14471   next_insn = NEXT_INSN (insn);
14472
14473   while (next_insn
14474          && next_insn != tail
14475          && (GET_CODE(next_insn) == NOTE
14476              || GET_CODE (PATTERN (next_insn)) == USE
14477              || GET_CODE (PATTERN (next_insn)) == CLOBBER))
14478     {
14479       next_insn = NEXT_INSN (next_insn);
14480     }
14481
14482   if (!next_insn || next_insn == tail)
14483     return NULL_RTX;
14484
14485   return next_insn;
14486 }
14487
14488 /* Return whether the presence of INSN causes a dispatch group termination
14489    of group WHICH_GROUP.
14490
14491    If WHICH_GROUP == current_group, this function will return true if INSN
14492    causes the termination of the current group (i.e, the dispatch group to
14493    which INSN belongs). This means that INSN will be the last insn in the
14494    group it belongs to.
14495
14496    If WHICH_GROUP == previous_group, this function will return true if INSN
14497    causes the termination of the previous group (i.e, the dispatch group that
14498    precedes the group to which INSN belongs).  This means that INSN will be
14499    the first insn in the group it belongs to).  */
14500
14501 static bool
14502 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14503 {
14504   enum attr_type type;
14505
14506   if (! insn)
14507     return false;
14508
14509   type = get_attr_type (insn);
14510
14511   if (is_microcoded_insn (insn))
14512     return true;
14513
14514   if (which_group == current_group)
14515     {
14516       if (is_branch_slot_insn (insn))
14517         return true;
14518       return false;
14519     }
14520   else if (which_group == previous_group)
14521     {
14522       if (is_dispatch_slot_restricted (insn))
14523         return true;
14524       return false;
14525     }
14526
14527   return false;
14528 }
14529
14530 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14531    dispatch group) from the insns in GROUP_INSNS.  Return false otherwise.  */
14532
14533 static bool
14534 is_costly_group (rtx *group_insns, rtx next_insn)
14535 {
14536   int i;
14537   rtx link;
14538   int cost;
14539   int issue_rate = rs6000_issue_rate ();
14540
14541   for (i = 0; i < issue_rate; i++)
14542     {
14543       rtx insn = group_insns[i];
14544       if (!insn)
14545         continue;
14546       for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14547         {
14548           rtx next = XEXP (link, 0);
14549           if (next == next_insn)
14550             {
14551               cost = insn_cost (insn, link, next_insn);
14552               if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14553                 return true;
14554             }
14555         }
14556     }
14557
14558   return false;
14559 }
14560
14561 /* Utility of the function redefine_groups.
14562    Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14563    in the same dispatch group.  If so, insert nops before NEXT_INSN, in order
14564    to keep it "far" (in a separate group) from GROUP_INSNS, following
14565    one of the following schemes, depending on the value of the flag
14566    -minsert_sched_nops = X:
14567    (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14568        in order to force NEXT_INSN into a separate group.
14569    (2) X < sched_finish_regroup_exact: insert exactly X nops.
14570    GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14571    insertion (has a group just ended, how many vacant issue slots remain in the
14572    last group, and how many dispatch groups were encountered so far).  */
14573
14574 static int
14575 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14576                  bool *group_end, int can_issue_more, int *group_count)
14577 {
14578   rtx nop;
14579   bool force;
14580   int issue_rate = rs6000_issue_rate ();
14581   bool end = *group_end;
14582   int i;
14583
14584   if (next_insn == NULL_RTX)
14585     return can_issue_more;
14586
14587   if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14588     return can_issue_more;
14589
14590   force = is_costly_group (group_insns, next_insn);
14591   if (!force)
14592     return can_issue_more;
14593
14594   if (sched_verbose > 6)
14595     fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14596                         *group_count ,can_issue_more);
14597
14598   if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14599     {
14600       if (*group_end)
14601         can_issue_more = 0;
14602
14603       /* Since only a branch can be issued in the last issue_slot, it is
14604          sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14605          a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14606          in this case the last nop will start a new group and the branch will be
14607          forced to the new group.  */
14608       if (can_issue_more && !is_branch_slot_insn (next_insn))
14609         can_issue_more--;
14610
14611       while (can_issue_more > 0)
14612         {
14613           nop = gen_nop();
14614           emit_insn_before (nop, next_insn);
14615           can_issue_more--;
14616         }
14617
14618       *group_end = true;
14619       return 0;
14620     }
14621
14622   if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14623     {
14624       int n_nops = rs6000_sched_insert_nops;
14625
14626       /* Nops can't be issued from the branch slot, so the effective
14627          issue_rate for nops is 'issue_rate - 1'.  */
14628       if (can_issue_more == 0)
14629         can_issue_more = issue_rate;
14630       can_issue_more--;
14631       if (can_issue_more == 0)
14632         {
14633           can_issue_more = issue_rate - 1;
14634           (*group_count)++;
14635           end = true;
14636           for (i = 0; i < issue_rate; i++)
14637             {
14638               group_insns[i] = 0;
14639             }
14640         }
14641
14642       while (n_nops > 0)
14643         {
14644           nop = gen_nop ();
14645           emit_insn_before (nop, next_insn);
14646           if (can_issue_more == issue_rate - 1) /* new group begins */
14647             end = false;
14648           can_issue_more--;
14649           if (can_issue_more == 0)
14650             {
14651               can_issue_more = issue_rate - 1;
14652               (*group_count)++;
14653               end = true;
14654               for (i = 0; i < issue_rate; i++)
14655                 {
14656                   group_insns[i] = 0;
14657                 }
14658             }
14659           n_nops--;
14660         }
14661
14662       /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1').  */
14663       can_issue_more++;
14664
14665       *group_end = /* Is next_insn going to start a new group?  */
14666           (end
14667            || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14668            || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14669            || (can_issue_more < issue_rate &&
14670               insn_terminates_group_p (next_insn, previous_group)));
14671       if (*group_end && end)
14672         (*group_count)--;
14673
14674       if (sched_verbose > 6)
14675         fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14676                         *group_count, can_issue_more);
14677       return can_issue_more;
14678     }
14679
14680   return can_issue_more;
14681 }
14682
14683 /* This function tries to synch the dispatch groups that the compiler "sees"
14684    with the dispatch groups that the processor dispatcher is expected to
14685    form in practice.  It tries to achieve this synchronization by forcing the
14686    estimated processor grouping on the compiler (as opposed to the function
14687    'pad_goups' which tries to force the scheduler's grouping on the processor).
14688
14689    The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14690    examines the (estimated) dispatch groups that will be formed by the processor
14691    dispatcher.  It marks these group boundaries to reflect the estimated
14692    processor grouping, overriding the grouping that the scheduler had marked.
14693    Depending on the value of the flag '-minsert-sched-nops' this function can
14694    force certain insns into separate groups or force a certain distance between
14695    them by inserting nops, for example, if there exists a "costly dependence"
14696    between the insns.
14697
14698    The function estimates the group boundaries that the processor will form as
14699    folllows:  It keeps track of how many vacant issue slots are available after
14700    each insn.  A subsequent insn will start a new group if one of the following
14701    4 cases applies:
14702    - no more vacant issue slots remain in the current dispatch group.
14703    - only the last issue slot, which is the branch slot, is vacant, but the next
14704      insn is not a branch.
14705    - only the last 2 or less issue slots, including the branch slot, are vacant,
14706      which means that a cracked insn (which occupies two issue slots) can't be
14707      issued in this group.
14708    - less than 'issue_rate' slots are vacant, and the next insn always needs to
14709      start a new group.  */
14710
14711 static int
14712 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14713 {
14714   rtx insn, next_insn;
14715   int issue_rate;
14716   int can_issue_more;
14717   int slot, i;
14718   bool group_end;
14719   int group_count = 0;
14720   rtx *group_insns;
14721
14722   /* Initialize.  */
14723   issue_rate = rs6000_issue_rate ();
14724   group_insns = alloca (issue_rate * sizeof (rtx));
14725   for (i = 0; i < issue_rate; i++)
14726     {
14727       group_insns[i] = 0;
14728     }
14729   can_issue_more = issue_rate;
14730   slot = 0;
14731   insn = get_next_active_insn (prev_head_insn, tail);
14732   group_end = false;
14733
14734   while (insn != NULL_RTX)
14735     {
14736       slot = (issue_rate - can_issue_more);
14737       group_insns[slot] = insn;
14738       can_issue_more =
14739         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14740       if (insn_terminates_group_p (insn, current_group))
14741         can_issue_more = 0;
14742
14743       next_insn = get_next_active_insn (insn, tail);
14744       if (next_insn == NULL_RTX)
14745         return group_count + 1;
14746
14747       group_end = /* Is next_insn going to start a new group?  */
14748         (can_issue_more == 0
14749          || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14750          || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14751          || (can_issue_more < issue_rate &&
14752              insn_terminates_group_p (next_insn, previous_group)));
14753
14754       can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14755                         next_insn, &group_end, can_issue_more, &group_count);
14756
14757       if (group_end)
14758         {
14759           group_count++;
14760           can_issue_more = 0;
14761           for (i = 0; i < issue_rate; i++)
14762             {
14763               group_insns[i] = 0;
14764             }
14765         }
14766
14767       if (GET_MODE (next_insn) == TImode && can_issue_more)
14768         PUT_MODE(next_insn, VOIDmode);
14769       else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14770         PUT_MODE (next_insn, TImode);
14771
14772       insn = next_insn;
14773       if (can_issue_more == 0)
14774         can_issue_more = issue_rate;
14775    } /* while */
14776
14777   return group_count;
14778 }
14779
14780 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14781    dispatch group boundaries that the scheduler had marked.  Pad with nops
14782    any dispatch groups which have vacant issue slots, in order to force the
14783    scheduler's grouping on the processor dispatcher.  The function
14784    returns the number of dispatch groups found.  */
14785
14786 static int
14787 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14788 {
14789   rtx insn, next_insn;
14790   rtx nop;
14791   int issue_rate;
14792   int can_issue_more;
14793   int group_end;
14794   int group_count = 0;
14795
14796   /* Initialize issue_rate.  */
14797   issue_rate = rs6000_issue_rate ();
14798   can_issue_more = issue_rate;
14799
14800   insn = get_next_active_insn (prev_head_insn, tail);
14801   next_insn = get_next_active_insn (insn, tail);
14802
14803   while (insn != NULL_RTX)
14804     {
14805       can_issue_more =
14806         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14807
14808       group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14809
14810       if (next_insn == NULL_RTX)
14811         break;
14812
14813       if (group_end)
14814         {
14815           /* If the scheduler had marked group termination at this location
14816              (between insn and next_indn), and neither insn nor next_insn will
14817              force group termination, pad the group with nops to force group
14818              termination.  */
14819           if (can_issue_more
14820               && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14821               && !insn_terminates_group_p (insn, current_group)
14822               && !insn_terminates_group_p (next_insn, previous_group))
14823             {
14824               if (!is_branch_slot_insn(next_insn))
14825                 can_issue_more--;
14826
14827               while (can_issue_more)
14828                 {
14829                   nop = gen_nop ();
14830                   emit_insn_before (nop, next_insn);
14831                   can_issue_more--;
14832                 }
14833             }
14834
14835           can_issue_more = issue_rate;
14836           group_count++;
14837         }
14838
14839       insn = next_insn;
14840       next_insn = get_next_active_insn (insn, tail);
14841     }
14842
14843   return group_count;
14844 }
14845
14846 /* The following function is called at the end of scheduling BB.
14847    After reload, it inserts nops at insn group bundling.  */
14848
14849 static void
14850 rs6000_sched_finish (FILE *dump, int sched_verbose)
14851 {
14852   int n_groups;
14853
14854   if (sched_verbose)
14855     fprintf (dump, "=== Finishing schedule.\n");
14856
14857   if (reload_completed && rs6000_sched_groups)
14858     {
14859       if (rs6000_sched_insert_nops == sched_finish_none)
14860         return;
14861
14862       if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14863         n_groups = pad_groups (dump, sched_verbose,
14864                                 current_sched_info->prev_head,
14865                                 current_sched_info->next_tail);
14866       else
14867         n_groups = redefine_groups (dump, sched_verbose,
14868                                 current_sched_info->prev_head,
14869                                 current_sched_info->next_tail);
14870
14871       if (sched_verbose >= 6)
14872         {
14873           fprintf (dump, "ngroups = %d\n", n_groups);
14874           print_rtl (dump, current_sched_info->prev_head);
14875           fprintf (dump, "Done finish_sched\n");
14876         }
14877     }
14878 }
14879 \f
14880 /* Length in units of the trampoline for entering a nested function.  */
14881
14882 int
14883 rs6000_trampoline_size (void)
14884 {
14885   int ret = 0;
14886
14887   switch (DEFAULT_ABI)
14888     {
14889     default:
14890       abort ();
14891
14892     case ABI_AIX:
14893       ret = (TARGET_32BIT) ? 12 : 24;
14894       break;
14895
14896     case ABI_DARWIN:
14897     case ABI_V4:
14898       ret = (TARGET_32BIT) ? 40 : 48;
14899       break;
14900     }
14901
14902   return ret;
14903 }
14904
14905 /* Emit RTL insns to initialize the variable parts of a trampoline.
14906    FNADDR is an RTX for the address of the function's pure code.
14907    CXT is an RTX for the static chain value for the function.  */
14908
14909 void
14910 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14911 {
14912   enum machine_mode pmode = Pmode;
14913   int regsize = (TARGET_32BIT) ? 4 : 8;
14914   rtx ctx_reg = force_reg (pmode, cxt);
14915
14916   switch (DEFAULT_ABI)
14917     {
14918     default:
14919       abort ();
14920
14921 /* Macros to shorten the code expansions below.  */
14922 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14923 #define MEM_PLUS(addr,offset) \
14924   gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14925
14926     /* Under AIX, just build the 3 word function descriptor */
14927     case ABI_AIX:
14928       {
14929         rtx fn_reg = gen_reg_rtx (pmode);
14930         rtx toc_reg = gen_reg_rtx (pmode);
14931         emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14932         emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14933         emit_move_insn (MEM_DEREF (addr), fn_reg);
14934         emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14935         emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14936       }
14937       break;
14938
14939     /* Under V.4/eabi/darwin, __trampoline_setup does the real work.  */
14940     case ABI_DARWIN:
14941     case ABI_V4:
14942       emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14943                          FALSE, VOIDmode, 4,
14944                          addr, pmode,
14945                          GEN_INT (rs6000_trampoline_size ()), SImode,
14946                          fnaddr, pmode,
14947                          ctx_reg, pmode);
14948       break;
14949     }
14950
14951   return;
14952 }
14953
14954 \f
14955 /* Table of valid machine attributes.  */
14956
14957 const struct attribute_spec rs6000_attribute_table[] =
14958 {
14959   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14960   { "altivec",   1, 1, false, true,  false, rs6000_handle_altivec_attribute },
14961   { "longcall",  0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14962   { "shortcall", 0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14963   { NULL,        0, 0, false, false, false, NULL }
14964 };
14965
14966 /* Handle the "altivec" attribute.  The attribute may have
14967    arguments as follows:
14968
14969         __attribute__((altivec(vector__)))
14970         __attribute__((altivec(pixel__)))       (always followed by 'unsigned short')
14971         __attribute__((altivec(bool__)))        (always followed by 'unsigned')
14972
14973   and may appear more than once (e.g., 'vector bool char') in a
14974   given declaration.  */
14975
14976 static tree
14977 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
14978                                  int flags ATTRIBUTE_UNUSED,
14979                                  bool *no_add_attrs)
14980 {
14981   tree type = *node, result = NULL_TREE;
14982   enum machine_mode mode;
14983   int unsigned_p;
14984   char altivec_type
14985     = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
14986         && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
14987        ? *IDENTIFIER_POINTER (TREE_VALUE (args))
14988        : '?');
14989
14990   while (POINTER_TYPE_P (type)
14991          || TREE_CODE (type) == FUNCTION_TYPE
14992          || TREE_CODE (type) == METHOD_TYPE
14993          || TREE_CODE (type) == ARRAY_TYPE)
14994     type = TREE_TYPE (type);
14995
14996   mode = TYPE_MODE (type);
14997
14998   if (rs6000_warn_altivec_long
14999       && (type == long_unsigned_type_node || type == long_integer_type_node))
15000     warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
15001
15002   switch (altivec_type)
15003     {
15004     case 'v':
15005       unsigned_p = TYPE_UNSIGNED (type);
15006       switch (mode)
15007         {
15008           case SImode:
15009             result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15010             break;
15011           case HImode:
15012             result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15013             break;
15014           case QImode:
15015             result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15016             break;
15017           case SFmode: result = V4SF_type_node; break;
15018             /* If the user says 'vector int bool', we may be handed the 'bool'
15019                attribute _before_ the 'vector' attribute, and so select the proper
15020                type in the 'b' case below.  */
15021           case V4SImode: case V8HImode: case V16QImode: result = type;
15022           default: break;
15023         }
15024       break;
15025     case 'b':
15026       switch (mode)
15027         {
15028           case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15029           case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15030           case QImode: case V16QImode: result = bool_V16QI_type_node;
15031           default: break;
15032         }
15033       break;
15034     case 'p':
15035       switch (mode)
15036         {
15037           case V8HImode: result = pixel_V8HI_type_node;
15038           default: break;
15039         }
15040     default: break;
15041     }
15042
15043   *no_add_attrs = true;  /* No need to hang on to the attribute.  */
15044
15045   if (!result)
15046     warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
15047   else
15048     *node = reconstruct_complex_type (*node, result);
15049
15050   return NULL_TREE;
15051 }
15052
15053 /* AltiVec defines four built-in scalar types that serve as vector
15054    elements; we must teach the compiler how to mangle them.  */
15055
15056 static const char *
15057 rs6000_mangle_fundamental_type (tree type)
15058 {
15059   if (type == bool_char_type_node) return "U6__boolc";
15060   if (type == bool_short_type_node) return "U6__bools";
15061   if (type == pixel_type_node) return "u7__pixel";
15062   if (type == bool_int_type_node) return "U6__booli";
15063
15064   /* For all other types, use normal C++ mangling.  */
15065   return NULL;
15066 }
15067
15068 /* Handle a "longcall" or "shortcall" attribute; arguments as in
15069    struct attribute_spec.handler.  */
15070
15071 static tree
15072 rs6000_handle_longcall_attribute (tree *node, tree name,
15073                                   tree args ATTRIBUTE_UNUSED,
15074                                   int flags ATTRIBUTE_UNUSED,
15075                                   bool *no_add_attrs)
15076 {
15077   if (TREE_CODE (*node) != FUNCTION_TYPE
15078       && TREE_CODE (*node) != FIELD_DECL
15079       && TREE_CODE (*node) != TYPE_DECL)
15080     {
15081       warning ("`%s' attribute only applies to functions",
15082                IDENTIFIER_POINTER (name));
15083       *no_add_attrs = true;
15084     }
15085
15086   return NULL_TREE;
15087 }
15088
15089 /* Set longcall attributes on all functions declared when
15090    rs6000_default_long_calls is true.  */
15091 static void
15092 rs6000_set_default_type_attributes (tree type)
15093 {
15094   if (rs6000_default_long_calls
15095       && (TREE_CODE (type) == FUNCTION_TYPE
15096           || TREE_CODE (type) == METHOD_TYPE))
15097     TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15098                                         NULL_TREE,
15099                                         TYPE_ATTRIBUTES (type));
15100 }
15101
15102 /* Return a reference suitable for calling a function with the
15103    longcall attribute.  */
15104
15105 struct rtx_def *
15106 rs6000_longcall_ref (rtx call_ref)
15107 {
15108   const char *call_name;
15109   tree node;
15110
15111   if (GET_CODE (call_ref) != SYMBOL_REF)
15112     return call_ref;
15113
15114   /* System V adds '.' to the internal name, so skip them.  */
15115   call_name = XSTR (call_ref, 0);
15116   if (*call_name == '.')
15117     {
15118       while (*call_name == '.')
15119         call_name++;
15120
15121       node = get_identifier (call_name);
15122       call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15123     }
15124
15125   return force_reg (Pmode, call_ref);
15126 }
15127 \f
15128 #ifdef USING_ELFOS_H
15129
15130 /* A C statement or statements to switch to the appropriate section
15131    for output of RTX in mode MODE.  You can assume that RTX is some
15132    kind of constant in RTL.  The argument MODE is redundant except in
15133    the case of a `const_int' rtx.  Select the section by calling
15134    `text_section' or one of the alternatives for other sections.
15135
15136    Do not define this macro if you put all constants in the read-only
15137    data section.  */
15138
15139 static void
15140 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15141                                unsigned HOST_WIDE_INT align)
15142 {
15143   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15144     toc_section ();
15145   else
15146     default_elf_select_rtx_section (mode, x, align);
15147 }
15148
15149 /* A C statement or statements to switch to the appropriate
15150    section for output of DECL.  DECL is either a `VAR_DECL' node
15151    or a constant of some sort.  RELOC indicates whether forming
15152    the initial value of DECL requires link-time relocations.  */
15153
15154 static void
15155 rs6000_elf_select_section (tree decl, int reloc,
15156                            unsigned HOST_WIDE_INT align)
15157 {
15158   /* Pretend that we're always building for a shared library when
15159      ABI_AIX, because otherwise we end up with dynamic relocations
15160      in read-only sections.  This happens for function pointers,
15161      references to vtables in typeinfo, and probably other cases.  */
15162   default_elf_select_section_1 (decl, reloc, align,
15163                                 flag_pic || DEFAULT_ABI == ABI_AIX);
15164 }
15165
15166 /* A C statement to build up a unique section name, expressed as a
15167    STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
15168    RELOC indicates whether the initial value of EXP requires
15169    link-time relocations.  If you do not define this macro, GCC will use
15170    the symbol name prefixed by `.' as the section name.  Note - this
15171    macro can now be called for uninitialized data items as well as
15172    initialized data and functions.  */
15173
15174 static void
15175 rs6000_elf_unique_section (tree decl, int reloc)
15176 {
15177   /* As above, pretend that we're always building for a shared library
15178      when ABI_AIX, to avoid dynamic relocations in read-only sections.  */
15179   default_unique_section_1 (decl, reloc,
15180                             flag_pic || DEFAULT_ABI == ABI_AIX);
15181 }
15182 \f
15183 /* For a SYMBOL_REF, set generic flags and then perform some
15184    target-specific processing.
15185
15186    When the AIX ABI is requested on a non-AIX system, replace the
15187    function name with the real name (with a leading .) rather than the
15188    function descriptor name.  This saves a lot of overriding code to
15189    read the prefixes.  */
15190
15191 static void
15192 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
15193 {
15194   default_encode_section_info (decl, rtl, first);
15195
15196   if (first
15197       && TREE_CODE (decl) == FUNCTION_DECL
15198       && !TARGET_AIX
15199       && DEFAULT_ABI == ABI_AIX)
15200     {
15201       rtx sym_ref = XEXP (rtl, 0);
15202       size_t len = strlen (XSTR (sym_ref, 0));
15203       char *str = alloca (len + 2);
15204       str[0] = '.';
15205       memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
15206       XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
15207     }
15208 }
15209
15210 static bool
15211 rs6000_elf_in_small_data_p (tree decl)
15212 {
15213   if (rs6000_sdata == SDATA_NONE)
15214     return false;
15215
15216   if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
15217     {
15218       const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
15219       if (strcmp (section, ".sdata") == 0
15220           || strcmp (section, ".sdata2") == 0
15221           || strcmp (section, ".sbss") == 0
15222           || strcmp (section, ".sbss2") == 0
15223           || strcmp (section, ".PPC.EMB.sdata0") == 0
15224           || strcmp (section, ".PPC.EMB.sbss0") == 0)
15225         return true;
15226     }
15227   else
15228     {
15229       HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
15230
15231       if (size > 0
15232           && (unsigned HOST_WIDE_INT) size <= g_switch_value
15233           /* If it's not public, and we're not going to reference it there,
15234              there's no need to put it in the small data section.  */
15235           && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
15236         return true;
15237     }
15238
15239   return false;
15240 }
15241
15242 #endif /* USING_ELFOS_H */
15243
15244 \f
15245 /* Return a REG that occurs in ADDR with coefficient 1.
15246    ADDR can be effectively incremented by incrementing REG.
15247
15248    r0 is special and we must not select it as an address
15249    register by this routine since our caller will try to
15250    increment the returned register via an "la" instruction.  */
15251
15252 struct rtx_def *
15253 find_addr_reg (rtx addr)
15254 {
15255   while (GET_CODE (addr) == PLUS)
15256     {
15257       if (GET_CODE (XEXP (addr, 0)) == REG
15258           && REGNO (XEXP (addr, 0)) != 0)
15259         addr = XEXP (addr, 0);
15260       else if (GET_CODE (XEXP (addr, 1)) == REG
15261                && REGNO (XEXP (addr, 1)) != 0)
15262         addr = XEXP (addr, 1);
15263       else if (CONSTANT_P (XEXP (addr, 0)))
15264         addr = XEXP (addr, 1);
15265       else if (CONSTANT_P (XEXP (addr, 1)))
15266         addr = XEXP (addr, 0);
15267       else
15268         abort ();
15269     }
15270   if (GET_CODE (addr) == REG && REGNO (addr) != 0)
15271     return addr;
15272   abort ();
15273 }
15274
15275 void
15276 rs6000_fatal_bad_address (rtx op)
15277 {
15278   fatal_insn ("bad address", op);
15279 }
15280
15281 #if TARGET_MACHO
15282
15283 #if 0
15284 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
15285    reference and a constant.  */
15286
15287 int
15288 symbolic_operand (rtx op)
15289 {
15290   switch (GET_CODE (op))
15291     {
15292     case SYMBOL_REF:
15293     case LABEL_REF:
15294       return 1;
15295     case CONST:
15296       op = XEXP (op, 0);
15297       return (GET_CODE (op) == SYMBOL_REF ||
15298               (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
15299                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
15300               && GET_CODE (XEXP (op, 1)) == CONST_INT);
15301     default:
15302       return 0;
15303     }
15304 }
15305 #endif
15306
15307 #if TARGET_MACHO
15308
15309 static tree branch_island_list = 0;
15310
15311 /* Remember to generate a branch island for far calls to the given
15312    function.  */
15313
15314 static void
15315 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
15316 {
15317   tree branch_island = build_tree_list (function_name, label_name);
15318   TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
15319   TREE_CHAIN (branch_island) = branch_island_list;
15320   branch_island_list = branch_island;
15321 }
15322
15323 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND)     TREE_VALUE (BRANCH_ISLAND)
15324 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND)  TREE_PURPOSE (BRANCH_ISLAND)
15325 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND)    \
15326                 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
15327
15328 /* Generate far-jump branch islands for everything on the
15329    branch_island_list.  Invoked immediately after the last instruction
15330    of the epilogue has been emitted; the branch-islands must be
15331    appended to, and contiguous with, the function body.  Mach-O stubs
15332    are generated in machopic_output_stub().  */
15333
15334 static void
15335 macho_branch_islands (void)
15336 {
15337   char tmp_buf[512];
15338   tree branch_island;
15339
15340   for (branch_island = branch_island_list;
15341        branch_island;
15342        branch_island = TREE_CHAIN (branch_island))
15343     {
15344       const char *label =
15345         IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
15346       const char *name  =
15347         darwin_strip_name_encoding (
15348           IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
15349       char name_buf[512];
15350       /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF().  */
15351       if (name[0] == '*' || name[0] == '&')
15352         strcpy (name_buf, name+1);
15353       else
15354         {
15355           name_buf[0] = '_';
15356           strcpy (name_buf+1, name);
15357         }
15358       strcpy (tmp_buf, "\n");
15359       strcat (tmp_buf, label);
15360 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15361       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15362         fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15363                  BRANCH_ISLAND_LINE_NUMBER(branch_island));
15364 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15365       if (flag_pic)
15366         {
15367           strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
15368           strcat (tmp_buf, label);
15369           strcat (tmp_buf, "_pic\n");
15370           strcat (tmp_buf, label);
15371           strcat (tmp_buf, "_pic:\n\tmflr r11\n");
15372
15373           strcat (tmp_buf, "\taddis r11,r11,ha16(");
15374           strcat (tmp_buf, name_buf);
15375           strcat (tmp_buf, " - ");
15376           strcat (tmp_buf, label);
15377           strcat (tmp_buf, "_pic)\n");
15378
15379           strcat (tmp_buf, "\tmtlr r0\n");
15380
15381           strcat (tmp_buf, "\taddi r12,r11,lo16(");
15382           strcat (tmp_buf, name_buf);
15383           strcat (tmp_buf, " - ");
15384           strcat (tmp_buf, label);
15385           strcat (tmp_buf, "_pic)\n");
15386
15387           strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
15388         }
15389       else
15390         {
15391           strcat (tmp_buf, ":\nlis r12,hi16(");
15392           strcat (tmp_buf, name_buf);
15393           strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
15394           strcat (tmp_buf, name_buf);
15395           strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
15396         }
15397       output_asm_insn (tmp_buf, 0);
15398 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15399       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15400         fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15401                 BRANCH_ISLAND_LINE_NUMBER (branch_island));
15402 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15403     }
15404
15405   branch_island_list = 0;
15406 }
15407
15408 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
15409    already there or not.  */
15410
15411 static int
15412 no_previous_def (tree function_name)
15413 {
15414   tree branch_island;
15415   for (branch_island = branch_island_list;
15416        branch_island;
15417        branch_island = TREE_CHAIN (branch_island))
15418     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15419       return 0;
15420   return 1;
15421 }
15422
15423 /* GET_PREV_LABEL gets the label name from the previous definition of
15424    the function.  */
15425
15426 static tree
15427 get_prev_label (tree function_name)
15428 {
15429   tree branch_island;
15430   for (branch_island = branch_island_list;
15431        branch_island;
15432        branch_island = TREE_CHAIN (branch_island))
15433     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15434       return BRANCH_ISLAND_LABEL_NAME (branch_island);
15435   return 0;
15436 }
15437
15438 /* INSN is either a function call or a millicode call.  It may have an
15439    unconditional jump in its delay slot.
15440
15441    CALL_DEST is the routine we are calling.  */
15442
15443 char *
15444 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
15445 {
15446   static char buf[256];
15447   if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
15448       && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
15449     {
15450       tree labelname;
15451       tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
15452
15453       if (no_previous_def (funname))
15454         {
15455           int line_number = 0;
15456           rtx label_rtx = gen_label_rtx ();
15457           char *label_buf, temp_buf[256];
15458           ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
15459                                        CODE_LABEL_NUMBER (label_rtx));
15460           label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
15461           labelname = get_identifier (label_buf);
15462           for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
15463           if (insn)
15464             line_number = NOTE_LINE_NUMBER (insn);
15465           add_compiler_branch_island (labelname, funname, line_number);
15466         }
15467       else
15468         labelname = get_prev_label (funname);
15469
15470       /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
15471          instruction will reach 'foo', otherwise link as 'bl L42'".
15472          "L42" should be a 'branch island', that will do a far jump to
15473          'foo'.  Branch islands are generated in
15474          macho_branch_islands().  */
15475       sprintf (buf, "jbsr %%z%d,%.246s",
15476                dest_operand_number, IDENTIFIER_POINTER (labelname));
15477     }
15478   else
15479     sprintf (buf, "bl %%z%d", dest_operand_number);
15480   return buf;
15481 }
15482
15483 #endif /* TARGET_MACHO */
15484
15485 /* Generate PIC and indirect symbol stubs.  */
15486
15487 void
15488 machopic_output_stub (FILE *file, const char *symb, const char *stub)
15489 {
15490   unsigned int length;
15491   char *symbol_name, *lazy_ptr_name;
15492   char *local_label_0;
15493   static int label = 0;
15494
15495   /* Lose our funky encoding stuff so it doesn't contaminate the stub.  */
15496   symb = (*targetm.strip_name_encoding) (symb);
15497
15498
15499   length = strlen (symb);
15500   symbol_name = alloca (length + 32);
15501   GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
15502
15503   lazy_ptr_name = alloca (length + 32);
15504   GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
15505
15506   if (flag_pic == 2)
15507     machopic_picsymbol_stub1_section ();
15508   else
15509     machopic_symbol_stub1_section ();
15510   fprintf (file, "\t.align 2\n");
15511
15512   fprintf (file, "%s:\n", stub);
15513   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15514
15515   if (flag_pic == 2)
15516     {
15517       label++;
15518       local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
15519       sprintf (local_label_0, "\"L%011d$spb\"", label);
15520
15521       fprintf (file, "\tmflr r0\n");
15522       fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
15523       fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
15524       fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
15525                lazy_ptr_name, local_label_0);
15526       fprintf (file, "\tmtlr r0\n");
15527       fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
15528                lazy_ptr_name, local_label_0);
15529       fprintf (file, "\tmtctr r12\n");
15530       fprintf (file, "\tbctr\n");
15531     }
15532   else
15533    {
15534      fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
15535      fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
15536      fprintf (file, "\tmtctr r12\n");
15537      fprintf (file, "\tbctr\n");
15538    }
15539
15540   machopic_lazy_symbol_ptr_section ();
15541   fprintf (file, "%s:\n", lazy_ptr_name);
15542   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15543   fprintf (file, "\t.long dyld_stub_binding_helper\n");
15544 }
15545
15546 /* Legitimize PIC addresses.  If the address is already
15547    position-independent, we return ORIG.  Newly generated
15548    position-independent addresses go into a reg.  This is REG if non
15549    zero, otherwise we allocate register(s) as necessary.  */
15550
15551 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
15552
15553 rtx
15554 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
15555                                         rtx reg)
15556 {
15557   rtx base, offset;
15558
15559   if (reg == NULL && ! reload_in_progress && ! reload_completed)
15560     reg = gen_reg_rtx (Pmode);
15561
15562   if (GET_CODE (orig) == CONST)
15563     {
15564       if (GET_CODE (XEXP (orig, 0)) == PLUS
15565           && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
15566         return orig;
15567
15568       if (GET_CODE (XEXP (orig, 0)) == PLUS)
15569         {
15570           /* Use a different reg for the intermediate value, as
15571              it will be marked UNCHANGING.  */
15572           rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
15573
15574           base =
15575             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
15576                                                     Pmode, reg_temp);
15577           offset =
15578             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
15579                                                     Pmode, reg);
15580         }
15581       else
15582         abort ();
15583
15584       if (GET_CODE (offset) == CONST_INT)
15585         {
15586           if (SMALL_INT (offset))
15587             return plus_constant (base, INTVAL (offset));
15588           else if (! reload_in_progress && ! reload_completed)
15589             offset = force_reg (Pmode, offset);
15590           else
15591             {
15592               rtx mem = force_const_mem (Pmode, orig);
15593               return machopic_legitimize_pic_address (mem, Pmode, reg);
15594             }
15595         }
15596       return gen_rtx_PLUS (Pmode, base, offset);
15597     }
15598
15599   /* Fall back on generic machopic code.  */
15600   return machopic_legitimize_pic_address (orig, mode, reg);
15601 }
15602
15603 /* This is just a placeholder to make linking work without having to
15604    add this to the generic Darwin EXTRA_SECTIONS.  If -mcall-aix is
15605    ever needed for Darwin (not too likely!) this would have to get a
15606    real definition.  */
15607
15608 void
15609 toc_section (void)
15610 {
15611 }
15612
15613 #endif /* TARGET_MACHO */
15614
15615 #if TARGET_ELF
15616 static unsigned int
15617 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15618 {
15619   return default_section_type_flags_1 (decl, name, reloc,
15620                                        flag_pic || DEFAULT_ABI == ABI_AIX);
15621 }
15622
15623 /* Record an element in the table of global constructors.  SYMBOL is
15624    a SYMBOL_REF of the function to be called; PRIORITY is a number
15625    between 0 and MAX_INIT_PRIORITY.
15626
15627    This differs from default_named_section_asm_out_constructor in
15628    that we have special handling for -mrelocatable.  */
15629
15630 static void
15631 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15632 {
15633   const char *section = ".ctors";
15634   char buf[16];
15635
15636   if (priority != DEFAULT_INIT_PRIORITY)
15637     {
15638       sprintf (buf, ".ctors.%.5u",
15639                /* Invert the numbering so the linker puts us in the proper
15640                   order; constructors are run from right to left, and the
15641                   linker sorts in increasing order.  */
15642                MAX_INIT_PRIORITY - priority);
15643       section = buf;
15644     }
15645
15646   named_section_flags (section, SECTION_WRITE);
15647   assemble_align (POINTER_SIZE);
15648
15649   if (TARGET_RELOCATABLE)
15650     {
15651       fputs ("\t.long (", asm_out_file);
15652       output_addr_const (asm_out_file, symbol);
15653       fputs (")@fixup\n", asm_out_file);
15654     }
15655   else
15656     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15657 }
15658
15659 static void
15660 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15661 {
15662   const char *section = ".dtors";
15663   char buf[16];
15664
15665   if (priority != DEFAULT_INIT_PRIORITY)
15666     {
15667       sprintf (buf, ".dtors.%.5u",
15668                /* Invert the numbering so the linker puts us in the proper
15669                   order; constructors are run from right to left, and the
15670                   linker sorts in increasing order.  */
15671                MAX_INIT_PRIORITY - priority);
15672       section = buf;
15673     }
15674
15675   named_section_flags (section, SECTION_WRITE);
15676   assemble_align (POINTER_SIZE);
15677
15678   if (TARGET_RELOCATABLE)
15679     {
15680       fputs ("\t.long (", asm_out_file);
15681       output_addr_const (asm_out_file, symbol);
15682       fputs (")@fixup\n", asm_out_file);
15683     }
15684   else
15685     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15686 }
15687
15688 void
15689 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15690 {
15691   if (TARGET_64BIT)
15692     {
15693       fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15694       ASM_OUTPUT_LABEL (file, name);
15695       fputs (DOUBLE_INT_ASM_OP, file);
15696       putc ('.', file);
15697       assemble_name (file, name);
15698       fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15699       assemble_name (file, name);
15700       fputs (",24\n\t.type\t.", file);
15701       assemble_name (file, name);
15702       fputs (",@function\n", file);
15703       if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15704         {
15705           fputs ("\t.globl\t.", file);
15706           assemble_name (file, name);
15707           putc ('\n', file);
15708         }
15709       ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15710       putc ('.', file);
15711       ASM_OUTPUT_LABEL (file, name);
15712       return;
15713     }
15714
15715   if (TARGET_RELOCATABLE
15716       && (get_pool_size () != 0 || current_function_profile)
15717       && uses_TOC ())
15718     {
15719       char buf[256];
15720
15721       (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15722
15723       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15724       fprintf (file, "\t.long ");
15725       assemble_name (file, buf);
15726       putc ('-', file);
15727       ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15728       assemble_name (file, buf);
15729       putc ('\n', file);
15730     }
15731
15732   ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15733   ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15734
15735   if (DEFAULT_ABI == ABI_AIX)
15736     {
15737       const char *desc_name, *orig_name;
15738
15739       orig_name = (*targetm.strip_name_encoding) (name);
15740       desc_name = orig_name;
15741       while (*desc_name == '.')
15742         desc_name++;
15743
15744       if (TREE_PUBLIC (decl))
15745         fprintf (file, "\t.globl %s\n", desc_name);
15746
15747       fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15748       fprintf (file, "%s:\n", desc_name);
15749       fprintf (file, "\t.long %s\n", orig_name);
15750       fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15751       if (DEFAULT_ABI == ABI_AIX)
15752         fputs ("\t.long 0\n", file);
15753       fprintf (file, "\t.previous\n");
15754     }
15755   ASM_OUTPUT_LABEL (file, name);
15756 }
15757 #endif
15758
15759 #if TARGET_XCOFF
15760 static void
15761 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15762 {
15763   fputs (GLOBAL_ASM_OP, stream);
15764   RS6000_OUTPUT_BASENAME (stream, name);
15765   putc ('\n', stream);
15766 }
15767
15768 static void
15769 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15770 {
15771   int smclass;
15772   static const char * const suffix[3] = { "PR", "RO", "RW" };
15773
15774   if (flags & SECTION_CODE)
15775     smclass = 0;
15776   else if (flags & SECTION_WRITE)
15777     smclass = 2;
15778   else
15779     smclass = 1;
15780
15781   fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15782            (flags & SECTION_CODE) ? "." : "",
15783            name, suffix[smclass], flags & SECTION_ENTSIZE);
15784 }
15785
15786 static void
15787 rs6000_xcoff_select_section (tree decl, int reloc,
15788                             unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15789 {
15790   if (decl_readonly_section_1 (decl, reloc, 1))
15791     {
15792       if (TREE_PUBLIC (decl))
15793         read_only_data_section ();
15794       else
15795         read_only_private_data_section ();
15796     }
15797   else
15798     {
15799       if (TREE_PUBLIC (decl))
15800         data_section ();
15801       else
15802         private_data_section ();
15803     }
15804 }
15805
15806 static void
15807 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15808 {
15809   const char *name;
15810
15811   /* Use select_section for private and uninitialized data.  */
15812   if (!TREE_PUBLIC (decl)
15813       || DECL_COMMON (decl)
15814       || DECL_INITIAL (decl) == NULL_TREE
15815       || DECL_INITIAL (decl) == error_mark_node
15816       || (flag_zero_initialized_in_bss
15817           && initializer_zerop (DECL_INITIAL (decl))))
15818     return;
15819
15820   name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15821   name = (*targetm.strip_name_encoding) (name);
15822   DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15823 }
15824
15825 /* Select section for constant in constant pool.
15826
15827    On RS/6000, all constants are in the private read-only data area.
15828    However, if this is being placed in the TOC it must be output as a
15829    toc entry.  */
15830
15831 static void
15832 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15833                                 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15834 {
15835   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15836     toc_section ();
15837   else
15838     read_only_private_data_section ();
15839 }
15840
15841 /* Remove any trailing [DS] or the like from the symbol name.  */
15842
15843 static const char *
15844 rs6000_xcoff_strip_name_encoding (const char *name)
15845 {
15846   size_t len;
15847   if (*name == '*')
15848     name++;
15849   len = strlen (name);
15850   if (name[len - 1] == ']')
15851     return ggc_alloc_string (name, len - 4);
15852   else
15853     return name;
15854 }
15855
15856 /* Section attributes.  AIX is always PIC.  */
15857
15858 static unsigned int
15859 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15860 {
15861   unsigned int align;
15862   unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15863
15864   /* Align to at least UNIT size.  */
15865   if (flags & SECTION_CODE)
15866     align = MIN_UNITS_PER_WORD;
15867   else
15868     /* Increase alignment of large objects if not already stricter.  */
15869     align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15870                  int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15871                  ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15872
15873   return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15874 }
15875
15876 /* Output at beginning of assembler file.
15877
15878    Initialize the section names for the RS/6000 at this point.
15879
15880    Specify filename, including full path, to assembler.
15881
15882    We want to go into the TOC section so at least one .toc will be emitted.
15883    Also, in order to output proper .bs/.es pairs, we need at least one static
15884    [RW] section emitted.
15885
15886    Finally, declare mcount when profiling to make the assembler happy.  */
15887
15888 static void
15889 rs6000_xcoff_file_start (void)
15890 {
15891   rs6000_gen_section_name (&xcoff_bss_section_name,
15892                            main_input_filename, ".bss_");
15893   rs6000_gen_section_name (&xcoff_private_data_section_name,
15894                            main_input_filename, ".rw_");
15895   rs6000_gen_section_name (&xcoff_read_only_section_name,
15896                            main_input_filename, ".ro_");
15897
15898   fputs ("\t.file\t", asm_out_file);
15899   output_quoted_string (asm_out_file, main_input_filename);
15900   fputc ('\n', asm_out_file);
15901   toc_section ();
15902   if (write_symbols != NO_DEBUG)
15903     private_data_section ();
15904   text_section ();
15905   if (profile_flag)
15906     fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15907   rs6000_file_start ();
15908 }
15909
15910 /* Output at end of assembler file.
15911    On the RS/6000, referencing data should automatically pull in text.  */
15912
15913 static void
15914 rs6000_xcoff_file_end (void)
15915 {
15916   text_section ();
15917   fputs ("_section_.text:\n", asm_out_file);
15918   data_section ();
15919   fputs (TARGET_32BIT
15920          ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15921          asm_out_file);
15922 }
15923 #endif /* TARGET_XCOFF */
15924
15925 #if TARGET_MACHO
15926 /* Cross-module name binding.  Darwin does not support overriding
15927    functions at dynamic-link time.  */
15928
15929 static bool
15930 rs6000_binds_local_p (tree decl)
15931 {
15932   return default_binds_local_p_1 (decl, 0);
15933 }
15934 #endif
15935
15936 /* Compute a (partial) cost for rtx X.  Return true if the complete
15937    cost has been computed, and false if subexpressions should be
15938    scanned.  In either case, *TOTAL contains the cost result.  */
15939
15940 static bool
15941 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15942                   int *total)
15943 {
15944   switch (code)
15945     {
15946       /* On the RS/6000, if it is valid in the insn, it is free.
15947          So this always returns 0.  */
15948     case CONST_INT:
15949     case CONST:
15950     case LABEL_REF:
15951     case SYMBOL_REF:
15952     case CONST_DOUBLE:
15953     case HIGH:
15954       *total = 0;
15955       return true;
15956
15957     case PLUS:
15958       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15959                  && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15960                                                + 0x8000) >= 0x10000)
15961                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15962                 ? COSTS_N_INSNS (2)
15963                 : COSTS_N_INSNS (1));
15964       return true;
15965
15966     case AND:
15967     case IOR:
15968     case XOR:
15969       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15970                  && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15971                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15972                 ? COSTS_N_INSNS (2)
15973                 : COSTS_N_INSNS (1));
15974       return true;
15975
15976     case MULT:
15977       if (optimize_size)
15978         {
15979           *total = COSTS_N_INSNS (2);
15980           return true;
15981         }
15982       switch (rs6000_cpu)
15983         {
15984         case PROCESSOR_RIOS1:
15985         case PROCESSOR_PPC405:
15986           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15987                     ? COSTS_N_INSNS (5)
15988                     : (INTVAL (XEXP (x, 1)) >= -256
15989                        && INTVAL (XEXP (x, 1)) <= 255)
15990                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15991           return true;
15992
15993         case PROCESSOR_PPC440:
15994           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15995                     ? COSTS_N_INSNS (3)
15996                     : COSTS_N_INSNS (2));
15997           return true;
15998
15999         case PROCESSOR_RS64A:
16000           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
16001                     ? GET_MODE (XEXP (x, 1)) != DImode
16002                     ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
16003                     : (INTVAL (XEXP (x, 1)) >= -256
16004                        && INTVAL (XEXP (x, 1)) <= 255)
16005                     ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
16006           return true;
16007
16008         case PROCESSOR_RIOS2:
16009         case PROCESSOR_MPCCORE:
16010         case PROCESSOR_PPC604e:
16011           *total = COSTS_N_INSNS (2);
16012           return true;
16013
16014         case PROCESSOR_PPC601:
16015           *total = COSTS_N_INSNS (5);
16016           return true;
16017
16018         case PROCESSOR_PPC603:
16019         case PROCESSOR_PPC7400:
16020         case PROCESSOR_PPC750:
16021           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
16022                     ? COSTS_N_INSNS (5)
16023                     : (INTVAL (XEXP (x, 1)) >= -256
16024                        && INTVAL (XEXP (x, 1)) <= 255)
16025                     ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
16026           return true;
16027
16028         case PROCESSOR_PPC7450:
16029           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
16030                     ? COSTS_N_INSNS (4)
16031                     : COSTS_N_INSNS (3));
16032           return true;
16033
16034         case PROCESSOR_PPC403:
16035         case PROCESSOR_PPC604:
16036         case PROCESSOR_PPC8540:
16037           *total = COSTS_N_INSNS (4);
16038           return true;
16039
16040         case PROCESSOR_PPC620:
16041         case PROCESSOR_PPC630:
16042           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
16043                     ? GET_MODE (XEXP (x, 1)) != DImode
16044                     ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
16045                     : (INTVAL (XEXP (x, 1)) >= -256
16046                        && INTVAL (XEXP (x, 1)) <= 255)
16047                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
16048           return true;
16049
16050         case PROCESSOR_POWER4:
16051         case PROCESSOR_POWER5:
16052           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
16053                     ? GET_MODE (XEXP (x, 1)) != DImode
16054                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
16055                     : COSTS_N_INSNS (2));
16056           return true;
16057
16058         default:
16059           abort ();
16060         }
16061
16062     case DIV:
16063     case MOD:
16064       if (GET_CODE (XEXP (x, 1)) == CONST_INT
16065           && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
16066         {
16067           *total = COSTS_N_INSNS (2);
16068           return true;
16069         }
16070       /* FALLTHRU */
16071
16072     case UDIV:
16073     case UMOD:
16074       switch (rs6000_cpu)
16075         {
16076         case PROCESSOR_RIOS1:
16077           *total = COSTS_N_INSNS (19);
16078           return true;
16079
16080         case PROCESSOR_RIOS2:
16081           *total = COSTS_N_INSNS (13);
16082           return true;
16083
16084         case PROCESSOR_RS64A:
16085           *total = (GET_MODE (XEXP (x, 1)) != DImode
16086                     ? COSTS_N_INSNS (65)
16087                     : COSTS_N_INSNS (67));
16088           return true;
16089
16090         case PROCESSOR_MPCCORE:
16091           *total = COSTS_N_INSNS (6);
16092           return true;
16093
16094         case PROCESSOR_PPC403:
16095           *total = COSTS_N_INSNS (33);
16096           return true;
16097
16098         case PROCESSOR_PPC405:
16099           *total = COSTS_N_INSNS (35);
16100           return true;
16101
16102         case PROCESSOR_PPC440:
16103           *total = COSTS_N_INSNS (34);
16104           return true;
16105
16106         case PROCESSOR_PPC601:
16107           *total = COSTS_N_INSNS (36);
16108           return true;
16109
16110         case PROCESSOR_PPC603:
16111           *total = COSTS_N_INSNS (37);
16112           return true;
16113
16114         case PROCESSOR_PPC604:
16115         case PROCESSOR_PPC604e:
16116           *total = COSTS_N_INSNS (20);
16117           return true;
16118
16119         case PROCESSOR_PPC620:
16120         case PROCESSOR_PPC630:
16121           *total = (GET_MODE (XEXP (x, 1)) != DImode
16122                     ? COSTS_N_INSNS (21)
16123                     : COSTS_N_INSNS (37));
16124           return true;
16125
16126         case PROCESSOR_PPC750:
16127         case PROCESSOR_PPC8540:
16128         case PROCESSOR_PPC7400:
16129           *total = COSTS_N_INSNS (19);
16130           return true;
16131
16132         case PROCESSOR_PPC7450:
16133           *total = COSTS_N_INSNS (23);
16134           return true;
16135
16136         case PROCESSOR_POWER4:
16137         case PROCESSOR_POWER5:
16138           *total = (GET_MODE (XEXP (x, 1)) != DImode
16139                     ? COSTS_N_INSNS (18)
16140                     : COSTS_N_INSNS (34));
16141           return true;
16142
16143         default:
16144           abort ();
16145         }
16146
16147     case FFS:
16148       *total = COSTS_N_INSNS (4);
16149       return true;
16150
16151     case MEM:
16152       /* MEM should be slightly more expensive than (plus (reg) (const)).  */
16153       *total = 5;
16154       return true;
16155
16156     default:
16157       return false;
16158     }
16159 }
16160
16161 /* A C expression returning the cost of moving data from a register of class
16162    CLASS1 to one of CLASS2.  */
16163
16164 int
16165 rs6000_register_move_cost (enum machine_mode mode,
16166                            enum reg_class from, enum reg_class to)
16167 {
16168   /*  Moves from/to GENERAL_REGS.  */
16169   if (reg_classes_intersect_p (to, GENERAL_REGS)
16170       || reg_classes_intersect_p (from, GENERAL_REGS))
16171     {
16172       if (! reg_classes_intersect_p (to, GENERAL_REGS))
16173         from = to;
16174
16175       if (from == FLOAT_REGS || from == ALTIVEC_REGS)
16176         return (rs6000_memory_move_cost (mode, from, 0)
16177                 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
16178
16179 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift....  */
16180       else if (from == CR_REGS)
16181         return 4;
16182
16183       else
16184 /* A move will cost one instruction per GPR moved.  */
16185         return 2 * HARD_REGNO_NREGS (0, mode);
16186     }
16187
16188 /* Moving between two similar registers is just one instruction.  */
16189   else if (reg_classes_intersect_p (to, from))
16190     return mode == TFmode ? 4 : 2;
16191
16192 /* Everything else has to go through GENERAL_REGS.  */
16193   else
16194     return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
16195             + rs6000_register_move_cost (mode, from, GENERAL_REGS));
16196 }
16197
16198 /* A C expressions returning the cost of moving data of MODE from a register to
16199    or from memory.  */
16200
16201 int
16202 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
16203                          int in ATTRIBUTE_UNUSED)
16204 {
16205   if (reg_classes_intersect_p (class, GENERAL_REGS))
16206     return 4 * HARD_REGNO_NREGS (0, mode);
16207   else if (reg_classes_intersect_p (class, FLOAT_REGS))
16208     return 4 * HARD_REGNO_NREGS (32, mode);
16209   else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
16210     return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
16211   else
16212     return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
16213 }
16214
16215 /* Return an RTX representing where to find the function value of a
16216    function returning MODE.  */
16217 static rtx
16218 rs6000_complex_function_value (enum machine_mode mode)
16219 {
16220   unsigned int regno;
16221   rtx r1, r2;
16222   enum machine_mode inner = GET_MODE_INNER (mode);
16223   unsigned int inner_bytes = GET_MODE_SIZE (inner);
16224
16225   if (FLOAT_MODE_P (mode))
16226     regno = FP_ARG_RETURN;
16227   else
16228     {
16229       regno = GP_ARG_RETURN;
16230
16231       /* 32-bit is OK since it'll go in r3/r4.  */
16232       if (TARGET_32BIT && inner_bytes >= 4)
16233         return gen_rtx_REG (mode, regno);
16234     }
16235
16236   if (inner_bytes >= 8)
16237     return gen_rtx_REG (mode, regno);
16238
16239   r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
16240                           const0_rtx);
16241   r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
16242                           GEN_INT (inner_bytes));
16243   return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
16244 }
16245
16246 /* Define how to find the value returned by a function.
16247    VALTYPE is the data type of the value (as a tree).
16248    If the precise function being called is known, FUNC is its FUNCTION_DECL;
16249    otherwise, FUNC is 0.
16250
16251    On the SPE, both FPs and vectors are returned in r3.
16252
16253    On RS/6000 an integer value is in r3 and a floating-point value is in
16254    fp1, unless -msoft-float.  */
16255
16256 rtx
16257 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
16258 {
16259   enum machine_mode mode;
16260   unsigned int regno;
16261
16262   if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
16263     {
16264       /* Long long return value need be split in -mpowerpc64, 32bit ABI.  */
16265       return gen_rtx_PARALLEL (DImode,
16266         gen_rtvec (2,
16267                    gen_rtx_EXPR_LIST (VOIDmode,
16268                                       gen_rtx_REG (SImode, GP_ARG_RETURN),
16269                                       const0_rtx),
16270                    gen_rtx_EXPR_LIST (VOIDmode,
16271                                       gen_rtx_REG (SImode,
16272                                                    GP_ARG_RETURN + 1),
16273                                       GEN_INT (4))));
16274     }
16275
16276   if ((INTEGRAL_TYPE_P (valtype)
16277        && TYPE_PRECISION (valtype) < BITS_PER_WORD)
16278       || POINTER_TYPE_P (valtype))
16279     mode = TARGET_32BIT ? SImode : DImode;
16280   else
16281     mode = TYPE_MODE (valtype);
16282
16283   if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
16284     regno = FP_ARG_RETURN;
16285   else if (TREE_CODE (valtype) == COMPLEX_TYPE
16286            && TARGET_HARD_FLOAT
16287            && targetm.calls.split_complex_arg)
16288     return rs6000_complex_function_value (mode);
16289   else if (TREE_CODE (valtype) == VECTOR_TYPE
16290            && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
16291     regno = ALTIVEC_ARG_RETURN;
16292   else
16293     regno = GP_ARG_RETURN;
16294
16295   return gen_rtx_REG (mode, regno);
16296 }
16297
16298 /* Define how to find the value returned by a library function
16299    assuming the value has mode MODE.  */
16300 rtx
16301 rs6000_libcall_value (enum machine_mode mode)
16302 {
16303   unsigned int regno;
16304
16305   if (GET_MODE_CLASS (mode) == MODE_FLOAT
16306            && TARGET_HARD_FLOAT && TARGET_FPRS)
16307     regno = FP_ARG_RETURN;
16308   else if (ALTIVEC_VECTOR_MODE (mode)
16309            && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
16310     regno = ALTIVEC_ARG_RETURN;
16311   else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
16312     return rs6000_complex_function_value (mode);
16313   else
16314     regno = GP_ARG_RETURN;
16315
16316   return gen_rtx_REG (mode, regno);
16317 }
16318
16319 /* Define the offset between two registers, FROM to be eliminated and its
16320    replacement TO, at the start of a routine.  */
16321 HOST_WIDE_INT
16322 rs6000_initial_elimination_offset (int from, int to)
16323 {
16324   rs6000_stack_t *info = rs6000_stack_info ();
16325   HOST_WIDE_INT offset;
16326
16327   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16328     offset = info->push_p ? 0 : -info->total_size;
16329   else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
16330     offset = info->total_size;
16331   else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16332     offset = info->push_p ? info->total_size : 0;
16333   else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
16334     offset = 0;
16335   else
16336     abort ();
16337
16338   return offset;
16339 }
16340
16341 /* Return true if TYPE is of type __ev64_opaque__.  */
16342
16343 static bool
16344 is_ev64_opaque_type (tree type)
16345 {
16346   return (TARGET_SPE
16347           && (type == opaque_V2SI_type_node
16348               || type == opaque_V2SF_type_node
16349               || type == opaque_p_V2SI_type_node));
16350 }
16351
16352 static rtx
16353 rs6000_dwarf_register_span (rtx reg)
16354 {
16355   unsigned regno;
16356
16357   if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
16358     return NULL_RTX;
16359
16360   regno = REGNO (reg);
16361
16362   /* The duality of the SPE register size wreaks all kinds of havoc.
16363      This is a way of distinguishing r0 in 32-bits from r0 in
16364      64-bits.  */
16365   return
16366     gen_rtx_PARALLEL (VOIDmode,
16367                       BYTES_BIG_ENDIAN
16368                       ? gen_rtvec (2,
16369                                    gen_rtx_REG (SImode, regno + 1200),
16370                                    gen_rtx_REG (SImode, regno))
16371                       : gen_rtvec (2,
16372                                    gen_rtx_REG (SImode, regno),
16373                                    gen_rtx_REG (SImode, regno + 1200)));
16374 }
16375
16376 /* Map internal gcc register numbers to DWARF2 register numbers.  */
16377
16378 unsigned int
16379 rs6000_dbx_register_number (unsigned int regno)
16380 {
16381   if (regno <= 63 || write_symbols != DWARF2_DEBUG)
16382     return regno;
16383   if (regno == MQ_REGNO)
16384     return 100;
16385   if (regno == LINK_REGISTER_REGNUM)
16386     return 108;
16387   if (regno == COUNT_REGISTER_REGNUM)
16388     return 109;
16389   if (CR_REGNO_P (regno))
16390     return regno - CR0_REGNO + 86;
16391   if (regno == XER_REGNO)
16392     return 101;
16393   if (ALTIVEC_REGNO_P (regno))
16394     return regno - FIRST_ALTIVEC_REGNO + 1124;
16395   if (regno == VRSAVE_REGNO)
16396     return 356;
16397   if (regno == VSCR_REGNO)
16398     return 67;
16399   if (regno == SPE_ACC_REGNO)
16400     return 99;
16401   if (regno == SPEFSCR_REGNO)
16402     return 612;
16403   /* SPE high reg number.  We get these values of regno from
16404      rs6000_dwarf_register_span.  */
16405   if (regno >= 1200 && regno < 1232)
16406     return regno;
16407
16408   abort ();
16409 }
16410
16411 #include "gt-rs6000.h"