2015-05-18 Steven G. Kargl <kargl@gcc.gnu.org>
[official-gcc.git] / gcc / lra-constraints.c
blobc8de418144e1a7b3a911e33634833b48b240340e
1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
107 #undef REG_OK_STRICT
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "tm.h"
113 #include "hard-reg-set.h"
114 #include "rtl.h"
115 #include "tm_p.h"
116 #include "regs.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
119 #include "recog.h"
120 #include "output.h"
121 #include "addresses.h"
122 #include "target.h"
123 #include "hashtab.h"
124 #include "hash-set.h"
125 #include "vec.h"
126 #include "machmode.h"
127 #include "input.h"
128 #include "function.h"
129 #include "symtab.h"
130 #include "flags.h"
131 #include "statistics.h"
132 #include "double-int.h"
133 #include "real.h"
134 #include "fixed-value.h"
135 #include "alias.h"
136 #include "wide-int.h"
137 #include "inchash.h"
138 #include "tree.h"
139 #include "expmed.h"
140 #include "dojump.h"
141 #include "explow.h"
142 #include "calls.h"
143 #include "emit-rtl.h"
144 #include "varasm.h"
145 #include "stmt.h"
146 #include "expr.h"
147 #include "predict.h"
148 #include "dominance.h"
149 #include "cfg.h"
150 #include "cfgrtl.h"
151 #include "basic-block.h"
152 #include "except.h"
153 #include "optabs.h"
154 #include "df.h"
155 #include "ira.h"
156 #include "rtl-error.h"
157 #include "params.h"
158 #include "lra-int.h"
160 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
161 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
162 reload insns. */
163 static int bb_reload_num;
165 /* The current insn being processed and corresponding its single set
166 (NULL otherwise), its data (basic block, the insn data, the insn
167 static data, and the mode of each operand). */
168 static rtx_insn *curr_insn;
169 static rtx curr_insn_set;
170 static basic_block curr_bb;
171 static lra_insn_recog_data_t curr_id;
172 static struct lra_static_insn_data *curr_static_id;
173 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
174 /* Mode of the register substituted by its equivalence with VOIDmode
175 (e.g. constant) and whose subreg is given operand of the current
176 insn. VOIDmode in all other cases. */
177 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
181 /* Start numbers for new registers and insns at the current constraints
182 pass start. */
183 static int new_regno_start;
184 static int new_insn_uid_start;
186 /* If LOC is nonnull, strip any outer subreg from it. */
187 static inline rtx *
188 strip_subreg (rtx *loc)
190 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
193 /* Return hard regno of REGNO or if it is was not assigned to a hard
194 register, use a hard register from its allocno class. */
195 static int
196 get_try_hard_regno (int regno)
198 int hard_regno;
199 enum reg_class rclass;
201 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
202 hard_regno = lra_get_regno_hard_regno (regno);
203 if (hard_regno >= 0)
204 return hard_regno;
205 rclass = lra_get_allocno_class (regno);
206 if (rclass == NO_REGS)
207 return -1;
208 return ira_class_hard_regs[rclass][0];
211 /* Return final hard regno (plus offset) which will be after
212 elimination. We do this for matching constraints because the final
213 hard regno could have a different class. */
214 static int
215 get_final_hard_regno (int hard_regno, int offset)
217 if (hard_regno < 0)
218 return hard_regno;
219 hard_regno = lra_get_elimination_hard_regno (hard_regno);
220 return hard_regno + offset;
223 /* Return hard regno of X after removing subreg and making
224 elimination. If X is not a register or subreg of register, return
225 -1. For pseudo use its assignment. */
226 static int
227 get_hard_regno (rtx x)
229 rtx reg;
230 int offset, hard_regno;
232 reg = x;
233 if (GET_CODE (x) == SUBREG)
234 reg = SUBREG_REG (x);
235 if (! REG_P (reg))
236 return -1;
237 if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
238 hard_regno = lra_get_regno_hard_regno (hard_regno);
239 if (hard_regno < 0)
240 return -1;
241 offset = 0;
242 if (GET_CODE (x) == SUBREG)
243 offset += subreg_regno_offset (hard_regno, GET_MODE (reg),
244 SUBREG_BYTE (x), GET_MODE (x));
245 return get_final_hard_regno (hard_regno, offset);
248 /* If REGNO is a hard register or has been allocated a hard register,
249 return the class of that register. If REGNO is a reload pseudo
250 created by the current constraints pass, return its allocno class.
251 Return NO_REGS otherwise. */
252 static enum reg_class
253 get_reg_class (int regno)
255 int hard_regno;
257 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
258 hard_regno = lra_get_regno_hard_regno (regno);
259 if (hard_regno >= 0)
261 hard_regno = get_final_hard_regno (hard_regno, 0);
262 return REGNO_REG_CLASS (hard_regno);
264 if (regno >= new_regno_start)
265 return lra_get_allocno_class (regno);
266 return NO_REGS;
269 /* Return true if REG satisfies (or will satisfy) reg class constraint
270 CL. Use elimination first if REG is a hard register. If REG is a
271 reload pseudo created by this constraints pass, assume that it will
272 be allocated a hard register from its allocno class, but allow that
273 class to be narrowed to CL if it is currently a superset of CL.
275 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
276 REGNO (reg), or NO_REGS if no change in its class was needed. */
277 static bool
278 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
280 enum reg_class rclass, common_class;
281 machine_mode reg_mode;
282 int class_size, hard_regno, nregs, i, j;
283 int regno = REGNO (reg);
285 if (new_class != NULL)
286 *new_class = NO_REGS;
287 if (regno < FIRST_PSEUDO_REGISTER)
289 rtx final_reg = reg;
290 rtx *final_loc = &final_reg;
292 lra_eliminate_reg_if_possible (final_loc);
293 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
295 reg_mode = GET_MODE (reg);
296 rclass = get_reg_class (regno);
297 if (regno < new_regno_start
298 /* Do not allow the constraints for reload instructions to
299 influence the classes of new pseudos. These reloads are
300 typically moves that have many alternatives, and restricting
301 reload pseudos for one alternative may lead to situations
302 where other reload pseudos are no longer allocatable. */
303 || (INSN_UID (curr_insn) >= new_insn_uid_start
304 && curr_insn_set != NULL
305 && ((OBJECT_P (SET_SRC (curr_insn_set))
306 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
307 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
308 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
309 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
310 /* When we don't know what class will be used finally for reload
311 pseudos, we use ALL_REGS. */
312 return ((regno >= new_regno_start && rclass == ALL_REGS)
313 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
314 && ! hard_reg_set_subset_p (reg_class_contents[cl],
315 lra_no_alloc_regs)));
316 else
318 common_class = ira_reg_class_subset[rclass][cl];
319 if (new_class != NULL)
320 *new_class = common_class;
321 if (hard_reg_set_subset_p (reg_class_contents[common_class],
322 lra_no_alloc_regs))
323 return false;
324 /* Check that there are enough allocatable regs. */
325 class_size = ira_class_hard_regs_num[common_class];
326 for (i = 0; i < class_size; i++)
328 hard_regno = ira_class_hard_regs[common_class][i];
329 nregs = hard_regno_nregs[hard_regno][reg_mode];
330 if (nregs == 1)
331 return true;
332 for (j = 0; j < nregs; j++)
333 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
334 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
335 hard_regno + j))
336 break;
337 if (j >= nregs)
338 return true;
340 return false;
344 /* Return true if REGNO satisfies a memory constraint. */
345 static bool
346 in_mem_p (int regno)
348 return get_reg_class (regno) == NO_REGS;
351 /* Return 1 if ADDR is a valid memory address for mode MODE in address
352 space AS, and check that each pseudo has the proper kind of hard
353 reg. */
354 static int
355 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
356 rtx addr, addr_space_t as)
358 #ifdef GO_IF_LEGITIMATE_ADDRESS
359 lra_assert (ADDR_SPACE_GENERIC_P (as));
360 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
361 return 0;
363 win:
364 return 1;
365 #else
366 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
367 #endif
370 namespace {
371 /* Temporarily eliminates registers in an address (for the lifetime of
372 the object). */
373 class address_eliminator {
374 public:
375 address_eliminator (struct address_info *ad);
376 ~address_eliminator ();
378 private:
379 struct address_info *m_ad;
380 rtx *m_base_loc;
381 rtx m_base_reg;
382 rtx *m_index_loc;
383 rtx m_index_reg;
387 address_eliminator::address_eliminator (struct address_info *ad)
388 : m_ad (ad),
389 m_base_loc (strip_subreg (ad->base_term)),
390 m_base_reg (NULL_RTX),
391 m_index_loc (strip_subreg (ad->index_term)),
392 m_index_reg (NULL_RTX)
394 if (m_base_loc != NULL)
396 m_base_reg = *m_base_loc;
397 lra_eliminate_reg_if_possible (m_base_loc);
398 if (m_ad->base_term2 != NULL)
399 *m_ad->base_term2 = *m_ad->base_term;
401 if (m_index_loc != NULL)
403 m_index_reg = *m_index_loc;
404 lra_eliminate_reg_if_possible (m_index_loc);
408 address_eliminator::~address_eliminator ()
410 if (m_base_loc && *m_base_loc != m_base_reg)
412 *m_base_loc = m_base_reg;
413 if (m_ad->base_term2 != NULL)
414 *m_ad->base_term2 = *m_ad->base_term;
416 if (m_index_loc && *m_index_loc != m_index_reg)
417 *m_index_loc = m_index_reg;
420 /* Return true if the eliminated form of AD is a legitimate target address. */
421 static bool
422 valid_address_p (struct address_info *ad)
424 address_eliminator eliminator (ad);
425 return valid_address_p (ad->mode, *ad->outer, ad->as);
428 /* Return true if the eliminated form of memory reference OP satisfies
429 extra memory constraint CONSTRAINT. */
430 static bool
431 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
433 struct address_info ad;
435 decompose_mem_address (&ad, op);
436 address_eliminator eliminator (&ad);
437 return constraint_satisfied_p (op, constraint);
440 /* Return true if the eliminated form of address AD satisfies extra
441 address constraint CONSTRAINT. */
442 static bool
443 satisfies_address_constraint_p (struct address_info *ad,
444 enum constraint_num constraint)
446 address_eliminator eliminator (ad);
447 return constraint_satisfied_p (*ad->outer, constraint);
450 /* Return true if the eliminated form of address OP satisfies extra
451 address constraint CONSTRAINT. */
452 static bool
453 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
455 struct address_info ad;
457 decompose_lea_address (&ad, &op);
458 return satisfies_address_constraint_p (&ad, constraint);
461 /* Initiate equivalences for LRA. As we keep original equivalences
462 before any elimination, we need to make copies otherwise any change
463 in insns might change the equivalences. */
464 void
465 lra_init_equiv (void)
467 ira_expand_reg_equiv ();
468 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
470 rtx res;
472 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
473 ira_reg_equiv[i].memory = copy_rtx (res);
474 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
475 ira_reg_equiv[i].invariant = copy_rtx (res);
479 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
481 /* Update equivalence for REGNO. We need to this as the equivalence
482 might contain other pseudos which are changed by their
483 equivalences. */
484 static void
485 update_equiv (int regno)
487 rtx x;
489 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
490 ira_reg_equiv[regno].memory
491 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
492 NULL_RTX);
493 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
494 ira_reg_equiv[regno].invariant
495 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
496 NULL_RTX);
499 /* If we have decided to substitute X with another value, return that
500 value, otherwise return X. */
501 static rtx
502 get_equiv (rtx x)
504 int regno;
505 rtx res;
507 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
508 || ! ira_reg_equiv[regno].defined_p
509 || ! ira_reg_equiv[regno].profitable_p
510 || lra_get_regno_hard_regno (regno) >= 0)
511 return x;
512 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
514 if (targetm.cannot_substitute_mem_equiv_p (res))
515 return x;
516 return res;
518 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
519 return res;
520 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
521 return res;
522 gcc_unreachable ();
525 /* If we have decided to substitute X with the equivalent value,
526 return that value after elimination for INSN, otherwise return
527 X. */
528 static rtx
529 get_equiv_with_elimination (rtx x, rtx_insn *insn)
531 rtx res = get_equiv (x);
533 if (x == res || CONSTANT_P (res))
534 return res;
535 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
536 false, false, 0, true);
539 /* Set up curr_operand_mode. */
540 static void
541 init_curr_operand_mode (void)
543 int nop = curr_static_id->n_operands;
544 for (int i = 0; i < nop; i++)
546 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
547 if (mode == VOIDmode)
549 /* The .md mode for address operands is the mode of the
550 addressed value rather than the mode of the address itself. */
551 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
552 mode = Pmode;
553 else
554 mode = curr_static_id->operand[i].mode;
556 curr_operand_mode[i] = mode;
562 /* The page contains code to reuse input reloads. */
564 /* Structure describes input reload of the current insns. */
565 struct input_reload
567 /* Reloaded value. */
568 rtx input;
569 /* Reload pseudo used. */
570 rtx reg;
573 /* The number of elements in the following array. */
574 static int curr_insn_input_reloads_num;
575 /* Array containing info about input reloads. It is used to find the
576 same input reload and reuse the reload pseudo in this case. */
577 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
579 /* Initiate data concerning reuse of input reloads for the current
580 insn. */
581 static void
582 init_curr_insn_input_reloads (void)
584 curr_insn_input_reloads_num = 0;
587 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
588 created input reload pseudo (only if TYPE is not OP_OUT). Don't
589 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
590 wrapped up in SUBREG. The result pseudo is returned through
591 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
592 reused the already created input reload pseudo. Use TITLE to
593 describe new registers for debug purposes. */
594 static bool
595 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
596 enum reg_class rclass, bool in_subreg_p,
597 const char *title, rtx *result_reg)
599 int i, regno;
600 enum reg_class new_class;
602 if (type == OP_OUT)
604 *result_reg
605 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
606 return true;
608 /* Prevent reuse value of expression with side effects,
609 e.g. volatile memory. */
610 if (! side_effects_p (original))
611 for (i = 0; i < curr_insn_input_reloads_num; i++)
612 if (rtx_equal_p (curr_insn_input_reloads[i].input, original)
613 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
615 rtx reg = curr_insn_input_reloads[i].reg;
616 regno = REGNO (reg);
617 /* If input is equal to original and both are VOIDmode,
618 GET_MODE (reg) might be still different from mode.
619 Ensure we don't return *result_reg with wrong mode. */
620 if (GET_MODE (reg) != mode)
622 if (in_subreg_p)
623 continue;
624 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode))
625 continue;
626 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
627 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
628 continue;
630 *result_reg = reg;
631 if (lra_dump_file != NULL)
633 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
634 dump_value_slim (lra_dump_file, original, 1);
636 if (new_class != lra_get_allocno_class (regno))
637 lra_change_class (regno, new_class, ", change to", false);
638 if (lra_dump_file != NULL)
639 fprintf (lra_dump_file, "\n");
640 return false;
642 *result_reg = lra_create_new_reg (mode, original, rclass, title);
643 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
644 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
645 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
646 return true;
651 /* The page contains code to extract memory address parts. */
653 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
654 static inline bool
655 ok_for_index_p_nonstrict (rtx reg)
657 unsigned regno = REGNO (reg);
659 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
662 /* A version of regno_ok_for_base_p for use here, when all pseudos
663 should count as OK. Arguments as for regno_ok_for_base_p. */
664 static inline bool
665 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
666 enum rtx_code outer_code, enum rtx_code index_code)
668 unsigned regno = REGNO (reg);
670 if (regno >= FIRST_PSEUDO_REGISTER)
671 return true;
672 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
677 /* The page contains major code to choose the current insn alternative
678 and generate reloads for it. */
680 /* Return the offset from REGNO of the least significant register
681 in (reg:MODE REGNO).
683 This function is used to tell whether two registers satisfy
684 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
686 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
687 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
689 lra_constraint_offset (int regno, machine_mode mode)
691 lra_assert (regno < FIRST_PSEUDO_REGISTER);
692 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD
693 && SCALAR_INT_MODE_P (mode))
694 return hard_regno_nregs[regno][mode] - 1;
695 return 0;
698 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
699 if they are the same hard reg, and has special hacks for
700 auto-increment and auto-decrement. This is specifically intended for
701 process_alt_operands to use in determining whether two operands
702 match. X is the operand whose number is the lower of the two.
704 It is supposed that X is the output operand and Y is the input
705 operand. Y_HARD_REGNO is the final hard regno of register Y or
706 register in subreg Y as we know it now. Otherwise, it is a
707 negative value. */
708 static bool
709 operands_match_p (rtx x, rtx y, int y_hard_regno)
711 int i;
712 RTX_CODE code = GET_CODE (x);
713 const char *fmt;
715 if (x == y)
716 return true;
717 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
718 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
720 int j;
722 i = get_hard_regno (x);
723 if (i < 0)
724 goto slow;
726 if ((j = y_hard_regno) < 0)
727 goto slow;
729 i += lra_constraint_offset (i, GET_MODE (x));
730 j += lra_constraint_offset (j, GET_MODE (y));
732 return i == j;
735 /* If two operands must match, because they are really a single
736 operand of an assembler insn, then two post-increments are invalid
737 because the assembler insn would increment only once. On the
738 other hand, a post-increment matches ordinary indexing if the
739 post-increment is the output operand. */
740 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
741 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
743 /* Two pre-increments are invalid because the assembler insn would
744 increment only once. On the other hand, a pre-increment matches
745 ordinary indexing if the pre-increment is the input operand. */
746 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
747 || GET_CODE (y) == PRE_MODIFY)
748 return operands_match_p (x, XEXP (y, 0), -1);
750 slow:
752 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
753 && x == SUBREG_REG (y))
754 return true;
755 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
756 && SUBREG_REG (x) == y)
757 return true;
759 /* Now we have disposed of all the cases in which different rtx
760 codes can match. */
761 if (code != GET_CODE (y))
762 return false;
764 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
765 if (GET_MODE (x) != GET_MODE (y))
766 return false;
768 switch (code)
770 CASE_CONST_UNIQUE:
771 return false;
773 case LABEL_REF:
774 return LABEL_REF_LABEL (x) == LABEL_REF_LABEL (y);
775 case SYMBOL_REF:
776 return XSTR (x, 0) == XSTR (y, 0);
778 default:
779 break;
782 /* Compare the elements. If any pair of corresponding elements fail
783 to match, return false for the whole things. */
785 fmt = GET_RTX_FORMAT (code);
786 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
788 int val, j;
789 switch (fmt[i])
791 case 'w':
792 if (XWINT (x, i) != XWINT (y, i))
793 return false;
794 break;
796 case 'i':
797 if (XINT (x, i) != XINT (y, i))
798 return false;
799 break;
801 case 'e':
802 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
803 if (val == 0)
804 return false;
805 break;
807 case '0':
808 break;
810 case 'E':
811 if (XVECLEN (x, i) != XVECLEN (y, i))
812 return false;
813 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
815 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
816 if (val == 0)
817 return false;
819 break;
821 /* It is believed that rtx's at this level will never
822 contain anything but integers and other rtx's, except for
823 within LABEL_REFs and SYMBOL_REFs. */
824 default:
825 gcc_unreachable ();
828 return true;
831 /* True if X is a constant that can be forced into the constant pool.
832 MODE is the mode of the operand, or VOIDmode if not known. */
833 #define CONST_POOL_OK_P(MODE, X) \
834 ((MODE) != VOIDmode \
835 && CONSTANT_P (X) \
836 && GET_CODE (X) != HIGH \
837 && !targetm.cannot_force_const_mem (MODE, X))
839 /* True if C is a non-empty register class that has too few registers
840 to be safely used as a reload target class. */
841 #define SMALL_REGISTER_CLASS_P(C) \
842 (ira_class_hard_regs_num [(C)] == 1 \
843 || (ira_class_hard_regs_num [(C)] >= 1 \
844 && targetm.class_likely_spilled_p (C)))
846 /* If REG is a reload pseudo, try to make its class satisfying CL. */
847 static void
848 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
850 enum reg_class rclass;
852 /* Do not make more accurate class from reloads generated. They are
853 mostly moves with a lot of constraints. Making more accurate
854 class may results in very narrow class and impossibility of find
855 registers for several reloads of one insn. */
856 if (INSN_UID (curr_insn) >= new_insn_uid_start)
857 return;
858 if (GET_CODE (reg) == SUBREG)
859 reg = SUBREG_REG (reg);
860 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
861 return;
862 if (in_class_p (reg, cl, &rclass) && rclass != cl)
863 lra_change_class (REGNO (reg), rclass, " Change to", true);
866 /* Generate reloads for matching OUT and INS (array of input operand
867 numbers with end marker -1) with reg class GOAL_CLASS. Add input
868 and output reloads correspondingly to the lists *BEFORE and *AFTER.
869 OUT might be negative. In this case we generate input reloads for
870 matched input operands INS. */
871 static void
872 match_reload (signed char out, signed char *ins, enum reg_class goal_class,
873 rtx_insn **before, rtx_insn **after)
875 int i, in;
876 rtx new_in_reg, new_out_reg, reg, clobber;
877 machine_mode inmode, outmode;
878 rtx in_rtx = *curr_id->operand_loc[ins[0]];
879 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
881 inmode = curr_operand_mode[ins[0]];
882 outmode = out < 0 ? inmode : curr_operand_mode[out];
883 push_to_sequence (*before);
884 if (inmode != outmode)
886 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
888 reg = new_in_reg
889 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
890 goal_class, "");
891 if (SCALAR_INT_MODE_P (inmode))
892 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
893 else
894 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
895 LRA_SUBREG_P (new_out_reg) = 1;
896 /* If the input reg is dying here, we can use the same hard
897 register for REG and IN_RTX. We do it only for original
898 pseudos as reload pseudos can die although original
899 pseudos still live where reload pseudos dies. */
900 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
901 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)))
902 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
904 else
906 reg = new_out_reg
907 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
908 goal_class, "");
909 if (SCALAR_INT_MODE_P (outmode))
910 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
911 else
912 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0);
913 /* NEW_IN_REG is non-paradoxical subreg. We don't want
914 NEW_OUT_REG living above. We add clobber clause for
915 this. This is just a temporary clobber. We can remove
916 it at the end of LRA work. */
917 clobber = emit_clobber (new_out_reg);
918 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
919 LRA_SUBREG_P (new_in_reg) = 1;
920 if (GET_CODE (in_rtx) == SUBREG)
922 rtx subreg_reg = SUBREG_REG (in_rtx);
924 /* If SUBREG_REG is dying here and sub-registers IN_RTX
925 and NEW_IN_REG are similar, we can use the same hard
926 register for REG and SUBREG_REG. */
927 if (REG_P (subreg_reg)
928 && (int) REGNO (subreg_reg) < lra_new_regno_start
929 && GET_MODE (subreg_reg) == outmode
930 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg)
931 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)))
932 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
936 else
938 /* Pseudos have values -- see comments for lra_reg_info.
939 Different pseudos with the same value do not conflict even if
940 they live in the same place. When we create a pseudo we
941 assign value of original pseudo (if any) from which we
942 created the new pseudo. If we create the pseudo from the
943 input pseudo, the new pseudo will no conflict with the input
944 pseudo which is wrong when the input pseudo lives after the
945 insn and as the new pseudo value is changed by the insn
946 output. Therefore we create the new pseudo from the output.
948 We cannot reuse the current output register because we might
949 have a situation like "a <- a op b", where the constraints
950 force the second input operand ("b") to match the output
951 operand ("a"). "b" must then be copied into a new register
952 so that it doesn't clobber the current value of "a". */
954 new_in_reg = new_out_reg
955 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
956 goal_class, "");
958 /* In operand can be got from transformations before processing insn
959 constraints. One example of such transformations is subreg
960 reloading (see function simplify_operand_subreg). The new
961 pseudos created by the transformations might have inaccurate
962 class (ALL_REGS) and we should make their classes more
963 accurate. */
964 narrow_reload_pseudo_class (in_rtx, goal_class);
965 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
966 *before = get_insns ();
967 end_sequence ();
968 for (i = 0; (in = ins[i]) >= 0; i++)
970 lra_assert
971 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
972 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
973 *curr_id->operand_loc[in] = new_in_reg;
975 lra_update_dups (curr_id, ins);
976 if (out < 0)
977 return;
978 /* See a comment for the input operand above. */
979 narrow_reload_pseudo_class (out_rtx, goal_class);
980 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
982 start_sequence ();
983 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
984 emit_insn (*after);
985 *after = get_insns ();
986 end_sequence ();
988 *curr_id->operand_loc[out] = new_out_reg;
989 lra_update_dup (curr_id, out);
992 /* Return register class which is union of all reg classes in insn
993 constraint alternative string starting with P. */
994 static enum reg_class
995 reg_class_from_constraints (const char *p)
997 int c, len;
998 enum reg_class op_class = NO_REGS;
1001 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1003 case '#':
1004 case ',':
1005 return op_class;
1007 case 'g':
1008 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1009 break;
1011 default:
1012 enum constraint_num cn = lookup_constraint (p);
1013 enum reg_class cl = reg_class_for_constraint (cn);
1014 if (cl == NO_REGS)
1016 if (insn_extra_address_constraint (cn))
1017 op_class
1018 = (reg_class_subunion
1019 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1020 ADDRESS, SCRATCH)]);
1021 break;
1024 op_class = reg_class_subunion[op_class][cl];
1025 break;
1027 while ((p += len), c);
1028 return op_class;
1031 /* If OP is a register, return the class of the register as per
1032 get_reg_class, otherwise return NO_REGS. */
1033 static inline enum reg_class
1034 get_op_class (rtx op)
1036 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1039 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1040 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1041 SUBREG for VAL to make them equal. */
1042 static rtx_insn *
1043 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1045 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1047 /* Usually size of mem_pseudo is greater than val size but in
1048 rare cases it can be less as it can be defined by target
1049 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1050 if (! MEM_P (val))
1052 val = gen_rtx_SUBREG (GET_MODE (mem_pseudo),
1053 GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val,
1055 LRA_SUBREG_P (val) = 1;
1057 else
1059 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1060 LRA_SUBREG_P (mem_pseudo) = 1;
1063 return as_a <rtx_insn *> (to_p
1064 ? gen_move_insn (mem_pseudo, val)
1065 : gen_move_insn (val, mem_pseudo));
1068 /* Process a special case insn (register move), return true if we
1069 don't need to process it anymore. INSN should be a single set
1070 insn. Set up that RTL was changed through CHANGE_P and macro
1071 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1072 SEC_MEM_P. */
1073 static bool
1074 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1076 int sregno, dregno;
1077 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1078 rtx_insn *before;
1079 enum reg_class dclass, sclass, secondary_class;
1080 secondary_reload_info sri;
1082 lra_assert (curr_insn_set != NULL_RTX);
1083 dreg = dest = SET_DEST (curr_insn_set);
1084 sreg = src = SET_SRC (curr_insn_set);
1085 if (GET_CODE (dest) == SUBREG)
1086 dreg = SUBREG_REG (dest);
1087 if (GET_CODE (src) == SUBREG)
1088 sreg = SUBREG_REG (src);
1089 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1090 return false;
1091 sclass = dclass = NO_REGS;
1092 if (REG_P (dreg))
1093 dclass = get_reg_class (REGNO (dreg));
1094 if (dclass == ALL_REGS)
1095 /* ALL_REGS is used for new pseudos created by transformations
1096 like reload of SUBREG_REG (see function
1097 simplify_operand_subreg). We don't know their class yet. We
1098 should figure out the class from processing the insn
1099 constraints not in this fast path function. Even if ALL_REGS
1100 were a right class for the pseudo, secondary_... hooks usually
1101 are not define for ALL_REGS. */
1102 return false;
1103 if (REG_P (sreg))
1104 sclass = get_reg_class (REGNO (sreg));
1105 if (sclass == ALL_REGS)
1106 /* See comments above. */
1107 return false;
1108 if (sclass == NO_REGS && dclass == NO_REGS)
1109 return false;
1110 #ifdef SECONDARY_MEMORY_NEEDED
1111 if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src))
1112 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1113 && ((sclass != NO_REGS && dclass != NO_REGS)
1114 || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src)))
1115 #endif
1118 *sec_mem_p = true;
1119 return false;
1121 #endif
1122 if (! REG_P (dreg) || ! REG_P (sreg))
1123 return false;
1124 sri.prev_sri = NULL;
1125 sri.icode = CODE_FOR_nothing;
1126 sri.extra_cost = 0;
1127 secondary_class = NO_REGS;
1128 /* Set up hard register for a reload pseudo for hook
1129 secondary_reload because some targets just ignore unassigned
1130 pseudos in the hook. */
1131 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1133 dregno = REGNO (dreg);
1134 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1136 else
1137 dregno = -1;
1138 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1140 sregno = REGNO (sreg);
1141 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1143 else
1144 sregno = -1;
1145 if (sclass != NO_REGS)
1146 secondary_class
1147 = (enum reg_class) targetm.secondary_reload (false, dest,
1148 (reg_class_t) sclass,
1149 GET_MODE (src), &sri);
1150 if (sclass == NO_REGS
1151 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1152 && dclass != NO_REGS))
1154 enum reg_class old_sclass = secondary_class;
1155 secondary_reload_info old_sri = sri;
1157 sri.prev_sri = NULL;
1158 sri.icode = CODE_FOR_nothing;
1159 sri.extra_cost = 0;
1160 secondary_class
1161 = (enum reg_class) targetm.secondary_reload (true, src,
1162 (reg_class_t) dclass,
1163 GET_MODE (src), &sri);
1164 /* Check the target hook consistency. */
1165 lra_assert
1166 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1167 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1168 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1170 if (sregno >= 0)
1171 reg_renumber [sregno] = -1;
1172 if (dregno >= 0)
1173 reg_renumber [dregno] = -1;
1174 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1175 return false;
1176 *change_p = true;
1177 new_reg = NULL_RTX;
1178 if (secondary_class != NO_REGS)
1179 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1180 secondary_class,
1181 "secondary");
1182 start_sequence ();
1183 if (sri.icode == CODE_FOR_nothing)
1184 lra_emit_move (new_reg, src);
1185 else
1187 enum reg_class scratch_class;
1189 scratch_class = (reg_class_from_constraints
1190 (insn_data[sri.icode].operand[2].constraint));
1191 scratch_reg = (lra_create_new_reg_with_unique_value
1192 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1193 scratch_class, "scratch"));
1194 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1195 src, scratch_reg));
1197 before = get_insns ();
1198 end_sequence ();
1199 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1200 if (new_reg != NULL_RTX)
1201 SET_SRC (curr_insn_set) = new_reg;
1202 else
1204 if (lra_dump_file != NULL)
1206 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1207 dump_insn_slim (lra_dump_file, curr_insn);
1209 lra_set_insn_deleted (curr_insn);
1210 return true;
1212 return false;
1215 /* The following data describe the result of process_alt_operands.
1216 The data are used in curr_insn_transform to generate reloads. */
1218 /* The chosen reg classes which should be used for the corresponding
1219 operands. */
1220 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1221 /* True if the operand should be the same as another operand and that
1222 other operand does not need a reload. */
1223 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1224 /* True if the operand does not need a reload. */
1225 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1226 /* True if the operand can be offsetable memory. */
1227 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1228 /* The number of an operand to which given operand can be matched to. */
1229 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1230 /* The number of elements in the following array. */
1231 static int goal_alt_dont_inherit_ops_num;
1232 /* Numbers of operands whose reload pseudos should not be inherited. */
1233 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1234 /* True if the insn commutative operands should be swapped. */
1235 static bool goal_alt_swapped;
1236 /* The chosen insn alternative. */
1237 static int goal_alt_number;
1239 /* The following five variables are used to choose the best insn
1240 alternative. They reflect final characteristics of the best
1241 alternative. */
1243 /* Number of necessary reloads and overall cost reflecting the
1244 previous value and other unpleasantness of the best alternative. */
1245 static int best_losers, best_overall;
1246 /* Overall number hard registers used for reloads. For example, on
1247 some targets we need 2 general registers to reload DFmode and only
1248 one floating point register. */
1249 static int best_reload_nregs;
1250 /* Overall number reflecting distances of previous reloading the same
1251 value. The distances are counted from the current BB start. It is
1252 used to improve inheritance chances. */
1253 static int best_reload_sum;
1255 /* True if the current insn should have no correspondingly input or
1256 output reloads. */
1257 static bool no_input_reloads_p, no_output_reloads_p;
1259 /* True if we swapped the commutative operands in the current
1260 insn. */
1261 static int curr_swapped;
1263 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1264 register of class CL. Add any input reloads to list BEFORE. AFTER
1265 is nonnull if *LOC is an automodified value; handle that case by
1266 adding the required output reloads to list AFTER. Return true if
1267 the RTL was changed.
1269 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1270 register. Return false if the address register is correct. */
1271 static bool
1272 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1273 enum reg_class cl)
1275 int regno;
1276 enum reg_class rclass, new_class;
1277 rtx reg;
1278 rtx new_reg;
1279 machine_mode mode;
1280 bool subreg_p, before_p = false;
1282 subreg_p = GET_CODE (*loc) == SUBREG;
1283 if (subreg_p)
1284 loc = &SUBREG_REG (*loc);
1285 reg = *loc;
1286 mode = GET_MODE (reg);
1287 if (! REG_P (reg))
1289 if (check_only_p)
1290 return true;
1291 /* Always reload memory in an address even if the target supports
1292 such addresses. */
1293 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1294 before_p = true;
1296 else
1298 regno = REGNO (reg);
1299 rclass = get_reg_class (regno);
1300 if (! check_only_p
1301 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1303 if (lra_dump_file != NULL)
1305 fprintf (lra_dump_file,
1306 "Changing pseudo %d in address of insn %u on equiv ",
1307 REGNO (reg), INSN_UID (curr_insn));
1308 dump_value_slim (lra_dump_file, *loc, 1);
1309 fprintf (lra_dump_file, "\n");
1311 *loc = copy_rtx (*loc);
1313 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1315 if (check_only_p)
1316 return true;
1317 reg = *loc;
1318 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1319 mode, reg, cl, subreg_p, "address", &new_reg))
1320 before_p = true;
1322 else if (new_class != NO_REGS && rclass != new_class)
1324 if (check_only_p)
1325 return true;
1326 lra_change_class (regno, new_class, " Change to", true);
1327 return false;
1329 else
1330 return false;
1332 if (before_p)
1334 push_to_sequence (*before);
1335 lra_emit_move (new_reg, reg);
1336 *before = get_insns ();
1337 end_sequence ();
1339 *loc = new_reg;
1340 if (after != NULL)
1342 start_sequence ();
1343 lra_emit_move (reg, new_reg);
1344 emit_insn (*after);
1345 *after = get_insns ();
1346 end_sequence ();
1348 return true;
1351 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1352 the insn to be inserted before curr insn. AFTER returns the
1353 the insn to be inserted after curr insn. ORIGREG and NEWREG
1354 are the original reg and new reg for reload. */
1355 static void
1356 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1357 rtx newreg)
1359 if (before)
1361 push_to_sequence (*before);
1362 lra_emit_move (newreg, origreg);
1363 *before = get_insns ();
1364 end_sequence ();
1366 if (after)
1368 start_sequence ();
1369 lra_emit_move (origreg, newreg);
1370 emit_insn (*after);
1371 *after = get_insns ();
1372 end_sequence ();
1376 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1378 /* Make reloads for subreg in operand NOP with internal subreg mode
1379 REG_MODE, add new reloads for further processing. Return true if
1380 any change was done. */
1381 static bool
1382 simplify_operand_subreg (int nop, machine_mode reg_mode)
1384 int hard_regno;
1385 rtx_insn *before, *after;
1386 machine_mode mode, innermode;
1387 rtx reg, new_reg;
1388 rtx operand = *curr_id->operand_loc[nop];
1389 enum reg_class regclass;
1390 enum op_type type;
1392 before = after = NULL;
1394 if (GET_CODE (operand) != SUBREG)
1395 return false;
1397 mode = GET_MODE (operand);
1398 reg = SUBREG_REG (operand);
1399 innermode = GET_MODE (reg);
1400 type = curr_static_id->operand[nop].type;
1401 /* If we change address for paradoxical subreg of memory, the
1402 address might violate the necessary alignment or the access might
1403 be slow. So take this into consideration. We should not worry
1404 about access beyond allocated memory for paradoxical memory
1405 subregs as we don't substitute such equiv memory (see processing
1406 equivalences in function lra_constraints) and because for spilled
1407 pseudos we allocate stack memory enough for the biggest
1408 corresponding paradoxical subreg. */
1409 if (MEM_P (reg)
1410 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg))
1411 || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode)))
1413 rtx subst, old = *curr_id->operand_loc[nop];
1415 alter_subreg (curr_id->operand_loc[nop], false);
1416 subst = *curr_id->operand_loc[nop];
1417 lra_assert (MEM_P (subst));
1418 if (! valid_address_p (innermode, XEXP (reg, 0),
1419 MEM_ADDR_SPACE (reg))
1420 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1421 MEM_ADDR_SPACE (subst)))
1422 return true;
1423 /* If the address was valid and became invalid, prefer to reload
1424 the memory. Typical case is when the index scale should
1425 correspond the memory. */
1426 *curr_id->operand_loc[nop] = old;
1428 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1430 alter_subreg (curr_id->operand_loc[nop], false);
1431 return true;
1433 else if (CONSTANT_P (reg))
1435 /* Try to simplify subreg of constant. It is usually result of
1436 equivalence substitution. */
1437 if (innermode == VOIDmode
1438 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1439 innermode = curr_static_id->operand[nop].mode;
1440 if ((new_reg = simplify_subreg (mode, reg, innermode,
1441 SUBREG_BYTE (operand))) != NULL_RTX)
1443 *curr_id->operand_loc[nop] = new_reg;
1444 return true;
1447 /* Put constant into memory when we have mixed modes. It generates
1448 a better code in most cases as it does not need a secondary
1449 reload memory. It also prevents LRA looping when LRA is using
1450 secondary reload memory again and again. */
1451 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1452 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1454 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1455 alter_subreg (curr_id->operand_loc[nop], false);
1456 return true;
1458 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1459 if there may be a problem accessing OPERAND in the outer
1460 mode. */
1461 if ((REG_P (reg)
1462 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1463 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1464 /* Don't reload paradoxical subregs because we could be looping
1465 having repeatedly final regno out of hard regs range. */
1466 && (hard_regno_nregs[hard_regno][innermode]
1467 >= hard_regno_nregs[hard_regno][mode])
1468 && simplify_subreg_regno (hard_regno, innermode,
1469 SUBREG_BYTE (operand), mode) < 0
1470 /* Don't reload subreg for matching reload. It is actually
1471 valid subreg in LRA. */
1472 && ! LRA_SUBREG_P (operand))
1473 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1475 enum reg_class rclass;
1477 if (REG_P (reg))
1478 /* There is a big probability that we will get the same class
1479 for the new pseudo and we will get the same insn which
1480 means infinite looping. So spill the new pseudo. */
1481 rclass = NO_REGS;
1482 else
1483 /* The class will be defined later in curr_insn_transform. */
1484 rclass
1485 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1487 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1488 rclass, TRUE, "subreg reg", &new_reg))
1490 bool insert_before, insert_after;
1491 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1493 insert_before = (type != OP_OUT
1494 || GET_MODE_SIZE (innermode) > GET_MODE_SIZE (mode));
1495 insert_after = (type != OP_IN);
1496 insert_move_for_subreg (insert_before ? &before : NULL,
1497 insert_after ? &after : NULL,
1498 reg, new_reg);
1500 SUBREG_REG (operand) = new_reg;
1501 lra_process_new_insns (curr_insn, before, after,
1502 "Inserting subreg reload");
1503 return true;
1505 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1506 IRA allocates hardreg to the inner pseudo reg according to its mode
1507 instead of the outermode, so the size of the hardreg may not be enough
1508 to contain the outermode operand, in that case we may need to insert
1509 reload for the reg. For the following two types of paradoxical subreg,
1510 we need to insert reload:
1511 1. If the op_type is OP_IN, and the hardreg could not be paired with
1512 other hardreg to contain the outermode operand
1513 (checked by in_hard_reg_set_p), we need to insert the reload.
1514 2. If the op_type is OP_OUT or OP_INOUT.
1516 Here is a paradoxical subreg example showing how the reload is generated:
1518 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1519 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1521 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1522 here, if reg107 is assigned to hardreg R15, because R15 is the last
1523 hardreg, compiler cannot find another hardreg to pair with R15 to
1524 contain TImode data. So we insert a TImode reload reg180 for it.
1525 After reload is inserted:
1527 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1528 (reg:DI 107 [ __comp ])) -1
1529 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1530 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1532 Two reload hard registers will be allocated to reg180 to save TImode data
1533 in LRA_assign. */
1534 else if (REG_P (reg)
1535 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1536 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1537 && (hard_regno_nregs[hard_regno][innermode]
1538 < hard_regno_nregs[hard_regno][mode])
1539 && (regclass = lra_get_allocno_class (REGNO (reg)))
1540 && (type != OP_IN
1541 || !in_hard_reg_set_p (reg_class_contents[regclass],
1542 mode, hard_regno)))
1544 /* The class will be defined later in curr_insn_transform. */
1545 enum reg_class rclass
1546 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1548 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1549 rclass, TRUE, "paradoxical subreg", &new_reg))
1551 rtx subreg;
1552 bool insert_before, insert_after;
1554 PUT_MODE (new_reg, mode);
1555 subreg = simplify_gen_subreg (innermode, new_reg, mode, 0);
1556 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1558 insert_before = (type != OP_OUT);
1559 insert_after = (type != OP_IN);
1560 insert_move_for_subreg (insert_before ? &before : NULL,
1561 insert_after ? &after : NULL,
1562 reg, subreg);
1564 SUBREG_REG (operand) = new_reg;
1565 lra_process_new_insns (curr_insn, before, after,
1566 "Inserting paradoxical subreg reload");
1567 return true;
1569 return false;
1572 /* Return TRUE if X refers for a hard register from SET. */
1573 static bool
1574 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1576 int i, j, x_hard_regno;
1577 machine_mode mode;
1578 const char *fmt;
1579 enum rtx_code code;
1581 if (x == NULL_RTX)
1582 return false;
1583 code = GET_CODE (x);
1584 mode = GET_MODE (x);
1585 if (code == SUBREG)
1587 x = SUBREG_REG (x);
1588 code = GET_CODE (x);
1589 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode))
1590 mode = GET_MODE (x);
1593 if (REG_P (x))
1595 x_hard_regno = get_hard_regno (x);
1596 return (x_hard_regno >= 0
1597 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1599 if (MEM_P (x))
1601 struct address_info ad;
1603 decompose_mem_address (&ad, x);
1604 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1605 return true;
1606 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1607 return true;
1609 fmt = GET_RTX_FORMAT (code);
1610 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1612 if (fmt[i] == 'e')
1614 if (uses_hard_regs_p (XEXP (x, i), set))
1615 return true;
1617 else if (fmt[i] == 'E')
1619 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1620 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1621 return true;
1624 return false;
1627 /* Return true if OP is a spilled pseudo. */
1628 static inline bool
1629 spilled_pseudo_p (rtx op)
1631 return (REG_P (op)
1632 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1635 /* Return true if X is a general constant. */
1636 static inline bool
1637 general_constant_p (rtx x)
1639 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1642 static bool
1643 reg_in_class_p (rtx reg, enum reg_class cl)
1645 if (cl == NO_REGS)
1646 return get_reg_class (REGNO (reg)) == NO_REGS;
1647 return in_class_p (reg, cl, NULL);
1650 /* Return true if SET of RCLASS contains no hard regs which can be
1651 used in MODE. */
1652 static bool
1653 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1654 HARD_REG_SET &set,
1655 enum machine_mode mode)
1657 HARD_REG_SET temp;
1659 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1660 COPY_HARD_REG_SET (temp, set);
1661 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1662 return (hard_reg_set_subset_p
1663 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1666 /* Major function to choose the current insn alternative and what
1667 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1668 negative we should consider only this alternative. Return false if
1669 we can not choose the alternative or find how to reload the
1670 operands. */
1671 static bool
1672 process_alt_operands (int only_alternative)
1674 bool ok_p = false;
1675 int nop, overall, nalt;
1676 int n_alternatives = curr_static_id->n_alternatives;
1677 int n_operands = curr_static_id->n_operands;
1678 /* LOSERS counts the operands that don't fit this alternative and
1679 would require loading. */
1680 int losers;
1681 /* REJECT is a count of how undesirable this alternative says it is
1682 if any reloading is required. If the alternative matches exactly
1683 then REJECT is ignored, but otherwise it gets this much counted
1684 against it in addition to the reloading needed. */
1685 int reject;
1686 int op_reject;
1687 /* The number of elements in the following array. */
1688 int early_clobbered_regs_num;
1689 /* Numbers of operands which are early clobber registers. */
1690 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1691 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1692 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1693 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1694 bool curr_alt_win[MAX_RECOG_OPERANDS];
1695 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1696 int curr_alt_matches[MAX_RECOG_OPERANDS];
1697 /* The number of elements in the following array. */
1698 int curr_alt_dont_inherit_ops_num;
1699 /* Numbers of operands whose reload pseudos should not be inherited. */
1700 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1701 rtx op;
1702 /* The register when the operand is a subreg of register, otherwise the
1703 operand itself. */
1704 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1705 /* The register if the operand is a register or subreg of register,
1706 otherwise NULL. */
1707 rtx operand_reg[MAX_RECOG_OPERANDS];
1708 int hard_regno[MAX_RECOG_OPERANDS];
1709 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1710 int reload_nregs, reload_sum;
1711 bool costly_p;
1712 enum reg_class cl;
1714 /* Calculate some data common for all alternatives to speed up the
1715 function. */
1716 for (nop = 0; nop < n_operands; nop++)
1718 rtx reg;
1720 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1721 /* The real hard regno of the operand after the allocation. */
1722 hard_regno[nop] = get_hard_regno (op);
1724 operand_reg[nop] = reg = op;
1725 biggest_mode[nop] = GET_MODE (op);
1726 if (GET_CODE (op) == SUBREG)
1728 operand_reg[nop] = reg = SUBREG_REG (op);
1729 if (GET_MODE_SIZE (biggest_mode[nop])
1730 < GET_MODE_SIZE (GET_MODE (reg)))
1731 biggest_mode[nop] = GET_MODE (reg);
1733 if (! REG_P (reg))
1734 operand_reg[nop] = NULL_RTX;
1735 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1736 || ((int) REGNO (reg)
1737 == lra_get_elimination_hard_regno (REGNO (reg))))
1738 no_subreg_reg_operand[nop] = reg;
1739 else
1740 operand_reg[nop] = no_subreg_reg_operand[nop]
1741 /* Just use natural mode for elimination result. It should
1742 be enough for extra constraints hooks. */
1743 = regno_reg_rtx[hard_regno[nop]];
1746 /* The constraints are made of several alternatives. Each operand's
1747 constraint looks like foo,bar,... with commas separating the
1748 alternatives. The first alternatives for all operands go
1749 together, the second alternatives go together, etc.
1751 First loop over alternatives. */
1752 alternative_mask preferred = curr_id->preferred_alternatives;
1753 if (only_alternative >= 0)
1754 preferred &= ALTERNATIVE_BIT (only_alternative);
1756 for (nalt = 0; nalt < n_alternatives; nalt++)
1758 /* Loop over operands for one constraint alternative. */
1759 if (!TEST_BIT (preferred, nalt))
1760 continue;
1762 overall = losers = reject = reload_nregs = reload_sum = 0;
1763 for (nop = 0; nop < n_operands; nop++)
1765 int inc = (curr_static_id
1766 ->operand_alternative[nalt * n_operands + nop].reject);
1767 if (lra_dump_file != NULL && inc != 0)
1768 fprintf (lra_dump_file,
1769 " Staticly defined alt reject+=%d\n", inc);
1770 reject += inc;
1772 early_clobbered_regs_num = 0;
1774 for (nop = 0; nop < n_operands; nop++)
1776 const char *p;
1777 char *end;
1778 int len, c, m, i, opalt_num, this_alternative_matches;
1779 bool win, did_match, offmemok, early_clobber_p;
1780 /* false => this operand can be reloaded somehow for this
1781 alternative. */
1782 bool badop;
1783 /* true => this operand can be reloaded if the alternative
1784 allows regs. */
1785 bool winreg;
1786 /* True if a constant forced into memory would be OK for
1787 this operand. */
1788 bool constmemok;
1789 enum reg_class this_alternative, this_costly_alternative;
1790 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
1791 bool this_alternative_match_win, this_alternative_win;
1792 bool this_alternative_offmemok;
1793 bool scratch_p;
1794 machine_mode mode;
1795 enum constraint_num cn;
1797 opalt_num = nalt * n_operands + nop;
1798 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
1800 /* Fast track for no constraints at all. */
1801 curr_alt[nop] = NO_REGS;
1802 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
1803 curr_alt_win[nop] = true;
1804 curr_alt_match_win[nop] = false;
1805 curr_alt_offmemok[nop] = false;
1806 curr_alt_matches[nop] = -1;
1807 continue;
1810 op = no_subreg_reg_operand[nop];
1811 mode = curr_operand_mode[nop];
1813 win = did_match = winreg = offmemok = constmemok = false;
1814 badop = true;
1816 early_clobber_p = false;
1817 p = curr_static_id->operand_alternative[opalt_num].constraint;
1819 this_costly_alternative = this_alternative = NO_REGS;
1820 /* We update set of possible hard regs besides its class
1821 because reg class might be inaccurate. For example,
1822 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1823 is translated in HI_REGS because classes are merged by
1824 pairs and there is no accurate intermediate class. */
1825 CLEAR_HARD_REG_SET (this_alternative_set);
1826 CLEAR_HARD_REG_SET (this_costly_alternative_set);
1827 this_alternative_win = false;
1828 this_alternative_match_win = false;
1829 this_alternative_offmemok = false;
1830 this_alternative_matches = -1;
1832 /* An empty constraint should be excluded by the fast
1833 track. */
1834 lra_assert (*p != 0 && *p != ',');
1836 op_reject = 0;
1837 /* Scan this alternative's specs for this operand; set WIN
1838 if the operand fits any letter in this alternative.
1839 Otherwise, clear BADOP if this operand could fit some
1840 letter after reloads, or set WINREG if this operand could
1841 fit after reloads provided the constraint allows some
1842 registers. */
1843 costly_p = false;
1846 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1848 case '\0':
1849 len = 0;
1850 break;
1851 case ',':
1852 c = '\0';
1853 break;
1855 case '&':
1856 early_clobber_p = true;
1857 break;
1859 case '$':
1860 op_reject += LRA_MAX_REJECT;
1861 break;
1862 case '^':
1863 op_reject += LRA_LOSER_COST_FACTOR;
1864 break;
1866 case '#':
1867 /* Ignore rest of this alternative. */
1868 c = '\0';
1869 break;
1871 case '0': case '1': case '2': case '3': case '4':
1872 case '5': case '6': case '7': case '8': case '9':
1874 int m_hregno;
1875 bool match_p;
1877 m = strtoul (p, &end, 10);
1878 p = end;
1879 len = 0;
1880 lra_assert (nop > m);
1882 this_alternative_matches = m;
1883 m_hregno = get_hard_regno (*curr_id->operand_loc[m]);
1884 /* We are supposed to match a previous operand.
1885 If we do, we win if that one did. If we do
1886 not, count both of the operands as losers.
1887 (This is too conservative, since most of the
1888 time only a single reload insn will be needed
1889 to make the two operands win. As a result,
1890 this alternative may be rejected when it is
1891 actually desirable.) */
1892 match_p = false;
1893 if (operands_match_p (*curr_id->operand_loc[nop],
1894 *curr_id->operand_loc[m], m_hregno))
1896 /* We should reject matching of an early
1897 clobber operand if the matching operand is
1898 not dying in the insn. */
1899 if (! curr_static_id->operand[m].early_clobber
1900 || operand_reg[nop] == NULL_RTX
1901 || (find_regno_note (curr_insn, REG_DEAD,
1902 REGNO (op))
1903 || REGNO (op) == REGNO (operand_reg[m])))
1904 match_p = true;
1906 if (match_p)
1908 /* If we are matching a non-offsettable
1909 address where an offsettable address was
1910 expected, then we must reject this
1911 combination, because we can't reload
1912 it. */
1913 if (curr_alt_offmemok[m]
1914 && MEM_P (*curr_id->operand_loc[m])
1915 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
1916 continue;
1918 else
1920 /* Operands don't match. Both operands must
1921 allow a reload register, otherwise we
1922 cannot make them match. */
1923 if (curr_alt[m] == NO_REGS)
1924 break;
1925 /* Retroactively mark the operand we had to
1926 match as a loser, if it wasn't already and
1927 it wasn't matched to a register constraint
1928 (e.g it might be matched by memory). */
1929 if (curr_alt_win[m]
1930 && (operand_reg[m] == NULL_RTX
1931 || hard_regno[m] < 0))
1933 losers++;
1934 reload_nregs
1935 += (ira_reg_class_max_nregs[curr_alt[m]]
1936 [GET_MODE (*curr_id->operand_loc[m])]);
1939 /* Prefer matching earlyclobber alternative as
1940 it results in less hard regs required for
1941 the insn than a non-matching earlyclobber
1942 alternative. */
1943 if (curr_static_id->operand[m].early_clobber)
1945 if (lra_dump_file != NULL)
1946 fprintf
1947 (lra_dump_file,
1948 " %d Matching earlyclobber alt:"
1949 " reject--\n",
1950 nop);
1951 reject--;
1953 /* Otherwise we prefer no matching
1954 alternatives because it gives more freedom
1955 in RA. */
1956 else if (operand_reg[nop] == NULL_RTX
1957 || (find_regno_note (curr_insn, REG_DEAD,
1958 REGNO (operand_reg[nop]))
1959 == NULL_RTX))
1961 if (lra_dump_file != NULL)
1962 fprintf
1963 (lra_dump_file,
1964 " %d Matching alt: reject+=2\n",
1965 nop);
1966 reject += 2;
1969 /* If we have to reload this operand and some
1970 previous operand also had to match the same
1971 thing as this operand, we don't know how to do
1972 that. */
1973 if (!match_p || !curr_alt_win[m])
1975 for (i = 0; i < nop; i++)
1976 if (curr_alt_matches[i] == m)
1977 break;
1978 if (i < nop)
1979 break;
1981 else
1982 did_match = true;
1984 /* This can be fixed with reloads if the operand
1985 we are supposed to match can be fixed with
1986 reloads. */
1987 badop = false;
1988 this_alternative = curr_alt[m];
1989 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
1990 winreg = this_alternative != NO_REGS;
1991 break;
1994 case 'g':
1995 if (MEM_P (op)
1996 || general_constant_p (op)
1997 || spilled_pseudo_p (op))
1998 win = true;
1999 cl = GENERAL_REGS;
2000 goto reg;
2002 default:
2003 cn = lookup_constraint (p);
2004 switch (get_constraint_type (cn))
2006 case CT_REGISTER:
2007 cl = reg_class_for_constraint (cn);
2008 if (cl != NO_REGS)
2009 goto reg;
2010 break;
2012 case CT_CONST_INT:
2013 if (CONST_INT_P (op)
2014 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2015 win = true;
2016 break;
2018 case CT_MEMORY:
2019 if (MEM_P (op)
2020 && satisfies_memory_constraint_p (op, cn))
2021 win = true;
2022 else if (spilled_pseudo_p (op))
2023 win = true;
2025 /* If we didn't already win, we can reload constants
2026 via force_const_mem or put the pseudo value into
2027 memory, or make other memory by reloading the
2028 address like for 'o'. */
2029 if (CONST_POOL_OK_P (mode, op)
2030 || MEM_P (op) || REG_P (op))
2031 badop = false;
2032 constmemok = true;
2033 offmemok = true;
2034 break;
2036 case CT_ADDRESS:
2037 /* If we didn't already win, we can reload the address
2038 into a base register. */
2039 if (satisfies_address_constraint_p (op, cn))
2040 win = true;
2041 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2042 ADDRESS, SCRATCH);
2043 badop = false;
2044 goto reg;
2046 case CT_FIXED_FORM:
2047 if (constraint_satisfied_p (op, cn))
2048 win = true;
2049 break;
2051 break;
2053 reg:
2054 this_alternative = reg_class_subunion[this_alternative][cl];
2055 IOR_HARD_REG_SET (this_alternative_set,
2056 reg_class_contents[cl]);
2057 if (costly_p)
2059 this_costly_alternative
2060 = reg_class_subunion[this_costly_alternative][cl];
2061 IOR_HARD_REG_SET (this_costly_alternative_set,
2062 reg_class_contents[cl]);
2064 if (mode == BLKmode)
2065 break;
2066 winreg = true;
2067 if (REG_P (op))
2069 if (hard_regno[nop] >= 0
2070 && in_hard_reg_set_p (this_alternative_set,
2071 mode, hard_regno[nop]))
2072 win = true;
2073 else if (hard_regno[nop] < 0
2074 && in_class_p (op, this_alternative, NULL))
2075 win = true;
2077 break;
2079 if (c != ' ' && c != '\t')
2080 costly_p = c == '*';
2082 while ((p += len), c);
2084 scratch_p = (operand_reg[nop] != NULL_RTX
2085 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2086 /* Record which operands fit this alternative. */
2087 if (win)
2089 this_alternative_win = true;
2090 if (operand_reg[nop] != NULL_RTX)
2092 if (hard_regno[nop] >= 0)
2094 if (in_hard_reg_set_p (this_costly_alternative_set,
2095 mode, hard_regno[nop]))
2097 if (lra_dump_file != NULL)
2098 fprintf (lra_dump_file,
2099 " %d Costly set: reject++\n",
2100 nop);
2101 reject++;
2104 else
2106 /* Prefer won reg to spilled pseudo under other
2107 equal conditions for possibe inheritance. */
2108 if (! scratch_p)
2110 if (lra_dump_file != NULL)
2111 fprintf
2112 (lra_dump_file,
2113 " %d Non pseudo reload: reject++\n",
2114 nop);
2115 reject++;
2117 if (in_class_p (operand_reg[nop],
2118 this_costly_alternative, NULL))
2120 if (lra_dump_file != NULL)
2121 fprintf
2122 (lra_dump_file,
2123 " %d Non pseudo costly reload:"
2124 " reject++\n",
2125 nop);
2126 reject++;
2129 /* We simulate the behaviour of old reload here.
2130 Although scratches need hard registers and it
2131 might result in spilling other pseudos, no reload
2132 insns are generated for the scratches. So it
2133 might cost something but probably less than old
2134 reload pass believes. */
2135 if (scratch_p)
2137 if (lra_dump_file != NULL)
2138 fprintf (lra_dump_file,
2139 " %d Scratch win: reject+=2\n",
2140 nop);
2141 reject += 2;
2145 else if (did_match)
2146 this_alternative_match_win = true;
2147 else
2149 int const_to_mem = 0;
2150 bool no_regs_p;
2152 reject += op_reject;
2153 /* Never do output reload of stack pointer. It makes
2154 impossible to do elimination when SP is changed in
2155 RTL. */
2156 if (op == stack_pointer_rtx && ! frame_pointer_needed
2157 && curr_static_id->operand[nop].type != OP_IN)
2158 goto fail;
2160 /* If this alternative asks for a specific reg class, see if there
2161 is at least one allocatable register in that class. */
2162 no_regs_p
2163 = (this_alternative == NO_REGS
2164 || (hard_reg_set_subset_p
2165 (reg_class_contents[this_alternative],
2166 lra_no_alloc_regs)));
2168 /* For asms, verify that the class for this alternative is possible
2169 for the mode that is specified. */
2170 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2172 int i;
2173 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2174 if (HARD_REGNO_MODE_OK (i, mode)
2175 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2176 mode, i))
2177 break;
2178 if (i == FIRST_PSEUDO_REGISTER)
2179 winreg = false;
2182 /* If this operand accepts a register, and if the
2183 register class has at least one allocatable register,
2184 then this operand can be reloaded. */
2185 if (winreg && !no_regs_p)
2186 badop = false;
2188 if (badop)
2190 if (lra_dump_file != NULL)
2191 fprintf (lra_dump_file,
2192 " alt=%d: Bad operand -- refuse\n",
2193 nalt);
2194 goto fail;
2197 /* If not assigned pseudo has a class which a subset of
2198 required reg class, it is a less costly alternative
2199 as the pseudo still can get a hard reg of necessary
2200 class. */
2201 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2202 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2203 && ira_class_subset_p[this_alternative][cl])
2205 if (lra_dump_file != NULL)
2206 fprintf
2207 (lra_dump_file,
2208 " %d Super set class reg: reject-=3\n", nop);
2209 reject -= 3;
2212 this_alternative_offmemok = offmemok;
2213 if (this_costly_alternative != NO_REGS)
2215 if (lra_dump_file != NULL)
2216 fprintf (lra_dump_file,
2217 " %d Costly loser: reject++\n", nop);
2218 reject++;
2220 /* If the operand is dying, has a matching constraint,
2221 and satisfies constraints of the matched operand
2222 which failed to satisfy the own constraints, most probably
2223 the reload for this operand will be gone. */
2224 if (this_alternative_matches >= 0
2225 && !curr_alt_win[this_alternative_matches]
2226 && REG_P (op)
2227 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2228 && (hard_regno[nop] >= 0
2229 ? in_hard_reg_set_p (this_alternative_set,
2230 mode, hard_regno[nop])
2231 : in_class_p (op, this_alternative, NULL)))
2233 if (lra_dump_file != NULL)
2234 fprintf
2235 (lra_dump_file,
2236 " %d Dying matched operand reload: reject++\n",
2237 nop);
2238 reject++;
2240 else
2242 /* Strict_low_part requires to reload the register
2243 not the sub-register. In this case we should
2244 check that a final reload hard reg can hold the
2245 value mode. */
2246 if (curr_static_id->operand[nop].strict_low
2247 && REG_P (op)
2248 && hard_regno[nop] < 0
2249 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2250 && ira_class_hard_regs_num[this_alternative] > 0
2251 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2252 [this_alternative][0],
2253 GET_MODE
2254 (*curr_id->operand_loc[nop])))
2256 if (lra_dump_file != NULL)
2257 fprintf
2258 (lra_dump_file,
2259 " alt=%d: Strict low subreg reload -- refuse\n",
2260 nalt);
2261 goto fail;
2263 losers++;
2265 if (operand_reg[nop] != NULL_RTX
2266 /* Output operands and matched input operands are
2267 not inherited. The following conditions do not
2268 exactly describe the previous statement but they
2269 are pretty close. */
2270 && curr_static_id->operand[nop].type != OP_OUT
2271 && (this_alternative_matches < 0
2272 || curr_static_id->operand[nop].type != OP_IN))
2274 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2275 (operand_reg[nop])]
2276 .last_reload);
2278 /* The value of reload_sum has sense only if we
2279 process insns in their order. It happens only on
2280 the first constraints sub-pass when we do most of
2281 reload work. */
2282 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2283 reload_sum += last_reload - bb_reload_num;
2285 /* If this is a constant that is reloaded into the
2286 desired class by copying it to memory first, count
2287 that as another reload. This is consistent with
2288 other code and is required to avoid choosing another
2289 alternative when the constant is moved into memory.
2290 Note that the test here is precisely the same as in
2291 the code below that calls force_const_mem. */
2292 if (CONST_POOL_OK_P (mode, op)
2293 && ((targetm.preferred_reload_class
2294 (op, this_alternative) == NO_REGS)
2295 || no_input_reloads_p))
2297 const_to_mem = 1;
2298 if (! no_regs_p)
2299 losers++;
2302 /* Alternative loses if it requires a type of reload not
2303 permitted for this insn. We can always reload
2304 objects with a REG_UNUSED note. */
2305 if ((curr_static_id->operand[nop].type != OP_IN
2306 && no_output_reloads_p
2307 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2308 || (curr_static_id->operand[nop].type != OP_OUT
2309 && no_input_reloads_p && ! const_to_mem)
2310 || (this_alternative_matches >= 0
2311 && (no_input_reloads_p
2312 || (no_output_reloads_p
2313 && (curr_static_id->operand
2314 [this_alternative_matches].type != OP_IN)
2315 && ! find_reg_note (curr_insn, REG_UNUSED,
2316 no_subreg_reg_operand
2317 [this_alternative_matches])))))
2319 if (lra_dump_file != NULL)
2320 fprintf
2321 (lra_dump_file,
2322 " alt=%d: No input/otput reload -- refuse\n",
2323 nalt);
2324 goto fail;
2327 /* Alternative loses if it required class pseudo can not
2328 hold value of required mode. Such insns can be
2329 described by insn definitions with mode iterators. */
2330 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2331 && ! hard_reg_set_empty_p (this_alternative_set)
2332 /* It is common practice for constraints to use a
2333 class which does not have actually enough regs to
2334 hold the value (e.g. x86 AREG for mode requiring
2335 more one general reg). Therefore we have 2
2336 conditions to check that the reload pseudo can
2337 not hold the mode value. */
2338 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2339 [this_alternative][0],
2340 GET_MODE (*curr_id->operand_loc[nop]))
2341 /* The above condition is not enough as the first
2342 reg in ira_class_hard_regs can be not aligned for
2343 multi-words mode values. */
2344 && (prohibited_class_reg_set_mode_p
2345 (this_alternative, this_alternative_set,
2346 GET_MODE (*curr_id->operand_loc[nop]))))
2348 if (lra_dump_file != NULL)
2349 fprintf (lra_dump_file,
2350 " alt=%d: reload pseudo for op %d "
2351 " can not hold the mode value -- refuse\n",
2352 nalt, nop);
2353 goto fail;
2356 /* Check strong discouragement of reload of non-constant
2357 into class THIS_ALTERNATIVE. */
2358 if (! CONSTANT_P (op) && ! no_regs_p
2359 && (targetm.preferred_reload_class
2360 (op, this_alternative) == NO_REGS
2361 || (curr_static_id->operand[nop].type == OP_OUT
2362 && (targetm.preferred_output_reload_class
2363 (op, this_alternative) == NO_REGS))))
2365 if (lra_dump_file != NULL)
2366 fprintf (lra_dump_file,
2367 " %d Non-prefered reload: reject+=%d\n",
2368 nop, LRA_MAX_REJECT);
2369 reject += LRA_MAX_REJECT;
2372 if (! (MEM_P (op) && offmemok)
2373 && ! (const_to_mem && constmemok))
2375 /* We prefer to reload pseudos over reloading other
2376 things, since such reloads may be able to be
2377 eliminated later. So bump REJECT in other cases.
2378 Don't do this in the case where we are forcing a
2379 constant into memory and it will then win since
2380 we don't want to have a different alternative
2381 match then. */
2382 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2384 if (lra_dump_file != NULL)
2385 fprintf
2386 (lra_dump_file,
2387 " %d Non-pseudo reload: reject+=2\n",
2388 nop);
2389 reject += 2;
2392 if (! no_regs_p)
2393 reload_nregs
2394 += ira_reg_class_max_nregs[this_alternative][mode];
2396 if (SMALL_REGISTER_CLASS_P (this_alternative))
2398 if (lra_dump_file != NULL)
2399 fprintf
2400 (lra_dump_file,
2401 " %d Small class reload: reject+=%d\n",
2402 nop, LRA_LOSER_COST_FACTOR / 2);
2403 reject += LRA_LOSER_COST_FACTOR / 2;
2407 /* We are trying to spill pseudo into memory. It is
2408 usually more costly than moving to a hard register
2409 although it might takes the same number of
2410 reloads. */
2411 if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0)
2413 if (lra_dump_file != NULL)
2414 fprintf
2415 (lra_dump_file,
2416 " %d Spill pseudo into memory: reject+=3\n",
2417 nop);
2418 reject += 3;
2419 if (VECTOR_MODE_P (mode))
2421 /* Spilling vectors into memory is usually more
2422 costly as they contain big values. */
2423 if (lra_dump_file != NULL)
2424 fprintf
2425 (lra_dump_file,
2426 " %d Spill vector pseudo: reject+=2\n",
2427 nop);
2428 reject += 2;
2432 #ifdef SECONDARY_MEMORY_NEEDED
2433 /* If reload requires moving value through secondary
2434 memory, it will need one more insn at least. */
2435 if (this_alternative != NO_REGS
2436 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2437 && ((curr_static_id->operand[nop].type != OP_OUT
2438 && SECONDARY_MEMORY_NEEDED (cl, this_alternative,
2439 GET_MODE (op)))
2440 || (curr_static_id->operand[nop].type != OP_IN
2441 && SECONDARY_MEMORY_NEEDED (this_alternative, cl,
2442 GET_MODE (op)))))
2443 losers++;
2444 #endif
2445 /* Input reloads can be inherited more often than output
2446 reloads can be removed, so penalize output
2447 reloads. */
2448 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2450 if (lra_dump_file != NULL)
2451 fprintf
2452 (lra_dump_file,
2453 " %d Non input pseudo reload: reject++\n",
2454 nop);
2455 reject++;
2459 if (early_clobber_p && ! scratch_p)
2461 if (lra_dump_file != NULL)
2462 fprintf (lra_dump_file,
2463 " %d Early clobber: reject++\n", nop);
2464 reject++;
2466 /* ??? We check early clobbers after processing all operands
2467 (see loop below) and there we update the costs more.
2468 Should we update the cost (may be approximately) here
2469 because of early clobber register reloads or it is a rare
2470 or non-important thing to be worth to do it. */
2471 overall = losers * LRA_LOSER_COST_FACTOR + reject;
2472 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2474 if (lra_dump_file != NULL)
2475 fprintf (lra_dump_file,
2476 " alt=%d,overall=%d,losers=%d -- refuse\n",
2477 nalt, overall, losers);
2478 goto fail;
2481 curr_alt[nop] = this_alternative;
2482 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2483 curr_alt_win[nop] = this_alternative_win;
2484 curr_alt_match_win[nop] = this_alternative_match_win;
2485 curr_alt_offmemok[nop] = this_alternative_offmemok;
2486 curr_alt_matches[nop] = this_alternative_matches;
2488 if (this_alternative_matches >= 0
2489 && !did_match && !this_alternative_win)
2490 curr_alt_win[this_alternative_matches] = false;
2492 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2493 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2495 if (curr_insn_set != NULL_RTX && n_operands == 2
2496 /* Prevent processing non-move insns. */
2497 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2498 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2499 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2500 && REG_P (no_subreg_reg_operand[0])
2501 && REG_P (no_subreg_reg_operand[1])
2502 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2503 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2504 || (! curr_alt_win[0] && curr_alt_win[1]
2505 && REG_P (no_subreg_reg_operand[1])
2506 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2507 || (curr_alt_win[0] && ! curr_alt_win[1]
2508 && REG_P (no_subreg_reg_operand[0])
2509 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2510 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2511 no_subreg_reg_operand[1])
2512 || (targetm.preferred_reload_class
2513 (no_subreg_reg_operand[1],
2514 (enum reg_class) curr_alt[1]) != NO_REGS))
2515 /* If it is a result of recent elimination in move
2516 insn we can transform it into an add still by
2517 using this alternative. */
2518 && GET_CODE (no_subreg_reg_operand[1]) != PLUS)))
2520 /* We have a move insn and a new reload insn will be similar
2521 to the current insn. We should avoid such situation as it
2522 results in LRA cycling. */
2523 overall += LRA_MAX_REJECT;
2525 ok_p = true;
2526 curr_alt_dont_inherit_ops_num = 0;
2527 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2529 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2530 HARD_REG_SET temp_set;
2532 i = early_clobbered_nops[nop];
2533 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2534 || hard_regno[i] < 0)
2535 continue;
2536 lra_assert (operand_reg[i] != NULL_RTX);
2537 clobbered_hard_regno = hard_regno[i];
2538 CLEAR_HARD_REG_SET (temp_set);
2539 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2540 first_conflict_j = last_conflict_j = -1;
2541 for (j = 0; j < n_operands; j++)
2542 if (j == i
2543 /* We don't want process insides of match_operator and
2544 match_parallel because otherwise we would process
2545 their operands once again generating a wrong
2546 code. */
2547 || curr_static_id->operand[j].is_operator)
2548 continue;
2549 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2550 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2551 continue;
2552 /* If we don't reload j-th operand, check conflicts. */
2553 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2554 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2556 if (first_conflict_j < 0)
2557 first_conflict_j = j;
2558 last_conflict_j = j;
2560 if (last_conflict_j < 0)
2561 continue;
2562 /* If earlyclobber operand conflicts with another
2563 non-matching operand which is actually the same register
2564 as the earlyclobber operand, it is better to reload the
2565 another operand as an operand matching the earlyclobber
2566 operand can be also the same. */
2567 if (first_conflict_j == last_conflict_j
2568 && operand_reg[last_conflict_j]
2569 != NULL_RTX && ! curr_alt_match_win[last_conflict_j]
2570 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2572 curr_alt_win[last_conflict_j] = false;
2573 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2574 = last_conflict_j;
2575 losers++;
2576 /* Early clobber was already reflected in REJECT. */
2577 lra_assert (reject > 0);
2578 if (lra_dump_file != NULL)
2579 fprintf
2580 (lra_dump_file,
2581 " %d Conflict early clobber reload: reject--\n",
2583 reject--;
2584 overall += LRA_LOSER_COST_FACTOR - 1;
2586 else
2588 /* We need to reload early clobbered register and the
2589 matched registers. */
2590 for (j = 0; j < n_operands; j++)
2591 if (curr_alt_matches[j] == i)
2593 curr_alt_match_win[j] = false;
2594 losers++;
2595 overall += LRA_LOSER_COST_FACTOR;
2597 if (! curr_alt_match_win[i])
2598 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2599 else
2601 /* Remember pseudos used for match reloads are never
2602 inherited. */
2603 lra_assert (curr_alt_matches[i] >= 0);
2604 curr_alt_win[curr_alt_matches[i]] = false;
2606 curr_alt_win[i] = curr_alt_match_win[i] = false;
2607 losers++;
2608 /* Early clobber was already reflected in REJECT. */
2609 lra_assert (reject > 0);
2610 if (lra_dump_file != NULL)
2611 fprintf
2612 (lra_dump_file,
2613 " %d Matched conflict early clobber reloads:"
2614 "reject--\n",
2616 reject--;
2617 overall += LRA_LOSER_COST_FACTOR - 1;
2620 if (lra_dump_file != NULL)
2621 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2622 nalt, overall, losers, reload_nregs);
2624 /* If this alternative can be made to work by reloading, and it
2625 needs less reloading than the others checked so far, record
2626 it as the chosen goal for reloading. */
2627 if ((best_losers != 0 && losers == 0)
2628 || (((best_losers == 0 && losers == 0)
2629 || (best_losers != 0 && losers != 0))
2630 && (best_overall > overall
2631 || (best_overall == overall
2632 /* If the cost of the reloads is the same,
2633 prefer alternative which requires minimal
2634 number of reload regs. */
2635 && (reload_nregs < best_reload_nregs
2636 || (reload_nregs == best_reload_nregs
2637 && (best_reload_sum < reload_sum
2638 || (best_reload_sum == reload_sum
2639 && nalt < goal_alt_number))))))))
2641 for (nop = 0; nop < n_operands; nop++)
2643 goal_alt_win[nop] = curr_alt_win[nop];
2644 goal_alt_match_win[nop] = curr_alt_match_win[nop];
2645 goal_alt_matches[nop] = curr_alt_matches[nop];
2646 goal_alt[nop] = curr_alt[nop];
2647 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
2649 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
2650 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
2651 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
2652 goal_alt_swapped = curr_swapped;
2653 best_overall = overall;
2654 best_losers = losers;
2655 best_reload_nregs = reload_nregs;
2656 best_reload_sum = reload_sum;
2657 goal_alt_number = nalt;
2659 if (losers == 0)
2660 /* Everything is satisfied. Do not process alternatives
2661 anymore. */
2662 break;
2663 fail:
2666 return ok_p;
2669 /* Make reload base reg from address AD. */
2670 static rtx
2671 base_to_reg (struct address_info *ad)
2673 enum reg_class cl;
2674 int code = -1;
2675 rtx new_inner = NULL_RTX;
2676 rtx new_reg = NULL_RTX;
2677 rtx_insn *insn;
2678 rtx_insn *last_insn = get_last_insn();
2680 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
2681 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
2682 get_index_code (ad));
2683 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
2684 cl, "base");
2685 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
2686 ad->disp_term == NULL
2687 ? gen_int_mode (0, ad->mode)
2688 : *ad->disp_term);
2689 if (!valid_address_p (ad->mode, new_inner, ad->as))
2690 return NULL_RTX;
2691 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base_term));
2692 code = recog_memoized (insn);
2693 if (code < 0)
2695 delete_insns_since (last_insn);
2696 return NULL_RTX;
2699 return new_inner;
2702 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2703 static rtx
2704 base_plus_disp_to_reg (struct address_info *ad)
2706 enum reg_class cl;
2707 rtx new_reg;
2709 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
2710 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
2711 get_index_code (ad));
2712 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
2713 cl, "base + disp");
2714 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term);
2715 return new_reg;
2718 /* Make reload of index part of address AD. Return the new
2719 pseudo. */
2720 static rtx
2721 index_part_to_reg (struct address_info *ad)
2723 rtx new_reg;
2725 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
2726 INDEX_REG_CLASS, "index term");
2727 expand_mult (GET_MODE (*ad->index), *ad->index_term,
2728 GEN_INT (get_index_scale (ad)), new_reg, 1);
2729 return new_reg;
2732 /* Return true if we can add a displacement to address AD, even if that
2733 makes the address invalid. The fix-up code requires any new address
2734 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2735 static bool
2736 can_add_disp_p (struct address_info *ad)
2738 return (!ad->autoinc_p
2739 && ad->segment == NULL
2740 && ad->base == ad->base_term
2741 && ad->disp == ad->disp_term);
2744 /* Make equiv substitution in address AD. Return true if a substitution
2745 was made. */
2746 static bool
2747 equiv_address_substitution (struct address_info *ad)
2749 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
2750 HOST_WIDE_INT disp, scale;
2751 bool change_p;
2753 base_term = strip_subreg (ad->base_term);
2754 if (base_term == NULL)
2755 base_reg = new_base_reg = NULL_RTX;
2756 else
2758 base_reg = *base_term;
2759 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
2761 index_term = strip_subreg (ad->index_term);
2762 if (index_term == NULL)
2763 index_reg = new_index_reg = NULL_RTX;
2764 else
2766 index_reg = *index_term;
2767 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
2769 if (base_reg == new_base_reg && index_reg == new_index_reg)
2770 return false;
2771 disp = 0;
2772 change_p = false;
2773 if (lra_dump_file != NULL)
2775 fprintf (lra_dump_file, "Changing address in insn %d ",
2776 INSN_UID (curr_insn));
2777 dump_value_slim (lra_dump_file, *ad->outer, 1);
2779 if (base_reg != new_base_reg)
2781 if (REG_P (new_base_reg))
2783 *base_term = new_base_reg;
2784 change_p = true;
2786 else if (GET_CODE (new_base_reg) == PLUS
2787 && REG_P (XEXP (new_base_reg, 0))
2788 && CONST_INT_P (XEXP (new_base_reg, 1))
2789 && can_add_disp_p (ad))
2791 disp += INTVAL (XEXP (new_base_reg, 1));
2792 *base_term = XEXP (new_base_reg, 0);
2793 change_p = true;
2795 if (ad->base_term2 != NULL)
2796 *ad->base_term2 = *ad->base_term;
2798 if (index_reg != new_index_reg)
2800 if (REG_P (new_index_reg))
2802 *index_term = new_index_reg;
2803 change_p = true;
2805 else if (GET_CODE (new_index_reg) == PLUS
2806 && REG_P (XEXP (new_index_reg, 0))
2807 && CONST_INT_P (XEXP (new_index_reg, 1))
2808 && can_add_disp_p (ad)
2809 && (scale = get_index_scale (ad)))
2811 disp += INTVAL (XEXP (new_index_reg, 1)) * scale;
2812 *index_term = XEXP (new_index_reg, 0);
2813 change_p = true;
2816 if (disp != 0)
2818 if (ad->disp != NULL)
2819 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
2820 else
2822 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
2823 update_address (ad);
2825 change_p = true;
2827 if (lra_dump_file != NULL)
2829 if (! change_p)
2830 fprintf (lra_dump_file, " -- no change\n");
2831 else
2833 fprintf (lra_dump_file, " on equiv ");
2834 dump_value_slim (lra_dump_file, *ad->outer, 1);
2835 fprintf (lra_dump_file, "\n");
2838 return change_p;
2841 /* Major function to make reloads for an address in operand NOP or
2842 check its correctness (If CHECK_ONLY_P is true). The supported
2843 cases are:
2845 1) an address that existed before LRA started, at which point it
2846 must have been valid. These addresses are subject to elimination
2847 and may have become invalid due to the elimination offset being out
2848 of range.
2850 2) an address created by forcing a constant to memory
2851 (force_const_to_mem). The initial form of these addresses might
2852 not be valid, and it is this function's job to make them valid.
2854 3) a frame address formed from a register and a (possibly zero)
2855 constant offset. As above, these addresses might not be valid and
2856 this function must make them so.
2858 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2859 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2860 address. Return true for any RTL change.
2862 The function is a helper function which does not produce all
2863 transformations (when CHECK_ONLY_P is false) which can be
2864 necessary. It does just basic steps. To do all necessary
2865 transformations use function process_address. */
2866 static bool
2867 process_address_1 (int nop, bool check_only_p,
2868 rtx_insn **before, rtx_insn **after)
2870 struct address_info ad;
2871 rtx new_reg;
2872 rtx op = *curr_id->operand_loc[nop];
2873 const char *constraint = curr_static_id->operand[nop].constraint;
2874 enum constraint_num cn = lookup_constraint (constraint);
2875 bool change_p = false;
2877 if (insn_extra_address_constraint (cn))
2878 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
2879 else if (MEM_P (op))
2880 decompose_mem_address (&ad, op);
2881 else if (GET_CODE (op) == SUBREG
2882 && MEM_P (SUBREG_REG (op)))
2883 decompose_mem_address (&ad, SUBREG_REG (op));
2884 else
2885 return false;
2886 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2887 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2888 when INDEX_REG_CLASS is a single register class. */
2889 if (ad.base_term != NULL
2890 && ad.index_term != NULL
2891 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
2892 && REG_P (*ad.base_term)
2893 && REG_P (*ad.index_term)
2894 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
2895 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
2897 std::swap (ad.base, ad.index);
2898 std::swap (ad.base_term, ad.index_term);
2900 if (! check_only_p)
2901 change_p = equiv_address_substitution (&ad);
2902 if (ad.base_term != NULL
2903 && (process_addr_reg
2904 (ad.base_term, check_only_p, before,
2905 (ad.autoinc_p
2906 && !(REG_P (*ad.base_term)
2907 && find_regno_note (curr_insn, REG_DEAD,
2908 REGNO (*ad.base_term)) != NULL_RTX)
2909 ? after : NULL),
2910 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
2911 get_index_code (&ad)))))
2913 change_p = true;
2914 if (ad.base_term2 != NULL)
2915 *ad.base_term2 = *ad.base_term;
2917 if (ad.index_term != NULL
2918 && process_addr_reg (ad.index_term, check_only_p,
2919 before, NULL, INDEX_REG_CLASS))
2920 change_p = true;
2922 /* Target hooks sometimes don't treat extra-constraint addresses as
2923 legitimate address_operands, so handle them specially. */
2924 if (insn_extra_address_constraint (cn)
2925 && satisfies_address_constraint_p (&ad, cn))
2926 return change_p;
2928 if (check_only_p)
2929 return change_p;
2931 /* There are three cases where the shape of *AD.INNER may now be invalid:
2933 1) the original address was valid, but either elimination or
2934 equiv_address_substitution was applied and that made
2935 the address invalid.
2937 2) the address is an invalid symbolic address created by
2938 force_const_to_mem.
2940 3) the address is a frame address with an invalid offset.
2942 4) the address is a frame address with an invalid base.
2944 All these cases involve a non-autoinc address, so there is no
2945 point revalidating other types. */
2946 if (ad.autoinc_p || valid_address_p (&ad))
2947 return change_p;
2949 /* Any index existed before LRA started, so we can assume that the
2950 presence and shape of the index is valid. */
2951 push_to_sequence (*before);
2952 lra_assert (ad.disp == ad.disp_term);
2953 if (ad.base == NULL)
2955 if (ad.index == NULL)
2957 int code = -1;
2958 enum reg_class cl = base_reg_class (ad.mode, ad.as,
2959 SCRATCH, SCRATCH);
2960 rtx addr = *ad.inner;
2962 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
2963 #ifdef HAVE_lo_sum
2965 rtx_insn *insn;
2966 rtx_insn *last = get_last_insn ();
2968 /* addr => lo_sum (new_base, addr), case (2) above. */
2969 insn = emit_insn (gen_rtx_SET
2970 (new_reg,
2971 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
2972 code = recog_memoized (insn);
2973 if (code >= 0)
2975 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
2976 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
2978 /* Try to put lo_sum into register. */
2979 insn = emit_insn (gen_rtx_SET
2980 (new_reg,
2981 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
2982 code = recog_memoized (insn);
2983 if (code >= 0)
2985 *ad.inner = new_reg;
2986 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
2988 *ad.inner = addr;
2989 code = -1;
2995 if (code < 0)
2996 delete_insns_since (last);
2998 #endif
2999 if (code < 0)
3001 /* addr => new_base, case (2) above. */
3002 lra_emit_move (new_reg, addr);
3003 *ad.inner = new_reg;
3006 else
3008 /* index * scale + disp => new base + index * scale,
3009 case (1) above. */
3010 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3011 GET_CODE (*ad.index));
3013 lra_assert (INDEX_REG_CLASS != NO_REGS);
3014 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3015 lra_emit_move (new_reg, *ad.disp);
3016 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3017 new_reg, *ad.index);
3020 else if (ad.index == NULL)
3022 int regno;
3023 enum reg_class cl;
3024 rtx set;
3025 rtx_insn *insns, *last_insn;
3026 /* Try to reload base into register only if the base is invalid
3027 for the address but with valid offset, case (4) above. */
3028 start_sequence ();
3029 new_reg = base_to_reg (&ad);
3031 /* base + disp => new base, cases (1) and (3) above. */
3032 /* Another option would be to reload the displacement into an
3033 index register. However, postreload has code to optimize
3034 address reloads that have the same base and different
3035 displacements, so reloading into an index register would
3036 not necessarily be a win. */
3037 if (new_reg == NULL_RTX)
3038 new_reg = base_plus_disp_to_reg (&ad);
3039 insns = get_insns ();
3040 last_insn = get_last_insn ();
3041 /* If we generated at least two insns, try last insn source as
3042 an address. If we succeed, we generate one less insn. */
3043 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX
3044 && GET_CODE (SET_SRC (set)) == PLUS
3045 && REG_P (XEXP (SET_SRC (set), 0))
3046 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3048 *ad.inner = SET_SRC (set);
3049 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3051 *ad.base_term = XEXP (SET_SRC (set), 0);
3052 *ad.disp_term = XEXP (SET_SRC (set), 1);
3053 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3054 get_index_code (&ad));
3055 regno = REGNO (*ad.base_term);
3056 if (regno >= FIRST_PSEUDO_REGISTER
3057 && cl != lra_get_allocno_class (regno))
3058 lra_change_class (regno, cl, " Change to", true);
3059 new_reg = SET_SRC (set);
3060 delete_insns_since (PREV_INSN (last_insn));
3063 /* Try if target can split displacement into legitimite new disp
3064 and offset. If it's the case, we replace the last insn with
3065 insns for base + offset => new_reg and set new_reg + new disp
3066 to *ad.inner. */
3067 last_insn = get_last_insn ();
3068 if ((set = single_set (last_insn)) != NULL_RTX
3069 && GET_CODE (SET_SRC (set)) == PLUS
3070 && REG_P (XEXP (SET_SRC (set), 0))
3071 && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER
3072 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
3074 rtx addend, disp = XEXP (SET_SRC (set), 1);
3075 if (targetm.legitimize_address_displacement (&disp, &addend,
3076 ad.mode))
3078 rtx_insn *new_insns;
3079 start_sequence ();
3080 lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend);
3081 new_insns = get_insns ();
3082 end_sequence ();
3083 new_reg = gen_rtx_PLUS (Pmode, new_reg, disp);
3084 delete_insns_since (PREV_INSN (last_insn));
3085 add_insn (new_insns);
3086 insns = get_insns ();
3089 end_sequence ();
3090 emit_insn (insns);
3091 *ad.inner = new_reg;
3093 else if (ad.disp_term != NULL)
3095 /* base + scale * index + disp => new base + scale * index,
3096 case (1) above. */
3097 new_reg = base_plus_disp_to_reg (&ad);
3098 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3099 new_reg, *ad.index);
3101 else if (get_index_scale (&ad) == 1)
3103 /* The last transformation to one reg will be made in
3104 curr_insn_transform function. */
3105 end_sequence ();
3106 return false;
3108 else
3110 /* base + scale * index => base + new_reg,
3111 case (1) above.
3112 Index part of address may become invalid. For example, we
3113 changed pseudo on the equivalent memory and a subreg of the
3114 pseudo onto the memory of different mode for which the scale is
3115 prohibitted. */
3116 new_reg = index_part_to_reg (&ad);
3117 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3118 *ad.base_term, new_reg);
3120 *before = get_insns ();
3121 end_sequence ();
3122 return true;
3125 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3126 Use process_address_1 as a helper function. Return true for any
3127 RTL changes.
3129 If CHECK_ONLY_P is true, just check address correctness. Return
3130 false if the address correct. */
3131 static bool
3132 process_address (int nop, bool check_only_p,
3133 rtx_insn **before, rtx_insn **after)
3135 bool res = false;
3137 while (process_address_1 (nop, check_only_p, before, after))
3139 if (check_only_p)
3140 return true;
3141 res = true;
3143 return res;
3146 /* Emit insns to reload VALUE into a new register. VALUE is an
3147 auto-increment or auto-decrement RTX whose operand is a register or
3148 memory location; so reloading involves incrementing that location.
3149 IN is either identical to VALUE, or some cheaper place to reload
3150 value being incremented/decremented from.
3152 INC_AMOUNT is the number to increment or decrement by (always
3153 positive and ignored for POST_MODIFY/PRE_MODIFY).
3155 Return pseudo containing the result. */
3156 static rtx
3157 emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount)
3159 /* REG or MEM to be copied and incremented. */
3160 rtx incloc = XEXP (value, 0);
3161 /* Nonzero if increment after copying. */
3162 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3163 || GET_CODE (value) == POST_MODIFY);
3164 rtx_insn *last;
3165 rtx inc;
3166 rtx_insn *add_insn;
3167 int code;
3168 rtx real_in = in == value ? incloc : in;
3169 rtx result;
3170 bool plus_p = true;
3172 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3174 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3175 || GET_CODE (XEXP (value, 1)) == MINUS);
3176 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3177 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3178 inc = XEXP (XEXP (value, 1), 1);
3180 else
3182 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3183 inc_amount = -inc_amount;
3185 inc = GEN_INT (inc_amount);
3188 if (! post && REG_P (incloc))
3189 result = incloc;
3190 else
3191 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3192 "INC/DEC result");
3194 if (real_in != result)
3196 /* First copy the location to the result register. */
3197 lra_assert (REG_P (result));
3198 emit_insn (gen_move_insn (result, real_in));
3201 /* We suppose that there are insns to add/sub with the constant
3202 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3203 old reload worked with this assumption. If the assumption
3204 becomes wrong, we should use approach in function
3205 base_plus_disp_to_reg. */
3206 if (in == value)
3208 /* See if we can directly increment INCLOC. */
3209 last = get_last_insn ();
3210 add_insn = emit_insn (plus_p
3211 ? gen_add2_insn (incloc, inc)
3212 : gen_sub2_insn (incloc, inc));
3214 code = recog_memoized (add_insn);
3215 if (code >= 0)
3217 if (! post && result != incloc)
3218 emit_insn (gen_move_insn (result, incloc));
3219 return result;
3221 delete_insns_since (last);
3224 /* If couldn't do the increment directly, must increment in RESULT.
3225 The way we do this depends on whether this is pre- or
3226 post-increment. For pre-increment, copy INCLOC to the reload
3227 register, increment it there, then save back. */
3228 if (! post)
3230 if (real_in != result)
3231 emit_insn (gen_move_insn (result, real_in));
3232 if (plus_p)
3233 emit_insn (gen_add2_insn (result, inc));
3234 else
3235 emit_insn (gen_sub2_insn (result, inc));
3236 if (result != incloc)
3237 emit_insn (gen_move_insn (incloc, result));
3239 else
3241 /* Post-increment.
3243 Because this might be a jump insn or a compare, and because
3244 RESULT may not be available after the insn in an input
3245 reload, we must do the incrementing before the insn being
3246 reloaded for.
3248 We have already copied IN to RESULT. Increment the copy in
3249 RESULT, save that back, then decrement RESULT so it has
3250 the original value. */
3251 if (plus_p)
3252 emit_insn (gen_add2_insn (result, inc));
3253 else
3254 emit_insn (gen_sub2_insn (result, inc));
3255 emit_insn (gen_move_insn (incloc, result));
3256 /* Restore non-modified value for the result. We prefer this
3257 way because it does not require an additional hard
3258 register. */
3259 if (plus_p)
3261 if (CONST_INT_P (inc))
3262 emit_insn (gen_add2_insn (result,
3263 gen_int_mode (-INTVAL (inc),
3264 GET_MODE (result))));
3265 else
3266 emit_insn (gen_sub2_insn (result, inc));
3268 else
3269 emit_insn (gen_add2_insn (result, inc));
3271 return result;
3274 /* Return true if the current move insn does not need processing as we
3275 already know that it satisfies its constraints. */
3276 static bool
3277 simple_move_p (void)
3279 rtx dest, src;
3280 enum reg_class dclass, sclass;
3282 lra_assert (curr_insn_set != NULL_RTX);
3283 dest = SET_DEST (curr_insn_set);
3284 src = SET_SRC (curr_insn_set);
3285 return ((dclass = get_op_class (dest)) != NO_REGS
3286 && (sclass = get_op_class (src)) != NO_REGS
3287 /* The backend guarantees that register moves of cost 2
3288 never need reloads. */
3289 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3292 /* Swap operands NOP and NOP + 1. */
3293 static inline void
3294 swap_operands (int nop)
3296 machine_mode mode = curr_operand_mode[nop];
3297 curr_operand_mode[nop] = curr_operand_mode[nop + 1];
3298 curr_operand_mode[nop + 1] = mode;
3299 mode = original_subreg_reg_mode[nop];
3300 original_subreg_reg_mode[nop] = original_subreg_reg_mode[nop + 1];
3301 original_subreg_reg_mode[nop + 1] = mode;
3302 rtx x = *curr_id->operand_loc[nop];
3303 *curr_id->operand_loc[nop] = *curr_id->operand_loc[nop + 1];
3304 *curr_id->operand_loc[nop + 1] = x;
3305 /* Swap the duplicates too. */
3306 lra_update_dup (curr_id, nop);
3307 lra_update_dup (curr_id, nop + 1);
3310 /* Main entry point of the constraint code: search the body of the
3311 current insn to choose the best alternative. It is mimicking insn
3312 alternative cost calculation model of former reload pass. That is
3313 because machine descriptions were written to use this model. This
3314 model can be changed in future. Make commutative operand exchange
3315 if it is chosen.
3317 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3318 constraints. Return true if any change happened during function
3319 call.
3321 If CHECK_ONLY_P is true then don't do any transformation. Just
3322 check that the insn satisfies all constraints. If the insn does
3323 not satisfy any constraint, return true. */
3324 static bool
3325 curr_insn_transform (bool check_only_p)
3327 int i, j, k;
3328 int n_operands;
3329 int n_alternatives;
3330 int commutative;
3331 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3332 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3333 rtx_insn *before, *after;
3334 bool alt_p = false;
3335 /* Flag that the insn has been changed through a transformation. */
3336 bool change_p;
3337 bool sec_mem_p;
3338 #ifdef SECONDARY_MEMORY_NEEDED
3339 bool use_sec_mem_p;
3340 #endif
3341 int max_regno_before;
3342 int reused_alternative_num;
3344 curr_insn_set = single_set (curr_insn);
3345 if (curr_insn_set != NULL_RTX && simple_move_p ())
3346 return false;
3348 no_input_reloads_p = no_output_reloads_p = false;
3349 goal_alt_number = -1;
3350 change_p = sec_mem_p = false;
3351 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3352 reloads; neither are insns that SET cc0. Insns that use CC0 are
3353 not allowed to have any input reloads. */
3354 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3355 no_output_reloads_p = true;
3357 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3358 no_input_reloads_p = true;
3359 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3360 no_output_reloads_p = true;
3362 n_operands = curr_static_id->n_operands;
3363 n_alternatives = curr_static_id->n_alternatives;
3365 /* Just return "no reloads" if insn has no operands with
3366 constraints. */
3367 if (n_operands == 0 || n_alternatives == 0)
3368 return false;
3370 max_regno_before = max_reg_num ();
3372 for (i = 0; i < n_operands; i++)
3374 goal_alt_matched[i][0] = -1;
3375 goal_alt_matches[i] = -1;
3378 commutative = curr_static_id->commutative;
3380 /* Now see what we need for pseudos that didn't get hard regs or got
3381 the wrong kind of hard reg. For this, we must consider all the
3382 operands together against the register constraints. */
3384 best_losers = best_overall = INT_MAX;
3385 best_reload_sum = 0;
3387 curr_swapped = false;
3388 goal_alt_swapped = false;
3390 if (! check_only_p)
3391 /* Make equivalence substitution and memory subreg elimination
3392 before address processing because an address legitimacy can
3393 depend on memory mode. */
3394 for (i = 0; i < n_operands; i++)
3396 rtx op = *curr_id->operand_loc[i];
3397 rtx subst, old = op;
3398 bool op_change_p = false;
3400 if (GET_CODE (old) == SUBREG)
3401 old = SUBREG_REG (old);
3402 subst = get_equiv_with_elimination (old, curr_insn);
3403 original_subreg_reg_mode[i] = VOIDmode;
3404 if (subst != old)
3406 subst = copy_rtx (subst);
3407 lra_assert (REG_P (old));
3408 if (GET_CODE (op) != SUBREG)
3409 *curr_id->operand_loc[i] = subst;
3410 else
3412 SUBREG_REG (op) = subst;
3413 if (GET_MODE (subst) == VOIDmode)
3414 original_subreg_reg_mode[i] = GET_MODE (old);
3416 if (lra_dump_file != NULL)
3418 fprintf (lra_dump_file,
3419 "Changing pseudo %d in operand %i of insn %u on equiv ",
3420 REGNO (old), i, INSN_UID (curr_insn));
3421 dump_value_slim (lra_dump_file, subst, 1);
3422 fprintf (lra_dump_file, "\n");
3424 op_change_p = change_p = true;
3426 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3428 change_p = true;
3429 lra_update_dup (curr_id, i);
3433 /* Reload address registers and displacements. We do it before
3434 finding an alternative because of memory constraints. */
3435 before = after = NULL;
3436 for (i = 0; i < n_operands; i++)
3437 if (! curr_static_id->operand[i].is_operator
3438 && process_address (i, check_only_p, &before, &after))
3440 if (check_only_p)
3441 return true;
3442 change_p = true;
3443 lra_update_dup (curr_id, i);
3446 if (change_p)
3447 /* If we've changed the instruction then any alternative that
3448 we chose previously may no longer be valid. */
3449 lra_set_used_insn_alternative (curr_insn, -1);
3451 if (! check_only_p && curr_insn_set != NULL_RTX
3452 && check_and_process_move (&change_p, &sec_mem_p))
3453 return change_p;
3455 try_swapped:
3457 reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative;
3458 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3459 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3460 reused_alternative_num, INSN_UID (curr_insn));
3462 if (process_alt_operands (reused_alternative_num))
3463 alt_p = true;
3465 if (check_only_p)
3466 return ! alt_p || best_losers != 0;
3468 /* If insn is commutative (it's safe to exchange a certain pair of
3469 operands) then we need to try each alternative twice, the second
3470 time matching those two operands as if we had exchanged them. To
3471 do this, really exchange them in operands.
3473 If we have just tried the alternatives the second time, return
3474 operands to normal and drop through. */
3476 if (reused_alternative_num < 0 && commutative >= 0)
3478 curr_swapped = !curr_swapped;
3479 if (curr_swapped)
3481 swap_operands (commutative);
3482 goto try_swapped;
3484 else
3485 swap_operands (commutative);
3488 if (! alt_p && ! sec_mem_p)
3490 /* No alternative works with reloads?? */
3491 if (INSN_CODE (curr_insn) >= 0)
3492 fatal_insn ("unable to generate reloads for:", curr_insn);
3493 error_for_asm (curr_insn,
3494 "inconsistent operand constraints in an %<asm%>");
3495 /* Avoid further trouble with this insn. */
3496 PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3497 lra_invalidate_insn_data (curr_insn);
3498 return true;
3501 /* If the best alternative is with operands 1 and 2 swapped, swap
3502 them. Update the operand numbers of any reloads already
3503 pushed. */
3505 if (goal_alt_swapped)
3507 if (lra_dump_file != NULL)
3508 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3509 INSN_UID (curr_insn));
3511 /* Swap the duplicates too. */
3512 swap_operands (commutative);
3513 change_p = true;
3516 #ifdef SECONDARY_MEMORY_NEEDED
3517 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3518 too conservatively. So we use the secondary memory only if there
3519 is no any alternative without reloads. */
3520 use_sec_mem_p = false;
3521 if (! alt_p)
3522 use_sec_mem_p = true;
3523 else if (sec_mem_p)
3525 for (i = 0; i < n_operands; i++)
3526 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3527 break;
3528 use_sec_mem_p = i < n_operands;
3531 if (use_sec_mem_p)
3533 rtx new_reg, src, dest, rld;
3534 machine_mode sec_mode, rld_mode;
3536 lra_assert (sec_mem_p);
3537 lra_assert (curr_static_id->operand[0].type == OP_OUT
3538 && curr_static_id->operand[1].type == OP_IN);
3539 dest = *curr_id->operand_loc[0];
3540 src = *curr_id->operand_loc[1];
3541 rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src))
3542 ? dest : src);
3543 rld_mode = GET_MODE (rld);
3544 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3545 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode);
3546 #else
3547 sec_mode = rld_mode;
3548 #endif
3549 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3550 NO_REGS, "secondary");
3551 /* If the mode is changed, it should be wider. */
3552 lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode));
3553 if (sec_mode != rld_mode)
3555 /* If the target says specifically to use another mode for
3556 secondary memory moves we can not reuse the original
3557 insn. */
3558 after = emit_spill_move (false, new_reg, dest);
3559 lra_process_new_insns (curr_insn, NULL, after,
3560 "Inserting the sec. move");
3561 /* We may have non null BEFORE here (e.g. after address
3562 processing. */
3563 push_to_sequence (before);
3564 before = emit_spill_move (true, new_reg, src);
3565 emit_insn (before);
3566 before = get_insns ();
3567 end_sequence ();
3568 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
3569 lra_set_insn_deleted (curr_insn);
3571 else if (dest == rld)
3573 *curr_id->operand_loc[0] = new_reg;
3574 after = emit_spill_move (false, new_reg, dest);
3575 lra_process_new_insns (curr_insn, NULL, after,
3576 "Inserting the sec. move");
3578 else
3580 *curr_id->operand_loc[1] = new_reg;
3581 /* See comments above. */
3582 push_to_sequence (before);
3583 before = emit_spill_move (true, new_reg, src);
3584 emit_insn (before);
3585 before = get_insns ();
3586 end_sequence ();
3587 lra_process_new_insns (curr_insn, before, NULL,
3588 "Inserting the sec. move");
3590 lra_update_insn_regno_info (curr_insn);
3591 return true;
3593 #endif
3595 lra_assert (goal_alt_number >= 0);
3596 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
3598 if (lra_dump_file != NULL)
3600 const char *p;
3602 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
3603 goal_alt_number, INSN_UID (curr_insn));
3604 for (i = 0; i < n_operands; i++)
3606 p = (curr_static_id->operand_alternative
3607 [goal_alt_number * n_operands + i].constraint);
3608 if (*p == '\0')
3609 continue;
3610 fprintf (lra_dump_file, " (%d) ", i);
3611 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
3612 fputc (*p, lra_dump_file);
3614 if (INSN_CODE (curr_insn) >= 0
3615 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
3616 fprintf (lra_dump_file, " {%s}", p);
3617 if (curr_id->sp_offset != 0)
3618 fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)",
3619 curr_id->sp_offset);
3620 fprintf (lra_dump_file, "\n");
3623 /* Right now, for any pair of operands I and J that are required to
3624 match, with J < I, goal_alt_matches[I] is J. Add I to
3625 goal_alt_matched[J]. */
3627 for (i = 0; i < n_operands; i++)
3628 if ((j = goal_alt_matches[i]) >= 0)
3630 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
3632 /* We allow matching one output operand and several input
3633 operands. */
3634 lra_assert (k == 0
3635 || (curr_static_id->operand[j].type == OP_OUT
3636 && curr_static_id->operand[i].type == OP_IN
3637 && (curr_static_id->operand
3638 [goal_alt_matched[j][0]].type == OP_IN)));
3639 goal_alt_matched[j][k] = i;
3640 goal_alt_matched[j][k + 1] = -1;
3643 for (i = 0; i < n_operands; i++)
3644 goal_alt_win[i] |= goal_alt_match_win[i];
3646 /* Any constants that aren't allowed and can't be reloaded into
3647 registers are here changed into memory references. */
3648 for (i = 0; i < n_operands; i++)
3649 if (goal_alt_win[i])
3651 int regno;
3652 enum reg_class new_class;
3653 rtx reg = *curr_id->operand_loc[i];
3655 if (GET_CODE (reg) == SUBREG)
3656 reg = SUBREG_REG (reg);
3658 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
3660 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
3662 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
3664 lra_assert (ok_p);
3665 lra_change_class (regno, new_class, " Change to", true);
3669 else
3671 const char *constraint;
3672 char c;
3673 rtx op = *curr_id->operand_loc[i];
3674 rtx subreg = NULL_RTX;
3675 machine_mode mode = curr_operand_mode[i];
3677 if (GET_CODE (op) == SUBREG)
3679 subreg = op;
3680 op = SUBREG_REG (op);
3681 mode = GET_MODE (op);
3684 if (CONST_POOL_OK_P (mode, op)
3685 && ((targetm.preferred_reload_class
3686 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
3687 || no_input_reloads_p))
3689 rtx tem = force_const_mem (mode, op);
3691 change_p = true;
3692 if (subreg != NULL_RTX)
3693 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
3695 *curr_id->operand_loc[i] = tem;
3696 lra_update_dup (curr_id, i);
3697 process_address (i, false, &before, &after);
3699 /* If the alternative accepts constant pool refs directly
3700 there will be no reload needed at all. */
3701 if (subreg != NULL_RTX)
3702 continue;
3703 /* Skip alternatives before the one requested. */
3704 constraint = (curr_static_id->operand_alternative
3705 [goal_alt_number * n_operands + i].constraint);
3706 for (;
3707 (c = *constraint) && c != ',' && c != '#';
3708 constraint += CONSTRAINT_LEN (c, constraint))
3710 enum constraint_num cn = lookup_constraint (constraint);
3711 if (insn_extra_memory_constraint (cn)
3712 && satisfies_memory_constraint_p (tem, cn))
3713 break;
3715 if (c == '\0' || c == ',' || c == '#')
3716 continue;
3718 goal_alt_win[i] = true;
3722 for (i = 0; i < n_operands; i++)
3724 int regno;
3725 bool optional_p = false;
3726 rtx old, new_reg;
3727 rtx op = *curr_id->operand_loc[i];
3729 if (goal_alt_win[i])
3731 if (goal_alt[i] == NO_REGS
3732 && REG_P (op)
3733 /* When we assign NO_REGS it means that we will not
3734 assign a hard register to the scratch pseudo by
3735 assigment pass and the scratch pseudo will be
3736 spilled. Spilled scratch pseudos are transformed
3737 back to scratches at the LRA end. */
3738 && lra_former_scratch_operand_p (curr_insn, i))
3740 int regno = REGNO (op);
3741 lra_change_class (regno, NO_REGS, " Change to", true);
3742 if (lra_get_regno_hard_regno (regno) >= 0)
3743 /* We don't have to mark all insn affected by the
3744 spilled pseudo as there is only one such insn, the
3745 current one. */
3746 reg_renumber[regno] = -1;
3748 /* We can do an optional reload. If the pseudo got a hard
3749 reg, we might improve the code through inheritance. If
3750 it does not get a hard register we coalesce memory/memory
3751 moves later. Ignore move insns to avoid cycling. */
3752 if (! lra_simple_p
3753 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
3754 && goal_alt[i] != NO_REGS && REG_P (op)
3755 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
3756 && regno < new_regno_start
3757 && ! lra_former_scratch_p (regno)
3758 && reg_renumber[regno] < 0
3759 /* Check that the optional reload pseudo will be able to
3760 hold given mode value. */
3761 && ! (prohibited_class_reg_set_mode_p
3762 (goal_alt[i], reg_class_contents[goal_alt[i]],
3763 PSEUDO_REGNO_MODE (regno)))
3764 && (curr_insn_set == NULL_RTX
3765 || !((REG_P (SET_SRC (curr_insn_set))
3766 || MEM_P (SET_SRC (curr_insn_set))
3767 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
3768 && (REG_P (SET_DEST (curr_insn_set))
3769 || MEM_P (SET_DEST (curr_insn_set))
3770 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
3771 optional_p = true;
3772 else
3773 continue;
3776 /* Operands that match previous ones have already been handled. */
3777 if (goal_alt_matches[i] >= 0)
3778 continue;
3780 /* We should not have an operand with a non-offsettable address
3781 appearing where an offsettable address will do. It also may
3782 be a case when the address should be special in other words
3783 not a general one (e.g. it needs no index reg). */
3784 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
3786 enum reg_class rclass;
3787 rtx *loc = &XEXP (op, 0);
3788 enum rtx_code code = GET_CODE (*loc);
3790 push_to_sequence (before);
3791 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
3792 MEM, SCRATCH);
3793 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
3794 new_reg = emit_inc (rclass, *loc, *loc,
3795 /* This value does not matter for MODIFY. */
3796 GET_MODE_SIZE (GET_MODE (op)));
3797 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
3798 "offsetable address", &new_reg))
3799 lra_emit_move (new_reg, *loc);
3800 before = get_insns ();
3801 end_sequence ();
3802 *loc = new_reg;
3803 lra_update_dup (curr_id, i);
3805 else if (goal_alt_matched[i][0] == -1)
3807 machine_mode mode;
3808 rtx reg, *loc;
3809 int hard_regno, byte;
3810 enum op_type type = curr_static_id->operand[i].type;
3812 loc = curr_id->operand_loc[i];
3813 mode = curr_operand_mode[i];
3814 if (GET_CODE (*loc) == SUBREG)
3816 reg = SUBREG_REG (*loc);
3817 byte = SUBREG_BYTE (*loc);
3818 if (REG_P (reg)
3819 /* Strict_low_part requires reload the register not
3820 the sub-register. */
3821 && (curr_static_id->operand[i].strict_low
3822 || (GET_MODE_SIZE (mode)
3823 <= GET_MODE_SIZE (GET_MODE (reg))
3824 && (hard_regno
3825 = get_try_hard_regno (REGNO (reg))) >= 0
3826 && (simplify_subreg_regno
3827 (hard_regno,
3828 GET_MODE (reg), byte, mode) < 0)
3829 && (goal_alt[i] == NO_REGS
3830 || (simplify_subreg_regno
3831 (ira_class_hard_regs[goal_alt[i]][0],
3832 GET_MODE (reg), byte, mode) >= 0)))))
3834 if (type == OP_OUT)
3835 type = OP_INOUT;
3836 loc = &SUBREG_REG (*loc);
3837 mode = GET_MODE (*loc);
3840 old = *loc;
3841 if (get_reload_reg (type, mode, old, goal_alt[i],
3842 loc != curr_id->operand_loc[i], "", &new_reg)
3843 && type != OP_OUT)
3845 push_to_sequence (before);
3846 lra_emit_move (new_reg, old);
3847 before = get_insns ();
3848 end_sequence ();
3850 *loc = new_reg;
3851 if (type != OP_IN
3852 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
3854 start_sequence ();
3855 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
3856 emit_insn (after);
3857 after = get_insns ();
3858 end_sequence ();
3859 *loc = new_reg;
3861 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
3862 if (goal_alt_dont_inherit_ops[j] == i)
3864 lra_set_regno_unique_value (REGNO (new_reg));
3865 break;
3867 lra_update_dup (curr_id, i);
3869 else if (curr_static_id->operand[i].type == OP_IN
3870 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3871 == OP_OUT))
3873 /* generate reloads for input and matched outputs. */
3874 match_inputs[0] = i;
3875 match_inputs[1] = -1;
3876 match_reload (goal_alt_matched[i][0], match_inputs,
3877 goal_alt[i], &before, &after);
3879 else if (curr_static_id->operand[i].type == OP_OUT
3880 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3881 == OP_IN))
3882 /* Generate reloads for output and matched inputs. */
3883 match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after);
3884 else if (curr_static_id->operand[i].type == OP_IN
3885 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3886 == OP_IN))
3888 /* Generate reloads for matched inputs. */
3889 match_inputs[0] = i;
3890 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
3891 match_inputs[j + 1] = k;
3892 match_inputs[j + 1] = -1;
3893 match_reload (-1, match_inputs, goal_alt[i], &before, &after);
3895 else
3896 /* We must generate code in any case when function
3897 process_alt_operands decides that it is possible. */
3898 gcc_unreachable ();
3899 if (optional_p)
3901 lra_assert (REG_P (op));
3902 regno = REGNO (op);
3903 op = *curr_id->operand_loc[i]; /* Substitution. */
3904 if (GET_CODE (op) == SUBREG)
3905 op = SUBREG_REG (op);
3906 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
3907 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
3908 lra_reg_info[REGNO (op)].restore_regno = regno;
3909 if (lra_dump_file != NULL)
3910 fprintf (lra_dump_file,
3911 " Making reload reg %d for reg %d optional\n",
3912 REGNO (op), regno);
3915 if (before != NULL_RTX || after != NULL_RTX
3916 || max_regno_before != max_reg_num ())
3917 change_p = true;
3918 if (change_p)
3920 lra_update_operator_dups (curr_id);
3921 /* Something changes -- process the insn. */
3922 lra_update_insn_regno_info (curr_insn);
3924 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
3925 return change_p;
3928 /* Return true if INSN satisfies all constraints. In other words, no
3929 reload insns are needed. */
3930 bool
3931 lra_constrain_insn (rtx_insn *insn)
3933 int saved_new_regno_start = new_regno_start;
3934 int saved_new_insn_uid_start = new_insn_uid_start;
3935 bool change_p;
3937 curr_insn = insn;
3938 curr_id = lra_get_insn_recog_data (curr_insn);
3939 curr_static_id = curr_id->insn_static_data;
3940 new_insn_uid_start = get_max_uid ();
3941 new_regno_start = max_reg_num ();
3942 change_p = curr_insn_transform (true);
3943 new_regno_start = saved_new_regno_start;
3944 new_insn_uid_start = saved_new_insn_uid_start;
3945 return ! change_p;
3948 /* Return true if X is in LIST. */
3949 static bool
3950 in_list_p (rtx x, rtx list)
3952 for (; list != NULL_RTX; list = XEXP (list, 1))
3953 if (XEXP (list, 0) == x)
3954 return true;
3955 return false;
3958 /* Return true if X contains an allocatable hard register (if
3959 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3960 static bool
3961 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
3963 int i, j;
3964 const char *fmt;
3965 enum rtx_code code;
3967 code = GET_CODE (x);
3968 if (REG_P (x))
3970 int regno = REGNO (x);
3971 HARD_REG_SET alloc_regs;
3973 if (hard_reg_p)
3975 if (regno >= FIRST_PSEUDO_REGISTER)
3976 regno = lra_get_regno_hard_regno (regno);
3977 if (regno < 0)
3978 return false;
3979 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
3980 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
3982 else
3984 if (regno < FIRST_PSEUDO_REGISTER)
3985 return false;
3986 if (! spilled_p)
3987 return true;
3988 return lra_get_regno_hard_regno (regno) < 0;
3991 fmt = GET_RTX_FORMAT (code);
3992 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3994 if (fmt[i] == 'e')
3996 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
3997 return true;
3999 else if (fmt[i] == 'E')
4001 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4002 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4003 return true;
4006 return false;
4009 /* Return true if X contains a symbol reg. */
4010 static bool
4011 contains_symbol_ref_p (rtx x)
4013 int i, j;
4014 const char *fmt;
4015 enum rtx_code code;
4017 code = GET_CODE (x);
4018 if (code == SYMBOL_REF)
4019 return true;
4020 fmt = GET_RTX_FORMAT (code);
4021 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4023 if (fmt[i] == 'e')
4025 if (contains_symbol_ref_p (XEXP (x, i)))
4026 return true;
4028 else if (fmt[i] == 'E')
4030 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4031 if (contains_symbol_ref_p (XVECEXP (x, i, j)))
4032 return true;
4035 return false;
4038 /* Process all regs in location *LOC and change them on equivalent
4039 substitution. Return true if any change was done. */
4040 static bool
4041 loc_equivalence_change_p (rtx *loc)
4043 rtx subst, reg, x = *loc;
4044 bool result = false;
4045 enum rtx_code code = GET_CODE (x);
4046 const char *fmt;
4047 int i, j;
4049 if (code == SUBREG)
4051 reg = SUBREG_REG (x);
4052 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4053 && GET_MODE (subst) == VOIDmode)
4055 /* We cannot reload debug location. Simplify subreg here
4056 while we know the inner mode. */
4057 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4058 GET_MODE (reg), SUBREG_BYTE (x));
4059 return true;
4062 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4064 *loc = subst;
4065 return true;
4068 /* Scan all the operand sub-expressions. */
4069 fmt = GET_RTX_FORMAT (code);
4070 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4072 if (fmt[i] == 'e')
4073 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4074 else if (fmt[i] == 'E')
4075 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4076 result
4077 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4079 return result;
4082 /* Similar to loc_equivalence_change_p, but for use as
4083 simplify_replace_fn_rtx callback. DATA is insn for which the
4084 elimination is done. If it null we don't do the elimination. */
4085 static rtx
4086 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4088 if (!REG_P (loc))
4089 return NULL_RTX;
4091 rtx subst = (data == NULL
4092 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4093 if (subst != loc)
4094 return subst;
4096 return NULL_RTX;
4099 /* Maximum number of generated reload insns per an insn. It is for
4100 preventing this pass cycling in a bug case. */
4101 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4103 /* The current iteration number of this LRA pass. */
4104 int lra_constraint_iter;
4106 /* True if we substituted equiv which needs checking register
4107 allocation correctness because the equivalent value contains
4108 allocatable hard registers or when we restore multi-register
4109 pseudo. */
4110 bool lra_risky_transformations_p;
4112 /* Return true if REGNO is referenced in more than one block. */
4113 static bool
4114 multi_block_pseudo_p (int regno)
4116 basic_block bb = NULL;
4117 unsigned int uid;
4118 bitmap_iterator bi;
4120 if (regno < FIRST_PSEUDO_REGISTER)
4121 return false;
4123 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4124 if (bb == NULL)
4125 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4126 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4127 return true;
4128 return false;
4131 /* Return true if LIST contains a deleted insn. */
4132 static bool
4133 contains_deleted_insn_p (rtx_insn_list *list)
4135 for (; list != NULL_RTX; list = list->next ())
4136 if (NOTE_P (list->insn ())
4137 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4138 return true;
4139 return false;
4142 /* Return true if X contains a pseudo dying in INSN. */
4143 static bool
4144 dead_pseudo_p (rtx x, rtx_insn *insn)
4146 int i, j;
4147 const char *fmt;
4148 enum rtx_code code;
4150 if (REG_P (x))
4151 return (insn != NULL_RTX
4152 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4153 code = GET_CODE (x);
4154 fmt = GET_RTX_FORMAT (code);
4155 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4157 if (fmt[i] == 'e')
4159 if (dead_pseudo_p (XEXP (x, i), insn))
4160 return true;
4162 else if (fmt[i] == 'E')
4164 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4165 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4166 return true;
4169 return false;
4172 /* Return true if INSN contains a dying pseudo in INSN right hand
4173 side. */
4174 static bool
4175 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4177 rtx set = single_set (insn);
4179 gcc_assert (set != NULL);
4180 return dead_pseudo_p (SET_SRC (set), insn);
4183 /* Return true if any init insn of REGNO contains a dying pseudo in
4184 insn right hand side. */
4185 static bool
4186 init_insn_rhs_dead_pseudo_p (int regno)
4188 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4190 if (insns == NULL)
4191 return false;
4192 for (; insns != NULL_RTX; insns = insns->next ())
4193 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4194 return true;
4195 return false;
4198 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4199 reverse only if we have one init insn with given REGNO as a
4200 source. */
4201 static bool
4202 reverse_equiv_p (int regno)
4204 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4205 rtx set;
4207 if (insns == NULL)
4208 return false;
4209 if (! INSN_P (insns->insn ())
4210 || insns->next () != NULL)
4211 return false;
4212 if ((set = single_set (insns->insn ())) == NULL_RTX)
4213 return false;
4214 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4217 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4218 call this function only for non-reverse equivalence. */
4219 static bool
4220 contains_reloaded_insn_p (int regno)
4222 rtx set;
4223 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4225 for (; list != NULL; list = list->next ())
4226 if ((set = single_set (list->insn ())) == NULL_RTX
4227 || ! REG_P (SET_DEST (set))
4228 || (int) REGNO (SET_DEST (set)) != regno)
4229 return true;
4230 return false;
4233 /* Entry function of LRA constraint pass. Return true if the
4234 constraint pass did change the code. */
4235 bool
4236 lra_constraints (bool first_p)
4238 bool changed_p;
4239 int i, hard_regno, new_insns_num;
4240 unsigned int min_len, new_min_len, uid;
4241 rtx set, x, reg, dest_reg;
4242 basic_block last_bb;
4243 bitmap_head equiv_insn_bitmap;
4244 bitmap_iterator bi;
4246 lra_constraint_iter++;
4247 if (lra_dump_file != NULL)
4248 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4249 lra_constraint_iter);
4250 changed_p = false;
4251 if (pic_offset_table_rtx
4252 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4253 lra_risky_transformations_p = true;
4254 else
4255 lra_risky_transformations_p = false;
4256 new_insn_uid_start = get_max_uid ();
4257 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4258 /* Mark used hard regs for target stack size calulations. */
4259 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4260 if (lra_reg_info[i].nrefs != 0
4261 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4263 int j, nregs;
4265 nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode];
4266 for (j = 0; j < nregs; j++)
4267 df_set_regs_ever_live (hard_regno + j, true);
4269 /* Do elimination before the equivalence processing as we can spill
4270 some pseudos during elimination. */
4271 lra_eliminate (false, first_p);
4272 bitmap_initialize (&equiv_insn_bitmap, &reg_obstack);
4273 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4274 if (lra_reg_info[i].nrefs != 0)
4276 ira_reg_equiv[i].profitable_p = true;
4277 reg = regno_reg_rtx[i];
4278 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4280 bool pseudo_p = contains_reg_p (x, false, false);
4282 /* After RTL transformation, we can not guarantee that
4283 pseudo in the substitution was not reloaded which might
4284 make equivalence invalid. For example, in reverse
4285 equiv of p0
4287 p0 <- ...
4289 equiv_mem <- p0
4291 the memory address register was reloaded before the 2nd
4292 insn. */
4293 if ((! first_p && pseudo_p)
4294 /* We don't use DF for compilation speed sake. So it
4295 is problematic to update live info when we use an
4296 equivalence containing pseudos in more than one
4297 BB. */
4298 || (pseudo_p && multi_block_pseudo_p (i))
4299 /* If an init insn was deleted for some reason, cancel
4300 the equiv. We could update the equiv insns after
4301 transformations including an equiv insn deletion
4302 but it is not worthy as such cases are extremely
4303 rare. */
4304 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4305 /* If it is not a reverse equivalence, we check that a
4306 pseudo in rhs of the init insn is not dying in the
4307 insn. Otherwise, the live info at the beginning of
4308 the corresponding BB might be wrong after we
4309 removed the insn. When the equiv can be a
4310 constant, the right hand side of the init insn can
4311 be a pseudo. */
4312 || (! reverse_equiv_p (i)
4313 && (init_insn_rhs_dead_pseudo_p (i)
4314 /* If we reloaded the pseudo in an equivalence
4315 init insn, we can not remove the equiv init
4316 insns and the init insns might write into
4317 const memory in this case. */
4318 || contains_reloaded_insn_p (i)))
4319 /* Prevent access beyond equivalent memory for
4320 paradoxical subregs. */
4321 || (MEM_P (x)
4322 && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode)
4323 > GET_MODE_SIZE (GET_MODE (x))))
4324 || (pic_offset_table_rtx
4325 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4326 && (targetm.preferred_reload_class
4327 (x, lra_get_allocno_class (i)) == NO_REGS))
4328 || contains_symbol_ref_p (x))))
4329 ira_reg_equiv[i].defined_p = false;
4330 if (contains_reg_p (x, false, true))
4331 ira_reg_equiv[i].profitable_p = false;
4332 if (get_equiv (reg) != reg)
4333 bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4336 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4337 update_equiv (i);
4338 /* We should add all insns containing pseudos which should be
4339 substituted by their equivalences. */
4340 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi)
4341 lra_push_insn_by_uid (uid);
4342 min_len = lra_insn_stack_length ();
4343 new_insns_num = 0;
4344 last_bb = NULL;
4345 changed_p = false;
4346 while ((new_min_len = lra_insn_stack_length ()) != 0)
4348 curr_insn = lra_pop_insn ();
4349 --new_min_len;
4350 curr_bb = BLOCK_FOR_INSN (curr_insn);
4351 if (curr_bb != last_bb)
4353 last_bb = curr_bb;
4354 bb_reload_num = lra_curr_reload_num;
4356 if (min_len > new_min_len)
4358 min_len = new_min_len;
4359 new_insns_num = 0;
4361 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4362 internal_error
4363 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4364 MAX_RELOAD_INSNS_NUMBER);
4365 new_insns_num++;
4366 if (DEBUG_INSN_P (curr_insn))
4368 /* We need to check equivalence in debug insn and change
4369 pseudo to the equivalent value if necessary. */
4370 curr_id = lra_get_insn_recog_data (curr_insn);
4371 if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)))
4373 rtx old = *curr_id->operand_loc[0];
4374 *curr_id->operand_loc[0]
4375 = simplify_replace_fn_rtx (old, NULL_RTX,
4376 loc_equivalence_callback, curr_insn);
4377 if (old != *curr_id->operand_loc[0])
4379 lra_update_insn_regno_info (curr_insn);
4380 changed_p = true;
4384 else if (INSN_P (curr_insn))
4386 if ((set = single_set (curr_insn)) != NULL_RTX)
4388 dest_reg = SET_DEST (set);
4389 /* The equivalence pseudo could be set up as SUBREG in a
4390 case when it is a call restore insn in a mode
4391 different from the pseudo mode. */
4392 if (GET_CODE (dest_reg) == SUBREG)
4393 dest_reg = SUBREG_REG (dest_reg);
4394 if ((REG_P (dest_reg)
4395 && (x = get_equiv (dest_reg)) != dest_reg
4396 /* Remove insns which set up a pseudo whose value
4397 can not be changed. Such insns might be not in
4398 init_insns because we don't update equiv data
4399 during insn transformations.
4401 As an example, let suppose that a pseudo got
4402 hard register and on the 1st pass was not
4403 changed to equivalent constant. We generate an
4404 additional insn setting up the pseudo because of
4405 secondary memory movement. Then the pseudo is
4406 spilled and we use the equiv constant. In this
4407 case we should remove the additional insn and
4408 this insn is not init_insns list. */
4409 && (! MEM_P (x) || MEM_READONLY_P (x)
4410 /* Check that this is actually an insn setting
4411 up the equivalence. */
4412 || in_list_p (curr_insn,
4413 ira_reg_equiv
4414 [REGNO (dest_reg)].init_insns)))
4415 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4416 && in_list_p (curr_insn,
4417 ira_reg_equiv
4418 [REGNO (SET_SRC (set))].init_insns)))
4420 /* This is equiv init insn of pseudo which did not get a
4421 hard register -- remove the insn. */
4422 if (lra_dump_file != NULL)
4424 fprintf (lra_dump_file,
4425 " Removing equiv init insn %i (freq=%d)\n",
4426 INSN_UID (curr_insn),
4427 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4428 dump_insn_slim (lra_dump_file, curr_insn);
4430 if (contains_reg_p (x, true, false))
4431 lra_risky_transformations_p = true;
4432 lra_set_insn_deleted (curr_insn);
4433 continue;
4436 curr_id = lra_get_insn_recog_data (curr_insn);
4437 curr_static_id = curr_id->insn_static_data;
4438 init_curr_insn_input_reloads ();
4439 init_curr_operand_mode ();
4440 if (curr_insn_transform (false))
4441 changed_p = true;
4442 /* Check non-transformed insns too for equiv change as USE
4443 or CLOBBER don't need reloads but can contain pseudos
4444 being changed on their equivalences. */
4445 else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))
4446 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4448 lra_update_insn_regno_info (curr_insn);
4449 changed_p = true;
4453 bitmap_clear (&equiv_insn_bitmap);
4454 /* If we used a new hard regno, changed_p should be true because the
4455 hard reg is assigned to a new pseudo. */
4456 #ifdef ENABLE_CHECKING
4457 if (! changed_p)
4459 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4460 if (lra_reg_info[i].nrefs != 0
4461 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4463 int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)];
4465 for (j = 0; j < nregs; j++)
4466 lra_assert (df_regs_ever_live_p (hard_regno + j));
4469 #endif
4470 return changed_p;
4473 /* Initiate the LRA constraint pass. It is done once per
4474 function. */
4475 void
4476 lra_constraints_init (void)
4480 /* Finalize the LRA constraint pass. It is done once per
4481 function. */
4482 void
4483 lra_constraints_finish (void)
4489 /* This page contains code to do inheritance/split
4490 transformations. */
4492 /* Number of reloads passed so far in current EBB. */
4493 static int reloads_num;
4495 /* Number of calls passed so far in current EBB. */
4496 static int calls_num;
4498 /* Current reload pseudo check for validity of elements in
4499 USAGE_INSNS. */
4500 static int curr_usage_insns_check;
4502 /* Info about last usage of registers in EBB to do inheritance/split
4503 transformation. Inheritance transformation is done from a spilled
4504 pseudo and split transformations from a hard register or a pseudo
4505 assigned to a hard register. */
4506 struct usage_insns
4508 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4509 value INSNS is valid. The insns is chain of optional debug insns
4510 and a finishing non-debug insn using the corresponding reg. The
4511 value is also used to mark the registers which are set up in the
4512 current insn. The negated insn uid is used for this. */
4513 int check;
4514 /* Value of global reloads_num at the last insn in INSNS. */
4515 int reloads_num;
4516 /* Value of global reloads_nums at the last insn in INSNS. */
4517 int calls_num;
4518 /* It can be true only for splitting. And it means that the restore
4519 insn should be put after insn given by the following member. */
4520 bool after_p;
4521 /* Next insns in the current EBB which use the original reg and the
4522 original reg value is not changed between the current insn and
4523 the next insns. In order words, e.g. for inheritance, if we need
4524 to use the original reg value again in the next insns we can try
4525 to use the value in a hard register from a reload insn of the
4526 current insn. */
4527 rtx insns;
4530 /* Map: regno -> corresponding pseudo usage insns. */
4531 static struct usage_insns *usage_insns;
4533 static void
4534 setup_next_usage_insn (int regno, rtx_insn *insn, int reloads_num, bool after_p)
4536 usage_insns[regno].check = curr_usage_insns_check;
4537 usage_insns[regno].insns = insn;
4538 usage_insns[regno].reloads_num = reloads_num;
4539 usage_insns[regno].calls_num = calls_num;
4540 usage_insns[regno].after_p = after_p;
4543 /* The function is used to form list REGNO usages which consists of
4544 optional debug insns finished by a non-debug insn using REGNO.
4545 RELOADS_NUM is current number of reload insns processed so far. */
4546 static void
4547 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
4549 rtx next_usage_insns;
4551 if (usage_insns[regno].check == curr_usage_insns_check
4552 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
4553 && DEBUG_INSN_P (insn))
4555 /* Check that we did not add the debug insn yet. */
4556 if (next_usage_insns != insn
4557 && (GET_CODE (next_usage_insns) != INSN_LIST
4558 || XEXP (next_usage_insns, 0) != insn))
4559 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
4560 next_usage_insns);
4562 else if (NONDEBUG_INSN_P (insn))
4563 setup_next_usage_insn (regno, insn, reloads_num, false);
4564 else
4565 usage_insns[regno].check = 0;
4568 /* Return first non-debug insn in list USAGE_INSNS. */
4569 static rtx_insn *
4570 skip_usage_debug_insns (rtx usage_insns)
4572 rtx insn;
4574 /* Skip debug insns. */
4575 for (insn = usage_insns;
4576 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
4577 insn = XEXP (insn, 1))
4579 return safe_as_a <rtx_insn *> (insn);
4582 /* Return true if we need secondary memory moves for insn in
4583 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4584 into the insn. */
4585 static bool
4586 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
4587 rtx usage_insns ATTRIBUTE_UNUSED)
4589 #ifndef SECONDARY_MEMORY_NEEDED
4590 return false;
4591 #else
4592 rtx_insn *insn;
4593 rtx set, dest;
4594 enum reg_class cl;
4596 if (inher_cl == ALL_REGS
4597 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
4598 return false;
4599 lra_assert (INSN_P (insn));
4600 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
4601 return false;
4602 dest = SET_DEST (set);
4603 if (! REG_P (dest))
4604 return false;
4605 lra_assert (inher_cl != NO_REGS);
4606 cl = get_reg_class (REGNO (dest));
4607 return (cl != NO_REGS && cl != ALL_REGS
4608 && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest)));
4609 #endif
4612 /* Registers involved in inheritance/split in the current EBB
4613 (inheritance/split pseudos and original registers). */
4614 static bitmap_head check_only_regs;
4616 /* Do inheritance transformations for insn INSN, which defines (if
4617 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4618 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4619 form as the "insns" field of usage_insns. Return true if we
4620 succeed in such transformation.
4622 The transformations look like:
4624 p <- ... i <- ...
4625 ... p <- i (new insn)
4626 ... =>
4627 <- ... p ... <- ... i ...
4629 ... i <- p (new insn)
4630 <- ... p ... <- ... i ...
4631 ... =>
4632 <- ... p ... <- ... i ...
4633 where p is a spilled original pseudo and i is a new inheritance pseudo.
4636 The inheritance pseudo has the smallest class of two classes CL and
4637 class of ORIGINAL REGNO. */
4638 static bool
4639 inherit_reload_reg (bool def_p, int original_regno,
4640 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
4642 if (optimize_function_for_size_p (cfun))
4643 return false;
4645 enum reg_class rclass = lra_get_allocno_class (original_regno);
4646 rtx original_reg = regno_reg_rtx[original_regno];
4647 rtx new_reg, usage_insn;
4648 rtx_insn *new_insns;
4650 lra_assert (! usage_insns[original_regno].after_p);
4651 if (lra_dump_file != NULL)
4652 fprintf (lra_dump_file,
4653 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4654 if (! ira_reg_classes_intersect_p[cl][rclass])
4656 if (lra_dump_file != NULL)
4658 fprintf (lra_dump_file,
4659 " Rejecting inheritance for %d "
4660 "because of disjoint classes %s and %s\n",
4661 original_regno, reg_class_names[cl],
4662 reg_class_names[rclass]);
4663 fprintf (lra_dump_file,
4664 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4666 return false;
4668 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
4669 /* We don't use a subset of two classes because it can be
4670 NO_REGS. This transformation is still profitable in most
4671 cases even if the classes are not intersected as register
4672 move is probably cheaper than a memory load. */
4673 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
4675 if (lra_dump_file != NULL)
4676 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
4677 reg_class_names[cl], reg_class_names[rclass]);
4679 rclass = cl;
4681 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
4683 /* Reject inheritance resulting in secondary memory moves.
4684 Otherwise, there is a danger in LRA cycling. Also such
4685 transformation will be unprofitable. */
4686 if (lra_dump_file != NULL)
4688 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
4689 rtx set = single_set (insn);
4691 lra_assert (set != NULL_RTX);
4693 rtx dest = SET_DEST (set);
4695 lra_assert (REG_P (dest));
4696 fprintf (lra_dump_file,
4697 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4698 "as secondary mem is needed\n",
4699 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
4700 original_regno, reg_class_names[rclass]);
4701 fprintf (lra_dump_file,
4702 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4704 return false;
4706 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
4707 rclass, "inheritance");
4708 start_sequence ();
4709 if (def_p)
4710 lra_emit_move (original_reg, new_reg);
4711 else
4712 lra_emit_move (new_reg, original_reg);
4713 new_insns = get_insns ();
4714 end_sequence ();
4715 if (NEXT_INSN (new_insns) != NULL_RTX)
4717 if (lra_dump_file != NULL)
4719 fprintf (lra_dump_file,
4720 " Rejecting inheritance %d->%d "
4721 "as it results in 2 or more insns:\n",
4722 original_regno, REGNO (new_reg));
4723 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
4724 fprintf (lra_dump_file,
4725 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4727 return false;
4729 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg);
4730 lra_update_insn_regno_info (insn);
4731 if (! def_p)
4732 /* We now have a new usage insn for original regno. */
4733 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
4734 if (lra_dump_file != NULL)
4735 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
4736 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
4737 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
4738 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
4739 bitmap_set_bit (&check_only_regs, original_regno);
4740 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
4741 if (def_p)
4742 lra_process_new_insns (insn, NULL, new_insns,
4743 "Add original<-inheritance");
4744 else
4745 lra_process_new_insns (insn, new_insns, NULL,
4746 "Add inheritance<-original");
4747 while (next_usage_insns != NULL_RTX)
4749 if (GET_CODE (next_usage_insns) != INSN_LIST)
4751 usage_insn = next_usage_insns;
4752 lra_assert (NONDEBUG_INSN_P (usage_insn));
4753 next_usage_insns = NULL;
4755 else
4757 usage_insn = XEXP (next_usage_insns, 0);
4758 lra_assert (DEBUG_INSN_P (usage_insn));
4759 next_usage_insns = XEXP (next_usage_insns, 1);
4761 lra_substitute_pseudo (&usage_insn, original_regno, new_reg);
4762 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
4763 if (lra_dump_file != NULL)
4765 fprintf (lra_dump_file,
4766 " Inheritance reuse change %d->%d (bb%d):\n",
4767 original_regno, REGNO (new_reg),
4768 BLOCK_FOR_INSN (usage_insn)->index);
4769 dump_insn_slim (lra_dump_file, usage_insn);
4772 if (lra_dump_file != NULL)
4773 fprintf (lra_dump_file,
4774 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4775 return true;
4778 /* Return true if we need a caller save/restore for pseudo REGNO which
4779 was assigned to a hard register. */
4780 static inline bool
4781 need_for_call_save_p (int regno)
4783 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
4784 return (usage_insns[regno].calls_num < calls_num
4785 && (overlaps_hard_reg_set_p
4786 ((flag_ipa_ra &&
4787 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
4788 ? lra_reg_info[regno].actual_call_used_reg_set
4789 : call_used_reg_set,
4790 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
4791 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno],
4792 PSEUDO_REGNO_MODE (regno))));
4795 /* Global registers occurring in the current EBB. */
4796 static bitmap_head ebb_global_regs;
4798 /* Return true if we need a split for hard register REGNO or pseudo
4799 REGNO which was assigned to a hard register.
4800 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4801 used for reloads since the EBB end. It is an approximation of the
4802 used hard registers in the split range. The exact value would
4803 require expensive calculations. If we were aggressive with
4804 splitting because of the approximation, the split pseudo will save
4805 the same hard register assignment and will be removed in the undo
4806 pass. We still need the approximation because too aggressive
4807 splitting would result in too inaccurate cost calculation in the
4808 assignment pass because of too many generated moves which will be
4809 probably removed in the undo pass. */
4810 static inline bool
4811 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
4813 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
4815 lra_assert (hard_regno >= 0);
4816 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
4817 /* Don't split eliminable hard registers, otherwise we can
4818 split hard registers like hard frame pointer, which
4819 lives on BB start/end according to DF-infrastructure,
4820 when there is a pseudo assigned to the register and
4821 living in the same BB. */
4822 && (regno >= FIRST_PSEUDO_REGISTER
4823 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
4824 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
4825 /* Don't split call clobbered hard regs living through
4826 calls, otherwise we might have a check problem in the
4827 assign sub-pass as in the most cases (exception is a
4828 situation when lra_risky_transformations_p value is
4829 true) the assign pass assumes that all pseudos living
4830 through calls are assigned to call saved hard regs. */
4831 && (regno >= FIRST_PSEUDO_REGISTER
4832 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
4833 || usage_insns[regno].calls_num == calls_num)
4834 /* We need at least 2 reloads to make pseudo splitting
4835 profitable. We should provide hard regno splitting in
4836 any case to solve 1st insn scheduling problem when
4837 moving hard register definition up might result in
4838 impossibility to find hard register for reload pseudo of
4839 small register class. */
4840 && (usage_insns[regno].reloads_num
4841 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
4842 && (regno < FIRST_PSEUDO_REGISTER
4843 /* For short living pseudos, spilling + inheritance can
4844 be considered a substitution for splitting.
4845 Therefore we do not splitting for local pseudos. It
4846 decreases also aggressiveness of splitting. The
4847 minimal number of references is chosen taking into
4848 account that for 2 references splitting has no sense
4849 as we can just spill the pseudo. */
4850 || (regno >= FIRST_PSEUDO_REGISTER
4851 && lra_reg_info[regno].nrefs > 3
4852 && bitmap_bit_p (&ebb_global_regs, regno))))
4853 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
4856 /* Return class for the split pseudo created from original pseudo with
4857 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4858 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4859 results in no secondary memory movements. */
4860 static enum reg_class
4861 choose_split_class (enum reg_class allocno_class,
4862 int hard_regno ATTRIBUTE_UNUSED,
4863 machine_mode mode ATTRIBUTE_UNUSED)
4865 #ifndef SECONDARY_MEMORY_NEEDED
4866 return allocno_class;
4867 #else
4868 int i;
4869 enum reg_class cl, best_cl = NO_REGS;
4870 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4871 = REGNO_REG_CLASS (hard_regno);
4873 if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode)
4874 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
4875 return allocno_class;
4876 for (i = 0;
4877 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
4878 i++)
4879 if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode)
4880 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode)
4881 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
4882 && (best_cl == NO_REGS
4883 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
4884 best_cl = cl;
4885 return best_cl;
4886 #endif
4889 /* Do split transformations for insn INSN, which defines or uses
4890 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4891 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4892 "insns" field of usage_insns.
4894 The transformations look like:
4896 p <- ... p <- ...
4897 ... s <- p (new insn -- save)
4898 ... =>
4899 ... p <- s (new insn -- restore)
4900 <- ... p ... <- ... p ...
4902 <- ... p ... <- ... p ...
4903 ... s <- p (new insn -- save)
4904 ... =>
4905 ... p <- s (new insn -- restore)
4906 <- ... p ... <- ... p ...
4908 where p is an original pseudo got a hard register or a hard
4909 register and s is a new split pseudo. The save is put before INSN
4910 if BEFORE_P is true. Return true if we succeed in such
4911 transformation. */
4912 static bool
4913 split_reg (bool before_p, int original_regno, rtx_insn *insn,
4914 rtx next_usage_insns)
4916 enum reg_class rclass;
4917 rtx original_reg;
4918 int hard_regno, nregs;
4919 rtx new_reg, usage_insn;
4920 rtx_insn *restore, *save;
4921 bool after_p;
4922 bool call_save_p;
4924 if (original_regno < FIRST_PSEUDO_REGISTER)
4926 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
4927 hard_regno = original_regno;
4928 call_save_p = false;
4929 nregs = 1;
4931 else
4933 hard_regno = reg_renumber[original_regno];
4934 nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)];
4935 rclass = lra_get_allocno_class (original_regno);
4936 original_reg = regno_reg_rtx[original_regno];
4937 call_save_p = need_for_call_save_p (original_regno);
4939 original_reg = regno_reg_rtx[original_regno];
4940 lra_assert (hard_regno >= 0);
4941 if (lra_dump_file != NULL)
4942 fprintf (lra_dump_file,
4943 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4944 if (call_save_p)
4946 machine_mode mode = GET_MODE (original_reg);
4948 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
4949 hard_regno_nregs[hard_regno][mode],
4950 mode);
4951 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
4953 else
4955 rclass = choose_split_class (rclass, hard_regno,
4956 GET_MODE (original_reg));
4957 if (rclass == NO_REGS)
4959 if (lra_dump_file != NULL)
4961 fprintf (lra_dump_file,
4962 " Rejecting split of %d(%s): "
4963 "no good reg class for %d(%s)\n",
4964 original_regno,
4965 reg_class_names[lra_get_allocno_class (original_regno)],
4966 hard_regno,
4967 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
4968 fprintf
4969 (lra_dump_file,
4970 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4972 return false;
4974 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
4975 rclass, "split");
4976 reg_renumber[REGNO (new_reg)] = hard_regno;
4978 save = emit_spill_move (true, new_reg, original_reg);
4979 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
4981 if (lra_dump_file != NULL)
4983 fprintf
4984 (lra_dump_file,
4985 " Rejecting split %d->%d resulting in > 2 save insns:\n",
4986 original_regno, REGNO (new_reg));
4987 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
4988 fprintf (lra_dump_file,
4989 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4991 return false;
4993 restore = emit_spill_move (false, new_reg, original_reg);
4994 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
4996 if (lra_dump_file != NULL)
4998 fprintf (lra_dump_file,
4999 " Rejecting split %d->%d "
5000 "resulting in > 2 restore insns:\n",
5001 original_regno, REGNO (new_reg));
5002 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5003 fprintf (lra_dump_file,
5004 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5006 return false;
5008 after_p = usage_insns[original_regno].after_p;
5009 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
5010 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5011 bitmap_set_bit (&check_only_regs, original_regno);
5012 bitmap_set_bit (&lra_split_regs, REGNO (new_reg));
5013 for (;;)
5015 if (GET_CODE (next_usage_insns) != INSN_LIST)
5017 usage_insn = next_usage_insns;
5018 break;
5020 usage_insn = XEXP (next_usage_insns, 0);
5021 lra_assert (DEBUG_INSN_P (usage_insn));
5022 next_usage_insns = XEXP (next_usage_insns, 1);
5023 lra_substitute_pseudo (&usage_insn, original_regno, new_reg);
5024 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5025 if (lra_dump_file != NULL)
5027 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5028 original_regno, REGNO (new_reg));
5029 dump_insn_slim (lra_dump_file, usage_insn);
5032 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5033 lra_assert (usage_insn != insn || (after_p && before_p));
5034 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5035 after_p ? NULL : restore,
5036 after_p ? restore : NULL,
5037 call_save_p
5038 ? "Add reg<-save" : "Add reg<-split");
5039 lra_process_new_insns (insn, before_p ? save : NULL,
5040 before_p ? NULL : save,
5041 call_save_p
5042 ? "Add save<-reg" : "Add split<-reg");
5043 if (nregs > 1)
5044 /* If we are trying to split multi-register. We should check
5045 conflicts on the next assignment sub-pass. IRA can allocate on
5046 sub-register levels, LRA do this on pseudos level right now and
5047 this discrepancy may create allocation conflicts after
5048 splitting. */
5049 lra_risky_transformations_p = true;
5050 if (lra_dump_file != NULL)
5051 fprintf (lra_dump_file,
5052 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5053 return true;
5056 /* Recognize that we need a split transformation for insn INSN, which
5057 defines or uses REGNO in its insn biggest MODE (we use it only if
5058 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5059 hard registers which might be used for reloads since the EBB end.
5060 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5061 uid before starting INSN processing. Return true if we succeed in
5062 such transformation. */
5063 static bool
5064 split_if_necessary (int regno, machine_mode mode,
5065 HARD_REG_SET potential_reload_hard_regs,
5066 bool before_p, rtx_insn *insn, int max_uid)
5068 bool res = false;
5069 int i, nregs = 1;
5070 rtx next_usage_insns;
5072 if (regno < FIRST_PSEUDO_REGISTER)
5073 nregs = hard_regno_nregs[regno][mode];
5074 for (i = 0; i < nregs; i++)
5075 if (usage_insns[regno + i].check == curr_usage_insns_check
5076 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5077 /* To avoid processing the register twice or more. */
5078 && ((GET_CODE (next_usage_insns) != INSN_LIST
5079 && INSN_UID (next_usage_insns) < max_uid)
5080 || (GET_CODE (next_usage_insns) == INSN_LIST
5081 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5082 && need_for_split_p (potential_reload_hard_regs, regno + i)
5083 && split_reg (before_p, regno + i, insn, next_usage_insns))
5084 res = true;
5085 return res;
5088 /* Check only registers living at the current program point in the
5089 current EBB. */
5090 static bitmap_head live_regs;
5092 /* Update live info in EBB given by its HEAD and TAIL insns after
5093 inheritance/split transformation. The function removes dead moves
5094 too. */
5095 static void
5096 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5098 unsigned int j;
5099 int i, regno;
5100 bool live_p;
5101 rtx_insn *prev_insn;
5102 rtx set;
5103 bool remove_p;
5104 basic_block last_bb, prev_bb, curr_bb;
5105 bitmap_iterator bi;
5106 struct lra_insn_reg *reg;
5107 edge e;
5108 edge_iterator ei;
5110 last_bb = BLOCK_FOR_INSN (tail);
5111 prev_bb = NULL;
5112 for (curr_insn = tail;
5113 curr_insn != PREV_INSN (head);
5114 curr_insn = prev_insn)
5116 prev_insn = PREV_INSN (curr_insn);
5117 /* We need to process empty blocks too. They contain
5118 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5119 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5120 continue;
5121 curr_bb = BLOCK_FOR_INSN (curr_insn);
5122 if (curr_bb != prev_bb)
5124 if (prev_bb != NULL)
5126 /* Update df_get_live_in (prev_bb): */
5127 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5128 if (bitmap_bit_p (&live_regs, j))
5129 bitmap_set_bit (df_get_live_in (prev_bb), j);
5130 else
5131 bitmap_clear_bit (df_get_live_in (prev_bb), j);
5133 if (curr_bb != last_bb)
5135 /* Update df_get_live_out (curr_bb): */
5136 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5138 live_p = bitmap_bit_p (&live_regs, j);
5139 if (! live_p)
5140 FOR_EACH_EDGE (e, ei, curr_bb->succs)
5141 if (bitmap_bit_p (df_get_live_in (e->dest), j))
5143 live_p = true;
5144 break;
5146 if (live_p)
5147 bitmap_set_bit (df_get_live_out (curr_bb), j);
5148 else
5149 bitmap_clear_bit (df_get_live_out (curr_bb), j);
5152 prev_bb = curr_bb;
5153 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5155 if (! NONDEBUG_INSN_P (curr_insn))
5156 continue;
5157 curr_id = lra_get_insn_recog_data (curr_insn);
5158 curr_static_id = curr_id->insn_static_data;
5159 remove_p = false;
5160 if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set))
5161 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5162 && bitmap_bit_p (&check_only_regs, regno)
5163 && ! bitmap_bit_p (&live_regs, regno))
5164 remove_p = true;
5165 /* See which defined values die here. */
5166 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5167 if (reg->type == OP_OUT && ! reg->subreg_p)
5168 bitmap_clear_bit (&live_regs, reg->regno);
5169 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5170 if (reg->type == OP_OUT && ! reg->subreg_p)
5171 bitmap_clear_bit (&live_regs, reg->regno);
5172 /* Mark each used value as live. */
5173 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5174 if (reg->type != OP_OUT
5175 && bitmap_bit_p (&check_only_regs, reg->regno))
5176 bitmap_set_bit (&live_regs, reg->regno);
5177 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5178 if (reg->type != OP_OUT
5179 && bitmap_bit_p (&check_only_regs, reg->regno))
5180 bitmap_set_bit (&live_regs, reg->regno);
5181 if (curr_id->arg_hard_regs != NULL)
5182 /* Make argument hard registers live. */
5183 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5184 if (bitmap_bit_p (&check_only_regs, regno))
5185 bitmap_set_bit (&live_regs, regno);
5186 /* It is quite important to remove dead move insns because it
5187 means removing dead store. We don't need to process them for
5188 constraints. */
5189 if (remove_p)
5191 if (lra_dump_file != NULL)
5193 fprintf (lra_dump_file, " Removing dead insn:\n ");
5194 dump_insn_slim (lra_dump_file, curr_insn);
5196 lra_set_insn_deleted (curr_insn);
5201 /* The structure describes info to do an inheritance for the current
5202 insn. We need to collect such info first before doing the
5203 transformations because the transformations change the insn
5204 internal representation. */
5205 struct to_inherit
5207 /* Original regno. */
5208 int regno;
5209 /* Subsequent insns which can inherit original reg value. */
5210 rtx insns;
5213 /* Array containing all info for doing inheritance from the current
5214 insn. */
5215 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
5217 /* Number elements in the previous array. */
5218 static int to_inherit_num;
5220 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5221 structure to_inherit. */
5222 static void
5223 add_to_inherit (int regno, rtx insns)
5225 int i;
5227 for (i = 0; i < to_inherit_num; i++)
5228 if (to_inherit[i].regno == regno)
5229 return;
5230 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
5231 to_inherit[to_inherit_num].regno = regno;
5232 to_inherit[to_inherit_num++].insns = insns;
5235 /* Return the last non-debug insn in basic block BB, or the block begin
5236 note if none. */
5237 static rtx_insn *
5238 get_last_insertion_point (basic_block bb)
5240 rtx_insn *insn;
5242 FOR_BB_INSNS_REVERSE (bb, insn)
5243 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
5244 return insn;
5245 gcc_unreachable ();
5248 /* Set up RES by registers living on edges FROM except the edge (FROM,
5249 TO) or by registers set up in a jump insn in BB FROM. */
5250 static void
5251 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
5253 rtx_insn *last;
5254 struct lra_insn_reg *reg;
5255 edge e;
5256 edge_iterator ei;
5258 lra_assert (to != NULL);
5259 bitmap_clear (res);
5260 FOR_EACH_EDGE (e, ei, from->succs)
5261 if (e->dest != to)
5262 bitmap_ior_into (res, df_get_live_in (e->dest));
5263 last = get_last_insertion_point (from);
5264 if (! JUMP_P (last))
5265 return;
5266 curr_id = lra_get_insn_recog_data (last);
5267 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5268 if (reg->type != OP_IN)
5269 bitmap_set_bit (res, reg->regno);
5272 /* Used as a temporary results of some bitmap calculations. */
5273 static bitmap_head temp_bitmap;
5275 /* We split for reloads of small class of hard regs. The following
5276 defines how many hard regs the class should have to be qualified as
5277 small. The code is mostly oriented to x86/x86-64 architecture
5278 where some insns need to use only specific register or pair of
5279 registers and these register can live in RTL explicitly, e.g. for
5280 parameter passing. */
5281 static const int max_small_class_regs_num = 2;
5283 /* Do inheritance/split transformations in EBB starting with HEAD and
5284 finishing on TAIL. We process EBB insns in the reverse order.
5285 Return true if we did any inheritance/split transformation in the
5286 EBB.
5288 We should avoid excessive splitting which results in worse code
5289 because of inaccurate cost calculations for spilling new split
5290 pseudos in such case. To achieve this we do splitting only if
5291 register pressure is high in given basic block and there are reload
5292 pseudos requiring hard registers. We could do more register
5293 pressure calculations at any given program point to avoid necessary
5294 splitting even more but it is to expensive and the current approach
5295 works well enough. */
5296 static bool
5297 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
5299 int i, src_regno, dst_regno, nregs;
5300 bool change_p, succ_p, update_reloads_num_p;
5301 rtx_insn *prev_insn, *last_insn;
5302 rtx next_usage_insns, set;
5303 enum reg_class cl;
5304 struct lra_insn_reg *reg;
5305 basic_block last_processed_bb, curr_bb = NULL;
5306 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
5307 bitmap to_process;
5308 unsigned int j;
5309 bitmap_iterator bi;
5310 bool head_p, after_p;
5312 change_p = false;
5313 curr_usage_insns_check++;
5314 reloads_num = calls_num = 0;
5315 bitmap_clear (&check_only_regs);
5316 last_processed_bb = NULL;
5317 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5318 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
5319 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
5320 /* We don't process new insns generated in the loop. */
5321 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
5323 prev_insn = PREV_INSN (curr_insn);
5324 if (BLOCK_FOR_INSN (curr_insn) != NULL)
5325 curr_bb = BLOCK_FOR_INSN (curr_insn);
5326 if (last_processed_bb != curr_bb)
5328 /* We are at the end of BB. Add qualified living
5329 pseudos for potential splitting. */
5330 to_process = df_get_live_out (curr_bb);
5331 if (last_processed_bb != NULL)
5333 /* We are somewhere in the middle of EBB. */
5334 get_live_on_other_edges (curr_bb, last_processed_bb,
5335 &temp_bitmap);
5336 to_process = &temp_bitmap;
5338 last_processed_bb = curr_bb;
5339 last_insn = get_last_insertion_point (curr_bb);
5340 after_p = (! JUMP_P (last_insn)
5341 && (! CALL_P (last_insn)
5342 || (find_reg_note (last_insn,
5343 REG_NORETURN, NULL_RTX) == NULL_RTX
5344 && ! SIBLING_CALL_P (last_insn))));
5345 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5346 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5348 if ((int) j >= lra_constraint_new_regno_start)
5349 break;
5350 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5352 if (j < FIRST_PSEUDO_REGISTER)
5353 SET_HARD_REG_BIT (live_hard_regs, j);
5354 else
5355 add_to_hard_reg_set (&live_hard_regs,
5356 PSEUDO_REGNO_MODE (j),
5357 reg_renumber[j]);
5358 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
5362 src_regno = dst_regno = -1;
5363 if (NONDEBUG_INSN_P (curr_insn)
5364 && (set = single_set (curr_insn)) != NULL_RTX
5365 && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
5367 src_regno = REGNO (SET_SRC (set));
5368 dst_regno = REGNO (SET_DEST (set));
5370 update_reloads_num_p = true;
5371 if (src_regno < lra_constraint_new_regno_start
5372 && src_regno >= FIRST_PSEUDO_REGISTER
5373 && reg_renumber[src_regno] < 0
5374 && dst_regno >= lra_constraint_new_regno_start
5375 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
5377 /* 'reload_pseudo <- original_pseudo'. */
5378 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5379 reloads_num++;
5380 update_reloads_num_p = false;
5381 succ_p = false;
5382 if (usage_insns[src_regno].check == curr_usage_insns_check
5383 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
5384 succ_p = inherit_reload_reg (false, src_regno, cl,
5385 curr_insn, next_usage_insns);
5386 if (succ_p)
5387 change_p = true;
5388 else
5389 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5390 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5391 IOR_HARD_REG_SET (potential_reload_hard_regs,
5392 reg_class_contents[cl]);
5394 else if (src_regno >= lra_constraint_new_regno_start
5395 && dst_regno < lra_constraint_new_regno_start
5396 && dst_regno >= FIRST_PSEUDO_REGISTER
5397 && reg_renumber[dst_regno] < 0
5398 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
5399 && usage_insns[dst_regno].check == curr_usage_insns_check
5400 && (next_usage_insns
5401 = usage_insns[dst_regno].insns) != NULL_RTX)
5403 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5404 reloads_num++;
5405 update_reloads_num_p = false;
5406 /* 'original_pseudo <- reload_pseudo'. */
5407 if (! JUMP_P (curr_insn)
5408 && inherit_reload_reg (true, dst_regno, cl,
5409 curr_insn, next_usage_insns))
5410 change_p = true;
5411 /* Invalidate. */
5412 usage_insns[dst_regno].check = 0;
5413 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5414 IOR_HARD_REG_SET (potential_reload_hard_regs,
5415 reg_class_contents[cl]);
5417 else if (INSN_P (curr_insn))
5419 int iter;
5420 int max_uid = get_max_uid ();
5422 curr_id = lra_get_insn_recog_data (curr_insn);
5423 curr_static_id = curr_id->insn_static_data;
5424 to_inherit_num = 0;
5425 /* Process insn definitions. */
5426 for (iter = 0; iter < 2; iter++)
5427 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5428 reg != NULL;
5429 reg = reg->next)
5430 if (reg->type != OP_IN
5431 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
5433 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
5434 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
5435 && usage_insns[dst_regno].check == curr_usage_insns_check
5436 && (next_usage_insns
5437 = usage_insns[dst_regno].insns) != NULL_RTX)
5439 struct lra_insn_reg *r;
5441 for (r = curr_id->regs; r != NULL; r = r->next)
5442 if (r->type != OP_OUT && r->regno == dst_regno)
5443 break;
5444 /* Don't do inheritance if the pseudo is also
5445 used in the insn. */
5446 if (r == NULL)
5447 /* We can not do inheritance right now
5448 because the current insn reg info (chain
5449 regs) can change after that. */
5450 add_to_inherit (dst_regno, next_usage_insns);
5452 /* We can not process one reg twice here because of
5453 usage_insns invalidation. */
5454 if ((dst_regno < FIRST_PSEUDO_REGISTER
5455 || reg_renumber[dst_regno] >= 0)
5456 && ! reg->subreg_p && reg->type != OP_IN)
5458 HARD_REG_SET s;
5460 if (split_if_necessary (dst_regno, reg->biggest_mode,
5461 potential_reload_hard_regs,
5462 false, curr_insn, max_uid))
5463 change_p = true;
5464 CLEAR_HARD_REG_SET (s);
5465 if (dst_regno < FIRST_PSEUDO_REGISTER)
5466 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
5467 else
5468 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
5469 reg_renumber[dst_regno]);
5470 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
5472 /* We should invalidate potential inheritance or
5473 splitting for the current insn usages to the next
5474 usage insns (see code below) as the output pseudo
5475 prevents this. */
5476 if ((dst_regno >= FIRST_PSEUDO_REGISTER
5477 && reg_renumber[dst_regno] < 0)
5478 || (reg->type == OP_OUT && ! reg->subreg_p
5479 && (dst_regno < FIRST_PSEUDO_REGISTER
5480 || reg_renumber[dst_regno] >= 0)))
5482 /* Invalidate and mark definitions. */
5483 if (dst_regno >= FIRST_PSEUDO_REGISTER)
5484 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
5485 else
5487 nregs = hard_regno_nregs[dst_regno][reg->biggest_mode];
5488 for (i = 0; i < nregs; i++)
5489 usage_insns[dst_regno + i].check
5490 = -(int) INSN_UID (curr_insn);
5494 if (! JUMP_P (curr_insn))
5495 for (i = 0; i < to_inherit_num; i++)
5496 if (inherit_reload_reg (true, to_inherit[i].regno,
5497 ALL_REGS, curr_insn,
5498 to_inherit[i].insns))
5499 change_p = true;
5500 if (CALL_P (curr_insn))
5502 rtx cheap, pat, dest;
5503 rtx_insn *restore;
5504 int regno, hard_regno;
5506 calls_num++;
5507 if ((cheap = find_reg_note (curr_insn,
5508 REG_RETURNED, NULL_RTX)) != NULL_RTX
5509 && ((cheap = XEXP (cheap, 0)), true)
5510 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
5511 && (hard_regno = reg_renumber[regno]) >= 0
5512 /* If there are pending saves/restores, the
5513 optimization is not worth. */
5514 && usage_insns[regno].calls_num == calls_num - 1
5515 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
5517 /* Restore the pseudo from the call result as
5518 REG_RETURNED note says that the pseudo value is
5519 in the call result and the pseudo is an argument
5520 of the call. */
5521 pat = PATTERN (curr_insn);
5522 if (GET_CODE (pat) == PARALLEL)
5523 pat = XVECEXP (pat, 0, 0);
5524 dest = SET_DEST (pat);
5525 /* For multiple return values dest is PARALLEL.
5526 Currently we handle only single return value case. */
5527 if (REG_P (dest))
5529 start_sequence ();
5530 emit_move_insn (cheap, copy_rtx (dest));
5531 restore = get_insns ();
5532 end_sequence ();
5533 lra_process_new_insns (curr_insn, NULL, restore,
5534 "Inserting call parameter restore");
5535 /* We don't need to save/restore of the pseudo from
5536 this call. */
5537 usage_insns[regno].calls_num = calls_num;
5538 bitmap_set_bit (&check_only_regs, regno);
5542 to_inherit_num = 0;
5543 /* Process insn usages. */
5544 for (iter = 0; iter < 2; iter++)
5545 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5546 reg != NULL;
5547 reg = reg->next)
5548 if ((reg->type != OP_OUT
5549 || (reg->type == OP_OUT && reg->subreg_p))
5550 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
5552 if (src_regno >= FIRST_PSEUDO_REGISTER
5553 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
5555 if (usage_insns[src_regno].check == curr_usage_insns_check
5556 && (next_usage_insns
5557 = usage_insns[src_regno].insns) != NULL_RTX
5558 && NONDEBUG_INSN_P (curr_insn))
5559 add_to_inherit (src_regno, next_usage_insns);
5560 else if (usage_insns[src_regno].check
5561 != -(int) INSN_UID (curr_insn))
5562 /* Add usages but only if the reg is not set up
5563 in the same insn. */
5564 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5566 else if (src_regno < FIRST_PSEUDO_REGISTER
5567 || reg_renumber[src_regno] >= 0)
5569 bool before_p;
5570 rtx_insn *use_insn = curr_insn;
5572 before_p = (JUMP_P (curr_insn)
5573 || (CALL_P (curr_insn) && reg->type == OP_IN));
5574 if (NONDEBUG_INSN_P (curr_insn)
5575 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
5576 && split_if_necessary (src_regno, reg->biggest_mode,
5577 potential_reload_hard_regs,
5578 before_p, curr_insn, max_uid))
5580 if (reg->subreg_p)
5581 lra_risky_transformations_p = true;
5582 change_p = true;
5583 /* Invalidate. */
5584 usage_insns[src_regno].check = 0;
5585 if (before_p)
5586 use_insn = PREV_INSN (curr_insn);
5588 if (NONDEBUG_INSN_P (curr_insn))
5590 if (src_regno < FIRST_PSEUDO_REGISTER)
5591 add_to_hard_reg_set (&live_hard_regs,
5592 reg->biggest_mode, src_regno);
5593 else
5594 add_to_hard_reg_set (&live_hard_regs,
5595 PSEUDO_REGNO_MODE (src_regno),
5596 reg_renumber[src_regno]);
5598 add_next_usage_insn (src_regno, use_insn, reloads_num);
5601 /* Process call args. */
5602 if (curr_id->arg_hard_regs != NULL)
5603 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5604 if (src_regno < FIRST_PSEUDO_REGISTER)
5606 SET_HARD_REG_BIT (live_hard_regs, src_regno);
5607 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5609 for (i = 0; i < to_inherit_num; i++)
5611 src_regno = to_inherit[i].regno;
5612 if (inherit_reload_reg (false, src_regno, ALL_REGS,
5613 curr_insn, to_inherit[i].insns))
5614 change_p = true;
5615 else
5616 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5619 if (update_reloads_num_p
5620 && NONDEBUG_INSN_P (curr_insn)
5621 && (set = single_set (curr_insn)) != NULL_RTX)
5623 int regno = -1;
5624 if ((REG_P (SET_DEST (set))
5625 && (regno = REGNO (SET_DEST (set))) >= lra_constraint_new_regno_start
5626 && reg_renumber[regno] < 0
5627 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
5628 || (REG_P (SET_SRC (set))
5629 && (regno = REGNO (SET_SRC (set))) >= lra_constraint_new_regno_start
5630 && reg_renumber[regno] < 0
5631 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
5633 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5634 reloads_num++;
5635 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5636 IOR_HARD_REG_SET (potential_reload_hard_regs,
5637 reg_class_contents[cl]);
5640 /* We reached the start of the current basic block. */
5641 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
5642 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
5644 /* We reached the beginning of the current block -- do
5645 rest of spliting in the current BB. */
5646 to_process = df_get_live_in (curr_bb);
5647 if (BLOCK_FOR_INSN (head) != curr_bb)
5649 /* We are somewhere in the middle of EBB. */
5650 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
5651 curr_bb, &temp_bitmap);
5652 to_process = &temp_bitmap;
5654 head_p = true;
5655 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5657 if ((int) j >= lra_constraint_new_regno_start)
5658 break;
5659 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5660 && usage_insns[j].check == curr_usage_insns_check
5661 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
5663 if (need_for_split_p (potential_reload_hard_regs, j))
5665 if (lra_dump_file != NULL && head_p)
5667 fprintf (lra_dump_file,
5668 " ----------------------------------\n");
5669 head_p = false;
5671 if (split_reg (false, j, bb_note (curr_bb),
5672 next_usage_insns))
5673 change_p = true;
5675 usage_insns[j].check = 0;
5680 return change_p;
5683 /* This value affects EBB forming. If probability of edge from EBB to
5684 a BB is not greater than the following value, we don't add the BB
5685 to EBB. */
5686 #define EBB_PROBABILITY_CUTOFF \
5687 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
5689 /* Current number of inheritance/split iteration. */
5690 int lra_inheritance_iter;
5692 /* Entry function for inheritance/split pass. */
5693 void
5694 lra_inheritance (void)
5696 int i;
5697 basic_block bb, start_bb;
5698 edge e;
5700 lra_inheritance_iter++;
5701 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
5702 return;
5703 timevar_push (TV_LRA_INHERITANCE);
5704 if (lra_dump_file != NULL)
5705 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
5706 lra_inheritance_iter);
5707 curr_usage_insns_check = 0;
5708 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
5709 for (i = 0; i < lra_constraint_new_regno_start; i++)
5710 usage_insns[i].check = 0;
5711 bitmap_initialize (&check_only_regs, &reg_obstack);
5712 bitmap_initialize (&live_regs, &reg_obstack);
5713 bitmap_initialize (&temp_bitmap, &reg_obstack);
5714 bitmap_initialize (&ebb_global_regs, &reg_obstack);
5715 FOR_EACH_BB_FN (bb, cfun)
5717 start_bb = bb;
5718 if (lra_dump_file != NULL)
5719 fprintf (lra_dump_file, "EBB");
5720 /* Form a EBB starting with BB. */
5721 bitmap_clear (&ebb_global_regs);
5722 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
5723 for (;;)
5725 if (lra_dump_file != NULL)
5726 fprintf (lra_dump_file, " %d", bb->index);
5727 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
5728 || LABEL_P (BB_HEAD (bb->next_bb)))
5729 break;
5730 e = find_fallthru_edge (bb->succs);
5731 if (! e)
5732 break;
5733 if (e->probability < EBB_PROBABILITY_CUTOFF)
5734 break;
5735 bb = bb->next_bb;
5737 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
5738 if (lra_dump_file != NULL)
5739 fprintf (lra_dump_file, "\n");
5740 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
5741 /* Remember that the EBB head and tail can change in
5742 inherit_in_ebb. */
5743 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
5745 bitmap_clear (&ebb_global_regs);
5746 bitmap_clear (&temp_bitmap);
5747 bitmap_clear (&live_regs);
5748 bitmap_clear (&check_only_regs);
5749 free (usage_insns);
5751 timevar_pop (TV_LRA_INHERITANCE);
5756 /* This page contains code to undo failed inheritance/split
5757 transformations. */
5759 /* Current number of iteration undoing inheritance/split. */
5760 int lra_undo_inheritance_iter;
5762 /* Fix BB live info LIVE after removing pseudos created on pass doing
5763 inheritance/split which are REMOVED_PSEUDOS. */
5764 static void
5765 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
5767 unsigned int regno;
5768 bitmap_iterator bi;
5770 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
5771 if (bitmap_clear_bit (live, regno))
5772 bitmap_set_bit (live, lra_reg_info[regno].restore_regno);
5775 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5776 number. */
5777 static int
5778 get_regno (rtx reg)
5780 if (GET_CODE (reg) == SUBREG)
5781 reg = SUBREG_REG (reg);
5782 if (REG_P (reg))
5783 return REGNO (reg);
5784 return -1;
5787 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5788 return true if we did any change. The undo transformations for
5789 inheritance looks like
5790 i <- i2
5791 p <- i => p <- i2
5792 or removing
5793 p <- i, i <- p, and i <- i3
5794 where p is original pseudo from which inheritance pseudo i was
5795 created, i and i3 are removed inheritance pseudos, i2 is another
5796 not removed inheritance pseudo. All split pseudos or other
5797 occurrences of removed inheritance pseudos are changed on the
5798 corresponding original pseudos.
5800 The function also schedules insns changed and created during
5801 inheritance/split pass for processing by the subsequent constraint
5802 pass. */
5803 static bool
5804 remove_inheritance_pseudos (bitmap remove_pseudos)
5806 basic_block bb;
5807 int regno, sregno, prev_sregno, dregno, restore_regno;
5808 rtx set, prev_set;
5809 rtx_insn *prev_insn;
5810 bool change_p, done_p;
5812 change_p = ! bitmap_empty_p (remove_pseudos);
5813 /* We can not finish the function right away if CHANGE_P is true
5814 because we need to marks insns affected by previous
5815 inheritance/split pass for processing by the subsequent
5816 constraint pass. */
5817 FOR_EACH_BB_FN (bb, cfun)
5819 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
5820 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
5821 FOR_BB_INSNS_REVERSE (bb, curr_insn)
5823 if (! INSN_P (curr_insn))
5824 continue;
5825 done_p = false;
5826 sregno = dregno = -1;
5827 if (change_p && NONDEBUG_INSN_P (curr_insn)
5828 && (set = single_set (curr_insn)) != NULL_RTX)
5830 dregno = get_regno (SET_DEST (set));
5831 sregno = get_regno (SET_SRC (set));
5834 if (sregno >= 0 && dregno >= 0)
5836 if ((bitmap_bit_p (remove_pseudos, sregno)
5837 && (lra_reg_info[sregno].restore_regno == dregno
5838 || (bitmap_bit_p (remove_pseudos, dregno)
5839 && (lra_reg_info[sregno].restore_regno
5840 == lra_reg_info[dregno].restore_regno))))
5841 || (bitmap_bit_p (remove_pseudos, dregno)
5842 && lra_reg_info[dregno].restore_regno == sregno))
5843 /* One of the following cases:
5844 original <- removed inheritance pseudo
5845 removed inherit pseudo <- another removed inherit pseudo
5846 removed inherit pseudo <- original pseudo
5848 removed_split_pseudo <- original_reg
5849 original_reg <- removed_split_pseudo */
5851 if (lra_dump_file != NULL)
5853 fprintf (lra_dump_file, " Removing %s:\n",
5854 bitmap_bit_p (&lra_split_regs, sregno)
5855 || bitmap_bit_p (&lra_split_regs, dregno)
5856 ? "split" : "inheritance");
5857 dump_insn_slim (lra_dump_file, curr_insn);
5859 lra_set_insn_deleted (curr_insn);
5860 done_p = true;
5862 else if (bitmap_bit_p (remove_pseudos, sregno)
5863 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
5865 /* Search the following pattern:
5866 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5867 original_pseudo <- inherit_or_split_pseudo1
5868 where the 2nd insn is the current insn and
5869 inherit_or_split_pseudo2 is not removed. If it is found,
5870 change the current insn onto:
5871 original_pseudo <- inherit_or_split_pseudo2. */
5872 for (prev_insn = PREV_INSN (curr_insn);
5873 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
5874 prev_insn = PREV_INSN (prev_insn))
5876 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
5877 && (prev_set = single_set (prev_insn)) != NULL_RTX
5878 /* There should be no subregs in insn we are
5879 searching because only the original reg might
5880 be in subreg when we changed the mode of
5881 load/store for splitting. */
5882 && REG_P (SET_DEST (prev_set))
5883 && REG_P (SET_SRC (prev_set))
5884 && (int) REGNO (SET_DEST (prev_set)) == sregno
5885 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
5886 >= FIRST_PSEUDO_REGISTER)
5887 /* As we consider chain of inheritance or
5888 splitting described in above comment we should
5889 check that sregno and prev_sregno were
5890 inheritance/split pseudos created from the
5891 same original regno. */
5892 && (lra_reg_info[sregno].restore_regno
5893 == lra_reg_info[prev_sregno].restore_regno)
5894 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
5896 lra_assert (GET_MODE (SET_SRC (prev_set))
5897 == GET_MODE (regno_reg_rtx[sregno]));
5898 if (GET_CODE (SET_SRC (set)) == SUBREG)
5899 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set);
5900 else
5901 SET_SRC (set) = SET_SRC (prev_set);
5902 /* As we are finishing with processing the insn
5903 here, check the destination too as it might
5904 inheritance pseudo for another pseudo. */
5905 if (bitmap_bit_p (remove_pseudos, dregno)
5906 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
5907 && (restore_regno
5908 = lra_reg_info[dregno].restore_regno) >= 0)
5910 if (GET_CODE (SET_DEST (set)) == SUBREG)
5911 SUBREG_REG (SET_DEST (set))
5912 = regno_reg_rtx[restore_regno];
5913 else
5914 SET_DEST (set) = regno_reg_rtx[restore_regno];
5916 lra_push_insn_and_update_insn_regno_info (curr_insn);
5917 lra_set_used_insn_alternative_by_uid
5918 (INSN_UID (curr_insn), -1);
5919 done_p = true;
5920 if (lra_dump_file != NULL)
5922 fprintf (lra_dump_file, " Change reload insn:\n");
5923 dump_insn_slim (lra_dump_file, curr_insn);
5928 if (! done_p)
5930 struct lra_insn_reg *reg;
5931 bool restored_regs_p = false;
5932 bool kept_regs_p = false;
5934 curr_id = lra_get_insn_recog_data (curr_insn);
5935 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5937 regno = reg->regno;
5938 restore_regno = lra_reg_info[regno].restore_regno;
5939 if (restore_regno >= 0)
5941 if (change_p && bitmap_bit_p (remove_pseudos, regno))
5943 lra_substitute_pseudo_within_insn (
5944 curr_insn, regno, regno_reg_rtx[restore_regno]);
5945 restored_regs_p = true;
5947 else
5948 kept_regs_p = true;
5951 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
5953 /* The instruction has changed since the previous
5954 constraints pass. */
5955 lra_push_insn_and_update_insn_regno_info (curr_insn);
5956 lra_set_used_insn_alternative_by_uid
5957 (INSN_UID (curr_insn), -1);
5959 else if (restored_regs_p)
5960 /* The instruction has been restored to the form that
5961 it had during the previous constraints pass. */
5962 lra_update_insn_regno_info (curr_insn);
5963 if (restored_regs_p && lra_dump_file != NULL)
5965 fprintf (lra_dump_file, " Insn after restoring regs:\n");
5966 dump_insn_slim (lra_dump_file, curr_insn);
5971 return change_p;
5974 /* If optional reload pseudos failed to get a hard register or was not
5975 inherited, it is better to remove optional reloads. We do this
5976 transformation after undoing inheritance to figure out necessity to
5977 remove optional reloads easier. Return true if we do any
5978 change. */
5979 static bool
5980 undo_optional_reloads (void)
5982 bool change_p, keep_p;
5983 unsigned int regno, uid;
5984 bitmap_iterator bi, bi2;
5985 rtx_insn *insn;
5986 rtx set, src, dest;
5987 bitmap_head removed_optional_reload_pseudos, insn_bitmap;
5989 bitmap_initialize (&removed_optional_reload_pseudos, &reg_obstack);
5990 bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
5991 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
5993 keep_p = false;
5994 /* Keep optional reloads from previous subpasses. */
5995 if (lra_reg_info[regno].restore_regno < 0
5996 /* If the original pseudo changed its allocation, just
5997 removing the optional pseudo is dangerous as the original
5998 pseudo will have longer live range. */
5999 || reg_renumber[lra_reg_info[regno].restore_regno] >= 0)
6000 keep_p = true;
6001 else if (reg_renumber[regno] >= 0)
6002 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6004 insn = lra_insn_recog_data[uid]->insn;
6005 if ((set = single_set (insn)) == NULL_RTX)
6006 continue;
6007 src = SET_SRC (set);
6008 dest = SET_DEST (set);
6009 if (! REG_P (src) || ! REG_P (dest))
6010 continue;
6011 if (REGNO (dest) == regno
6012 /* Ignore insn for optional reloads itself. */
6013 && lra_reg_info[regno].restore_regno != (int) REGNO (src)
6014 /* Check only inheritance on last inheritance pass. */
6015 && (int) REGNO (src) >= new_regno_start
6016 /* Check that the optional reload was inherited. */
6017 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6019 keep_p = true;
6020 break;
6023 if (keep_p)
6025 bitmap_clear_bit (&removed_optional_reload_pseudos, regno);
6026 if (lra_dump_file != NULL)
6027 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6030 change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos);
6031 bitmap_initialize (&insn_bitmap, &reg_obstack);
6032 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi)
6034 if (lra_dump_file != NULL)
6035 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6036 bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6037 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2)
6039 insn = lra_insn_recog_data[uid]->insn;
6040 if ((set = single_set (insn)) != NULL_RTX)
6042 src = SET_SRC (set);
6043 dest = SET_DEST (set);
6044 if (REG_P (src) && REG_P (dest)
6045 && ((REGNO (src) == regno
6046 && (lra_reg_info[regno].restore_regno
6047 == (int) REGNO (dest)))
6048 || (REGNO (dest) == regno
6049 && (lra_reg_info[regno].restore_regno
6050 == (int) REGNO (src)))))
6052 if (lra_dump_file != NULL)
6054 fprintf (lra_dump_file, " Deleting move %u\n",
6055 INSN_UID (insn));
6056 dump_insn_slim (lra_dump_file, insn);
6058 lra_set_insn_deleted (insn);
6059 continue;
6061 /* We should not worry about generation memory-memory
6062 moves here as if the corresponding inheritance did
6063 not work (inheritance pseudo did not get a hard reg),
6064 we remove the inheritance pseudo and the optional
6065 reload. */
6067 lra_substitute_pseudo_within_insn (
6068 insn, regno,
6069 regno_reg_rtx[lra_reg_info[regno].restore_regno]);
6070 lra_update_insn_regno_info (insn);
6071 if (lra_dump_file != NULL)
6073 fprintf (lra_dump_file,
6074 " Restoring original insn:\n");
6075 dump_insn_slim (lra_dump_file, insn);
6079 /* Clear restore_regnos. */
6080 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6081 lra_reg_info[regno].restore_regno = -1;
6082 bitmap_clear (&insn_bitmap);
6083 bitmap_clear (&removed_optional_reload_pseudos);
6084 return change_p;
6087 /* Entry function for undoing inheritance/split transformation. Return true
6088 if we did any RTL change in this pass. */
6089 bool
6090 lra_undo_inheritance (void)
6092 unsigned int regno;
6093 int restore_regno, hard_regno;
6094 int n_all_inherit, n_inherit, n_all_split, n_split;
6095 bitmap_head remove_pseudos;
6096 bitmap_iterator bi;
6097 bool change_p;
6099 lra_undo_inheritance_iter++;
6100 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6101 return false;
6102 if (lra_dump_file != NULL)
6103 fprintf (lra_dump_file,
6104 "\n********** Undoing inheritance #%d: **********\n\n",
6105 lra_undo_inheritance_iter);
6106 bitmap_initialize (&remove_pseudos, &reg_obstack);
6107 n_inherit = n_all_inherit = 0;
6108 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6109 if (lra_reg_info[regno].restore_regno >= 0)
6111 n_all_inherit++;
6112 if (reg_renumber[regno] < 0
6113 /* If the original pseudo changed its allocation, just
6114 removing inheritance is dangerous as for changing
6115 allocation we used shorter live-ranges. */
6116 && reg_renumber[lra_reg_info[regno].restore_regno] < 0)
6117 bitmap_set_bit (&remove_pseudos, regno);
6118 else
6119 n_inherit++;
6121 if (lra_dump_file != NULL && n_all_inherit != 0)
6122 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
6123 n_inherit, n_all_inherit,
6124 (double) n_inherit / n_all_inherit * 100);
6125 n_split = n_all_split = 0;
6126 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6127 if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0)
6129 n_all_split++;
6130 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
6131 ? reg_renumber[restore_regno] : restore_regno);
6132 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
6133 bitmap_set_bit (&remove_pseudos, regno);
6134 else
6136 n_split++;
6137 if (lra_dump_file != NULL)
6138 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
6139 regno, restore_regno);
6142 if (lra_dump_file != NULL && n_all_split != 0)
6143 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
6144 n_split, n_all_split,
6145 (double) n_split / n_all_split * 100);
6146 change_p = remove_inheritance_pseudos (&remove_pseudos);
6147 bitmap_clear (&remove_pseudos);
6148 /* Clear restore_regnos. */
6149 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6150 lra_reg_info[regno].restore_regno = -1;
6151 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6152 lra_reg_info[regno].restore_regno = -1;
6153 change_p = undo_optional_reloads () || change_p;
6154 return change_p;