libjava/sysdep/x86-64/locks.h

   1 /* locks.h - Thread synchronization primitives. X86/x86-64 implementation.
   2
   3    Copyright (C) 2002  Free Software Foundation
   4
   5    Contributed by Bo Thorsen <bo@suse.de>.
   6
   7    This file is part of libgcj.
   8
   9 This software is copyrighted work licensed under the terms of the
  10 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
  11 details.  */
  12
  13 #ifndef __SYSDEP_LOCKS_H__
  14 #define __SYSDEP_LOCKS_H__
  15
  16 typedef size_t obj_addr_t;      /* Integer type big enough for object   */
  17                                 /* address.                             */
  18
  19 // Atomically replace *addr by new_val if it was initially equal to old.
  20 // Return true if the comparison succeeded.
  21 // Assumed to have acquire semantics, i.e. later memory operations
  22 // cannot execute before the compare_and_swap finishes.
  23 inline static bool
  24 compare_and_swap(volatile obj_addr_t *addr,
  25                  obj_addr_t old,
  26                  obj_addr_t new_val)
  27 {
  28   char result;
  29 #ifdef __x86_64__
  30   __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
  31               : "=m"(*(addr)), "=q"(result)
  32               : "r" (new_val), "a"(old), "m"(*addr)
  33               : "memory");
  34 #else
  35   __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
  36                        : "=m"(*addr), "=q"(result)
  37                        : "r" (new_val), "a"(old), "m"(*addr)
  38                        : "memory");
  39 #endif
  40   return (bool) result;
  41 }
  42
  43 // Set *addr to new_val with release semantics, i.e. making sure
  44 // that prior loads and stores complete before this
  45 // assignment.
  46 // On X86/x86-64, the hardware shouldn't reorder reads and writes,
  47 // so we just have to convince gcc not to do it either.
  48 inline static void
  49 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  50 {
  51   __asm__ __volatile__(" " : : : "memory");
  52   *(addr) = new_val;
  53 }
  54
  55 // Compare_and_swap with release semantics instead of acquire semantics.
  56 // On many architecture, the operation makes both guarantees, so the
  57 // implementation can be the same.
  58 inline static bool
  59 compare_and_swap_release(volatile obj_addr_t *addr,
  60                          obj_addr_t old,
  61                          obj_addr_t new_val)
  62 {
  63   return compare_and_swap(addr, old, new_val);
  64 }
  65
  66 // Ensure that subsequent instructions do not execute on stale
  67 // data that was loaded from memory before the barrier.
  68 // On X86/x86-64, the hardware ensures that reads are properly ordered.
  69 inline static void
  70 read_barrier()
  71 {
  72 }
  73
  74 // Ensure that prior stores to memory are completed with respect to other
  75 // processors.
  76 inline static void
  77 write_barrier()
  78 {
  79   /* x86-64/X86 does not reorder writes. We just need to ensure that
  80      gcc also doesn't.  */
  81   __asm__ __volatile__(" " : : : "memory");
  82 }
  83 #endif