| blob | ebed78fda3fb9f60485ef2bd513ad8d053e3754c |
1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
51 machine_mode *);
55 /* Debug facility for use in GDB. */
57 \f
58 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
59 the result of operation CODE applied to OP0 (and OP1 if it is a binary
60 operation). OP0_MODE is OP0's mode.
62 If the last insn does not set TARGET, don't do anything, but return 1.
64 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
65 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
66 try again, ensuring that TARGET is not one of the operands. */
68 static int
71 {
73 rtx set;
74 rtx note;
91 ;
93 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
94 a value changing in the insn, so the note would be invalid for CSE. */
97 {
101 {
102 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
103 over expanding it as temp = MEM op X, MEM = temp. If the target
104 supports MEM = MEM op X instructions, it is sometimes too hard
105 to reconstruct that form later, especially if X is also a memory,
106 and due to multiple occurrences of addresses the address might
107 be forced into register unnecessarily.
108 Note that not emitting the REG_EQUIV note might inhibit
109 CSE in some cases. */
118 }
120 }
127 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
134 {
143 {
149 else
153 }
154 /* FALLTHRU */
158 }
159 else
165 }
166 \f
167 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
168 for a widening operation would be. In most cases this would be OP0, but if
169 that's a constant it'll be VOIDmode, which isn't useful. */
171 static machine_mode
173 {
176 machine_mode result;
182 else
189 }
190 \f
191 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
192 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
193 not actually do a sign-extend or zero-extend, but can leave the
194 higher-order bits of the result rtx undefined, for example, in the case
195 of logical operations, but not right shifts. */
197 static rtx
200 {
201 rtx result;
202 scalar_int_mode int_mode;
204 /* If we don't have to extend and this is a constant, return it. */
208 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
209 extend since it will be more efficient to do so unless the signedness of
210 a promoted object differs from our extension. */
217 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
218 SUBREG. */
222 /* Otherwise, get an object of MODE, clobber it, and set the low-order
223 part to OP. */
229 }
230 \f
231 /* Expand vector widening operations.
233 There are two different classes of operations handled here:
234 1) Operations whose result is wider than all the arguments to the operation.
235 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
236 In this case OP0 and optionally OP1 would be initialized,
237 but WIDE_OP wouldn't (not relevant for this case).
238 2) Operations whose result is of the same size as the last argument to the
239 operation, but wider than all the other arguments to the operation.
240 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
241 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
243 E.g, when called to expand the following operations, this is how
244 the arguments will be initialized:
245 nops OP0 OP1 WIDE_OP
246 widening-sum 2 oprnd0 - oprnd1
247 widening-dot-product 3 oprnd0 oprnd1 oprnd2
248 widening-mult 2 oprnd0 oprnd1 -
249 type-promotion (vec-unpack) 1 oprnd0 - - */
251 rtx
254 {
258 optab widen_pattern_optab;
273 /* The sign is from the result type rather than operand's type
274 for these ops. */
275 widen_pattern_optab
283 {
284 /* For VEC_UNPACK_{LO,HI}_EXPR if the mode of op0 and result is
285 the same scalar mode for VECTOR_BOOLEAN_TYPE_P vectors, use
286 vec_unpacks_sbool_{lo,hi}_optab, so that we can pass in
287 the pattern number of elements in the wider vector. */
288 widen_pattern_optab
292 }
294 {
299 ;
301 {
303 /* Same as optab_vector_mixed_sign but flip the operands. */
305 }
308 else
311 widen_pattern_optab
313 }
314 else
315 widen_pattern_optab
321 tmode0);
322 else
329 {
333 }
335 /* The last operand is of a wider mode than the rest of the operands. */
339 {
343 }
354 }
356 /* Generate code to perform an operation specified by TERNARY_OPTAB
357 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
359 UNSIGNEDP is for the case where we have to widen the operands
360 to perform the operation. It says to use zero-extension.
362 If TARGET is nonzero, the value
363 is generated there, if it is convenient to do so.
364 In all cases an rtx is returned for the locus of the value;
365 this may or may not be TARGET. */
367 rtx
370 {
382 }
385 /* Like expand_binop, but return a constant rtx if the result can be
386 calculated at compile time. The arguments and return value are
387 otherwise the same as for expand_binop. */
389 rtx
393 {
395 {
400 }
403 }
405 /* Like simplify_expand_binop, but always put the result in TARGET.
406 Return true if the expansion succeeded. */
408 bool
412 {
420 }
422 /* Create a new vector value in VMODE with all elements set to OP. The
423 mode of OP must be the element mode of VMODE. If OP is a constant,
424 then the return value will be a constant. */
426 rtx
428 {
430 rtvec vec;
439 {
445 }
450 /* ??? If the target doesn't have a vec_init, then we have no easy way
451 of performing this operation. Most of this sort of generic support
452 is hidden away in the vector lowering support in gimple. */
465 }
467 /* This subroutine of expand_doubleword_shift handles the cases in which
468 the effective shift value is >= BITS_PER_WORD. The arguments and return
469 value are the same as for the parent routine, except that SUPERWORD_OP1
470 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
471 INTO_TARGET may be null if the caller has decided to calculate it. */
473 static bool
477 {
484 {
485 /* For a signed right shift, we must fill OUTOF_TARGET with copies
486 of the sign bit, otherwise we must fill it with zeros. */
489 else
495 }
497 }
499 /* This subroutine of expand_doubleword_shift handles the cases in which
500 the effective shift value is < BITS_PER_WORD. The arguments and return
501 value are the same as for the parent routine. */
503 static bool
509 {
516 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
517 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
518 the opposite direction to BINOPTAB. */
520 {
526 }
527 else
528 {
529 /* We must avoid shifting by BITS_PER_WORD bits since that is either
530 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
531 has unknown behavior. Do a single shift first, then shift by the
532 remainder. It's OK to use ~OP1 as the remainder if shift counts
533 are truncated to the mode size. */
537 {
538 tmp = immed_wide_int_const
542 }
543 else
544 {
549 }
550 }
558 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
559 so the result can go directly into INTO_TARGET if convenient. */
565 /* Now OR in the bits carried over from OUTOF_INPUT. */
570 /* Use a standard word_mode shift for the out-of half. */
577 }
580 /* Try implementing expand_doubleword_shift using conditional moves.
581 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
582 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
583 are the shift counts to use in the former and latter case. All other
584 arguments are the same as the parent routine. */
586 static bool
594 {
597 /* Put the superword version of the output into OUTOF_SUPERWORD and
598 INTO_SUPERWORD. */
601 {
602 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
603 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
608 }
609 else
610 {
616 }
618 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
625 /* Select between them. Do the INTO half first because INTO_SUPERWORD
626 might be the current value of OUTOF_TARGET. */
638 }
640 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
641 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
642 input operand; the shift moves bits in the direction OUTOF_INPUT->
643 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
644 of the target. OP1 is the shift count and OP1_MODE is its mode.
645 If OP1 is constant, it will have been truncated as appropriate
646 and is known to be nonzero.
648 If SHIFT_MASK is zero, the result of word shifts is undefined when the
649 shift count is outside the range [0, BITS_PER_WORD). This routine must
650 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
652 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
653 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
654 fill with zeros or sign bits as appropriate.
656 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
657 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
658 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
659 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
660 are undefined.
662 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
663 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
664 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
665 function wants to calculate it itself.
667 Return true if the shift could be successfully synthesized. */
669 static bool
675 {
679 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
680 fill the result with sign or zero bits as appropriate. If so, the value
681 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
682 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
683 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
685 This isn't worthwhile for constant shifts since the optimizers will
686 cope better with in-range shift counts. */
690 {
700 }
702 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
703 is true when the effective shift value is less than BITS_PER_WORD.
704 Set SUPERWORD_OP1 to the shift count that should be used to shift
705 OUTOF_INPUT into INTO_TARGET when the condition is false. */
708 {
709 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
710 is a subword shift count. */
716 }
717 else
718 {
719 /* Set CMP1 to OP1 - BITS_PER_WORD. */
725 }
729 /* If we can compute the condition at compile time, pick the
730 appropriate subroutine. */
733 {
738 else
743 }
745 /* Try using conditional moves to generate straight-line code. */
747 {
757 }
759 /* As a last resort, use branches to select the correct alternative. */
763 NO_DEFER_POP;
767 OK_DEFER_POP;
786 }
787 \f
788 /* Subroutine of expand_binop. Perform a double word multiplication of
789 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
790 as the target's word_mode. This function return NULL_RTX if anything
791 goes wrong, in which case it may have already emitted instructions
792 which need to be deleted.
794 If we want to multiply two two-word values and have normal and widening
795 multiplies of single-word values, we can do this with three smaller
796 multiplications.
798 The multiplication proceeds as follows:
799 _______________________
800 [__op0_high_|__op0_low__]
801 _______________________
802 * [__op1_high_|__op1_low__]
803 _______________________________________________
804 _______________________
805 (1) [__op0_low__*__op1_low__]
806 _______________________
807 (2a) [__op0_low__*__op1_high_]
808 _______________________
809 (2b) [__op0_high_*__op1_low__]
810 _______________________
811 (3) [__op0_high_*__op1_high_]
814 This gives a 4-word result. Since we are only interested in the
815 lower 2 words, partial result (3) and the upper words of (2a) and
816 (2b) don't need to be calculated. Hence (2a) and (2b) can be
817 calculated using non-widening multiplication.
819 (1), however, needs to be calculated with an unsigned widening
820 multiplication. If this operation is not directly supported we
821 try using a signed widening multiplication and adjust the result.
822 This adjustment works as follows:
824 If both operands are positive then no adjustment is needed.
826 If the operands have different signs, for example op0_low < 0 and
827 op1_low >= 0, the instruction treats the most significant bit of
828 op0_low as a sign bit instead of a bit with significance
829 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
830 with 2**BITS_PER_WORD - op0_low, and two's complements the
831 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
832 the result.
834 Similarly, if both operands are negative, we need to add
835 (op0_low + op1_low) * 2**BITS_PER_WORD.
837 We use a trick to adjust quickly. We logically shift op0_low right
838 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
839 op0_high (op1_high) before it is used to calculate 2b (2a). If no
840 logical shift exists, we do an arithmetic right shift and subtract
841 the 0 or -1. */
843 static rtx
846 {
858 /* If we're using an unsigned multiply to directly compute the product
859 of the low-order words of the operands and perform any required
860 adjustments of the operands, we begin by trying two more multiplications
861 and then computing the appropriate sum.
863 We have checked above that the required addition is provided.
864 Full-word addition will normally always succeed, especially if
865 it is provided at all, so we don't worry about its failure. The
866 multiplication may well fail, however, so we do handle that. */
869 {
870 /* ??? This could be done with emit_store_flag where available. */
876 else
877 {
884 }
888 }
895 /* OP0_HIGH should now be dead. */
898 {
899 /* ??? This could be done with emit_store_flag where available. */
905 else
906 {
913 }
917 }
924 /* OP1_HIGH should now be dead. */
932 /* *_widen_optab needs to determine operand mode, make sure at least
933 one operand has non-VOID mode. */
940 else
952 }
954 /* Subroutine of expand_binop. Optimize unsigned double-word OP0 % OP1 for
955 constant OP1. If for some bit in [BITS_PER_WORD / 2, BITS_PER_WORD] range
956 (prefer higher bits) ((1w << bit) % OP1) == 1, then the modulo can be
957 computed in word-mode as ((OP0 & (bit - 1)) + ((OP0 >> bit) & (bit - 1))
958 + (OP0 >> (2 * bit))) % OP1. Whether we need to sum 2, 3 or 4 values
959 depends on the bit value, if 2, then carry from the addition needs to be
960 added too, i.e. like:
961 sum += __builtin_add_overflow (low, high, &sum)
963 Optimize signed double-word OP0 % OP1 similarly, just apply some correction
964 factor to the sum before doing unsigned remainder, in the form of
965 sum += (((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & const);
966 then perform unsigned
967 remainder = sum % OP1;
968 and finally
969 remainder += ((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1); */
971 static rtx
973 {
979 {
985 {
986 /* For signed modulo we need to add correction to the sum
987 and that might again overflow. */
1010 OPTAB_DIRECT);
1013 }
1014 else
1015 {
1016 /* Code below uses GEN_INT, so we need the masks to be representable
1017 in HOST_WIDE_INTs. */
1020 /* If op0 is e.g. -1 or -2 unsigned, then the 2 additions might
1021 overflow. Consider 64-bit -1ULL for word size 32, if we add
1022 0x7fffffffU + 0x7fffffffU + 3U, it wraps around to 1. */
1030 {
1031 /* For signed modulo, compute it as unsigned modulo of
1032 sum with a correction added to it if OP0 is negative,
1033 such that the result can be computed as unsigned
1034 remainder + ((OP1 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1). */
1038 /* wmod2 == -wmod1. */
1041 {
1045 /* Now verify if the count sums can't overflow, and punt
1046 if they could. */
1057 mode);
1066 OPTAB_DIRECT);
1069 }
1070 }
1073 {
1087 OPTAB_DIRECT);
1092 else
1097 }
1099 {
1104 }
1105 }
1113 {
1115 {
1117 mode);
1123 }
1126 word_mode),
1134 }
1137 /* Punt if we need any library calls. */
1142 }
1144 }
1146 /* Similarly to the above function, but compute both quotient and remainder.
1147 Quotient can be computed from the remainder as:
1148 rem = op0 % op1; // Handled using expand_doubleword_mod
1149 quot = (op0 - rem) * inv; // inv is multiplicative inverse of op1 modulo
1150 // 2 * BITS_PER_WORD
1152 We can also handle cases where op1 is a multiple of power of two constant
1153 and constant handled by expand_doubleword_mod.
1154 op11 = 1 << __builtin_ctz (op1);
1155 op12 = op1 / op11;
1156 rem1 = op0 % op12; // Handled using expand_doubleword_mod
1157 quot1 = (op0 - rem1) * inv; // inv is multiplicative inverse of op12 modulo
1158 // 2 * BITS_PER_WORD
1159 rem = (quot1 % op11) * op12 + rem1;
1160 quot = quot1 / op11; */
1162 rtx
1165 {
1168 /* Negative dividend should have been optimized into positive,
1169 similarly modulo by 1 and modulo by power of two is optimized
1170 differently too. */
1177 {
1181 }
1205 {
1228 }
1230 /* Punt if we need any library calls. */
1237 }
1238 \f
1239 /* Wrapper around expand_binop which takes an rtx code to specify
1240 the operation to perform, not an optab pointer. All other
1241 arguments are the same. */
1242 rtx
1246 {
1251 }
1253 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1254 binop. Order them according to commutative_operand_precedence and, if
1255 possible, try to put TARGET or a pseudo first. */
1256 static bool
1258 {
1268 /* With equal precedence, both orders are ok, but it is better if the
1269 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1272 else
1274 }
1276 /* Return true if BINOPTAB implements a shift operation. */
1278 static bool
1280 {
1282 {
1294 }
1295 }
1297 /* Return true if BINOPTAB implements a commutative binary operation. */
1299 static bool
1301 {
1307 }
1309 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1310 optimizing, and if the operand is a constant that costs more than
1311 1 instruction, force the constant into a register and return that
1312 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1314 static rtx
1317 {
1321 && optimize
1325 {
1327 {
1331 }
1332 else
1335 }
1337 }
1339 /* Helper function for expand_binop: handle the case where there
1340 is an insn ICODE that directly implements the indicated operation.
1341 Returns null if this is not possible. */
1342 static rtx
1347 {
1357 /* If it is a commutative operator and the modes would match
1358 if we would swap the operands, we can save the conversions. */
1365 /* If we are optimizing, force expensive constants into a register. */
1369 else
1370 /* Shifts and rotates often use a different mode for op1 from op0;
1371 for VOIDmode constants we don't know the mode, so force it
1372 to be canonicalized using convert_modes. */
1375 /* In case the insn wants input operands in modes different from
1376 those of the actual operands, convert the operands. It would
1377 seem that we don't need to convert CONST_INTs, but we do, so
1378 that they're properly zero-extended, sign-extended or truncated
1379 for their mode. */
1383 {
1386 }
1391 {
1394 }
1396 /* If operation is commutative,
1397 try to make the first operand a register.
1398 Even better, try to make it the same as the target.
1399 Also try to make the last operand a constant. */
1404 /* Now, if insn's predicates don't allow our operands, put them into
1405 pseudo regs. */
1414 {
1415 /* The mode of the result is different then the mode of the
1416 arguments. */
1420 {
1423 }
1424 }
1425 else
1433 {
1434 /* If PAT is composed of more than one insn, try to add an appropriate
1435 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1436 operand, call expand_binop again, this time without a target. */
1441 {
1445 }
1449 }
1452 }
1454 /* Generate code to perform an operation specified by BINOPTAB
1455 on operands OP0 and OP1, with result having machine-mode MODE.
1457 UNSIGNEDP is for the case where we have to widen the operands
1458 to perform the operation. It says to use zero-extension.
1460 If TARGET is nonzero, the value
1461 is generated there, if it is convenient to do so.
1462 In all cases an rtx is returned for the locus of the value;
1463 this may or may not be TARGET. */
1465 rtx
1468 {
1469 enum optab_methods next_methods
1474 machine_mode wider_mode;
1475 scalar_int_mode int_mode;
1476 rtx libfunc;
1477 rtx temp;
1483 /* If subtracting an integer constant, convert this into an addition of
1484 the negated constant. */
1487 {
1490 }
1491 /* For shifts, constant invalid op1 might be expanded from different
1492 mode than MODE. As those are invalid, force them to a register
1493 to avoid further problems during expansion. */
1497 {
1500 }
1502 /* Record where to delete back to if we backtrack. */
1505 /* If we can do it with a three-operand insn, do so. */
1508 {
1510 {
1513 }
1514 else
1517 {
1522 }
1523 }
1525 /* If we were trying to rotate, and that didn't work, try rotating
1526 the other direction before falling back to shifts and bitwise-or. */
1532 {
1534 rtx newop1;
1541 else
1550 }
1552 /* If this is a multiply, see if we can do a widening operation that
1553 takes operands of this mode and makes a wider mode. */
1558 ? umul_widen_optab
1561 {
1562 /* *_widen_optab needs to determine operand mode, make sure at least
1563 one operand has non-VOID mode. */
1571 {
1575 else
1577 }
1578 }
1580 /* If this is a vector shift by a scalar, see if we can do a vector
1581 shift by a vector. If so, broadcast the scalar into a vector. */
1583 {
1599 {
1600 /* The scalar may have been extended to be too wide. Truncate
1601 it back to the proper size to fit in the broadcast vector. */
1611 {
1616 }
1617 }
1618 }
1620 /* Look for a wider mode of the same class for which we think we
1621 can open-code the operation. Check for a widening multiply at the
1622 wider mode as well. */
1627 {
1628 machine_mode next_mode;
1633 ? umul_widen_optab
1637 {
1641 /* For certain integer operations, we need not actually extend
1642 the narrow operands, as long as we will truncate
1643 the results to the same narrowness. */
1650 {
1657 }
1661 /* The second operand of a shift must always be extended. */
1668 {
1671 {
1676 }
1677 else
1679 }
1680 else
1682 }
1683 }
1685 /* If operation is commutative,
1686 try to make the first operand a register.
1687 Even better, try to make it the same as the target.
1688 Also try to make the last operand a constant. */
1693 /* These can be done a word at a time. */
1698 {
1702 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1703 won't be accurate, so use a new target. */
1714 /* Do the actual arithmetic. */
1722 {
1734 }
1740 {
1743 }
1744 }
1746 /* Synthesize double word shifts from single word shifts. */
1756 {
1758 scalar_int_mode op1_mode;
1766 /* Apply the truncation to constant shifts. */
1773 /* Make sure that this is a combination that expand_doubleword_shift
1774 can handle. See the comments there for details. */
1778 {
1784 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1785 won't be accurate, so use a new target. */
1796 /* OUTOF_* is the word we are shifting bits away from, and
1797 INTO_* is the word that we are shifting bits towards, thus
1798 they differ depending on the direction of the shift and
1799 WORDS_BIG_ENDIAN. */
1814 {
1820 }
1822 }
1823 }
1825 /* Synthesize double word rotates from single word shifts. */
1832 {
1836 rtx inter;
1839 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1840 won't be accurate, so use a new target. Do this also if target is not
1841 a REG, first because having a register instead may open optimization
1842 opportunities, and second because if target and op0 happen to be MEMs
1843 designating the same location, we would risk clobbering it too early
1844 in the code sequence we generate below. */
1858 /* OUTOF_* is the word we are shifting bits away from, and
1859 INTO_* is the word that we are shifting bits towards, thus
1860 they differ depending on the direction of the shift and
1861 WORDS_BIG_ENDIAN. */
1873 {
1874 /* This is just a word swap. */
1878 }
1879 else
1880 {
1892 {
1895 }
1896 else
1897 {
1900 }
1901 rtx first_shift_count_rtx
1903 rtx second_shift_count_rtx
1916 else
1936 }
1942 {
1945 }
1946 }
1948 /* These can be done a word at a time by propagating carries. */
1953 {
1960 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1961 value is one of those, use it. Otherwise, use 1 since it is the
1962 one easiest to get. */
1963 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1965 #else
1967 #endif
1969 /* Prepare the operands. */
1978 /* Indicate for flow that the entire target reg is being set. */
1982 /* Do the actual arithmetic. */
1984 {
1989 rtx x;
1991 /* Main add/subtract of the input operands. */
1999 {
2000 /* Store carry from main add/subtract. */
2007 }
2010 {
2011 rtx newx;
2013 /* Add/subtract previous carry to main result. */
2020 {
2021 /* Get out carry from adding/subtracting carry in. */
2029 /* Logical-ior the two poss. carry together. */
2035 }
2037 }
2038 else
2039 {
2042 }
2045 }
2048 {
2051 {
2058 target);
2059 }
2060 else
2064 }
2066 else
2068 }
2070 /* Attempt to synthesize double word multiplies using a sequence of word
2071 mode multiplications. We first attempt to generate a sequence using a
2072 more efficient unsigned widening multiply, and if that fails we then
2073 try using a signed widening multiply. */
2080 {
2084 {
2089 }
2094 {
2099 }
2102 {
2104 {
2106 product);
2108 REG_EQUAL,
2113 }
2115 }
2116 }
2118 /* Attempt to synthetize double word modulo by constant divisor. */
2123 && optimize
2129 int_mode) == CODE_FOR_nothing
2133 {
2139 else
2140 {
2142 binoptab == umod_optab
2148 }
2150 {
2152 {
2154 res);
2159 }
2161 }
2162 else
2164 }
2166 /* It can't be open-coded in this mode.
2167 Use a library call if one is available and caller says that's ok. */
2172 {
2176 rtx value;
2181 {
2183 /* Specify unsigned here,
2184 since negative shift counts are meaningless. */
2186 }
2192 /* Pass 1 for NO_QUEUE so we don't lose any increments
2193 if the libcall is cse'd or moved. */
2204 trapv ? NULL_RTX
2209 }
2213 /* It can't be done in this mode. Can we do it in a wider mode? */
2217 {
2218 /* Caller says, don't even try. */
2221 }
2223 /* Compute the value of METHODS to pass to recursive calls.
2224 Don't allow widening to be tried recursively. */
2228 /* Look for a wider mode of the same class for which it appears we can do
2229 the operation. */
2232 {
2233 /* This code doesn't make sense for conversion optabs, since we
2234 wouldn't then want to extend the operands to be the same size
2235 as the result. */
2238 {
2242 {
2246 /* For certain integer operations, we need not actually extend
2247 the narrow operands, as long as we will truncate
2248 the results to the same narrowness. */
2260 /* The second operand of a shift must always be extended. */
2267 {
2270 {
2275 }
2276 else
2278 }
2279 else
2281 }
2282 }
2283 }
2287 }
2288 \f
2289 /* Expand a binary operator which has both signed and unsigned forms.
2290 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2291 signed operations.
2293 If we widen unsigned operands, we may use a signed wider operation instead
2294 of an unsigned wider operation, since the result would be the same. */
2296 rtx
2300 {
2301 rtx temp;
2305 /* Do it without widening, if possible. */
2311 /* Try widening to a signed int. Disable any direct use of any
2312 signed insn in the current mode. */
2318 /* For unsigned operands, try widening to an unsigned int. */
2325 /* Use the right width libcall if that exists. */
2331 /* Must widen and use a libcall, use either signed or unsigned. */
2338 egress:
2339 /* Undo the fiddling above. */
2343 }
2344 \f
2345 /* Generate code to perform an operation specified by UNOPPTAB
2346 on operand OP0, with two results to TARG0 and TARG1.
2347 We assume that the order of the operands for the instruction
2348 is TARG0, TARG1, OP0.
2350 Either TARG0 or TARG1 may be zero, but what that means is that
2351 the result is not actually wanted. We will generate it into
2352 a dummy pseudo-reg and discard it. They may not both be zero.
2354 Returns 1 if this operation can be performed; 0 if not. */
2356 int
2359 {
2362 machine_mode wider_mode;
2373 /* Record where to go back to if we fail. */
2377 {
2386 }
2388 /* It can't be done in this mode. Can we do it in a wider mode? */
2391 {
2393 {
2395 {
2401 {
2405 }
2406 else
2408 }
2409 }
2410 }
2414 }
2415 \f
2416 /* Generate code to perform an operation specified by BINOPTAB
2417 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2418 We assume that the order of the operands for the instruction
2419 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2420 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2422 Either TARG0 or TARG1 may be zero, but what that means is that
2423 the result is not actually wanted. We will generate it into
2424 a dummy pseudo-reg and discard it. They may not both be zero.
2426 Returns 1 if this operation can be performed; 0 if not. */
2428 int
2431 {
2434 machine_mode wider_mode;
2445 /* Record where to go back to if we fail. */
2449 {
2456 /* If we are optimizing, force expensive constants into a register. */
2467 }
2469 /* It can't be done in this mode. Can we do it in a wider mode? */
2472 {
2474 {
2476 {
2484 {
2488 }
2489 else
2491 }
2492 }
2493 }
2497 }
2499 /* Expand the two-valued library call indicated by BINOPTAB, but
2500 preserve only one of the values. If TARG0 is non-NULL, the first
2501 value is placed into TARG0; otherwise the second value is placed
2502 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2503 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2504 This routine assumes that the value returned by the library call is
2505 as if the return value was of an integral mode twice as wide as the
2506 mode of OP0. Returns 1 if the call was successful. */
2508 bool
2511 {
2512 machine_mode mode;
2513 machine_mode libval_mode;
2514 rtx libval;
2516 rtx libfunc;
2518 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2526 /* The value returned by the library function will have twice as
2527 many bits as the nominal MODE. */
2531 libval_mode,
2534 /* Get the part of VAL containing the value that we want. */
2539 /* Move the into the desired location. */
2544 }
2546 \f
2547 /* Wrapper around expand_unop which takes an rtx code to specify
2548 the operation to perform, not an optab pointer. All other
2549 arguments are the same. */
2550 rtx
2553 {
2558 }
2560 /* Try calculating
2561 (clz:narrow x)
2562 as
2563 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2565 A similar operation can be used for clrsb. UNOPTAB says which operation
2566 we are trying to expand. */
2567 static rtx
2569 {
2570 opt_scalar_int_mode wider_mode_iter;
2572 {
2575 {
2588 temp = expand_binop
2592 wider_mode),
2598 }
2599 }
2601 }
2603 /* Attempt to emit (clrsb:mode op0) as
2604 (plus:mode (clz:mode (xor:mode op0 (ashr:mode op0 (const_int prec-1))))
2605 (const_int -1))
2606 if CLZ_DEFINED_VALUE_AT_ZERO (mode, val) is 2 and val is prec,
2607 or as
2608 (clz:mode (ior:mode (xor:mode (ashl:mode op0 (const_int 1))
2609 (ashr:mode op0 (const_int prec-1)))
2610 (const_int 1)))
2611 otherwise. */
2613 static rtx
2615 {
2625 else
2630 {
2634 {
2635 fail:
2638 }
2639 }
2648 OPTAB_DIRECT);
2653 {
2658 }
2664 {
2669 }
2677 }
2679 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2680 quantities, choosing which based on whether the high word is nonzero. */
2681 static rtx
2683 {
2692 /* If we were not given a target, use a word_mode register, not a
2693 'mode' register. The result will fit, and nobody is expecting
2694 anything bigger (the return type of __builtin_clz* is int). */
2698 /* In any case, write to a word_mode scratch in both branches of the
2699 conditional, so we can ensure there is a single move insn setting
2700 'target' to tag a REG_EQUAL note on. */
2705 /* If the high word is not equal to zero,
2706 then clz of the full value is clz of the high word. */
2720 /* Else clz of the full value is clz of the low word plus the number
2721 of bits in the high word. */
2745 fail:
2748 }
2750 /* Try calculating popcount of a double-word quantity as two popcount's of
2751 word-sized quantities and summing up the results. */
2752 static rtx
2754 {
2767 {
2770 }
2772 /* If we were not given a target, use a word_mode register, not a
2773 'mode' register. The result will fit, and nobody is expecting
2774 anything bigger (the return type of __builtin_popcount* is int). */
2786 }
2788 /* Try calculating
2789 (parity:wide x)
2790 as
2791 (parity:narrow (low (x) ^ high (x))) */
2792 static rtx
2794 {
2800 }
2802 /* Try calculating
2803 (bswap:narrow x)
2804 as
2805 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2806 static rtx
2808 {
2809 rtx x;
2811 opt_scalar_int_mode wider_mode_iter;
2836 {
2840 }
2841 else
2845 }
2847 /* Try calculating bswap as two bswaps of two word-sized operands. */
2849 static rtx
2851 {
2867 }
2869 /* Try calculating (parity x) as (and (popcount x) 1), where
2870 popcount can also be done in a wider mode. */
2871 static rtx
2873 {
2875 opt_scalar_int_mode wider_mode_iter;
2877 {
2880 {
2897 {
2901 else
2903 }
2904 else
2906 }
2907 }
2909 }
2911 /* Try calculating ctz(x) as K - clz(x & -x) ,
2912 where K is GET_MODE_PRECISION(mode) - 1.
2914 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2915 don't have to worry about what the hardware does in that case. (If
2916 the clz instruction produces the usual value at 0, which is K, the
2917 result of this code sequence will be -1; expand_ffs, below, relies
2918 on this. It might be nice to have it be K instead, for consistency
2919 with the (very few) processors that provide a ctz with a defined
2920 value, but that would take one more instruction, and it would be
2921 less convenient for expand_ffs anyway. */
2923 static rtx
2925 {
2927 rtx temp;
2946 {
2949 }
2957 }
2960 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2961 else with the sequence used by expand_clz.
2963 The ffs builtin promises to return zero for a zero value and ctz/clz
2964 may have an undefined value in that case. If they do not give us a
2965 convenient value, we have to generate a test and branch. */
2966 static rtx
2968 {
2971 rtx temp;
2975 {
2983 }
2985 {
2992 {
2995 }
2996 }
2997 else
3002 else
3003 {
3004 /* We don't try to do anything clever with the situation found
3005 on some processors (eg Alpha) where ctz(0:mode) ==
3006 bitsize(mode). If someone can think of a way to send N to -1
3007 and leave alone all values in the range 0..N-1 (where N is a
3008 power of two), cheaper than this test-and-branch, please add it.
3010 The test-and-branch is done after the operation itself, in case
3011 the operation sets condition codes that can be recycled for this.
3012 (This is true on i386, for instance.) */
3020 }
3022 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
3023 to produce a value in the range 0..bitsize. */
3036 fail:
3039 }
3041 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
3042 conditions, VAL may already be a SUBREG against which we cannot generate
3043 a further SUBREG. In this case, we expect forcing the value into a
3044 register will work around the situation. */
3046 static rtx
3048 machine_mode imode)
3049 {
3050 rtx ret;
3053 {
3057 }
3059 }
3061 /* Expand a floating point absolute value or negation operation via a
3062 logical operation on the sign bit. */
3064 static rtx
3067 {
3070 scalar_int_mode imode;
3071 rtx temp;
3074 /* The format has to have a simple sign bit. */
3083 /* Don't create negative zeros if the format doesn't support them. */
3088 {
3093 }
3094 else
3095 {
3100 else
3104 }
3117 {
3121 {
3126 {
3128 op0_piece,
3133 }
3134 else
3136 }
3142 }
3143 else
3144 {
3153 target);
3154 }
3157 }
3159 /* As expand_unop, but will fail rather than attempt the operation in a
3160 different mode or with a libcall. */
3161 static rtx
3164 {
3166 {
3176 {
3181 {
3184 }
3189 }
3190 }
3192 }
3194 /* Generate code to perform an operation specified by UNOPTAB
3195 on operand OP0, with result having machine-mode MODE.
3197 UNSIGNEDP is for the case where we have to widen the operands
3198 to perform the operation. It says to use zero-extension.
3200 If TARGET is nonzero, the value
3201 is generated there, if it is convenient to do so.
3202 In all cases an rtx is returned for the locus of the value;
3203 this may or may not be TARGET. */
3205 rtx
3208 {
3210 machine_mode wider_mode;
3211 scalar_int_mode int_mode;
3212 scalar_float_mode float_mode;
3213 rtx temp;
3214 rtx libfunc;
3220 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3222 /* Widening (or narrowing) clz needs special treatment. */
3224 {
3226 {
3233 {
3237 }
3238 }
3241 }
3244 {
3246 {
3253 }
3255 }
3262 {
3266 }
3274 {
3278 }
3280 /* Widening (or narrowing) bswap needs special treatment. */
3282 {
3283 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3284 or ROTATERT. First try these directly; if this fails, then try the
3285 obvious pair of shifts with allowed widening, as this will probably
3286 be always more efficient than the other fallback methods. */
3288 {
3293 {
3299 }
3302 {
3308 }
3319 {
3324 }
3327 }
3330 {
3335 /* We do not provide a 128-bit bswap in libgcc so force the use of
3336 a double bswap for 64-bit targets. */
3340 {
3344 }
3345 }
3348 }
3352 {
3354 {
3358 /* For certain operations, we need not actually extend
3359 the narrow operand, as long as we will truncate the
3360 results to the same narrowness. */
3368 unsignedp);
3371 {
3374 {
3379 }
3380 else
3382 }
3383 else
3385 }
3386 }
3388 /* These can be done a word at a time. */
3393 {
3405 /* Do the actual arithmetic. */
3407 {
3415 }
3422 }
3424 /* Emit ~op0 as op0 ^ -1. */
3428 {
3433 }
3436 {
3437 /* Try negating floating point values by flipping the sign bit. */
3439 {
3443 }
3445 /* If there is no negation pattern, and we have no negative zero,
3446 try subtracting from zero. */
3448 {
3455 }
3456 }
3458 /* Try calculating parity (x) as popcount (x) % 2. */
3460 {
3464 }
3466 /* Try implementing ffs (x) in terms of clz (x). */
3468 {
3472 }
3474 /* Try implementing ctz (x) in terms of clz (x). */
3476 {
3480 }
3482 try_libcall:
3483 /* Now try a library call in this mode. */
3486 {
3488 rtx value;
3489 rtx eq_value;
3492 /* All of these functions return small values. Thus we choose to
3493 have them return something that isn't a double-word. */
3497 outmode
3503 /* Pass 1 for NO_QUEUE so we don't lose any increments
3504 if the libcall is cse'd or moved. */
3514 else
3515 {
3522 }
3526 }
3528 /* It can't be done in this mode. Can we do it in a wider mode? */
3531 {
3533 {
3536 {
3540 /* For certain operations, we need not actually extend
3541 the narrow operand, as long as we will truncate the
3542 results to the same narrowness. */
3550 unsignedp);
3552 /* If we are generating clz using wider mode, adjust the
3553 result. Similarly for clrsb. */
3556 {
3557 scalar_int_mode wider_int_mode
3560 temp = expand_binop
3564 wider_int_mode),
3566 }
3568 /* Likewise for bswap. */
3570 {
3571 scalar_int_mode wider_int_mode
3583 }
3586 {
3588 {
3593 }
3594 else
3596 }
3597 else
3599 }
3600 }
3601 }
3603 /* One final attempt at implementing negation via subtraction,
3604 this time allowing widening of the operand. */
3606 {
3607 rtx temp;
3614 }
3617 }
3618 \f
3619 /* Emit code to compute the absolute value of OP0, with result to
3620 TARGET if convenient. (TARGET may be 0.) The return value says
3621 where the result actually is to be found.
3623 MODE is the mode of the operand; the mode of the result is
3624 different but can be deduced from MODE.
3626 */
3628 rtx
3631 {
3632 rtx temp;
3638 /* First try to do it with a special abs instruction. */
3644 /* For floating point modes, try clearing the sign bit. */
3645 scalar_float_mode float_mode;
3647 {
3651 }
3653 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3656 {
3663 OPTAB_WIDEN);
3669 }
3671 /* If this machine has expensive jumps, we can do integer absolute
3672 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3673 where W is the width of MODE. */
3675 scalar_int_mode int_mode;
3679 {
3685 OPTAB_LIB_WIDEN);
3693 }
3696 }
3698 rtx
3701 {
3702 rtx temp;
3713 /* If that does not win, use conditional jump and negate. */
3715 /* It is safe to use the target if it is the same
3716 as the source if this is also a pseudo register */
3730 NO_DEFER_POP;
3741 OK_DEFER_POP;
3743 }
3745 /* Emit code to compute the one's complement absolute value of OP0
3746 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3747 (TARGET may be NULL_RTX.) The return value says where the result
3748 actually is to be found.
3750 MODE is the mode of the operand; the mode of the result is
3751 different but can be deduced from MODE. */
3753 rtx
3755 {
3756 rtx temp;
3758 /* Not applicable for floating point modes. */
3762 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3764 {
3770 OPTAB_WIDEN);
3776 }
3778 /* If this machine has expensive jumps, we can do one's complement
3779 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3781 scalar_int_mode int_mode;
3785 {
3791 OPTAB_LIB_WIDEN);
3795 }
3798 }
3800 /* A subroutine of expand_copysign, perform the copysign operation using the
3801 abs and neg primitives advertised to exist on the target. The assumption
3802 is that we have a split register file, and leaving op0 in fp registers,
3803 and not playing with subregs so much, will help the register allocator. */
3805 static rtx
3808 {
3809 scalar_int_mode imode;
3811 rtx sign;
3817 /* Check if the back end provides an insn that handles signbit for the
3818 argument's mode. */
3821 {
3825 }
3826 else
3827 {
3829 {
3833 }
3834 else
3835 {
3841 else
3845 }
3851 }
3854 {
3859 }
3860 else
3861 {
3864 else
3866 }
3873 else
3881 }
3884 /* A subroutine of expand_copysign, perform the entire copysign operation
3885 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3886 is true if op0 is known to have its sign bit clear. */
3888 static rtx
3891 {
3892 scalar_int_mode imode;
3894 rtx temp;
3898 {
3903 }
3904 else
3905 {
3910 else
3914 }
3927 {
3931 {
3936 {
3938 op0_piece
3951 }
3952 else
3954 }
3960 }
3961 else
3962 {
3976 }
3979 }
3981 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3982 scalar floating point mode. Return NULL if we do not know how to
3983 expand the operation inline. */
3985 rtx
3987 {
3988 scalar_float_mode mode;
3991 rtx temp;
3996 /* First try to do it with a special instruction. */
4008 {
4012 }
4018 {
4023 }
4029 }
4030 \f
4031 /* Generate an instruction whose insn-code is INSN_CODE,
4032 with two operands: an output TARGET and an input OP0.
4033 TARGET *must* be nonzero, and the output is always stored there.
4034 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4035 the value that is stored into TARGET.
4037 Return false if expansion failed. */
4039 bool
4042 {
4062 }
4063 /* Generate an instruction whose insn-code is INSN_CODE,
4064 with two operands: an output TARGET and an input OP0.
4065 TARGET *must* be nonzero, and the output is always stored there.
4066 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4067 the value that is stored into TARGET. */
4069 void
4071 {
4074 }
4075 \f
4076 struct no_conflict_data
4077 {
4078 rtx target;
4081 };
4083 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
4084 the currently examined clobber / store has to stay in the list of
4085 insns that constitute the actual libcall block. */
4086 static void
4088 {
4091 /* If this inns directly contributes to setting the target, it must stay. */
4094 /* If we haven't committed to keeping any other insns in the list yet,
4095 there is nothing more to check. */
4098 /* If this insn sets / clobbers a register that feeds one of the insns
4099 already in the list, this insn has to stay too. */
4103 /* Likewise if this insn depends on a register set by a previous
4104 insn in the list, or if it sets a result (presumably a hard
4105 register) that is set or clobbered by a previous insn.
4106 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
4107 SET_DEST perform the former check on the address, and the latter
4108 check on the MEM. */
4115 }
4117 \f
4118 /* Emit code to make a call to a constant function or a library call.
4120 INSNS is a list containing all insns emitted in the call.
4121 These insns leave the result in RESULT. Our block is to copy RESULT
4122 to TARGET, which is logically equivalent to EQUIV.
4124 We first emit any insns that set a pseudo on the assumption that these are
4125 loading constants into registers; doing so allows them to be safely cse'ed
4126 between blocks. Then we emit all the other insns in the block, followed by
4127 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
4128 note with an operand of EQUIV. */
4130 static void
4133 {
4137 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
4138 into a MEM later. Protect the libcall block from this change. */
4142 /* If we're using non-call exceptions, a libcall corresponding to an
4143 operation that may trap may also trap. */
4144 /* ??? See the comment in front of make_reg_eh_region_note. */
4147 {
4150 {
4153 {
4157 }
4158 }
4159 }
4160 else
4161 {
4162 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
4163 reg note to indicate that this call cannot throw or execute a nonlocal
4164 goto (unless there is already a REG_EH_REGION note, in which case
4165 we update it). */
4169 }
4171 /* First emit all insns that set pseudos. Remove them from the list as
4172 we go. Avoid insns that set pseudos which were referenced in previous
4173 insns. These can be generated by move_by_pieces, for example,
4174 to update an address. Similarly, avoid insns that reference things
4175 set in previous insns. */
4178 {
4185 {
4194 {
4197 else
4204 }
4205 }
4207 /* Some ports use a loop to copy large arguments onto the stack.
4208 Don't move anything outside such a loop. */
4211 }
4213 /* Write the remaining insns followed by the final copy. */
4215 {
4219 }
4227 }
4229 void
4231 {
4233 }
4234 \f
4235 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4236 PURPOSE describes how this comparison will be used. CODE is the rtx
4237 comparison code we will be using.
4239 ??? Actually, CODE is slightly weaker than that. A target is still
4240 required to implement all of the normal bcc operations, but not
4241 required to implement all (or any) of the unordered bcc operations. */
4243 int
4246 {
4247 rtx test;
4249 do
4250 {
4267 }
4271 }
4273 /* Return whether RTL code CODE corresponds to an unsigned optab. */
4275 static bool
4277 {
4279 }
4281 /* Return whether the backend-emitted comparison for code CODE, comparing
4282 operands of mode VALUE_MODE and producing a result with MASK_MODE, matches
4283 operand OPNO of pattern ICODE. */
4285 static bool
4288 machine_mode value_mode)
4289 {
4294 }
4296 /* Return whether the backend can emit a vector comparison (vec_cmp/vec_cmpu)
4297 for code CODE, comparing operands of mode VALUE_MODE and producing a result
4298 with MASK_MODE. */
4300 bool
4302 machine_mode mask_mode)
4303 {
4304 enum insn_code icode
4310 }
4312 /* Return whether the backend can emit a vector comparison (vcond/vcondu) for
4313 code CODE, comparing operands of mode CMP_OP_MODE and producing a result
4314 with VALUE_MODE. */
4316 bool
4318 machine_mode cmp_op_mode)
4319 {
4320 enum insn_code icode
4326 }
4328 /* Return whether the backend can emit vector set instructions for inserting
4329 element into vector at variable index position. */
4331 bool
4333 {
4347 }
4349 /* This function is called when we are going to emit a compare instruction that
4350 compares the values found in X and Y, using the rtl operator COMPARISON.
4352 If they have mode BLKmode, then SIZE specifies the size of both operands.
4354 UNSIGNEDP nonzero says that the operands are unsigned;
4355 this matters if they need to be widened (as given by METHODS).
4357 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
4358 if we failed to produce one.
4360 *PMODE is the mode of the inputs (in case they are const_int).
4362 This function performs all the setup necessary so that the caller only has
4363 to emit a single comparison insn. This setup can involve doing a BLKmode
4364 comparison or emitting a library call to perform the comparison if no insn
4365 is available to handle it.
4366 The values which are passed in through pointers can be modified; the caller
4367 should perform the comparison on the modified values. Constant
4368 comparisons must have already been folded. */
4370 static void
4374 {
4377 machine_mode cmp_mode;
4380 /* The other methods are not needed. */
4387 /* If we are optimizing, force expensive constants into a register. */
4398 /* Don't let both operands fail to indicate the mode. */
4404 /* Handle all BLKmode compares. */
4407 {
4408 machine_mode result_mode;
4410 rtx result;
4411 rtx opalign
4416 /* Try to use a memory block compare insn - either cmpstr
4417 or cmpmem will do. */
4418 opt_scalar_int_mode cmp_mode_iter;
4420 {
4430 /* Must make sure the size fits the insn's mode. */
4445 }
4450 /* Otherwise call a library function. */
4458 }
4460 /* Don't allow operands to the compare to trap, as that can put the
4461 compare and branch in different basic blocks. */
4463 {
4468 }
4471 {
4478 }
4483 {
4488 {
4495 {
4501 }
4503 }
4507 }
4513 {
4514 /* Small trick if UNORDERED isn't implemented by the hardware. */
4516 {
4521 }
4524 }
4525 else
4526 {
4527 rtx result;
4528 machine_mode ret_mode;
4530 /* Handle a libcall just for the mode we are using. */
4534 /* If we want unsigned, and this mode has a distinct unsigned
4535 comparison routine, use that. */
4537 {
4541 }
4547 /* There are two kinds of comparison routines. Biased routines
4548 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4549 of gcc expect that the comparison operation is equivalent
4550 to the modified comparison. For signed comparisons compare the
4551 result against 1 in the biased case, and zero in the unbiased
4552 case. For unsigned comparisons always compare against 1 after
4553 biasing the unbiased result by adding 1. This gives us a way to
4554 represent LTU.
4555 The comparisons in the fixed-point helper library are always
4556 biased. */
4561 {
4564 else
4566 }
4571 }
4575 fail:
4577 }
4579 /* Before emitting an insn with code ICODE, make sure that X, which is going
4580 to be used for operand OPNUM of the insn, is converted from mode MODE to
4581 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4582 that it is accepted by the operand predicate. Return the new value. */
4584 rtx
4587 {
4592 {
4599 }
4602 }
4604 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4605 we can do the branch. */
4607 static void
4609 profile_probability prob)
4610 {
4611 machine_mode optab_mode;
4626 && insn
4631 }
4633 /* Generate code to compare X with Y so that the condition codes are
4634 set and to jump to LABEL if the condition is true. If X is a
4635 constant and Y is not a constant, then the comparison is swapped to
4636 ensure that the comparison RTL has the canonical form.
4638 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4639 need to be widened. UNSIGNEDP is also used to select the proper
4640 branch condition code.
4642 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4644 MODE is the mode of the inputs (in case they are const_int).
4646 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4647 It will be potentially converted into an unsigned variant based on
4648 UNSIGNEDP to select a proper jump instruction.
4650 PROB is the probability of jumping to LABEL. */
4652 void
4655 profile_probability prob)
4656 {
4658 rtx test;
4660 /* Swap operands and condition to ensure canonical RTL. */
4663 {
4666 }
4668 /* If OP0 is still a constant, then both X and Y must be constants
4669 or the opposite comparison is not supported. Force X into a register
4670 to create canonical RTL. */
4680 }
4682 \f
4683 /* Emit a library call comparison between floating point X and Y.
4684 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4686 static void
4689 {
4693 machine_mode mode;
4702 {
4709 {
4713 }
4717 {
4721 }
4722 }
4727 {
4730 }
4732 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4733 the RTL. The allows the RTL optimizers to delete the libcall if the
4734 condition can be determined at compile-time. */
4737 {
4740 }
4741 else
4742 {
4744 {
4777 }
4778 }
4781 {
4786 }
4787 else
4788 {
4793 }
4808 else
4812 }
4813 \f
4814 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4816 void
4818 {
4821 else
4822 {
4827 }
4828 }
4829 \f
4831 /* Emit a conditional move instruction if the machine supports one for that
4832 condition and machine mode.
4834 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4835 the mode to use should they be constants. If it is VOIDmode, they cannot
4836 both be constants.
4838 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4839 should be stored there. MODE is the mode to use should they be constants.
4840 If it is VOIDmode, they cannot both be constants.
4842 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4843 is not supported. */
4845 rtx
4849 {
4850 rtx comparison;
4855 /* If the two source operands are identical, that's just a move. */
4858 {
4864 }
4866 /* If one operand is constant, make it the second one. Only do this
4867 if the other operand is not constant as well. */
4870 {
4873 }
4875 /* get_condition will prefer to generate LT and GT even if the old
4876 comparison was against zero, so undo that canonicalization here since
4877 comparisons against zero are cheaper. */
4891 {
4895 }
4909 {
4913 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4914 punt and let the caller figure out how best to deal with this
4915 situation. */
4917 {
4918 saved_pending_stack_adjust save;
4927 {
4935 {
4939 }
4940 }
4943 }
4948 /* If the preferred op2/op3 order is not usable, retry with other
4949 operand order, perhaps it will expand successfully. */
4953 NULL))
4956 else
4959 }
4960 }
4963 /* Emit a conditional negate or bitwise complement using the
4964 negcc or notcc optabs if available. Return NULL_RTX if such operations
4965 are not available. Otherwise return the RTX holding the result.
4966 TARGET is the desired destination of the result. COMP is the comparison
4967 on which to negate. If COND is true move into TARGET the negation
4968 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
4969 CODE is either NEG or NOT. MODE is the machine mode in which the
4970 operation is performed. */
4972 rtx
4975 rtx op2)
4976 {
4982 else
5002 {
5007 }
5010 }
5012 /* Emit a conditional addition instruction if the machine supports one for that
5013 condition and machine mode.
5015 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
5016 the mode to use should they be constants. If it is VOIDmode, they cannot
5017 both be constants.
5019 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
5020 should be stored there. MODE is the mode to use should they be constants.
5021 If it is VOIDmode, they cannot both be constants.
5023 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
5024 is not supported. */
5026 rtx
5030 {
5031 rtx comparison;
5035 /* If one operand is constant, make it the second one. Only do this
5036 if the other operand is not constant as well. */
5039 {
5042 }
5044 /* get_condition will prefer to generate LT and GT even if the old
5045 comparison was against zero, so undo that canonicalization here since
5046 comparisons against zero are cheaper. */
5069 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5070 return NULL and let the caller figure out how best to deal with this
5071 situation. */
5081 {
5089 {
5093 }
5094 }
5097 }
5098 \f
5099 /* These functions attempt to generate an insn body, rather than
5100 emitting the insn, but if the gen function already emits them, we
5101 make no attempt to turn them back into naked patterns. */
5103 /* Generate and return an insn body to add Y to X. */
5105 rtx_insn *
5107 {
5115 }
5117 /* Generate and return an insn body to add r1 and c,
5118 storing the result in r0. */
5120 rtx_insn *
5122 {
5132 }
5134 int
5136 {
5152 }
5154 /* Generate and return an insn body to add Y to X. */
5156 rtx_insn *
5158 {
5166 }
5168 /* Return true if the target implements an addptr pattern and X, Y,
5169 and Z are valid for the pattern predicates. */
5171 int
5173 {
5189 }
5191 /* Generate and return an insn body to subtract Y from X. */
5193 rtx_insn *
5195 {
5203 }
5205 /* Generate and return an insn body to subtract r1 and c,
5206 storing the result in r0. */
5208 rtx_insn *
5210 {
5220 }
5222 int
5224 {
5240 }
5241 \f
5242 /* Generate the body of an insn to extend Y (with mode MFROM)
5243 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
5245 rtx_insn *
5248 {
5251 }
5252 \f
5253 /* Generate code to convert FROM to floating point
5254 and store in TO. FROM must be fixed point and not VOIDmode.
5255 UNSIGNEDP nonzero means regard FROM as unsigned.
5256 Normally this is done by correcting the final value
5257 if it is negative. */
5259 void
5261 {
5268 /* Crash now, because we won't be able to decide which mode to use. */
5271 /* Look for an insn to do the conversion. Do it in the specified
5272 modes if possible; otherwise convert either input, output or both to
5273 wider mode. If the integer mode is wider than the mode of FROM,
5274 we can do the conversion signed even if the input is unsigned. */
5278 {
5288 {
5294 }
5297 {
5310 }
5311 }
5313 /* Unsigned integer, and no way to convert directly. Convert as signed,
5314 then unconditionally adjust the result. */
5316 && can_do_signed
5319 {
5320 opt_scalar_mode fmode_iter;
5322 rtx temp;
5323 REAL_VALUE_TYPE offset;
5325 /* Look for a usable floating mode FMODE wider than the source and at
5326 least as wide as the target. Using FMODE will avoid rounding woes
5327 with unsigned values greater than the signed maximum value. */
5330 {
5335 }
5338 {
5339 /* There is no such mode. Pretend the target is wide enough. */
5342 /* Avoid double-rounding when TO is narrower than FROM. */
5345 {
5346 rtx temp1;
5349 /* Don't use TARGET if it isn't a register, is a hard register,
5350 or is the wrong mode. */
5359 /* Test whether the sign bit is set. */
5363 /* The sign bit is not set. Convert as signed. */
5368 /* The sign bit is set.
5369 Convert to a usable (positive signed) value by shifting right
5370 one bit, while remembering if a nonzero bit was shifted
5371 out; i.e., compute (from & 1) | (from >> 1). */
5378 OPTAB_LIB_WIDEN);
5381 /* Multiply by 2 to undo the shift above. */
5390 }
5391 }
5393 /* If we are about to do some arithmetic to correct for an
5394 unsigned operand, do it in a pseudo-register. */
5400 /* Convert as signed integer to floating. */
5403 /* If FROM is negative (and therefore TO is negative),
5404 correct its value by 2**bitwidth. */
5421 }
5423 /* No hardware instruction available; call a library routine. */
5424 {
5425 rtx libfunc;
5427 rtx value;
5446 }
5448 done:
5450 /* Copy result to requested destination
5451 if we have been computing in a temp location. */
5454 {
5457 else
5459 }
5460 }
5461 \f
5462 /* Generate code to convert FROM to fixed point and store in TO. FROM
5463 must be floating point. */
5465 void
5467 {
5471 opt_scalar_mode fmode_iter;
5474 /* We first try to find a pair of modes, one real and one integer, at
5475 least as wide as FROM and TO, respectively, in which we can open-code
5476 this conversion. If the integer mode is wider than the mode of TO,
5477 we can do the conversion either signed or unsigned. */
5481 {
5489 {
5495 {
5499 }
5506 {
5510 }
5512 }
5513 }
5515 /* For an unsigned conversion, there is one more way to do it.
5516 If we have a signed conversion, we generate code that compares
5517 the real value to the largest representable positive number. If if
5518 is smaller, the conversion is done normally. Otherwise, subtract
5519 one plus the highest signed number, convert, and add it back.
5521 We only need to check all real modes, since we know we didn't find
5522 anything with a wider integer mode.
5524 This code used to extend FP value into mode wider than the destination.
5525 This is needed for decimal float modes which cannot accurately
5526 represent one plus the highest signed number of the same size, but
5527 not for binary modes. Consider, for instance conversion from SFmode
5528 into DImode.
5530 The hot path through the code is dealing with inputs smaller than 2^63
5531 and doing just the conversion, so there is no bits to lose.
5533 In the other path we know the value is positive in the range 2^63..2^64-1
5534 inclusive. (as for other input overflow happens and result is undefined)
5535 So we know that the most important bit set in mantissa corresponds to
5536 2^63. The subtraction of 2^63 should not generate any rounding as it
5537 simply clears out that bit. The rest is trivial. */
5539 scalar_int_mode to_mode;
5544 {
5550 {
5552 REAL_VALUE_TYPE offset;
5553 rtx limit;
5566 /* See if we need to do the subtraction. */
5571 /* If not, do the signed "fix" and branch around fixup code. */
5576 /* Otherwise, subtract 2**(N-1), convert to signed number,
5577 then add 2**(N-1). Do the addition using XOR since this
5578 will often generate better code. */
5584 gen_int_mode
5586 to_mode),
5595 {
5596 /* Make a place for a REG_NOTE and add it. */
5601 to);
5602 }
5605 }
5606 }
5608 /* We can't do it with an insn, so use a library call. But first ensure
5609 that the mode of TO is at least as wide as SImode, since those are the
5610 only library calls we know about. */
5613 {
5617 }
5618 else
5619 {
5621 rtx value;
5622 rtx libfunc;
5638 }
5641 {
5644 else
5646 }
5647 }
5650 /* Promote integer arguments for a libcall if necessary.
5651 emit_library_call_value cannot do the promotion because it does not
5652 know if it should do a signed or unsigned promotion. This is because
5653 there are no tree types defined for libcalls. */
5655 static rtx
5657 {
5658 scalar_int_mode mode;
5659 machine_mode arg_mode;
5661 {
5662 /* If we need to promote the integer function argument we need to do
5663 it here instead of inside emit_library_call_value because in
5664 emit_library_call_value we don't know if we should do a signed or
5665 unsigned promotion. */
5672 }
5674 }
5676 /* Generate code to convert FROM or TO a fixed-point.
5677 If UINTP is true, either TO or FROM is an unsigned integer.
5678 If SATP is true, we need to saturate the result. */
5680 void
5682 {
5685 convert_optab tab;
5689 rtx value;
5690 rtx libfunc;
5693 {
5696 }
5699 {
5702 }
5703 else
5704 {
5707 }
5710 {
5713 }
5729 }
5731 /* Generate code to convert FROM to fixed point and store in TO. FROM
5732 must be floating point, TO must be signed. Use the conversion optab
5733 TAB to do the conversion. */
5735 bool
5737 {
5742 /* We first try to find a pair of modes, one real and one integer, at
5743 least as wide as FROM and TO, respectively, in which we can open-code
5744 this conversion. If the integer mode is wider than the mode of TO,
5745 we can do the conversion either signed or unsigned. */
5749 {
5752 {
5761 {
5764 }
5768 }
5769 }
5772 }
5773 \f
5774 /* Report whether we have an instruction to perform the operation
5775 specified by CODE on operands of mode MODE. */
5776 int
5778 {
5782 }
5784 /* Print information about the current contents of the optabs on
5785 STDERR. */
5787 DEBUG_FUNCTION void
5789 {
5792 /* Dump the arithmetic optabs. */
5795 {
5798 {
5804 }
5805 }
5807 /* Dump the conversion optabs. */
5811 {
5815 {
5822 }
5823 }
5824 }
5826 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5827 CODE. Return 0 on failure. */
5829 rtx_insn *
5831 {
5835 rtx trap_rtx;
5844 /* Some targets only accept a zero trap code. */
5854 else
5856 tcode);
5858 /* If that failed, then give up. */
5860 {
5863 }
5869 }
5871 /* Return rtx code for TCODE or UNKNOWN. Use UNSIGNEDP to select signed
5872 or unsigned operation code. */
5874 enum rtx_code
5876 {
5879 {
5935 }
5937 }
5939 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
5940 or unsigned operation code. */
5942 enum rtx_code
5944 {
5948 }
5950 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
5951 select signed or unsigned operators. OPNO holds the index of the
5952 first comparison operand for insn ICODE. Do not generate the
5953 compare instruction itself. */
5955 rtx
5959 {
5967 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
5968 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
5969 cases, use the original mode. */
5971 EXPAND_STACK_PARM);
5977 EXPAND_STACK_PARM);
5987 }
5989 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
5990 the first vec_perm operand, assuming the second operand (for left shift
5991 first operand) is a constant vector of zeros. Return the shift distance
5992 in bits if so, or NULL_RTX if the vec_perm is not a shift. MODE is the
5993 mode of the value being shifted. SHIFT_OPTAB is vec_shr_optab for right
5994 shift or vec_shl_optab for left shift. */
5995 static rtx
5997 optab shift_optab)
5998 {
6005 {
6011 {
6013 {
6017 }
6022 }
6027 }
6029 {
6034 {
6036 /* Indices into the second vector are all equivalent. */
6041 }
6042 }
6045 }
6047 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
6049 static rtx
6052 {
6062 /* Make an effort to preserve v0 == v1. The target expander is able to
6063 rely on this to determine if we're permuting a single input operand. */
6065 {
6073 }
6074 else
6075 {
6078 }
6083 }
6085 /* Implement a permutation of vectors v0 and v1 using the permutation
6086 vector in SEL and return the result. Use TARGET to hold the result
6087 if nonnull and convenient.
6089 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
6090 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
6091 to have a particular mode. */
6093 rtx
6096 rtx target)
6097 {
6101 /* Set QIMODE to a different vector mode with byte elements.
6102 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6103 machine_mode qimode;
6110 /* Always specify two input vectors here and leave the target to handle
6111 cases in which the inputs are equal. Not all backends can cope with
6112 the single-input representation when testing for a double-input
6113 target instruction. */
6116 /* See if this can be handled with a vec_shr or vec_shl. We only do this
6117 if the second (for vec_shr) or first (for vec_shl) vector is all
6118 zeroes. */
6126 {
6129 }
6131 {
6136 }
6138 {
6141 {
6146 {
6152 }
6154 {
6161 }
6162 }
6163 }
6166 {
6172 }
6174 /* Fall back to a constant byte-based permutation. */
6175 vec_perm_indices qimode_indices;
6178 {
6187 }
6194 /* Otherwise expand as a fully variable permuation. */
6196 /* The optabs are only defined for selectors with the same width
6197 as the values being permuted. */
6198 machine_mode required_sel_mode;
6200 {
6203 }
6205 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
6206 If that isn't the mode we want then we need to prove that using
6207 REQUIRED_SEL_MODE is OK. */
6209 {
6211 {
6214 }
6216 }
6220 {
6225 }
6229 {
6232 {
6237 }
6238 }
6242 }
6244 /* Implement a permutation of vectors v0 and v1 using the permutation
6245 vector in SEL and return the result. Use TARGET to hold the result
6246 if nonnull and convenient.
6248 MODE is the mode of the vectors being permuted (V0 and V1).
6249 SEL must have the integer equivalent of MODE and is known to be
6250 unsuitable for permutes with a constant permutation vector. */
6252 rtx
6254 {
6266 {
6270 }
6272 /* As a special case to aid several targets, lower the element-based
6273 permutation to a byte-based permutation and try again. */
6274 machine_mode qimode;
6282 /* Multiply each element by its byte size. */
6287 else
6293 /* Broadcast the low byte each element into each of its bytes.
6294 The encoding has U interleaved stepped patterns, one for each
6295 byte of an element. */
6305 /* Add the byte offset to each byte element. */
6306 /* Note that the definition of the indicies here is memory ordering,
6307 so there should be no difference between big and little endian. */
6322 }
6324 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
6325 Use TARGET for the result if nonnull and convenient. */
6327 rtx
6329 {
6343 }
6345 /* Generate insns for a vector comparison into a mask. */
6347 rtx
6349 {
6352 rtx comparison;
6354 machine_mode vmode;
6368 {
6373 }
6383 }
6385 /* Expand a highpart multiply. */
6387 rtx
6390 {
6394 machine_mode wmode;
6400 {
6406 OPTAB_LIB_WIDEN);
6419 }
6439 vec_perm_builder sel;
6441 {
6442 /* The encoding has 2 interleaved stepped patterns. */
6447 }
6448 else
6449 {
6450 /* The encoding has a single interleaved stepped pattern. */
6454 }
6457 }
6458 \f
6459 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6460 pattern. */
6462 static void
6464 {
6467 {
6471 }
6472 }
6474 /* This is a helper function for the other atomic operations. This function
6475 emits a loop that contains SEQ that iterates until a compare-and-swap
6476 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6477 a set of instructions that takes a value from OLD_REG as an input and
6478 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6479 set to the current contents of MEM. After SEQ, a compare-and-swap will
6480 attempt to update MEM with NEW_REG. The function returns true when the
6481 loop was generated successfully. */
6483 static bool
6485 {
6490 /* The loop we want to generate looks like
6492 cmp_reg = mem;
6493 label:
6494 old_reg = cmp_reg;
6495 seq;
6496 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6497 if (success)
6498 goto label;
6500 Note that we only do the plain load from memory once. Subsequent
6501 iterations use the value loaded by the compare-and-swap pattern. */
6516 MEMMODEL_RELAXED))
6522 /* Mark this jump predicted not taken. */
6527 }
6530 /* This function tries to emit an atomic_exchange intruction. VAL is written
6531 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6532 using TARGET if possible. */
6534 static rtx
6536 {
6540 /* If the target supports the exchange directly, great. */
6543 {
6552 }
6555 }
6557 /* This function tries to implement an atomic exchange operation using
6558 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6559 The previous contents of *MEM are returned, using TARGET if possible.
6560 Since this instructionn is an acquire barrier only, stronger memory
6561 models may require additional barriers to be emitted. */
6563 static rtx
6566 {
6573 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6574 exists, and the memory model is stronger than acquire, add a release
6575 barrier before the instruction. */
6581 {
6588 }
6590 /* If an external test-and-set libcall is provided, use that instead of
6591 any external compare-and-swap that we might get from the compare-and-
6592 swap-loop expansion later. */
6594 {
6597 {
6598 rtx addr;
6604 }
6605 }
6607 /* If the test_and_set can't be emitted, eliminate any barrier that might
6608 have been emitted. */
6611 }
6613 /* This function tries to implement an atomic exchange operation using a
6614 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6615 *MEM are returned, using TARGET if possible. No memory model is required
6616 since a compare_and_swap loop is seq-cst. */
6618 static rtx
6620 {
6624 {
6629 }
6632 }
6634 /* This function tries to implement an atomic test-and-set operation
6635 using the atomic_test_and_set instruction pattern. A boolean value
6636 is returned from the operation, using TARGET if possible. */
6638 static rtx
6640 {
6641 machine_mode pat_bool_mode;
6647 /* While we always get QImode from __atomic_test_and_set, we get
6648 other memory modes from __sync_lock_test_and_set. Note that we
6649 use no endian adjustment here. This matches the 4.6 behavior
6650 in the Sparc backend. */
6664 }
6666 /* This function expands the legacy _sync_lock test_and_set operation which is
6667 generally an atomic exchange. Some limited targets only allow the
6668 constant 1 to be stored. This is an ACQUIRE operation.
6670 TARGET is an optional place to stick the return value.
6671 MEM is where VAL is stored. */
6673 rtx
6675 {
6676 rtx ret;
6678 /* Try an atomic_exchange first. */
6684 MEMMODEL_SYNC_ACQUIRE);
6692 /* If there are no other options, try atomic_test_and_set if the value
6693 being stored is 1. */
6698 }
6700 /* This function expands the atomic test_and_set operation:
6701 atomically store a boolean TRUE into MEM and return the previous value.
6703 MEMMODEL is the memory model variant to use.
6704 TARGET is an optional place to stick the return value. */
6706 rtx
6708 {
6716 /* Be binary compatible with non-default settings of trueval, and different
6717 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6718 another only has atomic-exchange. */
6720 {
6723 }
6724 else
6725 {
6728 }
6730 /* Try the atomic-exchange optab... */
6733 /* ... then an atomic-compare-and-swap loop ... */
6737 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6741 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6742 things with the value 1. Thus we try again without trueval. */
6746 /* Failing all else, assume a single threaded environment and simply
6747 perform the operation. */
6749 {
6750 /* If the result is ignored skip the move to target. */
6756 }
6758 /* Recall that have to return a boolean value; rectify if trueval
6759 is not exactly one. */
6764 }
6766 /* This function expands the atomic exchange operation:
6767 atomically store VAL in MEM and return the previous value in MEM.
6769 MEMMODEL is the memory model variant to use.
6770 TARGET is an optional place to stick the return value. */
6772 rtx
6774 {
6776 rtx ret;
6778 /* If loads are not atomic for the required size and we are not called to
6779 provide a __sync builtin, do not do anything so that we stay consistent
6780 with atomic loads of the same size. */
6786 /* Next try a compare-and-swap loop for the exchange. */
6791 }
6793 /* This function expands the atomic compare exchange operation:
6795 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6796 *PTARGET_OVAL is an optional place to store the old value from memory.
6797 Both target parameters may be NULL or const0_rtx to indicate that we do
6798 not care about that return value. Both target parameters are updated on
6799 success to the actual location of the corresponding result.
6801 MEMMODEL is the memory model variant to use.
6803 The return value of the function is true for success. */
6805 bool
6810 {
6815 rtx libfunc;
6817 /* If loads are not atomic for the required size and we are not called to
6818 provide a __sync builtin, do not do anything so that we stay consistent
6819 with atomic loads of the same size. */
6823 /* Load expected into a register for the compare and swap. */
6827 /* Make sure we always have some place to put the return oldval.
6828 Further, make sure that place is distinct from the input expected,
6829 just in case we need that path down below. */
6840 {
6846 /* Make sure we always have a place for the bool operand. */
6852 /* Emit the compare_and_swap. */
6862 {
6863 /* Return success/failure. */
6867 }
6868 }
6870 /* Otherwise fall back to the original __sync_val_compare_and_swap
6871 which is always seq-cst. */
6874 {
6875 rtx cc_reg;
6886 /* If the caller isn't interested in the boolean return value,
6887 skip the computation of it. */
6891 /* Otherwise, work out if the compare-and-swap succeeded. */
6896 {
6900 }
6902 }
6904 /* Also check for library support for __sync_val_compare_and_swap. */
6907 {
6914 /* Compute the boolean return value only if requested. */
6917 else
6919 }
6921 /* Failure. */
6924 success_bool_from_val:
6927 success:
6928 /* Make sure that the oval output winds up where the caller asked. */
6934 }
6936 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
6938 static void
6940 {
6953 }
6955 /* Do not propagate memory accesses across this point. */
6957 static void
6959 {
6962 else
6964 }
6966 /* Generate asm volatile("" : : : "memory") as a memory blockage, at the
6967 same time clobbering the register set specified by REGS. */
6969 void
6971 {
6977 num_of_regs++;
6994 {
6998 {
7000 j++;
7001 }
7003 }
7006 }
7008 /* This routine will either emit the mem_thread_fence pattern or issue a
7009 sync_synchronize to generate a fence for memory model MEMMODEL. */
7011 void
7013 {
7017 {
7020 }
7025 else
7027 }
7029 /* Emit a signal fence with given memory model. */
7031 void
7033 {
7034 /* No machine barrier is required to implement a signal fence, but
7035 a compiler memory barrier must be issued, except for relaxed MM. */
7038 }
7040 /* This function expands the atomic load operation:
7041 return the atomically loaded value in MEM.
7043 MEMMODEL is the memory model variant to use.
7044 TARGET is an option place to stick the return value. */
7046 rtx
7048 {
7052 /* If the target supports the load directly, great. */
7055 {
7065 {
7069 }
7071 }
7073 /* If the size of the object is greater than word size on this target,
7074 then we assume that a load will not be atomic. We could try to
7075 emulate a load with a compare-and-swap operation, but the store that
7076 doing this could result in would be incorrect if this is a volatile
7077 atomic load or targetting read-only-mapped memory. */
7079 /* If there is no atomic load, leave the library call. */
7082 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7086 /* For SEQ_CST, emit a barrier before the load. */
7092 /* Emit the appropriate barrier after the load. */
7096 }
7098 /* This function expands the atomic store operation:
7099 Atomically store VAL in MEM.
7100 MEMMODEL is the memory model variant to use.
7101 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7102 function returns const0_rtx if a pattern was emitted. */
7104 rtx
7106 {
7111 /* If the target supports the store directly, great. */
7114 {
7122 {
7126 }
7128 }
7130 /* If using __sync_lock_release is a viable alternative, try it.
7131 Note that this will not be set to true if we are expanding a generic
7132 __atomic_store_n. */
7134 {
7137 {
7141 {
7142 /* lock_release is only a release barrier. */
7146 }
7147 }
7148 }
7150 /* If the size of the object is greater than word size on this target,
7151 a default store will not be atomic. */
7153 {
7154 /* If loads are atomic or we are called to provide a __sync builtin,
7155 we can try a atomic_exchange and throw away the result. Otherwise,
7156 don't do anything so that we do not create an inconsistency between
7157 loads and stores. */
7159 {
7163 val);
7166 }
7168 }
7170 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7175 /* For SEQ_CST, also emit a barrier after the store. */
7180 }
7183 /* Structure containing the pointers and values required to process the
7184 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7186 struct atomic_op_functions
7187 {
7188 direct_optab mem_fetch_before;
7189 direct_optab mem_fetch_after;
7190 direct_optab mem_no_result;
7191 optab fetch_before;
7192 optab fetch_after;
7193 direct_optab no_result;
7195 };
7198 /* Fill in structure pointed to by OP with the various optab entries for an
7199 operation of type CODE. */
7201 static void
7203 {
7206 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7207 in the source code during compilation, and the optab entries are not
7208 computable until runtime. Fill in the values at runtime. */
7210 {
7267 }
7268 }
7270 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7271 using memory order MODEL. If AFTER is true the operation needs to return
7272 the value of *MEM after the operation, otherwise the previous value.
7273 TARGET is an optional place to place the result. The result is unused if
7274 it is const0_rtx.
7275 Return the result if there is a better sequence, otherwise NULL_RTX. */
7277 static rtx
7280 {
7281 /* If the value is prefetched, or not used, it may be possible to replace
7282 the sequence with a native exchange operation. */
7284 {
7285 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7287 {
7291 }
7293 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7295 {
7299 }
7300 }
7303 }
7305 /* Try to emit an instruction for a specific operation varaition.
7306 OPTAB contains the OP functions.
7307 TARGET is an optional place to return the result. const0_rtx means unused.
7308 MEM is the memory location to operate on.
7309 VAL is the value to use in the operation.
7310 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7311 MODEL is the memory model, if used.
7312 AFTER is true if the returned result is the value after the operation. */
7314 static rtx
7317 {
7324 /* Check to see if there is a result returned. */
7326 {
7328 {
7332 }
7333 else
7334 {
7337 }
7338 }
7339 /* Otherwise, we need to generate a result. */
7340 else
7341 {
7343 {
7348 }
7349 else
7350 {
7354 }
7356 }
7361 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7368 }
7371 /* This function expands an atomic fetch_OP or OP_fetch operation:
7372 TARGET is an option place to stick the return value. const0_rtx indicates
7373 the result is unused.
7374 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7375 CODE is the operation being performed (OP)
7376 MEMMODEL is the memory model variant to use.
7377 AFTER is true to return the result of the operation (OP_fetch).
7378 AFTER is false to return the value before the operation (fetch_OP).
7380 This function will *only* generate instructions if there is a direct
7381 optab. No compare and swap loops or libcalls will be generated. */
7383 static rtx
7387 {
7390 rtx result;
7395 /* Check to see if there are any better instructions. */
7400 /* Check for the case where the result isn't used and try those patterns. */
7402 {
7403 /* Try the memory model variant first. */
7408 /* Next try the old style withuot a memory model. */
7413 /* There is no no-result pattern, so try patterns with a result. */
7415 }
7417 /* Try the __atomic version. */
7422 /* Try the older __sync version. */
7427 /* If the fetch value can be calculated from the other variation of fetch,
7428 try that operation. */
7430 {
7431 /* Try the __atomic version, then the older __sync version. */
7437 {
7438 /* If the result isn't used, no need to do compensation code. */
7442 /* Issue compensation code. Fetch_after == fetch_before OP val.
7443 Fetch_before == after REVERSE_OP val. */
7447 {
7451 }
7452 else
7456 }
7457 }
7459 /* No direct opcode can be generated. */
7461 }
7465 /* This function expands an atomic fetch_OP or OP_fetch operation:
7466 TARGET is an option place to stick the return value. const0_rtx indicates
7467 the result is unused.
7468 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7469 CODE is the operation being performed (OP)
7470 MEMMODEL is the memory model variant to use.
7471 AFTER is true to return the result of the operation (OP_fetch).
7472 AFTER is false to return the value before the operation (fetch_OP). */
7473 rtx
7476 {
7478 rtx result;
7481 /* If loads are not atomic for the required size and we are not called to
7482 provide a __sync builtin, do not do anything so that we stay consistent
7483 with atomic loads of the same size. */
7488 after);
7493 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7495 {
7496 rtx tmp;
7504 {
7505 /* PLUS worked so emit the insns and return. */
7510 }
7512 /* PLUS did not work, so throw away the negation code and continue. */
7514 }
7516 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7518 {
7519 rtx libfunc;
7529 {
7535 }
7537 {
7546 }
7548 /* We need the original code for any further attempts. */
7550 }
7552 /* If nothing else has succeeded, default to a compare and swap loop. */
7554 {
7560 /* If the result is used, get a register for it. */
7562 {
7565 /* If fetch_before, copy the value now. */
7568 }
7569 else
7574 {
7578 }
7579 else
7581 OPTAB_LIB_WIDEN);
7583 /* For after, copy the value now. */
7591 }
7594 }
7595 \f
7596 /* Return true if OPERAND is suitable for operand number OPNO of
7597 instruction ICODE. */
7599 bool
7601 {
7605 }
7606 \f
7607 /* TARGET is a target of a multiword operation that we are going to
7608 implement as a series of word-mode operations. Return true if
7609 TARGET is suitable for this purpose. */
7611 bool
7613 {
7614 machine_mode mode;
7624 }
7626 /* Make OP describe an input operand that has value INTVAL and that has
7627 no inherent mode. This function should only be used for operands that
7628 are always expand-time constants. The backend may request that INTVAL
7629 be copied into a different kind of rtx, but it must specify the mode
7630 of that rtx if so. */
7632 void
7634 {
7638 }
7640 /* Like maybe_legitimize_operand, but do not change the code of the
7641 current rtx value. */
7643 static bool
7646 {
7647 /* See if the operand matches in its current form. */
7651 /* If the operand is a memory whose address has no side effects,
7652 try forcing the address into a non-virtual pseudo register.
7653 The check for side effects is important because copy_to_mode_reg
7654 cannot handle things like auto-modified addresses. */
7656 {
7663 {
7665 machine_mode mode;
7671 {
7674 }
7676 }
7677 }
7680 }
7682 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7683 on success, storing the new operand value back in OP. */
7685 static bool
7688 {
7693 {
7695 {
7698 }
7713 input:
7731 else
7732 /* The caller must tell us what mode this value has. */
7739 {
7742 }
7744 {
7748 }
7761 {
7764 }
7766 }
7768 }
7770 /* Make OP describe an input operand that should have the same value
7771 as VALUE, after any mode conversion that the target might request.
7772 TYPE is the type of VALUE. */
7774 void
7777 {
7780 }
7782 /* Return true if the requirements on operands OP1 and OP2 of instruction
7783 ICODE are similar enough for the result of legitimizing OP1 to be
7784 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7785 with OP1 and OP2 respectively. */
7792 {
7793 /* Check requirements that are common to all types. */
7800 /* Check the requirements for specific types. */
7802 {
7804 /* Outputs must remain distinct. */
7816 }
7818 }
7820 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
7821 of instruction ICODE. Return true on success, leaving the new operand
7822 values in the OPS themselves. Emit no code on failure. */
7824 bool
7827 {
7831 {
7834 /* First try reusing the result of an earlier legitimization.
7835 This avoids duplicate rtl and ensures that tied operands
7836 remain tied.
7838 This search is linear, but NOPS is bounded at compile time
7839 to a small number (current a single digit). */
7846 {
7849 }
7851 /* Otherwise try legitimizing the operand on its own. */
7853 {
7856 }
7857 }
7859 }
7861 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
7862 as its operands. Return the instruction pattern on success,
7863 and emit any necessary set-up code. Return null and emit no
7864 code on failure. */
7866 rtx_insn *
7869 {
7875 {
7903 }
7905 }
7907 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
7908 as its operands. Return true on success and emit no code on failure. */
7910 bool
7913 {
7916 {
7919 }
7921 }
7923 /* Like maybe_expand_insn, but for jumps. */
7925 bool
7928 {
7931 {
7934 }
7936 }
7938 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
7939 as its operands. */
7941 void
7944 {
7947 }
7949 /* Like expand_insn, but for jumps. */
7951 void
7954 {
7957 }