1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 /* Middle-to-low level generation of rtx code and insns.
23 This file contains support functions for creating rtl expressions
24 and manipulating them in the doubly-linked chain of insns.
26 The patterns of the insns are created by machine-dependent
27 routines in insn-emit.c, which is generated automatically from
28 the machine description. These routines make the individual rtx's
29 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
30 which are automatically generated from rtl.def; what is machine
31 dependent is the kind of rtx's they make and what arguments they
36 #include "coretypes.h"
44 #include "stringpool.h"
45 #include "insn-config.h"
49 #include "diagnostic-core.h"
51 #include "fold-const.h"
59 #include "stor-layout.h"
62 #include "rtx-vector-builder.h"
64 #include "gimple-ssa.h"
67 struct target_rtl default_target_rtl
;
69 struct target_rtl
*this_target_rtl
= &default_target_rtl
;
72 #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx)
74 /* Commonly used modes. */
76 scalar_int_mode byte_mode
; /* Mode whose width is BITS_PER_UNIT. */
77 scalar_int_mode word_mode
; /* Mode whose width is BITS_PER_WORD. */
78 scalar_int_mode ptr_mode
; /* Mode whose width is POINTER_SIZE. */
80 /* Datastructures maintained for currently processed function in RTL form. */
82 struct rtl_data x_rtl
;
84 /* Indexed by pseudo register number, gives the rtx for that pseudo.
85 Allocated in parallel with regno_pointer_align.
86 FIXME: We could put it into emit_status struct, but gengtype is not able to deal
87 with length attribute nested in top level structures. */
91 /* This is *not* reset after each function. It gives each CODE_LABEL
92 in the entire compilation a unique label number. */
94 static GTY(()) int label_num
= 1;
96 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
97 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
98 record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX
99 is set only for MODE_INT and MODE_VECTOR_INT modes. */
101 rtx const_tiny_rtx
[4][(int) MAX_MACHINE_MODE
];
105 REAL_VALUE_TYPE dconst0
;
106 REAL_VALUE_TYPE dconst1
;
107 REAL_VALUE_TYPE dconst2
;
108 REAL_VALUE_TYPE dconstm1
;
109 REAL_VALUE_TYPE dconsthalf
;
111 /* Record fixed-point constant 0 and 1. */
112 FIXED_VALUE_TYPE fconst0
[MAX_FCONST0
];
113 FIXED_VALUE_TYPE fconst1
[MAX_FCONST1
];
115 /* We make one copy of (const_int C) where C is in
116 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
117 to save space during the compilation and simplify comparisons of
120 rtx const_int_rtx
[MAX_SAVED_CONST_INT
* 2 + 1];
122 /* Standard pieces of rtx, to be substituted directly into things. */
125 rtx simple_return_rtx
;
127 /* Marker used for denoting an INSN, which should never be accessed (i.e.,
128 this pointer should normally never be dereferenced), but is required to be
129 distinct from NULL_RTX. Currently used by peephole2 pass. */
130 rtx_insn
*invalid_insn_rtx
;
132 /* A hash table storing CONST_INTs whose absolute value is greater
133 than MAX_SAVED_CONST_INT. */
135 struct const_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
137 typedef HOST_WIDE_INT compare_type
;
139 static hashval_t
hash (rtx i
);
140 static bool equal (rtx i
, HOST_WIDE_INT h
);
143 static GTY ((cache
)) hash_table
<const_int_hasher
> *const_int_htab
;
145 struct const_wide_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
147 static hashval_t
hash (rtx x
);
148 static bool equal (rtx x
, rtx y
);
151 static GTY ((cache
)) hash_table
<const_wide_int_hasher
> *const_wide_int_htab
;
153 struct const_poly_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
155 typedef std::pair
<machine_mode
, poly_wide_int_ref
> compare_type
;
157 static hashval_t
hash (rtx x
);
158 static bool equal (rtx x
, const compare_type
&y
);
161 static GTY ((cache
)) hash_table
<const_poly_int_hasher
> *const_poly_int_htab
;
163 /* A hash table storing register attribute structures. */
164 struct reg_attr_hasher
: ggc_cache_ptr_hash
<reg_attrs
>
166 static hashval_t
hash (reg_attrs
*x
);
167 static bool equal (reg_attrs
*a
, reg_attrs
*b
);
170 static GTY ((cache
)) hash_table
<reg_attr_hasher
> *reg_attrs_htab
;
172 /* A hash table storing all CONST_DOUBLEs. */
173 struct const_double_hasher
: ggc_cache_ptr_hash
<rtx_def
>
175 static hashval_t
hash (rtx x
);
176 static bool equal (rtx x
, rtx y
);
179 static GTY ((cache
)) hash_table
<const_double_hasher
> *const_double_htab
;
181 /* A hash table storing all CONST_FIXEDs. */
182 struct const_fixed_hasher
: ggc_cache_ptr_hash
<rtx_def
>
184 static hashval_t
hash (rtx x
);
185 static bool equal (rtx x
, rtx y
);
188 static GTY ((cache
)) hash_table
<const_fixed_hasher
> *const_fixed_htab
;
190 #define cur_insn_uid (crtl->emit.x_cur_insn_uid)
191 #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid)
192 #define first_label_num (crtl->emit.x_first_label_num)
194 static void set_used_decls (tree
);
195 static void mark_label_nuses (rtx
);
196 #if TARGET_SUPPORTS_WIDE_INT
197 static rtx
lookup_const_wide_int (rtx
);
199 static rtx
lookup_const_double (rtx
);
200 static rtx
lookup_const_fixed (rtx
);
201 static rtx
gen_const_vector (machine_mode
, int);
202 static void copy_rtx_if_shared_1 (rtx
*orig
);
204 /* Probability of the conditional branch currently proceeded by try_split. */
205 profile_probability split_branch_probability
;
207 /* Returns a hash code for X (which is a really a CONST_INT). */
210 const_int_hasher::hash (rtx x
)
212 return (hashval_t
) INTVAL (x
);
215 /* Returns nonzero if the value represented by X (which is really a
216 CONST_INT) is the same as that given by Y (which is really a
220 const_int_hasher::equal (rtx x
, HOST_WIDE_INT y
)
222 return (INTVAL (x
) == y
);
225 #if TARGET_SUPPORTS_WIDE_INT
226 /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */
229 const_wide_int_hasher::hash (rtx x
)
232 unsigned HOST_WIDE_INT hash
= 0;
235 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
236 hash
+= CONST_WIDE_INT_ELT (xr
, i
);
238 return (hashval_t
) hash
;
241 /* Returns nonzero if the value represented by X (which is really a
242 CONST_WIDE_INT) is the same as that given by Y (which is really a
246 const_wide_int_hasher::equal (rtx x
, rtx y
)
251 if (CONST_WIDE_INT_NUNITS (xr
) != CONST_WIDE_INT_NUNITS (yr
))
254 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
255 if (CONST_WIDE_INT_ELT (xr
, i
) != CONST_WIDE_INT_ELT (yr
, i
))
262 /* Returns a hash code for CONST_POLY_INT X. */
265 const_poly_int_hasher::hash (rtx x
)
268 h
.add_int (GET_MODE (x
));
269 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
270 h
.add_wide_int (CONST_POLY_INT_COEFFS (x
)[i
]);
274 /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */
277 const_poly_int_hasher::equal (rtx x
, const compare_type
&y
)
279 if (GET_MODE (x
) != y
.first
)
281 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
282 if (CONST_POLY_INT_COEFFS (x
)[i
] != y
.second
.coeffs
[i
])
287 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
289 const_double_hasher::hash (rtx x
)
291 const_rtx
const value
= x
;
294 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (value
) == VOIDmode
)
295 h
= CONST_DOUBLE_LOW (value
) ^ CONST_DOUBLE_HIGH (value
);
298 h
= real_hash (CONST_DOUBLE_REAL_VALUE (value
));
299 /* MODE is used in the comparison, so it should be in the hash. */
300 h
^= GET_MODE (value
);
305 /* Returns nonzero if the value represented by X (really a ...)
306 is the same as that represented by Y (really a ...) */
308 const_double_hasher::equal (rtx x
, rtx y
)
310 const_rtx
const a
= x
, b
= y
;
312 if (GET_MODE (a
) != GET_MODE (b
))
314 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (a
) == VOIDmode
)
315 return (CONST_DOUBLE_LOW (a
) == CONST_DOUBLE_LOW (b
)
316 && CONST_DOUBLE_HIGH (a
) == CONST_DOUBLE_HIGH (b
));
318 return real_identical (CONST_DOUBLE_REAL_VALUE (a
),
319 CONST_DOUBLE_REAL_VALUE (b
));
322 /* Returns a hash code for X (which is really a CONST_FIXED). */
325 const_fixed_hasher::hash (rtx x
)
327 const_rtx
const value
= x
;
330 h
= fixed_hash (CONST_FIXED_VALUE (value
));
331 /* MODE is used in the comparison, so it should be in the hash. */
332 h
^= GET_MODE (value
);
336 /* Returns nonzero if the value represented by X is the same as that
340 const_fixed_hasher::equal (rtx x
, rtx y
)
342 const_rtx
const a
= x
, b
= y
;
344 if (GET_MODE (a
) != GET_MODE (b
))
346 return fixed_identical (CONST_FIXED_VALUE (a
), CONST_FIXED_VALUE (b
));
349 /* Return true if the given memory attributes are equal. */
352 mem_attrs_eq_p (const class mem_attrs
*p
, const class mem_attrs
*q
)
358 return (p
->alias
== q
->alias
359 && p
->offset_known_p
== q
->offset_known_p
360 && (!p
->offset_known_p
|| known_eq (p
->offset
, q
->offset
))
361 && p
->size_known_p
== q
->size_known_p
362 && (!p
->size_known_p
|| known_eq (p
->size
, q
->size
))
363 && p
->align
== q
->align
364 && p
->addrspace
== q
->addrspace
365 && (p
->expr
== q
->expr
366 || (p
->expr
!= NULL_TREE
&& q
->expr
!= NULL_TREE
367 && operand_equal_p (p
->expr
, q
->expr
, 0))));
370 /* Set MEM's memory attributes so that they are the same as ATTRS. */
373 set_mem_attrs (rtx mem
, mem_attrs
*attrs
)
375 /* If everything is the default, we can just clear the attributes. */
376 if (mem_attrs_eq_p (attrs
, mode_mem_attrs
[(int) GET_MODE (mem
)]))
383 || !mem_attrs_eq_p (attrs
, MEM_ATTRS (mem
)))
385 MEM_ATTRS (mem
) = ggc_alloc
<mem_attrs
> ();
386 memcpy (MEM_ATTRS (mem
), attrs
, sizeof (mem_attrs
));
390 /* Returns a hash code for X (which is a really a reg_attrs *). */
393 reg_attr_hasher::hash (reg_attrs
*x
)
395 const reg_attrs
*const p
= x
;
399 h
.add_poly_hwi (p
->offset
);
403 /* Returns nonzero if the value represented by X is the same as that given by
407 reg_attr_hasher::equal (reg_attrs
*x
, reg_attrs
*y
)
409 const reg_attrs
*const p
= x
;
410 const reg_attrs
*const q
= y
;
412 return (p
->decl
== q
->decl
&& known_eq (p
->offset
, q
->offset
));
414 /* Allocate a new reg_attrs structure and insert it into the hash table if
415 one identical to it is not already in the table. We are doing this for
419 get_reg_attrs (tree decl
, poly_int64 offset
)
423 /* If everything is the default, we can just return zero. */
424 if (decl
== 0 && known_eq (offset
, 0))
428 attrs
.offset
= offset
;
430 reg_attrs
**slot
= reg_attrs_htab
->find_slot (&attrs
, INSERT
);
433 *slot
= ggc_alloc
<reg_attrs
> ();
434 memcpy (*slot
, &attrs
, sizeof (reg_attrs
));
442 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
443 and to block register equivalences to be seen across this insn. */
448 rtx x
= gen_rtx_ASM_INPUT (VOIDmode
, "");
449 MEM_VOLATILE_P (x
) = true;
455 /* Set the mode and register number of X to MODE and REGNO. */
458 set_mode_and_regno (rtx x
, machine_mode mode
, unsigned int regno
)
460 unsigned int nregs
= (HARD_REGISTER_NUM_P (regno
)
461 ? hard_regno_nregs (regno
, mode
)
463 PUT_MODE_RAW (x
, mode
);
464 set_regno_raw (x
, regno
, nregs
);
467 /* Initialize a fresh REG rtx with mode MODE and register REGNO. */
470 init_raw_REG (rtx x
, machine_mode mode
, unsigned int regno
)
472 set_mode_and_regno (x
, mode
, regno
);
473 REG_ATTRS (x
) = NULL
;
474 ORIGINAL_REGNO (x
) = regno
;
478 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
479 don't attempt to share with the various global pieces of rtl (such as
480 frame_pointer_rtx). */
483 gen_raw_REG (machine_mode mode
, unsigned int regno
)
485 rtx x
= rtx_alloc (REG MEM_STAT_INFO
);
486 init_raw_REG (x
, mode
, regno
);
490 /* There are some RTL codes that require special attention; the generation
491 functions do the raw handling. If you add to this list, modify
492 special_rtx in gengenrtl.c as well. */
495 gen_rtx_EXPR_LIST (machine_mode mode
, rtx expr
, rtx expr_list
)
497 return as_a
<rtx_expr_list
*> (gen_rtx_fmt_ee (EXPR_LIST
, mode
, expr
,
502 gen_rtx_INSN_LIST (machine_mode mode
, rtx insn
, rtx insn_list
)
504 return as_a
<rtx_insn_list
*> (gen_rtx_fmt_ue (INSN_LIST
, mode
, insn
,
509 gen_rtx_INSN (machine_mode mode
, rtx_insn
*prev_insn
, rtx_insn
*next_insn
,
510 basic_block bb
, rtx pattern
, int location
, int code
,
513 return as_a
<rtx_insn
*> (gen_rtx_fmt_uuBeiie (INSN
, mode
,
514 prev_insn
, next_insn
,
515 bb
, pattern
, location
, code
,
520 gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED
, HOST_WIDE_INT arg
)
522 if (arg
>= - MAX_SAVED_CONST_INT
&& arg
<= MAX_SAVED_CONST_INT
)
523 return const_int_rtx
[arg
+ MAX_SAVED_CONST_INT
];
525 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
526 if (const_true_rtx
&& arg
== STORE_FLAG_VALUE
)
527 return const_true_rtx
;
530 /* Look up the CONST_INT in the hash table. */
531 rtx
*slot
= const_int_htab
->find_slot_with_hash (arg
, (hashval_t
) arg
,
534 *slot
= gen_rtx_raw_CONST_INT (VOIDmode
, arg
);
540 gen_int_mode (poly_int64 c
, machine_mode mode
)
542 c
= trunc_int_for_mode (c
, mode
);
543 if (c
.is_constant ())
544 return GEN_INT (c
.coeffs
[0]);
545 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
546 return immed_wide_int_const (poly_wide_int::from (c
, prec
, SIGNED
), mode
);
549 /* CONST_DOUBLEs might be created from pairs of integers, or from
550 REAL_VALUE_TYPEs. Also, their length is known only at run time,
551 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
553 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
554 hash table. If so, return its counterpart; otherwise add it
555 to the hash table and return it. */
557 lookup_const_double (rtx real
)
559 rtx
*slot
= const_double_htab
->find_slot (real
, INSERT
);
566 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
567 VALUE in mode MODE. */
569 const_double_from_real_value (REAL_VALUE_TYPE value
, machine_mode mode
)
571 rtx real
= rtx_alloc (CONST_DOUBLE
);
572 PUT_MODE (real
, mode
);
576 return lookup_const_double (real
);
579 /* Determine whether FIXED, a CONST_FIXED, already exists in the
580 hash table. If so, return its counterpart; otherwise add it
581 to the hash table and return it. */
584 lookup_const_fixed (rtx fixed
)
586 rtx
*slot
= const_fixed_htab
->find_slot (fixed
, INSERT
);
593 /* Return a CONST_FIXED rtx for a fixed-point value specified by
594 VALUE in mode MODE. */
597 const_fixed_from_fixed_value (FIXED_VALUE_TYPE value
, machine_mode mode
)
599 rtx fixed
= rtx_alloc (CONST_FIXED
);
600 PUT_MODE (fixed
, mode
);
604 return lookup_const_fixed (fixed
);
607 #if TARGET_SUPPORTS_WIDE_INT == 0
608 /* Constructs double_int from rtx CST. */
611 rtx_to_double_int (const_rtx cst
)
615 if (CONST_INT_P (cst
))
616 r
= double_int::from_shwi (INTVAL (cst
));
617 else if (CONST_DOUBLE_AS_INT_P (cst
))
619 r
.low
= CONST_DOUBLE_LOW (cst
);
620 r
.high
= CONST_DOUBLE_HIGH (cst
);
629 #if TARGET_SUPPORTS_WIDE_INT
630 /* Determine whether CONST_WIDE_INT WINT already exists in the hash table.
631 If so, return its counterpart; otherwise add it to the hash table and
635 lookup_const_wide_int (rtx wint
)
637 rtx
*slot
= const_wide_int_htab
->find_slot (wint
, INSERT
);
645 /* Return an rtx constant for V, given that the constant has mode MODE.
646 The returned rtx will be a CONST_INT if V fits, otherwise it will be
647 a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT
648 (if TARGET_SUPPORTS_WIDE_INT). */
651 immed_wide_int_const_1 (const wide_int_ref
&v
, machine_mode mode
)
653 unsigned int len
= v
.get_len ();
654 /* Not scalar_int_mode because we also allow pointer bound modes. */
655 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
657 /* Allow truncation but not extension since we do not know if the
658 number is signed or unsigned. */
659 gcc_assert (prec
<= v
.get_precision ());
661 if (len
< 2 || prec
<= HOST_BITS_PER_WIDE_INT
)
662 return gen_int_mode (v
.elt (0), mode
);
664 #if TARGET_SUPPORTS_WIDE_INT
668 unsigned int blocks_needed
669 = (prec
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
;
671 if (len
> blocks_needed
)
674 value
= const_wide_int_alloc (len
);
676 /* It is so tempting to just put the mode in here. Must control
678 PUT_MODE (value
, VOIDmode
);
679 CWI_PUT_NUM_ELEM (value
, len
);
681 for (i
= 0; i
< len
; i
++)
682 CONST_WIDE_INT_ELT (value
, i
) = v
.elt (i
);
684 return lookup_const_wide_int (value
);
687 return immed_double_const (v
.elt (0), v
.elt (1), mode
);
691 #if TARGET_SUPPORTS_WIDE_INT == 0
692 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
693 of ints: I0 is the low-order word and I1 is the high-order word.
694 For values that are larger than HOST_BITS_PER_DOUBLE_INT, the
695 implied upper bits are copies of the high bit of i1. The value
696 itself is neither signed nor unsigned. Do not use this routine for
697 non-integer modes; convert to REAL_VALUE_TYPE and use
698 const_double_from_real_value. */
701 immed_double_const (HOST_WIDE_INT i0
, HOST_WIDE_INT i1
, machine_mode mode
)
706 /* There are the following cases (note that there are no modes with
707 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT):
709 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
711 2) If the value of the integer fits into HOST_WIDE_INT anyway
712 (i.e., i1 consists only from copies of the sign bit, and sign
713 of i0 and i1 are the same), then we return a CONST_INT for i0.
714 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
716 if (is_a
<scalar_mode
> (mode
, &smode
)
717 && GET_MODE_BITSIZE (smode
) <= HOST_BITS_PER_WIDE_INT
)
718 return gen_int_mode (i0
, mode
);
720 /* If this integer fits in one word, return a CONST_INT. */
721 if ((i1
== 0 && i0
>= 0) || (i1
== ~0 && i0
< 0))
724 /* We use VOIDmode for integers. */
725 value
= rtx_alloc (CONST_DOUBLE
);
726 PUT_MODE (value
, VOIDmode
);
728 CONST_DOUBLE_LOW (value
) = i0
;
729 CONST_DOUBLE_HIGH (value
) = i1
;
731 for (i
= 2; i
< (sizeof CONST_DOUBLE_FORMAT
- 1); i
++)
732 XWINT (value
, i
) = 0;
734 return lookup_const_double (value
);
738 /* Return an rtx representation of C in mode MODE. */
741 immed_wide_int_const (const poly_wide_int_ref
&c
, machine_mode mode
)
743 if (c
.is_constant ())
744 return immed_wide_int_const_1 (c
.coeffs
[0], mode
);
746 /* Not scalar_int_mode because we also allow pointer bound modes. */
747 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
749 /* Allow truncation but not extension since we do not know if the
750 number is signed or unsigned. */
751 gcc_assert (prec
<= c
.coeffs
[0].get_precision ());
752 poly_wide_int newc
= poly_wide_int::from (c
, prec
, SIGNED
);
754 /* See whether we already have an rtx for this constant. */
757 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
758 h
.add_wide_int (newc
.coeffs
[i
]);
759 const_poly_int_hasher::compare_type
typed_value (mode
, newc
);
760 rtx
*slot
= const_poly_int_htab
->find_slot_with_hash (typed_value
,
766 /* Create a new rtx. There's a choice to be made here between installing
767 the actual mode of the rtx or leaving it as VOIDmode (for consistency
768 with CONST_INT). In practice the handling of the codes is different
769 enough that we get no benefit from using VOIDmode, and various places
770 assume that VOIDmode implies CONST_INT. Using the real mode seems like
771 the right long-term direction anyway. */
772 typedef trailing_wide_ints
<NUM_POLY_INT_COEFFS
> twi
;
773 size_t extra_size
= twi::extra_size (prec
);
774 x
= rtx_alloc_v (CONST_POLY_INT
,
775 sizeof (struct const_poly_int_def
) + extra_size
);
777 CONST_POLY_INT_COEFFS (x
).set_precision (prec
);
778 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
779 CONST_POLY_INT_COEFFS (x
)[i
] = newc
.coeffs
[i
];
786 gen_rtx_REG (machine_mode mode
, unsigned int regno
)
788 /* In case the MD file explicitly references the frame pointer, have
789 all such references point to the same frame pointer. This is
790 used during frame pointer elimination to distinguish the explicit
791 references to these registers from pseudos that happened to be
794 If we have eliminated the frame pointer or arg pointer, we will
795 be using it as a normal register, for example as a spill
796 register. In such cases, we might be accessing it in a mode that
797 is not Pmode and therefore cannot use the pre-allocated rtx.
799 Also don't do this when we are making new REGs in reload, since
800 we don't want to get confused with the real pointers. */
802 if (mode
== Pmode
&& !reload_in_progress
&& !lra_in_progress
)
804 if (regno
== FRAME_POINTER_REGNUM
805 && (!reload_completed
|| frame_pointer_needed
))
806 return frame_pointer_rtx
;
808 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
809 && regno
== HARD_FRAME_POINTER_REGNUM
810 && (!reload_completed
|| frame_pointer_needed
))
811 return hard_frame_pointer_rtx
;
812 #if !HARD_FRAME_POINTER_IS_ARG_POINTER
813 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
814 && regno
== ARG_POINTER_REGNUM
)
815 return arg_pointer_rtx
;
817 #ifdef RETURN_ADDRESS_POINTER_REGNUM
818 if (regno
== RETURN_ADDRESS_POINTER_REGNUM
)
819 return return_address_pointer_rtx
;
821 if (regno
== (unsigned) PIC_OFFSET_TABLE_REGNUM
822 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
823 && fixed_regs
[PIC_OFFSET_TABLE_REGNUM
])
824 return pic_offset_table_rtx
;
825 if (regno
== STACK_POINTER_REGNUM
)
826 return stack_pointer_rtx
;
830 /* If the per-function register table has been set up, try to re-use
831 an existing entry in that table to avoid useless generation of RTL.
833 This code is disabled for now until we can fix the various backends
834 which depend on having non-shared hard registers in some cases. Long
835 term we want to re-enable this code as it can significantly cut down
836 on the amount of useless RTL that gets generated.
838 We'll also need to fix some code that runs after reload that wants to
839 set ORIGINAL_REGNO. */
844 && regno
< FIRST_PSEUDO_REGISTER
845 && reg_raw_mode
[regno
] == mode
)
846 return regno_reg_rtx
[regno
];
849 return gen_raw_REG (mode
, regno
);
853 gen_rtx_MEM (machine_mode mode
, rtx addr
)
855 rtx rt
= gen_rtx_raw_MEM (mode
, addr
);
857 /* This field is not cleared by the mere allocation of the rtx, so
864 /* Generate a memory referring to non-trapping constant memory. */
867 gen_const_mem (machine_mode mode
, rtx addr
)
869 rtx mem
= gen_rtx_MEM (mode
, addr
);
870 MEM_READONLY_P (mem
) = 1;
871 MEM_NOTRAP_P (mem
) = 1;
875 /* Generate a MEM referring to fixed portions of the frame, e.g., register
879 gen_frame_mem (machine_mode mode
, rtx addr
)
881 rtx mem
= gen_rtx_MEM (mode
, addr
);
882 MEM_NOTRAP_P (mem
) = 1;
883 set_mem_alias_set (mem
, get_frame_alias_set ());
887 /* Generate a MEM referring to a temporary use of the stack, not part
888 of the fixed stack frame. For example, something which is pushed
889 by a target splitter. */
891 gen_tmp_stack_mem (machine_mode mode
, rtx addr
)
893 rtx mem
= gen_rtx_MEM (mode
, addr
);
894 MEM_NOTRAP_P (mem
) = 1;
895 if (!cfun
->calls_alloca
)
896 set_mem_alias_set (mem
, get_frame_alias_set ());
900 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
901 this construct would be valid, and false otherwise. */
904 validate_subreg (machine_mode omode
, machine_mode imode
,
905 const_rtx reg
, poly_uint64 offset
)
907 poly_uint64 isize
= GET_MODE_SIZE (imode
);
908 poly_uint64 osize
= GET_MODE_SIZE (omode
);
910 /* The sizes must be ordered, so that we know whether the subreg
911 is partial, paradoxical or complete. */
912 if (!ordered_p (isize
, osize
))
915 /* All subregs must be aligned. */
916 if (!multiple_p (offset
, osize
))
919 /* The subreg offset cannot be outside the inner object. */
920 if (maybe_ge (offset
, isize
))
923 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (imode
);
925 /* ??? This should not be here. Temporarily continue to allow word_mode
926 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
927 Generally, backends are doing something sketchy but it'll take time to
929 if (omode
== word_mode
)
931 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
932 is the culprit here, and not the backends. */
933 else if (known_ge (osize
, regsize
) && known_ge (isize
, osize
))
935 /* Allow component subregs of complex and vector. Though given the below
936 extraction rules, it's not always clear what that means. */
937 else if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
938 && GET_MODE_INNER (imode
) == omode
)
940 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
941 i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This
942 surely isn't the cleanest way to represent this. It's questionable
943 if this ought to be represented at all -- why can't this all be hidden
944 in post-reload splitters that make arbitrarily mode changes to the
945 registers themselves. */
946 else if (VECTOR_MODE_P (omode
)
947 && GET_MODE_INNER (omode
) == GET_MODE_INNER (imode
))
949 /* Subregs involving floating point modes are not allowed to
950 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
951 (subreg:SI (reg:DF) 0) isn't. */
952 else if (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))
954 if (! (known_eq (isize
, osize
)
955 /* LRA can use subreg to store a floating point value in
956 an integer mode. Although the floating point and the
957 integer modes need the same number of hard registers,
958 the size of floating point mode can be less than the
959 integer mode. LRA also uses subregs for a register
960 should be used in different mode in on insn. */
965 /* Paradoxical subregs must have offset zero. */
966 if (maybe_gt (osize
, isize
))
967 return known_eq (offset
, 0U);
969 /* This is a normal subreg. Verify that the offset is representable. */
971 /* For hard registers, we already have most of these rules collected in
972 subreg_offset_representable_p. */
973 if (reg
&& REG_P (reg
) && HARD_REGISTER_P (reg
))
975 unsigned int regno
= REGNO (reg
);
977 if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
978 && GET_MODE_INNER (imode
) == omode
)
980 else if (!REG_CAN_CHANGE_MODE_P (regno
, imode
, omode
))
983 return subreg_offset_representable_p (regno
, imode
, offset
, omode
);
986 /* The outer size must be ordered wrt the register size, otherwise
987 we wouldn't know at compile time how many registers the outer
989 if (!ordered_p (osize
, regsize
))
992 /* For pseudo registers, we want most of the same checks. Namely:
994 Assume that the pseudo register will be allocated to hard registers
995 that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE,
996 the remainder must correspond to the lowpart of the containing hard
997 register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset,
998 otherwise it is at the lowest offset.
1000 Given that we've already checked the mode and offset alignment,
1001 we only have to check subblock subregs here. */
1002 if (maybe_lt (osize
, regsize
)
1003 && ! (lra_in_progress
&& (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))))
1005 /* It is invalid for the target to pick a register size for a mode
1006 that isn't ordered wrt to the size of that mode. */
1007 poly_uint64 block_size
= ordered_min (isize
, regsize
);
1008 unsigned int start_reg
;
1009 poly_uint64 offset_within_reg
;
1010 if (!can_div_trunc_p (offset
, block_size
, &start_reg
, &offset_within_reg
)
1011 || (BYTES_BIG_ENDIAN
1012 ? maybe_ne (offset_within_reg
, block_size
- osize
)
1013 : maybe_ne (offset_within_reg
, 0U)))
1020 gen_rtx_SUBREG (machine_mode mode
, rtx reg
, poly_uint64 offset
)
1022 gcc_assert (validate_subreg (mode
, GET_MODE (reg
), reg
, offset
));
1023 return gen_rtx_raw_SUBREG (mode
, reg
, offset
);
1026 /* Generate a SUBREG representing the least-significant part of REG if MODE
1027 is smaller than mode of REG, otherwise paradoxical SUBREG. */
1030 gen_lowpart_SUBREG (machine_mode mode
, rtx reg
)
1032 machine_mode inmode
;
1034 inmode
= GET_MODE (reg
);
1035 if (inmode
== VOIDmode
)
1037 return gen_rtx_SUBREG (mode
, reg
,
1038 subreg_lowpart_offset (mode
, inmode
));
1042 gen_rtx_VAR_LOCATION (machine_mode mode
, tree decl
, rtx loc
,
1043 enum var_init_status status
)
1045 rtx x
= gen_rtx_fmt_te (VAR_LOCATION
, mode
, decl
, loc
);
1046 PAT_VAR_LOCATION_STATUS (x
) = status
;
1051 /* Create an rtvec and stores within it the RTXen passed in the arguments. */
1054 gen_rtvec (int n
, ...)
1062 /* Don't allocate an empty rtvec... */
1069 rt_val
= rtvec_alloc (n
);
1071 for (i
= 0; i
< n
; i
++)
1072 rt_val
->elem
[i
] = va_arg (p
, rtx
);
1079 gen_rtvec_v (int n
, rtx
*argp
)
1084 /* Don't allocate an empty rtvec... */
1088 rt_val
= rtvec_alloc (n
);
1090 for (i
= 0; i
< n
; i
++)
1091 rt_val
->elem
[i
] = *argp
++;
1097 gen_rtvec_v (int n
, rtx_insn
**argp
)
1102 /* Don't allocate an empty rtvec... */
1106 rt_val
= rtvec_alloc (n
);
1108 for (i
= 0; i
< n
; i
++)
1109 rt_val
->elem
[i
] = *argp
++;
1115 /* Return the number of bytes between the start of an OUTER_MODE
1116 in-memory value and the start of an INNER_MODE in-memory value,
1117 given that the former is a lowpart of the latter. It may be a
1118 paradoxical lowpart, in which case the offset will be negative
1119 on big-endian targets. */
1122 byte_lowpart_offset (machine_mode outer_mode
,
1123 machine_mode inner_mode
)
1125 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1126 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1128 return subreg_lowpart_offset (outer_mode
, inner_mode
);
1131 /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET)
1132 from address X. For paradoxical big-endian subregs this is a
1133 negative value, otherwise it's the same as OFFSET. */
1136 subreg_memory_offset (machine_mode outer_mode
, machine_mode inner_mode
,
1139 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1141 gcc_assert (known_eq (offset
, 0U));
1142 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1147 /* As above, but return the offset that existing subreg X would have
1148 if SUBREG_REG (X) were stored in memory. The only significant thing
1149 about the current SUBREG_REG is its mode. */
1152 subreg_memory_offset (const_rtx x
)
1154 return subreg_memory_offset (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
1158 /* Generate a REG rtx for a new pseudo register of mode MODE.
1159 This pseudo is assigned the next sequential register number. */
1162 gen_reg_rtx (machine_mode mode
)
1165 unsigned int align
= GET_MODE_ALIGNMENT (mode
);
1167 gcc_assert (can_create_pseudo_p ());
1169 /* If a virtual register with bigger mode alignment is generated,
1170 increase stack alignment estimation because it might be spilled
1172 if (SUPPORTS_STACK_ALIGNMENT
1173 && crtl
->stack_alignment_estimated
< align
1174 && !crtl
->stack_realign_processed
)
1176 unsigned int min_align
= MINIMUM_ALIGNMENT (NULL
, mode
, align
);
1177 if (crtl
->stack_alignment_estimated
< min_align
)
1178 crtl
->stack_alignment_estimated
= min_align
;
1181 if (generating_concat_p
1182 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1183 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
))
1185 /* For complex modes, don't make a single pseudo.
1186 Instead, make a CONCAT of two pseudos.
1187 This allows noncontiguous allocation of the real and imaginary parts,
1188 which makes much better code. Besides, allocating DCmode
1189 pseudos overstrains reload on some machines like the 386. */
1190 rtx realpart
, imagpart
;
1191 machine_mode partmode
= GET_MODE_INNER (mode
);
1193 realpart
= gen_reg_rtx (partmode
);
1194 imagpart
= gen_reg_rtx (partmode
);
1195 return gen_rtx_CONCAT (mode
, realpart
, imagpart
);
1198 /* Do not call gen_reg_rtx with uninitialized crtl. */
1199 gcc_assert (crtl
->emit
.regno_pointer_align_length
);
1201 crtl
->emit
.ensure_regno_capacity ();
1202 gcc_assert (reg_rtx_no
< crtl
->emit
.regno_pointer_align_length
);
1204 val
= gen_raw_REG (mode
, reg_rtx_no
);
1205 regno_reg_rtx
[reg_rtx_no
++] = val
;
1209 /* Make sure m_regno_pointer_align, and regno_reg_rtx are large
1210 enough to have elements in the range 0 <= idx <= reg_rtx_no. */
1213 emit_status::ensure_regno_capacity ()
1215 int old_size
= regno_pointer_align_length
;
1217 if (reg_rtx_no
< old_size
)
1220 int new_size
= old_size
* 2;
1221 while (reg_rtx_no
>= new_size
)
1224 char *tmp
= XRESIZEVEC (char, regno_pointer_align
, new_size
);
1225 memset (tmp
+ old_size
, 0, new_size
- old_size
);
1226 regno_pointer_align
= (unsigned char *) tmp
;
1228 rtx
*new1
= GGC_RESIZEVEC (rtx
, regno_reg_rtx
, new_size
);
1229 memset (new1
+ old_size
, 0, (new_size
- old_size
) * sizeof (rtx
));
1230 regno_reg_rtx
= new1
;
1232 crtl
->emit
.regno_pointer_align_length
= new_size
;
1235 /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */
1238 reg_is_parm_p (rtx reg
)
1242 gcc_assert (REG_P (reg
));
1243 decl
= REG_EXPR (reg
);
1244 return (decl
&& TREE_CODE (decl
) == PARM_DECL
);
1247 /* Update NEW with the same attributes as REG, but with OFFSET added
1248 to the REG_OFFSET. */
1251 update_reg_offset (rtx new_rtx
, rtx reg
, poly_int64 offset
)
1253 REG_ATTRS (new_rtx
) = get_reg_attrs (REG_EXPR (reg
),
1254 REG_OFFSET (reg
) + offset
);
1257 /* Generate a register with same attributes as REG, but with OFFSET
1258 added to the REG_OFFSET. */
1261 gen_rtx_REG_offset (rtx reg
, machine_mode mode
, unsigned int regno
,
1264 rtx new_rtx
= gen_rtx_REG (mode
, regno
);
1266 update_reg_offset (new_rtx
, reg
, offset
);
1270 /* Generate a new pseudo-register with the same attributes as REG, but
1271 with OFFSET added to the REG_OFFSET. */
1274 gen_reg_rtx_offset (rtx reg
, machine_mode mode
, int offset
)
1276 rtx new_rtx
= gen_reg_rtx (mode
);
1278 update_reg_offset (new_rtx
, reg
, offset
);
1282 /* Adjust REG in-place so that it has mode MODE. It is assumed that the
1283 new register is a (possibly paradoxical) lowpart of the old one. */
1286 adjust_reg_mode (rtx reg
, machine_mode mode
)
1288 update_reg_offset (reg
, reg
, byte_lowpart_offset (mode
, GET_MODE (reg
)));
1289 PUT_MODE (reg
, mode
);
1292 /* Copy REG's attributes from X, if X has any attributes. If REG and X
1293 have different modes, REG is a (possibly paradoxical) lowpart of X. */
1296 set_reg_attrs_from_value (rtx reg
, rtx x
)
1299 bool can_be_reg_pointer
= true;
1301 /* Don't call mark_reg_pointer for incompatible pointer sign
1303 while (GET_CODE (x
) == SIGN_EXTEND
1304 || GET_CODE (x
) == ZERO_EXTEND
1305 || GET_CODE (x
) == TRUNCATE
1306 || (GET_CODE (x
) == SUBREG
&& subreg_lowpart_p (x
)))
1308 #if defined(POINTERS_EXTEND_UNSIGNED)
1309 if (((GET_CODE (x
) == SIGN_EXTEND
&& POINTERS_EXTEND_UNSIGNED
)
1310 || (GET_CODE (x
) == ZERO_EXTEND
&& ! POINTERS_EXTEND_UNSIGNED
)
1311 || (paradoxical_subreg_p (x
)
1312 && ! (SUBREG_PROMOTED_VAR_P (x
)
1313 && SUBREG_CHECK_PROMOTED_SIGN (x
,
1314 POINTERS_EXTEND_UNSIGNED
))))
1315 && !targetm
.have_ptr_extend ())
1316 can_be_reg_pointer
= false;
1321 /* Hard registers can be reused for multiple purposes within the same
1322 function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN
1323 on them is wrong. */
1324 if (HARD_REGISTER_P (reg
))
1327 offset
= byte_lowpart_offset (GET_MODE (reg
), GET_MODE (x
));
1330 if (MEM_OFFSET_KNOWN_P (x
))
1331 REG_ATTRS (reg
) = get_reg_attrs (MEM_EXPR (x
),
1332 MEM_OFFSET (x
) + offset
);
1333 if (can_be_reg_pointer
&& MEM_POINTER (x
))
1334 mark_reg_pointer (reg
, 0);
1339 update_reg_offset (reg
, x
, offset
);
1340 if (can_be_reg_pointer
&& REG_POINTER (x
))
1341 mark_reg_pointer (reg
, REGNO_POINTER_ALIGN (REGNO (x
)));
1345 /* Generate a REG rtx for a new pseudo register, copying the mode
1346 and attributes from X. */
1349 gen_reg_rtx_and_attrs (rtx x
)
1351 rtx reg
= gen_reg_rtx (GET_MODE (x
));
1352 set_reg_attrs_from_value (reg
, x
);
1356 /* Set the register attributes for registers contained in PARM_RTX.
1357 Use needed values from memory attributes of MEM. */
1360 set_reg_attrs_for_parm (rtx parm_rtx
, rtx mem
)
1362 if (REG_P (parm_rtx
))
1363 set_reg_attrs_from_value (parm_rtx
, mem
);
1364 else if (GET_CODE (parm_rtx
) == PARALLEL
)
1366 /* Check for a NULL entry in the first slot, used to indicate that the
1367 parameter goes both on the stack and in registers. */
1368 int i
= XEXP (XVECEXP (parm_rtx
, 0, 0), 0) ? 0 : 1;
1369 for (; i
< XVECLEN (parm_rtx
, 0); i
++)
1371 rtx x
= XVECEXP (parm_rtx
, 0, i
);
1372 if (REG_P (XEXP (x
, 0)))
1373 REG_ATTRS (XEXP (x
, 0))
1374 = get_reg_attrs (MEM_EXPR (mem
),
1375 INTVAL (XEXP (x
, 1)));
1380 /* Set the REG_ATTRS for registers in value X, given that X represents
1384 set_reg_attrs_for_decl_rtl (tree t
, rtx x
)
1389 if (GET_CODE (x
) == SUBREG
)
1391 gcc_assert (subreg_lowpart_p (x
));
1396 = get_reg_attrs (t
, byte_lowpart_offset (GET_MODE (x
),
1399 : TYPE_MODE (TREE_TYPE (tdecl
))));
1400 if (GET_CODE (x
) == CONCAT
)
1402 if (REG_P (XEXP (x
, 0)))
1403 REG_ATTRS (XEXP (x
, 0)) = get_reg_attrs (t
, 0);
1404 if (REG_P (XEXP (x
, 1)))
1405 REG_ATTRS (XEXP (x
, 1))
1406 = get_reg_attrs (t
, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x
, 0))));
1408 if (GET_CODE (x
) == PARALLEL
)
1412 /* Check for a NULL entry, used to indicate that the parameter goes
1413 both on the stack and in registers. */
1414 if (XEXP (XVECEXP (x
, 0, 0), 0))
1419 for (i
= start
; i
< XVECLEN (x
, 0); i
++)
1421 rtx y
= XVECEXP (x
, 0, i
);
1422 if (REG_P (XEXP (y
, 0)))
1423 REG_ATTRS (XEXP (y
, 0)) = get_reg_attrs (t
, INTVAL (XEXP (y
, 1)));
1428 /* Assign the RTX X to declaration T. */
1431 set_decl_rtl (tree t
, rtx x
)
1433 DECL_WRTL_CHECK (t
)->decl_with_rtl
.rtl
= x
;
1435 set_reg_attrs_for_decl_rtl (t
, x
);
1438 /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true
1439 if the ABI requires the parameter to be passed by reference. */
1442 set_decl_incoming_rtl (tree t
, rtx x
, bool by_reference_p
)
1444 DECL_INCOMING_RTL (t
) = x
;
1445 if (x
&& !by_reference_p
)
1446 set_reg_attrs_for_decl_rtl (t
, x
);
1449 /* Identify REG (which may be a CONCAT) as a user register. */
1452 mark_user_reg (rtx reg
)
1454 if (GET_CODE (reg
) == CONCAT
)
1456 REG_USERVAR_P (XEXP (reg
, 0)) = 1;
1457 REG_USERVAR_P (XEXP (reg
, 1)) = 1;
1461 gcc_assert (REG_P (reg
));
1462 REG_USERVAR_P (reg
) = 1;
1466 /* Identify REG as a probable pointer register and show its alignment
1467 as ALIGN, if nonzero. */
1470 mark_reg_pointer (rtx reg
, int align
)
1472 if (! REG_POINTER (reg
))
1474 REG_POINTER (reg
) = 1;
1477 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1479 else if (align
&& align
< REGNO_POINTER_ALIGN (REGNO (reg
)))
1480 /* We can no-longer be sure just how aligned this pointer is. */
1481 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1484 /* Return 1 plus largest pseudo reg number used in the current function. */
1492 /* Return 1 + the largest label number used so far in the current function. */
1495 max_label_num (void)
1500 /* Return first label number used in this function (if any were used). */
1503 get_first_label_num (void)
1505 return first_label_num
;
1508 /* If the rtx for label was created during the expansion of a nested
1509 function, then first_label_num won't include this label number.
1510 Fix this now so that array indices work later. */
1513 maybe_set_first_label_num (rtx_code_label
*x
)
1515 if (CODE_LABEL_NUMBER (x
) < first_label_num
)
1516 first_label_num
= CODE_LABEL_NUMBER (x
);
1519 /* For use by the RTL function loader, when mingling with normal
1521 Ensure that label_num is greater than the label num of X, to avoid
1522 duplicate labels in the generated assembler. */
1525 maybe_set_max_label_num (rtx_code_label
*x
)
1527 if (CODE_LABEL_NUMBER (x
) >= label_num
)
1528 label_num
= CODE_LABEL_NUMBER (x
) + 1;
1532 /* Return a value representing some low-order bits of X, where the number
1533 of low-order bits is given by MODE. Note that no conversion is done
1534 between floating-point and fixed-point values, rather, the bit
1535 representation is returned.
1537 This function handles the cases in common between gen_lowpart, below,
1538 and two variants in cse.c and combine.c. These are the cases that can
1539 be safely handled at all points in the compilation.
1541 If this is not a case we can handle, return 0. */
1544 gen_lowpart_common (machine_mode mode
, rtx x
)
1546 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1547 machine_mode innermode
;
1549 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1550 so we have to make one up. Yuk. */
1551 innermode
= GET_MODE (x
);
1553 && known_le (msize
* BITS_PER_UNIT
,
1554 (unsigned HOST_WIDE_INT
) HOST_BITS_PER_WIDE_INT
))
1555 innermode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1556 else if (innermode
== VOIDmode
)
1557 innermode
= int_mode_for_size (HOST_BITS_PER_DOUBLE_INT
, 0).require ();
1559 gcc_assert (innermode
!= VOIDmode
&& innermode
!= BLKmode
);
1561 if (innermode
== mode
)
1564 /* The size of the outer and inner modes must be ordered. */
1565 poly_uint64 xsize
= GET_MODE_SIZE (innermode
);
1566 if (!ordered_p (msize
, xsize
))
1569 if (SCALAR_FLOAT_MODE_P (mode
))
1571 /* Don't allow paradoxical FLOAT_MODE subregs. */
1572 if (maybe_gt (msize
, xsize
))
1577 /* MODE must occupy no more of the underlying registers than X. */
1578 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (innermode
);
1579 unsigned int mregs
, xregs
;
1580 if (!can_div_away_from_zero_p (msize
, regsize
, &mregs
)
1581 || !can_div_away_from_zero_p (xsize
, regsize
, &xregs
)
1586 scalar_int_mode int_mode
, int_innermode
, from_mode
;
1587 if ((GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
1588 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1589 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
1590 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &from_mode
))
1592 /* If we are getting the low-order part of something that has been
1593 sign- or zero-extended, we can either just use the object being
1594 extended or make a narrower extension. If we want an even smaller
1595 piece than the size of the object being extended, call ourselves
1598 This case is used mostly by combine and cse. */
1600 if (from_mode
== int_mode
)
1602 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (from_mode
))
1603 return gen_lowpart_common (int_mode
, XEXP (x
, 0));
1604 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (int_innermode
))
1605 return gen_rtx_fmt_e (GET_CODE (x
), int_mode
, XEXP (x
, 0));
1607 else if (GET_CODE (x
) == SUBREG
|| REG_P (x
)
1608 || GET_CODE (x
) == CONCAT
|| GET_CODE (x
) == CONST_VECTOR
1609 || CONST_DOUBLE_AS_FLOAT_P (x
) || CONST_SCALAR_INT_P (x
)
1610 || CONST_POLY_INT_P (x
))
1611 return lowpart_subreg (mode
, x
, innermode
);
1613 /* Otherwise, we can't do this. */
1618 gen_highpart (machine_mode mode
, rtx x
)
1620 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1623 /* This case loses if X is a subreg. To catch bugs early,
1624 complain if an invalid MODE is used even in other cases. */
1625 gcc_assert (known_le (msize
, (unsigned int) UNITS_PER_WORD
)
1626 || known_eq (msize
, GET_MODE_UNIT_SIZE (GET_MODE (x
))));
1628 result
= simplify_gen_subreg (mode
, x
, GET_MODE (x
),
1629 subreg_highpart_offset (mode
, GET_MODE (x
)));
1630 gcc_assert (result
);
1632 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1633 the target if we have a MEM. gen_highpart must return a valid operand,
1634 emitting code if necessary to do so. */
1637 result
= validize_mem (result
);
1638 gcc_assert (result
);
1644 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1645 be VOIDmode constant. */
1647 gen_highpart_mode (machine_mode outermode
, machine_mode innermode
, rtx exp
)
1649 if (GET_MODE (exp
) != VOIDmode
)
1651 gcc_assert (GET_MODE (exp
) == innermode
);
1652 return gen_highpart (outermode
, exp
);
1654 return simplify_gen_subreg (outermode
, exp
, innermode
,
1655 subreg_highpart_offset (outermode
, innermode
));
1658 /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has
1659 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1662 subreg_size_lowpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1664 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
1665 if (maybe_gt (outer_bytes
, inner_bytes
))
1666 /* Paradoxical subregs always have a SUBREG_BYTE of 0. */
1669 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1670 return inner_bytes
- outer_bytes
;
1671 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1674 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
, 0);
1677 /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has
1678 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1681 subreg_size_highpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1683 gcc_assert (known_ge (inner_bytes
, outer_bytes
));
1685 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1687 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1688 return inner_bytes
- outer_bytes
;
1690 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
,
1691 (inner_bytes
- outer_bytes
)
1695 /* Return 1 iff X, assumed to be a SUBREG,
1696 refers to the least significant part of its containing reg.
1697 If X is not a SUBREG, always return 1 (it is its own low part!). */
1700 subreg_lowpart_p (const_rtx x
)
1702 if (GET_CODE (x
) != SUBREG
)
1704 else if (GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
1707 return known_eq (subreg_lowpart_offset (GET_MODE (x
),
1708 GET_MODE (SUBREG_REG (x
))),
1712 /* Return subword OFFSET of operand OP.
1713 The word number, OFFSET, is interpreted as the word number starting
1714 at the low-order address. OFFSET 0 is the low-order word if not
1715 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1717 If we cannot extract the required word, we return zero. Otherwise,
1718 an rtx corresponding to the requested word will be returned.
1720 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1721 reload has completed, a valid address will always be returned. After
1722 reload, if a valid address cannot be returned, we return zero.
1724 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1725 it is the responsibility of the caller.
1727 MODE is the mode of OP in case it is a CONST_INT.
1729 ??? This is still rather broken for some cases. The problem for the
1730 moment is that all callers of this thing provide no 'goal mode' to
1731 tell us to work with. This exists because all callers were written
1732 in a word based SUBREG world.
1733 Now use of this function can be deprecated by simplify_subreg in most
1738 operand_subword (rtx op
, poly_uint64 offset
, int validate_address
,
1741 if (mode
== VOIDmode
)
1742 mode
= GET_MODE (op
);
1744 gcc_assert (mode
!= VOIDmode
);
1746 /* If OP is narrower than a word, fail. */
1748 && maybe_lt (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
1751 /* If we want a word outside OP, return zero. */
1753 && maybe_gt ((offset
+ 1) * UNITS_PER_WORD
, GET_MODE_SIZE (mode
)))
1756 /* Form a new MEM at the requested address. */
1759 rtx new_rtx
= adjust_address_nv (op
, word_mode
, offset
* UNITS_PER_WORD
);
1761 if (! validate_address
)
1764 else if (reload_completed
)
1766 if (! strict_memory_address_addr_space_p (word_mode
,
1768 MEM_ADDR_SPACE (op
)))
1772 return replace_equiv_address (new_rtx
, XEXP (new_rtx
, 0));
1775 /* Rest can be handled by simplify_subreg. */
1776 return simplify_gen_subreg (word_mode
, op
, mode
, (offset
* UNITS_PER_WORD
));
1779 /* Similar to `operand_subword', but never return 0. If we can't
1780 extract the required subword, put OP into a register and try again.
1781 The second attempt must succeed. We always validate the address in
1784 MODE is the mode of OP, in case it is CONST_INT. */
1787 operand_subword_force (rtx op
, poly_uint64 offset
, machine_mode mode
)
1789 rtx result
= operand_subword (op
, offset
, 1, mode
);
1794 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
1796 /* If this is a register which cannot be accessed by words, copy it
1797 to a pseudo register. */
1799 op
= copy_to_reg (op
);
1801 op
= force_reg (mode
, op
);
1804 result
= operand_subword (op
, offset
, 1, mode
);
1805 gcc_assert (result
);
1810 mem_attrs::mem_attrs ()
1816 addrspace (ADDR_SPACE_GENERIC
),
1817 offset_known_p (false),
1818 size_known_p (false)
1821 /* Returns 1 if both MEM_EXPR can be considered equal
1825 mem_expr_equal_p (const_tree expr1
, const_tree expr2
)
1830 if (! expr1
|| ! expr2
)
1833 if (TREE_CODE (expr1
) != TREE_CODE (expr2
))
1836 return operand_equal_p (expr1
, expr2
, 0);
1839 /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN
1840 bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or
1844 get_mem_align_offset (rtx mem
, unsigned int align
)
1849 /* This function can't use
1850 if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem)
1851 || (MAX (MEM_ALIGN (mem),
1852 MAX (align, get_object_alignment (MEM_EXPR (mem))))
1856 return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1);
1858 - COMPONENT_REFs in MEM_EXPR can have NULL first operand,
1859 for <variable>. get_inner_reference doesn't handle it and
1860 even if it did, the alignment in that case needs to be determined
1861 from DECL_FIELD_CONTEXT's TYPE_ALIGN.
1862 - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR
1863 isn't sufficiently aligned, the object it is in might be. */
1864 gcc_assert (MEM_P (mem
));
1865 expr
= MEM_EXPR (mem
);
1866 if (expr
== NULL_TREE
|| !MEM_OFFSET_KNOWN_P (mem
))
1869 offset
= MEM_OFFSET (mem
);
1872 if (DECL_ALIGN (expr
) < align
)
1875 else if (INDIRECT_REF_P (expr
))
1877 if (TYPE_ALIGN (TREE_TYPE (expr
)) < (unsigned int) align
)
1880 else if (TREE_CODE (expr
) == COMPONENT_REF
)
1884 tree inner
= TREE_OPERAND (expr
, 0);
1885 tree field
= TREE_OPERAND (expr
, 1);
1886 tree byte_offset
= component_ref_field_offset (expr
);
1887 tree bit_offset
= DECL_FIELD_BIT_OFFSET (field
);
1889 poly_uint64 suboffset
;
1891 || !poly_int_tree_p (byte_offset
, &suboffset
)
1892 || !tree_fits_uhwi_p (bit_offset
))
1895 offset
+= suboffset
;
1896 offset
+= tree_to_uhwi (bit_offset
) / BITS_PER_UNIT
;
1898 if (inner
== NULL_TREE
)
1900 if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field
))
1901 < (unsigned int) align
)
1905 else if (DECL_P (inner
))
1907 if (DECL_ALIGN (inner
) < align
)
1911 else if (TREE_CODE (inner
) != COMPONENT_REF
)
1919 HOST_WIDE_INT misalign
;
1920 if (!known_misalignment (offset
, align
/ BITS_PER_UNIT
, &misalign
))
1925 /* Given REF (a MEM) and T, either the type of X or the expression
1926 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1927 if we are making a new object of this type. BITPOS is nonzero if
1928 there is an offset outstanding on T that will be applied later. */
1931 set_mem_attributes_minus_bitpos (rtx ref
, tree t
, int objectp
,
1934 poly_int64 apply_bitpos
= 0;
1936 class mem_attrs attrs
, *defattrs
, *refattrs
;
1939 /* It can happen that type_for_mode was given a mode for which there
1940 is no language-level type. In which case it returns NULL, which
1945 type
= TYPE_P (t
) ? t
: TREE_TYPE (t
);
1946 if (type
== error_mark_node
)
1949 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1950 wrong answer, as it assumes that DECL_RTL already has the right alias
1951 info. Callers should not set DECL_RTL until after the call to
1952 set_mem_attributes. */
1953 gcc_assert (!DECL_P (t
) || ref
!= DECL_RTL_IF_SET (t
));
1955 /* Get the alias set from the expression or type (perhaps using a
1956 front-end routine) and use it. */
1957 attrs
.alias
= get_alias_set (t
);
1959 MEM_VOLATILE_P (ref
) |= TYPE_VOLATILE (type
);
1960 MEM_POINTER (ref
) = POINTER_TYPE_P (type
);
1962 /* Default values from pre-existing memory attributes if present. */
1963 refattrs
= MEM_ATTRS (ref
);
1966 /* ??? Can this ever happen? Calling this routine on a MEM that
1967 already carries memory attributes should probably be invalid. */
1968 attrs
.expr
= refattrs
->expr
;
1969 attrs
.offset_known_p
= refattrs
->offset_known_p
;
1970 attrs
.offset
= refattrs
->offset
;
1971 attrs
.size_known_p
= refattrs
->size_known_p
;
1972 attrs
.size
= refattrs
->size
;
1973 attrs
.align
= refattrs
->align
;
1976 /* Otherwise, default values from the mode of the MEM reference. */
1979 defattrs
= mode_mem_attrs
[(int) GET_MODE (ref
)];
1980 gcc_assert (!defattrs
->expr
);
1981 gcc_assert (!defattrs
->offset_known_p
);
1983 /* Respect mode size. */
1984 attrs
.size_known_p
= defattrs
->size_known_p
;
1985 attrs
.size
= defattrs
->size
;
1986 /* ??? Is this really necessary? We probably should always get
1987 the size from the type below. */
1989 /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type;
1990 if T is an object, always compute the object alignment below. */
1992 attrs
.align
= defattrs
->align
;
1994 attrs
.align
= BITS_PER_UNIT
;
1995 /* ??? If T is a type, respecting mode alignment may *also* be wrong
1996 e.g. if the type carries an alignment attribute. Should we be
1997 able to simply always use TYPE_ALIGN? */
2000 /* We can set the alignment from the type if we are making an object or if
2001 this is an INDIRECT_REF. */
2002 if (objectp
|| TREE_CODE (t
) == INDIRECT_REF
)
2003 attrs
.align
= MAX (attrs
.align
, TYPE_ALIGN (type
));
2005 /* If the size is known, we can set that. */
2006 tree new_size
= TYPE_SIZE_UNIT (type
);
2008 /* The address-space is that of the type. */
2009 as
= TYPE_ADDR_SPACE (type
);
2011 /* If T is not a type, we may be able to deduce some more information about
2017 if (TREE_THIS_VOLATILE (t
))
2018 MEM_VOLATILE_P (ref
) = 1;
2020 /* Now remove any conversions: they don't change what the underlying
2021 object is. Likewise for SAVE_EXPR. */
2022 while (CONVERT_EXPR_P (t
)
2023 || TREE_CODE (t
) == VIEW_CONVERT_EXPR
2024 || TREE_CODE (t
) == SAVE_EXPR
)
2025 t
= TREE_OPERAND (t
, 0);
2027 /* Note whether this expression can trap. */
2028 MEM_NOTRAP_P (ref
) = !tree_could_trap_p (t
);
2030 base
= get_base_address (t
);
2034 && TREE_READONLY (base
)
2035 && (TREE_STATIC (base
) || DECL_EXTERNAL (base
))
2036 && !TREE_THIS_VOLATILE (base
))
2037 MEM_READONLY_P (ref
) = 1;
2039 /* Mark static const strings readonly as well. */
2040 if (TREE_CODE (base
) == STRING_CST
2041 && TREE_READONLY (base
)
2042 && TREE_STATIC (base
))
2043 MEM_READONLY_P (ref
) = 1;
2045 /* Address-space information is on the base object. */
2046 if (TREE_CODE (base
) == MEM_REF
2047 || TREE_CODE (base
) == TARGET_MEM_REF
)
2048 as
= TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base
,
2051 as
= TYPE_ADDR_SPACE (TREE_TYPE (base
));
2054 /* If this expression uses it's parent's alias set, mark it such
2055 that we won't change it. */
2056 if (component_uses_parent_alias_set_from (t
) != NULL_TREE
)
2057 MEM_KEEP_ALIAS_SET_P (ref
) = 1;
2059 /* If this is a decl, set the attributes of the MEM from it. */
2063 attrs
.offset_known_p
= true;
2065 apply_bitpos
= bitpos
;
2066 new_size
= DECL_SIZE_UNIT (t
);
2069 /* ??? If we end up with a constant or a descriptor do not
2070 record a MEM_EXPR. */
2071 else if (CONSTANT_CLASS_P (t
)
2072 || TREE_CODE (t
) == CONSTRUCTOR
)
2075 /* If this is a field reference, record it. */
2076 else if (TREE_CODE (t
) == COMPONENT_REF
)
2079 attrs
.offset_known_p
= true;
2081 apply_bitpos
= bitpos
;
2082 if (DECL_BIT_FIELD (TREE_OPERAND (t
, 1)))
2083 new_size
= DECL_SIZE_UNIT (TREE_OPERAND (t
, 1));
2086 /* Else record it. */
2089 gcc_assert (handled_component_p (t
)
2090 || TREE_CODE (t
) == MEM_REF
2091 || TREE_CODE (t
) == TARGET_MEM_REF
);
2093 attrs
.offset_known_p
= true;
2095 apply_bitpos
= bitpos
;
2098 /* If this is a reference based on a partitioned decl replace the
2099 base with a MEM_REF of the pointer representative we created
2100 during stack slot partitioning. */
2103 && ! is_global_var (base
)
2104 && cfun
->gimple_df
->decls_to_pointers
!= NULL
)
2106 tree
*namep
= cfun
->gimple_df
->decls_to_pointers
->get (base
);
2109 attrs
.expr
= unshare_expr (attrs
.expr
);
2110 tree
*orig_base
= &attrs
.expr
;
2111 while (handled_component_p (*orig_base
))
2112 orig_base
= &TREE_OPERAND (*orig_base
, 0);
2113 tree aptrt
= reference_alias_ptr_type (*orig_base
);
2114 *orig_base
= build2 (MEM_REF
, TREE_TYPE (*orig_base
), *namep
,
2115 build_int_cst (aptrt
, 0));
2119 /* Compute the alignment. */
2120 unsigned int obj_align
;
2121 unsigned HOST_WIDE_INT obj_bitpos
;
2122 get_object_alignment_1 (t
, &obj_align
, &obj_bitpos
);
2123 unsigned int diff_align
= known_alignment (obj_bitpos
- bitpos
);
2124 if (diff_align
!= 0)
2125 obj_align
= MIN (obj_align
, diff_align
);
2126 attrs
.align
= MAX (attrs
.align
, obj_align
);
2129 poly_uint64 const_size
;
2130 if (poly_int_tree_p (new_size
, &const_size
))
2132 attrs
.size_known_p
= true;
2133 attrs
.size
= const_size
;
2136 /* If we modified OFFSET based on T, then subtract the outstanding
2137 bit position offset. Similarly, increase the size of the accessed
2138 object to contain the negative offset. */
2139 if (maybe_ne (apply_bitpos
, 0))
2141 gcc_assert (attrs
.offset_known_p
);
2142 poly_int64 bytepos
= bits_to_bytes_round_down (apply_bitpos
);
2143 attrs
.offset
-= bytepos
;
2144 if (attrs
.size_known_p
)
2145 attrs
.size
+= bytepos
;
2148 /* Now set the attributes we computed above. */
2149 attrs
.addrspace
= as
;
2150 set_mem_attrs (ref
, &attrs
);
2154 set_mem_attributes (rtx ref
, tree t
, int objectp
)
2156 set_mem_attributes_minus_bitpos (ref
, t
, objectp
, 0);
2159 /* Set the alias set of MEM to SET. */
2162 set_mem_alias_set (rtx mem
, alias_set_type set
)
2164 /* If the new and old alias sets don't conflict, something is wrong. */
2165 gcc_checking_assert (alias_sets_conflict_p (set
, MEM_ALIAS_SET (mem
)));
2166 mem_attrs
attrs (*get_mem_attrs (mem
));
2168 set_mem_attrs (mem
, &attrs
);
2171 /* Set the address space of MEM to ADDRSPACE (target-defined). */
2174 set_mem_addr_space (rtx mem
, addr_space_t addrspace
)
2176 mem_attrs
attrs (*get_mem_attrs (mem
));
2177 attrs
.addrspace
= addrspace
;
2178 set_mem_attrs (mem
, &attrs
);
2181 /* Set the alignment of MEM to ALIGN bits. */
2184 set_mem_align (rtx mem
, unsigned int align
)
2186 mem_attrs
attrs (*get_mem_attrs (mem
));
2187 attrs
.align
= align
;
2188 set_mem_attrs (mem
, &attrs
);
2191 /* Set the expr for MEM to EXPR. */
2194 set_mem_expr (rtx mem
, tree expr
)
2196 mem_attrs
attrs (*get_mem_attrs (mem
));
2198 set_mem_attrs (mem
, &attrs
);
2201 /* Set the offset of MEM to OFFSET. */
2204 set_mem_offset (rtx mem
, poly_int64 offset
)
2206 mem_attrs
attrs (*get_mem_attrs (mem
));
2207 attrs
.offset_known_p
= true;
2208 attrs
.offset
= offset
;
2209 set_mem_attrs (mem
, &attrs
);
2212 /* Clear the offset of MEM. */
2215 clear_mem_offset (rtx mem
)
2217 mem_attrs
attrs (*get_mem_attrs (mem
));
2218 attrs
.offset_known_p
= false;
2219 set_mem_attrs (mem
, &attrs
);
2222 /* Set the size of MEM to SIZE. */
2225 set_mem_size (rtx mem
, poly_int64 size
)
2227 mem_attrs
attrs (*get_mem_attrs (mem
));
2228 attrs
.size_known_p
= true;
2230 set_mem_attrs (mem
, &attrs
);
2233 /* Clear the size of MEM. */
2236 clear_mem_size (rtx mem
)
2238 mem_attrs
attrs (*get_mem_attrs (mem
));
2239 attrs
.size_known_p
= false;
2240 set_mem_attrs (mem
, &attrs
);
2243 /* Return a memory reference like MEMREF, but with its mode changed to MODE
2244 and its address changed to ADDR. (VOIDmode means don't change the mode.
2245 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
2246 returned memory location is required to be valid. INPLACE is true if any
2247 changes can be made directly to MEMREF or false if MEMREF must be treated
2250 The memory attributes are not changed. */
2253 change_address_1 (rtx memref
, machine_mode mode
, rtx addr
, int validate
,
2259 gcc_assert (MEM_P (memref
));
2260 as
= MEM_ADDR_SPACE (memref
);
2261 if (mode
== VOIDmode
)
2262 mode
= GET_MODE (memref
);
2264 addr
= XEXP (memref
, 0);
2265 if (mode
== GET_MODE (memref
) && addr
== XEXP (memref
, 0)
2266 && (!validate
|| memory_address_addr_space_p (mode
, addr
, as
)))
2269 /* Don't validate address for LRA. LRA can make the address valid
2270 by itself in most efficient way. */
2271 if (validate
&& !lra_in_progress
)
2273 if (reload_in_progress
|| reload_completed
)
2274 gcc_assert (memory_address_addr_space_p (mode
, addr
, as
));
2276 addr
= memory_address_addr_space (mode
, addr
, as
);
2279 if (rtx_equal_p (addr
, XEXP (memref
, 0)) && mode
== GET_MODE (memref
))
2284 XEXP (memref
, 0) = addr
;
2288 new_rtx
= gen_rtx_MEM (mode
, addr
);
2289 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2293 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
2294 way we are changing MEMREF, so we only preserve the alias set. */
2297 change_address (rtx memref
, machine_mode mode
, rtx addr
)
2299 rtx new_rtx
= change_address_1 (memref
, mode
, addr
, 1, false);
2300 machine_mode mmode
= GET_MODE (new_rtx
);
2301 class mem_attrs
*defattrs
;
2303 mem_attrs
attrs (*get_mem_attrs (memref
));
2304 defattrs
= mode_mem_attrs
[(int) mmode
];
2305 attrs
.expr
= NULL_TREE
;
2306 attrs
.offset_known_p
= false;
2307 attrs
.size_known_p
= defattrs
->size_known_p
;
2308 attrs
.size
= defattrs
->size
;
2309 attrs
.align
= defattrs
->align
;
2311 /* If there are no changes, just return the original memory reference. */
2312 if (new_rtx
== memref
)
2314 if (mem_attrs_eq_p (get_mem_attrs (memref
), &attrs
))
2317 new_rtx
= gen_rtx_MEM (mmode
, XEXP (memref
, 0));
2318 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2321 set_mem_attrs (new_rtx
, &attrs
);
2325 /* Return a memory reference like MEMREF, but with its mode changed
2326 to MODE and its address offset by OFFSET bytes. If VALIDATE is
2327 nonzero, the memory address is forced to be valid.
2328 If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS
2329 and the caller is responsible for adjusting MEMREF base register.
2330 If ADJUST_OBJECT is zero, the underlying object associated with the
2331 memory reference is left unchanged and the caller is responsible for
2332 dealing with it. Otherwise, if the new memory reference is outside
2333 the underlying object, even partially, then the object is dropped.
2334 SIZE, if nonzero, is the size of an access in cases where MODE
2335 has no inherent size. */
2338 adjust_address_1 (rtx memref
, machine_mode mode
, poly_int64 offset
,
2339 int validate
, int adjust_address
, int adjust_object
,
2342 rtx addr
= XEXP (memref
, 0);
2344 scalar_int_mode address_mode
;
2345 class mem_attrs
attrs (*get_mem_attrs (memref
)), *defattrs
;
2346 unsigned HOST_WIDE_INT max_align
;
2347 #ifdef POINTERS_EXTEND_UNSIGNED
2348 scalar_int_mode pointer_mode
2349 = targetm
.addr_space
.pointer_mode (attrs
.addrspace
);
2352 /* VOIDmode means no mode change for change_address_1. */
2353 if (mode
== VOIDmode
)
2354 mode
= GET_MODE (memref
);
2356 /* Take the size of non-BLKmode accesses from the mode. */
2357 defattrs
= mode_mem_attrs
[(int) mode
];
2358 if (defattrs
->size_known_p
)
2359 size
= defattrs
->size
;
2361 /* If there are no changes, just return the original memory reference. */
2362 if (mode
== GET_MODE (memref
)
2363 && known_eq (offset
, 0)
2364 && (known_eq (size
, 0)
2365 || (attrs
.size_known_p
&& known_eq (attrs
.size
, size
)))
2366 && (!validate
|| memory_address_addr_space_p (mode
, addr
,
2370 /* ??? Prefer to create garbage instead of creating shared rtl.
2371 This may happen even if offset is nonzero -- consider
2372 (plus (plus reg reg) const_int) -- so do this always. */
2373 addr
= copy_rtx (addr
);
2375 /* Convert a possibly large offset to a signed value within the
2376 range of the target address space. */
2377 address_mode
= get_address_mode (memref
);
2378 offset
= trunc_int_for_mode (offset
, address_mode
);
2382 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
2383 object, we can merge it into the LO_SUM. */
2384 if (GET_MODE (memref
) != BLKmode
2385 && GET_CODE (addr
) == LO_SUM
2386 && known_in_range_p (offset
,
2387 0, (GET_MODE_ALIGNMENT (GET_MODE (memref
))
2389 addr
= gen_rtx_LO_SUM (address_mode
, XEXP (addr
, 0),
2390 plus_constant (address_mode
,
2391 XEXP (addr
, 1), offset
));
2392 #ifdef POINTERS_EXTEND_UNSIGNED
2393 /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid
2394 in that mode, we merge it into the ZERO_EXTEND. We take advantage of
2395 the fact that pointers are not allowed to overflow. */
2396 else if (POINTERS_EXTEND_UNSIGNED
> 0
2397 && GET_CODE (addr
) == ZERO_EXTEND
2398 && GET_MODE (XEXP (addr
, 0)) == pointer_mode
2399 && known_eq (trunc_int_for_mode (offset
, pointer_mode
), offset
))
2400 addr
= gen_rtx_ZERO_EXTEND (address_mode
,
2401 plus_constant (pointer_mode
,
2402 XEXP (addr
, 0), offset
));
2405 addr
= plus_constant (address_mode
, addr
, offset
);
2408 new_rtx
= change_address_1 (memref
, mode
, addr
, validate
, false);
2410 /* If the address is a REG, change_address_1 rightfully returns memref,
2411 but this would destroy memref's MEM_ATTRS. */
2412 if (new_rtx
== memref
&& maybe_ne (offset
, 0))
2413 new_rtx
= copy_rtx (new_rtx
);
2415 /* Conservatively drop the object if we don't know where we start from. */
2416 if (adjust_object
&& (!attrs
.offset_known_p
|| !attrs
.size_known_p
))
2418 attrs
.expr
= NULL_TREE
;
2422 /* Compute the new values of the memory attributes due to this adjustment.
2423 We add the offsets and update the alignment. */
2424 if (attrs
.offset_known_p
)
2426 attrs
.offset
+= offset
;
2428 /* Drop the object if the new left end is not within its bounds. */
2429 if (adjust_object
&& maybe_lt (attrs
.offset
, 0))
2431 attrs
.expr
= NULL_TREE
;
2436 /* Compute the new alignment by taking the MIN of the alignment and the
2437 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
2439 if (maybe_ne (offset
, 0))
2441 max_align
= known_alignment (offset
) * BITS_PER_UNIT
;
2442 attrs
.align
= MIN (attrs
.align
, max_align
);
2445 if (maybe_ne (size
, 0))
2447 /* Drop the object if the new right end is not within its bounds. */
2448 if (adjust_object
&& maybe_gt (offset
+ size
, attrs
.size
))
2450 attrs
.expr
= NULL_TREE
;
2453 attrs
.size_known_p
= true;
2456 else if (attrs
.size_known_p
)
2458 gcc_assert (!adjust_object
);
2459 attrs
.size
-= offset
;
2460 /* ??? The store_by_pieces machinery generates negative sizes,
2461 so don't assert for that here. */
2464 set_mem_attrs (new_rtx
, &attrs
);
2469 /* Return a memory reference like MEMREF, but with its mode changed
2470 to MODE and its address changed to ADDR, which is assumed to be
2471 MEMREF offset by OFFSET bytes. If VALIDATE is
2472 nonzero, the memory address is forced to be valid. */
2475 adjust_automodify_address_1 (rtx memref
, machine_mode mode
, rtx addr
,
2476 poly_int64 offset
, int validate
)
2478 memref
= change_address_1 (memref
, VOIDmode
, addr
, validate
, false);
2479 return adjust_address_1 (memref
, mode
, offset
, validate
, 0, 0, 0);
2482 /* Return a memory reference like MEMREF, but whose address is changed by
2483 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
2484 known to be in OFFSET (possibly 1). */
2487 offset_address (rtx memref
, rtx offset
, unsigned HOST_WIDE_INT pow2
)
2489 rtx new_rtx
, addr
= XEXP (memref
, 0);
2490 machine_mode address_mode
;
2491 class mem_attrs
*defattrs
;
2493 mem_attrs
attrs (*get_mem_attrs (memref
));
2494 address_mode
= get_address_mode (memref
);
2495 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2497 /* At this point we don't know _why_ the address is invalid. It
2498 could have secondary memory references, multiplies or anything.
2500 However, if we did go and rearrange things, we can wind up not
2501 being able to recognize the magic around pic_offset_table_rtx.
2502 This stuff is fragile, and is yet another example of why it is
2503 bad to expose PIC machinery too early. */
2504 if (! memory_address_addr_space_p (GET_MODE (memref
), new_rtx
,
2506 && GET_CODE (addr
) == PLUS
2507 && XEXP (addr
, 0) == pic_offset_table_rtx
)
2509 addr
= force_reg (GET_MODE (addr
), addr
);
2510 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2513 update_temp_slot_address (XEXP (memref
, 0), new_rtx
);
2514 new_rtx
= change_address_1 (memref
, VOIDmode
, new_rtx
, 1, false);
2516 /* If there are no changes, just return the original memory reference. */
2517 if (new_rtx
== memref
)
2520 /* Update the alignment to reflect the offset. Reset the offset, which
2522 defattrs
= mode_mem_attrs
[(int) GET_MODE (new_rtx
)];
2523 attrs
.offset_known_p
= false;
2524 attrs
.size_known_p
= defattrs
->size_known_p
;
2525 attrs
.size
= defattrs
->size
;
2526 attrs
.align
= MIN (attrs
.align
, pow2
* BITS_PER_UNIT
);
2527 set_mem_attrs (new_rtx
, &attrs
);
2531 /* Return a memory reference like MEMREF, but with its address changed to
2532 ADDR. The caller is asserting that the actual piece of memory pointed
2533 to is the same, just the form of the address is being changed, such as
2534 by putting something into a register. INPLACE is true if any changes
2535 can be made directly to MEMREF or false if MEMREF must be treated as
2539 replace_equiv_address (rtx memref
, rtx addr
, bool inplace
)
2541 /* change_address_1 copies the memory attribute structure without change
2542 and that's exactly what we want here. */
2543 update_temp_slot_address (XEXP (memref
, 0), addr
);
2544 return change_address_1 (memref
, VOIDmode
, addr
, 1, inplace
);
2547 /* Likewise, but the reference is not required to be valid. */
2550 replace_equiv_address_nv (rtx memref
, rtx addr
, bool inplace
)
2552 return change_address_1 (memref
, VOIDmode
, addr
, 0, inplace
);
2555 /* Return a memory reference like MEMREF, but with its mode widened to
2556 MODE and offset by OFFSET. This would be used by targets that e.g.
2557 cannot issue QImode memory operations and have to use SImode memory
2558 operations plus masking logic. */
2561 widen_memory_access (rtx memref
, machine_mode mode
, poly_int64 offset
)
2563 rtx new_rtx
= adjust_address_1 (memref
, mode
, offset
, 1, 1, 0, 0);
2564 poly_uint64 size
= GET_MODE_SIZE (mode
);
2566 /* If there are no changes, just return the original memory reference. */
2567 if (new_rtx
== memref
)
2570 mem_attrs
attrs (*get_mem_attrs (new_rtx
));
2572 /* If we don't know what offset we were at within the expression, then
2573 we can't know if we've overstepped the bounds. */
2574 if (! attrs
.offset_known_p
)
2575 attrs
.expr
= NULL_TREE
;
2579 if (TREE_CODE (attrs
.expr
) == COMPONENT_REF
)
2581 tree field
= TREE_OPERAND (attrs
.expr
, 1);
2582 tree offset
= component_ref_field_offset (attrs
.expr
);
2584 if (! DECL_SIZE_UNIT (field
))
2586 attrs
.expr
= NULL_TREE
;
2590 /* Is the field at least as large as the access? If so, ok,
2591 otherwise strip back to the containing structure. */
2592 if (poly_int_tree_p (DECL_SIZE_UNIT (field
))
2593 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field
)), size
)
2594 && known_ge (attrs
.offset
, 0))
2597 poly_uint64 suboffset
;
2598 if (!poly_int_tree_p (offset
, &suboffset
))
2600 attrs
.expr
= NULL_TREE
;
2604 attrs
.expr
= TREE_OPERAND (attrs
.expr
, 0);
2605 attrs
.offset
+= suboffset
;
2606 attrs
.offset
+= (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field
))
2609 /* Similarly for the decl. */
2610 else if (DECL_P (attrs
.expr
)
2611 && DECL_SIZE_UNIT (attrs
.expr
)
2612 && poly_int_tree_p (DECL_SIZE_UNIT (attrs
.expr
))
2613 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs
.expr
)),
2615 && known_ge (attrs
.offset
, 0))
2619 /* The widened memory access overflows the expression, which means
2620 that it could alias another expression. Zap it. */
2621 attrs
.expr
= NULL_TREE
;
2627 attrs
.offset_known_p
= false;
2629 /* The widened memory may alias other stuff, so zap the alias set. */
2630 /* ??? Maybe use get_alias_set on any remaining expression. */
2632 attrs
.size_known_p
= true;
2634 set_mem_attrs (new_rtx
, &attrs
);
2638 /* A fake decl that is used as the MEM_EXPR of spill slots. */
2639 static GTY(()) tree spill_slot_decl
;
2642 get_spill_slot_decl (bool force_build_p
)
2644 tree d
= spill_slot_decl
;
2647 if (d
|| !force_build_p
)
2650 d
= build_decl (DECL_SOURCE_LOCATION (current_function_decl
),
2651 VAR_DECL
, get_identifier ("%sfp"), void_type_node
);
2652 DECL_ARTIFICIAL (d
) = 1;
2653 DECL_IGNORED_P (d
) = 1;
2655 spill_slot_decl
= d
;
2657 rd
= gen_rtx_MEM (BLKmode
, frame_pointer_rtx
);
2658 MEM_NOTRAP_P (rd
) = 1;
2659 mem_attrs
attrs (*mode_mem_attrs
[(int) BLKmode
]);
2660 attrs
.alias
= new_alias_set ();
2662 set_mem_attrs (rd
, &attrs
);
2663 SET_DECL_RTL (d
, rd
);
2668 /* Given MEM, a result from assign_stack_local, fill in the memory
2669 attributes as appropriate for a register allocator spill slot.
2670 These slots are not aliasable by other memory. We arrange for
2671 them all to use a single MEM_EXPR, so that the aliasing code can
2672 work properly in the case of shared spill slots. */
2675 set_mem_attrs_for_spill (rtx mem
)
2679 mem_attrs
attrs (*get_mem_attrs (mem
));
2680 attrs
.expr
= get_spill_slot_decl (true);
2681 attrs
.alias
= MEM_ALIAS_SET (DECL_RTL (attrs
.expr
));
2682 attrs
.addrspace
= ADDR_SPACE_GENERIC
;
2684 /* We expect the incoming memory to be of the form:
2685 (mem:MODE (plus (reg sfp) (const_int offset)))
2686 with perhaps the plus missing for offset = 0. */
2687 addr
= XEXP (mem
, 0);
2688 attrs
.offset_known_p
= true;
2689 strip_offset (addr
, &attrs
.offset
);
2691 set_mem_attrs (mem
, &attrs
);
2692 MEM_NOTRAP_P (mem
) = 1;
2695 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2698 gen_label_rtx (void)
2700 return as_a
<rtx_code_label
*> (
2701 gen_rtx_CODE_LABEL (VOIDmode
, NULL_RTX
, NULL_RTX
,
2702 NULL
, label_num
++, NULL
));
2705 /* For procedure integration. */
2707 /* Install new pointers to the first and last insns in the chain.
2708 Also, set cur_insn_uid to one higher than the last in use.
2709 Used for an inline-procedure after copying the insn chain. */
2712 set_new_first_and_last_insn (rtx_insn
*first
, rtx_insn
*last
)
2716 set_first_insn (first
);
2717 set_last_insn (last
);
2720 if (param_min_nondebug_insn_uid
|| MAY_HAVE_DEBUG_INSNS
)
2722 int debug_count
= 0;
2724 cur_insn_uid
= param_min_nondebug_insn_uid
- 1;
2725 cur_debug_insn_uid
= 0;
2727 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2728 if (INSN_UID (insn
) < param_min_nondebug_insn_uid
)
2729 cur_debug_insn_uid
= MAX (cur_debug_insn_uid
, INSN_UID (insn
));
2732 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2733 if (DEBUG_INSN_P (insn
))
2738 cur_debug_insn_uid
= param_min_nondebug_insn_uid
+ debug_count
;
2740 cur_debug_insn_uid
++;
2743 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2744 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2749 /* Go through all the RTL insn bodies and copy any invalid shared
2750 structure. This routine should only be called once. */
2753 unshare_all_rtl_1 (rtx_insn
*insn
)
2755 /* Unshare just about everything else. */
2756 unshare_all_rtl_in_chain (insn
);
2758 /* Make sure the addresses of stack slots found outside the insn chain
2759 (such as, in DECL_RTL of a variable) are not shared
2760 with the insn chain.
2762 This special care is necessary when the stack slot MEM does not
2763 actually appear in the insn chain. If it does appear, its address
2764 is unshared from all else at that point. */
2767 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2768 (*stack_slot_list
)[i
] = copy_rtx_if_shared (temp
);
2771 /* Go through all the RTL insn bodies and copy any invalid shared
2772 structure, again. This is a fairly expensive thing to do so it
2773 should be done sparingly. */
2776 unshare_all_rtl_again (rtx_insn
*insn
)
2781 for (p
= insn
; p
; p
= NEXT_INSN (p
))
2784 reset_used_flags (PATTERN (p
));
2785 reset_used_flags (REG_NOTES (p
));
2787 reset_used_flags (CALL_INSN_FUNCTION_USAGE (p
));
2790 /* Make sure that virtual stack slots are not shared. */
2791 set_used_decls (DECL_INITIAL (cfun
->decl
));
2793 /* Make sure that virtual parameters are not shared. */
2794 for (decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2795 set_used_flags (DECL_RTL (decl
));
2799 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2800 reset_used_flags (temp
);
2802 unshare_all_rtl_1 (insn
);
2806 unshare_all_rtl (void)
2808 unshare_all_rtl_1 (get_insns ());
2810 for (tree decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2812 if (DECL_RTL_SET_P (decl
))
2813 SET_DECL_RTL (decl
, copy_rtx_if_shared (DECL_RTL (decl
)));
2814 DECL_INCOMING_RTL (decl
) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl
));
2821 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2822 Recursively does the same for subexpressions. */
2825 verify_rtx_sharing (rtx orig
, rtx insn
)
2830 const char *format_ptr
;
2835 code
= GET_CODE (x
);
2837 /* These types may be freely shared. */
2852 /* SCRATCH must be shared because they represent distinct values. */
2855 /* Share clobbers of hard registers, but do not share pseudo reg
2856 clobbers or clobbers of hard registers that originated as pseudos.
2857 This is needed to allow safe register renaming. */
2858 if (REG_P (XEXP (x
, 0))
2859 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
2860 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
2865 if (shared_const_p (orig
))
2870 /* A MEM is allowed to be shared if its address is constant. */
2871 if (CONSTANT_ADDRESS_P (XEXP (x
, 0))
2872 || reload_completed
|| reload_in_progress
)
2881 /* This rtx may not be shared. If it has already been seen,
2882 replace it with a copy of itself. */
2883 if (flag_checking
&& RTX_FLAG (x
, used
))
2885 error ("invalid rtl sharing found in the insn");
2887 error ("shared rtx");
2889 internal_error ("internal consistency failure");
2891 gcc_assert (!RTX_FLAG (x
, used
));
2893 RTX_FLAG (x
, used
) = 1;
2895 /* Now scan the subexpressions recursively. */
2897 format_ptr
= GET_RTX_FORMAT (code
);
2899 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
2901 switch (*format_ptr
++)
2904 verify_rtx_sharing (XEXP (x
, i
), insn
);
2908 if (XVEC (x
, i
) != NULL
)
2911 int len
= XVECLEN (x
, i
);
2913 for (j
= 0; j
< len
; j
++)
2915 /* We allow sharing of ASM_OPERANDS inside single
2917 if (j
&& GET_CODE (XVECEXP (x
, i
, j
)) == SET
2918 && (GET_CODE (SET_SRC (XVECEXP (x
, i
, j
)))
2920 verify_rtx_sharing (SET_DEST (XVECEXP (x
, i
, j
)), insn
);
2922 verify_rtx_sharing (XVECEXP (x
, i
, j
), insn
);
2931 /* Reset used-flags for INSN. */
2934 reset_insn_used_flags (rtx insn
)
2936 gcc_assert (INSN_P (insn
));
2937 reset_used_flags (PATTERN (insn
));
2938 reset_used_flags (REG_NOTES (insn
));
2940 reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn
));
2943 /* Go through all the RTL insn bodies and clear all the USED bits. */
2946 reset_all_used_flags (void)
2950 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
2953 rtx pat
= PATTERN (p
);
2954 if (GET_CODE (pat
) != SEQUENCE
)
2955 reset_insn_used_flags (p
);
2958 gcc_assert (REG_NOTES (p
) == NULL
);
2959 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
2961 rtx insn
= XVECEXP (pat
, 0, i
);
2963 reset_insn_used_flags (insn
);
2969 /* Verify sharing in INSN. */
2972 verify_insn_sharing (rtx insn
)
2974 gcc_assert (INSN_P (insn
));
2975 verify_rtx_sharing (PATTERN (insn
), insn
);
2976 verify_rtx_sharing (REG_NOTES (insn
), insn
);
2978 verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn
), insn
);
2981 /* Go through all the RTL insn bodies and check that there is no unexpected
2982 sharing in between the subexpressions. */
2985 verify_rtl_sharing (void)
2989 timevar_push (TV_VERIFY_RTL_SHARING
);
2991 reset_all_used_flags ();
2993 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
2996 rtx pat
= PATTERN (p
);
2997 if (GET_CODE (pat
) != SEQUENCE
)
2998 verify_insn_sharing (p
);
3000 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
3002 rtx insn
= XVECEXP (pat
, 0, i
);
3004 verify_insn_sharing (insn
);
3008 reset_all_used_flags ();
3010 timevar_pop (TV_VERIFY_RTL_SHARING
);
3013 /* Go through all the RTL insn bodies and copy any invalid shared structure.
3014 Assumes the mark bits are cleared at entry. */
3017 unshare_all_rtl_in_chain (rtx_insn
*insn
)
3019 for (; insn
; insn
= NEXT_INSN (insn
))
3022 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
3023 REG_NOTES (insn
) = copy_rtx_if_shared (REG_NOTES (insn
));
3025 CALL_INSN_FUNCTION_USAGE (insn
)
3026 = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn
));
3030 /* Go through all virtual stack slots of a function and mark them as
3031 shared. We never replace the DECL_RTLs themselves with a copy,
3032 but expressions mentioned into a DECL_RTL cannot be shared with
3033 expressions in the instruction stream.
3035 Note that reload may convert pseudo registers into memories in-place.
3036 Pseudo registers are always shared, but MEMs never are. Thus if we
3037 reset the used flags on MEMs in the instruction stream, we must set
3038 them again on MEMs that appear in DECL_RTLs. */
3041 set_used_decls (tree blk
)
3046 for (t
= BLOCK_VARS (blk
); t
; t
= DECL_CHAIN (t
))
3047 if (DECL_RTL_SET_P (t
))
3048 set_used_flags (DECL_RTL (t
));
3050 /* Now process sub-blocks. */
3051 for (t
= BLOCK_SUBBLOCKS (blk
); t
; t
= BLOCK_CHAIN (t
))
3055 /* Mark ORIG as in use, and return a copy of it if it was already in use.
3056 Recursively does the same for subexpressions. Uses
3057 copy_rtx_if_shared_1 to reduce stack space. */
3060 copy_rtx_if_shared (rtx orig
)
3062 copy_rtx_if_shared_1 (&orig
);
3066 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
3067 use. Recursively does the same for subexpressions. */
3070 copy_rtx_if_shared_1 (rtx
*orig1
)
3076 const char *format_ptr
;
3080 /* Repeat is used to turn tail-recursion into iteration. */
3087 code
= GET_CODE (x
);
3089 /* These types may be freely shared. */
3104 /* SCRATCH must be shared because they represent distinct values. */
3107 /* Share clobbers of hard registers, but do not share pseudo reg
3108 clobbers or clobbers of hard registers that originated as pseudos.
3109 This is needed to allow safe register renaming. */
3110 if (REG_P (XEXP (x
, 0))
3111 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
3112 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
3117 if (shared_const_p (x
))
3127 /* The chain of insns is not being copied. */
3134 /* This rtx may not be shared. If it has already been seen,
3135 replace it with a copy of itself. */
3137 if (RTX_FLAG (x
, used
))
3139 x
= shallow_copy_rtx (x
);
3142 RTX_FLAG (x
, used
) = 1;
3144 /* Now scan the subexpressions recursively.
3145 We can store any replaced subexpressions directly into X
3146 since we know X is not shared! Any vectors in X
3147 must be copied if X was copied. */
3149 format_ptr
= GET_RTX_FORMAT (code
);
3150 length
= GET_RTX_LENGTH (code
);
3153 for (i
= 0; i
< length
; i
++)
3155 switch (*format_ptr
++)
3159 copy_rtx_if_shared_1 (last_ptr
);
3160 last_ptr
= &XEXP (x
, i
);
3164 if (XVEC (x
, i
) != NULL
)
3167 int len
= XVECLEN (x
, i
);
3169 /* Copy the vector iff I copied the rtx and the length
3171 if (copied
&& len
> 0)
3172 XVEC (x
, i
) = gen_rtvec_v (len
, XVEC (x
, i
)->elem
);
3174 /* Call recursively on all inside the vector. */
3175 for (j
= 0; j
< len
; j
++)
3178 copy_rtx_if_shared_1 (last_ptr
);
3179 last_ptr
= &XVECEXP (x
, i
, j
);
3194 /* Set the USED bit in X and its non-shareable subparts to FLAG. */
3197 mark_used_flags (rtx x
, int flag
)
3201 const char *format_ptr
;
3204 /* Repeat is used to turn tail-recursion into iteration. */
3209 code
= GET_CODE (x
);
3211 /* These types may be freely shared so we needn't do any resetting
3234 /* The chain of insns is not being copied. */
3241 RTX_FLAG (x
, used
) = flag
;
3243 format_ptr
= GET_RTX_FORMAT (code
);
3244 length
= GET_RTX_LENGTH (code
);
3246 for (i
= 0; i
< length
; i
++)
3248 switch (*format_ptr
++)
3256 mark_used_flags (XEXP (x
, i
), flag
);
3260 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3261 mark_used_flags (XVECEXP (x
, i
, j
), flag
);
3267 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
3268 to look for shared sub-parts. */
3271 reset_used_flags (rtx x
)
3273 mark_used_flags (x
, 0);
3276 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
3277 to look for shared sub-parts. */
3280 set_used_flags (rtx x
)
3282 mark_used_flags (x
, 1);
3285 /* Copy X if necessary so that it won't be altered by changes in OTHER.
3286 Return X or the rtx for the pseudo reg the value of X was copied into.
3287 OTHER must be valid as a SET_DEST. */
3290 make_safe_from (rtx x
, rtx other
)
3293 switch (GET_CODE (other
))
3296 other
= SUBREG_REG (other
);
3298 case STRICT_LOW_PART
:
3301 other
= XEXP (other
, 0);
3310 && GET_CODE (x
) != SUBREG
)
3312 && (REGNO (other
) < FIRST_PSEUDO_REGISTER
3313 || reg_mentioned_p (other
, x
))))
3315 rtx temp
= gen_reg_rtx (GET_MODE (x
));
3316 emit_move_insn (temp
, x
);
3322 /* Emission of insns (adding them to the doubly-linked list). */
3324 /* Return the last insn emitted, even if it is in a sequence now pushed. */
3327 get_last_insn_anywhere (void)
3329 struct sequence_stack
*seq
;
3330 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
3336 /* Return the first nonnote insn emitted in current sequence or current
3337 function. This routine looks inside SEQUENCEs. */
3340 get_first_nonnote_insn (void)
3342 rtx_insn
*insn
= get_insns ();
3347 for (insn
= next_insn (insn
);
3348 insn
&& NOTE_P (insn
);
3349 insn
= next_insn (insn
))
3353 if (NONJUMP_INSN_P (insn
)
3354 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3355 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3362 /* Return the last nonnote insn emitted in current sequence or current
3363 function. This routine looks inside SEQUENCEs. */
3366 get_last_nonnote_insn (void)
3368 rtx_insn
*insn
= get_last_insn ();
3373 for (insn
= previous_insn (insn
);
3374 insn
&& NOTE_P (insn
);
3375 insn
= previous_insn (insn
))
3379 if (NONJUMP_INSN_P (insn
))
3380 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3381 insn
= seq
->insn (seq
->len () - 1);
3388 /* Return the number of actual (non-debug) insns emitted in this
3392 get_max_insn_count (void)
3394 int n
= cur_insn_uid
;
3396 /* The table size must be stable across -g, to avoid codegen
3397 differences due to debug insns, and not be affected by
3398 -fmin-insn-uid, to avoid excessive table size and to simplify
3399 debugging of -fcompare-debug failures. */
3400 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
3401 n
-= cur_debug_insn_uid
;
3403 n
-= param_min_nondebug_insn_uid
;
3409 /* Return the next insn. If it is a SEQUENCE, return the first insn
3413 next_insn (rtx_insn
*insn
)
3417 insn
= NEXT_INSN (insn
);
3418 if (insn
&& NONJUMP_INSN_P (insn
)
3419 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3420 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3426 /* Return the previous insn. If it is a SEQUENCE, return the last insn
3430 previous_insn (rtx_insn
*insn
)
3434 insn
= PREV_INSN (insn
);
3435 if (insn
&& NONJUMP_INSN_P (insn
))
3436 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3437 insn
= seq
->insn (seq
->len () - 1);
3443 /* Return the next insn after INSN that is not a NOTE. This routine does not
3444 look inside SEQUENCEs. */
3447 next_nonnote_insn (rtx_insn
*insn
)
3451 insn
= NEXT_INSN (insn
);
3452 if (insn
== 0 || !NOTE_P (insn
))
3459 /* Return the next insn after INSN that is not a DEBUG_INSN. This
3460 routine does not look inside SEQUENCEs. */
3463 next_nondebug_insn (rtx_insn
*insn
)
3467 insn
= NEXT_INSN (insn
);
3468 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3475 /* Return the previous insn before INSN that is not a NOTE. This routine does
3476 not look inside SEQUENCEs. */
3479 prev_nonnote_insn (rtx_insn
*insn
)
3483 insn
= PREV_INSN (insn
);
3484 if (insn
== 0 || !NOTE_P (insn
))
3491 /* Return the previous insn before INSN that is not a DEBUG_INSN.
3492 This routine does not look inside SEQUENCEs. */
3495 prev_nondebug_insn (rtx_insn
*insn
)
3499 insn
= PREV_INSN (insn
);
3500 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3507 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN.
3508 This routine does not look inside SEQUENCEs. */
3511 next_nonnote_nondebug_insn (rtx_insn
*insn
)
3515 insn
= NEXT_INSN (insn
);
3516 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3523 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN,
3524 but stop the search before we enter another basic block. This
3525 routine does not look inside SEQUENCEs. */
3528 next_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3532 insn
= NEXT_INSN (insn
);
3535 if (DEBUG_INSN_P (insn
))
3539 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3546 /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN.
3547 This routine does not look inside SEQUENCEs. */
3550 prev_nonnote_nondebug_insn (rtx_insn
*insn
)
3554 insn
= PREV_INSN (insn
);
3555 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3562 /* Return the previous insn before INSN that is not a NOTE nor
3563 DEBUG_INSN, but stop the search before we enter another basic
3564 block. This routine does not look inside SEQUENCEs. */
3567 prev_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3571 insn
= PREV_INSN (insn
);
3574 if (DEBUG_INSN_P (insn
))
3578 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3585 /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN;
3586 or 0, if there is none. This routine does not look inside
3590 next_real_insn (rtx_insn
*insn
)
3594 insn
= NEXT_INSN (insn
);
3595 if (insn
== 0 || INSN_P (insn
))
3602 /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN;
3603 or 0, if there is none. This routine does not look inside
3607 prev_real_insn (rtx_insn
*insn
)
3611 insn
= PREV_INSN (insn
);
3612 if (insn
== 0 || INSN_P (insn
))
3619 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
3620 or 0, if there is none. This routine does not look inside
3624 next_real_nondebug_insn (rtx uncast_insn
)
3626 rtx_insn
*insn
= safe_as_a
<rtx_insn
*> (uncast_insn
);
3630 insn
= NEXT_INSN (insn
);
3631 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3638 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
3639 or 0, if there is none. This routine does not look inside
3643 prev_real_nondebug_insn (rtx_insn
*insn
)
3647 insn
= PREV_INSN (insn
);
3648 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3655 /* Return the last CALL_INSN in the current list, or 0 if there is none.
3656 This routine does not look inside SEQUENCEs. */
3659 last_call_insn (void)
3663 for (insn
= get_last_insn ();
3664 insn
&& !CALL_P (insn
);
3665 insn
= PREV_INSN (insn
))
3668 return safe_as_a
<rtx_call_insn
*> (insn
);
3671 /* Find the next insn after INSN that really does something. This routine
3672 does not look inside SEQUENCEs. After reload this also skips over
3673 standalone USE and CLOBBER insn. */
3676 active_insn_p (const rtx_insn
*insn
)
3678 return (CALL_P (insn
) || JUMP_P (insn
)
3679 || JUMP_TABLE_DATA_P (insn
) /* FIXME */
3680 || (NONJUMP_INSN_P (insn
)
3681 && (! reload_completed
3682 || (GET_CODE (PATTERN (insn
)) != USE
3683 && GET_CODE (PATTERN (insn
)) != CLOBBER
))));
3687 next_active_insn (rtx_insn
*insn
)
3691 insn
= NEXT_INSN (insn
);
3692 if (insn
== 0 || active_insn_p (insn
))
3699 /* Find the last insn before INSN that really does something. This routine
3700 does not look inside SEQUENCEs. After reload this also skips over
3701 standalone USE and CLOBBER insn. */
3704 prev_active_insn (rtx_insn
*insn
)
3708 insn
= PREV_INSN (insn
);
3709 if (insn
== 0 || active_insn_p (insn
))
3716 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3719 find_auto_inc (const_rtx x
, const_rtx reg
)
3721 subrtx_iterator::array_type array
;
3722 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
3724 const_rtx x
= *iter
;
3725 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
3726 && rtx_equal_p (reg
, XEXP (x
, 0)))
3732 /* Increment the label uses for all labels present in rtx. */
3735 mark_label_nuses (rtx x
)
3741 code
= GET_CODE (x
);
3742 if (code
== LABEL_REF
&& LABEL_P (label_ref_label (x
)))
3743 LABEL_NUSES (label_ref_label (x
))++;
3745 fmt
= GET_RTX_FORMAT (code
);
3746 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3749 mark_label_nuses (XEXP (x
, i
));
3750 else if (fmt
[i
] == 'E')
3751 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3752 mark_label_nuses (XVECEXP (x
, i
, j
));
3757 /* Try splitting insns that can be split for better scheduling.
3758 PAT is the pattern which might split.
3759 TRIAL is the insn providing PAT.
3760 LAST is nonzero if we should return the last insn of the sequence produced.
3762 If this routine succeeds in splitting, it returns the first or last
3763 replacement insn depending on the value of LAST. Otherwise, it
3764 returns TRIAL. If the insn to be returned can be split, it will be. */
3767 try_split (rtx pat
, rtx_insn
*trial
, int last
)
3769 rtx_insn
*before
, *after
;
3771 rtx_insn
*seq
, *tem
;
3772 profile_probability probability
;
3773 rtx_insn
*insn_last
, *insn
;
3775 rtx_insn
*call_insn
= NULL
;
3777 if (any_condjump_p (trial
)
3778 && (note
= find_reg_note (trial
, REG_BR_PROB
, 0)))
3779 split_branch_probability
3780 = profile_probability::from_reg_br_prob_note (XINT (note
, 0));
3782 split_branch_probability
= profile_probability::uninitialized ();
3784 probability
= split_branch_probability
;
3786 seq
= split_insns (pat
, trial
);
3788 split_branch_probability
= profile_probability::uninitialized ();
3793 int split_insn_count
= 0;
3794 /* Avoid infinite loop if any insn of the result matches
3795 the original pattern. */
3799 if (INSN_P (insn_last
)
3800 && rtx_equal_p (PATTERN (insn_last
), pat
))
3803 if (!NEXT_INSN (insn_last
))
3805 insn_last
= NEXT_INSN (insn_last
);
3808 /* We're not good at redistributing frame information if
3809 the split occurs before reload or if it results in more
3811 if (RTX_FRAME_RELATED_P (trial
))
3813 if (!reload_completed
|| split_insn_count
!= 1)
3816 rtx_insn
*new_insn
= seq
;
3817 rtx_insn
*old_insn
= trial
;
3818 copy_frame_info_to_split_insn (old_insn
, new_insn
);
3821 /* We will be adding the new sequence to the function. The splitters
3822 may have introduced invalid RTL sharing, so unshare the sequence now. */
3823 unshare_all_rtl_in_chain (seq
);
3825 /* Mark labels and copy flags. */
3826 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3831 CROSSING_JUMP_P (insn
) = CROSSING_JUMP_P (trial
);
3832 mark_jump_label (PATTERN (insn
), insn
, 0);
3834 if (probability
.initialized_p ()
3835 && any_condjump_p (insn
)
3836 && !find_reg_note (insn
, REG_BR_PROB
, 0))
3838 /* We can preserve the REG_BR_PROB notes only if exactly
3839 one jump is created, otherwise the machine description
3840 is responsible for this step using
3841 split_branch_probability variable. */
3842 gcc_assert (njumps
== 1);
3843 add_reg_br_prob_note (insn
, probability
);
3848 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3849 in SEQ and copy any additional information across. */
3852 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3855 gcc_assert (call_insn
== NULL_RTX
);
3858 /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the
3859 target may have explicitly specified. */
3860 rtx
*p
= &CALL_INSN_FUNCTION_USAGE (insn
);
3863 *p
= CALL_INSN_FUNCTION_USAGE (trial
);
3865 /* If the old call was a sibling call, the new one must
3867 SIBLING_CALL_P (insn
) = SIBLING_CALL_P (trial
);
3871 /* Copy notes, particularly those related to the CFG. */
3872 for (note
= REG_NOTES (trial
); note
; note
= XEXP (note
, 1))
3874 switch (REG_NOTE_KIND (note
))
3877 copy_reg_eh_region_note_backward (note
, insn_last
, NULL
);
3883 case REG_CALL_NOCF_CHECK
:
3884 case REG_CALL_ARG_LOCATION
:
3885 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3888 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3892 case REG_NON_LOCAL_GOTO
:
3893 case REG_LABEL_TARGET
:
3894 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3897 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3905 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3907 rtx reg
= XEXP (note
, 0);
3908 if (!FIND_REG_INC_NOTE (insn
, reg
)
3909 && find_auto_inc (PATTERN (insn
), reg
))
3910 add_reg_note (insn
, REG_INC
, reg
);
3915 fixup_args_size_notes (NULL
, insn_last
, get_args_size (note
));
3919 case REG_UNTYPED_CALL
:
3920 gcc_assert (call_insn
!= NULL_RTX
);
3921 add_reg_note (call_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3929 /* If there are LABELS inside the split insns increment the
3930 usage count so we don't delete the label. */
3934 while (insn
!= NULL_RTX
)
3936 /* JUMP_P insns have already been "marked" above. */
3937 if (NONJUMP_INSN_P (insn
))
3938 mark_label_nuses (PATTERN (insn
));
3940 insn
= PREV_INSN (insn
);
3944 before
= PREV_INSN (trial
);
3945 after
= NEXT_INSN (trial
);
3947 emit_insn_after_setloc (seq
, trial
, INSN_LOCATION (trial
));
3949 delete_insn (trial
);
3951 /* Recursively call try_split for each new insn created; by the
3952 time control returns here that insn will be fully split, so
3953 set LAST and continue from the insn after the one returned.
3954 We can't use next_active_insn here since AFTER may be a note.
3955 Ignore deleted insns, which can be occur if not optimizing. */
3956 for (tem
= NEXT_INSN (before
); tem
!= after
; tem
= NEXT_INSN (tem
))
3957 if (! tem
->deleted () && INSN_P (tem
))
3958 tem
= try_split (PATTERN (tem
), tem
, 1);
3960 /* Return either the first or the last insn, depending on which was
3963 ? (after
? PREV_INSN (after
) : get_last_insn ())
3964 : NEXT_INSN (before
);
3967 /* Make and return an INSN rtx, initializing all its slots.
3968 Store PATTERN in the pattern slots. */
3971 make_insn_raw (rtx pattern
)
3975 insn
= as_a
<rtx_insn
*> (rtx_alloc (INSN
));
3977 INSN_UID (insn
) = cur_insn_uid
++;
3978 PATTERN (insn
) = pattern
;
3979 INSN_CODE (insn
) = -1;
3980 REG_NOTES (insn
) = NULL
;
3981 INSN_LOCATION (insn
) = curr_insn_location ();
3982 BLOCK_FOR_INSN (insn
) = NULL
;
3984 #ifdef ENABLE_RTL_CHECKING
3987 && (returnjump_p (insn
)
3988 || (GET_CODE (insn
) == SET
3989 && SET_DEST (insn
) == pc_rtx
)))
3991 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
3999 /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */
4002 make_debug_insn_raw (rtx pattern
)
4004 rtx_debug_insn
*insn
;
4006 insn
= as_a
<rtx_debug_insn
*> (rtx_alloc (DEBUG_INSN
));
4007 INSN_UID (insn
) = cur_debug_insn_uid
++;
4008 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
4009 INSN_UID (insn
) = cur_insn_uid
++;
4011 PATTERN (insn
) = pattern
;
4012 INSN_CODE (insn
) = -1;
4013 REG_NOTES (insn
) = NULL
;
4014 INSN_LOCATION (insn
) = curr_insn_location ();
4015 BLOCK_FOR_INSN (insn
) = NULL
;
4020 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
4023 make_jump_insn_raw (rtx pattern
)
4025 rtx_jump_insn
*insn
;
4027 insn
= as_a
<rtx_jump_insn
*> (rtx_alloc (JUMP_INSN
));
4028 INSN_UID (insn
) = cur_insn_uid
++;
4030 PATTERN (insn
) = pattern
;
4031 INSN_CODE (insn
) = -1;
4032 REG_NOTES (insn
) = NULL
;
4033 JUMP_LABEL (insn
) = NULL
;
4034 INSN_LOCATION (insn
) = curr_insn_location ();
4035 BLOCK_FOR_INSN (insn
) = NULL
;
4040 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
4043 make_call_insn_raw (rtx pattern
)
4045 rtx_call_insn
*insn
;
4047 insn
= as_a
<rtx_call_insn
*> (rtx_alloc (CALL_INSN
));
4048 INSN_UID (insn
) = cur_insn_uid
++;
4050 PATTERN (insn
) = pattern
;
4051 INSN_CODE (insn
) = -1;
4052 REG_NOTES (insn
) = NULL
;
4053 CALL_INSN_FUNCTION_USAGE (insn
) = NULL
;
4054 INSN_LOCATION (insn
) = curr_insn_location ();
4055 BLOCK_FOR_INSN (insn
) = NULL
;
4060 /* Like `make_insn_raw' but make a NOTE instead of an insn. */
4063 make_note_raw (enum insn_note subtype
)
4065 /* Some notes are never created this way at all. These notes are
4066 only created by patching out insns. */
4067 gcc_assert (subtype
!= NOTE_INSN_DELETED_LABEL
4068 && subtype
!= NOTE_INSN_DELETED_DEBUG_LABEL
);
4070 rtx_note
*note
= as_a
<rtx_note
*> (rtx_alloc (NOTE
));
4071 INSN_UID (note
) = cur_insn_uid
++;
4072 NOTE_KIND (note
) = subtype
;
4073 BLOCK_FOR_INSN (note
) = NULL
;
4074 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
4078 /* Add INSN to the end of the doubly-linked list, between PREV and NEXT.
4079 INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects,
4080 but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */
4083 link_insn_into_chain (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4085 SET_PREV_INSN (insn
) = prev
;
4086 SET_NEXT_INSN (insn
) = next
;
4089 SET_NEXT_INSN (prev
) = insn
;
4090 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4092 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4093 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = insn
;
4098 SET_PREV_INSN (next
) = insn
;
4099 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4101 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4102 SET_PREV_INSN (sequence
->insn (0)) = insn
;
4106 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4108 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (insn
));
4109 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4110 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4114 /* Add INSN to the end of the doubly-linked list.
4115 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
4118 add_insn (rtx_insn
*insn
)
4120 rtx_insn
*prev
= get_last_insn ();
4121 link_insn_into_chain (insn
, prev
, NULL
);
4122 if (get_insns () == NULL
)
4123 set_first_insn (insn
);
4124 set_last_insn (insn
);
4127 /* Add INSN into the doubly-linked list after insn AFTER. */
4130 add_insn_after_nobb (rtx_insn
*insn
, rtx_insn
*after
)
4132 rtx_insn
*next
= NEXT_INSN (after
);
4134 gcc_assert (!optimize
|| !after
->deleted ());
4136 link_insn_into_chain (insn
, after
, next
);
4140 struct sequence_stack
*seq
;
4142 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4143 if (after
== seq
->last
)
4151 /* Add INSN into the doubly-linked list before insn BEFORE. */
4154 add_insn_before_nobb (rtx_insn
*insn
, rtx_insn
*before
)
4156 rtx_insn
*prev
= PREV_INSN (before
);
4158 gcc_assert (!optimize
|| !before
->deleted ());
4160 link_insn_into_chain (insn
, prev
, before
);
4164 struct sequence_stack
*seq
;
4166 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4167 if (before
== seq
->first
)
4177 /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN.
4178 If BB is NULL, an attempt is made to infer the bb from before.
4180 This and the next function should be the only functions called
4181 to insert an insn once delay slots have been filled since only
4182 they know how to update a SEQUENCE. */
4185 add_insn_after (rtx_insn
*insn
, rtx_insn
*after
, basic_block bb
)
4187 add_insn_after_nobb (insn
, after
);
4188 if (!BARRIER_P (after
)
4189 && !BARRIER_P (insn
)
4190 && (bb
= BLOCK_FOR_INSN (after
)))
4192 set_block_for_insn (insn
, bb
);
4194 df_insn_rescan (insn
);
4195 /* Should not happen as first in the BB is always
4196 either NOTE or LABEL. */
4197 if (BB_END (bb
) == after
4198 /* Avoid clobbering of structure when creating new BB. */
4199 && !BARRIER_P (insn
)
4200 && !NOTE_INSN_BASIC_BLOCK_P (insn
))
4205 /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN.
4206 If BB is NULL, an attempt is made to infer the bb from before.
4208 This and the previous function should be the only functions called
4209 to insert an insn once delay slots have been filled since only
4210 they know how to update a SEQUENCE. */
4213 add_insn_before (rtx_insn
*insn
, rtx_insn
*before
, basic_block bb
)
4215 add_insn_before_nobb (insn
, before
);
4218 && !BARRIER_P (before
)
4219 && !BARRIER_P (insn
))
4220 bb
= BLOCK_FOR_INSN (before
);
4224 set_block_for_insn (insn
, bb
);
4226 df_insn_rescan (insn
);
4227 /* Should not happen as first in the BB is always either NOTE or
4229 gcc_assert (BB_HEAD (bb
) != insn
4230 /* Avoid clobbering of structure when creating new BB. */
4232 || NOTE_INSN_BASIC_BLOCK_P (insn
));
4236 /* Replace insn with an deleted instruction note. */
4239 set_insn_deleted (rtx_insn
*insn
)
4242 df_insn_delete (insn
);
4243 PUT_CODE (insn
, NOTE
);
4244 NOTE_KIND (insn
) = NOTE_INSN_DELETED
;
4248 /* Unlink INSN from the insn chain.
4250 This function knows how to handle sequences.
4252 This function does not invalidate data flow information associated with
4253 INSN (i.e. does not call df_insn_delete). That makes this function
4254 usable for only disconnecting an insn from the chain, and re-emit it
4257 To later insert INSN elsewhere in the insn chain via add_insn and
4258 similar functions, PREV_INSN and NEXT_INSN must be nullified by
4259 the caller. Nullifying them here breaks many insn chain walks.
4261 To really delete an insn and related DF information, use delete_insn. */
4264 remove_insn (rtx_insn
*insn
)
4266 rtx_insn
*next
= NEXT_INSN (insn
);
4267 rtx_insn
*prev
= PREV_INSN (insn
);
4272 SET_NEXT_INSN (prev
) = next
;
4273 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4275 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4276 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4281 struct sequence_stack
*seq
;
4283 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4284 if (insn
== seq
->first
)
4295 SET_PREV_INSN (next
) = prev
;
4296 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4298 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4299 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4304 struct sequence_stack
*seq
;
4306 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4307 if (insn
== seq
->last
)
4316 /* Fix up basic block boundaries, if necessary. */
4317 if (!BARRIER_P (insn
)
4318 && (bb
= BLOCK_FOR_INSN (insn
)))
4320 if (BB_HEAD (bb
) == insn
)
4322 /* Never ever delete the basic block note without deleting whole
4324 gcc_assert (!NOTE_P (insn
));
4325 BB_HEAD (bb
) = next
;
4327 if (BB_END (bb
) == insn
)
4332 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
4335 add_function_usage_to (rtx call_insn
, rtx call_fusage
)
4337 gcc_assert (call_insn
&& CALL_P (call_insn
));
4339 /* Put the register usage information on the CALL. If there is already
4340 some usage information, put ours at the end. */
4341 if (CALL_INSN_FUNCTION_USAGE (call_insn
))
4345 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); XEXP (link
, 1) != 0;
4346 link
= XEXP (link
, 1))
4349 XEXP (link
, 1) = call_fusage
;
4352 CALL_INSN_FUNCTION_USAGE (call_insn
) = call_fusage
;
4355 /* Delete all insns made since FROM.
4356 FROM becomes the new last instruction. */
4359 delete_insns_since (rtx_insn
*from
)
4364 SET_NEXT_INSN (from
) = 0;
4365 set_last_insn (from
);
4368 /* This function is deprecated, please use sequences instead.
4370 Move a consecutive bunch of insns to a different place in the chain.
4371 The insns to be moved are those between FROM and TO.
4372 They are moved to a new position after the insn AFTER.
4373 AFTER must not be FROM or TO or any insn in between.
4375 This function does not know about SEQUENCEs and hence should not be
4376 called after delay-slot filling has been done. */
4379 reorder_insns_nobb (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4383 for (rtx_insn
*x
= from
; x
!= to
; x
= NEXT_INSN (x
))
4384 gcc_assert (after
!= x
);
4385 gcc_assert (after
!= to
);
4388 /* Splice this bunch out of where it is now. */
4389 if (PREV_INSN (from
))
4390 SET_NEXT_INSN (PREV_INSN (from
)) = NEXT_INSN (to
);
4392 SET_PREV_INSN (NEXT_INSN (to
)) = PREV_INSN (from
);
4393 if (get_last_insn () == to
)
4394 set_last_insn (PREV_INSN (from
));
4395 if (get_insns () == from
)
4396 set_first_insn (NEXT_INSN (to
));
4398 /* Make the new neighbors point to it and it to them. */
4399 if (NEXT_INSN (after
))
4400 SET_PREV_INSN (NEXT_INSN (after
)) = to
;
4402 SET_NEXT_INSN (to
) = NEXT_INSN (after
);
4403 SET_PREV_INSN (from
) = after
;
4404 SET_NEXT_INSN (after
) = from
;
4405 if (after
== get_last_insn ())
4409 /* Same as function above, but take care to update BB boundaries. */
4411 reorder_insns (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4413 rtx_insn
*prev
= PREV_INSN (from
);
4414 basic_block bb
, bb2
;
4416 reorder_insns_nobb (from
, to
, after
);
4418 if (!BARRIER_P (after
)
4419 && (bb
= BLOCK_FOR_INSN (after
)))
4422 df_set_bb_dirty (bb
);
4424 if (!BARRIER_P (from
)
4425 && (bb2
= BLOCK_FOR_INSN (from
)))
4427 if (BB_END (bb2
) == to
)
4428 BB_END (bb2
) = prev
;
4429 df_set_bb_dirty (bb2
);
4432 if (BB_END (bb
) == after
)
4435 for (x
= from
; x
!= NEXT_INSN (to
); x
= NEXT_INSN (x
))
4437 df_insn_change_bb (x
, bb
);
4442 /* Emit insn(s) of given code and pattern
4443 at a specified place within the doubly-linked list.
4445 All of the emit_foo global entry points accept an object
4446 X which is either an insn list or a PATTERN of a single
4449 There are thus a few canonical ways to generate code and
4450 emit it at a specific place in the instruction stream. For
4451 example, consider the instruction named SPOT and the fact that
4452 we would like to emit some instructions before SPOT. We might
4456 ... emit the new instructions ...
4457 insns_head = get_insns ();
4460 emit_insn_before (insns_head, SPOT);
4462 It used to be common to generate SEQUENCE rtl instead, but that
4463 is a relic of the past which no longer occurs. The reason is that
4464 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
4465 generated would almost certainly die right after it was created. */
4468 emit_pattern_before_noloc (rtx x
, rtx_insn
*before
, rtx_insn
*last
,
4470 rtx_insn
*(*make_raw
) (rtx
))
4474 gcc_assert (before
);
4479 switch (GET_CODE (x
))
4488 insn
= as_a
<rtx_insn
*> (x
);
4491 rtx_insn
*next
= NEXT_INSN (insn
);
4492 add_insn_before (insn
, before
, bb
);
4498 #ifdef ENABLE_RTL_CHECKING
4505 last
= (*make_raw
) (x
);
4506 add_insn_before (last
, before
, bb
);
4513 /* Make X be output before the instruction BEFORE. */
4516 emit_insn_before_noloc (rtx x
, rtx_insn
*before
, basic_block bb
)
4518 return emit_pattern_before_noloc (x
, before
, before
, bb
, make_insn_raw
);
4521 /* Make an instruction with body X and code JUMP_INSN
4522 and output it before the instruction BEFORE. */
4525 emit_jump_insn_before_noloc (rtx x
, rtx_insn
*before
)
4527 return as_a
<rtx_jump_insn
*> (
4528 emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4529 make_jump_insn_raw
));
4532 /* Make an instruction with body X and code CALL_INSN
4533 and output it before the instruction BEFORE. */
4536 emit_call_insn_before_noloc (rtx x
, rtx_insn
*before
)
4538 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4539 make_call_insn_raw
);
4542 /* Make an instruction with body X and code DEBUG_INSN
4543 and output it before the instruction BEFORE. */
4546 emit_debug_insn_before_noloc (rtx x
, rtx_insn
*before
)
4548 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4549 make_debug_insn_raw
);
4552 /* Make an insn of code BARRIER
4553 and output it before the insn BEFORE. */
4556 emit_barrier_before (rtx_insn
*before
)
4558 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4560 INSN_UID (insn
) = cur_insn_uid
++;
4562 add_insn_before (insn
, before
, NULL
);
4566 /* Emit the label LABEL before the insn BEFORE. */
4569 emit_label_before (rtx_code_label
*label
, rtx_insn
*before
)
4571 gcc_checking_assert (INSN_UID (label
) == 0);
4572 INSN_UID (label
) = cur_insn_uid
++;
4573 add_insn_before (label
, before
, NULL
);
4577 /* Helper for emit_insn_after, handles lists of instructions
4581 emit_insn_after_1 (rtx_insn
*first
, rtx_insn
*after
, basic_block bb
)
4584 rtx_insn
*after_after
;
4585 if (!bb
&& !BARRIER_P (after
))
4586 bb
= BLOCK_FOR_INSN (after
);
4590 df_set_bb_dirty (bb
);
4591 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4592 if (!BARRIER_P (last
))
4594 set_block_for_insn (last
, bb
);
4595 df_insn_rescan (last
);
4597 if (!BARRIER_P (last
))
4599 set_block_for_insn (last
, bb
);
4600 df_insn_rescan (last
);
4602 if (BB_END (bb
) == after
)
4606 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4609 after_after
= NEXT_INSN (after
);
4611 SET_NEXT_INSN (after
) = first
;
4612 SET_PREV_INSN (first
) = after
;
4613 SET_NEXT_INSN (last
) = after_after
;
4615 SET_PREV_INSN (after_after
) = last
;
4617 if (after
== get_last_insn ())
4618 set_last_insn (last
);
4624 emit_pattern_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
,
4625 rtx_insn
*(*make_raw
)(rtx
))
4627 rtx_insn
*last
= after
;
4634 switch (GET_CODE (x
))
4643 last
= emit_insn_after_1 (as_a
<rtx_insn
*> (x
), after
, bb
);
4646 #ifdef ENABLE_RTL_CHECKING
4653 last
= (*make_raw
) (x
);
4654 add_insn_after (last
, after
, bb
);
4661 /* Make X be output after the insn AFTER and set the BB of insn. If
4662 BB is NULL, an attempt is made to infer the BB from AFTER. */
4665 emit_insn_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
)
4667 return emit_pattern_after_noloc (x
, after
, bb
, make_insn_raw
);
4671 /* Make an insn of code JUMP_INSN with body X
4672 and output it after the insn AFTER. */
4675 emit_jump_insn_after_noloc (rtx x
, rtx_insn
*after
)
4677 return as_a
<rtx_jump_insn
*> (
4678 emit_pattern_after_noloc (x
, after
, NULL
, make_jump_insn_raw
));
4681 /* Make an instruction with body X and code CALL_INSN
4682 and output it after the instruction AFTER. */
4685 emit_call_insn_after_noloc (rtx x
, rtx_insn
*after
)
4687 return emit_pattern_after_noloc (x
, after
, NULL
, make_call_insn_raw
);
4690 /* Make an instruction with body X and code CALL_INSN
4691 and output it after the instruction AFTER. */
4694 emit_debug_insn_after_noloc (rtx x
, rtx_insn
*after
)
4696 return emit_pattern_after_noloc (x
, after
, NULL
, make_debug_insn_raw
);
4699 /* Make an insn of code BARRIER
4700 and output it after the insn AFTER. */
4703 emit_barrier_after (rtx_insn
*after
)
4705 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4707 INSN_UID (insn
) = cur_insn_uid
++;
4709 add_insn_after (insn
, after
, NULL
);
4713 /* Emit the label LABEL after the insn AFTER. */
4716 emit_label_after (rtx_insn
*label
, rtx_insn
*after
)
4718 gcc_checking_assert (INSN_UID (label
) == 0);
4719 INSN_UID (label
) = cur_insn_uid
++;
4720 add_insn_after (label
, after
, NULL
);
4724 /* Notes require a bit of special handling: Some notes need to have their
4725 BLOCK_FOR_INSN set, others should never have it set, and some should
4726 have it set or clear depending on the context. */
4728 /* Return true iff a note of kind SUBTYPE should be emitted with routines
4729 that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the
4730 caller is asked to emit a note before BB_HEAD, or after BB_END. */
4733 note_outside_basic_block_p (enum insn_note subtype
, bool on_bb_boundary_p
)
4737 /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */
4738 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
4741 /* Notes for var tracking and EH region markers can appear between or
4742 inside basic blocks. If the caller is emitting on the basic block
4743 boundary, do not set BLOCK_FOR_INSN on the new note. */
4744 case NOTE_INSN_VAR_LOCATION
:
4745 case NOTE_INSN_EH_REGION_BEG
:
4746 case NOTE_INSN_EH_REGION_END
:
4747 return on_bb_boundary_p
;
4749 /* Otherwise, BLOCK_FOR_INSN must be set. */
4755 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4758 emit_note_after (enum insn_note subtype
, rtx_insn
*after
)
4760 rtx_note
*note
= make_note_raw (subtype
);
4761 basic_block bb
= BARRIER_P (after
) ? NULL
: BLOCK_FOR_INSN (after
);
4762 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_END (bb
) == after
);
4764 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4765 add_insn_after_nobb (note
, after
);
4767 add_insn_after (note
, after
, bb
);
4771 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
4774 emit_note_before (enum insn_note subtype
, rtx_insn
*before
)
4776 rtx_note
*note
= make_note_raw (subtype
);
4777 basic_block bb
= BARRIER_P (before
) ? NULL
: BLOCK_FOR_INSN (before
);
4778 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_HEAD (bb
) == before
);
4780 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4781 add_insn_before_nobb (note
, before
);
4783 add_insn_before (note
, before
, bb
);
4787 /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC.
4788 MAKE_RAW indicates how to turn PATTERN into a real insn. */
4791 emit_pattern_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
,
4792 rtx_insn
*(*make_raw
) (rtx
))
4794 rtx_insn
*last
= emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4796 if (pattern
== NULL_RTX
|| !loc
)
4799 after
= NEXT_INSN (after
);
4802 if (active_insn_p (after
)
4803 && !JUMP_TABLE_DATA_P (after
) /* FIXME */
4804 && !INSN_LOCATION (after
))
4805 INSN_LOCATION (after
) = loc
;
4808 after
= NEXT_INSN (after
);
4813 /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN
4814 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after
4818 emit_pattern_after (rtx pattern
, rtx_insn
*after
, bool skip_debug_insns
,
4819 rtx_insn
*(*make_raw
) (rtx
))
4821 rtx_insn
*prev
= after
;
4823 if (skip_debug_insns
)
4824 while (DEBUG_INSN_P (prev
))
4825 prev
= PREV_INSN (prev
);
4828 return emit_pattern_after_setloc (pattern
, after
, INSN_LOCATION (prev
),
4831 return emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4834 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4836 emit_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4838 return emit_pattern_after_setloc (pattern
, after
, loc
, make_insn_raw
);
4841 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4843 emit_insn_after (rtx pattern
, rtx_insn
*after
)
4845 return emit_pattern_after (pattern
, after
, true, make_insn_raw
);
4848 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4850 emit_jump_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4852 return as_a
<rtx_jump_insn
*> (
4853 emit_pattern_after_setloc (pattern
, after
, loc
, make_jump_insn_raw
));
4856 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4858 emit_jump_insn_after (rtx pattern
, rtx_insn
*after
)
4860 return as_a
<rtx_jump_insn
*> (
4861 emit_pattern_after (pattern
, after
, true, make_jump_insn_raw
));
4864 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4866 emit_call_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4868 return emit_pattern_after_setloc (pattern
, after
, loc
, make_call_insn_raw
);
4871 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4873 emit_call_insn_after (rtx pattern
, rtx_insn
*after
)
4875 return emit_pattern_after (pattern
, after
, true, make_call_insn_raw
);
4878 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4880 emit_debug_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4882 return emit_pattern_after_setloc (pattern
, after
, loc
, make_debug_insn_raw
);
4885 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4887 emit_debug_insn_after (rtx pattern
, rtx_insn
*after
)
4889 return emit_pattern_after (pattern
, after
, false, make_debug_insn_raw
);
4892 /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC.
4893 MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP
4894 indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN,
4898 emit_pattern_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
,
4899 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
4901 rtx_insn
*first
= PREV_INSN (before
);
4902 rtx_insn
*last
= emit_pattern_before_noloc (pattern
, before
,
4903 insnp
? before
: NULL
,
4906 if (pattern
== NULL_RTX
|| !loc
)
4910 first
= get_insns ();
4912 first
= NEXT_INSN (first
);
4915 if (active_insn_p (first
)
4916 && !JUMP_TABLE_DATA_P (first
) /* FIXME */
4917 && !INSN_LOCATION (first
))
4918 INSN_LOCATION (first
) = loc
;
4921 first
= NEXT_INSN (first
);
4926 /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN
4927 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert
4928 before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an
4929 INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */
4932 emit_pattern_before (rtx pattern
, rtx_insn
*before
, bool skip_debug_insns
,
4933 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
4935 rtx_insn
*next
= before
;
4937 if (skip_debug_insns
)
4938 while (DEBUG_INSN_P (next
))
4939 next
= PREV_INSN (next
);
4942 return emit_pattern_before_setloc (pattern
, before
, INSN_LOCATION (next
),
4945 return emit_pattern_before_noloc (pattern
, before
,
4946 insnp
? before
: NULL
,
4950 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
4952 emit_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
4954 return emit_pattern_before_setloc (pattern
, before
, loc
, true,
4958 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
4960 emit_insn_before (rtx pattern
, rtx_insn
*before
)
4962 return emit_pattern_before (pattern
, before
, true, true, make_insn_raw
);
4965 /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
4967 emit_jump_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
4969 return as_a
<rtx_jump_insn
*> (
4970 emit_pattern_before_setloc (pattern
, before
, loc
, false,
4971 make_jump_insn_raw
));
4974 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
4976 emit_jump_insn_before (rtx pattern
, rtx_insn
*before
)
4978 return as_a
<rtx_jump_insn
*> (
4979 emit_pattern_before (pattern
, before
, true, false,
4980 make_jump_insn_raw
));
4983 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
4985 emit_call_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
4987 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
4988 make_call_insn_raw
);
4991 /* Like emit_call_insn_before_noloc,
4992 but set insn_location according to BEFORE. */
4994 emit_call_insn_before (rtx pattern
, rtx_insn
*before
)
4996 return emit_pattern_before (pattern
, before
, true, false,
4997 make_call_insn_raw
);
5000 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5002 emit_debug_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5004 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
5005 make_debug_insn_raw
);
5008 /* Like emit_debug_insn_before_noloc,
5009 but set insn_location according to BEFORE. */
5011 emit_debug_insn_before (rtx pattern
, rtx_insn
*before
)
5013 return emit_pattern_before (pattern
, before
, false, false,
5014 make_debug_insn_raw
);
5017 /* Take X and emit it at the end of the doubly-linked
5020 Returns the last insn emitted. */
5025 rtx_insn
*last
= get_last_insn ();
5031 switch (GET_CODE (x
))
5040 insn
= as_a
<rtx_insn
*> (x
);
5043 rtx_insn
*next
= NEXT_INSN (insn
);
5050 #ifdef ENABLE_RTL_CHECKING
5051 case JUMP_TABLE_DATA
:
5058 last
= make_insn_raw (x
);
5066 /* Make an insn of code DEBUG_INSN with pattern X
5067 and add it to the end of the doubly-linked list. */
5070 emit_debug_insn (rtx x
)
5072 rtx_insn
*last
= get_last_insn ();
5078 switch (GET_CODE (x
))
5087 insn
= as_a
<rtx_insn
*> (x
);
5090 rtx_insn
*next
= NEXT_INSN (insn
);
5097 #ifdef ENABLE_RTL_CHECKING
5098 case JUMP_TABLE_DATA
:
5105 last
= make_debug_insn_raw (x
);
5113 /* Make an insn of code JUMP_INSN with pattern X
5114 and add it to the end of the doubly-linked list. */
5117 emit_jump_insn (rtx x
)
5119 rtx_insn
*last
= NULL
;
5122 switch (GET_CODE (x
))
5131 insn
= as_a
<rtx_insn
*> (x
);
5134 rtx_insn
*next
= NEXT_INSN (insn
);
5141 #ifdef ENABLE_RTL_CHECKING
5142 case JUMP_TABLE_DATA
:
5149 last
= make_jump_insn_raw (x
);
5157 /* Make an insn of code CALL_INSN with pattern X
5158 and add it to the end of the doubly-linked list. */
5161 emit_call_insn (rtx x
)
5165 switch (GET_CODE (x
))
5174 insn
= emit_insn (x
);
5177 #ifdef ENABLE_RTL_CHECKING
5179 case JUMP_TABLE_DATA
:
5185 insn
= make_call_insn_raw (x
);
5193 /* Add the label LABEL to the end of the doubly-linked list. */
5196 emit_label (rtx uncast_label
)
5198 rtx_code_label
*label
= as_a
<rtx_code_label
*> (uncast_label
);
5200 gcc_checking_assert (INSN_UID (label
) == 0);
5201 INSN_UID (label
) = cur_insn_uid
++;
5206 /* Make an insn of code JUMP_TABLE_DATA
5207 and add it to the end of the doubly-linked list. */
5209 rtx_jump_table_data
*
5210 emit_jump_table_data (rtx table
)
5212 rtx_jump_table_data
*jump_table_data
=
5213 as_a
<rtx_jump_table_data
*> (rtx_alloc (JUMP_TABLE_DATA
));
5214 INSN_UID (jump_table_data
) = cur_insn_uid
++;
5215 PATTERN (jump_table_data
) = table
;
5216 BLOCK_FOR_INSN (jump_table_data
) = NULL
;
5217 add_insn (jump_table_data
);
5218 return jump_table_data
;
5221 /* Make an insn of code BARRIER
5222 and add it to the end of the doubly-linked list. */
5227 rtx_barrier
*barrier
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
5228 INSN_UID (barrier
) = cur_insn_uid
++;
5233 /* Emit a copy of note ORIG. */
5236 emit_note_copy (rtx_note
*orig
)
5238 enum insn_note kind
= (enum insn_note
) NOTE_KIND (orig
);
5239 rtx_note
*note
= make_note_raw (kind
);
5240 NOTE_DATA (note
) = NOTE_DATA (orig
);
5245 /* Make an insn of code NOTE or type NOTE_NO
5246 and add it to the end of the doubly-linked list. */
5249 emit_note (enum insn_note kind
)
5251 rtx_note
*note
= make_note_raw (kind
);
5256 /* Emit a clobber of lvalue X. */
5259 emit_clobber (rtx x
)
5261 /* CONCATs should not appear in the insn stream. */
5262 if (GET_CODE (x
) == CONCAT
)
5264 emit_clobber (XEXP (x
, 0));
5265 return emit_clobber (XEXP (x
, 1));
5267 return emit_insn (gen_rtx_CLOBBER (VOIDmode
, x
));
5270 /* Return a sequence of insns to clobber lvalue X. */
5284 /* Emit a use of rvalue X. */
5289 /* CONCATs should not appear in the insn stream. */
5290 if (GET_CODE (x
) == CONCAT
)
5292 emit_use (XEXP (x
, 0));
5293 return emit_use (XEXP (x
, 1));
5295 return emit_insn (gen_rtx_USE (VOIDmode
, x
));
5298 /* Return a sequence of insns to use rvalue X. */
5312 /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction.
5313 Return the set in INSN that such notes describe, or NULL if the notes
5314 have no meaning for INSN. */
5317 set_for_reg_notes (rtx insn
)
5324 pat
= PATTERN (insn
);
5325 if (GET_CODE (pat
) == PARALLEL
)
5327 /* We do not use single_set because that ignores SETs of unused
5328 registers. REG_EQUAL and REG_EQUIV notes really do require the
5329 PARALLEL to have a single SET. */
5330 if (multiple_sets (insn
))
5332 pat
= XVECEXP (pat
, 0, 0);
5335 if (GET_CODE (pat
) != SET
)
5338 reg
= SET_DEST (pat
);
5340 /* Notes apply to the contents of a STRICT_LOW_PART. */
5341 if (GET_CODE (reg
) == STRICT_LOW_PART
5342 || GET_CODE (reg
) == ZERO_EXTRACT
)
5343 reg
= XEXP (reg
, 0);
5345 /* Check that we have a register. */
5346 if (!(REG_P (reg
) || GET_CODE (reg
) == SUBREG
))
5352 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
5353 note of this type already exists, remove it first. */
5356 set_unique_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
5358 rtx note
= find_reg_note (insn
, kind
, NULL_RTX
);
5364 /* We need to support the REG_EQUAL on USE trick of find_reloads. */
5365 if (!set_for_reg_notes (insn
) && GET_CODE (PATTERN (insn
)) != USE
)
5368 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
5369 It serves no useful purpose and breaks eliminate_regs. */
5370 if (GET_CODE (datum
) == ASM_OPERANDS
)
5373 /* Notes with side effects are dangerous. Even if the side-effect
5374 initially mirrors one in PATTERN (INSN), later optimizations
5375 might alter the way that the final register value is calculated
5376 and so move or alter the side-effect in some way. The note would
5377 then no longer be a valid substitution for SET_SRC. */
5378 if (side_effects_p (datum
))
5387 XEXP (note
, 0) = datum
;
5390 add_reg_note (insn
, kind
, datum
);
5391 note
= REG_NOTES (insn
);
5398 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
5407 /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */
5409 set_dst_reg_note (rtx insn
, enum reg_note kind
, rtx datum
, rtx dst
)
5411 rtx set
= set_for_reg_notes (insn
);
5413 if (set
&& SET_DEST (set
) == dst
)
5414 return set_unique_reg_note (insn
, kind
, datum
);
5418 /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a
5419 following barrier if the instruction needs one and if ALLOW_BARRIER_P
5422 If X is a label, it is simply added into the insn chain. */
5425 emit (rtx x
, bool allow_barrier_p
)
5427 enum rtx_code code
= classify_insn (x
);
5432 return emit_label (x
);
5434 return emit_insn (x
);
5437 rtx_insn
*insn
= emit_jump_insn (x
);
5439 && (any_uncondjump_p (insn
) || GET_CODE (x
) == RETURN
))
5440 return emit_barrier ();
5444 return emit_call_insn (x
);
5446 return emit_debug_insn (x
);
5452 /* Space for free sequence stack entries. */
5453 static GTY ((deletable
)) struct sequence_stack
*free_sequence_stack
;
5455 /* Begin emitting insns to a sequence. If this sequence will contain
5456 something that might cause the compiler to pop arguments to function
5457 calls (because those pops have previously been deferred; see
5458 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
5459 before calling this function. That will ensure that the deferred
5460 pops are not accidentally emitted in the middle of this sequence. */
5463 start_sequence (void)
5465 struct sequence_stack
*tem
;
5467 if (free_sequence_stack
!= NULL
)
5469 tem
= free_sequence_stack
;
5470 free_sequence_stack
= tem
->next
;
5473 tem
= ggc_alloc
<sequence_stack
> ();
5475 tem
->next
= get_current_sequence ()->next
;
5476 tem
->first
= get_insns ();
5477 tem
->last
= get_last_insn ();
5478 get_current_sequence ()->next
= tem
;
5484 /* Set up the insn chain starting with FIRST as the current sequence,
5485 saving the previously current one. See the documentation for
5486 start_sequence for more information about how to use this function. */
5489 push_to_sequence (rtx_insn
*first
)
5495 for (last
= first
; last
&& NEXT_INSN (last
); last
= NEXT_INSN (last
))
5498 set_first_insn (first
);
5499 set_last_insn (last
);
5502 /* Like push_to_sequence, but take the last insn as an argument to avoid
5503 looping through the list. */
5506 push_to_sequence2 (rtx_insn
*first
, rtx_insn
*last
)
5510 set_first_insn (first
);
5511 set_last_insn (last
);
5514 /* Set up the outer-level insn chain
5515 as the current sequence, saving the previously current one. */
5518 push_topmost_sequence (void)
5520 struct sequence_stack
*top
;
5524 top
= get_topmost_sequence ();
5525 set_first_insn (top
->first
);
5526 set_last_insn (top
->last
);
5529 /* After emitting to the outer-level insn chain, update the outer-level
5530 insn chain, and restore the previous saved state. */
5533 pop_topmost_sequence (void)
5535 struct sequence_stack
*top
;
5537 top
= get_topmost_sequence ();
5538 top
->first
= get_insns ();
5539 top
->last
= get_last_insn ();
5544 /* After emitting to a sequence, restore previous saved state.
5546 To get the contents of the sequence just made, you must call
5547 `get_insns' *before* calling here.
5549 If the compiler might have deferred popping arguments while
5550 generating this sequence, and this sequence will not be immediately
5551 inserted into the instruction stream, use do_pending_stack_adjust
5552 before calling get_insns. That will ensure that the deferred
5553 pops are inserted into this sequence, and not into some random
5554 location in the instruction stream. See INHIBIT_DEFER_POP for more
5555 information about deferred popping of arguments. */
5560 struct sequence_stack
*tem
= get_current_sequence ()->next
;
5562 set_first_insn (tem
->first
);
5563 set_last_insn (tem
->last
);
5564 get_current_sequence ()->next
= tem
->next
;
5566 memset (tem
, 0, sizeof (*tem
));
5567 tem
->next
= free_sequence_stack
;
5568 free_sequence_stack
= tem
;
5571 /* Return 1 if currently emitting into a sequence. */
5574 in_sequence_p (void)
5576 return get_current_sequence ()->next
!= 0;
5579 /* Put the various virtual registers into REGNO_REG_RTX. */
5582 init_virtual_regs (void)
5584 regno_reg_rtx
[VIRTUAL_INCOMING_ARGS_REGNUM
] = virtual_incoming_args_rtx
;
5585 regno_reg_rtx
[VIRTUAL_STACK_VARS_REGNUM
] = virtual_stack_vars_rtx
;
5586 regno_reg_rtx
[VIRTUAL_STACK_DYNAMIC_REGNUM
] = virtual_stack_dynamic_rtx
;
5587 regno_reg_rtx
[VIRTUAL_OUTGOING_ARGS_REGNUM
] = virtual_outgoing_args_rtx
;
5588 regno_reg_rtx
[VIRTUAL_CFA_REGNUM
] = virtual_cfa_rtx
;
5589 regno_reg_rtx
[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
]
5590 = virtual_preferred_stack_boundary_rtx
;
5594 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
5595 static rtx copy_insn_scratch_in
[MAX_RECOG_OPERANDS
];
5596 static rtx copy_insn_scratch_out
[MAX_RECOG_OPERANDS
];
5597 static int copy_insn_n_scratches
;
5599 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5600 copied an ASM_OPERANDS.
5601 In that case, it is the original input-operand vector. */
5602 static rtvec orig_asm_operands_vector
;
5604 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5605 copied an ASM_OPERANDS.
5606 In that case, it is the copied input-operand vector. */
5607 static rtvec copy_asm_operands_vector
;
5609 /* Likewise for the constraints vector. */
5610 static rtvec orig_asm_constraints_vector
;
5611 static rtvec copy_asm_constraints_vector
;
5613 /* Recursively create a new copy of an rtx for copy_insn.
5614 This function differs from copy_rtx in that it handles SCRATCHes and
5615 ASM_OPERANDs properly.
5616 Normally, this function is not used directly; use copy_insn as front end.
5617 However, you could first copy an insn pattern with copy_insn and then use
5618 this function afterwards to properly copy any REG_NOTEs containing
5622 copy_insn_1 (rtx orig
)
5627 const char *format_ptr
;
5632 code
= GET_CODE (orig
);
5646 /* Share clobbers of hard registers, but do not share pseudo reg
5647 clobbers or clobbers of hard registers that originated as pseudos.
5648 This is needed to allow safe register renaming. */
5649 if (REG_P (XEXP (orig
, 0))
5650 && HARD_REGISTER_NUM_P (REGNO (XEXP (orig
, 0)))
5651 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig
, 0))))
5656 for (i
= 0; i
< copy_insn_n_scratches
; i
++)
5657 if (copy_insn_scratch_in
[i
] == orig
)
5658 return copy_insn_scratch_out
[i
];
5662 if (shared_const_p (orig
))
5666 /* A MEM with a constant address is not sharable. The problem is that
5667 the constant address may need to be reloaded. If the mem is shared,
5668 then reloading one copy of this mem will cause all copies to appear
5669 to have been reloaded. */
5675 /* Copy the various flags, fields, and other information. We assume
5676 that all fields need copying, and then clear the fields that should
5677 not be copied. That is the sensible default behavior, and forces
5678 us to explicitly document why we are *not* copying a flag. */
5679 copy
= shallow_copy_rtx (orig
);
5681 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
5684 RTX_FLAG (copy
, jump
) = 0;
5685 RTX_FLAG (copy
, call
) = 0;
5686 RTX_FLAG (copy
, frame_related
) = 0;
5689 format_ptr
= GET_RTX_FORMAT (GET_CODE (copy
));
5691 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (copy
)); i
++)
5692 switch (*format_ptr
++)
5695 if (XEXP (orig
, i
) != NULL
)
5696 XEXP (copy
, i
) = copy_insn_1 (XEXP (orig
, i
));
5701 if (XVEC (orig
, i
) == orig_asm_constraints_vector
)
5702 XVEC (copy
, i
) = copy_asm_constraints_vector
;
5703 else if (XVEC (orig
, i
) == orig_asm_operands_vector
)
5704 XVEC (copy
, i
) = copy_asm_operands_vector
;
5705 else if (XVEC (orig
, i
) != NULL
)
5707 XVEC (copy
, i
) = rtvec_alloc (XVECLEN (orig
, i
));
5708 for (j
= 0; j
< XVECLEN (copy
, i
); j
++)
5709 XVECEXP (copy
, i
, j
) = copy_insn_1 (XVECEXP (orig
, i
, j
));
5721 /* These are left unchanged. */
5728 if (code
== SCRATCH
)
5730 i
= copy_insn_n_scratches
++;
5731 gcc_assert (i
< MAX_RECOG_OPERANDS
);
5732 copy_insn_scratch_in
[i
] = orig
;
5733 copy_insn_scratch_out
[i
] = copy
;
5735 else if (code
== ASM_OPERANDS
)
5737 orig_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (orig
);
5738 copy_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (copy
);
5739 orig_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig
);
5740 copy_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy
);
5746 /* Create a new copy of an rtx.
5747 This function differs from copy_rtx in that it handles SCRATCHes and
5748 ASM_OPERANDs properly.
5749 INSN doesn't really have to be a full INSN; it could be just the
5752 copy_insn (rtx insn
)
5754 copy_insn_n_scratches
= 0;
5755 orig_asm_operands_vector
= 0;
5756 orig_asm_constraints_vector
= 0;
5757 copy_asm_operands_vector
= 0;
5758 copy_asm_constraints_vector
= 0;
5759 return copy_insn_1 (insn
);
5762 /* Return a copy of INSN that can be used in a SEQUENCE delay slot,
5763 on that assumption that INSN itself remains in its original place. */
5766 copy_delay_slot_insn (rtx_insn
*insn
)
5768 /* Copy INSN with its rtx_code, all its notes, location etc. */
5769 insn
= as_a
<rtx_insn
*> (copy_rtx (insn
));
5770 INSN_UID (insn
) = cur_insn_uid
++;
5774 /* Initialize data structures and variables in this file
5775 before generating rtl for each function. */
5780 set_first_insn (NULL
);
5781 set_last_insn (NULL
);
5782 if (param_min_nondebug_insn_uid
)
5783 cur_insn_uid
= param_min_nondebug_insn_uid
;
5786 cur_debug_insn_uid
= 1;
5787 reg_rtx_no
= LAST_VIRTUAL_REGISTER
+ 1;
5788 first_label_num
= label_num
;
5789 get_current_sequence ()->next
= NULL
;
5791 /* Init the tables that describe all the pseudo regs. */
5793 crtl
->emit
.regno_pointer_align_length
= LAST_VIRTUAL_REGISTER
+ 101;
5795 crtl
->emit
.regno_pointer_align
5796 = XCNEWVEC (unsigned char, crtl
->emit
.regno_pointer_align_length
);
5799 = ggc_cleared_vec_alloc
<rtx
> (crtl
->emit
.regno_pointer_align_length
);
5801 /* Put copies of all the hard registers into regno_reg_rtx. */
5802 memcpy (regno_reg_rtx
,
5803 initial_regno_reg_rtx
,
5804 FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
5806 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
5807 init_virtual_regs ();
5809 /* Indicate that the virtual registers and stack locations are
5811 REG_POINTER (stack_pointer_rtx
) = 1;
5812 REG_POINTER (frame_pointer_rtx
) = 1;
5813 REG_POINTER (hard_frame_pointer_rtx
) = 1;
5814 REG_POINTER (arg_pointer_rtx
) = 1;
5816 REG_POINTER (virtual_incoming_args_rtx
) = 1;
5817 REG_POINTER (virtual_stack_vars_rtx
) = 1;
5818 REG_POINTER (virtual_stack_dynamic_rtx
) = 1;
5819 REG_POINTER (virtual_outgoing_args_rtx
) = 1;
5820 REG_POINTER (virtual_cfa_rtx
) = 1;
5822 #ifdef STACK_BOUNDARY
5823 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM
) = STACK_BOUNDARY
;
5824 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5825 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5826 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) = STACK_BOUNDARY
;
5828 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5829 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM
) = STACK_BOUNDARY
;
5830 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM
) = STACK_BOUNDARY
;
5831 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5833 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM
) = BITS_PER_WORD
;
5836 #ifdef INIT_EXPANDERS
5841 /* Return the value of element I of CONST_VECTOR X as a wide_int. */
5844 const_vector_int_elt (const_rtx x
, unsigned int i
)
5846 /* First handle elements that are directly encoded. */
5847 machine_mode elt_mode
= GET_MODE_INNER (GET_MODE (x
));
5848 if (i
< (unsigned int) XVECLEN (x
, 0))
5849 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, i
), elt_mode
);
5851 /* Identify the pattern that contains element I and work out the index of
5852 the last encoded element for that pattern. */
5853 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5854 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5855 unsigned int count
= i
/ npatterns
;
5856 unsigned int pattern
= i
% npatterns
;
5857 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5859 /* If there are no steps, the final encoded value is the right one. */
5860 if (!CONST_VECTOR_STEPPED_P (x
))
5861 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, final_i
), elt_mode
);
5863 /* Otherwise work out the value from the last two encoded elements. */
5864 rtx v1
= CONST_VECTOR_ENCODED_ELT (x
, final_i
- npatterns
);
5865 rtx v2
= CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5866 wide_int diff
= wi::sub (rtx_mode_t (v2
, elt_mode
),
5867 rtx_mode_t (v1
, elt_mode
));
5868 return wi::add (rtx_mode_t (v2
, elt_mode
), (count
- 2) * diff
);
5871 /* Return the value of element I of CONST_VECTOR X. */
5874 const_vector_elt (const_rtx x
, unsigned int i
)
5876 /* First handle elements that are directly encoded. */
5877 if (i
< (unsigned int) XVECLEN (x
, 0))
5878 return CONST_VECTOR_ENCODED_ELT (x
, i
);
5880 /* If there are no steps, the final encoded value is the right one. */
5881 if (!CONST_VECTOR_STEPPED_P (x
))
5883 /* Identify the pattern that contains element I and work out the index of
5884 the last encoded element for that pattern. */
5885 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5886 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5887 unsigned int pattern
= i
% npatterns
;
5888 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5889 return CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5892 /* Otherwise work out the value from the last two encoded elements. */
5893 return immed_wide_int_const (const_vector_int_elt (x
, i
),
5894 GET_MODE_INNER (GET_MODE (x
)));
5897 /* Return true if X is a valid element for a CONST_VECTOR of the given
5901 valid_for_const_vector_p (machine_mode
, rtx x
)
5903 return (CONST_SCALAR_INT_P (x
)
5904 || CONST_POLY_INT_P (x
)
5905 || CONST_DOUBLE_AS_FLOAT_P (x
)
5906 || CONST_FIXED_P (x
));
5909 /* Generate a vector constant of mode MODE in which every element has
5913 gen_const_vec_duplicate (machine_mode mode
, rtx elt
)
5915 rtx_vector_builder
builder (mode
, 1, 1);
5916 builder
.quick_push (elt
);
5917 return builder
.build ();
5920 /* Return a vector rtx of mode MODE in which every element has value X.
5921 The result will be a constant if X is constant. */
5924 gen_vec_duplicate (machine_mode mode
, rtx x
)
5926 if (valid_for_const_vector_p (mode
, x
))
5927 return gen_const_vec_duplicate (mode
, x
);
5928 return gen_rtx_VEC_DUPLICATE (mode
, x
);
5931 /* A subroutine of const_vec_series_p that handles the case in which:
5933 (GET_CODE (X) == CONST_VECTOR
5934 && CONST_VECTOR_NPATTERNS (X) == 1
5935 && !CONST_VECTOR_DUPLICATE_P (X))
5937 is known to hold. */
5940 const_vec_series_p_1 (const_rtx x
, rtx
*base_out
, rtx
*step_out
)
5942 /* Stepped sequences are only defined for integers, to avoid specifying
5943 rounding behavior. */
5944 if (GET_MODE_CLASS (GET_MODE (x
)) != MODE_VECTOR_INT
)
5947 /* A non-duplicated vector with two elements can always be seen as a
5948 series with a nonzero step. Longer vectors must have a stepped
5950 if (maybe_ne (CONST_VECTOR_NUNITS (x
), 2)
5951 && !CONST_VECTOR_STEPPED_P (x
))
5954 /* Calculate the step between the first and second elements. */
5955 scalar_mode inner
= GET_MODE_INNER (GET_MODE (x
));
5956 rtx base
= CONST_VECTOR_ELT (x
, 0);
5957 rtx step
= simplify_binary_operation (MINUS
, inner
,
5958 CONST_VECTOR_ENCODED_ELT (x
, 1), base
);
5959 if (rtx_equal_p (step
, CONST0_RTX (inner
)))
5962 /* If we have a stepped encoding, check that the step between the
5963 second and third elements is the same as STEP. */
5964 if (CONST_VECTOR_STEPPED_P (x
))
5966 rtx diff
= simplify_binary_operation (MINUS
, inner
,
5967 CONST_VECTOR_ENCODED_ELT (x
, 2),
5968 CONST_VECTOR_ENCODED_ELT (x
, 1));
5969 if (!rtx_equal_p (step
, diff
))
5978 /* Generate a vector constant of mode MODE in which element I has
5979 the value BASE + I * STEP. */
5982 gen_const_vec_series (machine_mode mode
, rtx base
, rtx step
)
5984 gcc_assert (valid_for_const_vector_p (mode
, base
)
5985 && valid_for_const_vector_p (mode
, step
));
5987 rtx_vector_builder
builder (mode
, 1, 3);
5988 builder
.quick_push (base
);
5989 for (int i
= 1; i
< 3; ++i
)
5990 builder
.quick_push (simplify_gen_binary (PLUS
, GET_MODE_INNER (mode
),
5991 builder
[i
- 1], step
));
5992 return builder
.build ();
5995 /* Generate a vector of mode MODE in which element I has the value
5996 BASE + I * STEP. The result will be a constant if BASE and STEP
5997 are both constants. */
6000 gen_vec_series (machine_mode mode
, rtx base
, rtx step
)
6002 if (step
== const0_rtx
)
6003 return gen_vec_duplicate (mode
, base
);
6004 if (valid_for_const_vector_p (mode
, base
)
6005 && valid_for_const_vector_p (mode
, step
))
6006 return gen_const_vec_series (mode
, base
, step
);
6007 return gen_rtx_VEC_SERIES (mode
, base
, step
);
6010 /* Generate a new vector constant for mode MODE and constant value
6014 gen_const_vector (machine_mode mode
, int constant
)
6016 machine_mode inner
= GET_MODE_INNER (mode
);
6018 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner
));
6020 rtx el
= const_tiny_rtx
[constant
][(int) inner
];
6023 return gen_const_vec_duplicate (mode
, el
);
6026 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
6027 all elements are zero, and the one vector when all elements are one. */
6029 gen_rtx_CONST_VECTOR (machine_mode mode
, rtvec v
)
6031 gcc_assert (known_eq (GET_MODE_NUNITS (mode
), GET_NUM_ELEM (v
)));
6033 /* If the values are all the same, check to see if we can use one of the
6034 standard constant vectors. */
6035 if (rtvec_all_equal_p (v
))
6036 return gen_const_vec_duplicate (mode
, RTVEC_ELT (v
, 0));
6038 unsigned int nunits
= GET_NUM_ELEM (v
);
6039 rtx_vector_builder
builder (mode
, nunits
, 1);
6040 for (unsigned int i
= 0; i
< nunits
; ++i
)
6041 builder
.quick_push (RTVEC_ELT (v
, i
));
6042 return builder
.build (v
);
6045 /* Initialise global register information required by all functions. */
6048 init_emit_regs (void)
6054 /* Reset register attributes */
6055 reg_attrs_htab
->empty ();
6057 /* We need reg_raw_mode, so initialize the modes now. */
6058 init_reg_modes_target ();
6060 /* Assign register numbers to the globally defined register rtx. */
6061 stack_pointer_rtx
= gen_raw_REG (Pmode
, STACK_POINTER_REGNUM
);
6062 frame_pointer_rtx
= gen_raw_REG (Pmode
, FRAME_POINTER_REGNUM
);
6063 hard_frame_pointer_rtx
= gen_raw_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
6064 arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
6065 virtual_incoming_args_rtx
=
6066 gen_raw_REG (Pmode
, VIRTUAL_INCOMING_ARGS_REGNUM
);
6067 virtual_stack_vars_rtx
=
6068 gen_raw_REG (Pmode
, VIRTUAL_STACK_VARS_REGNUM
);
6069 virtual_stack_dynamic_rtx
=
6070 gen_raw_REG (Pmode
, VIRTUAL_STACK_DYNAMIC_REGNUM
);
6071 virtual_outgoing_args_rtx
=
6072 gen_raw_REG (Pmode
, VIRTUAL_OUTGOING_ARGS_REGNUM
);
6073 virtual_cfa_rtx
= gen_raw_REG (Pmode
, VIRTUAL_CFA_REGNUM
);
6074 virtual_preferred_stack_boundary_rtx
=
6075 gen_raw_REG (Pmode
, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
);
6077 /* Initialize RTL for commonly used hard registers. These are
6078 copied into regno_reg_rtx as we begin to compile each function. */
6079 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6080 initial_regno_reg_rtx
[i
] = gen_raw_REG (reg_raw_mode
[i
], i
);
6082 #ifdef RETURN_ADDRESS_POINTER_REGNUM
6083 return_address_pointer_rtx
6084 = gen_raw_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
);
6087 pic_offset_table_rtx
= NULL_RTX
;
6088 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6089 pic_offset_table_rtx
= gen_raw_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
);
6091 for (i
= 0; i
< (int) MAX_MACHINE_MODE
; i
++)
6093 mode
= (machine_mode
) i
;
6094 attrs
= ggc_cleared_alloc
<mem_attrs
> ();
6095 attrs
->align
= BITS_PER_UNIT
;
6096 attrs
->addrspace
= ADDR_SPACE_GENERIC
;
6097 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
6099 attrs
->size_known_p
= true;
6100 attrs
->size
= GET_MODE_SIZE (mode
);
6101 if (STRICT_ALIGNMENT
)
6102 attrs
->align
= GET_MODE_ALIGNMENT (mode
);
6104 mode_mem_attrs
[i
] = attrs
;
6107 split_branch_probability
= profile_probability::uninitialized ();
6110 /* Initialize global machine_mode variables. */
6113 init_derived_machine_modes (void)
6115 opt_scalar_int_mode mode_iter
, opt_byte_mode
, opt_word_mode
;
6116 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_INT
)
6118 scalar_int_mode mode
= mode_iter
.require ();
6120 if (GET_MODE_BITSIZE (mode
) == BITS_PER_UNIT
6121 && !opt_byte_mode
.exists ())
6122 opt_byte_mode
= mode
;
6124 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
6125 && !opt_word_mode
.exists ())
6126 opt_word_mode
= mode
;
6129 byte_mode
= opt_byte_mode
.require ();
6130 word_mode
= opt_word_mode
.require ();
6131 ptr_mode
= as_a
<scalar_int_mode
>
6132 (mode_for_size (POINTER_SIZE
, GET_MODE_CLASS (Pmode
), 0).require ());
6135 /* Create some permanent unique rtl objects shared between all functions. */
6138 init_emit_once (void)
6142 scalar_float_mode double_mode
;
6143 opt_scalar_mode smode_iter
;
6145 /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
6146 CONST_FIXED, and memory attribute hash tables. */
6147 const_int_htab
= hash_table
<const_int_hasher
>::create_ggc (37);
6149 #if TARGET_SUPPORTS_WIDE_INT
6150 const_wide_int_htab
= hash_table
<const_wide_int_hasher
>::create_ggc (37);
6152 const_double_htab
= hash_table
<const_double_hasher
>::create_ggc (37);
6154 if (NUM_POLY_INT_COEFFS
> 1)
6155 const_poly_int_htab
= hash_table
<const_poly_int_hasher
>::create_ggc (37);
6157 const_fixed_htab
= hash_table
<const_fixed_hasher
>::create_ggc (37);
6159 reg_attrs_htab
= hash_table
<reg_attr_hasher
>::create_ggc (37);
6161 #ifdef INIT_EXPANDERS
6162 /* This is to initialize {init|mark|free}_machine_status before the first
6163 call to push_function_context_to. This is needed by the Chill front
6164 end which calls push_function_context_to before the first call to
6165 init_function_start. */
6169 /* Create the unique rtx's for certain rtx codes and operand values. */
6171 /* Process stack-limiting command-line options. */
6172 if (opt_fstack_limit_symbol_arg
!= NULL
)
6174 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (opt_fstack_limit_symbol_arg
));
6175 if (opt_fstack_limit_register_no
>= 0)
6176 stack_limit_rtx
= gen_rtx_REG (Pmode
, opt_fstack_limit_register_no
);
6178 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
6179 tries to use these variables. */
6180 for (i
= - MAX_SAVED_CONST_INT
; i
<= MAX_SAVED_CONST_INT
; i
++)
6181 const_int_rtx
[i
+ MAX_SAVED_CONST_INT
] =
6182 gen_rtx_raw_CONST_INT (VOIDmode
, (HOST_WIDE_INT
) i
);
6184 if (STORE_FLAG_VALUE
>= - MAX_SAVED_CONST_INT
6185 && STORE_FLAG_VALUE
<= MAX_SAVED_CONST_INT
)
6186 const_true_rtx
= const_int_rtx
[STORE_FLAG_VALUE
+ MAX_SAVED_CONST_INT
];
6188 const_true_rtx
= gen_rtx_CONST_INT (VOIDmode
, STORE_FLAG_VALUE
);
6190 double_mode
= float_mode_for_size (DOUBLE_TYPE_SIZE
).require ();
6192 real_from_integer (&dconst0
, double_mode
, 0, SIGNED
);
6193 real_from_integer (&dconst1
, double_mode
, 1, SIGNED
);
6194 real_from_integer (&dconst2
, double_mode
, 2, SIGNED
);
6199 dconsthalf
= dconst1
;
6200 SET_REAL_EXP (&dconsthalf
, REAL_EXP (&dconsthalf
) - 1);
6202 for (i
= 0; i
< 3; i
++)
6204 const REAL_VALUE_TYPE
*const r
=
6205 (i
== 0 ? &dconst0
: i
== 1 ? &dconst1
: &dconst2
);
6207 FOR_EACH_MODE_IN_CLASS (mode
, MODE_FLOAT
)
6208 const_tiny_rtx
[i
][(int) mode
] =
6209 const_double_from_real_value (*r
, mode
);
6211 FOR_EACH_MODE_IN_CLASS (mode
, MODE_DECIMAL_FLOAT
)
6212 const_tiny_rtx
[i
][(int) mode
] =
6213 const_double_from_real_value (*r
, mode
);
6215 const_tiny_rtx
[i
][(int) VOIDmode
] = GEN_INT (i
);
6217 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6218 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6220 for (mode
= MIN_MODE_PARTIAL_INT
;
6221 mode
<= MAX_MODE_PARTIAL_INT
;
6222 mode
= (machine_mode
)((int)(mode
) + 1))
6223 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6226 const_tiny_rtx
[3][(int) VOIDmode
] = constm1_rtx
;
6228 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6229 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6231 /* For BImode, 1 and -1 are unsigned and signed interpretations
6232 of the same value. */
6233 const_tiny_rtx
[0][(int) BImode
] = const0_rtx
;
6234 const_tiny_rtx
[1][(int) BImode
] = const_true_rtx
;
6235 const_tiny_rtx
[3][(int) BImode
] = const_true_rtx
;
6237 for (mode
= MIN_MODE_PARTIAL_INT
;
6238 mode
<= MAX_MODE_PARTIAL_INT
;
6239 mode
= (machine_mode
)((int)(mode
) + 1))
6240 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6242 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_INT
)
6244 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6245 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6248 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_FLOAT
)
6250 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6251 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6254 /* As for BImode, "all 1" and "all -1" are unsigned and signed
6255 interpretations of the same value. */
6256 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_BOOL
)
6258 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6259 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6260 const_tiny_rtx
[1][(int) mode
] = const_tiny_rtx
[3][(int) mode
];
6263 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_INT
)
6265 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6266 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6267 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6270 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FLOAT
)
6272 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6273 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6276 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_FRACT
)
6278 scalar_mode smode
= smode_iter
.require ();
6279 FCONST0 (smode
).data
.high
= 0;
6280 FCONST0 (smode
).data
.low
= 0;
6281 FCONST0 (smode
).mode
= smode
;
6282 const_tiny_rtx
[0][(int) smode
]
6283 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6286 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UFRACT
)
6288 scalar_mode smode
= smode_iter
.require ();
6289 FCONST0 (smode
).data
.high
= 0;
6290 FCONST0 (smode
).data
.low
= 0;
6291 FCONST0 (smode
).mode
= smode
;
6292 const_tiny_rtx
[0][(int) smode
]
6293 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6296 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_ACCUM
)
6298 scalar_mode smode
= smode_iter
.require ();
6299 FCONST0 (smode
).data
.high
= 0;
6300 FCONST0 (smode
).data
.low
= 0;
6301 FCONST0 (smode
).mode
= smode
;
6302 const_tiny_rtx
[0][(int) smode
]
6303 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6305 /* We store the value 1. */
6306 FCONST1 (smode
).data
.high
= 0;
6307 FCONST1 (smode
).data
.low
= 0;
6308 FCONST1 (smode
).mode
= smode
;
6309 FCONST1 (smode
).data
6310 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6311 HOST_BITS_PER_DOUBLE_INT
,
6312 SIGNED_FIXED_POINT_MODE_P (smode
));
6313 const_tiny_rtx
[1][(int) smode
]
6314 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6317 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UACCUM
)
6319 scalar_mode smode
= smode_iter
.require ();
6320 FCONST0 (smode
).data
.high
= 0;
6321 FCONST0 (smode
).data
.low
= 0;
6322 FCONST0 (smode
).mode
= smode
;
6323 const_tiny_rtx
[0][(int) smode
]
6324 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6326 /* We store the value 1. */
6327 FCONST1 (smode
).data
.high
= 0;
6328 FCONST1 (smode
).data
.low
= 0;
6329 FCONST1 (smode
).mode
= smode
;
6330 FCONST1 (smode
).data
6331 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6332 HOST_BITS_PER_DOUBLE_INT
,
6333 SIGNED_FIXED_POINT_MODE_P (smode
));
6334 const_tiny_rtx
[1][(int) smode
]
6335 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6338 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FRACT
)
6340 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6343 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UFRACT
)
6345 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6348 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_ACCUM
)
6350 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6351 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6354 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UACCUM
)
6356 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6357 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6360 for (i
= (int) CCmode
; i
< (int) MAX_MACHINE_MODE
; ++i
)
6361 if (GET_MODE_CLASS ((machine_mode
) i
) == MODE_CC
)
6362 const_tiny_rtx
[0][i
] = const0_rtx
;
6364 pc_rtx
= gen_rtx_fmt_ (PC
, VOIDmode
);
6365 ret_rtx
= gen_rtx_fmt_ (RETURN
, VOIDmode
);
6366 simple_return_rtx
= gen_rtx_fmt_ (SIMPLE_RETURN
, VOIDmode
);
6367 invalid_insn_rtx
= gen_rtx_INSN (VOIDmode
,
6371 /*pattern=*/NULL_RTX
,
6374 /*reg_notes=*/NULL_RTX
);
6377 /* Produce exact duplicate of insn INSN after AFTER.
6378 Care updating of libcall regions if present. */
6381 emit_copy_of_insn_after (rtx_insn
*insn
, rtx_insn
*after
)
6386 switch (GET_CODE (insn
))
6389 new_rtx
= emit_insn_after (copy_insn (PATTERN (insn
)), after
);
6393 new_rtx
= emit_jump_insn_after (copy_insn (PATTERN (insn
)), after
);
6394 CROSSING_JUMP_P (new_rtx
) = CROSSING_JUMP_P (insn
);
6398 new_rtx
= emit_debug_insn_after (copy_insn (PATTERN (insn
)), after
);
6402 new_rtx
= emit_call_insn_after (copy_insn (PATTERN (insn
)), after
);
6403 if (CALL_INSN_FUNCTION_USAGE (insn
))
6404 CALL_INSN_FUNCTION_USAGE (new_rtx
)
6405 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn
));
6406 SIBLING_CALL_P (new_rtx
) = SIBLING_CALL_P (insn
);
6407 RTL_CONST_CALL_P (new_rtx
) = RTL_CONST_CALL_P (insn
);
6408 RTL_PURE_CALL_P (new_rtx
) = RTL_PURE_CALL_P (insn
);
6409 RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx
)
6410 = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn
);
6417 /* Update LABEL_NUSES. */
6418 mark_jump_label (PATTERN (new_rtx
), new_rtx
, 0);
6420 INSN_LOCATION (new_rtx
) = INSN_LOCATION (insn
);
6422 /* If the old insn is frame related, then so is the new one. This is
6423 primarily needed for IA-64 unwind info which marks epilogue insns,
6424 which may be duplicated by the basic block reordering code. */
6425 RTX_FRAME_RELATED_P (new_rtx
) = RTX_FRAME_RELATED_P (insn
);
6427 /* Locate the end of existing REG_NOTES in NEW_RTX. */
6428 rtx
*ptail
= ®_NOTES (new_rtx
);
6429 while (*ptail
!= NULL_RTX
)
6430 ptail
= &XEXP (*ptail
, 1);
6432 /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label
6433 will make them. REG_LABEL_TARGETs are created there too, but are
6434 supposed to be sticky, so we copy them. */
6435 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
6436 if (REG_NOTE_KIND (link
) != REG_LABEL_OPERAND
)
6438 *ptail
= duplicate_reg_note (link
);
6439 ptail
= &XEXP (*ptail
, 1);
6442 INSN_CODE (new_rtx
) = INSN_CODE (insn
);
6446 static GTY((deletable
)) rtx hard_reg_clobbers
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
6448 gen_hard_reg_clobber (machine_mode mode
, unsigned int regno
)
6450 if (hard_reg_clobbers
[mode
][regno
])
6451 return hard_reg_clobbers
[mode
][regno
];
6453 return (hard_reg_clobbers
[mode
][regno
] =
6454 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (mode
, regno
)));
6457 location_t prologue_location
;
6458 location_t epilogue_location
;
6460 /* Hold current location information and last location information, so the
6461 datastructures are built lazily only when some instructions in given
6462 place are needed. */
6463 static location_t curr_location
;
6465 /* Allocate insn location datastructure. */
6467 insn_locations_init (void)
6469 prologue_location
= epilogue_location
= 0;
6470 curr_location
= UNKNOWN_LOCATION
;
6473 /* At the end of emit stage, clear current location. */
6475 insn_locations_finalize (void)
6477 epilogue_location
= curr_location
;
6478 curr_location
= UNKNOWN_LOCATION
;
6481 /* Set current location. */
6483 set_curr_insn_location (location_t location
)
6485 curr_location
= location
;
6488 /* Get current location. */
6490 curr_insn_location (void)
6492 return curr_location
;
6495 /* Set the location of the insn chain starting at INSN to LOC. */
6497 set_insn_locations (rtx_insn
*insn
, location_t loc
)
6502 INSN_LOCATION (insn
) = loc
;
6503 insn
= NEXT_INSN (insn
);
6507 /* Return lexical scope block insn belongs to. */
6509 insn_scope (const rtx_insn
*insn
)
6511 return LOCATION_BLOCK (INSN_LOCATION (insn
));
6514 /* Return line number of the statement that produced this insn. */
6516 insn_line (const rtx_insn
*insn
)
6518 return LOCATION_LINE (INSN_LOCATION (insn
));
6521 /* Return source file of the statement that produced this insn. */
6523 insn_file (const rtx_insn
*insn
)
6525 return LOCATION_FILE (INSN_LOCATION (insn
));
6528 /* Return expanded location of the statement that produced this insn. */
6530 insn_location (const rtx_insn
*insn
)
6532 return expand_location (INSN_LOCATION (insn
));
6535 /* Return true if memory model MODEL requires a pre-operation (release-style)
6536 barrier or a post-operation (acquire-style) barrier. While not universal,
6537 this function matches behavior of several targets. */
6540 need_atomic_barrier_p (enum memmodel model
, bool pre
)
6542 switch (model
& MEMMODEL_BASE_MASK
)
6544 case MEMMODEL_RELAXED
:
6545 case MEMMODEL_CONSUME
:
6547 case MEMMODEL_RELEASE
:
6549 case MEMMODEL_ACQUIRE
:
6551 case MEMMODEL_ACQ_REL
:
6552 case MEMMODEL_SEQ_CST
:
6559 /* Return a constant shift amount for shifting a value of mode MODE
6563 gen_int_shift_amount (machine_mode
, poly_int64 value
)
6565 /* Use a 64-bit mode, to avoid any truncation.
6567 ??? Perhaps this should be automatically derived from the .md files
6568 instead, or perhaps have a target hook. */
6569 scalar_int_mode shift_mode
= (BITS_PER_UNIT
== 8
6571 : int_mode_for_size (64, 0).require ());
6572 return gen_int_mode (value
, shift_mode
);
6575 /* Initialize fields of rtl_data related to stack alignment. */
6578 rtl_data::init_stack_alignment ()
6580 stack_alignment_needed
= STACK_BOUNDARY
;
6581 max_used_stack_slot_alignment
= STACK_BOUNDARY
;
6582 stack_alignment_estimated
= 0;
6583 preferred_stack_boundary
= STACK_BOUNDARY
;
6587 #include "gt-emit-rtl.h"