| blob | 5883f4ba35adefba7f1692f953c903e3093f2e32 |
1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
29 ;;-
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
55 ;;
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
57 ;; info.
59 ;;- Immediate integer operand constraints:
60 ;;- 'I' 1 .. 8
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
63 ;;- 'L' -8 .. -1
64 ;;- 'M' all integers EXCEPT -256 .. 255
65 ;;- 'N' 24 .. 31
66 ;;- 'O' 16
67 ;;- 'P' 8 .. 15
69 ;;- Assembler specs:
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TARGET_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
93 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
94 ;;- you can make these instructions the default.
96 ;;- These new instructions aren't directly in the md. They are brought
97 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
98 ;;- than "".
100 ;;- Information about 68060 port.
102 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
103 ;;- be emulated in software by the OS. It is faster to avoid these
104 ;;- instructions and issue a library call rather than trapping into
105 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
106 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
107 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
109 ;;- Some of these insn's are composites of several m68000 op codes.
110 ;;- The assembler (or final @@??) insures that the appropriate one is
111 ;;- selected.
113 ;; UNSPEC usage:
115 (define_constants
116 [(UNSPEC_SIN 1)
117 (UNSPEC_COS 2)
118 ])
120 ;; UNSPEC_VOLATILE usage:
122 (define_constants
123 [(UNSPECV_BLOCKAGE 0)
124 ])
125 \f
126 (define_insn ""
127 [(set (match_operand:DF 0 "push_operand" "=m")
128 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
129 ""
130 "*
131 {
132 if (FP_REG_P (operands[1]))
133 return \"fmove%.d %f1,%0\";
134 return output_move_double (operands);
135 }")
137 (define_insn "pushdi"
138 [(set (match_operand:DI 0 "push_operand" "=m")
139 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
140 ""
141 "*
142 {
143 return output_move_double (operands);
144 }")
145 \f
146 ;; We don't want to allow a constant operand for test insns because
147 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
148 ;; be folded while optimizing anyway.
150 (define_expand "tstdi"
151 [(parallel [(set (cc0)
152 (match_operand:DI 0 "nonimmediate_operand" ""))
153 (clobber (match_scratch:SI 1 ""))
154 (clobber (match_scratch:DI 2 ""))])]
155 ""
156 "m68k_last_compare_had_fp_operands = 0;")
158 (define_insn ""
159 [(set (cc0)
160 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
161 (clobber (match_scratch:SI 1 "=X,d"))
162 (clobber (match_scratch:DI 2 "=d,X"))]
163 ""
164 "*
165 {
166 if (which_alternative == 0)
167 {
168 rtx xoperands[2];
170 xoperands[0] = operands[2];
171 xoperands[1] = operands[0];
172 output_move_double (xoperands);
173 cc_status.flags |= CC_REVERSED;
174 return \"neg%.l %R2\;negx%.l %2\";
175 }
176 if (find_reg_note (insn, REG_DEAD, operands[0]))
177 {
178 cc_status.flags |= CC_REVERSED;
179 return \"neg%.l %R0\;negx%.l %0\";
180 }
181 else
182 /*
183 ** 'sub' clears %1, and also clears the X cc bit
184 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
185 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
186 */
187 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
188 }")
190 (define_expand "tstsi"
191 [(set (cc0)
192 (match_operand:SI 0 "nonimmediate_operand" ""))]
193 ""
194 "m68k_last_compare_had_fp_operands = 0;")
196 (define_insn ""
197 [(set (cc0)
198 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
199 ""
200 "*
201 {
202 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
203 return \"tst%.l %0\";
204 /* If you think that the 68020 does not support tstl a0,
205 reread page B-167 of the 68020 manual more carefully. */
206 /* On an address reg, cmpw may replace cmpl. */
207 #ifdef SGS_CMP_ORDER
208 return \"cmp%.w %0,%#0\";
209 #else
210 return \"cmp%.w %#0,%0\";
211 #endif
212 }")
214 ;; This can't use an address register, because comparisons
215 ;; with address registers as second operand always test the whole word.
216 (define_expand "tsthi"
217 [(set (cc0)
218 (match_operand:HI 0 "nonimmediate_operand" ""))]
219 ""
220 "m68k_last_compare_had_fp_operands = 0;")
222 (define_insn ""
223 [(set (cc0)
224 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
225 ""
226 "tst%.w %0")
228 (define_expand "tstqi"
229 [(set (cc0)
230 (match_operand:QI 0 "nonimmediate_operand" ""))]
231 ""
232 "m68k_last_compare_had_fp_operands = 0;")
234 (define_insn ""
235 [(set (cc0)
236 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
237 ""
238 "tst%.b %0")
240 (define_expand "tstsf"
241 [(set (cc0)
242 (match_operand:SF 0 "general_operand" ""))]
243 "TARGET_68881"
244 "
245 {
246 m68k_last_compare_had_fp_operands = 1;
247 }")
249 (define_insn ""
250 [(set (cc0)
251 (match_operand:SF 0 "general_operand" "fdm"))]
252 "TARGET_68881"
253 "*
254 {
255 cc_status.flags = CC_IN_68881;
256 if (FP_REG_P (operands[0]))
257 return \"ftst%.x %0\";
258 return \"ftst%.s %0\";
259 }")
261 (define_expand "tstdf"
262 [(set (cc0)
263 (match_operand:DF 0 "general_operand" ""))]
264 "TARGET_68881"
265 "
266 {
267 m68k_last_compare_had_fp_operands = 1;
268 }")
270 (define_insn ""
271 [(set (cc0)
272 (match_operand:DF 0 "general_operand" "fm"))]
273 "TARGET_68881"
274 "*
275 {
276 cc_status.flags = CC_IN_68881;
277 if (FP_REG_P (operands[0]))
278 return \"ftst%.x %0\";
279 return \"ftst%.d %0\";
280 }")
281 \f
282 ;; compare instructions.
284 (define_expand "cmpdi"
285 [(parallel
286 [(set (cc0)
287 (compare (match_operand:DI 0 "nonimmediate_operand" "")
288 (match_operand:DI 1 "general_operand" "")))
289 (clobber (match_dup 2))])]
290 ""
291 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
293 (define_insn ""
294 [(set (cc0)
295 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
296 (match_operand:DI 2 "general_operand" "d,0")))
297 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
298 ""
299 "*
300 {
301 if (rtx_equal_p (operands[0], operands[1]))
302 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
303 else
304 {
305 cc_status.flags |= CC_REVERSED;
306 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
307 }
308 }")
310 ;; This is the second "hook" for PIC code (in addition to movsi). See
311 ;; comment of movsi for a description of PIC handling.
312 (define_expand "cmpsi"
313 [(set (cc0)
314 (compare (match_operand:SI 0 "nonimmediate_operand" "")
315 (match_operand:SI 1 "general_operand" "")))]
316 ""
317 "
318 {
319 m68k_last_compare_had_fp_operands = 0;
320 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
321 {
322 /* The source is an address which requires PIC relocation.
323 Call legitimize_pic_address with the source, mode, and a relocation
324 register (a new pseudo, or the final destination if reload_in_progress
325 is set). Then fall through normally */
326 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
327 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
328 }
329 }")
331 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
332 (define_insn ""
333 [(set (cc0)
334 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
335 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
336 "!TARGET_COLDFIRE"
337 "*
338 {
339 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
340 #ifdef SGS_CMP_ORDER
341 return \"cmpm%.l %0,%1\";
342 #else
343 return \"cmpm%.l %1,%0\";
344 #endif
345 if (REG_P (operands[1])
346 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
347 { cc_status.flags |= CC_REVERSED;
348 #ifdef SGS_CMP_ORDER
349 return \"cmp%.l %d1,%d0\";
350 #else
351 return \"cmp%.l %d0,%d1\";
352 #endif
353 }
354 if (ADDRESS_REG_P (operands[0])
355 && GET_CODE (operands[1]) == CONST_INT
356 && INTVAL (operands[1]) < 0x8000
357 && INTVAL (operands[1]) >= -0x8000)
358 {
359 #ifdef SGS_CMP_ORDER
360 return \"cmp%.w %0,%1\";
361 #else
362 return \"cmp%.w %1,%0\";
363 #endif
364 }
365 #ifdef SGS_CMP_ORDER
366 return \"cmp%.l %d0,%d1\";
367 #else
368 return \"cmp%.l %d1,%d0\";
369 #endif
370 }")
372 (define_insn ""
373 [(set (cc0)
374 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
375 (match_operand:SI 1 "general_operand" "r,mrKs")))]
376 "TARGET_COLDFIRE"
377 "*
378 {
379 if (REG_P (operands[1])
380 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
381 { cc_status.flags |= CC_REVERSED;
382 #ifdef SGS_CMP_ORDER
383 return \"cmp%.l %d1,%d0\";
384 #else
385 return \"cmp%.l %d0,%d1\";
386 #endif
387 }
388 #ifdef SGS_CMP_ORDER
389 return \"cmp%.l %d0,%d1\";
390 #else
391 return \"cmp%.l %d1,%d0\";
392 #endif
393 }")
395 (define_expand "cmphi"
396 [(set (cc0)
397 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
398 (match_operand:HI 1 "general_src_operand" "")))]
399 "!TARGET_COLDFIRE"
400 "m68k_last_compare_had_fp_operands = 0;")
402 (define_insn ""
403 [(set (cc0)
404 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
405 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
406 "!TARGET_COLDFIRE"
407 "*
408 {
409 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
410 #ifdef SGS_CMP_ORDER
411 return \"cmpm%.w %0,%1\";
412 #else
413 return \"cmpm%.w %1,%0\";
414 #endif
415 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
416 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
417 { cc_status.flags |= CC_REVERSED;
418 #ifdef SGS_CMP_ORDER
419 return \"cmp%.w %d1,%d0\";
420 #else
421 return \"cmp%.w %d0,%d1\";
422 #endif
423 }
424 #ifdef SGS_CMP_ORDER
425 return \"cmp%.w %d0,%d1\";
426 #else
427 return \"cmp%.w %d1,%d0\";
428 #endif
429 }")
431 (define_expand "cmpqi"
432 [(set (cc0)
433 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
434 (match_operand:QI 1 "general_src_operand" "")))]
435 "!TARGET_COLDFIRE"
436 "m68k_last_compare_had_fp_operands = 0;")
438 (define_insn ""
439 [(set (cc0)
440 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
441 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
442 "!TARGET_COLDFIRE"
443 "*
444 {
445 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
446 #ifdef SGS_CMP_ORDER
447 return \"cmpm%.b %0,%1\";
448 #else
449 return \"cmpm%.b %1,%0\";
450 #endif
451 if (REG_P (operands[1])
452 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
453 { cc_status.flags |= CC_REVERSED;
454 #ifdef SGS_CMP_ORDER
455 return \"cmp%.b %d1,%d0\";
456 #else
457 return \"cmp%.b %d0,%d1\";
458 #endif
459 }
460 #ifdef SGS_CMP_ORDER
461 return \"cmp%.b %d0,%d1\";
462 #else
463 return \"cmp%.b %d1,%d0\";
464 #endif
465 }")
467 (define_expand "cmpdf"
468 [(set (cc0)
469 (compare (match_operand:DF 0 "general_operand" "")
470 (match_operand:DF 1 "general_operand" "")))]
471 "TARGET_68881"
472 "
473 {
474 m68k_last_compare_had_fp_operands = 1;
475 }")
477 (define_insn ""
478 [(set (cc0)
479 (compare (match_operand:DF 0 "general_operand" "f,mG")
480 (match_operand:DF 1 "general_operand" "fmG,f")))]
481 "TARGET_68881"
482 "*
483 {
484 cc_status.flags = CC_IN_68881;
485 #ifdef SGS_CMP_ORDER
486 if (REG_P (operands[0]))
487 {
488 if (REG_P (operands[1]))
489 return \"fcmp%.x %0,%1\";
490 else
491 return \"fcmp%.d %0,%f1\";
492 }
493 cc_status.flags |= CC_REVERSED;
494 return \"fcmp%.d %1,%f0\";
495 #else
496 if (REG_P (operands[0]))
497 {
498 if (REG_P (operands[1]))
499 return \"fcmp%.x %1,%0\";
500 else
501 return \"fcmp%.d %f1,%0\";
502 }
503 cc_status.flags |= CC_REVERSED;
504 return \"fcmp%.d %f0,%1\";
505 #endif
506 }")
508 (define_expand "cmpsf"
509 [(set (cc0)
510 (compare (match_operand:SF 0 "general_operand" "")
511 (match_operand:SF 1 "general_operand" "")))]
512 "TARGET_68881"
513 "
514 {
515 m68k_last_compare_had_fp_operands = 1;
516 }")
518 (define_insn ""
519 [(set (cc0)
520 (compare (match_operand:SF 0 "general_operand" "f,mdG")
521 (match_operand:SF 1 "general_operand" "fmdG,f")))]
522 "TARGET_68881"
523 "*
524 {
525 cc_status.flags = CC_IN_68881;
526 #ifdef SGS_CMP_ORDER
527 if (FP_REG_P (operands[0]))
528 {
529 if (FP_REG_P (operands[1]))
530 return \"fcmp%.x %0,%1\";
531 else
532 return \"fcmp%.s %0,%f1\";
533 }
534 cc_status.flags |= CC_REVERSED;
535 return \"fcmp%.s %1,%f0\";
536 #else
537 if (FP_REG_P (operands[0]))
538 {
539 if (FP_REG_P (operands[1]))
540 return \"fcmp%.x %1,%0\";
541 else
542 return \"fcmp%.s %f1,%0\";
543 }
544 cc_status.flags |= CC_REVERSED;
545 return \"fcmp%.s %f0,%1\";
546 #endif
547 }")
548 \f
549 ;; Recognizers for btst instructions.
551 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
552 ;; specified as a constant, so we must disable all patterns that may extract
553 ;; from a MEM at a constant bit position if we can't use this as a constraint.
555 (define_insn ""
556 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
557 (const_int 1)
558 (minus:SI (const_int 7)
559 (match_operand:SI 1 "general_operand" "di"))))]
560 "!TARGET_COLDFIRE"
561 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
563 ;; This is the same as the above pattern except for the constraints. The 'i'
564 ;; has been deleted.
566 (define_insn ""
567 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
568 (const_int 1)
569 (minus:SI (const_int 7)
570 (match_operand:SI 1 "general_operand" "d"))))]
571 "TARGET_COLDFIRE"
572 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
574 (define_insn ""
575 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
576 (const_int 1)
577 (minus:SI (const_int 31)
578 (match_operand:SI 1 "general_operand" "di"))))]
579 ""
580 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
582 ;; The following two patterns are like the previous two
583 ;; except that they use the fact that bit-number operands
584 ;; are automatically masked to 3 or 5 bits.
586 (define_insn ""
587 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
588 (const_int 1)
589 (minus:SI (const_int 7)
590 (and:SI
591 (match_operand:SI 1 "register_operand" "d")
592 (const_int 7)))))]
593 ""
594 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
596 (define_insn ""
597 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
598 (const_int 1)
599 (minus:SI (const_int 31)
600 (and:SI
601 (match_operand:SI 1 "register_operand" "d")
602 (const_int 31)))))]
603 ""
604 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
606 ;; Nonoffsettable mem refs are ok in this one pattern
607 ;; since we don't try to adjust them.
608 (define_insn ""
609 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
610 (const_int 1)
611 (match_operand:SI 1 "const_int_operand" "n")))]
612 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
613 "*
614 {
615 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
616 return output_btst (operands, operands[1], operands[0], insn, 7);
617 }")
619 (define_insn ""
620 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
621 (const_int 1)
622 (match_operand:SI 1 "const_int_operand" "n")))]
623 "!TARGET_COLDFIRE"
624 "*
625 {
626 if (GET_CODE (operands[0]) == MEM)
627 {
628 operands[0] = adjust_address (operands[0], QImode,
629 INTVAL (operands[1]) / 8);
630 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
631 return output_btst (operands, operands[1], operands[0], insn, 7);
632 }
633 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
634 return output_btst (operands, operands[1], operands[0], insn, 31);
635 }")
637 ;; This is the same as the above pattern except for the constraints.
638 ;; The 'o' has been replaced with 'Q'.
640 (define_insn ""
641 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
642 (const_int 1)
643 (match_operand:SI 1 "const_int_operand" "n")))]
644 "TARGET_COLDFIRE"
645 "*
646 {
647 if (GET_CODE (operands[0]) == MEM)
648 {
649 operands[0] = adjust_address (operands[0], QImode,
650 INTVAL (operands[1]) / 8);
651 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
652 return output_btst (operands, operands[1], operands[0], insn, 7);
653 }
654 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
655 return output_btst (operands, operands[1], operands[0], insn, 31);
656 }")
658 \f
659 ;; move instructions
661 ;; A special case in which it is not desirable
662 ;; to reload the constant into a data register.
663 (define_insn "pushexthisi_const"
664 [(set (match_operand:SI 0 "push_operand" "=m")
665 (match_operand:SI 1 "const_int_operand" "J"))]
666 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
667 "*
668 {
669 if (operands[1] == const0_rtx)
670 return \"clr%.l %0\";
671 return \"pea %a1\";
672 }")
674 ;This is never used.
675 ;(define_insn "swapsi"
676 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
677 ; (match_operand:SI 1 "general_operand" "+r"))
678 ; (set (match_dup 1) (match_dup 0))]
679 ; ""
680 ; "exg %1,%0")
682 ;; Special case of fullword move when source is zero.
683 ;; The reason this is special is to avoid loading a zero
684 ;; into a data reg with moveq in order to store it elsewhere.
686 (define_insn "movsi_const0"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
688 (const_int 0))]
689 ;; clr insns on 68000 read before writing.
690 ;; This isn't so on the 68010, but we have no TARGET_68010.
691 "((TARGET_68020 || TARGET_COLDFIRE)
692 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
693 "*
694 {
695 if (ADDRESS_REG_P (operands[0]))
696 {
697 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
698 if (!TARGET_68040 && !TARGET_68060)
699 return \"sub%.l %0,%0\";
700 else
701 {
702 #ifdef MOTOROLA
703 #ifdef SGS
704 /* Many SGS assemblers croak on size specifiers for constants. */
705 return \"lea 0,%0\";
706 #else
707 return \"lea 0.w,%0\";
708 #endif
709 #else
710 return \"lea 0:w,%0\";
711 #endif
712 }
713 }
714 /* moveq is faster on the 68000. */
715 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
716 return \"moveq %#0,%0\";
717 return \"clr%.l %0\";
718 }")
720 ;; General case of fullword move.
721 ;;
722 ;; This is the main "hook" for PIC code. When generating
723 ;; PIC, movsi is responsible for determining when the source address
724 ;; needs PIC relocation and appropriately calling legitimize_pic_address
725 ;; to perform the actual relocation.
726 ;;
727 ;; In both the PIC and non-PIC cases the patterns generated will
728 ;; matched by the next define_insn.
729 (define_expand "movsi"
730 [(set (match_operand:SI 0 "nonimmediate_operand" "")
731 (match_operand:SI 1 "general_operand" ""))]
732 ""
733 "
734 {
735 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
736 {
737 /* The source is an address which requires PIC relocation.
738 Call legitimize_pic_address with the source, mode, and a relocation
739 register (a new pseudo, or the final destination if reload_in_progress
740 is set). Then fall through normally */
741 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
742 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
743 }
744 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
745 {
746 /* Don't allow writes to memory except via a register;
747 the m68k doesn't consider PC-relative addresses to be writable. */
748 if (symbolic_operand (operands[0], SImode))
749 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
750 else if (GET_CODE (operands[0]) == MEM
751 && symbolic_operand (XEXP (operands[0], 0), SImode))
752 operands[0] = gen_rtx (MEM, SImode,
753 force_reg (SImode, XEXP (operands[0], 0)));
754 }
755 }")
757 ;; General case of fullword move. The register constraints
758 ;; force integer constants in range for a moveq to be reloaded
759 ;; if they are headed for memory.
760 (define_insn ""
761 ;; Notes: make sure no alternative allows g vs g.
762 ;; We don't allow f-regs since fixed point cannot go in them.
763 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
764 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
766 "!TARGET_COLDFIRE"
767 "*
768 {
769 return output_move_simode (operands);
770 }")
772 (define_insn ""
773 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
774 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
775 "TARGET_COLDFIRE"
776 "* return output_move_simode (operands);")
778 ;; Special case of fullword move, where we need to get a non-GOT PIC
779 ;; reference into an address register.
780 (define_insn ""
781 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
782 (match_operand:SI 1 "pcrel_address" ""))]
783 "TARGET_PCREL"
784 "*
785 {
786 if (push_operand (operands[0], SImode))
787 return \"pea %a1\";
788 return \"lea %a1,%0\";
789 }")
791 (define_expand "movhi"
792 [(set (match_operand:HI 0 "nonimmediate_operand" "")
793 (match_operand:HI 1 "general_operand" ""))]
794 ""
795 "")
797 (define_insn ""
798 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
799 (match_operand:HI 1 "general_src_operand" "gS"))]
800 "!TARGET_COLDFIRE"
801 "* return output_move_himode (operands);")
803 (define_insn ""
804 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
805 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
806 "TARGET_COLDFIRE"
807 "* return output_move_himode (operands);")
809 (define_expand "movstricthi"
810 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
811 (match_operand:HI 1 "general_src_operand" ""))]
812 ""
813 "")
815 (define_insn ""
816 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
817 (match_operand:HI 1 "general_src_operand" "rmSn"))]
818 "!TARGET_COLDFIRE"
819 "* return output_move_stricthi (operands);")
821 (define_insn ""
822 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
823 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
824 "TARGET_COLDFIRE"
825 "* return output_move_stricthi (operands);")
827 (define_expand "movqi"
828 [(set (match_operand:QI 0 "nonimmediate_operand" "")
829 (match_operand:QI 1 "general_src_operand" ""))]
830 ""
831 "")
833 (define_insn ""
834 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
835 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
836 "!TARGET_COLDFIRE"
837 "* return output_move_qimode (operands);")
839 (define_insn ""
840 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
841 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
842 "TARGET_COLDFIRE"
843 "* return output_move_qimode (operands);")
845 (define_expand "movstrictqi"
846 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
847 (match_operand:QI 1 "general_src_operand" ""))]
848 ""
849 "")
851 (define_insn ""
852 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
853 (match_operand:QI 1 "general_src_operand" "dmSn"))]
854 "!TARGET_COLDFIRE"
855 "* return output_move_strictqi (operands);")
857 (define_insn ""
858 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
859 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
860 "TARGET_COLDFIRE"
861 "* return output_move_strictqi (operands);")
863 (define_expand "pushqi1"
864 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
865 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
866 (match_operand:QI 0 "general_operand" ""))]
867 "!TARGET_COLDFIRE"
868 "")
870 (define_expand "movsf"
871 [(set (match_operand:SF 0 "nonimmediate_operand" "")
872 (match_operand:SF 1 "general_operand" ""))]
873 ""
874 "")
876 (define_insn ""
877 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
878 (match_operand:SF 1 "general_operand" "rmfF"))]
879 "!TARGET_COLDFIRE"
880 "*
881 {
882 if (FP_REG_P (operands[0]))
883 {
884 if (FP_REG_P (operands[1]))
885 return \"f%$move%.x %1,%0\";
886 else if (ADDRESS_REG_P (operands[1]))
887 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
888 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
889 return output_move_const_single (operands);
890 return \"f%$move%.s %f1,%0\";
891 }
892 if (FP_REG_P (operands[1]))
893 {
894 if (ADDRESS_REG_P (operands[0]))
895 return \"fmove%.s %1,%-\;move%.l %+,%0\";
896 return \"fmove%.s %f1,%0\";
897 }
898 if (operands[1] == CONST0_RTX (SFmode)
899 /* clr insns on 68000 read before writing.
900 This isn't so on the 68010, but we have no TARGET_68010. */
901 && ((TARGET_68020 || TARGET_COLDFIRE)
902 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
903 {
904 if (ADDRESS_REG_P (operands[0]))
905 {
906 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
907 if (!TARGET_68040 && !TARGET_68060)
908 return \"sub%.l %0,%0\";
909 else
910 {
911 #ifdef MOTOROLA
912 #ifdef SGS
913 /* Many SGS assemblers croak on size specifiers for constants. */
914 return \"lea 0,%0\";
915 #else
916 return \"lea 0.w,%0\";
917 #endif
918 #else
919 return \"lea 0:w,%0\";
920 #endif
921 }
922 }
923 /* moveq is faster on the 68000. */
924 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
925 {
926 return \"moveq %#0,%0\";
927 }
928 return \"clr%.l %0\";
929 }
930 return \"move%.l %1,%0\";
931 }")
933 (define_insn ""
934 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
935 (match_operand:SF 1 "general_operand" "g,r"))]
936 "TARGET_COLDFIRE"
937 "* return \"move%.l %1,%0\";")
939 (define_expand "movdf"
940 [(set (match_operand:DF 0 "nonimmediate_operand" "")
941 (match_operand:DF 1 "general_operand" ""))]
942 ""
943 "")
945 (define_insn ""
946 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
947 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
948 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
949 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
950 "!TARGET_COLDFIRE"
951 "*
952 {
953 if (FP_REG_P (operands[0]))
954 {
955 if (FP_REG_P (operands[1]))
956 return \"f%&move%.x %1,%0\";
957 if (REG_P (operands[1]))
958 {
959 rtx xoperands[2];
960 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
961 output_asm_insn (\"move%.l %1,%-\", xoperands);
962 output_asm_insn (\"move%.l %1,%-\", operands);
963 return \"f%&move%.d %+,%0\";
964 }
965 if (GET_CODE (operands[1]) == CONST_DOUBLE)
966 return output_move_const_double (operands);
967 return \"f%&move%.d %f1,%0\";
968 }
969 else if (FP_REG_P (operands[1]))
970 {
971 if (REG_P (operands[0]))
972 {
973 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
974 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
975 return \"move%.l %+,%0\";
976 }
977 else
978 return \"fmove%.d %f1,%0\";
979 }
980 return output_move_double (operands);
981 }")
983 (define_insn ""
984 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
985 (match_operand:DF 1 "general_operand" "g,r"))]
986 "TARGET_COLDFIRE"
987 "* return output_move_double (operands);")
989 ;; ??? The XFmode patterns are schizophrenic about whether constants are
990 ;; allowed. Most but not all have predicates and constraint that disallow
991 ;; constants. Most but not all have output templates that handle constants.
992 ;; See also LEGITIMATE_CONSTANT_P.
994 (define_expand "movxf"
995 [(set (match_operand:XF 0 "nonimmediate_operand" "")
996 (match_operand:XF 1 "general_operand" ""))]
997 ""
998 "
999 {
1000 /* We can't rewrite operands during reload. */
1001 if (! reload_in_progress)
1002 {
1003 if (CONSTANT_P (operands[1]))
1004 {
1005 operands[1] = force_const_mem (XFmode, operands[1]);
1006 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1007 operands[1] = adjust_address (operands[1], XFmode, 0);
1008 }
1009 if (flag_pic && TARGET_PCREL)
1010 {
1011 /* Don't allow writes to memory except via a register; the
1012 m68k doesn't consider PC-relative addresses to be writable. */
1013 if (GET_CODE (operands[0]) == MEM
1014 && symbolic_operand (XEXP (operands[0], 0), SImode))
1015 operands[0] = gen_rtx (MEM, XFmode,
1016 force_reg (SImode, XEXP (operands[0], 0)));
1017 }
1018 }
1019 }")
1021 (define_insn ""
1022 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1023 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1024 "TARGET_68881"
1025 "*
1026 {
1027 if (FP_REG_P (operands[0]))
1028 {
1029 if (FP_REG_P (operands[1]))
1030 return \"fmove%.x %1,%0\";
1031 if (REG_P (operands[1]))
1032 {
1033 rtx xoperands[2];
1034 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1035 output_asm_insn (\"move%.l %1,%-\", xoperands);
1036 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1037 output_asm_insn (\"move%.l %1,%-\", xoperands);
1038 output_asm_insn (\"move%.l %1,%-\", operands);
1039 return \"fmove%.x %+,%0\";
1040 }
1041 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1042 return \"fmove%.x %1,%0\";
1043 return \"fmove%.x %f1,%0\";
1044 }
1045 if (FP_REG_P (operands[1]))
1046 {
1047 if (REG_P (operands[0]))
1048 {
1049 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1050 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1051 output_asm_insn (\"move%.l %+,%0\", operands);
1052 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1053 return \"move%.l %+,%0\";
1054 }
1055 /* Must be memory destination. */
1056 return \"fmove%.x %f1,%0\";
1057 }
1058 return output_move_double (operands);
1059 }
1060 ")
1062 (define_insn ""
1063 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1064 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1065 "! TARGET_68881 && ! TARGET_COLDFIRE"
1066 "*
1067 {
1068 if (FP_REG_P (operands[0]))
1069 {
1070 if (FP_REG_P (operands[1]))
1071 return \"fmove%.x %1,%0\";
1072 if (REG_P (operands[1]))
1073 {
1074 rtx xoperands[2];
1075 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1076 output_asm_insn (\"move%.l %1,%-\", xoperands);
1077 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1078 output_asm_insn (\"move%.l %1,%-\", xoperands);
1079 output_asm_insn (\"move%.l %1,%-\", operands);
1080 return \"fmove%.x %+,%0\";
1081 }
1082 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1083 return \"fmove%.x %1,%0\";
1084 return \"fmove%.x %f1,%0\";
1085 }
1086 if (FP_REG_P (operands[1]))
1087 {
1088 if (REG_P (operands[0]))
1089 {
1090 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1091 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1092 output_asm_insn (\"move%.l %+,%0\", operands);
1093 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1094 return \"move%.l %+,%0\";
1095 }
1096 else
1097 return \"fmove%.x %f1,%0\";
1098 }
1099 return output_move_double (operands);
1100 }
1101 ")
1103 (define_insn ""
1104 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1105 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1106 "! TARGET_68881 && TARGET_COLDFIRE"
1107 "* return output_move_double (operands);")
1109 (define_expand "movdi"
1110 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1111 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1112 (match_operand:DI 1 "general_operand" ""))]
1113 ""
1114 "")
1116 ;; movdi can apply to fp regs in some cases
1117 (define_insn ""
1118 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1119 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1120 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1121 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1122 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1123 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1124 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1125 "!TARGET_COLDFIRE"
1126 "*
1127 {
1128 if (FP_REG_P (operands[0]))
1129 {
1130 if (FP_REG_P (operands[1]))
1131 return \"fmove%.x %1,%0\";
1132 if (REG_P (operands[1]))
1133 {
1134 rtx xoperands[2];
1135 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1136 output_asm_insn (\"move%.l %1,%-\", xoperands);
1137 output_asm_insn (\"move%.l %1,%-\", operands);
1138 return \"fmove%.d %+,%0\";
1139 }
1140 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1141 return output_move_const_double (operands);
1142 return \"fmove%.d %f1,%0\";
1143 }
1144 else if (FP_REG_P (operands[1]))
1145 {
1146 if (REG_P (operands[0]))
1147 {
1148 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1149 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1150 return \"move%.l %+,%0\";
1151 }
1152 else
1153 return \"fmove%.d %f1,%0\";
1154 }
1155 return output_move_double (operands);
1156 }")
1158 (define_insn ""
1159 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1160 (match_operand:DI 1 "general_operand" "g,r"))]
1161 "TARGET_COLDFIRE"
1162 "* return output_move_double (operands);")
1164 ;; Thus goes after the move instructions
1165 ;; because the move instructions are better (require no spilling)
1166 ;; when they can apply. It goes before the add/sub insns
1167 ;; so we will prefer it to them.
1169 (define_insn "pushasi"
1170 [(set (match_operand:SI 0 "push_operand" "=m")
1171 (match_operand:SI 1 "address_operand" "p"))]
1172 ""
1173 "pea %a1")
1174 \f
1175 ;; truncation instructions
1176 (define_insn "truncsiqi2"
1177 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1178 (truncate:QI
1179 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1180 ""
1181 "*
1182 {
1183 if (GET_CODE (operands[0]) == REG)
1184 {
1185 /* Must clear condition codes, since the move.l bases them on
1186 the entire 32 bits, not just the desired 8 bits. */
1187 CC_STATUS_INIT;
1188 return \"move%.l %1,%0\";
1189 }
1190 if (GET_CODE (operands[1]) == MEM)
1191 operands[1] = adjust_address (operands[1], QImode, 3);
1192 return \"move%.b %1,%0\";
1193 }")
1195 (define_insn "trunchiqi2"
1196 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1197 (truncate:QI
1198 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1199 ""
1200 "*
1201 {
1202 if (GET_CODE (operands[0]) == REG
1203 && (GET_CODE (operands[1]) == MEM
1204 || GET_CODE (operands[1]) == CONST_INT))
1205 {
1206 /* Must clear condition codes, since the move.w bases them on
1207 the entire 16 bits, not just the desired 8 bits. */
1208 CC_STATUS_INIT;
1209 return \"move%.w %1,%0\";
1210 }
1211 if (GET_CODE (operands[0]) == REG)
1212 {
1213 /* Must clear condition codes, since the move.l bases them on
1214 the entire 32 bits, not just the desired 8 bits. */
1215 CC_STATUS_INIT;
1216 return \"move%.l %1,%0\";
1217 }
1218 if (GET_CODE (operands[1]) == MEM)
1219 operands[1] = adjust_address (operands[1], QImode, 1);
1220 return \"move%.b %1,%0\";
1221 }")
1223 (define_insn "truncsihi2"
1224 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1225 (truncate:HI
1226 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1227 ""
1228 "*
1229 {
1230 if (GET_CODE (operands[0]) == REG)
1231 {
1232 /* Must clear condition codes, since the move.l bases them on
1233 the entire 32 bits, not just the desired 8 bits. */
1234 CC_STATUS_INIT;
1235 return \"move%.l %1,%0\";
1236 }
1237 if (GET_CODE (operands[1]) == MEM)
1238 operands[1] = adjust_address (operands[1], QImode, 2);
1239 return \"move%.w %1,%0\";
1240 }")
1241 \f
1242 ;; zero extension instructions
1244 (define_insn "zero_extendqidi2"
1245 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1246 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1247 ""
1248 "*
1249 {
1250 CC_STATUS_INIT;
1251 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1252 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1253 }")
1255 (define_insn "zero_extendhidi2"
1256 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1257 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1258 ""
1259 "*
1260 {
1261 CC_STATUS_INIT;
1262 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1263 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1264 }")
1266 ;; this is the canonical form for (lshiftrt:DI x 32)
1267 (define_expand "zero_extendsidi2"
1268 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1269 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1270 ""
1271 "")
1273 (define_insn "*zero_extendsidi2_cf"
1274 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1275 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1276 "TARGET_COLDFIRE"
1277 "*
1278 {
1279 CC_STATUS_INIT;
1280 if (GET_CODE (operands[0]) == REG)
1281 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1282 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1283 return \"move%.l %1,%0\;clr%.l %0\";
1284 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1285 return \"clr%.l %0\;move%.l %1,%0\";
1286 else
1287 operands[2] = adjust_address (operands[0], SImode, 4);
1288 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1289 || REGNO (operands[1]) != REGNO (operands[2]))
1290 output_asm_insn (\"move%.l %1,%2\", operands);
1291 if (ADDRESS_REG_P (operands[0]))
1292 return \"sub%.l %0,%0\";
1293 else
1294 return \"clr%.l %0\";
1295 }")
1297 (define_insn "*zero_extendsidi2"
1298 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1299 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1300 "!TARGET_COLDFIRE"
1301 "*
1302 {
1303 CC_STATUS_INIT;
1304 if (GET_CODE (operands[0]) == REG)
1305 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1306 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1307 return \"move%.l %1,%0\;clr%.l %0\";
1308 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1309 return \"clr%.l %0\;move%.l %1,%0\";
1310 else
1311 operands[2] = adjust_address (operands[0], SImode, 4);
1312 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1313 || REGNO (operands[1]) != REGNO (operands[2]))
1314 output_asm_insn (\"move%.l %1,%2\", operands);
1315 if (ADDRESS_REG_P (operands[0]))
1316 return \"sub%.l %0,%0\";
1317 else
1318 return \"clr%.l %0\";
1319 }")
1321 (define_expand "zero_extendhisi2"
1322 [(set (match_operand:SI 0 "register_operand" "")
1323 (const_int 0))
1324 (set (strict_low_part (match_dup 2))
1325 (match_operand:HI 1 "general_operand" ""))]
1326 ""
1327 "
1328 {
1329 operands[1] = make_safe_from (operands[1], operands[0]);
1330 operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
1331 }")
1333 (define_expand "zero_extendqihi2"
1334 [(set (match_operand:HI 0 "register_operand" "")
1335 (const_int 0))
1336 (set (strict_low_part (match_dup 2))
1337 (match_operand:QI 1 "general_operand" ""))]
1338 ""
1339 "
1340 {
1341 operands[1] = make_safe_from (operands[1], operands[0]);
1342 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1343 }")
1345 (define_expand "zero_extendqisi2"
1346 [(set (match_operand:SI 0 "register_operand" "")
1347 (const_int 0))
1348 (set (strict_low_part (match_dup 2))
1349 (match_operand:QI 1 "general_operand" ""))]
1350 ""
1351 "
1352 {
1353 operands[1] = make_safe_from (operands[1], operands[0]);
1354 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1355 }")
1356 \f
1357 ;; Patterns to recognize zero-extend insns produced by the combiner.
1358 ;; We don't allow both operands in memory, because of aliasing problems.
1359 ;; Explicitly disallow two memory operands via the condition since reloading
1360 ;; of this case will result in worse code than the uncombined patterns.
1362 (define_insn ""
1363 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1364 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1365 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1366 "*
1367 {
1368 if (DATA_REG_P (operands[0]))
1369 {
1370 if (GET_CODE (operands[1]) == REG
1371 && REGNO (operands[0]) == REGNO (operands[1]))
1372 return \"and%.l %#0xFFFF,%0\";
1373 if (reg_mentioned_p (operands[0], operands[1]))
1374 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1375 return \"clr%.l %0\;move%.w %1,%0\";
1376 }
1377 else if (GET_CODE (operands[0]) == MEM
1378 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1379 return \"move%.w %1,%0\;clr%.w %0\";
1380 else if (GET_CODE (operands[0]) == MEM
1381 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1382 return \"clr%.w %0\;move%.w %1,%0\";
1383 else
1384 {
1385 output_asm_insn (\"clr%.w %0\", operands);
1386 operands[0] = adjust_address (operands[0], HImode, 2);
1387 return \"move%.w %1,%0\";
1388 }
1389 }")
1391 (define_insn ""
1392 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1393 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1394 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1395 "*
1396 {
1397 if (DATA_REG_P (operands[0]))
1398 {
1399 if (GET_CODE (operands[1]) == REG
1400 && REGNO (operands[0]) == REGNO (operands[1]))
1401 return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1402 if (reg_mentioned_p (operands[0], operands[1]))
1403 return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1404 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1405 return \"clr%.w %0\;move%.b %1,%0\";
1406 }
1407 else if (GET_CODE (operands[0]) == MEM
1408 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1409 {
1410 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1411 == STACK_POINTER_REGNUM)
1412 {
1413 output_asm_insn (\"clr%.w %-\", operands);
1414 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1415 plus_constant (stack_pointer_rtx, 1));
1416 return \"move%.b %1,%0\";
1417 }
1418 else
1419 return \"move%.b %1,%0\;clr%.b %0\";
1420 }
1421 else if (GET_CODE (operands[0]) == MEM
1422 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1423 return \"clr%.b %0\;move%.b %1,%0\";
1424 else
1425 {
1426 output_asm_insn (\"clr%.b %0\", operands);
1427 operands[0] = adjust_address (operands[0], QImode, 1);
1428 return \"move%.b %1,%0\";
1429 }
1430 }")
1432 (define_insn ""
1433 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1434 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1435 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1436 "*
1437 {
1438 if (DATA_REG_P (operands[0]))
1439 {
1440 if (GET_CODE (operands[1]) == REG
1441 && REGNO (operands[0]) == REGNO (operands[1]))
1442 return \"and%.l %#0xFF,%0\";
1443 if (reg_mentioned_p (operands[0], operands[1]))
1444 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1445 return \"clr%.l %0\;move%.b %1,%0\";
1446 }
1447 else if (GET_CODE (operands[0]) == MEM
1448 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1449 {
1450 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1451 #ifdef MOTOROLA
1452 #ifdef SGS
1453 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1454 #else
1455 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1456 #endif
1457 #else
1458 return \"clrl %0@-\;moveb %1,%0@(3)\";
1459 #endif
1460 }
1461 else if (GET_CODE (operands[0]) == MEM
1462 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1463 {
1464 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1465 #ifdef MOTOROLA
1466 #ifdef SGS
1467 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1468 #else
1469 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1470 #endif
1471 #else
1472 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1473 #endif
1474 }
1475 else
1476 {
1477 output_asm_insn (\"clr%.l %0\", operands);
1478 operands[0] = adjust_address (operands[0], QImode, 3);
1479 return \"move%.b %1,%0\";
1480 }
1481 }")
1482 \f
1483 ;; sign extension instructions
1485 (define_insn "extendqidi2"
1486 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1487 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1488 ""
1489 "*
1490 {
1491 CC_STATUS_INIT;
1492 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1493 if (TARGET_68020 || TARGET_COLDFIRE)
1494 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1495 else
1496 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1497 }")
1499 (define_insn "extendhidi2"
1500 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1501 (sign_extend:DI
1502 (match_operand:HI 1 "general_src_operand" "rmS")))]
1503 ""
1504 "*
1505 {
1506 CC_STATUS_INIT;
1507 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1508 if (TARGET_68020 || TARGET_COLDFIRE)
1509 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1510 else
1511 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1512 }")
1514 (define_insn "extendsidi2"
1515 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1516 (sign_extend:DI
1517 (match_operand:SI 1 "general_operand" "rm")))]
1518 ""
1519 "*
1520 {
1521 CC_STATUS_INIT;
1522 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1523 if (TARGET_68020 || TARGET_COLDFIRE)
1524 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1525 else
1526 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1527 }")
1529 ;; Special case when one can avoid register clobbering, copy and test
1530 ;; Maybe there is a way to make that the general case, by forcing the
1531 ;; result of the SI tree to be in the lower register of the DI target
1533 (define_insn "extendplussidi"
1534 [(set (match_operand:DI 0 "register_operand" "=d")
1535 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1536 (match_operand:SI 2 "general_operand" "rmn"))))]
1537 ""
1538 "*
1539 {
1540 CC_STATUS_INIT;
1541 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1542 if (GET_CODE (operands[1]) == CONST_INT
1543 && (unsigned) INTVAL (operands[1]) > 8)
1544 {
1545 rtx tmp = operands[1];
1547 operands[1] = operands[2];
1548 operands[2] = tmp;
1549 }
1550 if (GET_CODE (operands[1]) == REG
1551 && REGNO (operands[1]) == REGNO (operands[3]))
1552 output_asm_insn (\"add%.l %2,%3\", operands);
1553 else
1554 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1555 if (TARGET_68020 || TARGET_COLDFIRE)
1556 return \"smi %0\;extb%.l %0\";
1557 else
1558 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1559 }")
1561 (define_insn "extendhisi2"
1562 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1563 (sign_extend:SI
1564 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1565 ""
1566 "*
1567 {
1568 if (ADDRESS_REG_P (operands[0]))
1569 return \"move%.w %1,%0\";
1570 return \"ext%.l %0\";
1571 }")
1573 (define_insn "extendqihi2"
1574 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1575 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1576 ""
1577 "ext%.w %0")
1579 (define_insn "extendqisi2"
1580 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1581 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1582 "TARGET_68020 || TARGET_COLDFIRE"
1583 "extb%.l %0")
1584 \f
1585 ;; Conversions between float and double.
1587 (define_expand "extendsfdf2"
1588 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1589 (float_extend:DF
1590 (match_operand:SF 1 "general_operand" "")))]
1591 "TARGET_68881"
1592 "")
1594 (define_insn ""
1595 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1596 (float_extend:DF
1597 (match_operand:SF 1 "general_operand" "f,dmF")))]
1598 "TARGET_68881"
1599 "*
1600 {
1601 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1602 {
1603 if (REGNO (operands[0]) == REGNO (operands[1]))
1604 {
1605 /* Extending float to double in an fp-reg is a no-op.
1606 NOTICE_UPDATE_CC has already assumed that the
1607 cc will be set. So cancel what it did. */
1608 cc_status = cc_prev_status;
1609 return \"\";
1610 }
1611 return \"f%&move%.x %1,%0\";
1612 }
1613 if (FP_REG_P (operands[0]))
1614 return \"f%&move%.s %f1,%0\";
1615 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1616 {
1617 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1618 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1619 return \"move%.l %+,%0\";
1620 }
1621 return \"fmove%.d %f1,%0\";
1622 }")
1624 ;; This cannot output into an f-reg because there is no way to be
1625 ;; sure of truncating in that case.
1626 (define_expand "truncdfsf2"
1627 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1628 (float_truncate:SF
1629 (match_operand:DF 1 "general_operand" "")))]
1630 "TARGET_68881"
1631 "")
1633 ;; On the '040 we can truncate in a register accurately and easily.
1634 (define_insn ""
1635 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1636 (float_truncate:SF
1637 (match_operand:DF 1 "general_operand" "fmG")))]
1638 "TARGET_68040_ONLY"
1639 "*
1640 {
1641 if (FP_REG_P (operands[1]))
1642 return \"f%$move%.x %1,%0\";
1643 return \"f%$move%.d %f1,%0\";
1644 }")
1646 (define_insn ""
1647 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1648 (float_truncate:SF
1649 (match_operand:DF 1 "general_operand" "f")))]
1650 "TARGET_68881"
1651 "fmove%.s %f1,%0")
1652 \f
1653 ;; Conversion between fixed point and floating point.
1654 ;; Note that among the fix-to-float insns
1655 ;; the ones that start with SImode come first.
1656 ;; That is so that an operand that is a CONST_INT
1657 ;; (and therefore lacks a specific machine mode).
1658 ;; will be recognized as SImode (which is always valid)
1659 ;; rather than as QImode or HImode.
1661 (define_expand "floatsisf2"
1662 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1663 (float:SF (match_operand:SI 1 "general_operand" "")))]
1664 "TARGET_68881"
1665 "")
1667 (define_insn ""
1668 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1669 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1670 "TARGET_68881"
1671 "f%$move%.l %1,%0")
1673 (define_expand "floatsidf2"
1674 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1675 (float:DF (match_operand:SI 1 "general_operand" "")))]
1676 "TARGET_68881"
1677 "")
1679 (define_insn ""
1680 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1681 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1682 "TARGET_68881"
1683 "f%&move%.l %1,%0")
1685 (define_insn "floathisf2"
1686 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1687 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1688 "TARGET_68881"
1689 "f%$move%.w %1,%0")
1691 (define_insn "floathidf2"
1692 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1693 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1694 "TARGET_68881"
1695 "fmove%.w %1,%0")
1697 (define_insn "floatqisf2"
1698 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1699 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1700 "TARGET_68881"
1701 "fmove%.b %1,%0")
1703 (define_insn "floatqidf2"
1704 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1705 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1706 "TARGET_68881"
1707 "f%&move%.b %1,%0")
1709 ;; New routines to convert floating-point values to integers
1710 ;; to be used on the '040. These should be faster than trapping
1711 ;; into the kernel to emulate fintrz. They should also be faster
1712 ;; than calling the subroutines fixsfsi or fixdfsi.
1714 (define_insn "fix_truncdfsi2"
1715 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1716 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1717 (clobber (match_scratch:SI 2 "=d"))
1718 (clobber (match_scratch:SI 3 "=d"))]
1719 "TARGET_68881 && TARGET_68040"
1720 "*
1721 {
1722 CC_STATUS_INIT;
1723 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1724 }")
1726 (define_insn "fix_truncdfhi2"
1727 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1728 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1729 (clobber (match_scratch:SI 2 "=d"))
1730 (clobber (match_scratch:SI 3 "=d"))]
1731 "TARGET_68881 && TARGET_68040"
1732 "*
1733 {
1734 CC_STATUS_INIT;
1735 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1736 }")
1738 (define_insn "fix_truncdfqi2"
1739 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1740 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1741 (clobber (match_scratch:SI 2 "=d"))
1742 (clobber (match_scratch:SI 3 "=d"))]
1743 "TARGET_68881 && TARGET_68040"
1744 "*
1745 {
1746 CC_STATUS_INIT;
1747 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1748 }")
1750 ;; Convert a float to a float whose value is an integer.
1751 ;; This is the first stage of converting it to an integer type.
1753 (define_insn "ftruncdf2"
1754 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1755 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1756 "TARGET_68881 && !TARGET_68040"
1757 "*
1758 {
1759 if (FP_REG_P (operands[1]))
1760 return \"fintrz%.x %f1,%0\";
1761 return \"fintrz%.d %f1,%0\";
1762 }")
1764 (define_insn "ftruncsf2"
1765 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1766 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1767 "TARGET_68881 && !TARGET_68040"
1768 "*
1769 {
1770 if (FP_REG_P (operands[1]))
1771 return \"fintrz%.x %f1,%0\";
1772 return \"fintrz%.s %f1,%0\";
1773 }")
1775 ;; Convert a float whose value is an integer
1776 ;; to an actual integer. Second stage of converting float to integer type.
1777 (define_insn "fixsfqi2"
1778 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1779 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1780 "TARGET_68881"
1781 "fmove%.b %1,%0")
1783 (define_insn "fixsfhi2"
1784 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1785 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1786 "TARGET_68881"
1787 "fmove%.w %1,%0")
1789 (define_insn "fixsfsi2"
1790 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1791 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1792 "TARGET_68881"
1793 "fmove%.l %1,%0")
1795 (define_insn "fixdfqi2"
1796 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1797 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1798 "TARGET_68881"
1799 "fmove%.b %1,%0")
1801 (define_insn "fixdfhi2"
1802 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1803 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1804 "TARGET_68881"
1805 "fmove%.w %1,%0")
1807 (define_insn "fixdfsi2"
1808 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1809 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1810 "TARGET_68881"
1811 "fmove%.l %1,%0")
1812 \f
1813 ;; add instructions
1815 (define_insn "adddi_lshrdi_63"
1816 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1817 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1818 (const_int 63))
1819 (match_dup 1)))
1820 (clobber (match_scratch:SI 2 "=d"))]
1821 ""
1822 "*
1823 {
1824 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1825 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1826 return
1827 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1828 if (GET_CODE (operands[1]) == REG)
1829 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1830 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1831 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1832 operands[4] = operands[1];
1833 else
1834 operands[4] = adjust_address (operands[1], SImode, 4);
1835 if (GET_CODE (operands[1]) == MEM
1836 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1837 output_asm_insn (\"move%.l %4,%3\", operands);
1838 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1839 if (TARGET_68020 || TARGET_COLDFIRE)
1840 output_asm_insn (\"extb%.l %2\", operands);
1841 else
1842 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1843 if (GET_CODE (operands[1]) != MEM
1844 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1845 output_asm_insn (\"move%.l %4,%3\", operands);
1846 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1847 }")
1849 (define_insn "adddi_sexthishl32"
1850 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1851 (plus:DI (ashift:DI (sign_extend:DI
1852 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1853 (const_int 32))
1854 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1855 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1856 "!TARGET_COLDFIRE"
1857 "*
1858 {
1859 CC_STATUS_INIT;
1860 if (ADDRESS_REG_P (operands[0]))
1861 return \"add%.w %1,%0\";
1862 else if (ADDRESS_REG_P (operands[3]))
1863 return \"move%.w %1,%3\;add%.l %3,%0\";
1864 else
1865 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1866 } ")
1868 (define_insn "adddi_dilshr32"
1869 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1870 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1871 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1872 ;; (const_int 32))))]
1873 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1874 (const_int 32))
1875 (match_operand:DI 2 "general_operand" "0,0")))]
1876 ""
1877 "*
1878 {
1879 CC_STATUS_INIT;
1880 if (GET_CODE (operands[0]) == REG)
1881 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1882 else
1883 operands[2] = adjust_address (operands[0], SImode, 4);
1884 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
1885 } ")
1887 (define_insn "adddi_dishl32"
1888 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1889 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1890 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1891 ;; (const_int 32))))]
1892 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1893 (const_int 32))
1894 (match_operand:DI 2 "general_operand" "0,0")))]
1895 ""
1896 "*
1897 {
1898 CC_STATUS_INIT;
1899 if (GET_CODE (operands[1]) == REG)
1900 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1901 else
1902 operands[1] = adjust_address (operands[1], SImode, 4);
1903 return \"add%.l %1,%0\";
1904 } ")
1906 (define_insn "adddi3"
1907 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1908 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1909 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1910 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1911 ""
1912 "*
1913 {
1914 if (DATA_REG_P (operands[0]))
1915 {
1916 if (DATA_REG_P (operands[2]))
1917 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
1918 else if (GET_CODE (operands[2]) == MEM
1919 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1920 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
1921 else
1922 {
1923 rtx high, low;
1924 rtx xoperands[2];
1926 if (GET_CODE (operands[2]) == REG)
1927 {
1928 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1929 high = operands[2];
1930 }
1931 else if (CONSTANT_P (operands[2]))
1932 split_double (operands[2], &high, &low);
1933 else
1934 {
1935 low = adjust_address (operands[2], SImode, 4);
1936 high = operands[2];
1937 }
1939 operands[1] = low, operands[2] = high;
1940 xoperands[0] = operands[3];
1941 if (GET_CODE (operands[1]) == CONST_INT
1942 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1943 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
1944 else
1945 xoperands[1] = operands[2];
1947 output_asm_insn (output_move_simode (xoperands), xoperands);
1948 if (GET_CODE (operands[1]) == CONST_INT)
1949 {
1950 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
1951 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
1952 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1953 {
1954 operands[1] = GEN_INT (-INTVAL (operands[1]));
1955 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
1956 }
1957 }
1958 return \"add%.l %1,%R0\;addx%.l %3,%0\";
1959 }
1960 }
1961 else if (GET_CODE (operands[0]) == MEM)
1962 {
1963 if (GET_CODE (operands[2]) == MEM
1964 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
1965 return \"add%.l %2,%0\;addx%.l %2,%0\";
1966 CC_STATUS_INIT;
1967 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1968 {
1969 operands[1] = gen_rtx_MEM (SImode,
1970 plus_constant (XEXP(operands[0], 0), -8));
1971 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
1972 }
1973 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1974 {
1975 operands[1] = XEXP(operands[0], 0);
1976 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
1977 }
1978 else
1979 {
1980 operands[1] = adjust_address (operands[0], SImode, 4);
1981 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
1982 }
1983 }
1984 else
1985 abort ();
1986 } ")
1988 (define_insn "addsi_lshrsi_31"
1989 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1990 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
1991 (const_int 31))
1992 (match_dup 1)))]
1993 ""
1994 "*
1995 {
1996 operands[2] = operands[0];
1997 operands[3] = gen_label_rtx();
1998 if (GET_CODE (operands[0]) == MEM)
1999 {
2000 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2001 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2002 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2003 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2004 }
2005 output_asm_insn (\"move%.l %1,%0\", operands);
2006 #ifdef MOTOROLA
2007 output_asm_insn (\"jbpl %l3\", operands);
2008 #else
2009 output_asm_insn (\"jpl %l3\", operands);
2010 #endif
2011 output_asm_insn (\"addq%.l %#1,%2\", operands);
2012 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2013 CODE_LABEL_NUMBER (operands[3]));
2014 return \"\";
2015 }")
2017 (define_expand "addsi3"
2018 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2019 (plus:SI (match_operand:SI 1 "general_operand" "")
2020 (match_operand:SI 2 "general_src_operand" "")))]
2021 ""
2022 "")
2024 ;; Note that the middle two alternatives are near-duplicates
2025 ;; in order to handle insns generated by reload.
2026 ;; This is needed since they are not themselves reloaded,
2027 ;; so commutativity won't apply to them.
2028 (define_insn "*addsi3_internal"
2029 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2030 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2031 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2034 "! TARGET_COLDFIRE"
2035 "* return output_addsi3 (operands);")
2037 (define_insn "*addsi3_5200"
2038 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2039 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2040 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2041 "TARGET_COLDFIRE"
2042 "* return output_addsi3 (operands);")
2044 (define_insn ""
2045 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2046 (plus:SI (match_operand:SI 1 "general_operand" "0")
2047 (sign_extend:SI
2048 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2049 "!TARGET_COLDFIRE"
2050 "add%.w %2,%0")
2052 (define_insn "addhi3"
2053 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2054 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2055 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2056 "!TARGET_COLDFIRE"
2057 "*
2058 {
2059 if (GET_CODE (operands[2]) == CONST_INT)
2060 {
2061 /* If the constant would be a negative number when interpreted as
2062 HImode, make it negative. This is usually, but not always, done
2063 elsewhere in the compiler. First check for constants out of range,
2064 which could confuse us. */
2066 if (INTVAL (operands[2]) >= 32768)
2067 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2069 if (INTVAL (operands[2]) > 0
2070 && INTVAL (operands[2]) <= 8)
2071 return \"addq%.w %2,%0\";
2072 if (INTVAL (operands[2]) < 0
2073 && INTVAL (operands[2]) >= -8)
2074 {
2075 operands[2] = GEN_INT (- INTVAL (operands[2]));
2076 return \"subq%.w %2,%0\";
2077 }
2078 /* On the CPU32 it is faster to use two addqw instructions to
2079 add a small integer (8 < N <= 16) to a register.
2080 Likewise for subqw. */
2081 if (TARGET_CPU32 && REG_P (operands[0]))
2082 {
2083 if (INTVAL (operands[2]) > 8
2084 && INTVAL (operands[2]) <= 16)
2085 {
2086 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2087 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2088 }
2089 if (INTVAL (operands[2]) < -8
2090 && INTVAL (operands[2]) >= -16)
2091 {
2092 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2093 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2094 }
2095 }
2096 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2097 #ifdef MOTOROLA
2098 return \"lea (%c2,%0),%0\";
2099 #else
2100 return \"lea %0@(%c2),%0\";
2101 #endif
2102 }
2103 return \"add%.w %2,%0\";
2104 }")
2106 ;; These insns must use MATCH_DUP instead of the more expected
2107 ;; use of a matching constraint because the "output" here is also
2108 ;; an input, so you can't use the matching constraint. That also means
2109 ;; that you can't use the "%", so you need patterns with the matched
2110 ;; operand in both positions.
2112 (define_insn ""
2113 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2114 (plus:HI (match_dup 0)
2115 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2116 "!TARGET_COLDFIRE"
2117 "*
2118 {
2119 if (GET_CODE (operands[1]) == CONST_INT)
2120 {
2121 /* If the constant would be a negative number when interpreted as
2122 HImode, make it negative. This is usually, but not always, done
2123 elsewhere in the compiler. First check for constants out of range,
2124 which could confuse us. */
2126 if (INTVAL (operands[1]) >= 32768)
2127 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2129 if (INTVAL (operands[1]) > 0
2130 && INTVAL (operands[1]) <= 8)
2131 return \"addq%.w %1,%0\";
2132 if (INTVAL (operands[1]) < 0
2133 && INTVAL (operands[1]) >= -8)
2134 {
2135 operands[1] = GEN_INT (- INTVAL (operands[1]));
2136 return \"subq%.w %1,%0\";
2137 }
2138 /* On the CPU32 it is faster to use two addqw instructions to
2139 add a small integer (8 < N <= 16) to a register.
2140 Likewise for subqw. */
2141 if (TARGET_CPU32 && REG_P (operands[0]))
2142 {
2143 if (INTVAL (operands[1]) > 8
2144 && INTVAL (operands[1]) <= 16)
2145 {
2146 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2147 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2148 }
2149 if (INTVAL (operands[1]) < -8
2150 && INTVAL (operands[1]) >= -16)
2151 {
2152 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2153 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2154 }
2155 }
2156 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2157 #ifdef MOTOROLA
2158 return \"lea (%c1,%0),%0\";
2159 #else
2160 return \"lea %0@(%c1),%0\";
2161 #endif
2162 }
2163 return \"add%.w %1,%0\";
2164 }")
2166 (define_insn ""
2167 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2168 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2169 (match_dup 0)))]
2170 "!TARGET_COLDFIRE"
2171 "*
2172 {
2173 if (GET_CODE (operands[1]) == CONST_INT)
2174 {
2175 /* If the constant would be a negative number when interpreted as
2176 HImode, make it negative. This is usually, but not always, done
2177 elsewhere in the compiler. First check for constants out of range,
2178 which could confuse us. */
2180 if (INTVAL (operands[1]) >= 32768)
2181 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2183 if (INTVAL (operands[1]) > 0
2184 && INTVAL (operands[1]) <= 8)
2185 return \"addq%.w %1,%0\";
2186 if (INTVAL (operands[1]) < 0
2187 && INTVAL (operands[1]) >= -8)
2188 {
2189 operands[1] = GEN_INT (- INTVAL (operands[1]));
2190 return \"subq%.w %1,%0\";
2191 }
2192 /* On the CPU32 it is faster to use two addqw instructions to
2193 add a small integer (8 < N <= 16) to a register.
2194 Likewise for subqw. */
2195 if (TARGET_CPU32 && REG_P (operands[0]))
2196 {
2197 if (INTVAL (operands[1]) > 8
2198 && INTVAL (operands[1]) <= 16)
2199 {
2200 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2201 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2202 }
2203 if (INTVAL (operands[1]) < -8
2204 && INTVAL (operands[1]) >= -16)
2205 {
2206 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2207 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2208 }
2209 }
2210 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2211 #ifdef MOTOROLA
2212 return \"lea (%c1,%0),%0\";
2213 #else
2214 return \"lea %0@(%c1),%0\";
2215 #endif
2216 }
2217 return \"add%.w %1,%0\";
2218 }")
2220 (define_insn "addqi3"
2221 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2222 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2223 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2224 "!TARGET_COLDFIRE"
2225 "*
2226 {
2227 if (GET_CODE (operands[2]) == CONST_INT)
2228 {
2229 if (INTVAL (operands[2]) >= 128)
2230 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2232 if (INTVAL (operands[2]) > 0
2233 && INTVAL (operands[2]) <= 8)
2234 return \"addq%.b %2,%0\";
2235 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2236 {
2237 operands[2] = GEN_INT (- INTVAL (operands[2]));
2238 return \"subq%.b %2,%0\";
2239 }
2240 }
2241 return \"add%.b %2,%0\";
2242 }")
2244 (define_insn ""
2245 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2246 (plus:QI (match_dup 0)
2247 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2248 "!TARGET_COLDFIRE"
2249 "*
2250 {
2251 if (GET_CODE (operands[1]) == CONST_INT)
2252 {
2253 if (INTVAL (operands[1]) >= 128)
2254 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2256 if (INTVAL (operands[1]) > 0
2257 && INTVAL (operands[1]) <= 8)
2258 return \"addq%.b %1,%0\";
2259 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2260 {
2261 operands[1] = GEN_INT (- INTVAL (operands[1]));
2262 return \"subq%.b %1,%0\";
2263 }
2264 }
2265 return \"add%.b %1,%0\";
2266 }")
2268 (define_insn ""
2269 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2270 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2271 (match_dup 0)))]
2272 "!TARGET_COLDFIRE"
2273 "*
2274 {
2275 if (GET_CODE (operands[1]) == CONST_INT)
2276 {
2277 if (INTVAL (operands[1]) >= 128)
2278 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2280 if (INTVAL (operands[1]) > 0
2281 && INTVAL (operands[1]) <= 8)
2282 return \"addq%.b %1,%0\";
2283 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2284 {
2285 operands[1] = GEN_INT (- INTVAL (operands[1]));
2286 return \"subq%.b %1,%0\";
2287 }
2288 }
2289 return \"add%.b %1,%0\";
2290 }")
2292 (define_expand "adddf3"
2293 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2294 (plus:DF (match_operand:DF 1 "general_operand" "")
2295 (match_operand:DF 2 "general_operand" "")))]
2296 "TARGET_68881"
2297 "")
2299 (define_insn ""
2300 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2301 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2302 (match_operand:DF 1 "general_operand" "0")))]
2303 "TARGET_68881"
2304 "f%&add%.l %2,%0")
2306 (define_insn ""
2307 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2308 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2309 (match_operand:DF 1 "general_operand" "0")))]
2310 "TARGET_68881"
2311 "f%&add%.w %2,%0")
2313 (define_insn ""
2314 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2315 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2316 (match_operand:DF 1 "general_operand" "0")))]
2317 "TARGET_68881"
2318 "f%&add%.b %2,%0")
2320 (define_insn ""
2321 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2322 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2323 (match_operand:DF 2 "general_operand" "fmG")))]
2324 "TARGET_68881"
2325 "*
2326 {
2327 if (REG_P (operands[2]))
2328 return \"f%&add%.x %2,%0\";
2329 return \"f%&add%.d %f2,%0\";
2330 }")
2332 (define_expand "addsf3"
2333 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2334 (plus:SF (match_operand:SF 1 "general_operand" "")
2335 (match_operand:SF 2 "general_operand" "")))]
2336 "TARGET_68881"
2337 "")
2339 (define_insn ""
2340 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2341 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2342 (match_operand:SF 1 "general_operand" "0")))]
2343 "TARGET_68881"
2344 "f%$add%.l %2,%0")
2346 (define_insn ""
2347 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2348 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2349 (match_operand:SF 1 "general_operand" "0")))]
2350 "TARGET_68881"
2351 "f%$add%.w %2,%0")
2353 (define_insn ""
2354 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2355 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2356 (match_operand:SF 1 "general_operand" "0")))]
2357 "TARGET_68881"
2358 "f%$add%.b %2,%0")
2360 (define_insn ""
2361 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2362 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2363 (match_operand:SF 2 "general_operand" "fdmF")))]
2364 "TARGET_68881"
2365 "*
2366 {
2367 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2368 return \"f%$add%.x %2,%0\";
2369 return \"f%$add%.s %f2,%0\";
2370 }")
2371 \f
2372 ;; subtract instructions
2374 (define_insn "subdi_sexthishl32"
2375 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2376 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2377 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2378 (const_int 32))))
2379 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2380 "!TARGET_COLDFIRE"
2381 "*
2382 {
2383 CC_STATUS_INIT;
2384 if (ADDRESS_REG_P (operands[0]))
2385 return \"sub%.w %2,%0\";
2386 else if (ADDRESS_REG_P (operands[3]))
2387 return \"move%.w %2,%3\;sub%.l %3,%0\";
2388 else
2389 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2390 } ")
2392 (define_insn "subdi_dishl32"
2393 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2394 (minus:DI (match_dup 0)
2395 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2396 (const_int 32))))]
2397 ""
2398 "*
2399 {
2400 CC_STATUS_INIT;
2401 if (GET_CODE (operands[1]) == REG)
2402 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2403 else
2404 operands[1] = adjust_address (operands[1], SImode, 4);
2405 return \"sub%.l %1,%0\";
2406 } ")
2408 (define_insn "subdi3"
2409 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2410 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2411 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2412 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2413 ""
2414 "*
2415 {
2416 if (DATA_REG_P (operands[0]))
2417 {
2418 if (DATA_REG_P (operands[2]))
2419 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2420 else if (GET_CODE (operands[2]) == MEM
2421 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2422 {
2423 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2424 }
2425 else
2426 {
2427 rtx high, low;
2428 rtx xoperands[2];
2430 if (GET_CODE (operands[2]) == REG)
2431 {
2432 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2433 high = operands[2];
2434 }
2435 else if (CONSTANT_P (operands[2]))
2436 split_double (operands[2], &high, &low);
2437 else
2438 {
2439 low = adjust_address (operands[2], SImode, 4);
2440 high = operands[2];
2441 }
2443 operands[1] = low, operands[2] = high;
2444 xoperands[0] = operands[3];
2445 if (GET_CODE (operands[1]) == CONST_INT
2446 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2447 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2448 else
2449 xoperands[1] = operands[2];
2451 output_asm_insn (output_move_simode (xoperands), xoperands);
2452 if (GET_CODE (operands[1]) == CONST_INT)
2453 {
2454 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2455 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2456 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2457 {
2458 operands[1] = GEN_INT (-INTVAL (operands[1]));
2459 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2460 }
2461 }
2462 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2463 }
2464 }
2465 else if (GET_CODE (operands[0]) == MEM)
2466 {
2467 if (GET_CODE (operands[2]) == MEM
2468 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2469 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2470 CC_STATUS_INIT;
2471 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2472 {
2473 operands[1]
2474 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2475 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2476 }
2477 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2478 {
2479 operands[1] = XEXP(operands[0], 0);
2480 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2481 }
2482 else
2483 {
2484 operands[1] = adjust_address (operands[0], SImode, 4);
2485 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2486 }
2487 }
2488 else
2489 abort ();
2490 } ")
2492 (define_insn "subsi3"
2493 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2494 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2495 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2496 ""
2497 "sub%.l %2,%0")
2499 (define_insn ""
2500 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2501 (minus:SI (match_operand:SI 1 "general_operand" "0")
2502 (sign_extend:SI
2503 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2504 "!TARGET_COLDFIRE"
2505 "sub%.w %2,%0")
2507 (define_insn "subhi3"
2508 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2509 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2510 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2511 "!TARGET_COLDFIRE"
2512 "sub%.w %2,%0")
2514 (define_insn ""
2515 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2516 (minus:HI (match_dup 0)
2517 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2518 "!TARGET_COLDFIRE"
2519 "sub%.w %1,%0")
2521 (define_insn "subqi3"
2522 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2523 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2524 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2525 "!TARGET_COLDFIRE"
2526 "sub%.b %2,%0")
2528 (define_insn ""
2529 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2530 (minus:QI (match_dup 0)
2531 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2532 "!TARGET_COLDFIRE"
2533 "sub%.b %1,%0")
2535 (define_expand "subdf3"
2536 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2537 (minus:DF (match_operand:DF 1 "general_operand" "")
2538 (match_operand:DF 2 "general_operand" "")))]
2539 "TARGET_68881"
2540 "")
2542 (define_insn ""
2543 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2544 (minus:DF (match_operand:DF 1 "general_operand" "0")
2545 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2546 "TARGET_68881"
2547 "f%&sub%.l %2,%0")
2549 (define_insn ""
2550 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2551 (minus:DF (match_operand:DF 1 "general_operand" "0")
2552 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2553 "TARGET_68881"
2554 "f%&sub%.w %2,%0")
2556 (define_insn ""
2557 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2558 (minus:DF (match_operand:DF 1 "general_operand" "0")
2559 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2560 "TARGET_68881"
2561 "f%&sub%.b %2,%0")
2563 (define_insn ""
2564 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2565 (minus:DF (match_operand:DF 1 "general_operand" "0")
2566 (match_operand:DF 2 "general_operand" "fmG")))]
2567 "TARGET_68881"
2568 "*
2569 {
2570 if (REG_P (operands[2]))
2571 return \"f%&sub%.x %2,%0\";
2572 return \"f%&sub%.d %f2,%0\";
2573 }")
2575 (define_expand "subsf3"
2576 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2577 (minus:SF (match_operand:SF 1 "general_operand" "")
2578 (match_operand:SF 2 "general_operand" "")))]
2579 "TARGET_68881"
2580 "")
2582 (define_insn ""
2583 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2584 (minus:SF (match_operand:SF 1 "general_operand" "0")
2585 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2586 "TARGET_68881"
2587 "f%$sub%.l %2,%0")
2589 (define_insn ""
2590 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2591 (minus:SF (match_operand:SF 1 "general_operand" "0")
2592 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2593 "TARGET_68881"
2594 "f%$sub%.w %2,%0")
2596 (define_insn ""
2597 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2598 (minus:SF (match_operand:SF 1 "general_operand" "0")
2599 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2600 "TARGET_68881"
2601 "f%$sub%.b %2,%0")
2603 (define_insn ""
2604 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2605 (minus:SF (match_operand:SF 1 "general_operand" "0")
2606 (match_operand:SF 2 "general_operand" "fdmF")))]
2607 "TARGET_68881"
2608 "*
2609 {
2610 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2611 return \"f%$sub%.x %2,%0\";
2612 return \"f%$sub%.s %f2,%0\";
2613 }")
2614 \f
2615 ;; multiply instructions
2617 (define_insn "mulhi3"
2618 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2619 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2620 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2621 ""
2622 "*
2623 {
2624 #if defined(MOTOROLA)
2625 return \"muls%.w %2,%0\";
2626 #else
2627 return \"muls %2,%0\";
2628 #endif
2629 }")
2631 (define_insn "mulhisi3"
2632 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2633 (mult:SI (sign_extend:SI
2634 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2635 (sign_extend:SI
2636 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2637 ""
2638 "*
2639 {
2640 #if defined(MOTOROLA)
2641 return \"muls%.w %2,%0\";
2642 #else
2643 return \"muls %2,%0\";
2644 #endif
2645 }")
2647 (define_insn ""
2648 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2649 (mult:SI (sign_extend:SI
2650 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2651 (match_operand:SI 2 "const_int_operand" "n")))]
2652 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2653 "*
2654 {
2655 #if defined(MOTOROLA)
2656 return \"muls%.w %2,%0\";
2657 #else
2658 return \"muls %2,%0\";
2659 #endif
2660 }")
2662 (define_expand "mulsi3"
2663 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2664 (mult:SI (match_operand:SI 1 "general_operand" "")
2665 (match_operand:SI 2 "general_operand" "")))]
2666 "TARGET_68020 || TARGET_COLDFIRE"
2667 "")
2669 (define_insn ""
2670 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2671 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2672 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2674 "TARGET_68020"
2675 "muls%.l %2,%0")
2677 (define_insn ""
2678 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2679 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2680 (match_operand:SI 2 "general_operand" "d<Q>")))]
2681 "TARGET_COLDFIRE"
2682 "muls%.l %2,%0")
2684 (define_insn "umulhisi3"
2685 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2686 (mult:SI (zero_extend:SI
2687 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2688 (zero_extend:SI
2689 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2690 ""
2691 "*
2692 {
2693 #if defined(MOTOROLA)
2694 return \"mulu%.w %2,%0\";
2695 #else
2696 return \"mulu %2,%0\";
2697 #endif
2698 }")
2700 (define_insn ""
2701 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2702 (mult:SI (zero_extend:SI
2703 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2704 (match_operand:SI 2 "const_int_operand" "n")))]
2705 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2706 "*
2707 {
2708 #if defined(MOTOROLA)
2709 return \"mulu%.w %2,%0\";
2710 #else
2711 return \"mulu %2,%0\";
2712 #endif
2713 }")
2715 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2716 ;; proper matching constraint. This is because the matching is between
2717 ;; the high-numbered word of the DImode operand[0] and operand[1].
2718 (define_expand "umulsidi3"
2719 [(parallel
2720 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2721 (mult:SI (match_operand:SI 1 "register_operand" "")
2722 (match_operand:SI 2 "register_operand" "")))
2723 (set (subreg:SI (match_dup 0) 0)
2724 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2725 (zero_extend:DI (match_dup 2)))
2726 (const_int 32))))])]
2727 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2728 "")
2730 (define_insn ""
2731 [(set (match_operand:SI 0 "register_operand" "=d")
2732 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2733 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2734 (set (match_operand:SI 3 "register_operand" "=d")
2735 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2736 (zero_extend:DI (match_dup 2)))
2737 (const_int 32))))]
2738 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2739 "mulu%.l %2,%3:%0")
2741 ; Match immediate case. For 2.4 only match things < 2^31.
2742 ; It's tricky with larger values in these patterns since we need to match
2743 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2744 ; a CONST_INT.
2745 (define_insn ""
2746 [(set (match_operand:SI 0 "register_operand" "=d")
2747 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2748 (match_operand:SI 2 "const_int_operand" "n")))
2749 (set (match_operand:SI 3 "register_operand" "=d")
2750 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2751 (match_dup 2))
2752 (const_int 32))))]
2753 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
2754 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2755 "mulu%.l %2,%3:%0")
2757 (define_expand "mulsidi3"
2758 [(parallel
2759 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2760 (mult:SI (match_operand:SI 1 "register_operand" "")
2761 (match_operand:SI 2 "register_operand" "")))
2762 (set (subreg:SI (match_dup 0) 0)
2763 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2764 (sign_extend:DI (match_dup 2)))
2765 (const_int 32))))])]
2766 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2767 "")
2769 (define_insn ""
2770 [(set (match_operand:SI 0 "register_operand" "=d")
2771 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2772 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2773 (set (match_operand:SI 3 "register_operand" "=d")
2774 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2775 (sign_extend:DI (match_dup 2)))
2776 (const_int 32))))]
2777 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2778 "muls%.l %2,%3:%0")
2780 (define_insn ""
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2782 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2783 (match_operand:SI 2 "const_int_operand" "n")))
2784 (set (match_operand:SI 3 "register_operand" "=d")
2785 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2786 (match_dup 2))
2787 (const_int 32))))]
2788 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2789 "muls%.l %2,%3:%0")
2791 (define_expand "umulsi3_highpart"
2792 [(parallel
2793 [(set (match_operand:SI 0 "register_operand" "")
2794 (truncate:SI
2795 (lshiftrt:DI
2796 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2797 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2798 (const_int 32))))
2799 (clobber (match_dup 3))])]
2800 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2801 "
2802 {
2803 operands[3] = gen_reg_rtx (SImode);
2805 if (GET_CODE (operands[2]) == CONST_INT)
2806 {
2807 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2808 0, DImode);
2810 /* We have to adjust the operand order for the matching constraints. */
2811 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2812 operands[1], operands[2]));
2813 DONE;
2814 }
2815 }")
2817 (define_insn ""
2818 [(set (match_operand:SI 0 "register_operand" "=d")
2819 (truncate:SI
2820 (lshiftrt:DI
2821 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2822 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2823 (const_int 32))))
2824 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2825 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2826 "mulu%.l %3,%0:%1")
2828 (define_insn "const_umulsi3_highpart"
2829 [(set (match_operand:SI 0 "register_operand" "=d")
2830 (truncate:SI
2831 (lshiftrt:DI
2832 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2833 (match_operand:DI 3 "const_uint32_operand" "n"))
2834 (const_int 32))))
2835 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2836 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2837 "mulu%.l %3,%0:%1")
2839 (define_expand "smulsi3_highpart"
2840 [(parallel
2841 [(set (match_operand:SI 0 "register_operand" "")
2842 (truncate:SI
2843 (lshiftrt:DI
2844 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2845 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2846 (const_int 32))))
2847 (clobber (match_dup 3))])]
2848 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2849 "
2850 {
2851 operands[3] = gen_reg_rtx (SImode);
2852 if (GET_CODE (operands[2]) == CONST_INT)
2853 {
2854 /* We have to adjust the operand order for the matching constraints. */
2855 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2856 operands[1], operands[2]));
2857 DONE;
2858 }
2859 }")
2861 (define_insn ""
2862 [(set (match_operand:SI 0 "register_operand" "=d")
2863 (truncate:SI
2864 (lshiftrt:DI
2865 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2866 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2867 (const_int 32))))
2868 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2869 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2870 "muls%.l %3,%0:%1")
2872 (define_insn "const_smulsi3_highpart"
2873 [(set (match_operand:SI 0 "register_operand" "=d")
2874 (truncate:SI
2875 (lshiftrt:DI
2876 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2877 (match_operand:DI 3 "const_sint32_operand" "n"))
2878 (const_int 32))))
2879 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2880 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2881 "muls%.l %3,%0:%1")
2883 (define_expand "muldf3"
2884 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2885 (mult:DF (match_operand:DF 1 "general_operand" "")
2886 (match_operand:DF 2 "general_operand" "")))]
2887 "TARGET_68881"
2888 "")
2890 (define_insn ""
2891 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2892 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2893 (match_operand:DF 1 "general_operand" "0")))]
2894 "TARGET_68881"
2895 "f%&mul%.l %2,%0")
2897 (define_insn ""
2898 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2899 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2900 (match_operand:DF 1 "general_operand" "0")))]
2901 "TARGET_68881"
2902 "f%&mul%.w %2,%0")
2904 (define_insn ""
2905 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2906 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2907 (match_operand:DF 1 "general_operand" "0")))]
2908 "TARGET_68881"
2909 "f%&mul%.b %2,%0")
2911 (define_insn ""
2912 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2913 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2914 (match_operand:DF 2 "general_operand" "fmG")))]
2915 "TARGET_68881"
2916 "*
2917 {
2918 if (GET_CODE (operands[2]) == CONST_DOUBLE
2919 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
2920 {
2921 int i = floating_exact_log2 (operands[2]);
2922 operands[2] = GEN_INT (i);
2923 return \"fscale%.l %2,%0\";
2924 }
2925 if (REG_P (operands[2]))
2926 return \"f%&mul%.x %2,%0\";
2927 return \"f%&mul%.d %f2,%0\";
2928 }")
2930 (define_expand "mulsf3"
2931 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2932 (mult:SF (match_operand:SF 1 "general_operand" "")
2933 (match_operand:SF 2 "general_operand" "")))]
2934 "TARGET_68881"
2935 "")
2937 (define_insn ""
2938 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2939 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2940 (match_operand:SF 1 "general_operand" "0")))]
2941 "TARGET_68881"
2942 "*
2943 {
2944 return (TARGET_68040_ONLY
2945 ? \"fsmul%.l %2,%0\"
2946 : \"fsglmul%.l %2,%0\");
2947 }")
2949 (define_insn ""
2950 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2951 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2952 (match_operand:SF 1 "general_operand" "0")))]
2953 "TARGET_68881"
2954 "*
2955 {
2956 return (TARGET_68040_ONLY
2957 ? \"fsmul%.w %2,%0\"
2958 : \"fsglmul%.w %2,%0\");
2959 }")
2961 (define_insn ""
2962 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2963 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2964 (match_operand:SF 1 "general_operand" "0")))]
2965 "TARGET_68881"
2966 "*
2967 {
2968 return (TARGET_68040_ONLY
2969 ? \"fsmul%.b %2,%0\"
2970 : \"fsglmul%.b %2,%0\");
2971 }")
2973 (define_insn ""
2974 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2975 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2976 (match_operand:SF 2 "general_operand" "fdmF")))]
2977 "TARGET_68881"
2978 "*
2979 {
2980 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2981 return (TARGET_68040_ONLY
2982 ? \"fsmul%.x %2,%0\"
2983 : \"fsglmul%.x %2,%0\");
2984 return (TARGET_68040_ONLY
2985 ? \"fsmul%.s %f2,%0\"
2986 : \"fsglmul%.s %f2,%0\");
2987 }")
2988 \f
2989 ;; divide instructions
2991 (define_expand "divdf3"
2992 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2993 (div:DF (match_operand:DF 1 "general_operand" "")
2994 (match_operand:DF 2 "general_operand" "")))]
2995 "TARGET_68881"
2996 "")
2998 (define_insn ""
2999 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3000 (div:DF (match_operand:DF 1 "general_operand" "0")
3001 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3002 "TARGET_68881"
3003 "f%&div%.l %2,%0")
3005 (define_insn ""
3006 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3007 (div:DF (match_operand:DF 1 "general_operand" "0")
3008 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3009 "TARGET_68881"
3010 "f%&div%.w %2,%0")
3012 (define_insn ""
3013 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3014 (div:DF (match_operand:DF 1 "general_operand" "0")
3015 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3016 "TARGET_68881"
3017 "f%&div%.b %2,%0")
3019 (define_insn ""
3020 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3021 (div:DF (match_operand:DF 1 "general_operand" "0")
3022 (match_operand:DF 2 "general_operand" "fmG")))]
3023 "TARGET_68881"
3024 "*
3025 {
3026 if (REG_P (operands[2]))
3027 return \"f%&div%.x %2,%0\";
3028 return \"f%&div%.d %f2,%0\";
3029 }")
3031 (define_expand "divsf3"
3032 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3033 (div:SF (match_operand:SF 1 "general_operand" "")
3034 (match_operand:SF 2 "general_operand" "")))]
3035 "TARGET_68881"
3036 "")
3038 (define_insn ""
3039 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3040 (div:SF (match_operand:SF 1 "general_operand" "0")
3041 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3042 "TARGET_68881"
3043 "*
3044 {
3045 return (TARGET_68040_ONLY
3046 ? \"fsdiv%.l %2,%0\"
3047 : \"fsgldiv%.l %2,%0\");
3048 }")
3050 (define_insn ""
3051 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3052 (div:SF (match_operand:SF 1 "general_operand" "0")
3053 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3054 "TARGET_68881"
3055 "*
3056 {
3057 return (TARGET_68040_ONLY
3058 ? \"fsdiv%.w %2,%0\"
3059 : \"fsgldiv%.w %2,%0\");
3060 }")
3062 (define_insn ""
3063 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3064 (div:SF (match_operand:SF 1 "general_operand" "0")
3065 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3066 "TARGET_68881"
3067 "*
3068 {
3069 return (TARGET_68040_ONLY
3070 ? \"fsdiv%.b %2,%0\"
3071 : \"fsgldiv%.b %2,%0\");
3072 }")
3074 (define_insn ""
3075 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3076 (div:SF (match_operand:SF 1 "general_operand" "0")
3077 (match_operand:SF 2 "general_operand" "fdmF")))]
3078 "TARGET_68881"
3079 "*
3080 {
3081 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3082 return (TARGET_68040_ONLY
3083 ? \"fsdiv%.x %2,%0\"
3084 : \"fsgldiv%.x %2,%0\");
3085 return (TARGET_68040_ONLY
3086 ? \"fsdiv%.s %f2,%0\"
3087 : \"fsgldiv%.s %f2,%0\");
3088 }")
3089 \f
3090 ;; Remainder instructions.
3092 (define_expand "divmodsi4"
3093 [(parallel
3094 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3095 (div:SI (match_operand:SI 1 "general_operand" "")
3096 (match_operand:SI 2 "general_src_operand" "")))
3097 (set (match_operand:SI 3 "nonimmediate_operand" "")
3098 (mod:SI (match_dup 1) (match_dup 2)))])]
3099 "TARGET_68020 || TARGET_CF_HWDIV"
3100 "")
3102 (define_insn ""
3103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3104 (div:SI (match_operand:SI 1 "general_operand" "0")
3105 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3106 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3107 (mod:SI (match_dup 1) (match_dup 2)))]
3108 "TARGET_CF_HWDIV"
3109 "*
3110 {
3111 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3112 return \"divs%.l %2,%0\";
3113 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3114 return \"rems%.l %2,%3:%0\";
3115 else
3116 return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
3117 }")
3119 (define_insn ""
3120 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3121 (div:SI (match_operand:SI 1 "general_operand" "0")
3122 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3123 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3124 (mod:SI (match_dup 1) (match_dup 2)))]
3125 "TARGET_68020"
3126 "*
3127 {
3128 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3129 return \"divs%.l %2,%0\";
3130 else
3131 return \"divsl%.l %2,%3:%0\";
3132 }")
3134 (define_expand "udivmodsi4"
3135 [(parallel
3136 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3137 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3138 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3139 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3140 (umod:SI (match_dup 1) (match_dup 2)))])]
3141 "TARGET_68020 || TARGET_CF_HWDIV"
3142 "")
3144 (define_insn ""
3145 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3146 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3147 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3148 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3149 (umod:SI (match_dup 1) (match_dup 2)))]
3150 "TARGET_CF_HWDIV"
3151 "*
3152 {
3153 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3154 return \"divu%.l %2,%0\";
3155 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3156 return \"remu%.l %2,%3:%0\";
3157 else
3158 return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
3159 }")
3161 (define_insn ""
3162 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3163 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3164 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3165 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3166 (umod:SI (match_dup 1) (match_dup 2)))]
3167 "TARGET_68020 && !TARGET_COLDFIRE"
3168 "*
3169 {
3170 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3171 return \"divu%.l %2,%0\";
3172 else
3173 return \"divul%.l %2,%3:%0\";
3174 }")
3176 (define_insn "divmodhi4"
3177 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3178 (div:HI (match_operand:HI 1 "general_operand" "0")
3179 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3180 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3181 (mod:HI (match_dup 1) (match_dup 2)))]
3182 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3183 "*
3184 {
3185 #ifdef MOTOROLA
3186 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3187 #else
3188 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3189 #endif
3190 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3191 {
3192 CC_STATUS_INIT;
3193 return \"move%.l %0,%3\;swap %3\";
3194 }
3195 else
3196 return \"\";
3197 }")
3199 (define_insn "udivmodhi4"
3200 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3201 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3202 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3203 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3204 (umod:HI (match_dup 1) (match_dup 2)))]
3205 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3206 "*
3207 {
3208 #ifdef MOTOROLA
3209 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3210 #else
3211 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3212 #endif
3213 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3214 {
3215 CC_STATUS_INIT;
3216 return \"move%.l %0,%3\;swap %3\";
3217 }
3218 else
3219 return \"\";
3220 }")
3221 \f
3222 ;; logical-and instructions
3224 ;; "anddi3" is mainly here to help combine().
3225 (define_insn "anddi3"
3226 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3227 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3228 (match_operand:DI 2 "general_operand" "dn,don")))]
3229 "!TARGET_COLDFIRE"
3230 "*
3231 {
3232 CC_STATUS_INIT;
3233 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3234 if (CONSTANT_P (operands[2]))
3235 {
3236 rtx hi, lo;
3238 split_double (operands[2], &hi, &lo);
3240 switch (INTVAL (hi))
3241 {
3242 case 0 :
3243 output_asm_insn (\"clr%.l %0\", operands);
3244 break;
3245 case -1 :
3246 break;
3247 default :
3248 {
3249 rtx xoperands[3];
3251 xoperands[0] = operands[0];
3252 xoperands[2] = hi;
3253 output_asm_insn (output_andsi3 (xoperands), xoperands);
3254 }
3255 }
3256 if (GET_CODE (operands[0]) == REG)
3257 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3258 else
3259 operands[0] = adjust_address (operands[0], SImode, 4);
3260 switch (INTVAL (lo))
3261 {
3262 case 0 :
3263 output_asm_insn (\"clr%.l %0\", operands);
3264 break;
3265 case -1 :
3266 break;
3267 default :
3268 {
3269 rtx xoperands[3];
3271 xoperands[0] = operands[0];
3272 xoperands[2] = lo;
3273 output_asm_insn (output_andsi3 (xoperands), xoperands);
3274 }
3275 }
3276 return \"\";
3277 }
3278 if (GET_CODE (operands[0]) != REG)
3279 {
3280 operands[1] = adjust_address (operands[0], SImode, 4);
3281 return \"and%.l %2,%0\;and%.l %R2,%1\";
3282 }
3283 if (GET_CODE (operands[2]) != REG)
3284 {
3285 operands[1] = adjust_address (operands[2], SImode, 4);
3286 return \"and%.l %2,%0\;and%.l %1,%R0\";
3287 }
3288 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3289 }")
3291 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3292 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3293 ;; can't allocate pseudos into it.
3295 (define_expand "andsi3"
3296 [(set (match_operand:SI 0 "not_sp_operand" "")
3297 (and:SI (match_operand:SI 1 "general_operand" "")
3298 (match_operand:SI 2 "general_src_operand" "")))]
3299 ""
3300 "")
3302 (define_insn "andsi3_internal"
3303 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3304 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3305 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3306 "!TARGET_COLDFIRE"
3307 "*
3308 {
3309 return output_andsi3 (operands);
3310 }")
3312 (define_insn "andsi3_5200"
3313 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3314 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3315 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3316 "TARGET_COLDFIRE"
3317 "and%.l %2,%0")
3319 (define_insn "andhi3"
3320 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3321 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3322 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3323 "!TARGET_COLDFIRE"
3324 "and%.w %2,%0")
3326 (define_insn ""
3327 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3328 (and:HI (match_dup 0)
3329 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3330 "!TARGET_COLDFIRE"
3331 "and%.w %1,%0")
3333 (define_insn ""
3334 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3335 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3336 (match_dup 0)))]
3337 "!TARGET_COLDFIRE"
3338 "and%.w %1,%0")
3340 (define_insn "andqi3"
3341 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3342 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3343 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3344 "!TARGET_COLDFIRE"
3345 "and%.b %2,%0")
3347 (define_insn ""
3348 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3349 (and:QI (match_dup 0)
3350 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3351 "!TARGET_COLDFIRE"
3352 "and%.b %1,%0")
3354 (define_insn ""
3355 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3356 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3357 (match_dup 0)))]
3358 "!TARGET_COLDFIRE"
3359 "and%.b %1,%0")
3360 \f
3361 ;; inclusive-or instructions
3363 (define_insn "iordi_zext"
3364 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3365 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3366 (match_operand:DI 2 "general_operand" "0,0")))]
3367 "!TARGET_COLDFIRE"
3368 "*
3369 {
3370 int byte_mode;
3372 CC_STATUS_INIT;
3373 if (GET_CODE (operands[0]) == REG)
3374 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3375 else
3376 operands[0] = adjust_address (operands[0], SImode, 4);
3377 if (GET_MODE (operands[1]) == SImode)
3378 return \"or%.l %1,%0\";
3379 byte_mode = (GET_MODE (operands[1]) == QImode);
3380 if (GET_CODE (operands[0]) == MEM)
3381 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3382 byte_mode ? 3 : 2);
3383 if (byte_mode)
3384 return \"or%.b %1,%0\";
3385 else
3386 return \"or%.w %1,%0\";
3387 }")
3389 ;; "iordi3" is mainly here to help combine().
3390 (define_insn "iordi3"
3391 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3392 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3393 (match_operand:DI 2 "general_operand" "dn,don")))]
3394 "!TARGET_COLDFIRE"
3395 "*
3396 {
3397 CC_STATUS_INIT;
3398 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3399 if (CONSTANT_P (operands[2]))
3400 {
3401 rtx hi, lo;
3403 split_double (operands[2], &hi, &lo);
3405 switch (INTVAL (hi))
3406 {
3407 case 0 :
3408 break;
3409 case -1 :
3410 /* FIXME : a scratch register would be welcome here if operand[0]
3411 is not a register */
3412 output_asm_insn (\"move%.l %#-1,%0\", operands);
3413 break;
3414 default :
3415 {
3416 rtx xoperands[3];
3418 xoperands[0] = operands[0];
3419 xoperands[2] = hi;
3420 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3421 }
3422 }
3423 if (GET_CODE (operands[0]) == REG)
3424 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3425 else
3426 operands[0] = adjust_address (operands[0], SImode, 4);
3427 switch (INTVAL (lo))
3428 {
3429 case 0 :
3430 break;
3431 case -1 :
3432 /* FIXME : a scratch register would be welcome here if operand[0]
3433 is not a register */
3434 output_asm_insn (\"move%.l %#-1,%0\", operands);
3435 break;
3436 default :
3437 {
3438 rtx xoperands[3];
3440 xoperands[0] = operands[0];
3441 xoperands[2] = lo;
3442 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3443 }
3444 }
3445 return \"\";
3446 }
3447 if (GET_CODE (operands[0]) != REG)
3448 {
3449 operands[1] = adjust_address (operands[0], SImode, 4);
3450 return \"or%.l %2,%0\;or%.l %R2,%1\";
3451 }
3452 if (GET_CODE (operands[2]) != REG)
3453 {
3454 operands[1] = adjust_address (operands[2], SImode, 4);
3455 return \"or%.l %2,%0\;or%.l %1,%R0\";
3456 }
3457 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3458 }")
3460 (define_expand "iorsi3"
3461 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3462 (ior:SI (match_operand:SI 1 "general_operand" "")
3463 (match_operand:SI 2 "general_src_operand" "")))]
3464 ""
3465 "")
3467 (define_insn "iorsi3_internal"
3468 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3469 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3470 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3471 "! TARGET_COLDFIRE"
3472 "*
3473 {
3474 return output_iorsi3 (operands);
3475 }")
3477 (define_insn "iorsi3_5200"
3478 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3479 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3480 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3481 "TARGET_COLDFIRE"
3482 "or%.l %2,%0")
3484 (define_insn "iorhi3"
3485 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3486 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3487 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3488 "!TARGET_COLDFIRE"
3489 "or%.w %2,%0")
3491 (define_insn ""
3492 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3493 (ior:HI (match_dup 0)
3494 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3495 "!TARGET_COLDFIRE"
3496 "or%.w %1,%0")
3498 (define_insn ""
3499 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3500 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3501 (match_dup 0)))]
3502 "!TARGET_COLDFIRE"
3503 "or%.w %1,%0")
3505 (define_insn "iorqi3"
3506 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3507 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3508 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3509 "!TARGET_COLDFIRE"
3510 "or%.b %2,%0")
3512 (define_insn ""
3513 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3514 (ior:QI (match_dup 0)
3515 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3516 "!TARGET_COLDFIRE"
3517 "or%.b %1,%0")
3519 (define_insn ""
3520 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3521 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3522 (match_dup 0)))]
3523 "!TARGET_COLDFIRE"
3524 "or%.b %1,%0")
3526 ;; On all 68k models, this makes faster code in a special case.
3527 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3529 (define_insn "iorsi_zexthi_ashl16"
3530 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3531 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3532 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3533 (const_int 16))))]
3534 ""
3535 "*
3536 {
3537 CC_STATUS_INIT;
3538 if (GET_CODE (operands[2]) != REG)
3539 operands[2] = adjust_address (operands[2], HImode, 2);
3540 if (GET_CODE (operands[2]) != REG
3541 || REGNO (operands[2]) != REGNO (operands[0]))
3542 output_asm_insn (\"move%.w %2,%0\", operands);
3543 return \"swap %0\;mov%.w %1,%0\";
3544 }")
3546 (define_insn "iorsi_zext"
3547 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3548 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3549 (match_operand:SI 2 "general_operand" "0,0")))]
3550 "!TARGET_COLDFIRE"
3551 "*
3552 {
3553 int byte_mode;
3555 CC_STATUS_INIT;
3556 byte_mode = (GET_MODE (operands[1]) == QImode);
3557 if (GET_CODE (operands[0]) == MEM)
3558 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3559 byte_mode ? 3 : 2);
3560 if (byte_mode)
3561 return \"or%.b %1,%0\";
3562 else
3563 return \"or%.w %1,%0\";
3564 }")
3565 \f
3566 ;; xor instructions
3568 ;; "xordi3" is mainly here to help combine().
3569 (define_insn "xordi3"
3570 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3571 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3572 (match_operand:DI 2 "general_operand" "dn")))]
3573 "!TARGET_COLDFIRE"
3574 "*
3575 {
3576 CC_STATUS_INIT;
3577 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3579 if (CONSTANT_P (operands[2]))
3580 {
3581 rtx hi, lo;
3583 split_double (operands[2], &hi, &lo);
3585 switch (INTVAL (hi))
3586 {
3587 case 0 :
3588 break;
3589 case -1 :
3590 output_asm_insn (\"not%.l %0\", operands);
3591 break;
3592 default :
3593 /* FIXME : a scratch register would be welcome here if
3594 -128 <= INTVAL (hi) < -1 */
3595 {
3596 rtx xoperands[3];
3598 xoperands[0] = operands[0];
3599 xoperands[2] = hi;
3600 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3601 }
3602 }
3603 if (GET_CODE (operands[0]) == REG)
3604 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3605 else
3606 operands[0] = adjust_address (operands[0], SImode, 4);
3607 switch (INTVAL (lo))
3608 {
3609 case 0 :
3610 break;
3611 case -1 :
3612 output_asm_insn (\"not%.l %0\", operands);
3613 break;
3614 default :
3615 /* FIXME : a scratch register would be welcome here if
3616 -128 <= INTVAL (lo) < -1 */
3617 operands[2] = lo;
3618 /* FIXME : this should be merged with xorsi3 */
3619 {
3620 rtx xoperands[3];
3622 xoperands[0] = operands[0];
3623 xoperands[2] = lo;
3624 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3625 }
3626 }
3627 return \"\";
3628 }
3629 if (GET_CODE (operands[0]) != REG)
3630 {
3631 operands[1] = adjust_address (operands[0], SImode, 4);
3632 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3633 }
3634 if (GET_CODE (operands[2]) != REG)
3635 {
3636 operands[1] = adjust_address (operands[2], SImode, 4);
3637 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3638 }
3639 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3640 }")
3642 (define_expand "xorsi3"
3643 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3644 (xor:SI (match_operand:SI 1 "general_operand" "")
3645 (match_operand:SI 2 "general_operand" "")))]
3646 ""
3647 "")
3649 (define_insn "xorsi3_internal"
3650 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3651 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3652 (match_operand:SI 2 "general_operand" "di,dKT")))]
3654 "!TARGET_COLDFIRE"
3655 "*
3656 {
3657 return output_xorsi3 (operands);
3658 }")
3660 (define_insn "xorsi3_5200"
3661 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3662 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3663 (match_operand:SI 2 "general_operand" "d,Ks")))]
3664 "TARGET_COLDFIRE"
3665 "eor%.l %2,%0")
3667 (define_insn "xorhi3"
3668 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3669 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3670 (match_operand:HI 2 "general_operand" "dn")))]
3671 "!TARGET_COLDFIRE"
3672 "eor%.w %2,%0")
3674 (define_insn ""
3675 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3676 (xor:HI (match_dup 0)
3677 (match_operand:HI 1 "general_operand" "dn")))]
3678 "!TARGET_COLDFIRE"
3679 "eor%.w %1,%0")
3681 (define_insn ""
3682 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3683 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3684 (match_dup 0)))]
3685 "!TARGET_COLDFIRE"
3686 "eor%.w %1,%0")
3688 (define_insn "xorqi3"
3689 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3690 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3691 (match_operand:QI 2 "general_operand" "dn")))]
3692 "!TARGET_COLDFIRE"
3693 "eor%.b %2,%0")
3695 (define_insn ""
3696 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3697 (xor:QI (match_dup 0)
3698 (match_operand:QI 1 "general_operand" "dn")))]
3699 "!TARGET_COLDFIRE"
3700 "eor%.b %1,%0")
3702 (define_insn ""
3703 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3704 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3705 (match_dup 0)))]
3706 "!TARGET_COLDFIRE"
3707 "eor%.b %1,%0")
3708 \f
3709 ;; negation instructions
3711 (define_expand "negdi2"
3712 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3713 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3714 ""
3715 "
3716 {
3717 if (TARGET_COLDFIRE)
3718 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3719 else
3720 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3721 DONE;
3722 }")
3724 (define_insn "negdi2_internal"
3725 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3726 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3727 "!TARGET_COLDFIRE"
3728 "*
3729 {
3730 if (which_alternative == 0)
3731 return \"neg%.l %0\;negx%.l %0\";
3732 if (GET_CODE (operands[0]) == REG)
3733 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3734 else
3735 operands[1] = adjust_address (operands[0], SImode, 4);
3736 if (ADDRESS_REG_P (operands[0]))
3737 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3738 else
3739 return \"neg%.l %1\;negx%.l %0\";
3740 } ")
3742 (define_insn "negdi2_5200"
3743 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3744 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3745 "TARGET_COLDFIRE"
3746 "*
3747 {
3748 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3749 return \"neg%.l %1\;negx%.l %0\";
3750 } ")
3752 (define_expand "negsi2"
3753 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3754 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3755 ""
3756 "
3757 {
3758 if (TARGET_COLDFIRE)
3759 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3760 else
3761 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3762 DONE;
3763 }")
3765 (define_insn "negsi2_internal"
3766 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3767 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3768 "!TARGET_COLDFIRE"
3769 "neg%.l %0")
3771 (define_insn "negsi2_5200"
3772 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3773 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3774 "TARGET_COLDFIRE"
3775 "neg%.l %0")
3777 (define_insn "neghi2"
3778 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3779 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3780 "!TARGET_COLDFIRE"
3781 "neg%.w %0")
3783 (define_insn ""
3784 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3785 (neg:HI (match_dup 0)))]
3786 "!TARGET_COLDFIRE"
3787 "neg%.w %0")
3789 (define_insn "negqi2"
3790 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3791 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3792 "!TARGET_COLDFIRE"
3793 "neg%.b %0")
3795 (define_insn ""
3796 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3797 (neg:QI (match_dup 0)))]
3798 "!TARGET_COLDFIRE"
3799 "neg%.b %0")
3801 ;; If using software floating point, just flip the sign bit.
3803 (define_expand "negsf2"
3804 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3805 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3806 ""
3807 "
3808 {
3809 if (!TARGET_68881)
3810 {
3811 rtx result;
3812 rtx target;
3814 target = operand_subword_force (operands[0], 0, SFmode);
3815 result = expand_binop (SImode, xor_optab,
3816 operand_subword_force (operands[1], 0, SFmode),
3817 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3818 if (result == 0)
3819 abort ();
3821 if (result != target)
3822 emit_move_insn (result, target);
3824 /* Make a place for REG_EQUAL. */
3825 emit_move_insn (operands[0], operands[0]);
3826 DONE;
3827 }
3828 }")
3830 (define_insn ""
3831 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
3832 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3833 "TARGET_68881"
3834 "*
3835 {
3836 if (DATA_REG_P (operands[0]))
3837 {
3838 operands[1] = GEN_INT (31);
3839 return \"bchg %1,%0\";
3840 }
3841 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3842 return \"f%$neg%.x %1,%0\";
3843 return \"f%$neg%.s %f1,%0\";
3844 }")
3846 (define_expand "negdf2"
3847 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3848 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3849 ""
3850 "
3851 {
3852 if (!TARGET_68881)
3853 {
3854 rtx result;
3855 rtx target;
3856 rtx insns;
3858 start_sequence ();
3859 target = operand_subword (operands[0], 0, 1, DFmode);
3860 result = expand_binop (SImode, xor_optab,
3861 operand_subword_force (operands[1], 0, DFmode),
3862 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3863 if (result == 0)
3864 abort ();
3866 if (result != target)
3867 emit_move_insn (result, target);
3869 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3870 operand_subword_force (operands[1], 1, DFmode));
3872 insns = get_insns ();
3873 end_sequence ();
3875 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3876 DONE;
3877 }
3878 }")
3880 (define_insn ""
3881 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
3882 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3883 "TARGET_68881"
3884 "*
3885 {
3886 if (DATA_REG_P (operands[0]))
3887 {
3888 operands[1] = GEN_INT (31);
3889 return \"bchg %1,%0\";
3890 }
3891 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3892 return \"f%&neg%.x %1,%0\";
3893 return \"f%&neg%.d %f1,%0\";
3894 }")
3895 \f
3896 ;; Sqrt instruction for the 68881
3898 (define_insn "sqrtsf2"
3899 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3900 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3901 "TARGET_68881"
3902 "*
3903 {
3904 if (FP_REG_P (operands[1]))
3905 return \"f%$sqrt%.x %1,%0\";
3906 else
3907 return \"f%$sqrt%.s %1,%0\";
3908 }")
3910 (define_insn "sqrtdf2"
3911 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3912 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3913 "TARGET_68881"
3914 "*
3915 {
3916 if (FP_REG_P (operands[1]))
3917 return \"f%&sqrt%.x %1,%0\";
3918 else
3919 return \"f%&sqrt%.d %1,%0\";
3920 }")
3922 ;; Absolute value instructions
3923 ;; If using software floating point, just zero the sign bit.
3925 (define_expand "abssf2"
3926 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3927 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3928 ""
3929 "
3930 {
3931 if (!TARGET_68881)
3932 {
3933 rtx result;
3934 rtx target;
3936 target = operand_subword_force (operands[0], 0, SFmode);
3937 result = expand_binop (SImode, and_optab,
3938 operand_subword_force (operands[1], 0, SFmode),
3939 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3940 if (result == 0)
3941 abort ();
3943 if (result != target)
3944 emit_move_insn (result, target);
3946 /* Make a place for REG_EQUAL. */
3947 emit_move_insn (operands[0], operands[0]);
3948 DONE;
3949 }
3950 }")
3952 (define_insn ""
3953 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3954 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3955 "TARGET_68881"
3956 "*
3957 {
3958 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3959 return \"f%$abs%.x %1,%0\";
3960 return \"f%$abs%.s %f1,%0\";
3961 }")
3963 (define_expand "absdf2"
3964 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3965 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3966 ""
3967 "
3968 {
3969 if (!TARGET_68881)
3970 {
3971 rtx result;
3972 rtx target;
3973 rtx insns;
3975 start_sequence ();
3976 target = operand_subword (operands[0], 0, 1, DFmode);
3977 result = expand_binop (SImode, and_optab,
3978 operand_subword_force (operands[1], 0, DFmode),
3979 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3980 if (result == 0)
3981 abort ();
3983 if (result != target)
3984 emit_move_insn (result, target);
3986 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3987 operand_subword_force (operands[1], 1, DFmode));
3989 insns = get_insns ();
3990 end_sequence ();
3992 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3993 DONE;
3994 }
3995 }")
3997 (define_insn ""
3998 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3999 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4000 "TARGET_68881"
4001 "*
4002 {
4003 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4004 return \"f%&abs%.x %1,%0\";
4005 return \"f%&abs%.d %f1,%0\";
4006 }")
4007 \f
4008 ;; one complement instructions
4010 ;; "one_cmpldi2" is mainly here to help combine().
4011 (define_insn "one_cmpldi2"
4012 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4013 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4014 "!TARGET_COLDFIRE"
4015 "*
4016 {
4017 CC_STATUS_INIT;
4018 if (GET_CODE (operands[0]) == REG)
4019 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4020 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4021 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4022 operands[1] = operands[0];
4023 else
4024 operands[1] = adjust_address (operands[0], SImode, 4);
4025 return \"not%.l %1\;not%.l %0\";
4026 }")
4028 (define_expand "one_cmplsi2"
4029 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4030 (not:SI (match_operand:SI 1 "general_operand" "")))]
4031 ""
4032 "
4033 {
4034 if (TARGET_COLDFIRE)
4035 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4036 else
4037 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4038 DONE;
4039 }")
4041 (define_insn "one_cmplsi2_internal"
4042 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4043 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4044 "!TARGET_COLDFIRE"
4045 "not%.l %0")
4047 (define_insn "one_cmplsi2_5200"
4048 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4049 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4050 "TARGET_COLDFIRE"
4051 "not%.l %0")
4053 (define_insn "one_cmplhi2"
4054 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4055 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4056 "!TARGET_COLDFIRE"
4057 "not%.w %0")
4059 (define_insn ""
4060 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4061 (not:HI (match_dup 0)))]
4062 "!TARGET_COLDFIRE"
4063 "not%.w %0")
4065 (define_insn "one_cmplqi2"
4066 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4067 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4068 "!TARGET_COLDFIRE"
4069 "not%.b %0")
4071 (define_insn ""
4072 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4073 (not:QI (match_dup 0)))]
4074 "!TARGET_COLDFIRE"
4075 "not%.b %0")
4076 \f
4077 ;; arithmetic shift instructions
4078 ;; We don't need the shift memory by 1 bit instruction
4080 (define_insn "ashldi_extsi"
4081 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4082 (ashift:DI
4083 (match_operator:DI 2 "extend_operator"
4084 [(match_operand:SI 1 "general_operand" "rm")])
4085 (const_int 32)))]
4086 ""
4087 "*
4088 {
4089 CC_STATUS_INIT;
4090 if (GET_CODE (operands[0]) == REG)
4091 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4092 else
4093 operands[2] = adjust_address (operands[0], SImode, 4);
4094 if (ADDRESS_REG_P (operands[0]))
4095 return \"move%.l %1,%0\;sub%.l %2,%2\";
4096 else
4097 return \"move%.l %1,%0\;clr%.l %2\";
4098 } ")
4100 (define_insn "ashldi_sexthi"
4101 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4102 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4103 (const_int 32)))
4104 (clobber (match_scratch:SI 2 "=a,X"))]
4105 ""
4106 "*
4107 {
4108 CC_STATUS_INIT;
4109 if (GET_CODE (operands[0]) == MEM)
4110 {
4111 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4112 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4113 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4114 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4115 else
4116 {
4117 operands[3] = adjust_address (operands[0], SImode, 4);
4118 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4119 }
4120 }
4121 else if (DATA_REG_P (operands[0]))
4122 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4123 else
4124 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4125 } ")
4127 (define_insn "ashldi_const32"
4128 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4129 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4130 (const_int 32)))]
4131 ""
4132 "*
4133 {
4134 CC_STATUS_INIT;
4135 if (GET_CODE (operands[1]) == REG)
4136 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4137 else
4138 operands[3] = adjust_address (operands[1], SImode, 4);
4139 if (GET_CODE (operands[0]) == REG)
4140 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4141 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4142 return \"clr%.l %0\;move%.l %3,%0\";
4143 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4144 return \"move%.l %3,%0\;clr%.l %0\";
4145 else
4146 operands[2] = adjust_address (operands[0], SImode, 4);
4147 if (ADDRESS_REG_P (operands[2]))
4148 return \"move%.l %3,%0\;sub%.l %2,%2\";
4149 else
4150 return \"move%.l %3,%0\;clr%.l %2\";
4151 } ")
4153 ;; The predicate below must be general_operand, because ashldi3 allows that
4154 (define_insn "ashldi_const"
4155 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4156 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4157 (match_operand 2 "const_int_operand" "n")))]
4158 "(!TARGET_COLDFIRE
4159 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4160 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4161 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4162 "*
4163 {
4164 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4165 if (INTVAL (operands[2]) == 1)
4166 return \"add%.l %1,%1\;addx%.l %0,%0\";
4167 else if (INTVAL (operands[2]) == 8)
4168 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4169 else if (INTVAL (operands[2]) == 16)
4170 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4171 else if (INTVAL (operands[2]) == 48)
4172 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4173 else if (INTVAL (operands[2]) == 2)
4174 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4175 else if (INTVAL (operands[2]) == 3)
4176 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4177 else /* 32 < INTVAL (operands[2]) <= 63 */
4178 {
4179 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4180 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4181 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4182 return \"mov%.l %1,%0\;moveq %#0,%1\";
4183 }
4184 } ")
4186 (define_expand "ashldi3"
4187 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4188 (ashift:DI (match_operand:DI 1 "general_operand" "")
4189 (match_operand 2 "const_int_operand" "")))]
4190 "!TARGET_COLDFIRE"
4191 "
4192 {
4193 /* ??? This is a named pattern like this is not allowed to FAIL based
4194 on its operands. */
4195 if (GET_CODE (operands[2]) != CONST_INT
4196 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4197 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4198 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4199 FAIL;
4200 } ")
4202 ;; On most 68k models, this makes faster code in a special case.
4204 (define_insn "ashlsi_16"
4205 [(set (match_operand:SI 0 "register_operand" "=d")
4206 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4207 (const_int 16)))]
4208 "!TARGET_68060"
4209 "*
4210 {
4211 CC_STATUS_INIT;
4212 return \"swap %0\;clr%.w %0\";
4213 }")
4215 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4216 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4218 ;; On the 68000, this makes faster code in a special case.
4220 (define_insn "ashlsi_17_24"
4221 [(set (match_operand:SI 0 "register_operand" "=d")
4222 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4223 (match_operand:SI 2 "const_int_operand" "n")))]
4224 "(! TARGET_68020 && !TARGET_COLDFIRE
4225 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4226 "*
4227 {
4228 CC_STATUS_INIT;
4230 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4231 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4232 }")
4234 (define_insn "ashlsi3"
4235 [(set (match_operand:SI 0 "register_operand" "=d")
4236 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4237 (match_operand:SI 2 "general_operand" "dI")))]
4238 ""
4239 "*
4240 {
4241 if (operands[2] == const1_rtx)
4242 {
4243 cc_status.flags = CC_NO_OVERFLOW;
4244 return \"add%.l %0,%0\";
4245 }
4246 return \"lsl%.l %2,%0\";
4247 }")
4249 (define_insn "ashlhi3"
4250 [(set (match_operand:HI 0 "register_operand" "=d")
4251 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4252 (match_operand:HI 2 "general_operand" "dI")))]
4253 "!TARGET_COLDFIRE"
4254 "lsl%.w %2,%0")
4256 (define_insn ""
4257 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4258 (ashift:HI (match_dup 0)
4259 (match_operand:HI 1 "general_operand" "dI")))]
4260 "!TARGET_COLDFIRE"
4261 "lsl%.w %1,%0")
4263 (define_insn "ashlqi3"
4264 [(set (match_operand:QI 0 "register_operand" "=d")
4265 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4266 (match_operand:QI 2 "general_operand" "dI")))]
4267 "!TARGET_COLDFIRE"
4268 "lsl%.b %2,%0")
4270 (define_insn ""
4271 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4272 (ashift:QI (match_dup 0)
4273 (match_operand:QI 1 "general_operand" "dI")))]
4274 "!TARGET_COLDFIRE"
4275 "lsl%.b %1,%0")
4277 ;; On most 68k models, this makes faster code in a special case.
4279 (define_insn "ashrsi_16"
4280 [(set (match_operand:SI 0 "register_operand" "=d")
4281 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4282 (const_int 16)))]
4283 "!TARGET_68060"
4284 "swap %0\;ext%.l %0")
4286 ;; On the 68000, this makes faster code in a special case.
4288 (define_insn ""
4289 [(set (match_operand:SI 0 "register_operand" "=d")
4290 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4291 (match_operand:SI 2 "const_int_operand" "n")))]
4292 "(! TARGET_68020 && !TARGET_COLDFIRE
4293 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4294 "*
4295 {
4296 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4297 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4298 }")
4300 (define_insn "subreghi1ashrdi_const32"
4301 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4302 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4303 (const_int 32)) 6))]
4304 ""
4305 "*
4306 {
4307 if (GET_CODE (operands[1]) != REG)
4308 operands[1] = adjust_address (operands[1], HImode, 2);
4309 return \"move%.w %1,%0\";
4310 } ")
4312 (define_insn "subregsi1ashrdi_const32"
4313 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4314 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4315 (const_int 32)) 4))]
4316 ""
4317 "*
4318 {
4319 return \"move%.l %1,%0\";
4320 } ")
4322 (define_insn "ashrdi_const32"
4323 [(set (match_operand:DI 0 "register_operand" "=d")
4324 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4325 (const_int 32)))]
4326 ""
4327 "*
4328 {
4329 CC_STATUS_INIT;
4330 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4331 if (TARGET_68020)
4332 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4333 else
4334 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4335 } ")
4337 (define_insn "ashrdi_const32_mem"
4338 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4339 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4340 (const_int 32)))
4341 (clobber (match_scratch:SI 2 "=d,d"))]
4342 ""
4343 "*
4344 {
4345 CC_STATUS_INIT;
4346 if (which_alternative == 1)
4347 operands[3] = operands[0];
4348 else
4349 operands[3] = adjust_address (operands[0], SImode, 4);
4350 if (TARGET_68020)
4351 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4352 else
4353 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4354 } ")
4356 ;; The predicate below must be general_operand, because ashrdi3 allows that
4357 (define_insn "ashrdi_const"
4358 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4359 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4360 (match_operand 2 "const_int_operand" "n")))]
4361 "(!TARGET_COLDFIRE
4362 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4363 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4364 || INTVAL (operands[2]) == 31
4365 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4366 "*
4367 {
4368 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4369 if (INTVAL (operands[2]) == 63)
4370 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4371 CC_STATUS_INIT;
4372 if (INTVAL (operands[2]) == 1)
4373 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4374 else if (INTVAL (operands[2]) == 8)
4375 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4376 else if (INTVAL (operands[2]) == 16)
4377 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4378 else if (INTVAL (operands[2]) == 48)
4379 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4380 else if (INTVAL (operands[2]) == 31)
4381 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4382 else if (INTVAL (operands[2]) == 2)
4383 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4384 else if (INTVAL (operands[2]) == 3)
4385 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4386 else /* 32 < INTVAL (operands[2]) <= 63 */
4387 {
4388 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4389 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4390 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4391 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4392 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4393 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4394 }
4395 } ")
4397 (define_expand "ashrdi3"
4398 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4399 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4400 (match_operand 2 "const_int_operand" "")))]
4401 "!TARGET_COLDFIRE"
4402 "
4403 {
4404 /* ??? This is a named pattern like this is not allowed to FAIL based
4405 on its operands. */
4406 if (GET_CODE (operands[2]) != CONST_INT
4407 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4408 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4409 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4410 FAIL;
4411 } ")
4413 ;; On all 68k models, this makes faster code in a special case.
4415 (define_insn "ashrsi_31"
4416 [(set (match_operand:SI 0 "register_operand" "=d")
4417 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4418 (const_int 31)))]
4419 ""
4420 "*
4421 {
4422 return \"add%.l %0,%0\;subx%.l %0,%0\";
4423 }")
4425 (define_insn "ashrsi3"
4426 [(set (match_operand:SI 0 "register_operand" "=d")
4427 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4428 (match_operand:SI 2 "general_operand" "dI")))]
4429 ""
4430 "asr%.l %2,%0")
4432 (define_insn "ashrhi3"
4433 [(set (match_operand:HI 0 "register_operand" "=d")
4434 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4435 (match_operand:HI 2 "general_operand" "dI")))]
4436 "!TARGET_COLDFIRE"
4437 "asr%.w %2,%0")
4439 (define_insn ""
4440 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4441 (ashiftrt:HI (match_dup 0)
4442 (match_operand:HI 1 "general_operand" "dI")))]
4443 "!TARGET_COLDFIRE"
4444 "asr%.w %1,%0")
4446 (define_insn "ashrqi3"
4447 [(set (match_operand:QI 0 "register_operand" "=d")
4448 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4449 (match_operand:QI 2 "general_operand" "dI")))]
4450 "!TARGET_COLDFIRE"
4451 "asr%.b %2,%0")
4453 (define_insn ""
4454 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4455 (ashiftrt:QI (match_dup 0)
4456 (match_operand:QI 1 "general_operand" "dI")))]
4457 "!TARGET_COLDFIRE"
4458 "asr%.b %1,%0")
4459 \f
4460 ;; logical shift instructions
4462 ;; commented out because of reload problems in 950612-1.c
4463 ;;(define_insn ""
4464 ;; [(set (cc0)
4465 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4466 ;; (const_int 32)) 4))
4467 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4468 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4469 ;; (const_int 32)) 4))]
4470 ;; ""
4471 ;; "*
4472 ;;{
4473 ;; return \"move%.l %0,%1\";
4474 ;;} ")
4475 ;;
4476 ;;(define_insn ""
4477 ;; [(set (cc0)
4478 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4479 ;; (const_int 32)) 0))
4480 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4481 ;; (lshiftrt:DI (match_dup 0)
4482 ;; (const_int 32)))]
4483 ;; ""
4484 ;; "*
4485 ;;{
4486 ;; if (GET_CODE (operands[1]) == REG)
4487 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4488 ;; else
4489 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4490 ;; return \"move%.l %0,%2\;clr%.l %1\";
4491 ;;} ")
4493 (define_insn "subreg1lshrdi_const32"
4494 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4495 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4496 (const_int 32)) 4))]
4497 ""
4498 "*
4499 {
4500 return \"move%.l %1,%0\";
4501 } ")
4503 (define_insn "lshrdi_const32"
4504 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4505 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4506 (const_int 32)))]
4507 ""
4508 "*
4509 {
4510 CC_STATUS_INIT;
4511 if (which_alternative == 1)
4512 return \"move%.l %1,%0\;clr%.l %0\";
4513 if (which_alternative == 2)
4514 return \"clr%.l %0\;move%.l %1,%0\";
4515 if (GET_CODE (operands[0]) == REG)
4516 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4517 else
4518 operands[2] = adjust_address (operands[0], SImode, 4);
4519 if (GET_CODE (operands[1]) == REG)
4520 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4521 else
4522 operands[3] = adjust_address (operands[1], SImode, 4);
4523 if (ADDRESS_REG_P (operands[0]))
4524 return \"move%.l %1,%2\;sub%.l %0,%0\";
4525 else
4526 return \"move%.l %1,%2\;clr%.l %0\";
4527 } ")
4529 ;; The predicate below must be general_operand, because lshrdi3 allows that
4530 (define_insn "lshrdi_const"
4531 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4532 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4533 (match_operand 2 "const_int_operand" "n")))]
4534 "(!TARGET_COLDFIRE
4535 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4536 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4537 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4538 "*
4539 {
4540 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4541 if (INTVAL (operands[2]) == 63)
4542 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4543 CC_STATUS_INIT;
4544 if (INTVAL (operands[2]) == 1)
4545 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4546 else if (INTVAL (operands[2]) == 8)
4547 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4548 else if (INTVAL (operands[2]) == 16)
4549 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4550 else if (INTVAL (operands[2]) == 48)
4551 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4552 else if (INTVAL (operands[2]) == 2)
4553 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4554 else if (INTVAL (operands[2]) == 3)
4555 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4556 else /* 32 < INTVAL (operands[2]) <= 63 */
4557 {
4558 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4559 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4560 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4561 return \"mov%.l %0,%1\;moveq %#0,%0\";
4562 }
4563 } ")
4565 (define_expand "lshrdi3"
4566 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4567 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4568 (match_operand 2 "const_int_operand" "")))]
4569 "!TARGET_COLDFIRE"
4570 "
4571 {
4572 /* ??? This is a named pattern like this is not allowed to FAIL based
4573 on its operands. */
4574 if (GET_CODE (operands[2]) != CONST_INT
4575 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4576 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4577 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4578 FAIL;
4579 } ")
4581 ;; On all 68k models, this makes faster code in a special case.
4583 (define_insn "lshrsi_31"
4584 [(set (match_operand:SI 0 "register_operand" "=d")
4585 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4586 (const_int 31)))]
4587 ""
4588 "*
4589 {
4590 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4591 }")
4593 ;; On most 68k models, this makes faster code in a special case.
4595 (define_insn "lshrsi_16"
4596 [(set (match_operand:SI 0 "register_operand" "=d")
4597 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4598 (const_int 16)))]
4599 "!TARGET_68060"
4600 "*
4601 {
4602 CC_STATUS_INIT;
4603 return \"clr%.w %0\;swap %0\";
4604 }")
4606 ;; On the 68000, this makes faster code in a special case.
4608 (define_insn "lshrsi_17_24"
4609 [(set (match_operand:SI 0 "register_operand" "=d")
4610 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4611 (match_operand:SI 2 "const_int_operand" "n")))]
4612 "(! TARGET_68020 && !TARGET_COLDFIRE
4613 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4614 "*
4615 {
4616 /* I think lsr%.w sets the CC properly. */
4617 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4618 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4619 }")
4621 (define_insn "lshrsi3"
4622 [(set (match_operand:SI 0 "register_operand" "=d")
4623 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4624 (match_operand:SI 2 "general_operand" "dI")))]
4625 ""
4626 "lsr%.l %2,%0")
4628 (define_insn "lshrhi3"
4629 [(set (match_operand:HI 0 "register_operand" "=d")
4630 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4631 (match_operand:HI 2 "general_operand" "dI")))]
4632 "!TARGET_COLDFIRE"
4633 "lsr%.w %2,%0")
4635 (define_insn ""
4636 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4637 (lshiftrt:HI (match_dup 0)
4638 (match_operand:HI 1 "general_operand" "dI")))]
4639 "!TARGET_COLDFIRE"
4640 "lsr%.w %1,%0")
4642 (define_insn "lshrqi3"
4643 [(set (match_operand:QI 0 "register_operand" "=d")
4644 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4645 (match_operand:QI 2 "general_operand" "dI")))]
4646 "!TARGET_COLDFIRE"
4647 "lsr%.b %2,%0")
4649 (define_insn ""
4650 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4651 (lshiftrt:QI (match_dup 0)
4652 (match_operand:QI 1 "general_operand" "dI")))]
4653 "!TARGET_COLDFIRE"
4654 "lsr%.b %1,%0")
4655 \f
4656 ;; rotate instructions
4658 (define_insn "rotlsi3"
4659 [(set (match_operand:SI 0 "register_operand" "=d")
4660 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4661 (match_operand:SI 2 "general_operand" "dINO")))]
4662 "!TARGET_COLDFIRE"
4663 "*
4664 {
4665 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4666 return \"swap %0\";
4667 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4668 {
4669 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4670 return \"ror%.l %2,%0\";
4671 }
4672 else
4673 return \"rol%.l %2,%0\";
4674 }")
4676 (define_insn "rotlhi3"
4677 [(set (match_operand:HI 0 "register_operand" "=d")
4678 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4679 (match_operand:HI 2 "general_operand" "dIP")))]
4680 "!TARGET_COLDFIRE"
4681 "*
4682 {
4683 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4684 {
4685 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4686 return \"ror%.w %2,%0\";
4687 }
4688 else
4689 return \"rol%.w %2,%0\";
4690 }")
4692 (define_insn ""
4693 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4694 (rotate:HI (match_dup 0)
4695 (match_operand:HI 1 "general_operand" "dIP")))]
4696 "!TARGET_COLDFIRE"
4697 "*
4698 {
4699 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4700 {
4701 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4702 return \"ror%.w %2,%0\";
4703 }
4704 else
4705 return \"rol%.w %2,%0\";
4706 }")
4708 (define_insn "rotlqi3"
4709 [(set (match_operand:QI 0 "register_operand" "=d")
4710 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4711 (match_operand:QI 2 "general_operand" "dI")))]
4712 "!TARGET_COLDFIRE"
4713 "*
4714 {
4715 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4716 {
4717 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4718 return \"ror%.b %2,%0\";
4719 }
4720 else
4721 return \"rol%.b %2,%0\";
4722 }")
4724 (define_insn ""
4725 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4726 (rotate:QI (match_dup 0)
4727 (match_operand:QI 1 "general_operand" "dI")))]
4728 "!TARGET_COLDFIRE"
4729 "*
4730 {
4731 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4732 {
4733 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4734 return \"ror%.b %2,%0\";
4735 }
4736 else
4737 return \"rol%.b %2,%0\";
4738 }")
4740 (define_insn "rotrsi3"
4741 [(set (match_operand:SI 0 "register_operand" "=d")
4742 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4743 (match_operand:SI 2 "general_operand" "dI")))]
4744 "!TARGET_COLDFIRE"
4745 "ror%.l %2,%0")
4747 (define_insn "rotrhi3"
4748 [(set (match_operand:HI 0 "register_operand" "=d")
4749 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4750 (match_operand:HI 2 "general_operand" "dI")))]
4751 "!TARGET_COLDFIRE"
4752 "ror%.w %2,%0")
4754 (define_insn ""
4755 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4756 (rotatert:HI (match_dup 0)
4757 (match_operand:HI 1 "general_operand" "dI")))]
4758 "!TARGET_COLDFIRE"
4759 "ror%.w %1,%0")
4761 (define_insn "rotrqi3"
4762 [(set (match_operand:QI 0 "register_operand" "=d")
4763 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4764 (match_operand:QI 2 "general_operand" "dI")))]
4765 "!TARGET_COLDFIRE"
4766 "ror%.b %2,%0")
4768 (define_insn ""
4769 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4770 (rotatert:QI (match_dup 0)
4771 (match_operand:QI 1 "general_operand" "dI")))]
4772 "!TARGET_COLDFIRE"
4773 "ror%.b %1,%0")
4774 \f
4776 ;; Bit set/clear in memory byte.
4778 ;; set bit, bit number is int
4779 (define_insn "bsetmemqi"
4780 [(set (match_operand:QI 0 "memory_operand" "+m")
4781 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4782 (match_operand:SI 1 "general_operand" "d")) 3)
4783 (match_dup 0)))]
4784 ""
4785 "*
4786 {
4787 CC_STATUS_INIT;
4788 return \"bset %1,%0\";
4789 }")
4791 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4792 (define_insn ""
4793 [(set (match_operand:QI 0 "memory_operand" "+m")
4794 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4795 (match_operator:SI 2 "extend_operator"
4796 [(match_operand 1 "general_operand" "d")])) 3)
4797 (match_dup 0)))]
4798 ""
4799 "*
4800 {
4801 CC_STATUS_INIT;
4802 return \"bset %1,%0\";
4803 }")
4805 ;; clear bit, bit number is int
4806 (define_insn "bclrmemqi"
4807 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4808 (const_int 1)
4809 (minus:SI (const_int 7)
4810 (match_operand:SI 1 "general_operand" "d")))
4811 (const_int 0))]
4812 ""
4813 "*
4814 {
4815 CC_STATUS_INIT;
4816 return \"bclr %1,%0\";
4817 }")
4819 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4820 (define_insn ""
4821 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4822 (const_int 1)
4823 (minus:SI (const_int 7)
4824 (match_operator:SI 2 "extend_operator"
4825 [(match_operand 1 "general_operand" "d")])))
4826 (const_int 0))]
4827 ""
4828 "*
4829 {
4830 CC_STATUS_INIT;
4831 return \"bclr %1,%0\";
4832 }")
4834 ;; Special cases of bit-field insns which we should
4835 ;; recognize in preference to the general case.
4836 ;; These handle aligned 8-bit and 16-bit fields,
4837 ;; which can usually be done with move instructions.
4839 ;
4840 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4841 ; alignment of structure members is specified.
4842 ;
4843 ; The move is allowed to be odd byte aligned, because that's still faster
4844 ; than an odd byte aligned bit-field instruction.
4845 ;
4846 (define_insn ""
4847 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4848 (const_int 32)
4849 (match_operand:SI 1 "const_int_operand" "n"))
4850 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4851 "TARGET_68020 && TARGET_BITFIELD
4852 && (INTVAL (operands[1]) % 8) == 0
4853 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4854 "*
4855 {
4856 operands[0]
4857 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4859 return \"move%.l %2,%0\";
4860 }")
4862 (define_insn ""
4863 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4864 (match_operand:SI 1 "const_int_operand" "n")
4865 (match_operand:SI 2 "const_int_operand" "n"))
4866 (match_operand:SI 3 "register_operand" "d"))]
4867 "TARGET_68020 && TARGET_BITFIELD
4868 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4869 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4870 && (GET_CODE (operands[0]) == REG
4871 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4872 "*
4873 {
4874 if (REG_P (operands[0]))
4875 {
4876 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4877 return \"bfins %3,%0{%b2:%b1}\";
4878 }
4879 else
4880 operands[0] = adjust_address (operands[0],
4881 INTVAL (operands[1]) == 8 ? QImode : HImode,
4882 INTVAL (operands[2]) / 8);
4884 if (GET_CODE (operands[3]) == MEM)
4885 operands[3] = adjust_address (operands[3],
4886 INTVAL (operands[1]) == 8 ? QImode : HImode,
4887 (32 - INTVAL (operands[1])) / 8);
4889 if (INTVAL (operands[1]) == 8)
4890 return \"move%.b %3,%0\";
4891 return \"move%.w %3,%0\";
4892 }")
4895 ;
4896 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4897 ; alignment of structure members is specified.
4898 ;
4899 ; The move is allowed to be odd byte aligned, because that's still faster
4900 ; than an odd byte aligned bit-field instruction.
4901 ;
4902 (define_insn ""
4903 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4904 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4905 (const_int 32)
4906 (match_operand:SI 2 "const_int_operand" "n")))]
4907 "TARGET_68020 && TARGET_BITFIELD
4908 && (INTVAL (operands[2]) % 8) == 0
4909 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4910 "*
4911 {
4912 operands[1]
4913 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4915 return \"move%.l %1,%0\";
4916 }")
4918 (define_insn ""
4919 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4920 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4921 (match_operand:SI 2 "const_int_operand" "n")
4922 (match_operand:SI 3 "const_int_operand" "n")))]
4923 "TARGET_68020 && TARGET_BITFIELD
4924 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4925 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4926 && (GET_CODE (operands[1]) == REG
4927 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4928 "*
4929 {
4930 cc_status.flags |= CC_NOT_NEGATIVE;
4931 if (REG_P (operands[1]))
4932 {
4933 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4934 return \"bfextu %1{%b3:%b2},%0\";
4935 }
4936 else
4937 operands[1]
4938 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4940 output_asm_insn (\"clr%.l %0\", operands);
4941 if (GET_CODE (operands[0]) == MEM)
4942 operands[0] = adjust_address (operands[0],
4943 INTVAL (operands[2]) == 8 ? QImode : HImode,
4944 (32 - INTVAL (operands[1])) / 8);
4946 if (INTVAL (operands[2]) == 8)
4947 return \"move%.b %1,%0\";
4948 return \"move%.w %1,%0\";
4949 }")
4951 ;
4952 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4953 ; alignment of structure members is specified.
4954 ;
4955 ; The move is allowed to be odd byte aligned, because that's still faster
4956 ; than an odd byte aligned bit-field instruction.
4957 ;
4958 (define_insn ""
4959 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4960 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4961 (const_int 32)
4962 (match_operand:SI 2 "const_int_operand" "n")))]
4963 "TARGET_68020 && TARGET_BITFIELD
4964 && (INTVAL (operands[2]) % 8) == 0
4965 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4966 "*
4967 {
4968 operands[1]
4969 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4971 return \"move%.l %1,%0\";
4972 }")
4974 (define_insn ""
4975 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4976 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4977 (match_operand:SI 2 "const_int_operand" "n")
4978 (match_operand:SI 3 "const_int_operand" "n")))]
4979 "TARGET_68020 && TARGET_BITFIELD
4980 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4981 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4982 && (GET_CODE (operands[1]) == REG
4983 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4984 "*
4985 {
4986 if (REG_P (operands[1]))
4987 {
4988 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4989 return \"bfexts %1{%b3:%b2},%0\";
4990 }
4991 else
4992 operands[1]
4993 = adjust_address (operands[1],
4994 INTVAL (operands[2]) == 8 ? QImode : HImode,
4995 INTVAL (operands[3]) / 8);
4997 if (INTVAL (operands[2]) == 8)
4998 return \"move%.b %1,%0\;extb%.l %0\";
4999 return \"move%.w %1,%0\;ext%.l %0\";
5000 }")
5001 \f
5002 ;; Bit-field instructions, general cases.
5003 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5004 ;; so that its address is reloaded.
5006 (define_expand "extv"
5007 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5008 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5009 (match_operand:SI 2 "general_operand" "")
5010 (match_operand:SI 3 "general_operand" "")))]
5011 "TARGET_68020 && TARGET_BITFIELD"
5012 "")
5014 (define_insn ""
5015 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5016 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5017 (match_operand:SI 2 "general_operand" "di")
5018 (match_operand:SI 3 "general_operand" "di")))]
5019 "TARGET_68020 && TARGET_BITFIELD"
5020 "bfexts %1{%b3:%b2},%0")
5022 (define_expand "extzv"
5023 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5024 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5025 (match_operand:SI 2 "general_operand" "")
5026 (match_operand:SI 3 "general_operand" "")))]
5027 "TARGET_68020 && TARGET_BITFIELD"
5028 "")
5030 (define_insn ""
5031 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
5032 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5033 (match_operand:SI 2 "general_operand" "di,di")
5034 (match_operand:SI 3 "general_operand" "di,di")))]
5035 "TARGET_68020 && TARGET_BITFIELD"
5036 "*
5037 {
5038 if (GET_CODE (operands[2]) == CONST_INT)
5039 {
5040 if (INTVAL (operands[2]) != 32)
5041 cc_status.flags |= CC_NOT_NEGATIVE;
5042 }
5043 else
5044 {
5045 CC_STATUS_INIT;
5046 }
5047 return \"bfextu %1{%b3:%b2},%0\";
5048 }")
5050 (define_insn ""
5051 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5052 (match_operand:SI 1 "general_operand" "di")
5053 (match_operand:SI 2 "general_operand" "di"))
5054 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5055 (match_operand 3 "const_int_operand" "n")))]
5056 "TARGET_68020 && TARGET_BITFIELD
5057 && (INTVAL (operands[3]) == -1
5058 || (GET_CODE (operands[1]) == CONST_INT
5059 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5060 "*
5061 {
5062 CC_STATUS_INIT;
5063 return \"bfchg %0{%b2:%b1}\";
5064 }")
5066 (define_insn ""
5067 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5068 (match_operand:SI 1 "general_operand" "di")
5069 (match_operand:SI 2 "general_operand" "di"))
5070 (const_int 0))]
5071 "TARGET_68020 && TARGET_BITFIELD"
5072 "*
5073 {
5074 CC_STATUS_INIT;
5075 return \"bfclr %0{%b2:%b1}\";
5076 }")
5078 (define_insn ""
5079 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5080 (match_operand:SI 1 "general_operand" "di")
5081 (match_operand:SI 2 "general_operand" "di"))
5082 (const_int -1))]
5083 "TARGET_68020 && TARGET_BITFIELD"
5084 "*
5085 {
5086 CC_STATUS_INIT;
5087 return \"bfset %0{%b2:%b1}\";
5088 }")
5090 (define_expand "insv"
5091 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5092 (match_operand:SI 1 "general_operand" "")
5093 (match_operand:SI 2 "general_operand" ""))
5094 (match_operand:SI 3 "register_operand" ""))]
5095 "TARGET_68020 && TARGET_BITFIELD"
5096 "")
5098 (define_insn ""
5099 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5100 (match_operand:SI 1 "general_operand" "di")
5101 (match_operand:SI 2 "general_operand" "di"))
5102 (match_operand:SI 3 "register_operand" "d"))]
5103 "TARGET_68020 && TARGET_BITFIELD"
5104 "bfins %3,%0{%b2:%b1}")
5106 ;; Now recognize bit-field insns that operate on registers
5107 ;; (or at least were intended to do so).
5109 (define_insn ""
5110 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5111 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5112 (match_operand:SI 2 "general_operand" "di")
5113 (match_operand:SI 3 "general_operand" "di")))]
5114 "TARGET_68020 && TARGET_BITFIELD"
5115 "bfexts %1{%b3:%b2},%0")
5117 (define_insn ""
5118 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5119 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5120 (match_operand:SI 2 "general_operand" "di")
5121 (match_operand:SI 3 "general_operand" "di")))]
5122 "TARGET_68020 && TARGET_BITFIELD"
5123 "*
5124 {
5125 if (GET_CODE (operands[2]) == CONST_INT)
5126 {
5127 if (INTVAL (operands[2]) != 32)
5128 cc_status.flags |= CC_NOT_NEGATIVE;
5129 }
5130 else
5131 {
5132 CC_STATUS_INIT;
5133 }
5134 return \"bfextu %1{%b3:%b2},%0\";
5135 }")
5137 (define_insn ""
5138 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5139 (match_operand:SI 1 "general_operand" "di")
5140 (match_operand:SI 2 "general_operand" "di"))
5141 (const_int 0))]
5142 "TARGET_68020 && TARGET_BITFIELD"
5143 "*
5144 {
5145 CC_STATUS_INIT;
5146 return \"bfclr %0{%b2:%b1}\";
5147 }")
5149 (define_insn ""
5150 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5151 (match_operand:SI 1 "general_operand" "di")
5152 (match_operand:SI 2 "general_operand" "di"))
5153 (const_int -1))]
5154 "TARGET_68020 && TARGET_BITFIELD"
5155 "*
5156 {
5157 CC_STATUS_INIT;
5158 return \"bfset %0{%b2:%b1}\";
5159 }")
5161 (define_insn ""
5162 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5163 (match_operand:SI 1 "general_operand" "di")
5164 (match_operand:SI 2 "general_operand" "di"))
5165 (match_operand:SI 3 "register_operand" "d"))]
5166 "TARGET_68020 && TARGET_BITFIELD"
5167 "*
5168 {
5169 #if 0
5170 /* These special cases are now recognized by a specific pattern. */
5171 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5172 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5173 return \"move%.w %3,%0\";
5174 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5175 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5176 return \"move%.b %3,%0\";
5177 #endif
5178 return \"bfins %3,%0{%b2:%b1}\";
5179 }")
5180 \f
5181 ;; Special patterns for optimizing bit-field instructions.
5183 (define_insn ""
5184 [(set (cc0)
5185 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5186 (match_operand:SI 1 "const_int_operand" "n")
5187 (match_operand:SI 2 "general_operand" "di")))]
5188 "TARGET_68020 && TARGET_BITFIELD"
5189 "*
5190 {
5191 if (operands[1] == const1_rtx
5192 && GET_CODE (operands[2]) == CONST_INT)
5193 {
5194 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5195 return output_btst (operands,
5196 GEN_INT (width - INTVAL (operands[2])),
5197 operands[0], insn, 1000);
5198 /* Pass 1000 as SIGNPOS argument so that btst will
5199 not think we are testing the sign bit for an `and'
5200 and assume that nonzero implies a negative result. */
5201 }
5202 if (INTVAL (operands[1]) != 32)
5203 cc_status.flags = CC_NOT_NEGATIVE;
5204 return \"bftst %0{%b2:%b1}\";
5205 }")
5208 ;;; now handle the register cases
5209 (define_insn ""
5210 [(set (cc0)
5211 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5212 (match_operand:SI 1 "const_int_operand" "n")
5213 (match_operand:SI 2 "general_operand" "di")))]
5214 "TARGET_68020 && TARGET_BITFIELD"
5215 "*
5216 {
5217 if (operands[1] == const1_rtx
5218 && GET_CODE (operands[2]) == CONST_INT)
5219 {
5220 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5221 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5222 operands[0], insn, 1000);
5223 /* Pass 1000 as SIGNPOS argument so that btst will
5224 not think we are testing the sign bit for an `and'
5225 and assume that nonzero implies a negative result. */
5226 }
5227 if (INTVAL (operands[1]) != 32)
5228 cc_status.flags = CC_NOT_NEGATIVE;
5229 return \"bftst %0{%b2:%b1}\";
5230 }")
5231 \f
5232 (define_insn "scc0_di"
5233 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5234 (match_operator 1 "valid_dbcc_comparison_p"
5235 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5236 "! TARGET_COLDFIRE"
5237 "*
5238 {
5239 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5240 } ")
5242 (define_insn "scc0_di_5200"
5243 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5244 (match_operator 1 "valid_dbcc_comparison_p"
5245 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5246 "TARGET_COLDFIRE"
5247 "*
5248 {
5249 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5250 } ")
5252 (define_insn "scc_di"
5253 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5254 (match_operator 1 "valid_dbcc_comparison_p"
5255 [(match_operand:DI 2 "general_operand" "ro,r")
5256 (match_operand:DI 3 "general_operand" "r,ro")]))]
5257 "! TARGET_COLDFIRE"
5258 "*
5259 {
5260 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5261 } ")
5263 (define_insn "scc_di_5200"
5264 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5265 (match_operator 1 "valid_dbcc_comparison_p"
5266 [(match_operand:DI 2 "general_operand" "ro,r")
5267 (match_operand:DI 3 "general_operand" "r,ro")]))]
5268 "TARGET_COLDFIRE"
5269 "*
5270 {
5271 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5272 } ")
5274 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5275 ;; memory, but we cannot allow it to be in memory in case the address
5276 ;; needs to be reloaded.
5278 (define_expand "seq"
5279 [(set (match_operand:QI 0 "register_operand" "")
5280 (eq:QI (cc0) (const_int 0)))]
5281 ""
5282 "
5283 {
5284 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5285 {
5286 m68k_last_compare_had_fp_operands = 0;
5287 FAIL;
5288 }
5289 }")
5291 (define_insn ""
5292 [(set (match_operand:QI 0 "register_operand" "=d")
5293 (eq:QI (cc0) (const_int 0)))]
5294 ""
5295 "*
5296 cc_status = cc_prev_status;
5297 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5298 ")
5300 (define_expand "sne"
5301 [(set (match_operand:QI 0 "register_operand" "")
5302 (ne:QI (cc0) (const_int 0)))]
5303 ""
5304 "
5305 {
5306 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5307 {
5308 m68k_last_compare_had_fp_operands = 0;
5309 FAIL;
5310 }
5311 }")
5313 (define_insn ""
5314 [(set (match_operand:QI 0 "register_operand" "=d")
5315 (ne:QI (cc0) (const_int 0)))]
5316 ""
5317 "*
5318 cc_status = cc_prev_status;
5319 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5320 ")
5322 (define_expand "sgt"
5323 [(set (match_operand:QI 0 "register_operand" "")
5324 (gt:QI (cc0) (const_int 0)))]
5325 ""
5326 "
5327 {
5328 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5329 {
5330 m68k_last_compare_had_fp_operands = 0;
5331 FAIL;
5332 }
5333 }")
5335 (define_insn ""
5336 [(set (match_operand:QI 0 "register_operand" "=d")
5337 (gt:QI (cc0) (const_int 0)))]
5338 ""
5339 "*
5340 cc_status = cc_prev_status;
5341 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5342 ")
5344 (define_expand "sgtu"
5345 [(set (match_operand:QI 0 "register_operand" "")
5346 (gtu:QI (cc0) (const_int 0)))]
5347 ""
5348 "")
5350 (define_insn ""
5351 [(set (match_operand:QI 0 "register_operand" "=d")
5352 (gtu:QI (cc0) (const_int 0)))]
5353 ""
5354 "*
5355 cc_status = cc_prev_status;
5356 return \"shi %0\"; ")
5358 (define_expand "slt"
5359 [(set (match_operand:QI 0 "register_operand" "")
5360 (lt:QI (cc0) (const_int 0)))]
5361 ""
5362 "
5363 {
5364 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5365 {
5366 m68k_last_compare_had_fp_operands = 0;
5367 FAIL;
5368 }
5369 }")
5371 (define_insn ""
5372 [(set (match_operand:QI 0 "register_operand" "=d")
5373 (lt:QI (cc0) (const_int 0)))]
5374 ""
5375 "*
5376 cc_status = cc_prev_status;
5377 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5379 (define_expand "sltu"
5380 [(set (match_operand:QI 0 "register_operand" "")
5381 (ltu:QI (cc0) (const_int 0)))]
5382 ""
5383 "")
5385 (define_insn ""
5386 [(set (match_operand:QI 0 "register_operand" "=d")
5387 (ltu:QI (cc0) (const_int 0)))]
5388 ""
5389 "*
5390 cc_status = cc_prev_status;
5391 return \"scs %0\"; ")
5393 (define_expand "sge"
5394 [(set (match_operand:QI 0 "register_operand" "")
5395 (ge:QI (cc0) (const_int 0)))]
5396 ""
5397 "
5398 {
5399 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5400 {
5401 m68k_last_compare_had_fp_operands = 0;
5402 FAIL;
5403 }
5404 }")
5406 (define_insn ""
5407 [(set (match_operand:QI 0 "register_operand" "=d")
5408 (ge:QI (cc0) (const_int 0)))]
5409 ""
5410 "*
5411 cc_status = cc_prev_status;
5412 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5414 (define_expand "sgeu"
5415 [(set (match_operand:QI 0 "register_operand" "")
5416 (geu:QI (cc0) (const_int 0)))]
5417 ""
5418 "")
5420 (define_insn ""
5421 [(set (match_operand:QI 0 "register_operand" "=d")
5422 (geu:QI (cc0) (const_int 0)))]
5423 ""
5424 "*
5425 cc_status = cc_prev_status;
5426 return \"scc %0\"; ")
5428 (define_expand "sle"
5429 [(set (match_operand:QI 0 "register_operand" "")
5430 (le:QI (cc0) (const_int 0)))]
5431 ""
5432 "
5433 {
5434 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5435 {
5436 m68k_last_compare_had_fp_operands = 0;
5437 FAIL;
5438 }
5439 }")
5441 (define_insn ""
5442 [(set (match_operand:QI 0 "register_operand" "=d")
5443 (le:QI (cc0) (const_int 0)))]
5444 ""
5445 "*
5446 cc_status = cc_prev_status;
5447 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5448 ")
5450 (define_expand "sleu"
5451 [(set (match_operand:QI 0 "register_operand" "")
5452 (leu:QI (cc0) (const_int 0)))]
5453 ""
5454 "")
5456 (define_insn ""
5457 [(set (match_operand:QI 0 "register_operand" "=d")
5458 (leu:QI (cc0) (const_int 0)))]
5459 ""
5460 "*
5461 cc_status = cc_prev_status;
5462 return \"sls %0\"; ")
5464 (define_expand "sordered"
5465 [(set (match_operand:QI 0 "register_operand" "")
5466 (ordered:QI (cc0) (const_int 0)))]
5467 "TARGET_68881 && !TARGET_68060"
5468 {
5469 if (! m68k_last_compare_had_fp_operands)
5470 abort ();
5471 m68k_last_compare_had_fp_operands = 0;
5472 })
5474 (define_insn "*sordered_1"
5475 [(set (match_operand:QI 0 "register_operand" "=d")
5476 (ordered:QI (cc0) (const_int 0)))]
5477 "TARGET_68881 && !TARGET_68060"
5478 {
5479 cc_status = cc_prev_status;
5480 return "fsor %0";
5481 })
5483 (define_expand "sunordered"
5484 [(set (match_operand:QI 0 "register_operand" "")
5485 (unordered:QI (cc0) (const_int 0)))]
5486 "TARGET_68881 && !TARGET_68060"
5487 {
5488 if (! m68k_last_compare_had_fp_operands)
5489 abort ();
5490 m68k_last_compare_had_fp_operands = 0;
5491 })
5493 (define_insn "*sunordered_1"
5494 [(set (match_operand:QI 0 "register_operand" "=d")
5495 (unordered:QI (cc0) (const_int 0)))]
5496 "TARGET_68881 && !TARGET_68060"
5497 {
5498 cc_status = cc_prev_status;
5499 return "fsun %0";
5500 })
5502 (define_expand "suneq"
5503 [(set (match_operand:QI 0 "register_operand" "")
5504 (uneq:QI (cc0) (const_int 0)))]
5505 "TARGET_68881 && !TARGET_68060"
5506 {
5507 if (! m68k_last_compare_had_fp_operands)
5508 abort ();
5509 m68k_last_compare_had_fp_operands = 0;
5510 })
5512 (define_insn "*suneq_1"
5513 [(set (match_operand:QI 0 "register_operand" "=d")
5514 (uneq:QI (cc0) (const_int 0)))]
5515 "TARGET_68881 && !TARGET_68060"
5516 {
5517 cc_status = cc_prev_status;
5518 return "fsueq %0";
5519 })
5521 (define_expand "sunge"
5522 [(set (match_operand:QI 0 "register_operand" "")
5523 (unge:QI (cc0) (const_int 0)))]
5524 "TARGET_68881 && !TARGET_68060"
5525 {
5526 if (! m68k_last_compare_had_fp_operands)
5527 abort ();
5528 m68k_last_compare_had_fp_operands = 0;
5529 })
5531 (define_insn "*sunge_1"
5532 [(set (match_operand:QI 0 "register_operand" "=d")
5533 (unge:QI (cc0) (const_int 0)))]
5534 "TARGET_68881 && !TARGET_68060"
5535 {
5536 cc_status = cc_prev_status;
5537 return "fsuge %0";
5538 })
5540 (define_expand "sungt"
5541 [(set (match_operand:QI 0 "register_operand" "")
5542 (ungt:QI (cc0) (const_int 0)))]
5543 "TARGET_68881 && !TARGET_68060"
5544 {
5545 if (! m68k_last_compare_had_fp_operands)
5546 abort ();
5547 m68k_last_compare_had_fp_operands = 0;
5548 })
5550 (define_insn "*sungt_1"
5551 [(set (match_operand:QI 0 "register_operand" "=d")
5552 (ungt:QI (cc0) (const_int 0)))]
5553 "TARGET_68881 && !TARGET_68060"
5554 {
5555 cc_status = cc_prev_status;
5556 return "fsugt %0";
5557 })
5559 (define_expand "sunle"
5560 [(set (match_operand:QI 0 "register_operand" "")
5561 (unle:QI (cc0) (const_int 0)))]
5562 "TARGET_68881 && !TARGET_68060"
5563 {
5564 if (! m68k_last_compare_had_fp_operands)
5565 abort ();
5566 m68k_last_compare_had_fp_operands = 0;
5567 })
5569 (define_insn "*sunle_1"
5570 [(set (match_operand:QI 0 "register_operand" "=d")
5571 (unle:QI (cc0) (const_int 0)))]
5572 "TARGET_68881 && !TARGET_68060"
5573 {
5574 cc_status = cc_prev_status;
5575 return "fsule %0";
5576 })
5578 (define_expand "sunlt"
5579 [(set (match_operand:QI 0 "register_operand" "")
5580 (unlt:QI (cc0) (const_int 0)))]
5581 "TARGET_68881 && !TARGET_68060"
5582 {
5583 if (! m68k_last_compare_had_fp_operands)
5584 abort ();
5585 m68k_last_compare_had_fp_operands = 0;
5586 })
5588 (define_insn "*sunlt_1"
5589 [(set (match_operand:QI 0 "register_operand" "=d")
5590 (unlt:QI (cc0) (const_int 0)))]
5591 "TARGET_68881 && !TARGET_68060"
5592 {
5593 cc_status = cc_prev_status;
5594 return "fsult %0";
5595 })
5597 (define_expand "sltgt"
5598 [(set (match_operand:QI 0 "register_operand" "")
5599 (ltgt:QI (cc0) (const_int 0)))]
5600 "TARGET_68881 && !TARGET_68060"
5601 {
5602 if (! m68k_last_compare_had_fp_operands)
5603 abort ();
5604 m68k_last_compare_had_fp_operands = 0;
5605 })
5607 (define_insn "*sltgt_1"
5608 [(set (match_operand:QI 0 "register_operand" "=d")
5609 (ltgt:QI (cc0) (const_int 0)))]
5610 "TARGET_68881 && !TARGET_68060"
5611 {
5612 cc_status = cc_prev_status;
5613 return "fsogl %0";
5614 })
5616 (define_insn "*fsogt_1"
5617 [(set (match_operand:QI 0 "register_operand" "=d")
5618 (not:QI (unle:QI (cc0) (const_int 0))))]
5619 "TARGET_68881 && !TARGET_68060"
5620 {
5621 cc_status = cc_prev_status;
5622 return "fsogt %0";
5623 })
5625 (define_insn "*fsoge_1"
5626 [(set (match_operand:QI 0 "register_operand" "=d")
5627 (not:QI (unlt:QI (cc0) (const_int 0))))]
5628 "TARGET_68881 && !TARGET_68060"
5629 {
5630 cc_status = cc_prev_status;
5631 return "fsoge %0";
5632 })
5634 (define_insn "*fsolt_1"
5635 [(set (match_operand:QI 0 "register_operand" "=d")
5636 (not:QI (unge:QI (cc0) (const_int 0))))]
5637 "TARGET_68881 && !TARGET_68060"
5638 {
5639 cc_status = cc_prev_status;
5640 return "fsolt %0";
5641 })
5643 (define_insn "*fsole_1"
5644 [(set (match_operand:QI 0 "register_operand" "=d")
5645 (not:QI (ungt:QI (cc0) (const_int 0))))]
5646 "TARGET_68881 && !TARGET_68060"
5647 {
5648 cc_status = cc_prev_status;
5649 return "fsole %0";
5650 })
5651 \f
5652 ;; Basic conditional jump instructions.
5654 (define_insn "beq0_di"
5655 [(set (pc)
5656 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5657 (const_int 0))
5658 (label_ref (match_operand 1 "" ","))
5659 (pc)))
5660 (clobber (match_scratch:SI 2 "=d,d"))]
5661 ""
5662 "*
5663 {
5664 CC_STATUS_INIT;
5665 if (which_alternative == 1)
5666 #ifdef MOTOROLA
5667 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5668 #else
5669 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5670 #endif
5671 if ((cc_prev_status.value1
5672 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5673 || (cc_prev_status.value2
5674 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5675 {
5676 cc_status = cc_prev_status;
5677 #ifdef MOTOROLA
5678 return \"jbeq %l1\";
5679 #else
5680 return \"jeq %l1\";
5681 #endif
5682 }
5683 if (GET_CODE (operands[0]) == REG)
5684 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5685 else
5686 operands[3] = adjust_address (operands[0], SImode, 4);
5687 if (! ADDRESS_REG_P (operands[0]))
5688 {
5689 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5690 {
5691 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5692 {
5693 #ifdef MOTOROLA
5694 return \"or%.l %0,%2\;jbeq %l1\";
5695 #else
5696 return \"or%.l %0,%2\;jeq %l1\";
5697 #endif
5698 }
5699 else
5700 {
5701 #ifdef MOTOROLA
5702 return \"or%.l %3,%2\;jbeq %l1\";
5703 #else
5704 return \"or%.l %3,%2\;jeq %l1\";
5705 #endif
5706 }
5707 }
5708 #ifdef MOTOROLA
5709 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5710 #else
5711 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5712 #endif
5713 }
5714 operands[4] = gen_label_rtx();
5715 if (TARGET_68020 || TARGET_COLDFIRE)
5716 {
5717 #ifdef MOTOROLA
5718 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5719 #else
5720 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5721 #endif
5722 }
5723 else
5724 {
5725 #ifdef MOTOROLA
5726 #ifdef SGS_CMP_ORDER
5727 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5728 #else
5729 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5730 #endif
5731 #else
5732 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5733 #endif
5734 }
5735 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5736 CODE_LABEL_NUMBER (operands[4]));
5737 return \"\";
5738 } ")
5740 (define_insn "bne0_di"
5741 [(set (pc)
5742 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5743 (const_int 0))
5744 (label_ref (match_operand 1 "" ","))
5745 (pc)))
5746 (clobber (match_scratch:SI 2 "=d,X"))]
5747 ""
5748 "*
5749 {
5750 if ((cc_prev_status.value1
5751 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5752 || (cc_prev_status.value2
5753 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5754 {
5755 cc_status = cc_prev_status;
5756 #ifdef MOTOROLA
5757 return \"jbne %l1\";
5758 #else
5759 return \"jne %l1\";
5760 #endif
5761 }
5762 CC_STATUS_INIT;
5763 if (GET_CODE (operands[0]) == REG)
5764 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5765 else
5766 operands[3] = adjust_address (operands[0], SImode, 4);
5767 if (!ADDRESS_REG_P (operands[0]))
5768 {
5769 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5770 {
5771 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5772 {
5773 #ifdef MOTOROLA
5774 return \"or%.l %0,%2\;jbne %l1\";
5775 #else
5776 return \"or%.l %0,%2\;jne %l1\";
5777 #endif
5778 }
5779 else
5780 {
5781 #ifdef MOTOROLA
5782 return \"or%.l %3,%2\;jbne %l1\";
5783 #else
5784 return \"or%.l %3,%2\;jne %l1\";
5785 #endif
5786 }
5787 }
5788 #ifdef MOTOROLA
5789 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5790 #else
5791 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5792 #endif
5793 }
5794 if (TARGET_68020 || TARGET_COLDFIRE)
5795 {
5796 #ifdef MOTOROLA
5797 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5798 #else
5799 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5800 #endif
5801 }
5802 else
5803 {
5804 #ifdef MOTOROLA
5805 #ifdef SGS_CMP_ORDER
5806 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5807 #else
5808 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5809 #endif
5810 #else
5811 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5812 #endif
5813 }
5814 } ")
5816 (define_insn "bge0_di"
5817 [(set (pc)
5818 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5819 (const_int 0))
5820 (label_ref (match_operand 1 "" ""))
5821 (pc)))]
5822 ""
5823 "*
5824 {
5825 if ((cc_prev_status.value1
5826 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5827 || (cc_prev_status.value2
5828 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5829 {
5830 cc_status = cc_prev_status;
5831 if (cc_status.flags & CC_REVERSED)
5832 {
5833 #ifdef MOTOROLA
5834 return \"jble %l1\";
5835 #else
5836 return \"jle %l1\";
5837 #endif
5838 }
5839 else
5840 {
5841 #ifdef MOTOROLA
5842 return \"jbpl %l1\";
5843 #else
5844 return \"jpl %l1\";
5845 #endif
5846 }
5847 }
5848 CC_STATUS_INIT;
5849 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5850 output_asm_insn(\"tst%.l %0\", operands);
5851 else
5852 {
5853 /* On an address reg, cmpw may replace cmpl. */
5854 #ifdef SGS_CMP_ORDER
5855 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5856 #else
5857 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5858 #endif
5859 }
5861 #ifdef MOTOROLA
5862 return \"jbpl %l1\";
5863 #else
5864 return \"jpl %l1\";
5865 #endif
5866 } ")
5868 (define_insn "blt0_di"
5869 [(set (pc)
5870 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5871 (const_int 0))
5872 (label_ref (match_operand 1 "" ""))
5873 (pc)))]
5874 ""
5875 "*
5876 {
5877 if ((cc_prev_status.value1
5878 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5879 || (cc_prev_status.value2
5880 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5881 {
5882 cc_status = cc_prev_status;
5883 if (cc_status.flags & CC_REVERSED)
5884 {
5885 #ifdef MOTOROLA
5886 return \"jbgt %l1\";
5887 #else
5888 return \"jgt %l1\";
5889 #endif
5890 }
5891 else
5892 {
5893 #ifdef MOTOROLA
5894 return \"jbmi %l1\";
5895 #else
5896 return \"jmi %l1\";
5897 #endif
5898 }
5899 }
5900 CC_STATUS_INIT;
5901 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5902 output_asm_insn(\"tst%.l %0\", operands);
5903 else
5904 {
5905 /* On an address reg, cmpw may replace cmpl. */
5906 #ifdef SGS_CMP_ORDER
5907 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5908 #else
5909 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5910 #endif
5911 }
5913 #ifdef MOTOROLA
5914 return \"jbmi %l1\";
5915 #else
5916 return \"jmi %l1\";
5917 #endif
5918 } ")
5920 (define_insn "beq"
5921 [(set (pc)
5922 (if_then_else (eq (cc0)
5923 (const_int 0))
5924 (label_ref (match_operand 0 "" ""))
5925 (pc)))]
5926 ""
5927 "*
5928 {
5929 #ifdef MOTOROLA
5930 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5931 #else
5932 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5933 #endif
5934 }")
5936 (define_insn "bne"
5937 [(set (pc)
5938 (if_then_else (ne (cc0)
5939 (const_int 0))
5940 (label_ref (match_operand 0 "" ""))
5941 (pc)))]
5942 ""
5943 "*
5944 {
5945 #ifdef MOTOROLA
5946 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5947 #else
5948 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5949 #endif
5950 }")
5952 (define_insn "bgt"
5953 [(set (pc)
5954 (if_then_else (gt (cc0)
5955 (const_int 0))
5956 (label_ref (match_operand 0 "" ""))
5957 (pc)))]
5958 ""
5959 "*
5960 #ifdef MOTOROLA
5961 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5962 #else
5963 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5964 #endif
5965 ")
5967 (define_insn "bgtu"
5968 [(set (pc)
5969 (if_then_else (gtu (cc0)
5970 (const_int 0))
5971 (label_ref (match_operand 0 "" ""))
5972 (pc)))]
5973 ""
5974 "*
5975 #ifdef MOTOROLA
5976 return \"jbhi %l0\";
5977 #else
5978 return \"jhi %l0\";
5979 #endif
5980 ")
5982 (define_insn "blt"
5983 [(set (pc)
5984 (if_then_else (lt (cc0)
5985 (const_int 0))
5986 (label_ref (match_operand 0 "" ""))
5987 (pc)))]
5988 ""
5989 "*
5990 #ifdef MOTOROLA
5991 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5992 #else
5993 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5994 #endif
5995 ")
5997 (define_insn "bltu"
5998 [(set (pc)
5999 (if_then_else (ltu (cc0)
6000 (const_int 0))
6001 (label_ref (match_operand 0 "" ""))
6002 (pc)))]
6003 ""
6004 "*
6005 #ifdef MOTOROLA
6006 return \"jbcs %l0\";
6007 #else
6008 return \"jcs %l0\";
6009 #endif
6010 ")
6012 (define_insn "bge"
6013 [(set (pc)
6014 (if_then_else (ge (cc0)
6015 (const_int 0))
6016 (label_ref (match_operand 0 "" ""))
6017 (pc)))]
6018 ""
6019 "*
6020 #ifdef MOTOROLA
6021 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6022 #else
6023 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6024 #endif
6025 ")
6027 (define_insn "bgeu"
6028 [(set (pc)
6029 (if_then_else (geu (cc0)
6030 (const_int 0))
6031 (label_ref (match_operand 0 "" ""))
6032 (pc)))]
6033 ""
6034 "*
6035 #ifdef MOTOROLA
6036 return \"jbcc %l0\";
6037 #else
6038 return \"jcc %l0\";
6039 #endif
6040 ")
6042 (define_insn "ble"
6043 [(set (pc)
6044 (if_then_else (le (cc0)
6045 (const_int 0))
6046 (label_ref (match_operand 0 "" ""))
6047 (pc)))]
6048 ""
6049 "*
6050 #ifdef MOTOROLA
6051 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6052 #else
6053 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6054 #endif
6055 ")
6057 (define_insn "bleu"
6058 [(set (pc)
6059 (if_then_else (leu (cc0)
6060 (const_int 0))
6061 (label_ref (match_operand 0 "" ""))
6062 (pc)))]
6063 ""
6064 "*
6065 #ifdef MOTOROLA
6066 return \"jbls %l0\";
6067 #else
6068 return \"jls %l0\";
6069 #endif
6070 ")
6072 (define_insn "bordered"
6073 [(set (pc)
6074 (if_then_else (ordered (cc0) (const_int 0))
6075 (label_ref (match_operand 0 "" ""))
6076 (pc)))]
6077 "TARGET_68881"
6078 {
6079 if (!(cc_prev_status.flags & CC_IN_68881))
6080 abort ();
6081 #ifdef MOTOROLA
6082 return "fbor %l0";
6083 #else
6084 return "fjor %l0";
6085 #endif
6086 })
6088 (define_insn "bunordered"
6089 [(set (pc)
6090 (if_then_else (unordered (cc0) (const_int 0))
6091 (label_ref (match_operand 0 "" ""))
6092 (pc)))]
6093 "TARGET_68881"
6094 {
6095 if (!(cc_prev_status.flags & CC_IN_68881))
6096 abort ();
6097 #ifdef MOTOROLA
6098 return "fbun %l0";
6099 #else
6100 return "fjun %l0";
6101 #endif
6102 })
6104 (define_insn "buneq"
6105 [(set (pc)
6106 (if_then_else (uneq (cc0) (const_int 0))
6107 (label_ref (match_operand 0 "" ""))
6108 (pc)))]
6109 "TARGET_68881"
6110 {
6111 if (!(cc_prev_status.flags & CC_IN_68881))
6112 abort ();
6113 #ifdef MOTOROLA
6114 return "fbueq %l0";
6115 #else
6116 return "fjueq %l0";
6117 #endif
6118 })
6120 (define_insn "bunge"
6121 [(set (pc)
6122 (if_then_else (unge (cc0) (const_int 0))
6123 (label_ref (match_operand 0 "" ""))
6124 (pc)))]
6125 "TARGET_68881"
6126 {
6127 if (!(cc_prev_status.flags & CC_IN_68881))
6128 abort ();
6129 #ifdef MOTOROLA
6130 return "fbuge %l0";
6131 #else
6132 return "fjuge %l0";
6133 #endif
6134 })
6136 (define_insn "bungt"
6137 [(set (pc)
6138 (if_then_else (ungt (cc0) (const_int 0))
6139 (label_ref (match_operand 0 "" ""))
6140 (pc)))]
6141 "TARGET_68881"
6142 {
6143 if (!(cc_prev_status.flags & CC_IN_68881))
6144 abort ();
6145 #ifdef MOTOROLA
6146 return "fbugt %l0";
6147 #else
6148 return "fjugt %l0";
6149 #endif
6150 })
6152 (define_insn "bunle"
6153 [(set (pc)
6154 (if_then_else (unle (cc0) (const_int 0))
6155 (label_ref (match_operand 0 "" ""))
6156 (pc)))]
6157 "TARGET_68881"
6158 {
6159 if (!(cc_prev_status.flags & CC_IN_68881))
6160 abort ();
6161 #ifdef MOTOROLA
6162 return "fbule %l0";
6163 #else
6164 return "fjule %l0";
6165 #endif
6166 })
6168 (define_insn "bunlt"
6169 [(set (pc)
6170 (if_then_else (unlt (cc0) (const_int 0))
6171 (label_ref (match_operand 0 "" ""))
6172 (pc)))]
6173 "TARGET_68881"
6174 {
6175 if (!(cc_prev_status.flags & CC_IN_68881))
6176 abort ();
6177 #ifdef MOTOROLA
6178 return "fbult %l0";
6179 #else
6180 return "fjult %l0";
6181 #endif
6182 })
6184 (define_insn "bltgt"
6185 [(set (pc)
6186 (if_then_else (ltgt (cc0) (const_int 0))
6187 (label_ref (match_operand 0 "" ""))
6188 (pc)))]
6189 "TARGET_68881"
6190 {
6191 if (!(cc_prev_status.flags & CC_IN_68881))
6192 abort ();
6193 #ifdef MOTOROLA
6194 return "fbogl %l0";
6195 #else
6196 return "fjogl %l0";
6197 #endif
6198 })
6199 \f
6200 ;; Negated conditional jump instructions.
6202 (define_insn ""
6203 [(set (pc)
6204 (if_then_else (eq (cc0)
6205 (const_int 0))
6206 (pc)
6207 (label_ref (match_operand 0 "" ""))))]
6208 ""
6209 "*
6210 {
6211 #ifdef MOTOROLA
6212 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6213 #else
6214 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6215 #endif
6216 }")
6218 (define_insn ""
6219 [(set (pc)
6220 (if_then_else (ne (cc0)
6221 (const_int 0))
6222 (pc)
6223 (label_ref (match_operand 0 "" ""))))]
6224 ""
6225 "*
6226 {
6227 #ifdef MOTOROLA
6228 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6229 #else
6230 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6231 #endif
6232 }")
6234 (define_insn ""
6235 [(set (pc)
6236 (if_then_else (gt (cc0)
6237 (const_int 0))
6238 (pc)
6239 (label_ref (match_operand 0 "" ""))))]
6240 ""
6241 "*
6242 #ifdef MOTOROLA
6243 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6244 #else
6245 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6246 #endif
6247 ")
6249 (define_insn ""
6250 [(set (pc)
6251 (if_then_else (gtu (cc0)
6252 (const_int 0))
6253 (pc)
6254 (label_ref (match_operand 0 "" ""))))]
6255 ""
6256 "*
6257 #ifdef MOTOROLA
6258 return \"jbls %l0\";
6259 #else
6260 return \"jls %l0\";
6261 #endif
6262 ")
6264 (define_insn ""
6265 [(set (pc)
6266 (if_then_else (lt (cc0)
6267 (const_int 0))
6268 (pc)
6269 (label_ref (match_operand 0 "" ""))))]
6270 ""
6271 "*
6272 #ifdef MOTOROLA
6273 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6274 #else
6275 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6276 #endif
6277 ")
6279 (define_insn ""
6280 [(set (pc)
6281 (if_then_else (ltu (cc0)
6282 (const_int 0))
6283 (pc)
6284 (label_ref (match_operand 0 "" ""))))]
6285 ""
6286 "*
6287 #ifdef MOTOROLA
6288 return \"jbcc %l0\";
6289 #else
6290 return \"jcc %l0\";
6291 #endif
6292 ")
6294 (define_insn ""
6295 [(set (pc)
6296 (if_then_else (ge (cc0)
6297 (const_int 0))
6298 (pc)
6299 (label_ref (match_operand 0 "" ""))))]
6300 ""
6301 "*
6302 #ifdef MOTOROLA
6303 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6304 #else
6305 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6306 #endif
6307 ")
6309 (define_insn ""
6310 [(set (pc)
6311 (if_then_else (geu (cc0)
6312 (const_int 0))
6313 (pc)
6314 (label_ref (match_operand 0 "" ""))))]
6315 ""
6316 "*
6317 #ifdef MOTOROLA
6318 return \"jbcs %l0\";
6319 #else
6320 return \"jcs %l0\";
6321 #endif
6322 ")
6324 (define_insn ""
6325 [(set (pc)
6326 (if_then_else (le (cc0)
6327 (const_int 0))
6328 (pc)
6329 (label_ref (match_operand 0 "" ""))))]
6330 ""
6331 "*
6332 #ifdef MOTOROLA
6333 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6334 #else
6335 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6336 #endif
6337 ")
6339 (define_insn ""
6340 [(set (pc)
6341 (if_then_else (leu (cc0)
6342 (const_int 0))
6343 (pc)
6344 (label_ref (match_operand 0 "" ""))))]
6345 ""
6346 "*
6347 #ifdef MOTOROLA
6348 return \"jbhi %l0\";
6349 #else
6350 return \"jhi %l0\";
6351 #endif
6352 ")
6354 (define_insn "*bordered_rev"
6355 [(set (pc)
6356 (if_then_else (ordered (cc0) (const_int 0))
6357 (pc)
6358 (label_ref (match_operand 0 "" ""))))]
6359 "TARGET_68881"
6360 {
6361 if (!(cc_prev_status.flags & CC_IN_68881))
6362 abort ();
6363 #ifdef MOTOROLA
6364 return "fbun %l0";
6365 #else
6366 return "fjun %l0";
6367 #endif
6368 })
6370 (define_insn "*bunordered_rev"
6371 [(set (pc)
6372 (if_then_else (unordered (cc0) (const_int 0))
6373 (pc)
6374 (label_ref (match_operand 0 "" ""))))]
6375 "TARGET_68881"
6376 {
6377 if (!(cc_prev_status.flags & CC_IN_68881))
6378 abort ();
6379 #ifdef MOTOROLA
6380 return "fbor %l0";
6381 #else
6382 return "fjor %l0";
6383 #endif
6384 })
6386 (define_insn "*buneq_rev"
6387 [(set (pc)
6388 (if_then_else (uneq (cc0) (const_int 0))
6389 (pc)
6390 (label_ref (match_operand 0 "" ""))))]
6391 "TARGET_68881"
6392 {
6393 if (!(cc_prev_status.flags & CC_IN_68881))
6394 abort ();
6395 #ifdef MOTOROLA
6396 return "fbogl %l0";
6397 #else
6398 return "fjogl %l0";
6399 #endif
6400 })
6402 (define_insn "*bunge_rev"
6403 [(set (pc)
6404 (if_then_else (unge (cc0) (const_int 0))
6405 (pc)
6406 (label_ref (match_operand 0 "" ""))))]
6407 "TARGET_68881"
6408 {
6409 if (!(cc_prev_status.flags & CC_IN_68881))
6410 abort ();
6411 #ifdef MOTOROLA
6412 return "fbolt %l0";
6413 #else
6414 return "fjolt %l0";
6415 #endif
6416 })
6418 (define_insn "*bunle_rev"
6419 [(set (pc)
6420 (if_then_else (unle (cc0) (const_int 0))
6421 (pc)
6422 (label_ref (match_operand 0 "" ""))))]
6423 "TARGET_68881"
6424 {
6425 if (!(cc_prev_status.flags & CC_IN_68881))
6426 abort ();
6427 #ifdef MOTOROLA
6428 return "fbogt %l0";
6429 #else
6430 return "fjogt %l0";
6431 #endif
6432 })
6434 (define_insn "*bunlt_rev"
6435 [(set (pc)
6436 (if_then_else (unlt (cc0) (const_int 0))
6437 (pc)
6438 (label_ref (match_operand 0 "" ""))))]
6439 "TARGET_68881"
6440 {
6441 if (!(cc_prev_status.flags & CC_IN_68881))
6442 abort ();
6443 #ifdef MOTOROLA
6444 return "fboge %l0";
6445 #else
6446 return "fjoge %l0";
6447 #endif
6448 })
6450 (define_insn "*bltgt_rev"
6451 [(set (pc)
6452 (if_then_else (ltgt (cc0) (const_int 0))
6453 (pc)
6454 (label_ref (match_operand 0 "" ""))))]
6455 "TARGET_68881"
6456 {
6457 if (!(cc_prev_status.flags & CC_IN_68881))
6458 abort ();
6459 #ifdef MOTOROLA
6460 return "fbueq %l0";
6461 #else
6462 return "fjueq %l0";
6463 #endif
6464 })
6465 \f
6466 ;; Unconditional and other jump instructions
6467 (define_insn "jump"
6468 [(set (pc)
6469 (label_ref (match_operand 0 "" "")))]
6470 ""
6471 "*
6472 #ifdef MOTOROLA
6473 return \"jbra %l0\";
6474 #else
6475 return \"jra %l0\";
6476 #endif
6477 ")
6479 ;; We support two different ways of handling dispatch tables.
6480 ;; The NeXT uses absolute tables, and other machines use relative.
6481 ;; This define_expand can generate either kind.
6482 (define_expand "tablejump"
6483 [(parallel [(set (pc) (match_operand 0 "" ""))
6484 (use (label_ref (match_operand 1 "" "")))])]
6485 ""
6486 "
6487 {
6488 #ifdef CASE_VECTOR_PC_RELATIVE
6489 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6490 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6491 #endif
6492 }")
6494 ;; Jump to variable address from dispatch table of absolute addresses.
6495 (define_insn ""
6496 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6497 (use (label_ref (match_operand 1 "" "")))]
6498 ""
6499 "*
6500 #ifdef MOTOROLA
6501 return \"jmp (%0)\";
6502 #else
6503 return \"jmp %0@\";
6504 #endif
6505 ")
6507 ;; Jump to variable address from dispatch table of relative addresses.
6508 (define_insn ""
6509 [(set (pc)
6510 (plus:SI (pc)
6511 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6512 (use (label_ref (match_operand 1 "" "")))]
6513 ""
6514 "*
6515 #ifdef ASM_RETURN_CASE_JUMP
6516 ASM_RETURN_CASE_JUMP;
6517 #else
6518 #ifdef SGS
6519 #ifdef ASM_OUTPUT_CASE_LABEL
6520 if (TARGET_COLDFIRE)
6521 {
6522 if (ADDRESS_REG_P (operands[0]))
6523 return \"jmp 6(%%pc,%0.l)\";
6524 else
6525 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6526 }
6527 else
6528 return \"jmp 6(%%pc,%0.w)\";
6529 #else
6530 if (TARGET_COLDFIRE)
6531 {
6532 if (ADDRESS_REG_P (operands[0]))
6533 return \"jmp 2(%%pc,%0.l)\";
6534 else
6535 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6536 }
6537 else
6538 return \"jmp 2(%%pc,%0.w)\";
6539 #endif
6540 #else /* not SGS */
6541 if (TARGET_COLDFIRE)
6542 {
6543 if (ADDRESS_REG_P (operands[0]))
6544 {
6545 #ifdef MOTOROLA
6546 return \"jmp (2,pc,%0.l)\";
6547 #else
6548 return \"jmp pc@(2,%0:l)\";
6549 #endif
6550 }
6551 else
6552 {
6553 #ifdef MOTOROLA
6554 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6555 #else
6556 return \"extl %0\;jmp pc@(2,%0:l)\";
6557 #endif
6558 }
6559 }
6560 else
6561 {
6562 #ifdef MOTOROLA
6563 return \"jmp (2,pc,%0.w)\";
6564 #else
6565 return \"jmp pc@(2,%0:w)\";
6566 #endif
6567 }
6568 #endif
6569 #endif
6570 ")
6572 ;; Decrement-and-branch insns.
6573 (define_insn ""
6574 [(set (pc)
6575 (if_then_else
6576 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6577 (const_int 0))
6578 (label_ref (match_operand 1 "" ""))
6579 (pc)))
6580 (set (match_dup 0)
6581 (plus:HI (match_dup 0)
6582 (const_int -1)))]
6583 "!TARGET_COLDFIRE"
6584 "*
6585 {
6586 CC_STATUS_INIT;
6587 if (DATA_REG_P (operands[0]))
6588 return \"dbra %0,%l1\";
6589 if (GET_CODE (operands[0]) == MEM)
6590 {
6591 #ifdef MOTOROLA
6592 return \"subq%.w %#1,%0\;jbcc %l1\";
6593 #else /* not MOTOROLA */
6594 return \"subqw %#1,%0\;jcc %l1\";
6595 #endif
6596 }
6597 #ifdef MOTOROLA
6598 #ifdef SGS_CMP_ORDER
6599 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6600 #else /* not SGS_CMP_ORDER */
6601 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6602 #endif
6603 #else /* not MOTOROLA */
6604 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6605 #endif
6606 }")
6608 (define_insn ""
6609 [(set (pc)
6610 (if_then_else
6611 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6612 (const_int 0))
6613 (label_ref (match_operand 1 "" ""))
6614 (pc)))
6615 (set (match_dup 0)
6616 (plus:SI (match_dup 0)
6617 (const_int -1)))]
6618 "!TARGET_COLDFIRE"
6619 "*
6620 {
6621 CC_STATUS_INIT;
6622 #ifdef MOTOROLA
6623 if (DATA_REG_P (operands[0]))
6624 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6625 if (GET_CODE (operands[0]) == MEM)
6626 return \"subq%.l %#1,%0\;jbcc %l1\";
6627 #ifdef SGS_CMP_ORDER
6628 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6629 #else /* not SGS_CMP_ORDER */
6630 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6631 #endif /* not SGS_CMP_ORDER */
6632 #else /* not MOTOROLA */
6633 if (DATA_REG_P (operands[0]))
6634 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6635 if (GET_CODE (operands[0]) == MEM)
6636 return \"subql %#1,%0\;jcc %l1\";
6637 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6638 #endif /* not MOTOROLA */
6639 }")
6641 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6643 (define_insn ""
6644 [(set (pc)
6645 (if_then_else
6646 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6647 (const_int -1))
6648 (const_int 0))
6649 (label_ref (match_operand 1 "" ""))
6650 (pc)))
6651 (set (match_dup 0)
6652 (plus:HI (match_dup 0)
6653 (const_int -1)))]
6654 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6655 "*
6656 {
6657 CC_STATUS_INIT;
6658 #ifdef MOTOROLA
6659 if (DATA_REG_P (operands[0]))
6660 return \"dbra %0,%l1\";
6661 if (GET_CODE (operands[0]) == MEM)
6662 return \"subq%.w %#1,%0\;jbcc %l1\";
6663 #ifdef SGS_CMP_ORDER
6664 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6665 #else /* not SGS_CMP_ORDER */
6666 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6667 #endif /* not SGS_CMP_ORDER */
6668 #else /* not MOTOROLA */
6669 if (DATA_REG_P (operands[0]))
6670 return \"dbra %0,%l1\";
6671 if (GET_CODE (operands[0]) == MEM)
6672 return \"subqw %#1,%0\;jcc %l1\";
6673 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6674 #endif /* not MOTOROLA */
6675 }")
6677 (define_expand "decrement_and_branch_until_zero"
6678 [(parallel [(set (pc)
6679 (if_then_else
6680 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6681 (const_int -1))
6682 (const_int 0))
6683 (label_ref (match_operand 1 "" ""))
6684 (pc)))
6685 (set (match_dup 0)
6686 (plus:SI (match_dup 0)
6687 (const_int -1)))])]
6688 ""
6689 "")
6691 (define_insn ""
6692 [(set (pc)
6693 (if_then_else
6694 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6695 (const_int -1))
6696 (const_int 0))
6697 (label_ref (match_operand 1 "" ""))
6698 (pc)))
6699 (set (match_dup 0)
6700 (plus:SI (match_dup 0)
6701 (const_int -1)))]
6702 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6703 "*
6704 {
6705 CC_STATUS_INIT;
6706 #ifdef MOTOROLA
6707 if (DATA_REG_P (operands[0]))
6708 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6709 if (GET_CODE (operands[0]) == MEM)
6710 return \"subq%.l %#1,%0\;jbcc %l1\";
6711 #ifdef SGS_CMP_ORDER
6712 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6713 #else /* not SGS_CMP_ORDER */
6714 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6715 #endif /* not SGS_CMP_ORDER */
6716 #else /* not MOTOROLA */
6717 if (DATA_REG_P (operands[0]))
6718 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6719 if (GET_CODE (operands[0]) == MEM)
6720 return \"subql %#1,%0\;jcc %l1\";
6721 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6722 #endif /* not MOTOROLA */
6723 }")
6726 ;; For PIC calls, in order to be able to support
6727 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6728 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6729 ;;
6730 ;; PIC calls are handled by loading the address of the function into a
6731 ;; register (via movsi), then emitting a register indirect call using
6732 ;; the "jsr" function call syntax.
6733 ;;
6734 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6735 ;; operand to the jbsr statement to indicate that this call should
6736 ;; go through the PLT (why? because this is the way that Sun does it).
6737 ;;
6738 ;; We have different patterns for PIC calls and non-PIC calls. The
6739 ;; different patterns are only used to choose the right syntax.
6740 ;;
6741 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6742 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6743 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6744 ;; section at link time. However, all global objects reference are still
6745 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6746 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6747 ;; We need to have a way to differentiate these two different operands.
6748 ;;
6749 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6750 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6751 ;; to be changed to recognize function calls symbol_ref operand as a valid
6752 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6753 ;; avoid the compiler to load this symbol_ref operand into a register.
6754 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6755 ;; since the value is a PC relative offset, not a real address.
6756 ;;
6757 ;; All global objects are treated in the similar way as in SUN3. The only
6758 ;; difference is: on m68k svr4, the reference of such global object needs
6759 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6760 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6761 ;; m68k.c.
6763 ;; Call subroutine with no return value.
6764 (define_expand "call"
6765 [(call (match_operand:QI 0 "memory_operand" "")
6766 (match_operand:SI 1 "general_operand" ""))]
6767 ;; Operand 1 not really used on the m68000.
6769 ""
6770 "
6771 {
6772 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6773 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6774 }")
6776 ;; This is a normal call sequence.
6777 (define_insn ""
6778 [(call (match_operand:QI 0 "memory_operand" "o")
6779 (match_operand:SI 1 "general_operand" "g"))]
6780 ;; Operand 1 not really used on the m68000.
6782 "! flag_pic"
6783 "*
6784 #if defined (MOTOROLA) && !defined (USE_GAS)
6785 return \"jsr %0\";
6786 #else
6787 return \"jbsr %0\";
6788 #endif
6789 ")
6791 ;; This is a PIC call sequence.
6792 (define_insn ""
6793 [(call (match_operand:QI 0 "memory_operand" "o")
6794 (match_operand:SI 1 "general_operand" "g"))]
6795 ;; Operand 1 not really used on the m68000.
6797 "flag_pic"
6798 "*
6799 m68k_output_pic_call(operands[0]);
6800 return \"\";
6801 ")
6803 ;; Call subroutine, returning value in operand 0
6804 ;; (which must be a hard register).
6805 ;; See comments before "call" regarding PIC calls.
6806 (define_expand "call_value"
6807 [(set (match_operand 0 "" "")
6808 (call (match_operand:QI 1 "memory_operand" "")
6809 (match_operand:SI 2 "general_operand" "")))]
6810 ;; Operand 2 not really used on the m68000.
6811 ""
6812 "
6813 {
6814 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6815 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6816 }")
6818 ;; This is a normal call_value
6819 (define_insn ""
6820 [(set (match_operand 0 "" "=rf")
6821 (call (match_operand:QI 1 "memory_operand" "o")
6822 (match_operand:SI 2 "general_operand" "g")))]
6823 ;; Operand 2 not really used on the m68000.
6824 "! flag_pic"
6825 "*
6826 #if defined (MOTOROLA) && !defined (USE_GAS)
6827 return \"jsr %1\";
6828 #else
6829 return \"jbsr %1\";
6830 #endif
6831 ")
6833 ;; This is a PIC call_value
6834 (define_insn ""
6835 [(set (match_operand 0 "" "=rf")
6836 (call (match_operand:QI 1 "memory_operand" "o")
6837 (match_operand:SI 2 "general_operand" "g")))]
6838 ;; Operand 2 not really used on the m68000.
6839 "flag_pic"
6840 "*
6841 m68k_output_pic_call(operands[1]);
6842 return \"\";
6843 ")
6845 ;; Call subroutine returning any type.
6847 (define_expand "untyped_call"
6848 [(parallel [(call (match_operand 0 "" "")
6849 (const_int 0))
6850 (match_operand 1 "" "")
6851 (match_operand 2 "" "")])]
6852 "NEEDS_UNTYPED_CALL"
6853 "
6854 {
6855 int i;
6857 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6859 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6860 {
6861 rtx set = XVECEXP (operands[2], 0, i);
6862 emit_move_insn (SET_DEST (set), SET_SRC (set));
6863 }
6865 /* The optimizer does not know that the call sets the function value
6866 registers we stored in the result block. We avoid problems by
6867 claiming that all hard registers are used and clobbered at this
6868 point. */
6869 emit_insn (gen_blockage ());
6871 DONE;
6872 }")
6874 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6875 ;; all of memory. This blocks insns from being moved across this point.
6877 (define_insn "blockage"
6878 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6879 ""
6880 "")
6882 (define_insn "nop"
6883 [(const_int 0)]
6884 ""
6885 "nop")
6887 ;; Used for frameless functions which save no regs and allocate no locals.
6888 (define_insn "return"
6889 [(return)]
6890 "USE_RETURN_INSN"
6891 "*
6892 {
6893 if (current_function_pops_args == 0)
6894 return \"rts\";
6895 operands[0] = GEN_INT (current_function_pops_args);
6896 return \"rtd %0\";
6897 }")
6899 (define_insn "indirect_jump"
6900 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6901 ""
6902 "jmp %a0")
6903 \f
6904 ;; This should not be used unless the add/sub insns can't be.
6906 (define_insn ""
6907 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6908 (match_operand:QI 1 "address_operand" "p"))]
6909 ""
6910 "*
6911 {
6912 /* Recognize an insn that refers to a table of offsets. Such an insn will
6913 need to refer to a label on the insn. So output one. Use the
6914 label-number of the table of offsets to generate this label. This code,
6915 and similar code above, assumes that there will be at most one reference
6916 to each table. */
6917 if (GET_CODE (operands[1]) == PLUS
6918 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6919 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6920 {
6921 rtx labelref = XEXP (operands[1], 1);
6922 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6923 #ifdef SGS
6924 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6925 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6926 #else /* not SGS */
6927 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6928 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6929 #endif /* not SGS */
6930 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6931 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
6932 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6933 #ifdef SGS_SWITCH_TABLES
6934 /* Set flag saying we need to define the symbol
6935 LD%n (with value L%n-LI%n) at the end of the switch table. */
6936 switch_table_difference_label_flag = 1;
6937 #endif /* SGS_SWITCH_TABLES */
6938 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6939 }
6941 return \"lea %a1,%0\";
6942 }")
6943 \f
6944 ;; This is the first machine-dependent peephole optimization.
6945 ;; It is useful when a floating value is returned from a function call
6946 ;; and then is moved into an FP register.
6947 ;; But it is mainly intended to test the support for these optimizations.
6949 (define_peephole
6950 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6951 (set (match_operand:DF 0 "register_operand" "=f")
6952 (match_operand:DF 1 "register_operand" "ad"))]
6953 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6954 "*
6955 {
6956 rtx xoperands[2];
6957 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6958 output_asm_insn (\"move%.l %1,%@\", xoperands);
6959 output_asm_insn (\"move%.l %1,%-\", operands);
6960 return \"fmove%.d %+,%0\";
6961 }
6962 ")
6964 ;; Optimize a stack-adjust followed by a push of an argument.
6965 ;; This is said to happen frequently with -msoft-float
6966 ;; when there are consecutive library calls.
6968 (define_peephole
6969 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6970 (match_operand:SI 0 "const_int_operand" "n")))
6971 (set (match_operand:SF 1 "push_operand" "=m")
6972 (match_operand:SF 2 "general_operand" "rmfF"))]
6973 "INTVAL (operands[0]) >= 4
6974 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6975 "*
6976 {
6977 if (INTVAL (operands[0]) > 4)
6978 {
6979 rtx xoperands[2];
6980 xoperands[0] = stack_pointer_rtx;
6981 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6982 if (INTVAL (xoperands[1]) <= 8)
6983 {
6984 if (!TARGET_COLDFIRE)
6985 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6986 else
6987 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6988 }
6989 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6990 {
6991 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6992 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6993 }
6994 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6995 {
6996 if (TARGET_68040)
6997 output_asm_insn (\"add%.w %1,%0\", xoperands);
6998 else
6999 #ifdef MOTOROLA
7000 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7001 #else
7002 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7003 #endif
7004 }
7005 else
7006 output_asm_insn (\"add%.l %1,%0\", xoperands);
7007 }
7008 if (FP_REG_P (operands[2]))
7009 return \"fmove%.s %2,%@\";
7010 return \"move%.l %2,%@\";
7011 }")
7013 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7015 (define_peephole
7016 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7017 (match_operand:SI 0 "const_int_operand" "n")))
7018 (set (match_operand:SI 1 "push_operand" "=m")
7019 (match_operand:SI 2 "general_operand" "g"))]
7020 "INTVAL (operands[0]) >= 4
7021 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7022 "*
7023 {
7024 if (INTVAL (operands[0]) > 4)
7025 {
7026 rtx xoperands[2];
7027 xoperands[0] = stack_pointer_rtx;
7028 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7029 if (INTVAL (xoperands[1]) <= 8)
7030 {
7031 if (!TARGET_COLDFIRE)
7032 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7033 else
7034 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7035 }
7036 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7037 {
7038 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7039 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7040 }
7041 else if (INTVAL (xoperands[1]) <= 0x7FFF)
7042 {
7043 if (TARGET_68040)
7044 output_asm_insn (\"add%.w %1,%0\", xoperands);
7045 else
7046 {
7047 #ifdef MOTOROLA
7048 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7049 #else
7050 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7051 #endif
7052 }
7053 }
7054 else
7055 output_asm_insn (\"add%.l %1,%0\", xoperands);
7056 }
7057 if (operands[2] == const0_rtx)
7058 return \"clr%.l %@\";
7059 return \"move%.l %2,%@\";
7060 }")
7062 ;; Speed up pushing a single byte but leaving four bytes of space.
7064 (define_peephole
7065 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7066 (match_operand:QI 1 "general_operand" "dami"))
7067 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7068 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7069 "*
7070 {
7071 rtx xoperands[4];
7073 if (GET_CODE (operands[1]) == REG)
7074 return \"move%.l %1,%-\";
7076 xoperands[1] = operands[1];
7077 xoperands[2]
7078 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7079 xoperands[3] = stack_pointer_rtx;
7080 if (!TARGET_COLDFIRE)
7081 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7082 else
7083 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7084 return \"\";
7085 }")
7087 (define_peephole
7088 [(set (match_operand:SI 0 "register_operand" "=d")
7089 (const_int 0))
7090 (set (strict_low_part (subreg:HI (match_dup 0) 2))
7091 (match_operand:HI 1 "general_operand" "rmn"))]
7092 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7093 "*
7094 {
7095 if (GET_CODE (operands[1]) == CONST_INT)
7096 {
7097 if (operands[1] == const0_rtx
7098 && (DATA_REG_P (operands[0])
7099 || GET_CODE (operands[0]) == MEM)
7100 /* clr insns on 68000 read before writing.
7101 This isn't so on the 68010, but we have no TARGET_68010. */
7102 && ((TARGET_68020 || TARGET_COLDFIRE)
7103 || !(GET_CODE (operands[0]) == MEM
7104 && MEM_VOLATILE_P (operands[0]))))
7105 return \"clr%.w %0\";
7106 }
7107 return \"move%.w %1,%0\";
7108 }")
7110 ;; dbCC peepholes
7111 ;;
7112 ;; Turns
7113 ;; loop:
7114 ;; [ ... ]
7115 ;; jCC label ; abnormal loop termination
7116 ;; dbra dN, loop ; normal loop termination
7117 ;;
7118 ;; Into
7119 ;; loop:
7120 ;; [ ... ]
7121 ;; dbCC dN, loop
7122 ;; jCC label
7123 ;;
7124 ;; Which moves the jCC condition outside the inner loop for free.
7125 ;;
7127 (define_peephole
7128 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7129 [(cc0) (const_int 0)])
7130 (label_ref (match_operand 2 "" ""))
7131 (pc)))
7132 (parallel
7133 [(set (pc)
7134 (if_then_else
7135 (ne (match_operand:HI 0 "register_operand" "")
7136 (const_int 0))
7137 (label_ref (match_operand 1 "" ""))
7138 (pc)))
7139 (set (match_dup 0)
7140 (plus:HI (match_dup 0)
7141 (const_int -1)))])]
7142 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7143 "*
7144 {
7145 CC_STATUS_INIT;
7146 output_dbcc_and_branch (operands);
7147 return \"\";
7148 }")
7150 (define_peephole
7151 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7152 [(cc0) (const_int 0)])
7153 (label_ref (match_operand 2 "" ""))
7154 (pc)))
7155 (parallel
7156 [(set (pc)
7157 (if_then_else
7158 (ne (match_operand:SI 0 "register_operand" "")
7159 (const_int 0))
7160 (label_ref (match_operand 1 "" ""))
7161 (pc)))
7162 (set (match_dup 0)
7163 (plus:SI (match_dup 0)
7164 (const_int -1)))])]
7165 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7166 "*
7167 {
7168 CC_STATUS_INIT;
7169 output_dbcc_and_branch (operands);
7170 return \"\";
7171 }")
7173 (define_peephole
7174 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7175 [(cc0) (const_int 0)])
7176 (label_ref (match_operand 2 "" ""))
7177 (pc)))
7178 (parallel
7179 [(set (pc)
7180 (if_then_else
7181 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7182 (const_int -1))
7183 (const_int 0))
7184 (label_ref (match_operand 1 "" ""))
7185 (pc)))
7186 (set (match_dup 0)
7187 (plus:HI (match_dup 0)
7188 (const_int -1)))])]
7189 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7190 "*
7191 {
7192 CC_STATUS_INIT;
7193 output_dbcc_and_branch (operands);
7194 return \"\";
7195 }")
7197 (define_peephole
7198 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7199 [(cc0) (const_int 0)])
7200 (label_ref (match_operand 2 "" ""))
7201 (pc)))
7202 (parallel
7203 [(set (pc)
7204 (if_then_else
7205 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7206 (const_int -1))
7207 (const_int 0))
7208 (label_ref (match_operand 1 "" ""))
7209 (pc)))
7210 (set (match_dup 0)
7211 (plus:SI (match_dup 0)
7212 (const_int -1)))])]
7213 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7214 "*
7215 {
7216 CC_STATUS_INIT;
7217 output_dbcc_and_branch (operands);
7218 return \"\";
7219 }")
7221 \f
7222 (define_expand "tstxf"
7223 [(set (cc0)
7224 (match_operand:XF 0 "nonimmediate_operand" ""))]
7225 "TARGET_68881"
7226 "m68k_last_compare_had_fp_operands = 1;")
7228 (define_insn ""
7229 [(set (cc0)
7230 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7231 "TARGET_68881"
7232 "*
7233 {
7234 cc_status.flags = CC_IN_68881;
7235 return \"ftst%.x %0\";
7236 }")
7238 (define_expand "cmpxf"
7239 [(set (cc0)
7240 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7241 (match_operand:XF 1 "nonimmediate_operand" "")))]
7242 "TARGET_68881"
7243 "m68k_last_compare_had_fp_operands = 1;")
7245 (define_insn ""
7246 [(set (cc0)
7247 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7248 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7249 "TARGET_68881"
7250 "*
7251 {
7252 cc_status.flags = CC_IN_68881;
7253 #ifdef SGS_CMP_ORDER
7254 if (REG_P (operands[0]))
7255 {
7256 if (REG_P (operands[1]))
7257 return \"fcmp%.x %0,%1\";
7258 else
7259 return \"fcmp%.x %0,%f1\";
7260 }
7261 cc_status.flags |= CC_REVERSED;
7262 return \"fcmp%.x %1,%f0\";
7263 #else
7264 if (REG_P (operands[0]))
7265 {
7266 if (REG_P (operands[1]))
7267 return \"fcmp%.x %1,%0\";
7268 else
7269 return \"fcmp%.x %f1,%0\";
7270 }
7271 cc_status.flags |= CC_REVERSED;
7272 return \"fcmp%.x %f0,%1\";
7273 #endif
7274 }")
7276 (define_insn "extendsfxf2"
7277 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7278 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7279 "TARGET_68881"
7280 "*
7281 {
7282 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7283 {
7284 if (REGNO (operands[0]) == REGNO (operands[1]))
7285 {
7286 /* Extending float to double in an fp-reg is a no-op.
7287 NOTICE_UPDATE_CC has already assumed that the
7288 cc will be set. So cancel what it did. */
7289 cc_status = cc_prev_status;
7290 return \"\";
7291 }
7292 return \"f%$move%.x %1,%0\";
7293 }
7294 if (FP_REG_P (operands[0]))
7295 {
7296 if (FP_REG_P (operands[1]))
7297 return \"f%$move%.x %1,%0\";
7298 else if (ADDRESS_REG_P (operands[1]))
7299 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7300 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7301 return output_move_const_single (operands);
7302 return \"f%$move%.s %f1,%0\";
7303 }
7304 return \"fmove%.x %f1,%0\";
7305 }")
7308 (define_insn "extenddfxf2"
7309 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7310 (float_extend:XF
7311 (match_operand:DF 1 "general_operand" "f,rmE")))]
7312 "TARGET_68881"
7313 "*
7314 {
7315 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7316 {
7317 if (REGNO (operands[0]) == REGNO (operands[1]))
7318 {
7319 /* Extending float to double in an fp-reg is a no-op.
7320 NOTICE_UPDATE_CC has already assumed that the
7321 cc will be set. So cancel what it did. */
7322 cc_status = cc_prev_status;
7323 return \"\";
7324 }
7325 return \"fmove%.x %1,%0\";
7326 }
7327 if (FP_REG_P (operands[0]))
7328 {
7329 if (REG_P (operands[1]))
7330 {
7331 rtx xoperands[2];
7332 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7333 output_asm_insn (\"move%.l %1,%-\", xoperands);
7334 output_asm_insn (\"move%.l %1,%-\", operands);
7335 return \"f%&move%.d %+,%0\";
7336 }
7337 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7338 return output_move_const_double (operands);
7339 return \"f%&move%.d %f1,%0\";
7340 }
7341 return \"fmove%.x %f1,%0\";
7342 }")
7344 (define_insn "truncxfdf2"
7345 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7346 (float_truncate:DF
7347 (match_operand:XF 1 "general_operand" "f,f")))]
7348 "TARGET_68881"
7349 "*
7350 {
7351 if (REG_P (operands[0]))
7352 {
7353 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7354 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7355 return \"move%.l %+,%0\";
7356 }
7357 return \"fmove%.d %f1,%0\";
7358 }")
7360 (define_insn "truncxfsf2"
7361 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7362 (float_truncate:SF
7363 (match_operand:XF 1 "general_operand" "f")))]
7364 "TARGET_68881"
7365 "fmove%.s %f1,%0")
7367 (define_insn "floatsixf2"
7368 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7369 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7370 "TARGET_68881"
7371 "fmove%.l %1,%0")
7373 (define_insn "floathixf2"
7374 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7375 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7376 "TARGET_68881"
7377 "fmove%.w %1,%0")
7379 (define_insn "floatqixf2"
7380 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7381 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7382 "TARGET_68881"
7383 "fmove%.b %1,%0")
7385 (define_insn "ftruncxf2"
7386 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7387 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7388 "TARGET_68881"
7389 "*
7390 {
7391 if (FP_REG_P (operands[1]))
7392 return \"fintrz%.x %f1,%0\";
7393 return \"fintrz%.x %f1,%0\";
7394 }")
7396 (define_insn "fixxfqi2"
7397 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
7398 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7399 "TARGET_68881"
7400 "fmove%.b %1,%0")
7402 (define_insn "fixxfhi2"
7403 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
7404 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7405 "TARGET_68881"
7406 "fmove%.w %1,%0")
7408 (define_insn "fixxfsi2"
7409 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
7410 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7411 "TARGET_68881"
7412 "fmove%.l %1,%0")
7414 (define_insn ""
7415 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7416 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7417 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7418 "TARGET_68881"
7419 "fadd%.l %2,%0")
7421 (define_insn ""
7422 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7423 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7424 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7425 "TARGET_68881"
7426 "fadd%.w %2,%0")
7428 (define_insn ""
7429 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7430 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7431 (match_operand:XF 1 "general_operand" "0")))]
7432 "TARGET_68881"
7433 "fadd%.b %2,%0")
7435 (define_insn "addxf3"
7436 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7437 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7438 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7439 "TARGET_68881"
7440 "*
7441 {
7442 if (REG_P (operands[2]))
7443 return \"fadd%.x %2,%0\";
7444 return \"fadd%.x %f2,%0\";
7445 }")
7447 (define_insn ""
7448 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7449 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7450 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7451 "TARGET_68881"
7452 "fsub%.l %2,%0")
7454 (define_insn ""
7455 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7456 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7457 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7458 "TARGET_68881"
7459 "fsub%.w %2,%0")
7461 (define_insn ""
7462 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7463 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7464 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7465 "TARGET_68881"
7466 "fsub%.b %2,%0")
7468 (define_insn "subxf3"
7469 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7470 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7471 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7472 "TARGET_68881"
7473 "*
7474 {
7475 if (REG_P (operands[2]))
7476 return \"fsub%.x %2,%0\";
7477 return \"fsub%.x %f2,%0\";
7478 }")
7480 (define_insn ""
7481 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7482 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7483 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7484 "TARGET_68881"
7485 "fmul%.l %2,%0")
7487 (define_insn ""
7488 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7489 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7490 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7491 "TARGET_68881"
7492 "fmul%.w %2,%0")
7494 (define_insn ""
7495 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7496 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7497 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7498 "TARGET_68881"
7499 "fmul%.b %2,%0")
7501 (define_insn "mulxf3"
7502 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7503 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7504 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7505 "TARGET_68881"
7506 "*
7507 {
7508 if (REG_P (operands[2]))
7509 return \"fmul%.x %2,%0\";
7510 return \"fmul%.x %f2,%0\";
7511 }")
7513 (define_insn ""
7514 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7515 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7516 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7517 "TARGET_68881"
7518 "fdiv%.l %2,%0")
7520 (define_insn ""
7521 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7522 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7523 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7524 "TARGET_68881"
7525 "fdiv%.w %2,%0")
7527 (define_insn ""
7528 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7529 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7530 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7531 "TARGET_68881"
7532 "fdiv%.b %2,%0")
7534 (define_insn "divxf3"
7535 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7536 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7537 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7538 "TARGET_68881"
7539 "*
7540 {
7541 if (REG_P (operands[2]))
7542 return \"fdiv%.x %2,%0\";
7543 return \"fdiv%.x %f2,%0\";
7544 }")
7546 (define_expand "negxf2"
7547 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7548 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7549 ""
7550 "
7551 {
7552 if (!TARGET_68881)
7553 {
7554 rtx result;
7555 rtx target;
7556 rtx insns;
7558 start_sequence ();
7559 target = operand_subword (operands[0], 0, 1, XFmode);
7560 result = expand_binop (SImode, xor_optab,
7561 operand_subword_force (operands[1], 0, XFmode),
7562 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7563 if (result == 0)
7564 abort ();
7566 if (result != target)
7567 emit_move_insn (result, target);
7569 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7570 operand_subword_force (operands[1], 1, XFmode));
7571 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7572 operand_subword_force (operands[1], 2, XFmode));
7574 insns = get_insns ();
7575 end_sequence ();
7577 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7578 DONE;
7579 }
7580 }")
7582 (define_insn "negxf2_68881"
7583 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7584 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7585 "TARGET_68881"
7586 "*
7587 {
7588 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7589 return \"fneg%.x %1,%0\";
7590 return \"fneg%.x %f1,%0\";
7591 }")
7593 (define_expand "absxf2"
7594 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7595 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7596 ""
7597 "
7598 {
7599 if (!TARGET_68881)
7600 {
7601 rtx result;
7602 rtx target;
7603 rtx insns;
7605 start_sequence ();
7606 target = operand_subword (operands[0], 0, 1, XFmode);
7607 result = expand_binop (SImode, and_optab,
7608 operand_subword_force (operands[1], 0, XFmode),
7609 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7610 if (result == 0)
7611 abort ();
7613 if (result != target)
7614 emit_move_insn (result, target);
7616 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7617 operand_subword_force (operands[1], 1, XFmode));
7618 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7619 operand_subword_force (operands[1], 2, XFmode));
7621 insns = get_insns ();
7622 end_sequence ();
7624 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7625 DONE;
7626 }
7627 }")
7629 (define_insn "absxf2_68881"
7630 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7631 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7632 "TARGET_68881"
7633 "*
7634 {
7635 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7636 return \"fabs%.x %1,%0\";
7637 return \"fabs%.x %f1,%0\";
7638 }")
7640 (define_insn "sqrtxf2"
7641 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7642 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7643 "TARGET_68881"
7644 "fsqrt%.x %1,%0")
7646 (define_insn "sinsf2"
7647 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7648 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
7649 "TARGET_68881 && flag_unsafe_math_optimizations"
7650 "*
7651 {
7652 if (FP_REG_P (operands[1]))
7653 return \"fsin%.x %1,%0\";
7654 else
7655 return \"fsin%.s %1,%0\";
7656 }")
7658 (define_insn "sindf2"
7659 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7660 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
7661 "TARGET_68881 && flag_unsafe_math_optimizations"
7662 "*
7663 {
7664 if (FP_REG_P (operands[1]))
7665 return \"fsin%.x %1,%0\";
7666 else
7667 return \"fsin%.d %1,%0\";
7668 }")
7670 (define_insn "sinxf2"
7671 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7672 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
7673 "TARGET_68881 && flag_unsafe_math_optimizations"
7674 "fsin%.x %1,%0")
7676 (define_insn "cossf2"
7677 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7678 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
7679 "TARGET_68881 && flag_unsafe_math_optimizations"
7680 "*
7681 {
7682 if (FP_REG_P (operands[1]))
7683 return \"fcos%.x %1,%0\";
7684 else
7685 return \"fcos%.s %1,%0\";
7686 }")
7688 (define_insn "cosdf2"
7689 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7690 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
7691 "TARGET_68881 && flag_unsafe_math_optimizations"
7692 "*
7693 {
7694 if (FP_REG_P (operands[1]))
7695 return \"fcos%.x %1,%0\";
7696 else
7697 return \"fcos%.d %1,%0\";
7698 }")
7700 (define_insn "cosxf2"
7701 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7702 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
7703 "TARGET_68881 && flag_unsafe_math_optimizations"
7704 "fcos%.x %1,%0")
7706 (define_insn "trap"
7707 [(trap_if (const_int -1) (const_int 7))]
7708 ""
7709 "trap %#7")
7711 (define_insn "conditional_trap"
7712 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7713 [(cc0) (const_int 0)])
7714 (match_operand:SI 1 "const_int_operand" "I"))]
7715 "TARGET_68020 && ! flags_in_68881 ()"
7716 "*
7717 {
7718 switch (GET_CODE (operands[0]))
7719 {
7720 case EQ: return \"trapeq\";
7721 case NE: return \"trapne\";
7722 case GT: return \"trapgt\";
7723 case GTU: return \"traphi\";
7724 case LT: return \"traplt\";
7725 case LTU: return \"trapcs\";
7726 case GE: return \"trapge\";
7727 case GEU: return \"trapcc\";
7728 case LE: return \"traple\";
7729 case LEU: return \"trapls\";
7730 default: abort();
7731 }
7732 }")