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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2418 };
2421 {
2432 /* Core 2 */
2434 /* Core i7 */
2436 /* Core avx2 */
2447 };
2450 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3242 else
3244 }
3246 {
3249 }
3256 {
3259 /* Default cpu tuning to the architecture. */
3384 }
3399 {
3403 {
3405 {
3407 {
3415 }
3416 else
3419 }
3420 }
3421 else
3422 {
3423 /* Adjust tuning when compiling for 32-bit ABI. */
3425 {
3433 }
3434 }
3435 /* Intel CPUs have always interpreted SSE prefetch instructions as
3436 NOPs; so, we can enable SSE prefetch instructions even when
3437 -mtune (rather than -march) points us to a processor that has them.
3438 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3439 higher processors. */
3444 }
3454 #ifndef USE_IX86_FRAME_POINTER
3455 #define USE_IX86_FRAME_POINTER 0
3456 #endif
3458 #ifndef USE_X86_64_FRAME_POINTER
3459 #define USE_X86_64_FRAME_POINTER 0
3460 #endif
3462 /* Set the default values for switches whose default depends on TARGET_64BIT
3463 in case they weren't overwritten by command line options. */
3465 {
3472 }
3473 else
3474 {
3481 }
3486 else
3489 /* Arrange to set up i386_stack_locals for all functions. */
3492 /* Validate -mregparm= value. */
3494 {
3498 {
3502 }
3503 }
3507 /* Default align_* from the processor table. */
3509 {
3512 }
3514 {
3517 }
3519 {
3521 }
3523 /* Provide default for -mbranch-cost= value. */
3528 {
3531 /* Enable by default the SSE and MMX builtins. Do allow the user to
3532 explicitly disable any of these. In particular, disabling SSE and
3533 MMX for kernel code is extremely useful. */
3535 ix86_isa_flags
3541 }
3542 else
3543 {
3547 ix86_isa_flags
3550 /* i386 ABI does not specify red zone. It still makes sense to use it
3551 when programmer takes care to stack from being destroyed. */
3554 }
3556 /* Keep nonleaf frame pointers. */
3562 /* If we're doing fast math, we don't care about comparison order
3563 wrt NaNs. This lets us use a shorter comparison sequence. */
3567 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3568 since the insns won't need emulation. */
3572 /* Likewise, if the target doesn't have a 387, or we've specified
3573 software floating point, don't use 387 inline intrinsics. */
3577 /* Turn on MMX builtins for -msse. */
3581 /* Enable SSE prefetch. */
3585 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3589 /* Turn on lzcnt instruction for -mabm. */
3593 /* Validate -mpreferred-stack-boundary= value or default it to
3594 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3597 {
3603 {
3607 else
3610 }
3611 else
3612 ix86_preferred_stack_boundary
3614 }
3616 /* Set the default value for -mstackrealign. */
3622 /* Validate -mincoming-stack-boundary= value or default it to
3623 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3626 {
3631 else
3632 {
3633 ix86_user_incoming_stack_boundary
3635 ix86_incoming_stack_boundary
3637 }
3638 }
3640 /* Accept -msseregparm only if at least SSE support is enabled. */
3646 {
3648 {
3650 {
3653 }
3655 {
3658 }
3659 }
3660 }
3661 else
3664 /* If the i387 is disabled, then do not return values in it. */
3668 /* Use external vectorized library in vectorizing intrinsics. */
3671 {
3682 }
3690 /* ??? Unwind info is not correct around the CFG unless either a frame
3691 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3692 unwind info generation to be aware of the CFG and propagating states
3693 around edges. */
3696 && flag_omit_frame_pointer
3698 {
3704 }
3706 /* If stack probes are required, the space used for large function
3707 arguments on the stack must also be probed, so enable
3708 -maccumulate-outgoing-args so this happens in the prologue. */
3711 {
3716 }
3718 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3719 {
3725 }
3727 /* When scheduling description is not available, disable scheduler pass
3728 so it won't slow down the compilation and make x87 code slower. */
3749 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3751 && HAVE_prefetch
3756 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3757 can be optimized to ap = __builtin_next_arg (0). */
3762 {
3765 {
3768 ix86_gen_tls_local_dynamic_base_64
3770 }
3771 else
3772 {
3775 ix86_gen_tls_local_dynamic_base_64
3777 }
3778 }
3779 else
3780 {
3783 }
3786 {
3795 }
3796 else
3797 {
3806 }
3808 #ifdef USE_IX86_CLD
3809 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3812 #endif
3815 {
3820 }
3822 {
3826 }
3828 {
3829 #if defined(PROFILE_BEFORE_PROLOGUE)
3831 #else
3833 #endif
3834 }
3837 {
3838 /* When not optimize for size, enable vzeroupper optimization for
3839 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3840 AVX unaligned load/store. */
3842 {
3852 /* Enable 128-bit AVX instruction generation
3853 for the auto-vectorizer. */
3857 }
3858 }
3859 else
3860 {
3861 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3863 }
3866 {
3873 {
3876 {
3878 q++;
3879 }
3880 else
3885 else
3886 {
3889 {
3892 }
3895 {
3899 }
3900 }
3905 else
3907 }
3908 }
3915 /* Default long double to 64-bit for Bionic. */
3920 /* Save the initial options in case the user does function specific
3921 options. */
3923 target_option_default_node = target_option_current_node
3925 }
3927 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3929 static void
3931 {
3932 static struct register_pass_info insert_vzeroupper_info
3935 };
3940 /* This needs to be done at start up. It's convenient to do it here. */
3942 }
3944 /* Update register usage after having seen the compiler flags. */
3946 static void
3948 {
3952 /* The PIC register, if it exists, is fixed. */
3957 /* For 32-bit targets, squash the REX registers. */
3959 {
3964 }
3966 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3974 {
3975 /* Set/reset conditionally defined registers from
3976 CALL_USED_REGISTERS initializer. */
3980 /* Calculate registers of CLOBBERED_REGS register set
3981 as call used registers from GENERAL_REGS register set. */
3985 }
3987 /* If MMX is disabled, squash the registers. */
3993 /* If SSE is disabled, squash the registers. */
3999 /* If the FPU is disabled, squash the registers. */
4004 }
4006 \f
4007 /* Save the current options */
4009 static void
4011 {
4022 /* The fields are char but the variables are not; make sure the
4023 values fit in the fields. */
4028 }
4030 /* Restore the current options */
4032 static void
4034 {
4050 /* Recreate the arch feature tests if the arch changed */
4052 {
4057 }
4059 /* Recreate the tune optimization tests */
4061 {
4066 }
4067 }
4069 /* Print the current options */
4071 static void
4074 {
4096 {
4099 }
4100 }
4102 \f
4103 /* Inner function to process the attribute((target(...))), take an argument and
4104 set the current options from the argument. If we have a list, recursively go
4105 over the list. */
4107 static bool
4110 {
4114 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4115 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4116 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4117 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4118 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4120 enum ix86_opt_type
4121 {
4122 ix86_opt_unknown,
4123 ix86_opt_yes,
4124 ix86_opt_no,
4125 ix86_opt_str,
4126 ix86_opt_enum,
4127 ix86_opt_isa
4128 };
4130 static const struct
4131 {
4138 /* isa options */
4175 /* enum options */
4178 /* string options */
4182 /* flag options */
4184 OPT_mcld,
4185 MASK_CLD),
4188 OPT_mfancy_math_387,
4189 MASK_NO_FANCY_MATH_387),
4192 OPT_mieee_fp,
4193 MASK_IEEE_FP),
4196 OPT_minline_all_stringops,
4197 MASK_INLINE_ALL_STRINGOPS),
4200 OPT_minline_stringops_dynamically,
4201 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4204 OPT_mno_align_stringops,
4205 MASK_NO_ALIGN_STRINGOPS),
4208 OPT_mrecip,
4209 MASK_RECIP),
4211 };
4213 /* If this is a list, recurse to get the options. */
4215 {
4225 }
4228 {
4231 }
4233 /* Handle multiple arguments separated by commas. */
4237 {
4251 {
4255 }
4256 else
4257 {
4260 }
4262 /* Recognize no-xxx. */
4264 {
4268 }
4269 else
4272 /* Find the option. */
4276 {
4284 {
4289 }
4290 }
4292 /* Process the option. */
4294 {
4297 }
4300 {
4306 }
4309 {
4315 else
4317 }
4320 {
4322 {
4325 }
4326 else
4328 }
4331 {
4339 global_dc);
4340 else
4341 {
4344 }
4345 }
4347 else
4349 }
4352 }
4354 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4356 tree
4358 {
4373 /* Process each of the options on the chain. */
4378 /* If the changed options are different from the default, rerun
4379 ix86_option_override_internal, and then save the options away.
4380 The string options are are attribute options, and will be undone
4381 when we copy the save structure. */
4387 {
4388 /* If we are using the default tune= or arch=, undo the string assigned,
4389 and use the default. */
4400 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4404 {
4407 }
4409 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4412 /* Add any builtin functions with the new isa if any. */
4415 /* Save the current options unless we are validating options for
4416 #pragma. */
4423 /* Free up memory allocated to hold the strings */
4426 }
4429 }
4431 /* Hook to validate attribute((target("string"))). */
4433 static bool
4436 tree args,
4438 {
4442 /* attribute((target("default"))) does nothing, beyond
4443 affecting multi-versioning. */
4454 /* If the function changed the optimization levels as well as setting target
4455 options, start with the optimizations specified. */
4460 /* The target attributes may also change some optimization flags, so update
4461 the optimization options if necessary. */
4470 {
4475 }
4484 }
4486 \f
4487 /* Hook to determine if one function can safely inline another. */
4489 static bool
4491 {
4496 /* If callee has no option attributes, then it is ok to inline. */
4500 /* If caller has no option attributes, but callee does then it is not ok to
4501 inline. */
4505 else
4506 {
4510 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4511 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4512 function. */
4517 /* See if we have the same non-isa options. */
4521 /* See if arch, tune, etc. are the same. */
4534 else
4536 }
4539 }
4541 \f
4542 /* Remember the last target of ix86_set_current_function. */
4545 /* Establish appropriate back-end context for processing the function
4546 FNDECL. The argument might be NULL to indicate processing at top
4547 level, outside of any function scope. */
4548 static void
4550 {
4551 /* Only change the context if the function changes. This hook is called
4552 several times in the course of compiling a function, and we don't want to
4553 slow things down too much or call target_reinit when it isn't safe. */
4555 {
4556 tree old_tree = (ix86_previous_fndecl
4560 tree new_tree = (fndecl
4566 ;
4569 {
4573 }
4576 {
4582 }
4583 }
4584 }
4586 \f
4587 /* Return true if this goes in large data/bss. */
4589 static bool
4591 {
4595 /* Functions are never large data. */
4600 {
4606 }
4607 else
4608 {
4611 /* If this is an incomplete type with size 0, then we can't put it
4612 in data because it might be too big when completed. */
4615 }
4618 }
4620 /* Switch to the appropriate section for output of DECL.
4621 DECL is either a `VAR_DECL' node or a constant of some sort.
4622 RELOC indicates whether forming the initial value of DECL requires
4623 link-time relocations. */
4626 ATTRIBUTE_UNUSED;
4631 {
4634 {
4638 {
4672 /* We don't split these for medium model. Place them into
4673 default sections and hope for best. */
4675 }
4677 {
4678 /* We might get called with string constants, but get_named_section
4679 doesn't like them as they are not DECLs. Also, we need to set
4680 flags in that case. */
4684 }
4685 }
4687 }
4689 /* Build up a unique section name, expressed as a
4690 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4691 RELOC indicates whether the initial value of EXP requires
4692 link-time relocations. */
4694 static void ATTRIBUTE_UNUSED
4696 {
4699 {
4701 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4705 {
4729 /* We don't split these for medium model. Place them into
4730 default sections and hope for best. */
4732 }
4734 {
4741 /* If we're using one_only, then there needs to be a .gnu.linkonce
4742 prefix to the section name. */
4749 }
4750 }
4752 }
4754 #ifdef COMMON_ASM_OP
4755 /* This says how to output assembler code to declare an
4756 uninitialized external linkage data object.
4758 For medium model x86-64 we need to use .largecomm opcode for
4759 large objects. */
4760 void
4764 {
4768 else
4773 }
4774 #endif
4776 /* Utility function for targets to use in implementing
4777 ASM_OUTPUT_ALIGNED_BSS. */
4779 void
4783 {
4787 else
4790 #ifdef ASM_DECLARE_OBJECT_NAME
4793 #else
4794 /* Standard thing is just output label for the object. */
4798 }
4799 \f
4800 /* Decide whether we must probe the stack before any space allocation
4801 on this target. It's essentially TARGET_STACK_PROBE except when
4802 -fstack-check causes the stack to be already probed differently. */
4804 bool
4806 {
4807 /* Do not probe the stack twice if static stack checking is enabled. */
4812 }
4813 \f
4814 /* Decide whether we can make a sibling call to a function. DECL is the
4815 declaration of the function being targeted by the call and EXP is the
4816 CALL_EXPR representing the call. */
4818 static bool
4820 {
4824 /* If we are generating position-independent code, we cannot sibcall
4825 optimize any indirect call, or a direct call to a global function,
4826 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4828 && !TARGET_64BIT
4829 && flag_pic
4833 /* If we need to align the outgoing stack, then sibcalling would
4834 unalign the stack, which may break the called function. */
4840 {
4843 }
4844 else
4845 {
4846 /* We're looking at the CALL_EXPR, we need the type of the function. */
4851 }
4853 /* Check that the return value locations are the same. Like
4854 if we are returning floats on the 80387 register stack, we cannot
4855 make a sibcall from a function that doesn't return a float to a
4856 function that does or, conversely, from a function that does return
4857 a float to a function that doesn't; the necessary stack adjustment
4858 would not be executed. This is also the place we notice
4859 differences in the return value ABI. Note that it is ok for one
4860 of the functions to have void return type as long as the return
4861 value of the other is passed in a register. */
4866 {
4869 }
4871 ;
4876 {
4877 /* The SYSV ABI has more call-clobbered registers;
4878 disallow sibcalls from MS to SYSV. */
4882 }
4883 else
4884 {
4885 /* If this call is indirect, we'll need to be able to use a
4886 call-clobbered register for the address of the target function.
4887 Make sure that all such registers are not used for passing
4888 parameters. Note that DLLIMPORT functions are indirect. */
4891 {
4893 {
4894 /* ??? Need to count the actual number of registers to be used,
4895 not the possible number of registers. Fix later. */
4897 }
4898 }
4899 }
4901 /* Otherwise okay. That also includes certain types of indirect calls. */
4903 }
4905 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4906 and "sseregparm" calling convention attributes;
4907 arguments as in struct attribute_spec.handler. */
4909 static tree
4911 tree args,
4914 {
4919 {
4921 name);
4924 }
4926 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4928 {
4929 tree cst;
4932 {
4934 }
4937 {
4939 }
4943 {
4946 name);
4948 }
4950 {
4954 }
4957 }
4960 {
4961 /* Do not warn when emulating the MS ABI. */
4966 name);
4969 }
4971 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4973 {
4975 {
4977 }
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine stdcall with fastcall (redundant), regparm and
4993 sseregparm. */
4995 {
4997 {
4999 }
5001 {
5003 }
5005 {
5007 }
5008 }
5010 /* Can combine cdecl with regparm and sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 {
5030 name);
5032 {
5034 }
5036 {
5038 }
5040 {
5042 }
5043 }
5045 /* Can combine sseregparm with all attributes. */
5048 }
5050 /* The transactional memory builtins are implicitly regparm or fastcall
5051 depending on the ABI. Override the generic do-nothing attribute that
5052 these builtins were declared with, and replace it with one of the two
5053 attributes that we expect elsewhere. */
5055 static tree
5057 tree args ATTRIBUTE_UNUSED,
5060 {
5061 tree alt;
5063 /* In no case do we want to add the placeholder attribute. */
5066 /* The 64-bit ABI is unchanged for transactional memory. */
5070 /* ??? Is there a better way to validate 32-bit windows? We have
5071 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5074 else
5075 {
5078 }
5082 }
5084 /* This function determines from TYPE the calling-convention. */
5086 unsigned int
5088 {
5091 tree attrs;
5098 {
5108 /* Regparam isn't allowed for thiscall and fastcall. */
5110 {
5115 }
5119 }
5126 || is_stdarg
5132 }
5134 /* Return 0 if the attributes for two types are incompatible, 1 if they
5135 are compatible, and 2 if they are nearly compatible (which causes a
5136 warning to be generated). */
5138 static int
5140 {
5156 }
5157 \f
5158 /* Return the regparm value for a function with the indicated TYPE and DECL.
5159 DECL may be NULL when calling function indirectly
5160 or considering a libcall. */
5162 static int
5164 {
5165 tree attr;
5176 {
5179 {
5182 }
5183 }
5189 /* Use register calling convention for local functions when possible. */
5192 && optimize
5194 {
5195 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5198 {
5201 /* Make sure no regparm register is taken by a
5202 fixed register variable. */
5207 /* We don't want to use regparm(3) for nested functions as
5208 these use a static chain pointer in the third argument. */
5212 /* In 32-bit mode save a register for the split stack. */
5216 /* Each fixed register usage increases register pressure,
5217 so less registers should be used for argument passing.
5218 This functionality can be overriden by an explicit
5219 regparm value. */
5222 globals++;
5224 local_regparm
5229 }
5230 }
5233 }
5235 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5236 DFmode (2) arguments in SSE registers for a function with the
5237 indicated TYPE and DECL. DECL may be NULL when calling function
5238 indirectly or considering a libcall. Otherwise return 0. */
5240 static int
5242 {
5245 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5246 by the sseregparm attribute. */
5249 {
5251 {
5253 {
5257 else
5260 }
5262 }
5265 }
5267 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5268 (and DFmode for SSE2) arguments in SSE registers. */
5271 {
5272 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5276 }
5279 }
5281 /* Return true if EAX is live at the start of the function. Used by
5282 ix86_expand_prologue to determine if we need special help before
5283 calling allocate_stack_worker. */
5285 static bool
5287 {
5288 /* Cheat. Don't bother working forward from ix86_function_regparm
5289 to the function type to whether an actual argument is located in
5290 eax. Instead just look at cfg info, which is still close enough
5291 to correct at this point. This gives false positives for broken
5292 functions that might use uninitialized data that happens to be
5293 allocated in eax, but who cares? */
5295 }
5297 static bool
5299 {
5300 tree attr;
5303 {
5309 /* For 32-bit MS-ABI the default is to keep aggregate
5310 return pointer. */
5313 }
5315 }
5317 /* Value is the number of bytes of arguments automatically
5318 popped when returning from a subroutine call.
5319 FUNDECL is the declaration node of the function (as a tree),
5320 FUNTYPE is the data type of the function (as a tree),
5321 or for a library call it is an identifier node for the subroutine name.
5322 SIZE is the number of bytes of arguments passed on the stack.
5324 On the 80386, the RTD insn may be used to pop them if the number
5325 of args is fixed, but if the number is variable then the caller
5326 must pop them all. RTD can't be used for library calls now
5327 because the library is compiled with the Unix compiler.
5328 Use of RTD is a selectable option, since it is incompatible with
5329 standard Unix calling sequences. If the option is not selected,
5330 the caller must always pop the args.
5332 The attribute stdcall is equivalent to RTD on a per module basis. */
5334 static int
5336 {
5339 /* None of the 64-bit ABIs pop arguments. */
5350 /* Lose any fake structure return argument if it is passed on the stack. */
5353 {
5357 }
5360 }
5362 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5364 static bool
5366 {
5367 /* Check operand constraints in case hard registers were propagated
5368 into insn pattern. This check prevents combine pass from
5369 generating insn patterns with invalid hard register operands.
5370 These invalid insns can eventually confuse reload to error out
5371 with a spill failure. See also PRs 46829 and 46843. */
5373 {
5380 {
5388 /* A unary operator may be accepted by the predicate, but it
5389 is irrelevant for matching constraints. */
5394 {
5402 }
5409 /* Operand has no constraints, anything is OK. */
5413 {
5416 && operands_match_p
5420 {
5423 }
5424 }
5428 }
5429 }
5432 }
5433 \f
5434 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5436 static unsigned HOST_WIDE_INT
5438 {
5442 }
5443 \f
5444 /* Argument support functions. */
5446 /* Return true when register may be used to pass function parameters. */
5447 bool
5449 {
5454 {
5458 else
5464 }
5467 {
5470 }
5471 else
5472 {
5476 }
5478 /* TODO: The function should depend on current function ABI but
5479 builtins.c would need updating then. Therefore we use the
5480 default ABI. */
5482 /* RAX is used as hidden argument to va_arg functions. */
5488 else
5495 }
5497 /* Return if we do not know how to pass TYPE solely in registers. */
5499 static bool
5501 {
5505 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5506 The layout_type routine is crafty and tries to trick us into passing
5507 currently unsupported vector types on the stack by using TImode. */
5510 }
5512 /* It returns the size, in bytes, of the area reserved for arguments passed
5513 in registers for the function represented by fndecl dependent to the used
5514 abi format. */
5515 int
5517 {
5521 else
5526 }
5528 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5529 call abi used. */
5530 enum calling_abi
5532 {
5534 {
5537 {
5540 }
5544 }
5546 }
5548 static bool
5550 {
5552 {
5556 else
5558 }
5560 }
5562 static enum calling_abi
5564 {
5568 }
5570 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5571 call abi used. */
5572 enum calling_abi
5574 {
5578 }
5580 /* Write the extra assembler code needed to declare a function properly. */
5582 void
5584 tree decl)
5585 {
5589 {
5595 }
5597 #ifdef SUBTARGET_ASM_UNWIND_INIT
5599 #endif
5603 /* Output magic byte marker, if hot-patch attribute is set. */
5605 {
5607 {
5608 /* leaq [%rsp + 0], %rsp */
5611 }
5612 else
5613 {
5614 /* movl.s %edi, %edi
5615 push %ebp
5616 movl.s %esp, %ebp */
5619 }
5620 }
5621 }
5623 /* regclass.c */
5626 /* Implementation of call abi switching target hook. Specific to FNDECL
5627 the specific call register sets are set. See also
5628 ix86_conditional_register_usage for more details. */
5629 void
5631 {
5634 else
5636 }
5638 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5639 expensive re-initialization of init_regs each time we switch function context
5640 since this is needed only during RTL expansion. */
5641 static void
5643 {
5647 }
5649 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5650 for a call to a function whose data type is FNTYPE.
5651 For a library call, FNTYPE is 0. */
5653 void
5657 tree fndecl,
5659 {
5665 {
5668 }
5669 else
5670 {
5673 }
5677 /* Set up the number of registers to use for passing arguments. */
5684 {
5686 ? X86_64_REGPARM_MAX
5688 }
5690 {
5693 {
5695 ? X86_64_SSE_REGPARM_MAX
5697 }
5698 }
5705 /* Because type might mismatch in between caller and callee, we need to
5706 use actual type of function for local calls.
5707 FIXME: cgraph_analyze can be told to actually record if function uses
5708 va_start so for local functions maybe_vaarg can be made aggressive
5709 helping K&R code.
5710 FIXME: once typesytem is fixed, we won't need this code anymore. */
5718 {
5719 /* If there are variable arguments, then we won't pass anything
5720 in registers in 32-bit mode. */
5722 {
5730 }
5732 /* Use ecx and edx registers if function has fastcall attribute,
5733 else look for regparm information. */
5735 {
5738 {
5741 }
5743 {
5746 }
5747 else
5749 }
5751 /* Set up the number of SSE registers used for passing SFmode
5752 and DFmode arguments. Warn for mismatching ABI. */
5754 }
5755 }
5757 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5758 But in the case of vector types, it is some vector mode.
5760 When we have only some of our vector isa extensions enabled, then there
5761 are some modes for which vector_mode_supported_p is false. For these
5762 modes, the generic vector support in gcc will choose some non-vector mode
5763 in order to implement the type. By computing the natural mode, we'll
5764 select the proper ABI location for the operand and not depend on whatever
5765 the middle-end decides to do with these vector types.
5767 The midde-end can't deal with the vector types > 16 bytes. In this
5768 case, we return the original mode and warn ABI change if CUM isn't
5769 NULL. */
5771 static enum machine_mode
5773 {
5777 {
5780 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5782 {
5787 else
5790 /* Get the mode which has this inner mode and number of units. */
5794 {
5796 {
5800 && !warnedavx
5802 {
5806 }
5808 }
5810 {
5814 && !warnedsse
5816 {
5820 }
5822 }
5823 else
5825 }
5828 }
5829 }
5832 }
5834 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5835 this may not agree with the mode that the type system has chosen for the
5836 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5837 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5839 static rtx
5842 {
5843 rtx tmp;
5847 else
5848 {
5852 }
5855 }
5857 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5858 of this code is to classify each 8bytes of incoming argument by the register
5859 class and assign registers accordingly. */
5861 /* Return the union class of CLASS1 and CLASS2.
5862 See the x86-64 PS ABI for details. */
5864 static enum x86_64_reg_class
5866 {
5867 /* Rule #1: If both classes are equal, this is the resulting class. */
5871 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5872 the other class. */
5878 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5882 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5890 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5891 MEMORY is used. */
5900 /* Rule #6: Otherwise class SSE is used. */
5902 }
5904 /* Classify the argument of type TYPE and mode MODE.
5905 CLASSES will be filled by the register class used to pass each word
5906 of the operand. The number of words is returned. In case the parameter
5907 should be passed in memory, 0 is returned. As a special case for zero
5908 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5910 BIT_OFFSET is used internally for handling records and specifies offset
5911 of the offset in bits modulo 256 to avoid overflow cases.
5913 See the x86-64 PS ABI for details.
5914 */
5916 static int
5919 {
5920 HOST_WIDE_INT bytes =
5922 int words
5925 /* Variable sized entities are always passed/returned in memory. */
5934 {
5936 tree field;
5939 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5946 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5947 signalize memory class, so handle it as special case. */
5949 {
5952 }
5954 /* Classify each field of record and merge classes. */
5956 {
5958 /* And now merge the fields of structure. */
5960 {
5962 {
5968 /* Bitfields are always classified as integer. Handle them
5969 early, since later code would consider them to be
5970 misaligned integers. */
5972 {
5981 }
5982 else
5983 {
5988 /* Flexible array member is ignored. */
5995 {
5999 {
6002 "the ABI of passing struct with"
6003 " a flexible array member has"
6005 }
6007 }
6009 subclasses,
6019 }
6020 }
6021 }
6025 /* Arrays are handled as small records. */
6026 {
6033 /* The partial classes are now full classes. */
6044 }
6047 /* Unions are similar to RECORD_TYPE but offset is always 0.
6048 */
6050 {
6052 {
6060 bit_offset);
6065 }
6066 }
6071 }
6074 {
6075 /* When size > 16 bytes, if the first one isn't
6076 X86_64_SSE_CLASS or any other ones aren't
6077 X86_64_SSEUP_CLASS, everything should be passed in
6078 memory. */
6085 }
6087 /* Final merger cleanup. */
6089 {
6090 /* If one class is MEMORY, everything should be passed in
6091 memory. */
6095 /* The X86_64_SSEUP_CLASS should be always preceded by
6096 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6100 {
6101 /* The first one should never be X86_64_SSEUP_CLASS. */
6104 }
6106 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6107 everything should be passed in memory. */
6110 {
6113 /* The first one should never be X86_64_X87UP_CLASS. */
6116 {
6119 "the ABI of passing union with long double"
6121 }
6123 }
6124 }
6126 }
6128 /* Compute alignment needed. We align all types to natural boundaries with
6129 exception of XFmode that is aligned to 64bits. */
6131 {
6140 /* Misaligned fields are always returned in memory. */
6143 }
6145 /* for V1xx modes, just use the base mode */
6150 /* Classification of atomic types. */
6152 {
6168 {
6172 {
6175 }
6177 {
6180 }
6182 {
6186 }
6188 {
6191 }
6192 else
6194 }
6201 /* OImode shouldn't be used directly. */
6208 else
6226 else
6227 {
6231 {
6234 "the ABI of passing structure with complex float"
6236 }
6239 }
6248 /* This modes is larger than 16 bytes. */
6291 else
6295 }
6296 }
6298 /* Examine the argument and return set number of register required in each
6299 class. Return 0 iff parameter should be passed in memory. */
6300 static int
6303 {
6313 {
6335 }
6337 }
6339 /* Construct container for the argument used by GCC interface. See
6340 FUNCTION_ARG for the detailed description. */
6342 static rtx
6346 {
6347 /* The following variables hold the static issued_error state. */
6361 rtx ret;
6372 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6373 some less clueful developer tries to use floating-point anyway. */
6375 {
6377 {
6379 {
6382 }
6383 }
6385 {
6388 }
6390 }
6392 /* Likewise, error if the ABI requires us to return values in the
6393 x87 registers and the user specified -mno-80387. */
6399 {
6401 {
6404 }
6406 }
6408 /* First construct simple cases. Avoid SCmode, since we want to use
6409 single register to pass this type. */
6412 {
6427 /* Zero sized array, struct or class. */
6431 }
6458 /* Otherwise figure out the entries of the PARALLEL. */
6460 {
6464 {
6469 /* Merge TImodes on aligned occasions here too. */
6471 tmpmode
6475 else
6477 /* We've requested 24 bytes we
6478 don't have mode for. Use DImode. */
6485 intreg++;
6493 sse_regno++;
6501 sse_regno++;
6506 {
6512 {
6514 i++;
6515 }
6516 else
6529 }
6535 sse_regno++;
6539 }
6540 }
6542 /* Empty aligned struct, union or class. */
6550 }
6552 /* Update the data in CUM to advance over an argument of mode MODE
6553 and data type TYPE. (TYPE is null for libcalls where that information
6554 may not be available.) */
6556 static void
6559 HOST_WIDE_INT words)
6560 {
6562 {
6569 /* FALLTHRU */
6580 {
6583 }
6587 /* OImode shouldn't be used directly. */
6596 /* FALLTHRU */
6612 {
6617 {
6620 }
6621 }
6631 {
6636 {
6639 }
6640 }
6642 }
6643 }
6645 static void
6648 {
6651 /* Unnamed 256bit vector mode parameters are passed on stack. */
6657 {
6662 }
6663 else
6664 {
6668 }
6669 }
6671 static void
6673 HOST_WIDE_INT words)
6674 {
6675 /* Otherwise, this should be passed indirect. */
6680 {
6683 }
6684 }
6686 /* Update the data in CUM to advance over an argument of mode MODE and
6687 data type TYPE. (TYPE is null for libcalls where that information
6688 may not be available.) */
6690 static void
6693 {
6699 else
6710 else
6712 }
6714 /* Define where to put the arguments to a function.
6715 Value is zero to push the argument on the stack,
6716 or a hard register in which to store the argument.
6718 MODE is the argument's machine mode.
6719 TYPE is the data type of the argument (as a tree).
6720 This is null for libcalls where that information may
6721 not be available.
6722 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6723 the preceding args and about the function being called.
6724 NAMED is nonzero if this argument is a named parameter
6725 (otherwise it is an extra parameter matching an ellipsis). */
6727 static rtx
6731 {
6734 /* Avoid the AL settings for the Unix64 ABI. */
6739 {
6746 /* FALLTHRU */
6752 {
6755 /* Fastcall allocates the first two DWORD (SImode) or
6756 smaller arguments to ECX and EDX if it isn't an
6757 aggregate type . */
6759 {
6765 /* ECX not EAX is the first allocated register. */
6768 }
6770 }
6779 /* FALLTHRU */
6781 /* In 32bit, we pass TImode in xmm registers. */
6789 {
6791 {
6795 }
6799 }
6803 /* OImode shouldn't be used directly. */
6813 {
6817 }
6827 {
6829 {
6833 }
6837 }
6839 }
6842 }
6844 static rtx
6847 {
6848 /* Handle a hidden AL argument containing number of registers
6849 for varargs x86-64 functions. */
6853 ? X86_64_SSE_REGPARM_MAX
6858 {
6868 /* Unnamed 256bit vector mode parameters are passed on stack. */
6872 }
6878 }
6880 static rtx
6883 HOST_WIDE_INT bytes)
6884 {
6887 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6888 We use value of -2 to specify that current function call is MSABI. */
6892 /* If we've run out of registers, it goes on the stack. */
6898 /* Only floating point modes are passed in anything but integer regs. */
6900 {
6903 else
6904 {
6907 /* Unnamed floating parameters are passed in both the
6908 SSE and integer registers. */
6914 }
6915 }
6916 /* Handle aggregated types passed in register. */
6918 {
6923 }
6926 }
6928 /* Return where to put the arguments to a function.
6929 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6931 MODE is the argument's machine mode. TYPE is the data type of the
6932 argument. It is null for libcalls where that information may not be
6933 available. CUM gives information about the preceding args and about
6934 the function being called. NAMED is nonzero if this argument is a
6935 named parameter (otherwise it is an extra parameter matching an
6936 ellipsis). */
6938 static rtx
6941 {
6945 rtx arg;
6949 else
6953 /* To simplify the code below, represent vector types with a vector mode
6954 even if MMX/SSE are not active. */
6962 else
6966 }
6968 /* A C expression that indicates when an argument must be passed by
6969 reference. If nonzero for an argument, a copy of that argument is
6970 made in memory and a pointer to the argument is passed instead of
6971 the argument itself. The pointer is passed in whatever way is
6972 appropriate for passing a pointer to that type. */
6974 static bool
6978 {
6981 /* See Windows x64 Software Convention. */
6983 {
6986 {
6987 /* Arrays are passed by reference. */
6992 {
6993 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6994 are passed by reference. */
6996 }
6997 }
6999 /* __m128 is passed by reference. */
7005 }
7006 }
7011 }
7013 /* Return true when TYPE should be 128bit aligned for 32bit argument
7014 passing ABI. XXX: This function is obsolete and is only used for
7015 checking psABI compatibility with previous versions of GCC. */
7017 static bool
7019 {
7031 {
7032 /* Walk the aggregates recursively. */
7034 {
7038 {
7039 tree field;
7041 /* Walk all the structure fields. */
7043 {
7047 }
7049 }
7052 /* Just for use if some languages passes arrays by value. */
7059 }
7060 }
7062 }
7064 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7065 XXX: This function is obsolete and is only used for checking psABI
7066 compatibility with previous versions of GCC. */
7068 static unsigned int
7071 {
7072 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7073 natural boundaries. */
7075 {
7076 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7077 make an exception for SSE modes since these require 128bit
7078 alignment.
7080 The handling here differs from field_alignment. ICC aligns MMX
7081 arguments to 4 byte boundaries, while structure fields are aligned
7082 to 8 byte boundaries. */
7084 {
7087 }
7088 else
7089 {
7092 }
7093 }
7097 }
7099 /* Return true when TYPE should be 128bit aligned for 32bit argument
7100 passing ABI. */
7102 static bool
7104 {
7114 {
7115 /* Walk the aggregates recursively. */
7117 {
7121 {
7122 tree field;
7124 /* Walk all the structure fields. */
7126 field;
7128 {
7132 }
7134 }
7137 /* Just for use if some languages passes arrays by value. */
7144 }
7145 }
7146 else
7150 }
7152 /* Gives the alignment boundary, in bits, of an argument with the
7153 specified mode and type. */
7155 static unsigned int
7157 {
7160 {
7161 /* Since the main variant type is used for call, we convert it to
7162 the main variant type. */
7165 }
7166 else
7170 else
7171 {
7176 {
7177 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7179 {
7182 }
7188 }
7191 && !warned
7193 saved_align))
7194 {
7197 "The ABI for passing parameters with %d-byte"
7200 }
7201 }
7204 }
7206 /* Return true if N is a possible register number of function value. */
7208 static bool
7210 {
7212 {
7217 /* TODO: The function should depend on current function ABI but
7218 builtins.c would need updating then. Therefore we use the
7219 default ABI. */
7231 }
7234 }
7236 /* Define how to find the value returned by a function.
7237 VALTYPE is the data type of the value (as a tree).
7238 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7239 otherwise, FUNC is 0. */
7241 static rtx
7244 {
7247 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7248 we normally prevent this case when mmx is not available. However
7249 some ABIs may require the result to be returned like DImode. */
7253 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7254 we prevent this case when sse is not available. However some ABIs
7255 may require the result to be returned like integer TImode. */
7260 /* 32-byte vector modes in %ymm0. */
7264 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7267 else
7268 /* Most things go in %eax. */
7271 /* Override FP return register with %xmm0 for local functions when
7272 SSE math is enabled or for functions with sseregparm attribute. */
7274 {
7279 }
7281 /* OImode shouldn't be used directly. */
7285 }
7287 static rtx
7289 const_tree valtype)
7290 {
7291 rtx ret;
7293 /* Handle libcalls, which don't provide a type node. */
7295 {
7299 {
7318 }
7321 }
7323 {
7324 /* Pointers are always returned in word_mode. */
7326 }
7332 /* For zero sized structures, construct_container returns NULL, but we
7333 need to keep rest of compiler happy by returning meaningful value. */
7338 }
7340 static rtx
7342 const_tree valtype)
7343 {
7347 {
7349 {
7368 }
7369 }
7371 }
7373 static rtx
7376 {
7388 else
7390 }
7392 static rtx
7395 {
7401 }
7403 /* Pointer function arguments and return values are promoted to
7404 word_mode. */
7406 static enum machine_mode
7410 {
7412 {
7415 }
7417 for_return);
7418 }
7420 /* Return true if a structure, union or array with MODE containing FIELD
7421 should be accessed using BLKmode. */
7423 static bool
7425 {
7426 /* Union with XFmode must be in BLKmode. */
7430 }
7432 rtx
7434 {
7436 }
7438 /* Return true iff type is returned in memory. */
7440 static bool ATTRIBUTE_UNUSED
7442 {
7443 HOST_WIDE_INT size;
7454 {
7455 /* User-created vectors small enough to fit in EAX. */
7459 /* MMX/3dNow values are returned in MM0,
7460 except when it doesn't exits or the ABI prescribes otherwise. */
7464 /* SSE values are returned in XMM0, except when it doesn't exist. */
7468 /* AVX values are returned in YMM0, except when it doesn't exist. */
7471 }
7479 /* OImode shouldn't be used directly. */
7483 }
7485 static bool ATTRIBUTE_UNUSED
7487 {
7490 }
7492 static bool ATTRIBUTE_UNUSED
7494 {
7497 /* __m128 is returned in xmm0. */
7504 /* Otherwise, the size must be exactly in [1248]. */
7506 }
7508 static bool
7510 {
7511 #ifdef SUBTARGET_RETURN_IN_MEMORY
7513 #else
7517 {
7520 else
7522 }
7523 else
7525 #endif
7526 }
7528 /* When returning SSE vector types, we have a choice of either
7529 (1) being abi incompatible with a -march switch, or
7530 (2) generating an error.
7531 Given no good solution, I think the safest thing is one warning.
7532 The user won't be able to use -Werror, but....
7534 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7535 called in response to actually generating a caller or callee that
7536 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7537 via aggregate_value_p for general type probing from tree-ssa. */
7539 static rtx
7541 {
7545 {
7546 /* Look at the return type of the function, not the function type. */
7550 {
7553 {
7557 }
7558 }
7561 {
7563 {
7567 }
7568 }
7569 }
7572 }
7574 \f
7575 /* Create the va_list data type. */
7577 /* Returns the calling convention specific va_list date type.
7578 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7580 static tree
7582 {
7585 /* For i386 we use plain pointer to argument area. */
7595 unsigned_type_node);
7598 unsigned_type_node);
7601 ptr_type_node);
7604 ptr_type_node);
7623 /* The correct type is an array type of one element. */
7625 }
7627 /* Setup the builtin va_list data type and for 64-bit the additional
7628 calling convention specific va_list data types. */
7630 static tree
7632 {
7635 /* Initialize abi specific va_list builtin types. */
7637 {
7638 tree t;
7640 {
7645 }
7646 else
7647 {
7652 }
7654 {
7659 }
7660 else
7661 {
7666 }
7667 }
7670 }
7672 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7674 static void
7676 {
7678 alias_set_type set;
7681 /* GPR size of varargs save area. */
7684 else
7687 /* FPR size of varargs save area. We don't need it if we don't pass
7688 anything in SSE registers. */
7691 else
7705 {
7713 }
7716 {
7720 /* Now emit code to save SSE registers. The AX parameter contains number
7721 of SSE parameter registers used to call this function, though all we
7722 actually check here is the zero/non-zero status. */
7727 label));
7729 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7730 we used movdqa (i.e. TImode) instead? Perhaps even better would
7731 be if we could determine the real mode of the data, via a hook
7732 into pass_stdarg. Ignore all that for now. */
7742 {
7751 }
7754 }
7755 }
7757 static void
7759 {
7763 /* Reset to zero, as there might be a sysv vaarg used
7764 before. */
7769 {
7780 }
7781 }
7783 static void
7787 {
7789 CUMULATIVE_ARGS next_cum;
7790 tree fntype;
7792 /* This argument doesn't appear to be used anymore. Which is good,
7793 because the old code here didn't suppress rtl generation. */
7801 /* For varargs, we do not want to skip the dummy va_dcl argument.
7802 For stdargs, we do want to skip the last named argument. */
7810 else
7812 }
7814 /* Checks if TYPE is of kind va_list char *. */
7816 static bool
7818 {
7819 tree canonic;
7821 /* For 32-bit it is always true. */
7827 }
7829 /* Implement va_start. */
7831 static void
7833 {
7837 tree type;
7838 rtx ovf_rtx;
7842 {
7845 /* When we are splitting the stack, we can't refer to the stack
7846 arguments using internal_arg_pointer, because they may be on
7847 the old stack. The split stack prologue will arrange to
7848 leave a pointer to the old stack arguments in a scratch
7849 register, which we here copy to a pseudo-register. The split
7850 stack prologue can't set the pseudo-register directly because
7851 it (the prologue) runs before any registers have been saved. */
7855 {
7869 }
7870 }
7872 /* Only 64bit target needs something special. */
7874 {
7877 else
7878 {
7887 }
7889 }
7898 /* The following should be folded into the MEM_REF offset. */
7908 /* Count number of gp and fp argument registers used. */
7914 {
7920 }
7923 {
7929 }
7931 /* Find the overflow area. */
7935 else
7945 {
7946 /* Find the register save area.
7947 Prologue of the function save it right above stack frame. */
7955 }
7956 }
7958 /* Implement va_arg. */
7960 static tree
7963 {
7970 rtx container;
7972 tree ptrtype;
7976 /* Only 64bit target needs something special. */
8000 {
8007 /* Unnamed 256bit vector mode parameters are passed on stack. */
8009 {
8012 }
8020 }
8022 /* Pull the value out of the saved registers. */
8027 {
8041 /* In case we are passing structure, verify that it is consecutive block
8042 on the register save area. If not we need to do moves. */
8044 {
8045 /* Verify that all registers are strictly consecutive */
8047 {
8051 {
8056 }
8057 }
8058 else
8059 {
8063 {
8068 }
8069 }
8070 }
8072 {
8075 }
8076 else
8077 {
8080 }
8082 /* First ensure that we fit completely in registers. */
8084 {
8091 }
8093 {
8101 }
8103 /* Compute index to start of area used for integer regs. */
8105 {
8106 /* int_addr = gpr + sav; */
8109 }
8111 {
8112 /* sse_addr = fpr + sav; */
8115 }
8117 {
8121 /* addr = &temp; */
8126 {
8130 tree piece_type;
8131 tree addr_type;
8132 tree daddr_type;
8141 {
8146 }
8150 else
8157 {
8160 }
8161 else
8162 {
8165 }
8172 {
8177 }
8178 else
8179 {
8180 tree copy
8185 }
8187 }
8188 }
8191 {
8195 }
8198 {
8202 }
8207 }
8209 /* ... otherwise out of the overflow area. */
8211 /* When we align parameter on stack for caller, if the parameter
8212 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8213 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8214 here with caller. */
8219 /* Care for on-stack alignment if needed. */
8222 else
8223 {
8228 }
8245 }
8246 \f
8247 /* Return true if OPNUM's MEM should be matched
8248 in movabs* patterns. */
8250 bool
8252 {
8264 }
8265 \f
8266 /* Initialize the table of extra 80387 mathematical constants. */
8268 static void
8270 {
8272 {
8278 };
8282 {
8284 /* Ensure each constant is rounded to XFmode precision. */
8287 }
8290 }
8292 /* Return non-zero if the constant is something that
8293 can be loaded with a special instruction. */
8295 int
8297 {
8300 REAL_VALUE_TYPE r;
8312 /* For XFmode constants, try to find a special 80387 instruction when
8313 optimizing for size or on those CPUs that benefit from them. */
8316 {
8325 }
8327 /* Load of the constant -0.0 or -1.0 will be split as
8328 fldz;fchs or fld1;fchs sequence. */
8335 }
8337 /* Return the opcode of the special instruction to be used to load
8338 the constant X. */
8342 {
8344 {
8364 }
8365 }
8367 /* Return the CONST_DOUBLE representing the 80387 constant that is
8368 loaded by the specified special instruction. The argument IDX
8369 matches the return value from standard_80387_constant_p. */
8371 rtx
8373 {
8380 {
8391 }
8394 XFmode);
8395 }
8397 /* Return 1 if X is all 0s and 2 if x is all 1s
8398 in supported SSE/AVX vector mode. */
8400 int
8402 {
8409 {
8424 }
8427 }
8429 /* Return the opcode of the special instruction to be used to load
8430 the constant X. */
8434 {
8436 {
8439 {
8456 }
8461 else
8466 }
8468 }
8470 /* Returns true if OP contains a symbol reference */
8472 bool
8474 {
8483 {
8485 {
8491 }
8495 }
8498 }
8500 /* Return true if it is appropriate to emit `ret' instructions in the
8501 body of a function. Do this only if the epilogue is simple, needing a
8502 couple of insns. Prior to reloading, we can't tell how many registers
8503 must be saved, so return false then. Return false if there is no frame
8504 marker to de-allocate. */
8506 bool
8508 {
8514 /* Don't allow more than 32k pop, since that's all we can do
8515 with one instruction. */
8522 }
8523 \f
8524 /* Value should be nonzero if functions must have frame pointers.
8525 Zero means the frame pointer need not be set up (and parms may
8526 be accessed via the stack pointer) in functions that seem suitable. */
8528 static bool
8530 {
8531 /* If we accessed previous frames, then the generated code expects
8532 to be able to access the saved ebp value in our frame. */
8536 /* Several x86 os'es need a frame pointer for other reasons,
8537 usually pertaining to setjmp. */
8541 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8545 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8546 allocation is 4GB. */
8550 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8551 turns off the frame pointer by default. Turn it back on now if
8552 we've not got a leaf function. */
8562 }
8564 /* Record that the current function accesses previous call frames. */
8566 void
8568 {
8570 }
8571 \f
8572 #ifndef USE_HIDDEN_LINKONCE
8573 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8574 # define USE_HIDDEN_LINKONCE 1
8575 # else
8576 # define USE_HIDDEN_LINKONCE 0
8577 # endif
8578 #endif
8582 /* Fills in the label name that should be used for a pc thunk for
8583 the given register. */
8585 static void
8587 {
8592 else
8594 }
8597 /* This function generates code for -fpic that loads %ebx with
8598 the return address of the caller and then returns. */
8600 static void
8602 {
8607 {
8609 tree decl;
8625 #if TARGET_MACHO
8627 {
8636 }
8637 else
8638 #endif
8640 {
8651 }
8652 else
8653 {
8656 }
8662 /* Make sure unwind info is emitted for the thunk if needed. */
8665 /* Pad stack IP move with 4 instructions (two NOPs count
8666 as one instruction). */
8668 {
8673 }
8684 }
8688 }
8690 /* Emit code for the SET_GOT patterns. */
8694 {
8700 {
8701 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8706 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8707 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8708 an unadorned address. */
8713 }
8718 {
8723 #if TARGET_MACHO
8724 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8725 is what will be referenced by the Mach-O PIC subsystem. */
8728 #endif
8732 }
8733 else
8734 {
8742 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8743 is what will be referenced by the Mach-O PIC subsystem. */
8744 #if TARGET_MACHO
8747 else
8750 #endif
8751 }
8757 }
8759 /* Generate an "push" pattern for input ARG. */
8761 static rtx
8763 {
8776 stack_pointer_rtx)),
8777 arg);
8778 }
8780 /* Generate an "pop" pattern for input ARG. */
8782 static rtx
8784 {
8789 arg,
8792 stack_pointer_rtx)));
8793 }
8795 /* Return >= 0 if there is an unused call-clobbered register available
8796 for the entire function. */
8798 static unsigned int
8800 {
8804 {
8806 /* Can't use the same register for both PIC and DRAP. */
8809 else
8814 }
8817 }
8819 /* Return TRUE if we need to save REGNO. */
8821 static bool
8823 {
8833 {
8836 {
8842 }
8843 }
8852 }
8854 /* Return number of saved general prupose registers. */
8856 static int
8858 {
8864 nregs ++;
8866 }
8868 /* Return number of saved SSE registrers. */
8870 static int
8872 {
8880 nregs ++;
8882 }
8884 /* Given FROM and TO register numbers, say whether this elimination is
8885 allowed. If stack alignment is needed, we can only replace argument
8886 pointer with hard frame pointer, or replace frame pointer with stack
8887 pointer. Otherwise, frame pointer elimination is automatically
8888 handled and all other eliminations are valid. */
8890 static bool
8892 {
8898 else
8900 }
8902 /* Return the offset between two registers, one to be eliminated, and the other
8903 its replacement, at the start of a routine. */
8905 HOST_WIDE_INT
8907 {
8916 else
8917 {
8925 }
8926 }
8928 /* In a dynamically-aligned function, we can't know the offset from
8929 stack pointer to frame pointer, so we must ensure that setjmp
8930 eliminates fp against the hard fp (%ebp) rather than trying to
8931 index from %esp up to the top of the frame across a gap that is
8932 of unknown (at compile-time) size. */
8933 static rtx
8935 {
8937 }
8939 /* When using -fsplit-stack, the allocation routines set a field in
8940 the TCB to the bottom of the stack plus this much space, measured
8941 in bytes. */
8943 #define SPLIT_STACK_AVAILABLE 256
8945 /* Fill structure ix86_frame about frame of currently computed function. */
8947 static void
8949 {
8951 HOST_WIDE_INT offset;
8954 HOST_WIDE_INT to_allocate;
8962 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8963 function prologues and leaf. */
8967 {
8972 }
8978 /* For SEH we have to limit the amount of code movement into the prologue.
8979 At present we do this via a BLOCKAGE, at which point there's very little
8980 scheduling that can be done, which means that there's very little point
8981 in doing anything except PUSHs. */
8985 /* During reload iteration the amount of registers saved can change.
8986 Recompute the value as needed. Do not recompute when amount of registers
8987 didn't change as reload does multiple calls to the function and does not
8988 expect the decision to change within single iteration. */
8991 {
8997 /* The fast prologue uses move instead of push to save registers. This
8998 is significantly longer, but also executes faster as modern hardware
8999 can execute the moves in parallel, but can't do that for push/pop.
9001 Be careful about choosing what prologue to emit: When function takes
9002 many instructions to execute we may use slow version as well as in
9003 case function is known to be outside hot spot (this is known with
9004 feedback only). Weight the size of function by number of registers
9005 to save as it is cheap to use one or two push instructions but very
9006 slow to use many of them. */
9010 || (flag_branch_probabilities
9013 else
9016 }
9018 frame->save_regs_using_mov
9020 /* If static stack checking is enabled and done with probes,
9021 the registers need to be saved before allocating the frame. */
9024 /* Skip return address. */
9027 /* Skip pushed static chain. */
9031 /* Skip saved base pointer. */
9036 /* The traditional frame pointer location is at the top of the frame. */
9039 /* Register save area */
9043 /* On SEH target, registers are pushed just before the frame pointer
9044 location. */
9048 /* Align and set SSE register save area. */
9050 {
9051 /* The only ABI that has saved SSE registers (Win64) also has a
9052 16-byte aligned default stack, and thus we don't need to be
9053 within the re-aligned local stack frame to save them. */
9057 }
9060 /* The re-aligned stack starts here. Values before this point are not
9061 directly comparable with values below this point. In order to make
9062 sure that no value happens to be the same before and after, force
9063 the alignment computation below to add a non-zero value. */
9067 /* Va-arg area */
9071 /* Align start of frame for local function. */
9080 /* Frame pointer points here. */
9085 /* Add outgoing arguments area. Can be skipped if we eliminated
9086 all the function calls as dead code.
9087 Skipping is however impossible when function calls alloca. Alloca
9088 expander assumes that last crtl->outgoing_args_size
9089 of stack frame are unused. */
9093 {
9096 }
9097 else
9100 /* Align stack boundary. Only needed if we're calling another function
9101 or using alloca. */
9106 /* We've reached end of stack frame. */
9109 /* Size prologue needs to allocate. */
9120 {
9126 }
9127 else
9131 /* The SEH frame pointer location is near the bottom of the frame.
9132 This is enforced by the fact that the difference between the
9133 stack pointer and the frame pointer is limited to 240 bytes in
9134 the unwind data structure. */
9136 {
9137 HOST_WIDE_INT diff;
9139 /* If we can leave the frame pointer where it is, do so. Also, returns
9140 the establisher frame for __builtin_frame_address (0). */
9145 {
9146 /* Ideally we'd determine what portion of the local stack frame
9147 (within the constraint of the lowest 240) is most heavily used.
9148 But without that complication, simply bias the frame pointer
9149 by 128 bytes so as to maximize the amount of the local stack
9150 frame that is addressable with 8-bit offsets. */
9152 }
9153 }
9154 }
9156 /* This is semi-inlined memory_address_length, but simplified
9157 since we know that we're always dealing with reg+offset, and
9158 to avoid having to create and discard all that rtl. */
9162 {
9166 {
9167 /* EBP and R13 cannot be encoded without an offset. */
9169 }
9173 /* ESP and R12 must be encoded with a SIB byte. */
9175 len++;
9178 }
9180 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9181 The valid base registers are taken from CFUN->MACHINE->FS. */
9183 static rtx
9185 {
9191 {
9192 /* Choose the base register most likely to allow the most scheduling
9193 opportunities. Generally FP is valid throughout the function,
9194 while DRAP must be reloaded within the epilogue. But choose either
9195 over the SP due to increased encoding size. */
9198 {
9201 }
9203 {
9206 }
9208 {
9211 }
9212 }
9213 else
9214 {
9215 HOST_WIDE_INT toffset;
9218 /* Choose the base register with the smallest address encoding.
9219 With a tie, choose FP > DRAP > SP. */
9221 {
9225 }
9227 {
9231 {
9235 }
9236 }
9238 {
9242 {
9246 }
9247 }
9248 }
9252 }
9254 /* Emit code to save registers in the prologue. */
9256 static void
9258 {
9260 rtx insn;
9264 {
9267 }
9268 }
9270 /* Emit a single register save at CFA - CFA_OFFSET. */
9272 static void
9274 HOST_WIDE_INT cfa_offset)
9275 {
9283 /* For SSE saves, we need to indicate the 128-bit alignment. */
9294 /* When saving registers into a re-aligned local stack frame, avoid
9295 any tricky guessing by dwarf2out. */
9297 {
9301 {
9302 /* A bit of a hack. We force the DRAP register to be saved in
9303 the re-aligned stack frame, which provides us with a copy
9304 of the CFA that will last past the prologue. Install it. */
9310 }
9311 else
9312 {
9313 /* The frame pointer is a stable reference within the
9314 aligned frame. Use it. */
9321 }
9322 }
9324 /* The memory may not be relative to the current CFA register,
9325 which means that we may need to generate a new pattern for
9326 use by the unwind info. */
9328 {
9333 }
9334 }
9336 /* Emit code to save registers using MOV insns.
9337 First register is stored at CFA - CFA_OFFSET. */
9338 static void
9340 {
9345 {
9348 }
9349 }
9351 /* Emit code to save SSE registers using MOV insns.
9352 First register is stored at CFA - CFA_OFFSET. */
9353 static void
9355 {
9360 {
9363 }
9364 }
9368 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9369 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9370 Don't add the note if the previously saved value will be left untouched
9371 within stack red-zone till return, as unwinders can find the same value
9372 in the register and on the stack. */
9374 static void
9376 {
9382 {
9385 }
9386 else
9387 queued_cfa_restores
9389 }
9391 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9393 static void
9395 {
9396 rtx last;
9400 ;
9405 }
9407 /* Expand prologue or epilogue stack adjustment.
9408 The pattern exist to put a dependency on all ebp-based memory accesses.
9409 STYLE should be negative if instructions should be marked as frame related,
9410 zero if %r11 register is live and cannot be freely used and positive
9411 otherwise. */
9413 static void
9416 {
9418 rtx insn;
9425 else
9426 {
9427 rtx tmp;
9428 /* r11 is used by indirect sibcall return as well, set before the
9429 epilogue and used after the epilogue. */
9432 else
9433 {
9437 }
9443 }
9450 {
9451 rtx r;
9461 }
9463 {
9466 {
9470 }
9471 }
9474 {
9479 {
9482 }
9484 {
9487 }
9488 else
9489 {
9490 /* Else there are two possibilities: SP itself, which we set
9491 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9492 taken care of this by hand along the eh_return path. */
9495 }
9499 }
9500 }
9502 /* Find an available register to be used as dynamic realign argument
9503 pointer regsiter. Such a register will be written in prologue and
9504 used in begin of body, so it must not be
9505 1. parameter passing register.
9506 2. GOT pointer.
9507 We reuse static-chain register if it is available. Otherwise, we
9508 use DI for i386 and R13 for x86-64. We chose R13 since it has
9509 shorter encoding.
9511 Return: the regno of chosen register. */
9513 static unsigned int
9515 {
9519 {
9520 /* Use R13 for nested function or function need static chain.
9521 Since function with tail call may use any caller-saved
9522 registers in epilogue, DRAP must not use caller-saved
9523 register in such case. */
9528 }
9529 else
9530 {
9531 /* Use DI for nested function or function need static chain.
9532 Since function with tail call may use any caller-saved
9533 registers in epilogue, DRAP must not use caller-saved
9534 register in such case. */
9538 /* Reuse static chain register if it isn't used for parameter
9539 passing. */
9541 {
9545 }
9547 }
9548 }
9550 /* Return minimum incoming stack alignment. */
9552 static unsigned int
9554 {
9557 /* Prefer the one specified at command line. */
9560 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9561 if -mstackrealign is used, it isn't used for sibcall check and
9562 estimated stack alignment is 128bit. */
9564 && !TARGET_64BIT
9565 && ix86_force_align_arg_pointer
9568 else
9571 /* Incoming stack alignment can be changed on individual functions
9572 via force_align_arg_pointer attribute. We use the smallest
9573 incoming stack boundary. */
9579 /* The incoming stack frame has to be aligned at least at
9580 parm_stack_boundary. */
9584 /* Stack at entrance of main is aligned by runtime. We use the
9585 smallest incoming stack boundary. */
9593 }
9595 /* Update incoming stack boundary and estimated stack alignment. */
9597 static void
9599 {
9600 ix86_incoming_stack_boundary
9603 /* x86_64 vararg needs 16byte stack alignment for register save
9604 area. */
9609 }
9611 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9612 needed or an rtx for DRAP otherwise. */
9614 static rtx
9616 {
9621 {
9622 /* Assign DRAP to vDRAP and returns vDRAP */
9624 rtx drap_vreg;
9625 rtx arg_ptr;
9638 {
9641 }
9643 }
9644 else
9646 }
9648 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9650 static rtx
9652 {
9654 }
9657 rtx reg;
9659 };
9661 /* Return a short-lived scratch register for use on function entry.
9662 In 32-bit mode, it is valid only after the registers are saved
9663 in the prologue. This register must be released by means of
9664 release_scratch_register_on_entry once it is dead. */
9666 static void
9668 {
9674 {
9675 /* We always use R11 in 64-bit mode. */
9677 }
9678 else
9679 {
9681 bool fastcall_p
9683 bool thiscall_p
9687 int drap_regno
9690 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9691 for the static chain register. */
9695 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9696 for the static chain register. */
9701 /* ecx is the static chain register. */
9703 && !static_chain_p
9708 /* esi is the static chain register. */
9714 else
9715 {
9718 }
9719 }
9723 {
9726 }
9727 }
9729 /* Release a scratch register obtained from the preceding function. */
9731 static void
9733 {
9735 {
9739 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9745 }
9746 }
9748 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9750 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9752 static void
9754 {
9755 /* We skip the probe for the first interval + a small dope of 4 words and
9756 probe that many bytes past the specified size to maintain a protection
9757 area at the botton of the stack. */
9761 /* See if we have a constant small number of probes to generate. If so,
9762 that's the easy case. The run-time loop is made up of 11 insns in the
9763 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9764 for n # of intervals. */
9766 {
9770 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9771 values of N from 1 until it exceeds SIZE. If only one probe is
9772 needed, this will not generate any code. Then adjust and probe
9773 to PROBE_INTERVAL + SIZE. */
9775 {
9777 {
9780 }
9781 else
9788 }
9792 else
9800 /* Adjust back to account for the additional first interval. */
9804 }
9806 /* Otherwise, do the same as above, but in a loop. Note that we must be
9807 extra careful with variables wrapping around because we might be at
9808 the very top (or the very bottom) of the address space and we have
9809 to be able to handle this case properly; in particular, we use an
9810 equality test for the loop condition. */
9811 else
9812 {
9813 HOST_WIDE_INT rounded_size;
9819 /* Step 1: round SIZE to the previous multiple of the interval. */
9824 /* Step 2: compute initial and final value of the loop counter. */
9826 /* SP = SP_0 + PROBE_INTERVAL. */
9831 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9835 stack_pointer_rtx)));
9838 /* Step 3: the loop
9840 while (SP != LAST_ADDR)
9841 {
9842 SP = SP + PROBE_INTERVAL
9843 probe at SP
9844 }
9846 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9847 values of N from 1 until it is equal to ROUNDED_SIZE. */
9852 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9853 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9856 {
9861 }
9863 /* Adjust back to account for the additional first interval. */
9869 }
9873 /* Even if the stack pointer isn't the CFA register, we need to correctly
9874 describe the adjustments made to it, in particular differentiate the
9875 frame-related ones from the frame-unrelated ones. */
9877 {
9890 }
9892 /* Make sure nothing is scheduled before we are done. */
9894 }
9896 /* Adjust the stack pointer up to REG while probing it. */
9900 {
9910 /* Jump to END_LAB if SP == LAST_ADDR. */
9918 /* SP = SP + PROBE_INTERVAL. */
9922 /* Probe at SP. */
9933 }
9935 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9936 inclusive. These are offsets from the current stack pointer. */
9938 static void
9940 {
9941 /* See if we have a constant small number of probes to generate. If so,
9942 that's the easy case. The run-time loop is made up of 7 insns in the
9943 generic case while the compile-time loop is made up of n insns for n #
9944 of intervals. */
9946 {
9947 HOST_WIDE_INT i;
9949 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9950 it exceeds SIZE. If only one probe is needed, this will not
9951 generate any code. Then probe at FIRST + SIZE. */
9958 }
9960 /* Otherwise, do the same as above, but in a loop. Note that we must be
9961 extra careful with variables wrapping around because we might be at
9962 the very top (or the very bottom) of the address space and we have
9963 to be able to handle this case properly; in particular, we use an
9964 equality test for the loop condition. */
9965 else
9966 {
9973 /* Step 1: round SIZE to the previous multiple of the interval. */
9978 /* Step 2: compute initial and final value of the loop counter. */
9980 /* TEST_OFFSET = FIRST. */
9983 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9987 /* Step 3: the loop
9989 while (TEST_ADDR != LAST_ADDR)
9990 {
9991 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9992 probe at TEST_ADDR
9993 }
9995 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9996 until it is equal to ROUNDED_SIZE. */
10001 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10002 that SIZE is equal to ROUNDED_SIZE. */
10007 stack_pointer_rtx,
10012 }
10014 /* Make sure nothing is scheduled before we are done. */
10016 }
10018 /* Probe a range of stack addresses from REG to END, inclusive. These are
10019 offsets from the current stack pointer. */
10023 {
10033 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10041 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10045 /* Probe at TEST_ADDR. */
10058 }
10060 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10061 to be generated in correct form. */
10062 static void
10064 {
10065 /* Check if stack realign is really needed after reload, and
10066 stores result in cfun */
10067 unsigned int incoming_stack_boundary
10076 {
10077 /* After stack_realign_needed is finalized, we can't no longer
10078 change it. */
10081 }
10083 /* If the only reason for frame_pointer_needed is that we conservatively
10084 assumed stack realignment might be needed, but in the end nothing that
10085 needed the stack alignment had been spilled, clear frame_pointer_needed
10086 and say we don't need stack realignment. */
10089 && frame_pointer_needed
10091 && flag_omit_frame_pointer
10093 && !ix86_current_function_calls_tls_descriptor
10102 {
10104 basic_block bb;
10111 HARD_FRAME_POINTER_REGNUM);
10113 {
10114 rtx insn;
10118 set_up_by_prologue))
10119 {
10123 }
10124 }
10138 }
10142 }
10144 /* Expand the prologue into a bunch of separate insns. */
10146 void
10148 {
10153 HOST_WIDE_INT allocate;
10159 /* DRAP should not coexist with stack_realign_fp */
10164 /* Initialize CFA state for before the prologue. */
10168 /* Track SP offset to the CFA. We continue tracking this after we've
10169 swapped the CFA register away from SP. In the case of re-alignment
10170 this is fudged; we're interested to offsets within the local frame. */
10177 {
10178 /* We should have already generated an error for any use of
10179 ms_hook on a nested function. */
10182 /* Check if profiling is active and we shall use profiling before
10183 prologue variant. If so sorry. */
10188 /* In ix86_asm_output_function_label we emitted:
10189 8b ff movl.s %edi,%edi
10190 55 push %ebp
10191 8b ec movl.s %esp,%ebp
10193 This matches the hookable function prologue in Win32 API
10194 functions in Microsoft Windows XP Service Pack 2 and newer.
10195 Wine uses this to enable Windows apps to hook the Win32 API
10196 functions provided by Wine.
10198 What that means is that we've already set up the frame pointer. */
10202 {
10205 /* We've decided to use the frame pointer already set up.
10206 Describe this to the unwinder by pretending that both
10207 push and mov insns happen right here.
10209 Putting the unwind info here at the end of the ms_hook
10210 is done so that we can make absolutely certain we get
10211 the required byte sequence at the start of the function,
10212 rather than relying on an assembler that can produce
10213 the exact encoding required.
10215 However it does mean (in the unpatched case) that we have
10216 a 1 insn window where the asynchronous unwind info is
10217 incorrect. However, if we placed the unwind info at
10218 its correct location we would have incorrect unwind info
10219 in the patched case. Which is probably all moot since
10220 I don't expect Wine generates dwarf2 unwind info for the
10221 system libraries that use this feature. */
10227 stack_pointer_rtx);
10235 /* Note that gen_push incremented m->fs.cfa_offset, even
10236 though we didn't emit the push insn here. */
10240 }
10241 else
10242 {
10243 /* The frame pointer is not needed so pop %ebp again.
10244 This leaves us with a pristine state. */
10246 }
10247 }
10249 /* The first insn of a function that accepts its static chain on the
10250 stack is to push the register that would be filled in by a direct
10251 call. This insn will be skipped by the trampoline. */
10253 {
10257 /* We don't want to interpret this push insn as a register save,
10258 only as a stack adjustment. The real copy of the register as
10259 a save will be done later, if needed. */
10264 }
10266 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10267 of DRAP is needed and stack realignment is really needed after reload */
10269 {
10272 /* Only need to push parameter pointer reg if it is caller saved. */
10274 {
10275 /* Push arg pointer reg */
10278 }
10280 /* Grab the argument pointer. */
10287 /* Align the stack. */
10289 stack_pointer_rtx,
10293 /* Replicate the return address on the stack so that return
10294 address can be reached via (argp - 1) slot. This is needed
10295 to implement macro RETURN_ADDR_RTX and intrinsic function
10296 expand_builtin_return_addr etc. */
10302 /* For the purposes of frame and register save area addressing,
10303 we've started over with a new frame. */
10306 }
10312 {
10313 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10314 slower on all targets. Also sdb doesn't like it. */
10318 /* Push registers now, before setting the frame pointer
10319 on SEH target. */
10321 && TARGET_SEH
10323 {
10327 }
10330 {
10338 }
10339 }
10342 {
10343 /* If saving registers via PUSH, do so now. */
10345 {
10349 }
10351 /* When using red zone we may start register saving before allocating
10352 the stack frame saving one cycle of the prologue. However, avoid
10353 doing this if we have to probe the stack; at least on x86_64 the
10354 stack probe can turn into a call that clobbers a red zone location. */
10356 && (! TARGET_STACK_PROBE
10358 {
10361 }
10362 }
10365 {
10369 /* The computation of the size of the re-aligned stack frame means
10370 that we must allocate the size of the register save area before
10371 performing the actual alignment. Otherwise we cannot guarantee
10372 that there's enough storage above the realignment point. */
10379 /* Align the stack. */
10381 stack_pointer_rtx,
10384 /* For the purposes of register save area addressing, the stack
10385 pointer is no longer valid. As for the value of sp_offset,
10386 see ix86_compute_frame_layout, which we need to match in order
10387 to pass verification of stack_pointer_offset at the end. */
10390 }
10395 {
10396 /* We start to count from ARG_POINTER. */
10399 /* If it was realigned, take into account the fake frame. */
10401 {
10408 /* This over-estimates by 1 minimal-stack-alignment-unit but
10409 mitigates that by counting in the new return address slot. */
10410 current_function_dynamic_stack_size
10412 }
10415 }
10417 /* On SEH target with very large frame size, allocate an area to save
10418 SSE registers (as the very large allocation won't be described). */
10422 {
10423 HOST_WIDE_INT sse_size =
10428 /* No need to do stack checking as the area will be immediately
10429 written. */
10436 }
10438 /* The stack has already been decremented by the instruction calling us
10439 so probe if the size is non-negative to preserve the protection area. */
10441 {
10442 /* We expect the registers to be saved when probes are used. */
10446 {
10449 }
10450 else
10451 {
10459 else
10461 }
10462 }
10465 ;
10468 {
10472 }
10473 else
10474 {
10487 /* Note that SEH directives need to continue tracking the stack
10488 pointer even after the frame pointer has been set up. */
10490 {
10494 {
10498 }
10499 }
10502 {
10507 {
10511 }
10512 }
10517 /* Use the fact that AX still contains ALLOCATE. */
10519 ? gen_pro_epilogue_adjust_stack_di_sub
10526 {
10534 }
10538 {
10545 }
10547 {
10552 }
10553 }
10556 /* If we havn't already set up the frame pointer, do so now. */
10558 {
10570 }
10581 {
10588 }
10591 {
10593 {
10595 {
10605 label));
10609 }
10610 else
10612 }
10613 else
10614 {
10618 }
10619 }
10621 /* In the pic_reg_used case, make sure that the got load isn't deleted
10622 when mcount needs it. Blockage to avoid call movement across mcount
10623 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10624 note. */
10629 {
10630 /* vDRAP is setup but after reload it turns out stack realign
10631 isn't necessary, here we will emit prologue to setup DRAP
10632 without stack realign adjustment */
10635 }
10637 /* Prevent instructions from being scheduled into register save push
10638 sequence when access to the redzone area is done through frame pointer.
10639 The offset between the frame pointer and the stack pointer is calculated
10640 relative to the value of the stack pointer at the end of the function
10641 prologue, and moving instructions that access redzone area via frame
10642 pointer inside push sequence violates this assumption. */
10646 /* Emit cld instruction if stringops are used in the function. */
10650 /* SEH requires that the prologue end within 256 bytes of the start of
10651 the function. Prevent instruction schedules that would extend that.
10652 Further, prevent alloca modifications to the stack pointer from being
10653 combined with prologue modifications. */
10656 }
10658 /* Emit code to restore REG using a POP insn. */
10660 static void
10662 {
10671 {
10672 /* Previously we'd represented the CFA as an expression
10673 like *(%ebp - 8). We've just popped that value from
10674 the stack, which means we need to reset the CFA to
10675 the drap register. This will remain until we restore
10676 the stack pointer. */
10680 /* This means that the DRAP register is valid for addressing too. */
10683 }
10686 {
10693 }
10695 /* When the frame pointer is the CFA, and we pop it, we are
10696 swapping back to the stack pointer as the CFA. This happens
10697 for stack frames that don't allocate other data, so we assume
10698 the stack pointer is now pointing at the return address, i.e.
10699 the function entry state, which makes the offset be 1 word. */
10701 {
10704 {
10712 }
10713 }
10714 }
10716 /* Emit code to restore saved registers using POP insns. */
10718 static void
10720 {
10726 }
10728 /* Emit code and notes for the LEAVE instruction. */
10730 static void
10732 {
10744 {
10752 }
10755 }
10757 /* Emit code to restore saved registers using MOV insns.
10758 First register is restored from CFA - CFA_OFFSET. */
10759 static void
10762 {
10768 {
10777 {
10778 /* Previously we'd represented the CFA as an expression
10779 like *(%ebp - 8). We've just popped that value from
10780 the stack, which means we need to reset the CFA to
10781 the drap register. This will remain until we restore
10782 the stack pointer. */
10786 /* This means that the DRAP register is valid for addressing. */
10788 }
10789 else
10793 }
10794 }
10796 /* Emit code to restore saved registers using MOV insns.
10797 First register is restored from CFA - CFA_OFFSET. */
10798 static void
10801 {
10806 {
10808 rtx mem;
10818 }
10819 }
10821 /* Restore function stack, frame, and registers. */
10823 void
10825 {
10841 /* The FP must be valid if the frame pointer is present. */
10846 /* We must have *some* valid pointer to the stack frame. */
10849 /* The DRAP is never valid at this point. */
10852 /* See the comment about red zone and frame
10853 pointer usage in ix86_expand_prologue. */
10860 /* Determine the CFA offset of the end of the red-zone. */
10863 {
10864 /* The red-zone begins below the return address. */
10867 /* When the register save area is in the aligned portion of
10868 the stack, determine the maximum runtime displacement that
10869 matches up with the aligned frame. */
10873 }
10875 /* Special care must be taken for the normal return case of a function
10876 using eh_return: the eax and edx registers are marked as saved, but
10877 not restored along this path. Adjust the save location to match. */
10881 /* EH_RETURN requires the use of moves to function properly. */
10884 /* SEH requires the use of pops to identify the epilogue. */
10887 /* If we're only restoring one register and sp is not valid then
10888 using a move instruction to restore the register since it's
10889 less work than reloading sp and popping the register. */
10902 && TARGET_USE_LEAVE
10906 else
10910 {
10911 /* Ensure that the entire register save area is addressable via
10912 the stack pointer, if we will restore via sp. */
10917 {
10921 style,
10923 }
10924 }
10926 /* If there are any SSE registers to restore, then we have to do it
10927 via moves, since there's obviously no pop for SSE regs. */
10933 {
10934 rtx t;
10939 /* eh_return epilogues need %ecx added to the stack pointer. */
10941 {
10944 /* Stack align doesn't work with eh_return. */
10946 /* Neither does regparm nested functions. */
10950 {
10958 /* Note that we use SA as a temporary CFA, as the return
10959 address is at the proper place relative to it. We
10960 pretend this happens at the FP restore insn because
10961 prior to this insn the FP would be stored at the wrong
10962 offset relative to SA, and after this insn we have no
10963 other reasonable register to use for the CFA. We don't
10964 bother resetting the CFA to the SP for the duration of
10965 the return insn. */
10978 }
10979 else
10980 {
10988 {
10992 UNITS_PER_WORD));
10994 }
10995 }
10998 }
10999 }
11000 else
11001 {
11002 /* SEH requires that the function end with (1) a stack adjustment
11003 if necessary, (2) a sequence of pops, and (3) a return or
11004 jump instruction. Prevent insns from the function body from
11005 being scheduled into this sequence. */
11007 {
11008 /* Prevent a catch region from being adjacent to the standard
11009 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11010 several other flags that would be interesting to test are
11011 not yet set up. */
11014 else
11016 }
11018 /* First step is to deallocate the stack frame so that we can
11019 pop the registers. Also do it on SEH target for very large
11020 frame as the emitted instructions aren't allowed by the ABI in
11021 epilogues. */
11023 || (TARGET_SEH
11026 {
11031 }
11033 {
11037 style,
11039 }
11042 }
11044 /* If we used a stack pointer and haven't already got rid of it,
11045 then do so now. */
11047 {
11048 /* If the stack pointer is valid and pointing at the frame
11049 pointer store address, then we only need a pop. */
11052 /* Leave results in shorter dependency chains on CPUs that are
11053 able to grok it fast. */
11058 else
11059 {
11061 hard_frame_pointer_rtx,
11064 }
11065 }
11068 {
11070 rtx insn;
11096 }
11098 /* At this point the stack pointer must be valid, and we must have
11099 restored all of the registers. We may not have deallocated the
11100 entire stack frame. We've delayed this until now because it may
11101 be possible to merge the local stack deallocation with the
11102 deallocation forced by ix86_static_chain_on_stack. */
11107 {
11111 }
11112 else
11115 /* Sibcall epilogues don't want a return instruction. */
11117 {
11120 }
11123 {
11126 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11127 address, do explicit add, and jump indirectly to the caller. */
11130 {
11132 rtx insn;
11134 /* There is no "pascal" calling convention in any 64bit ABI. */
11150 }
11151 else
11153 }
11154 else
11157 /* Restore the state back to the state from the prologue,
11158 so that it's correct for the next epilogue. */
11160 }
11162 /* Reset from the function's potential modifications. */
11164 static void
11166 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11167 {
11170 #if TARGET_MACHO
11171 /* Mach-O doesn't support labels at the end of objects, so if
11172 it looks like we might want one, insert a NOP. */
11173 {
11179 {
11180 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11181 notes only, instead set their CODE_LABEL_NUMBER to -1,
11182 otherwise there would be code generation differences
11183 in between -g and -g0. */
11187 }
11197 }
11198 #endif
11200 }
11202 /* Return a scratch register to use in the split stack prologue. The
11203 split stack prologue is used for -fsplit-stack. It is the first
11204 instructions in the function, even before the regular prologue.
11205 The scratch register can be any caller-saved register which is not
11206 used for parameters or for the static chain. */
11208 static unsigned int
11210 {
11213 else
11214 {
11227 {
11229 {
11233 }
11235 }
11237 {
11241 }
11243 {
11246 else
11247 {
11249 {
11253 }
11255 }
11256 }
11257 else
11258 {
11259 /* FIXME: We could make this work by pushing a register
11260 around the addition and comparison. */
11263 }
11264 }
11265 }
11267 /* A SYMBOL_REF for the function which allocates new stackspace for
11268 -fsplit-stack. */
11272 /* A SYMBOL_REF for the more stack function when using the large
11273 model. */
11277 /* Handle -fsplit-stack. These are the first instructions in the
11278 function, even before the regular prologue. */
11280 void
11282 {
11284 HOST_WIDE_INT allocate;
11289 rtx fn;
11297 /* This is the label we will branch to if we have enough stack
11298 space. We expect the basic block reordering pass to reverse this
11299 branch if optimizing, so that we branch in the unlikely case. */
11302 /* We need to compare the stack pointer minus the frame size with
11303 the stack boundary in the TCB. The stack boundary always gives
11304 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11305 can compare directly. Otherwise we need to do an addition. */
11308 UNSPEC_STACK_CHECK);
11313 else
11314 {
11316 rtx offset;
11318 /* We need a scratch register to hold the stack pointer minus
11319 the required frame size. Since this is the very start of the
11320 function, the scratch register can be any caller-saved
11321 register which is not used for parameters. */
11328 {
11329 /* We don't use ix86_gen_add3 in this case because it will
11330 want to split to lea, but when not optimizing the insn
11331 will not be split after this point. */
11334 offset)));
11335 }
11336 else
11337 {
11340 stack_pointer_rtx));
11341 }
11343 }
11349 /* Mark the jump as very likely to be taken. */
11357 /* Get more stack space. We pass in the desired stack space and the
11358 size of the arguments to copy to the new stack. In 32-bit mode
11359 we push the parameters; __morestack will return on a new stack
11360 anyhow. In 64-bit mode we pass the parameters in r10 and
11361 r11. */
11366 {
11372 /* If this function uses a static chain, it will be in %r10.
11373 Preserve it across the call to __morestack. */
11375 {
11376 rtx rax;
11381 }
11384 {
11385 HOST_WIDE_INT argval;
11388 /* When using the large model we need to load the address
11389 into a register, and we've run out of registers. So we
11390 switch to a different calling convention, and we call a
11391 different function: __morestack_large. We pass the
11392 argument size in the upper 32 bits of r10 and pass the
11393 frame size in the lower 32 bits. */
11398 split_stack_fn_large =
11402 {
11412 UNSPEC_GOT);
11418 }
11419 else
11426 }
11427 else
11428 {
11432 }
11435 }
11436 else
11437 {
11440 }
11446 /* In order to make call/return prediction work right, we now need
11447 to execute a return instruction. See
11448 libgcc/config/i386/morestack.S for the details on how this works.
11450 For flow purposes gcc must not see this as a return
11451 instruction--we need control flow to continue at the subsequent
11452 label. Therefore, we use an unspec. */
11456 /* If we are in 64-bit mode and this function uses a static chain,
11457 we saved %r10 in %rax before calling _morestack. */
11462 /* If this function calls va_start, we need to store a pointer to
11463 the arguments on the old stack, because they may not have been
11464 all copied to the new stack. At this point the old stack can be
11465 found at the frame pointer value used by __morestack, because
11466 __morestack has set that up before calling back to us. Here we
11467 store that pointer in a scratch register, and in
11468 ix86_expand_prologue we store the scratch register in a stack
11469 slot. */
11471 {
11473 rtx frame_reg;
11480 /* 64-bit:
11481 fp -> old fp value
11482 return address within this function
11483 return address of caller of this function
11484 stack arguments
11485 So we add three words to get to the stack arguments.
11487 32-bit:
11488 fp -> old fp value
11489 return address within this function
11490 first argument to __morestack
11491 second argument to __morestack
11492 return address of caller of this function
11493 stack arguments
11494 So we add five words to get to the stack arguments.
11495 */
11506 }
11511 /* If this function calls va_start, we now have to set the scratch
11512 register for the case where we do not call __morestack. In this
11513 case we need to set it based on the stack pointer. */
11515 {
11522 }
11523 }
11525 /* We may have to tell the dataflow pass that the split stack prologue
11526 is initializing a scratch register. */
11528 static void
11530 {
11532 {
11535 }
11536 }
11537 \f
11538 /* Determine if op is suitable SUBREG RTX for address. */
11540 static bool
11542 {
11553 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11554 failures when the register is one word out of a two word structure. */
11558 /* Allow only SUBREGs of non-eliminable hard registers. */
11560 }
11562 /* Extract the parts of an RTL expression that is a valid memory address
11563 for an instruction. Return 0 if the structure of the address is
11564 grossly off. Return -1 if the address contains ASHIFT, so it is not
11565 strictly valid, but still used for computing length of lea instruction. */
11567 int
11569 {
11574 rtx tmp;
11578 /* Allow zero-extended SImode addresses,
11579 they will be emitted with addr32 prefix. */
11581 {
11584 {
11588 }
11591 {
11598 }
11599 }
11601 /* Allow SImode subregs of DImode addresses,
11602 they will be emitted with addr32 prefix. */
11604 {
11607 {
11611 }
11612 }
11617 {
11620 else
11622 }
11624 {
11629 do
11630 {
11635 }
11642 {
11645 {
11670 /* FALLTHRU */
11674 && TARGET_TLS_DIRECT_SEG_REFS
11677 else
11684 /* FALLTHRU */
11691 else
11706 }
11707 }
11708 }
11710 {
11713 }
11715 {
11716 /* We're called for lea too, which implements ashift on occasion. */
11726 }
11728 {
11732 /* Constant addresses are sign extended to 64bit, we have to
11733 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11739 }
11740 else
11744 {
11746 ;
11749 ;
11750 else
11752 }
11754 /* Address override works only on the (%reg) part of %fs:(%reg). */
11760 /* Extract the integral value of scale. */
11762 {
11766 }
11771 /* Avoid useless 0 displacement. */
11775 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11780 {
11781 rtx tmp;
11784 }
11786 /* Special case: %ebp cannot be encoded as a base without a displacement.
11787 Similarly %r13. */
11789 && base_reg
11798 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11799 Avoid this by transforming to [%esi+0].
11800 Reload calls address legitimization without cfun defined, so we need
11801 to test cfun for being non-NULL. */
11807 /* Special case: encode reg+reg instead of reg*2. */
11811 /* Special case: scaling cannot be encoded without base or displacement. */
11822 }
11823 \f
11824 /* Return cost of the memory address x.
11825 For i386, it is better to use a complex address than let gcc copy
11826 the address into a reg and make a new pseudo. But not if the address
11827 requires to two regs - that would mean more pseudos with longer
11828 lifetimes. */
11829 static int
11831 addr_space_t as ATTRIBUTE_UNUSED,
11833 {
11845 /* Attempt to minimize number of registers in the address. */
11851 cost++;
11858 cost++;
11860 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11861 since it's predecode logic can't detect the length of instructions
11862 and it degenerates to vector decoded. Increase cost of such
11863 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11864 to split such addresses or even refuse such addresses at all.
11866 Following addressing modes are affected:
11867 [base+scale*index]
11868 [scale*index+disp]
11869 [base+index]
11871 The first and last case may be avoidable by explicitly coding the zero in
11872 memory address, but I don't have AMD-K6 machine handy to check this
11873 theory. */
11882 }
11883 \f
11884 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11885 this is used for to form addresses to local data when -fPIC is in
11886 use. */
11888 static bool
11890 {
11893 }
11895 /* Determine if a given RTX is a valid constant. We already know this
11896 satisfies CONSTANT_P. */
11898 static bool
11900 {
11902 {
11907 {
11911 }
11916 /* Only some unspecs are valid as "constants". */
11919 {
11935 }
11937 /* We must have drilled down to a symbol. */
11942 /* FALLTHRU */
11945 /* TLS symbols are never valid. */
11949 /* DLLIMPORT symbols are never valid. */
11954 #if TARGET_MACHO
11955 /* mdynamic-no-pic */
11958 #endif
11974 }
11976 /* Otherwise we handle everything else in the move patterns. */
11978 }
11980 /* Determine if it's legal to put X into the constant pool. This
11981 is not possible for the address of thread-local symbols, which
11982 is checked above. */
11984 static bool
11986 {
11987 /* We can always put integral constants and vectors in memory. */
11989 {
11997 }
11999 }
12002 /* Nonzero if the constant value X is a legitimate general operand
12003 when generating PIC code. It is given that flag_pic is on and
12004 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12006 bool
12008 {
12009 rtx inner;
12012 {
12019 /* Only some unspecs are valid as "constants". */
12022 {
12035 }
12036 /* FALLTHRU */
12044 }
12045 }
12047 /* Determine if a given CONST RTX is a valid memory displacement
12048 in PIC mode. */
12050 bool
12052 {
12055 /* In 64bit mode we can allow direct addresses of symbols and labels
12056 when they are not dynamic symbols. */
12058 {
12062 {
12086 /* FALLTHRU */
12089 /* TLS references should always be enclosed in UNSPEC. */
12099 }
12100 }
12106 {
12107 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12108 of GOT tables. We should not need these anyway. */
12120 }
12124 {
12129 }
12138 {
12142 /* We need to check for both symbols and labels because VxWorks loads
12143 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12144 details. */
12148 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12149 While ABI specify also 32bit relocation but we don't produce it in
12150 small PIC model at all. */
12172 }
12175 }
12177 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12178 replace the input X, or the original X if no replacement is called for.
12179 The output parameter *WIN is 1 if the calling macro should goto WIN,
12180 0 if it should not. */
12182 bool
12187 {
12188 /* Reload can generate:
12190 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12191 (reg:DI 97))
12192 (reg:DI 2 cx))
12194 This RTX is rejected from ix86_legitimate_address_p due to
12195 non-strictness of base register 97. Following this rejection,
12196 reload pushes all three components into separate registers,
12197 creating invalid memory address RTX.
12199 Following code reloads only the invalid part of the
12200 memory address RTX. */
12206 {
12212 {
12217 }
12221 {
12226 }
12230 }
12233 }
12235 /* Recognizes RTL expressions that are valid memory addresses for an
12236 instruction. The MODE argument is the machine mode for the MEM
12237 expression that wants to use this address.
12239 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12240 convert common non-canonical forms to canonical form so that they will
12241 be recognized. */
12243 static bool
12246 {
12249 HOST_WIDE_INT scale;
12252 /* Decomposition failed. */
12260 /* Validate base register. */
12262 {
12263 rtx reg;
12269 else
12270 /* Base is not a register. */
12278 /* Base is not valid. */
12280 }
12282 /* Validate index register. */
12284 {
12285 rtx reg;
12291 else
12292 /* Index is not a register. */
12300 /* Index is not valid. */
12302 }
12304 /* Index and base should have the same mode. */
12309 /* Validate scale factor. */
12311 {
12313 /* Scale without index. */
12317 /* Scale is not a valid multiplier. */
12319 }
12321 /* Validate displacement. */
12323 {
12328 {
12329 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12330 used. While ABI specify also 32bit relocations, we don't produce
12331 them at all and use IP relative instead. */
12338 /* 64bit address unspec. */
12358 /* Invalid address unspec. */
12360 }
12363 && (flag_pic
12364 || (TARGET_MACHO
12365 #if TARGET_MACHO
12366 && MACHOPIC_INDIRECT
12368 #endif
12369 )))
12370 {
12372 is_legitimate_pic:
12374 {
12375 /* foo@dtpoff(%rX) is ok. */
12382 /* Non-constant pic memory reference. */
12384 }
12387 /* Displacement is an invalid pic construct. */
12389 #if TARGET_MACHO
12392 /* displacment must be referenced via non_lazy_pointer */
12394 #endif
12396 /* This code used to verify that a symbolic pic displacement
12397 includes the pic_offset_table_rtx register.
12399 While this is good idea, unfortunately these constructs may
12400 be created by "adds using lea" optimization for incorrect
12401 code like:
12403 int a;
12404 int foo(int i)
12405 {
12406 return *(&a+i);
12407 }
12409 This code is nonsensical, but results in addressing
12410 GOT table with pic_offset_table_rtx base. We can't
12411 just refuse it easily, since it gets matched by
12412 "addsi3" pattern, that later gets split to lea in the
12413 case output register differs from input. While this
12414 can be handled by separate addsi pattern for this case
12415 that never results in lea, this seems to be easier and
12416 correct fix for crash to disable this test. */
12417 }
12424 /* Displacement is not constant. */
12428 /* Displacement is out of range. */
12430 }
12432 /* Everything looks valid. */
12434 }
12436 /* Determine if a given RTX is a valid constant address. */
12438 bool
12440 {
12442 }
12443 \f
12444 /* Return a unique alias set for the GOT. */
12446 static alias_set_type
12448 {
12453 }
12455 /* Return a legitimate reference for ORIG (an address) using the
12456 register REG. If REG is 0, a new pseudo is generated.
12458 There are two types of references that must be handled:
12460 1. Global data references must load the address from the GOT, via
12461 the PIC reg. An insn is emitted to do this load, and the reg is
12462 returned.
12464 2. Static data references, constant pool addresses, and code labels
12465 compute the address as an offset from the GOT, whose base is in
12466 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12467 differentiate them from global data objects. The returned
12468 address is the PIC reg + an unspec constant.
12470 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12471 reg also appears in the address. */
12473 static rtx
12475 {
12479 #if TARGET_MACHO
12481 {
12484 /* Use the generic Mach-O PIC machinery. */
12486 }
12487 #endif
12494 {
12495 rtx tmpreg;
12496 /* This symbol may be referenced via a displacement from the PIC
12497 base address (@GOTOFF). */
12504 {
12506 UNSPEC_GOTOFF);
12508 }
12509 else
12514 else
12519 {
12523 }
12525 }
12527 {
12528 /* This symbol may be referenced via a displacement from the PIC
12529 base address (@GOTOFF). */
12536 {
12538 UNSPEC_GOTOFF);
12540 }
12541 else
12547 {
12550 }
12551 }
12553 /* We can't use @GOTOFF for text labels on VxWorks;
12554 see gotoff_operand. */
12556 {
12558 {
12564 {
12567 }
12568 }
12570 /* For x64 PE-COFF there is no GOT table. So we use address
12571 directly. */
12573 {
12581 }
12583 {
12591 /* Use directly gen_movsi, otherwise the address is loaded
12592 into register for CSE. We don't want to CSE this addresses,
12593 instead we CSE addresses from the GOT table, so skip this. */
12596 }
12597 else
12598 {
12599 /* This symbol must be referenced via a load from the
12600 Global Offset Table (@GOT). */
12616 }
12617 }
12618 else
12619 {
12622 {
12624 {
12627 }
12628 else
12630 }
12632 {
12635 /* We must match stuff we generate before. Assume the only
12636 unspecs that can get here are ours. Not that we could do
12637 anything with them anyway.... */
12643 }
12645 {
12648 /* Check first to see if this is a constant offset from a @GOTOFF
12649 symbol reference. */
12652 {
12654 {
12658 UNSPEC_GOTOFF);
12664 {
12667 }
12668 }
12669 else
12670 {
12673 {
12677 }
12678 }
12679 }
12680 else
12681 {
12684 new_rtx
12688 {
12691 {
12694 new_rtx
12696 }
12697 else
12699 }
12700 else
12701 {
12704 {
12707 }
12709 }
12710 }
12711 }
12712 }
12714 }
12715 \f
12716 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12718 static rtx
12720 {
12724 {
12729 }
12735 }
12737 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12741 static rtx
12743 {
12745 {
12751 }
12754 }
12756 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12760 rtx
12762 {
12764 {
12765 ix86_tls_module_base_symbol
12770 }
12773 }
12775 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12776 false if we expect this to be used for a memory address and true if
12777 we expect to load the address into a register. */
12779 static rtx
12781 {
12788 {
12793 {
12796 else
12797 {
12800 }
12801 }
12804 {
12807 else
12817 }
12818 else
12819 {
12823 {
12825 rtx insns;
12828 emit_call_insn
12838 }
12839 else
12841 }
12848 {
12851 else
12852 {
12855 }
12856 }
12859 {
12864 else
12870 }
12871 else
12872 {
12876 {
12881 emit_call_insn
12886 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12887 share the LD_BASE result with other LD model accesses. */
12889 UNSPEC_TLS_LD_BASE);
12893 }
12894 else
12896 }
12904 {
12911 }
12916 {
12918 {
12919 /* The Sun linker took the AMD64 TLS spec literally
12920 and can only handle %rax as destination of the
12921 initial executable code sequence. */
12926 }
12928 /* Generate DImode references to avoid %fs:(%reg32)
12929 problems and linker IE->LE relaxation bug. */
12933 }
12935 {
12940 }
12942 {
12946 }
12947 else
12948 {
12951 }
12961 {
12966 }
12967 else
12968 {
12972 }
12982 {
12986 }
12987 else
12988 {
12992 }
12997 }
13000 }
13002 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13003 to symbol DECL. */
13006 htab_t dllimport_map;
13008 static tree
13010 {
13017 tree to;
13018 rtx rtl;
13062 }
13064 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13065 true if we require the result be a register. */
13067 static rtx
13069 {
13070 tree imp_decl;
13071 rtx x;
13080 }
13082 /* Try machine-dependent ways of modifying an illegitimate address
13083 to be legitimate. If we find one, return the new, valid address.
13084 This macro is used in only one place: `memory_address' in explow.c.
13086 OLDX is the address as it was before break_out_memory_refs was called.
13087 In some cases it is useful to look at this to decide what needs to be done.
13089 It is always safe for this macro to do nothing. It exists to recognize
13090 opportunities to optimize the output.
13092 For the 80386, we handle X+REG by loading X into a register R and
13093 using R+REG. R will go in a general reg and indexing will be used.
13094 However, if REG is a broken-out memory address or multiplication,
13095 nothing needs to be done because REG can certainly go in a general reg.
13097 When -fpic is used, special handling is needed for symbolic references.
13098 See comments by legitimize_pic_address in i386.c for details. */
13100 static rtx
13103 {
13114 {
13118 }
13121 {
13128 {
13131 }
13132 }
13137 #if TARGET_MACHO
13140 #endif
13142 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13146 {
13151 }
13154 {
13155 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13160 {
13166 }
13171 {
13177 }
13179 /* Put multiply first if it isn't already. */
13181 {
13186 }
13188 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13189 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13190 created by virtual register instantiation, register elimination, and
13191 similar optimizations. */
13193 {
13199 }
13201 /* Canonicalize
13202 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13203 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13208 {
13209 rtx constant;
13213 {
13216 }
13218 {
13221 }
13222 else
13226 {
13233 }
13234 }
13240 {
13243 }
13246 {
13249 }
13257 {
13260 }
13266 {
13270 {
13273 }
13277 }
13280 {
13284 {
13287 }
13291 }
13292 }
13295 }
13296 \f
13297 /* Print an integer constant expression in assembler syntax. Addition
13298 and subtraction are the only arithmetic that may appear in these
13299 expressions. FILE is the stdio stream to write to, X is the rtx, and
13300 CODE is the operand print code from the output string. */
13302 static void
13304 {
13308 {
13317 else
13318 {
13321 /* Mark the decl as referenced so that cgraph will
13322 output the function. */
13326 #if TARGET_MACHO
13330 #endif
13332 }
13340 /* FALLTHRU */
13351 /* This used to output parentheses around the expression,
13352 but that does not work on the 386 (either ATT or BSD assembler). */
13358 {
13359 /* We can use %d if the number is <32 bits and positive. */
13364 else
13366 }
13367 else
13368 /* We can't handle floating point constants;
13369 TARGET_PRINT_OPERAND must handle them. */
13374 /* Some assemblers need integer constants to appear first. */
13376 {
13380 }
13381 else
13382 {
13387 }
13402 {
13406 }
13411 {
13430 /* FIXME: This might be @TPOFF in Sun ld too. */
13439 else
13449 else
13455 #if TARGET_MACHO
13460 #endif
13464 }
13469 }
13470 }
13472 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13473 We need to emit DTP-relative relocations. */
13475 static void ATTRIBUTE_UNUSED
13477 {
13482 {
13490 }
13491 }
13493 /* Return true if X is a representation of the PIC register. This copes
13494 with calls from ix86_find_base_term, where the register might have
13495 been replaced by a cselib value. */
13497 static bool
13499 {
13503 else
13505 }
13507 /* Helper function for ix86_delegitimize_address.
13508 Attempt to delegitimize TLS local-exec accesses. */
13510 static rtx
13512 {
13537 {
13542 }
13548 }
13550 /* In the name of slightly smaller debug output, and to cater to
13551 general assembler lossage, recognize PIC+GOTOFF and turn it back
13552 into a direct symbol reference.
13554 On Darwin, this is necessary to avoid a crash, because Darwin
13555 has a different PIC label for each routine but the DWARF debugging
13556 information is not associated with any particular routine, so it's
13557 necessary to remove references to the PIC label from RTL stored by
13558 the DWARF output code. */
13560 static rtx
13562 {
13564 /* addend is NULL or some rtx if x is something+GOTOFF where
13565 something doesn't include the PIC register. */
13567 /* reg_addend is NULL or a multiple of some register. */
13569 /* const_addend is NULL or a const_int. */
13571 /* This is the result, or NULL. */
13580 {
13587 {
13593 }
13602 {
13607 }
13609 }
13616 /* %ebx + GOT/GOTOFF */
13617 ;
13619 {
13620 /* %ebx + %reg * scale + GOT/GOTOFF */
13626 else
13627 {
13630 }
13631 }
13632 else
13638 {
13641 }
13660 {
13661 /* If the rest of original X doesn't involve the PIC register, add
13662 addend and subtract pic_offset_table_rtx. This can happen e.g.
13663 for code like:
13664 leal (%ebx, %ecx, 4), %ecx
13665 ...
13666 movl foo@GOTOFF(%ecx), %edx
13667 in which case we return (%ecx - %ebx) + foo. */
13670 pic_offset_table_rtx),
13671 result);
13672 else
13674 }
13676 {
13680 }
13682 }
13684 /* If X is a machine specific address (i.e. a symbol or label being
13685 referenced as a displacement from the GOT implemented using an
13686 UNSPEC), then return the base term. Otherwise return X. */
13688 rtx
13690 {
13691 rtx term;
13694 {
13708 }
13711 }
13712 \f
13713 static void
13716 {
13720 {
13723 }
13728 {
13731 {
13750 }
13754 {
13773 }
13780 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13781 Those same assemblers have the same but opposite lossage on cmov. */
13786 else
13791 {
13804 }
13812 {
13825 }
13828 /* ??? As above. */
13837 /* ??? As above. */
13842 else
13853 }
13855 }
13857 /* Print the name of register X to FILE based on its machine mode and number.
13858 If CODE is 'w', pretend the mode is HImode.
13859 If CODE is 'b', pretend the mode is QImode.
13860 If CODE is 'k', pretend the mode is SImode.
13861 If CODE is 'q', pretend the mode is DImode.
13862 If CODE is 'x', pretend the mode is V4SFmode.
13863 If CODE is 't', pretend the mode is V8SFmode.
13864 If CODE is 'h', pretend the reg is the 'high' byte register.
13865 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13866 If CODE is 'd', duplicate the operand for AVX instruction.
13867 */
13869 void
13871 {
13880 {
13884 }
13909 else
13912 /* Irritatingly, AMD extended registers use different naming convention
13913 from the normal registers: "r%d[bwd]" */
13915 {
13920 {
13934 /* no suffix */
13939 }
13941 }
13945 {
13948 {
13951 }
13952 /* FALLTHRU */
13958 /* FALLTHRU */
13961 normal:
13976 {
13981 }
13985 }
13989 {
13992 else
13994 }
13995 }
13997 /* Locate some local-dynamic symbol still in use by this function
13998 so that we can print its name in some tls_local_dynamic_base
13999 pattern. */
14001 static int
14003 {
14008 {
14011 }
14014 }
14018 {
14019 rtx insn;
14030 }
14032 /* Meaning of CODE:
14033 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14034 C -- print opcode suffix for set/cmov insn.
14035 c -- like C, but print reversed condition
14036 F,f -- likewise, but for floating-point.
14037 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14038 otherwise nothing
14039 R -- print the prefix for register names.
14040 z -- print the opcode suffix for the size of the current operand.
14041 Z -- likewise, with special suffixes for x87 instructions.
14042 * -- print a star (in certain assembler syntax)
14043 A -- print an absolute memory reference.
14044 E -- print address with DImode register names if TARGET_64BIT.
14045 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14046 s -- print a shift double count, followed by the assemblers argument
14047 delimiter.
14048 b -- print the QImode name of the register for the indicated operand.
14049 %b0 would print %al if operands[0] is reg 0.
14050 w -- likewise, print the HImode name of the register.
14051 k -- likewise, print the SImode name of the register.
14052 q -- likewise, print the DImode name of the register.
14053 x -- likewise, print the V4SFmode name of the register.
14054 t -- likewise, print the V8SFmode name of the register.
14055 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14056 y -- print "st(0)" instead of "st" as a register.
14057 d -- print duplicated register operand for AVX instruction.
14058 D -- print condition for SSE cmp instruction.
14059 P -- if PIC, print an @PLT suffix.
14060 p -- print raw symbol name.
14061 X -- don't print any sort of PIC '@' suffix for a symbol.
14062 & -- print some in-use local-dynamic symbol name.
14063 H -- print a memory address offset by 8; used for sse high-parts
14064 Y -- print condition for XOP pcom* instruction.
14065 + -- print a branch hint as 'cs' or 'ds' prefix
14066 ; -- print a semicolon (after prefixes due to bug in older gas).
14067 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14068 @ -- print a segment register of thread base pointer load
14069 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14070 */
14072 void
14074 {
14076 {
14078 {
14081 {
14087 /* Intel syntax. For absolute addresses, registers should not
14088 be surrounded by braces. */
14090 {
14095 }
14100 }
14106 /* Wrap address in an UNSPEC to declare special handling. */
14144 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14149 {
14163 output_operand_lossage
14166 }
14169 #endif
14174 {
14175 /* Opcodes don't get size suffixes if using Intel opcodes. */
14180 {
14198 output_operand_lossage
14201 }
14202 }
14205 warning
14207 /* FALLTHRU */
14210 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14215 {
14217 {
14219 #ifdef HAVE_AS_IX86_FILDS
14221 #endif
14229 #ifdef HAVE_AS_IX86_FILDQ
14231 #else
14233 #endif
14238 }
14239 }
14241 {
14242 /* 387 opcodes don't get size suffixes
14243 if the operands are registers. */
14248 {
14264 }
14265 }
14266 else
14267 {
14268 output_operand_lossage
14271 }
14273 output_operand_lossage
14293 {
14296 }
14301 {
14352 }
14356 /* Little bit of braindamage here. The SSE compare instructions
14357 does use completely different names for the comparisons that the
14358 fp conditional moves. */
14360 {
14363 {
14366 }
14372 {
14375 }
14381 {
14384 }
14393 {
14396 }
14402 {
14405 }
14411 {
14414 }
14425 }
14430 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14433 #endif
14438 {
14442 }
14446 file);
14451 {
14455 }
14456 /* It doesn't actually matter what mode we use here, as we're
14457 only going to use this for printing. */
14465 #ifdef HAVE_AS_IX86_HLE
14467 #else
14469 #endif
14471 #ifdef HAVE_AS_IX86_HLE
14473 #else
14475 #endif
14476 /* We do not want to print value of the operand. */
14485 {
14490 else
14493 }
14496 {
14497 rtx x;
14506 {
14511 {
14513 bool cputaken
14516 /* Emit hints only in the case default branch prediction
14517 heuristics would fail. */
14519 {
14520 /* We use 3e (DS) prefix for taken branches and
14521 2e (CS) prefix for not taken branches. */
14524 else
14526 }
14527 }
14528 }
14530 }
14533 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14535 #endif
14542 /* The kernel uses a different segment register for performance
14543 reasons; a system call would not have to trash the userspace
14544 segment register, which would be expensive. */
14547 else
14562 }
14563 }
14569 {
14570 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14573 {
14576 {
14585 else
14591 }
14593 /* Check for explicit size override (codes 'b', 'w', 'k',
14594 'q' and 'x') */
14608 }
14611 /* Avoid (%rip) for call operands. */
14617 else
14619 }
14622 {
14623 REAL_VALUE_TYPE r;
14631 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14635 else
14637 }
14640 {
14641 REAL_VALUE_TYPE r;
14650 }
14652 /* These float cases don't actually occur as immediate operands. */
14654 {
14659 }
14661 else
14662 {
14663 /* We have patterns that allow zero sets of memory, for instance.
14664 In 64-bit mode, we should probably support all 8-byte vectors,
14665 since we can in fact encode that into an immediate. */
14667 {
14670 }
14673 {
14675 {
14678 }
14681 {
14684 else
14686 }
14687 }
14692 else
14694 }
14695 }
14697 static bool
14699 {
14702 }
14703 \f
14704 /* Print a memory operand whose address is ADDR. */
14706 static void
14708 {
14717 {
14724 }
14726 {
14730 }
14731 else
14742 {
14753 }
14755 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14757 {
14769 }
14771 {
14772 /* Displacement only requires special attention. */
14775 {
14779 }
14782 else
14784 }
14785 else
14786 {
14787 /* Print SImode register names to force addr32 prefix. */
14789 {
14790 #ifdef ENABLE_CHECKING
14793 {
14804 }
14805 #endif
14808 }
14810 && TARGET_X32
14811 && disp
14814 {
14815 /* X32 runs in 64-bit mode, where displacement, DISP, in
14816 address DISP(%r64), is encoded as 32-bit immediate sign-
14817 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14818 address is %r64 + 0xffffffffbffffd00. When %r64 <
14819 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14820 which is invalid for x32. The correct address is %r64
14821 - 0x40000300 == 0xf7ffdd64. To properly encode
14822 -0x40000300(%r64) for x32, we zero-extend negative
14823 displacement by forcing addr32 prefix which truncates
14824 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14825 zero-extend all negative displacements, including -1(%rsp).
14826 However, for small negative displacements, sign-extension
14827 won't cause overflow. We only zero-extend negative
14828 displacements if they < -16*1024*1024, which is also used
14829 to check legitimate address displacements for PIC. */
14831 }
14834 {
14836 {
14841 else
14843 }
14849 {
14854 }
14856 }
14857 else
14858 {
14862 {
14863 /* Pull out the offset of a symbol; print any symbol itself. */
14867 {
14871 }
14879 else
14881 }
14885 {
14888 {
14892 }
14893 }
14896 else
14900 {
14905 }
14907 }
14908 }
14909 }
14911 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14913 static bool
14915 {
14916 rtx op;
14923 {
14926 /* FIXME: This might be @TPOFF in Sun ld. */
14937 else
14949 else
14956 #if TARGET_MACHO
14962 #endif
14965 {
14970 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14972 #else
14974 #endif
14977 }
14982 }
14985 }
14986 \f
14987 /* Split one or more double-mode RTL references into pairs of half-mode
14988 references. The RTL can be REG, offsettable MEM, integer constant, or
14989 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14990 split and "num" is its length. lo_half and hi_half are output arrays
14991 that parallel "operands". */
14993 void
14996 {
15001 {
15010 }
15015 {
15018 /* simplify_subreg refuse to split volatile memory addresses,
15019 but we still have to handle it. */
15021 {
15024 }
15025 else
15026 {
15033 }
15034 }
15035 }
15036 \f
15037 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15038 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15039 is the expression of the binary operation. The output may either be
15040 emitted here, or returned to the caller, like all output_* functions.
15042 There is no guarantee that the operands are the same mode, as they
15043 might be within FLOAT or FLOAT_EXTEND expressions. */
15045 #ifndef SYSV386_COMPAT
15046 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15047 wants to fix the assemblers because that causes incompatibility
15048 with gcc. No-one wants to fix gcc because that causes
15049 incompatibility with assemblers... You can use the option of
15050 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15051 #define SYSV386_COMPAT 1
15052 #endif
15056 {
15062 #ifdef ENABLE_CHECKING
15063 /* Even if we do not want to check the inputs, this documents input
15064 constraints. Which helps in understanding the following code. */
15074 else
15076 #endif
15079 {
15084 else
15093 else
15102 else
15111 else
15118 }
15121 {
15123 {
15127 else
15129 }
15130 else
15131 {
15135 else
15137 }
15139 }
15143 {
15147 {
15151 }
15153 /* know operands[0] == operands[1]. */
15156 {
15159 }
15162 {
15164 /* How is it that we are storing to a dead operand[2]?
15165 Well, presumably operands[1] is dead too. We can't
15166 store the result to st(0) as st(0) gets popped on this
15167 instruction. Instead store to operands[2] (which I
15168 think has to be st(1)). st(1) will be popped later.
15169 gcc <= 2.8.1 didn't have this check and generated
15170 assembly code that the Unixware assembler rejected. */
15172 else
15175 }
15179 else
15186 {
15189 }
15192 {
15195 }
15198 {
15199 #if SYSV386_COMPAT
15200 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15201 derived assemblers, confusingly reverse the direction of
15202 the operation for fsub{r} and fdiv{r} when the
15203 destination register is not st(0). The Intel assembler
15204 doesn't have this brain damage. Read !SYSV386_COMPAT to
15205 figure out what the hardware really does. */
15208 else
15210 #else
15212 /* As above for fmul/fadd, we can't store to st(0). */
15214 else
15216 #endif
15218 }
15221 {
15222 #if SYSV386_COMPAT
15225 else
15227 #else
15230 else
15232 #endif
15234 }
15237 {
15240 else
15243 }
15245 {
15246 #if SYSV386_COMPAT
15248 #else
15250 #endif
15251 }
15252 else
15253 {
15254 #if SYSV386_COMPAT
15256 #else
15258 #endif
15259 }
15264 }
15268 }
15270 /* Check if a 256bit AVX register is referenced inside of EXP. */
15272 static int
15274 {
15285 }
15287 /* Return needed mode for entity in optimize_mode_switching pass. */
15289 static int
15291 {
15293 {
15294 rtx link;
15296 /* Needed mode is set to AVX_U128_CLEAN if there are
15297 no 256bit modes used in function arguments. */
15299 link;
15301 {
15303 {
15308 }
15309 }
15312 }
15314 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15315 changes state only when a 256bit register is written to, but we need
15316 to prevent the compiler from moving optimal insertion point above
15317 eventual read from 256bit register. */
15322 }
15324 /* Return mode that i387 must be switched into
15325 prior to the execution of insn. */
15327 static int
15329 {
15332 /* The mode UNINITIALIZED is used to store control word after a
15333 function call or ASM pattern. The mode ANY specify that function
15334 has no requirements on the control word and make no changes in the
15335 bits we are interested in. */
15349 {
15372 }
15375 }
15377 /* Return mode that entity must be switched into
15378 prior to the execution of insn. */
15380 int
15382 {
15384 {
15394 }
15396 }
15398 /* Check if a 256bit AVX register is referenced in stores. */
15400 static void
15402 {
15404 {
15407 }
15408 }
15410 /* Calculate mode of upper 128bit AVX registers after the insn. */
15412 static int
15414 {
15421 /* We know that state is clean after CALL insn if there are no
15422 256bit registers used in the function return register. */
15424 {
15429 }
15431 /* Otherwise, return current mode. Remember that if insn
15432 references AVX 256bit registers, the mode was already changed
15433 to DIRTY from MODE_NEEDED. */
15435 }
15437 /* Return the mode that an insn results in. */
15439 int
15441 {
15443 {
15453 }
15454 }
15456 static int
15458 {
15459 tree arg;
15461 /* Entry mode is set to AVX_U128_DIRTY if there are
15462 256bit modes used in function arguments. */
15465 {
15470 }
15473 }
15475 /* Return a mode that ENTITY is assumed to be
15476 switched to at function entry. */
15478 int
15480 {
15482 {
15492 }
15493 }
15495 static int
15497 {
15500 /* Exit mode is set to AVX_U128_DIRTY if there are
15501 256bit modes used in the function return register. */
15506 }
15508 /* Return a mode that ENTITY is assumed to be
15509 switched to at function exit. */
15511 int
15513 {
15515 {
15525 }
15526 }
15528 /* Output code to initialize control word copies used by trunc?f?i and
15529 rounding patterns. CURRENT_MODE is set to current control word,
15530 while NEW_MODE is set to new control word. */
15532 static void
15534 {
15536 rtx new_mode;
15547 {
15549 {
15551 /* round toward zero (truncate) */
15557 /* round down toward -oo */
15564 /* round up toward +oo */
15571 /* mask precision exception for nearbyint() */
15578 }
15579 }
15580 else
15581 {
15583 {
15585 /* round toward zero (truncate) */
15591 /* round down toward -oo */
15597 /* round up toward +oo */
15603 /* mask precision exception for nearbyint() */
15610 }
15611 }
15617 }
15619 /* Emit vzeroupper. */
15621 void
15623 {
15626 /* Cancel automatic vzeroupper insertion if there are
15627 live call-saved SSE registers at the insertion point. */
15639 }
15641 /* Generate one or more insns to set ENTITY to MODE. */
15643 void
15645 {
15647 {
15662 }
15663 }
15665 /* Output code for INSN to convert a float to a signed int. OPERANDS
15666 are the insn operands. The output may be [HSD]Imode and the input
15667 operand may be [SDX]Fmode. */
15671 {
15676 /* Jump through a hoop or two for DImode, since the hardware has no
15677 non-popping instruction. We used to do this a different way, but
15678 that was somewhat fragile and broke with post-reload splitters. */
15688 else
15689 {
15694 else
15698 }
15701 }
15703 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15704 have the values zero or one, indicates the ffreep insn's operand
15705 from the OPERANDS array. */
15709 {
15711 #ifdef HAVE_AS_IX86_FFREEP
15713 #else
15714 {
15724 }
15725 #endif
15728 }
15731 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15732 should be used. UNORDERED_P is true when fucom should be used. */
15736 {
15742 {
15745 }
15746 else
15747 {
15750 }
15753 {
15757 else
15759 else
15762 else
15764 }
15771 {
15773 {
15776 }
15777 else
15779 }
15782 && stack_top_dies
15785 {
15786 /* If both the top of the 387 stack dies, and the other operand
15787 is also a stack register that dies, then this must be a
15788 `fcompp' float compare */
15791 {
15792 /* There is no double popping fcomi variant. Fortunately,
15793 eflags is immune from the fstp's cc clobbering. */
15796 else
15799 }
15800 else
15801 {
15804 else
15806 }
15807 }
15808 else
15809 {
15810 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15813 {
15821 NULL,
15822 NULL,
15829 NULL,
15830 NULL,
15831 NULL,
15832 NULL
15833 };
15848 }
15849 }
15851 void
15853 {
15856 #ifdef ASM_QUAD
15859 #else
15861 #endif
15864 }
15866 void
15868 {
15871 #ifdef ASM_QUAD
15874 #else
15876 #endif
15877 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15883 #if TARGET_MACHO
15885 {
15889 }
15890 #endif
15891 else
15894 }
15895 \f
15896 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15897 for the target. */
15899 void
15901 {
15902 rtx tmp;
15904 /* We play register width games, which are only valid after reload. */
15907 /* Avoid HImode and its attendant prefix byte. */
15912 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15914 {
15917 }
15920 }
15922 /* X is an unchanging MEM. If it is a constant pool reference, return
15923 the constant pool rtx, else NULL. */
15925 rtx
15927 {
15934 }
15936 void
15938 {
15946 {
15949 {
15955 }
15959 }
15963 {
15976 {
15983 }
15984 }
15988 {
15990 {
15991 #if TARGET_MACHO
15992 /* dynamic-no-pic */
15994 {
15995 rtx temp = ((reload_in_progress
16003 }
16005 {
16009 }
16012 else
16013 {
16021 }
16022 /* dynamic-no-pic */
16023 #endif
16024 }
16025 else
16026 {
16030 {
16036 }
16037 }
16038 }
16039 else
16040 {
16051 /* Force large constants in 64bit compilation into register
16052 to get them CSEed. */
16064 {
16065 /* If we are loading a floating point constant to a register,
16066 force the value to memory now, since we'll get better code
16067 out the back end. */
16071 {
16076 }
16077 }
16078 }
16081 }
16083 void
16085 {
16089 /* Force constants other than zero into memory. We do not know how
16090 the instructions used to build constants modify the upper 64 bits
16091 of the register, once we have that information we may be able
16092 to handle some of them more efficiently. */
16101 /* We need to check memory alignment for SSE mode since attribute
16102 can make operands unaligned. */
16107 {
16110 /* ix86_expand_vector_move_misalign() does not like constants ... */
16116 /* ... nor both arguments in memory. */
16124 }
16126 /* Make operand1 a register if it isn't already. */
16130 {
16133 }
16136 }
16138 /* Split 32-byte AVX unaligned load and store if needed. */
16140 static void
16142 {
16143 rtx m;
16150 {
16171 }
16174 {
16176 {
16183 }
16184 else
16186 }
16188 {
16190 {
16195 }
16196 else
16198 }
16199 else
16201 }
16203 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16204 straight to ix86_expand_vector_move. */
16205 /* Code generation for scalar reg-reg moves of single and double precision data:
16206 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16207 movaps reg, reg
16208 else
16209 movss reg, reg
16210 if (x86_sse_partial_reg_dependency == true)
16211 movapd reg, reg
16212 else
16213 movsd reg, reg
16215 Code generation for scalar loads of double precision data:
16216 if (x86_sse_split_regs == true)
16217 movlpd mem, reg (gas syntax)
16218 else
16219 movsd mem, reg
16221 Code generation for unaligned packed loads of single precision data
16222 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16223 if (x86_sse_unaligned_move_optimal)
16224 movups mem, reg
16226 if (x86_sse_partial_reg_dependency == true)
16227 {
16228 xorps reg, reg
16229 movlps mem, reg
16230 movhps mem+8, reg
16231 }
16232 else
16233 {
16234 movlps mem, reg
16235 movhps mem+8, reg
16236 }
16238 Code generation for unaligned packed loads of double precision data
16239 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16240 if (x86_sse_unaligned_move_optimal)
16241 movupd mem, reg
16243 if (x86_sse_split_regs == true)
16244 {
16245 movlpd mem, reg
16246 movhpd mem+8, reg
16247 }
16248 else
16249 {
16250 movsd mem, reg
16251 movhpd mem+8, reg
16252 }
16253 */
16255 void
16257 {
16265 {
16267 {
16272 /* FALLTHRU */
16280 }
16283 }
16286 {
16287 /* ??? If we have typed data, then it would appear that using
16288 movdqu is the only way to get unaligned data loaded with
16289 integer type. */
16291 {
16294 /* We will eventually emit movups based on insn attributes. */
16296 }
16298 {
16299 rtx zero;
16302 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16303 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16305 {
16306 /* We will eventually emit movups based on insn attributes. */
16309 }
16311 /* When SSE registers are split into halves, we can avoid
16312 writing to the top half twice. */
16314 {
16317 }
16318 else
16319 {
16320 /* ??? Not sure about the best option for the Intel chips.
16321 The following would seem to satisfy; the register is
16322 entirely cleared, breaking the dependency chain. We
16323 then store to the upper half, with a dependency depth
16324 of one. A rumor has it that Intel recommends two movsd
16325 followed by an unpacklpd, but this is unconfirmed. And
16326 given that the dependency depth of the unpacklpd would
16327 still be one, I'm not sure why this would be better. */
16329 }
16335 }
16336 else
16337 {
16339 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16340 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16342 {
16347 }
16351 else
16361 }
16362 }
16364 {
16366 {
16369 /* We will eventually emit movups based on insn attributes. */
16371 }
16373 {
16375 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16376 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16378 /* We will eventually emit movups based on insn attributes. */
16380 else
16381 {
16386 }
16387 }
16388 else
16389 {
16394 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16395 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16397 {
16400 }
16401 else
16402 {
16407 }
16408 }
16409 }
16410 else
16412 }
16414 /* Expand a push in MODE. This is some mode for which we do not support
16415 proper push instructions, at least from the registers that we expect
16416 the value to live in. */
16418 void
16420 {
16421 rtx tmp;
16431 /* When we push an operand onto stack, it has to be aligned at least
16432 at the function argument boundary. However since we don't have
16433 the argument type, we can't determine the actual argument
16434 boundary. */
16436 }
16438 /* Helper function of ix86_fixup_binary_operands to canonicalize
16439 operand order. Returns true if the operands should be swapped. */
16441 static bool
16443 rtx operands[])
16444 {
16449 /* If the operation is not commutative, we can't do anything. */
16453 /* Highest priority is that src1 should match dst. */
16459 /* Next highest priority is that immediate constants come second. */
16465 /* Lowest priority is that memory references should come second. */
16472 }
16475 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16476 destination to use for the operation. If different from the true
16477 destination in operands[0], a copy operation will be required. */
16479 rtx
16481 rtx operands[])
16482 {
16487 /* Canonicalize operand order. */
16489 {
16490 rtx temp;
16492 /* It is invalid to swap operands of different modes. */
16498 }
16500 /* Both source operands cannot be in memory. */
16502 {
16503 /* Optimization: Only read from memory once. */
16505 {
16508 }
16509 else
16511 }
16513 /* If the destination is memory, and we do not have matching source
16514 operands, do things in registers. */
16518 /* Source 1 cannot be a constant. */
16522 /* Source 1 cannot be a non-matching memory. */
16526 /* Improve address combine. */
16535 }
16537 /* Similarly, but assume that the destination has already been
16538 set up properly. */
16540 void
16543 {
16546 }
16548 /* Attempt to expand a binary operator. Make the expansion closer to the
16549 actual machine, then just general_operand, which will allow 3 separate
16550 memory references (one output, two input) in a single insn. */
16552 void
16554 rtx operands[])
16555 {
16562 /* Emit the instruction. */
16566 {
16567 /* Reload doesn't know about the flags register, and doesn't know that
16568 it doesn't want to clobber it. We can only do this with PLUS. */
16571 }
16575 {
16576 /* This is going to be an LEA; avoid splitting it later. */
16578 }
16579 else
16580 {
16583 }
16585 /* Fix up the destination if needed. */
16588 }
16590 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16591 the given OPERANDS. */
16593 void
16595 rtx operands[])
16596 {
16599 {
16602 }
16604 {
16607 }
16608 /* Optimize (__m128i) d | (__m128i) e and similar code
16609 when d and e are float vectors into float vector logical
16610 insn. In C/C++ without using intrinsics there is no other way
16611 to express vector logical operation on float vectors than
16612 to cast them temporarily to integer vectors. */
16614 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16623 {
16624 rtx dst;
16626 {
16633 {
16636 }
16637 else
16638 {
16643 }
16654 }
16655 }
16664 }
16666 /* Return TRUE or FALSE depending on whether the binary operator meets the
16667 appropriate constraints. */
16669 bool
16672 {
16677 /* Both source operands cannot be in memory. */
16681 /* Canonicalize operand order for commutative operators. */
16683 {
16687 }
16689 /* If the destination is memory, we must have a matching source operand. */
16693 /* Source 1 cannot be a constant. */
16697 /* Source 1 cannot be a non-matching memory. */
16699 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16707 }
16709 /* Attempt to expand a unary operator. Make the expansion closer to the
16710 actual machine, then just general_operand, which will allow 2 separate
16711 memory references (one output, one input) in a single insn. */
16713 void
16715 rtx operands[])
16716 {
16723 /* If the destination is memory, and we do not have matching source
16724 operands, do things in registers. */
16727 {
16730 else
16732 }
16734 /* When source operand is memory, destination must match. */
16738 /* Emit the instruction. */
16742 {
16743 /* Reload doesn't know about the flags register, and doesn't know that
16744 it doesn't want to clobber it. */
16747 }
16748 else
16749 {
16752 }
16754 /* Fix up the destination if needed. */
16757 }
16759 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16760 divisor are within the range [0-255]. */
16762 void
16765 {
16774 {
16787 }
16794 /* Use 8bit unsigned divimod if dividend and divisor are within
16795 the range [0-255]. */
16804 pc_rtx);
16809 /* Generate original signed/unsigned divimod. */
16814 /* Branch to the end. */
16818 /* Generate 8bit unsigned divide. */
16820 /* Don't use operands[0] for result of 8bit divide since not all
16821 registers support QImode ZERO_EXTRACT. */
16828 {
16831 }
16832 else
16833 {
16836 }
16838 /* Extract remainder from AH. */
16842 else
16843 {
16844 /* Need a new scratch register since the old one has result
16845 of 8bit divide. */
16849 }
16852 /* Zero extend quotient from AL. */
16858 }
16860 #define LEA_MAX_STALL (3)
16861 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16863 /* Increase given DISTANCE in half-cycles according to
16864 dependencies between PREV and NEXT instructions.
16865 Add 1 half-cycle if there is no dependency and
16866 go to next cycle if there is some dependecy. */
16868 static unsigned int
16870 {
16887 }
16889 /* Function checks if instruction INSN defines register number
16890 REGNO1 or REGNO2. */
16892 static bool
16894 rtx insn)
16895 {
16903 {
16905 }
16908 }
16910 /* Function checks if instruction INSN uses register number
16911 REGNO as a part of address expression. */
16913 static bool
16915 {
16923 }
16925 /* Search backward for non-agu definition of register number REGNO1
16926 or register number REGNO2 in basic block starting from instruction
16927 START up to head of basic block or instruction INSN.
16929 Function puts true value into *FOUND var if definition was found
16930 and false otherwise.
16932 Distance in half-cycles between START and found instruction or head
16933 of BB is added to DISTANCE and returned. */
16935 static int
16939 {
16949 {
16951 {
16954 {
16957 {
16960 }
16961 }
16964 }
16969 }
16972 }
16974 /* Search backward for non-agu definition of register number REGNO1
16975 or register number REGNO2 in INSN's basic block until
16976 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16977 2. Reach neighbour BBs boundary, or
16978 3. Reach agu definition.
16979 Returns the distance between the non-agu definition point and INSN.
16980 If no definition point, returns -1. */
16982 static int
16984 rtx insn)
16985 {
16996 {
16997 edge e;
16998 edge_iterator ei;
17003 {
17006 }
17012 else
17013 {
17018 {
17019 int bb_dist
17025 {
17032 }
17033 }
17036 }
17037 }
17039 /* get_attr_type may modify recog data. We want to make sure
17040 that recog data is valid for instruction INSN, on which
17041 distance_non_agu_define is called. INSN is unchanged here. */
17048 }
17050 /* Return the distance in half-cycles between INSN and the next
17051 insn that uses register number REGNO in memory address added
17052 to DISTANCE. Return -1 if REGNO0 is set.
17054 Put true value into *FOUND if register usage was found and
17055 false otherwise.
17056 Put true value into *REDEFINED if register redefinition was
17057 found and false otherwise. */
17059 static int
17063 {
17074 {
17076 {
17079 {
17080 /* Return DISTANCE if OP0 is used in memory
17081 address in NEXT. */
17084 }
17087 {
17088 /* Return -1 if OP0 is set in NEXT. */
17091 }
17094 }
17100 }
17103 }
17105 /* Return the distance between INSN and the next insn that uses
17106 register number REGNO0 in memory address. Return -1 if no such
17107 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17109 static int
17111 {
17123 {
17124 edge e;
17125 edge_iterator ei;
17130 {
17133 }
17139 else
17140 {
17146 {
17147 int bb_dist
17152 {
17159 }
17160 }
17163 }
17164 }
17170 }
17172 /* Define this macro to tune LEA priority vs ADD, it take effect when
17173 there is a dilemma of choicing LEA or ADD
17174 Negative value: ADD is more preferred than LEA
17175 Zero: Netrual
17176 Positive value: LEA is more preferred than ADD*/
17177 #define IX86_LEA_PRIORITY 0
17179 /* Return true if usage of lea INSN has performance advantage
17180 over a sequence of instructions. Instructions sequence has
17181 SPLIT_COST cycles higher latency than lea latency. */
17183 static bool
17186 {
17193 {
17194 /* If there is no non AGU operand definition, no AGU
17195 operand usage and split cost is 0 then both lea
17196 and non lea variants have same priority. Currently
17197 we prefer lea for 64 bit code and non lea on 32 bit
17198 code. */
17201 else
17203 }
17205 /* With longer definitions distance lea is more preferable.
17206 Here we change it to take into account splitting cost and
17207 lea priority. */
17210 /* If there is no use in memory addess then we just check
17211 that split cost exceeds AGU stall. */
17215 /* If this insn has both backward non-agu dependence and forward
17216 agu dependence, the one with short distance takes effect. */
17218 }
17220 /* Return true if it is legal to clobber flags by INSN and
17221 false otherwise. */
17223 static bool
17225 {
17228 bitmap live;
17231 {
17233 {
17240 }
17246 }
17250 }
17252 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17253 move and add to avoid AGU stalls. */
17255 bool
17257 {
17260 /* Check if we need to optimize. */
17264 /* Check it is correct to split here. */
17272 /* We need to split only adds with non destructive
17273 destination operand. */
17276 else
17278 }
17280 /* Return true if we should emit lea instruction instead of mov
17281 instruction. */
17283 bool
17285 {
17288 /* Check if we need to optimize. */
17292 /* Use lea for reg to reg moves only. */
17300 }
17302 /* Return true if we need to split lea into a sequence of
17303 instructions to avoid AGU stalls. */
17305 bool
17307 {
17313 /* Check we need to optimize. */
17317 /* Check it is correct to split here. */
17324 /* There should be at least two components in the address. */
17329 /* We should not split into add if non legitimate pic
17330 operand is used as displacement. */
17345 /* Compute how many cycles we will add to execution time
17346 if split lea into a sequence of instructions. */
17348 {
17349 /* Have to use mov instruction if non desctructive
17350 destination form is used. */
17354 /* Have to add index to base if both exist. */
17358 /* Have to use shift and adds if scale is 2 or greater. */
17360 {
17365 else
17367 }
17369 /* Have to use add instruction with immediate if
17370 disp is non zero. */
17374 /* Subtract the price of lea. */
17376 }
17379 }
17381 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17382 matches destination. RTX includes clobber of FLAGS_REG. */
17384 static void
17387 {
17394 }
17396 /* Return true if regno1 def is nearest to the insn. */
17398 static bool
17400 {
17407 {
17409 {
17412 }
17418 }
17420 /* None of the regs is defined in the bb. */
17422 }
17424 /* Split lea instructions into a sequence of instructions
17425 which are executed on ALU to avoid AGU stalls.
17426 It is assumed that it is allowed to clobber flags register
17427 at lea position. */
17429 void
17431 {
17447 {
17450 }
17453 {
17456 }
17462 {
17463 /* Case r1 = r1 + ... */
17465 {
17466 /* If we have a case r1 = r1 + C * r1 then we
17467 should use multiplication which is very
17468 expensive. Assume cost model is wrong if we
17469 have such case here. */
17474 }
17475 else
17476 {
17477 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17481 /* Use shift for scaling. */
17490 }
17491 }
17493 {
17496 }
17497 else
17498 {
17500 {
17503 }
17505 {
17508 }
17509 else
17510 {
17515 else
17516 {
17517 rtx tmp1;
17519 /* Find better operand for SET instruction, depending
17520 on which definition is farther from the insn. */
17523 else
17533 }
17536 }
17540 }
17541 }
17543 /* Return true if it is ok to optimize an ADD operation to LEA
17544 operation to avoid flag register consumation. For most processors,
17545 ADD is faster than LEA. For the processors like ATOM, if the
17546 destination register of LEA holds an actual address which will be
17547 used soon, LEA is better and otherwise ADD is better. */
17549 bool
17551 {
17556 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17564 }
17566 /* Return true if destination reg of SET_BODY is shift count of
17567 USE_BODY. */
17569 static bool
17571 {
17572 rtx set_dest;
17573 rtx shift_rtx;
17576 /* Retrieve destination of SET_BODY. */
17578 {
17587 use_body))
17592 }
17594 /* Retrieve shift count of USE_BODY. */
17596 {
17608 }
17616 {
17619 /* Return true if shift count is dest of SET_BODY. */
17621 {
17622 /* Add check since it can be invoked before register
17623 allocation in pre-reload schedule. */
17629 }
17630 }
17633 }
17635 /* Return true if destination reg of SET_INSN is shift count of
17636 USE_INSN. */
17638 bool
17640 {
17643 }
17645 /* Return TRUE or FALSE depending on whether the unary operator meets the
17646 appropriate constraints. */
17648 bool
17652 {
17653 /* If one of operands is memory, source and destination must match. */
17659 }
17661 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17662 are ok, keeping in mind the possible movddup alternative. */
17664 bool
17666 {
17672 }
17674 /* Post-reload splitter for converting an SF or DFmode value in an
17675 SSE register into an unsigned SImode. */
17677 void
17679 {
17690 /* Load up the value into the low element. We must ensure that the other
17691 elements are valid floats -- zero is the easiest such value. */
17693 {
17696 else
17698 }
17699 else
17700 {
17705 else
17707 }
17727 else
17732 }
17734 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17735 Expects the 64-bit DImode to be supplied in a pair of integral
17736 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17737 -mfpmath=sse, !optimize_size only. */
17739 void
17741 {
17745 rtx x;
17751 {
17754 }
17755 else
17756 {
17760 }
17768 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17771 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17772 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17773 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17774 (0x1.0p84 + double(fp_value_hi_xmm)).
17775 Note these exponents differ by 32. */
17779 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17780 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17789 /* Add the upper and lower DFmode values together. */
17792 else
17793 {
17797 }
17800 }
17802 /* Not used, but eases macroization of patterns. */
17803 void
17805 rtx input ATTRIBUTE_UNUSED)
17806 {
17808 }
17810 /* Convert an unsigned SImode value into a DFmode. Only currently used
17811 for SSE, but applicable anywhere. */
17813 void
17815 {
17816 REAL_VALUE_TYPE TWO31r;
17831 }
17833 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17834 32-bit mode; otherwise we have a direct convert instruction. */
17836 void
17838 {
17839 REAL_VALUE_TYPE TWO32r;
17857 }
17859 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17860 For x86_32, -mfpmath=sse, !optimize_size only. */
17861 void
17863 {
17864 REAL_VALUE_TYPE ONE16r;
17883 }
17885 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17886 a vector of unsigned ints VAL to vector of floats TARGET. */
17888 void
17890 {
17892 REAL_VALUE_TYPE TWO16r;
17899 else
17904 OPTAB_DIRECT);
17915 OPTAB_DIRECT);
17917 OPTAB_DIRECT);
17920 }
17922 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17923 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17924 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17925 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17927 rtx
17929 {
17930 REAL_VALUE_TYPE TWO31r;
17945 {
17951 }
17960 OPTAB_DIRECT);
17961 else
17962 {
17968 OPTAB_DIRECT);
17969 }
17972 }
17974 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17975 then replicate the value for all elements of the vector
17976 register. */
17978 rtx
17980 {
17982 rtvec v;
17986 {
18013 }
18014 }
18016 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18017 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18018 for an SSE register. If VECT is true, then replicate the mask for
18019 all elements of the vector register. If INVERT is true, then create
18020 a mask excluding the sign bit. */
18022 rtx
18024 {
18028 rtx v;
18029 rtx mask;
18031 /* Find the sign bit, sign extended to 2*HWI. */
18033 {
18053 else
18061 {
18064 }
18065 else
18066 {
18067 rtvec vec;
18073 {
18076 }
18077 else
18087 }
18092 }
18097 /* Force this value into the low part of a fp vector constant. */
18106 }
18108 /* Generate code for floating point ABS or NEG. */
18110 void
18112 rtx operands[])
18113 {
18124 {
18130 }
18132 /* NEG and ABS performed with SSE use bitwise mask operations.
18133 Create the appropriate mask now. */
18136 else
18146 {
18148 rtvec par;
18153 else
18154 {
18157 }
18159 }
18160 else
18162 }
18164 /* Expand a copysign operation. Special case operand 0 being a constant. */
18166 void
18168 {
18182 else
18186 {
18193 {
18196 else
18197 {
18201 }
18202 }
18212 else
18216 }
18217 else
18218 {
18228 else
18232 }
18233 }
18235 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18236 be a constant, and so has already been expanded into a vector constant. */
18238 void
18240 {
18256 {
18259 }
18260 }
18262 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18263 so we have to do two masks. */
18265 void
18267 {
18282 {
18283 /* Shouldn't happen often (it's useless, obviously), but when it does
18284 we'd generate incorrect code if we continue below. */
18287 }
18290 {
18301 }
18302 else
18303 {
18305 {
18307 }
18309 {
18313 }
18317 {
18320 }
18322 {
18327 }
18329 }
18333 }
18335 /* Return TRUE or FALSE depending on whether the first SET in INSN
18336 has source and destination with matching CC modes, and that the
18337 CC mode is at least as constrained as REQ_MODE. */
18339 bool
18341 {
18342 rtx set;
18353 {
18363 /* FALLTHRU */
18367 /* FALLTHRU */
18371 /* FALLTHRU */
18385 }
18388 }
18390 /* Generate insn patterns to do an integer compare of OPERANDS. */
18392 static rtx
18394 {
18401 /* This is very simple, but making the interface the same as in the
18402 FP case makes the rest of the code easier. */
18406 /* Return the test that should be put into the flags user, i.e.
18407 the bcc, scc, or cmov instruction. */
18409 }
18411 /* Figure out whether to use ordered or unordered fp comparisons.
18412 Return the appropriate mode to use. */
18414 enum machine_mode
18416 {
18417 /* ??? In order to make all comparisons reversible, we do all comparisons
18418 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18419 all forms trapping and nontrapping comparisons, we can make inequality
18420 comparisons trapping again, since it results in better code when using
18421 FCOM based compares. */
18423 }
18425 enum machine_mode
18427 {
18431 {
18434 }
18437 {
18438 /* Only zero flag is needed. */
18442 /* Codes needing carry flag. */
18445 /* Detect overflow checks. They need just the carry flag. */
18449 else
18453 /* Detect overflow checks. They need just the carry flag. */
18457 else
18459 /* Codes possibly doable only with sign flag when
18460 comparing against zero. */
18465 else
18466 /* For other cases Carry flag is not required. */
18468 /* Codes doable only with sign flag when comparing
18469 against zero, but we miss jump instruction for it
18470 so we need to use relational tests against overflow
18471 that thus needs to be zero. */
18476 else
18478 /* strcmp pattern do (use flags) and combine may ask us for proper
18479 mode. */
18484 }
18485 }
18487 /* Return the fixed registers used for condition codes. */
18489 static bool
18491 {
18495 }
18497 /* If two condition code modes are compatible, return a condition code
18498 mode which is compatible with both. Otherwise, return
18499 VOIDmode. */
18501 static enum machine_mode
18503 {
18520 {
18534 {
18548 }
18552 /* These are only compatible with themselves, which we already
18553 checked above. */
18555 }
18556 }
18559 /* Return a comparison we can do and that it is equivalent to
18560 swap_condition (code) apart possibly from orderedness.
18561 But, never change orderedness if TARGET_IEEE_FP, returning
18562 UNKNOWN in that case if necessary. */
18564 static enum rtx_code
18566 {
18568 {
18579 }
18580 }
18582 /* Return cost of comparison CODE using the best strategy for performance.
18583 All following functions do use number of instructions as a cost metrics.
18584 In future this should be tweaked to compute bytes for optimize_size and
18585 take into account performance of various instructions on various CPUs. */
18587 static int
18589 {
18592 /* The cost of code using bit-twiddling on %ah. */
18594 {
18617 }
18620 {
18627 }
18628 }
18630 /* Return strategy to use for floating-point. We assume that fcomi is always
18631 preferrable where available, since that is also true when looking at size
18632 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18634 enum ix86_fpcmp_strategy
18636 {
18637 /* Do fcomi/sahf based test when profitable. */
18646 }
18648 /* Swap, force into registers, or otherwise massage the two operands
18649 to a fp comparison. The operands are updated in place; the new
18650 comparison code is returned. */
18652 static enum rtx_code
18654 {
18660 /* All of the unordered compare instructions only work on registers.
18661 The same is true of the fcomi compare instructions. The XFmode
18662 compare instructions require registers except when comparing
18663 against zero or when converting operand 1 from fixed point to
18664 floating point. */
18673 {
18676 }
18677 else
18678 {
18679 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18680 things around if they appear profitable, otherwise force op0
18681 into a register. */
18687 {
18690 {
18691 rtx tmp;
18694 }
18695 }
18701 {
18706 {
18709 }
18710 else
18712 }
18713 }
18715 /* Try to rearrange the comparison to make it cheaper. */
18719 {
18720 rtx tmp;
18725 }
18730 }
18732 /* Convert comparison codes we use to represent FP comparison to integer
18733 code that will result in proper branch. Return UNKNOWN if no such code
18734 is available. */
18736 enum rtx_code
18738 {
18740 {
18763 }
18764 }
18766 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18768 static rtx
18770 {
18777 /* Do fcomi/sahf based test when profitable. */
18779 {
18784 tmp);
18792 tmp);
18801 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18808 /* In the unordered case, we have to check C2 for NaN's, which
18809 doesn't happen to work out to anything nice combination-wise.
18810 So do some bit twiddling on the value we've got in AH to come
18811 up with an appropriate set of condition codes. */
18815 {
18819 {
18822 }
18823 else
18824 {
18830 }
18835 {
18840 }
18841 else
18842 {
18845 }
18850 {
18853 }
18854 else
18855 {
18859 }
18864 {
18870 }
18871 else
18872 {
18875 }
18880 {
18885 }
18886 else
18887 {
18890 }
18895 {
18900 }
18901 else
18902 {
18905 }
18919 }
18924 }
18926 /* Return the test that should be put into the flags user, i.e.
18927 the bcc, scc, or cmov instruction. */
18930 const0_rtx);
18931 }
18933 static rtx
18935 {
18936 rtx ret;
18942 {
18945 }
18946 else
18950 }
18952 void
18954 {
18956 rtx tmp;
18959 {
18966 simple:
18970 pc_rtx);
18978 /* Expand DImode branch into multiple compare+branch. */
18979 {
18985 {
18988 }
18995 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18996 avoid two branches. This costs one extra insn, so disable when
18997 optimizing for size. */
19002 {
19020 }
19022 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19023 op1 is a constant and the low word is zero, then we can just
19024 examine the high word. Similarly for low word -1 and
19025 less-or-equal-than or greater-than. */
19029 {
19032 {
19035 }
19039 {
19042 }
19046 }
19048 /* Otherwise, we need two or three jumps. */
19057 {
19071 }
19073 /*
19074 * a < b =>
19075 * if (hi(a) < hi(b)) goto true;
19076 * if (hi(a) > hi(b)) goto false;
19077 * if (lo(a) < lo(b)) goto true;
19078 * false:
19079 */
19091 }
19096 }
19097 }
19099 /* Split branch based on floating point condition. */
19100 void
19103 {
19104 rtx condition;
19105 rtx i;
19108 {
19113 }
19116 tmp);
19118 /* Remove pushed operand from stack. */
19128 }
19130 void
19132 {
19133 rtx ret;
19140 }
19142 /* Expand comparison setting or clearing carry flag. Return true when
19143 successful and set pop for the operation. */
19144 static bool
19146 {
19150 /* Do not handle double-mode compares that go through special path. */
19155 {
19160 /* Shortcut: following common codes never translate
19161 into carry flag compares. */
19166 /* These comparisons require zero flag; swap operands so they won't. */
19169 {
19174 }
19176 /* Try to expand the comparison and verify that we end up with
19177 carry flag based comparison. This fails to be true only when
19178 we decide to expand comparison using arithmetic that is not
19179 too common scenario. */
19188 else
19197 }
19203 {
19208 /* Convert a==0 into (unsigned)a<1. */
19217 /* Convert a>b into b<a or a>=b-1. */
19221 {
19223 /* Bail out on overflow. We still can swap operands but that
19224 would force loading of the constant into register. */
19229 }
19230 else
19231 {
19236 }
19239 /* Convert a>=0 into (unsigned)a<0x80000000. */
19257 }
19258 /* Swapping operands may cause constant to appear as first operand. */
19260 {
19264 }
19268 }
19270 bool
19272 {
19296 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19297 HImode insns, we'd be swallowed in word prefix ops. */
19303 {
19307 HOST_WIDE_INT diff;
19310 /* Sign bit compares are better done using shifts than we do by using
19311 sbb. */
19314 {
19315 /* Detect overlap between destination and compare sources. */
19319 {
19320 rtx flags;
19329 {
19331 compare_code
19333 }
19335 /* To simplify rest of code, restrict to the GEU case. */
19337 {
19343 }
19344 else
19345 {
19348 reverse_condition_maybe_unordered
19350 else
19353 }
19362 else
19365 }
19366 else
19367 {
19370 else
19371 {
19376 }
19378 }
19381 {
19382 /*
19383 * cmpl op0,op1
19384 * sbbl dest,dest
19385 * [addl dest, ct]
19386 *
19387 * Size 5 - 8.
19388 */
19393 }
19395 {
19396 /*
19397 * cmpl op0,op1
19398 * sbbl dest,dest
19399 * orl $ct, dest
19400 *
19401 * Size 8.
19402 */
19406 }
19408 {
19409 /*
19410 * cmpl op0,op1
19411 * sbbl dest,dest
19412 * notl dest
19413 * [addl dest, cf]
19414 *
19415 * Size 8 - 11.
19416 */
19422 }
19423 else
19424 {
19425 /*
19426 * cmpl op0,op1
19427 * sbbl dest,dest
19428 * [notl dest]
19429 * andl cf - ct, dest
19430 * [addl dest, ct]
19431 *
19432 * Size 8 - 11.
19433 */
19436 {
19440 }
19450 }
19456 }
19459 {
19462 HOST_WIDE_INT tmp;
19467 {
19470 /* We may be reversing unordered compare to normal compare, that
19471 is not valid in general (we may convert non-trapping condition
19472 to trapping one), however on i386 we currently emit all
19473 comparisons unordered. */
19476 }
19477 else
19478 {
19481 }
19482 }
19487 {
19492 {
19497 }
19498 }
19500 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19504 {
19505 /* If lea code below could be used, only optimize
19506 if it results in a 2 insn sequence. */
19512 {
19513 /*
19514 * notl op1 (if necessary)
19515 * sarl $31, op1
19516 * orl cf, op1
19517 */
19519 {
19523 }
19534 }
19535 }
19543 {
19544 /*
19545 * xorl dest,dest
19546 * cmpl op1,op2
19547 * setcc dest
19548 * lea cf(dest*(ct-cf)),dest
19549 *
19550 * Size 14.
19551 *
19552 * This also catches the degenerate setcc-only case.
19553 */
19555 rtx tmp;
19561 /* On x86_64 the lea instruction operates on Pmode, so we need
19562 to get arithmetics done in proper mode to match. */
19565 else
19566 {
19567 rtx out1;
19570 nops++;
19572 {
19574 nops++;
19575 }
19576 }
19578 {
19580 nops++;
19581 }
19583 {
19586 else
19588 }
19593 }
19595 /*
19596 * General case: Jumpful:
19597 * xorl dest,dest cmpl op1, op2
19598 * cmpl op1, op2 movl ct, dest
19599 * setcc dest jcc 1f
19600 * decl dest movl cf, dest
19601 * andl (cf-ct),dest 1:
19602 * addl ct,dest
19603 *
19604 * Size 20. Size 14.
19605 *
19606 * This is reasonably steep, but branch mispredict costs are
19607 * high on modern cpus, so consider failing only if optimizing
19608 * for space.
19609 */
19614 {
19616 {
19623 {
19626 /* We may be reversing unordered compare to normal compare,
19627 that is not valid in general (we may convert non-trapping
19628 condition to trapping one), however on i386 we currently
19629 emit all comparisons unordered. */
19631 }
19632 else
19633 {
19637 }
19638 }
19641 {
19642 /* notl op1 (if needed)
19643 sarl $31, op1
19644 andl (cf-ct), op1
19645 addl ct, op1
19647 For x < 0 (resp. x <= -1) there will be no notl,
19648 so if possible swap the constants to get rid of the
19649 complement.
19650 True/false will be -1/0 while code below (store flag
19651 followed by decrement) is 0/-1, so the constants need
19652 to be exchanged once more. */
19655 {
19658 }
19659 else
19660 {
19664 }
19667 }
19668 else
19669 {
19673 constm1_rtx,
19675 }
19687 }
19688 }
19691 {
19692 /* Try a few things more with specific constants and a variable. */
19694 optab op;
19700 /* If one of the two operands is an interesting constant, load a
19701 constant with the above and mask it in with a logical operation. */
19704 {
19710 else
19712 }
19714 {
19720 else
19722 }
19723 else
19730 /* Recurse to get the constant loaded. */
19734 /* Mask in the interesting variable. */
19736 OPTAB_WIDEN);
19741 }
19743 /*
19744 * For comparison with above,
19745 *
19746 * movl cf,dest
19747 * movl ct,tmp
19748 * cmpl op1,op2
19749 * cmovcc tmp,dest
19750 *
19751 * Size 15.
19752 */
19774 }
19776 /* Swap, force into registers, or otherwise massage the two operands
19777 to an sse comparison with a mask result. Thus we differ a bit from
19778 ix86_prepare_fp_compare_args which expects to produce a flags result.
19780 The DEST operand exists to help determine whether to commute commutative
19781 operators. The POP0/POP1 operands are updated in place. The new
19782 comparison code is returned, or UNKNOWN if not implementable. */
19784 static enum rtx_code
19787 {
19788 rtx tmp;
19791 {
19794 /* AVX supports all the needed comparisons. */
19797 /* We have no LTGT as an operator. We could implement it with
19798 NE & ORDERED, but this requires an extra temporary. It's
19799 not clear that it's worth it. */
19806 /* These are supported directly. */
19813 /* AVX has 3 operand comparisons, no need to swap anything. */
19816 /* For commutative operators, try to canonicalize the destination
19817 operand to be first in the comparison - this helps reload to
19818 avoid extra moves. */
19821 /* FALLTHRU */
19827 /* These are not supported directly before AVX, and furthermore
19828 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19829 comparison operands to transform into something that is
19830 supported. */
19839 }
19842 }
19844 /* Detect conditional moves that exactly match min/max operational
19845 semantics. Note that this is IEEE safe, as long as we don't
19846 interchange the operands.
19848 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19849 and TRUE if the operation is successful and instructions are emitted. */
19851 static bool
19854 {
19857 rtx tmp;
19860 ;
19862 {
19866 }
19867 else
19874 else
19879 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19880 but MODE may be a vector mode and thus not appropriate. */
19882 {
19884 rtvec v;
19889 }
19890 else
19891 {
19894 }
19898 }
19900 /* Expand an sse vector comparison. Return the register with the result. */
19902 static rtx
19905 {
19908 rtx x;
19921 {
19924 }
19925 else
19929 }
19931 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19932 operations. This is used for both scalar and vector conditional moves. */
19934 static void
19936 {
19942 {
19944 }
19946 {
19950 }
19952 {
19957 }
19959 {
19963 }
19965 {
19973 op_true,
19974 op_false)));
19975 }
19976 else
19977 {
19986 {
20000 {
20006 }
20021 {
20027 }
20031 }
20035 else
20036 {
20042 else
20054 }
20055 }
20056 }
20058 /* Expand a floating-point conditional move. Return true if successful. */
20060 bool
20062 {
20070 {
20073 /* Since we've no cmove for sse registers, don't force bad register
20074 allocation just to gain access to it. Deny movcc when the
20075 comparison mode doesn't match the move mode. */
20094 }
20101 /* The floating point conditional move instructions don't directly
20102 support conditions resulting from a signed integer comparison. */
20106 {
20111 }
20118 }
20120 /* Expand a floating-point vector conditional move; a vcond operation
20121 rather than a movcc operation. */
20123 bool
20125 {
20127 rtx cmp;
20132 {
20133 rtx temp;
20135 {
20152 }
20154 OPTAB_DIRECT);
20157 }
20167 }
20169 /* Expand a signed/unsigned integral vector conditional move. */
20171 bool
20173 {
20183 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20184 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20193 {
20197 {
20203 }
20206 {
20212 }
20213 }
20222 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20226 ;
20227 else
20228 {
20229 /* Canonicalize the comparison to EQ, GT, GTU. */
20231 {
20248 /* FALLTHRU */
20258 }
20260 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20262 {
20264 {
20266 /* SSE4.1 supports EQ. */
20273 /* SSE4.2 supports GT/GTU. */
20280 }
20281 }
20283 /* Unsigned parallel compare is not supported by the hardware.
20284 Play some tricks to turn this into a signed comparison
20285 against 0. */
20287 {
20291 {
20296 {
20301 {
20308 }
20309 /* Subtract (-(INT MAX) - 1) from both operands to make
20310 them signed. */
20321 }
20328 /* Perform a parallel unsigned saturating subtraction. */
20341 }
20342 }
20343 }
20345 /* Allow the comparison to be done in one mode, but the movcc to
20346 happen in another mode. */
20348 {
20351 }
20352 else
20353 {
20359 }
20364 }
20366 /* Expand a variable vector permutation. */
20368 void
20370 {
20381 /* Number of elements in the vector. */
20387 {
20389 {
20390 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20391 an constant shuffle operand. With a tiny bit of effort we can
20392 use VPERMD instead. A re-interpretation stall for V4DFmode is
20393 unfortunate but there's no avoiding it.
20394 Similarly for V16HImode we don't have instructions for variable
20395 shuffling, while for V32QImode we can use after preparing suitable
20396 masks vpshufb; vpshufb; vpermq; vpor. */
20399 {
20403 }
20404 else
20405 {
20409 }
20412 /* Replicate the low bits of the V4DImode mask into V8SImode:
20413 mask = { A B C D }
20414 t1 = { A A B B C C D D }. */
20422 else
20425 /* Multiply the shuffle indicies by two. */
20427 OPTAB_DIRECT);
20429 /* Add one to the odd shuffle indicies:
20430 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20432 {
20435 }
20439 OPTAB_DIRECT);
20441 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20446 }
20449 {
20451 /* The VPERMD and VPERMPS instructions already properly ignore
20452 the high bits of the shuffle elements. No need for us to
20453 perform an AND ourselves. */
20456 else
20457 {
20463 }
20470 else
20471 {
20477 }
20481 /* By combining the two 128-bit input vectors into one 256-bit
20482 input vector, we can use VPERMD and VPERMPS for the full
20483 two-operand shuffle. */
20515 /* From mask create two adjusted masks, which contain the same
20516 bits as mask in the low 7 bits of each vector element.
20517 The first mask will have the most significant bit clear
20518 if it requests element from the same 128-bit lane
20519 and MSB set if it requests element from the other 128-bit lane.
20520 The second mask will have the opposite values of the MSB,
20521 and additionally will have its 128-bit lanes swapped.
20522 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20523 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20524 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20525 stands for other 12 bytes. */
20526 /* The bit whether element is from the same lane or the other
20527 lane is bit 4, so shift it up by 3 to the MSB position. */
20531 /* Clear MSB bits from the mask just in case it had them set. */
20533 /* After this t1 will have MSB set for elements from other lane. */
20535 /* Clear bits other than MSB. */
20537 /* Or in the lower bits from mask into t3. */
20539 /* And invert MSB bits in t1, so MSB is set for elements from the same
20540 lane. */
20542 /* Swap 128-bit lanes in t3. */
20547 /* And or in the lower bits from mask into t1. */
20550 {
20551 /* Each of these shuffles will put 0s in places where
20552 element from the other 128-bit lane is needed, otherwise
20553 will shuffle in the requested value. */
20556 /* For t3 the 128-bit lanes are swapped again. */
20561 /* And oring both together leads to the result. */
20564 }
20567 /* Similarly to the above one_operand_shuffle code,
20568 just for repeated twice for each operand. merge_two:
20569 code will merge the two results together. */
20591 }
20592 }
20595 {
20596 /* The XOP VPPERM insn supports three inputs. By ignoring the
20597 one_operand_shuffle special case, we avoid creating another
20598 set of constant vectors in memory. */
20601 /* mask = mask & {2*w-1, ...} */
20603 }
20604 else
20605 {
20606 /* mask = mask & {w-1, ...} */
20608 }
20616 /* For non-QImode operations, convert the word permutation control
20617 into a byte permutation control. */
20619 {
20624 /* Convert mask to vector of chars. */
20627 /* Replicate each of the input bytes into byte positions:
20628 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20629 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20630 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20637 else
20640 /* Convert it into the byte positions by doing
20641 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20647 }
20649 /* The actual shuffle operations all operate on V16QImode. */
20655 {
20657 }
20659 {
20661 }
20662 else
20663 {
20667 /* Shuffle the two input vectors independently. */
20673 merge_two:
20674 /* Then merge them together. The key is whether any given control
20675 element contained a bit set that indicates the second word. */
20679 {
20680 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20681 more shuffle to convert the V2DI input mask into a V4SI
20682 input mask. At which point the masking that expand_int_vcond
20683 will work as desired. */
20691 }
20708 }
20709 }
20711 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20712 true if we should do zero extension, else sign extension. HIGH_P is
20713 true if we want the N/2 high elements, else the low elements. */
20715 void
20717 {
20719 rtx tmp;
20722 {
20728 {
20732 else
20735 extract
20741 else
20744 extract
20750 else
20753 extract
20759 else
20765 else
20771 else
20776 }
20779 {
20782 }
20784 {
20785 /* Shift higher 8 bytes to lower 8 bytes. */
20790 }
20791 else
20795 }
20796 else
20797 {
20801 {
20805 else
20811 else
20817 else
20822 }
20826 else
20831 }
20832 }
20834 /* Expand conditional increment or decrement using adb/sbb instructions.
20835 The default case using setcc followed by the conditional move can be
20836 done by generic code. */
20837 bool
20839 {
20841 rtx flags;
20843 rtx compare_op;
20861 {
20864 }
20867 {
20871 reverse_condition_maybe_unordered
20873 else
20875 }
20879 /* Construct either adc or sbb insn. */
20881 {
20883 {
20898 }
20899 }
20900 else
20901 {
20903 {
20918 }
20919 }
20923 }
20926 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20927 but works for floating pointer parameters and nonoffsetable memories.
20928 For pushes, it returns just stack offsets; the values will be saved
20929 in the right order. Maximally three parts are generated. */
20931 static int
20933 {
20938 else
20944 /* Optimize constant pool reference to immediates. This is used by fp
20945 moves, that force all constants to memory to allow combining. */
20947 {
20951 }
20954 {
20955 /* The only non-offsetable memories we handle are pushes. */
20964 }
20967 {
20969 /* Caution: if we looked through a constant pool memory above,
20970 the operand may actually have a different mode now. That's
20971 ok, since we want to pun this all the way back to an integer. */
20975 }
20978 {
20981 else
20982 {
20986 {
20990 }
20992 {
20997 }
20999 {
21000 REAL_VALUE_TYPE r;
21005 {
21012 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21013 long double may not be 80-bit. */
21022 }
21025 }
21026 else
21028 }
21029 }
21030 else
21031 {
21035 {
21038 {
21042 }
21044 {
21048 }
21050 {
21051 REAL_VALUE_TYPE r;
21057 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21060 = gen_int_mode
21063 DImode);
21064 else
21071 = gen_int_mode
21074 DImode);
21075 else
21077 }
21078 else
21080 }
21081 }
21084 }
21086 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21087 Return false when normal moves are needed; true when all required
21088 insns have been emitted. Operands 2-4 contain the input values
21089 int the correct order; operands 5-7 contain the output values. */
21091 void
21093 {
21101 /* The DFmode expanders may ask us to move double.
21102 For 64bit target this is single move. By hiding the fact
21103 here we simplify i386.md splitters. */
21105 {
21106 /* Optimize constant pool reference to immediates. This is used by
21107 fp moves, that force all constants to memory to allow combining. */
21114 {
21117 }
21118 else
21123 }
21125 /* The only non-offsettable memory we handle is push. */
21128 else
21135 /* When emitting push, take care for source operands on the stack. */
21138 {
21141 /* Compensate for the stack decrement by 4. */
21146 /* src_base refers to the stack pointer and is
21147 automatically decreased by emitted push. */
21151 }
21153 /* We need to do copy in the right order in case an address register
21154 of the source overlaps the destination. */
21156 {
21157 rtx tmp;
21160 {
21164 collisions++;
21165 }
21167 /* Collision in the middle part can be handled by reordering. */
21169 {
21172 }
21176 {
21178 {
21181 }
21182 else
21183 {
21186 }
21187 }
21189 /* If there are more collisions, we can't handle it by reordering.
21190 Do an lea to the last part and use only one colliding move. */
21192 {
21193 rtx base;
21199 /* Handle the case when the last part isn't valid for lea.
21200 Happens in 64-bit mode storing the 12-byte XFmode. */
21207 {
21210 }
21211 }
21212 }
21215 {
21217 {
21219 {
21224 }
21226 {
21229 }
21230 }
21231 else
21232 {
21233 /* In 64bit mode we don't have 32bit push available. In case this is
21234 register, it is OK - we will just use larger counterpart. We also
21235 retype memory - these comes from attempt to avoid REX prefix on
21236 moving of second half of TFmode value. */
21238 {
21240 {
21251 }
21255 }
21256 }
21260 }
21262 /* Choose correct order to not overwrite the source before it is copied. */
21272 {
21274 {
21277 }
21278 }
21279 else
21280 {
21282 {
21285 }
21286 }
21288 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21290 {
21299 }
21305 }
21307 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21308 left shift by a constant, either using a single shift or
21309 a sequence of add instructions. */
21311 static void
21313 {
21319 {
21323 }
21324 else
21325 {
21328 }
21329 }
21331 void
21333 {
21342 {
21347 {
21353 }
21354 else
21355 {
21363 }
21365 }
21372 {
21373 /* Assuming we've chosen a QImode capable registers, then 1 << N
21374 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21376 {
21392 }
21394 /* Otherwise, we can get the same results by manually performing
21395 a bit extract operation on bit 5/6, and then performing the two
21396 shifts. The two methods of getting 0/1 into low/high are exactly
21397 the same size. Avoiding the shift in the bit extract case helps
21398 pentium4 a bit; no one else seems to care much either way. */
21399 else
21400 {
21405 HOST_WIDE_INT bits;
21406 rtx x;
21409 {
21415 }
21416 else
21417 {
21423 }
21427 else
21435 }
21440 }
21443 {
21444 /* For -1 << N, we can avoid the shld instruction, because we
21445 know that we're shifting 0...31/63 ones into a -1. */
21449 else
21451 }
21452 else
21453 {
21461 }
21466 {
21472 }
21473 else
21474 {
21479 }
21480 }
21482 void
21484 {
21494 {
21499 {
21505 }
21507 {
21516 }
21517 else
21518 {
21526 }
21527 }
21528 else
21529 {
21541 {
21549 scratch));
21550 }
21551 else
21552 {
21557 }
21558 }
21559 }
21561 void
21563 {
21573 {
21578 {
21585 }
21586 else
21587 {
21595 }
21596 }
21597 else
21598 {
21610 {
21616 scratch));
21617 }
21618 else
21619 {
21624 }
21625 }
21626 }
21628 /* Predict just emitted jump instruction to be taken with probability PROB. */
21629 static void
21631 {
21635 }
21637 /* Helper function for the string operations below. Dest VARIABLE whether
21638 it is aligned to VALUE bytes. If true, jump to the label. */
21639 static rtx
21641 {
21646 else
21652 else
21655 }
21657 /* Adjust COUNTER by the VALUE. */
21658 static void
21660 {
21665 }
21667 /* Zero extend possibly SImode EXP to Pmode register. */
21668 rtx
21670 {
21672 }
21674 /* Divide COUNTREG by SCALE. */
21675 static rtx
21677 {
21678 rtx sc;
21690 }
21692 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21693 DImode for constant loop counts. */
21695 static enum machine_mode
21697 {
21705 }
21707 /* When SRCPTR is non-NULL, output simple loop to move memory
21708 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21709 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21710 equivalent loop to set memory by VALUE (supposed to be in MODE).
21712 The size is rounded down to whole number of chunk size moved at once.
21713 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21716 static void
21721 {
21726 rtx size;
21727 rtx x_addr;
21728 rtx y_addr;
21737 /* Those two should combine. */
21739 {
21743 }
21753 {
21757 /* When unrolling for chips that reorder memory reads and writes,
21758 we can save registers by using single temporary.
21759 Also using 4 temporaries is overkill in 32bit mode. */
21761 {
21763 {
21765 {
21766 destmem =
21768 srcmem =
21770 }
21772 }
21773 }
21774 else
21775 {
21779 {
21782 {
21783 srcmem =
21785 }
21787 }
21789 {
21791 {
21792 destmem =
21794 }
21796 }
21797 }
21798 }
21799 else
21801 {
21803 destmem =
21806 }
21816 {
21822 else
21824 }
21825 else
21833 {
21838 }
21840 }
21842 /* Output "rep; mov" instruction.
21843 Arguments have same meaning as for previous function */
21844 static void
21847 rtx count,
21849 {
21850 rtx destexp;
21851 rtx srcexp;
21852 rtx countreg;
21853 HOST_WIDE_INT rounded_count;
21855 /* If the size is known, it is shorter to use rep movs. */
21866 {
21873 }
21874 else
21875 {
21878 }
21880 {
21887 }
21888 else
21889 {
21894 }
21897 }
21899 /* Output "rep; stos" instruction.
21900 Arguments have same meaning as for previous function */
21901 static void
21904 rtx orig_value)
21905 {
21906 rtx destexp;
21907 rtx countreg;
21908 HOST_WIDE_INT rounded_count;
21915 {
21919 }
21920 else
21923 {
21928 }
21932 }
21934 static void
21937 {
21941 }
21943 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21944 static void
21947 {
21950 {
21955 {
21957 {
21960 }
21961 else
21964 }
21966 {
21969 else
21970 {
21973 }
21975 }
21977 {
21980 }
21982 {
21985 }
21987 {
21990 }
21992 }
21994 {
22000 }
22002 /* When there are stringops, we can cheaply increase dest and src pointers.
22003 Otherwise we save code size by maintaining offset (zero is readily
22004 available from preceding rep operation) and using x86 addressing modes.
22005 */
22007 {
22009 {
22016 }
22018 {
22025 }
22027 {
22034 }
22035 }
22036 else
22037 {
22039 rtx tmp;
22042 {
22053 }
22055 {
22068 }
22070 {
22079 }
22080 }
22081 }
22083 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22084 static void
22087 {
22088 count =
22094 }
22096 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22097 static void
22099 {
22100 rtx dest;
22103 {
22108 {
22110 {
22115 }
22116 else
22119 }
22121 {
22123 {
22126 }
22127 else
22128 {
22133 }
22135 }
22137 {
22141 }
22143 {
22147 }
22149 {
22153 }
22155 }
22157 {
22160 }
22162 {
22165 {
22169 }
22170 else
22171 {
22177 }
22180 }
22182 {
22185 {
22188 }
22189 else
22190 {
22194 }
22197 }
22199 {
22205 }
22207 {
22213 }
22215 {
22221 }
22222 }
22224 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22225 DESIRED_ALIGNMENT. */
22226 static void
22230 {
22232 {
22240 }
22242 {
22250 }
22252 {
22260 }
22262 }
22264 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22265 ALIGN_BYTES is how many bytes need to be copied. */
22266 static rtx
22269 {
22278 {
22283 }
22285 {
22296 }
22298 {
22304 {
22312 }
22315 }
22321 {
22333 }
22340 }
22342 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22343 DESIRED_ALIGNMENT. */
22344 static void
22347 {
22349 {
22356 }
22358 {
22365 }
22367 {
22374 }
22376 }
22378 /* Set enough from DST to align DST known to by aligned by ALIGN to
22379 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22380 static rtx
22383 {
22387 {
22392 }
22394 {
22401 }
22403 {
22410 }
22417 }
22419 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22420 static enum stringop_alg
22423 {
22426 /* Algorithms using the rep prefix want at least edi and ecx;
22427 additionally, memset wants eax and memcpy wants esi. Don't
22428 consider such algorithms if the user has appropriated those
22429 registers for their own purposes. */
22431 || (memset
22435 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22436 || (alg != rep_prefix_1_byte \
22437 && alg != rep_prefix_4_byte \
22438 && alg != rep_prefix_8_byte))
22441 /* Even if the string operation call is cold, we still might spend a lot
22442 of time processing large blocks. */
22447 else
22455 else
22459 /* rep; movq or rep; movl is the smallest variant. */
22461 {
22464 else
22466 }
22467 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22468 */
22472 {
22476 {
22477 /* We get here if the algorithms that were not libcall-based
22478 were rep-prefix based and we are unable to use rep prefixes
22479 based on global register usage. Break out of the loop and
22480 use the heuristic below. */
22484 {
22489 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22490 last non-libcall inline algorithm. */
22492 {
22493 /* When the current size is best to be copied by a libcall,
22494 but we are still forced to inline, run the heuristic below
22495 that will pick code for medium sized blocks. */
22499 }
22501 {
22504 }
22505 }
22506 }
22508 }
22509 /* When asked to inline the call anyway, try to pick meaningful choice.
22510 We look for maximal size of block that is faster to copy by hand and
22511 take blocks of at most of that size guessing that average size will
22512 be roughly half of the block.
22514 If this turns out to be bad, we might simply specify the preferred
22515 choice in ix86_costs. */
22518 {
22525 {
22532 }
22533 /* If there aren't any usable algorithms, then recursing on
22534 smaller sizes isn't going to find anything. Just return the
22535 simple byte-at-a-time copy loop. */
22537 {
22538 /* Pick something reasonable. */
22542 }
22551 }
22553 #undef ALG_USABLE_P
22554 }
22556 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22557 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22558 static int
22562 {
22565 {
22576 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22577 copying whole cacheline at once. */
22580 else
22584 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22585 copying whole cacheline at once. */
22588 else
22596 }
22605 }
22607 /* Return the smallest power of 2 greater than VAL. */
22608 static int
22610 {
22615 }
22617 /* Expand string move (memcpy) operation. Use i386 string operations
22618 when profitable. expand_setmem contains similar code. The code
22619 depends upon architecture, block size and alignment, but always has
22620 the same overall structure:
22622 1) Prologue guard: Conditional that jumps up to epilogues for small
22623 blocks that can be handled by epilogue alone. This is faster
22624 but also needed for correctness, since prologue assume the block
22625 is larger than the desired alignment.
22627 Optional dynamic check for size and libcall for large
22628 blocks is emitted here too, with -minline-stringops-dynamically.
22630 2) Prologue: copy first few bytes in order to get destination
22631 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22632 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22633 copied. We emit either a jump tree on power of two sized
22634 blocks, or a byte loop.
22636 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22637 with specified algorithm.
22639 4) Epilogue: code copying tail of the block that is too small to be
22640 handled by main body (or up to size guarded by prologue guard). */
22642 bool
22645 {
22646 rtx destreg;
22647 rtx srcreg;
22649 rtx tmp;
22663 /* i386 can do misaligned access on reasonably increased cost. */
22667 /* ALIGN is the minimum of destination and source alignment, but we care here
22668 just about destination alignment. */
22677 /* Make sure we don't need to care about overflow later on. */
22681 /* Step 0: Decide on preferred algorithm, desired alignment and
22682 size of chunks to be copied by main loop. */
22698 {
22723 }
22727 /* Step 1: Prologue guard. */
22729 /* Alignment code needs count to be in register. */
22731 {
22734 {
22735 align_bytes
22739 else
22741 }
22744 }
22747 /* Ensure that alignment prologue won't copy past end of block. */
22749 {
22751 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22752 Make sure it is power of 2. */
22756 {
22758 {
22759 /* If main algorithm works on QImode, no epilogue is needed.
22760 For small sizes just don't align anything. */
22763 else
22765 }
22766 }
22767 else
22768 {
22775 else
22777 }
22778 }
22780 /* Emit code to decide on runtime whether library call or inline should be
22781 used. */
22783 {
22785 {
22787 {
22791 }
22792 }
22793 else
22794 {
22803 }
22804 }
22806 /* Step 2: Alignment prologue. */
22809 {
22811 {
22812 /* Except for the first move in epilogue, we no longer know
22813 constant offset in aliasing info. It don't seems to worth
22814 the pain to maintain it for the first move, so throw away
22815 the info early. */
22819 desired_align);
22820 }
22821 else
22822 {
22823 /* If we know how many bytes need to be stored before dst is
22824 sufficiently aligned, maintain aliasing info accurately. */
22830 }
22836 {
22837 /* It is possible that we copied enough so the main loop will not
22838 execute. */
22848 else
22850 }
22851 }
22853 {
22858 }
22862 /* Step 3: Main loop. */
22865 {
22878 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22879 registers for 4 temporaries anyway. */
22882 expected_size);
22886 DImode);
22890 SImode);
22894 QImode);
22896 }
22897 /* Adjust properly the offset of src and dest memory for aliasing. */
22899 {
22904 }
22905 else
22906 {
22909 }
22911 /* Step 4: Epilogue to copy the remaining bytes. */
22912 epilogue:
22914 {
22915 /* When the main loop is done, COUNT_EXP might hold original count,
22916 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22917 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22918 bytes. Compensate if needed. */
22921 {
22922 tmp =
22925 OPTAB_DIRECT);
22928 }
22931 }
22935 epilogue_size_needed);
22939 }
22941 /* Helper function for memcpy. For QImode value 0xXY produce
22942 0xXYXYXYXY of wide specified by MODE. This is essentially
22943 a * 0x10101010, but we can do slightly better than
22944 synth_mult by unwinding the sequence by hand on CPUs with
22945 slow multiply. */
22946 static rtx
22948 {
22950 rtx tmp;
22957 {
22965 }
22974 nops--;
22979 {
22983 OPTAB_DIRECT);
22984 }
22985 else
22986 {
22992 else
22994 else
22995 {
22998 reg =
23000 }
23010 }
23011 }
23013 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23014 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23015 alignment from ALIGN to DESIRED_ALIGN. */
23016 static rtx
23018 {
23019 rtx promoted_val;
23028 else
23032 }
23034 /* Expand string clear operation (bzero). Use i386 string operations when
23035 profitable. See expand_movmem comment for explanation of individual
23036 steps performed. */
23037 bool
23040 {
23041 rtx destreg;
23043 rtx tmp;
23059 /* i386 can do misaligned access on reasonably increased cost. */
23068 /* Make sure we don't need to care about overflow later on. */
23072 /* Step 0: Decide on preferred algorithm, desired alignment and
23073 size of chunks to be copied by main loop. */
23088 {
23113 }
23116 /* Step 1: Prologue guard. */
23118 /* Alignment code needs count to be in register. */
23120 {
23123 {
23124 align_bytes
23128 else
23130 }
23132 {
23137 }
23138 }
23139 /* Do the cheap promotion to allow better CSE across the
23140 main loop and epilogue (ie one load of the big constant in the
23141 front of all code. */
23145 /* Ensure that alignment prologue won't copy past end of block. */
23147 {
23149 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23150 Make sure it is power of 2. */
23153 /* To improve performance of small blocks, we jump around the VAL
23154 promoting mode. This mean that if the promoted VAL is not constant,
23155 we might not use it in the epilogue and have to use byte
23156 loop variant. */
23160 {
23162 {
23163 /* If main algorithm works on QImode, no epilogue is needed.
23164 For small sizes just don't align anything. */
23167 else
23169 }
23170 }
23171 else
23172 {
23179 else
23181 }
23182 }
23184 {
23193 }
23195 /* Step 2: Alignment prologue. */
23197 /* Do the expensive promotion once we branched off the small blocks. */
23204 {
23206 {
23207 /* Except for the first move in epilogue, we no longer know
23208 constant offset in aliasing info. It don't seems to worth
23209 the pain to maintain it for the first move, so throw away
23210 the info early. */
23213 desired_align);
23214 }
23215 else
23216 {
23217 /* If we know how many bytes need to be stored before dst is
23218 sufficiently aligned, maintain aliasing info accurately. */
23224 }
23230 {
23231 /* It is possible that we copied enough so the main loop will not
23232 execute. */
23242 else
23244 }
23245 }
23247 {
23253 }
23257 /* Step 3: Main loop. */
23260 {
23288 }
23289 /* Adjust properly the offset of src and dest memory for aliasing. */
23293 else
23296 /* Step 4: Epilogue to copy the remaining bytes. */
23299 {
23300 /* When the main loop is done, COUNT_EXP might hold original count,
23301 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23302 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23303 bytes. Compensate if needed. */
23306 {
23307 tmp =
23310 OPTAB_DIRECT);
23313 }
23316 }
23317 epilogue:
23319 {
23322 epilogue_size_needed);
23323 else
23325 epilogue_size_needed);
23326 }
23330 }
23332 /* Expand the appropriate insns for doing strlen if not just doing
23333 repnz; scasb
23335 out = result, initialized with the start address
23336 align_rtx = alignment of the address.
23337 scratch = scratch register, initialized with the startaddress when
23338 not aligned, otherwise undefined
23340 This is just the body. It needs the initializations mentioned above and
23341 some address computing at the end. These things are done in i386.md. */
23343 static void
23345 {
23347 rtx tmp;
23352 rtx mem;
23355 rtx cmp;
23361 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23363 /* Is there a known alignment and is it less than 4? */
23365 {
23368 /* Is there a known alignment and is it not 2? */
23370 {
23374 /* Leave just the 3 lower bits. */
23384 }
23385 else
23386 {
23387 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23388 check if is aligned to 4 - byte. */
23395 }
23399 /* Now compare the bytes. */
23401 /* Compare the first n unaligned byte on a byte per byte basis. */
23405 /* Increment the address. */
23408 /* Not needed with an alignment of 2 */
23410 {
23414 end_0_label);
23419 }
23422 end_0_label);
23425 }
23427 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23428 align this loop. It gives only huge programs, but does not help to
23429 speed up. */
23436 /* This formula yields a nonzero result iff one of the bytes is zero.
23437 This saves three branches inside loop and many cycles. */
23445 align_4_label);
23448 {
23454 /* If zero is not in the first two bytes, move two bytes forward. */
23460 reg,
23461 tmpreg)));
23462 /* Emit lea manually to avoid clobbering of flags. */
23470 reg2,
23471 out)));
23472 }
23473 else
23474 {
23476 /* Is zero in the first two bytes? */
23483 pc_rtx);
23487 /* Not in the first two. Move two bytes forward. */
23493 }
23495 /* Avoid branch in fixing the byte. */
23503 }
23505 /* Expand strlen. */
23507 bool
23509 {
23512 /* The generic case of strlen expander is long. Avoid it's
23513 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23516 && !TARGET_INLINE_ALL_STRINGOPS
23526 {
23527 /* Well it seems that some optimizer does not combine a call like
23528 foo(strlen(bar), strlen(bar));
23529 when the move and the subtraction is done here. It does calculate
23530 the length just once when these instructions are done inside of
23531 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23532 often used and I use one fewer register for the lifetime of
23533 output_strlen_unroll() this is better. */
23539 /* strlensi_unroll_1 returns the address of the zero at the end of
23540 the string, like memchr(), so compute the length by subtracting
23541 the start address. */
23543 }
23544 else
23545 {
23546 rtx unspec;
23548 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23561 /* If .md starts supporting :P, this can be done in .md. */
23567 }
23569 }
23571 /* For given symbol (function) construct code to compute address of it's PLT
23572 entry in large x86-64 PIC model. */
23573 static rtx
23575 {
23588 }
23590 rtx
23592 rtx callarg2,
23594 {
23595 /* We need to represent that SI and DI registers are clobbered
23596 by SYSV calls. */
23602 };
23612 {
23613 #if TARGET_MACHO
23616 #endif
23617 }
23618 else
23619 {
23620 /* Static functions and indirect calls don't need the pic register. */
23625 }
23628 {
23632 }
23642 {
23645 }
23654 {
23658 }
23662 {
23666 UNSPEC_MS_TO_SYSV_CALL);
23674 }
23683 }
23685 /* Output the assembly for a call instruction. */
23689 {
23695 {
23698 /* SEH epilogue detection requires the indirect branch case
23699 to include REX.W. */
23702 else
23707 }
23709 /* SEH unwinding can require an extra nop to be emitted in several
23710 circumstances. Determine if we have one of those. */
23712 {
23713 rtx i;
23716 {
23717 /* If we get to another real insn, we don't need the nop. */
23721 /* If we get to the epilogue note, prevent a catch region from
23722 being adjacent to the standard epilogue sequence. If non-
23723 call-exceptions, we'll have done this during epilogue emission. */
23725 && !flag_non_call_exceptions
23727 {
23730 }
23731 }
23733 /* If we didn't find a real insn following the call, prevent the
23734 unwinder from looking into the next function. */
23737 }
23741 else
23750 }
23751 \f
23752 /* Clear stack slot assignments remembered from previous functions.
23753 This is called from INIT_EXPANDERS once before RTL is emitted for each
23754 function. */
23758 {
23766 }
23768 /* Return a MEM corresponding to a stack slot with mode MODE.
23769 Allocate a new slot if necessary.
23771 The RTL for a function can have several slots available: N is
23772 which slot to use. */
23774 rtx
23776 {
23793 }
23795 static void
23797 {
23803 }
23804 \f
23805 /* Calculate the length of the memory address in the instruction encoding.
23806 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23807 or other prefixes. We never generate addr32 prefix for LEA insn. */
23809 int
23811 {
23828 /* If this is not LEA instruction, add the length of addr32 prefix. */
23833 len++;
23847 /* Rule of thumb:
23848 - esp as the base always wants an index,
23849 - ebp as the base always wants a displacement,
23850 - r12 as the base always wants an index,
23851 - r13 as the base always wants a displacement. */
23853 /* Register Indirect. */
23855 {
23856 /* esp (for its index) and ebp (for its displacement) need
23857 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23858 code. */
23865 len++;
23866 }
23868 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23869 is not disp32, but disp32(%rip), so for disp32
23870 SIB byte is needed, unless print_operand_address
23871 optimizes it into disp32(%rip) or (%rip) is implied
23872 by UNSPEC. */
23874 {
23877 {
23893 len++;
23894 }
23895 }
23896 else
23897 {
23898 /* Find the length of the displacement constant. */
23900 {
23903 else
23905 }
23906 /* ebp always wants a displacement. Similarly r13. */
23908 len++;
23910 /* An index requires the two-byte modrm form.... */
23912 /* ...like esp (or r12), which always wants an index. */
23916 len++;
23917 }
23920 }
23922 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23923 is set, expect that insn have 8bit immediate alternative. */
23924 int
23926 {
23932 {
23937 {
23940 {
23952 }
23954 {
23957 }
23958 }
23960 {
23970 /* Immediates for DImode instructions are encoded
23971 as 32bit sign extended values. */
23977 }
23978 }
23980 }
23982 /* Compute default value for "length_address" attribute. */
23983 int
23985 {
23989 {
24000 }
24005 {
24008 {
24013 constraints++;
24016 ;
24017 /* Skip ignored operands. */
24020 }
24022 }
24024 }
24026 /* Compute default value for "length_vex" attribute. It includes
24027 2 or 3 byte VEX prefix and 1 opcode byte. */
24029 int
24031 {
24034 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24035 byte VEX prefix. */
24039 /* We can always use 2 byte VEX prefix in 32bit. */
24047 {
24048 /* REX.W bit uses 3 byte VEX prefix. */
24052 }
24053 else
24054 {
24055 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24059 }
24062 }
24063 \f
24064 /* Return the maximum number of instructions a cpu can issue. */
24066 static int
24068 {
24070 {
24096 }
24097 }
24099 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24100 by DEP_INSN and nothing set by DEP_INSN. */
24102 static bool
24104 {
24107 /* Simplify the test for uninteresting insns. */
24115 {
24118 }
24123 {
24126 }
24127 else
24133 /* This test is true if the dependent insn reads the flags but
24134 not any other potentially set register. */
24142 }
24144 /* Return true iff USE_INSN has a memory address with operands set by
24145 SET_INSN. */
24147 bool
24149 {
24154 {
24157 }
24159 }
24161 static int
24163 {
24169 /* Anti and output dependencies have zero cost on all CPUs. */
24175 /* If we can't recognize the insns, we can't really do anything. */
24183 {
24185 /* Address Generation Interlock adds a cycle of latency. */
24187 {
24198 }
24202 /* ??? Compares pair with jump/setcc. */
24206 /* Floating point stores require value to be ready one cycle earlier. */
24216 /* INT->FP conversion is expensive. */
24220 /* There is one cycle extra latency between an FP op and a store. */
24228 /* Show ability of reorder buffer to hide latency of load by executing
24229 in parallel with previous instruction in case
24230 previous instruction is not needed to compute the address. */
24233 {
24234 /* Claim moves to take one cycle, as core can issue one load
24235 at time and the next load can start cycle later. */
24240 cost--;
24241 }
24247 /* The esp dependency is resolved before the instruction is really
24248 finished. */
24253 /* INT->FP conversion is expensive. */
24257 /* Show ability of reorder buffer to hide latency of load by executing
24258 in parallel with previous instruction in case
24259 previous instruction is not needed to compute the address. */
24262 {
24263 /* Claim moves to take one cycle, as core can issue one load
24264 at time and the next load can start cycle later. */
24270 else
24272 }
24288 /* Show ability of reorder buffer to hide latency of load by executing
24289 in parallel with previous instruction in case
24290 previous instruction is not needed to compute the address. */
24293 {
24297 /* Because of the difference between the length of integer and
24298 floating unit pipeline preparation stages, the memory operands
24299 for floating point are cheaper.
24301 ??? For Athlon it the difference is most probably 2. */
24304 else
24309 else
24311 }
24315 }
24318 }
24320 /* How many alternative schedules to try. This should be as wide as the
24321 scheduling freedom in the DFA, but no wider. Making this value too
24322 large results extra work for the scheduler. */
24324 static int
24326 {
24328 {
24340 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24341 as many instructions can be executed on a cycle, i.e.,
24342 issue_rate. I wonder why tuning for many CPUs does not do this. */
24345 /* Don't use lookahead for pre-reload schedule to save compile time. */
24350 }
24351 }
24353 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24354 execution. It is applied if
24355 (1) IMUL instruction is on the top of list;
24356 (2) There exists the only producer of independent IMUL instruction in
24357 ready list;
24358 (3) Put found producer on the top of ready list.
24359 Returns issue rate. */
24361 static int
24364 {
24369 sd_iterator_def sd_it;
24370 dep_t dep;
24373 /* Set up issue rate. */
24376 /* Do reodering for Atom only. */
24379 /* Do not perform ready list reodering for pre-reload schedule pass. */
24382 /* Nothing to do if ready list contains only 1 instruction. */
24386 /* Check that IMUL instruction is on the top of ready list. */
24399 /* Search for producer of independent IMUL instruction. */
24401 {
24405 /* Skip IMUL instruction. */
24415 {
24416 rtx con;
24427 {
24428 sd_iterator_def sd_it1;
24429 dep_t dep1;
24430 /* Check if there is no other dependee for IMUL. */
24433 {
24434 rtx pro;
24440 }
24443 }
24444 }
24447 }
24455 /* Put IMUL producer (ready[index]) at the top of ready list. */
24462 }
24464 static bool
24467 /* Returns true if lhs of insn is HW function argument register and set up
24468 is_spilled to true if it is likely spilled HW register. */
24469 static bool
24471 {
24472 rtx dst;
24476 /* Call instructions are not movable, ignore it. */
24487 {
24488 /* Is it likely spilled HW register? */
24493 }
24495 }
24497 /* Add output dependencies for chain of function adjacent arguments if only
24498 there is a move to likely spilled HW register. Return first argument
24499 if at least one dependence was added or NULL otherwise. */
24500 static rtx
24502 {
24503 rtx insn;
24510 /* Find nearest to call argument passing instruction. */
24512 {
24521 }
24525 {
24532 {
24535 }
24537 {
24538 /* Add output depdendence between two function arguments if chain
24539 of output arguments contains likely spilled HW registers. */
24543 }
24544 else
24546 }
24550 }
24552 /* Add output or anti dependency from insn to first_arg to restrict its code
24553 motion. */
24554 static void
24556 {
24557 rtx set;
24558 rtx tmp;
24565 {
24566 /* Add output dependency to the first function argument. */
24569 }
24570 /* Add anti dependency. */
24572 }
24574 /* Avoid cross block motion of function argument through adding dependency
24575 from the first non-jump instruction in bb. */
24576 static void
24578 {
24582 {
24584 {
24587 {
24590 }
24591 }
24595 }
24596 }
24598 /* Hook for pre-reload schedule - avoid motion of function arguments
24599 passed in likely spilled HW registers. */
24600 static void
24602 {
24603 rtx insn;
24611 {
24614 {
24615 /* Add dependee for first argument to predecessors if only
24616 region contains more than one block. */
24620 /* Skip trivial regions and region head blocks that can have
24621 predecessors outside of region. */
24623 {
24624 edge e;
24625 edge_iterator ei;
24626 /* Assume that region is SCC, i.e. all immediate predecessors
24627 of non-head block are in the same region. */
24629 {
24630 /* Avoid creating of loop-carried dependencies through
24631 using topological odering in region. */
24634 }
24635 }
24639 }
24640 }
24643 }
24645 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24646 HW registers to maximum, to schedule them at soon as possible. These are
24647 moves from function argument registers at the top of the function entry
24648 and moves from function return value registers after call. */
24649 static int
24651 {
24652 rtx set;
24662 {
24669 }
24672 }
24674 /* Model decoder of Core 2/i7.
24675 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24676 track the instruction fetch block boundaries and make sure that long
24677 (9+ bytes) instructions are assigned to D0. */
24679 /* Maximum length of an insn that can be handled by
24680 a secondary decoder unit. '8' for Core 2/i7. */
24683 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24684 '16' for Core 2/i7. */
24687 /* Maximum number of instructions decoder can handle per cycle.
24688 '6' for Core 2/i7. */
24692 ix86_first_cycle_multipass_data_t;
24694 const_ix86_first_cycle_multipass_data_t;
24696 /* A variable to store target state across calls to max_issue within
24697 one cycle. */
24701 /* Initialize DATA. */
24702 static void
24704 {
24705 ix86_first_cycle_multipass_data_t data
24712 }
24714 /* Advancing the cycle; reset ifetch block counts. */
24715 static void
24717 {
24724 }
24728 /* Filter out insns from ready_try that the core will not be able to issue
24729 on current cycle due to decoder. */
24730 static void
24731 core2i7_first_cycle_multipass_filter_ready_try
24734 {
24736 {
24737 rtx insn;
24747 (!first_cycle_insn_p
24749 /* ... or it would not fit into the ifetch block ... */
24751 /* ... or the decoder is full already ... */
24753 /* ... mask the insn out. */
24754 {
24759 }
24760 }
24761 }
24763 /* Prepare for a new round of multipass lookahead scheduling. */
24764 static void
24767 {
24768 ix86_first_cycle_multipass_data_t data
24770 const_ix86_first_cycle_multipass_data_t prev_data
24773 /* Restore the state from the end of the previous round. */
24777 /* Filter instructions that cannot be issued on current cycle due to
24778 decoder restrictions. */
24780 first_cycle_insn_p);
24781 }
24783 /* INSN is being issued in current solution. Account for its impact on
24784 the decoder model. */
24785 static void
24788 {
24789 ix86_first_cycle_multipass_data_t data
24791 const_ix86_first_cycle_multipass_data_t prev_data
24801 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24803 {
24806 }
24808 {
24812 }
24815 /* Filter out insns from ready_try that the core will not be able to issue
24816 on current cycle due to decoder. */
24819 }
24821 /* Revert the effect on ready_try. */
24822 static void
24826 {
24827 const_ix86_first_cycle_multipass_data_t data
24830 sbitmap_iterator sbi;
24834 {
24836 }
24837 }
24839 /* Save the result of multipass lookahead scheduling for the next round. */
24840 static void
24842 {
24843 const_ix86_first_cycle_multipass_data_t data
24845 ix86_first_cycle_multipass_data_t next_data
24849 {
24852 }
24853 }
24855 /* Deallocate target data. */
24856 static void
24858 {
24859 ix86_first_cycle_multipass_data_t data
24863 {
24867 }
24868 }
24870 /* Prepare for scheduling pass. */
24871 static void
24875 {
24876 /* Install scheduling hooks for current CPU. Some of these hooks are used
24877 in time-critical parts of the scheduler, so we only set them up when
24878 they are actually used. */
24880 {
24884 /* Do not perform multipass scheduling for pre-reload schedule
24885 to save compile time. */
24887 {
24903 /* Set decoder parameters. */
24908 }
24909 /* ... Fall through ... */
24919 }
24920 }
24922 \f
24923 /* Compute the alignment given to a constant that is being placed in memory.
24924 EXP is the constant and ALIGN is the alignment that the object would
24925 ordinarily have.
24926 The value of this function is used instead of that alignment to align
24927 the object. */
24929 int
24931 {
24934 {
24939 }
24945 }
24947 /* Compute the alignment for a static variable.
24948 TYPE is the data type, and ALIGN is the alignment that
24949 the object would ordinarily have. The value of this function is used
24950 instead of that alignment to align the object. */
24952 int
24954 {
24965 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24966 to 16byte boundary. */
24968 {
24975 }
24978 {
24983 }
24985 {
24992 }
24997 {
25002 }
25005 {
25010 }
25013 }
25015 /* Compute the alignment for a local variable or a stack slot. EXP is
25016 the data type or decl itself, MODE is the widest mode available and
25017 ALIGN is the alignment that the object would ordinarily have. The
25018 value of this macro is used instead of that alignment to align the
25019 object. */
25021 unsigned int
25024 {
25028 {
25031 }
25032 else
25033 {
25036 }
25038 /* Don't do dynamic stack realignment for long long objects with
25039 -mpreferred-stack-boundary=2. */
25048 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25049 register in MODE. We will return the largest alignment of XF
25050 and DF. */
25052 {
25056 }
25058 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25059 to 16byte boundary. Exact wording is:
25061 An array uses the same alignment as its elements, except that a local or
25062 global array variable of length at least 16 bytes or
25063 a C99 variable-length array variable always has alignment of at least 16 bytes.
25065 This was added to allow use of aligned SSE instructions at arrays. This
25066 rule is meant for static storage (where compiler can not do the analysis
25067 by itself). We follow it for automatic variables only when convenient.
25068 We fully control everything in the function compiled and functions from
25069 other unit can not rely on the alignment.
25071 Exclude va_list type. It is the common case of local array where
25072 we can not benefit from the alignment. */
25075 {
25085 }
25087 {
25092 }
25094 {
25100 }
25105 {
25110 }
25113 {
25119 }
25121 }
25123 /* Compute the minimum required alignment for dynamic stack realignment
25124 purposes for a local variable, parameter or a stack slot. EXP is
25125 the data type or decl itself, MODE is its mode and ALIGN is the
25126 alignment that the object would ordinarily have. */
25128 unsigned int
25131 {
25135 {
25138 }
25139 else
25140 {
25143 }
25148 /* Don't do dynamic stack realignment for long long objects with
25149 -mpreferred-stack-boundary=2. */
25156 }
25157 \f
25158 /* Find a location for the static chain incoming to a nested function.
25159 This is a register, unless all free registers are used by arguments. */
25161 static rtx
25163 {
25170 {
25171 /* We always use R10 in 64-bit mode. */
25173 }
25174 else
25175 {
25176 tree fntype;
25179 /* By default in 32-bit mode we use ECX to pass the static chain. */
25185 {
25186 /* Fastcall functions use ecx/edx for arguments, which leaves
25187 us with EAX for the static chain.
25188 Thiscall functions use ecx for arguments, which also
25189 leaves us with EAX for the static chain. */
25191 }
25193 {
25194 /* Thiscall functions use ecx for arguments, which leaves
25195 us with EAX and EDX for the static chain.
25196 We are using for abi-compatibility EAX. */
25198 }
25200 {
25201 /* For regparm 3, we have no free call-clobbered registers in
25202 which to store the static chain. In order to implement this,
25203 we have the trampoline push the static chain to the stack.
25204 However, we can't push a value below the return address when
25205 we call the nested function directly, so we have to use an
25206 alternate entry point. For this we use ESI, and have the
25207 alternate entry point push ESI, so that things appear the
25208 same once we're executing the nested function. */
25210 {
25216 }
25218 }
25219 }
25222 }
25224 /* Emit RTL insns to initialize the variable parts of a trampoline.
25225 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25226 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25227 to be passed to the target function. */
25229 static void
25231 {
25239 {
25242 /* Load the function address to r11. Try to load address using
25243 the shorter movl instead of movabs. We may want to support
25244 movq for kernel mode, but kernel does not use trampolines at
25245 the moment. FNADDR is a 32bit address and may not be in
25246 DImode when ptr_mode == SImode. Always use movl in this
25247 case. */
25250 {
25259 }
25260 else
25261 {
25268 }
25270 /* Load static chain using movabs to r10. Use the shorter movl
25271 instead of movabs when ptr_mode == SImode. */
25273 {
25276 }
25277 else
25278 {
25281 }
25290 /* Jump to r11; the last (unused) byte is a nop, only there to
25291 pad the write out to a single 32-bit store. */
25295 }
25296 else
25297 {
25300 /* Depending on the static chain location, either load a register
25301 with a constant, or push the constant to the stack. All of the
25302 instructions are the same size. */
25305 {
25307 {
25314 }
25315 }
25316 else
25331 /* Compute offset from the end of the jmp to the target function.
25332 In the case in which the trampoline stores the static chain on
25333 the stack, we need to skip the first insn which pushes the
25334 (call-saved) register static chain; this push is 1 byte. */
25341 }
25345 #ifdef HAVE_ENABLE_EXECUTE_STACK
25346 #ifdef CHECK_EXECUTE_STACK_ENABLED
25348 #endif
25351 #endif
25352 }
25353 \f
25354 /* The following file contains several enumerations and data structures
25355 built from the definitions in i386-builtin-types.def. */
25359 /* Table for the ix86 builtin non-function types. */
25362 /* Retrieve an element from the above table, building some of
25363 the types lazily. */
25365 static tree
25367 {
25379 {
25387 }
25388 else
25389 {
25395 else
25403 }
25407 }
25409 /* Table for the ix86 builtin function types. */
25412 /* Retrieve an element from the above table, building some of
25413 the types lazily. */
25415 static tree
25417 {
25418 tree type;
25427 {
25435 {
25438 }
25441 }
25442 else
25443 {
25449 }
25453 }
25456 /* Codes for all the SSE/MMX builtins. */
25457 enum ix86_builtins
25458 {
25459 IX86_BUILTIN_ADDPS,
25460 IX86_BUILTIN_ADDSS,
25461 IX86_BUILTIN_DIVPS,
25462 IX86_BUILTIN_DIVSS,
25463 IX86_BUILTIN_MULPS,
25464 IX86_BUILTIN_MULSS,
25465 IX86_BUILTIN_SUBPS,
25466 IX86_BUILTIN_SUBSS,
25468 IX86_BUILTIN_CMPEQPS,
25469 IX86_BUILTIN_CMPLTPS,
25470 IX86_BUILTIN_CMPLEPS,
25471 IX86_BUILTIN_CMPGTPS,
25472 IX86_BUILTIN_CMPGEPS,
25473 IX86_BUILTIN_CMPNEQPS,
25474 IX86_BUILTIN_CMPNLTPS,
25475 IX86_BUILTIN_CMPNLEPS,
25476 IX86_BUILTIN_CMPNGTPS,
25477 IX86_BUILTIN_CMPNGEPS,
25478 IX86_BUILTIN_CMPORDPS,
25479 IX86_BUILTIN_CMPUNORDPS,
25480 IX86_BUILTIN_CMPEQSS,
25481 IX86_BUILTIN_CMPLTSS,
25482 IX86_BUILTIN_CMPLESS,
25483 IX86_BUILTIN_CMPNEQSS,
25484 IX86_BUILTIN_CMPNLTSS,
25485 IX86_BUILTIN_CMPNLESS,
25486 IX86_BUILTIN_CMPNGTSS,
25487 IX86_BUILTIN_CMPNGESS,
25488 IX86_BUILTIN_CMPORDSS,
25489 IX86_BUILTIN_CMPUNORDSS,
25491 IX86_BUILTIN_COMIEQSS,
25492 IX86_BUILTIN_COMILTSS,
25493 IX86_BUILTIN_COMILESS,
25494 IX86_BUILTIN_COMIGTSS,
25495 IX86_BUILTIN_COMIGESS,
25496 IX86_BUILTIN_COMINEQSS,
25497 IX86_BUILTIN_UCOMIEQSS,
25498 IX86_BUILTIN_UCOMILTSS,
25499 IX86_BUILTIN_UCOMILESS,
25500 IX86_BUILTIN_UCOMIGTSS,
25501 IX86_BUILTIN_UCOMIGESS,
25502 IX86_BUILTIN_UCOMINEQSS,
25504 IX86_BUILTIN_CVTPI2PS,
25505 IX86_BUILTIN_CVTPS2PI,
25506 IX86_BUILTIN_CVTSI2SS,
25507 IX86_BUILTIN_CVTSI642SS,
25508 IX86_BUILTIN_CVTSS2SI,
25509 IX86_BUILTIN_CVTSS2SI64,
25510 IX86_BUILTIN_CVTTPS2PI,
25511 IX86_BUILTIN_CVTTSS2SI,
25512 IX86_BUILTIN_CVTTSS2SI64,
25514 IX86_BUILTIN_MAXPS,
25515 IX86_BUILTIN_MAXSS,
25516 IX86_BUILTIN_MINPS,
25517 IX86_BUILTIN_MINSS,
25519 IX86_BUILTIN_LOADUPS,
25520 IX86_BUILTIN_STOREUPS,
25521 IX86_BUILTIN_MOVSS,
25523 IX86_BUILTIN_MOVHLPS,
25524 IX86_BUILTIN_MOVLHPS,
25525 IX86_BUILTIN_LOADHPS,
25526 IX86_BUILTIN_LOADLPS,
25527 IX86_BUILTIN_STOREHPS,
25528 IX86_BUILTIN_STORELPS,
25530 IX86_BUILTIN_MASKMOVQ,
25531 IX86_BUILTIN_MOVMSKPS,
25532 IX86_BUILTIN_PMOVMSKB,
25534 IX86_BUILTIN_MOVNTPS,
25535 IX86_BUILTIN_MOVNTQ,
25537 IX86_BUILTIN_LOADDQU,
25538 IX86_BUILTIN_STOREDQU,
25540 IX86_BUILTIN_PACKSSWB,
25541 IX86_BUILTIN_PACKSSDW,
25542 IX86_BUILTIN_PACKUSWB,
25544 IX86_BUILTIN_PADDB,
25545 IX86_BUILTIN_PADDW,
25546 IX86_BUILTIN_PADDD,
25547 IX86_BUILTIN_PADDQ,
25548 IX86_BUILTIN_PADDSB,
25549 IX86_BUILTIN_PADDSW,
25550 IX86_BUILTIN_PADDUSB,
25551 IX86_BUILTIN_PADDUSW,
25552 IX86_BUILTIN_PSUBB,
25553 IX86_BUILTIN_PSUBW,
25554 IX86_BUILTIN_PSUBD,
25555 IX86_BUILTIN_PSUBQ,
25556 IX86_BUILTIN_PSUBSB,
25557 IX86_BUILTIN_PSUBSW,
25558 IX86_BUILTIN_PSUBUSB,
25559 IX86_BUILTIN_PSUBUSW,
25561 IX86_BUILTIN_PAND,
25562 IX86_BUILTIN_PANDN,
25563 IX86_BUILTIN_POR,
25564 IX86_BUILTIN_PXOR,
25566 IX86_BUILTIN_PAVGB,
25567 IX86_BUILTIN_PAVGW,
25569 IX86_BUILTIN_PCMPEQB,
25570 IX86_BUILTIN_PCMPEQW,
25571 IX86_BUILTIN_PCMPEQD,
25572 IX86_BUILTIN_PCMPGTB,
25573 IX86_BUILTIN_PCMPGTW,
25574 IX86_BUILTIN_PCMPGTD,
25576 IX86_BUILTIN_PMADDWD,
25578 IX86_BUILTIN_PMAXSW,
25579 IX86_BUILTIN_PMAXUB,
25580 IX86_BUILTIN_PMINSW,
25581 IX86_BUILTIN_PMINUB,
25583 IX86_BUILTIN_PMULHUW,
25584 IX86_BUILTIN_PMULHW,
25585 IX86_BUILTIN_PMULLW,
25587 IX86_BUILTIN_PSADBW,
25588 IX86_BUILTIN_PSHUFW,
25590 IX86_BUILTIN_PSLLW,
25591 IX86_BUILTIN_PSLLD,
25592 IX86_BUILTIN_PSLLQ,
25593 IX86_BUILTIN_PSRAW,
25594 IX86_BUILTIN_PSRAD,
25595 IX86_BUILTIN_PSRLW,
25596 IX86_BUILTIN_PSRLD,
25597 IX86_BUILTIN_PSRLQ,
25598 IX86_BUILTIN_PSLLWI,
25599 IX86_BUILTIN_PSLLDI,
25600 IX86_BUILTIN_PSLLQI,
25601 IX86_BUILTIN_PSRAWI,
25602 IX86_BUILTIN_PSRADI,
25603 IX86_BUILTIN_PSRLWI,
25604 IX86_BUILTIN_PSRLDI,
25605 IX86_BUILTIN_PSRLQI,
25607 IX86_BUILTIN_PUNPCKHBW,
25608 IX86_BUILTIN_PUNPCKHWD,
25609 IX86_BUILTIN_PUNPCKHDQ,
25610 IX86_BUILTIN_PUNPCKLBW,
25611 IX86_BUILTIN_PUNPCKLWD,
25612 IX86_BUILTIN_PUNPCKLDQ,
25614 IX86_BUILTIN_SHUFPS,
25616 IX86_BUILTIN_RCPPS,
25617 IX86_BUILTIN_RCPSS,
25618 IX86_BUILTIN_RSQRTPS,
25619 IX86_BUILTIN_RSQRTPS_NR,
25620 IX86_BUILTIN_RSQRTSS,
25621 IX86_BUILTIN_RSQRTF,
25622 IX86_BUILTIN_SQRTPS,
25623 IX86_BUILTIN_SQRTPS_NR,
25624 IX86_BUILTIN_SQRTSS,
25626 IX86_BUILTIN_UNPCKHPS,
25627 IX86_BUILTIN_UNPCKLPS,
25629 IX86_BUILTIN_ANDPS,
25630 IX86_BUILTIN_ANDNPS,
25631 IX86_BUILTIN_ORPS,
25632 IX86_BUILTIN_XORPS,
25634 IX86_BUILTIN_EMMS,
25635 IX86_BUILTIN_LDMXCSR,
25636 IX86_BUILTIN_STMXCSR,
25637 IX86_BUILTIN_SFENCE,
25639 IX86_BUILTIN_FXSAVE,
25640 IX86_BUILTIN_FXRSTOR,
25641 IX86_BUILTIN_FXSAVE64,
25642 IX86_BUILTIN_FXRSTOR64,
25644 IX86_BUILTIN_XSAVE,
25645 IX86_BUILTIN_XRSTOR,
25646 IX86_BUILTIN_XSAVE64,
25647 IX86_BUILTIN_XRSTOR64,
25649 IX86_BUILTIN_XSAVEOPT,
25650 IX86_BUILTIN_XSAVEOPT64,
25652 /* 3DNow! Original */
25653 IX86_BUILTIN_FEMMS,
25654 IX86_BUILTIN_PAVGUSB,
25655 IX86_BUILTIN_PF2ID,
25656 IX86_BUILTIN_PFACC,
25657 IX86_BUILTIN_PFADD,
25658 IX86_BUILTIN_PFCMPEQ,
25659 IX86_BUILTIN_PFCMPGE,
25660 IX86_BUILTIN_PFCMPGT,
25661 IX86_BUILTIN_PFMAX,
25662 IX86_BUILTIN_PFMIN,
25663 IX86_BUILTIN_PFMUL,
25664 IX86_BUILTIN_PFRCP,
25665 IX86_BUILTIN_PFRCPIT1,
25666 IX86_BUILTIN_PFRCPIT2,
25667 IX86_BUILTIN_PFRSQIT1,
25668 IX86_BUILTIN_PFRSQRT,
25669 IX86_BUILTIN_PFSUB,
25670 IX86_BUILTIN_PFSUBR,
25671 IX86_BUILTIN_PI2FD,
25672 IX86_BUILTIN_PMULHRW,
25674 /* 3DNow! Athlon Extensions */
25675 IX86_BUILTIN_PF2IW,
25676 IX86_BUILTIN_PFNACC,
25677 IX86_BUILTIN_PFPNACC,
25678 IX86_BUILTIN_PI2FW,
25679 IX86_BUILTIN_PSWAPDSI,
25680 IX86_BUILTIN_PSWAPDSF,
25682 /* SSE2 */
25683 IX86_BUILTIN_ADDPD,
25684 IX86_BUILTIN_ADDSD,
25685 IX86_BUILTIN_DIVPD,
25686 IX86_BUILTIN_DIVSD,
25687 IX86_BUILTIN_MULPD,
25688 IX86_BUILTIN_MULSD,
25689 IX86_BUILTIN_SUBPD,
25690 IX86_BUILTIN_SUBSD,
25692 IX86_BUILTIN_CMPEQPD,
25693 IX86_BUILTIN_CMPLTPD,
25694 IX86_BUILTIN_CMPLEPD,
25695 IX86_BUILTIN_CMPGTPD,
25696 IX86_BUILTIN_CMPGEPD,
25697 IX86_BUILTIN_CMPNEQPD,
25698 IX86_BUILTIN_CMPNLTPD,
25699 IX86_BUILTIN_CMPNLEPD,
25700 IX86_BUILTIN_CMPNGTPD,
25701 IX86_BUILTIN_CMPNGEPD,
25702 IX86_BUILTIN_CMPORDPD,
25703 IX86_BUILTIN_CMPUNORDPD,
25704 IX86_BUILTIN_CMPEQSD,
25705 IX86_BUILTIN_CMPLTSD,
25706 IX86_BUILTIN_CMPLESD,
25707 IX86_BUILTIN_CMPNEQSD,
25708 IX86_BUILTIN_CMPNLTSD,
25709 IX86_BUILTIN_CMPNLESD,
25710 IX86_BUILTIN_CMPORDSD,
25711 IX86_BUILTIN_CMPUNORDSD,
25713 IX86_BUILTIN_COMIEQSD,
25714 IX86_BUILTIN_COMILTSD,
25715 IX86_BUILTIN_COMILESD,
25716 IX86_BUILTIN_COMIGTSD,
25717 IX86_BUILTIN_COMIGESD,
25718 IX86_BUILTIN_COMINEQSD,
25719 IX86_BUILTIN_UCOMIEQSD,
25720 IX86_BUILTIN_UCOMILTSD,
25721 IX86_BUILTIN_UCOMILESD,
25722 IX86_BUILTIN_UCOMIGTSD,
25723 IX86_BUILTIN_UCOMIGESD,
25724 IX86_BUILTIN_UCOMINEQSD,
25726 IX86_BUILTIN_MAXPD,
25727 IX86_BUILTIN_MAXSD,
25728 IX86_BUILTIN_MINPD,
25729 IX86_BUILTIN_MINSD,
25731 IX86_BUILTIN_ANDPD,
25732 IX86_BUILTIN_ANDNPD,
25733 IX86_BUILTIN_ORPD,
25734 IX86_BUILTIN_XORPD,
25736 IX86_BUILTIN_SQRTPD,
25737 IX86_BUILTIN_SQRTSD,
25739 IX86_BUILTIN_UNPCKHPD,
25740 IX86_BUILTIN_UNPCKLPD,
25742 IX86_BUILTIN_SHUFPD,
25744 IX86_BUILTIN_LOADUPD,
25745 IX86_BUILTIN_STOREUPD,
25746 IX86_BUILTIN_MOVSD,
25748 IX86_BUILTIN_LOADHPD,
25749 IX86_BUILTIN_LOADLPD,
25751 IX86_BUILTIN_CVTDQ2PD,
25752 IX86_BUILTIN_CVTDQ2PS,
25754 IX86_BUILTIN_CVTPD2DQ,
25755 IX86_BUILTIN_CVTPD2PI,
25756 IX86_BUILTIN_CVTPD2PS,
25757 IX86_BUILTIN_CVTTPD2DQ,
25758 IX86_BUILTIN_CVTTPD2PI,
25760 IX86_BUILTIN_CVTPI2PD,
25761 IX86_BUILTIN_CVTSI2SD,
25762 IX86_BUILTIN_CVTSI642SD,
25764 IX86_BUILTIN_CVTSD2SI,
25765 IX86_BUILTIN_CVTSD2SI64,
25766 IX86_BUILTIN_CVTSD2SS,
25767 IX86_BUILTIN_CVTSS2SD,
25768 IX86_BUILTIN_CVTTSD2SI,
25769 IX86_BUILTIN_CVTTSD2SI64,
25771 IX86_BUILTIN_CVTPS2DQ,
25772 IX86_BUILTIN_CVTPS2PD,
25773 IX86_BUILTIN_CVTTPS2DQ,
25775 IX86_BUILTIN_MOVNTI,
25776 IX86_BUILTIN_MOVNTI64,
25777 IX86_BUILTIN_MOVNTPD,
25778 IX86_BUILTIN_MOVNTDQ,
25780 IX86_BUILTIN_MOVQ128,
25782 /* SSE2 MMX */
25783 IX86_BUILTIN_MASKMOVDQU,
25784 IX86_BUILTIN_MOVMSKPD,
25785 IX86_BUILTIN_PMOVMSKB128,
25787 IX86_BUILTIN_PACKSSWB128,
25788 IX86_BUILTIN_PACKSSDW128,
25789 IX86_BUILTIN_PACKUSWB128,
25791 IX86_BUILTIN_PADDB128,
25792 IX86_BUILTIN_PADDW128,
25793 IX86_BUILTIN_PADDD128,
25794 IX86_BUILTIN_PADDQ128,
25795 IX86_BUILTIN_PADDSB128,
25796 IX86_BUILTIN_PADDSW128,
25797 IX86_BUILTIN_PADDUSB128,
25798 IX86_BUILTIN_PADDUSW128,
25799 IX86_BUILTIN_PSUBB128,
25800 IX86_BUILTIN_PSUBW128,
25801 IX86_BUILTIN_PSUBD128,
25802 IX86_BUILTIN_PSUBQ128,
25803 IX86_BUILTIN_PSUBSB128,
25804 IX86_BUILTIN_PSUBSW128,
25805 IX86_BUILTIN_PSUBUSB128,
25806 IX86_BUILTIN_PSUBUSW128,
25808 IX86_BUILTIN_PAND128,
25809 IX86_BUILTIN_PANDN128,
25810 IX86_BUILTIN_POR128,
25811 IX86_BUILTIN_PXOR128,
25813 IX86_BUILTIN_PAVGB128,
25814 IX86_BUILTIN_PAVGW128,
25816 IX86_BUILTIN_PCMPEQB128,
25817 IX86_BUILTIN_PCMPEQW128,
25818 IX86_BUILTIN_PCMPEQD128,
25819 IX86_BUILTIN_PCMPGTB128,
25820 IX86_BUILTIN_PCMPGTW128,
25821 IX86_BUILTIN_PCMPGTD128,
25823 IX86_BUILTIN_PMADDWD128,
25825 IX86_BUILTIN_PMAXSW128,
25826 IX86_BUILTIN_PMAXUB128,
25827 IX86_BUILTIN_PMINSW128,
25828 IX86_BUILTIN_PMINUB128,
25830 IX86_BUILTIN_PMULUDQ,
25831 IX86_BUILTIN_PMULUDQ128,
25832 IX86_BUILTIN_PMULHUW128,
25833 IX86_BUILTIN_PMULHW128,
25834 IX86_BUILTIN_PMULLW128,
25836 IX86_BUILTIN_PSADBW128,
25837 IX86_BUILTIN_PSHUFHW,
25838 IX86_BUILTIN_PSHUFLW,
25839 IX86_BUILTIN_PSHUFD,
25841 IX86_BUILTIN_PSLLDQI128,
25842 IX86_BUILTIN_PSLLWI128,
25843 IX86_BUILTIN_PSLLDI128,
25844 IX86_BUILTIN_PSLLQI128,
25845 IX86_BUILTIN_PSRAWI128,
25846 IX86_BUILTIN_PSRADI128,
25847 IX86_BUILTIN_PSRLDQI128,
25848 IX86_BUILTIN_PSRLWI128,
25849 IX86_BUILTIN_PSRLDI128,
25850 IX86_BUILTIN_PSRLQI128,
25852 IX86_BUILTIN_PSLLDQ128,
25853 IX86_BUILTIN_PSLLW128,
25854 IX86_BUILTIN_PSLLD128,
25855 IX86_BUILTIN_PSLLQ128,
25856 IX86_BUILTIN_PSRAW128,
25857 IX86_BUILTIN_PSRAD128,
25858 IX86_BUILTIN_PSRLW128,
25859 IX86_BUILTIN_PSRLD128,
25860 IX86_BUILTIN_PSRLQ128,
25862 IX86_BUILTIN_PUNPCKHBW128,
25863 IX86_BUILTIN_PUNPCKHWD128,
25864 IX86_BUILTIN_PUNPCKHDQ128,
25865 IX86_BUILTIN_PUNPCKHQDQ128,
25866 IX86_BUILTIN_PUNPCKLBW128,
25867 IX86_BUILTIN_PUNPCKLWD128,
25868 IX86_BUILTIN_PUNPCKLDQ128,
25869 IX86_BUILTIN_PUNPCKLQDQ128,
25871 IX86_BUILTIN_CLFLUSH,
25872 IX86_BUILTIN_MFENCE,
25873 IX86_BUILTIN_LFENCE,
25874 IX86_BUILTIN_PAUSE,
25876 IX86_BUILTIN_BSRSI,
25877 IX86_BUILTIN_BSRDI,
25878 IX86_BUILTIN_RDPMC,
25879 IX86_BUILTIN_RDTSC,
25880 IX86_BUILTIN_RDTSCP,
25881 IX86_BUILTIN_ROLQI,
25882 IX86_BUILTIN_ROLHI,
25883 IX86_BUILTIN_RORQI,
25884 IX86_BUILTIN_RORHI,
25886 /* SSE3. */
25887 IX86_BUILTIN_ADDSUBPS,
25888 IX86_BUILTIN_HADDPS,
25889 IX86_BUILTIN_HSUBPS,
25890 IX86_BUILTIN_MOVSHDUP,
25891 IX86_BUILTIN_MOVSLDUP,
25892 IX86_BUILTIN_ADDSUBPD,
25893 IX86_BUILTIN_HADDPD,
25894 IX86_BUILTIN_HSUBPD,
25895 IX86_BUILTIN_LDDQU,
25897 IX86_BUILTIN_MONITOR,
25898 IX86_BUILTIN_MWAIT,
25900 /* SSSE3. */
25901 IX86_BUILTIN_PHADDW,
25902 IX86_BUILTIN_PHADDD,
25903 IX86_BUILTIN_PHADDSW,
25904 IX86_BUILTIN_PHSUBW,
25905 IX86_BUILTIN_PHSUBD,
25906 IX86_BUILTIN_PHSUBSW,
25907 IX86_BUILTIN_PMADDUBSW,
25908 IX86_BUILTIN_PMULHRSW,
25909 IX86_BUILTIN_PSHUFB,
25910 IX86_BUILTIN_PSIGNB,
25911 IX86_BUILTIN_PSIGNW,
25912 IX86_BUILTIN_PSIGND,
25913 IX86_BUILTIN_PALIGNR,
25914 IX86_BUILTIN_PABSB,
25915 IX86_BUILTIN_PABSW,
25916 IX86_BUILTIN_PABSD,
25918 IX86_BUILTIN_PHADDW128,
25919 IX86_BUILTIN_PHADDD128,
25920 IX86_BUILTIN_PHADDSW128,
25921 IX86_BUILTIN_PHSUBW128,
25922 IX86_BUILTIN_PHSUBD128,
25923 IX86_BUILTIN_PHSUBSW128,
25924 IX86_BUILTIN_PMADDUBSW128,
25925 IX86_BUILTIN_PMULHRSW128,
25926 IX86_BUILTIN_PSHUFB128,
25927 IX86_BUILTIN_PSIGNB128,
25928 IX86_BUILTIN_PSIGNW128,
25929 IX86_BUILTIN_PSIGND128,
25930 IX86_BUILTIN_PALIGNR128,
25931 IX86_BUILTIN_PABSB128,
25932 IX86_BUILTIN_PABSW128,
25933 IX86_BUILTIN_PABSD128,
25935 /* AMDFAM10 - SSE4A New Instructions. */
25936 IX86_BUILTIN_MOVNTSD,
25937 IX86_BUILTIN_MOVNTSS,
25938 IX86_BUILTIN_EXTRQI,
25939 IX86_BUILTIN_EXTRQ,
25940 IX86_BUILTIN_INSERTQI,
25941 IX86_BUILTIN_INSERTQ,
25943 /* SSE4.1. */
25944 IX86_BUILTIN_BLENDPD,
25945 IX86_BUILTIN_BLENDPS,
25946 IX86_BUILTIN_BLENDVPD,
25947 IX86_BUILTIN_BLENDVPS,
25948 IX86_BUILTIN_PBLENDVB128,
25949 IX86_BUILTIN_PBLENDW128,
25951 IX86_BUILTIN_DPPD,
25952 IX86_BUILTIN_DPPS,
25954 IX86_BUILTIN_INSERTPS128,
25956 IX86_BUILTIN_MOVNTDQA,
25957 IX86_BUILTIN_MPSADBW128,
25958 IX86_BUILTIN_PACKUSDW128,
25959 IX86_BUILTIN_PCMPEQQ,
25960 IX86_BUILTIN_PHMINPOSUW128,
25962 IX86_BUILTIN_PMAXSB128,
25963 IX86_BUILTIN_PMAXSD128,
25964 IX86_BUILTIN_PMAXUD128,
25965 IX86_BUILTIN_PMAXUW128,
25967 IX86_BUILTIN_PMINSB128,
25968 IX86_BUILTIN_PMINSD128,
25969 IX86_BUILTIN_PMINUD128,
25970 IX86_BUILTIN_PMINUW128,
25972 IX86_BUILTIN_PMOVSXBW128,
25973 IX86_BUILTIN_PMOVSXBD128,
25974 IX86_BUILTIN_PMOVSXBQ128,
25975 IX86_BUILTIN_PMOVSXWD128,
25976 IX86_BUILTIN_PMOVSXWQ128,
25977 IX86_BUILTIN_PMOVSXDQ128,
25979 IX86_BUILTIN_PMOVZXBW128,
25980 IX86_BUILTIN_PMOVZXBD128,
25981 IX86_BUILTIN_PMOVZXBQ128,
25982 IX86_BUILTIN_PMOVZXWD128,
25983 IX86_BUILTIN_PMOVZXWQ128,
25984 IX86_BUILTIN_PMOVZXDQ128,
25986 IX86_BUILTIN_PMULDQ128,
25987 IX86_BUILTIN_PMULLD128,
25989 IX86_BUILTIN_ROUNDSD,
25990 IX86_BUILTIN_ROUNDSS,
25992 IX86_BUILTIN_ROUNDPD,
25993 IX86_BUILTIN_ROUNDPS,
25995 IX86_BUILTIN_FLOORPD,
25996 IX86_BUILTIN_CEILPD,
25997 IX86_BUILTIN_TRUNCPD,
25998 IX86_BUILTIN_RINTPD,
25999 IX86_BUILTIN_ROUNDPD_AZ,
26001 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26002 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26003 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26005 IX86_BUILTIN_FLOORPS,
26006 IX86_BUILTIN_CEILPS,
26007 IX86_BUILTIN_TRUNCPS,
26008 IX86_BUILTIN_RINTPS,
26009 IX86_BUILTIN_ROUNDPS_AZ,
26011 IX86_BUILTIN_FLOORPS_SFIX,
26012 IX86_BUILTIN_CEILPS_SFIX,
26013 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26015 IX86_BUILTIN_PTESTZ,
26016 IX86_BUILTIN_PTESTC,
26017 IX86_BUILTIN_PTESTNZC,
26019 IX86_BUILTIN_VEC_INIT_V2SI,
26020 IX86_BUILTIN_VEC_INIT_V4HI,
26021 IX86_BUILTIN_VEC_INIT_V8QI,
26022 IX86_BUILTIN_VEC_EXT_V2DF,
26023 IX86_BUILTIN_VEC_EXT_V2DI,
26024 IX86_BUILTIN_VEC_EXT_V4SF,
26025 IX86_BUILTIN_VEC_EXT_V4SI,
26026 IX86_BUILTIN_VEC_EXT_V8HI,
26027 IX86_BUILTIN_VEC_EXT_V2SI,
26028 IX86_BUILTIN_VEC_EXT_V4HI,
26029 IX86_BUILTIN_VEC_EXT_V16QI,
26030 IX86_BUILTIN_VEC_SET_V2DI,
26031 IX86_BUILTIN_VEC_SET_V4SF,
26032 IX86_BUILTIN_VEC_SET_V4SI,
26033 IX86_BUILTIN_VEC_SET_V8HI,
26034 IX86_BUILTIN_VEC_SET_V4HI,
26035 IX86_BUILTIN_VEC_SET_V16QI,
26037 IX86_BUILTIN_VEC_PACK_SFIX,
26038 IX86_BUILTIN_VEC_PACK_SFIX256,
26040 /* SSE4.2. */
26041 IX86_BUILTIN_CRC32QI,
26042 IX86_BUILTIN_CRC32HI,
26043 IX86_BUILTIN_CRC32SI,
26044 IX86_BUILTIN_CRC32DI,
26046 IX86_BUILTIN_PCMPESTRI128,
26047 IX86_BUILTIN_PCMPESTRM128,
26048 IX86_BUILTIN_PCMPESTRA128,
26049 IX86_BUILTIN_PCMPESTRC128,
26050 IX86_BUILTIN_PCMPESTRO128,
26051 IX86_BUILTIN_PCMPESTRS128,
26052 IX86_BUILTIN_PCMPESTRZ128,
26053 IX86_BUILTIN_PCMPISTRI128,
26054 IX86_BUILTIN_PCMPISTRM128,
26055 IX86_BUILTIN_PCMPISTRA128,
26056 IX86_BUILTIN_PCMPISTRC128,
26057 IX86_BUILTIN_PCMPISTRO128,
26058 IX86_BUILTIN_PCMPISTRS128,
26059 IX86_BUILTIN_PCMPISTRZ128,
26061 IX86_BUILTIN_PCMPGTQ,
26063 /* AES instructions */
26064 IX86_BUILTIN_AESENC128,
26065 IX86_BUILTIN_AESENCLAST128,
26066 IX86_BUILTIN_AESDEC128,
26067 IX86_BUILTIN_AESDECLAST128,
26068 IX86_BUILTIN_AESIMC128,
26069 IX86_BUILTIN_AESKEYGENASSIST128,
26071 /* PCLMUL instruction */
26072 IX86_BUILTIN_PCLMULQDQ128,
26074 /* AVX */
26075 IX86_BUILTIN_ADDPD256,
26076 IX86_BUILTIN_ADDPS256,
26077 IX86_BUILTIN_ADDSUBPD256,
26078 IX86_BUILTIN_ADDSUBPS256,
26079 IX86_BUILTIN_ANDPD256,
26080 IX86_BUILTIN_ANDPS256,
26081 IX86_BUILTIN_ANDNPD256,
26082 IX86_BUILTIN_ANDNPS256,
26083 IX86_BUILTIN_BLENDPD256,
26084 IX86_BUILTIN_BLENDPS256,
26085 IX86_BUILTIN_BLENDVPD256,
26086 IX86_BUILTIN_BLENDVPS256,
26087 IX86_BUILTIN_DIVPD256,
26088 IX86_BUILTIN_DIVPS256,
26089 IX86_BUILTIN_DPPS256,
26090 IX86_BUILTIN_HADDPD256,
26091 IX86_BUILTIN_HADDPS256,
26092 IX86_BUILTIN_HSUBPD256,
26093 IX86_BUILTIN_HSUBPS256,
26094 IX86_BUILTIN_MAXPD256,
26095 IX86_BUILTIN_MAXPS256,
26096 IX86_BUILTIN_MINPD256,
26097 IX86_BUILTIN_MINPS256,
26098 IX86_BUILTIN_MULPD256,
26099 IX86_BUILTIN_MULPS256,
26100 IX86_BUILTIN_ORPD256,
26101 IX86_BUILTIN_ORPS256,
26102 IX86_BUILTIN_SHUFPD256,
26103 IX86_BUILTIN_SHUFPS256,
26104 IX86_BUILTIN_SUBPD256,
26105 IX86_BUILTIN_SUBPS256,
26106 IX86_BUILTIN_XORPD256,
26107 IX86_BUILTIN_XORPS256,
26108 IX86_BUILTIN_CMPSD,
26109 IX86_BUILTIN_CMPSS,
26110 IX86_BUILTIN_CMPPD,
26111 IX86_BUILTIN_CMPPS,
26112 IX86_BUILTIN_CMPPD256,
26113 IX86_BUILTIN_CMPPS256,
26114 IX86_BUILTIN_CVTDQ2PD256,
26115 IX86_BUILTIN_CVTDQ2PS256,
26116 IX86_BUILTIN_CVTPD2PS256,
26117 IX86_BUILTIN_CVTPS2DQ256,
26118 IX86_BUILTIN_CVTPS2PD256,
26119 IX86_BUILTIN_CVTTPD2DQ256,
26120 IX86_BUILTIN_CVTPD2DQ256,
26121 IX86_BUILTIN_CVTTPS2DQ256,
26122 IX86_BUILTIN_EXTRACTF128PD256,
26123 IX86_BUILTIN_EXTRACTF128PS256,
26124 IX86_BUILTIN_EXTRACTF128SI256,
26125 IX86_BUILTIN_VZEROALL,
26126 IX86_BUILTIN_VZEROUPPER,
26127 IX86_BUILTIN_VPERMILVARPD,
26128 IX86_BUILTIN_VPERMILVARPS,
26129 IX86_BUILTIN_VPERMILVARPD256,
26130 IX86_BUILTIN_VPERMILVARPS256,
26131 IX86_BUILTIN_VPERMILPD,
26132 IX86_BUILTIN_VPERMILPS,
26133 IX86_BUILTIN_VPERMILPD256,
26134 IX86_BUILTIN_VPERMILPS256,
26135 IX86_BUILTIN_VPERMIL2PD,
26136 IX86_BUILTIN_VPERMIL2PS,
26137 IX86_BUILTIN_VPERMIL2PD256,
26138 IX86_BUILTIN_VPERMIL2PS256,
26139 IX86_BUILTIN_VPERM2F128PD256,
26140 IX86_BUILTIN_VPERM2F128PS256,
26141 IX86_BUILTIN_VPERM2F128SI256,
26142 IX86_BUILTIN_VBROADCASTSS,
26143 IX86_BUILTIN_VBROADCASTSD256,
26144 IX86_BUILTIN_VBROADCASTSS256,
26145 IX86_BUILTIN_VBROADCASTPD256,
26146 IX86_BUILTIN_VBROADCASTPS256,
26147 IX86_BUILTIN_VINSERTF128PD256,
26148 IX86_BUILTIN_VINSERTF128PS256,
26149 IX86_BUILTIN_VINSERTF128SI256,
26150 IX86_BUILTIN_LOADUPD256,
26151 IX86_BUILTIN_LOADUPS256,
26152 IX86_BUILTIN_STOREUPD256,
26153 IX86_BUILTIN_STOREUPS256,
26154 IX86_BUILTIN_LDDQU256,
26155 IX86_BUILTIN_MOVNTDQ256,
26156 IX86_BUILTIN_MOVNTPD256,
26157 IX86_BUILTIN_MOVNTPS256,
26158 IX86_BUILTIN_LOADDQU256,
26159 IX86_BUILTIN_STOREDQU256,
26160 IX86_BUILTIN_MASKLOADPD,
26161 IX86_BUILTIN_MASKLOADPS,
26162 IX86_BUILTIN_MASKSTOREPD,
26163 IX86_BUILTIN_MASKSTOREPS,
26164 IX86_BUILTIN_MASKLOADPD256,
26165 IX86_BUILTIN_MASKLOADPS256,
26166 IX86_BUILTIN_MASKSTOREPD256,
26167 IX86_BUILTIN_MASKSTOREPS256,
26168 IX86_BUILTIN_MOVSHDUP256,
26169 IX86_BUILTIN_MOVSLDUP256,
26170 IX86_BUILTIN_MOVDDUP256,
26172 IX86_BUILTIN_SQRTPD256,
26173 IX86_BUILTIN_SQRTPS256,
26174 IX86_BUILTIN_SQRTPS_NR256,
26175 IX86_BUILTIN_RSQRTPS256,
26176 IX86_BUILTIN_RSQRTPS_NR256,
26178 IX86_BUILTIN_RCPPS256,
26180 IX86_BUILTIN_ROUNDPD256,
26181 IX86_BUILTIN_ROUNDPS256,
26183 IX86_BUILTIN_FLOORPD256,
26184 IX86_BUILTIN_CEILPD256,
26185 IX86_BUILTIN_TRUNCPD256,
26186 IX86_BUILTIN_RINTPD256,
26187 IX86_BUILTIN_ROUNDPD_AZ256,
26189 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26190 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26191 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26193 IX86_BUILTIN_FLOORPS256,
26194 IX86_BUILTIN_CEILPS256,
26195 IX86_BUILTIN_TRUNCPS256,
26196 IX86_BUILTIN_RINTPS256,
26197 IX86_BUILTIN_ROUNDPS_AZ256,
26199 IX86_BUILTIN_FLOORPS_SFIX256,
26200 IX86_BUILTIN_CEILPS_SFIX256,
26201 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26203 IX86_BUILTIN_UNPCKHPD256,
26204 IX86_BUILTIN_UNPCKLPD256,
26205 IX86_BUILTIN_UNPCKHPS256,
26206 IX86_BUILTIN_UNPCKLPS256,
26208 IX86_BUILTIN_SI256_SI,
26209 IX86_BUILTIN_PS256_PS,
26210 IX86_BUILTIN_PD256_PD,
26211 IX86_BUILTIN_SI_SI256,
26212 IX86_BUILTIN_PS_PS256,
26213 IX86_BUILTIN_PD_PD256,
26215 IX86_BUILTIN_VTESTZPD,
26216 IX86_BUILTIN_VTESTCPD,
26217 IX86_BUILTIN_VTESTNZCPD,
26218 IX86_BUILTIN_VTESTZPS,
26219 IX86_BUILTIN_VTESTCPS,
26220 IX86_BUILTIN_VTESTNZCPS,
26221 IX86_BUILTIN_VTESTZPD256,
26222 IX86_BUILTIN_VTESTCPD256,
26223 IX86_BUILTIN_VTESTNZCPD256,
26224 IX86_BUILTIN_VTESTZPS256,
26225 IX86_BUILTIN_VTESTCPS256,
26226 IX86_BUILTIN_VTESTNZCPS256,
26227 IX86_BUILTIN_PTESTZ256,
26228 IX86_BUILTIN_PTESTC256,
26229 IX86_BUILTIN_PTESTNZC256,
26231 IX86_BUILTIN_MOVMSKPD256,
26232 IX86_BUILTIN_MOVMSKPS256,
26234 /* AVX2 */
26235 IX86_BUILTIN_MPSADBW256,
26236 IX86_BUILTIN_PABSB256,
26237 IX86_BUILTIN_PABSW256,
26238 IX86_BUILTIN_PABSD256,
26239 IX86_BUILTIN_PACKSSDW256,
26240 IX86_BUILTIN_PACKSSWB256,
26241 IX86_BUILTIN_PACKUSDW256,
26242 IX86_BUILTIN_PACKUSWB256,
26243 IX86_BUILTIN_PADDB256,
26244 IX86_BUILTIN_PADDW256,
26245 IX86_BUILTIN_PADDD256,
26246 IX86_BUILTIN_PADDQ256,
26247 IX86_BUILTIN_PADDSB256,
26248 IX86_BUILTIN_PADDSW256,
26249 IX86_BUILTIN_PADDUSB256,
26250 IX86_BUILTIN_PADDUSW256,
26251 IX86_BUILTIN_PALIGNR256,
26252 IX86_BUILTIN_AND256I,
26253 IX86_BUILTIN_ANDNOT256I,
26254 IX86_BUILTIN_PAVGB256,
26255 IX86_BUILTIN_PAVGW256,
26256 IX86_BUILTIN_PBLENDVB256,
26257 IX86_BUILTIN_PBLENDVW256,
26258 IX86_BUILTIN_PCMPEQB256,
26259 IX86_BUILTIN_PCMPEQW256,
26260 IX86_BUILTIN_PCMPEQD256,
26261 IX86_BUILTIN_PCMPEQQ256,
26262 IX86_BUILTIN_PCMPGTB256,
26263 IX86_BUILTIN_PCMPGTW256,
26264 IX86_BUILTIN_PCMPGTD256,
26265 IX86_BUILTIN_PCMPGTQ256,
26266 IX86_BUILTIN_PHADDW256,
26267 IX86_BUILTIN_PHADDD256,
26268 IX86_BUILTIN_PHADDSW256,
26269 IX86_BUILTIN_PHSUBW256,
26270 IX86_BUILTIN_PHSUBD256,
26271 IX86_BUILTIN_PHSUBSW256,
26272 IX86_BUILTIN_PMADDUBSW256,
26273 IX86_BUILTIN_PMADDWD256,
26274 IX86_BUILTIN_PMAXSB256,
26275 IX86_BUILTIN_PMAXSW256,
26276 IX86_BUILTIN_PMAXSD256,
26277 IX86_BUILTIN_PMAXUB256,
26278 IX86_BUILTIN_PMAXUW256,
26279 IX86_BUILTIN_PMAXUD256,
26280 IX86_BUILTIN_PMINSB256,
26281 IX86_BUILTIN_PMINSW256,
26282 IX86_BUILTIN_PMINSD256,
26283 IX86_BUILTIN_PMINUB256,
26284 IX86_BUILTIN_PMINUW256,
26285 IX86_BUILTIN_PMINUD256,
26286 IX86_BUILTIN_PMOVMSKB256,
26287 IX86_BUILTIN_PMOVSXBW256,
26288 IX86_BUILTIN_PMOVSXBD256,
26289 IX86_BUILTIN_PMOVSXBQ256,
26290 IX86_BUILTIN_PMOVSXWD256,
26291 IX86_BUILTIN_PMOVSXWQ256,
26292 IX86_BUILTIN_PMOVSXDQ256,
26293 IX86_BUILTIN_PMOVZXBW256,
26294 IX86_BUILTIN_PMOVZXBD256,
26295 IX86_BUILTIN_PMOVZXBQ256,
26296 IX86_BUILTIN_PMOVZXWD256,
26297 IX86_BUILTIN_PMOVZXWQ256,
26298 IX86_BUILTIN_PMOVZXDQ256,
26299 IX86_BUILTIN_PMULDQ256,
26300 IX86_BUILTIN_PMULHRSW256,
26301 IX86_BUILTIN_PMULHUW256,
26302 IX86_BUILTIN_PMULHW256,
26303 IX86_BUILTIN_PMULLW256,
26304 IX86_BUILTIN_PMULLD256,
26305 IX86_BUILTIN_PMULUDQ256,
26306 IX86_BUILTIN_POR256,
26307 IX86_BUILTIN_PSADBW256,
26308 IX86_BUILTIN_PSHUFB256,
26309 IX86_BUILTIN_PSHUFD256,
26310 IX86_BUILTIN_PSHUFHW256,
26311 IX86_BUILTIN_PSHUFLW256,
26312 IX86_BUILTIN_PSIGNB256,
26313 IX86_BUILTIN_PSIGNW256,
26314 IX86_BUILTIN_PSIGND256,
26315 IX86_BUILTIN_PSLLDQI256,
26316 IX86_BUILTIN_PSLLWI256,
26317 IX86_BUILTIN_PSLLW256,
26318 IX86_BUILTIN_PSLLDI256,
26319 IX86_BUILTIN_PSLLD256,
26320 IX86_BUILTIN_PSLLQI256,
26321 IX86_BUILTIN_PSLLQ256,
26322 IX86_BUILTIN_PSRAWI256,
26323 IX86_BUILTIN_PSRAW256,
26324 IX86_BUILTIN_PSRADI256,
26325 IX86_BUILTIN_PSRAD256,
26326 IX86_BUILTIN_PSRLDQI256,
26327 IX86_BUILTIN_PSRLWI256,
26328 IX86_BUILTIN_PSRLW256,
26329 IX86_BUILTIN_PSRLDI256,
26330 IX86_BUILTIN_PSRLD256,
26331 IX86_BUILTIN_PSRLQI256,
26332 IX86_BUILTIN_PSRLQ256,
26333 IX86_BUILTIN_PSUBB256,
26334 IX86_BUILTIN_PSUBW256,
26335 IX86_BUILTIN_PSUBD256,
26336 IX86_BUILTIN_PSUBQ256,
26337 IX86_BUILTIN_PSUBSB256,
26338 IX86_BUILTIN_PSUBSW256,
26339 IX86_BUILTIN_PSUBUSB256,
26340 IX86_BUILTIN_PSUBUSW256,
26341 IX86_BUILTIN_PUNPCKHBW256,
26342 IX86_BUILTIN_PUNPCKHWD256,
26343 IX86_BUILTIN_PUNPCKHDQ256,
26344 IX86_BUILTIN_PUNPCKHQDQ256,
26345 IX86_BUILTIN_PUNPCKLBW256,
26346 IX86_BUILTIN_PUNPCKLWD256,
26347 IX86_BUILTIN_PUNPCKLDQ256,
26348 IX86_BUILTIN_PUNPCKLQDQ256,
26349 IX86_BUILTIN_PXOR256,
26350 IX86_BUILTIN_MOVNTDQA256,
26351 IX86_BUILTIN_VBROADCASTSS_PS,
26352 IX86_BUILTIN_VBROADCASTSS_PS256,
26353 IX86_BUILTIN_VBROADCASTSD_PD256,
26354 IX86_BUILTIN_VBROADCASTSI256,
26355 IX86_BUILTIN_PBLENDD256,
26356 IX86_BUILTIN_PBLENDD128,
26357 IX86_BUILTIN_PBROADCASTB256,
26358 IX86_BUILTIN_PBROADCASTW256,
26359 IX86_BUILTIN_PBROADCASTD256,
26360 IX86_BUILTIN_PBROADCASTQ256,
26361 IX86_BUILTIN_PBROADCASTB128,
26362 IX86_BUILTIN_PBROADCASTW128,
26363 IX86_BUILTIN_PBROADCASTD128,
26364 IX86_BUILTIN_PBROADCASTQ128,
26365 IX86_BUILTIN_VPERMVARSI256,
26366 IX86_BUILTIN_VPERMDF256,
26367 IX86_BUILTIN_VPERMVARSF256,
26368 IX86_BUILTIN_VPERMDI256,
26369 IX86_BUILTIN_VPERMTI256,
26370 IX86_BUILTIN_VEXTRACT128I256,
26371 IX86_BUILTIN_VINSERT128I256,
26372 IX86_BUILTIN_MASKLOADD,
26373 IX86_BUILTIN_MASKLOADQ,
26374 IX86_BUILTIN_MASKLOADD256,
26375 IX86_BUILTIN_MASKLOADQ256,
26376 IX86_BUILTIN_MASKSTORED,
26377 IX86_BUILTIN_MASKSTOREQ,
26378 IX86_BUILTIN_MASKSTORED256,
26379 IX86_BUILTIN_MASKSTOREQ256,
26380 IX86_BUILTIN_PSLLVV4DI,
26381 IX86_BUILTIN_PSLLVV2DI,
26382 IX86_BUILTIN_PSLLVV8SI,
26383 IX86_BUILTIN_PSLLVV4SI,
26384 IX86_BUILTIN_PSRAVV8SI,
26385 IX86_BUILTIN_PSRAVV4SI,
26386 IX86_BUILTIN_PSRLVV4DI,
26387 IX86_BUILTIN_PSRLVV2DI,
26388 IX86_BUILTIN_PSRLVV8SI,
26389 IX86_BUILTIN_PSRLVV4SI,
26391 IX86_BUILTIN_GATHERSIV2DF,
26392 IX86_BUILTIN_GATHERSIV4DF,
26393 IX86_BUILTIN_GATHERDIV2DF,
26394 IX86_BUILTIN_GATHERDIV4DF,
26395 IX86_BUILTIN_GATHERSIV4SF,
26396 IX86_BUILTIN_GATHERSIV8SF,
26397 IX86_BUILTIN_GATHERDIV4SF,
26398 IX86_BUILTIN_GATHERDIV8SF,
26399 IX86_BUILTIN_GATHERSIV2DI,
26400 IX86_BUILTIN_GATHERSIV4DI,
26401 IX86_BUILTIN_GATHERDIV2DI,
26402 IX86_BUILTIN_GATHERDIV4DI,
26403 IX86_BUILTIN_GATHERSIV4SI,
26404 IX86_BUILTIN_GATHERSIV8SI,
26405 IX86_BUILTIN_GATHERDIV4SI,
26406 IX86_BUILTIN_GATHERDIV8SI,
26408 /* Alternate 4 element gather for the vectorizer where
26409 all operands are 32-byte wide. */
26410 IX86_BUILTIN_GATHERALTSIV4DF,
26411 IX86_BUILTIN_GATHERALTDIV8SF,
26412 IX86_BUILTIN_GATHERALTSIV4DI,
26413 IX86_BUILTIN_GATHERALTDIV8SI,
26415 /* TFmode support builtins. */
26416 IX86_BUILTIN_INFQ,
26417 IX86_BUILTIN_HUGE_VALQ,
26418 IX86_BUILTIN_FABSQ,
26419 IX86_BUILTIN_COPYSIGNQ,
26421 /* Vectorizer support builtins. */
26422 IX86_BUILTIN_CPYSGNPS,
26423 IX86_BUILTIN_CPYSGNPD,
26424 IX86_BUILTIN_CPYSGNPS256,
26425 IX86_BUILTIN_CPYSGNPD256,
26427 /* FMA4 instructions. */
26428 IX86_BUILTIN_VFMADDSS,
26429 IX86_BUILTIN_VFMADDSD,
26430 IX86_BUILTIN_VFMADDPS,
26431 IX86_BUILTIN_VFMADDPD,
26432 IX86_BUILTIN_VFMADDPS256,
26433 IX86_BUILTIN_VFMADDPD256,
26434 IX86_BUILTIN_VFMADDSUBPS,
26435 IX86_BUILTIN_VFMADDSUBPD,
26436 IX86_BUILTIN_VFMADDSUBPS256,
26437 IX86_BUILTIN_VFMADDSUBPD256,
26439 /* FMA3 instructions. */
26440 IX86_BUILTIN_VFMADDSS3,
26441 IX86_BUILTIN_VFMADDSD3,
26443 /* XOP instructions. */
26444 IX86_BUILTIN_VPCMOV,
26445 IX86_BUILTIN_VPCMOV_V2DI,
26446 IX86_BUILTIN_VPCMOV_V4SI,
26447 IX86_BUILTIN_VPCMOV_V8HI,
26448 IX86_BUILTIN_VPCMOV_V16QI,
26449 IX86_BUILTIN_VPCMOV_V4SF,
26450 IX86_BUILTIN_VPCMOV_V2DF,
26451 IX86_BUILTIN_VPCMOV256,
26452 IX86_BUILTIN_VPCMOV_V4DI256,
26453 IX86_BUILTIN_VPCMOV_V8SI256,
26454 IX86_BUILTIN_VPCMOV_V16HI256,
26455 IX86_BUILTIN_VPCMOV_V32QI256,
26456 IX86_BUILTIN_VPCMOV_V8SF256,
26457 IX86_BUILTIN_VPCMOV_V4DF256,
26459 IX86_BUILTIN_VPPERM,
26461 IX86_BUILTIN_VPMACSSWW,
26462 IX86_BUILTIN_VPMACSWW,
26463 IX86_BUILTIN_VPMACSSWD,
26464 IX86_BUILTIN_VPMACSWD,
26465 IX86_BUILTIN_VPMACSSDD,
26466 IX86_BUILTIN_VPMACSDD,
26467 IX86_BUILTIN_VPMACSSDQL,
26468 IX86_BUILTIN_VPMACSSDQH,
26469 IX86_BUILTIN_VPMACSDQL,
26470 IX86_BUILTIN_VPMACSDQH,
26471 IX86_BUILTIN_VPMADCSSWD,
26472 IX86_BUILTIN_VPMADCSWD,
26474 IX86_BUILTIN_VPHADDBW,
26475 IX86_BUILTIN_VPHADDBD,
26476 IX86_BUILTIN_VPHADDBQ,
26477 IX86_BUILTIN_VPHADDWD,
26478 IX86_BUILTIN_VPHADDWQ,
26479 IX86_BUILTIN_VPHADDDQ,
26480 IX86_BUILTIN_VPHADDUBW,
26481 IX86_BUILTIN_VPHADDUBD,
26482 IX86_BUILTIN_VPHADDUBQ,
26483 IX86_BUILTIN_VPHADDUWD,
26484 IX86_BUILTIN_VPHADDUWQ,
26485 IX86_BUILTIN_VPHADDUDQ,
26486 IX86_BUILTIN_VPHSUBBW,
26487 IX86_BUILTIN_VPHSUBWD,
26488 IX86_BUILTIN_VPHSUBDQ,
26490 IX86_BUILTIN_VPROTB,
26491 IX86_BUILTIN_VPROTW,
26492 IX86_BUILTIN_VPROTD,
26493 IX86_BUILTIN_VPROTQ,
26494 IX86_BUILTIN_VPROTB_IMM,
26495 IX86_BUILTIN_VPROTW_IMM,
26496 IX86_BUILTIN_VPROTD_IMM,
26497 IX86_BUILTIN_VPROTQ_IMM,
26499 IX86_BUILTIN_VPSHLB,
26500 IX86_BUILTIN_VPSHLW,
26501 IX86_BUILTIN_VPSHLD,
26502 IX86_BUILTIN_VPSHLQ,
26503 IX86_BUILTIN_VPSHAB,
26504 IX86_BUILTIN_VPSHAW,
26505 IX86_BUILTIN_VPSHAD,
26506 IX86_BUILTIN_VPSHAQ,
26508 IX86_BUILTIN_VFRCZSS,
26509 IX86_BUILTIN_VFRCZSD,
26510 IX86_BUILTIN_VFRCZPS,
26511 IX86_BUILTIN_VFRCZPD,
26512 IX86_BUILTIN_VFRCZPS256,
26513 IX86_BUILTIN_VFRCZPD256,
26515 IX86_BUILTIN_VPCOMEQUB,
26516 IX86_BUILTIN_VPCOMNEUB,
26517 IX86_BUILTIN_VPCOMLTUB,
26518 IX86_BUILTIN_VPCOMLEUB,
26519 IX86_BUILTIN_VPCOMGTUB,
26520 IX86_BUILTIN_VPCOMGEUB,
26521 IX86_BUILTIN_VPCOMFALSEUB,
26522 IX86_BUILTIN_VPCOMTRUEUB,
26524 IX86_BUILTIN_VPCOMEQUW,
26525 IX86_BUILTIN_VPCOMNEUW,
26526 IX86_BUILTIN_VPCOMLTUW,
26527 IX86_BUILTIN_VPCOMLEUW,
26528 IX86_BUILTIN_VPCOMGTUW,
26529 IX86_BUILTIN_VPCOMGEUW,
26530 IX86_BUILTIN_VPCOMFALSEUW,
26531 IX86_BUILTIN_VPCOMTRUEUW,
26533 IX86_BUILTIN_VPCOMEQUD,
26534 IX86_BUILTIN_VPCOMNEUD,
26535 IX86_BUILTIN_VPCOMLTUD,
26536 IX86_BUILTIN_VPCOMLEUD,
26537 IX86_BUILTIN_VPCOMGTUD,
26538 IX86_BUILTIN_VPCOMGEUD,
26539 IX86_BUILTIN_VPCOMFALSEUD,
26540 IX86_BUILTIN_VPCOMTRUEUD,
26542 IX86_BUILTIN_VPCOMEQUQ,
26543 IX86_BUILTIN_VPCOMNEUQ,
26544 IX86_BUILTIN_VPCOMLTUQ,
26545 IX86_BUILTIN_VPCOMLEUQ,
26546 IX86_BUILTIN_VPCOMGTUQ,
26547 IX86_BUILTIN_VPCOMGEUQ,
26548 IX86_BUILTIN_VPCOMFALSEUQ,
26549 IX86_BUILTIN_VPCOMTRUEUQ,
26551 IX86_BUILTIN_VPCOMEQB,
26552 IX86_BUILTIN_VPCOMNEB,
26553 IX86_BUILTIN_VPCOMLTB,
26554 IX86_BUILTIN_VPCOMLEB,
26555 IX86_BUILTIN_VPCOMGTB,
26556 IX86_BUILTIN_VPCOMGEB,
26557 IX86_BUILTIN_VPCOMFALSEB,
26558 IX86_BUILTIN_VPCOMTRUEB,
26560 IX86_BUILTIN_VPCOMEQW,
26561 IX86_BUILTIN_VPCOMNEW,
26562 IX86_BUILTIN_VPCOMLTW,
26563 IX86_BUILTIN_VPCOMLEW,
26564 IX86_BUILTIN_VPCOMGTW,
26565 IX86_BUILTIN_VPCOMGEW,
26566 IX86_BUILTIN_VPCOMFALSEW,
26567 IX86_BUILTIN_VPCOMTRUEW,
26569 IX86_BUILTIN_VPCOMEQD,
26570 IX86_BUILTIN_VPCOMNED,
26571 IX86_BUILTIN_VPCOMLTD,
26572 IX86_BUILTIN_VPCOMLED,
26573 IX86_BUILTIN_VPCOMGTD,
26574 IX86_BUILTIN_VPCOMGED,
26575 IX86_BUILTIN_VPCOMFALSED,
26576 IX86_BUILTIN_VPCOMTRUED,
26578 IX86_BUILTIN_VPCOMEQQ,
26579 IX86_BUILTIN_VPCOMNEQ,
26580 IX86_BUILTIN_VPCOMLTQ,
26581 IX86_BUILTIN_VPCOMLEQ,
26582 IX86_BUILTIN_VPCOMGTQ,
26583 IX86_BUILTIN_VPCOMGEQ,
26584 IX86_BUILTIN_VPCOMFALSEQ,
26585 IX86_BUILTIN_VPCOMTRUEQ,
26587 /* LWP instructions. */
26588 IX86_BUILTIN_LLWPCB,
26589 IX86_BUILTIN_SLWPCB,
26590 IX86_BUILTIN_LWPVAL32,
26591 IX86_BUILTIN_LWPVAL64,
26592 IX86_BUILTIN_LWPINS32,
26593 IX86_BUILTIN_LWPINS64,
26595 IX86_BUILTIN_CLZS,
26597 /* RTM */
26598 IX86_BUILTIN_XBEGIN,
26599 IX86_BUILTIN_XEND,
26600 IX86_BUILTIN_XABORT,
26601 IX86_BUILTIN_XTEST,
26603 /* BMI instructions. */
26604 IX86_BUILTIN_BEXTR32,
26605 IX86_BUILTIN_BEXTR64,
26606 IX86_BUILTIN_CTZS,
26608 /* TBM instructions. */
26609 IX86_BUILTIN_BEXTRI32,
26610 IX86_BUILTIN_BEXTRI64,
26612 /* BMI2 instructions. */
26613 IX86_BUILTIN_BZHI32,
26614 IX86_BUILTIN_BZHI64,
26615 IX86_BUILTIN_PDEP32,
26616 IX86_BUILTIN_PDEP64,
26617 IX86_BUILTIN_PEXT32,
26618 IX86_BUILTIN_PEXT64,
26620 /* ADX instructions. */
26621 IX86_BUILTIN_ADDCARRYX32,
26622 IX86_BUILTIN_ADDCARRYX64,
26624 /* FSGSBASE instructions. */
26625 IX86_BUILTIN_RDFSBASE32,
26626 IX86_BUILTIN_RDFSBASE64,
26627 IX86_BUILTIN_RDGSBASE32,
26628 IX86_BUILTIN_RDGSBASE64,
26629 IX86_BUILTIN_WRFSBASE32,
26630 IX86_BUILTIN_WRFSBASE64,
26631 IX86_BUILTIN_WRGSBASE32,
26632 IX86_BUILTIN_WRGSBASE64,
26634 /* RDRND instructions. */
26635 IX86_BUILTIN_RDRAND16_STEP,
26636 IX86_BUILTIN_RDRAND32_STEP,
26637 IX86_BUILTIN_RDRAND64_STEP,
26639 /* RDSEED instructions. */
26640 IX86_BUILTIN_RDSEED16_STEP,
26641 IX86_BUILTIN_RDSEED32_STEP,
26642 IX86_BUILTIN_RDSEED64_STEP,
26644 /* F16C instructions. */
26645 IX86_BUILTIN_CVTPH2PS,
26646 IX86_BUILTIN_CVTPH2PS256,
26647 IX86_BUILTIN_CVTPS2PH,
26648 IX86_BUILTIN_CVTPS2PH256,
26650 /* CFString built-in for darwin */
26651 IX86_BUILTIN_CFSTRING,
26653 /* Builtins to get CPU type and supported features. */
26654 IX86_BUILTIN_CPU_INIT,
26655 IX86_BUILTIN_CPU_IS,
26656 IX86_BUILTIN_CPU_SUPPORTS,
26658 IX86_BUILTIN_MAX
26659 };
26661 /* Table for the ix86 builtin decls. */
26664 /* Table of all of the builtin functions that are possible with different ISA's
26665 but are waiting to be built until a function is declared to use that
26666 ISA. */
26673 };
26678 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26679 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26680 function decl in the ix86_builtins array. Returns the function decl or
26681 NULL_TREE, if the builtin was not added.
26683 If the front end has a special hook for builtin functions, delay adding
26684 builtin functions that aren't in the current ISA until the ISA is changed
26685 with function specific optimization. Doing so, can save about 300K for the
26686 default compiler. When the builtin is expanded, check at that time whether
26687 it is valid.
26689 If the front end doesn't have a special hook, record all builtins, even if
26690 it isn't an instruction set in the current ISA in case the user uses
26691 function specific options for a different ISA, so that we don't get scope
26692 errors if a builtin is added in the middle of a function scope. */
26698 {
26702 {
26711 {
26717 }
26718 else
26719 {
26725 }
26726 }
26729 }
26731 /* Like def_builtin, but also marks the function decl "const". */
26736 {
26740 else
26744 }
26746 /* Add any new builtin functions for a given ISA that may not have been
26747 declared. This saves a bit of space compared to adding all of the
26748 declarations to the tree, even if we didn't use them. */
26750 static void
26752 {
26756 {
26759 {
26762 /* Don't define the builtin again. */
26768 NULL_TREE);
26773 }
26774 }
26775 }
26777 /* Bits for builtin_description.flag. */
26779 /* Set when we don't support the comparison natively, and should
26780 swap_comparison in order to support it. */
26781 #define BUILTIN_DESC_SWAP_OPERANDS 1
26783 struct builtin_description
26784 {
26791 };
26794 {
26795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26819 };
26822 {
26823 /* SSE4.2 */
26824 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26825 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26826 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26827 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26828 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26829 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26830 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26831 };
26834 {
26835 /* SSE4.2 */
26836 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26837 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26838 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26839 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26840 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26841 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26842 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26843 };
26845 /* Special builtins with variable number of arguments. */
26847 {
26848 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26849 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26850 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26852 /* MMX */
26853 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26855 /* 3DNow! */
26856 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26858 /* FXSR, XSAVE and XSAVEOPT */
26859 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26860 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26861 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26862 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26863 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26865 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26866 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26867 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26868 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26869 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26871 /* SSE */
26872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26881 /* SSE or 3DNow!A */
26882 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26883 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26885 /* SSE2 */
26886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26893 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26900 /* SSE3 */
26901 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26903 /* SSE4.1 */
26904 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26906 /* SSE4A */
26907 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26908 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26910 /* AVX */
26911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26916 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26922 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26923 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26926 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26932 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26934 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26938 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26939 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26941 /* AVX2 */
26942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26952 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26953 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26954 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26955 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26956 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26957 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26959 /* FSGSBASE */
26960 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26961 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26962 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26963 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26964 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26965 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26966 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26967 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26969 /* RTM */
26970 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26971 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26972 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26973 };
26975 /* Builtins with variable number of arguments. */
26977 {
26978 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26979 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26980 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26981 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26982 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26983 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26984 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26986 /* MMX */
26987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27050 /* 3DNow! */
27051 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27052 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27053 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27054 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27056 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27057 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27058 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27059 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27060 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27061 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27072 /* 3DNow!A */
27073 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27074 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27075 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27076 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27077 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27078 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27080 /* SSE */
27081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27083 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27089 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27092 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27135 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27142 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27143 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27144 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27146 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27148 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27150 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27154 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27156 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27157 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27159 /* SSE MMX or 3Dnow!A */
27160 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27161 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27162 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27164 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27165 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27166 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27167 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27169 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27170 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27172 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27174 /* SSE2 */
27175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27181 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27193 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27194 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27286 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27289 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27291 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27296 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27311 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27332 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27333 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27342 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27344 /* SSE2 MMX */
27345 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27346 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27348 /* SSE3 */
27349 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27350 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27352 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27353 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27354 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27355 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27356 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27357 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27359 /* SSSE3 */
27360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27361 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27362 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27365 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27392 /* SSSE3. */
27393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27396 /* SSE4.1 */
27397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27435 /* SSE4.1 */
27436 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27437 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27438 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27439 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27441 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27442 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27443 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27444 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27447 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27449 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27450 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27452 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27453 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27458 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27460 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27461 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27463 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27465 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27467 /* SSE4.2 */
27468 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27469 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27470 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27471 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27472 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27474 /* SSE4A */
27475 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27476 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27477 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27478 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27480 /* AES */
27481 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27482 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27484 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27485 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27486 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27487 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27489 /* PCLMUL */
27490 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27492 /* AVX */
27493 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27494 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27495 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27501 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27581 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27606 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27631 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27633 /* AVX2 */
27634 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27635 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27636 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27781 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27783 /* BMI */
27784 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27785 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27786 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27788 /* TBM */
27789 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27790 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27792 /* F16C */
27793 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27794 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27795 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27796 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27798 /* BMI2 */
27799 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27800 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27801 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27802 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27803 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27804 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27805 };
27807 /* FMA4 and XOP. */
27808 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27809 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27810 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27811 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27812 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27813 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27814 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27815 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27816 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27817 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27818 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27819 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27820 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27821 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27822 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27823 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27824 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27825 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27826 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27827 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27828 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27829 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27830 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27831 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27832 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27833 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27834 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27835 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27836 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27837 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27838 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27839 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27840 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27841 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27842 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27843 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27844 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27845 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27846 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27847 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27848 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27849 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27850 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27851 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27852 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27853 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27854 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27855 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27856 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27857 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27858 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27859 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27862 {
27903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27913 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28061 };
28062 \f
28063 /* TM vector builtins. */
28065 /* Reuse the existing x86-specific `struct builtin_description' cause
28066 we're lazy. Add casts to make them fit. */
28068 {
28069 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28070 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28071 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28072 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28073 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28074 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28075 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28077 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28078 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28079 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28080 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28081 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28082 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28083 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28085 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28086 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28087 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28088 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28089 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28090 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28091 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28093 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28094 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28095 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28096 };
28098 /* TM callbacks. */
28100 /* Return the builtin decl needed to load a vector of TYPE. */
28102 static tree
28104 {
28106 {
28108 {
28115 }
28116 }
28118 }
28120 /* Return the builtin decl needed to store a vector of TYPE. */
28122 static tree
28124 {
28126 {
28128 {
28135 }
28136 }
28138 }
28139 \f
28140 /* Initialize the transactional memory vector load/store builtins. */
28142 static void
28144 {
28148 tree decl;
28155 /* If there are no builtins defined, we must be compiling in a
28156 language without trans-mem support. */
28160 /* Use whatever attributes a normal TM load has. */
28164 /* Use whatever attributes a normal TM store has. */
28168 /* Use whatever attributes a normal TM log has. */
28176 {
28180 {
28188 {
28191 }
28193 {
28196 }
28197 else
28198 {
28201 }
28203 /* The builtin without the prefix for
28204 calling it directly. */
28206 attrs);
28207 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28208 set the TYPE_ATTRIBUTES. */
28212 }
28213 }
28214 }
28216 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28217 in the current target ISA to allow the user to compile particular modules
28218 with different target specific options that differ from the command line
28219 options. */
28220 static void
28222 {
28227 /* Add all special builtins with variable number of operands. */
28231 {
28237 }
28239 /* Add all builtins with variable number of operands. */
28243 {
28249 }
28251 /* pcmpestr[im] insns. */
28255 {
28258 else
28261 }
28263 /* pcmpistr[im] insns. */
28267 {
28270 else
28273 }
28275 /* comi/ucomi insns. */
28277 {
28280 else
28283 }
28285 /* SSE */
28291 /* SSE or 3DNow!A */
28294 IX86_BUILTIN_MASKMOVQ);
28296 /* SSE2 */
28305 /* SSE3. */
28311 /* AES */
28325 /* PCLMUL */
28329 /* RDRND */
28336 IX86_BUILTIN_RDRAND64_STEP);
28338 /* AVX2 */
28340 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28341 IX86_BUILTIN_GATHERSIV2DF);
28344 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28345 IX86_BUILTIN_GATHERSIV4DF);
28348 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28349 IX86_BUILTIN_GATHERDIV2DF);
28352 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28353 IX86_BUILTIN_GATHERDIV4DF);
28356 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28357 IX86_BUILTIN_GATHERSIV4SF);
28360 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28361 IX86_BUILTIN_GATHERSIV8SF);
28364 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28365 IX86_BUILTIN_GATHERDIV4SF);
28368 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28369 IX86_BUILTIN_GATHERDIV8SF);
28372 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28373 IX86_BUILTIN_GATHERSIV2DI);
28376 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28377 IX86_BUILTIN_GATHERSIV4DI);
28380 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28381 IX86_BUILTIN_GATHERDIV2DI);
28384 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28385 IX86_BUILTIN_GATHERDIV4DI);
28388 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28389 IX86_BUILTIN_GATHERSIV4SI);
28392 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28393 IX86_BUILTIN_GATHERSIV8SI);
28396 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28397 IX86_BUILTIN_GATHERDIV4SI);
28400 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28401 IX86_BUILTIN_GATHERDIV8SI);
28404 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28405 IX86_BUILTIN_GATHERALTSIV4DF);
28408 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28409 IX86_BUILTIN_GATHERALTDIV8SF);
28412 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28413 IX86_BUILTIN_GATHERALTSIV4DI);
28416 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28417 IX86_BUILTIN_GATHERALTDIV8SI);
28419 /* RTM. */
28423 /* MMX access to the vec_init patterns. */
28428 V4HI_FTYPE_HI_HI_HI_HI,
28429 IX86_BUILTIN_VEC_INIT_V4HI);
28432 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28433 IX86_BUILTIN_VEC_INIT_V8QI);
28435 /* Access to the vec_extract patterns. */
28457 /* Access to the vec_set patterns. */
28478 /* RDSEED */
28487 /* ADCX */
28492 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28493 IX86_BUILTIN_ADDCARRYX64);
28495 /* Add FMA4 multi-arg argument instructions */
28497 {
28503 }
28504 }
28506 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28507 to return a pointer to VERSION_DECL if the outcome of the expression
28508 formed by PREDICATE_CHAIN is true. This function will be called during
28509 version dispatch to decide which function version to execute. It returns
28510 the basic block at the end, to which more conditions can be added. */
28512 static basic_block
28515 {
28516 gimple return_stmt;
28518 gimple convert_stmt;
28519 gimple call_cond_stmt;
28520 gimple if_else_stmt;
28526 gimple_seq gseq;
28543 {
28551 }
28554 {
28569 else
28570 {
28571 gimple assign_stmt;
28572 /* Use MIN_EXPR to check if any integer is zero?.
28573 and_expr_var = min_expr <cond_var, and_expr_var> */
28581 }
28582 }
28585 integer_zero_node,
28615 }
28617 /* This parses the attribute arguments to target in DECL and determines
28618 the right builtin to use to match the platform specification.
28619 It returns the priority value for this version decl. If PREDICATE_LIST
28620 is not NULL, it stores the list of cpu features that need to be checked
28621 before dispatching this function. */
28623 static unsigned int
28625 {
28626 tree attrs;
28628 tree target_node;
28635 /* Priority of i386 features, greater value is higher priority. This is
28636 used to decide the order in which function dispatch must happen. For
28637 instance, a version specialized for SSE4.2 should be checked for dispatch
28638 before a version for SSE3, as SSE4.2 implies SSE3. */
28639 enum feature_priority
28640 {
28642 P_MMX,
28643 P_SSE,
28644 P_SSE2,
28645 P_SSE3,
28646 P_SSSE3,
28647 P_PROC_SSSE3,
28648 P_SSE4_a,
28649 P_PROC_SSE4_a,
28650 P_SSE4_1,
28651 P_SSE4_2,
28652 P_PROC_SSE4_2,
28653 P_POPCNT,
28654 P_AVX,
28655 P_AVX2,
28656 P_FMA,
28657 P_PROC_FMA
28658 };
28662 /* These are the target attribute strings for which a dispatcher is
28663 available, from fold_builtin_cpu. */
28665 static struct _feature_list
28666 {
28669 }
28671 {
28682 };
28685 static unsigned int NUM_FEATURES
28701 /* Return priority zero for default function. */
28705 /* Handle arch= if specified. For priority, set it to be 1 more than
28706 the best instruction set the processor can handle. For instance, if
28707 there is a version for atom and a version for ssse3 (the highest ISA
28708 priority for atom), the atom version must be checked for dispatch
28709 before the ssse3 version. */
28711 {
28720 {
28722 {
28747 }
28748 }
28753 {
28757 }
28760 {
28762 /* For a C string literal the length includes the trailing NULL. */
28765 predicate_chain);
28766 }
28767 }
28769 /* Process feature name. */
28776 {
28777 /* Do not process "arch=" */
28779 {
28782 }
28784 {
28786 {
28788 {
28793 predicate_chain);
28794 }
28795 /* Find the maximum priority feature. */
28800 }
28801 }
28803 {
28807 }
28809 }
28813 {
28816 attrs_str);
28818 }
28820 {
28823 }
28826 }
28828 /* This compares the priority of target features in function DECL1
28829 and DECL2. It returns positive value if DECL1 is higher priority,
28830 negative value if DECL2 is higher priority and 0 if they are the
28831 same. */
28833 static int
28835 {
28840 }
28842 /* V1 and V2 point to function versions with different priorities
28843 based on the target ISA. This function compares their priorities. */
28845 static int
28847 {
28849 {
28850 tree version_decl;
28851 tree predicate_chain;
28858 }
28860 /* This function generates the dispatch function for
28861 multi-versioned functions. DISPATCH_DECL is the function which will
28862 contain the dispatch logic. FNDECLS are the function choices for
28863 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28864 in DISPATCH_DECL in which the dispatch code is generated. */
28866 static int
28870 {
28871 tree default_decl;
28872 gimple ifunc_cpu_init_stmt;
28873 gimple_seq gseq;
28875 tree ele;
28881 struct _function_version_info
28882 {
28883 tree version_decl;
28884 tree predicate_chain;
28892 /*fndecls_p is actually a vector. */
28895 /* At least one more version other than the default. */
28902 /* The first version in the vector is the default decl. */
28908 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28909 constructors, so explicity call __builtin_cpu_init here. */
28920 {
28924 /* Get attribute string, parse it and find the right predicate decl.
28925 The predicate function could be a lengthy combination of many
28926 features, like arch-type and various isa-variants. */
28933 actual_versions++;
28937 }
28939 /* Sort the versions according to descending order of dispatch priority. The
28940 priority is based on the ISA. This is not a perfect solution. There
28941 could still be ambiguity. If more than one function version is suitable
28942 to execute, which one should be dispatched? In future, allow the user
28943 to specify a dispatch priority next to the version. */
28953 /* dispatch default version at the end. */
28959 }
28961 /* Comparator function to be used in qsort routine to sort attribute
28962 specification strings to "target". */
28964 static int
28966 {
28970 }
28972 /* ARGLIST is the argument to target attribute. This function tokenizes
28973 the comma separated arguments, sorts them and returns a string which
28974 is a unique identifier for the comma separated arguments. It also
28975 replaces non-identifier characters "=,-" with "_". */
28979 {
28980 tree arg;
28989 {
28994 argnum++;
28997 argnum++;
28998 }
29003 {
29009 }
29011 /* Replace "=,-" with "_". */
29024 {
29026 i++;
29028 }
29035 {
29040 }
29045 }
29047 /* This function changes the assembler name for functions that are
29048 versions. If DECL is a function version and has a "target"
29049 attribute, it appends the attribute string to its assembler name. */
29051 static tree
29053 {
29054 tree version_attr;
29062 "Function versions cannot be marked as gnu_inline,"
29071 /* target attribute string cannot be NULL. */
29075 version_string
29086 /* Allow assembler name to be modified if already set. */
29094 }
29096 /* This function returns true if FN1 and FN2 are versions of the same function,
29097 that is, the target strings of the function decls are different. This assumes
29098 that FN1 and FN2 have the same signature. */
29100 static bool
29102 {
29114 /* At least one function decl should have the target attribute specified. */
29118 /* Diagnose missing target attribute if one of the decls is already
29119 multi-versioned. */
29121 {
29123 {
29125 {
29130 }
29133 fn2);
29136 /* Prevent diagnosing of the same error multiple times. */
29141 }
29143 }
29148 /* The sorted target strings must be different for fn1 and fn2
29149 to be versions. */
29152 else
29159 }
29161 static tree
29163 {
29164 /* For function version, add the target suffix to the assembler name. */
29168 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29170 #endif
29173 }
29175 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29176 is true, append the full path name of the source file. */
29180 {
29188 /* Get a unique name that can be used globally without any chances
29189 of collision at link time. */
29199 /* Use '.' to concatenate names as it is demangler friendly. */
29202 suffix);
29203 else
29207 }
29209 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29211 /* Make a dispatcher declaration for the multi-versioned function DECL.
29212 Calls to DECL function will be replaced with calls to the dispatcher
29213 by the front-end. Return the decl created. */
29215 static tree
29217 {
29218 tree func_decl;
29238 /* Mark this func as external, the resolver will flip it again if
29239 it gets generated. */
29241 /* This will be of type IFUNCs have to be externally visible. */
29245 }
29247 #endif
29249 /* Returns true if decl is multi-versioned and DECL is the default function,
29250 that is it is not tagged with target specific optimization. */
29252 static bool
29254 {
29263 }
29265 /* Make a dispatcher declaration for the multi-versioned function DECL.
29266 Calls to DECL function will be replaced with calls to the dispatcher
29267 by the front-end. Returns the decl of the dispatcher function. */
29269 static tree
29271 {
29280 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29284 #endif
29299 /* Find the default version and make it the first node. */
29301 /* Go to the beginnig of the chain. */
29306 {
29311 }
29313 /* If there is no default node, just return NULL. */
29317 /* Make default info the first node. */
29319 {
29326 }
29330 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29331 /* Right now, the dispatching is done via ifunc. */
29337 dispatcher_version_info
29342 /* Set the dispatcher for all the versions. */
29345 {
29348 }
29349 #else
29351 "multiversioning needs ifunc which is not supported "
29353 #endif
29355 }
29357 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29358 it to CHAIN. */
29360 static tree
29362 {
29363 tree attr_name;
29364 tree attr_arg_name;
29365 tree attr_args;
29366 tree attr;
29373 }
29375 /* Make the resolver function decl to dispatch the versions of
29376 a multi-versioned function, DEFAULT_DECL. Create an
29377 empty basic block in the resolver and store the pointer in
29378 EMPTY_BB. Return the decl of the resolver function. */
29380 static tree
29384 {
29389 /* IFUNC's have to be globally visible. So, if the default_decl is
29390 not, then the name of the IFUNC should be made unique. */
29394 /* Append the filename to the resolver function if the versions are
29395 not externally visible. This is because the resolver function has
29396 to be externally visible for the loader to find it. So, appending
29397 the filename will prevent conflicts with a resolver function from
29398 another module which is based on the same version name. */
29401 /* The resolver function should return a (void *). */
29412 /* IFUNC resolvers have to be externally visible. */
29416 /* Resolver is not external, body is generated. */
29426 {
29427 /* In this case, each translation unit with a call to this
29428 versioned function will put out a resolver. Ensure it
29429 is comdat to keep just one copy. */
29432 }
29433 /* Build result decl and add to function_decl. */
29449 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29453 /* Create the alias for dispatch to resolver here. */
29454 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29458 }
29460 /* Generate the dispatching code body to dispatch multi-versioned function
29461 DECL. The target hook is called to process the "target" attributes and
29462 provide the code to dispatch the right function at run-time. NODE points
29463 to the dispatcher decl whose body will be created. */
29465 static tree
29467 {
29468 tree resolver_decl;
29469 basic_block empty_bb;
29471 tree default_ver_decl;
29487 /* The first version in the chain corresponds to the default version. */
29490 /* node is going to be an alias, so remove the finalized bit. */
29504 {
29506 /* Check for virtual functions here again, as by this time it should
29507 have been determined if this function needs a vtable index or
29508 not. This happens for methods in derived classes that override
29509 virtual methods in base classes but are not explicitly marked as
29510 virtual. */
29515 }
29522 }
29523 /* This builds the processor_model struct type defined in
29524 libgcc/config/i386/cpuinfo.c */
29526 static tree
29528 {
29535 /* The first 3 fields are unsigned int. */
29537 {
29543 }
29545 /* The last field is an array of unsigned integers of size one. */
29556 }
29558 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29560 static tree
29562 {
29563 tree new_decl;
29566 VAR_DECL,
29568 type);
29581 }
29583 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29584 into an integer defined in libgcc/config/i386/cpuinfo.c */
29586 static tree
29588 {
29594 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29595 enum processor_features
29596 {
29598 F_MMX,
29599 F_POPCNT,
29600 F_SSE,
29601 F_SSE2,
29602 F_SSE3,
29603 F_SSSE3,
29604 F_SSE4_1,
29605 F_SSE4_2,
29606 F_AVX,
29607 F_AVX2,
29608 F_MAX
29609 };
29611 /* These are the values for vendor types and cpu types and subtypes
29612 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29613 the corresponding start value. */
29614 enum processor_model
29615 {
29617 M_AMD,
29618 M_CPU_TYPE_START,
29619 M_INTEL_ATOM,
29620 M_INTEL_CORE2,
29621 M_INTEL_COREI7,
29622 M_AMDFAM10H,
29623 M_AMDFAM15H,
29624 M_CPU_SUBTYPE_START,
29625 M_INTEL_COREI7_NEHALEM,
29626 M_INTEL_COREI7_WESTMERE,
29627 M_INTEL_COREI7_SANDYBRIDGE,
29628 M_AMDFAM10H_BARCELONA,
29629 M_AMDFAM10H_SHANGHAI,
29630 M_AMDFAM10H_ISTANBUL,
29631 M_AMDFAM15H_BDVER1,
29632 M_AMDFAM15H_BDVER2,
29633 M_AMDFAM15H_BDVER3
29634 };
29636 static struct _arch_names_table
29637 {
29640 }
29642 {
29659 };
29661 static struct _isa_names_table
29662 {
29665 }
29667 {
29679 };
29690 {
29691 /* *args must be a expr that can contain other EXPRS leading to a
29692 STRING_CST. */
29694 {
29697 }
29699 }
29704 {
29705 tree ref;
29706 tree field;
29707 tree final;
29710 unsigned int NUM_ARCH_NAMES
29719 {
29723 }
29728 /* CPU types are stored in the next field. */
29731 {
29734 }
29736 /* CPU subtypes are stored in the next field. */
29738 {
29741 }
29743 /* Get the appropriate field in __cpu_model. */
29747 /* Check the value. */
29751 }
29753 {
29754 tree ref;
29755 tree array_elt;
29756 tree field;
29757 tree final;
29760 unsigned int NUM_ISA_NAMES
29769 {
29773 }
29776 /* Get the last field, which is __cpu_features. */
29780 /* Get the appropriate field: __cpu_model.__cpu_features */
29784 /* Access the 0th element of __cpu_features array. */
29789 /* Return __cpu_model.__cpu_features[0] & field_val */
29793 }
29795 }
29797 static tree
29800 {
29802 {
29807 {
29810 }
29811 }
29813 #ifdef SUBTARGET_FOLD_BUILTIN
29815 #endif
29818 }
29820 /* Make builtins to detect cpu type and features supported. NAME is
29821 the builtin name, CODE is the builtin code, and FTYPE is the function
29822 type of the builtin. */
29824 static void
29827 {
29828 tree decl;
29829 tree type;
29837 }
29839 /* Make builtins to get CPU type and features supported. The created
29840 builtins are :
29842 __builtin_cpu_init (), to detect cpu type and features,
29843 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29844 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29845 */
29847 static void
29849 {
29856 }
29858 /* Internal method for ix86_init_builtins. */
29860 static void
29862 {
29874 sysv_va_ref =
29877 fnvoid_va_end_ms =
29879 fnvoid_va_start_ms =
29881 fnvoid_va_end_sysv =
29883 fnvoid_va_start_sysv =
29885 NULL_TREE);
29886 fnvoid_va_copy_ms =
29888 NULL_TREE);
29889 fnvoid_va_copy_sysv =
29905 }
29907 static void
29909 {
29912 /* The __float80 type. */
29915 {
29916 /* The __float80 type. */
29921 }
29924 /* The __float128 type. */
29930 /* This macro is built by i386-builtin-types.awk. */
29931 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29932 }
29934 static void
29936 {
29937 tree t;
29941 /* Builtins to get CPU type and features. */
29944 /* TFmode support builtins. */
29950 /* We will expand them to normal call if SSE isn't available since
29951 they are used by libgcc. */
29970 #ifdef SUBTARGET_INIT_BUILTINS
29971 SUBTARGET_INIT_BUILTINS;
29972 #endif
29973 }
29975 /* Return the ix86 builtin for CODE. */
29977 static tree
29979 {
29984 }
29986 /* Errors in the source file can cause expand_expr to return const0_rtx
29987 where we expect a vector. To avoid crashing, use one of the vector
29988 clear instructions. */
29989 static rtx
29991 {
29995 }
29997 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
29999 static rtx
30001 {
30002 rtx pat;
30022 {
30026 }
30040 }
30042 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30044 static rtx
30048 {
30049 rtx pat;
30057 rtx op;
30064 {
30144 }
30154 {
30161 {
30163 {
30166 {
30184 xop_rotl:
30186 {
30189 gcc_checking_assert
30191 }
30192 else
30193 {
30194 gcc_checking_assert
30205 }
30209 }
30210 }
30211 }
30212 else
30213 {
30214 non_constant:
30218 /* If we aren't optimizing, only allow one memory operand to be
30219 generated. */
30221 num_memory++;
30229 }
30233 }
30236 {
30247 else
30248 {
30254 }
30267 }
30274 }
30276 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30277 insns with vec_merge. */
30279 static rtx
30281 rtx target)
30282 {
30283 rtx pat;
30310 }
30312 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30314 static rtx
30317 {
30318 rtx pat;
30323 rtx op2;
30334 /* Swap operands if we have a comparison that isn't available in
30335 hardware. */
30337 {
30342 }
30362 }
30364 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30366 static rtx
30368 rtx target)
30369 {
30370 rtx pat;
30384 /* Swap operands if we have a comparison that isn't available in
30385 hardware. */
30387 {
30391 }
30412 const0_rtx)));
30415 }
30417 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30419 static rtx
30421 rtx target)
30422 {
30423 rtx pat;
30448 }
30450 static rtx
30453 {
30454 rtx pat;
30459 rtx op2;
30486 }
30488 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30490 static rtx
30492 rtx target)
30493 {
30494 rtx pat;
30527 const0_rtx)));
30530 }
30532 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30534 static rtx
30537 {
30538 rtx pat;
30576 {
30579 }
30582 {
30591 }
30593 {
30602 }
30603 else
30604 {
30611 }
30619 {
30624 emit_insn
30628 FLAGS_REG),
30629 const0_rtx)));
30631 }
30632 else
30634 }
30637 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30639 static rtx
30642 {
30643 rtx pat;
30671 {
30674 }
30677 {
30686 }
30688 {
30697 }
30698 else
30699 {
30706 }
30714 {
30719 emit_insn
30723 FLAGS_REG),
30724 const0_rtx)));
30726 }
30727 else
30729 }
30731 /* Subroutine of ix86_expand_builtin to take care of insns with
30732 variable number of operands. */
30734 static rtx
30737 {
30742 struct
30743 {
30744 rtx op;
30756 {
31035 }
31040 {
31043 }
31046 {
31053 }
31054 else
31055 {
31058 }
31061 {
31068 {
31069 /* SIMD shift insns take either an 8-bit immediate or
31070 register as count. But builtin functions take int as
31071 count. If count doesn't match, we put it in register. */
31073 {
31077 }
31078 }
31080 {
31083 {
31137 {
31140 {
31143 }
31149 }
31151 }
31152 }
31153 else
31154 {
31158 /* If we aren't optimizing, only allow one memory operand to
31159 be generated. */
31161 num_memory++;
31164 {
31167 }
31168 else
31169 {
31172 }
31173 }
31177 }
31180 {
31197 }
31204 }
31206 /* Subroutine of ix86_expand_builtin to take care of special insns
31207 with variable number of operands. */
31209 static rtx
31212 {
31213 tree arg;
31216 struct
31217 {
31218 rtx op;
31228 {
31276 /* Reserve memory operand for target. */
31307 /* Reserve memory operand for target. */
31321 }
31326 {
31331 {
31334 }
31335 else
31338 }
31339 else
31340 {
31347 }
31350 {
31359 {
31361 {
31367 else
31370 }
31371 }
31372 else
31373 {
31375 {
31376 /* This must be the memory operand. */
31381 }
31382 else
31383 {
31384 /* This must be register. */
31391 }
31392 }
31396 }
31399 {
31414 }
31420 }
31422 /* Return the integer constant in ARG. Constrain it to be in the range
31423 of the subparts of VEC_TYPE; issue an error if not. */
31425 static int
31427 {
31432 {
31435 }
31438 }
31440 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31441 ix86_expand_vector_init. We DO have language-level syntax for this, in
31442 the form of (type){ init-list }. Except that since we can't place emms
31443 instructions from inside the compiler, we can't allow the use of MMX
31444 registers unless the user explicitly asks for it. So we do *not* define
31445 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31446 we have builtins invoked by mmintrin.h that gives us license to emit
31447 these sorts of instructions. */
31449 static rtx
31451 {
31461 {
31464 }
31471 }
31473 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31474 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31475 had a language-level syntax for referencing vector elements. */
31477 static rtx
31479 {
31483 rtx op0;
31503 }
31505 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31506 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31507 a language-level syntax for referencing vector elements. */
31509 static rtx
31511 {
31535 /* OP0 is the source of these builtin functions and shouldn't be
31536 modified. Create a copy, use it and return it as target. */
31542 }
31544 /* Expand an expression EXP that calls a built-in function,
31545 with result going to TARGET if that's convenient
31546 (and in mode MODE if that's convenient).
31547 SUBTARGET may be used as the target for computing one of EXP's operands.
31548 IGNORE is nonzero if the value is to be ignored. */
31550 static rtx
31554 {
31564 /* For CPU builtins that can be folded, fold first and expand the fold. */
31566 {
31568 {
31569 /* Make it call __cpu_indicator_init in libgcc. */
31575 }
31578 {
31583 }
31584 }
31586 /* Determine whether the builtin function is available under the current ISA.
31587 Originally the builtin was not created if it wasn't applicable to the
31588 current ISA based on the command line switches. With function specific
31589 options, we need to check in the context of the function making the call
31590 whether it is supported. */
31593 {
31599 else
31600 {
31604 }
31606 }
31609 {
31613 ? CODE_FOR_mmx_maskmovq
31615 /* Note the arg order is different from the operand order. */
31716 {
31717 REAL_VALUE_TYPE inf;
31718 rtx tmp;
31730 }
31740 {
31746 insn = (TARGET_64BIT
31750 }
31752 {
31753 insn = (TARGET_64BIT
31757 }
31758 else
31759 {
31762 insn = (TARGET_64BIT
31770 {
31773 }
31775 }
31781 {
31786 }
31796 {
31811 }
31817 {
31820 }
31840 {
31843 }
31849 {
31853 {
31874 }
31879 }
31880 else
31881 {
31883 {
31895 }
31897 }
31927 ? CODE_FOR_tbm_bextri_si
31930 {
31933 }
31934 else
31935 {
31944 }
31960 rdrand_step:
31967 {
31970 }
31976 /* Emit SImode conditional move. */
31978 {
31981 }
31984 else
31991 const0_rtx);
32010 rdseed_step:
32017 {
32020 }
32026 const0_rtx);
32044 addcarryx:
32052 /* Generate CF from input operand. */
32057 /* Gen ADCX instruction to compute X+Y+CF. */
32072 /* Store the result. */
32075 {
32078 }
32081 /* Return current CF value. */
32150 gather_gen:
32161 /* Note the arg order is different from the operand order. */
32170 else
32175 {
32181 }
32184 {
32189 else
32199 }
32201 /* Force memory operand only with base register here. But we
32202 don't want to do it on memory operand for other builtin
32203 functions. */
32215 {
32218 }
32220 /* Optimize. If mask is known to have all high bits set,
32221 replace op0 with pc_rtx to signal that the instruction
32222 overwrites the whole destination and doesn't use its
32223 previous contents. */
32225 {
32227 {
32230 {
32234 negative++;
32237 negative++;
32238 }
32241 }
32243 {
32244 /* Recognize also when mask is like:
32245 __v2df src = _mm_setzero_pd ();
32246 __v2df mask = _mm_cmpeq_pd (src, src);
32247 or
32248 __v8sf src = _mm256_setzero_ps ();
32249 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32250 as that is a cheaper way to load all ones into
32251 a register than having to load a constant from
32252 memory. */
32255 {
32260 {
32267 /* FALLTHRU */
32277 }
32278 }
32279 }
32280 }
32289 {
32296 else
32298 }
32299 else
32310 {
32313 }
32319 }
32332 {
32336 /* Emit a normal call if SSE isn't available. */
32340 }
32365 }
32367 /* Returns a function decl for a vectorized version of the builtin function
32368 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32369 if it is not available. */
32371 static tree
32373 tree type_in)
32374 {
32390 {
32393 {
32398 }
32403 {
32408 }
32414 /* The round insn does not trap on denormals. */
32419 {
32424 }
32430 /* The round insn does not trap on denormals. */
32435 {
32440 }
32446 /* The round insn does not trap on denormals. */
32451 {
32456 }
32462 /* The round insn does not trap on denormals. */
32467 {
32472 }
32479 {
32484 }
32491 {
32496 }
32502 /* The round insn does not trap on denormals. */
32507 {
32512 }
32518 /* The round insn does not trap on denormals. */
32523 {
32528 }
32533 {
32538 }
32543 {
32548 }
32552 /* The round insn does not trap on denormals. */
32557 {
32562 }
32566 /* The round insn does not trap on denormals. */
32571 {
32576 }
32580 /* The round insn does not trap on denormals. */
32585 {
32590 }
32594 /* The round insn does not trap on denormals. */
32599 {
32604 }
32608 /* The round insn does not trap on denormals. */
32613 {
32618 }
32622 /* The round insn does not trap on denormals. */
32627 {
32632 }
32636 /* The round insn does not trap on denormals. */
32641 {
32646 }
32650 /* The round insn does not trap on denormals. */
32655 {
32660 }
32664 /* The round insn does not trap on denormals. */
32669 {
32674 }
32678 /* The round insn does not trap on denormals. */
32683 {
32688 }
32693 {
32698 }
32703 {
32708 }
32713 }
32715 /* Dispatch to a handler for a vectorization library. */
32718 type_in);
32721 }
32723 /* Handler for an SVML-style interface to
32724 a library with vectorized intrinsics. */
32726 static tree
32728 {
32736 /* The SVML is suitable for unsafe math only. */
32749 {
32796 }
32805 {
32808 }
32809 else
32812 /* Convert to uppercase. */
32817 args;
32819 arity++;
32823 else
32826 /* Build a function declaration for the vectorized function. */
32835 }
32837 /* Handler for an ACML-style interface to
32838 a library with vectorized intrinsics. */
32840 static tree
32842 {
32850 /* The ACML is 64bits only and suitable for unsafe math only as
32851 it does not correctly support parts of IEEE with the required
32852 precision such as denormals. */
32866 {
32896 }
32903 args;
32905 arity++;
32909 else
32912 /* Build a function declaration for the vectorized function. */
32921 }
32923 /* Returns a decl of a function that implements gather load with
32924 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32925 Return NULL_TREE if it is not available. */
32927 static tree
32930 {
32946 /* v*gather* insn sign extends index to pointer mode. */
32958 {
32985 }
32988 }
32990 /* Returns a code for a target-specific builtin that implements
32991 reciprocal of the function, or NULL_TREE if not available. */
32993 static tree
32996 {
33003 /* Machine dependent builtins. */
33005 {
33006 /* Vectorized version of sqrt to rsqrt conversion. */
33015 }
33016 else
33017 /* Normal builtins. */
33019 {
33020 /* Sqrt to rsqrt conversion. */
33026 }
33027 }
33028 \f
33029 /* Helper for avx_vpermilps256_operand et al. This is also used by
33030 the expansion functions to turn the parallel back into a mask.
33031 The return value is 0 for no match and the imm8+1 for a match. */
33033 int
33035 {
33043 /* Validate that all of the elements are constants, and not totally
33044 out of range. Copy the data into an integral array to make the
33045 subsequent checks easier. */
33047 {
33057 }
33060 {
33062 /* In the 256-bit DFmode case, we can only move elements within
33063 a 128-bit lane. */
33065 {
33069 }
33071 {
33075 }
33079 /* In the 256-bit SFmode case, we have full freedom of movement
33080 within the low 128-bit lane, but the high 128-bit lane must
33081 mirror the exact same pattern. */
33086 /* FALLTHRU */
33090 /* In the 128-bit case, we've full freedom in the placement of
33091 the elements from the source operand. */
33098 }
33100 /* Make sure success has a non-zero value by adding one. */
33102 }
33104 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33105 the expansion functions to turn the parallel back into a mask.
33106 The return value is 0 for no match and the imm8+1 for a match. */
33108 int
33110 {
33118 /* Validate that all of the elements are constants, and not totally
33119 out of range. Copy the data into an integral array to make the
33120 subsequent checks easier. */
33122 {
33132 }
33134 /* Validate that the halves of the permute are halves. */
33142 /* Reconstruct the mask. */
33144 {
33150 }
33152 /* Make sure success has a non-zero value by adding one. */
33154 }
33155 \f
33156 /* Store OPERAND to the memory after reload is completed. This means
33157 that we can't easily use assign_stack_local. */
33158 rtx
33160 {
33161 rtx result;
33165 {
33168 stack_pointer_rtx,
33171 }
33173 {
33175 {
33179 /* FALLTHRU */
33185 stack_pointer_rtx)),
33186 operand));
33190 }
33192 }
33193 else
33194 {
33196 {
33198 {
33205 stack_pointer_rtx)),
33211 stack_pointer_rtx)),
33213 }
33216 /* Store HImodes as SImodes. */
33218 /* FALLTHRU */
33224 stack_pointer_rtx)),
33225 operand));
33229 }
33231 }
33233 }
33235 /* Free operand from the memory. */
33236 void
33238 {
33240 {
33245 else
33247 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33248 to pop or add instruction if registers are available. */
33252 }
33253 }
33255 /* Return a register priority for hard reg REGNO. */
33256 static int
33258 {
33259 /* ebp and r13 as the base always wants a displacement, r12 as the
33260 base always wants an index. So discourage their usage in an
33261 address. */
33266 /* New x86-64 int registers result in bigger code size. Discourage
33267 them. */
33270 /* New x86-64 SSE registers result in bigger code size. Discourage
33271 them. */
33274 /* Usage of AX register results in smaller code. Prefer it. */
33278 }
33280 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33282 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33283 QImode must go into class Q_REGS.
33284 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33285 movdf to do mem-to-mem moves through integer regs. */
33287 static reg_class_t
33289 {
33292 /* We're only allowed to return a subclass of CLASS. Many of the
33293 following checks fail for NO_REGS, so eliminate that early. */
33297 /* All classes can load zeros. */
33301 /* Force constants into memory if we are loading a (nonzero) constant into
33302 an MMX or SSE register. This is because there are no MMX/SSE instructions
33303 to load from a constant. */
33308 /* Prefer SSE regs only, if we can use them for math. */
33312 /* Floating-point constants need more complex checks. */
33314 {
33315 /* General regs can load everything. */
33319 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33320 zero above. We only want to wind up preferring 80387 registers if
33321 we plan on doing computation with them. */
33324 {
33325 /* Limit class to non-sse. */
33334 }
33337 }
33339 /* Generally when we see PLUS here, it's the function invariant
33340 (plus soft-fp const_int). Which can only be computed into general
33341 regs. */
33345 /* QImode constants are easy to load, but non-constant QImode data
33346 must go into Q_REGS. */
33348 {
33354 }
33357 }
33359 /* Discourage putting floating-point values in SSE registers unless
33360 SSE math is being used, and likewise for the 387 registers. */
33361 static reg_class_t
33363 {
33366 /* Restrict the output reload class to the register bank that we are doing
33367 math on. If we would like not to return a subset of CLASS, reject this
33368 alternative: if reload cannot do this, it will still use its choice. */
33374 {
33379 else
33381 }
33384 }
33386 static reg_class_t
33389 {
33390 /* Double-word spills from general registers to non-offsettable memory
33391 references (zero-extended addresses) require special handling. */
33397 {
33399 ? CODE_FOR_reload_noff_load
33401 /* Add the cost of moving address to a temporary. */
33405 }
33407 /* QImode spills from non-QI registers require
33408 intermediate register on 32bit targets. */
33417 {
33422 else
33428 /* Return Q_REGS if the operand is in memory. */
33431 }
33433 /* This condition handles corner case where an expression involving
33434 pointers gets vectorized. We're trying to use the address of a
33435 stack slot as a vector initializer.
33437 (set (reg:V2DI 74 [ vect_cst_.2 ])
33438 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33440 Eventually frame gets turned into sp+offset like this:
33442 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33443 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33444 (const_int 392 [0x188]))))
33446 That later gets turned into:
33448 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33449 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33450 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33452 We'll have the following reload recorded:
33454 Reload 0: reload_in (DI) =
33455 (plus:DI (reg/f:DI 7 sp)
33456 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33457 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33458 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33459 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33460 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33461 reload_reg_rtx: (reg:V2DI 22 xmm1)
33463 Which isn't going to work since SSE instructions can't handle scalar
33464 additions. Returning GENERAL_REGS forces the addition into integer
33465 register and reload can handle subsequent reloads without problems. */
33473 }
33475 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33477 static bool
33479 {
33481 {
33496 }
33499 }
33501 /* If we are copying between general and FP registers, we need a memory
33502 location. The same is true for SSE and MMX registers.
33504 To optimize register_move_cost performance, allow inline variant.
33506 The macro can't work reliably when one of the CLASSES is class containing
33507 registers from multiple units (SSE, MMX, integer). We avoid this by never
33508 combining those units in single alternative in the machine description.
33509 Ensure that this constraint holds to avoid unexpected surprises.
33511 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33512 enforce these sanity checks. */
33517 {
33524 {
33527 }
33532 /* ??? This is a lie. We do have moves between mmx/general, and for
33533 mmx/sse2. But by saying we need secondary memory we discourage the
33534 register allocator from using the mmx registers unless needed. */
33539 {
33540 /* SSE1 doesn't have any direct moves from other classes. */
33544 /* If the target says that inter-unit moves are more expensive
33545 than moving through memory, then don't generate them. */
33549 /* Between SSE and general, we have moves no larger than word size. */
33552 }
33555 }
33557 bool
33560 {
33562 }
33564 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33566 On the 80386, this is the size of MODE in words,
33567 except in the FP regs, where a single reg is always enough. */
33569 static unsigned char
33571 {
33573 {
33578 else
33580 }
33581 else
33582 {
33585 else
33587 }
33588 }
33590 /* Return true if the registers in CLASS cannot represent the change from
33591 modes FROM to TO. */
33593 bool
33596 {
33600 /* x87 registers can't do subreg at all, as all values are reformatted
33601 to extended precision. */
33606 {
33607 /* Vector registers do not support QI or HImode loads. If we don't
33608 disallow a change to these modes, reload will assume it's ok to
33609 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33610 the vec_dupv4hi pattern. */
33614 /* Vector registers do not support subreg with nonzero offsets, which
33615 are otherwise valid for integer registers. Since we can't see
33616 whether we have a nonzero offset from here, prohibit all
33617 nonparadoxical subregs changing size. */
33620 }
33623 }
33625 /* Return the cost of moving data of mode M between a
33626 register and memory. A value of 2 is the default; this cost is
33627 relative to those in `REGISTER_MOVE_COST'.
33629 This function is used extensively by register_move_cost that is used to
33630 build tables at startup. Make it inline in this case.
33631 When IN is 2, return maximum of in and out move cost.
33633 If moving between registers and memory is more expensive than
33634 between two registers, you should define this macro to express the
33635 relative cost.
33637 Model also increased moving costs of QImode registers in non
33638 Q_REGS classes.
33639 */
33643 {
33646 {
33649 {
33661 }
33665 }
33667 {
33670 {
33682 }
33686 }
33688 {
33691 {
33700 }
33704 }
33706 {
33709 {
33715 else
33720 }
33721 else
33722 {
33727 else
33729 }
33736 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33743 else
33747 }
33748 }
33750 static int
33753 {
33755 }
33758 /* Return the cost of moving data from a register in class CLASS1 to
33759 one in class CLASS2.
33761 It is not required that the cost always equal 2 when FROM is the same as TO;
33762 on some machines it is expensive to move between registers if they are not
33763 general registers. */
33765 static int
33767 reg_class_t class2_i)
33768 {
33772 /* In case we require secondary memory, compute cost of the store followed
33773 by load. In order to avoid bad register allocation choices, we need
33774 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33777 {
33783 /* In case of copying from general_purpose_register we may emit multiple
33784 stores followed by single load causing memory size mismatch stall.
33785 Count this as arbitrarily high cost of 20. */
33790 /* In the case of FP/MMX moves, the registers actually overlap, and we
33791 have to switch modes in order to treat them differently. */
33797 }
33799 /* Moves between SSE/MMX and integer unit are expensive. */
33803 /* ??? By keeping returned value relatively high, we limit the number
33804 of moves between integer and MMX/SSE registers for all targets.
33805 Additionally, high value prevents problem with x86_modes_tieable_p(),
33806 where integer modes in MMX/SSE registers are not tieable
33807 because of missing QImode and HImode moves to, from or between
33808 MMX/SSE registers. */
33818 }
33820 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33821 MODE. */
33823 bool
33825 {
33826 /* Flags and only flags can only hold CCmode values. */
33836 {
33837 /* We implement the move patterns for all vector modes into and
33838 out of SSE registers, even when no operation instructions
33839 are available. OImode move is available only when AVX is
33840 enabled. */
33847 }
33849 {
33850 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33851 so if the register is available at all, then we can move data of
33852 the given mode into or out of it. */
33855 }
33858 {
33859 /* Take care for QImode values - they can be in non-QI regs,
33860 but then they do cause partial register stalls. */
33866 }
33867 /* We handle both integer and floats in the general purpose registers. */
33874 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33875 on to use that value in smaller contexts, this can easily force a
33876 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33877 supporting DImode, allow it. */
33882 }
33884 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33885 tieable integer mode. */
33887 static bool
33889 {
33891 {
33904 }
33905 }
33907 /* Return true if MODE1 is accessible in a register that can hold MODE2
33908 without copying. That is, all register classes that can hold MODE2
33909 can also hold MODE1. */
33911 bool
33913 {
33921 /* MODE2 being XFmode implies fp stack or general regs, which means we
33922 can tie any smaller floating point modes to it. Note that we do not
33923 tie this with TFmode. */
33927 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33928 that we can tie it with SFmode. */
33932 /* If MODE2 is only appropriate for an SSE register, then tie with
33933 any other mode acceptable to SSE registers. */
33943 /* If MODE2 is appropriate for an MMX register, then tie
33944 with any other mode acceptable to MMX registers. */
33951 }
33953 /* Return the cost of moving between two registers of mode MODE. */
33955 static int
33957 {
33961 {
33992 }
33994 /* Return the cost of moving between two registers of mode MODE,
33995 assuming that the move will be in pieces of at most UNITS bytes. */
33997 }
33999 /* Compute a (partial) cost for rtx X. Return true if the complete
34000 cost has been computed, and false if subexpressions should be
34001 scanned. In either case, *TOTAL contains the cost result. */
34003 static bool
34006 {
34013 {
34017 {
34020 }
34032 && (!TARGET_64BIT
34037 else
34043 {
34046 }
34048 {
34058 }
34060 {
34063 {
34072 }
34073 }
34074 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34075 it'll probably end up. Add a penalty for size. */
34082 /* The zero extensions is often completely free on x86_64, so make
34083 it as cheap as possible. */
34089 else
34101 {
34104 {
34107 }
34110 {
34113 }
34114 }
34115 /* FALLTHRU */
34122 {
34123 /* ??? Should be SSE vector operation cost. */
34124 /* At least for published AMD latencies, this really is the same
34125 as the latency for a simple fpu operation like fabs. */
34126 /* V*QImode is emulated with 1-11 insns. */
34128 {
34131 {
34132 /* For XOP we use vpshab, which requires a broadcast of the
34133 value to the variable shift insn. For constants this
34134 means a V16Q const in mem; even when we can perform the
34135 shift with one insn set the cost to prefer paddb. */
34137 {
34142 }
34144 }
34148 }
34149 else
34151 }
34153 {
34155 {
34158 else
34160 }
34161 else
34162 {
34165 else
34167 }
34168 }
34169 else
34170 {
34173 else
34175 }
34179 {
34180 rtx sub;
34185 /* ??? SSE scalar/vector cost should be used here. */
34186 /* ??? Bald assumption that fma has the same cost as fmul. */
34190 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34201 }
34205 {
34206 /* ??? SSE scalar cost should be used here. */
34209 }
34211 {
34214 }
34216 {
34217 /* ??? SSE vector cost should be used here. */
34220 }
34222 {
34223 /* V*QImode is emulated with 7-13 insns. */
34225 {
34232 }
34233 /* V*DImode is emulated with 5-8 insns. */
34235 {
34238 else
34240 }
34241 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34242 insns, including two PMULUDQ. */
34245 else
34248 }
34249 else
34250 {
34255 {
34258 nbits++;
34259 }
34260 else
34261 /* This is arbitrary. */
34264 /* Compute costs correctly for widening multiplication. */
34268 {
34275 {
34279 else
34281 }
34285 }
34293 }
34300 /* ??? SSE cost should be used here. */
34305 /* ??? SSE vector cost should be used here. */
34307 else
34314 {
34319 {
34322 {
34330 }
34331 }
34334 {
34337 {
34343 }
34344 }
34346 {
34354 }
34355 }
34356 /* FALLTHRU */
34360 {
34361 /* ??? SSE cost should be used here. */
34364 }
34366 {
34369 }
34371 {
34372 /* ??? SSE vector cost should be used here. */
34375 }
34376 /* FALLTHRU */
34383 {
34390 }
34391 /* FALLTHRU */
34395 {
34396 /* ??? SSE cost should be used here. */
34399 }
34401 {
34404 }
34406 {
34407 /* ??? SSE vector cost should be used here. */
34410 }
34411 /* FALLTHRU */
34415 {
34416 /* ??? Should be SSE vector operation cost. */
34417 /* At least for published AMD latencies, this really is the same
34418 as the latency for a simple fpu operation like fabs. */
34420 }
34423 else
34432 {
34433 /* This kind of construct is implemented using test[bwl].
34434 Treat it as if we had an AND. */
34439 }
34449 /* ??? SSE cost should be used here. */
34454 /* ??? SSE vector cost should be used here. */
34460 /* ??? SSE cost should be used here. */
34465 /* ??? SSE vector cost should be used here. */
34478 /* ??? Assume all of these vector manipulation patterns are
34479 recognizable. In which case they all pretty much have the
34480 same cost. */
34486 }
34487 }
34489 #if TARGET_MACHO
34493 /* Given a symbol name and its associated stub, write out the
34494 definition of the stub. */
34496 void
34498 {
34503 /* For 64-bit we shouldn't get here. */
34506 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34523 else
34530 {
34532 }
34534 {
34535 /* PIC stub. */
34536 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34542 }
34543 else
34546 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34547 it needs no stub-binding-helper. */
34554 {
34557 }
34558 else
34563 /* N.B. Keep the correspondence of these
34564 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34565 old-pic/new-pic/non-pic stubs; altering this will break
34566 compatibility with existing dylibs. */
34568 {
34569 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34571 }
34572 else
34573 /* 16-byte -mdynamic-no-pic stub. */
34579 }
34582 /* Order the registers for register allocator. */
34584 void
34586 {
34590 /* First allocate the local general purpose registers. */
34595 /* Global general purpose registers. */
34600 /* x87 registers come first in case we are doing FP math
34601 using them. */
34606 /* SSE registers. */
34612 /* x87 registers. */
34620 /* Initialize the rest of array as we do not allocate some registers
34621 at all. */
34624 }
34626 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34627 in struct attribute_spec handler. */
34628 static tree
34630 tree args,
34633 {
34638 {
34640 name);
34643 }
34645 {
34647 name);
34650 }
34652 {
34653 tree cst;
34657 {
34660 name);
34662 }
34665 {
34668 name);
34670 }
34673 }
34676 }
34678 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34679 struct attribute_spec.handler. */
34680 static tree
34682 tree args ATTRIBUTE_UNUSED,
34684 {
34689 {
34691 name);
34694 }
34696 /* Can combine regparm with all attributes but fastcall. */
34698 {
34700 {
34702 }
34705 }
34707 {
34709 {
34711 }
34714 }
34717 }
34719 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34720 struct attribute_spec.handler. */
34721 static tree
34723 tree args ATTRIBUTE_UNUSED,
34725 {
34728 {
34731 }
34732 else
34736 {
34738 name);
34740 }
34746 {
34748 name);
34750 }
34753 }
34755 static tree
34757 tree args ATTRIBUTE_UNUSED,
34759 {
34761 {
34763 name);
34765 }
34767 }
34769 static bool
34771 {
34775 }
34777 /* Returns an expression indicating where the this parameter is
34778 located on entry to the FUNCTION. */
34780 static rtx
34782 {
34788 {
34793 else
34796 }
34801 {
34808 {
34813 }
34814 else
34815 {
34818 {
34824 }
34825 }
34827 }
34831 }
34833 /* Determine whether x86_output_mi_thunk can succeed. */
34835 static bool
34837 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34839 {
34840 /* 64-bit can handle anything. */
34844 /* For 32-bit, everything's fine if we have one free register. */
34848 /* Need a free register for vcall_offset. */
34852 /* Need a free register for GOT references. */
34856 /* Otherwise ok. */
34858 }
34860 /* Output the assembler code for a thunk function. THUNK_DECL is the
34861 declaration for the thunk function itself, FUNCTION is the decl for
34862 the target function. DELTA is an immediate constant offset to be
34863 added to THIS. If VCALL_OFFSET is nonzero, the word at
34864 *(*this + vcall_offset) should be added to THIS. */
34866 static void
34870 {
34877 else
34878 {
34884 else
34886 }
34890 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34891 pull it in now and let DELTA benefit. */
34895 {
34896 /* Put the this parameter into %eax. */
34899 }
34900 else
34903 /* Adjust the this parameter by a fixed constant. */
34905 {
34910 {
34912 {
34916 }
34917 }
34920 }
34922 /* Adjust the this parameter by a value stored in the vtable. */
34924 {
34934 /* Adjust the this parameter. */
34938 {
34942 }
34949 vcall_mem));
34950 else
34952 }
34954 /* If necessary, drop THIS back to its stack slot. */
34960 {
34963 ;
34964 else
34965 {
34969 }
34970 }
34971 else
34972 {
34974 ;
34975 #if TARGET_MACHO
34977 {
34980 }
34982 else
34983 {
34990 }
34991 }
34993 /* Our sibling call patterns do not allow memories, because we have no
34994 predicate that can distinguish between frame and non-frame memory.
34995 For our purposes here, we can get away with (ab)using a jump pattern,
34996 because we're going to do no optimization. */
34999 else
35000 {
35006 {
35012 }
35018 }
35021 /* Emit just enough of rest_of_compilation to get the insns emitted.
35022 Note that use_thunk calls assemble_start_function et al. */
35028 }
35030 static void
35032 {
35034 #if TARGET_MACHO
35036 #endif
35043 }
35045 int
35047 {
35059 }
35061 /* Output assembler code to FILE to increment profiler label # LABELNO
35062 for profiling a function entry. */
35063 void
35065 {
35070 {
35071 #ifndef NO_PROFILE_COUNTERS
35073 #endif
35077 else
35079 }
35081 {
35082 #ifndef NO_PROFILE_COUNTERS
35085 #endif
35087 }
35088 else
35089 {
35090 #ifndef NO_PROFILE_COUNTERS
35093 #endif
35095 }
35096 }
35098 /* We don't have exact information about the insn sizes, but we may assume
35099 quite safely that we are informed about all 1 byte insns and memory
35100 address sizes. This is enough to eliminate unnecessary padding in
35101 99% of cases. */
35103 static int
35105 {
35111 /* Discard alignments we've emit and jump instructions. */
35118 /* Important case - calls are always 5 bytes.
35119 It is common to have many calls in the row. */
35128 /* For normal instructions we rely on get_attr_length being exact,
35129 with a few exceptions. */
35131 {
35135 {
35145 /* Otherwise trust get_attr_length. */
35147 }
35152 }
35155 else
35157 }
35159 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35161 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35162 window. */
35164 static void
35166 {
35171 /* Look for all minimal intervals of instructions containing 4 jumps.
35172 The intervals are bounded by START and INSN. NBYTES is the total
35173 size of instructions in the interval including INSN and not including
35174 START. When the NBYTES is smaller than 16 bytes, it is possible
35175 that the end of START and INSN ends up in the same 16byte page.
35177 The smallest offset in the page INSN can start is the case where START
35178 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35179 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35180 */
35182 {
35186 {
35192 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35193 already in the current 16 byte page, because otherwise
35194 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35195 bytes to reach 16 byte boundary. */
35203 {
35205 {
35212 else
35215 }
35216 }
35218 }
35229 njumps++;
35230 else
35234 {
35241 else
35244 }
35251 {
35258 }
35259 }
35260 }
35261 #endif
35263 /* AMD Athlon works faster
35264 when RET is not destination of conditional jump or directly preceded
35265 by other jump instruction. We avoid the penalty by inserting NOP just
35266 before the RET instructions in such cases. */
35267 static void
35269 {
35270 edge e;
35271 edge_iterator ei;
35274 {
35277 rtx prev;
35287 {
35288 edge e;
35289 edge_iterator ei;
35295 }
35297 {
35303 /* Empty functions get branch mispredict even when
35304 the jump destination is not visible to us. */
35307 }
35309 {
35312 }
35313 }
35314 }
35316 /* Count the minimum number of instructions in BB. Return 4 if the
35317 number of instructions >= 4. */
35319 static int
35321 {
35322 rtx insn;
35325 /* Count number of instructions in this block. Return 4 if the number
35326 of instructions >= 4. */
35328 {
35329 /* Only happen in exit blocks. */
35337 {
35338 insn_count++;
35341 }
35342 }
35345 }
35348 /* Count the minimum number of instructions in code path in BB.
35349 Return 4 if the number of instructions >= 4. */
35351 static int
35353 {
35354 edge e;
35355 edge_iterator ei;
35358 /* Only bother counting instructions along paths with no
35359 more than 2 basic blocks between entry and exit. Given
35360 that BB has an edge to exit, determine if a predecessor
35361 of BB has an edge from entry. If so, compute the number
35362 of instructions in the predecessor block. If there
35363 happen to be multiple such blocks, compute the minimum. */
35366 {
35367 edge prev_e;
35368 edge_iterator prev_ei;
35371 {
35374 }
35376 {
35378 {
35383 }
35384 }
35385 }
35391 }
35393 /* Pad short function to 4 instructions. */
35395 static void
35397 {
35398 edge e;
35399 edge_iterator ei;
35402 {
35405 {
35408 /* Pad short function. */
35410 {
35413 /* Find epilogue. */
35422 /* Two NOPs count as one instruction. */
35425 }
35426 }
35427 }
35428 }
35430 /* Implement machine specific optimizations. We implement padding of returns
35431 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35432 static void
35434 {
35435 /* We are freeing block_for_insn in the toplev to keep compatibility
35436 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35440 {
35445 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35448 #endif
35449 }
35450 }
35452 /* Return nonzero when QImode register that must be represented via REX prefix
35453 is used. */
35454 bool
35456 {
35464 }
35466 /* Return nonzero when P points to register encoded via REX prefix.
35467 Called via for_each_rtx. */
35468 static int
35470 {
35476 }
35478 /* Return true when INSN mentions register that must be encoded using REX
35479 prefix. */
35480 bool
35482 {
35485 }
35487 /* If profitable, negate (without causing overflow) integer constant
35488 of mode MODE at location LOC. Return true in this case. */
35489 bool
35491 {
35492 HOST_WIDE_INT val;
35498 {
35500 /* DImode x86_64 constants must fit in 32 bits. */
35513 }
35515 /* Avoid overflows. */
35521 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35522 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35525 {
35528 }
35531 }
35533 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35534 optabs would emit if we didn't have TFmode patterns. */
35536 void
35538 {
35572 }
35573 \f
35574 /* AVX2 does support 32-byte integer vector operations,
35575 thus the longest vector we are faced with is V32QImode. */
35576 #define MAX_VECT_LEN 32
35578 struct expand_vec_perm_d
35579 {
35586 };
35592 /* Get a vector mode of the same size as the original but with elements
35593 twice as wide. This is only guaranteed to apply to integral vectors. */
35597 {
35598 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35603 }
35605 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35606 with all elements equal to VAR. Return true if successful. */
35608 static bool
35611 {
35615 {
35620 /* FALLTHRU */
35630 {
35633 /* First attempt to recognize VAL as-is. */
35637 {
35638 rtx seq;
35639 /* If that fails, force VAL into a register. */
35650 }
35651 }
35658 {
35659 rtx x;
35666 }
35676 {
35680 permute:
35688 /* Extend to SImode using a paradoxical SUBREG. */
35692 /* Insert the SImode value as low element of a V4SImode vector. */
35700 }
35708 widen:
35709 /* Replicate the value once into the next wider mode and recurse. */
35710 {
35712 rtx x;
35728 }
35732 {
35741 }
35746 }
35747 }
35749 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35750 whose ONE_VAR element is VAR, and other elements are zero. Return true
35751 if successful. */
35753 static bool
35756 {
35758 rtx new_target;
35763 {
35765 /* For SSE4.1, we normally use vector set. But if the second
35766 element is zero and inter-unit moves are OK, we use movq
35767 instead. */
35768 use_vector_set = (TARGET_64BIT
35769 && TARGET_SSE4_1
35770 && !(TARGET_INTER_UNIT_MOVES
35792 /* Use ix86_expand_vector_set in 64bit mode only. */
35797 }
35800 {
35805 }
35808 {
35813 /* FALLTHRU */
35828 else
35835 {
35836 /* We need to shuffle the value to the correct position, so
35837 create a new pseudo to store the intermediate result. */
35839 /* With SSE2, we can use the integer shuffle insns. */
35841 {
35843 const1_rtx,
35850 }
35852 /* Otherwise convert the intermediate result to V4SFmode and
35853 use the SSE1 shuffle instructions. */
35855 {
35858 }
35859 else
35863 const1_rtx,
35872 }
35887 widen:
35891 /* Zero extend the variable element to SImode and recurse. */
35904 }
35905 }
35907 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35908 consisting of the values in VALS. It is known that all elements
35909 except ONE_VAR are constants. Return true if successful. */
35911 static bool
35914 {
35924 {
35929 /* For the two element vectors, it's just as easy to use
35930 the general case. */
35934 /* Use ix86_expand_vector_set in 64bit mode only. */
35956 widen:
35957 /* There's no way to set one QImode entry easily. Combine
35958 the variable value with its adjacent constant value, and
35959 promote to an HImode set. */
35962 {
35967 }
35968 else
35969 {
35972 }
35986 }
35991 }
35993 /* A subroutine of ix86_expand_vector_init_general. Use vector
35994 concatenate to handle the most general case: all values variable,
35995 and none identical. */
35997 static void
36000 {
36003 rtvec v;
36007 {
36010 {
36043 }
36056 {
36071 }
36076 {
36087 }
36090 half:
36091 /* FIXME: We process inputs backward to help RA. PR 36222. */
36095 {
36100 }
36104 {
36107 {
36111 }
36114 }
36115 else
36121 }
36122 }
36124 /* A subroutine of ix86_expand_vector_init_general. Use vector
36125 interleave to handle the most general case: all values variable,
36126 and none identical. */
36128 static void
36131 {
36140 {
36161 }
36164 {
36165 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36169 /* Insert the SImode value as low element of V4SImode vector. */
36173 op0),
36175 const1_rtx);
36178 /* Cast the V4SImode vector back to a vector in orignal mode. */
36182 /* Load even elements into the second positon. */
36186 const1_rtx));
36188 /* Cast vector to FIRST_IMODE vector. */
36191 }
36193 /* Interleave low FIRST_IMODE vectors. */
36195 {
36199 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36202 }
36204 /* Interleave low SECOND_IMODE vectors. */
36206 {
36209 {
36214 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36215 vector. */
36218 }
36221 /* FALLTHRU */
36228 /* Cast the SECOND_IMODE vector back to a vector on original
36229 mode. */
36236 }
36237 }
36239 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36240 all values variable, and none identical. */
36242 static void
36245 {
36251 {
36256 /* FALLTHRU */
36280 half:
36297 /* FALLTHRU */
36303 /* Don't use ix86_expand_vector_init_interleave if we can't
36304 move from GPR to SSE register directly. */
36320 }
36322 {
36334 {
36338 {
36344 else
36345 {
36350 }
36351 }
36354 }
36359 {
36365 }
36367 {
36373 }
36374 else
36376 }
36377 }
36379 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36380 instructions unless MMX_OK is true. */
36382 void
36384 {
36391 rtx x;
36394 {
36404 }
36406 /* Constants are best loaded from the constant pool. */
36408 {
36411 }
36413 /* If all values are identical, broadcast the value. */
36419 /* Values where only one field is non-constant are best loaded from
36420 the pool and overwritten via move later. */
36422 {
36426 one_var))
36431 }
36434 }
36436 void
36438 {
36443 rtx tmp;
36445 = {
36452 };
36454 = {
36461 };
36465 {
36469 {
36474 else
36478 }
36490 else
36496 {
36499 /* For the two element vectors, we implement a VEC_CONCAT with
36500 the extraction of the other element. */
36507 else
36512 }
36521 {
36527 /* tmp = target = A B C D */
36529 /* target = A A B B */
36531 /* target = X A B B */
36533 /* target = A X C D */
36540 /* tmp = target = A B C D */
36542 /* tmp = X B C D */
36544 /* target = A B X D */
36551 /* tmp = target = A B C D */
36553 /* tmp = X B C D */
36555 /* target = A B X D */
36563 }
36571 /* Element 0 handled by vec_merge below. */
36573 {
36576 }
36579 {
36580 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36581 store into element 0, then shuffle them back. */
36598 }
36599 else
36600 {
36601 /* For SSE1, we have to reuse the V4SF code. */
36604 }
36657 half:
36658 /* Compute offset. */
36664 /* Extract the half. */
36668 /* Put val in tmp at elt. */
36671 /* Put it back. */
36677 }
36680 {
36684 }
36685 else
36686 {
36695 }
36696 }
36698 void
36700 {
36704 rtx tmp;
36707 {
36712 /* FALLTHRU */
36725 {
36745 }
36757 {
36759 {
36779 }
36783 }
36784 else
36785 {
36786 /* For SSE1, we have to reuse the V4SF code. */
36790 }
36806 {
36810 else
36814 }
36819 {
36823 else
36827 }
36832 {
36836 else
36840 }
36845 {
36849 else
36853 }
36858 {
36862 else
36866 }
36871 {
36875 else
36879 }
36883 /* ??? Could extract the appropriate HImode element and shift. */
36886 }
36889 {
36893 /* Let the rtl optimizers know about the zero extension performed. */
36895 {
36898 }
36901 }
36902 else
36903 {
36910 }
36911 }
36913 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36914 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36915 The upper bits of DEST are undefined, though they shouldn't cause
36916 exceptions (some bits from src or all zeros are ok). */
36918 static void
36920 {
36921 rtx tem;
36923 {
36927 else
36945 else
36952 else
36963 const1_rtx);
36964 else
36971 }
36973 }
36975 /* Expand a vector reduction. FN is the binary pattern to reduce;
36976 DEST is the destination; IN is the input vector. */
36978 void
36980 {
36985 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36989 {
36992 }
36997 {
37002 else
37006 }
37007 }
37008 \f
37009 /* Target hook for scalar_mode_supported_p. */
37010 static bool
37012 {
37017 else
37019 }
37021 /* Implements target hook vector_mode_supported_p. */
37022 static bool
37024 {
37036 }
37038 /* Target hook for c_mode_for_suffix. */
37039 static enum machine_mode
37041 {
37048 }
37050 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37052 We do this in the new i386 backend to maintain source compatibility
37053 with the old cc0-based compiler. */
37055 static tree
37057 tree inputs ATTRIBUTE_UNUSED,
37058 tree clobbers)
37059 {
37061 clobbers);
37063 clobbers);
37065 }
37067 /* Implements target vector targetm.asm.encode_section_info. */
37069 static void ATTRIBUTE_UNUSED
37071 {
37078 }
37080 /* Worker function for REVERSE_CONDITION. */
37082 enum rtx_code
37084 {
37088 }
37090 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37091 to OPERANDS[0]. */
37095 {
37097 {
37100 {
37104 }
37108 }
37110 {
37114 else
37115 {
37116 /* There is no non-popping store to memory for XFmode.
37117 So if we need one, follow the store with a load. */
37120 else
37122 }
37123 }
37124 else
37126 }
37128 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37129 FP status register is set. */
37131 void
37133 {
37135 rtx temp;
37140 {
37145 }
37146 else
37147 {
37152 }
37156 pc_rtx);
37161 }
37163 /* Output code to perform a log1p XFmode calculation. */
37166 {
37172 rtx test;
37178 XFmode));
37192 }
37194 /* Emit code for round calculation. */
37196 {
37203 rtx insn;
37208 {
37220 }
37223 {
37244 }
37252 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37254 /* scratch = fxam(op1) */
37257 UNSPEC_FXAM)));
37258 /* e1 = fabs(op1) */
37261 /* e2 = e1 + 0.5 */
37266 /* res = floor(e2) */
37268 {
37273 }
37274 else
37278 {
37281 {
37288 UNSPEC_TRUNC_NOOP)));
37289 }
37305 }
37307 /* flags = signbit(a) */
37310 /* if (flags) then res = -res */
37314 pc_rtx);
37325 }
37327 /* Output code to perform a Newton-Rhapson approximation of a single precision
37328 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37331 {
37339 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37343 /* x0 = rcp(b) estimate */
37346 UNSPEC_RCP)));
37347 /* e0 = x0 * b */
37351 /* e0 = x0 * e0 */
37355 /* e1 = x0 + x0 */
37359 /* x1 = e1 - e0 */
37363 /* res = a * x1 */
37366 }
37368 /* Output code to perform a Newton-Rhapson approximation of a
37369 single precision floating point [reciprocal] square root. */
37373 {
37375 REAL_VALUE_TYPE r;
37390 {
37393 }
37395 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37396 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37400 /* x0 = rsqrt(a) estimate */
37403 UNSPEC_RSQRT)));
37405 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37407 {
37419 }
37421 /* e0 = x0 * a */
37424 /* e1 = e0 * x0 */
37428 /* e2 = e1 - 3. */
37435 /* e3 = -.5 * x0 */
37438 else
37439 /* e3 = -.5 * e0 */
37442 /* ret = e2 * e3 */
37445 }
37447 #ifdef TARGET_SOLARIS
37448 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37450 static void
37452 tree decl)
37453 {
37454 /* With Binutils 2.15, the "@unwind" marker must be specified on
37455 every occurrence of the ".eh_frame" section, not just the first
37456 one. */
37459 {
37463 }
37465 #ifndef USE_GAS
37467 {
37470 }
37471 #endif
37474 }
37477 /* Return the mangling of TYPE if it is an extended fundamental type. */
37481 {
37489 {
37491 /* __float128 is "g". */
37494 /* "long double" or __float80 is "e". */
37498 }
37499 }
37501 /* For 32-bit code we can save PIC register setup by using
37502 __stack_chk_fail_local hidden function instead of calling
37503 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37504 register, so it is better to call __stack_chk_fail directly. */
37506 static tree ATTRIBUTE_UNUSED
37508 {
37509 return TARGET_64BIT
37512 }
37514 /* Select a format to encode pointers in exception handling data. CODE
37515 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37516 true if the symbol may be affected by dynamic relocations.
37518 ??? All x86 object file formats are capable of representing this.
37519 After all, the relocation needed is the same as for the call insn.
37520 Whether or not a particular assembler allows us to enter such, I
37521 guess we'll have to see. */
37522 int
37524 {
37526 {
37533 }
37538 }
37539 \f
37540 /* Expand copysign from SIGN to the positive value ABS_VALUE
37541 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37542 the sign-bit. */
37543 static void
37545 {
37549 {
37556 else
37561 {
37562 /* We need to generate a scalar mode mask in this case. */
37567 }
37568 }
37569 else
37575 }
37577 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37578 mask for masking out the sign-bit is stored in *SMASK, if that is
37579 non-null. */
37580 static rtx
37582 {
37591 else
37595 {
37596 /* We need to generate a scalar mode mask in this case. */
37601 }
37609 }
37611 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37612 swapping the operands if SWAP_OPERANDS is true. The expanded
37613 code is a forward jump to a newly created label in case the
37614 comparison is true. The generated label rtx is returned. */
37615 static rtx
37618 {
37622 {
37626 }
37639 }
37641 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37642 using comparison code CODE. Operands are swapped for the comparison if
37643 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37644 static rtx
37647 {
37653 {
37657 }
37664 }
37666 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37667 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37668 static rtx
37670 {
37671 REAL_VALUE_TYPE TWO52r;
37672 rtx TWO52;
37679 }
37681 /* Expand SSE sequence for computing lround from OP1 storing
37682 into OP0. */
37683 void
37685 {
37686 /* C code for the stuff we're doing below:
37687 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37688 return (long)tmp;
37689 */
37693 rtx adj;
37695 /* load nextafter (0.5, 0.0) */
37700 /* adj = copysign (0.5, op1) */
37704 /* adj = op1 + adj */
37707 /* op0 = (imode)adj */
37709 }
37711 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37712 into OPERAND0. */
37713 void
37715 {
37716 /* C code for the stuff we're doing below (for do_floor):
37717 xi = (long)op1;
37718 xi -= (double)xi > op1 ? 1 : 0;
37719 return xi;
37720 */
37725 /* reg = (long)op1 */
37729 /* freg = (double)reg */
37733 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37744 }
37746 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37747 result in OPERAND0. */
37748 void
37750 {
37751 /* C code for the stuff we're doing below:
37752 xa = fabs (operand1);
37753 if (!isless (xa, 2**52))
37754 return operand1;
37755 xa = xa + 2**52 - 2**52;
37756 return copysign (xa, operand1);
37757 */
37764 /* xa = abs (operand1) */
37767 /* if (!isless (xa, TWO52)) goto label; */
37780 }
37782 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37783 into OPERAND0. */
37784 void
37786 {
37787 /* C code for the stuff we expand below.
37788 double xa = fabs (x), x2;
37789 if (!isless (xa, TWO52))
37790 return x;
37791 xa = xa + TWO52 - TWO52;
37792 x2 = copysign (xa, x);
37793 Compensate. Floor:
37794 if (x2 > x)
37795 x2 -= 1;
37796 Compensate. Ceil:
37797 if (x2 < x)
37798 x2 -= -1;
37799 return x2;
37800 */
37806 /* Temporary for holding the result, initialized to the input
37807 operand to ease control flow. */
37811 /* xa = abs (operand1) */
37814 /* if (!isless (xa, TWO52)) goto label; */
37817 /* xa = xa + TWO52 - TWO52; */
37821 /* xa = copysign (xa, operand1) */
37824 /* generate 1.0 or -1.0 */
37829 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37833 /* We always need to subtract here to preserve signed zero. */
37842 }
37844 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37845 into OPERAND0. */
37846 void
37848 {
37849 /* C code for the stuff we expand below.
37850 double xa = fabs (x), x2;
37851 if (!isless (xa, TWO52))
37852 return x;
37853 x2 = (double)(long)x;
37854 Compensate. Floor:
37855 if (x2 > x)
37856 x2 -= 1;
37857 Compensate. Ceil:
37858 if (x2 < x)
37859 x2 += 1;
37860 if (HONOR_SIGNED_ZEROS (mode))
37861 return copysign (x2, x);
37862 return x2;
37863 */
37869 /* Temporary for holding the result, initialized to the input
37870 operand to ease control flow. */
37874 /* xa = abs (operand1) */
37877 /* if (!isless (xa, TWO52)) goto label; */
37880 /* xa = (double)(long)x */
37885 /* generate 1.0 */
37888 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37903 }
37905 /* Expand SSE sequence for computing round from OPERAND1 storing
37906 into OPERAND0. Sequence that works without relying on DImode truncation
37907 via cvttsd2siq that is only available on 64bit targets. */
37908 void
37910 {
37911 /* C code for the stuff we expand below.
37912 double xa = fabs (x), xa2, x2;
37913 if (!isless (xa, TWO52))
37914 return x;
37915 Using the absolute value and copying back sign makes
37916 -0.0 -> -0.0 correct.
37917 xa2 = xa + TWO52 - TWO52;
37918 Compensate.
37919 dxa = xa2 - xa;
37920 if (dxa <= -0.5)
37921 xa2 += 1;
37922 else if (dxa > 0.5)
37923 xa2 -= 1;
37924 x2 = copysign (xa2, x);
37925 return x2;
37926 */
37932 /* Temporary for holding the result, initialized to the input
37933 operand to ease control flow. */
37937 /* xa = abs (operand1) */
37940 /* if (!isless (xa, TWO52)) goto label; */
37943 /* xa2 = xa + TWO52 - TWO52; */
37947 /* dxa = xa2 - xa; */
37950 /* generate 0.5, 1.0 and -0.5 */
37956 /* Compensate. */
37958 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37963 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37969 /* res = copysign (xa2, operand1) */
37976 }
37978 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37979 into OPERAND0. */
37980 void
37982 {
37983 /* C code for SSE variant we expand below.
37984 double xa = fabs (x), x2;
37985 if (!isless (xa, TWO52))
37986 return x;
37987 x2 = (double)(long)x;
37988 if (HONOR_SIGNED_ZEROS (mode))
37989 return copysign (x2, x);
37990 return x2;
37991 */
37997 /* Temporary for holding the result, initialized to the input
37998 operand to ease control flow. */
38002 /* xa = abs (operand1) */
38005 /* if (!isless (xa, TWO52)) goto label; */
38008 /* x = (double)(long)x */
38020 }
38022 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38023 into OPERAND0. */
38024 void
38026 {
38030 /* C code for SSE variant we expand below.
38031 double xa = fabs (x), x2;
38032 if (!isless (xa, TWO52))
38033 return x;
38034 xa2 = xa + TWO52 - TWO52;
38035 Compensate:
38036 if (xa2 > xa)
38037 xa2 -= 1.0;
38038 x2 = copysign (xa2, x);
38039 return x2;
38040 */
38044 /* Temporary for holding the result, initialized to the input
38045 operand to ease control flow. */
38049 /* xa = abs (operand1) */
38052 /* if (!isless (xa, TWO52)) goto label; */
38055 /* res = xa + TWO52 - TWO52; */
38060 /* generate 1.0 */
38063 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38071 /* res = copysign (res, operand1) */
38078 }
38080 /* Expand SSE sequence for computing round from OPERAND1 storing
38081 into OPERAND0. */
38082 void
38084 {
38085 /* C code for the stuff we're doing below:
38086 double xa = fabs (x);
38087 if (!isless (xa, TWO52))
38088 return x;
38089 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38090 return copysign (xa, x);
38091 */
38097 /* Temporary for holding the result, initialized to the input
38098 operand to ease control flow. */
38106 /* load nextafter (0.5, 0.0) */
38111 /* xa = xa + 0.5 */
38115 /* xa = (double)(int64_t)xa */
38120 /* res = copysign (xa, operand1) */
38127 }
38129 /* Expand SSE sequence for computing round
38130 from OP1 storing into OP0 using sse4 round insn. */
38131 void
38133 {
38142 {
38153 }
38155 /* round (a) = trunc (a + copysign (0.5, a)) */
38157 /* load nextafter (0.5, 0.0) */
38163 /* e1 = copysign (0.5, op1) */
38167 /* e2 = op1 + e1 */
38170 /* res = trunc (e2) */
38175 }
38176 \f
38178 /* Table of valid machine attributes. */
38180 {
38181 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38182 affects_type_identity } */
38183 /* Stdcall attribute says callee is responsible for popping arguments
38184 if they are not variable. */
38187 /* Fastcall attribute says callee is responsible for popping arguments
38188 if they are not variable. */
38191 /* Thiscall attribute says callee is responsible for popping arguments
38192 if they are not variable. */
38195 /* Cdecl attribute says the callee is a normal C declaration */
38198 /* Regparm attribute specifies how many integer arguments are to be
38199 passed in registers. */
38202 /* Sseregparm attribute says we are using x86_64 calling conventions
38203 for FP arguments. */
38206 /* The transactional memory builtins are implicitly regparm or fastcall
38207 depending on the ABI. Override the generic do-nothing attribute that
38208 these builtins were declared with. */
38211 /* force_align_arg_pointer says this function realigns the stack at entry. */
38214 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38219 #endif
38224 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38225 SUBTARGET_ATTRIBUTE_TABLE,
38226 #endif
38227 /* ms_abi and sysv_abi calling convention function attributes. */
38234 /* End element. */
38236 };
38238 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38239 static int
38241 tree vectype,
38243 {
38247 {
38292 }
38293 }
38295 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38296 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38297 insn every time. */
38301 /* Initialize vselect_insn. */
38303 static void
38305 {
38307 rtx x;
38318 }
38320 /* Construct (set target (vec_select op0 (parallel perm))) and
38321 return true if that's a valid instruction in the active ISA. */
38323 static bool
38326 {
38352 }
38354 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38356 static bool
38360 {
38362 rtx x;
38377 }
38379 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38380 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38382 static bool
38384 {
38393 ;
38395 ;
38397 ;
38398 else
38401 /* This is a blend, not a permute. Elements must stay in their
38402 respective lanes. */
38404 {
38408 }
38413 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38414 decision should be extracted elsewhere, so that we only try that
38415 sequence once all budget==3 options have been tried. */
38422 {
38446 /* See if bytes move in pairs so we can use pblendw with
38447 an immediate argument, rather than pblendvb with a vector
38448 argument. */
38451 {
38452 use_pblendvb:
38456 finish_pblendvb:
38462 else
38465 }
38470 /* FALLTHRU */
38472 do_subreg:
38479 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38483 /* See if bytes move in quadruplets. If yes, vpblendd
38484 with immediate can be used. */
38489 {
38490 /* See if bytes move the same in both lanes. If yes,
38491 vpblendw with immediate can be used. */
38496 /* Use vpblendw. */
38501 }
38503 /* Use vpblendd. */
38510 /* See if words move in pairs. If yes, vpblendd can be used. */
38515 {
38516 /* See if words move the same in both lanes. If not,
38517 vpblendvb must be used. */
38520 {
38521 /* Use vpblendvb. */
38531 }
38533 /* Use vpblendw. */
38537 }
38539 /* Use vpblendd. */
38546 /* Use vpblendd. */
38554 }
38556 /* This matches five different patterns with the different modes. */
38562 }
38564 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38565 in terms of the variable form of vpermilps.
38567 Note that we will have already failed the immediate input vpermilps,
38568 which requires that the high and low part shuffle be identical; the
38569 variable form doesn't require that. */
38571 static bool
38573 {
38580 /* We can only permute within the 128-bit lane. */
38582 {
38586 }
38592 {
38595 /* Within each 128-bit lane, the elements of op0 are numbered
38596 from 0 and the elements of op1 are numbered from 4. */
38603 }
38610 }
38612 /* Return true if permutation D can be performed as VMODE permutation
38613 instead. */
38615 static bool
38617 {
38632 else
38638 }
38640 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38641 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38643 static bool
38645 {
38654 {
38656 {
38659 {
38663 /* Use vperm2i128 insn. The pattern uses
38664 V4DImode instead of V2TImode. */
38673 }
38675 }
38676 }
38677 else
38678 {
38680 {
38683 }
38685 {
38689 /* V4DImode should be already handled through
38690 expand_vselect by vpermq instruction. */
38697 {
38698 /* First see if vpermq can be used for
38699 V8SImode/V16HImode/V32QImode. */
38701 {
38709 }
38711 /* Next see if vpermd can be used. */
38714 }
38715 /* Or if vpermps can be used. */
38720 {
38721 /* vpshufb only works intra lanes, it is not
38722 possible to shuffle bytes in between the lanes. */
38726 }
38727 }
38728 else
38730 }
38738 else
38739 {
38745 else
38749 {
38753 }
38754 }
38763 {
38770 else
38772 }
38773 else
38774 {
38777 }
38780 }
38782 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38783 in a single instruction. */
38785 static bool
38787 {
38791 /* Check plain VEC_SELECT first, because AVX has instructions that could
38792 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38793 input where SEL+CONCAT may not. */
38795 {
38801 {
38807 }
38810 {
38814 }
38816 {
38817 /* Use vpbroadcast{b,w,d}. */
38820 {
38839 /* For other modes prefer other shuffles this function creates. */
38841 }
38843 {
38847 }
38848 }
38853 /* There are plenty of patterns in sse.md that are written for
38854 SEL+CONCAT and are not replicated for a single op. Perhaps
38855 that should be changed, to avoid the nastiness here. */
38857 /* Recognize interleave style patterns, which means incrementing
38858 every other permutation operand. */
38860 {
38863 }
38868 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38870 {
38872 {
38877 }
38882 }
38883 }
38885 /* Finally, try the fully general two operand permute. */
38890 /* Recognize interleave style patterns with reversed operands. */
38892 {
38894 {
38898 else
38901 }
38906 }
38908 /* Try the SSE4.1 blend variable merge instructions. */
38912 /* Try one of the AVX vpermil variable permutations. */
38916 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38917 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38922 }
38924 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38925 in terms of a pair of pshuflw + pshufhw instructions. */
38927 static bool
38929 {
38937 /* The two permutations only operate in 64-bit lanes. */
38948 /* Emit the pshuflw. */
38955 /* Emit the pshufhw. */
38963 }
38965 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38966 the permutation using the SSSE3 palignr instruction. This succeeds
38967 when all of the elements in PERM fit within one vector and we merely
38968 need to shift them down so that a single vector permutation has a
38969 chance to succeed. */
38971 static bool
38973 {
38977 rtx shift;
38979 /* Even with AVX, palignr only operates on 128-bit vectors. */
38985 {
38991 }
38995 /* Given that we have SSSE3, we know we'll be able to implement the
38996 single operand permutation after the palignr with pshufb. */
39010 {
39015 }
39017 /* Test for the degenerate case where the alignment by itself
39018 produces the desired permutation. */
39026 }
39030 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39031 a two vector permutation into a single vector permutation by using
39032 an interleave operation to merge the vectors. */
39034 static bool
39036 {
39041 rtx seq;
39045 {
39048 }
39050 {
39053 /* For 32-byte modes allow even d->one_operand_p.
39054 The lack of cross-lane shuffling in some instructions
39055 might prevent a single insn shuffle. */
39058 /* If expand_vec_perm_interleave3 can expand this into
39059 a 3 insn sequence, give up and let it be expanded as
39060 3 insn sequence. While that is one insn longer,
39061 it doesn't need a memory operand and in the common
39062 case that both interleave low and high permutations
39063 with the same operands are adjacent needs 4 insns
39064 for both after CSE. */
39067 }
39068 else
39071 /* Examine from whence the elements come. */
39080 {
39083 /* Split the two input vectors into 4 halves. */
39089 /* If the elements from the low halves use interleave low, and similarly
39090 for interleave high. If the elements are from mis-matched halves, we
39091 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39093 {
39094 /* punpckl* */
39096 {
39101 }
39104 }
39106 {
39107 /* punpckh* */
39109 {
39114 }
39117 }
39119 {
39120 /* shufps */
39122 {
39127 }
39129 {
39130 /* shufpd */
39135 }
39136 }
39138 {
39139 /* shufps */
39141 {
39146 }
39148 {
39149 /* shufpd */
39154 }
39155 }
39156 else
39158 }
39159 else
39160 {
39165 /* Split the two input vectors into 8 quarters. */
39171 {
39174 }
39177 {
39181 }
39183 {
39186 }
39189 {
39191 {
39192 /* Attempt to increase the likelihood that dfinal
39193 shuffle will be intra-lane. */
39197 }
39199 /* vperm2f128 or vperm2i128. */
39201 {
39206 }
39211 {
39215 {
39218 }
39219 }
39220 }
39225 {
39226 /* vpunpckl* */
39228 {
39237 }
39238 }
39241 {
39242 /* vpunpckh* */
39244 {
39253 }
39254 }
39255 else
39257 }
39259 /* Use the remapping array set up above to move the elements from their
39260 swizzled locations into their final destinations. */
39263 {
39266 /* If same_halves is true, both halves of the remapped vector are the
39267 same. Avoid cross-lane accesses if possible. */
39269 {
39272 }
39273 else
39275 }
39281 /* Test if the final remap can be done with a single insn. For V4SFmode or
39282 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39295 {
39299 }
39306 }
39308 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39309 a single vector cross-lane permutation into vpermq followed
39310 by any of the single insn permutations. */
39312 static bool
39314 {
39328 {
39331 }
39334 {
39339 }
39352 {
39359 }
39366 {
39371 ;
39374 else
39376 }
39385 }
39387 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39388 a vector permutation using two instructions, vperm2f128 resp.
39389 vperm2i128 followed by any single in-lane permutation. */
39391 static bool
39393 {
39407 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39408 immediate. For perm < 16 the second permutation uses
39409 d->op0 as first operand, for perm >= 16 it uses d->op1
39410 as first operand. The second operand is the result of
39411 vperm2[fi]128. */
39413 {
39414 /* Ignore permutations which do not move anything cross-lane. */
39416 {
39417 /* The second shuffle for e.g. V4DFmode has
39418 0123 and ABCD operands.
39419 Ignore AB23, as 23 is already in the second lane
39420 of the first operand. */
39422 /* And 01CD, as 01 is in the first lane of the first
39423 operand. */
39425 /* And 4567, as then the vperm2[fi]128 doesn't change
39426 anything on the original 4567 second operand. */
39428 }
39429 else
39430 {
39431 /* The second shuffle for e.g. V4DFmode has
39432 4567 and ABCD operands.
39433 Ignore AB67, as 67 is already in the second lane
39434 of the first operand. */
39436 /* And 45CD, as 45 is in the first lane of the first
39437 operand. */
39439 /* And 0123, as then the vperm2[fi]128 doesn't change
39440 anything on the original 0123 first operand. */
39442 }
39445 {
39451 else
39453 }
39456 {
39460 }
39461 else
39465 {
39469 /* Found a usable second shuffle. dfirst will be
39470 vperm2f128 on d->op0 and d->op1. */
39481 /* And dsecond is some single insn shuffle, taking
39482 d->op0 and result of vperm2f128 (if perm < 16) or
39483 d->op1 and result of vperm2f128 (otherwise). */
39492 }
39494 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39497 }
39500 }
39502 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39503 a two vector permutation using 2 intra-lane interleave insns
39504 and cross-lane shuffle for 32-byte vectors. */
39506 static bool
39508 {
39515 ;
39517 ;
39518 else
39533 {
39537 else
39543 else
39549 else
39555 else
39561 else
39567 else
39572 }
39576 }
39578 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39579 a single vector permutation using a single intra-lane vector
39580 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39581 the non-swapped and swapped vectors together. */
39583 static bool
39585 {
39588 rtx seq;
39593 || TARGET_AVX2
39602 {
39609 }
39644 }
39646 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39647 permutation using two vperm2f128, followed by a vshufpd insn blending
39648 the two vectors together. */
39650 static bool
39652 {
39695 }
39697 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39698 permutation with two pshufb insns and an ior. We should have already
39699 failed all two instruction sequences. */
39701 static bool
39703 {
39714 /* Generate two permutation masks. If the required element is within
39715 the given vector it is shuffled into the proper lane. If the required
39716 element is in the other vector, force a zero into the lane by setting
39717 bit 7 in the permutation mask. */
39720 {
39727 {
39730 }
39731 }
39751 }
39753 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39754 with two vpshufb insns, vpermq and vpor. We should have already failed
39755 all two or three instruction sequences. */
39757 static bool
39759 {
39774 /* Generate two permutation masks. If the required element is within
39775 the same lane, it is shuffled in. If the required element from the
39776 other lane, force a zero by setting bit 7 in the permutation mask.
39777 In the other mask the mask has non-negative elements if element
39778 is requested from the other lane, but also moved to the other lane,
39779 so that the result of vpshufb can have the two V2TImode halves
39780 swapped. */
39783 {
39788 {
39791 }
39792 }
39801 /* Swap the 128-byte lanes of h into hp. */
39805 const1_rtx));
39818 }
39820 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39821 and extract-odd permutations of two V32QImode and V16QImode operand
39822 with two vpshufb insns, vpor and vpermq. We should have already
39823 failed all two or three instruction sequences. */
39825 static bool
39827 {
39846 /* Generate two permutation masks. In the first permutation mask
39847 the first quarter will contain indexes for the first half
39848 of the op0, the second quarter will contain bit 7 set, third quarter
39849 will contain indexes for the second half of the op0 and the
39850 last quarter bit 7 set. In the second permutation mask
39851 the first quarter will contain bit 7 set, the second quarter
39852 indexes for the first half of the op1, the third quarter bit 7 set
39853 and last quarter indexes for the second half of the op1.
39854 I.e. the first mask e.g. for V32QImode extract even will be:
39855 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39856 (all values masked with 0xf except for -128) and second mask
39857 for extract even will be
39858 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39861 {
39867 {
39870 }
39871 }
39890 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39897 }
39899 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39900 and extract-odd permutations. */
39902 static bool
39904 {
39908 {
39913 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39917 /* Now an unpck[lh]pd will produce the result required. */
39920 else
39926 {
39933 /* Shuffle within the 128-bit lanes to produce:
39934 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39938 /* Shuffle the lanes around to produce:
39939 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39943 /* Shuffle within the 128-bit lanes to produce:
39944 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39947 /* Shuffle within the 128-bit lanes to produce:
39948 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39951 /* Shuffle the lanes around to produce:
39952 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39955 }
39962 /* These are always directly implementable by expand_vec_perm_1. */
39968 else
39969 {
39970 /* We need 2*log2(N)-1 operations to achieve odd/even
39971 with interleave. */
39980 else
39983 }
39989 else
39990 {
40002 else
40005 }
40014 {
40021 }
40026 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40030 /* Now an vpunpck[lh]qdq will produce the result required. */
40033 else
40040 {
40047 }
40052 /* Shuffle the lanes around into
40053 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40063 /* Swap the 2nd and 3rd position in each lane into
40064 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40070 /* Now an vpunpck[lh]qdq will produce
40071 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40076 else
40085 }
40088 }
40090 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40091 extract-even and extract-odd permutations. */
40093 static bool
40095 {
40107 }
40109 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40110 permutations. We assume that expand_vec_perm_1 has already failed. */
40112 static bool
40114 {
40122 {
40125 /* These are special-cased in sse.md so that we can optionally
40126 use the vbroadcast instruction. They expand to two insns
40127 if the input happens to be in a register. */
40134 /* These are always implementable using standard shuffle patterns. */
40139 /* These can be implemented via interleave. We save one insn by
40140 stopping once we have promoted to V4SImode and then use pshufd. */
40141 do
40142 {
40143 rtx dest;
40149 {
40153 }
40160 }
40173 /* For AVX2 broadcasts of the first element vpbroadcast* or
40174 vpermq should be used by expand_vec_perm_1. */
40180 }
40181 }
40183 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40184 broadcast permutations. */
40186 static bool
40188 {
40200 }
40202 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40203 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40204 all the shorter instruction sequences. */
40206 static bool
40208 {
40224 /* Generate 4 permutation masks. If the required element is within
40225 the same lane, it is shuffled in. If the required element from the
40226 other lane, force a zero by setting bit 7 in the permutation mask.
40227 In the other mask the mask has non-negative elements if element
40228 is requested from the other lane, but also moved to the other lane,
40229 so that the result of vpshufb can have the two V2TImode halves
40230 swapped. */
40233 {
40238 }
40244 {
40252 }
40255 {
40257 {
40260 }
40267 }
40269 /* Swap the 128-byte lanes of h[X]. */
40271 {
40277 const1_rtx));
40279 }
40282 {
40284 {
40287 }
40293 }
40296 {
40298 {
40302 }
40305 }
40311 }
40313 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40314 With all of the interface bits taken care of, perform the expansion
40315 in D and return true on success. */
40317 static bool
40319 {
40320 /* Try a single instruction expansion. */
40324 /* Try sequences of two instructions. */
40344 /* Try sequences of three instructions. */
40358 /* Try sequences of four instructions. */
40366 /* ??? Look for narrow permutations whose element orderings would
40367 allow the promotion to a wider mode. */
40369 /* ??? Look for sequences of interleave or a wider permute that place
40370 the data into the correct lanes for a half-vector shuffle like
40371 pshuf[lh]w or vpermilps. */
40373 /* ??? Look for sequences of interleave that produce the desired results.
40374 The combinatorics of punpck[lh] get pretty ugly... */
40379 /* Even longer sequences. */
40384 }
40386 /* If a permutation only uses one operand, make it clear. Returns true
40387 if the permutation references both operands. */
40389 static bool
40391 {
40399 {
40405 {
40408 }
40409 /* The elements of PERM do not suggest that only the first operand
40410 is used, but both operands are identical. Allow easier matching
40411 of the permutation by folding the permutation into the single
40412 input vector. */
40413 /* FALLTHRU */
40424 }
40427 }
40429 bool
40431 {
40436 rtx sel;
40453 {
40458 }
40465 /* If the selector says both arguments are needed, but the operands are the
40466 same, the above tried to expand with one_operand_p and flattened selector.
40467 If that didn't work, retry without one_operand_p; we succeeded with that
40468 during testing. */
40470 {
40474 }
40477 }
40479 /* Implement targetm.vectorize.vec_perm_const_ok. */
40481 static bool
40484 {
40493 /* Given sufficient ISA support we can just return true here
40494 for selected vector modes. */
40496 {
40497 /* All implementable with a single vpperm insn. */
40500 /* All implementable with 2 pshufb + 1 ior. */
40503 /* All implementable with shufpd or unpck[lh]pd. */
40506 }
40508 /* Extract the values from the vector CST into the permutation
40509 array in D. */
40512 {
40516 }
40518 /* For all elements from second vector, fold the elements to first. */
40523 /* Check whether the mask can be applied to the vector type. */
40526 /* Implementable with shufps or pshufd. */
40530 /* Otherwise we have to go through the motions and see if we can
40531 figure out how to generate the requested permutation. */
40542 }
40544 void
40546 {
40561 /* We'll either be able to implement the permutation directly... */
40565 /* ... or we use the special-case patterns. */
40567 }
40569 static void
40571 {
40586 {
40589 }
40591 /* Note that for AVX this isn't one instruction. */
40594 }
40597 /* Expand a vector operation CODE for a V*QImode in terms of the
40598 same operation on V*HImode. */
40600 void
40602 {
40614 {
40627 }
40631 {
40633 /* Unpack data such that we've got a source byte in each low byte of
40634 each word. We don't care what goes into the high byte of each word.
40635 Rather than trying to get zero in there, most convenient is to let
40636 it be a copy of the low byte. */
40641 /* FALLTHRU */
40653 /* FALLTHRU */
40663 }
40665 /* Perform the operation. */
40672 /* Merge the data back into the right place. */
40682 {
40683 /* For SSE2, we used an full interleave, so the desired
40684 results are in the even elements. */
40687 }
40688 else
40689 {
40690 /* For AVX, the interleave used above was not cross-lane. So the
40691 extraction is evens but with the second and third quarter swapped.
40692 Happily, that is even one insn shorter than even extraction. */
40695 }
40702 }
40704 void
40707 {
40710 rtx x;
40712 /* We only play even/odd games with vectors of SImode. */
40715 /* If we're looking for the odd results, shift those members down to
40716 the even slots. For some cpus this is faster than a PSHUFD. */
40718 {
40720 {
40724 }
40733 }
40736 {
40739 else
40741 }
40746 else
40747 {
40750 /* The easiest way to implement this without PMULDQ is to go through
40751 the motions as if we are performing a full 64-bit multiply. With
40752 the exception that we need to do less shuffling of the elements. */
40754 /* Compute the sign-extension, aka highparts, of the two operands. */
40760 /* Multiply LO(A) * HI(B), and vice-versa. */
40766 /* Multiply LO(A) * LO(B). */
40770 /* Combine and shift the highparts into place. */
40775 /* Combine high and low parts. */
40778 }
40780 }
40782 void
40785 {
40791 {
40796 {
40797 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40798 shuffle the elements once so that all elements are in the right
40799 place for immediate use: { A C B D }. */
40804 }
40805 else
40806 {
40807 /* Put the elements into place for the multiply. */
40811 }
40816 /* Shuffle the elements between the lanes. After this we
40817 have { A B E F | C D G H } for each operand. */
40827 /* Shuffle the elements within the lanes. After this we
40828 have { A A B B | C C D D } or { E E F F | G G H H }. */
40864 }
40865 }
40867 void
40869 {
40879 /* Move the results in element 2 down to element 1; we don't care
40880 what goes in elements 2 and 3. Then we can merge the parts
40881 back together with an interleave.
40883 Note that two other sequences were tried:
40884 (1) Use interleaves at the start instead of psrldq, which allows
40885 us to use a single shufps to merge things back at the end.
40886 (2) Use shufps here to combine the two vectors, then pshufd to
40887 put the elements in the correct order.
40888 In both cases the cost of the reformatting stall was too high
40889 and the overall sequence slower. */
40898 }
40900 void
40902 {
40907 {
40908 /* op1: A,B,C,D, op2: E,F,G,H */
40917 /* t1: B,A,D,C */
40924 /* t2: (B*E),(A*F),(D*G),(C*H) */
40927 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40930 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40933 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40935 }
40936 else
40937 {
40942 {
40945 }
40947 {
40950 }
40951 else
40955 /* Multiply low parts. */
40959 /* Shift input vectors right 32 bits so we can multiply high parts. */
40964 /* Multiply high parts by low parts. */
40970 /* Combine and shift the highparts back. */
40974 /* Combine high and low parts. */
40976 }
40980 }
40982 /* Expand an insert into a vector register through pinsr insn.
40983 Return true if successful. */
40985 bool
40987 {
40995 {
40998 }
41004 {
41009 {
41016 {
41048 }
41057 }
41061 }
41062 }
41063 \f
41064 /* This function returns the calling abi specific va_list type node.
41065 It returns the FNDECL specific va_list type. */
41067 static tree
41069 {
41076 else
41078 }
41080 /* Returns the canonical va_list type specified by TYPE. If there
41081 is no valid TYPE provided, it return NULL_TREE. */
41083 static tree
41085 {
41088 /* Resolve references and pointers to va_list type. */
41097 {
41102 {
41103 /* If va_list is an array type, the argument may have decayed
41104 to a pointer type, e.g. by being passed to another function.
41105 In that case, unwrap both types so that we can compare the
41106 underlying records. */
41109 {
41112 }
41113 }
41120 {
41121 /* If va_list is an array type, the argument may have decayed
41122 to a pointer type, e.g. by being passed to another function.
41123 In that case, unwrap both types so that we can compare the
41124 underlying records. */
41127 {
41130 }
41131 }
41138 {
41139 /* If va_list is an array type, the argument may have decayed
41140 to a pointer type, e.g. by being passed to another function.
41141 In that case, unwrap both types so that we can compare the
41142 underlying records. */
41145 {
41148 }
41149 }
41153 }
41155 }
41157 /* Iterate through the target-specific builtin types for va_list.
41158 IDX denotes the iterator, *PTREE is set to the result type of
41159 the va_list builtin, and *PNAME to its internal type.
41160 Returns zero if there is no element for this index, otherwise
41161 IDX should be increased upon the next call.
41162 Note, do not iterate a base builtin's name like __builtin_va_list.
41163 Used from c_common_nodes_and_builtins. */
41165 static int
41167 {
41169 {
41171 {
41184 }
41185 }
41188 }
41190 #undef TARGET_SCHED_DISPATCH
41191 #define TARGET_SCHED_DISPATCH has_dispatch
41192 #undef TARGET_SCHED_DISPATCH_DO
41193 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41194 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41195 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41196 #undef TARGET_SCHED_REORDER
41197 #define TARGET_SCHED_REORDER ix86_sched_reorder
41198 #undef TARGET_SCHED_ADJUST_PRIORITY
41199 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41200 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41201 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41203 /* The size of the dispatch window is the total number of bytes of
41204 object code allowed in a window. */
41205 #define DISPATCH_WINDOW_SIZE 16
41207 /* Number of dispatch windows considered for scheduling. */
41208 #define MAX_DISPATCH_WINDOWS 3
41210 /* Maximum number of instructions in a window. */
41211 #define MAX_INSN 4
41213 /* Maximum number of immediate operands in a window. */
41214 #define MAX_IMM 4
41216 /* Maximum number of immediate bits allowed in a window. */
41217 #define MAX_IMM_SIZE 128
41219 /* Maximum number of 32 bit immediates allowed in a window. */
41220 #define MAX_IMM_32 4
41222 /* Maximum number of 64 bit immediates allowed in a window. */
41223 #define MAX_IMM_64 2
41225 /* Maximum total of loads or prefetches allowed in a window. */
41226 #define MAX_LOAD 2
41228 /* Maximum total of stores allowed in a window. */
41229 #define MAX_STORE 1
41231 #undef BIG
41232 #define BIG 100
41235 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41238 disp_load,
41239 disp_store,
41240 disp_load_store,
41241 disp_prefetch,
41242 disp_imm,
41243 disp_imm_32,
41244 disp_imm_64,
41245 disp_branch,
41246 disp_cmp,
41247 disp_jcc,
41248 disp_last
41249 };
41251 /* Number of allowable groups in a dispatch window. It is an array
41252 indexed by dispatch_group enum. 100 is used as a big number,
41253 because the number of these kind of operations does not have any
41254 effect in dispatch window, but we need them for other reasons in
41255 the table. */
41258 };
41264 };
41266 /* Instruction path. */
41272 last_path
41273 };
41275 /* sched_insn_info defines a window to the instructions scheduled in
41276 the basic block. It contains a pointer to the insn_info table and
41277 the instruction scheduled.
41279 Windows are allocated for each basic block and are linked
41280 together. */
41282 rtx insn;
41289 /* Linked list of dispatch windows. This is a two way list of
41290 dispatch windows of a basic block. It contains information about
41291 the number of uops in the window and the total number of
41292 instructions and of bytes in the object code for this dispatch
41293 window. */
41311 /* Immediate valuse used in an insn. */
41313 {
41322 /* Get dispatch group of insn. */
41324 static enum dispatch_group
41326 {
41342 }
41344 /* Return true if insn is a compare instruction. */
41346 static bool
41348 {
41356 }
41358 /* Return true if a dispatch violation encountered. */
41360 static bool
41362 {
41366 }
41368 /* Return true if insn is a branch instruction. */
41370 static bool
41372 {
41374 }
41376 /* Return true if insn is a prefetch instruction. */
41378 static bool
41380 {
41382 }
41384 /* This function initializes a dispatch window and the list container holding a
41385 pointer to the window. */
41387 static void
41389 {
41395 else
41413 {
41419 }
41421 }
41423 /* This function allocates and initializes a dispatch window and the
41424 list container holding a pointer to the window. */
41428 {
41433 }
41435 /* This routine initializes the dispatch scheduling information. It
41436 initiates building dispatch scheduler tables and constructs the
41437 first dispatch window. */
41439 static void
41441 {
41442 /* Allocate a dispatch list and a window. */
41447 }
41449 /* This function returns true if a branch is detected. End of a basic block
41450 does not have to be a branch, but here we assume only branches end a
41451 window. */
41453 static bool
41455 {
41457 }
41459 /* This function is called when the end of a window processing is reached. */
41461 static void
41463 {
41466 {
41471 }
41473 }
41475 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41476 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41477 for 48 bytes of instructions. Note that these windows are not dispatch
41478 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41482 {
41484 {
41489 }
41495 }
41497 /* Increment the number of immediate operands of an instruction. */
41499 static int
41501 {
41506 {
41513 else
41524 {
41527 }
41532 }
41535 }
41537 /* Compute number of immediate operands of an instruction. */
41539 static void
41541 {
41544 }
41546 /* Return total size of immediate operands of an instruction along with number
41547 of corresponding immediate-operands. It initializes its parameters to zero
41548 befor calling FIND_CONSTANT.
41549 INSN is the input instruction. IMM is the total of immediates.
41550 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41551 bit immediates. */
41553 static int
41555 {
41563 }
41565 /* This function indicates if an operand of an instruction is an
41566 immediate. */
41568 static bool
41570 {
41579 }
41581 /* Return single or double path for instructions. */
41583 static enum insn_path
41585 {
41595 }
41597 /* Return insn dispatch group. */
41599 static enum dispatch_group
41601 {
41619 }
41621 /* Count number of GROUP restricted instructions in a dispatch
41622 window WINDOW_LIST. */
41624 static int
41626 {
41637 {
41656 }
41669 }
41671 /* This function returns true if insn satisfies dispatch rules on the
41672 last window scheduled. */
41674 static bool
41676 {
41684 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41685 instructions should be given the lowest priority in the
41686 scheduling process in Haifa scheduler to make sure they will be
41687 scheduled in the same dispatch window as the reference to them. */
41691 /* Check nonrestricted. */
41695 /* Get last dispatch window. */
41700 {
41705 /* Window 1 is full. Go for next window. */
41707 }
41714 /* See if it fits in the first window. */
41716 {
41717 /* The first widow should have only single and double path
41718 uops. */
41724 }
41726 }
41728 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41729 dispatch window WINDOW_LIST. */
41731 static void
41733 {
41751 /* Initialize window with new instruction. */
41772 {
41775 }
41776 }
41778 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41779 If the total bytes of instructions or the number of instructions in
41780 the window exceed allowable, it allocates a new window. */
41782 static void
41784 {
41807 /* Get the last dispatch window. */
41815 else
41818 /* If current window is full, get a new window.
41819 Window number zero is full, if MAX_INSN uops are scheduled in it.
41820 Window number one is full, if window zero's bytes plus window
41821 one's bytes is 32, or if the bytes of the new instruction added
41822 to the total makes it greater than 48, or it has already MAX_INSN
41823 instructions in it. */
41832 {
41835 }
41838 {
41842 {
41845 }
41846 }
41848 {
41853 {
41856 }
41859 }
41860 else
41864 {
41865 /* End of basic block is reached do end-basic-block process. */
41868 }
41869 }
41871 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41873 DEBUG_FUNCTION static void
41875 {
41881 else
41895 {
41898 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41904 }
41905 }
41907 /* Print to stdout a dispatch window. */
41909 DEBUG_FUNCTION void
41911 {
41913 }
41915 /* Print INSN dispatch information to FILE. */
41917 DEBUG_FUNCTION static void
41919 {
41942 }
41944 /* Print to STDERR the status of the ready list with respect to
41945 dispatch windows. */
41947 DEBUG_FUNCTION void
41949 {
41957 }
41959 /* This routine is the driver of the dispatch scheduler. */
41961 static void
41963 {
41968 }
41970 /* Return TRUE if Dispatch Scheduling is supported. */
41972 static bool
41974 {
41978 {
41994 }
41997 }
41999 /* Implementation of reassociation_width target hook used by
42000 reassoc phase to identify parallelism level in reassociated
42001 tree. Statements tree_code is passed in OPC. Arguments type
42002 is passed in MODE.
42004 Currently parallel reassociation is enabled for Atom
42005 processors only and we set reassociation width to be 2
42006 because Atom may issue up to 2 instructions per cycle.
42008 Return value should be fixed if parallel reassociation is
42009 enabled for other processors. */
42011 static int
42014 {
42023 }
42025 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42026 place emms and femms instructions. */
42028 static enum machine_mode
42030 {
42035 {
42048 else
42058 /* FALLTHRU */
42062 }
42063 }
42065 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42066 vectors. */
42068 static unsigned int
42070 {
42072 }
42074 \f
42076 /* Return class of registers which could be used for pseudo of MODE
42077 and of class RCLASS for spilling instead of memory. Return NO_REGS
42078 if it is not possible or non-profitable. */
42079 static reg_class_t
42081 {
42087 }
42089 /* Implement targetm.vectorize.init_cost. */
42093 {
42097 }
42099 /* Implement targetm.vectorize.add_stmt_cost. */
42101 static unsigned
42105 {
42110 {
42114 /* Statements in an inner loop relative to the loop being
42115 vectorized are weighted more heavily. The value here is
42116 arbitrary and could potentially be improved with analysis. */
42122 }
42125 }
42127 /* Implement targetm.vectorize.finish_cost. */
42129 static void
42132 {
42137 }
42139 /* Implement targetm.vectorize.destroy_cost_data. */
42141 static void
42143 {
42145 }
42147 /* Validate target specific memory model bits in VAL. */
42149 static unsigned HOST_WIDE_INT
42151 {
42158 {
42162 }
42165 {
42169 }
42171 {
42175 }
42177 }
42179 /* Initialize the GCC target structure. */
42180 #undef TARGET_RETURN_IN_MEMORY
42181 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42183 #undef TARGET_LEGITIMIZE_ADDRESS
42184 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42186 #undef TARGET_ATTRIBUTE_TABLE
42187 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42188 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42189 # undef TARGET_MERGE_DECL_ATTRIBUTES
42190 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42191 #endif
42193 #undef TARGET_COMP_TYPE_ATTRIBUTES
42194 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42196 #undef TARGET_INIT_BUILTINS
42197 #define TARGET_INIT_BUILTINS ix86_init_builtins
42198 #undef TARGET_BUILTIN_DECL
42199 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42200 #undef TARGET_EXPAND_BUILTIN
42201 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42203 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42204 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42205 ix86_builtin_vectorized_function
42207 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42208 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42210 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42211 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42213 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42214 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42216 #undef TARGET_BUILTIN_RECIPROCAL
42217 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42219 #undef TARGET_ASM_FUNCTION_EPILOGUE
42220 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42222 #undef TARGET_ENCODE_SECTION_INFO
42223 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42224 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42225 #else
42226 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42227 #endif
42229 #undef TARGET_ASM_OPEN_PAREN
42231 #undef TARGET_ASM_CLOSE_PAREN
42234 #undef TARGET_ASM_BYTE_OP
42235 #define TARGET_ASM_BYTE_OP ASM_BYTE
42237 #undef TARGET_ASM_ALIGNED_HI_OP
42238 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42239 #undef TARGET_ASM_ALIGNED_SI_OP
42240 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42241 #ifdef ASM_QUAD
42242 #undef TARGET_ASM_ALIGNED_DI_OP
42243 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42244 #endif
42246 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42247 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42249 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42250 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42252 #undef TARGET_ASM_UNALIGNED_HI_OP
42253 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42254 #undef TARGET_ASM_UNALIGNED_SI_OP
42255 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42256 #undef TARGET_ASM_UNALIGNED_DI_OP
42257 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42259 #undef TARGET_PRINT_OPERAND
42260 #define TARGET_PRINT_OPERAND ix86_print_operand
42261 #undef TARGET_PRINT_OPERAND_ADDRESS
42262 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42263 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42264 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42265 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42266 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42268 #undef TARGET_SCHED_INIT_GLOBAL
42269 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42270 #undef TARGET_SCHED_ADJUST_COST
42271 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42272 #undef TARGET_SCHED_ISSUE_RATE
42273 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42274 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42275 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42276 ia32_multipass_dfa_lookahead
42278 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42279 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42281 #undef TARGET_MEMMODEL_CHECK
42282 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42284 #ifdef HAVE_AS_TLS
42285 #undef TARGET_HAVE_TLS
42286 #define TARGET_HAVE_TLS true
42287 #endif
42288 #undef TARGET_CANNOT_FORCE_CONST_MEM
42289 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42290 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42291 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42293 #undef TARGET_DELEGITIMIZE_ADDRESS
42294 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42296 #undef TARGET_MS_BITFIELD_LAYOUT_P
42297 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42299 #if TARGET_MACHO
42300 #undef TARGET_BINDS_LOCAL_P
42301 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42302 #endif
42303 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42304 #undef TARGET_BINDS_LOCAL_P
42305 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42306 #endif
42308 #undef TARGET_ASM_OUTPUT_MI_THUNK
42309 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42310 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42311 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42313 #undef TARGET_ASM_FILE_START
42314 #define TARGET_ASM_FILE_START x86_file_start
42316 #undef TARGET_OPTION_OVERRIDE
42317 #define TARGET_OPTION_OVERRIDE ix86_option_override
42319 #undef TARGET_REGISTER_MOVE_COST
42320 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42321 #undef TARGET_MEMORY_MOVE_COST
42322 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42323 #undef TARGET_RTX_COSTS
42324 #define TARGET_RTX_COSTS ix86_rtx_costs
42325 #undef TARGET_ADDRESS_COST
42326 #define TARGET_ADDRESS_COST ix86_address_cost
42328 #undef TARGET_FIXED_CONDITION_CODE_REGS
42329 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42330 #undef TARGET_CC_MODES_COMPATIBLE
42331 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42333 #undef TARGET_MACHINE_DEPENDENT_REORG
42334 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42336 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42337 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42339 #undef TARGET_BUILD_BUILTIN_VA_LIST
42340 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42342 #undef TARGET_FOLD_BUILTIN
42343 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42345 #undef TARGET_COMPARE_VERSION_PRIORITY
42346 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42348 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42349 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42350 ix86_generate_version_dispatcher_body
42352 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42353 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42354 ix86_get_function_versions_dispatcher
42356 #undef TARGET_ENUM_VA_LIST_P
42357 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42359 #undef TARGET_FN_ABI_VA_LIST
42360 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42362 #undef TARGET_CANONICAL_VA_LIST_TYPE
42363 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42365 #undef TARGET_EXPAND_BUILTIN_VA_START
42366 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42368 #undef TARGET_MD_ASM_CLOBBERS
42369 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42371 #undef TARGET_PROMOTE_PROTOTYPES
42372 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42373 #undef TARGET_STRUCT_VALUE_RTX
42374 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42375 #undef TARGET_SETUP_INCOMING_VARARGS
42376 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42377 #undef TARGET_MUST_PASS_IN_STACK
42378 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42379 #undef TARGET_FUNCTION_ARG_ADVANCE
42380 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42381 #undef TARGET_FUNCTION_ARG
42382 #define TARGET_FUNCTION_ARG ix86_function_arg
42383 #undef TARGET_FUNCTION_ARG_BOUNDARY
42384 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42385 #undef TARGET_PASS_BY_REFERENCE
42386 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42387 #undef TARGET_INTERNAL_ARG_POINTER
42388 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42389 #undef TARGET_UPDATE_STACK_BOUNDARY
42390 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42391 #undef TARGET_GET_DRAP_RTX
42392 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42393 #undef TARGET_STRICT_ARGUMENT_NAMING
42394 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42395 #undef TARGET_STATIC_CHAIN
42396 #define TARGET_STATIC_CHAIN ix86_static_chain
42397 #undef TARGET_TRAMPOLINE_INIT
42398 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42399 #undef TARGET_RETURN_POPS_ARGS
42400 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42402 #undef TARGET_LEGITIMATE_COMBINED_INSN
42403 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42405 #undef TARGET_ASAN_SHADOW_OFFSET
42406 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42408 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42409 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42411 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42412 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42414 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42415 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42417 #undef TARGET_C_MODE_FOR_SUFFIX
42418 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42420 #ifdef HAVE_AS_TLS
42421 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42422 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42423 #endif
42425 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42426 #undef TARGET_INSERT_ATTRIBUTES
42427 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42428 #endif
42430 #undef TARGET_MANGLE_TYPE
42431 #define TARGET_MANGLE_TYPE ix86_mangle_type
42433 #if !TARGET_MACHO
42434 #undef TARGET_STACK_PROTECT_FAIL
42435 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42436 #endif
42438 #undef TARGET_FUNCTION_VALUE
42439 #define TARGET_FUNCTION_VALUE ix86_function_value
42441 #undef TARGET_FUNCTION_VALUE_REGNO_P
42442 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42444 #undef TARGET_PROMOTE_FUNCTION_MODE
42445 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42447 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42448 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42450 #undef TARGET_INSTANTIATE_DECLS
42451 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42453 #undef TARGET_SECONDARY_RELOAD
42454 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42456 #undef TARGET_CLASS_MAX_NREGS
42457 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42459 #undef TARGET_PREFERRED_RELOAD_CLASS
42460 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42461 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42462 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42463 #undef TARGET_CLASS_LIKELY_SPILLED_P
42464 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42466 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42467 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42468 ix86_builtin_vectorization_cost
42469 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42470 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42471 ix86_vectorize_vec_perm_const_ok
42472 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42473 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42474 ix86_preferred_simd_mode
42475 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42476 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42477 ix86_autovectorize_vector_sizes
42478 #undef TARGET_VECTORIZE_INIT_COST
42479 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42480 #undef TARGET_VECTORIZE_ADD_STMT_COST
42481 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42482 #undef TARGET_VECTORIZE_FINISH_COST
42483 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42484 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42485 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42487 #undef TARGET_SET_CURRENT_FUNCTION
42488 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42490 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42491 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42493 #undef TARGET_OPTION_SAVE
42494 #define TARGET_OPTION_SAVE ix86_function_specific_save
42496 #undef TARGET_OPTION_RESTORE
42497 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42499 #undef TARGET_OPTION_PRINT
42500 #define TARGET_OPTION_PRINT ix86_function_specific_print
42502 #undef TARGET_OPTION_FUNCTION_VERSIONS
42503 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42505 #undef TARGET_CAN_INLINE_P
42506 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42508 #undef TARGET_EXPAND_TO_RTL_HOOK
42509 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42511 #undef TARGET_LEGITIMATE_ADDRESS_P
42512 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42514 #undef TARGET_LRA_P
42515 #define TARGET_LRA_P hook_bool_void_true
42517 #undef TARGET_REGISTER_PRIORITY
42518 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42520 #undef TARGET_LEGITIMATE_CONSTANT_P
42521 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42523 #undef TARGET_FRAME_POINTER_REQUIRED
42524 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42526 #undef TARGET_CAN_ELIMINATE
42527 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42529 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42530 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42532 #undef TARGET_ASM_CODE_END
42533 #define TARGET_ASM_CODE_END ix86_code_end
42535 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42536 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42538 #if TARGET_MACHO
42539 #undef TARGET_INIT_LIBFUNCS
42540 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42541 #endif
42543 #undef TARGET_SPILL_CLASS
42544 #define TARGET_SPILL_CLASS ix86_spill_class
42547 \f