1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
52 enum reg_class regno_reg_class
[] =
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
64 /* The minimum number of integer registers that we want to save with the
65 movem instruction. Using two movel instructions instead of a single
66 moveml is about 15% faster for the 68020 and 68030 at no expense in
68 #define MIN_MOVEM_REGS 3
70 /* The minimum number of floating point registers that we want to save
71 with the fmovem instruction. */
72 #define MIN_FMOVEM_REGS 1
74 /* Structure describing stack frame layout. */
77 /* Stack pointer to frame pointer offset. */
80 /* Offset of FPU registers. */
81 HOST_WIDE_INT foffset
;
83 /* Frame size in bytes (rounded up). */
86 /* Data and address register. */
88 unsigned int reg_mask
;
92 unsigned int fpu_mask
;
94 /* Offsets relative to ARG_POINTER. */
95 HOST_WIDE_INT frame_pointer_offset
;
96 HOST_WIDE_INT stack_pointer_offset
;
98 /* Function which the above information refers to. */
102 /* Current frame information calculated by m68k_compute_frame_layout(). */
103 static struct m68k_frame current_frame
;
105 /* Structure describing an m68k address.
107 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
108 with null fields evaluating to 0. Here:
110 - BASE satisfies m68k_legitimate_base_reg_p
111 - INDEX satisfies m68k_legitimate_index_reg_p
112 - OFFSET satisfies m68k_legitimate_constant_address_p
114 INDEX is either HImode or SImode. The other fields are SImode.
116 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
117 the address is (BASE)+. */
118 struct m68k_address
{
126 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
127 static int m68k_sched_issue_rate (void);
128 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
129 static void m68k_sched_md_init_global (FILE *, int, int);
130 static void m68k_sched_md_finish_global (FILE *, int);
131 static void m68k_sched_md_init (FILE *, int, int);
132 static void m68k_sched_dfa_pre_advance_cycle (void);
133 static void m68k_sched_dfa_post_advance_cycle (void);
134 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
136 static bool m68k_can_eliminate (const int, const int);
137 static void m68k_conditional_register_usage (void);
138 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
139 static void m68k_option_override (void);
140 static void m68k_override_options_after_change (void);
141 static rtx
find_addr_reg (rtx
);
142 static const char *singlemove_string (rtx
*);
143 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
144 HOST_WIDE_INT
, tree
);
145 static rtx
m68k_struct_value_rtx (tree
, int);
146 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
147 tree args
, int flags
,
149 static void m68k_compute_frame_layout (void);
150 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
151 static bool m68k_ok_for_sibcall_p (tree
, tree
);
152 static bool m68k_tls_symbol_p (rtx
);
153 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
154 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
155 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
156 static bool m68k_return_in_memory (const_tree
, const_tree
);
158 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
159 static void m68k_trampoline_init (rtx
, tree
, rtx
);
160 static int m68k_return_pops_args (tree
, tree
, int);
161 static rtx
m68k_delegitimize_address (rtx
);
162 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
164 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
166 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
167 static bool m68k_output_addr_const_extra (FILE *, rtx
);
168 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
170 /* Initialize the GCC target structure. */
172 #if INT_OP_GROUP == INT_OP_DOT_WORD
173 #undef TARGET_ASM_ALIGNED_HI_OP
174 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
177 #if INT_OP_GROUP == INT_OP_NO_DOT
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tbyte\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
186 #if INT_OP_GROUP == INT_OP_DC
187 #undef TARGET_ASM_BYTE_OP
188 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
195 #undef TARGET_ASM_UNALIGNED_HI_OP
196 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
197 #undef TARGET_ASM_UNALIGNED_SI_OP
198 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
200 #undef TARGET_ASM_OUTPUT_MI_THUNK
201 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
202 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
203 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
205 #undef TARGET_ASM_FILE_START_APP_OFF
206 #define TARGET_ASM_FILE_START_APP_OFF true
208 #undef TARGET_LEGITIMIZE_ADDRESS
209 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
211 #undef TARGET_SCHED_ADJUST_COST
212 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
214 #undef TARGET_SCHED_ISSUE_RATE
215 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
217 #undef TARGET_SCHED_VARIABLE_ISSUE
218 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
220 #undef TARGET_SCHED_INIT_GLOBAL
221 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
223 #undef TARGET_SCHED_FINISH_GLOBAL
224 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
226 #undef TARGET_SCHED_INIT
227 #define TARGET_SCHED_INIT m68k_sched_md_init
229 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
230 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
232 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
233 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
235 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
236 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
237 m68k_sched_first_cycle_multipass_dfa_lookahead
239 #undef TARGET_OPTION_OVERRIDE
240 #define TARGET_OPTION_OVERRIDE m68k_option_override
242 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
243 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
245 #undef TARGET_RTX_COSTS
246 #define TARGET_RTX_COSTS m68k_rtx_costs
248 #undef TARGET_ATTRIBUTE_TABLE
249 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
251 #undef TARGET_PROMOTE_PROTOTYPES
252 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
254 #undef TARGET_STRUCT_VALUE_RTX
255 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
257 #undef TARGET_CANNOT_FORCE_CONST_MEM
258 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
263 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
264 #undef TARGET_RETURN_IN_MEMORY
265 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
269 #undef TARGET_HAVE_TLS
270 #define TARGET_HAVE_TLS (true)
272 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
273 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
276 #undef TARGET_LEGITIMATE_ADDRESS_P
277 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
279 #undef TARGET_CAN_ELIMINATE
280 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
282 #undef TARGET_CONDITIONAL_REGISTER_USAGE
283 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
285 #undef TARGET_TRAMPOLINE_INIT
286 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
288 #undef TARGET_RETURN_POPS_ARGS
289 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
291 #undef TARGET_DELEGITIMIZE_ADDRESS
292 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
294 #undef TARGET_FUNCTION_ARG
295 #define TARGET_FUNCTION_ARG m68k_function_arg
297 #undef TARGET_FUNCTION_ARG_ADVANCE
298 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
300 #undef TARGET_LEGITIMATE_CONSTANT_P
301 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
303 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
304 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
306 static const struct attribute_spec m68k_attribute_table
[] =
308 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
309 affects_type_identity } */
310 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
312 { "interrupt_handler", 0, 0, true, false, false,
313 m68k_handle_fndecl_attribute
, false },
314 { "interrupt_thread", 0, 0, true, false, false,
315 m68k_handle_fndecl_attribute
, false },
316 { NULL
, 0, 0, false, false, false, NULL
, false }
319 struct gcc_target targetm
= TARGET_INITIALIZER
;
321 /* Base flags for 68k ISAs. */
322 #define FL_FOR_isa_00 FL_ISA_68000
323 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
324 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
325 generated 68881 code for 68020 and 68030 targets unless explicitly told
327 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
328 | FL_BITFIELD | FL_68881 | FL_CAS)
329 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
330 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
332 /* Base flags for ColdFire ISAs. */
333 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
334 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
335 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
336 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
337 /* ISA_C is not upwardly compatible with ISA_B. */
338 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
342 /* Traditional 68000 instruction sets. */
348 /* ColdFire instruction set variants. */
356 /* Information about one of the -march, -mcpu or -mtune arguments. */
357 struct m68k_target_selection
359 /* The argument being described. */
362 /* For -mcpu, this is the device selected by the option.
363 For -mtune and -march, it is a representative device
364 for the microarchitecture or ISA respectively. */
365 enum target_device device
;
367 /* The M68K_DEVICE fields associated with DEVICE. See the comment
368 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
370 enum uarch_type microarch
;
375 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
376 static const struct m68k_target_selection all_devices
[] =
378 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
379 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
380 #include "m68k-devices.def"
382 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
385 /* A list of all ISAs, mapping each one to a representative device.
386 Used for -march selection. */
387 static const struct m68k_target_selection all_isas
[] =
389 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
390 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
391 #include "m68k-isas.def"
393 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
396 /* A list of all microarchitectures, mapping each one to a representative
397 device. Used for -mtune selection. */
398 static const struct m68k_target_selection all_microarchs
[] =
400 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
401 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
402 #include "m68k-microarchs.def"
403 #undef M68K_MICROARCH
404 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
407 /* The entries associated with the -mcpu, -march and -mtune settings,
408 or null for options that have not been used. */
409 const struct m68k_target_selection
*m68k_cpu_entry
;
410 const struct m68k_target_selection
*m68k_arch_entry
;
411 const struct m68k_target_selection
*m68k_tune_entry
;
413 /* Which CPU we are generating code for. */
414 enum target_device m68k_cpu
;
416 /* Which microarchitecture to tune for. */
417 enum uarch_type m68k_tune
;
419 /* Which FPU to use. */
420 enum fpu_type m68k_fpu
;
422 /* The set of FL_* flags that apply to the target processor. */
423 unsigned int m68k_cpu_flags
;
425 /* The set of FL_* flags that apply to the processor to be tuned for. */
426 unsigned int m68k_tune_flags
;
428 /* Asm templates for calling or jumping to an arbitrary symbolic address,
429 or NULL if such calls or jumps are not supported. The address is held
431 const char *m68k_symbolic_call
;
432 const char *m68k_symbolic_jump
;
434 /* Enum variable that corresponds to m68k_symbolic_call values. */
435 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
438 /* Implement TARGET_OPTION_OVERRIDE. */
441 m68k_option_override (void)
443 const struct m68k_target_selection
*entry
;
444 unsigned long target_mask
;
446 if (global_options_set
.x_m68k_arch_option
)
447 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
449 if (global_options_set
.x_m68k_cpu_option
)
450 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
452 if (global_options_set
.x_m68k_tune_option
)
453 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
461 -march=ARCH should generate code that runs any processor
462 implementing architecture ARCH. -mcpu=CPU should override -march
463 and should generate code that runs on processor CPU, making free
464 use of any instructions that CPU understands. -mtune=UARCH applies
465 on top of -mcpu or -march and optimizes the code for UARCH. It does
466 not change the target architecture. */
469 /* Complain if the -march setting is for a different microarchitecture,
470 or includes flags that the -mcpu setting doesn't. */
472 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
473 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
474 warning (0, "-mcpu=%s conflicts with -march=%s",
475 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
477 entry
= m68k_cpu_entry
;
480 entry
= m68k_arch_entry
;
483 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
485 m68k_cpu_flags
= entry
->flags
;
487 /* Use the architecture setting to derive default values for
491 /* ColdFire is lenient about alignment. */
492 if (!TARGET_COLDFIRE
)
493 target_mask
|= MASK_STRICT_ALIGNMENT
;
495 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
496 target_mask
|= MASK_BITFIELD
;
497 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
498 target_mask
|= MASK_CF_HWDIV
;
499 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
500 target_mask
|= MASK_HARD_FLOAT
;
501 target_flags
|= target_mask
& ~target_flags_explicit
;
503 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
504 m68k_cpu
= entry
->device
;
507 m68k_tune
= m68k_tune_entry
->microarch
;
508 m68k_tune_flags
= m68k_tune_entry
->flags
;
510 #ifdef M68K_DEFAULT_TUNE
511 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
513 enum target_device dev
;
514 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
515 m68k_tune_flags
= all_devices
[dev
]->flags
;
520 m68k_tune
= entry
->microarch
;
521 m68k_tune_flags
= entry
->flags
;
524 /* Set the type of FPU. */
525 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
526 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
529 /* Sanity check to ensure that msep-data and mid-sahred-library are not
530 * both specified together. Doing so simply doesn't make sense.
532 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
533 error ("cannot specify both -msep-data and -mid-shared-library");
535 /* If we're generating code for a separate A5 relative data segment,
536 * we've got to enable -fPIC as well. This might be relaxable to
537 * -fpic but it hasn't been tested properly.
539 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
542 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
543 error if the target does not support them. */
544 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
545 error ("-mpcrel -fPIC is not currently supported on selected cpu");
547 /* ??? A historic way of turning on pic, or is this intended to
548 be an embedded thing that doesn't have the same name binding
549 significance that it does on hosted ELF systems? */
550 if (TARGET_PCREL
&& flag_pic
== 0)
555 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
557 m68k_symbolic_jump
= "jra %a0";
559 else if (TARGET_ID_SHARED_LIBRARY
)
560 /* All addresses must be loaded from the GOT. */
562 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
565 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
567 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
570 /* No unconditional long branch */;
571 else if (TARGET_PCREL
)
572 m68k_symbolic_jump
= "bra%.l %c0";
574 m68k_symbolic_jump
= "bra%.l %p0";
575 /* Turn off function cse if we are doing PIC. We always want
576 function call to be done as `bsr foo@PLTPC'. */
577 /* ??? It's traditional to do this for -mpcrel too, but it isn't
578 clear how intentional that is. */
579 flag_no_function_cse
= 1;
582 switch (m68k_symbolic_call_var
)
584 case M68K_SYMBOLIC_CALL_JSR
:
585 m68k_symbolic_call
= "jsr %a0";
588 case M68K_SYMBOLIC_CALL_BSR_C
:
589 m68k_symbolic_call
= "bsr%.l %c0";
592 case M68K_SYMBOLIC_CALL_BSR_P
:
593 m68k_symbolic_call
= "bsr%.l %p0";
596 case M68K_SYMBOLIC_CALL_NONE
:
597 gcc_assert (m68k_symbolic_call
== NULL
);
604 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
605 if (align_labels
> 2)
607 warning (0, "-falign-labels=%d is not supported", align_labels
);
612 warning (0, "-falign-loops=%d is not supported", align_loops
);
617 SUBTARGET_OVERRIDE_OPTIONS
;
619 /* Setup scheduling options. */
621 m68k_sched_cpu
= CPU_CFV1
;
623 m68k_sched_cpu
= CPU_CFV2
;
625 m68k_sched_cpu
= CPU_CFV3
;
627 m68k_sched_cpu
= CPU_CFV4
;
630 m68k_sched_cpu
= CPU_UNKNOWN
;
631 flag_schedule_insns
= 0;
632 flag_schedule_insns_after_reload
= 0;
633 flag_modulo_sched
= 0;
636 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
638 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
639 m68k_sched_mac
= MAC_CF_EMAC
;
640 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
641 m68k_sched_mac
= MAC_CF_MAC
;
643 m68k_sched_mac
= MAC_NO
;
647 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
650 m68k_override_options_after_change (void)
652 if (m68k_sched_cpu
== CPU_UNKNOWN
)
654 flag_schedule_insns
= 0;
655 flag_schedule_insns_after_reload
= 0;
656 flag_modulo_sched
= 0;
660 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
661 given argument and NAME is the argument passed to -mcpu. Return NULL
662 if -mcpu was not passed. */
665 m68k_cpp_cpu_ident (const char *prefix
)
669 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
672 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
673 given argument and NAME is the name of the representative device for
674 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
677 m68k_cpp_cpu_family (const char *prefix
)
681 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
684 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
685 "interrupt_handler" attribute and interrupt_thread if FUNC has an
686 "interrupt_thread" attribute. Otherwise, return
687 m68k_fk_normal_function. */
689 enum m68k_function_kind
690 m68k_get_function_kind (tree func
)
694 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
696 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
698 return m68k_fk_interrupt_handler
;
700 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
702 return m68k_fk_interrupt_handler
;
704 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
706 return m68k_fk_interrupt_thread
;
708 return m68k_fk_normal_function
;
711 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
712 struct attribute_spec.handler. */
714 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
715 tree args ATTRIBUTE_UNUSED
,
716 int flags ATTRIBUTE_UNUSED
,
719 if (TREE_CODE (*node
) != FUNCTION_DECL
)
721 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
723 *no_add_attrs
= true;
726 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
728 error ("multiple interrupt attributes not allowed");
729 *no_add_attrs
= true;
733 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
735 error ("interrupt_thread is available only on fido");
736 *no_add_attrs
= true;
743 m68k_compute_frame_layout (void)
747 enum m68k_function_kind func_kind
=
748 m68k_get_function_kind (current_function_decl
);
749 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
750 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
752 /* Only compute the frame once per function.
753 Don't cache information until reload has been completed. */
754 if (current_frame
.funcdef_no
== current_function_funcdef_no
758 current_frame
.size
= (get_frame_size () + 3) & -4;
762 /* Interrupt thread does not need to save any register. */
763 if (!interrupt_thread
)
764 for (regno
= 0; regno
< 16; regno
++)
765 if (m68k_save_reg (regno
, interrupt_handler
))
767 mask
|= 1 << (regno
- D0_REG
);
770 current_frame
.offset
= saved
* 4;
771 current_frame
.reg_no
= saved
;
772 current_frame
.reg_mask
= mask
;
774 current_frame
.foffset
= 0;
776 if (TARGET_HARD_FLOAT
)
778 /* Interrupt thread does not need to save any register. */
779 if (!interrupt_thread
)
780 for (regno
= 16; regno
< 24; regno
++)
781 if (m68k_save_reg (regno
, interrupt_handler
))
783 mask
|= 1 << (regno
- FP0_REG
);
786 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
787 current_frame
.offset
+= current_frame
.foffset
;
789 current_frame
.fpu_no
= saved
;
790 current_frame
.fpu_mask
= mask
;
792 /* Remember what function this frame refers to. */
793 current_frame
.funcdef_no
= current_function_funcdef_no
;
796 /* Worker function for TARGET_CAN_ELIMINATE. */
799 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
801 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
805 m68k_initial_elimination_offset (int from
, int to
)
808 /* The arg pointer points 8 bytes before the start of the arguments,
809 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
810 frame pointer in most frames. */
811 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
812 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
813 return argptr_offset
;
815 m68k_compute_frame_layout ();
817 gcc_assert (to
== STACK_POINTER_REGNUM
);
820 case ARG_POINTER_REGNUM
:
821 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
822 case FRAME_POINTER_REGNUM
:
823 return current_frame
.offset
+ current_frame
.size
;
829 /* Refer to the array `regs_ever_live' to determine which registers
830 to save; `regs_ever_live[I]' is nonzero if register number I
831 is ever used in the function. This function is responsible for
832 knowing which registers should not be saved even if used.
833 Return true if we need to save REGNO. */
836 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
838 if (flag_pic
&& regno
== PIC_REG
)
840 if (crtl
->saves_all_registers
)
842 if (crtl
->uses_pic_offset_table
)
844 /* Reload may introduce constant pool references into a function
845 that thitherto didn't need a PIC register. Note that the test
846 above will not catch that case because we will only set
847 crtl->uses_pic_offset_table when emitting
848 the address reloads. */
849 if (crtl
->uses_const_pool
)
853 if (crtl
->calls_eh_return
)
858 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
859 if (test
== INVALID_REGNUM
)
866 /* Fixed regs we never touch. */
867 if (fixed_regs
[regno
])
870 /* The frame pointer (if it is such) is handled specially. */
871 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
874 /* Interrupt handlers must also save call_used_regs
875 if they are live or when calling nested functions. */
876 if (interrupt_handler
)
878 if (df_regs_ever_live_p (regno
))
881 if (!current_function_is_leaf
&& call_used_regs
[regno
])
885 /* Never need to save registers that aren't touched. */
886 if (!df_regs_ever_live_p (regno
))
889 /* Otherwise save everything that isn't call-clobbered. */
890 return !call_used_regs
[regno
];
893 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
894 the lowest memory address. COUNT is the number of registers to be
895 moved, with register REGNO + I being moved if bit I of MASK is set.
896 STORE_P specifies the direction of the move and ADJUST_STACK_P says
897 whether or not this is pre-decrement (if STORE_P) or post-increment
898 (if !STORE_P) operation. */
901 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
902 unsigned int count
, unsigned int regno
,
903 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
906 rtx body
, addr
, src
, operands
[2];
907 enum machine_mode mode
;
909 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
910 mode
= reg_raw_mode
[regno
];
915 src
= plus_constant (base
, (count
916 * GET_MODE_SIZE (mode
)
917 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
918 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
921 for (; mask
!= 0; mask
>>= 1, regno
++)
924 addr
= plus_constant (base
, offset
);
925 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
926 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
927 XVECEXP (body
, 0, i
++)
928 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
929 offset
+= GET_MODE_SIZE (mode
);
931 gcc_assert (i
== XVECLEN (body
, 0));
933 return emit_insn (body
);
936 /* Make INSN a frame-related instruction. */
939 m68k_set_frame_related (rtx insn
)
944 RTX_FRAME_RELATED_P (insn
) = 1;
945 body
= PATTERN (insn
);
946 if (GET_CODE (body
) == PARALLEL
)
947 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
948 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
951 /* Emit RTL for the "prologue" define_expand. */
954 m68k_expand_prologue (void)
956 HOST_WIDE_INT fsize_with_regs
;
957 rtx limit
, src
, dest
;
959 m68k_compute_frame_layout ();
961 if (flag_stack_usage_info
)
962 current_function_static_stack_size
963 = current_frame
.size
+ current_frame
.offset
;
965 /* If the stack limit is a symbol, we can check it here,
966 before actually allocating the space. */
967 if (crtl
->limit_stack
968 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
970 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
971 if (!m68k_legitimate_constant_p (Pmode
, limit
))
973 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
974 limit
= gen_rtx_REG (Pmode
, D0_REG
);
976 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
977 stack_pointer_rtx
, limit
),
978 stack_pointer_rtx
, limit
,
982 fsize_with_regs
= current_frame
.size
;
985 /* ColdFire's move multiple instructions do not allow pre-decrement
986 addressing. Add the size of movem saves to the initial stack
987 allocation instead. */
988 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
989 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
990 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
991 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
994 if (frame_pointer_needed
)
996 if (fsize_with_regs
== 0 && TUNE_68040
)
998 /* On the 68040, two separate moves are faster than link.w 0. */
999 dest
= gen_frame_mem (Pmode
,
1000 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1001 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1002 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1003 stack_pointer_rtx
));
1005 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1006 m68k_set_frame_related
1007 (emit_insn (gen_link (frame_pointer_rtx
,
1008 GEN_INT (-4 - fsize_with_regs
))));
1011 m68k_set_frame_related
1012 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1013 m68k_set_frame_related
1014 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1016 GEN_INT (-fsize_with_regs
))));
1019 /* If the frame pointer is needed, emit a special barrier that
1020 will prevent the scheduler from moving stores to the frame
1021 before the stack adjustment. */
1022 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1024 else if (fsize_with_regs
!= 0)
1025 m68k_set_frame_related
1026 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1028 GEN_INT (-fsize_with_regs
))));
1030 if (current_frame
.fpu_mask
)
1032 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1034 m68k_set_frame_related
1035 (m68k_emit_movem (stack_pointer_rtx
,
1036 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1037 current_frame
.fpu_no
, FP0_REG
,
1038 current_frame
.fpu_mask
, true, true));
1043 /* If we're using moveml to save the integer registers,
1044 the stack pointer will point to the bottom of the moveml
1045 save area. Find the stack offset of the first FP register. */
1046 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1049 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1050 m68k_set_frame_related
1051 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1052 current_frame
.fpu_no
, FP0_REG
,
1053 current_frame
.fpu_mask
, true, false));
1057 /* If the stack limit is not a symbol, check it here.
1058 This has the disadvantage that it may be too late... */
1059 if (crtl
->limit_stack
)
1061 if (REG_P (stack_limit_rtx
))
1062 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1064 stack_pointer_rtx
, stack_limit_rtx
,
1067 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1068 warning (0, "stack limit expression is not supported");
1071 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1073 /* Store each register separately in the same order moveml does. */
1076 for (i
= 16; i
-- > 0; )
1077 if (current_frame
.reg_mask
& (1 << i
))
1079 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1080 dest
= gen_frame_mem (SImode
,
1081 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1082 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1087 if (TARGET_COLDFIRE
)
1088 /* The required register save space has already been allocated.
1089 The first register should be stored at (%sp). */
1090 m68k_set_frame_related
1091 (m68k_emit_movem (stack_pointer_rtx
, 0,
1092 current_frame
.reg_no
, D0_REG
,
1093 current_frame
.reg_mask
, true, false));
1095 m68k_set_frame_related
1096 (m68k_emit_movem (stack_pointer_rtx
,
1097 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1098 current_frame
.reg_no
, D0_REG
,
1099 current_frame
.reg_mask
, true, true));
1102 if (!TARGET_SEP_DATA
1103 && crtl
->uses_pic_offset_table
)
1104 emit_insn (gen_load_got (pic_offset_table_rtx
));
1107 /* Return true if a simple (return) instruction is sufficient for this
1108 instruction (i.e. if no epilogue is needed). */
1111 m68k_use_return_insn (void)
1113 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1116 m68k_compute_frame_layout ();
1117 return current_frame
.offset
== 0;
1120 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1121 SIBCALL_P says which.
1123 The function epilogue should not depend on the current stack pointer!
1124 It should use the frame pointer only, if there is a frame pointer.
1125 This is mandatory because of alloca; we also take advantage of it to
1126 omit stack adjustments before returning. */
1129 m68k_expand_epilogue (bool sibcall_p
)
1131 HOST_WIDE_INT fsize
, fsize_with_regs
;
1132 bool big
, restore_from_sp
;
1134 m68k_compute_frame_layout ();
1136 fsize
= current_frame
.size
;
1138 restore_from_sp
= false;
1140 /* FIXME : current_function_is_leaf below is too strong.
1141 What we really need to know there is if there could be pending
1142 stack adjustment needed at that point. */
1143 restore_from_sp
= (!frame_pointer_needed
1144 || (!cfun
->calls_alloca
1145 && current_function_is_leaf
));
1147 /* fsize_with_regs is the size we need to adjust the sp when
1148 popping the frame. */
1149 fsize_with_regs
= fsize
;
1150 if (TARGET_COLDFIRE
&& restore_from_sp
)
1152 /* ColdFire's move multiple instructions do not allow post-increment
1153 addressing. Add the size of movem loads to the final deallocation
1155 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1156 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1157 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1158 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1161 if (current_frame
.offset
+ fsize
>= 0x8000
1163 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1166 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1167 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1169 /* ColdFire's move multiple instructions do not support the
1170 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1171 stack-based restore. */
1172 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1173 GEN_INT (-(current_frame
.offset
+ fsize
)));
1174 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1175 gen_rtx_REG (Pmode
, A1_REG
),
1176 frame_pointer_rtx
));
1177 restore_from_sp
= true;
1181 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1187 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1189 /* Restore each register separately in the same order moveml does. */
1191 HOST_WIDE_INT offset
;
1193 offset
= current_frame
.offset
+ fsize
;
1194 for (i
= 0; i
< 16; i
++)
1195 if (current_frame
.reg_mask
& (1 << i
))
1201 /* Generate the address -OFFSET(%fp,%a1.l). */
1202 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1203 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1204 addr
= plus_constant (addr
, -offset
);
1206 else if (restore_from_sp
)
1207 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1209 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1210 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1211 gen_frame_mem (SImode
, addr
));
1212 offset
-= GET_MODE_SIZE (SImode
);
1215 else if (current_frame
.reg_mask
)
1218 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1219 gen_rtx_REG (Pmode
, A1_REG
),
1221 -(current_frame
.offset
+ fsize
),
1222 current_frame
.reg_no
, D0_REG
,
1223 current_frame
.reg_mask
, false, false);
1224 else if (restore_from_sp
)
1225 m68k_emit_movem (stack_pointer_rtx
, 0,
1226 current_frame
.reg_no
, D0_REG
,
1227 current_frame
.reg_mask
, false,
1230 m68k_emit_movem (frame_pointer_rtx
,
1231 -(current_frame
.offset
+ fsize
),
1232 current_frame
.reg_no
, D0_REG
,
1233 current_frame
.reg_mask
, false, false);
1236 if (current_frame
.fpu_no
> 0)
1239 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1240 gen_rtx_REG (Pmode
, A1_REG
),
1242 -(current_frame
.foffset
+ fsize
),
1243 current_frame
.fpu_no
, FP0_REG
,
1244 current_frame
.fpu_mask
, false, false);
1245 else if (restore_from_sp
)
1247 if (TARGET_COLDFIRE
)
1251 /* If we used moveml to restore the integer registers, the
1252 stack pointer will still point to the bottom of the moveml
1253 save area. Find the stack offset of the first FP
1255 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1258 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1259 m68k_emit_movem (stack_pointer_rtx
, offset
,
1260 current_frame
.fpu_no
, FP0_REG
,
1261 current_frame
.fpu_mask
, false, false);
1264 m68k_emit_movem (stack_pointer_rtx
, 0,
1265 current_frame
.fpu_no
, FP0_REG
,
1266 current_frame
.fpu_mask
, false, true);
1269 m68k_emit_movem (frame_pointer_rtx
,
1270 -(current_frame
.foffset
+ fsize
),
1271 current_frame
.fpu_no
, FP0_REG
,
1272 current_frame
.fpu_mask
, false, false);
1275 if (frame_pointer_needed
)
1276 emit_insn (gen_unlink (frame_pointer_rtx
));
1277 else if (fsize_with_regs
)
1278 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1280 GEN_INT (fsize_with_regs
)));
1282 if (crtl
->calls_eh_return
)
1283 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1285 EH_RETURN_STACKADJ_RTX
));
1288 emit_jump_insn (ret_rtx
);
1291 /* Return true if X is a valid comparison operator for the dbcc
1294 Note it rejects floating point comparison operators.
1295 (In the future we could use Fdbcc).
1297 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1300 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1302 switch (GET_CODE (x
))
1304 case EQ
: case NE
: case GTU
: case LTU
:
1308 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1310 case GT
: case LT
: case GE
: case LE
:
1311 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1317 /* Return nonzero if flags are currently in the 68881 flag register. */
1319 flags_in_68881 (void)
1321 /* We could add support for these in the future */
1322 return cc_status
.flags
& CC_IN_68881
;
1325 /* Return true if PARALLEL contains register REGNO. */
1327 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1331 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1334 if (GET_CODE (parallel
) != PARALLEL
)
1337 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1341 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1342 if (REG_P (x
) && REGNO (x
) == regno
)
1349 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1352 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1354 enum m68k_function_kind kind
;
1356 /* We cannot use sibcalls for nested functions because we use the
1357 static chain register for indirect calls. */
1358 if (CALL_EXPR_STATIC_CHAIN (exp
))
1361 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1363 /* Check that the return value locations are the same. For
1364 example that we aren't returning a value from the sibling in
1365 a D0 register but then need to transfer it to a A0 register. */
1369 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1371 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1373 /* Check that the values are equal or that the result the callee
1374 function returns is superset of what the current function returns. */
1375 if (!(rtx_equal_p (cfun_value
, call_value
)
1376 || (REG_P (cfun_value
)
1377 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1381 kind
= m68k_get_function_kind (current_function_decl
);
1382 if (kind
== m68k_fk_normal_function
)
1383 /* We can always sibcall from a normal function, because it's
1384 undefined if it is calling an interrupt function. */
1387 /* Otherwise we can only sibcall if the function kind is known to be
1389 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1395 /* On the m68k all args are always pushed. */
1398 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1399 enum machine_mode mode ATTRIBUTE_UNUSED
,
1400 const_tree type ATTRIBUTE_UNUSED
,
1401 bool named ATTRIBUTE_UNUSED
)
1407 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1408 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1410 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1412 *cum
+= (mode
!= BLKmode
1413 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1414 : (int_size_in_bytes (type
) + 3) & ~3);
1417 /* Convert X to a legitimate function call memory reference and return the
1421 m68k_legitimize_call_address (rtx x
)
1423 gcc_assert (MEM_P (x
));
1424 if (call_operand (XEXP (x
, 0), VOIDmode
))
1426 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1429 /* Likewise for sibling calls. */
1432 m68k_legitimize_sibcall_address (rtx x
)
1434 gcc_assert (MEM_P (x
));
1435 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1438 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1439 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1442 /* Convert X to a legitimate address and return it if successful. Otherwise
1445 For the 68000, we handle X+REG by loading X into a register R and
1446 using R+REG. R will go in an address reg and indexing will be used.
1447 However, if REG is a broken-out memory address or multiplication,
1448 nothing needs to be done because REG can certainly go in an address reg. */
1451 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1453 if (m68k_tls_symbol_p (x
))
1454 return m68k_legitimize_tls_address (x
);
1456 if (GET_CODE (x
) == PLUS
)
1458 int ch
= (x
) != (oldx
);
1461 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1463 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1466 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1468 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1471 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1475 if (GET_CODE (XEXP (x
, 1)) == REG
1476 && GET_CODE (XEXP (x
, 0)) == REG
)
1478 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1481 x
= force_operand (x
, 0);
1485 if (memory_address_p (mode
, x
))
1488 if (GET_CODE (XEXP (x
, 0)) == REG
1489 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1490 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1491 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1493 rtx temp
= gen_reg_rtx (Pmode
);
1494 rtx val
= force_operand (XEXP (x
, 1), 0);
1495 emit_move_insn (temp
, val
);
1498 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1499 && GET_CODE (XEXP (x
, 0)) == REG
)
1500 x
= force_operand (x
, 0);
1502 else if (GET_CODE (XEXP (x
, 1)) == REG
1503 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1504 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1505 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1507 rtx temp
= gen_reg_rtx (Pmode
);
1508 rtx val
= force_operand (XEXP (x
, 0), 0);
1509 emit_move_insn (temp
, val
);
1512 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1513 && GET_CODE (XEXP (x
, 1)) == REG
)
1514 x
= force_operand (x
, 0);
1522 /* Output a dbCC; jCC sequence. Note we do not handle the
1523 floating point version of this sequence (Fdbcc). We also
1524 do not handle alternative conditions when CC_NO_OVERFLOW is
1525 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1526 kick those out before we get here. */
1529 output_dbcc_and_branch (rtx
*operands
)
1531 switch (GET_CODE (operands
[3]))
1534 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1538 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1542 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1546 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1550 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1554 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1558 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1562 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1566 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1570 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1577 /* If the decrement is to be done in SImode, then we have
1578 to compensate for the fact that dbcc decrements in HImode. */
1579 switch (GET_MODE (operands
[0]))
1582 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1594 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1597 enum rtx_code op_code
= GET_CODE (op
);
1599 /* This does not produce a useful cc. */
1602 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1603 below. Swap the operands and change the op if these requirements
1604 are not fulfilled. */
1605 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1609 operand1
= operand2
;
1611 op_code
= swap_condition (op_code
);
1613 loperands
[0] = operand1
;
1614 if (GET_CODE (operand1
) == REG
)
1615 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1617 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1618 if (operand2
!= const0_rtx
)
1620 loperands
[2] = operand2
;
1621 if (GET_CODE (operand2
) == REG
)
1622 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1624 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1626 loperands
[4] = gen_label_rtx ();
1627 if (operand2
!= const0_rtx
)
1628 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1631 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1632 output_asm_insn ("tst%.l %0", loperands
);
1634 output_asm_insn ("cmp%.w #0,%0", loperands
);
1636 output_asm_insn ("jne %l4", loperands
);
1638 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1639 output_asm_insn ("tst%.l %1", loperands
);
1641 output_asm_insn ("cmp%.w #0,%1", loperands
);
1644 loperands
[5] = dest
;
1649 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1650 CODE_LABEL_NUMBER (loperands
[4]));
1651 output_asm_insn ("seq %5", loperands
);
1655 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1656 CODE_LABEL_NUMBER (loperands
[4]));
1657 output_asm_insn ("sne %5", loperands
);
1661 loperands
[6] = gen_label_rtx ();
1662 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1663 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1664 CODE_LABEL_NUMBER (loperands
[4]));
1665 output_asm_insn ("sgt %5", loperands
);
1666 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1667 CODE_LABEL_NUMBER (loperands
[6]));
1671 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1672 CODE_LABEL_NUMBER (loperands
[4]));
1673 output_asm_insn ("shi %5", loperands
);
1677 loperands
[6] = gen_label_rtx ();
1678 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1679 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1680 CODE_LABEL_NUMBER (loperands
[4]));
1681 output_asm_insn ("slt %5", loperands
);
1682 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1683 CODE_LABEL_NUMBER (loperands
[6]));
1687 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1688 CODE_LABEL_NUMBER (loperands
[4]));
1689 output_asm_insn ("scs %5", loperands
);
1693 loperands
[6] = gen_label_rtx ();
1694 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1695 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1696 CODE_LABEL_NUMBER (loperands
[4]));
1697 output_asm_insn ("sge %5", loperands
);
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[6]));
1703 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1704 CODE_LABEL_NUMBER (loperands
[4]));
1705 output_asm_insn ("scc %5", loperands
);
1709 loperands
[6] = gen_label_rtx ();
1710 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1711 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1712 CODE_LABEL_NUMBER (loperands
[4]));
1713 output_asm_insn ("sle %5", loperands
);
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[6]));
1719 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1720 CODE_LABEL_NUMBER (loperands
[4]));
1721 output_asm_insn ("sls %5", loperands
);
1731 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1733 operands
[0] = countop
;
1734 operands
[1] = dataop
;
1736 if (GET_CODE (countop
) == CONST_INT
)
1738 register int count
= INTVAL (countop
);
1739 /* If COUNT is bigger than size of storage unit in use,
1740 advance to the containing unit of same size. */
1741 if (count
> signpos
)
1743 int offset
= (count
& ~signpos
) / 8;
1744 count
= count
& signpos
;
1745 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1747 if (count
== signpos
)
1748 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1750 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1752 /* These three statements used to use next_insns_test_no...
1753 but it appears that this should do the same job. */
1755 && next_insn_tests_no_inequality (insn
))
1758 && next_insn_tests_no_inequality (insn
))
1761 && next_insn_tests_no_inequality (insn
))
1763 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1764 On some m68k variants unfortunately that's slower than btst.
1765 On 68000 and higher, that should also work for all HImode operands. */
1766 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1768 if (count
== 3 && DATA_REG_P (operands
[1])
1769 && next_insn_tests_no_inequality (insn
))
1771 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1772 return "move%.w %1,%%ccr";
1774 if (count
== 2 && DATA_REG_P (operands
[1])
1775 && next_insn_tests_no_inequality (insn
))
1777 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1778 return "move%.w %1,%%ccr";
1780 /* count == 1 followed by bvc/bvs and
1781 count == 0 followed by bcc/bcs are also possible, but need
1782 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1785 cc_status
.flags
= CC_NOT_NEGATIVE
;
1787 return "btst %0,%1";
1790 /* Return true if X is a legitimate base register. STRICT_P says
1791 whether we need strict checking. */
1794 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1796 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1797 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1802 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1803 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1806 /* Return true if X is a legitimate index register. STRICT_P says
1807 whether we need strict checking. */
1810 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1812 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1817 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1818 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1821 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1822 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1823 ADDRESS if so. STRICT_P says whether we need strict checking. */
1826 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1830 /* Check for a scale factor. */
1832 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1833 && GET_CODE (x
) == MULT
1834 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1835 && (INTVAL (XEXP (x
, 1)) == 2
1836 || INTVAL (XEXP (x
, 1)) == 4
1837 || (INTVAL (XEXP (x
, 1)) == 8
1838 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1840 scale
= INTVAL (XEXP (x
, 1));
1844 /* Check for a word extension. */
1845 if (!TARGET_COLDFIRE
1846 && GET_CODE (x
) == SIGN_EXTEND
1847 && GET_MODE (XEXP (x
, 0)) == HImode
)
1850 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1852 address
->scale
= scale
;
1860 /* Return true if X is an illegitimate symbolic constant. */
1863 m68k_illegitimate_symbolic_constant_p (rtx x
)
1867 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1869 split_const (x
, &base
, &offset
);
1870 if (GET_CODE (base
) == SYMBOL_REF
1871 && !offset_within_block_p (base
, INTVAL (offset
)))
1874 return m68k_tls_reference_p (x
, false);
1877 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1880 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1882 return m68k_illegitimate_symbolic_constant_p (x
);
1885 /* Return true if X is a legitimate constant address that can reach
1886 bytes in the range [X, X + REACH). STRICT_P says whether we need
1890 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1894 if (!CONSTANT_ADDRESS_P (x
))
1898 && !(strict_p
&& TARGET_PCREL
)
1899 && symbolic_operand (x
, VOIDmode
))
1902 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1904 split_const (x
, &base
, &offset
);
1905 if (GET_CODE (base
) == SYMBOL_REF
1906 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1910 return !m68k_tls_reference_p (x
, false);
1913 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1914 labels will become jump tables. */
1917 m68k_jump_table_ref_p (rtx x
)
1919 if (GET_CODE (x
) != LABEL_REF
)
1923 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1926 x
= next_nonnote_insn (x
);
1927 return x
&& JUMP_TABLE_DATA_P (x
);
1930 /* Return true if X is a legitimate address for values of mode MODE.
1931 STRICT_P says whether strict checking is needed. If the address
1932 is valid, describe its components in *ADDRESS. */
1935 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1936 bool strict_p
, struct m68k_address
*address
)
1940 memset (address
, 0, sizeof (*address
));
1942 if (mode
== BLKmode
)
1945 reach
= GET_MODE_SIZE (mode
);
1947 /* Check for (An) (mode 2). */
1948 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1954 /* Check for -(An) and (An)+ (modes 3 and 4). */
1955 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1956 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1958 address
->code
= GET_CODE (x
);
1959 address
->base
= XEXP (x
, 0);
1963 /* Check for (d16,An) (mode 5). */
1964 if (GET_CODE (x
) == PLUS
1965 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1966 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1967 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1969 address
->base
= XEXP (x
, 0);
1970 address
->offset
= XEXP (x
, 1);
1974 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1975 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1977 if (GET_CODE (x
) == PLUS
1978 && XEXP (x
, 0) == pic_offset_table_rtx
)
1980 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1981 they are invalid in this context. */
1982 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1984 address
->base
= XEXP (x
, 0);
1985 address
->offset
= XEXP (x
, 1);
1990 /* The ColdFire FPU only accepts addressing modes 2-5. */
1991 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1994 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1995 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1996 All these modes are variations of mode 7. */
1997 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1999 address
->offset
= x
;
2003 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2006 ??? do_tablejump creates these addresses before placing the target
2007 label, so we have to assume that unplaced labels are jump table
2008 references. It seems unlikely that we would ever generate indexed
2009 accesses to unplaced labels in other cases. */
2010 if (GET_CODE (x
) == PLUS
2011 && m68k_jump_table_ref_p (XEXP (x
, 1))
2012 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2014 address
->offset
= XEXP (x
, 1);
2018 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2019 (bd,An,Xn.SIZE*SCALE) addresses. */
2023 /* Check for a nonzero base displacement. */
2024 if (GET_CODE (x
) == PLUS
2025 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2027 address
->offset
= XEXP (x
, 1);
2031 /* Check for a suppressed index register. */
2032 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2038 /* Check for a suppressed base register. Do not allow this case
2039 for non-symbolic offsets as it effectively gives gcc freedom
2040 to treat data registers as base registers, which can generate
2043 && symbolic_operand (address
->offset
, VOIDmode
)
2044 && m68k_decompose_index (x
, strict_p
, address
))
2049 /* Check for a nonzero base displacement. */
2050 if (GET_CODE (x
) == PLUS
2051 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2052 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2054 address
->offset
= XEXP (x
, 1);
2059 /* We now expect the sum of a base and an index. */
2060 if (GET_CODE (x
) == PLUS
)
2062 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2063 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2065 address
->base
= XEXP (x
, 0);
2069 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2070 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2072 address
->base
= XEXP (x
, 1);
2079 /* Return true if X is a legitimate address for values of mode MODE.
2080 STRICT_P says whether strict checking is needed. */
2083 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2085 struct m68k_address address
;
2087 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2090 /* Return true if X is a memory, describing its address in ADDRESS if so.
2091 Apply strict checking if called during or after reload. */
2094 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2097 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2098 reload_in_progress
|| reload_completed
,
2102 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2105 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2107 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2110 /* Return true if X matches the 'Q' constraint. It must be a memory
2111 with a base address and no constant offset or index. */
2114 m68k_matches_q_p (rtx x
)
2116 struct m68k_address address
;
2118 return (m68k_legitimate_mem_p (x
, &address
)
2119 && address
.code
== UNKNOWN
2125 /* Return true if X matches the 'U' constraint. It must be a base address
2126 with a constant offset and no index. */
2129 m68k_matches_u_p (rtx x
)
2131 struct m68k_address address
;
2133 return (m68k_legitimate_mem_p (x
, &address
)
2134 && address
.code
== UNKNOWN
2140 /* Return GOT pointer. */
2145 if (pic_offset_table_rtx
== NULL_RTX
)
2146 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2148 crtl
->uses_pic_offset_table
= 1;
2150 return pic_offset_table_rtx
;
2153 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2155 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2156 RELOC_TLSIE
, RELOC_TLSLE
};
2158 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2160 /* Wrap symbol X into unspec representing relocation RELOC.
2161 BASE_REG - register that should be added to the result.
2162 TEMP_REG - if non-null, temporary register. */
2165 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2169 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2171 if (TARGET_COLDFIRE
&& use_x_p
)
2172 /* When compiling with -mx{got, tls} switch the code will look like this:
2174 move.l <X>@<RELOC>,<TEMP_REG>
2175 add.l <BASE_REG>,<TEMP_REG> */
2177 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2178 to put @RELOC after reference. */
2179 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2181 x
= gen_rtx_CONST (Pmode
, x
);
2183 if (temp_reg
== NULL
)
2185 gcc_assert (can_create_pseudo_p ());
2186 temp_reg
= gen_reg_rtx (Pmode
);
2189 emit_move_insn (temp_reg
, x
);
2190 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2195 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2197 x
= gen_rtx_CONST (Pmode
, x
);
2199 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2205 /* Helper for m68k_unwrap_symbol.
2206 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2207 sets *RELOC_PTR to relocation type for the symbol. */
2210 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2211 enum m68k_reloc
*reloc_ptr
)
2213 if (GET_CODE (orig
) == CONST
)
2216 enum m68k_reloc dummy
;
2220 if (reloc_ptr
== NULL
)
2223 /* Handle an addend. */
2224 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2225 && CONST_INT_P (XEXP (x
, 1)))
2228 if (GET_CODE (x
) == UNSPEC
)
2230 switch (XINT (x
, 1))
2232 case UNSPEC_RELOC16
:
2233 orig
= XVECEXP (x
, 0, 0);
2234 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2237 case UNSPEC_RELOC32
:
2238 if (unwrap_reloc32_p
)
2240 orig
= XVECEXP (x
, 0, 0);
2241 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2254 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2255 UNSPEC_RELOC32 wrappers. */
2258 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2260 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2263 /* Helper for m68k_final_prescan_insn. */
2266 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2270 if (m68k_unwrap_symbol (x
, true) != x
)
2271 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2275 gcc_assert (GET_CODE (x
) == CONST
);
2278 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2283 unspec
= XEXP (plus
, 0);
2284 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2285 addend
= XEXP (plus
, 1);
2286 gcc_assert (CONST_INT_P (addend
));
2288 /* We now have all the pieces, rearrange them. */
2290 /* Move symbol to plus. */
2291 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2293 /* Move plus inside unspec. */
2294 XVECEXP (unspec
, 0, 0) = plus
;
2296 /* Move unspec to top level of const. */
2297 XEXP (x
, 0) = unspec
;
2306 /* Prescan insn before outputing assembler for it. */
2309 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2310 rtx
*operands
, int n_operands
)
2314 /* Combine and, possibly, other optimizations may do good job
2316 (const (unspec [(symbol)]))
2318 (const (plus (unspec [(symbol)])
2320 The problem with this is emitting @TLS or @GOT decorations.
2321 The decoration is emitted when processing (unspec), so the
2322 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2324 It seems that the easiest solution to this is to convert such
2326 (const (unspec [(plus (symbol)
2328 Note, that the top level of operand remains intact, so we don't have
2329 to patch up anything outside of the operand. */
2331 for (i
= 0; i
< n_operands
; ++i
)
2337 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2341 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2342 If REG is non-null, use it; generate new pseudo otherwise. */
2345 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2349 if (reg
== NULL_RTX
)
2351 gcc_assert (can_create_pseudo_p ());
2352 reg
= gen_reg_rtx (Pmode
);
2355 insn
= emit_move_insn (reg
, x
);
2356 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2358 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2363 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2367 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2369 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2371 x
= gen_rtx_MEM (Pmode
, x
);
2372 MEM_READONLY_P (x
) = 1;
2377 /* Legitimize PIC addresses. If the address is already
2378 position-independent, we return ORIG. Newly generated
2379 position-independent addresses go to REG. If we need more
2380 than one register, we lose.
2382 An address is legitimized by making an indirect reference
2383 through the Global Offset Table with the name of the symbol
2386 The assembler and linker are responsible for placing the
2387 address of the symbol in the GOT. The function prologue
2388 is responsible for initializing a5 to the starting address
2391 The assembler is also responsible for translating a symbol name
2392 into a constant displacement from the start of the GOT.
2394 A quick example may make things a little clearer:
2396 When not generating PIC code to store the value 12345 into _foo
2397 we would generate the following code:
2401 When generating PIC two transformations are made. First, the compiler
2402 loads the address of foo into a register. So the first transformation makes:
2407 The code in movsi will intercept the lea instruction and call this
2408 routine which will transform the instructions into:
2410 movel a5@(_foo:w), a0
2414 That (in a nutshell) is how *all* symbol and label references are
2418 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2423 /* First handle a simple SYMBOL_REF or LABEL_REF */
2424 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2428 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2429 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2431 else if (GET_CODE (orig
) == CONST
)
2435 /* Make sure this has not already been legitimized. */
2436 if (m68k_unwrap_symbol (orig
, true) != orig
)
2441 /* legitimize both operands of the PLUS */
2442 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2444 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2445 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2446 base
== reg
? 0 : reg
);
2448 if (GET_CODE (orig
) == CONST_INT
)
2449 pic_ref
= plus_constant (base
, INTVAL (orig
));
2451 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2457 /* The __tls_get_addr symbol. */
2458 static GTY(()) rtx m68k_tls_get_addr
;
2460 /* Return SYMBOL_REF for __tls_get_addr. */
2463 m68k_get_tls_get_addr (void)
2465 if (m68k_tls_get_addr
== NULL_RTX
)
2466 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2468 return m68k_tls_get_addr
;
2471 /* Return libcall result in A0 instead of usual D0. */
2472 static bool m68k_libcall_value_in_a0_p
= false;
2474 /* Emit instruction sequence that calls __tls_get_addr. X is
2475 the TLS symbol we are referencing and RELOC is the symbol type to use
2476 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2477 emitted. A pseudo register with result of __tls_get_addr call is
2481 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2487 /* Emit the call sequence. */
2490 /* FIXME: Unfortunately, emit_library_call_value does not
2491 consider (plus (%a5) (const (unspec))) to be a good enough
2492 operand for push, so it forces it into a register. The bad
2493 thing about this is that combiner, due to copy propagation and other
2494 optimizations, sometimes can not later fix this. As a consequence,
2495 additional register may be allocated resulting in a spill.
2496 For reference, see args processing loops in
2497 calls.c:emit_library_call_value_1.
2498 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2499 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2501 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2502 is the simpliest way of generating a call. The difference between
2503 __tls_get_addr() and libcall is that the result is returned in D0
2504 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2505 which temporarily switches returning the result to A0. */
2507 m68k_libcall_value_in_a0_p
= true;
2508 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2509 Pmode
, 1, x
, Pmode
);
2510 m68k_libcall_value_in_a0_p
= false;
2512 insns
= get_insns ();
2515 gcc_assert (can_create_pseudo_p ());
2516 dest
= gen_reg_rtx (Pmode
);
2517 emit_libcall_block (insns
, dest
, a0
, eqv
);
2522 /* The __tls_get_addr symbol. */
2523 static GTY(()) rtx m68k_read_tp
;
2525 /* Return SYMBOL_REF for __m68k_read_tp. */
2528 m68k_get_m68k_read_tp (void)
2530 if (m68k_read_tp
== NULL_RTX
)
2531 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2533 return m68k_read_tp
;
2536 /* Emit instruction sequence that calls __m68k_read_tp.
2537 A pseudo register with result of __m68k_read_tp call is returned. */
2540 m68k_call_m68k_read_tp (void)
2549 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2550 is the simpliest way of generating a call. The difference between
2551 __m68k_read_tp() and libcall is that the result is returned in D0
2552 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2553 which temporarily switches returning the result to A0. */
2555 /* Emit the call sequence. */
2556 m68k_libcall_value_in_a0_p
= true;
2557 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2559 m68k_libcall_value_in_a0_p
= false;
2560 insns
= get_insns ();
2563 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2564 share the m68k_read_tp result with other IE/LE model accesses. */
2565 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2567 gcc_assert (can_create_pseudo_p ());
2568 dest
= gen_reg_rtx (Pmode
);
2569 emit_libcall_block (insns
, dest
, a0
, eqv
);
2574 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2575 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2579 m68k_legitimize_tls_address (rtx orig
)
2581 switch (SYMBOL_REF_TLS_MODEL (orig
))
2583 case TLS_MODEL_GLOBAL_DYNAMIC
:
2584 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2587 case TLS_MODEL_LOCAL_DYNAMIC
:
2593 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2594 share the LDM result with other LD model accesses. */
2595 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2598 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2600 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2602 if (can_create_pseudo_p ())
2603 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2609 case TLS_MODEL_INITIAL_EXEC
:
2614 a0
= m68k_call_m68k_read_tp ();
2616 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2617 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2619 if (can_create_pseudo_p ())
2620 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2626 case TLS_MODEL_LOCAL_EXEC
:
2631 a0
= m68k_call_m68k_read_tp ();
2633 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2635 if (can_create_pseudo_p ())
2636 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2649 /* Return true if X is a TLS symbol. */
2652 m68k_tls_symbol_p (rtx x
)
2654 if (!TARGET_HAVE_TLS
)
2657 if (GET_CODE (x
) != SYMBOL_REF
)
2660 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2663 /* Helper for m68k_tls_referenced_p. */
2666 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2668 /* Note: this is not the same as m68k_tls_symbol_p. */
2669 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2670 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2672 /* Don't recurse into legitimate TLS references. */
2673 if (m68k_tls_reference_p (*x_ptr
, true))
2679 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2680 though illegitimate one.
2681 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2684 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2686 if (!TARGET_HAVE_TLS
)
2690 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2693 enum m68k_reloc reloc
= RELOC_GOT
;
2695 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2696 && TLS_RELOC_P (reloc
));
2702 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2704 /* Return the type of move that should be used for integer I. */
2707 m68k_const_method (HOST_WIDE_INT i
)
2714 /* The ColdFire doesn't have byte or word operations. */
2715 /* FIXME: This may not be useful for the m68060 either. */
2716 if (!TARGET_COLDFIRE
)
2718 /* if -256 < N < 256 but N is not in range for a moveq
2719 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2720 if (USE_MOVQ (i
^ 0xff))
2722 /* Likewise, try with not.w */
2723 if (USE_MOVQ (i
^ 0xffff))
2725 /* This is the only value where neg.w is useful */
2730 /* Try also with swap. */
2732 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2737 /* Try using MVZ/MVS with an immediate value to load constants. */
2738 if (i
>= 0 && i
<= 65535)
2740 if (i
>= -32768 && i
<= 32767)
2744 /* Otherwise, use move.l */
2748 /* Return the cost of moving constant I into a data register. */
2751 const_int_cost (HOST_WIDE_INT i
)
2753 switch (m68k_const_method (i
))
2756 /* Constants between -128 and 127 are cheap due to moveq. */
2764 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2774 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2775 int *total
, bool speed ATTRIBUTE_UNUSED
)
2780 /* Constant zero is super cheap due to clr instruction. */
2781 if (x
== const0_rtx
)
2784 *total
= const_int_cost (INTVAL (x
));
2794 /* Make 0.0 cheaper than other floating constants to
2795 encourage creating tstsf and tstdf insns. */
2796 if (outer_code
== COMPARE
2797 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2803 /* These are vaguely right for a 68020. */
2804 /* The costs for long multiply have been adjusted to work properly
2805 in synth_mult on the 68020, relative to an average of the time
2806 for add and the time for shift, taking away a little more because
2807 sometimes move insns are needed. */
2808 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2813 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2814 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2816 : TARGET_COLDFIRE ? 3 : 13)
2821 : TUNE_68000_10 ? 5 \
2822 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2823 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2825 : TARGET_COLDFIRE ? 2 : 8)
2828 (TARGET_CF_HWDIV ? 11 \
2829 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2832 /* An lea costs about three times as much as a simple add. */
2833 if (GET_MODE (x
) == SImode
2834 && GET_CODE (XEXP (x
, 1)) == REG
2835 && GET_CODE (XEXP (x
, 0)) == MULT
2836 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2837 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2838 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2839 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2840 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2842 /* lea an@(dx:l:i),am */
2843 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2853 *total
= COSTS_N_INSNS(1);
2858 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2860 if (INTVAL (XEXP (x
, 1)) < 16)
2861 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2863 /* We're using clrw + swap for these cases. */
2864 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2867 *total
= COSTS_N_INSNS (10); /* Worst case. */
2870 /* A shift by a big integer takes an extra instruction. */
2871 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2872 && (INTVAL (XEXP (x
, 1)) == 16))
2874 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2877 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2878 && !(INTVAL (XEXP (x
, 1)) > 0
2879 && INTVAL (XEXP (x
, 1)) <= 8))
2881 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2887 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2888 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2889 && GET_MODE (x
) == SImode
)
2890 *total
= COSTS_N_INSNS (MULW_COST
);
2891 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2892 *total
= COSTS_N_INSNS (MULW_COST
);
2894 *total
= COSTS_N_INSNS (MULL_COST
);
2901 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2902 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2903 else if (TARGET_CF_HWDIV
)
2904 *total
= COSTS_N_INSNS (18);
2906 *total
= COSTS_N_INSNS (43); /* div.l */
2910 if (outer_code
== COMPARE
)
2919 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2923 output_move_const_into_data_reg (rtx
*operands
)
2927 i
= INTVAL (operands
[1]);
2928 switch (m68k_const_method (i
))
2931 return "mvzw %1,%0";
2933 return "mvsw %1,%0";
2935 return "moveq %1,%0";
2938 operands
[1] = GEN_INT (i
^ 0xff);
2939 return "moveq %1,%0\n\tnot%.b %0";
2942 operands
[1] = GEN_INT (i
^ 0xffff);
2943 return "moveq %1,%0\n\tnot%.w %0";
2946 return "moveq #-128,%0\n\tneg%.w %0";
2951 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2952 return "moveq %1,%0\n\tswap %0";
2955 return "move%.l %1,%0";
2961 /* Return true if I can be handled by ISA B's mov3q instruction. */
2964 valid_mov3q_const (HOST_WIDE_INT i
)
2966 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2969 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2970 I is the value of OPERANDS[1]. */
2973 output_move_simode_const (rtx
*operands
)
2979 src
= INTVAL (operands
[1]);
2981 && (DATA_REG_P (dest
) || MEM_P (dest
))
2982 /* clr insns on 68000 read before writing. */
2983 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2984 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2986 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2987 return "mov3q%.l %1,%0";
2988 else if (src
== 0 && ADDRESS_REG_P (dest
))
2989 return "sub%.l %0,%0";
2990 else if (DATA_REG_P (dest
))
2991 return output_move_const_into_data_reg (operands
);
2992 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2994 if (valid_mov3q_const (src
))
2995 return "mov3q%.l %1,%0";
2996 return "move%.w %1,%0";
2998 else if (MEM_P (dest
)
2999 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3000 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3001 && IN_RANGE (src
, -0x8000, 0x7fff))
3003 if (valid_mov3q_const (src
))
3004 return "mov3q%.l %1,%-";
3007 return "move%.l %1,%0";
3011 output_move_simode (rtx
*operands
)
3013 if (GET_CODE (operands
[1]) == CONST_INT
)
3014 return output_move_simode_const (operands
);
3015 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3016 || GET_CODE (operands
[1]) == CONST
)
3017 && push_operand (operands
[0], SImode
))
3019 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3020 || GET_CODE (operands
[1]) == CONST
)
3021 && ADDRESS_REG_P (operands
[0]))
3022 return "lea %a1,%0";
3023 return "move%.l %1,%0";
3027 output_move_himode (rtx
*operands
)
3029 if (GET_CODE (operands
[1]) == CONST_INT
)
3031 if (operands
[1] == const0_rtx
3032 && (DATA_REG_P (operands
[0])
3033 || GET_CODE (operands
[0]) == MEM
)
3034 /* clr insns on 68000 read before writing. */
3035 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3036 || !(GET_CODE (operands
[0]) == MEM
3037 && MEM_VOLATILE_P (operands
[0]))))
3039 else if (operands
[1] == const0_rtx
3040 && ADDRESS_REG_P (operands
[0]))
3041 return "sub%.l %0,%0";
3042 else if (DATA_REG_P (operands
[0])
3043 && INTVAL (operands
[1]) < 128
3044 && INTVAL (operands
[1]) >= -128)
3045 return "moveq %1,%0";
3046 else if (INTVAL (operands
[1]) < 0x8000
3047 && INTVAL (operands
[1]) >= -0x8000)
3048 return "move%.w %1,%0";
3050 else if (CONSTANT_P (operands
[1]))
3051 return "move%.l %1,%0";
3052 return "move%.w %1,%0";
3056 output_move_qimode (rtx
*operands
)
3058 /* 68k family always modifies the stack pointer by at least 2, even for
3059 byte pushes. The 5200 (ColdFire) does not do this. */
3061 /* This case is generated by pushqi1 pattern now. */
3062 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3063 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3064 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3065 && ! ADDRESS_REG_P (operands
[1])
3066 && ! TARGET_COLDFIRE
));
3068 /* clr and st insns on 68000 read before writing. */
3069 if (!ADDRESS_REG_P (operands
[0])
3070 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3071 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3073 if (operands
[1] == const0_rtx
)
3075 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3076 && GET_CODE (operands
[1]) == CONST_INT
3077 && (INTVAL (operands
[1]) & 255) == 255)
3083 if (GET_CODE (operands
[1]) == CONST_INT
3084 && DATA_REG_P (operands
[0])
3085 && INTVAL (operands
[1]) < 128
3086 && INTVAL (operands
[1]) >= -128)
3087 return "moveq %1,%0";
3088 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3089 return "sub%.l %0,%0";
3090 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3091 return "move%.l %1,%0";
3092 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3093 from address registers. */
3094 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3095 return "move%.w %1,%0";
3096 return "move%.b %1,%0";
3100 output_move_stricthi (rtx
*operands
)
3102 if (operands
[1] == const0_rtx
3103 /* clr insns on 68000 read before writing. */
3104 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3105 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3107 return "move%.w %1,%0";
3111 output_move_strictqi (rtx
*operands
)
3113 if (operands
[1] == const0_rtx
3114 /* clr insns on 68000 read before writing. */
3115 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3116 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3118 return "move%.b %1,%0";
3121 /* Return the best assembler insn template
3122 for moving operands[1] into operands[0] as a fullword. */
3125 singlemove_string (rtx
*operands
)
3127 if (GET_CODE (operands
[1]) == CONST_INT
)
3128 return output_move_simode_const (operands
);
3129 return "move%.l %1,%0";
3133 /* Output assembler or rtl code to perform a doubleword move insn
3134 with operands OPERANDS.
3135 Pointers to 3 helper functions should be specified:
3136 HANDLE_REG_ADJUST to adjust a register by a small value,
3137 HANDLE_COMPADR to compute an address and
3138 HANDLE_MOVSI to move 4 bytes. */
3141 handle_move_double (rtx operands
[2],
3142 void (*handle_reg_adjust
) (rtx
, int),
3143 void (*handle_compadr
) (rtx
[2]),
3144 void (*handle_movsi
) (rtx
[2]))
3148 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3153 rtx addreg0
= 0, addreg1
= 0;
3154 int dest_overlapped_low
= 0;
3155 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3160 /* First classify both operands. */
3162 if (REG_P (operands
[0]))
3164 else if (offsettable_memref_p (operands
[0]))
3166 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3168 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3170 else if (GET_CODE (operands
[0]) == MEM
)
3175 if (REG_P (operands
[1]))
3177 else if (CONSTANT_P (operands
[1]))
3179 else if (offsettable_memref_p (operands
[1]))
3181 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3183 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3185 else if (GET_CODE (operands
[1]) == MEM
)
3190 /* Check for the cases that the operand constraints are not supposed
3191 to allow to happen. Generating code for these cases is
3193 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3195 /* If one operand is decrementing and one is incrementing
3196 decrement the former register explicitly
3197 and change that operand into ordinary indexing. */
3199 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3201 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3203 handle_reg_adjust (operands
[0], -size
);
3205 if (GET_MODE (operands
[1]) == XFmode
)
3206 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3207 else if (GET_MODE (operands
[0]) == DFmode
)
3208 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3210 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3213 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3215 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3217 handle_reg_adjust (operands
[1], -size
);
3219 if (GET_MODE (operands
[1]) == XFmode
)
3220 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3221 else if (GET_MODE (operands
[1]) == DFmode
)
3222 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3224 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3228 /* If an operand is an unoffsettable memory ref, find a register
3229 we can increment temporarily to make it refer to the second word. */
3231 if (optype0
== MEMOP
)
3232 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3234 if (optype1
== MEMOP
)
3235 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3237 /* Ok, we can do one word at a time.
3238 Normally we do the low-numbered word first,
3239 but if either operand is autodecrementing then we
3240 do the high-numbered word first.
3242 In either case, set up in LATEHALF the operands to use
3243 for the high-numbered word and in some cases alter the
3244 operands in OPERANDS to be suitable for the low-numbered word. */
3248 if (optype0
== REGOP
)
3250 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3251 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3253 else if (optype0
== OFFSOP
)
3255 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3256 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3260 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3261 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3264 if (optype1
== REGOP
)
3266 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3267 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3269 else if (optype1
== OFFSOP
)
3271 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3272 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3274 else if (optype1
== CNSTOP
)
3276 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3281 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3282 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3283 operands
[1] = GEN_INT (l
[0]);
3284 middlehalf
[1] = GEN_INT (l
[1]);
3285 latehalf
[1] = GEN_INT (l
[2]);
3289 /* No non-CONST_DOUBLE constant should ever appear
3291 gcc_assert (!CONSTANT_P (operands
[1]));
3296 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3297 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3301 /* size is not 12: */
3303 if (optype0
== REGOP
)
3304 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3305 else if (optype0
== OFFSOP
)
3306 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3308 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3310 if (optype1
== REGOP
)
3311 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3312 else if (optype1
== OFFSOP
)
3313 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3314 else if (optype1
== CNSTOP
)
3315 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3317 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3320 /* If insn is effectively movd N(sp),-(sp) then we will do the
3321 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3322 for the low word as well, to compensate for the first decrement of sp. */
3323 if (optype0
== PUSHOP
3324 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3325 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3326 operands
[1] = middlehalf
[1] = latehalf
[1];
3328 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3329 if the upper part of reg N does not appear in the MEM, arrange to
3330 emit the move late-half first. Otherwise, compute the MEM address
3331 into the upper part of N and use that as a pointer to the memory
3333 if (optype0
== REGOP
3334 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3336 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3338 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3339 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3341 /* If both halves of dest are used in the src memory address,
3342 compute the address into latehalf of dest.
3343 Note that this can't happen if the dest is two data regs. */
3345 xops
[0] = latehalf
[0];
3346 xops
[1] = XEXP (operands
[1], 0);
3348 handle_compadr (xops
);
3349 if (GET_MODE (operands
[1]) == XFmode
)
3351 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3352 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3353 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3357 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3358 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3362 && reg_overlap_mentioned_p (middlehalf
[0],
3363 XEXP (operands
[1], 0)))
3365 /* Check for two regs used by both source and dest.
3366 Note that this can't happen if the dest is all data regs.
3367 It can happen if the dest is d6, d7, a0.
3368 But in that case, latehalf is an addr reg, so
3369 the code at compadr does ok. */
3371 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3372 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3375 /* JRV says this can't happen: */
3376 gcc_assert (!addreg0
&& !addreg1
);
3378 /* Only the middle reg conflicts; simply put it last. */
3379 handle_movsi (operands
);
3380 handle_movsi (latehalf
);
3381 handle_movsi (middlehalf
);
3385 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3386 /* If the low half of dest is mentioned in the source memory
3387 address, the arrange to emit the move late half first. */
3388 dest_overlapped_low
= 1;
3391 /* If one or both operands autodecrementing,
3392 do the two words, high-numbered first. */
3394 /* Likewise, the first move would clobber the source of the second one,
3395 do them in the other order. This happens only for registers;
3396 such overlap can't happen in memory unless the user explicitly
3397 sets it up, and that is an undefined circumstance. */
3399 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3400 || (optype0
== REGOP
&& optype1
== REGOP
3401 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3402 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3403 || dest_overlapped_low
)
3405 /* Make any unoffsettable addresses point at high-numbered word. */
3407 handle_reg_adjust (addreg0
, size
- 4);
3409 handle_reg_adjust (addreg1
, size
- 4);
3412 handle_movsi (latehalf
);
3414 /* Undo the adds we just did. */
3416 handle_reg_adjust (addreg0
, -4);
3418 handle_reg_adjust (addreg1
, -4);
3422 handle_movsi (middlehalf
);
3425 handle_reg_adjust (addreg0
, -4);
3427 handle_reg_adjust (addreg1
, -4);
3430 /* Do low-numbered word. */
3432 handle_movsi (operands
);
3436 /* Normal case: do the two words, low-numbered first. */
3438 m68k_final_prescan_insn (NULL
, operands
, 2);
3439 handle_movsi (operands
);
3441 /* Do the middle one of the three words for long double */
3445 handle_reg_adjust (addreg0
, 4);
3447 handle_reg_adjust (addreg1
, 4);
3449 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3450 handle_movsi (middlehalf
);
3453 /* Make any unoffsettable addresses point at high-numbered word. */
3455 handle_reg_adjust (addreg0
, 4);
3457 handle_reg_adjust (addreg1
, 4);
3460 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3461 handle_movsi (latehalf
);
3463 /* Undo the adds we just did. */
3465 handle_reg_adjust (addreg0
, -(size
- 4));
3467 handle_reg_adjust (addreg1
, -(size
- 4));
3472 /* Output assembler code to adjust REG by N. */
3474 output_reg_adjust (rtx reg
, int n
)
3478 gcc_assert (GET_MODE (reg
) == SImode
3479 && -12 <= n
&& n
!= 0 && n
<= 12);
3484 s
= "add%.l #12,%0";
3488 s
= "addq%.l #8,%0";
3492 s
= "addq%.l #4,%0";
3496 s
= "sub%.l #12,%0";
3500 s
= "subq%.l #8,%0";
3504 s
= "subq%.l #4,%0";
3512 output_asm_insn (s
, ®
);
3515 /* Emit rtl code to adjust REG by N. */
3517 emit_reg_adjust (rtx reg1
, int n
)
3521 gcc_assert (GET_MODE (reg1
) == SImode
3522 && -12 <= n
&& n
!= 0 && n
<= 12);
3524 reg1
= copy_rtx (reg1
);
3525 reg2
= copy_rtx (reg1
);
3528 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3530 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3535 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3537 output_compadr (rtx operands
[2])
3539 output_asm_insn ("lea %a1,%0", operands
);
3542 /* Output the best assembler insn for moving operands[1] into operands[0]
3545 output_movsi (rtx operands
[2])
3547 output_asm_insn (singlemove_string (operands
), operands
);
3550 /* Copy OP and change its mode to MODE. */
3552 copy_operand (rtx op
, enum machine_mode mode
)
3554 /* ??? This looks really ugly. There must be a better way
3555 to change a mode on the operand. */
3556 if (GET_MODE (op
) != VOIDmode
)
3559 op
= gen_rtx_REG (mode
, REGNO (op
));
3563 PUT_MODE (op
, mode
);
3570 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3572 emit_movsi (rtx operands
[2])
3574 operands
[0] = copy_operand (operands
[0], SImode
);
3575 operands
[1] = copy_operand (operands
[1], SImode
);
3577 emit_insn (gen_movsi (operands
[0], operands
[1]));
3580 /* Output assembler code to perform a doubleword move insn
3581 with operands OPERANDS. */
3583 output_move_double (rtx
*operands
)
3585 handle_move_double (operands
,
3586 output_reg_adjust
, output_compadr
, output_movsi
);
3591 /* Output rtl code to perform a doubleword move insn
3592 with operands OPERANDS. */
3594 m68k_emit_move_double (rtx operands
[2])
3596 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3599 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3600 new rtx with the correct mode. */
3603 force_mode (enum machine_mode mode
, rtx orig
)
3605 if (mode
== GET_MODE (orig
))
3608 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3611 return gen_rtx_REG (mode
, REGNO (orig
));
3615 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3617 return reg_renumber
&& FP_REG_P (op
);
3620 /* Emit insns to move operands[1] into operands[0].
3622 Return 1 if we have written out everything that needs to be done to
3623 do the move. Otherwise, return 0 and the caller will emit the move
3626 Note SCRATCH_REG may not be in the proper mode depending on how it
3627 will be used. This routine is responsible for creating a new copy
3628 of SCRATCH_REG in the proper mode. */
3631 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3633 register rtx operand0
= operands
[0];
3634 register rtx operand1
= operands
[1];
3638 && reload_in_progress
&& GET_CODE (operand0
) == REG
3639 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3640 operand0
= reg_equiv_mem (REGNO (operand0
));
3641 else if (scratch_reg
3642 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3643 && GET_CODE (SUBREG_REG (operand0
)) == REG
3644 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3646 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3647 the code which tracks sets/uses for delete_output_reload. */
3648 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3649 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3650 SUBREG_BYTE (operand0
));
3651 operand0
= alter_subreg (&temp
);
3655 && reload_in_progress
&& GET_CODE (operand1
) == REG
3656 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3657 operand1
= reg_equiv_mem (REGNO (operand1
));
3658 else if (scratch_reg
3659 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3660 && GET_CODE (SUBREG_REG (operand1
)) == REG
3661 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3663 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3664 the code which tracks sets/uses for delete_output_reload. */
3665 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3666 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3667 SUBREG_BYTE (operand1
));
3668 operand1
= alter_subreg (&temp
);
3671 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3672 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3673 != XEXP (operand0
, 0)))
3674 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3675 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3676 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3677 != XEXP (operand1
, 0)))
3678 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3680 /* Handle secondary reloads for loads/stores of FP registers where
3681 the address is symbolic by using the scratch register */
3682 if (fp_reg_operand (operand0
, mode
)
3683 && ((GET_CODE (operand1
) == MEM
3684 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3685 || ((GET_CODE (operand1
) == SUBREG
3686 && GET_CODE (XEXP (operand1
, 0)) == MEM
3687 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3690 if (GET_CODE (operand1
) == SUBREG
)
3691 operand1
= XEXP (operand1
, 0);
3693 /* SCRATCH_REG will hold an address. We want
3694 it in SImode regardless of what mode it was originally given
3696 scratch_reg
= force_mode (SImode
, scratch_reg
);
3698 /* D might not fit in 14 bits either; for such cases load D into
3700 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3702 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3703 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3705 XEXP (XEXP (operand1
, 0), 0),
3709 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3710 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3711 gen_rtx_MEM (mode
, scratch_reg
)));
3714 else if (fp_reg_operand (operand1
, mode
)
3715 && ((GET_CODE (operand0
) == MEM
3716 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3717 || ((GET_CODE (operand0
) == SUBREG
)
3718 && GET_CODE (XEXP (operand0
, 0)) == MEM
3719 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3722 if (GET_CODE (operand0
) == SUBREG
)
3723 operand0
= XEXP (operand0
, 0);
3725 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3726 it in SIMODE regardless of what mode it was originally given
3728 scratch_reg
= force_mode (SImode
, scratch_reg
);
3730 /* D might not fit in 14 bits either; for such cases load D into
3732 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3734 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3735 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3738 XEXP (XEXP (operand0
, 0),
3743 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3744 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3748 /* Handle secondary reloads for loads of FP registers from constant
3749 expressions by forcing the constant into memory.
3751 use scratch_reg to hold the address of the memory location.
3753 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3754 NO_REGS when presented with a const_int and an register class
3755 containing only FP registers. Doing so unfortunately creates
3756 more problems than it solves. Fix this for 2.5. */
3757 else if (fp_reg_operand (operand0
, mode
)
3758 && CONSTANT_P (operand1
)
3763 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3764 it in SIMODE regardless of what mode it was originally given
3766 scratch_reg
= force_mode (SImode
, scratch_reg
);
3768 /* Force the constant into memory and put the address of the
3769 memory location into scratch_reg. */
3770 xoperands
[0] = scratch_reg
;
3771 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3772 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3774 /* Now load the destination register. */
3775 emit_insn (gen_rtx_SET (mode
, operand0
,
3776 gen_rtx_MEM (mode
, scratch_reg
)));
3780 /* Now have insn-emit do whatever it normally does. */
3784 /* Split one or more DImode RTL references into pairs of SImode
3785 references. The RTL can be REG, offsettable MEM, integer constant, or
3786 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3787 split and "num" is its length. lo_half and hi_half are output arrays
3788 that parallel "operands". */
3791 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3795 rtx op
= operands
[num
];
3797 /* simplify_subreg refuses to split volatile memory addresses,
3798 but we still have to handle it. */
3799 if (GET_CODE (op
) == MEM
)
3801 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3802 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3806 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3807 GET_MODE (op
) == VOIDmode
3808 ? DImode
: GET_MODE (op
), 4);
3809 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3810 GET_MODE (op
) == VOIDmode
3811 ? DImode
: GET_MODE (op
), 0);
3816 /* Split X into a base and a constant offset, storing them in *BASE
3817 and *OFFSET respectively. */
3820 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3823 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3825 *offset
+= INTVAL (XEXP (x
, 1));
3831 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3832 instruction. STORE_P says whether the move is a load or store.
3834 If the instruction uses post-increment or pre-decrement addressing,
3835 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3836 adjustment. This adjustment will be made by the first element of
3837 PARALLEL, with the loads or stores starting at element 1. If the
3838 instruction does not use post-increment or pre-decrement addressing,
3839 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3840 start at element 0. */
3843 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3844 HOST_WIDE_INT automod_offset
, bool store_p
)
3846 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3847 HOST_WIDE_INT offset
, mem_offset
;
3849 enum reg_class rclass
;
3851 len
= XVECLEN (pattern
, 0);
3852 first
= (automod_base
!= NULL
);
3856 /* Stores must be pre-decrement and loads must be post-increment. */
3857 if (store_p
!= (automod_offset
< 0))
3860 /* Work out the base and offset for lowest memory location. */
3861 base
= automod_base
;
3862 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3866 /* Allow any valid base and offset in the first access. */
3873 for (i
= first
; i
< len
; i
++)
3875 /* We need a plain SET. */
3876 set
= XVECEXP (pattern
, 0, i
);
3877 if (GET_CODE (set
) != SET
)
3880 /* Check that we have a memory location... */
3881 mem
= XEXP (set
, !store_p
);
3882 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3885 /* ...with the right address. */
3888 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3889 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3890 There are no mode restrictions for 680x0 besides the
3891 automodification rules enforced above. */
3893 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3898 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3899 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3903 /* Check that we have a register of the required mode and class. */
3904 reg
= XEXP (set
, store_p
);
3906 || !HARD_REGISTER_P (reg
)
3907 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3912 /* The register must belong to RCLASS and have a higher number
3913 than the register in the previous SET. */
3914 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3915 || REGNO (last_reg
) >= REGNO (reg
))
3920 /* Work out which register class we need. */
3921 if (INT_REGNO_P (REGNO (reg
)))
3922 rclass
= GENERAL_REGS
;
3923 else if (FP_REGNO_P (REGNO (reg
)))
3930 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3933 /* If we have an automodification, check whether the final offset is OK. */
3934 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3937 /* Reject unprofitable cases. */
3938 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3944 /* Return the assembly code template for a movem or fmovem instruction
3945 whose pattern is given by PATTERN. Store the template's operands
3948 If the instruction uses post-increment or pre-decrement addressing,
3949 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3950 is true if this is a store instruction. */
3953 m68k_output_movem (rtx
*operands
, rtx pattern
,
3954 HOST_WIDE_INT automod_offset
, bool store_p
)
3959 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3961 first
= (automod_offset
!= 0);
3962 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3964 /* When using movem with pre-decrement addressing, register X + D0_REG
3965 is controlled by bit 15 - X. For all other addressing modes,
3966 register X + D0_REG is controlled by bit X. Confusingly, the
3967 register mask for fmovem is in the opposite order to that for
3971 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3972 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3973 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3974 if (automod_offset
< 0)
3976 if (FP_REGNO_P (regno
))
3977 mask
|= 1 << (regno
- FP0_REG
);
3979 mask
|= 1 << (15 - (regno
- D0_REG
));
3983 if (FP_REGNO_P (regno
))
3984 mask
|= 1 << (7 - (regno
- FP0_REG
));
3986 mask
|= 1 << (regno
- D0_REG
);
3991 if (automod_offset
== 0)
3992 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3993 else if (automod_offset
< 0)
3994 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3996 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3997 operands
[1] = GEN_INT (mask
);
3998 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4001 return "fmovem %1,%a0";
4003 return "fmovem %a0,%1";
4008 return "movem%.l %1,%a0";
4010 return "movem%.l %a0,%1";
4014 /* Return a REG that occurs in ADDR with coefficient 1.
4015 ADDR can be effectively incremented by incrementing REG. */
4018 find_addr_reg (rtx addr
)
4020 while (GET_CODE (addr
) == PLUS
)
4022 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4023 addr
= XEXP (addr
, 0);
4024 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4025 addr
= XEXP (addr
, 1);
4026 else if (CONSTANT_P (XEXP (addr
, 0)))
4027 addr
= XEXP (addr
, 1);
4028 else if (CONSTANT_P (XEXP (addr
, 1)))
4029 addr
= XEXP (addr
, 0);
4033 gcc_assert (GET_CODE (addr
) == REG
);
4037 /* Output assembler code to perform a 32-bit 3-operand add. */
4040 output_addsi3 (rtx
*operands
)
4042 if (! operands_match_p (operands
[0], operands
[1]))
4044 if (!ADDRESS_REG_P (operands
[1]))
4046 rtx tmp
= operands
[1];
4048 operands
[1] = operands
[2];
4052 /* These insns can result from reloads to access
4053 stack slots over 64k from the frame pointer. */
4054 if (GET_CODE (operands
[2]) == CONST_INT
4055 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4056 return "move%.l %2,%0\n\tadd%.l %1,%0";
4057 if (GET_CODE (operands
[2]) == REG
)
4058 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4059 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4061 if (GET_CODE (operands
[2]) == CONST_INT
)
4063 if (INTVAL (operands
[2]) > 0
4064 && INTVAL (operands
[2]) <= 8)
4065 return "addq%.l %2,%0";
4066 if (INTVAL (operands
[2]) < 0
4067 && INTVAL (operands
[2]) >= -8)
4069 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4070 return "subq%.l %2,%0";
4072 /* On the CPU32 it is faster to use two addql instructions to
4073 add a small integer (8 < N <= 16) to a register.
4074 Likewise for subql. */
4075 if (TUNE_CPU32
&& REG_P (operands
[0]))
4077 if (INTVAL (operands
[2]) > 8
4078 && INTVAL (operands
[2]) <= 16)
4080 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4081 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4083 if (INTVAL (operands
[2]) < -8
4084 && INTVAL (operands
[2]) >= -16)
4086 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4087 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4090 if (ADDRESS_REG_P (operands
[0])
4091 && INTVAL (operands
[2]) >= -0x8000
4092 && INTVAL (operands
[2]) < 0x8000)
4095 return "add%.w %2,%0";
4097 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4100 return "add%.l %2,%0";
4103 /* Store in cc_status the expressions that the condition codes will
4104 describe after execution of an instruction whose pattern is EXP.
4105 Do not alter them if the instruction would not alter the cc's. */
4107 /* On the 68000, all the insns to store in an address register fail to
4108 set the cc's. However, in some cases these instructions can make it
4109 possibly invalid to use the saved cc's. In those cases we clear out
4110 some or all of the saved cc's so they won't be used. */
4113 notice_update_cc (rtx exp
, rtx insn
)
4115 if (GET_CODE (exp
) == SET
)
4117 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4119 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4121 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4122 cc_status
.value1
= 0;
4123 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4124 cc_status
.value2
= 0;
4126 /* fmoves to memory or data registers do not set the condition
4127 codes. Normal moves _do_ set the condition codes, but not in
4128 a way that is appropriate for comparison with 0, because -0.0
4129 would be treated as a negative nonzero number. Note that it
4130 isn't appropriate to conditionalize this restriction on
4131 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4132 we care about the difference between -0.0 and +0.0. */
4133 else if (!FP_REG_P (SET_DEST (exp
))
4134 && SET_DEST (exp
) != cc0_rtx
4135 && (FP_REG_P (SET_SRC (exp
))
4136 || GET_CODE (SET_SRC (exp
)) == FIX
4137 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4139 /* A pair of move insns doesn't produce a useful overall cc. */
4140 else if (!FP_REG_P (SET_DEST (exp
))
4141 && !FP_REG_P (SET_SRC (exp
))
4142 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4143 && (GET_CODE (SET_SRC (exp
)) == REG
4144 || GET_CODE (SET_SRC (exp
)) == MEM
4145 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4147 else if (SET_DEST (exp
) != pc_rtx
)
4149 cc_status
.flags
= 0;
4150 cc_status
.value1
= SET_DEST (exp
);
4151 cc_status
.value2
= SET_SRC (exp
);
4154 else if (GET_CODE (exp
) == PARALLEL
4155 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4157 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4158 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4160 if (ADDRESS_REG_P (dest
))
4162 else if (dest
!= pc_rtx
)
4164 cc_status
.flags
= 0;
4165 cc_status
.value1
= dest
;
4166 cc_status
.value2
= src
;
4171 if (cc_status
.value2
!= 0
4172 && ADDRESS_REG_P (cc_status
.value2
)
4173 && GET_MODE (cc_status
.value2
) == QImode
)
4175 if (cc_status
.value2
!= 0)
4176 switch (GET_CODE (cc_status
.value2
))
4178 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4179 case ROTATE
: case ROTATERT
:
4180 /* These instructions always clear the overflow bit, and set
4181 the carry to the bit shifted out. */
4182 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4185 case PLUS
: case MINUS
: case MULT
:
4186 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4187 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4188 cc_status
.flags
|= CC_NO_OVERFLOW
;
4191 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4192 ends with a move insn moving r2 in r2's mode.
4193 Thus, the cc's are set for r2.
4194 This can set N bit spuriously. */
4195 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4200 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4202 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4203 cc_status
.value2
= 0;
4204 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4205 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4206 cc_status
.flags
= CC_IN_68881
;
4207 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4208 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4210 cc_status
.flags
= CC_IN_68881
;
4211 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4212 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4213 cc_status
.flags
|= CC_REVERSED
;
4218 output_move_const_double (rtx
*operands
)
4220 int code
= standard_68881_constant_p (operands
[1]);
4224 static char buf
[40];
4226 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4229 return "fmove%.d %1,%0";
4233 output_move_const_single (rtx
*operands
)
4235 int code
= standard_68881_constant_p (operands
[1]);
4239 static char buf
[40];
4241 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4244 return "fmove%.s %f1,%0";
4247 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4248 from the "fmovecr" instruction.
4249 The value, anded with 0xff, gives the code to use in fmovecr
4250 to get the desired constant. */
4252 /* This code has been fixed for cross-compilation. */
4254 static int inited_68881_table
= 0;
4256 static const char *const strings_68881
[7] = {
4266 static const int codes_68881
[7] = {
4276 REAL_VALUE_TYPE values_68881
[7];
4278 /* Set up values_68881 array by converting the decimal values
4279 strings_68881 to binary. */
4282 init_68881_table (void)
4286 enum machine_mode mode
;
4289 for (i
= 0; i
< 7; i
++)
4293 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4294 values_68881
[i
] = r
;
4296 inited_68881_table
= 1;
4300 standard_68881_constant_p (rtx x
)
4305 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4306 used at all on those chips. */
4310 if (! inited_68881_table
)
4311 init_68881_table ();
4313 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4315 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4317 for (i
= 0; i
< 6; i
++)
4319 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4320 return (codes_68881
[i
]);
4323 if (GET_MODE (x
) == SFmode
)
4326 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4327 return (codes_68881
[6]);
4329 /* larger powers of ten in the constants ram are not used
4330 because they are not equal to a `double' C constant. */
4334 /* If X is a floating-point constant, return the logarithm of X base 2,
4335 or 0 if X is not a power of 2. */
4338 floating_exact_log2 (rtx x
)
4340 REAL_VALUE_TYPE r
, r1
;
4343 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4345 if (REAL_VALUES_LESS (r
, dconst1
))
4348 exp
= real_exponent (&r
);
4349 real_2expN (&r1
, exp
, DFmode
);
4350 if (REAL_VALUES_EQUAL (r1
, r
))
4356 /* A C compound statement to output to stdio stream STREAM the
4357 assembler syntax for an instruction operand X. X is an RTL
4360 CODE is a value that can be used to specify one of several ways
4361 of printing the operand. It is used when identical operands
4362 must be printed differently depending on the context. CODE
4363 comes from the `%' specification that was used to request
4364 printing of the operand. If the specification was just `%DIGIT'
4365 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4366 is the ASCII code for LTR.
4368 If X is a register, this macro should print the register's name.
4369 The names can be found in an array `reg_names' whose type is
4370 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4372 When the machine description has a specification `%PUNCT' (a `%'
4373 followed by a punctuation character), this macro is called with
4374 a null pointer for X and the punctuation character for CODE.
4376 The m68k specific codes are:
4378 '.' for dot needed in Motorola-style opcode names.
4379 '-' for an operand pushing on the stack:
4380 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4381 '+' for an operand pushing on the stack:
4382 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4383 '@' for a reference to the top word on the stack:
4384 sp@, (sp) or (%sp) depending on the style of syntax.
4385 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4386 but & in SGS syntax).
4387 '!' for the cc register (used in an `and to cc' insn).
4388 '$' for the letter `s' in an op code, but only on the 68040.
4389 '&' for the letter `d' in an op code, but only on the 68040.
4390 '/' for register prefix needed by longlong.h.
4391 '?' for m68k_library_id_string
4393 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4394 'd' to force memory addressing to be absolute, not relative.
4395 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4396 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4397 or print pair of registers as rx:ry.
4398 'p' print an address with @PLTPC attached, but only if the operand
4399 is not locally-bound. */
4402 print_operand (FILE *file
, rtx op
, int letter
)
4407 fprintf (file
, ".");
4409 else if (letter
== '#')
4410 asm_fprintf (file
, "%I");
4411 else if (letter
== '-')
4412 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4413 else if (letter
== '+')
4414 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4415 else if (letter
== '@')
4416 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4417 else if (letter
== '!')
4418 asm_fprintf (file
, "%Rfpcr");
4419 else if (letter
== '$')
4422 fprintf (file
, "s");
4424 else if (letter
== '&')
4427 fprintf (file
, "d");
4429 else if (letter
== '/')
4430 asm_fprintf (file
, "%R");
4431 else if (letter
== '?')
4432 asm_fprintf (file
, m68k_library_id_string
);
4433 else if (letter
== 'p')
4435 output_addr_const (file
, op
);
4436 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4437 fprintf (file
, "@PLTPC");
4439 else if (GET_CODE (op
) == REG
)
4442 /* Print out the second register name of a register pair.
4443 I.e., R (6) => 7. */
4444 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4446 fputs (M68K_REGNAME(REGNO (op
)), file
);
4448 else if (GET_CODE (op
) == MEM
)
4450 output_address (XEXP (op
, 0));
4451 if (letter
== 'd' && ! TARGET_68020
4452 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4453 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4454 && INTVAL (XEXP (op
, 0)) < 0x8000
4455 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4456 fprintf (file
, MOTOROLA
? ".l" : ":l");
4458 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4462 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4463 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4464 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4466 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4470 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4471 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4472 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4473 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4475 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4479 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4480 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4481 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4485 /* Use `print_operand_address' instead of `output_addr_const'
4486 to ensure that we print relevant PIC stuff. */
4487 asm_fprintf (file
, "%I");
4489 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4490 print_operand_address (file
, op
);
4492 output_addr_const (file
, op
);
4496 /* Return string for TLS relocation RELOC. */
4499 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4501 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4502 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4509 if (flag_pic
== 1 && TARGET_68020
)
4550 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4553 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4555 if (GET_CODE (x
) == UNSPEC
)
4557 switch (XINT (x
, 1))
4559 case UNSPEC_RELOC16
:
4560 case UNSPEC_RELOC32
:
4561 output_addr_const (file
, XVECEXP (x
, 0, 0));
4562 fputs (m68k_get_reloc_decoration
4563 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4574 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4577 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4579 gcc_assert (size
== 4);
4580 fputs ("\t.long\t", file
);
4581 output_addr_const (file
, x
);
4582 fputs ("@TLSLDO+0x8000", file
);
4585 /* In the name of slightly smaller debug output, and to cater to
4586 general assembler lossage, recognize various UNSPEC sequences
4587 and turn them back into a direct symbol reference. */
4590 m68k_delegitimize_address (rtx orig_x
)
4593 struct m68k_address addr
;
4596 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4601 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4604 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4605 || addr
.offset
== NULL_RTX
4606 || GET_CODE (addr
.offset
) != CONST
)
4609 unspec
= XEXP (addr
.offset
, 0);
4610 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4611 unspec
= XEXP (unspec
, 0);
4612 if (GET_CODE (unspec
) != UNSPEC
4613 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4614 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4616 x
= XVECEXP (unspec
, 0, 0);
4617 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4618 if (unspec
!= XEXP (addr
.offset
, 0))
4619 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4622 rtx idx
= addr
.index
;
4623 if (addr
.scale
!= 1)
4624 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4625 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4628 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4630 x
= replace_equiv_address_nv (orig_x
, x
);
4635 /* A C compound statement to output to stdio stream STREAM the
4636 assembler syntax for an instruction operand that is a memory
4637 reference whose address is ADDR. ADDR is an RTL expression.
4639 Note that this contains a kludge that knows that the only reason
4640 we have an address (plus (label_ref...) (reg...)) when not generating
4641 PIC code is in the insn before a tablejump, and we know that m68k.md
4642 generates a label LInnn: on such an insn.
4644 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4645 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4647 This routine is responsible for distinguishing between -fpic and -fPIC
4648 style relocations in an address. When generating -fpic code the
4649 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4650 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4653 print_operand_address (FILE *file
, rtx addr
)
4655 struct m68k_address address
;
4657 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4660 if (address
.code
== PRE_DEC
)
4661 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4662 M68K_REGNAME (REGNO (address
.base
)));
4663 else if (address
.code
== POST_INC
)
4664 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4665 M68K_REGNAME (REGNO (address
.base
)));
4666 else if (!address
.base
&& !address
.index
)
4668 /* A constant address. */
4669 gcc_assert (address
.offset
== addr
);
4670 if (GET_CODE (addr
) == CONST_INT
)
4672 /* (xxx).w or (xxx).l. */
4673 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4674 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4676 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4678 else if (TARGET_PCREL
)
4680 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4682 output_addr_const (file
, addr
);
4683 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4687 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4688 name ends in `.<letter>', as the last 2 characters can be
4689 mistaken as a size suffix. Put the name in parentheses. */
4690 if (GET_CODE (addr
) == SYMBOL_REF
4691 && strlen (XSTR (addr
, 0)) > 2
4692 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4695 output_addr_const (file
, addr
);
4699 output_addr_const (file
, addr
);
4706 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4707 label being accessed, otherwise it is -1. */
4708 labelno
= (address
.offset
4710 && GET_CODE (address
.offset
) == LABEL_REF
4711 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4715 /* Print the "offset(base" component. */
4717 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4721 output_addr_const (file
, address
.offset
);
4725 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4727 /* Print the ",index" component, if any. */
4732 fprintf (file
, "%s.%c",
4733 M68K_REGNAME (REGNO (address
.index
)),
4734 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4735 if (address
.scale
!= 1)
4736 fprintf (file
, "*%d", address
.scale
);
4740 else /* !MOTOROLA */
4742 if (!address
.offset
&& !address
.index
)
4743 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4746 /* Print the "base@(offset" component. */
4748 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4752 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4753 fprintf (file
, "@(");
4755 output_addr_const (file
, address
.offset
);
4757 /* Print the ",index" component, if any. */
4760 fprintf (file
, ",%s:%c",
4761 M68K_REGNAME (REGNO (address
.index
)),
4762 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4763 if (address
.scale
!= 1)
4764 fprintf (file
, ":%d", address
.scale
);
4772 /* Check for cases where a clr insns can be omitted from code using
4773 strict_low_part sets. For example, the second clrl here is not needed:
4774 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4776 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4777 insn we are checking for redundancy. TARGET is the register set by the
4781 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4786 while ((p
= PREV_INSN (p
)))
4788 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4794 /* If it isn't an insn, then give up. */
4798 if (reg_set_p (target
, p
))
4800 rtx set
= single_set (p
);
4803 /* If it isn't an easy to recognize insn, then give up. */
4807 dest
= SET_DEST (set
);
4809 /* If this sets the entire target register to zero, then our
4810 first_insn is redundant. */
4811 if (rtx_equal_p (dest
, target
)
4812 && SET_SRC (set
) == const0_rtx
)
4814 else if (GET_CODE (dest
) == STRICT_LOW_PART
4815 && GET_CODE (XEXP (dest
, 0)) == REG
4816 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4817 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4818 <= GET_MODE_SIZE (mode
)))
4819 /* This is a strict low part set which modifies less than
4820 we are using, so it is safe. */
4830 /* Operand predicates for implementing asymmetric pc-relative addressing
4831 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4832 when used as a source operand, but not as a destination operand.
4834 We model this by restricting the meaning of the basic predicates
4835 (general_operand, memory_operand, etc) to forbid the use of this
4836 addressing mode, and then define the following predicates that permit
4837 this addressing mode. These predicates can then be used for the
4838 source operands of the appropriate instructions.
4840 n.b. While it is theoretically possible to change all machine patterns
4841 to use this addressing more where permitted by the architecture,
4842 it has only been implemented for "common" cases: SImode, HImode, and
4843 QImode operands, and only for the principle operations that would
4844 require this addressing mode: data movement and simple integer operations.
4846 In parallel with these new predicates, two new constraint letters
4847 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4848 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4849 In the pcrel case 's' is only valid in combination with 'a' registers.
4850 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4851 of how these constraints are used.
4853 The use of these predicates is strictly optional, though patterns that
4854 don't will cause an extra reload register to be allocated where one
4857 lea (abc:w,%pc),%a0 ; need to reload address
4858 moveq &1,%d1 ; since write to pc-relative space
4859 movel %d1,%a0@ ; is not allowed
4861 lea (abc:w,%pc),%a1 ; no need to reload address here
4862 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4864 For more info, consult tiemann@cygnus.com.
4867 All of the ugliness with predicates and constraints is due to the
4868 simple fact that the m68k does not allow a pc-relative addressing
4869 mode as a destination. gcc does not distinguish between source and
4870 destination addresses. Hence, if we claim that pc-relative address
4871 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4872 end up with invalid code. To get around this problem, we left
4873 pc-relative modes as invalid addresses, and then added special
4874 predicates and constraints to accept them.
4876 A cleaner way to handle this is to modify gcc to distinguish
4877 between source and destination addresses. We can then say that
4878 pc-relative is a valid source address but not a valid destination
4879 address, and hopefully avoid a lot of the predicate and constraint
4880 hackery. Unfortunately, this would be a pretty big change. It would
4881 be a useful change for a number of ports, but there aren't any current
4882 plans to undertake this.
4884 ***************************************************************************/
4888 output_andsi3 (rtx
*operands
)
4891 if (GET_CODE (operands
[2]) == CONST_INT
4892 && (INTVAL (operands
[2]) | 0xffff) == -1
4893 && (DATA_REG_P (operands
[0])
4894 || offsettable_memref_p (operands
[0]))
4895 && !TARGET_COLDFIRE
)
4897 if (GET_CODE (operands
[0]) != REG
)
4898 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4899 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4900 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4902 if (operands
[2] == const0_rtx
)
4904 return "and%.w %2,%0";
4906 if (GET_CODE (operands
[2]) == CONST_INT
4907 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4908 && (DATA_REG_P (operands
[0])
4909 || offsettable_memref_p (operands
[0])))
4911 if (DATA_REG_P (operands
[0]))
4912 operands
[1] = GEN_INT (logval
);
4915 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4916 operands
[1] = GEN_INT (logval
% 8);
4918 /* This does not set condition codes in a standard way. */
4920 return "bclr %1,%0";
4922 return "and%.l %2,%0";
4926 output_iorsi3 (rtx
*operands
)
4928 register int logval
;
4929 if (GET_CODE (operands
[2]) == CONST_INT
4930 && INTVAL (operands
[2]) >> 16 == 0
4931 && (DATA_REG_P (operands
[0])
4932 || offsettable_memref_p (operands
[0]))
4933 && !TARGET_COLDFIRE
)
4935 if (GET_CODE (operands
[0]) != REG
)
4936 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4937 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4939 if (INTVAL (operands
[2]) == 0xffff)
4940 return "mov%.w %2,%0";
4941 return "or%.w %2,%0";
4943 if (GET_CODE (operands
[2]) == CONST_INT
4944 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4945 && (DATA_REG_P (operands
[0])
4946 || offsettable_memref_p (operands
[0])))
4948 if (DATA_REG_P (operands
[0]))
4949 operands
[1] = GEN_INT (logval
);
4952 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4953 operands
[1] = GEN_INT (logval
% 8);
4956 return "bset %1,%0";
4958 return "or%.l %2,%0";
4962 output_xorsi3 (rtx
*operands
)
4964 register int logval
;
4965 if (GET_CODE (operands
[2]) == CONST_INT
4966 && INTVAL (operands
[2]) >> 16 == 0
4967 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4968 && !TARGET_COLDFIRE
)
4970 if (! DATA_REG_P (operands
[0]))
4971 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4972 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4974 if (INTVAL (operands
[2]) == 0xffff)
4976 return "eor%.w %2,%0";
4978 if (GET_CODE (operands
[2]) == CONST_INT
4979 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4980 && (DATA_REG_P (operands
[0])
4981 || offsettable_memref_p (operands
[0])))
4983 if (DATA_REG_P (operands
[0]))
4984 operands
[1] = GEN_INT (logval
);
4987 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4988 operands
[1] = GEN_INT (logval
% 8);
4991 return "bchg %1,%0";
4993 return "eor%.l %2,%0";
4996 /* Return the instruction that should be used for a call to address X,
4997 which is known to be in operand 0. */
5002 if (symbolic_operand (x
, VOIDmode
))
5003 return m68k_symbolic_call
;
5008 /* Likewise sibling calls. */
5011 output_sibcall (rtx x
)
5013 if (symbolic_operand (x
, VOIDmode
))
5014 return m68k_symbolic_jump
;
5020 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5021 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5024 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5026 /* Avoid clobbering the struct value reg by using the
5027 static chain reg as a temporary. */
5028 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5030 /* Pretend to be a post-reload pass while generating rtl. */
5031 reload_completed
= 1;
5033 /* The "this" pointer is stored at 4(%sp). */
5034 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5036 /* Add DELTA to THIS. */
5039 /* Make the offset a legitimate operand for memory addition. */
5040 offset
= GEN_INT (delta
);
5041 if ((delta
< -8 || delta
> 8)
5042 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5044 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5045 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5047 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5048 copy_rtx (this_slot
), offset
));
5051 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5052 if (vcall_offset
!= 0)
5054 /* Set the static chain register to *THIS. */
5055 emit_move_insn (tmp
, this_slot
);
5056 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5058 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5059 addr
= plus_constant (tmp
, vcall_offset
);
5060 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5062 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5066 /* Load the offset into %d0 and add it to THIS. */
5067 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5068 gen_rtx_MEM (Pmode
, addr
));
5069 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5070 copy_rtx (this_slot
),
5071 gen_rtx_REG (Pmode
, D0_REG
)));
5074 /* Jump to the target function. Use a sibcall if direct jumps are
5075 allowed, otherwise load the address into a register first. */
5076 mem
= DECL_RTL (function
);
5077 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5079 gcc_assert (flag_pic
);
5081 if (!TARGET_SEP_DATA
)
5083 /* Use the static chain register as a temporary (call-clobbered)
5084 GOT pointer for this function. We can use the static chain
5085 register because it isn't live on entry to the thunk. */
5086 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5087 emit_insn (gen_load_got (pic_offset_table_rtx
));
5089 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5090 mem
= replace_equiv_address (mem
, tmp
);
5092 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5093 SIBLING_CALL_P (insn
) = 1;
5095 /* Run just enough of rest_of_compilation. */
5096 insn
= get_insns ();
5097 split_all_insns_noflow ();
5098 final_start_function (insn
, file
, 1);
5099 final (insn
, file
, 1);
5100 final_end_function ();
5102 /* Clean up the vars set above. */
5103 reload_completed
= 0;
5105 /* Restore the original PIC register. */
5107 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5110 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5113 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5114 int incoming ATTRIBUTE_UNUSED
)
5116 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5119 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5121 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5122 unsigned int new_reg
)
5125 /* Interrupt functions can only use registers that have already been
5126 saved by the prologue, even if they would normally be
5129 if ((m68k_get_function_kind (current_function_decl
)
5130 == m68k_fk_interrupt_handler
)
5131 && !df_regs_ever_live_p (new_reg
))
5137 /* Value is true if hard register REGNO can hold a value of machine-mode
5138 MODE. On the 68000, we let the cpu registers can hold any mode, but
5139 restrict the 68881 registers to floating-point modes. */
5142 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5144 if (DATA_REGNO_P (regno
))
5146 /* Data Registers, can hold aggregate if fits in. */
5147 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5150 else if (ADDRESS_REGNO_P (regno
))
5152 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5155 else if (FP_REGNO_P (regno
))
5157 /* FPU registers, hold float or complex float of long double or
5159 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5160 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5161 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5167 /* Implement SECONDARY_RELOAD_CLASS. */
5170 m68k_secondary_reload_class (enum reg_class rclass
,
5171 enum machine_mode mode
, rtx x
)
5175 regno
= true_regnum (x
);
5177 /* If one operand of a movqi is an address register, the other
5178 operand must be a general register or constant. Other types
5179 of operand must be reloaded through a data register. */
5180 if (GET_MODE_SIZE (mode
) == 1
5181 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5182 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5185 /* PC-relative addresses must be loaded into an address register first. */
5187 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5188 && symbolic_operand (x
, VOIDmode
))
5194 /* Implement PREFERRED_RELOAD_CLASS. */
5197 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5199 enum reg_class secondary_class
;
5201 /* If RCLASS might need a secondary reload, try restricting it to
5202 a class that doesn't. */
5203 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5204 if (secondary_class
!= NO_REGS
5205 && reg_class_subset_p (secondary_class
, rclass
))
5206 return secondary_class
;
5208 /* Prefer to use moveq for in-range constants. */
5209 if (GET_CODE (x
) == CONST_INT
5210 && reg_class_subset_p (DATA_REGS
, rclass
)
5211 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5214 /* ??? Do we really need this now? */
5215 if (GET_CODE (x
) == CONST_DOUBLE
5216 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5218 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5227 /* Return floating point values in a 68881 register. This makes 68881 code
5228 a little bit faster. It also makes -msoft-float code incompatible with
5229 hard-float code, so people have to be careful not to mix the two.
5230 For ColdFire it was decided the ABI incompatibility is undesirable.
5231 If there is need for a hard-float ABI it is probably worth doing it
5232 properly and also passing function arguments in FP registers. */
5234 m68k_libcall_value (enum machine_mode mode
)
5241 return gen_rtx_REG (mode
, FP0_REG
);
5247 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5250 /* Location in which function value is returned.
5251 NOTE: Due to differences in ABIs, don't call this function directly,
5252 use FUNCTION_VALUE instead. */
5254 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5256 enum machine_mode mode
;
5258 mode
= TYPE_MODE (valtype
);
5264 return gen_rtx_REG (mode
, FP0_REG
);
5270 /* If the function returns a pointer, push that into %a0. */
5271 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5272 /* For compatibility with the large body of existing code which
5273 does not always properly declare external functions returning
5274 pointer types, the m68k/SVR4 convention is to copy the value
5275 returned for pointer functions from a0 to d0 in the function
5276 epilogue, so that callers that have neglected to properly
5277 declare the callee can still find the correct return value in
5279 return gen_rtx_PARALLEL
5282 gen_rtx_EXPR_LIST (VOIDmode
,
5283 gen_rtx_REG (mode
, A0_REG
),
5285 gen_rtx_EXPR_LIST (VOIDmode
,
5286 gen_rtx_REG (mode
, D0_REG
),
5288 else if (POINTER_TYPE_P (valtype
))
5289 return gen_rtx_REG (mode
, A0_REG
);
5291 return gen_rtx_REG (mode
, D0_REG
);
5294 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5295 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5297 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5299 enum machine_mode mode
= TYPE_MODE (type
);
5301 if (mode
== BLKmode
)
5304 /* If TYPE's known alignment is less than the alignment of MODE that
5305 would contain the structure, then return in memory. We need to
5306 do so to maintain the compatibility between code compiled with
5307 -mstrict-align and that compiled with -mno-strict-align. */
5308 if (AGGREGATE_TYPE_P (type
)
5309 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5316 /* CPU to schedule the program for. */
5317 enum attr_cpu m68k_sched_cpu
;
5319 /* MAC to schedule the program for. */
5320 enum attr_mac m68k_sched_mac
;
5328 /* Integer register. */
5334 /* Implicit mem reference (e.g. stack). */
5337 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5340 /* Memory with offset but without indexing. EA mode 5. */
5343 /* Memory with indexing. EA mode 6. */
5346 /* Memory referenced by absolute address. EA mode 7. */
5349 /* Immediate operand that doesn't require extension word. */
5352 /* Immediate 16 bit operand. */
5355 /* Immediate 32 bit operand. */
5359 /* Return type of memory ADDR_RTX refers to. */
5360 static enum attr_op_type
5361 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5363 struct m68k_address address
;
5365 if (symbolic_operand (addr_rtx
, VOIDmode
))
5366 return OP_TYPE_MEM7
;
5368 if (!m68k_decompose_address (mode
, addr_rtx
,
5369 reload_completed
, &address
))
5371 gcc_assert (!reload_completed
);
5372 /* Reload will likely fix the address to be in the register. */
5373 return OP_TYPE_MEM234
;
5376 if (address
.scale
!= 0)
5377 return OP_TYPE_MEM6
;
5379 if (address
.base
!= NULL_RTX
)
5381 if (address
.offset
== NULL_RTX
)
5382 return OP_TYPE_MEM234
;
5384 return OP_TYPE_MEM5
;
5387 gcc_assert (address
.offset
!= NULL_RTX
);
5389 return OP_TYPE_MEM7
;
5392 /* Return X or Y (depending on OPX_P) operand of INSN. */
5394 sched_get_operand (rtx insn
, bool opx_p
)
5398 if (recog_memoized (insn
) < 0)
5401 extract_constrain_insn_cached (insn
);
5404 i
= get_attr_opx (insn
);
5406 i
= get_attr_opy (insn
);
5408 if (i
>= recog_data
.n_operands
)
5411 return recog_data
.operand
[i
];
5414 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5415 If ADDRESS_P is true, return type of memory location operand refers to. */
5416 static enum attr_op_type
5417 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5421 op
= sched_get_operand (insn
, opx_p
);
5425 gcc_assert (!reload_completed
);
5430 return sched_address_type (QImode
, op
);
5432 if (memory_operand (op
, VOIDmode
))
5433 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5435 if (register_operand (op
, VOIDmode
))
5437 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5438 || (reload_completed
&& FP_REG_P (op
)))
5444 if (GET_CODE (op
) == CONST_INT
)
5450 /* Check for quick constants. */
5451 switch (get_attr_type (insn
))
5454 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5455 return OP_TYPE_IMM_Q
;
5457 gcc_assert (!reload_completed
);
5461 if (USE_MOVQ (ival
))
5462 return OP_TYPE_IMM_Q
;
5464 gcc_assert (!reload_completed
);
5468 if (valid_mov3q_const (ival
))
5469 return OP_TYPE_IMM_Q
;
5471 gcc_assert (!reload_completed
);
5478 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5479 return OP_TYPE_IMM_W
;
5481 return OP_TYPE_IMM_L
;
5484 if (GET_CODE (op
) == CONST_DOUBLE
)
5486 switch (GET_MODE (op
))
5489 return OP_TYPE_IMM_W
;
5493 return OP_TYPE_IMM_L
;
5500 if (GET_CODE (op
) == CONST
5501 || symbolic_operand (op
, VOIDmode
)
5504 switch (GET_MODE (op
))
5507 return OP_TYPE_IMM_Q
;
5510 return OP_TYPE_IMM_W
;
5513 return OP_TYPE_IMM_L
;
5516 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5518 return OP_TYPE_IMM_W
;
5520 return OP_TYPE_IMM_L
;
5524 gcc_assert (!reload_completed
);
5526 if (FLOAT_MODE_P (GET_MODE (op
)))
5532 /* Implement opx_type attribute.
5533 Return type of INSN's operand X.
5534 If ADDRESS_P is true, return type of memory location operand refers to. */
5536 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5538 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5544 return OPX_TYPE_FPN
;
5547 return OPX_TYPE_MEM1
;
5549 case OP_TYPE_MEM234
:
5550 return OPX_TYPE_MEM234
;
5553 return OPX_TYPE_MEM5
;
5556 return OPX_TYPE_MEM6
;
5559 return OPX_TYPE_MEM7
;
5562 return OPX_TYPE_IMM_Q
;
5565 return OPX_TYPE_IMM_W
;
5568 return OPX_TYPE_IMM_L
;
5575 /* Implement opy_type attribute.
5576 Return type of INSN's operand Y.
5577 If ADDRESS_P is true, return type of memory location operand refers to. */
5579 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5581 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5587 return OPY_TYPE_FPN
;
5590 return OPY_TYPE_MEM1
;
5592 case OP_TYPE_MEM234
:
5593 return OPY_TYPE_MEM234
;
5596 return OPY_TYPE_MEM5
;
5599 return OPY_TYPE_MEM6
;
5602 return OPY_TYPE_MEM7
;
5605 return OPY_TYPE_IMM_Q
;
5608 return OPY_TYPE_IMM_W
;
5611 return OPY_TYPE_IMM_L
;
5618 /* Return size of INSN as int. */
5620 sched_get_attr_size_int (rtx insn
)
5624 switch (get_attr_type (insn
))
5627 /* There should be no references to m68k_sched_attr_size for 'ignore'
5641 switch (get_attr_opx_type (insn
))
5647 case OPX_TYPE_MEM234
:
5648 case OPY_TYPE_IMM_Q
:
5653 /* Here we assume that most absolute references are short. */
5655 case OPY_TYPE_IMM_W
:
5659 case OPY_TYPE_IMM_L
:
5667 switch (get_attr_opy_type (insn
))
5673 case OPY_TYPE_MEM234
:
5674 case OPY_TYPE_IMM_Q
:
5679 /* Here we assume that most absolute references are short. */
5681 case OPY_TYPE_IMM_W
:
5685 case OPY_TYPE_IMM_L
:
5695 gcc_assert (!reload_completed
);
5703 /* Return size of INSN as attribute enum value. */
5705 m68k_sched_attr_size (rtx insn
)
5707 switch (sched_get_attr_size_int (insn
))
5723 /* Return operand X or Y (depending on OPX_P) of INSN,
5724 if it is a MEM, or NULL overwise. */
5725 static enum attr_op_type
5726 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5730 switch (get_attr_opx_type (insn
))
5735 case OPX_TYPE_IMM_Q
:
5736 case OPX_TYPE_IMM_W
:
5737 case OPX_TYPE_IMM_L
:
5741 case OPX_TYPE_MEM234
:
5744 return OP_TYPE_MEM1
;
5747 return OP_TYPE_MEM6
;
5755 switch (get_attr_opy_type (insn
))
5760 case OPY_TYPE_IMM_Q
:
5761 case OPY_TYPE_IMM_W
:
5762 case OPY_TYPE_IMM_L
:
5766 case OPY_TYPE_MEM234
:
5769 return OP_TYPE_MEM1
;
5772 return OP_TYPE_MEM6
;
5780 /* Implement op_mem attribute. */
5782 m68k_sched_attr_op_mem (rtx insn
)
5784 enum attr_op_type opx
;
5785 enum attr_op_type opy
;
5787 opx
= sched_get_opxy_mem_type (insn
, true);
5788 opy
= sched_get_opxy_mem_type (insn
, false);
5790 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5793 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5795 switch (get_attr_opx_access (insn
))
5811 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5813 switch (get_attr_opx_access (insn
))
5829 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5832 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5834 switch (get_attr_opx_access (insn
))
5840 gcc_assert (!reload_completed
);
5845 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5847 switch (get_attr_opx_access (insn
))
5853 gcc_assert (!reload_completed
);
5858 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5861 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5863 switch (get_attr_opx_access (insn
))
5869 gcc_assert (!reload_completed
);
5874 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5875 gcc_assert (!reload_completed
);
5879 /* Jump instructions types. Indexed by INSN_UID.
5880 The same rtl insn can be expanded into different asm instructions
5881 depending on the cc0_status. To properly determine type of jump
5882 instructions we scan instruction stream and map jumps types to this
5884 static enum attr_type
*sched_branch_type
;
5886 /* Return the type of the jump insn. */
5888 m68k_sched_branch_type (rtx insn
)
5890 enum attr_type type
;
5892 type
= sched_branch_type
[INSN_UID (insn
)];
5894 gcc_assert (type
!= 0);
5899 /* Data for ColdFire V4 index bypass.
5900 Producer modifies register that is used as index in consumer with
5904 /* Producer instruction. */
5907 /* Consumer instruction. */
5910 /* Scale of indexed memory access within consumer.
5911 Or zero if bypass should not be effective at the moment. */
5913 } sched_cfv4_bypass_data
;
5915 /* An empty state that is used in m68k_sched_adjust_cost. */
5916 static state_t sched_adjust_cost_state
;
5918 /* Implement adjust_cost scheduler hook.
5919 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5921 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5926 if (recog_memoized (def_insn
) < 0
5927 || recog_memoized (insn
) < 0)
5930 if (sched_cfv4_bypass_data
.scale
== 1)
5931 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5933 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5934 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5935 that the data in sched_cfv4_bypass_data is up to date. */
5936 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5937 && sched_cfv4_bypass_data
.con
== insn
);
5942 sched_cfv4_bypass_data
.pro
= NULL
;
5943 sched_cfv4_bypass_data
.con
= NULL
;
5944 sched_cfv4_bypass_data
.scale
= 0;
5947 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5948 && sched_cfv4_bypass_data
.con
== NULL
5949 && sched_cfv4_bypass_data
.scale
== 0);
5951 /* Don't try to issue INSN earlier than DFA permits.
5952 This is especially useful for instructions that write to memory,
5953 as their true dependence (default) latency is better to be set to 0
5954 to workaround alias analysis limitations.
5955 This is, in fact, a machine independent tweak, so, probably,
5956 it should be moved to haifa-sched.c: insn_cost (). */
5957 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5964 /* Return maximal number of insns that can be scheduled on a single cycle. */
5966 m68k_sched_issue_rate (void)
5968 switch (m68k_sched_cpu
)
5984 /* Maximal length of instruction for current CPU.
5985 E.g. it is 3 for any ColdFire core. */
5986 static int max_insn_size
;
5988 /* Data to model instruction buffer of CPU. */
5991 /* True if instruction buffer model is modeled for current CPU. */
5994 /* Size of the instruction buffer in words. */
5997 /* Number of filled words in the instruction buffer. */
6000 /* Additional information about instruction buffer for CPUs that have
6001 a buffer of instruction records, rather then a plain buffer
6002 of instruction words. */
6003 struct _sched_ib_records
6005 /* Size of buffer in records. */
6008 /* Array to hold data on adjustements made to the size of the buffer. */
6011 /* Index of the above array. */
6015 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6019 static struct _sched_ib sched_ib
;
6021 /* ID of memory unit. */
6022 static int sched_mem_unit_code
;
6024 /* Implementation of the targetm.sched.variable_issue () hook.
6025 It is called after INSN was issued. It returns the number of insns
6026 that can possibly get scheduled on the current cycle.
6027 It is used here to determine the effect of INSN on the instruction
6030 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6031 int sched_verbose ATTRIBUTE_UNUSED
,
6032 rtx insn
, int can_issue_more
)
6036 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6038 switch (m68k_sched_cpu
)
6042 insn_size
= sched_get_attr_size_int (insn
);
6046 insn_size
= sched_get_attr_size_int (insn
);
6048 /* ColdFire V3 and V4 cores have instruction buffers that can
6049 accumulate up to 8 instructions regardless of instructions'
6050 sizes. So we should take care not to "prefetch" 24 one-word
6051 or 12 two-words instructions.
6052 To model this behavior we temporarily decrease size of the
6053 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6057 adjust
= max_insn_size
- insn_size
;
6058 sched_ib
.size
-= adjust
;
6060 if (sched_ib
.filled
> sched_ib
.size
)
6061 sched_ib
.filled
= sched_ib
.size
;
6063 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6066 ++sched_ib
.records
.adjust_index
;
6067 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6068 sched_ib
.records
.adjust_index
= 0;
6070 /* Undo adjustement we did 7 instructions ago. */
6072 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6077 gcc_assert (!sched_ib
.enabled_p
);
6085 if (insn_size
> sched_ib
.filled
)
6086 /* Scheduling for register pressure does not always take DFA into
6087 account. Workaround instruction buffer not being filled enough. */
6089 gcc_assert (sched_pressure_p
);
6090 insn_size
= sched_ib
.filled
;
6095 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6096 || asm_noperands (PATTERN (insn
)) >= 0)
6097 insn_size
= sched_ib
.filled
;
6101 sched_ib
.filled
-= insn_size
;
6103 return can_issue_more
;
6106 /* Return how many instructions should scheduler lookahead to choose the
6109 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6111 return m68k_sched_issue_rate () - 1;
6114 /* Implementation of targetm.sched.init_global () hook.
6115 It is invoked once per scheduling pass and is used here
6116 to initialize scheduler constants. */
6118 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6119 int sched_verbose ATTRIBUTE_UNUSED
,
6120 int n_insns ATTRIBUTE_UNUSED
)
6122 /* Init branch types. */
6126 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6128 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6131 /* !!! FIXME: Implement real scan here. */
6132 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6136 #ifdef ENABLE_CHECKING
6137 /* Check that all instructions have DFA reservations and
6138 that all instructions can be issued from a clean state. */
6143 state
= alloca (state_size ());
6145 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6147 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6149 gcc_assert (insn_has_dfa_reservation_p (insn
));
6151 state_reset (state
);
6152 if (state_transition (state
, insn
) >= 0)
6159 /* Setup target cpu. */
6161 /* ColdFire V4 has a set of features to keep its instruction buffer full
6162 (e.g., a separate memory bus for instructions) and, hence, we do not model
6163 buffer for this CPU. */
6164 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6166 switch (m68k_sched_cpu
)
6169 sched_ib
.filled
= 0;
6176 sched_ib
.records
.n_insns
= 0;
6177 sched_ib
.records
.adjust
= NULL
;
6182 sched_ib
.records
.n_insns
= 8;
6183 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6190 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6192 sched_adjust_cost_state
= xmalloc (state_size ());
6193 state_reset (sched_adjust_cost_state
);
6196 emit_insn (gen_ib ());
6197 sched_ib
.insn
= get_insns ();
6201 /* Scheduling pass is now finished. Free/reset static variables. */
6203 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6204 int verbose ATTRIBUTE_UNUSED
)
6206 sched_ib
.insn
= NULL
;
6208 free (sched_adjust_cost_state
);
6209 sched_adjust_cost_state
= NULL
;
6211 sched_mem_unit_code
= 0;
6213 free (sched_ib
.records
.adjust
);
6214 sched_ib
.records
.adjust
= NULL
;
6215 sched_ib
.records
.n_insns
= 0;
6218 free (sched_branch_type
);
6219 sched_branch_type
= NULL
;
6222 /* Implementation of targetm.sched.init () hook.
6223 It is invoked each time scheduler starts on the new block (basic block or
6224 extended basic block). */
6226 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6227 int sched_verbose ATTRIBUTE_UNUSED
,
6228 int n_insns ATTRIBUTE_UNUSED
)
6230 switch (m68k_sched_cpu
)
6238 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6240 memset (sched_ib
.records
.adjust
, 0,
6241 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6242 sched_ib
.records
.adjust_index
= 0;
6246 gcc_assert (!sched_ib
.enabled_p
);
6254 if (sched_ib
.enabled_p
)
6255 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6256 the first cycle. Workaround that. */
6257 sched_ib
.filled
= -2;
6260 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6261 It is invoked just before current cycle finishes and is used here
6262 to track if instruction buffer got its two words this cycle. */
6264 m68k_sched_dfa_pre_advance_cycle (void)
6266 if (!sched_ib
.enabled_p
)
6269 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6271 sched_ib
.filled
+= 2;
6273 if (sched_ib
.filled
> sched_ib
.size
)
6274 sched_ib
.filled
= sched_ib
.size
;
6278 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6279 It is invoked just after new cycle begins and is used here
6280 to setup number of filled words in the instruction buffer so that
6281 instructions which won't have all their words prefetched would be
6282 stalled for a cycle. */
6284 m68k_sched_dfa_post_advance_cycle (void)
6288 if (!sched_ib
.enabled_p
)
6291 /* Setup number of prefetched instruction words in the instruction
6293 i
= max_insn_size
- sched_ib
.filled
;
6297 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6302 /* Return X or Y (depending on OPX_P) operand of INSN,
6303 if it is an integer register, or NULL overwise. */
6305 sched_get_reg_operand (rtx insn
, bool opx_p
)
6311 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6313 op
= sched_get_operand (insn
, true);
6314 gcc_assert (op
!= NULL
);
6316 if (!reload_completed
&& !REG_P (op
))
6322 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6324 op
= sched_get_operand (insn
, false);
6325 gcc_assert (op
!= NULL
);
6327 if (!reload_completed
&& !REG_P (op
))
6335 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6338 sched_mem_operand_p (rtx insn
, bool opx_p
)
6340 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6351 /* Return X or Y (depending on OPX_P) operand of INSN,
6352 if it is a MEM, or NULL overwise. */
6354 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6374 if (opy_p
&& sched_mem_operand_p (insn
, false))
6375 return sched_get_operand (insn
, false);
6377 if (opx_p
&& sched_mem_operand_p (insn
, true))
6378 return sched_get_operand (insn
, true);
6384 /* Return non-zero if PRO modifies register used as part of
6387 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6392 pro_x
= sched_get_reg_operand (pro
, true);
6396 con_mem_read
= sched_get_mem_operand (con
, true, false);
6397 gcc_assert (con_mem_read
!= NULL
);
6399 if (reg_mentioned_p (pro_x
, con_mem_read
))
6405 /* Helper function for m68k_sched_indexed_address_bypass_p.
6406 if PRO modifies register used as index in CON,
6407 return scale of indexed memory access in CON. Return zero overwise. */
6409 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6413 struct m68k_address address
;
6415 reg
= sched_get_reg_operand (pro
, true);
6419 mem
= sched_get_mem_operand (con
, true, false);
6420 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6422 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6426 if (REGNO (reg
) == REGNO (address
.index
))
6428 gcc_assert (address
.scale
!= 0);
6429 return address
.scale
;
6435 /* Return non-zero if PRO modifies register used
6436 as index with scale 2 or 4 in CON. */
6438 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6440 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6441 && sched_cfv4_bypass_data
.con
== NULL
6442 && sched_cfv4_bypass_data
.scale
== 0);
6444 switch (sched_get_indexed_address_scale (pro
, con
))
6447 /* We can't have a variable latency bypass, so
6448 remember to adjust the insn cost in adjust_cost hook. */
6449 sched_cfv4_bypass_data
.pro
= pro
;
6450 sched_cfv4_bypass_data
.con
= con
;
6451 sched_cfv4_bypass_data
.scale
= 1;
6463 /* We generate a two-instructions program at M_TRAMP :
6464 movea.l &CHAIN_VALUE,%a0
6466 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6469 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6471 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6474 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6476 mem
= adjust_address (m_tramp
, HImode
, 0);
6477 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6478 mem
= adjust_address (m_tramp
, SImode
, 2);
6479 emit_move_insn (mem
, chain_value
);
6481 mem
= adjust_address (m_tramp
, HImode
, 6);
6482 emit_move_insn (mem
, GEN_INT(0x4EF9));
6483 mem
= adjust_address (m_tramp
, SImode
, 8);
6484 emit_move_insn (mem
, fnaddr
);
6486 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6489 /* On the 68000, the RTS insn cannot pop anything.
6490 On the 68010, the RTD insn may be used to pop them if the number
6491 of args is fixed, but if the number is variable then the caller
6492 must pop them all. RTD can't be used for library calls now
6493 because the library is compiled with the Unix compiler.
6494 Use of RTD is a selectable option, since it is incompatible with
6495 standard Unix calling sequences. If the option is not selected,
6496 the caller must always pop the args. */
6499 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6503 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6504 && (!stdarg_p (funtype
)))
6508 /* Make sure everything's fine if we *don't* have a given processor.
6509 This assumes that putting a register in fixed_regs will keep the
6510 compiler's mitts completely off it. We don't bother to zero it out
6511 of register classes. */
6514 m68k_conditional_register_usage (void)
6518 if (!TARGET_HARD_FLOAT
)
6520 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6521 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6522 if (TEST_HARD_REG_BIT (x
, i
))
6523 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6526 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6530 m68k_init_sync_libfuncs (void)
6532 init_sync_libfuncs (UNITS_PER_WORD
);
6535 #include "gt-m68k.h"