1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
24 [(set (match_operand:QI 0 "mra_or_sp_operand"
25 "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
26 (plus:QI (match_operand:QI 1 "mra_operand"
28 (match_operand:QI 2 "mrai_operand"
29 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
32 [(set_attr "flags" "oszc")]
36 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
37 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
38 (plus:HI (match_operand:HI 1 "m32c_any_operand"
39 "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
40 (match_operand:HI 2 "m32c_any_operand"
41 "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
54 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
57 (define_insn "addpsi3"
58 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
59 (plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
60 (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
70 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
73 (define_expand "addsi3"
74 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
75 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
76 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
77 "TARGET_A24 ||TARGET_A16"
81 (define_insn "addsi3_1"
82 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
83 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
84 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
88 switch (which_alternative)
91 return \"add.w %X2,%h0\;adcf.w %H0\";
93 return \"add.w %X2,%h0\;adcf.w %H0\";
95 if (GET_CODE (operands[2]) == SYMBOL_REF)
97 output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
98 return \"adc.w #%%hi(%d2),%H0\";
102 output_asm_insn (\"add.w %X2,%h0\",operands);
103 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
104 return \"adc.w %X2,%H0\";
107 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
109 output_asm_insn (\"add.w %X2,%h0\",operands);
110 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
111 return \"adc.w %X2,%H0\";
113 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
115 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
117 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
121 [(set_attr "flags" "x,x,x,x,x,x,x,x")]
124 (define_insn "addsi3_2"
125 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
126 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
127 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
130 [(set_attr "flags" "oszc")]
133 (define_insn "subqi3"
134 [(set (match_operand:QI 0 "mra_or_sp_operand"
135 "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
136 (minus:QI (match_operand:QI 1 "mra_operand"
137 "0,0,0,0, 0,0,0,0, 0")
138 (match_operand:QI 2 "mrai_operand"
139 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
142 [(set_attr "flags" "oszc")]
145 (define_insn "subhi3"
146 [(set (match_operand:HI 0 "mra_operand"
147 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
148 (minus:HI (match_operand:HI 1 "mras_operand"
150 (match_operand:HI 2 "mrai_operand"
151 "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
160 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
163 (define_insn "subpsi3"
164 [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
165 (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
166 (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
169 [(set_attr "flags" "oszc")]
172 (define_expand "subsi3"
173 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
174 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
175 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
176 "TARGET_A24 ||TARGET_A16"
180 (define_insn "subsi3_1"
181 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
182 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
183 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
186 switch (which_alternative)
189 output_asm_insn (\"sub.w %X2,%h0\",operands);
190 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
191 return \"sbb.w %X2,%H0\";
193 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
195 output_asm_insn (\"sub.w %X2,%h0\",operands);
196 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
197 return \"sbb.w %X2,%H0\";
199 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
201 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
203 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
207 [(set_attr "flags" "x,x,x,x,x,x")]
210 (define_insn "subsi3_2"
211 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
212 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
213 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
216 [(set_attr "flags" "oszc,oszc,oszc,oszc")]
219 (define_insn "negqi2"
220 [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
221 (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
224 [(set_attr "flags" "oszc,oszc")]
227 (define_insn "neghi2"
228 [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
229 (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
232 [(set_attr "flags" "oszc,oszc")]
235 ; We can negate an SImode by operating on the subparts. GCC deals
236 ; with this itself for larger modes, but not SI.
237 (define_insn "negsi2"
238 [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
239 (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
241 "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
242 [(set_attr "flags" "x")]
245 (define_insn "absqi2"
246 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
247 (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
250 [(set_attr "flags" "oszc")]
253 (define_insn "abshi2"
254 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
255 (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
258 [(set_attr "flags" "oszc")]