1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; -------------------------------------------------------------------
23 ;; -------------------------------------------------------------------
26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27 (define_mode_iterator GPI [SI DI])
29 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
32 ;; Iterator for QI and HI modes
33 (define_mode_iterator SHORT [QI HI])
35 ;; Iterator for all integer modes (up to 64-bit)
36 (define_mode_iterator ALLI [QI HI SI DI])
38 ;; Iterator for all integer modes that can be extended (up to 64-bit)
39 (define_mode_iterator ALLX [QI HI SI])
41 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42 (define_mode_iterator GPF [SF DF])
44 ;; Iterator for all scalar floating point modes (HF, SF, DF)
45 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
47 ;; Iterator for all scalar floating point modes (HF, SF, DF)
48 (define_mode_iterator GPF_HF [HF SF DF])
50 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
53 ;; Double vector modes.
54 (define_mode_iterator VDF [V2SF V4HF])
56 ;; Iterator for all scalar floating point modes (SF, DF and TF)
57 (define_mode_iterator GPF_TF [SF DF TF])
59 ;; Integer vector modes.
60 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
62 ;; vector and scalar, 64 & 128-bit container, all integer modes
63 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
65 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
66 ;; 64-bit scalar integer mode
67 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
69 ;; Double vector modes.
70 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
72 ;; vector, 64-bit container, all integer modes
73 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
75 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
76 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
79 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
81 ;; VQ without 2 element modes.
82 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
84 ;; Quad vector with only 2 element modes.
85 (define_mode_iterator VQ_2E [V2DI V2DF])
87 ;; This mode iterator allows :P to be used for patterns that operate on
88 ;; addresses in different modes. In LP64, only DI will match, while in
89 ;; ILP32, either can match.
90 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
91 (DI "ptr_mode == DImode || Pmode == DImode")])
93 ;; This mode iterator allows :PTR to be used for patterns that operate on
94 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
95 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
97 ;; Vector Float modes suitable for moving, loading and storing.
98 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
100 ;; Vector Float modes.
101 (define_mode_iterator VDQF [V2SF V4SF V2DF])
102 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
103 (V8HF "TARGET_SIMD_F16INST")
106 ;; Vector Float modes, and DF.
107 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
108 (V8HF "TARGET_SIMD_F16INST")
110 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
111 (V8HF "TARGET_SIMD_F16INST")
113 (HF "TARGET_SIMD_F16INST")
116 ;; Vector single Float modes.
117 (define_mode_iterator VDQSF [V2SF V4SF])
119 ;; Quad vector Float modes with half/single elements.
120 (define_mode_iterator VQ_HSF [V8HF V4SF])
122 ;; Modes suitable to use as the return type of a vcond expression.
123 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
126 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
128 ;; Vector Float modes with 2 elements.
129 (define_mode_iterator V2F [V2SF V2DF])
131 ;; All vector modes on which we support any arithmetic operations.
132 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
134 ;; All vector modes suitable for moving, loading, and storing.
135 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
136 V4HF V8HF V2SF V4SF V2DF])
138 ;; The VALL_F16 modes except the 128-bit 2-element ones.
139 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
140 V4HF V8HF V2SF V4SF])
142 ;; All vector modes barring HF modes, plus DI.
143 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
145 ;; All vector modes and DI.
146 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
147 V4HF V8HF V2SF V4SF V2DF DI])
149 ;; All vector modes, plus DI and DF.
150 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
151 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
153 ;; Vector modes for Integer reduction across lanes.
154 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
156 ;; Vector modes(except V2DI) for Integer reduction across lanes.
157 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
159 ;; All double integer narrow-able modes.
160 (define_mode_iterator VDN [V4HI V2SI DI])
162 ;; All quad integer narrow-able modes.
163 (define_mode_iterator VQN [V8HI V4SI V2DI])
165 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
166 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
168 ;; All quad integer widen-able modes.
169 (define_mode_iterator VQW [V16QI V8HI V4SI])
171 ;; Double vector modes for combines.
172 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
174 ;; Vector modes except double int.
175 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
176 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
177 V4HF V8HF V2SF V4SF V2DF])
179 ;; Vector modes for S type.
180 (define_mode_iterator VDQ_SI [V2SI V4SI])
182 ;; Vector modes for S and D
183 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
185 ;; Vector modes for H, S and D
186 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
187 (V8HI "TARGET_SIMD_F16INST")
190 ;; Scalar and Vector modes for S and D
191 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
193 ;; Scalar and Vector modes for S and D, Vector modes for H.
194 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
195 (V8HI "TARGET_SIMD_F16INST")
197 (HI "TARGET_SIMD_F16INST")
200 ;; Vector modes for Q and H types.
201 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
203 ;; Vector modes for H and S types.
204 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
206 ;; Vector modes for H, S and D types.
207 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
209 ;; Vector and scalar integer modes for H and S
210 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
212 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
213 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
215 ;; Vector 64-bit container: 16, 32-bit integer modes
216 (define_mode_iterator VD_HSI [V4HI V2SI])
218 ;; Scalar 64-bit container: 16, 32-bit integer modes
219 (define_mode_iterator SD_HSI [HI SI])
221 ;; Vector 64-bit container: 16, 32-bit integer modes
222 (define_mode_iterator VQ_HSI [V8HI V4SI])
225 (define_mode_iterator VB [V8QI V16QI])
227 ;; 2 and 4 lane SI modes.
228 (define_mode_iterator VS [V2SI V4SI])
230 (define_mode_iterator TX [TI TF])
232 ;; Opaque structure modes.
233 (define_mode_iterator VSTRUCT [OI CI XI])
235 ;; Double scalar modes
236 (define_mode_iterator DX [DI DF])
238 ;; Modes available for <f>mul lane operations.
239 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
240 (V4HF "TARGET_SIMD_F16INST")
241 (V8HF "TARGET_SIMD_F16INST")
244 ;; Modes available for <f>mul lane operations changing lane count.
245 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
247 ;; ------------------------------------------------------------------
248 ;; Unspec enumerations for Advance SIMD. These could well go into
249 ;; aarch64.md but for their use in int_iterators here.
250 ;; ------------------------------------------------------------------
252 (define_c_enum "unspec"
254 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
255 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
256 UNSPEC_ABS ; Used in aarch64-simd.md.
257 UNSPEC_FMAX ; Used in aarch64-simd.md.
258 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
259 UNSPEC_FMAXV ; Used in aarch64-simd.md.
260 UNSPEC_FMIN ; Used in aarch64-simd.md.
261 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
262 UNSPEC_FMINV ; Used in aarch64-simd.md.
263 UNSPEC_FADDV ; Used in aarch64-simd.md.
264 UNSPEC_ADDV ; Used in aarch64-simd.md.
265 UNSPEC_SMAXV ; Used in aarch64-simd.md.
266 UNSPEC_SMINV ; Used in aarch64-simd.md.
267 UNSPEC_UMAXV ; Used in aarch64-simd.md.
268 UNSPEC_UMINV ; Used in aarch64-simd.md.
269 UNSPEC_SHADD ; Used in aarch64-simd.md.
270 UNSPEC_UHADD ; Used in aarch64-simd.md.
271 UNSPEC_SRHADD ; Used in aarch64-simd.md.
272 UNSPEC_URHADD ; Used in aarch64-simd.md.
273 UNSPEC_SHSUB ; Used in aarch64-simd.md.
274 UNSPEC_UHSUB ; Used in aarch64-simd.md.
275 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
276 UNSPEC_URHSUB ; Used in aarch64-simd.md.
277 UNSPEC_ADDHN ; Used in aarch64-simd.md.
278 UNSPEC_RADDHN ; Used in aarch64-simd.md.
279 UNSPEC_SUBHN ; Used in aarch64-simd.md.
280 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
281 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
282 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
283 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
284 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
285 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
286 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
287 UNSPEC_PMUL ; Used in aarch64-simd.md.
288 UNSPEC_FMULX ; Used in aarch64-simd.md.
289 UNSPEC_USQADD ; Used in aarch64-simd.md.
290 UNSPEC_SUQADD ; Used in aarch64-simd.md.
291 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
292 UNSPEC_SQXTN ; Used in aarch64-simd.md.
293 UNSPEC_UQXTN ; Used in aarch64-simd.md.
294 UNSPEC_SSRA ; Used in aarch64-simd.md.
295 UNSPEC_USRA ; Used in aarch64-simd.md.
296 UNSPEC_SRSRA ; Used in aarch64-simd.md.
297 UNSPEC_URSRA ; Used in aarch64-simd.md.
298 UNSPEC_SRSHR ; Used in aarch64-simd.md.
299 UNSPEC_URSHR ; Used in aarch64-simd.md.
300 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
301 UNSPEC_SQSHL ; Used in aarch64-simd.md.
302 UNSPEC_UQSHL ; Used in aarch64-simd.md.
303 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
304 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
305 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
306 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
307 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
308 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
309 UNSPEC_SSHL ; Used in aarch64-simd.md.
310 UNSPEC_USHL ; Used in aarch64-simd.md.
311 UNSPEC_SRSHL ; Used in aarch64-simd.md.
312 UNSPEC_URSHL ; Used in aarch64-simd.md.
313 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
314 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
315 UNSPEC_SSLI ; Used in aarch64-simd.md.
316 UNSPEC_USLI ; Used in aarch64-simd.md.
317 UNSPEC_SSRI ; Used in aarch64-simd.md.
318 UNSPEC_USRI ; Used in aarch64-simd.md.
319 UNSPEC_SSHLL ; Used in aarch64-simd.md.
320 UNSPEC_USHLL ; Used in aarch64-simd.md.
321 UNSPEC_ADDP ; Used in aarch64-simd.md.
322 UNSPEC_TBL ; Used in vector permute patterns.
323 UNSPEC_TBX ; Used in vector permute patterns.
324 UNSPEC_CONCAT ; Used in vector permute patterns.
325 UNSPEC_ZIP1 ; Used in vector permute patterns.
326 UNSPEC_ZIP2 ; Used in vector permute patterns.
327 UNSPEC_UZP1 ; Used in vector permute patterns.
328 UNSPEC_UZP2 ; Used in vector permute patterns.
329 UNSPEC_TRN1 ; Used in vector permute patterns.
330 UNSPEC_TRN2 ; Used in vector permute patterns.
331 UNSPEC_EXT ; Used in aarch64-simd.md.
332 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
333 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
334 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
335 UNSPEC_AESE ; Used in aarch64-simd.md.
336 UNSPEC_AESD ; Used in aarch64-simd.md.
337 UNSPEC_AESMC ; Used in aarch64-simd.md.
338 UNSPEC_AESIMC ; Used in aarch64-simd.md.
339 UNSPEC_SHA1C ; Used in aarch64-simd.md.
340 UNSPEC_SHA1M ; Used in aarch64-simd.md.
341 UNSPEC_SHA1P ; Used in aarch64-simd.md.
342 UNSPEC_SHA1H ; Used in aarch64-simd.md.
343 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
344 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
345 UNSPEC_SHA256H ; Used in aarch64-simd.md.
346 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
347 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
348 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
349 UNSPEC_PMULL ; Used in aarch64-simd.md.
350 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
351 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
352 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
353 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
354 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
355 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
356 UNSPEC_FMINNM ; Used in aarch64-simd.md.
359 ;; ------------------------------------------------------------------
360 ;; Unspec enumerations for Atomics. They are here so that they can be
361 ;; used in the int_iterators for atomic operations.
362 ;; ------------------------------------------------------------------
364 (define_c_enum "unspecv"
366 UNSPECV_LX ; Represent a load-exclusive.
367 UNSPECV_SX ; Represent a store-exclusive.
368 UNSPECV_LDA ; Represent an atomic load or load-acquire.
369 UNSPECV_STL ; Represent an atomic store or store-release.
370 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
371 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
372 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
373 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
374 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
375 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
376 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
377 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
378 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
379 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
382 ;; -------------------------------------------------------------------
384 ;; -------------------------------------------------------------------
386 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
387 ;; 32-bit version and "%x0" in the 64-bit version.
388 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
390 ;; For inequal width int to float conversion
391 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
392 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
394 (define_mode_attr short_mask [(HI "65535") (QI "255")])
396 ;; For constraints used in scalar immediate vector moves
397 (define_mode_attr hq [(HI "h") (QI "q")])
399 ;; For doubling width of an integer mode
400 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
402 ;; For scalar usage of vector/FP registers
403 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
404 (HF "h") (SF "s") (DF "d")
410 (V8HF "") (V2DF "")])
412 ;; For scalar usage of vector/FP registers, narrowing
413 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
418 (V4SF "") (V2DF "")])
420 ;; For scalar usage of vector/FP registers, widening
421 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
426 (V4SF "") (V2DF "")])
428 ;; Register Type Name and Vector Arrangement Specifier for when
429 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
431 (define_mode_attr rtn [(DI "d") (SI "")])
432 (define_mode_attr vas [(DI "") (SI ".2s")])
434 ;; Map a floating point mode to the appropriate register name prefix
435 (define_mode_attr s [(HF "h") (SF "s") (DF "d")])
437 ;; Give the length suffix letter for a sign- or zero-extension.
438 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
440 ;; Give the number of bits in the mode
441 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
443 ;; Give the ordinal of the MSB in the mode
444 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
446 ;; Attribute to describe constants acceptable in logical operations
447 (define_mode_attr lconst [(SI "K") (DI "L")])
449 ;; Attribute to describe constants acceptable in logical and operations
450 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
452 ;; Map a mode to a specific constraint character.
453 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
455 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
456 (V4HI "4h") (V8HI "8h")
457 (V2SI "2s") (V4SI "4s")
459 (V2DI "2d") (V2SF "2s")
460 (V4SF "4s") (V2DF "2d")
461 (V4HF "4h") (V8HF "8h")])
463 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
464 (V4SI "32") (V2DI "64")])
466 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
467 (V4HI ".4h") (V8HI ".8h")
468 (V2SI ".2s") (V4SI ".4s")
469 (V2DI ".2d") (V4HF ".4h")
470 (V8HF ".8h") (V2SF ".2s")
471 (V4SF ".4s") (V2DF ".2d")
477 ;; Register suffix narrowed modes for VQN.
478 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
483 ;; Mode-to-individual element type mapping.
484 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
485 (V4HI "h") (V8HI "h")
486 (V2SI "s") (V4SI "s")
487 (V2DI "d") (V4HF "h")
488 (V8HF "h") (V2SF "s")
489 (V4SF "s") (V2DF "d")
495 ;; Vetype is used everywhere in scheduling type and assembly output,
496 ;; sometimes they are not the same, for example HF modes on some
497 ;; instructions. stype is defined to represent scheduling type
499 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
500 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
501 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
502 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
505 ;; Mode-to-bitwise operation type mapping.
506 (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
507 (V4HI "8b") (V8HI "16b")
508 (V2SI "8b") (V4SI "16b")
509 (V2DI "16b") (V4HF "8b")
510 (V8HF "16b") (V2SF "8b")
511 (V4SF "16b") (V2DF "16b")
515 ;; Define element mode for each vector mode.
516 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
517 (V4HI "HI") (V8HI "HI")
518 (V2SI "SI") (V4SI "SI")
519 (DI "DI") (V2DI "DI")
520 (V4HF "HF") (V8HF "HF")
521 (V2SF "SF") (V4SF "SF")
522 (V2DF "DF") (DF "DF")
526 ;; Define element mode for each vector mode (lower case).
527 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
528 (V4HI "hi") (V8HI "hi")
529 (V2SI "si") (V4SI "si")
530 (DI "di") (V2DI "di")
531 (V4HF "hf") (V8HF "hf")
532 (V2SF "sf") (V4SF "sf")
533 (V2DF "df") (DF "df")
537 ;; 64-bit container modes the inner or scalar source mode.
538 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
539 (V4HI "V4HI") (V8HI "V4HI")
540 (V2SI "V2SI") (V4SI "V2SI")
541 (DI "DI") (V2DI "DI")
542 (V2SF "V2SF") (V4SF "V2SF")
545 ;; 128-bit container modes the inner or scalar source mode.
546 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
547 (V4HI "V8HI") (V8HI "V8HI")
548 (V2SI "V4SI") (V4SI "V4SI")
549 (DI "V2DI") (V2DI "V2DI")
550 (V4HF "V8HF") (V8HF "V8HF")
551 (V2SF "V2SF") (V4SF "V4SF")
552 (V2DF "V2DF") (SI "V4SI")
553 (HI "V8HI") (QI "V16QI")])
555 ;; Half modes of all vector modes.
556 (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
557 (V4HI "V2HI") (V8HI "V4HI")
558 (V2SI "SI") (V4SI "V2SI")
559 (V2DI "DI") (V2SF "SF")
560 (V4SF "V2SF") (V4HF "V2HF")
561 (V8HF "V4HF") (V2DF "DF")])
563 ;; Half modes of all vector modes, in lower-case.
564 (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
565 (V4HI "v2hi") (V8HI "v4hi")
566 (V2SI "si") (V4SI "v2si")
567 (V2DI "di") (V2SF "sf")
568 (V4SF "v2sf") (V2DF "df")])
570 ;; Double modes of vector modes.
571 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
573 (V2SI "V4SI") (V2SF "V4SF")
574 (SI "V2SI") (DI "V2DI")
577 ;; Register suffix for double-length mode.
578 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
580 ;; Double modes of vector modes (lower case).
581 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
583 (V2SI "v4si") (V2SF "v4sf")
584 (SI "v2si") (DI "v2di")
587 ;; Modes with double-width elements.
588 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
589 (V4HI "V2SI") (V8HI "V4SI")
590 (V2SI "DI") (V4SI "V2DI")])
592 ;; Narrowed modes for VDN.
593 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
596 ;; Narrowed double-modes for VQN (Used for XTN).
597 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
602 ;; Narrowed quad-modes for VQN (Used for XTN2).
603 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
606 ;; Register suffix narrowed modes for VQN.
607 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
610 ;; Register suffix narrowed modes for VQN.
611 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
614 ;; Widened modes of vector modes.
615 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
616 (V2SI "V2DI") (V16QI "V8HI")
617 (V8HI "V4SI") (V4SI "V2DI")
619 (V8HF "V4SF") (V4SF "V2DF")
620 (V4HF "V4SF") (V2SF "V2DF")]
623 ;; Widened modes of vector modes, lowercase
624 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
626 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
627 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
628 (V2SI "2d") (V16QI "8h")
629 (V8HI "4s") (V4SI "2d")
630 (V8HF "4s") (V4SF "2d")])
632 ;; Widened mode register suffixes for VDW/VQW.
633 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
634 (V2SI ".2d") (V16QI ".8h")
635 (V8HI ".4s") (V4SI ".2d")
636 (V4HF ".4s") (V2SF ".2d")
639 ;; Lower part register suffixes for VQW/VQ_HSF.
640 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
641 (V4SI "2s") (V8HF "4h")
644 ;; Define corresponding core/FP element mode for each vector mode.
645 (define_mode_attr vw [(V8QI "w") (V16QI "w")
646 (V4HI "w") (V8HI "w")
647 (V2SI "w") (V4SI "w")
649 (V2SF "s") (V4SF "s")
652 ;; Corresponding core element mode for each vector mode. This is a
653 ;; variation on <vw> mapping FP modes to GP regs.
654 (define_mode_attr vwcore [(V8QI "w") (V16QI "w")
655 (V4HI "w") (V8HI "w")
656 (V2SI "w") (V4SI "w")
658 (V4HF "w") (V8HF "w")
659 (V2SF "w") (V4SF "w")
662 ;; Double vector types for ALLX.
663 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
665 ;; Mode with floating-point values replaced by like-sized integers.
666 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
667 (V4HI "V4HI") (V8HI "V8HI")
668 (V2SI "V2SI") (V4SI "V4SI")
669 (DI "DI") (V2DI "V2DI")
670 (V4HF "V4HI") (V8HF "V8HI")
671 (V2SF "V2SI") (V4SF "V4SI")
672 (V2DF "V2DI") (DF "DI")
673 (SF "SI") (HF "HI")])
675 ;; Lower case mode with floating-point values replaced by like-sized integers.
676 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
677 (V4HI "v4hi") (V8HI "v8hi")
678 (V2SI "v2si") (V4SI "v4si")
679 (DI "di") (V2DI "v2di")
680 (V4HF "v4hi") (V8HF "v8hi")
681 (V2SF "v2si") (V4SF "v4si")
682 (V2DF "v2di") (DF "di")
685 ;; Mode for vector conditional operations where the comparison has
686 ;; different type from the lhs.
687 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
688 (V2DI "V2DF") (V2SF "V2SI")
689 (V4SF "V4SI") (V2DF "V2DI")])
691 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
692 (V2DI "v2df") (V2SF "v2si")
693 (V4SF "v4si") (V2DF "v2di")])
695 ;; Lower case element modes (as used in shift immediate patterns).
696 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
697 (V4HI "hi") (V8HI "hi")
698 (V2SI "si") (V4SI "si")
699 (DI "di") (V2DI "di")
703 ;; Vm for lane instructions is restricted to FP_LO_REGS.
704 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
705 (V2SI "w") (V4SI "w") (SI "w")])
707 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
709 ;; This is both the number of Q-Registers needed to hold the corresponding
710 ;; opaque large integer mode, and the number of elements touched by the
711 ;; ld..._lane and st..._lane operations.
712 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
714 ;; Mode for atomic operation suffixes
715 (define_mode_attr atomic_sfx
716 [(QI "b") (HI "h") (SI "") (DI "")])
718 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
719 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
720 (SF "si") (DF "di") (SI "sf") (DI "df")
721 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
722 (V8HI "v8hf") (HF "hi") (HI "hf")])
723 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
724 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
725 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
726 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
727 (V8HI "V8HF") (HF "HI") (HI "HF")])
730 ;; for the inequal width integer to fp conversions
731 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
732 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
734 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
735 (V4HI "V8HI") (V8HI "V4HI")
736 (V2SI "V4SI") (V4SI "V2SI")
737 (DI "V2DI") (V2DI "DI")
738 (V2SF "V4SF") (V4SF "V2SF")
739 (V4HF "V8HF") (V8HF "V4HF")
740 (DF "V2DF") (V2DF "DF")])
742 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
743 (V4HI "to_128") (V8HI "to_64")
744 (V2SI "to_128") (V4SI "to_64")
745 (DI "to_128") (V2DI "to_64")
746 (V4HF "to_128") (V8HF "to_64")
747 (V2SF "to_128") (V4SF "to_64")
748 (DF "to_128") (V2DF "to_64")])
750 ;; For certain vector-by-element multiplication instructions we must
751 ;; constrain the 16-bit cases to use only V0-V15. This is covered by
752 ;; the 'x' constraint. All other modes may use the 'w' constraint.
753 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
754 (V4HI "x") (V8HI "x")
755 (V4HF "x") (V8HF "x")
756 (V2SF "w") (V4SF "w")
757 (V2DF "w") (DF "w")])
759 ;; Defined to 'f' for types whose element type is a float type.
760 (define_mode_attr f [(V8QI "") (V16QI "")
764 (V4HF "f") (V8HF "f")
765 (V2SF "f") (V4SF "f")
766 (V2DF "f") (DF "f")])
768 ;; Defined to '_fp' for types whose element type is a float type.
769 (define_mode_attr fp [(V8QI "") (V16QI "")
773 (V4HF "_fp") (V8HF "_fp")
774 (V2SF "_fp") (V4SF "_fp")
775 (V2DF "_fp") (DF "_fp")
778 ;; Defined to '_q' for 128-bit types.
779 (define_mode_attr q [(V8QI "") (V16QI "_q")
780 (V4HI "") (V8HI "_q")
781 (V2SI "") (V4SI "_q")
783 (V4HF "") (V8HF "_q")
784 (V2SF "") (V4SF "_q")
786 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
788 (define_mode_attr vp [(V8QI "v") (V16QI "v")
789 (V4HI "v") (V8HI "v")
790 (V2SI "p") (V4SI "v")
791 (V2DI "p") (V2DF "p")
792 (V2SF "p") (V4SF "v")
793 (V4HF "v") (V8HF "v")])
795 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
796 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
798 ;; Sum of lengths of instructions needed to move vector registers of a mode.
799 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
801 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
802 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
803 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
805 ;; -------------------------------------------------------------------
807 ;; -------------------------------------------------------------------
809 ;; This code iterator allows the various shifts supported on the core
810 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
812 ;; This code iterator allows the shifts supported in arithmetic instructions
813 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
815 ;; Code iterator for logical operations
816 (define_code_iterator LOGICAL [and ior xor])
818 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
819 (define_code_iterator NLOGICAL [and ior])
821 ;; Code iterator for unary negate and bitwise complement.
822 (define_code_iterator NEG_NOT [neg not])
824 ;; Code iterator for sign/zero extension
825 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
827 ;; All division operations (signed/unsigned)
828 (define_code_iterator ANY_DIV [div udiv])
830 ;; Code iterator for sign/zero extraction
831 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
833 ;; Code iterator for equality comparisons
834 (define_code_iterator EQL [eq ne])
836 ;; Code iterator for less-than and greater/equal-to
837 (define_code_iterator LTGE [lt ge])
839 ;; Iterator for __sync_<op> operations that where the operation can be
840 ;; represented directly RTL. This is all of the sync operations bar
842 (define_code_iterator atomic_op [plus minus ior xor and])
844 ;; Iterator for integer conversions
845 (define_code_iterator FIXUORS [fix unsigned_fix])
847 ;; Iterator for float conversions
848 (define_code_iterator FLOATUORS [float unsigned_float])
850 ;; Code iterator for variants of vector max and min.
851 (define_code_iterator MAXMIN [smax smin umax umin])
853 (define_code_iterator FMAXMIN [smax smin])
855 ;; Code iterator for variants of vector max and min.
856 (define_code_iterator ADDSUB [plus minus])
858 ;; Code iterator for variants of vector saturating binary ops.
859 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
861 ;; Code iterator for variants of vector saturating unary ops.
862 (define_code_iterator UNQOPS [ss_neg ss_abs])
864 ;; Code iterator for signed variants of vector saturating binary ops.
865 (define_code_iterator SBINQOPS [ss_plus ss_minus])
867 ;; Comparison operators for <F>CM.
868 (define_code_iterator COMPARISONS [lt le eq ge gt])
870 ;; Unsigned comparison operators.
871 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
873 ;; Unsigned comparison operators.
874 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
876 ;; -------------------------------------------------------------------
878 ;; -------------------------------------------------------------------
879 ;; Map rtl objects to optab names
880 (define_code_attr optab [(ashift "ashl")
884 (sign_extend "extend")
885 (zero_extend "zero_extend")
886 (sign_extract "extv")
887 (zero_extract "extzv")
889 (unsigned_fix "fixuns")
891 (unsigned_float "floatuns")
916 ;; For comparison operators we use the FCM* and CM* instructions.
917 ;; As there are no CMLE or CMLT instructions which act on 3 vector
918 ;; operands, we must use CMGE or CMGT and swap the order of the
921 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
922 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
923 (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
924 (ltu "2") (leu "2") (geu "1") (gtu "1")])
925 (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
926 (ltu "1") (leu "1") (geu "2") (gtu "2")])
928 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
929 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
932 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
933 (unsigned_fix "fixuns_trunc")])
935 ;; Optab prefix for sign/zero-extending operations
936 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
938 (fix "") (unsigned_fix "u")
939 (float "s") (unsigned_float "u")
940 (ss_plus "s") (us_plus "u")
941 (ss_minus "s") (us_minus "u")])
943 ;; Similar for the instruction mnemonics
944 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
945 (lshiftrt "lsr") (rotatert "ror")])
947 ;; Map shift operators onto underlying bit-field instructions
948 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
949 (lshiftrt "ubfx") (rotatert "extr")])
951 ;; Logical operator instruction mnemonics
952 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
954 ;; Operation names for negate and bitwise complement.
955 (define_code_attr neg_not_op [(neg "neg") (not "not")])
957 ;; Similar, but when not(op)
958 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
960 ;; Sign- or zero-extending data-op
961 (define_code_attr su [(sign_extend "s") (zero_extend "u")
962 (sign_extract "s") (zero_extract "u")
963 (fix "s") (unsigned_fix "u")
965 (smax "s") (umax "u")
966 (smin "s") (umin "u")])
968 ;; Emit conditional branch instructions.
969 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
971 ;; Emit cbz/cbnz depending on comparison type.
972 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
974 ;; Emit inverted cbz/cbnz depending on comparison type.
975 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
977 ;; Emit tbz/tbnz depending on comparison type.
978 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
980 ;; Emit inverted tbz/tbnz depending on comparison type.
981 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
983 ;; Max/min attributes.
984 (define_code_attr maxmin [(smax "max")
989 ;; MLA/MLS attributes.
990 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
993 (define_code_attr atomic_optab
994 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
996 (define_code_attr atomic_op_operand
997 [(ior "aarch64_logical_operand")
998 (xor "aarch64_logical_operand")
999 (and "aarch64_logical_operand")
1000 (plus "aarch64_plus_operand")
1001 (minus "aarch64_plus_operand")])
1003 ;; Constants acceptable for atomic operations.
1004 ;; This definition must appear in this file before the iterators it refers to.
1005 (define_code_attr const_atomic
1006 [(plus "IJ") (minus "IJ")
1007 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1008 (and "<lconst_atomic>")])
1010 ;; Attribute to describe constants acceptable in atomic logical operations
1011 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1013 ;; -------------------------------------------------------------------
1015 ;; -------------------------------------------------------------------
1016 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1017 UNSPEC_SMAXV UNSPEC_SMINV])
1019 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1020 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
1022 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1023 UNSPEC_SRHADD UNSPEC_URHADD
1024 UNSPEC_SHSUB UNSPEC_UHSUB
1025 UNSPEC_SRHSUB UNSPEC_URHSUB])
1028 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1029 UNSPEC_SUBHN UNSPEC_RSUBHN])
1031 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1032 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1034 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1035 UNSPEC_FMAXNM UNSPEC_FMINNM])
1037 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1039 (define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1041 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1043 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1045 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1047 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1048 UNSPEC_SRSHL UNSPEC_URSHL])
1050 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1052 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1053 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1055 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1056 UNSPEC_SRSRA UNSPEC_URSRA])
1058 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1059 UNSPEC_SSRI UNSPEC_USRI])
1062 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1064 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1066 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1067 UNSPEC_SQSHRN UNSPEC_UQSHRN
1068 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1070 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1072 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1073 UNSPEC_TRN1 UNSPEC_TRN2
1074 UNSPEC_UZP1 UNSPEC_UZP2])
1076 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1078 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1079 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1082 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1083 UNSPEC_FRINTA UNSPEC_FRINTN])
1085 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1086 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1088 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1090 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1091 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1092 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1094 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1095 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1097 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1099 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1101 ;; Iterators for atomic operations.
1103 (define_int_iterator ATOMIC_LDOP
1104 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1105 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1107 (define_int_attr atomic_ldop
1108 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1109 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1111 ;; -------------------------------------------------------------------
1112 ;; Int Iterators Attributes.
1113 ;; -------------------------------------------------------------------
1114 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1115 (UNSPEC_UMINV "umin")
1116 (UNSPEC_SMAXV "smax")
1117 (UNSPEC_SMINV "smin")
1118 (UNSPEC_FMAX "smax_nan")
1119 (UNSPEC_FMAXNMV "smax")
1120 (UNSPEC_FMAXV "smax_nan")
1121 (UNSPEC_FMIN "smin_nan")
1122 (UNSPEC_FMINNMV "smin")
1123 (UNSPEC_FMINV "smin_nan")
1124 (UNSPEC_FMAXNM "fmax")
1125 (UNSPEC_FMINNM "fmin")])
1127 (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1128 (UNSPEC_UMINV "umin")
1129 (UNSPEC_SMAXV "smax")
1130 (UNSPEC_SMINV "smin")
1131 (UNSPEC_FMAX "fmax")
1132 (UNSPEC_FMAXNMV "fmaxnm")
1133 (UNSPEC_FMAXV "fmax")
1134 (UNSPEC_FMIN "fmin")
1135 (UNSPEC_FMINNMV "fminnm")
1136 (UNSPEC_FMINV "fmin")
1137 (UNSPEC_FMAXNM "fmaxnm")
1138 (UNSPEC_FMINNM "fminnm")])
1140 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1141 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1142 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1143 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1144 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1145 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1146 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1147 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1148 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1149 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1150 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1151 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1152 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1153 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1154 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1155 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1157 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1158 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1159 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1160 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1161 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1162 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1163 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
1166 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1167 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1168 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1169 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1170 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1171 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1174 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1175 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1177 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1178 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1179 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1180 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1182 (define_int_attr addsub [(UNSPEC_SHADD "add")
1183 (UNSPEC_UHADD "add")
1184 (UNSPEC_SRHADD "add")
1185 (UNSPEC_URHADD "add")
1186 (UNSPEC_SHSUB "sub")
1187 (UNSPEC_UHSUB "sub")
1188 (UNSPEC_SRHSUB "sub")
1189 (UNSPEC_URHSUB "sub")
1190 (UNSPEC_ADDHN "add")
1191 (UNSPEC_SUBHN "sub")
1192 (UNSPEC_RADDHN "add")
1193 (UNSPEC_RSUBHN "sub")
1194 (UNSPEC_ADDHN2 "add")
1195 (UNSPEC_SUBHN2 "sub")
1196 (UNSPEC_RADDHN2 "add")
1197 (UNSPEC_RSUBHN2 "sub")])
1199 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1200 (UNSPEC_SSRI "offset_")
1201 (UNSPEC_USRI "offset_")])
1203 ;; Standard pattern names for floating-point rounding instructions.
1204 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1205 (UNSPEC_FRINTP "ceil")
1206 (UNSPEC_FRINTM "floor")
1207 (UNSPEC_FRINTI "nearbyint")
1208 (UNSPEC_FRINTX "rint")
1209 (UNSPEC_FRINTA "round")
1210 (UNSPEC_FRINTN "frintn")])
1212 ;; frint suffix for floating-point rounding instructions.
1213 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1214 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1215 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1216 (UNSPEC_FRINTN "n")])
1218 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1219 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1220 (UNSPEC_FRINTN "frintn")])
1222 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1223 (UNSPEC_UCVTF "ucvtf")
1224 (UNSPEC_FCVTZS "fcvtzs")
1225 (UNSPEC_FCVTZU "fcvtzu")])
1227 ;; Pointer authentication mnemonic prefix.
1228 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1229 (UNSPEC_AUTISP "auti")
1230 (UNSPEC_PACI1716 "paci")
1231 (UNSPEC_AUTI1716 "auti")])
1233 ;; Pointer authentication HINT number for NOP space instructions using A Key.
1234 (define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1235 (UNSPEC_AUTISP "29")
1236 (UNSPEC_PACI1716 "8")
1237 (UNSPEC_AUTI1716 "12")])
1239 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1240 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1241 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1243 ; op code for REV instructions (size within which elements are reversed).
1244 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1245 (UNSPEC_REV16 "16")])
1247 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1248 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1249 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
1251 (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
1253 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1254 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1255 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1256 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1258 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1259 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1260 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1261 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1263 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1264 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1266 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1267 (UNSPEC_SHA1M "m")])
1269 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
1271 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])