1 /* { dg-do compile } */
2 /* { dg-require-effective-target arm_fp_ok } */
3 /* { dg-options "-O2 -ffp-contract=off" } */
4 /* { dg-add-options arm_fp } */
5 /* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
7 extern float fabsf (float);
8 extern float sqrtf (float);
9 extern double fabs (double);
10 extern double sqrt (double);
12 volatile float f1
, f2
, f3
;
16 /* { dg-final { scan-assembler "vabs.f32" } } */
19 /* { dg-final { scan-assembler "vneg.f32" } } */
22 /* { dg-final { scan-assembler "vadd.f32" } } */
25 /* { dg-final { scan-assembler "vsub.f32" } } */
28 /* { dg-final { scan-assembler "vdiv.f32" } } */
31 /* { dg-final { scan-assembler "vmul.f32" } } */
34 /* { dg-final { scan-assembler "vnmul.f32" } } */
37 /* { dg-final { scan-assembler "vmla.f32" } } */
40 /* { dg-final { scan-assembler "vnmls.f32" } } */
42 /* mulsf3negsfaddsf_vfp */
43 /* { dg-final { scan-assembler "vmls.f32" } } */
45 /* mulsf3negsfsubsf_vfp */
46 /* { dg-final { scan-assembler "vnmla.f32" } } */
49 /* { dg-final { scan-assembler "vsqrt.f32" } } */
53 volatile double d1
, d2
, d3
;
57 /* { dg-final { scan-assembler "vabs.f64" } } */
60 /* { dg-final { scan-assembler "vneg.f64" } } */
63 /* { dg-final { scan-assembler "vadd.f64" } } */
66 /* { dg-final { scan-assembler "vsub.f64" } } */
69 /* { dg-final { scan-assembler "vdiv.f64" } } */
72 /* { dg-final { scan-assembler "vmul.f64" } } */
75 /* { dg-final { scan-assembler "vnmul.f64" } } */
78 /* { dg-final { scan-assembler "vmla.f64" } } */
81 /* { dg-final { scan-assembler "vnmls.f64" } } */
83 /* muldf3negdfadddf_vfp */
84 /* { dg-final { scan-assembler "vmls.f64" } } */
86 /* muldf3negdfsubdf_vfp */
87 /* { dg-final { scan-assembler "vnmla.f64" } } */
90 /* { dg-final { scan-assembler "vsqrt.f64" } } */
95 volatile unsigned int u1
;
97 void test_convert () {
99 /* { dg-final { scan-assembler "vcvt.f64.f32" } } */
102 /* { dg-final { scan-assembler "vcvt.f32.f64" } } */
105 /* { dg-final { scan-assembler "vcvt.s32.f32" } } */
108 /* { dg-final { scan-assembler "vcvt.s32.f64" } } */
110 /* fixuns_truncsfsi2 */
111 /* { dg-final { scan-assembler "vcvt.u32.f32" } } */
113 /* fixuns_truncdfsi2 */
114 /* { dg-final { scan-assembler "vcvt.u32.f64" } } */
117 /* { dg-final { scan-assembler "vcvt.f32.s32" } } */
120 /* { dg-final { scan-assembler "vcvt.f64.s32" } } */
123 /* { dg-final { scan-assembler "vcvt.f32.u32" } } */
126 /* { dg-final { scan-assembler "vcvt.f64.u32" } } */
130 void test_ldst (float f
[], double d
[]) {
131 /* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #-?\[0-9\]+\\\]" } } */
132 /* { dg-final { scan-assembler "vldr.32.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
133 /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
134 /* { dg-final { scan-assembler "vstr.32.+ \\\[r\[0-9\]\\\]\n" } } */
135 f
[256] = f
[255] + f
[-255];
137 /* { dg-final { scan-assembler "vldr.64.+ \\\[r1, #1016\\\]" } } */
138 /* { dg-final { scan-assembler "vldr.64.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
139 /* { dg-final { scan-assembler "vstr.64.+ \\\[r1, #256\\\]" } } */
140 d
[32] = d
[127] + d
[-127];