1 /* { dg-do compile } */
2 /* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
3 /* { dg-options "-O2" } */
4 /* { dg-add-options arm_v8_2a_fp16_scalar } */
6 /* Test instructions generated for the FP16 scalar intrinsics. */
9 #define MSTRCAT(L, str) L##str
11 #define UNOP_TEST(insn) \
13 MSTRCAT (test_##insn, 16) (float16_t a) \
15 return MSTRCAT (insn, h_f16) (a); \
18 #define BINOP_TEST(insn) \
20 MSTRCAT (test_##insn, 16) (float16_t a, float16_t b) \
22 return MSTRCAT (insn, h_f16) (a, b); \
25 #define TERNOP_TEST(insn) \
27 MSTRCAT (test_##insn, 16) (float16_t a, float16_t b, float16_t c) \
29 return MSTRCAT (insn, h_f16) (a, b, c); \
33 test_vcvth_f16_s32 (int32_t a
)
35 return vcvth_f16_s32 (a
);
39 test_vcvth_n_f16_s32 (int32_t a
)
41 return vcvth_n_f16_s32 (a
, 1);
43 /* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+} 2 } } */
44 /* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+, #1} 1 } } */
47 test_vcvth_f16_u32 (uint32_t a
)
49 return vcvth_f16_u32 (a
);
53 test_vcvth_n_f16_u32 (uint32_t a
)
55 return vcvth_n_f16_u32 (a
, 1);
58 /* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+} 2 } } */
59 /* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+, #1} 1 } } */
62 test_vcvth_u32_f16 (float16_t a
)
64 return vcvth_u32_f16 (a
);
66 /* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+} 2 } } */
69 test_vcvth_n_u32_f16 (float16_t a
)
71 return vcvth_n_u32_f16 (a
, 1);
73 /* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } } */
76 test_vcvth_s32_f16 (float16_t a
)
78 return vcvth_s32_f16 (a
);
82 test_vcvth_n_s32_f16 (float16_t a
)
84 return vcvth_n_s32_f16 (a
, 1);
87 /* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+} 2 } } */
88 /* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } } */
91 test_vcvtah_s32_f16 (float16_t a
)
93 return vcvtah_s32_f16 (a
);
95 /* { dg-final { scan-assembler-times {vcvta\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } } */
98 test_vcvtah_u32_f16 (float16_t a
)
100 return vcvtah_u32_f16 (a
);
102 /* { dg-final { scan-assembler-times {vcvta\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } } */
105 test_vcvtmh_s32_f16 (float16_t a
)
107 return vcvtmh_s32_f16 (a
);
109 /* { dg-final { scan-assembler-times {vcvtm\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } } */
112 test_vcvtmh_u32_f16 (float16_t a
)
114 return vcvtmh_u32_f16 (a
);
116 /* { dg-final { scan-assembler-times {vcvtm\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
120 test_vcvtnh_s32_f16 (float16_t a
)
122 return vcvtnh_s32_f16 (a
);
124 /* { dg-final { scan-assembler-times {vcvtn\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
128 test_vcvtnh_u32_f16 (float16_t a
)
130 return vcvtnh_u32_f16 (a
);
132 /* { dg-final { scan-assembler-times {vcvtn\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
136 test_vcvtph_s32_f16 (float16_t a
)
138 return vcvtph_s32_f16 (a
);
140 /* { dg-final { scan-assembler-times {vcvtp\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
144 test_vcvtph_u32_f16 (float16_t a
)
146 return vcvtph_u32_f16 (a
);
148 /* { dg-final { scan-assembler-times {vcvtp\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
152 /* { dg-final { scan-assembler-times {vabs\.f16\ts[0-9]+, s[0-9]+} 1 } } */
155 /* { dg-final { scan-assembler-times {vneg\.f16\ts[0-9]+, s[0-9]+} 1 } } */
158 /* { dg-final { scan-assembler-times {vrintz\.f16\ts[0-9]+, s[0-9]+} 1 } } */
161 /* { dg-final { scan-assembler-times {vrintr\.f16\ts[0-9]+, s[0-9]+} 1 } } */
164 /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */
167 /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */
170 /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */
173 /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */
176 /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */
179 /* { dg-final { scan-assembler-times {vsqrt\.f16\ts[0-9]+, s[0-9]+} 1 } } */
182 /* { dg-final { scan-assembler-times {vadd\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
185 /* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
188 /* { dg-final { scan-assembler-times {vmaxnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
191 /* { dg-final { scan-assembler-times {vminnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
194 /* { dg-final { scan-assembler-times {vmul\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
197 /* { dg-final { scan-assembler-times {vsub\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
200 /* { dg-final { scan-assembler-times {vfma\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
203 /* { dg-final { scan-assembler-times {vfms\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */